diff --git a/Documentation/ABI/obsolete/sysfs-selinux-disable b/Documentation/ABI/obsolete/sysfs-selinux-disable deleted file mode 100644 index c340278e3cf8..000000000000 --- a/Documentation/ABI/obsolete/sysfs-selinux-disable +++ /dev/null @@ -1,26 +0,0 @@ -What: /sys/fs/selinux/disable -Date: April 2005 (predates git) -KernelVersion: 2.6.12-rc2 (predates git) -Contact: selinux@vger.kernel.org -Description: - - The selinuxfs "disable" node allows SELinux to be disabled at runtime - prior to a policy being loaded into the kernel. If disabled via this - mechanism, SELinux will remain disabled until the system is rebooted. - - The preferred method of disabling SELinux is via the "selinux=0" boot - parameter, but the selinuxfs "disable" node was created to make it - easier for systems with primitive bootloaders that did not allow for - easy modification of the kernel command line. Unfortunately, allowing - for SELinux to be disabled at runtime makes it difficult to secure the - kernel's LSM hooks using the "__ro_after_init" feature. - - Thankfully, the need for the SELinux runtime disable appears to be - gone, the default Kconfig configuration disables this selinuxfs node, - and only one of the major distributions, Fedora, supports disabling - SELinux at runtime. Fedora is in the process of removing the - selinuxfs "disable" node and once that is complete we will start the - slow process of removing this code from the kernel. - - More information on /sys/fs/selinux/disable can be found under the - CONFIG_SECURITY_SELINUX_DISABLE Kconfig option. diff --git a/Documentation/ABI/testing/configfs-usb-gadget-uvc b/Documentation/ABI/testing/configfs-usb-gadget-uvc index 5d4180aaf18e..809765bd9573 100644 --- a/Documentation/ABI/testing/configfs-usb-gadget-uvc +++ b/Documentation/ABI/testing/configfs-usb-gadget-uvc @@ -265,71 +265,6 @@ Description: Specific uncompressed frame descriptors bmCapabilities - still image support, fixed frame-rate support -What: /config/usb-gadget/gadget/functions/uvc.name/streaming/framebased -Date: Oct 2025 -KernelVersion: 5.4 -Description: Framebased format descriptors - -What: /config/usb-gadget/gadget/functions/uvc.name/streaming/framebased/name -Date: Oct 2025 -KernelVersion: 5.4 -Description: Specific framebased format descriptors - - ================== ======================================= - bFormatIndex unique id for this format descriptor; - only defined after parent header is - linked into the streaming class; - read-only - bmaControls this format's data for bmaControls in - the streaming header - bmInterlaceFlags specifies interlace information, - read-only - bAspectRatioY the X dimension of the picture aspect - ratio, read-only - bAspectRatioX the Y dimension of the picture aspect - ratio, read-only - bDefaultFrameIndex optimum frame index for this stream - bBitsPerPixel number of bits per pixel used to - specify color in the decoded video - frame - guidFormat globally unique id used to identify - stream-encoding format - ================== ======================================= - -What: /config/usb-gadget/gadget/functions/uvc.name/streaming/framebased/name/name -Date: Sept 2024 -KernelVersion: 5.15 -Description: Specific framebased frame descriptors - - ========================= ===================================== - bFrameIndex unique id for this framedescriptor; - only defined after parent format is - linked into the streaming header; - read-only - dwFrameInterval indicates how frame interval can be - programmed; a number of values - separated by newline can be specified - dwDefaultFrameInterval the frame interval the device would - like to use as default - dwBytesPerLine Specifies the number of bytes per line - - of video for packed fixed frame size - formats, allowing the receiver to - perform stride alignment of the video. - If the bVariableSize value (above) is - TRUE (1), or if the format does not - permit such alignment, this value shall - be set to zero (0). - dwMaxBitRate the maximum bit rate at the shortest - frame interval in bps - dwMinBitRate the minimum bit rate at the longest - frame interval in bps - wHeight height of decoded bitmap frame in px - wWidth width of decoded bitmam frame in px - bmCapabilities still image support, fixed frame-rate - support - ========================= ===================================== - What: /config/usb-gadget/gadget/functions/uvc.name/streaming/header Date: Dec 2014 KernelVersion: 4.0 diff --git a/Documentation/ABI/testing/sysfs-fs-fuse b/Documentation/ABI/testing/sysfs-fs-fuse deleted file mode 100644 index b9956842b36f..000000000000 --- a/Documentation/ABI/testing/sysfs-fs-fuse +++ /dev/null @@ -1,19 +0,0 @@ -What: /sys/fs/fuse/features/fuse_bpf -Date: December 2022 -Contact: Paul Lawrence -Description: - Read-only file that contains the word 'supported' if fuse-bpf is - supported, does not exist otherwise - -What: /sys/fs/fuse/bpf_prog_type_fuse -Date: December 2022 -Contact: Paul Lawrence -Description: - bpf_prog_type_fuse defines the program type of bpf programs that - may be passed to fuse-bpf. For upstream bpf program types, this - is a constant defined in a contiguous array of constants. - bpf_prog_type_fuse is appended to the end of the list, so it may - change and therefore its value must be read from this file. - - Contents is ASCII decimal representation of bpf_prog_type_fuse - diff --git a/Documentation/admin-guide/cgroup-v2.rst b/Documentation/admin-guide/cgroup-v2.rst index 39e774179f04..5361ebec3361 100644 --- a/Documentation/admin-guide/cgroup-v2.rst +++ b/Documentation/admin-guide/cgroup-v2.rst @@ -186,17 +186,6 @@ cgroup v2 currently supports the following mount options. modified through remount from the init namespace. The mount option is ignored on non-init namespace mounts. - memory_recursiveprot - - Recursively apply memory.min and memory.low protection to - entire subtrees, without requiring explicit downward - propagation into leaf cgroups. This allows protecting entire - subtrees from one another, while retaining free competition - within those subtrees. This should have been the default - behavior but is a mount-option to avoid regressing setups - relying on the original semantics (e.g. specifying bogusly - high 'bypass' protection values at higher tree levels). - Organizing Processes and Threads -------------------------------- diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index c33eb805ec85..2442c22d6380 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -526,7 +526,7 @@ 1 -- check protection requested by application. Default value is set via a kernel config option. Value can be changed at runtime via - /sys/fs/selinux/checkreqprot. + /selinux/checkreqprot. cio_ignore= [S390] See Documentation/s390/common_io.rst for details. @@ -1251,8 +1251,7 @@ 0 -- permissive (log only, no denials). 1 -- enforcing (deny and log). Default value is 0. - Value can be changed at runtime via - /sys/fs/selinux/enforce. + Value can be changed at runtime via /selinux/enforce. erst_disable [ACPI] Disable Error Record Serialization Table (ERST) @@ -3187,21 +3186,6 @@ in certain environments such as networked servers or real-time systems. - no_hash_pointers - Force pointers printed to the console or buffers to be - unhashed. By default, when a pointer is printed via %p - format string, that pointer is "hashed", i.e. obscured - by hashing the pointer value. This is a security feature - that hides actual kernel addresses from unprivileged - users, but it also makes debugging the kernel more - difficult since unequal pointers can no longer be - compared. However, if this command-line option is - specified, then all normal pointers will have their true - value printed. Pointers printed via %pK may still be - hashed. This option should only be specified when - debugging the kernel. Please do not use on production - kernels. - nohibernate [HIBERNATION] Disable hibernation and resume. nohz= [KNL] Boottime enable/disable dynamic ticks @@ -4296,13 +4280,6 @@ only normal grace-period primitives. No effect on CONFIG_TINY_RCU kernels. - rcupdate.rcu_task_ipi_delay= [KNL] - Set time in jiffies during which RCU tasks will - avoid sending IPIs, starting with the beginning - of a given grace period. Setting a large - number avoids disturbing real-time workloads, - but lengthens grace periods. - rcupdate.rcu_task_stall_timeout= [KNL] Set timeout in jiffies for RCU task stall warning messages. Disable with a value less than or equal @@ -4447,9 +4424,6 @@ rootflags= [KNL] Set root filesystem mount option string - initramfs_options= [KNL] - Specify mount options for for the initramfs mount. - rootfstype= [KNL] Set root filesystem type rootwait [KNL] Wait (indefinitely) for root device to show up. @@ -4502,7 +4476,9 @@ See security/selinux/Kconfig help text. 0 -- disable. 1 -- enable. - Default value is 1. + Default value is set via kernel config option. + If enabled at boot time, /selinux/disable can be used + later to disable prior to initial policy load. apparmor= [APPARMOR] Disable or enable AppArmor at boot time Format: { "0" | "1" } diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index 951657baeaa8..17da97209976 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -134,8 +134,6 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ -| ARM | Neoverse-V3AE | #3312417 | ARM64_ERRATUM_3194386 | -+----------------+-----------------+-----------------+-----------------------------+ | ARM | MMU-500 | #841119,826419 | N/A | +----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ diff --git a/Documentation/bpf/prog_flow_dissector.rst b/Documentation/bpf/prog_flow_dissector.rst index 4d86780ab0f1..a78bf036cadd 100644 --- a/Documentation/bpf/prog_flow_dissector.rst +++ b/Documentation/bpf/prog_flow_dissector.rst @@ -142,6 +142,3 @@ BPF flow dissector doesn't support exporting all the metadata that in-kernel C-based implementation can export. Notable example is single VLAN (802.1Q) and double VLAN (802.1AD) tags. Please refer to the ``struct bpf_flow_keys`` for a set of information that's currently can be exported from the BPF context. - -When BPF flow dissector is attached to the root network namespace (machine-wide -policy), users can't override it in their child network namespaces. diff --git a/Documentation/core-api/printk-formats.rst b/Documentation/core-api/printk-formats.rst index cf8c2ad8abef..ecbebf4ca8e7 100644 --- a/Documentation/core-api/printk-formats.rst +++ b/Documentation/core-api/printk-formats.rst @@ -110,20 +110,6 @@ used when printing stack backtraces. The specifier takes into consideration the effect of compiler optimisations which may occur when tail-calls are used and marked with the noreturn GCC attribute. -Probed Pointers from BPF / tracing ----------------------------------- - -:: - - %pks kernel string - %pus user string - -The ``k`` and ``u`` specifiers are used for printing prior probed memory from -either kernel memory (k) or user memory (u). The subsequent ``s`` specifier -results in printing a string. For direct use in regular vsnprintf() the (k) -and (u) annotation is ignored, however, when used out of BPF's bpf_trace_printk(), -for example, it reads the memory it is pointing to without faulting. - Kernel Pointers --------------- diff --git a/Documentation/dev-tools/index.rst b/Documentation/dev-tools/index.rst index cdabec1e168c..b0522a4dd107 100644 --- a/Documentation/dev-tools/index.rst +++ b/Documentation/dev-tools/index.rst @@ -21,7 +21,6 @@ whole; patches welcome! kasan ubsan kmemleak - kfence gdb-kernel-debugging kgdb kselftest diff --git a/Documentation/dev-tools/kfence.rst b/Documentation/dev-tools/kfence.rst deleted file mode 100644 index fdf04e741ea5..000000000000 --- a/Documentation/dev-tools/kfence.rst +++ /dev/null @@ -1,298 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 -.. Copyright (C) 2020, Google LLC. - -Kernel Electric-Fence (KFENCE) -============================== - -Kernel Electric-Fence (KFENCE) is a low-overhead sampling-based memory safety -error detector. KFENCE detects heap out-of-bounds access, use-after-free, and -invalid-free errors. - -KFENCE is designed to be enabled in production kernels, and has near zero -performance overhead. Compared to KASAN, KFENCE trades performance for -precision. The main motivation behind KFENCE's design, is that with enough -total uptime KFENCE will detect bugs in code paths not typically exercised by -non-production test workloads. One way to quickly achieve a large enough total -uptime is when the tool is deployed across a large fleet of machines. - -Usage ------ - -To enable KFENCE, configure the kernel with:: - - CONFIG_KFENCE=y - -To build a kernel with KFENCE support, but disabled by default (to enable, set -``kfence.sample_interval`` to non-zero value), configure the kernel with:: - - CONFIG_KFENCE=y - CONFIG_KFENCE_SAMPLE_INTERVAL=0 - -KFENCE provides several other configuration options to customize behaviour (see -the respective help text in ``lib/Kconfig.kfence`` for more info). - -Tuning performance -~~~~~~~~~~~~~~~~~~ - -The most important parameter is KFENCE's sample interval, which can be set via -the kernel boot parameter ``kfence.sample_interval`` in milliseconds. The -sample interval determines the frequency with which heap allocations will be -guarded by KFENCE. The default is configurable via the Kconfig option -``CONFIG_KFENCE_SAMPLE_INTERVAL``. Setting ``kfence.sample_interval=0`` -disables KFENCE. - -The KFENCE memory pool is of fixed size, and if the pool is exhausted, no -further KFENCE allocations occur. With ``CONFIG_KFENCE_NUM_OBJECTS`` (default -255), the number of available guarded objects can be controlled. Each object -requires 2 pages, one for the object itself and the other one used as a guard -page; object pages are interleaved with guard pages, and every object page is -therefore surrounded by two guard pages. - -The total memory dedicated to the KFENCE memory pool can be computed as:: - - ( #objects + 1 ) * 2 * PAGE_SIZE - -Using the default config, and assuming a page size of 4 KiB, results in -dedicating 2 MiB to the KFENCE memory pool. - -Note: On architectures that support huge pages, KFENCE will ensure that the -pool is using pages of size ``PAGE_SIZE``. This will result in additional page -tables being allocated. - -Error reports -~~~~~~~~~~~~~ - -A typical out-of-bounds access looks like this:: - - ================================================================== - BUG: KFENCE: out-of-bounds read in test_out_of_bounds_read+0xa3/0x22b - - Out-of-bounds read at 0xffffffffb672efff (1B left of kfence-#17): - test_out_of_bounds_read+0xa3/0x22b - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - kfence-#17 [0xffffffffb672f000-0xffffffffb672f01f, size=32, cache=kmalloc-32] allocated by task 507: - test_alloc+0xf3/0x25b - test_out_of_bounds_read+0x98/0x22b - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - CPU: 4 PID: 107 Comm: kunit_try_catch Not tainted 5.8.0-rc6+ #7 - Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.13.0-1 04/01/2014 - ================================================================== - -The header of the report provides a short summary of the function involved in -the access. It is followed by more detailed information about the access and -its origin. Note that, real kernel addresses are only shown when using the -kernel command line option ``no_hash_pointers``. - -Use-after-free accesses are reported as:: - - ================================================================== - BUG: KFENCE: use-after-free read in test_use_after_free_read+0xb3/0x143 - - Use-after-free read at 0xffffffffb673dfe0 (in kfence-#24): - test_use_after_free_read+0xb3/0x143 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - kfence-#24 [0xffffffffb673dfe0-0xffffffffb673dfff, size=32, cache=kmalloc-32] allocated by task 507: - test_alloc+0xf3/0x25b - test_use_after_free_read+0x76/0x143 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - freed by task 507: - test_use_after_free_read+0xa8/0x143 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - CPU: 4 PID: 109 Comm: kunit_try_catch Tainted: G W 5.8.0-rc6+ #7 - Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.13.0-1 04/01/2014 - ================================================================== - -KFENCE also reports on invalid frees, such as double-frees:: - - ================================================================== - BUG: KFENCE: invalid free in test_double_free+0xdc/0x171 - - Invalid free of 0xffffffffb6741000: - test_double_free+0xdc/0x171 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - kfence-#26 [0xffffffffb6741000-0xffffffffb674101f, size=32, cache=kmalloc-32] allocated by task 507: - test_alloc+0xf3/0x25b - test_double_free+0x76/0x171 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - freed by task 507: - test_double_free+0xa8/0x171 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - CPU: 4 PID: 111 Comm: kunit_try_catch Tainted: G W 5.8.0-rc6+ #7 - Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.13.0-1 04/01/2014 - ================================================================== - -KFENCE also uses pattern-based redzones on the other side of an object's guard -page, to detect out-of-bounds writes on the unprotected side of the object. -These are reported on frees:: - - ================================================================== - BUG: KFENCE: memory corruption in test_kmalloc_aligned_oob_write+0xef/0x184 - - Corrupted memory at 0xffffffffb6797ff9 [ 0xac . . . . . . ] (in kfence-#69): - test_kmalloc_aligned_oob_write+0xef/0x184 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - kfence-#69 [0xffffffffb6797fb0-0xffffffffb6797ff8, size=73, cache=kmalloc-96] allocated by task 507: - test_alloc+0xf3/0x25b - test_kmalloc_aligned_oob_write+0x57/0x184 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - CPU: 4 PID: 120 Comm: kunit_try_catch Tainted: G W 5.8.0-rc6+ #7 - Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.13.0-1 04/01/2014 - ================================================================== - -For such errors, the address where the corruption occurred as well as the -invalidly written bytes (offset from the address) are shown; in this -representation, '.' denote untouched bytes. In the example above ``0xac`` is -the value written to the invalid address at offset 0, and the remaining '.' -denote that no following bytes have been touched. Note that, real values are -only shown if the kernel was booted with ``no_hash_pointers``; to avoid -information disclosure otherwise, '!' is used instead to denote invalidly -written bytes. - -And finally, KFENCE may also report on invalid accesses to any protected page -where it was not possible to determine an associated object, e.g. if adjacent -object pages had not yet been allocated:: - - ================================================================== - BUG: KFENCE: invalid read in test_invalid_access+0x26/0xe0 - - Invalid read at 0xffffffffb670b00a: - test_invalid_access+0x26/0xe0 - kunit_try_run_case+0x51/0x85 - kunit_generic_run_threadfn_adapter+0x16/0x30 - kthread+0x137/0x160 - ret_from_fork+0x22/0x30 - - CPU: 4 PID: 124 Comm: kunit_try_catch Tainted: G W 5.8.0-rc6+ #7 - Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.13.0-1 04/01/2014 - ================================================================== - -DebugFS interface -~~~~~~~~~~~~~~~~~ - -Some debugging information is exposed via debugfs: - -* The file ``/sys/kernel/debug/kfence/stats`` provides runtime statistics. - -* The file ``/sys/kernel/debug/kfence/objects`` provides a list of objects - allocated via KFENCE, including those already freed but protected. - -Implementation Details ----------------------- - -Guarded allocations are set up based on the sample interval. After expiration -of the sample interval, the next allocation through the main allocator (SLAB or -SLUB) returns a guarded allocation from the KFENCE object pool (allocation -sizes up to PAGE_SIZE are supported). At this point, the timer is reset, and -the next allocation is set up after the expiration of the interval. To "gate" a -KFENCE allocation through the main allocator's fast-path without overhead, -KFENCE relies on static branches via the static keys infrastructure. The static -branch is toggled to redirect the allocation to KFENCE. - -KFENCE objects each reside on a dedicated page, at either the left or right -page boundaries selected at random. The pages to the left and right of the -object page are "guard pages", whose attributes are changed to a protected -state, and cause page faults on any attempted access. Such page faults are then -intercepted by KFENCE, which handles the fault gracefully by reporting an -out-of-bounds access, and marking the page as accessible so that the faulting -code can (wrongly) continue executing (set ``panic_on_warn`` to panic instead). - -To detect out-of-bounds writes to memory within the object's page itself, -KFENCE also uses pattern-based redzones. For each object page, a redzone is set -up for all non-object memory. For typical alignments, the redzone is only -required on the unguarded side of an object. Because KFENCE must honor the -cache's requested alignment, special alignments may result in unprotected gaps -on either side of an object, all of which are redzoned. - -The following figure illustrates the page layout:: - - ---+-----------+-----------+-----------+-----------+-----------+--- - | xxxxxxxxx | O : | xxxxxxxxx | : O | xxxxxxxxx | - | xxxxxxxxx | B : | xxxxxxxxx | : B | xxxxxxxxx | - | x GUARD x | J : RED- | x GUARD x | RED- : J | x GUARD x | - | xxxxxxxxx | E : ZONE | xxxxxxxxx | ZONE : E | xxxxxxxxx | - | xxxxxxxxx | C : | xxxxxxxxx | : C | xxxxxxxxx | - | xxxxxxxxx | T : | xxxxxxxxx | : T | xxxxxxxxx | - ---+-----------+-----------+-----------+-----------+-----------+--- - -Upon deallocation of a KFENCE object, the object's page is again protected and -the object is marked as freed. Any further access to the object causes a fault -and KFENCE reports a use-after-free access. Freed objects are inserted at the -tail of KFENCE's freelist, so that the least recently freed objects are reused -first, and the chances of detecting use-after-frees of recently freed objects -is increased. - -Interface ---------- - -The following describes the functions which are used by allocators as well as -page handling code to set up and deal with KFENCE allocations. - -.. kernel-doc:: include/linux/kfence.h - :functions: is_kfence_address - kfence_shutdown_cache - kfence_alloc kfence_free __kfence_free - kfence_ksize kfence_object_start - kfence_handle_page_fault - -Related Tools -------------- - -In userspace, a similar approach is taken by `GWP-ASan -`_. GWP-ASan also relies on guard pages and -a sampling strategy to detect memory unsafety bugs at scale. KFENCE's design is -directly influenced by GWP-ASan, and can be seen as its kernel sibling. Another -similar but non-sampling approach, that also inspired the name "KFENCE", can be -found in the userspace `Electric Fence Malloc Debugger -`_. - -In the kernel, several tools exist to debug memory access errors, and in -particular KASAN can detect all bug classes that KFENCE can detect. While KASAN -is more precise, relying on compiler instrumentation, this comes at a -performance cost. - -It is worth highlighting that KASAN and KFENCE are complementary, with -different target environments. For instance, KASAN is the better debugging-aid, -where test cases or reproducers exists: due to the lower chance to detect the -error, it would require more effort using KFENCE to debug. Deployments at scale -that cannot afford to enable KASAN, however, would benefit from using KFENCE to -discover bugs due to code paths not exercised by test cases or fuzzers. diff --git a/Documentation/filesystems/fuse.txt b/Documentation/filesystems/fuse.txt index d32457766947..13af4a49e7db 100644 --- a/Documentation/filesystems/fuse.txt +++ b/Documentation/filesystems/fuse.txt @@ -46,8 +46,10 @@ non-privileged mounts. This opens up new possibilities for the use of filesystems. A good example is sshfs: a secure network filesystem using the sftp protocol. -The userspace library and utilities are available from the -`FUSE homepage: `_ +The userspace library and utilities are available from the FUSE +homepage: + + http://fuse.sourceforge.net/ Filesystem type ~~~~~~~~~~~~~~~ diff --git a/Documentation/filesystems/proc.txt b/Documentation/filesystems/proc.txt index 8acb7244b2e6..6882bfd2c097 100644 --- a/Documentation/filesystems/proc.txt +++ b/Documentation/filesystems/proc.txt @@ -1823,20 +1823,18 @@ if precise results are needed. 3.8 /proc//fdinfo/ - Information about opened file --------------------------------------------------------------- This file provides information associated with an opened file. The regular -files have at least four fields -- 'pos', 'flags', 'mnt_id' and 'ino'. -The 'pos' represents the current offset of the opened file in decimal -form [see lseek(2) for details], 'flags' denotes the octal O_xxx mask the -file has been created with [see open(2) for details] and 'mnt_id' represents -mount ID of the file system containing the opened file [see 3.5 -/proc//mountinfo for details]. 'ino' represents the inode number of -the file. +files have at least three fields -- 'pos', 'flags' and mnt_id. The 'pos' +represents the current offset of the opened file in decimal form [see lseek(2) +for details], 'flags' denotes the octal O_xxx mask the file has been +created with [see open(2) for details] and 'mnt_id' represents mount ID of +the file system containing the opened file [see 3.5 /proc//mountinfo +for details]. A typical output is pos: 0 flags: 0100002 mnt_id: 19 - ino: 63107 All locks associated with a file descriptor are shown in its fdinfo too. @@ -1850,7 +1848,6 @@ pair provide additional information particular to the objects they represent. pos: 0 flags: 04002 mnt_id: 9 - ino: 63107 eventfd-count: 5a where 'eventfd-count' is hex value of a counter. @@ -1860,7 +1857,6 @@ pair provide additional information particular to the objects they represent. pos: 0 flags: 04002 mnt_id: 9 - ino: 63107 sigmask: 0000000000000200 where 'sigmask' is hex value of the signal mask associated @@ -1871,7 +1867,6 @@ pair provide additional information particular to the objects they represent. pos: 0 flags: 02 mnt_id: 9 - ino: 63107 tfd: 5 events: 1d data: ffffffffffffffff pos:0 ino:61af sdev:7 where 'tfd' is a target file descriptor number in decimal form, @@ -1888,8 +1883,6 @@ pair provide additional information particular to the objects they represent. pos: 0 flags: 02000000 - mnt_id: 9 - ino: 63107 inotify wd:3 ino:9e7e sdev:800013 mask:800afce ignored_mask:0 fhandle-bytes:8 fhandle-type:1 f_handle:7e9e0000640d1b6d where 'wd' is a watch descriptor in decimal form, ie a target file @@ -1912,7 +1905,6 @@ pair provide additional information particular to the objects they represent. pos: 0 flags: 02 mnt_id: 9 - ino: 63107 fanotify flags:10 event-flags:0 fanotify mnt_id:12 mflags:40 mask:38 ignored_mask:40000003 fanotify ino:4f969 sdev:800013 mflags:0 mask:3b ignored_mask:40000000 fhandle-bytes:8 fhandle-type:1 f_handle:69f90400c275b5b4 @@ -1935,7 +1927,6 @@ pair provide additional information particular to the objects they represent. pos: 0 flags: 02 mnt_id: 9 - ino: 63107 clockid: 0 ticks: 0 settime flags: 01 @@ -1950,22 +1941,6 @@ pair provide additional information particular to the objects they represent. with TIMER_ABSTIME option which will be shown in 'settime flags', but 'it_value' still exhibits timer's remaining time. -DMA Buffer files -~~~~~~~~~~~~~~~~ - -:: - - pos: 0 - flags: 04002 - mnt_id: 9 - ino: 63107 - size: 32768 - count: 2 - exp_name: system-heap - -where 'size' is the size of the DMA buffer in bytes. 'count' is the file count of -the DMA buffer file. 'exp_name' is the name of the DMA buffer exporter. - 3.9 /proc//map_files - Information about memory mapped files --------------------------------------------------------------------- This directory contains symbolic links which represent memory mapped files diff --git a/Documentation/networking/ip-sysctl.txt b/Documentation/networking/ip-sysctl.txt index 11ad3403bdda..12cf648120f4 100644 --- a/Documentation/networking/ip-sysctl.txt +++ b/Documentation/networking/ip-sysctl.txt @@ -1660,14 +1660,6 @@ accept_ra_min_hop_limit - INTEGER Default: 1 -accept_ra_min_lft - INTEGER - Minimum acceptable lifetime value in Router Advertisement. - - RA sections with a lifetime less than this value shall be - ignored. Zero lifetimes stay unaffected. - - Default: 0 - accept_ra_pinfo - BOOLEAN Learn Prefix Information in Router Advertisement. diff --git a/Documentation/security/siphash.rst b/Documentation/security/siphash.rst index d135c5951077..9965821ab333 100644 --- a/Documentation/security/siphash.rst +++ b/Documentation/security/siphash.rst @@ -7,7 +7,7 @@ SipHash - a short input PRF SipHash is a cryptographically secure PRF -- a keyed hash function -- that performs very well for short inputs, hence the name. It was designed by cryptographers Daniel J. Bernstein and Jean-Philippe Aumasson. It is intended -as a replacement for some uses of: `jhash`, `md5_transform`, `sha1_transform`, +as a replacement for some uses of: `jhash`, `md5_transform`, `sha_transform`, and so forth. SipHash takes a secret key filled with randomly generated numbers and either diff --git a/Documentation/trace/ftrace-uses.rst b/Documentation/trace/ftrace-uses.rst index 740bd0224d35..1fbc69894eed 100644 --- a/Documentation/trace/ftrace-uses.rst +++ b/Documentation/trace/ftrace-uses.rst @@ -170,14 +170,6 @@ FTRACE_OPS_FL_RCU a callback may be executed and RCU synchronization will not protect it. -FTRACE_OPS_FL_PERMANENT - If this is set on any ftrace ops, then the tracing cannot disabled by - writing 0 to the proc sysctl ftrace_enabled. Equally, a callback with - the flag set cannot be registered if ftrace_enabled is 0. - - Livepatch uses it not to lose the function redirection, so the system - stays protected. - Filtering which functions to trace ================================== diff --git a/Documentation/trace/ftrace.rst b/Documentation/trace/ftrace.rst index d2b5657ed33e..e3060eedb22d 100644 --- a/Documentation/trace/ftrace.rst +++ b/Documentation/trace/ftrace.rst @@ -2976,9 +2976,7 @@ Note, the proc sysctl ftrace_enable is a big on/off switch for the function tracer. By default it is enabled (when function tracing is enabled in the kernel). If it is disabled, all function tracing is disabled. This includes not only the function tracers for ftrace, but -also for any other uses (perf, kprobes, stack tracing, profiling, etc). It -cannot be disabled if there is a callback with FTRACE_OPS_FL_PERMANENT set -registered. +also for any other uses (perf, kprobes, stack tracing, profiling, etc). Please disable this with care. diff --git a/MAINTAINERS b/MAINTAINERS index 3cf5cc8042c4..acdcd544e8bc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3054,7 +3054,6 @@ R: Martin KaFai Lau R: Song Liu R: Yonghong Song R: Andrii Nakryiko -R: KP Singh L: netdev@vger.kernel.org L: bpf@vger.kernel.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git @@ -6742,8 +6741,7 @@ F: drivers/platform/x86/fujitsu-tablet.c FUSE: FILESYSTEM IN USERSPACE M: Miklos Szeredi L: linux-fsdevel@vger.kernel.org -S: Maintained -W: https://github.com/libfuse/ +W: http://fuse.sourceforge.net/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/fuse.git S: Maintained F: fs/fuse/ @@ -9141,7 +9139,6 @@ F: include/linux/skmsg.h F: net/core/skmsg.c F: net/core/sock_map.c F: net/ipv4/tcp_bpf.c -F: net/ipv4/udp_bpf.c LANTIQ / INTEL Ethernet drivers M: Hauke Mehrtens @@ -12851,7 +12848,6 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/brauner/linux.git F: samples/pidfd/ F: tools/testing/selftests/pidfd/ -F: tools/testing/selftests/clone3/ K: (?i)pidfd K: (?i)clone3 K: \b(clone_args|kernel_clone_args)\b @@ -14626,7 +14622,6 @@ F: include/uapi/linux/selinux_netlink.h F: security/selinux/ F: scripts/selinux/ F: Documentation/admin-guide/LSM/SELinux.rst -F: Documentation/ABI/obsolete/sysfs-selinux-disable SENSABLE PHANTOM M: Jiri Slaby diff --git a/Makefile b/Makefile index 8fad00d03e52..f0db281e9248 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 5 PATCHLEVEL = 4 -SUBLEVEL = 302 +SUBLEVEL = 300 EXTRAVERSION = NAME = Kleptomaniac Octopus @@ -447,7 +447,6 @@ OBJSIZE = $(CROSS_COMPILE)size STRIP = $(CROSS_COMPILE)strip endif PAHOLE = pahole -RESOLVE_BTFIDS = $(objtree)/tools/bpf/resolve_btfids/resolve_btfids LEX = flex YACC = bison AWK = awk @@ -510,7 +509,7 @@ GCC_PLUGINS_CFLAGS := CLANG_FLAGS := export ARCH SRCARCH CONFIG_SHELL BASH HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE LD CC -export CPP AR NM STRIP OBJCOPY OBJDUMP OBJSIZE READELF PAHOLE RESOLVE_BTFIDS LEX YACC AWK INSTALLKERNEL +export CPP AR NM STRIP OBJCOPY OBJDUMP OBJSIZE READELF PAHOLE LEX YACC AWK INSTALLKERNEL export PERL PYTHON PYTHON3 CHECK CHECKFLAGS MAKE UTS_MACHINE HOSTCXX export KGZIP KBZIP2 KLZOP LZMA LZ4 XZ export KBUILD_HOSTCXXFLAGS KBUILD_HOSTLDFLAGS KBUILD_HOSTLDLIBS LDFLAGS_MODULE @@ -596,11 +595,9 @@ CLANG_FLAGS += --target=$(notdir $(CROSS_COMPILE:%-=%)) endif # CROSS_COMPILE ifeq ($(LLVM_IAS),0) -CLANG_FLAGS += -fno-integrated-as +CLANG_FLAGS += -no-integrated-as GCC_TOOLCHAIN_DIR := $(dir $(shell which $(CROSS_COMPILE)elfedit)) CLANG_FLAGS += --prefix=$(GCC_TOOLCHAIN_DIR)$(notdir $(CROSS_COMPILE)) -else -CLANG_FLAGS += -fintegrated-as endif CLANG_FLAGS += -Werror=unknown-warning-option KBUILD_CPPFLAGS += $(CLANG_FLAGS) @@ -873,8 +870,7 @@ DEBUG_CFLAGS += -gsplit-dwarf else DEBUG_CFLAGS += -g endif - -ifdef CONFIG_AS_IS_LLVM +ifeq ($(LLVM_IAS),1) KBUILD_AFLAGS += -g else KBUILD_AFLAGS += -Wa,-gdwarf-2 @@ -947,6 +943,7 @@ endif ifdef CONFIG_LTO_CLANG ifdef CONFIG_THINLTO CC_FLAGS_LTO_CLANG := -flto=thin $(call cc-option, -fsplit-lto-unit) +KBUILD_LDFLAGS += --thinlto-cache-dir=.thinlto-cache else CC_FLAGS_LTO_CLANG := -flto endif @@ -963,8 +960,7 @@ endif ifdef CONFIG_LTO CC_FLAGS_LTO := $(CC_FLAGS_LTO_CLANG) -KBUILD_CFLAGS += -fno-lto $(CC_FLAGS_LTO) -KBUILD_AFLAGS += -fno-lto +KBUILD_CFLAGS += $(CC_FLAGS_LTO) export CC_FLAGS_LTO endif @@ -1017,6 +1013,15 @@ KBUILD_CFLAGS += $(call cc-disable-warning, maybe-uninitialized) # disable invalid "can't wrap" optimizations for signed / pointers KBUILD_CFLAGS += $(call cc-option,-fno-strict-overflow) +# clang sets -fmerge-all-constants by default as optimization, but this +# is non-conforming behavior for C and in fact breaks the kernel, so we +# need to disable it here generally. +KBUILD_CFLAGS += $(call cc-option,-fno-merge-all-constants) + +# for gcc -fno-merge-all-constants disables everything, but it is fine +# to have actual conforming behavior enabled. +KBUILD_CFLAGS += $(call cc-option,-fmerge-constants) + # Make sure -fstack-check isn't enabled (like gentoo apparently did) KBUILD_CFLAGS += $(call cc-option,-fno-stack-check,) @@ -1058,8 +1063,7 @@ LDFLAGS_vmlinux += $(call ld-option, -X,) endif ifeq ($(CONFIG_RELR),y) -# ld.lld before 15 did not support -z pack-relative-relocs. -LDFLAGS_vmlinux += $(call ld-option,--pack-dyn-relocs=relr,-z pack-relative-relocs) +LDFLAGS_vmlinux += --pack-dyn-relocs=relr --use-android-relr-tags endif # userspace programs are linked via the compiler, use the correct linker diff --git a/android/GKI_VERSION b/android/GKI_VERSION index eaa5b79f5d73..f8a4b6045b59 100644 --- a/android/GKI_VERSION +++ b/android/GKI_VERSION @@ -1 +1 @@ -LTS_5.4.302_91d385eb2a41 +LTS_5.4.281_d62984adb112 diff --git a/android/abi_gki_aarch64_4c8fb3275889.xml b/android/abi_gki_aarch64_7453ecf4d1fe.xml similarity index 75% rename from android/abi_gki_aarch64_4c8fb3275889.xml rename to android/abi_gki_aarch64_7453ecf4d1fe.xml index e9f6e2c6a941..6b194712e6d8 100644 --- a/android/abi_gki_aarch64_4c8fb3275889.xml +++ b/android/abi_gki_aarch64_7453ecf4d1fe.xml @@ -2935,315 +2935,315 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -3268,11 +3268,11 @@ - + - + @@ -3339,17 +3339,17 @@ - + - + - + - - - + + + @@ -3358,224 +3358,224 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + @@ -3588,7 +3588,7 @@ - + @@ -3606,89 +3606,89 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + @@ -3701,211 +3701,211 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + @@ -3921,195 +3921,195 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - + - + - + - + @@ -4134,232 +4134,232 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - + + + + + - - + + - + - + - + - + @@ -4374,238 +4374,238 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - - - + + + + + + + - + - + - + - + - + - + - + @@ -4627,223 +4627,223 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - + + + + + - + - + - + @@ -4871,65 +4871,65 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - + + + + + @@ -4947,174 +4947,174 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + @@ -5126,242 +5126,242 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - + - + @@ -5390,899 +5390,899 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + @@ -6307,14 +6307,14 @@ - + - + @@ -6322,7 +6322,7 @@ - + @@ -6364,849 +6364,849 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - - - - - - - - - + + + + + + + + + - + - + - + - + - + - + - + - + - + @@ -7229,7 +7229,7 @@ - + @@ -7242,7 +7242,7 @@ - + @@ -7270,1600 +7270,1600 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - - - + + + + + + + - + - + - + - + - + - + @@ -8925,13 +8925,13 @@ - + - + @@ -8985,1195 +8985,1195 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - - - - + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -10215,13 +10215,13 @@ - + - + @@ -10229,20 +10229,20 @@ - + - + - + @@ -10278,1317 +10278,1317 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - - - + + + + + + + - - - - + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -11638,7 +11638,7 @@ - + @@ -11646,19 +11646,19 @@ - + - + - + @@ -11700,1447 +11700,1447 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - - - - - - - - + + + + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -13190,7 +13190,7 @@ - + @@ -13199,7 +13199,7 @@ - + @@ -13270,1133 +13270,1133 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - - - - - - + + + + + + + + + + @@ -14408,58 +14408,58 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -14519,12 +14519,12 @@ - + - + @@ -14559,1066 +14559,1066 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - - - - - - - - - - - - - - + + + + + + + + + + + + + + - - - - - - + + + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -15662,7 +15662,7 @@ - + @@ -15670,7 +15670,7 @@ - + @@ -15702,736 +15702,736 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - - + + - + @@ -16448,61 +16448,61 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -16545,7 +16545,7 @@ - + @@ -16592,515 +16592,515 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + @@ -17114,12 +17114,12 @@ - + - + - + @@ -17170,637 +17170,637 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + @@ -17902,90 +17902,90 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + @@ -18005,115 +18005,115 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + @@ -18127,18 +18127,18 @@ - + - + - + - + - + @@ -18151,35 +18151,35 @@ - + - + - + - + - + - + - + - + - + - + @@ -18198,7 +18198,7 @@ - + @@ -18210,430 +18210,430 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -18654,20 +18654,20 @@ - + - + - + @@ -18724,172 +18724,172 @@ - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - - + + - + - + - + - + - + - + - + - + - + @@ -18905,213 +18905,213 @@ - - + + - + - - - - + + + + - - - - + + + + - - - - + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -19119,13 +19119,13 @@ - + - + @@ -19138,27 +19138,27 @@ - + - + - + - + - + - + - + - + @@ -19178,105 +19178,105 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -19285,730 +19285,730 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - - - - + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -20042,7 +20042,7 @@ - + @@ -20134,49 +20134,49 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -20185,91 +20185,91 @@ - - - - + + + + - - + + - + - - + + - + - + - + - - + + - - - + + + - + - + - + - + - + - + - + - + - + - + - + @@ -20278,61 +20278,61 @@ - - - + + + - - + + - + - + - + - + - + - + - + - + - + - + - + @@ -20340,45 +20340,45 @@ - + - - - + + + - - + + - - + + - - + + - - + + - + - + @@ -20388,169 +20388,169 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + @@ -20562,24 +20562,24 @@ - + - + - + - + - + - + - + @@ -20587,158 +20587,158 @@ - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -20779,15 +20779,15 @@ - - - - - - + + + + + + - + @@ -20937,42 +20937,42 @@ - - - - - + + + + + - + - - - - - + + + + + - + - - - - + + + + - - + + @@ -20983,439 +20983,439 @@ - + - - + + - - - + + + - - - - - + + + + + - - - + + + - - + + - - - - + + + + - - + + - - - - + + + + - - - - - - - + + + + + + + - - - - - + + + + + - - + + - - + + - - + + - + - + - + - + - + - + - - - - - - + + + + + + - - + + - - - - - - - + + + + + + + - - - - - - + + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - + + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - + - + - + - + - + - + - + - + - + - + - + @@ -21450,10 +21450,10 @@ - - - - + + + + @@ -21532,218 +21532,218 @@ - + - + - + - + - - - + + + - - - + + + - - - + + + - - + + - - + + - - - + + + - - + + - - - + + + - - + + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -21757,141 +21757,141 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -21902,55 +21902,55 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -21959,122 +21959,122 @@ - + - + - + - + - + - + - - + + - - - - + + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - - + + + + - - - + + + - - + + - - + + - + @@ -22097,415 +22097,415 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - - - - - + + + + + - - - - - - + + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + @@ -22545,11 +22545,11 @@ - + - + @@ -22640,49 +22640,49 @@ - - - - + + + + - - - + + + - - - + + + - - - - + + + + - - + + - - + + - - - + + + - + - + @@ -22695,36 +22695,36 @@ - + - + - + - + - + - + - + - + - + - + @@ -22732,30 +22732,30 @@ - - - - - - - + + + + + + + - - + + - - - + + + - - + + - - + + @@ -22773,29 +22773,29 @@ - - + + - + - + - + - + - + - + @@ -22808,7 +22808,7 @@ - + @@ -22816,206 +22816,206 @@ - + - + - + - + - - - - - - + + + + + + - - - + + + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - - - + + + - - + + - - - - + + + + - - + + - - + + - + - + - + - + - + - + - + - + - - + + @@ -23023,27 +23023,27 @@ - - + + - + - + - + - + - + - + - + @@ -23051,14 +23051,14 @@ - - - + + + - - - + + + @@ -23082,27 +23082,27 @@ - - + + - + - + - + @@ -23111,61 +23111,61 @@ - - - - + + + + - - - + + + - + - + - + - - + + - + - + - + - + - + @@ -23173,76 +23173,76 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -23252,134 +23252,134 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -23387,149 +23387,149 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -23547,143 +23547,143 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - + + + + + - + - + - - - - + + + + - - - - + + + + - - + + - + - + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + @@ -23700,123 +23700,123 @@ - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -23824,59 +23824,59 @@ - + - - + + - - - - - + + + + + - - - - + + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - + @@ -23888,68 +23888,68 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + @@ -23974,42 +23974,42 @@ - - + + - + - - + + - + - + - + - + - - - - - + + + + + - - - - - + + + + + @@ -24019,46 +24019,46 @@ - - - - - - + + + + + + - + - - - - + + + + - - - - + + + + - - - - - - + + + + + + - - - - - - - - + + + + + + + + @@ -24068,26 +24068,26 @@ - + - + - + - + - + - - + + - - + + @@ -24096,46 +24096,46 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -24143,47 +24143,47 @@ - - - + + + - + - - - + + + - - - - + + + + - - - - + + + + - - - + + + - - - + + + - - - - + + + + @@ -24191,485 +24191,485 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - - + + - - + + - - + + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + @@ -24695,49 +24695,49 @@ - - - + + + - - - + + + - - - - + + + + - - + + - - - + + + - + - + - - - + + + - - + + - + @@ -24745,7 +24745,7 @@ - + @@ -24753,7 +24753,7 @@ - + @@ -24813,450 +24813,450 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - - + + - - + + - - - - - - + + + + + + - - + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - + + - - + + - - + + - - - + + + - - + + - - - + + + - - + + - - + + - - + + - + - + - - - - + + + + - - - - - + + + + + - - - - - + + + + + - - - - - + + + + + - - - - + + + + - - - - + + + + - - + + - - - + + + - - + + - + - - + + - - - + + + - - - - + + + + - - - + + + - - + + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -25269,180 +25269,180 @@ - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -25452,32 +25452,32 @@ - + - + - + - + - + - + - - - - - - - - - + + + + + + + + + @@ -25488,93 +25488,93 @@ - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - - - - - + + + + + - + - + - + - + - + @@ -25582,198 +25582,198 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -25781,88 +25781,88 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -25870,169 +25870,169 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -26041,81 +26041,81 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -26129,198 +26129,198 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -26330,25 +26330,25 @@ - - - - - - - - + + + + + + + + - - - - + + + + - - - + + + @@ -26357,411 +26357,411 @@ - - - - - - - - + + + + + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -26784,7 +26784,7 @@ - + @@ -26853,614 +26853,614 @@ - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - + - + - + - - - - - - - + + + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -27499,77 +27499,77 @@ - - - - - - - + + + + + + + - - - - + + + + - + - + - - - - - - - + + + + + + + - - - - + + + + - - - - - - - + + + + + + + - - - - - + + + + + - - - - - + + + + + - - - + + + - - - - - + + + + + @@ -27656,266 +27656,266 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - - + + - - + + - - - + + + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + @@ -27924,12 +27924,12 @@ - - + + - - + + @@ -27958,388 +27958,388 @@ - - + + - + - + - - - - + + + + - - - + + + - + - + - - - + + + - + - + - + - + - - + + - + - + - - - - - - - + + + + + + + - - - - - - - - + + + + + + + + - - - - - - - - - + + + + + + + + + - - - - - - + + + + + + - - + + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -28372,159 +28372,159 @@ - - + + - - + + - - + + - - + + - - + + - - - + + + - - + + - - + + - - + + - - + + - - + + - - - + + + - - - + + + - + - + - - + + - - - + + + - - - + + + - - + + - - + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - - + + + + - - + + - - - - + + + + - - + + - - + + - - - + + + - + @@ -28602,50 +28602,50 @@ - - - - + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + @@ -28653,59 +28653,59 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -28713,24 +28713,24 @@ - + - + - + - + - + - + - + @@ -28739,77 +28739,77 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -28828,132 +28828,132 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -28970,8 +28970,8 @@ - - + + @@ -28998,116 +28998,116 @@ - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -29120,37 +29120,37 @@ - - + + - - + + - - + + - - + + - - - + + + - - + + - - + + - - + + @@ -29187,162 +29187,162 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -29350,97 +29350,97 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -29449,32 +29449,32 @@ - + - - - - - + + + + + - + - - + + - - + + - - + + @@ -29489,358 +29489,358 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - - - - - + + + + + - - - + + + - - - - - + + + + + - - - + + + - - - - + + + + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -29848,44 +29848,44 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -29902,62 +29902,62 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -29966,291 +29966,291 @@ - - + + - + - + - + - + - + - + - - - - - - - + + + + + + + - - - + + + - - - - + + + + - - - - + + + + - - + + - - + + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - - + + @@ -30260,46 +30260,46 @@ - + - + - + - + - + - + - + - + - + - + - + - + - - + + @@ -30310,55 +30310,55 @@ - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -30366,88 +30366,88 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -30459,52 +30459,52 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -30545,37 +30545,37 @@ - - + + - - + + - - + + - - - - - + + + + + - - - + + + - - + + - - - + + + @@ -30717,38 +30717,38 @@ - - + + - + - + - + - + - + - + - - - - + + + + - - + + @@ -30762,203 +30762,203 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - - + + - - - + + + - - - + + + - + - + - + - + - + - + - - - - + + + + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -30973,13 +30973,13 @@ - + - + - + @@ -30992,212 +30992,212 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - - - - - + + + + + - - - - - + + + + + - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - + + - - + + - - + + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -31205,43 +31205,43 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -31251,26 +31251,26 @@ - - + + - - + + - - + + - - + + - - - - + + + + @@ -31287,94 +31287,94 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -31384,7 +31384,7 @@ - + @@ -31402,64 +31402,64 @@ - - - - - + + + + + - - - - - + + + + + - - - - + + + + - - - - - - - + + + + + + + - - - - + + + + - + - + - - - - - + + + + + - + - + @@ -31469,28 +31469,28 @@ - - + + - + - + - + - - - + + + - - + + @@ -31500,22 +31500,22 @@ - + - - - - - + + + + + - - + + @@ -31528,178 +31528,178 @@ - - + + - - - + + + - + - - - - + + + + - - - - + + + + - - - - - - - - - + + + + + + + + + - - - + + + - - - + + + - - - - + + + + - - + + - - - + + + - - - + + + - - - + + + - - + + - - + + - - + + - - - + + + - - - + + + - - + + - - + + - - + + - - + + - - - + + + - - - + + + - - - - + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -31708,15 +31708,15 @@ - + - + - + @@ -31738,334 +31738,334 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -32087,26 +32087,26 @@ - + - + - + - + @@ -32114,498 +32114,498 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -32625,7 +32625,7 @@ - + @@ -32641,274 +32641,274 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -32925,12 +32925,12 @@ - + - + @@ -32941,225 +32941,225 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -33178,7 +33178,7 @@ - + @@ -33193,334 +33193,334 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -33552,519 +33552,519 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -34091,7 +34091,7 @@ - + @@ -34138,340 +34138,340 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -34490,7 +34490,7 @@ - + @@ -34506,176 +34506,176 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -34711,163 +34711,163 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -34875,12 +34875,12 @@ - + - + - + @@ -34892,95 +34892,95 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -34991,72 +34991,72 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -35065,57 +35065,57 @@ - + - + - + - + - + - + - + - + - + - + - - - + + + - - - + + + - - + + - - + + - + @@ -35123,97 +35123,97 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -35226,215 +35226,215 @@ - + - + - + - + - - - + + + - - - + + + - - - + + + - + - + - + - - - + + + - - - - + + + + - + - - - + + + - - - - + + + + - + - - + + - - - + + + - - - - + + + + - - - + + + - - - + + + - - - - - - - - - - - - - + + + + + + + + + + + + + - + - + - + - + - + - - - + + + - - - + + + - + - - + + - + - - - + + + - - + + - - - + + + - - - + + + - + - - - - - - + + + + + + - + - + @@ -35463,352 +35463,352 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - - - - + + + + - - + + - - - + + + - + - - + + - - + + - - - + + + - - - + + + - - + + - - + + - - - + + + - - + + - - - + + + - - - + + + - - + + - - + + - - - + + + - - + + - - - + + + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -35816,21 +35816,21 @@ - + - - + + - - + + - - + + @@ -35840,14 +35840,14 @@ - - - - - + + + + + - + @@ -35856,105 +35856,105 @@ - - - + + + - + - + - + - - - + + + - - + + - - + + - - + + - - + + - - - - + + + + - - - - - - + + + + + + - - + + - - - + + + - - + + - + - + - - + + - - + + - - + + - - + + - + - + @@ -35962,7 +35962,7 @@ - + @@ -35970,69 +35970,69 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + @@ -36040,31 +36040,31 @@ - + - - + + - + - + - + - + @@ -36073,7 +36073,7 @@ - + @@ -36085,57 +36085,57 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -36164,556 +36164,556 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -36756,7 +36756,7 @@ - + @@ -36765,1235 +36765,1235 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -38002,570 +38002,570 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -38576,799 +38576,799 @@ - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -39627,61 +39627,61 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -40416,146 +40416,146 @@ - + - + - + - + - + - + - - + + - - - - - - - + + + + + + + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -40567,102 +40567,102 @@ - - - + + + - - - + + + - - - + + + - - - + + + - - + + - - + + - - + + - - + + - - - - - + + + + + - - - - - + + + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - + - - + + - + - - + + - + - + @@ -40675,7 +40675,7 @@ - + @@ -40691,520 +40691,520 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -41219,143 +41219,143 @@ - - - - - - - + + + + + + + - - + + - - + + - - - - + + + + - - + + - - + + - - - + + + - - - - + + + + - - - - + + + + - + - - - - + + + + - + - + - - - + + + - - - - - + + + + + - + - - - - + + + + - - - - - + + + + + - - - + + + - - - + + + - - + + - - - + + + - - - + + + - - + + - + - - + + - + @@ -41371,90 +41371,90 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -41470,124 +41470,124 @@ - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -41596,173 +41596,173 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - - + + - - + + - - - + + + - - - + + + - - - + + + - + - - + + - - - + + + - - - - + + + + - + - + - - + + - - - - + + + + @@ -41773,208 +41773,208 @@ - - - + + + - + - - - + + + - - - + + + - - - - - + + + + + - - - + + + - - - - - + + + + + - - - + + + - + - + - + - + - + - - - + + + - - - + + + - - + + - + - + - + - - - - + + + + - + - - - - + + + + - + - - + + - + - - + + - + - - + + - - - - - + + + + + - + - - + + - + - - + + - - + + - - + + - - - - + + + + - - - + + + - + - + - + - + - + @@ -41982,462 +41982,462 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + @@ -42471,54 +42471,54 @@ - - - + + + - - + + - + - + - - - - + + + + - + - + - + - + - + @@ -42608,181 +42608,181 @@ - - - - - + + + + + - - - + + + - - + + - - - - + + + + - - + + - + - + - + - + - + - - - - - + + + + + - - - - - + + + + + - - - - + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -42794,32 +42794,32 @@ - - + + - + - - + + - - - + + + - - + + - - - + + + @@ -42833,8 +42833,8 @@ - - + + @@ -42849,99 +42849,99 @@ - - - - - - - - - + + + + + + + + + - - + + - - - - + + + + - - + + - - - + + + - - - + + + - - + + - - - - - - - - - + + + + + + + + + - - + + - + - - - - - + + + + + - + - + - + - + - + - + - + - + - + @@ -42949,23 +42949,23 @@ - + - + - - - - - + + + + + - + @@ -42973,179 +42973,179 @@ - + - + - + - + - - - + + + - - + + - - + + - - + + - - - + + + - - - + + + - - - - + + + + - - - - + + + + - - + + - - + + - + - + - + - + - + - + - + - + - - - - - + + + + + - + - - - - - - + + + + + + - + - - - + + + - - - + + + - - - + + + - + - + - + - + - - - + + + - - - - + + + + - + @@ -43168,304 +43168,304 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -43474,126 +43474,126 @@ - - + + - + - + - + - + - + - - - - + + + + - + - + - + - + - + - + - + - + - + - + - - + + - - + + - - + + - - + + - - + + - - - - + + + + - + - + - + @@ -43606,7 +43606,7 @@ - + @@ -43616,7 +43616,7 @@ - + @@ -43625,136 +43625,136 @@ - + - - + + - + - + - + - + - + - + - + - + - + - + - - - + + + - - + + - - - - + + + + - - + + - - - + + + - - + + - - + + - - - + + + - - + + - - + + - - + + - + - + - + - + - + - - + + - + @@ -43764,493 +43764,493 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -44291,7 +44291,7 @@ - + @@ -44407,244 +44407,244 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -44663,18 +44663,18 @@ - + - + - + - + - + @@ -44684,143 +44684,143 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -44837,51 +44837,51 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -44906,84 +44906,84 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -45065,7 +45065,7 @@ - + @@ -45082,39 +45082,39 @@ - + - + - + - + - + - + - + - + - + - + - + - + @@ -45124,142 +45124,142 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -45272,36 +45272,36 @@ - + - + - + - + - + - + - + - + - + - + - + @@ -45309,29 +45309,29 @@ - - - - - + + + + + - - - - + + + + - - - - - - + + + + + + - - + + @@ -45343,46 +45343,46 @@ - - + + - + - + - + - - - - + + + + - - + + - - - + + + - - - - + + + + - - - + + + - + @@ -45392,318 +45392,318 @@ - - + + - - + + - - - + + + - - - - + + + + - - - + + + - - - + + + - - - - - - - - + + + + + + + + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -45741,53 +45741,53 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -45796,92 +45796,92 @@ - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -45890,21 +45890,21 @@ - + - + - + - + - + - + @@ -45953,15 +45953,15 @@ - - - + + + - - - - + + + + @@ -46135,171 +46135,171 @@ - + - + - + - + - + - - - + + + - - + + - - - + + + - - - + + + - - - + + + - - - - + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -46312,196 +46312,196 @@ - + + + + + + + + + + + + + + + + + + + + - + - + - + - + - - - - - - - - - - - - - - - - - - - - + - - - - - + + + + + - - + + - - - - - - - + + + + + + + - - + + - - + + - - - - + + + + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -46512,65 +46512,65 @@ - - - + + + - - - + + + - - - + + + - - - - + + + + - - - - + + + + - - + + - - + + - - + + - - - + + + - - - + + + - - + + - - + + - - + + @@ -46597,47 +46597,47 @@ - - - + + + - - + + - - - + + + - - - - + + + + - - + + - + - + - + - + - + - + @@ -46647,110 +46647,110 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -46765,14 +46765,14 @@ - - - - + + + + - - + + @@ -46819,265 +46819,265 @@ - - + + - + - + - + - + - - + + - - + + - - - - - + + + + + - - + + - - - - + + + + - - - - - - + + + + + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - - - + + + + - - - + + + - + - + - - + + - - - - + + + + - - + + - - + + - - - + + + - - - + + + - - - - + + + + - - - - - - + + + + + + - - - - - + + + + + - - - - + + + + - - + + - + - - - - + + + + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + @@ -47092,23 +47092,23 @@ - + - + - + - + @@ -47161,54 +47161,54 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -47220,8 +47220,8 @@ - - + + @@ -47230,12 +47230,12 @@ - - + + - + @@ -47243,117 +47243,117 @@ - - + + - - + + - + - + - + - + - - + + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -47363,14 +47363,14 @@ - - - - + + + + - - + + @@ -47394,96 +47394,96 @@ - - - - - + + + + + - - - - - + + + + + - - - + + + - - - + + + - - - + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -47495,27 +47495,27 @@ - - - + + + - - - + + + - - + + - - + + - - - + + + @@ -47546,56 +47546,56 @@ - + - + - + - + - + - + - + - - - + + + - - - + + + - - - + + + - - + + - - + + - - - + + + - + @@ -47609,211 +47609,211 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -47836,114 +47836,114 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -47954,134 +47954,134 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -48091,78 +48091,78 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -48178,15 +48178,15 @@ - + - + - + - + @@ -48194,64 +48194,64 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -48261,84 +48261,84 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -48346,260 +48346,260 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - - - - - + + + + + - - + + - + - + - + - + - + - + - - + + - - - + + + - - - + + + - - - - + + + + - - - + + + - - - - + + + + - - - - + + + + - - - + + + - - - + + + - - - + + + - - + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - + + + - - + + - - - - - + + + + + - - - + + + - - + + - - + + - + @@ -48621,102 +48621,102 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -48728,272 +48728,272 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -49009,78 +49009,78 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + @@ -49090,391 +49090,391 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -49511,30 +49511,30 @@ - - + + - - - + + + - - + + - - + + - - - + + + - - + + @@ -49584,238 +49584,238 @@ - + - + - + - + - - + + - + - + - + - - - - + + + + - - - - - - + + + + + + - - + + - - - - - - + + + + + + - - + + - - + + - - - - + + + + - - + + - + - + - + - + - + - + - + - + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - + + + + + - - + + - - + + - - - + + + - - - - + + + + - - - - - - - - + + + + + + + + - - - - - - - + + + + + + + - - + + - - + + - - - + + + - - - - - - + + + + + + - - - + + + - - - + + + - - - + + + @@ -49823,7 +49823,7 @@ - + @@ -49851,225 +49851,225 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -50077,143 +50077,143 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -50230,191 +50230,191 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -50432,13 +50432,13 @@ - + - + @@ -50448,384 +50448,384 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + @@ -50851,202 +50851,202 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -51076,415 +51076,415 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -51543,18 +51543,18 @@ - + - + - + - + - + @@ -51565,7 +51565,7 @@ - + @@ -51620,30 +51620,30 @@ - + - + - + - + - + - + - + - + - + @@ -51656,335 +51656,335 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -51992,347 +51992,347 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -52342,639 +52342,639 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -52984,822 +52984,822 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -53817,567 +53817,567 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -54606,39 +54606,39 @@ - + - - + + - - + + - - + + - - + + - - - - - - + + + + + + - + - - + + @@ -55250,112 +55250,112 @@ - + - + - + - + - - - - + + + + - - + + - - + + - - + + - - - + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -55368,30 +55368,30 @@ - - - + + + - - - + + + - - + + - - - - - + + + + + - - - + + + @@ -55414,36 +55414,36 @@ - + - - - + + + - - + + - - + + - - + + - - + + - - + + - + @@ -55485,50 +55485,50 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -55552,813 +55552,813 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -56374,291 +56374,291 @@ - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -56668,225 +56668,225 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -56951,20 +56951,20 @@ - - - - - + + + + + - + - + @@ -57083,102 +57083,102 @@ - - - - - + + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -57193,12 +57193,12 @@ - + - + @@ -57233,14 +57233,14 @@ - - + + - + @@ -57252,1128 +57252,1128 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -58409,9 +58409,9 @@ - - - + + + @@ -58493,361 +58493,361 @@ - - - + + + - + - - - - + + + + - - + + - + - + - + - - + + - - - - + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -58870,315 +58870,315 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -59203,65 +59203,65 @@ - - + + - - + + - - - + + + - - - + + + - - - + + + - - - + + + - - + + - - - + + + - - - - - + + + + + - - + + - - + + - - + + - - - + + + @@ -59364,40 +59364,40 @@ - + - + - + - + - + - + - + - + - + @@ -59406,87 +59406,87 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -59499,411 +59499,411 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -59925,7 +59925,7 @@ - + @@ -59934,7 +59934,7 @@ - + @@ -59955,108 +59955,108 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + @@ -60071,466 +60071,466 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -60557,7 +60557,7 @@ - + @@ -60605,661 +60605,661 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + @@ -61357,608 +61357,608 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -62020,1005 +62020,1005 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -63033,12 +63033,12 @@ - + - + - + @@ -63055,7 +63055,7 @@ - + @@ -63067,14 +63067,14 @@ - + - + @@ -63128,800 +63128,800 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + @@ -63961,871 +63961,871 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -64847,7 +64847,7 @@ - + @@ -64902,721 +64902,721 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -65698,300 +65698,300 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + @@ -66014,7 +66014,7 @@ - + @@ -66026,518 +66026,518 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + @@ -66575,401 +66575,401 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + @@ -67007,305 +67007,305 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -67320,156 +67320,156 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -67479,506 +67479,506 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -67987,46 +67987,46 @@ - - - + + + - - - + + + - - - + + + - - + + - - + + - - - - + + + + - + - - - - - + + + + + @@ -68041,146 +68041,146 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - - + + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -68194,42 +68194,42 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -68238,7 +68238,7 @@ - + @@ -68249,375 +68249,375 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -68626,20 +68626,20 @@ - + - + - + - + - + @@ -68648,8 +68648,8 @@ - - + + @@ -68706,36 +68706,36 @@ - - + + - - - - + + + + - - + + - - + + - - - + + + - - - + + + - - + + @@ -68853,21 +68853,21 @@ - + - + - + - + - + - + @@ -68878,137 +68878,137 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -69017,67 +69017,67 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + @@ -69087,146 +69087,146 @@ - - - - - - - - - + + + + + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - - + + + + + + - - + + - - + + - - + + - + - + - - + + - + - + - + - + - + @@ -69238,7 +69238,7 @@ - + @@ -69249,538 +69249,538 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -69799,134 +69799,134 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -69935,15 +69935,15 @@ - + - + - + - + @@ -69955,103 +69955,103 @@ - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -70059,7 +70059,7 @@ - + @@ -70068,9 +70068,9 @@ - + - + @@ -70083,15 +70083,15 @@ - + - + - + @@ -70099,140 +70099,140 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -70254,29 +70254,29 @@ - + - + - + - + - + - + - + - - + + @@ -70286,221 +70286,221 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -70511,413 +70511,413 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -70927,7 +70927,7 @@ - + @@ -70939,7 +70939,7 @@ - + @@ -70947,195 +70947,195 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -71156,225 +71156,225 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -71383,64 +71383,64 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -71458,347 +71458,347 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -71813,35 +71813,35 @@ - + - + - + - + - + - + - + @@ -71892,89 +71892,89 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -71982,104 +71982,104 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -72101,553 +72101,553 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -72659,7 +72659,7 @@ - + @@ -72669,491 +72669,491 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + @@ -73187,17 +73187,17 @@ - + - + - + @@ -73209,52 +73209,52 @@ - + - + - + - + - + - + - + - + - + - + - + @@ -73262,11 +73262,11 @@ - + - + @@ -73275,11 +73275,11 @@ - + - + @@ -73314,18 +73314,18 @@ - + - + - + - + - + @@ -73333,311 +73333,311 @@ - + - + - + - - - - + + + + - + - + - - - + + + - + - + - - + + - - + + - - - + + + - - - + + + - - - + + + - - + + - + - - + + - - + + - - - + + + - - + + - - - + + + - - + + - + - + - - - - - - - - + + + + + + + + - - - - - - - - + + + + + + + + - - - - - - - - + + + + + + + + - - - - - - - - + + + + + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - - - - + + + + - - - + + + - - - - + + + + - - - - + + + + - - - - - - + + + + + + - - - + + + - - + + - + - + - + - + - + - + - + - + - + - + @@ -73645,18 +73645,18 @@ - - - - + + + + - - + + - - + + @@ -73670,91 +73670,91 @@ - - - + + + - - - - - - - + + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -73763,22 +73763,22 @@ - - + + - - + + - - - + + + - - - + + + @@ -73786,83 +73786,83 @@ - - - - + + + + - - - + + + - + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - - + + + + + - - - - + + + + - + - - - + + + - - + + - - + + @@ -73871,89 +73871,89 @@ - - + + - - + + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -73961,252 +73961,252 @@ - + - + - + - + - + - + - + - + - + - + - + - + - - + + - - + + - + - - - - - - + + + + + + - + - - - - + + + + - + - - - - - - + + + + + + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - - + + - - - - + + + + - - + + - + - - - + + + - - + + - - + + - - + + - - - + + + - - - + + + - - + + - - + + - + - - + + - + - - - + + + - - + + - - + + - - + + - + @@ -74214,8 +74214,8 @@ - - + + @@ -74223,9 +74223,9 @@ - + - + @@ -74233,11 +74233,11 @@ - + - + @@ -74249,102 +74249,102 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -74359,58 +74359,58 @@ - + - - - + + + - + - + - + - + - + - - + + - + - - + + - + @@ -74462,89 +74462,89 @@ - - + + - - - - - + + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -74565,111 +74565,111 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -74684,94 +74684,94 @@ - - + + - - + + - + - + - - + + - - + + - - + + - + - + - - + + - - - - + + + + - - + + - + - - - + + + - - - + + + - + - + - - - - + + + + - - - - - + + + + + - + @@ -74807,153 +74807,153 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -74961,71 +74961,71 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -75053,99 +75053,99 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -75186,77 +75186,77 @@ - - + + - + - - + + - - + + - - - + + + - - - + + + - + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - - - + + + + - - - - - + + + + + @@ -75314,8 +75314,8 @@ - - + + @@ -75323,223 +75323,223 @@ - + - - + + - - - - - - + + + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -75561,19 +75561,19 @@ - + - + - + @@ -75581,15 +75581,15 @@ - + - + - + @@ -75682,266 +75682,266 @@ - + - + - + - + - - + + - - + + - + - + - + - + - + - - - - + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -75949,79 +75949,79 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -76061,40 +76061,40 @@ - - + + - - + + - - - + + + - - - - + + + + - - - - + + + + - - + + - - + + - + @@ -76105,11 +76105,11 @@ - + - + @@ -76212,161 +76212,161 @@ - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -76385,28 +76385,28 @@ - - + + - - + + - - - + + + - - - - + + + + - - - + + + @@ -76457,640 +76457,640 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -77126,113 +77126,113 @@ - - - + + + - - + + - - + + - - - + + + - - - + + + - - + + - - + + - - - + + + - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - + + - - - + + + - - + + - - - + + + - - - + + + - - - + + + - - - - + + + + - + - - + + - - + + - - + + @@ -77316,52 +77316,52 @@ - - - - + + + + - - + + - - - - + + + + - - - + + + - - + + - + - + - - + + - + - + @@ -77371,63 +77371,63 @@ - - - + + + - + - - - - + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -77435,28 +77435,28 @@ - - - + + + - - + + - - - - - - - + + + + + + + - - - - + + + + @@ -77470,144 +77470,144 @@ - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -77632,66 +77632,66 @@ - - - - - + + + + + - - + + - - - - + + + + - - - - + + + + - - - - + + + + - - + + - - - - + + + + - - - + + + - - + + - - - + + + - - - + + + - - + + @@ -77766,162 +77766,162 @@ - - - + + + - - - + + + - - - - - + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -77935,221 +77935,221 @@ - - + + - + - - - - - + + + + + - - - - + + + + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + @@ -78164,104 +78164,104 @@ - - - - + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - - + + - - - - + + + + - - + + @@ -78280,379 +78280,379 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -78680,939 +78680,939 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -79620,7 +79620,7 @@ - + @@ -79630,24 +79630,24 @@ - + - + - + - + - - + + - + - + @@ -79690,20 +79690,20 @@ - - - + + + - - + + - - + + - + @@ -79797,115 +79797,115 @@ - + - + - + - - - + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + @@ -79916,37 +79916,37 @@ - + - - - - - - + + + + + + - - - + + + - - - + + + - - - - + + + + - + @@ -79979,10 +79979,10 @@ - + - + @@ -79990,39 +79990,39 @@ - - - - + + + + - - - - + + + + - + - + - + - - + + - - + + - + @@ -80030,80 +80030,80 @@ - + - - - - - + + + + + - - - + + + - - + + - - + + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + @@ -80124,475 +80124,475 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -80602,312 +80602,312 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -80915,408 +80915,408 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -81324,63 +81324,63 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -81396,41 +81396,41 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -81477,12 +81477,12 @@ - + - + @@ -81597,24 +81597,24 @@ - - - - - + + + + + - - + + - - + + - - + + @@ -81622,7 +81622,7 @@ - + @@ -81630,34 +81630,34 @@ - - - + + + - - + + - - + + - - + + - - + + - - + + - - + + @@ -81669,7 +81669,7 @@ - + @@ -81686,7 +81686,7 @@ - + @@ -81717,7 +81717,7 @@ - + @@ -81731,85 +81731,85 @@ - - - - - + + + + + - - + + - - - + + + - - + + - - - - - - + + + + + + - - - - - - - + + + + + + + - - - - - - - - + + + + + + + + - - + + - - + + - + - + - + - + - + - + @@ -81817,56 +81817,56 @@ - - + + - + - + - + - + - + - + - + - + - - - - + + + + - - - - + + + + - - - - + + + + - - + + @@ -81876,29 +81876,29 @@ - - + + - + - + - + - + - + - + @@ -81906,135 +81906,135 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -82052,27 +82052,27 @@ - - + + - - - + + + - - + + - - - - + + + + - - + + @@ -82110,44 +82110,44 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -82158,67 +82158,67 @@ - - - - + + + + - - - - - + + + + + - - - - - + + + + + - - - - + + + + - - - + + + - - - - - + + + + + - - - - - + + + + + - - - + + + - - + + - - + + - - - + + + @@ -82254,120 +82254,120 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -82377,19 +82377,19 @@ - - - - + + + + - - + + - - - + + + @@ -82414,218 +82414,218 @@ - - - + + + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -82639,25 +82639,25 @@ - + - + - + - + - - + + @@ -82679,58 +82679,58 @@ - - + + - - - + + + - - + + - + - - + + - + - + - + - + - + - + - + - + - + - + @@ -82741,41 +82741,41 @@ - - + + - - - + + + - - + + - - - - - + + + + + - + - - - + + + - - - - - + + + + + @@ -82801,82 +82801,82 @@ - - - - + + + + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -82887,116 +82887,116 @@ - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -83009,33 +83009,33 @@ - - - - + + + + - + - - + + - - - + + + - - - - - + + + + + - - + + @@ -83075,368 +83075,368 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -83446,99 +83446,99 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + @@ -83546,108 +83546,108 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -83667,66 +83667,66 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -83791,88 +83791,88 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -83891,46 +83891,46 @@ - - + + - - + + - - + + - - - - - + + + + + - - - + + + - - - + + + - - - + + + - + - + @@ -83987,179 +83987,179 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -84171,27 +84171,27 @@ - - + + - - + + - - + + - - + + - - + + - + @@ -84208,177 +84208,177 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -84386,77 +84386,77 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + @@ -84472,65 +84472,65 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -84539,86 +84539,86 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -84630,31 +84630,29 @@ - - + + + + + + + + + + + + - - - - - - - - - - - - - + - + @@ -84664,385 +84662,385 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -85071,102 +85069,102 @@ - - - - - - - + + + + + + + - - - + + + - - + + - - - - + + + + - - - - - - + + + + + + - - - - - + + + + + - - - - - - + + + + + + - - - + + + - - - + + + - - + + - - + + - - - + + + - - - + + + - - - - - - + + + + + + - + - + - + @@ -85266,86 +85264,86 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -85366,507 +85364,507 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -85903,32 +85901,32 @@ - + - + - + - + - + - + - + @@ -86025,32 +86023,32 @@ - - - - - - + + + + + + - - - - + + + + - - + + - - + + - + @@ -86061,140 +86059,140 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -86207,14 +86205,14 @@ - - - - + + + + - - + + @@ -86237,502 +86235,502 @@ - - + + - - + + - - - + + + - - + + - - + + - + - - + + - - - - - - - - - + + + + + + + + + - - + + - + - - - - + + + + - - - - - + + + + + - - + + - - + + - - - - - + + + + + - - - - - - + + + + + + - - + + - - - - + + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - - + + + + - - + + - - + + - - - + + + - - + + - - - - - + + + + + - - - - + + + + - - - - + + + + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -86754,119 +86752,119 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -86877,13 +86875,13 @@ - + - + @@ -86892,7 +86890,7 @@ - + @@ -86900,7 +86898,7 @@ - + @@ -86912,108 +86910,108 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -87039,516 +87037,516 @@ - - - - + + + + - - + + - - - + + + - - + + - - - + + + - + - + - - + + - + - + - + - + - + - + - + - + - + - - - - - - - + + + + + + + - - - - - - - - - + + + + + + + + + - - + + - - + + - - - + + + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -87556,42 +87554,42 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -87608,15 +87606,15 @@ - + - + - + - + @@ -87624,59 +87622,59 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -87729,64 +87727,64 @@ - + - - - - - - + + + + + + - + - - - - + + + + - - + + - - + + - - + + - - + + - - - + + + - - + + - - - - - + + + + + - - - - - + + + + + @@ -87982,61 +87980,61 @@ - - - - - + + + + + - - - + + + - - + + - - - - + + + + - + - + - + - + - + - + - - + + @@ -88047,423 +88045,423 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -88480,32 +88478,32 @@ - + - + - + - + - + - + - + - + - + - + @@ -88530,224 +88528,224 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -88766,44 +88764,44 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -88815,78 +88813,78 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -88895,70 +88893,70 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -88968,22 +88966,22 @@ - - + + - + - + - + - + - + @@ -88992,721 +88990,721 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -89782,16 +89780,16 @@ - - - - - - + + + + + + - - + + @@ -89962,62 +89960,62 @@ - + - - - - - - + + + + + + - - + + - - - - + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + @@ -90042,630 +90040,630 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - + + + + + - + - + - + - + - + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - + - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -90698,7 +90696,7 @@ - + @@ -90707,13 +90705,13 @@ - + - + @@ -90721,7 +90719,7 @@ - + @@ -90809,311 +90807,311 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -91121,7 +91119,7 @@ - + @@ -91130,15 +91128,15 @@ - + - + - + @@ -91147,233 +91145,233 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -91381,72 +91379,72 @@ - - + + - - + + - - - + + + - - - + + + - - - - + + + + - - - + + + - - - - + + + + - - - - + + + + - - - + + + - - + + - - - - + + + + - - + + - - + + - - + + @@ -91465,127 +91463,127 @@ - - - + + + - - + + - - + + - - - - - - - - + + + + - - + + - - + + - - + + - - + + - - + + + + + + - - + + - - + + - - + + - - - - + + + + - - - - + + + + - - - + + + - - - + + + - - - + + + - - + + - - + + - + - - + + - + - + - - - + + + - - + + - - + + - - + + @@ -91594,90 +91592,90 @@ - - + + - - - - + + + + - - - - + + + + - + - + - - + + - - + + - + - - - - + + + + - + - + - + - + - + - + - + - - - + + + - - + + - - + + @@ -91690,114 +91688,114 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - - - + + + - - - - - + + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -91824,262 +91822,262 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -92108,75 +92106,75 @@ - - - + + + - - - + + + - - + + - - - + + + - - - + + + - - + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - + + - - - + + + - - + + @@ -92219,166 +92217,166 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -92398,7 +92396,7 @@ - + @@ -92411,7 +92409,7 @@ - + @@ -92493,162 +92491,162 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -92681,30 +92679,30 @@ - + - + - + - + - + - + @@ -92765,7 +92763,7 @@ - + @@ -92778,727 +92776,727 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -93540,34 +93538,34 @@ - - - - - - + + + + + + - - - + + + - - + + - - + + - - - - - - - + + + + + + + @@ -93675,46 +93673,46 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -93722,165 +93720,165 @@ - - - + + + - - + + - - + + - - + + - - + + - - + + - + - - + + - - - - - - - + + + + + + + - - + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - - + + + + + + + - - + + - - + + - - - - + + + + - - - + + + - - + + - - + + - - - + + + - - + + - - + + - - + + - - - + + + - - - - - - - - - - - + + + + + + + + + + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + @@ -93888,45 +93886,45 @@ - - + + - + - + - + - + - + - + - + - + - + - + - - + + @@ -93934,203 +93932,203 @@ - - - + + + - - + + - + - + - - - - + + + + - - - - - + + + + + - - - - - - + + + + + + - + - - - - + + + + - - - + + + - - - - - + + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -94154,11 +94152,11 @@ - + - + @@ -94215,102 +94213,102 @@ - - + + - + - + - + - + - + - + - + - + - + - - + + - - + + - + - - + + - + - - + + - + - + - + - + - + - + - + - + @@ -94327,147 +94325,147 @@ - - - + + + - - - + + + - - + + - + - + - + - - - - + + + + - - + + - - - - + + + + - - - - + + + + - - - + + + - - - + + + - - + + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -94475,16 +94473,16 @@ - - + + - + - + @@ -94497,8 +94495,8 @@ - - + + @@ -94508,26 +94506,26 @@ - - + + - + - - - + + + - - - - - + + + + + @@ -94537,127 +94535,127 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - - + + - - - - - - + + + + + + - - + + @@ -94666,113 +94664,113 @@ - - + + - - + + - + - + - - - - + + + + - + - - - - - - + + + + + + - - - - - + + + + + - - - + + + - - - - - + + + + + - - - + + + - - - - + + + + - - - + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - + + + - - - - - + + + + + - - - - - + + + + + @@ -94789,186 +94787,186 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - + + + + + - - - - + + + + - - - - + + + + - - - - + + + + - + - - - + + + - - - + + + - - - - - + + + + + - - - - + + + + - - - + + + - - - - + + + + - - - - - + + + + + - - - - - - - + + + + + + + - - + + - + - + @@ -94983,24 +94981,24 @@ - + - + - + - + - + @@ -95008,122 +95006,122 @@ - - - - + + + + - - - + + + - - - + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + @@ -95131,29 +95129,29 @@ - - + + - + - + - - + + - - - - - + + + + + - - - - + + + + @@ -95163,66 +95161,66 @@ - - - - - - - + + + + + + + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + @@ -95230,17 +95228,17 @@ - + - + - + @@ -95259,83 +95257,83 @@ - - - - - + + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - - + + + + + - - - - + + + + - + - + - + - + - - - - - - + + + + + + - - - - + + + + - - - - - - - - - + + + + + + + + + - + @@ -95346,59 +95344,59 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - - + + + + + + - - - - + + + + @@ -95408,59 +95406,59 @@ - - - - + + + + - - - - - - + + + + + + - + - - + + - + - - - - - - + + + + + + - - - + + + - - + + - - + + - - - + + + @@ -95474,73 +95472,73 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -95550,7 +95548,7 @@ - + @@ -95558,47 +95556,47 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -95606,238 +95604,238 @@ - + - - - - + + + + - - - + + + - - - + + + - - - - + + + + - - - - - - - + + + + + + + - - - - - + + + + + - - - - + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -95876,45 +95874,45 @@ - + - + - + - + - + - + - + - + @@ -96054,53 +96052,53 @@ - - + + - - + + - + - + - + - + - + - + - + - + - + @@ -96110,35 +96108,35 @@ - + - + - + - + - + - + @@ -96146,7 +96144,7 @@ - + @@ -96284,362 +96282,362 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -96647,286 +96645,286 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -96935,301 +96933,301 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -97237,83 +97235,83 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -97587,7 +97585,7 @@ - + @@ -97597,7 +97595,7 @@ - + @@ -97607,114 +97605,114 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -97725,3304 +97723,3304 @@ - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - - - - + + + + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - - - + + + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - - - - - - - + + + + + + + - + - - + + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - - - - + + + + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - - + + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - - + + @@ -101030,290 +101028,290 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -101326,159 +101324,159 @@ - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -101491,6093 +101489,6093 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - - + + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - - - + + + - + - - + + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - - - - + + + + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -107585,2333 +107583,2333 @@ - - + + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - - + + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - - + + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -109920,27 +109918,27 @@ - + - + - + - + - + - + - + - + @@ -109948,468 +109946,468 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - - - - - - + + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -110418,648 +110416,648 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -111859,43 +111857,43 @@ - - + + - + - + - + - + - + - + - + @@ -111906,7 +111904,7 @@ - + @@ -111916,150 +111914,150 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -113690,259 +113688,259 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -113950,61 +113948,61 @@ - + - + - + - + - + - + - + - + - + - + - + - + @@ -114025,211 +114023,211 @@ - - - + + + - + - + - + - + - + - + - - + + - - + + - + - - + + - + - - - - + + + + - + - - - - - - + + - - - - - - - - - - - - - - - - - - - - - - - + + - + - + - + - + - + - + - + - + + + + + - + - + - - - + + - + - + + + + + + + - + + + + + + + + + + + + + + + + + - + - + - + - + - + - + - + - - + + - + - + - + - - + + @@ -114237,44 +114235,44 @@ - - - - + + + + - - - + + + - + - - + + - - - - + + + + - - + + - + @@ -114322,617 +114320,617 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -114998,109 +114996,109 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -115110,2084 +115108,2084 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - - + + - + - + - - + + - + - + - + - + - + - + - + - - + + - + - - + + - + - + - - + + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -117204,115 +117202,115 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -117322,94 +117320,94 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -117438,7 +117436,7 @@ - + @@ -117465,591 +117463,591 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + @@ -118078,1906 +118076,1906 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -119986,395 +119984,395 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + @@ -120382,591 +120380,591 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -120976,21 +120974,21 @@ - + - + - + - + - + - + @@ -121008,15 +121006,15 @@ - + - + - + - + @@ -121455,35 +121453,35 @@ - + - + - + - + - + - + - + - + @@ -122808,23 +122806,23 @@ - - - + + + - + - + - + - + @@ -122836,7 +122834,7 @@ - + @@ -123002,15 +123000,15 @@ - - - - - - + + + + + + - + @@ -123018,7 +123016,7 @@ - + @@ -123027,86 +123025,86 @@ - + - + - + - + - - + + - - + + - + - + - + - + - - - - + + + + - - - - - - - + + + + + + + - - - - + + + + - - - + + + - + - + - + @@ -123117,193 +123115,193 @@ - - - + + + - - - + + + - - + + - - + + - - + + - + - + - + - + - + - + - - - - - - + + + + + + - - - - - + + + + + - + - - - - - + + + + + - - - - - + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - - + + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - + - - - - - + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - + - - - - - - - + + + + + + + - + @@ -123311,64 +123309,64 @@ - - - - - - - + + + + + + + - - - + + + - - - + + + - - + + - - + + - - + + - + - + - + - + - + - + - + - + - + @@ -123377,17 +123375,17 @@ - + - + - + @@ -123395,12 +123393,12 @@ - + - + @@ -123418,78 +123416,78 @@ - - + + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -123499,19 +123497,19 @@ - - + + - - + + - + @@ -123520,49 +123518,49 @@ - - + + - + - + - + - + - + - - + + - + - - - + + + - + - + - + @@ -123577,7 +123575,7 @@ - + @@ -123593,506 +123591,506 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -124158,2315 +124156,2315 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -126484,7 +126482,7 @@ - + @@ -126620,120 +126618,120 @@ - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -126741,11 +126739,11 @@ - + - + @@ -126967,147 +126965,147 @@ - - - - + + + + - - + + - - + + - - + + - - - - + + + + - - - + + + - - - + + + - - + + - - + + - - + + - - + + - - + + - - - - - + + + + + - - - - + + + + - - - - - + + + + + - - - - + + + + - - - - + + + + - - + + - - + + - - + + - - + + - - + + - - + + - - - - + + + + - - - + + + - - + + - - - + + + - - - + + + - + @@ -127115,228 +127113,228 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - - - - - + + + + + + + + + - - - - - - - + + + + + + + - - - - + + + + - + - - + + - + - + - + - + - + - + @@ -127347,25 +127345,25 @@ - + - - - + + + - + - + @@ -127373,109 +127371,109 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -127485,32 +127483,32 @@ - + - + - - + + - + - + - + @@ -127519,7 +127517,7 @@ - + @@ -127539,198 +127537,198 @@ - + - - + + - - - - - - - + + + + + + + - - + + - - - + + + - - - + + + - - - + + + - - + + - - + + - - - - - - - + + + + + + + - - - - - - - + + + + + + + - - - - - - - + + + + + + + - - - - - - + + + + + + - - - - + + + + - - - - + + + + - - - - - + + + + + - - - + + + - - + + - - - + + + - - - + + + - - + + - - + + - - + + - - - + + + - - - + + + - - - + + + - - - - - - - + + + + + + + - - - + + + - - + + - - - + + + - - - - - - + + + + + + - - - - + + + + - - - - + + + + - - + + @@ -127738,187 +127736,187 @@ - + - + - - - - + + + + - - - - + + + + - + - - + + - + - + - + - + - - - + + + - - - - + + + + - - + + - + - - - + + + - - - + + + - - + + - - - - + + + + - - + + - - - - + + + + - - + + - - + + - - + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -127926,478 +127924,478 @@ - - - - + + + + - - + + - - + + - - - + + + - - - + + + - - + + - + - + - + - - + + - - + + - - + + - - - - - + + + + + - - + + - + - + - + - - + + - - + + - + - - + + - - + + - - + + - - + + - - + + - - + + - - - + + + - - + + - - + + - - + + - - + + - - - + + + - - + + - + - + - + - + - + - + - + - - + + - + - - - - - - + + + + + + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - - + + - - - + + + - - - + + + - - - - + + + + - - - + + + - - - + + + - - - - + + + + - - - + + + - - - + + + - + - - - - + + + + - + - - + + - + - + - + - + - + - - - + + + - + - + - + - - + + - + - + - + - - - - - - - - - - - + + + + + + + + + + + - + - + - - - + + + - - - + + + - + - + - + - - - + + + - - - + + + - + - + - - - + + + - - - + + + - + - + - + - + - + @@ -128406,29 +128404,29 @@ - - + + - + - + - + - + - + - + - + @@ -128436,132 +128434,132 @@ - + - - - - + + + + - - - + + + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -128569,37 +128567,37 @@ - + - + - + - + - + - + - + - + - + - + - + - + @@ -128609,56 +128607,56 @@ - - + + - - - - + + + + - - - + + + - - + + - - - + + + - - - + + + - + - - - - - + + + + + - - - + + + - - + + - + @@ -128666,7 +128664,7 @@ - + @@ -128674,24 +128672,24 @@ - - + + - + - + - + @@ -128699,337 +128697,337 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + @@ -129057,11 +129055,11 @@ - + - + @@ -129146,43 +129144,43 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + @@ -129191,22 +129189,22 @@ - - - + + + - + - - + + @@ -129239,67 +129237,67 @@ - - + + - + - + - + - + - - + + - - + + - - + + - - - + + + - - + + - + - + - + - - + + @@ -129308,99 +129306,99 @@ - - - + + + - - + + - - + + - - + + - - + + - + - - + + - + - - - - - - + + + + + + - - - - + + + + - + - + - + - + - + - - - - - - + + + + + + - + - + @@ -129416,30 +129414,30 @@ - - - + + + - - + + - - - + + + - - + + - - + + - + @@ -129465,923 +129463,923 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + @@ -130422,7 +130420,7 @@ - + @@ -130438,7 +130436,7 @@ - + @@ -130453,7 +130451,7 @@ - + @@ -130467,41 +130465,41 @@ - + - - - - + + + + - - - + + + - + - + - + - + @@ -130579,56 +130577,56 @@ - + - + - + - - + + - - + + - + - + - + - + - + - + - + @@ -130636,16 +130634,16 @@ - - + + - - + + @@ -130656,196 +130654,196 @@ - + - + - + - + - + - + - - + + - - - - + + + + - - - - - + + + + + - - - - + + + + - - - + + + - - - - + + + + - - - - - + + + + + - + - - - - + + + + - + - + - - - - + + + + - + - - - + + + - - - + + + - - - - + + + + - - + + - - + + - + - + - + - + - + - + - + - + - + - - - + + + - - + + - - + + - - - - + + + + - - + + - + @@ -130856,222 +130854,222 @@ - - - - - + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -131086,12 +131084,12 @@ - + - + @@ -131100,19 +131098,19 @@ - + - + - + @@ -131134,235 +131132,235 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + @@ -131370,89 +131368,89 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + @@ -131485,49 +131483,49 @@ - + - - + + - - - - + + + + - - - + + + - - + + - + - + - + - + - + - + @@ -131584,404 +131582,404 @@ - - + + - + - + - - - + + + - - - + + + - - - + + + - - - - + + + + - - + + - + - + - + - - + + - + - + - + - + - + - + - - - + + + - - + + - - + + - - + + - + - - + + - + - + - + - + - + - + - + - + - - - - + + + + - - - + + + - + - - + + - - - - + + + + - - + + - - + + - - - - - - - - + + + + + + + + - - - - - - - - - - + + + + + + + + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -132004,39 +132002,39 @@ - + - - + + - - + + - + - + - + - + @@ -132092,104 +132090,104 @@ - - - + + + - - - - + + + + - - - - + + + + - - + + - - - - - - + + + + + + - - - - - + + + + + - - - - + + + + - - + + - - + + - + - - + + - + - + - + - + - + @@ -132199,214 +132197,214 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -132427,103 +132425,103 @@ - - - - + + + + - - - - - - - + + + + + + + - - + + - - - - - + + + + + - + - + - - - - - + + + + + - + - - + + - - + + - - + + - - + + - - + + - + - - + + - - + + - + - + - - + + - + @@ -132531,51 +132529,51 @@ - + - + - + - + - + - + - - + + - + - + - + @@ -132583,7 +132581,7 @@ - + @@ -132591,511 +132589,511 @@ - + - + - + - + - + - + - + - - - - - + + + + + - - - - + + + + - - - - + + + + - - - - - + + + + + - - - - - + + + + + - - - - - - + + + + + + - - - - + + + + - - - - - + + + + + - + - + - - - - - + + + + + - - - - + + + + - - - - + + + + - - - + + + - - - + + + - + - + - + - + - + - + - + - - + + - + - + - - - + + + - - + + - - - - - - - - + + + + + + + + - + - + - + - - - + + + - - + + - - + + - - + + - + - + - + - + - - - + + + - - - + + + - - - - + + + + - - - - + + + + - - - - - + + + + + - - - - + + + + - - + + - - + + - + - + - + - + - + - - - - + + + + - - - - + + + + - + - - - - + + + + - - - - - + + + + + - - - - - + + + + + - - - - - + + + + + - - - - - + + + + + - - + + - - - - + + + + - - - - - - - - + + + + + + + + - - - - + + + + - - - - - - - - - + + + + + + + + + - - - - + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - + + + + - - - - - + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -133106,133 +133104,133 @@ - + - - - + + + - + - - + + - - + + - - + + - - + + - - - + + + - - + + - - - - - - - - + + + + + + + + - - - - - - - + + + + + + + - - - - - + + + + + - - + + - - - + + + - - - - - - + + + + + + - - - - - + + + + + - - + + - - - - - - + + + + + + - - + + - + - + - - - + + + - - - - - - + + + + + + - + @@ -133240,68 +133238,68 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -133310,160 +133308,160 @@ - + - + - - + + - - + + - + - + - + - + - + - + - + - + - - - - - - + + + + + + - - + + - - - - + + + + - - - - + + + + - - + + - - - + + + - + - - - + + + - + - - + + - + - + - + - + - + - - - - - + + + + + - - + + - - + + - - + + - - + + - - + + - + - - - - - - + + + + + + - - + + @@ -133471,138 +133469,138 @@ - - + + - - - + + + - + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - + - - + + - - - - - + + + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - + + - - - + + + - + - - - - + + + + - - - - - + + + + + - - - + + + - - - + + + - + - - - - + + + + - + - + @@ -133612,59 +133610,59 @@ - - + + - - - - - + + + + + - + - + - - - - + + + + - + - + - + - + - + - + - + @@ -133675,122 +133673,122 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - - + + @@ -133798,76 +133796,76 @@ - - - - + + + + - + - - - + + + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -133879,12 +133877,12 @@ - - - + + + - + @@ -133939,54 +133937,54 @@ - - - - - + + + + + - - - - + + + + - - - - + + + + - - - - - + + + + + - - - - - + + + + + - - + + - - - - + + + + - - + + @@ -134023,79 +134021,79 @@ - - + + - - + + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -134108,15 +134106,15 @@ - + - + - + - + @@ -134124,7 +134122,7 @@ - + @@ -134132,15 +134130,15 @@ - + - + - + @@ -134155,27 +134153,27 @@ - - - - - - + + + + + + - - - + + + - - - - + + + + - + @@ -134194,379 +134192,379 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -134591,164 +134589,164 @@ - - + + - - - + + + - - - + + + - - - + + + - - + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - + + - - - + + + - - + + - - - - - + + + + + - + - - - + + + - - - - + + + + - - - - + + + + - - + + - - - - + + + + - - + + - - - - + + + + - - + + - - - + + + - - + + - - - - + + + + - - - - - - + + + + + + - - - + + + - - + + - - - + + + - - + + - - - - + + + + @@ -134781,67 +134779,67 @@ - - - - + + + + - - - + + + - - - + + + - - - + + + - + - + - + - + - + - + - + - + - - - + + + - - - + + + - + @@ -134864,307 +134862,307 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + @@ -135178,146 +135176,146 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -135337,21 +135335,21 @@ - - - - - - - - - - - + + + + + + + + + + + - - + + @@ -135370,77 +135368,77 @@ - - + + - + - + - + - + - - - + + + - - - + + + - - + + - - - - + + + + - - - + + + - - + + - - - + + + - + - - - - - - - + + + + + + + - - - + + + - - + + @@ -135450,92 +135448,92 @@ - - - - - - + + + + + + - - - - + + + + - - - - + + + + - - - - - + + + + + - - + + - - - + + + - - - + + + - - - + + + - - - - + + + + - - - - - + + + + + - - - - - + + + + + - - + + - - - - - + + + + + - - - - - + + + + + - + @@ -135547,465 +135545,465 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -136014,56 +136012,56 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -136106,15 +136104,15 @@ - - + + - - + + - + @@ -136122,87 +136120,87 @@ - - - - - + + + + + - - - - + + + + - - - - - + + + + + - - - + + + - - - - - + + + + + - - - - + + + + - - - - + + + + - - - + + + - - - + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - + + + + - - - - - + + + + + @@ -136301,36 +136299,36 @@ - - + + - + - + - + - + - - - + + + - - + + - - + + @@ -136344,99 +136342,99 @@ - - - - + + + + - - - + + + - - - + + + - - + + - - - + + + - - + + - - + + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -136444,27 +136442,27 @@ - - - - - + + + + + - - - - - - - + + + + + + + - - - - - + + + + + @@ -136483,15 +136481,15 @@ - - - - + + + + - - + + @@ -136500,76 +136498,76 @@ - + - - + + - - - + + + - - - - - - + + + + + + - - - - + + + + - - - - - - - + + + + + + + - - - - - - + + + + + + - - - - + + + + - - - - - + + + + + - - - + + + - - - - - - + + + + + + - + @@ -136578,7 +136576,7 @@ - + @@ -136597,30 +136595,30 @@ - + - + - + - + - + - + - + - + - + @@ -136669,612 +136667,612 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -137282,132 +137280,132 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -137425,47 +137423,47 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -137473,182 +137471,182 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -137659,15 +137657,15 @@ - + - + - + - + @@ -137682,999 +137680,999 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -138688,7 +138686,7 @@ - + @@ -138696,168 +138694,168 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -138866,506 +138864,506 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -139373,302 +139371,302 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -139677,172 +139675,172 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -139850,18 +139848,18 @@ - + - + - + - + - + @@ -139869,175 +139867,175 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -140045,207 +140043,207 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -140457,36 +140455,36 @@ - - - - + + + + - - + + - - + + - - + + - + - - - - + + + + - + @@ -141141,35 +141139,35 @@ - - + + - - - - - - - + + + + + + + - - - - - - - + + + + + + + - - + + @@ -141317,7 +141315,7 @@ - + @@ -141613,143 +141611,143 @@ - + - + - + - + - + - + - - - - - - - - - + + + + + + + + + - - - + + + - - - - - + + + + + - - + + - - - - + + + + - - - - - - + + + + + + - - - - - + + + + + - - - - - + + + + + - - - - - + + + + + - - - - - - - + + + + + + + - - - - - + + + + + - - - - - - + + + + + + - - - + + + - - - - - - + + + + + + - - - + + + - - - - + + + + - - - - + + + + - - + + @@ -141757,539 +141755,539 @@ - - - + + + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - + + + - - - + + + - - - - - - - - + + + + + + + + - - - - - - - - - - - + + + + + + + + + + + - - - - - - + + + + + + - - - + + + - - + + @@ -142304,159 +142302,159 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - + + + + - - - - + + + + - - - - - - - + + + + + + + - + - - - + + + - - + + - - - + + + - - + + - - + + - - - - - - + + + + + + - + - - - + + + - + @@ -142472,409 +142470,409 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -142914,14 +142912,14 @@ - + - + @@ -143013,13 +143011,13 @@ - - + + - + @@ -143029,361 +143027,361 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -143409,8 +143407,8 @@ - - + + @@ -143469,7 +143467,7 @@ - + @@ -143509,280 +143507,280 @@ - + - + - + - + - + - + - + - - - + + + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -143796,37 +143794,37 @@ - - - - + + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - - - + + + + + @@ -143851,101 +143849,101 @@ - - - + + + - - - - + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -143958,43 +143956,43 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -144013,10 +144011,10 @@ - - - - + + + + @@ -144024,61 +144022,61 @@ - - + + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + @@ -144087,179 +144085,179 @@ - - - - - - + + + + + + - - - - - + + + + + - - - - + + + + - - - - - - - + + + + + + + - - - - + + + + - - + + - - - + + + - - - + + + - - - + + + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -144275,13 +144273,13 @@ - + - + @@ -144356,111 +144354,111 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -144469,9 +144467,9 @@ - - - + + + @@ -144499,73 +144497,73 @@ - - - - + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -144575,387 +144573,387 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -144963,7 +144961,7 @@ - + @@ -144976,13 +144974,13 @@ - + - + @@ -145002,67 +145000,67 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -145071,14 +145069,14 @@ - + - + @@ -145091,323 +145089,323 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -145457,159 +145455,159 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -145631,214 +145629,214 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -145870,29 +145868,29 @@ - + - + - + - + - + - + - + - + - + @@ -145905,7 +145903,7 @@ - + @@ -145943,419 +145941,419 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -146397,27 +146395,27 @@ - + - + - + - + - + - + - + - + @@ -146430,658 +146428,658 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -147094,617 +147092,617 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -147815,95 +147813,95 @@ - - - - + + + + - - - + + + - + - - - + + + - + - - - + + + - - - - + + + + - + - + - + - - + + - - - + + + - - + + - - - - - + + + + + - - + + - - - + + + - - - + + + - - - + + + @@ -148241,241 +148239,241 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - + + - + - + - + - + - + - + - + - + - + - - + + - - - - - - + + + + + + - - - - - + + + + + - + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - + - - - + + + - - - - + + + + - - - - + + + + - - + + - + - + - + - + - - - - - - - + + + + + + + - - - - + + + + - - - - + + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - - - + + + + + - + @@ -148491,546 +148489,546 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -149044,12 +149042,12 @@ - - - - - - + + + + + + @@ -149062,11 +149060,11 @@ - - - - - + + + + + diff --git a/arch/alpha/include/uapi/asm/socket.h b/arch/alpha/include/uapi/asm/socket.h index d033d3f92d6d..de6c4df61082 100644 --- a/arch/alpha/include/uapi/asm/socket.h +++ b/arch/alpha/include/uapi/asm/socket.h @@ -124,8 +124,6 @@ #define SO_DETACH_REUSEPORT_BPF 68 -#define SO_NETNS_COOKIE 71 - #if !defined(__KERNEL__) #if __BITS_PER_LONG == 64 diff --git a/arch/alpha/kernel/syscalls/syscall.tbl b/arch/alpha/kernel/syscalls/syscall.tbl index 1a3036bf4611..7a04003bfcb4 100644 --- a/arch/alpha/kernel/syscalls/syscall.tbl +++ b/arch/alpha/kernel/syscalls/syscall.tbl @@ -475,9 +475,8 @@ 543 common fspick sys_fspick 544 common pidfd_open sys_pidfd_open # 545 reserved for clone3 -546 common close_range sys_close_range +# 546 reserved for close_range # 547 reserved for openat2 # 548 reserved for pidfd_getfd # 549 reserved for faccessat2 550 common process_madvise sys_process_madvise -551 common epoll_pwait2 sys_epoll_pwait2 diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h index 7d6afe5cdb7a..50eb3f64a77c 100644 --- a/arch/arc/include/asm/bitops.h +++ b/arch/arc/include/asm/bitops.h @@ -371,8 +371,6 @@ static inline __attribute__ ((const)) int fls(unsigned long x) */ static inline __attribute__ ((const)) int __fls(unsigned long x) { - if (__builtin_constant_p(x)) - return x ? BITS_PER_LONG - 1 - __builtin_clzl(x) : 0; /* FLS insn has exactly same semantics as the API */ return __builtin_arc_fls(x); } diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b282da8e4268..6ebd99010f0e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -16,7 +16,6 @@ config ARM select ARCH_HAS_KEEPINITRD select ARCH_HAS_KCOV select ARCH_HAS_MEMBARRIER_SYNC_CORE - select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE select ARCH_HAS_PTE_SPECIAL if ARM_LPAE select ARCH_HAS_PHYS_TO_DMA select ARCH_HAS_SETUP_DMA_OPS diff --git a/arch/arm/configs/vendor/sdxlemur.config b/arch/arm/configs/vendor/sdxlemur.config index 0d6a262c17ea..2646540a9f28 100644 --- a/arch/arm/configs/vendor/sdxlemur.config +++ b/arch/arm/configs/vendor/sdxlemur.config @@ -51,10 +51,6 @@ CONFIG_CNSS_ASYNC=y CONFIG_CNSS_QCA6490=y CONFIG_CNSS_UTILS=y # CONFIG_CNSS_GENL is not set -CONFIG_CNSS=m -CONFIG_CNSS_CRYPTO=y -CONFIG_CNSS_PCI=y -CONFIG_CNSS_LOGGER=m CONFIG_QCOM_MEMORY_DUMP_V2=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -254,7 +250,7 @@ CONFIG_USB_CONFIGFS_F_UAC2=y CONFIG_USB_CONFIGFS_F_CCID=y CONFIG_USB_G_QTI=y CONFIG_USB_BAM=y -CONFIG_USB_R8152_RTL=m +CONFIG_USB_RTL8152=y CONFIG_USB_NET_SMSC75XX=y CONFIG_USB_NET_SMSC95XX=y CONFIG_ARM_PSCI=y diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild index 580ed13b70a7..68ca86f85eb7 100644 --- a/arch/arm/include/asm/Kbuild +++ b/arch/arm/include/asm/Kbuild @@ -15,6 +15,7 @@ generic-y += mmiowb.h generic-y += msi.h generic-y += parport.h generic-y += preempt.h +generic-y += seccomp.h generic-y += serial.h generic-y += trace_clock.h diff --git a/arch/arm/include/asm/seccomp.h b/arch/arm/include/asm/seccomp.h deleted file mode 100644 index e9ad0f37d2ba..000000000000 --- a/arch/arm/include/asm/seccomp.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _ASM_SECCOMP_H -#define _ASM_SECCOMP_H - -#include - -#define SECCOMP_ARCH_NATIVE AUDIT_ARCH_ARM -#define SECCOMP_ARCH_NATIVE_NR NR_syscalls -#define SECCOMP_ARCH_NATIVE_NAME "arm" - -#endif /* _ASM_SECCOMP_H */ diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c index 1e16cedd6411..12b6da56f88d 100644 --- a/arch/arm/kernel/ftrace.c +++ b/arch/arm/kernel/ftrace.c @@ -91,8 +91,7 @@ static int ftrace_modify_code(unsigned long pc, unsigned long old, } if (validate) { - if (copy_from_kernel_nofault(&replaced, (void *)pc, - MCOUNT_INSN_SIZE)) + if (probe_kernel_read(&replaced, (void *)pc, MCOUNT_INSN_SIZE)) return -EFAULT; if (replaced != old) diff --git a/arch/arm/kernel/kgdb.c b/arch/arm/kernel/kgdb.c index 22f937e6f3ff..183a6f2f165a 100644 --- a/arch/arm/kernel/kgdb.c +++ b/arch/arm/kernel/kgdb.c @@ -256,7 +256,7 @@ int kgdb_arch_set_breakpoint(struct kgdb_bkpt *bpt) /* patch_text() only supports int-sized breakpoints */ BUILD_BUG_ON(sizeof(int) != BREAK_INSTR_SIZE); - err = copy_from_kernel_nofault(bpt->saved_instr, (char *)bpt->bpt_addr, + err = probe_kernel_read(bpt->saved_instr, (char *)bpt->bpt_addr, BREAK_INSTR_SIZE); if (err) return err; diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 069b2b097c8a..1e414f67c5f7 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -391,7 +391,7 @@ int is_valid_bugaddr(unsigned long pc) u32 insn = __opcode_to_mem_arm(BUG_INSTR_VALUE); #endif - if (get_kernel_nofault(bkpt, (unsigned *)pc)) + if (probe_kernel_address((unsigned *)pc, bkpt)) return 0; return bkpt == insn; diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index 387b6d2ad7ad..52ff66f004e4 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c @@ -774,7 +774,7 @@ static int alignment_get_arm(struct pt_regs *regs, u32 *ip, u32 *inst) if (user_mode(regs)) fault = get_user(instr, ip); else - fault = get_kernel_nofault(instr, ip); + fault = probe_kernel_address(ip, instr); *inst = __mem_to_opcode_arm(instr); @@ -789,7 +789,7 @@ static int alignment_get_thumb(struct pt_regs *regs, u16 *ip, u16 *inst) if (user_mode(regs)) fault = get_user(instr, ip); else - fault = get_kernel_nofault(instr, ip); + fault = probe_kernel_address(ip, instr); *inst = __mem_to_opcode_thumb16(instr); diff --git a/arch/arm/tools/syscall.tbl b/arch/arm/tools/syscall.tbl index b95205271c1b..b7eb74edf569 100644 --- a/arch/arm/tools/syscall.tbl +++ b/arch/arm/tools/syscall.tbl @@ -449,9 +449,8 @@ 433 common fspick sys_fspick 434 common pidfd_open sys_pidfd_open 435 common clone3 sys_clone3 -436 common close_range sys_close_range +# 436 reserved for close_range # 437 reserved for openat2 # 438 reserved for pidfd_getfd # 439 reserved for faccessat2 440 common process_madvise sys_process_madvise -441 common epoll_pwait2 sys_epoll_pwait2 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 79f9288483f8..aa26865c386d 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -22,7 +22,6 @@ config ARM64 select ARCH_HAS_KCOV select ARCH_HAS_KEEPINITRD select ARCH_HAS_MEMBARRIER_SYNC_CORE - select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE select ARCH_HAS_PTE_DEVMAP select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_SETUP_DMA_OPS @@ -74,7 +73,6 @@ config ARM64 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG select ARCH_SUPPORTS_NUMA_BALANCING select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT - select ARCH_WANT_DEFAULT_BPF_JIT select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT select ARCH_WANT_FRAME_POINTERS select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) @@ -129,7 +127,6 @@ config ARM64 select HAVE_ARCH_JUMP_LABEL_RELATIVE select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN - select HAVE_ARCH_KFENCE select HAVE_ARCH_KGDB select HAVE_ARCH_MMAP_RND_BITS select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT @@ -646,7 +643,6 @@ config ARM64_ERRATUM_3194386 * ARM Neoverse-V1 erratum 3324341 * ARM Neoverse V2 erratum 3324336 * ARM Neoverse-V3 erratum 3312417 - * ARM Neoverse-V3AE erratum 3312417 On affected cores "MSR SSBS, #0" instructions may not affect subsequent speculative instructions, which may permit unexepected diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index f01e2f0895a0..e1097ba6c948 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1599,8 +1599,6 @@ hexagon_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; - resets = <&gcc GCC_MDSS_BCR>; - interrupt-controller; #interrupt-cells = <2>; }; diff --git a/arch/arm64/boot/dts/vendor/qcom/blair-corfur-common-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/blair-corfur-common-overlay.dtsi index cfb1e952d730..6fb4921566ab 100644 --- a/arch/arm64/boot/dts/vendor/qcom/blair-corfur-common-overlay.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/blair-corfur-common-overlay.dtsi @@ -187,7 +187,7 @@ label = "google_key"; gpios = <&tlmm 11 GPIO_ACTIVE_LOW>; linux,input-type = <1>; - linux,code = ; + linux,code = ; gpio-key,wakeup; debounce-interval = <15>; linux,can-disable; diff --git a/arch/arm64/boot/dts/vendor/qcom/blair-cypfr-common-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/blair-cypfr-common-overlay.dtsi index ab2183f6ca94..3e89b8cf3d34 100644 --- a/arch/arm64/boot/dts/vendor/qcom/blair-cypfr-common-overlay.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/blair-cypfr-common-overlay.dtsi @@ -628,7 +628,7 @@ label = "google_key"; gpios = <&tlmm 60 GPIO_ACTIVE_LOW>; linux,input-type = <1>; - linux,code = ; + linux,code = ; gpio-key,wakeup; debounce-interval = <15>; linux,can-disable; diff --git a/arch/arm64/boot/dts/vendor/qcom/holi-cypfg-common-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/holi-cypfg-common-overlay.dtsi index 23137456e0ce..87a94a1759d8 100644 --- a/arch/arm64/boot/dts/vendor/qcom/holi-cypfg-common-overlay.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/holi-cypfg-common-overlay.dtsi @@ -152,7 +152,7 @@ label = "google_key"; gpios = <&tlmm 11 GPIO_ACTIVE_LOW>; linux,input-type = <1>; - linux,code = ; + linux,code = ; gpio-key,wakeup; debounce-interval = <15>; linux,can-disable; diff --git a/arch/arm64/boot/dts/vendor/qcom/holi-cypfq-common-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/holi-cypfq-common-overlay.dtsi index bf340b75a419..86055b0cbda9 100644 --- a/arch/arm64/boot/dts/vendor/qcom/holi-cypfq-common-overlay.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/holi-cypfq-common-overlay.dtsi @@ -340,7 +340,7 @@ label = "google_key"; gpios = <&tlmm 11 GPIO_ACTIVE_LOW>; linux,input-type = <1>; - linux,code = ; + linux,code = ; gpio-key,wakeup; debounce-interval = <15>; linux,can-disable; diff --git a/arch/arm64/boot/dts/vendor/qcom/holi-ibiza-common-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/holi-ibiza-common-overlay.dtsi index 30d1a5ca4100..e8d6e24d0018 100644 --- a/arch/arm64/boot/dts/vendor/qcom/holi-ibiza-common-overlay.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/holi-ibiza-common-overlay.dtsi @@ -135,7 +135,7 @@ label = "google_key"; gpios = <&tlmm 11 GPIO_ACTIVE_LOW>; linux,input-type = <1>; - linux,code = ; + linux,code = ; gpio-key,wakeup; debounce-interval = <15>; linux,can-disable; diff --git a/arch/arm64/configs/gki_defconfig b/arch/arm64/configs/gki_defconfig index 64beb2922cf9..05bf817a7639 100644 --- a/arch/arm64/configs/gki_defconfig +++ b/arch/arm64/configs/gki_defconfig @@ -209,27 +209,14 @@ CONFIG_L2TP=y CONFIG_BRIDGE=y CONFIG_NET_SCHED=y CONFIG_NET_SCH_HTB=y -CONFIG_NET_SCH_PRIO=y -CONFIG_NET_SCH_MULTIQ=y -CONFIG_NET_SCH_TBF=y -CONFIG_NET_SCH_NETEM=y CONFIG_NET_SCH_INGRESS=y CONFIG_NET_CLS_U32=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=y CONFIG_NET_CLS_BPF=y CONFIG_NET_CLS_MATCHALL=y CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=y -CONFIG_NET_EMATCH_NBYTE=y CONFIG_NET_EMATCH_U32=y -CONFIG_NET_EMATCH_META=y -CONFIG_NET_EMATCH_TEXT=y CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_POLICE=y -CONFIG_NET_ACT_GACT=y -CONFIG_NET_ACT_MIRRED=y -CONFIG_NET_ACT_SKBEDIT=y CONFIG_NET_ACT_BPF=y CONFIG_BPF_JIT=y CONFIG_BT=y @@ -326,8 +313,6 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_JOYSTICK=y CONFIG_JOYSTICK_XPAD=y -CONFIG_JOYSTICK_XPAD_FF=y -CONFIG_JOYSTICK_XPAD_LEDS=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_INPUT_MISC=y CONFIG_INPUT_UINPUT=y @@ -408,7 +393,6 @@ CONFIG_HID_BATTERY_STRENGTH=y CONFIG_HIDRAW=y CONFIG_UHID=y CONFIG_HID_APPLE=y -CONFIG_HID_BETOP_FF=y CONFIG_HID_PRODIKEYS=y CONFIG_HID_ELECOM=y CONFIG_HID_UCLOGIC=y @@ -513,7 +497,6 @@ CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y CONFIG_QUOTA=y CONFIG_QFMT_V2=y CONFIG_FUSE_FS=y -CONFIG_FUSE_BPF=y CONFIG_OVERLAY_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y @@ -603,9 +586,6 @@ CONFIG_DEBUG_INFO_DWARF4=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_STACK_USAGE=y CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_KFENCE=y -CONFIG_KFENCE_SAMPLE_INTERVAL=500 -CONFIG_KFENCE_NUM_OBJECTS=63 CONFIG_SOFTLOCKUP_DETECTOR=y # CONFIG_DETECT_HUNG_TASK is not set CONFIG_PANIC_ON_OOPS=y diff --git a/arch/arm64/configs/vendor/ext_config/moto-holi-cypfr.config b/arch/arm64/configs/vendor/ext_config/moto-holi-cypfr.config index b32b086618be..f87419fb43f4 100644 --- a/arch/arm64/configs/vendor/ext_config/moto-holi-cypfr.config +++ b/arch/arm64/configs/vendor/ext_config/moto-holi-cypfr.config @@ -21,7 +21,6 @@ CONFIG_CAM_SENSOR_PROBE_RETRY=y # Charger CONFIG_QG_LEGACY=y -CONFIG_USE_MMI_CHARGER=y # UFS # CONFIG_MICRON_UFSHID is not set diff --git a/arch/arm64/configs/vendor/ext_config/moto-holi-ibiza.config b/arch/arm64/configs/vendor/ext_config/moto-holi-ibiza.config index 4804e99b9e0c..dc13da133a82 100644 --- a/arch/arm64/configs/vendor/ext_config/moto-holi-ibiza.config +++ b/arch/arm64/configs/vendor/ext_config/moto-holi-ibiza.config @@ -17,49 +17,9 @@ CONFIG_IBIZA_DTB=y # Camera CONFIG_CAM_SENSOR_PROBE_RETRY=y -CONFIG_CAMERA_CCI_INTF=m -# CONFIG_CAMERA_CCI_MASTER_CHANGE is not set -CONFIG_REGULATOR_WL2864C=m # Charger -CONFIG_MMI_SMBCHARGER_IIO=m CONFIG_QG_LEGACY=y -CONFIG_QPNP_ADAPTIVE_CHARGE=m - -# Fingerprint -CONFIG_INPUT_CHIPONE_FPS_MMI=m -CONFIG_INPUT_MISC_FPC1020=m -CONFIG_INPUT_MISC_FPC1020_SAVE_TO_CLASS_DEVICE=y - -# MMI -CONFIG_MMI_ANNOTATE=m -CONFIG_MMI_INFO=m -CONFIG_MMI_RELAY=m -CONFIG_MMI_SYS_TEMP=m -CONFIG_MOTO_UTAGS=m -CONFIG_SENSORS_CLASS=m - -# NFC -CONFIG_NFC_QTI_I2C=m - -# SAR -CONFIG_SARSENSOR_SX937X=m - -# Touchscreen -CONFIG_TOUCHSCREEN_NT36xxx_HOSTDL_SPI_MMI=m -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_ENABLE_DOUBLE_TAP=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_NOTIFY_TOUCH_STATE=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_LAST_TIME=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_STOWED_MODE_EN=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_CHIP_VER_1=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_WAKEUP_GESTURE_CTRL=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_STYLUS_PALM=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_STYLUS_PALM_RANGE=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_DDA_STYLUS=y -CONFIG_TOUCHSCREEN_NOVA_0FLASH_MMI_PEN_NOTIFIER=y -CONFIG_TOUCHSCREEN_CHIPONE_TDDI=m -CONFIG_TOUCHSCREEN_CHIPONE_TDDI_ESD=y -CONFIG_BOARD_USES_DOUBLE_TAP_CTRL=y # UFS # CONFIG_UFSFEATURE is not set diff --git a/arch/arm64/configs/vendor/ext_config/moto-holi-milanf.config b/arch/arm64/configs/vendor/ext_config/moto-holi-milanf.config index 921287b0132d..6ed0faf46def 100644 --- a/arch/arm64/configs/vendor/ext_config/moto-holi-milanf.config +++ b/arch/arm64/configs/vendor/ext_config/moto-holi-milanf.config @@ -39,7 +39,6 @@ CONFIG_BQ2597X_MMI_IIO=m CONFIG_CW2217B_FG_MMI=m CONFIG_RT9426A_FG_MMI=m CONFIG_SD77426_FG_MMI=m -CONFIG_USE_MMI_CHARGER=y # Display # CONFIG_REGULATOR_QPNP_LCDB is not set diff --git a/arch/arm64/configs/vendor/ext_config/moto-holi-penang.config b/arch/arm64/configs/vendor/ext_config/moto-holi-penang.config index fb99e46df5f9..f081e1efaced 100644 --- a/arch/arm64/configs/vendor/ext_config/moto-holi-penang.config +++ b/arch/arm64/configs/vendor/ext_config/moto-holi-penang.config @@ -36,7 +36,6 @@ CONFIG_TCPC_CLASS=m CONFIG_TCPC_RT1711H=m CONFIG_TCPC_SGM7220=m CONFIG_TYPEC_ADAPTER_CLASS=m -CONFIG_USE_MMI_CHARGER=y # Display # CONFIG_REGULATOR_QPNP_LCDB is not set diff --git a/arch/arm64/configs/vendor/ext_config/moto-holi-pnangn.config b/arch/arm64/configs/vendor/ext_config/moto-holi-pnangn.config index 583322e8c3f4..a8bcf26d9d58 100644 --- a/arch/arm64/configs/vendor/ext_config/moto-holi-pnangn.config +++ b/arch/arm64/configs/vendor/ext_config/moto-holi-pnangn.config @@ -38,7 +38,6 @@ CONFIG_TCPC_CLASS=m CONFIG_TCPC_RT1711H=m CONFIG_TCPC_SGM7220=m CONFIG_TYPEC_ADAPTER_CLASS=m -CONFIG_USE_MMI_CHARGER=y # Display # CONFIG_REGULATOR_QPNP_LCDB is not set diff --git a/arch/arm64/configs/vendor/ext_config/moto-holi-rhodec.config b/arch/arm64/configs/vendor/ext_config/moto-holi-rhodec.config index 63b46ccccfb6..fd9e13c68907 100644 --- a/arch/arm64/configs/vendor/ext_config/moto-holi-rhodec.config +++ b/arch/arm64/configs/vendor/ext_config/moto-holi-rhodec.config @@ -24,8 +24,5 @@ CONFIG_AW882XX_MAPSIZE_16K=y CONFIG_AF_NOISE_ELIMINATION=y CONFIG_CAM_SENSOR_PROBE_RETRY=y -# Charger -CONFIG_USE_MMI_CHARGER=y - # Display # CONFIG_REGULATOR_QPNP_LCDB is not set diff --git a/arch/arm64/configs/vendor/ext_config/moto-holi-rhodei.config b/arch/arm64/configs/vendor/ext_config/moto-holi-rhodei.config index 7abab1bc172d..520a096e5d6d 100644 --- a/arch/arm64/configs/vendor/ext_config/moto-holi-rhodei.config +++ b/arch/arm64/configs/vendor/ext_config/moto-holi-rhodei.config @@ -24,9 +24,6 @@ CONFIG_AW882XX_MAPSIZE_16K=y CONFIG_AF_NOISE_ELIMINATION=y CONFIG_CAM_SENSOR_PROBE_RETRY=y -# Charger -CONFIG_USE_MMI_CHARGER=y - # Display # CONFIG_REGULATOR_QPNP_LCDB is not set diff --git a/arch/arm64/configs/vendor/ext_config/moto-holi-rhodep.config b/arch/arm64/configs/vendor/ext_config/moto-holi-rhodep.config index 84a684d3484a..032caff886e0 100644 --- a/arch/arm64/configs/vendor/ext_config/moto-holi-rhodep.config +++ b/arch/arm64/configs/vendor/ext_config/moto-holi-rhodep.config @@ -43,7 +43,6 @@ CONFIG_BQ2589X_CHARGER=m CONFIG_BQ2597X_MMI_IIO=m CONFIG_CW2217B_FG_MMI=m CONFIG_MMI_QC3P_TURBO_CHARGER=y -CONFIG_USE_MMI_CHARGER=y # Display # CONFIG_REGULATOR_QPNP_LCDB is not set diff --git a/arch/arm64/configs/vendor/holi-qgki_defconfig b/arch/arm64/configs/vendor/holi-qgki_defconfig index f9282a24cc5d..44b770441caa 100644 --- a/arch/arm64/configs/vendor/holi-qgki_defconfig +++ b/arch/arm64/configs/vendor/holi-qgki_defconfig @@ -239,27 +239,15 @@ CONFIG_BRIDGE=y CONFIG_NET_SCHED=y CONFIG_NET_SCH_HTB=y CONFIG_NET_SCH_PRIO=y -CONFIG_NET_SCH_MULTIQ=y -CONFIG_NET_SCH_TBF=y -CONFIG_NET_SCH_NETEM=y CONFIG_NET_SCH_INGRESS=y CONFIG_NET_CLS_FW=y CONFIG_NET_CLS_U32=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=y CONFIG_NET_CLS_BPF=y CONFIG_NET_CLS_MATCHALL=y CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=y -CONFIG_NET_EMATCH_NBYTE=y CONFIG_NET_EMATCH_U32=y -CONFIG_NET_EMATCH_META=y -CONFIG_NET_EMATCH_TEXT=y CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_POLICE=y -CONFIG_NET_ACT_GACT=y -CONFIG_NET_ACT_MIRRED=y -CONFIG_NET_ACT_SKBEDIT=y CONFIG_NET_ACT_BPF=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y @@ -380,8 +368,6 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_JOYSTICK=y CONFIG_JOYSTICK_XPAD=y -CONFIG_JOYSTICK_XPAD_FF=y -CONFIG_JOYSTICK_XPAD_LEDS=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_USB_COMPOSITE=y CONFIG_TOUCHSCREEN_FTS=y @@ -524,7 +510,6 @@ CONFIG_HID_BATTERY_STRENGTH=y CONFIG_HIDRAW=y CONFIG_UHID=y CONFIG_HID_APPLE=y -CONFIG_HID_BETOP_FF=y CONFIG_HID_PRODIKEYS=y CONFIG_HID_ELECOM=y CONFIG_HID_UCLOGIC=y @@ -782,7 +767,6 @@ CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y CONFIG_QUOTA=y CONFIG_QFMT_V2=y CONFIG_FUSE_FS=y -CONFIG_FUSE_BPF=y CONFIG_OVERLAY_FS=y CONFIG_INCREMENTAL_FS=y CONFIG_MSDOS_FS=y @@ -878,9 +862,6 @@ CONFIG_HEADERS_INSTALL=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_STACK_USAGE=y CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_KFENCE=y -CONFIG_KFENCE_SAMPLE_INTERVAL=500 -CONFIG_KFENCE_NUM_OBJECTS=63 CONFIG_SOFTLOCKUP_DETECTOR=y # CONFIG_DETECT_HUNG_TASK is not set CONFIG_PANIC_ON_OOPS=y diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 58e935916c4d..8be75679f766 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -88,7 +88,6 @@ #define ARM_CPU_PART_NEOVERSE_V2 0xD4F #define ARM_CPU_PART_CORTEX_A720 0xD81 #define ARM_CPU_PART_CORTEX_X4 0xD82 -#define ARM_CPU_PART_NEOVERSE_V3AE 0xD83 #define ARM_CPU_PART_NEOVERSE_V3 0xD84 #define ARM_CPU_PART_CORTEX_X925 0xD85 #define ARM_CPU_PART_CORTEX_A725 0xD87 @@ -142,7 +141,6 @@ #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) -#define MIDR_NEOVERSE_V3AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3AE) #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725) diff --git a/arch/arm64/include/asm/kfence.h b/arch/arm64/include/asm/kfence.h deleted file mode 100644 index d061176d57ea..000000000000 --- a/arch/arm64/include/asm/kfence.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arm64 KFENCE support. - * - * Copyright (C) 2020, Google LLC. - */ - -#ifndef __ASM_KFENCE_H -#define __ASM_KFENCE_H - -#include - -static inline bool arch_kfence_init_pool(void) { return true; } - -static inline bool kfence_protect_page(unsigned long addr, bool protect) -{ - set_memory_valid(addr, 1, !protect); - - return true; -} - -#endif /* __ASM_KFENCE_H */ diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 7389975f8809..18faae2e9e6f 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -145,8 +145,7 @@ static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) static inline pte_t pte_mkwrite(pte_t pte) { pte = set_pte_bit(pte, __pgprot(PTE_WRITE)); - if (pte_sw_dirty(pte)) - pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); + pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY)); return pte; } diff --git a/arch/arm64/include/asm/seccomp.h b/arch/arm64/include/asm/seccomp.h index 30256233788b..c36387170936 100644 --- a/arch/arm64/include/asm/seccomp.h +++ b/arch/arm64/include/asm/seccomp.h @@ -19,13 +19,4 @@ #include -#define SECCOMP_ARCH_NATIVE AUDIT_ARCH_AARCH64 -#define SECCOMP_ARCH_NATIVE_NR NR_syscalls -#define SECCOMP_ARCH_NATIVE_NAME "aarch64" -#ifdef CONFIG_COMPAT -# define SECCOMP_ARCH_COMPAT AUDIT_ARCH_ARM -# define SECCOMP_ARCH_COMPAT_NR __NR_compat_syscalls -# define SECCOMP_ARCH_COMPAT_NAME "arm" -#endif - #endif /* _ASM_SECCOMP_H */ diff --git a/arch/arm64/include/asm/unistd.h b/arch/arm64/include/asm/unistd.h index 86a9d7b3eabe..b3b2019f8d16 100644 --- a/arch/arm64/include/asm/unistd.h +++ b/arch/arm64/include/asm/unistd.h @@ -38,7 +38,7 @@ #define __ARM_NR_compat_set_tls (__ARM_NR_COMPAT_BASE + 5) #define __ARM_NR_COMPAT_END (__ARM_NR_COMPAT_BASE + 0x800) -#define __NR_compat_syscalls 442 +#define __NR_compat_syscalls 441 #endif #define __ARCH_WANT_SYS_CLONE diff --git a/arch/arm64/include/asm/unistd32.h b/arch/arm64/include/asm/unistd32.h index a907534385d0..52879c7aaa54 100644 --- a/arch/arm64/include/asm/unistd32.h +++ b/arch/arm64/include/asm/unistd32.h @@ -879,12 +879,8 @@ __SYSCALL(__NR_fspick, sys_fspick) __SYSCALL(__NR_pidfd_open, sys_pidfd_open) #define __NR_clone3 435 __SYSCALL(__NR_clone3, sys_clone3) -#define __NR_close_range 436 -__SYSCALL(__NR_close_range, sys_close_range) #define __NR_process_madvise 440 __SYSCALL(__NR_process_madvise, sys_process_madvise) -#define __NR_epoll_pwait2 441 -__SYSCALL(__NR_epoll_pwait2, compat_sys_epoll_pwait2) /* * Please add new compat syscalls above this comment and update diff --git a/arch/arm64/kernel/armv8_deprecated.c b/arch/arm64/kernel/armv8_deprecated.c index 508e10c6c61c..12b545f7fb32 100644 --- a/arch/arm64/kernel/armv8_deprecated.c +++ b/arch/arm64/kernel/armv8_deprecated.c @@ -204,7 +204,7 @@ static void __init register_insn_emulation(struct insn_emulation_ops *ops) } static int emulation_proc_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, + void __user *buffer, size_t *lenp, loff_t *ppos) { int ret = 0; diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index ebf39755eaf5..1e1dfe59a469 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -863,7 +863,6 @@ static const struct midr_range erratum_spec_ssbs_list[] = { MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), - MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE), {} }; #endif diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 3536d6e68f6a..e62c9cbf99f4 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -341,7 +341,8 @@ static unsigned int find_supported_vector_length(unsigned int vl) #if defined(CONFIG_ARM64_SVE) && defined(CONFIG_SYSCTL) static int sve_proc_do_default_vl(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { int ret; int vl = sve_default_vl; diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c index 4f9f344c8163..a02c294a4753 100644 --- a/arch/arm64/kernel/insn.c +++ b/arch/arm64/kernel/insn.c @@ -123,7 +123,7 @@ int __kprobes aarch64_insn_read(void *addr, u32 *insnp) int ret; __le32 val; - ret = copy_from_kernel_nofault(&val, addr, AARCH64_INSN_SIZE); + ret = probe_kernel_read(&val, addr, AARCH64_INSN_SIZE); if (!ret) *insnp = le32_to_cpu(val); @@ -139,7 +139,7 @@ static int __kprobes __aarch64_insn_write(void *addr, __le32 insn) raw_spin_lock_irqsave(&patch_lock, flags); waddr = patch_map(addr, FIX_TEXT_POKE0); - ret = copy_to_kernel_nofault(waddr, &insn, AARCH64_INSN_SIZE); + ret = probe_kernel_write(waddr, &insn, AARCH64_INSN_SIZE); patch_unmap(FIX_TEXT_POKE0); raw_spin_unlock_irqrestore(&patch_lock, flags); diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index ceb8d1e66fb9..a436a6972ced 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -311,7 +311,7 @@ static int call_undef_hook(struct pt_regs *regs) if (!user_mode(regs)) { __le32 instr_le; - if (get_kernel_nofault(instr_le, (__force __le32 *)pc)) + if (probe_kernel_address((__force __le32 *)pc, instr_le)) goto exit; instr = le32_to_cpu(instr_le); } else if (compat_thumb_mode(regs)) { diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index ae412b438122..8fcd1dbe1fb7 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -328,9 +327,6 @@ static void __do_kernel_fault(unsigned long addr, unsigned int esr, } else if (addr < PAGE_SIZE) { msg = "NULL pointer dereference"; } else { - if (kfence_handle_page_fault(addr, esr & ESR_ELx_WNR, regs)) - return; - msg = "paging request"; } diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index b6983b5502bc..9eaaa69fea9a 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -471,8 +471,7 @@ static void __init map_mem(pgd_t *pgdp) struct memblock_region *reg; int flags = 0; - if (rodata_full || debug_pagealloc_enabled() || - IS_ENABLED(CONFIG_KFENCE)) + if (rodata_full || debug_pagealloc_enabled()) flags = NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS; /* @@ -1471,12 +1470,7 @@ int arch_add_memory(int nid, u64 start, u64 size, return -1; } - /* - * KFENCE requires linear map to be mapped at page granularity, so that - * it is possible to protect/unprotect single pages in the KFENCE pool. - */ - if (rodata_full || debug_pagealloc_enabled() || - IS_ENABLED(CONFIG_KFENCE)) + if (rodata_full || debug_pagealloc_enabled()) flags = NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS; __create_pgd_mapping(swapper_pg_dir, start, __phys_to_virt(start), diff --git a/arch/csky/include/asm/seccomp.h b/arch/csky/include/asm/seccomp.h deleted file mode 100644 index d33e758126fb..000000000000 --- a/arch/csky/include/asm/seccomp.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _ASM_SECCOMP_H -#define _ASM_SECCOMP_H - -#include - -#define SECCOMP_ARCH_NATIVE AUDIT_ARCH_CSKY -#define SECCOMP_ARCH_NATIVE_NR NR_syscalls -#define SECCOMP_ARCH_NATIVE_NAME "csky" - -#endif /* _ASM_SECCOMP_H */ diff --git a/arch/csky/kernel/ftrace.c b/arch/csky/kernel/ftrace.c index def2b89d4f83..44f4880179b7 100644 --- a/arch/csky/kernel/ftrace.c +++ b/arch/csky/kernel/ftrace.c @@ -71,8 +71,7 @@ static int ftrace_check_current_nop(unsigned long hook) uint16_t olds[7]; unsigned long hook_pos = hook - 2; - if (copy_from_kernel_nofault((void *)olds, (void *)hook_pos, - sizeof(nops))) + if (probe_kernel_read((void *)olds, (void *)hook_pos, sizeof(nops))) return -EFAULT; if (memcmp((void *)nops, (void *)olds, sizeof(nops))) { @@ -97,7 +96,7 @@ static int ftrace_modify_code(unsigned long hook, unsigned long target, make_jbsr(target, hook, call, nolr); - ret = copy_to_kernel_nofault((void *)hook_pos, enable ? call : nops, + ret = probe_kernel_write((void *)hook_pos, enable ? call : nops, sizeof(nops)); if (ret) return -EPERM; diff --git a/arch/ia64/include/asm/sections.h b/arch/ia64/include/asm/sections.h index ad4fc06e5f4b..cea15f2dd38d 100644 --- a/arch/ia64/include/asm/sections.h +++ b/arch/ia64/include/asm/sections.h @@ -35,7 +35,7 @@ static inline void *dereference_function_descriptor(void *ptr) struct fdesc *desc = ptr; void *p; - if (!get_kernel_nofault(p, &desc->ip)) + if (!probe_kernel_address(&desc->ip, p)) ptr = p; return ptr; } diff --git a/arch/ia64/kernel/ftrace.c b/arch/ia64/kernel/ftrace.c index b2ab2d58fb30..cee411e647ca 100644 --- a/arch/ia64/kernel/ftrace.c +++ b/arch/ia64/kernel/ftrace.c @@ -108,7 +108,7 @@ ftrace_modify_code(unsigned long ip, unsigned char *old_code, goto skip_check; /* read the text we want to modify */ - if (copy_from_kernel_nofault(replaced, (void *)ip, MCOUNT_INSN_SIZE)) + if (probe_kernel_read(replaced, (void *)ip, MCOUNT_INSN_SIZE)) return -EFAULT; /* Make sure it is what we expect it to be */ @@ -117,7 +117,7 @@ ftrace_modify_code(unsigned long ip, unsigned char *old_code, skip_check: /* replace the text with the new text */ - if (copy_to_kernel_nofault(((void *)ip), new_code, MCOUNT_INSN_SIZE)) + if (probe_kernel_write(((void *)ip), new_code, MCOUNT_INSN_SIZE)) return -EPERM; flush_icache_range(ip, ip + MCOUNT_INSN_SIZE); @@ -129,7 +129,7 @@ static int ftrace_make_nop_check(struct dyn_ftrace *rec, unsigned long addr) unsigned char __attribute__((aligned(8))) replaced[MCOUNT_INSN_SIZE]; unsigned long ip = rec->ip; - if (copy_from_kernel_nofault(replaced, (void *)ip, MCOUNT_INSN_SIZE)) + if (probe_kernel_read(replaced, (void *)ip, MCOUNT_INSN_SIZE)) return -EFAULT; if (rec->flags & FTRACE_FL_CONVERTED) { struct ftrace_call_insn *call_insn, *tmp_call; diff --git a/arch/ia64/kernel/syscalls/syscall.tbl b/arch/ia64/kernel/syscalls/syscall.tbl index 998cbcc4964d..6915e787a037 100644 --- a/arch/ia64/kernel/syscalls/syscall.tbl +++ b/arch/ia64/kernel/syscalls/syscall.tbl @@ -356,9 +356,8 @@ 433 common fspick sys_fspick 434 common pidfd_open sys_pidfd_open # 435 reserved for clone3 -436 common close_range sys_close_range +# 436 reserved for close_range # 437 reserved for openat2 # 438 reserved for pidfd_getfd # 439 reserved for faccessat2 440 common process_madvise sys_process_madvise -441 common epoll_pwait2 sys_epoll_pwait2 diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h index d2a9aa048517..10133a968c8e 100644 --- a/arch/m68k/include/asm/bitops.h +++ b/arch/m68k/include/asm/bitops.h @@ -314,12 +314,12 @@ static inline int bfchg_mem_test_and_change_bit(int nr, #include #else -static inline unsigned long find_first_zero_bit(const unsigned long *vaddr, - unsigned long size) +static inline int find_first_zero_bit(const unsigned long *vaddr, + unsigned size) { const unsigned long *p = vaddr; - unsigned long res = 32; - unsigned long words; + int res = 32; + unsigned int words; unsigned long num; if (!size) @@ -340,9 +340,8 @@ out: } #define find_first_zero_bit find_first_zero_bit -static inline unsigned long find_next_zero_bit(const unsigned long *vaddr, - unsigned long size, - unsigned long offset) +static inline int find_next_zero_bit(const unsigned long *vaddr, int size, + int offset) { const unsigned long *p = vaddr + (offset >> 5); int bit = offset & 31UL, res; @@ -371,12 +370,11 @@ static inline unsigned long find_next_zero_bit(const unsigned long *vaddr, } #define find_next_zero_bit find_next_zero_bit -static inline unsigned long find_first_bit(const unsigned long *vaddr, - unsigned long size) +static inline int find_first_bit(const unsigned long *vaddr, unsigned size) { const unsigned long *p = vaddr; - unsigned long res = 32; - unsigned long words; + int res = 32; + unsigned int words; unsigned long num; if (!size) @@ -397,9 +395,8 @@ out: } #define find_first_bit find_first_bit -static inline unsigned long find_next_bit(const unsigned long *vaddr, - unsigned long size, - unsigned long offset) +static inline int find_next_bit(const unsigned long *vaddr, int size, + int offset) { const unsigned long *p = vaddr + (offset >> 5); int bit = offset & 31UL, res; diff --git a/arch/m68k/kernel/syscalls/syscall.tbl b/arch/m68k/kernel/syscalls/syscall.tbl index 1c95471e18b8..95cc3b9d40ef 100644 --- a/arch/m68k/kernel/syscalls/syscall.tbl +++ b/arch/m68k/kernel/syscalls/syscall.tbl @@ -435,9 +435,8 @@ 433 common fspick sys_fspick 434 common pidfd_open sys_pidfd_open # 435 reserved for clone3 -436 common close_range sys_close_range +# 436 reserved for close_range # 437 reserved for openat2 # 438 reserved for pidfd_getfd # 439 reserved for faccessat2 440 common process_madvise sys_process_madvise -441 common epoll_pwait2 sys_epoll_pwait2 diff --git a/arch/microblaze/kernel/syscalls/syscall.tbl b/arch/microblaze/kernel/syscalls/syscall.tbl index b9e78e528825..0bf9a04e19b5 100644 --- a/arch/microblaze/kernel/syscalls/syscall.tbl +++ b/arch/microblaze/kernel/syscalls/syscall.tbl @@ -441,9 +441,8 @@ 433 common fspick sys_fspick 434 common pidfd_open sys_pidfd_open 435 common clone3 sys_clone3 -436 common close_range sys_close_range +# 436 reserved for close_range # 437 reserved for openat2 # 438 reserved for pidfd_getfd # 439 reserved for faccessat2 440 common process_madvise sys_process_madvise -441 common epoll_pwait2 sys_epoll_pwait2 diff --git a/arch/mips/boot/dts/lantiq/danube.dtsi b/arch/mips/boot/dts/lantiq/danube.dtsi index 1a5f4faa0831..510be63c8bdf 100644 --- a/arch/mips/boot/dts/lantiq/danube.dtsi +++ b/arch/mips/boot/dts/lantiq/danube.dtsi @@ -5,12 +5,8 @@ compatible = "lantiq,xway", "lantiq,danube"; cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { compatible = "mips,mips24Kc"; - reg = <0>; }; }; @@ -105,8 +101,6 @@ 0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */ reg = <0x7000000 0x8000 /* config space */ 0xe105400 0x400>; /* pci bridge */ - - device_type = "pci"; }; }; }; diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index 7bcb3092aef2..f85bd5b15f51 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -398,8 +398,6 @@ static inline pte_t pte_mkspecial(pte_t pte) return pte; } -#define pte_sw_mkyoung pte_mkyoung - #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT static inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_HUGE; } diff --git a/arch/mips/include/asm/seccomp.h b/arch/mips/include/asm/seccomp.h index aa809589a181..e383d7e27b93 100644 --- a/arch/mips/include/asm/seccomp.h +++ b/arch/mips/include/asm/seccomp.h @@ -9,12 +9,12 @@ static inline const int *get_compat_mode1_syscalls(void) static const int syscalls_O32[] = { __NR_O32_Linux + 3, __NR_O32_Linux + 4, __NR_O32_Linux + 1, __NR_O32_Linux + 193, - -1, /* negative terminated */ + 0, /* null terminated */ }; static const int syscalls_N32[] = { __NR_N32_Linux + 0, __NR_N32_Linux + 1, __NR_N32_Linux + 58, __NR_N32_Linux + 211, - -1, /* negative terminated */ + 0, /* null terminated */ }; if (IS_ENABLED(CONFIG_MIPS32_O32) && test_thread_flag(TIF_32BIT_REGS)) diff --git a/arch/mips/include/uapi/asm/socket.h b/arch/mips/include/uapi/asm/socket.h index ff3ab771e769..d0a9ed2ca2d6 100644 --- a/arch/mips/include/uapi/asm/socket.h +++ b/arch/mips/include/uapi/asm/socket.h @@ -135,8 +135,6 @@ #define SO_DETACH_REUSEPORT_BPF 68 -#define SO_NETNS_COOKIE 71 - #if !defined(__KERNEL__) #if __BITS_PER_LONG == 64 diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c index d043c2f897fc..6cfae2411c04 100644 --- a/arch/mips/kernel/kprobes.c +++ b/arch/mips/kernel/kprobes.c @@ -86,9 +86,9 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p) goto out; } - if (copy_from_kernel_nofault(&prev_insn, p->addr - 1, - sizeof(mips_instruction)) == 0 && - insn_has_delayslot(prev_insn)) { + if ((probe_kernel_read(&prev_insn, p->addr - 1, + sizeof(mips_instruction)) == 0) && + insn_has_delayslot(prev_insn)) { pr_notice("Kprobes for branch delayslot are not supported\n"); ret = -EINVAL; goto out; diff --git a/arch/mips/kernel/syscalls/syscall_n32.tbl b/arch/mips/kernel/syscalls/syscall_n32.tbl index 65c00397cc54..6ae6842599ac 100644 --- a/arch/mips/kernel/syscalls/syscall_n32.tbl +++ b/arch/mips/kernel/syscalls/syscall_n32.tbl @@ -374,9 +374,8 @@ 433 n32 fspick sys_fspick 434 n32 pidfd_open sys_pidfd_open 435 n32 clone3 __sys_clone3 -436 n32 close_range sys_close_range +# 436 reserved for close_range # 437 reserved for openat2 # 438 reserved for pidfd_getfd # 439 reserved for faccessat2 440 n32 process_madvise sys_process_madvise -441 n32 epoll_pwait2 compat_sys_epoll_pwait2 diff --git a/arch/mips/kernel/syscalls/syscall_n64.tbl b/arch/mips/kernel/syscalls/syscall_n64.tbl index bfe00627bce6..6a663f85820c 100644 --- a/arch/mips/kernel/syscalls/syscall_n64.tbl +++ b/arch/mips/kernel/syscalls/syscall_n64.tbl @@ -350,9 +350,8 @@ 433 n64 fspick sys_fspick 434 n64 pidfd_open sys_pidfd_open 435 n64 clone3 __sys_clone3 -436 n64 close_range sys_close_range +# 436 reserved for close_range # 437 reserved for openat2 # 438 reserved for pidfd_getfd # 439 reserved for faccessat2 440 n64 process_madvise sys_process_madvise -441 n64 epoll_pwait2 sys_epoll_pwait2 diff --git a/arch/mips/kernel/syscalls/syscall_o32.tbl b/arch/mips/kernel/syscalls/syscall_o32.tbl index a1992d7cfb83..5f2c2636e7a4 100644 --- a/arch/mips/kernel/syscalls/syscall_o32.tbl +++ b/arch/mips/kernel/syscalls/syscall_o32.tbl @@ -423,5 +423,3 @@ 433 o32 fspick sys_fspick 434 o32 pidfd_open sys_pidfd_open 435 o32 clone3 __sys_clone3 -436 o32 close_range sys_close_range -441 o32 epoll_pwait2 sys_epoll_pwait2 compat_sys_epoll_pwait2 diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index e52dfd4bad57..6c2d9779ac72 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -459,7 +459,7 @@ void __init ltq_soc_init(void) /* add our generic xway clocks */ clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI); clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT); - clkdev_add_pmu("1e100bb0.gpio", NULL, 1, 0, PMU_STP); + clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP); clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1); clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA); clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI); diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c index 2119541a5b8b..e666fe26c50d 100644 --- a/arch/mips/lasat/sysctl.c +++ b/arch/mips/lasat/sysctl.c @@ -95,15 +95,16 @@ int proc_lasat_ip(struct ctl_table *table, int write, len = 0; p = buffer; while (len < *lenp) { - c = *p; - p++; + if (get_user(c, p++)) + return -EFAULT; if (c == 0 || c == '\n') break; len++; } if (len >= sizeof(ipbuf)-1) len = sizeof(ipbuf) - 1; - memcpy(ipbuf, buffer, len); + if (copy_from_user(ipbuf, buffer, len)) + return -EFAULT; ipbuf[len] = 0; *ppos += *lenp; /* Now see if we can convert it to a valid IP */ @@ -121,9 +122,11 @@ int proc_lasat_ip(struct ctl_table *table, int write, if (len > *lenp) len = *lenp; if (len) - memcpy(buffer, ipbuf, len); + if (copy_to_user(buffer, ipbuf, len)) + return -EFAULT; if (len < *lenp) { - *((char *)buffer + len) = '\n'; + if (put_user('\n', ((char *) buffer) + len)) + return -EFAULT; len++; } *lenp = len; diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c index 72b82700a59d..ff2c1d809538 100644 --- a/arch/mips/mti-malta/malta-init.c +++ b/arch/mips/mti-malta/malta-init.c @@ -242,22 +242,16 @@ mips_pci_controller: #endif /* - * Set up memory mapping in host bridge for PCI DMA masters, - * in transparent addressing mode. For EVA use the Malta - * maximum of 2 GiB memory in the alias space at 0x80000000 - * as per PHYS_OFFSET. Otherwise use 256 MiB of memory in - * the regular space, avoiding mapping the PCI MMIO window - * for DMA as it seems to confuse the system controller's - * logic, causing PCI MMIO to stop working. + * Setup the Malta max (2GB) memory for PCI DMA in host bridge + * in transparent addressing mode. */ - mask = PHYS_OFFSET ? PHYS_OFFSET : 0xf0000000; - MSC_WRITE(MSC01_PCI_BAR0, - mask | PCI_BASE_ADDRESS_MEM_PREFETCH); - MSC_WRITE(MSC01_PCI_HEAD4, - PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_PREFETCH); + mask = PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_PREFETCH; + MSC_WRITE(MSC01_PCI_BAR0, mask); + MSC_WRITE(MSC01_PCI_HEAD4, mask); + mask &= MSC01_PCI_BAR0_SIZE_MSK; MSC_WRITE(MSC01_PCI_P2SCMSKL, mask); - MSC_WRITE(MSC01_PCI_P2SCMAPL, PHYS_OFFSET); + MSC_WRITE(MSC01_PCI_P2SCMAPL, mask); /* Don't handle target retries indefinitely. */ if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index ba6a3d4c1050..c4ad5a9b4bc1 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -48,7 +48,7 @@ static struct resource standard_io_resources[] = { .name = "keyboard", .start = 0x60, .end = 0x6f, - .flags = IORESOURCE_IO + .flags = IORESOURCE_IO | IORESOURCE_BUSY }, { .name = "dma page reg", diff --git a/arch/nds32/kernel/ftrace.c b/arch/nds32/kernel/ftrace.c index 69c29b228f80..fd2a54b8cd57 100644 --- a/arch/nds32/kernel/ftrace.c +++ b/arch/nds32/kernel/ftrace.c @@ -143,14 +143,13 @@ static int __ftrace_modify_code(unsigned long pc, unsigned long *old_insn, unsigned long orig_insn[3]; if (validate) { - if (copy_from_kernel_nofault(orig_insn, (void *)pc, - MCOUNT_INSN_SIZE)) + if (probe_kernel_read(orig_insn, (void *)pc, MCOUNT_INSN_SIZE)) return -EFAULT; if (memcmp(orig_insn, old_insn, MCOUNT_INSN_SIZE)) return -EINVAL; } - if (copy_to_kernel_nofault((void *)pc, new_insn, MCOUNT_INSN_SIZE)) + if (probe_kernel_write((void *)pc, new_insn, MCOUNT_INSN_SIZE)) return -EPERM; return 0; diff --git a/arch/parisc/include/asm/Kbuild b/arch/parisc/include/asm/Kbuild index ae63364de2cf..9ceedf6393c4 100644 --- a/arch/parisc/include/asm/Kbuild +++ b/arch/parisc/include/asm/Kbuild @@ -19,6 +19,7 @@ generic-y += mm-arch-hooks.h generic-y += mmiowb.h generic-y += percpu.h generic-y += preempt.h +generic-y += seccomp.h generic-y += trace_clock.h generic-y += user.h generic-y += vga.h diff --git a/arch/parisc/include/asm/seccomp.h b/arch/parisc/include/asm/seccomp.h deleted file mode 100644 index b058b2220322..000000000000 --- a/arch/parisc/include/asm/seccomp.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _ASM_SECCOMP_H -#define _ASM_SECCOMP_H - -#include - -#ifdef CONFIG_64BIT -# define SECCOMP_ARCH_NATIVE AUDIT_ARCH_PARISC64 -# define SECCOMP_ARCH_NATIVE_NR NR_syscalls -# define SECCOMP_ARCH_NATIVE_NAME "parisc64" -# ifdef CONFIG_COMPAT -# define SECCOMP_ARCH_COMPAT AUDIT_ARCH_PARISC -# define SECCOMP_ARCH_COMPAT_NR NR_syscalls -# define SECCOMP_ARCH_COMPAT_NAME "parisc" -# endif -#else /* !CONFIG_64BIT */ -# define SECCOMP_ARCH_NATIVE AUDIT_ARCH_PARISC -# define SECCOMP_ARCH_NATIVE_NR NR_syscalls -# define SECCOMP_ARCH_NATIVE_NAME "parisc" -#endif - -#endif /* _ASM_SECCOMP_H */ diff --git a/arch/parisc/include/uapi/asm/ioctls.h b/arch/parisc/include/uapi/asm/ioctls.h index 74b4027a4e80..82d1148c6379 100644 --- a/arch/parisc/include/uapi/asm/ioctls.h +++ b/arch/parisc/include/uapi/asm/ioctls.h @@ -10,10 +10,10 @@ #define TCSETS _IOW('T', 17, struct termios) /* TCSETATTR */ #define TCSETSW _IOW('T', 18, struct termios) /* TCSETATTRD */ #define TCSETSF _IOW('T', 19, struct termios) /* TCSETATTRF */ -#define TCGETA 0x40125401 -#define TCSETA 0x80125402 -#define TCSETAW 0x80125403 -#define TCSETAF 0x80125404 +#define TCGETA _IOR('T', 1, struct termio) +#define TCSETA _IOW('T', 2, struct termio) +#define TCSETAW _IOW('T', 3, struct termio) +#define TCSETAF _IOW('T', 4, struct termio) #define TCSBRK _IO('T', 5) #define TCXONC _IO('T', 6) #define TCFLSH _IO('T', 7) diff --git a/arch/parisc/include/uapi/asm/socket.h b/arch/parisc/include/uapi/asm/socket.h index 1a8ec3838c9b..10173c32195e 100644 --- a/arch/parisc/include/uapi/asm/socket.h +++ b/arch/parisc/include/uapi/asm/socket.h @@ -116,8 +116,6 @@ #define SO_DETACH_REUSEPORT_BPF 0x4042 -#define SO_NETNS_COOKIE 0x4045 - #if !defined(__KERNEL__) #if __BITS_PER_LONG == 64 diff --git a/arch/parisc/kernel/ftrace.c b/arch/parisc/kernel/ftrace.c index 236284a05f55..f3a5c5e480cf 100644 --- a/arch/parisc/kernel/ftrace.c +++ b/arch/parisc/kernel/ftrace.c @@ -172,7 +172,7 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) ip = (void *)(rec->ip + 4 - size); - ret = copy_from_kernel_nofault(insn, ip, size); + ret = probe_kernel_read(insn, ip, size); if (ret) return ret; diff --git a/arch/parisc/kernel/kgdb.c b/arch/parisc/kernel/kgdb.c index c4554ac13eac..664278db9b97 100644 --- a/arch/parisc/kernel/kgdb.c +++ b/arch/parisc/kernel/kgdb.c @@ -154,8 +154,8 @@ void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip) int kgdb_arch_set_breakpoint(struct kgdb_bkpt *bpt) { - int ret = copy_from_kernel_nofault(bpt->saved_instr, - (char *)bpt->bpt_addr, BREAK_INSTR_SIZE); + int ret = probe_kernel_read(bpt->saved_instr, (char *)bpt->bpt_addr, + BREAK_INSTR_SIZE); if (ret) return ret; diff --git a/arch/parisc/kernel/process.c b/arch/parisc/kernel/process.c index 03d42f399b15..0e67ab681b4e 100644 --- a/arch/parisc/kernel/process.c +++ b/arch/parisc/kernel/process.c @@ -298,7 +298,7 @@ void *dereference_function_descriptor(void *ptr) Elf64_Fdesc *desc = ptr; void *p; - if (!get_kernel_nofault(p, &desc->addr)) + if (!probe_kernel_address(&desc->addr, p)) ptr = p; return ptr; } diff --git a/arch/parisc/kernel/syscalls/syscall.tbl b/arch/parisc/kernel/syscalls/syscall.tbl index e7357a228264..1b85a9ff9000 100644 --- a/arch/parisc/kernel/syscalls/syscall.tbl +++ b/arch/parisc/kernel/syscalls/syscall.tbl @@ -433,9 +433,8 @@ 433 common fspick sys_fspick 434 common pidfd_open sys_pidfd_open 435 common clone3 sys_clone3_wrapper -436 common close_range sys_close_range +# 436 reserved for close_range # 437 reserved for openat2 # 438 reserved for pidfd_getfd # 439 reserved for faccessat2 440 common process_madvise sys_process_madvise -441 common epoll_pwait2 sys_epoll_pwait2 compat_sys_epoll_pwait2 diff --git a/arch/parisc/lib/memcpy.c b/arch/parisc/lib/memcpy.c index 4b75388190b4..beceaab34ecb 100644 --- a/arch/parisc/lib/memcpy.c +++ b/arch/parisc/lib/memcpy.c @@ -57,10 +57,14 @@ void * memcpy(void * dst,const void *src, size_t count) EXPORT_SYMBOL(raw_copy_in_user); EXPORT_SYMBOL(memcpy); -bool copy_from_kernel_nofault_allowed(const void *unsafe_src, size_t size) +long probe_kernel_read(void *dst, const void *src, size_t size) { - if ((unsigned long)unsafe_src < PAGE_SIZE) - return false; + unsigned long addr = (unsigned long)src; + + if (addr < PAGE_SIZE) + return -EFAULT; + /* check for I/O space F_EXTEND(0xfff00000) access as well? */ - return true; + + return __probe_kernel_read(dst, src, size); } diff --git a/arch/powerpc/include/asm/seccomp.h b/arch/powerpc/include/asm/seccomp.h index ac2033f134f0..51209f6071c5 100644 --- a/arch/powerpc/include/asm/seccomp.h +++ b/arch/powerpc/include/asm/seccomp.h @@ -8,27 +8,4 @@ #include -#ifdef __LITTLE_ENDIAN__ -#define __SECCOMP_ARCH_LE __AUDIT_ARCH_LE -#define __SECCOMP_ARCH_LE_NAME "le" -#else -#define __SECCOMP_ARCH_LE 0 -#define __SECCOMP_ARCH_LE_NAME -#endif - -#ifdef CONFIG_PPC64 -# define SECCOMP_ARCH_NATIVE (AUDIT_ARCH_PPC64 | __SECCOMP_ARCH_LE) -# define SECCOMP_ARCH_NATIVE_NR NR_syscalls -# define SECCOMP_ARCH_NATIVE_NAME "ppc64" __SECCOMP_ARCH_LE_NAME -# ifdef CONFIG_COMPAT -# define SECCOMP_ARCH_COMPAT (AUDIT_ARCH_PPC | __SECCOMP_ARCH_LE) -# define SECCOMP_ARCH_COMPAT_NR NR_syscalls -# define SECCOMP_ARCH_COMPAT_NAME "ppc" __SECCOMP_ARCH_LE_NAME -# endif -#else /* !CONFIG_PPC64 */ -# define SECCOMP_ARCH_NATIVE (AUDIT_ARCH_PPC | __SECCOMP_ARCH_LE) -# define SECCOMP_ARCH_NATIVE_NR NR_syscalls -# define SECCOMP_ARCH_NATIVE_NAME "ppc" __SECCOMP_ARCH_LE_NAME -#endif - #endif /* _ASM_POWERPC_SECCOMP_H */ diff --git a/arch/powerpc/include/asm/sections.h b/arch/powerpc/include/asm/sections.h index bd311616fca8..d19871763ed4 100644 --- a/arch/powerpc/include/asm/sections.h +++ b/arch/powerpc/include/asm/sections.h @@ -85,7 +85,7 @@ static inline void *dereference_function_descriptor(void *ptr) struct ppc64_opd_entry *desc = ptr; void *p; - if (!get_kernel_nofault(p, &desc->funcaddr)) + if (!probe_kernel_address(&desc->funcaddr, p)) ptr = p; return ptr; } diff --git a/arch/powerpc/kernel/eeh_driver.c b/arch/powerpc/kernel/eeh_driver.c index 7ce80ad5e9d3..68decc2bf42b 100644 --- a/arch/powerpc/kernel/eeh_driver.c +++ b/arch/powerpc/kernel/eeh_driver.c @@ -351,7 +351,7 @@ static enum pci_ers_result eeh_report_error(struct eeh_dev *edev, rc = driver->err_handler->error_detected(pdev, pci_channel_io_frozen); edev->in_error = true; - pci_uevent_ers(pdev, rc); + pci_uevent_ers(pdev, PCI_ERS_RESULT_NONE); return rc; } diff --git a/arch/powerpc/kernel/kgdb.c b/arch/powerpc/kernel/kgdb.c index 56ed33549ccc..7dd55eb1259d 100644 --- a/arch/powerpc/kernel/kgdb.c +++ b/arch/powerpc/kernel/kgdb.c @@ -420,7 +420,7 @@ int kgdb_arch_set_breakpoint(struct kgdb_bkpt *bpt) unsigned int instr; unsigned int *addr = (unsigned int *)bpt->bpt_addr; - err = get_kernel_nofault(instr, addr); + err = probe_kernel_address(addr, instr); if (err) return err; diff --git a/arch/powerpc/kernel/module_64.c b/arch/powerpc/kernel/module_64.c index 3f023cc02de6..007606a48fd9 100644 --- a/arch/powerpc/kernel/module_64.c +++ b/arch/powerpc/kernel/module_64.c @@ -159,7 +159,7 @@ int module_trampoline_target(struct module *mod, unsigned long addr, stub = (struct ppc64_stub_entry *)addr; - if (copy_from_kernel_nofault(&magic, &stub->magic, sizeof(magic))) { + if (probe_kernel_read(&magic, &stub->magic, sizeof(magic))) { pr_err("%s: fault reading magic for stub %lx for %s\n", __func__, addr, mod->name); return -EFAULT; } @@ -169,7 +169,7 @@ int module_trampoline_target(struct module *mod, unsigned long addr, return -EFAULT; } - if (copy_from_kernel_nofault(&funcdata, &stub->funcdata, sizeof(funcdata))) { + if (probe_kernel_read(&funcdata, &stub->funcdata, sizeof(funcdata))) { pr_err("%s: fault reading funcdata for stub %lx for %s\n", __func__, addr, mod->name); return -EFAULT; } diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index aae6796f8495..cf87573e6e78 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -1239,7 +1239,7 @@ static void show_instructions(struct pt_regs *regs) pr_cont("\n"); if (!__kernel_text_address(pc) || - get_kernel_nofault(instr, (const void *)pc)) { + probe_kernel_address((const void *)pc, instr)) { pr_cont("XXXXXXXX "); } else { if (nip == pc) @@ -1263,6 +1263,16 @@ void show_user_instructions(struct pt_regs *regs) pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int)); + /* + * Make sure the NIP points at userspace, not kernel text/data or + * elsewhere. + */ + if (!__access_ok(pc, NR_INSN_TO_PRINT * sizeof(int), USER_DS)) { + pr_info("%s[%d]: Bad NIP, not dumping instructions.\n", + current->comm, current->pid); + return; + } + seq_buf_init(&s, buf, sizeof(buf)); while (n) { @@ -1273,8 +1283,7 @@ void show_user_instructions(struct pt_regs *regs) for (i = 0; i < 8 && n; i++, n--, pc += sizeof(int)) { int instr; - if (copy_from_user_nofault(&instr, (void __user *)pc, - sizeof(instr))) { + if (probe_kernel_address((const void *)pc, instr)) { seq_buf_printf(&s, "XXXXXXXX "); continue; } diff --git a/arch/powerpc/kernel/syscalls/syscall.tbl b/arch/powerpc/kernel/syscalls/syscall.tbl index 9fd2fa43ef1d..f3b2b0c58abb 100644 --- a/arch/powerpc/kernel/syscalls/syscall.tbl +++ b/arch/powerpc/kernel/syscalls/syscall.tbl @@ -517,9 +517,8 @@ 433 common fspick sys_fspick 434 common pidfd_open sys_pidfd_open 435 nospu clone3 ppc_clone3 -436 common close_range sys_close_range +# 436 reserved for close_range # 437 reserved for openat2 # 438 reserved for pidfd_getfd # 439 reserved for faccessat2 440 common process_madvise sys_process_madvise -441 common epoll_pwait2 sys_epoll_pwait2 compat_sys_epoll_pwait2 diff --git a/arch/powerpc/kernel/trace/ftrace.c b/arch/powerpc/kernel/trace/ftrace.c index 363b1f6ae4ae..d816e714f2f4 100644 --- a/arch/powerpc/kernel/trace/ftrace.c +++ b/arch/powerpc/kernel/trace/ftrace.c @@ -67,7 +67,7 @@ ftrace_modify_code(unsigned long ip, unsigned int old, unsigned int new) */ /* read the text we want to modify */ - if (copy_from_kernel_nofault(&replaced, (void *)ip, MCOUNT_INSN_SIZE)) + if (probe_kernel_read(&replaced, (void *)ip, MCOUNT_INSN_SIZE)) return -EFAULT; /* Make sure it is what we expect it to be */ @@ -128,7 +128,7 @@ __ftrace_make_nop(struct module *mod, unsigned int op, pop; /* read where this goes */ - if (copy_from_kernel_nofault(&op, (void *)ip, sizeof(int))) { + if (probe_kernel_read(&op, (void *)ip, sizeof(int))) { pr_err("Fetching opcode failed.\n"); return -EFAULT; } @@ -162,7 +162,7 @@ __ftrace_make_nop(struct module *mod, /* When using -mkernel_profile there is no load to jump over */ pop = PPC_INST_NOP; - if (copy_from_kernel_nofault(&op, (void *)(ip - 4), 4)) { + if (probe_kernel_read(&op, (void *)(ip - 4), 4)) { pr_err("Fetching instruction at %lx failed.\n", ip - 4); return -EFAULT; } @@ -193,7 +193,7 @@ __ftrace_make_nop(struct module *mod, * Check what is in the next instruction. We can see ld r2,40(r1), but * on first pass after boot we will see mflr r0. */ - if (copy_from_kernel_nofault(&op, (void *)(ip+4), MCOUNT_INSN_SIZE)) { + if (probe_kernel_read(&op, (void *)(ip+4), MCOUNT_INSN_SIZE)) { pr_err("Fetching op failed.\n"); return -EFAULT; } @@ -222,7 +222,7 @@ __ftrace_make_nop(struct module *mod, unsigned long ip = rec->ip; unsigned long tramp; - if (copy_from_kernel_nofault(&op, (void *)ip, MCOUNT_INSN_SIZE)) + if (probe_kernel_read(&op, (void *)ip, MCOUNT_INSN_SIZE)) return -EFAULT; /* Make sure that that this is still a 24bit jump */ @@ -245,7 +245,7 @@ __ftrace_make_nop(struct module *mod, pr_devel("ip:%lx jumps to %lx", ip, tramp); /* Find where the trampoline jumps to */ - if (copy_from_kernel_nofault(jmp, (void *)tramp, sizeof(jmp))) { + if (probe_kernel_read(jmp, (void *)tramp, sizeof(jmp))) { pr_err("Failed to read %lx\n", tramp); return -EFAULT; } @@ -339,7 +339,7 @@ static int setup_mcount_compiler_tramp(unsigned long tramp) return -1; /* New trampoline -- read where this goes */ - if (copy_from_kernel_nofault(&op, (void *)tramp, sizeof(int))) { + if (probe_kernel_read(&op, (void *)tramp, sizeof(int))) { pr_debug("Fetching opcode failed.\n"); return -1; } @@ -389,7 +389,7 @@ static int __ftrace_make_nop_kernel(struct dyn_ftrace *rec, unsigned long addr) unsigned int op; /* Read where this goes */ - if (copy_from_kernel_nofault(&op, (void *)ip, sizeof(int))) { + if (probe_kernel_read(&op, (void *)ip, sizeof(int))) { pr_err("Fetching opcode failed.\n"); return -EFAULT; } @@ -514,7 +514,7 @@ __ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) struct module *mod = rec->arch.mod; /* read where this goes */ - if (copy_from_kernel_nofault(op, ip, sizeof(op))) + if (probe_kernel_read(op, ip, sizeof(op))) return -EFAULT; if (!expected_nop_sequence(ip, op[0], op[1])) { @@ -576,7 +576,7 @@ __ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) unsigned long ip = rec->ip; /* read where this goes */ - if (copy_from_kernel_nofault(&op, (void *)ip, MCOUNT_INSN_SIZE)) + if (probe_kernel_read(&op, (void *)ip, MCOUNT_INSN_SIZE)) return -EFAULT; /* It should be pointing to a nop */ @@ -632,7 +632,7 @@ static int __ftrace_make_call_kernel(struct dyn_ftrace *rec, unsigned long addr) } /* Make sure we have a nop */ - if (copy_from_kernel_nofault(&op, ip, sizeof(op))) { + if (probe_kernel_read(&op, ip, sizeof(op))) { pr_err("Unable to read ftrace location %p\n", ip); return -EFAULT; } @@ -710,7 +710,7 @@ __ftrace_modify_call(struct dyn_ftrace *rec, unsigned long old_addr, } /* read where this goes */ - if (copy_from_kernel_nofault(&op, (void *)ip, sizeof(int))) { + if (probe_kernel_read(&op, (void *)ip, sizeof(int))) { pr_err("Fetching opcode failed.\n"); return -EFAULT; } diff --git a/arch/powerpc/kvm/book3s_64_mmu_radix.c b/arch/powerpc/kvm/book3s_64_mmu_radix.c index daf8e720d12a..25f1aaf78026 100644 --- a/arch/powerpc/kvm/book3s_64_mmu_radix.c +++ b/arch/powerpc/kvm/book3s_64_mmu_radix.c @@ -62,10 +62,12 @@ unsigned long __kvmhv_copy_tofrom_guest_radix(int lpid, int pid, } isync(); + pagefault_disable(); if (is_load) - ret = copy_from_user_nofault(to, (const void __user *)from, n); + ret = raw_copy_from_user(to, from, n); else - ret = copy_to_user_nofault((void __user *)to, from, n); + ret = raw_copy_to_user(to, from, n); + pagefault_enable(); /* switch the pid first to avoid running host with unallocated pid */ if (quadrant == 1 && pid != old_pid) diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c index 51331dc9554d..ade062dcc4e4 100644 --- a/arch/powerpc/mm/fault.c +++ b/arch/powerpc/mm/fault.c @@ -280,8 +280,12 @@ static bool bad_stack_expansion(struct pt_regs *regs, unsigned long address, if ((flags & FAULT_FLAG_WRITE) && (flags & FAULT_FLAG_USER) && access_ok(nip, sizeof(*nip))) { unsigned int inst; + int res; - if (!probe_user_read(&inst, nip, sizeof(inst))) + pagefault_disable(); + res = __get_user_inatomic(inst, nip); + pagefault_enable(); + if (!res) return !store_updates_sp(inst); *must_retry = true; } diff --git a/arch/powerpc/oprofile/backtrace.c b/arch/powerpc/oprofile/backtrace.c index c4208a59addd..43245f4a9bcb 100644 --- a/arch/powerpc/oprofile/backtrace.c +++ b/arch/powerpc/oprofile/backtrace.c @@ -28,13 +28,15 @@ static unsigned int user_getsp32(unsigned int sp, int is_first) unsigned int stack_frame[2]; void __user *p = compat_ptr(sp); + if (!access_ok(p, sizeof(stack_frame))) + return 0; + /* * The most likely reason for this is that we returned -EFAULT, * which means that we've done all that we can do from * interrupt context. */ - if (copy_from_user_nofault(stack_frame, (void __user *)p, - sizeof(stack_frame))) + if (__copy_from_user_inatomic(stack_frame, p, sizeof(stack_frame))) return 0; if (!is_first) @@ -52,8 +54,11 @@ static unsigned long user_getsp64(unsigned long sp, int is_first) { unsigned long stack_frame[3]; - if (copy_from_user_nofault(stack_frame, (void __user *)sp, - sizeof(stack_frame))) + if (!access_ok((void __user *)sp, sizeof(stack_frame))) + return 0; + + if (__copy_from_user_inatomic(stack_frame, (void __user *)sp, + sizeof(stack_frame))) return 0; if (!is_first) @@ -98,6 +103,7 @@ void op_powerpc_backtrace(struct pt_regs * const regs, unsigned int depth) first_frame = 0; } } else { + pagefault_disable(); #ifdef CONFIG_PPC64 if (!is_32bit_task()) { while (depth--) { @@ -106,6 +112,7 @@ void op_powerpc_backtrace(struct pt_regs * const regs, unsigned int depth) break; first_frame = 0; } + pagefault_enable(); return; } #endif @@ -116,5 +123,6 @@ void op_powerpc_backtrace(struct pt_regs * const regs, unsigned int depth) break; first_frame = 0; } + pagefault_enable(); } } diff --git a/arch/powerpc/perf/callchain.c b/arch/powerpc/perf/callchain.c index 73ee4c42889b..4c9aaedd2b1b 100644 --- a/arch/powerpc/perf/callchain.c +++ b/arch/powerpc/perf/callchain.c @@ -156,8 +156,12 @@ static int read_user_stack_64(unsigned long __user *ptr, unsigned long *ret) ((unsigned long)ptr & 7)) return -EFAULT; - if (!probe_user_read(ret, ptr, sizeof(*ret))) + pagefault_disable(); + if (!__get_user_inatomic(*ret, ptr)) { + pagefault_enable(); return 0; + } + pagefault_enable(); return read_user_stack_slow(ptr, ret, 8); } @@ -168,8 +172,12 @@ static int read_user_stack_32(unsigned int __user *ptr, unsigned int *ret) ((unsigned long)ptr & 3)) return -EFAULT; - if (!probe_user_read(ret, ptr, sizeof(*ret))) + pagefault_disable(); + if (!__get_user_inatomic(*ret, ptr)) { + pagefault_enable(); return 0; + } + pagefault_enable(); return read_user_stack_slow(ptr, ret, 4); } @@ -296,11 +304,17 @@ static inline int current_is_64bit(void) */ static int read_user_stack_32(unsigned int __user *ptr, unsigned int *ret) { + int rc; + if ((unsigned long)ptr > TASK_SIZE - sizeof(unsigned int) || ((unsigned long)ptr & 3)) return -EFAULT; - return probe_user_read(ret, ptr, sizeof(*ret)); + pagefault_disable(); + rc = __get_user_inatomic(*ret, ptr); + pagefault_enable(); + + return rc; } static inline void perf_callchain_user_64(struct perf_callchain_entry_ctx *entry, diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 9d6904ea88a6..04d20dcf7f08 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -418,20 +418,24 @@ static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) static __u64 power_pmu_bhrb_to(u64 addr) { unsigned int instr; + int ret; __u64 target; if (is_kernel_addr(addr)) { - if (copy_from_kernel_nofault(&instr, (void *)addr, - sizeof(instr))) + if (probe_kernel_read(&instr, (void *)addr, sizeof(instr))) return 0; return branch_target(&instr); } /* Userspace: need copy instruction here then translate it */ - if (copy_from_user_nofault(&instr, (unsigned int __user *)addr, - sizeof(instr))) + pagefault_disable(); + ret = __get_user_inatomic(instr, (unsigned int __user *)addr); + if (ret) { + pagefault_enable(); return 0; + } + pagefault_enable(); target = branch_target(&instr); if ((!target) || (instr & BRANCH_ABSOLUTE)) diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 4e2855c178ac..6adf2fdec799 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -1073,11 +1073,13 @@ int fsl_pci_mcheck_exception(struct pt_regs *regs) addr += mfspr(SPRN_MCAR); if (is_in_pci_mem_space(addr)) { - if (user_mode(regs)) - ret = copy_from_user_nofault(&inst, - (void __user *)regs->nip, sizeof(inst)); - else + if (user_mode(regs)) { + pagefault_disable(); + ret = get_user(inst, (__u32 __user *)regs->nip); + pagefault_enable(); + } else { ret = probe_kernel_address((void *)regs->nip, inst); + } if (!ret && mcheck_handle_load(regs, inst)) { regs->nip += 4; diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 054ab2f280db..1641d8201412 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -38,7 +38,7 @@ ifeq ($(CONFIG_LD_IS_LLD),y) ifeq ($(shell test $(CONFIG_LLD_VERSION) -lt 150000; echo $$?),0) KBUILD_CFLAGS += -mno-relax KBUILD_AFLAGS += -mno-relax -ifndef CONFIG_AS_IS_LLVM +ifneq ($(LLVM_IAS),1) KBUILD_CFLAGS += -Wa,-mno-relax KBUILD_AFLAGS += -Wa,-mno-relax endif diff --git a/arch/riscv/kernel/ftrace.c b/arch/riscv/kernel/ftrace.c index bcdc072427a3..291c579e1245 100644 --- a/arch/riscv/kernel/ftrace.c +++ b/arch/riscv/kernel/ftrace.c @@ -24,8 +24,7 @@ static int ftrace_check_current_call(unsigned long hook_pos, * Read the text we want to modify; * return must be -EFAULT on read error */ - if (copy_from_kernel_nofault(replaced, (void *)hook_pos, - MCOUNT_INSN_SIZE)) + if (probe_kernel_read(replaced, (void *)hook_pos, MCOUNT_INSN_SIZE)) return -EFAULT; /* diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 8c20b0ed75ac..c28d4debf592 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -120,7 +120,7 @@ static inline unsigned long get_break_insn_length(unsigned long pc) { bug_insn_t insn; - if (get_kernel_nofault(insn, (bug_insn_t *)pc)) + if (probe_kernel_address((bug_insn_t *)pc, insn)) return 0; return (((insn & __INSN_LENGTH_MASK) == __INSN_LENGTH_32) ? 4UL : 2UL); } @@ -142,7 +142,7 @@ int is_valid_bugaddr(unsigned long pc) if (pc < VMALLOC_START) return 0; - if (get_kernel_nofault(insn, (bug_insn_t *)pc)) + if (probe_kernel_address((bug_insn_t *)pc, insn)) return 0; if ((insn & __INSN_LENGTH_MASK) == __INSN_LENGTH_32) return (insn == __BUG_INSN_32); diff --git a/arch/s390/appldata/appldata_base.c b/arch/s390/appldata/appldata_base.c index d74a4c7d5df6..aa738cad1338 100644 --- a/arch/s390/appldata/appldata_base.c +++ b/arch/s390/appldata/appldata_base.c @@ -51,9 +51,10 @@ static struct platform_device *appldata_pdev; */ static const char appldata_proc_name[APPLDATA_PROC_NAME_LENGTH] = "appldata"; static int appldata_timer_handler(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); static int appldata_interval_handler(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, + size_t *lenp, loff_t *ppos); static struct ctl_table_header *appldata_sysctl_header; static struct ctl_table appldata_table[] = { @@ -216,7 +217,7 @@ static void __appldata_vtimer_setup(int cmd) */ static int appldata_timer_handler(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int timer_active = appldata_timer_active; int rc; @@ -249,7 +250,7 @@ appldata_timer_handler(struct ctl_table *ctl, int write, */ static int appldata_interval_handler(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int interval = appldata_interval; int rc; @@ -279,7 +280,7 @@ appldata_interval_handler(struct ctl_table *ctl, int write, */ static int appldata_generic_handler(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct appldata_ops *ops = NULL, *tmp_ops; struct list_head *lh; diff --git a/arch/s390/include/asm/seccomp.h b/arch/s390/include/asm/seccomp.h index 71d46f0ba97b..795bbe0d7ca6 100644 --- a/arch/s390/include/asm/seccomp.h +++ b/arch/s390/include/asm/seccomp.h @@ -16,13 +16,4 @@ #include -#define SECCOMP_ARCH_NATIVE AUDIT_ARCH_S390X -#define SECCOMP_ARCH_NATIVE_NR NR_syscalls -#define SECCOMP_ARCH_NATIVE_NAME "s390x" -#ifdef CONFIG_COMPAT -# define SECCOMP_ARCH_COMPAT AUDIT_ARCH_S390 -# define SECCOMP_ARCH_COMPAT_NR NR_syscalls -# define SECCOMP_ARCH_COMPAT_NAME "s390" -#endif - #endif /* _ASM_S390_SECCOMP_H */ diff --git a/arch/s390/kernel/debug.c b/arch/s390/kernel/debug.c index 083aa28880a3..b1aadc3ad065 100644 --- a/arch/s390/kernel/debug.c +++ b/arch/s390/kernel/debug.c @@ -878,7 +878,7 @@ static int debug_active = 1; * if debug_active is already off */ static int s390dbf_procactive(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { if (!write || debug_stoppable || !debug_active) return proc_dointvec(table, write, buffer, lenp, ppos); diff --git a/arch/s390/kernel/ftrace.c b/arch/s390/kernel/ftrace.c index de21130c4da6..7df6b2642ddb 100644 --- a/arch/s390/kernel/ftrace.c +++ b/arch/s390/kernel/ftrace.c @@ -109,7 +109,7 @@ int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec, { struct ftrace_insn orig, new, old; - if (copy_from_kernel_nofault(&old, (void *) rec->ip, sizeof(old))) + if (probe_kernel_read(&old, (void *) rec->ip, sizeof(old))) return -EFAULT; if (addr == MCOUNT_ADDR) { /* Initial code replacement */ @@ -141,7 +141,7 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) { struct ftrace_insn orig, new, old; - if (copy_from_kernel_nofault(&old, (void *) rec->ip, sizeof(old))) + if (probe_kernel_read(&old, (void *) rec->ip, sizeof(old))) return -EFAULT; if (is_kprobe_on_ftrace(&old)) { /* diff --git a/arch/s390/kernel/syscalls/syscall.tbl b/arch/s390/kernel/syscalls/syscall.tbl index 2b4a2df11f27..3c7aa43482b9 100644 --- a/arch/s390/kernel/syscalls/syscall.tbl +++ b/arch/s390/kernel/syscalls/syscall.tbl @@ -438,9 +438,8 @@ 433 common fspick sys_fspick sys_fspick 434 common pidfd_open sys_pidfd_open sys_pidfd_open 435 common clone3 sys_clone3 sys_clone3 -436 common close_range sys_close_range sys_close_range +# 436 reserved for close_range # 437 reserved for openat2 # 438 reserved for pidfd_getfd # 439 reserved for faccessat2 440 common process_madvise sys_process_madvise sys_process_madvise -441 common epoll_pwait2 sys_epoll_pwait2 compat_sys_epoll_pwait2 diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c index d1a67554ca0b..3627953007ed 100644 --- a/arch/s390/kernel/topology.c +++ b/arch/s390/kernel/topology.c @@ -584,7 +584,7 @@ static int __init topology_setup(char *str) early_param("topology", topology_setup); static int topology_ctl_handler(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int enabled = topology_is_enabled(); int new_mode; diff --git a/arch/s390/mm/cmm.c b/arch/s390/mm/cmm.c index ab9d41b75048..756aefbd0524 100644 --- a/arch/s390/mm/cmm.c +++ b/arch/s390/mm/cmm.c @@ -263,7 +263,7 @@ static int cmm_skip_blanks(char *cp, char **endp) } static int cmm_pages_handler(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { long nr = cmm_get_pages(); struct ctl_table ctl_entry = { @@ -282,7 +282,7 @@ static int cmm_pages_handler(struct ctl_table *ctl, int write, } static int cmm_timed_pages_handler(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, + void __user *buffer, size_t *lenp, loff_t *ppos) { long nr = cmm_get_timed_pages(); @@ -302,7 +302,7 @@ static int cmm_timed_pages_handler(struct ctl_table *ctl, int write, } static int cmm_timeout_handler(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { char buf[64], *p; long nr, seconds; @@ -315,7 +315,8 @@ static int cmm_timeout_handler(struct ctl_table *ctl, int write, if (write) { len = min(*lenp, sizeof(buf)); - memcpy(buf, buffer, len); + if (copy_from_user(buf, buffer, len)) + return -EFAULT; buf[len - 1] = '\0'; cmm_skip_blanks(buf, &p); nr = simple_strtoul(p, &p, 0); @@ -328,7 +329,8 @@ static int cmm_timeout_handler(struct ctl_table *ctl, int write, cmm_timeout_pages, cmm_timeout_seconds); if (len > *lenp) len = *lenp; - memcpy(buffer, buf, len); + if (copy_to_user(buffer, buf, len)) + return -EFAULT; *lenp = len; *ppos += len; } diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c index 9a618d2ef9f7..987c663317e0 100644 --- a/arch/s390/mm/fault.c +++ b/arch/s390/mm/fault.c @@ -105,7 +105,7 @@ static int bad_address(void *p) { unsigned long dummy; - return get_kernel_nofault(dummy, (unsigned long *)p); + return probe_kernel_address((unsigned long *)p, dummy); } static void dump_pagetable(unsigned long asce, unsigned long address) diff --git a/arch/sh/include/asm/seccomp.h b/arch/sh/include/asm/seccomp.h index d4578395fd66..54111e4d32b8 100644 --- a/arch/sh/include/asm/seccomp.h +++ b/arch/sh/include/asm/seccomp.h @@ -8,14 +8,4 @@ #define __NR_seccomp_exit __NR_exit #define __NR_seccomp_sigreturn __NR_rt_sigreturn -#ifdef CONFIG_CPU_LITTLE_ENDIAN -#define __SECCOMP_ARCH_LE __AUDIT_ARCH_LE -#else -#define __SECCOMP_ARCH_LE 0 -#endif - -#define SECCOMP_ARCH_NATIVE (AUDIT_ARCH_SH | __SECCOMP_ARCH_LE) -#define SECCOMP_ARCH_NATIVE_NR NR_syscalls -#define SECCOMP_ARCH_NATIVE_NAME "sh" - #endif /* __ASM_SECCOMP_H */ diff --git a/arch/sh/kernel/ftrace.c b/arch/sh/kernel/ftrace.c index 0646c5961846..1b04270e5460 100644 --- a/arch/sh/kernel/ftrace.c +++ b/arch/sh/kernel/ftrace.c @@ -119,7 +119,7 @@ static void ftrace_mod_code(void) * But if one were to fail, then they all should, and if one were * to succeed, then they all should. */ - mod_code_status = copy_to_kernel_nofault(mod_code_ip, mod_code_newcode, + mod_code_status = probe_kernel_write(mod_code_ip, mod_code_newcode, MCOUNT_INSN_SIZE); /* if we fail, then kill any new writers */ @@ -203,7 +203,7 @@ static int ftrace_modify_code(unsigned long ip, unsigned char *old_code, */ /* read the text we want to modify */ - if (copy_from_kernel_nofault(replaced, (void *)ip, MCOUNT_INSN_SIZE)) + if (probe_kernel_read(replaced, (void *)ip, MCOUNT_INSN_SIZE)) return -EFAULT; /* Make sure it is what we expect it to be */ @@ -268,7 +268,7 @@ static int ftrace_mod(unsigned long ip, unsigned long old_addr, { unsigned char code[MCOUNT_INSN_SIZE]; - if (copy_from_kernel_nofault(code, (void *)ip, MCOUNT_INSN_SIZE)) + if (probe_kernel_read(code, (void *)ip, MCOUNT_INSN_SIZE)) return -EFAULT; if (old_addr != __raw_readl((unsigned long *)code)) diff --git a/arch/sh/kernel/syscalls/syscall.tbl b/arch/sh/kernel/syscalls/syscall.tbl index 93f8fc0f66b8..5a4b36ba71c4 100644 --- a/arch/sh/kernel/syscalls/syscall.tbl +++ b/arch/sh/kernel/syscalls/syscall.tbl @@ -438,9 +438,8 @@ 433 common fspick sys_fspick 434 common pidfd_open sys_pidfd_open # 435 reserved for clone3 -436 common close_range sys_close_range +# 436 reserved for close_range # 437 reserved for openat2 # 438 reserved for pidfd_getfd # 439 reserved for faccessat2 440 common process_madvise sys_process_madvise -441 common epoll_pwait2 sys_epoll_pwait2 diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c index c519473d0d3c..6a228c00b73f 100644 --- a/arch/sh/kernel/traps.c +++ b/arch/sh/kernel/traps.c @@ -118,7 +118,7 @@ int is_valid_bugaddr(unsigned long addr) if (addr < PAGE_OFFSET) return 0; - if (get_kernel_nofault(opcode, (insn_size_t *)addr)) + if (probe_kernel_address((insn_size_t *)addr, opcode)) return 0; if (opcode == TRAPA_BUG_OPCODE) return 1; diff --git a/arch/sparc/include/asm/elf_64.h b/arch/sparc/include/asm/elf_64.h index d3dda47d0bc5..7e078bc73ef5 100644 --- a/arch/sparc/include/asm/elf_64.h +++ b/arch/sparc/include/asm/elf_64.h @@ -59,7 +59,6 @@ #define R_SPARC_7 43 #define R_SPARC_5 44 #define R_SPARC_6 45 -#define R_SPARC_UA64 54 /* Bits present in AT_HWCAP, primarily for Sparc32. */ #define HWCAP_SPARC_FLUSH 0x00000001 diff --git a/arch/sparc/include/uapi/asm/socket.h b/arch/sparc/include/uapi/asm/socket.h index 08f9bbbf5bf2..8029b681fc7c 100644 --- a/arch/sparc/include/uapi/asm/socket.h +++ b/arch/sparc/include/uapi/asm/socket.h @@ -117,8 +117,6 @@ #define SO_DETACH_REUSEPORT_BPF 0x0047 -#define SO_NETNS_COOKIE 0x0050 - #if !defined(__KERNEL__) diff --git a/arch/sparc/kernel/module.c b/arch/sparc/kernel/module.c index 737f7a5c2835..df39580f398d 100644 --- a/arch/sparc/kernel/module.c +++ b/arch/sparc/kernel/module.c @@ -117,7 +117,6 @@ int apply_relocate_add(Elf_Shdr *sechdrs, break; #ifdef CONFIG_SPARC64 case R_SPARC_64: - case R_SPARC_UA64: location[0] = v >> 56; location[1] = v >> 48; location[2] = v >> 40; diff --git a/arch/sparc/kernel/of_device_32.c b/arch/sparc/kernel/of_device_32.c index b06b92c9a375..4ebf51e6e78e 100644 --- a/arch/sparc/kernel/of_device_32.c +++ b/arch/sparc/kernel/of_device_32.c @@ -387,7 +387,6 @@ static struct platform_device * __init scan_one_device(struct device_node *dp, if (of_device_register(op)) { printk("%pOF: Could not register of device.\n", dp); - put_device(&op->dev); kfree(op); op = NULL; } diff --git a/arch/sparc/kernel/of_device_64.c b/arch/sparc/kernel/of_device_64.c index 6e616bd5cc46..5a9f86b1d4e7 100644 --- a/arch/sparc/kernel/of_device_64.c +++ b/arch/sparc/kernel/of_device_64.c @@ -680,7 +680,6 @@ static struct platform_device * __init scan_one_device(struct device_node *dp, if (of_device_register(op)) { printk("%pOF: Could not register of device.\n", dp); - put_device(&op->dev); kfree(op); op = NULL; } diff --git a/arch/sparc/kernel/syscalls/syscall.tbl b/arch/sparc/kernel/syscalls/syscall.tbl index 6a1b13bf4335..4d6bdb03e44d 100644 --- a/arch/sparc/kernel/syscalls/syscall.tbl +++ b/arch/sparc/kernel/syscalls/syscall.tbl @@ -481,9 +481,8 @@ 433 common fspick sys_fspick 434 common pidfd_open sys_pidfd_open # 435 reserved for clone3 -436 common close_range sys_close_range +# 436 reserved for close_range # 437 reserved for openat2 # 438 reserved for pidfd_getfd # 439 reserved for faccessat2 440 common process_madvise sys_process_madvise -441 common epoll_pwait2 sys_epoll_pwait2 compat_sys_epoll_pwait2 diff --git a/arch/sparc/lib/M7memcpy.S b/arch/sparc/lib/M7memcpy.S index 99357bfa8e82..cbd42ea7c3f7 100644 --- a/arch/sparc/lib/M7memcpy.S +++ b/arch/sparc/lib/M7memcpy.S @@ -696,16 +696,16 @@ FUNC_NAME: EX_LD_FP(LOAD(ldd, %o4+40, %f26), memcpy_retl_o2_plus_o5_plus_40) faligndata %f24, %f26, %f10 EX_ST_FP(STORE(std, %f6, %o0+24), memcpy_retl_o2_plus_o5_plus_40) - EX_LD_FP(LOAD(ldd, %o4+48, %f28), memcpy_retl_o2_plus_o5_plus_32) + EX_LD_FP(LOAD(ldd, %o4+48, %f28), memcpy_retl_o2_plus_o5_plus_40) faligndata %f26, %f28, %f12 - EX_ST_FP(STORE(std, %f8, %o0+32), memcpy_retl_o2_plus_o5_plus_32) + EX_ST_FP(STORE(std, %f8, %o0+32), memcpy_retl_o2_plus_o5_plus_40) add %o4, 64, %o4 - EX_LD_FP(LOAD(ldd, %o4-8, %f30), memcpy_retl_o2_plus_o5_plus_24) + EX_LD_FP(LOAD(ldd, %o4-8, %f30), memcpy_retl_o2_plus_o5_plus_40) faligndata %f28, %f30, %f14 - EX_ST_FP(STORE(std, %f10, %o0+40), memcpy_retl_o2_plus_o5_plus_24) - EX_ST_FP(STORE(std, %f12, %o0+48), memcpy_retl_o2_plus_o5_plus_16) + EX_ST_FP(STORE(std, %f10, %o0+40), memcpy_retl_o2_plus_o5_plus_40) + EX_ST_FP(STORE(std, %f12, %o0+48), memcpy_retl_o2_plus_o5_plus_40) add %o0, 64, %o0 - EX_ST_FP(STORE(std, %f14, %o0-8), memcpy_retl_o2_plus_o5_plus_8) + EX_ST_FP(STORE(std, %f14, %o0-8), memcpy_retl_o2_plus_o5_plus_40) fsrc2 %f30, %f14 bgu,pt %xcc, .Lunalign_sloop prefetch [%o4 + (8 * BLOCK_SIZE)], 20 @@ -728,7 +728,7 @@ FUNC_NAME: add %o4, 8, %o4 faligndata %f0, %f2, %f16 subcc %o5, 8, %o5 - EX_ST_FP(STORE(std, %f16, %o0), memcpy_retl_o2_plus_o5_plus_8) + EX_ST_FP(STORE(std, %f16, %o0), memcpy_retl_o2_plus_o5) fsrc2 %f2, %f0 bgu,pt %xcc, .Lunalign_by8 add %o0, 8, %o0 @@ -772,7 +772,7 @@ FUNC_NAME: subcc %o5, 0x20, %o5 EX_ST(STORE(stx, %o3, %o0 + 0x00), memcpy_retl_o2_plus_o5_plus_32) EX_ST(STORE(stx, %g2, %o0 + 0x08), memcpy_retl_o2_plus_o5_plus_24) - EX_ST(STORE(stx, %g7, %o0 + 0x10), memcpy_retl_o2_plus_o5_plus_16) + EX_ST(STORE(stx, %g7, %o0 + 0x10), memcpy_retl_o2_plus_o5_plus_24) EX_ST(STORE(stx, %o4, %o0 + 0x18), memcpy_retl_o2_plus_o5_plus_8) bne,pt %xcc, 1b add %o0, 0x20, %o0 @@ -804,12 +804,12 @@ FUNC_NAME: brz,pt %o3, 2f sub %o2, %o3, %o2 -1: EX_LD(LOAD(ldub, %o1 + 0x00, %g2), memcpy_retl_o2_plus_o3) +1: EX_LD(LOAD(ldub, %o1 + 0x00, %g2), memcpy_retl_o2_plus_g1) add %o1, 1, %o1 subcc %o3, 1, %o3 add %o0, 1, %o0 bne,pt %xcc, 1b - EX_ST(STORE(stb, %g2, %o0 - 0x01), memcpy_retl_o2_plus_o3_plus_1) + EX_ST(STORE(stb, %g2, %o0 - 0x01), memcpy_retl_o2_plus_g1_plus_1) 2: and %o1, 0x7, %o3 brz,pn %o3, .Lmedium_noprefetch_cp diff --git a/arch/sparc/lib/Memcpy_utils.S b/arch/sparc/lib/Memcpy_utils.S index 207343367bb2..64fbac28b3db 100644 --- a/arch/sparc/lib/Memcpy_utils.S +++ b/arch/sparc/lib/Memcpy_utils.S @@ -137,15 +137,6 @@ ENTRY(memcpy_retl_o2_plus_63_8) ba,pt %xcc, __restore_asi add %o2, 8, %o0 ENDPROC(memcpy_retl_o2_plus_63_8) -ENTRY(memcpy_retl_o2_plus_o3) - ba,pt %xcc, __restore_asi - add %o2, %o3, %o0 -ENDPROC(memcpy_retl_o2_plus_o3) -ENTRY(memcpy_retl_o2_plus_o3_plus_1) - add %o3, 1, %o3 - ba,pt %xcc, __restore_asi - add %o2, %o3, %o0 -ENDPROC(memcpy_retl_o2_plus_o3_plus_1) ENTRY(memcpy_retl_o2_plus_o5) ba,pt %xcc, __restore_asi add %o2, %o5, %o0 diff --git a/arch/sparc/lib/NG4memcpy.S b/arch/sparc/lib/NG4memcpy.S index df0ec1bd1948..7ad58ebe0d00 100644 --- a/arch/sparc/lib/NG4memcpy.S +++ b/arch/sparc/lib/NG4memcpy.S @@ -281,7 +281,7 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ subcc %o5, 0x20, %o5 EX_ST(STORE(stx, %g1, %o0 + 0x00), memcpy_retl_o2_plus_o5_plus_32) EX_ST(STORE(stx, %g2, %o0 + 0x08), memcpy_retl_o2_plus_o5_plus_24) - EX_ST(STORE(stx, GLOBAL_SPARE, %o0 + 0x10), memcpy_retl_o2_plus_o5_plus_16) + EX_ST(STORE(stx, GLOBAL_SPARE, %o0 + 0x10), memcpy_retl_o2_plus_o5_plus_24) EX_ST(STORE(stx, %o4, %o0 + 0x18), memcpy_retl_o2_plus_o5_plus_8) bne,pt %icc, 1b add %o0, 0x20, %o0 diff --git a/arch/sparc/lib/NGmemcpy.S b/arch/sparc/lib/NGmemcpy.S index 846a8c4ea394..8e4d22a6ba0b 100644 --- a/arch/sparc/lib/NGmemcpy.S +++ b/arch/sparc/lib/NGmemcpy.S @@ -80,8 +80,8 @@ #ifndef EX_RETVAL #define EX_RETVAL(x) x __restore_asi: - wr %g0, ASI_AIUS, %asi ret + wr %g0, ASI_AIUS, %asi restore ENTRY(NG_ret_i2_plus_i4_plus_1) ba,pt %xcc, __restore_asi @@ -126,16 +126,15 @@ ENTRY(NG_ret_i2_plus_g1_minus_56) ba,pt %xcc, __restore_asi add %i2, %g1, %i0 ENDPROC(NG_ret_i2_plus_g1_minus_56) -ENTRY(NG_ret_i2_plus_i4_plus_16) - add %i4, 16, %i4 +ENTRY(NG_ret_i2_plus_i4) ba,pt %xcc, __restore_asi add %i2, %i4, %i0 -ENDPROC(NG_ret_i2_plus_i4_plus_16) -ENTRY(NG_ret_i2_plus_i4_plus_8) - add %i4, 8, %i4 +ENDPROC(NG_ret_i2_plus_i4) +ENTRY(NG_ret_i2_plus_i4_minus_8) + sub %i4, 8, %i4 ba,pt %xcc, __restore_asi add %i2, %i4, %i0 -ENDPROC(NG_ret_i2_plus_i4_plus_8) +ENDPROC(NG_ret_i2_plus_i4_minus_8) ENTRY(NG_ret_i2_plus_8) ba,pt %xcc, __restore_asi add %i2, 8, %i0 @@ -162,12 +161,6 @@ ENTRY(NG_ret_i2_and_7_plus_i4) ba,pt %xcc, __restore_asi add %i2, %i4, %i0 ENDPROC(NG_ret_i2_and_7_plus_i4) -ENTRY(NG_ret_i2_and_7_plus_i4_plus_8) - and %i2, 7, %i2 - add %i4, 8, %i4 - ba,pt %xcc, __restore_asi - add %i2, %i4, %i0 -ENDPROC(NG_ret_i2_and_7_plus_i4) #endif .align 64 @@ -413,13 +406,13 @@ FUNC_NAME: /* %i0=dst, %i1=src, %i2=len */ andn %i2, 0xf, %i4 and %i2, 0xf, %i2 1: subcc %i4, 0x10, %i4 - EX_LD(LOAD(ldx, %i1, %o4), NG_ret_i2_plus_i4_plus_16) + EX_LD(LOAD(ldx, %i1, %o4), NG_ret_i2_plus_i4) add %i1, 0x08, %i1 - EX_LD(LOAD(ldx, %i1, %g1), NG_ret_i2_plus_i4_plus_16) + EX_LD(LOAD(ldx, %i1, %g1), NG_ret_i2_plus_i4) sub %i1, 0x08, %i1 - EX_ST(STORE(stx, %o4, %i1 + %i3), NG_ret_i2_plus_i4_plus_16) + EX_ST(STORE(stx, %o4, %i1 + %i3), NG_ret_i2_plus_i4) add %i1, 0x8, %i1 - EX_ST(STORE(stx, %g1, %i1 + %i3), NG_ret_i2_plus_i4_plus_8) + EX_ST(STORE(stx, %g1, %i1 + %i3), NG_ret_i2_plus_i4_minus_8) bgu,pt %XCC, 1b add %i1, 0x8, %i1 73: andcc %i2, 0x8, %g0 @@ -476,7 +469,7 @@ FUNC_NAME: /* %i0=dst, %i1=src, %i2=len */ subcc %i4, 0x8, %i4 srlx %g3, %i3, %i5 or %i5, %g2, %i5 - EX_ST(STORE(stx, %i5, %o0), NG_ret_i2_and_7_plus_i4_plus_8) + EX_ST(STORE(stx, %i5, %o0), NG_ret_i2_and_7_plus_i4) add %o0, 0x8, %o0 bgu,pt %icc, 1b sllx %g3, %g1, %g2 diff --git a/arch/sparc/lib/U1memcpy.S b/arch/sparc/lib/U1memcpy.S index 021b94a383d1..a6f4ee391897 100644 --- a/arch/sparc/lib/U1memcpy.S +++ b/arch/sparc/lib/U1memcpy.S @@ -164,18 +164,17 @@ ENTRY(U1_gs_40_fp) retl add %o0, %o2, %o0 ENDPROC(U1_gs_40_fp) +ENTRY(U1_g3_0_fp) + VISExitHalf + retl + add %g3, %o2, %o0 +ENDPROC(U1_g3_0_fp) ENTRY(U1_g3_8_fp) VISExitHalf add %g3, 8, %g3 retl add %g3, %o2, %o0 ENDPROC(U1_g3_8_fp) -ENTRY(U1_g3_16_fp) - VISExitHalf - add %g3, 16, %g3 - retl - add %g3, %o2, %o0 -ENDPROC(U1_g3_16_fp) ENTRY(U1_o2_0_fp) VISExitHalf retl @@ -548,18 +547,18 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ 62: FINISH_VISCHUNK(o0, f44, f46) 63: UNEVEN_VISCHUNK_LAST(o0, f46, f0) -93: EX_LD_FP(LOAD(ldd, %o1, %f2), U1_g3_8_fp) +93: EX_LD_FP(LOAD(ldd, %o1, %f2), U1_g3_0_fp) add %o1, 8, %o1 subcc %g3, 8, %g3 faligndata %f0, %f2, %f8 - EX_ST_FP(STORE(std, %f8, %o0), U1_g3_16_fp) + EX_ST_FP(STORE(std, %f8, %o0), U1_g3_8_fp) bl,pn %xcc, 95f add %o0, 8, %o0 - EX_LD_FP(LOAD(ldd, %o1, %f0), U1_g3_8_fp) + EX_LD_FP(LOAD(ldd, %o1, %f0), U1_g3_0_fp) add %o1, 8, %o1 subcc %g3, 8, %g3 faligndata %f2, %f0, %f8 - EX_ST_FP(STORE(std, %f8, %o0), U1_g3_16_fp) + EX_ST_FP(STORE(std, %f8, %o0), U1_g3_8_fp) bge,pt %xcc, 93b add %o0, 8, %o0 diff --git a/arch/sparc/lib/U3memcpy.S b/arch/sparc/lib/U3memcpy.S index bace3a18f836..9248d59c734c 100644 --- a/arch/sparc/lib/U3memcpy.S +++ b/arch/sparc/lib/U3memcpy.S @@ -267,7 +267,6 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ faligndata %f10, %f12, %f26 EX_LD_FP(LOAD(ldd, %o1 + 0x040, %f0), U3_retl_o2) - and %o2, 0x3f, %o2 subcc GLOBAL_SPARE, 0x80, GLOBAL_SPARE add %o1, 0x40, %o1 bgu,pt %XCC, 1f @@ -337,6 +336,7 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ * Also notice how this code is careful not to perform a * load past the end of the src buffer. */ + and %o2, 0x3f, %o2 andcc %o2, 0x38, %g2 be,pn %XCC, 2f subcc %g2, 0x8, %g2 diff --git a/arch/sparc/mm/hugetlbpage.c b/arch/sparc/mm/hugetlbpage.c index d1b939636440..9aabfae83177 100644 --- a/arch/sparc/mm/hugetlbpage.c +++ b/arch/sparc/mm/hugetlbpage.c @@ -134,26 +134,6 @@ hugetlb_get_unmapped_area(struct file *file, unsigned long addr, static pte_t sun4u_hugepage_shift_to_tte(pte_t entry, unsigned int shift) { - unsigned long hugepage_size = _PAGE_SZ4MB_4U; - - pte_val(entry) = pte_val(entry) & ~_PAGE_SZALL_4U; - - switch (shift) { - case HPAGE_256MB_SHIFT: - hugepage_size = _PAGE_SZ256MB_4U; - pte_val(entry) |= _PAGE_PMD_HUGE; - break; - case HPAGE_SHIFT: - pte_val(entry) |= _PAGE_PMD_HUGE; - break; - case HPAGE_64K_SHIFT: - hugepage_size = _PAGE_SZ64K_4U; - break; - default: - WARN_ONCE(1, "unsupported hugepage shift=%u\n", shift); - } - - pte_val(entry) = pte_val(entry) | hugepage_size; return entry; } diff --git a/arch/um/kernel/maccess.c b/arch/um/kernel/maccess.c index 8ccd56813f68..67b2e0fa92bb 100644 --- a/arch/um/kernel/maccess.c +++ b/arch/um/kernel/maccess.c @@ -7,13 +7,15 @@ #include #include -bool copy_from_kernel_nofault_allowed(const void *src, size_t size) +long probe_kernel_read(void *dst, const void *src, size_t size) { void *psrc = (void *)rounddown((unsigned long)src, PAGE_SIZE); if ((unsigned long)src < PAGE_SIZE || size <= 0) - return false; + return -EFAULT; + if (os_mincore(psrc, size + src - psrc) <= 0) - return false; - return true; + return -EFAULT; + + return __probe_kernel_read(dst, src, size); } diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 8a42463ffee5..0d438140d592 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -71,7 +71,6 @@ config X86 select ARCH_HAS_KCOV if X86_64 select ARCH_HAS_MEM_ENCRYPT select ARCH_HAS_MEMBARRIER_SYNC_CORE - select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE select ARCH_HAS_PMEM_API if X86_64 select ARCH_HAS_PTE_DEVMAP if X86_64 select ARCH_HAS_PTE_SPECIAL @@ -97,7 +96,6 @@ config X86 select ARCH_USE_QUEUED_RWLOCKS select ARCH_USE_QUEUED_SPINLOCKS select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH - select ARCH_WANT_DEFAULT_BPF_JIT if X86_64 select ARCH_WANTS_DYNAMIC_TASK_STRUCT select ARCH_WANT_HUGE_PMD_SHARE if X86_64 select ARCH_WANTS_THP_SWAP if X86_64 @@ -139,7 +137,6 @@ config X86 select HAVE_ARCH_JUMP_LABEL select HAVE_ARCH_JUMP_LABEL_RELATIVE select HAVE_ARCH_KASAN if X86_64 - select HAVE_ARCH_KFENCE select HAVE_ARCH_KGDB select HAVE_ARCH_MMAP_RND_BITS if MMU select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT diff --git a/arch/x86/configs/gki_defconfig b/arch/x86/configs/gki_defconfig index ebab1f1901d8..aecbc3383f84 100644 --- a/arch/x86/configs/gki_defconfig +++ b/arch/x86/configs/gki_defconfig @@ -188,27 +188,14 @@ CONFIG_L2TP=y CONFIG_BRIDGE=y CONFIG_NET_SCHED=y CONFIG_NET_SCH_HTB=y -CONFIG_NET_SCH_PRIO=y -CONFIG_NET_SCH_MULTIQ=y -CONFIG_NET_SCH_TBF=y -CONFIG_NET_SCH_NETEM=y CONFIG_NET_SCH_INGRESS=y CONFIG_NET_CLS_U32=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=y CONFIG_NET_CLS_BPF=y CONFIG_NET_CLS_MATCHALL=y CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=y -CONFIG_NET_EMATCH_NBYTE=y CONFIG_NET_EMATCH_U32=y -CONFIG_NET_EMATCH_META=y -CONFIG_NET_EMATCH_TEXT=y CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_POLICE=y -CONFIG_NET_ACT_GACT=y -CONFIG_NET_ACT_MIRRED=y -CONFIG_NET_ACT_SKBEDIT=y CONFIG_NET_ACT_BPF=y CONFIG_BPF_JIT=y CONFIG_BT=y @@ -301,8 +288,6 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_JOYSTICK=y CONFIG_JOYSTICK_XPAD=y -CONFIG_JOYSTICK_XPAD_FF=y -CONFIG_JOYSTICK_XPAD_LEDS=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_INPUT_MISC=y CONFIG_INPUT_UINPUT=y @@ -359,7 +344,6 @@ CONFIG_HID_BATTERY_STRENGTH=y CONFIG_HIDRAW=y CONFIG_UHID=y CONFIG_HID_APPLE=y -CONFIG_HID_BETOP_FF=y CONFIG_HID_PRODIKEYS=y CONFIG_HID_ELECOM=y CONFIG_HID_UCLOGIC=y @@ -442,7 +426,6 @@ CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y CONFIG_QUOTA=y CONFIG_QFMT_V2=y CONFIG_FUSE_FS=y -CONFIG_FUSE_BPF=y CONFIG_OVERLAY_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y @@ -534,9 +517,6 @@ CONFIG_DEBUG_INFO_DWARF4=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_STACK_USAGE=y CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_KFENCE=y -CONFIG_KFENCE_SAMPLE_INTERVAL=500 -CONFIG_KFENCE_NUM_OBJECTS=63 CONFIG_SOFTLOCKUP_DETECTOR=y # CONFIG_DETECT_HUNG_TASK is not set CONFIG_PANIC_ON_OOPS=y diff --git a/arch/x86/entry/syscalls/syscall_32.tbl b/arch/x86/entry/syscalls/syscall_32.tbl index 67dfcbc9bf98..3b161e17479e 100644 --- a/arch/x86/entry/syscalls/syscall_32.tbl +++ b/arch/x86/entry/syscalls/syscall_32.tbl @@ -440,9 +440,8 @@ 433 i386 fspick sys_fspick __ia32_sys_fspick 434 i386 pidfd_open sys_pidfd_open __ia32_sys_pidfd_open 435 i386 clone3 sys_clone3 __ia32_sys_clone3 -436 i386 close_range sys_close_range +# 436 reserved for close_range # 437 reserved for openat2 # 438 reserved for pidfd_getfd # 439 reserved for faccessat2 440 i386 process_madvise sys_process_madvise -441 i386 epoll_pwait2 sys_epoll_pwait2 compat_sys_epoll_pwait2 diff --git a/arch/x86/entry/syscalls/syscall_64.tbl b/arch/x86/entry/syscalls/syscall_64.tbl index d6ebcaee65c3..9ebbe98df765 100644 --- a/arch/x86/entry/syscalls/syscall_64.tbl +++ b/arch/x86/entry/syscalls/syscall_64.tbl @@ -357,12 +357,11 @@ 433 common fspick __x64_sys_fspick 434 common pidfd_open __x64_sys_pidfd_open 435 common clone3 __x64_sys_clone3/ptregs -436 common close_range sys_close_range +# 436 reserved for close_range # 437 reserved for openat2 # 438 reserved for pidfd_getfd # 439 reserved for faccessat2 440 common process_madvise sys_process_madvise -441 common epoll_pwait2 sys_epoll_pwait2 # # x32-specific system call numbers start at 512 to avoid cache impact diff --git a/arch/x86/entry/vsyscall/vsyscall_64.c b/arch/x86/entry/vsyscall/vsyscall_64.c index 85e80f0a8b15..86e5a1c1055f 100644 --- a/arch/x86/entry/vsyscall/vsyscall_64.c +++ b/arch/x86/entry/vsyscall/vsyscall_64.c @@ -124,12 +124,7 @@ bool emulate_vsyscall(unsigned long error_code, if ((error_code & (X86_PF_WRITE | X86_PF_USER)) != X86_PF_USER) return false; - /* - * Assume that faults at regs->ip are because of an - * instruction fetch. Return early and avoid - * emulation for faults during data accesses: - */ - if (address != regs->ip) { + if (!(error_code & X86_PF_INSTR)) { /* Failed vsyscall read */ if (vsyscall_mode == EMULATE) return false; @@ -141,19 +136,13 @@ bool emulate_vsyscall(unsigned long error_code, return false; } - /* - * X86_PF_INSTR is only set when NX is supported. When - * available, use it to double-check that the emulation code - * is only being used for instruction fetches: - */ - if (cpu_feature_enabled(X86_FEATURE_NX)) - WARN_ON_ONCE(!(error_code & X86_PF_INSTR)); - /* * No point in checking CS -- the only way to get here is a user mode * trap to a high address, which means that we're in 64-bit user code. */ + WARN_ON_ONCE(address != regs->ip); + if (vsyscall_mode == NONE) { warn_bad_vsyscall(KERN_INFO, regs, "vsyscall attempted with vsyscall=none"); diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c index 748074645aba..df4a4a9dc1e8 100644 --- a/arch/x86/hyperv/hv_init.c +++ b/arch/x86/hyperv/hv_init.c @@ -83,7 +83,8 @@ static int hv_cpu_init(unsigned int cpu) * not be stopped in the case of CPU offlining and the VM will hang. */ if (!*hvp) { - *hvp = __vmalloc(PAGE_SIZE, GFP_KERNEL | __GFP_ZERO); + *hvp = __vmalloc(PAGE_SIZE, GFP_KERNEL | __GFP_ZERO, + PAGE_KERNEL); } if (*hvp) { diff --git a/arch/x86/include/asm/kfence.h b/arch/x86/include/asm/kfence.h deleted file mode 100644 index 2d66d70600bd..000000000000 --- a/arch/x86/include/asm/kfence.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * x86 KFENCE support. - * - * Copyright (C) 2020, Google LLC. - */ - -#ifndef _ASM_X86_KFENCE_H -#define _ASM_X86_KFENCE_H - -#include -#include - -#include -#include -#include -#include - -/* Force 4K pages for __kfence_pool. */ -static inline bool arch_kfence_init_pool(void) -{ - unsigned long addr; - - for (addr = (unsigned long)__kfence_pool; is_kfence_address((void *)addr); - addr += PAGE_SIZE) { - unsigned int level; - - if (!lookup_address(addr, &level)) - return false; - - if (level != PG_LEVEL_4K) - set_memory_4k(addr, 1); - } - - return true; -} - -/* Protect the given page and flush TLB. */ -static inline bool kfence_protect_page(unsigned long addr, bool protect) -{ - unsigned int level; - pte_t *pte = lookup_address(addr, &level); - - if (WARN_ON(!pte || level != PG_LEVEL_4K)) - return false; - - /* - * We need to avoid IPIs, as we may get KFENCE allocations or faults - * with interrupts disabled. Therefore, the below is best-effort, and - * does not flush TLBs on all CPUs. We can tolerate some inaccuracy; - * lazy fault handling takes care of faults after the page is PRESENT. - */ - - if (protect) - set_pte(pte, __pte(pte_val(*pte) & ~_PAGE_PRESENT)); - else - set_pte(pte, __pte(pte_val(*pte) | _PAGE_PRESENT)); - - /* Flush this CPU's TLB. */ - __flush_tlb_one_kernel(addr); - return true; -} - -#endif /* _ASM_X86_KFENCE_H */ diff --git a/arch/x86/include/asm/kvm_emulate.h b/arch/x86/include/asm/kvm_emulate.h index f8e8799a8757..77cf6c11f66b 100644 --- a/arch/x86/include/asm/kvm_emulate.h +++ b/arch/x86/include/asm/kvm_emulate.h @@ -448,7 +448,7 @@ bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt); #define EMULATION_RESTART 1 #define EMULATION_INTERCEPTED 2 void init_decode_cache(struct x86_emulate_ctxt *ctxt); -int x86_emulate_insn(struct x86_emulate_ctxt *ctxt, bool check_intercepts); +int x86_emulate_insn(struct x86_emulate_ctxt *ctxt); int emulator_task_switch(struct x86_emulate_ctxt *ctxt, u16 tss_selector, int idt_index, int reason, bool has_error_code, u32 error_code); diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h index 6d4652329e4f..a88135c358c0 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -414,19 +414,19 @@ static inline void mds_idle_clear_cpu_buffers(void) * lfence * jmp spec_trap * do_rop: - * mov %rcx,(%rsp) for x86_64 + * mov %rax,(%rsp) for x86_64 * mov %edx,(%esp) for x86_32 * retq * * Without retpolines configured: * - * jmp *%rcx for x86_64 + * jmp *%rax for x86_64 * jmp *%edx for x86_32 */ #ifdef CONFIG_RETPOLINE # ifdef CONFIG_X86_64 -# define RETPOLINE_RCX_BPF_JIT_SIZE 17 -# define RETPOLINE_RCX_BPF_JIT() \ +# define RETPOLINE_RAX_BPF_JIT_SIZE 17 +# define RETPOLINE_RAX_BPF_JIT() \ do { \ EMIT1_off32(0xE8, 7); /* callq do_rop */ \ /* spec_trap: */ \ @@ -434,7 +434,7 @@ do { \ EMIT3(0x0F, 0xAE, 0xE8); /* lfence */ \ EMIT2(0xEB, 0xF9); /* jmp spec_trap */ \ /* do_rop: */ \ - EMIT4(0x48, 0x89, 0x0C, 0x24); /* mov %rcx,(%rsp) */ \ + EMIT4(0x48, 0x89, 0x04, 0x24); /* mov %rax,(%rsp) */ \ EMIT1(0xC3); /* retq */ \ } while (0) # else /* !CONFIG_X86_64 */ @@ -452,9 +452,9 @@ do { \ # endif #else /* !CONFIG_RETPOLINE */ # ifdef CONFIG_X86_64 -# define RETPOLINE_RCX_BPF_JIT_SIZE 2 -# define RETPOLINE_RCX_BPF_JIT() \ - EMIT2(0xFF, 0xE1); /* jmp *%rcx */ +# define RETPOLINE_RAX_BPF_JIT_SIZE 2 +# define RETPOLINE_RAX_BPF_JIT() \ + EMIT2(0xFF, 0xE0); /* jmp *%rax */ # else /* !CONFIG_X86_64 */ # define RETPOLINE_EDX_BPF_JIT() \ EMIT2(0xFF, 0xE2) /* jmp *%edx */ diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h index a7291fdeca21..902be2e6e96c 100644 --- a/arch/x86/include/asm/ptrace.h +++ b/arch/x86/include/asm/ptrace.h @@ -265,7 +265,7 @@ static inline unsigned long *regs_get_kernel_stack_nth_addr(struct pt_regs *regs } /* To avoid include hell, we can't include uaccess.h */ -extern long copy_from_kernel_nofault(void *dst, const void *src, size_t size); +extern long probe_kernel_read(void *dst, const void *src, size_t size); /** * regs_get_kernel_stack_nth() - get Nth entry of the stack @@ -285,7 +285,7 @@ static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, addr = regs_get_kernel_stack_nth_addr(regs, n); if (addr) { - ret = copy_from_kernel_nofault(&val, addr, sizeof(val)); + ret = probe_kernel_read(&val, addr, sizeof(val)); if (!ret) return val; } diff --git a/arch/x86/include/asm/seccomp.h b/arch/x86/include/asm/seccomp.h index fef16e398161..2bd1338de236 100644 --- a/arch/x86/include/asm/seccomp.h +++ b/arch/x86/include/asm/seccomp.h @@ -16,26 +16,6 @@ #define __NR_seccomp_sigreturn_32 __NR_ia32_sigreturn #endif -#ifdef CONFIG_X86_64 -# define SECCOMP_ARCH_NATIVE AUDIT_ARCH_X86_64 -# define SECCOMP_ARCH_NATIVE_NR NR_syscalls -# define SECCOMP_ARCH_NATIVE_NAME "x86_64" -# ifdef CONFIG_COMPAT -# define SECCOMP_ARCH_COMPAT AUDIT_ARCH_I386 -# define SECCOMP_ARCH_COMPAT_NR IA32_NR_syscalls -# define SECCOMP_ARCH_COMPAT_NAME "ia32" -# endif -/* - * x32 will have __X32_SYSCALL_BIT set in syscall number. We don't support - * caching them and they are treated as out of range syscalls, which will - * always pass through the BPF filter. - */ -#else /* !CONFIG_X86_64 */ -# define SECCOMP_ARCH_NATIVE AUDIT_ARCH_I386 -# define SECCOMP_ARCH_NATIVE_NR NR_syscalls -# define SECCOMP_ARCH_NATIVE_NAME "ia32" -#endif - #include #endif /* _ASM_X86_SECCOMP_H */ diff --git a/arch/x86/include/asm/segment.h b/arch/x86/include/asm/segment.h index 531a0cb93b47..6669164abadc 100644 --- a/arch/x86/include/asm/segment.h +++ b/arch/x86/include/asm/segment.h @@ -253,7 +253,7 @@ static inline unsigned long vdso_encode_cpunode(int cpu, unsigned long node) static inline void vdso_read_cpunode(unsigned *cpu, unsigned *node) { - unsigned long p; + unsigned int p; /* * Load CPU and node number from the GDT. LSL is faster than RDTSCP @@ -263,10 +263,10 @@ static inline void vdso_read_cpunode(unsigned *cpu, unsigned *node) * * If RDPID is available, use it. */ - alternative_io ("lsl %[seg],%k[p]", - "rdpid %[p]", + alternative_io ("lsl %[seg],%[p]", + ".byte 0xf3,0x0f,0xc7,0xf8", /* RDPID %eax/rax */ X86_FEATURE_RDPID, - [p] "=r" (p), [seg] "r" (__CPUNODE_SEG)); + [p] "=a" (p), [seg] "r" (__CPUNODE_SEG)); if (cpu) *cpu = (p & VDSO_CPUNODE_MASK); diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index b10e257799c1..4f803aed2ef0 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -1188,7 +1188,7 @@ set_mode: static const char * const spectre_v2_strings[] = { [SPECTRE_V2_NONE] = "Vulnerable", [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines", - [SPECTRE_V2_LFENCE] = "Vulnerable: LFENCE", + [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE", [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced / Automatic IBRS", [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced / Automatic IBRS + LFENCE", [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced / Automatic IBRS + Retpolines", @@ -2280,6 +2280,9 @@ static char *pbrsb_eibrs_state(void) static ssize_t spectre_v2_show_state(char *buf) { + if (spectre_v2_enabled == SPECTRE_V2_LFENCE) + return sysfs_emit(buf, "Vulnerable: LFENCE\n"); + if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled()) return sysfs_emit(buf, "Vulnerable: eIBRS with unprivileged eBPF\n"); diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index 85d275573af8..008bcb15fe96 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -225,19 +225,11 @@ static u64 mbm_overflow_count(u64 prev_msr, u64 cur_msr) static u64 __mon_event_count(u32 rmid, struct rmid_read *rr) { - struct mbm_state *m = NULL; + struct mbm_state *m; u64 chunks, tval; tval = __rmid_read(rmid, rr->evtid); if (tval & (RMID_VAL_ERROR | RMID_VAL_UNAVAIL)) { - if (tval & RMID_VAL_UNAVAIL) { - if (rr->evtid == QOS_L3_MBM_TOTAL_EVENT_ID) - m = &rr->d->mbm_total[rmid]; - else if (rr->evtid == QOS_L3_MBM_LOCAL_EVENT_ID) - m = &rr->d->mbm_local[rmid]; - if (m) - m->prev_msr = 0; - } return tval; } switch (rr->evtid) { diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index b5cc848a07fd..caf14c49539b 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -106,7 +106,7 @@ void show_opcodes(struct pt_regs *regs, const char *loglvl) bad_ip = user_mode(regs) && __chk_range_not_ok(prologue, OPCODE_BUFSIZE, TASK_SIZE_MAX); - if (bad_ip || copy_from_kernel_nofault(opcodes, (u8 *)prologue, + if (bad_ip || probe_kernel_read(opcodes, (u8 *)prologue, OPCODE_BUFSIZE)) { printk("%sCode: Bad RIP value.\n", loglvl); } else { diff --git a/arch/x86/kernel/ftrace.c b/arch/x86/kernel/ftrace.c index f969847dc85e..024c3053dbba 100644 --- a/arch/x86/kernel/ftrace.c +++ b/arch/x86/kernel/ftrace.c @@ -131,7 +131,7 @@ ftrace_modify_code_direct(unsigned long ip, unsigned const char *old_code, */ /* read the text we want to modify */ - if (copy_from_kernel_nofault(replaced, (void *)ip, MCOUNT_INSN_SIZE)) + if (probe_kernel_read(replaced, (void *)ip, MCOUNT_INSN_SIZE)) return -EFAULT; /* Make sure it is what we expect it to be */ @@ -341,7 +341,7 @@ static int add_break(unsigned long ip, const char *old) unsigned char replaced[MCOUNT_INSN_SIZE]; unsigned char brk = BREAKPOINT_INSTRUCTION; - if (copy_from_kernel_nofault(replaced, (void *)ip, MCOUNT_INSN_SIZE)) + if (probe_kernel_read(replaced, (void *)ip, MCOUNT_INSN_SIZE)) return -EFAULT; ftrace_expected = old; @@ -415,7 +415,7 @@ static int remove_breakpoint(struct dyn_ftrace *rec) unsigned long ip = rec->ip; /* If we fail the read, just give up */ - if (copy_from_kernel_nofault(ins, (void *)ip, MCOUNT_INSN_SIZE)) + if (probe_kernel_read(ins, (void *)ip, MCOUNT_INSN_SIZE)) return -EFAULT; /* If this does not have a breakpoint, we are done */ @@ -784,7 +784,7 @@ create_trampoline(struct ftrace_ops *ops, unsigned int *tramp_size) npages = DIV_ROUND_UP(*tramp_size, PAGE_SIZE); /* Copy ftrace_caller onto the trampoline memory */ - ret = copy_from_kernel_nofault(trampoline, (void *)start_offset, size); + ret = probe_kernel_read(trampoline, (void *)start_offset, size); if (WARN_ON(ret < 0)) goto fail; @@ -792,7 +792,7 @@ create_trampoline(struct ftrace_ops *ops, unsigned int *tramp_size) /* The trampoline ends with ret(q) */ retq = (unsigned long)ftrace_stub; - ret = copy_from_kernel_nofault(ip, (void *)retq, RET_SIZE); + ret = probe_kernel_read(ip, (void *)retq, RET_SIZE); if (WARN_ON(ret < 0)) goto fail; @@ -904,7 +904,7 @@ static void *addr_from_call(void *ptr) union ftrace_code_union calc; int ret; - ret = copy_from_kernel_nofault(&calc, ptr, MCOUNT_INSN_SIZE); + ret = probe_kernel_read(&calc, ptr, MCOUNT_INSN_SIZE); if (WARN_ON_ONCE(ret < 0)) return NULL; diff --git a/arch/x86/kernel/itmt.c b/arch/x86/kernel/itmt.c index 1afbdd1dd777..1cb3ca9bba49 100644 --- a/arch/x86/kernel/itmt.c +++ b/arch/x86/kernel/itmt.c @@ -39,7 +39,8 @@ static bool __read_mostly sched_itmt_capable; unsigned int __read_mostly sysctl_sched_itmt_enabled; static int sched_itmt_update_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { unsigned int old_sysctl; int ret; diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c index 68acd30c6b87..c44fe7d8d9a4 100644 --- a/arch/x86/kernel/kgdb.c +++ b/arch/x86/kernel/kgdb.c @@ -732,11 +732,11 @@ int kgdb_arch_set_breakpoint(struct kgdb_bkpt *bpt) int err; bpt->type = BP_BREAKPOINT; - err = copy_from_kernel_nofault(bpt->saved_instr, (char *)bpt->bpt_addr, + err = probe_kernel_read(bpt->saved_instr, (char *)bpt->bpt_addr, BREAK_INSTR_SIZE); if (err) return err; - err = copy_to_kernel_nofault((char *)bpt->bpt_addr, + err = probe_kernel_write((char *)bpt->bpt_addr, arch_kgdb_ops.gdb_bpt_instr, BREAK_INSTR_SIZE); if (!err) return err; @@ -768,7 +768,7 @@ int kgdb_arch_remove_breakpoint(struct kgdb_bkpt *bpt) return 0; knl_write: - return copy_to_kernel_nofault((char *)bpt->bpt_addr, + return probe_kernel_write((char *)bpt->bpt_addr, (char *)bpt->saved_instr, BREAK_INSTR_SIZE); } diff --git a/arch/x86/kernel/kprobes/core.c b/arch/x86/kernel/kprobes/core.c index 44a6cd1a1eba..3700dc94847c 100644 --- a/arch/x86/kernel/kprobes/core.c +++ b/arch/x86/kernel/kprobes/core.c @@ -249,7 +249,7 @@ __recover_probed_insn(kprobe_opcode_t *buf, unsigned long addr) * Fortunately, we know that the original code is the ideal 5-byte * long NOP. */ - if (copy_from_kernel_nofault(buf, (void *)addr, + if (probe_kernel_read(buf, (void *)addr, MAX_INSN_SIZE * sizeof(kprobe_opcode_t))) return 0UL; @@ -352,8 +352,7 @@ int __copy_instruction(u8 *dest, u8 *src, u8 *real, struct insn *insn) return 0; /* This can access kernel text if given address is not recovered */ - if (copy_from_kernel_nofault(dest, (void *)recovered_insn, - MAX_INSN_SIZE)) + if (probe_kernel_read(dest, (void *)recovered_insn, MAX_INSN_SIZE)) return 0; kernel_insn_init(insn, dest, MAX_INSN_SIZE); diff --git a/arch/x86/kernel/kprobes/opt.c b/arch/x86/kernel/kprobes/opt.c index ece2a868c29f..90d41b22c5c2 100644 --- a/arch/x86/kernel/kprobes/opt.c +++ b/arch/x86/kernel/kprobes/opt.c @@ -56,7 +56,7 @@ found: * overwritten by jump destination address. In this case, original * bytes must be recovered from op->optinsn.copied_insn buffer. */ - if (copy_from_kernel_nofault(buf, (void *)addr, + if (probe_kernel_read(buf, (void *)addr, MAX_INSN_SIZE * sizeof(kprobe_opcode_t))) return 0UL; diff --git a/arch/x86/kernel/probe_roms.c b/arch/x86/kernel/probe_roms.c index 65b0dd2bf25c..ee0286390a4c 100644 --- a/arch/x86/kernel/probe_roms.c +++ b/arch/x86/kernel/probe_roms.c @@ -99,7 +99,7 @@ static bool probe_list(struct pci_dev *pdev, unsigned short vendor, unsigned short device; do { - if (get_kernel_nofault(device, rom_list) != 0) + if (probe_kernel_address(rom_list, device) != 0) device = 0; if (device && match_id(pdev, vendor, device)) @@ -125,13 +125,13 @@ static struct resource *find_oprom(struct pci_dev *pdev) break; rom = isa_bus_to_virt(res->start); - if (get_kernel_nofault(offset, rom + 0x18) != 0) + if (probe_kernel_address(rom + 0x18, offset) != 0) continue; - if (get_kernel_nofault(vendor, rom + offset + 0x4) != 0) + if (probe_kernel_address(rom + offset + 0x4, vendor) != 0) continue; - if (get_kernel_nofault(device, rom + offset + 0x6) != 0) + if (probe_kernel_address(rom + offset + 0x6, device) != 0) continue; if (match_id(pdev, vendor, device)) { @@ -139,8 +139,8 @@ static struct resource *find_oprom(struct pci_dev *pdev) break; } - if (get_kernel_nofault(list, rom + offset + 0x8) == 0 && - get_kernel_nofault(rev, rom + offset + 0xc) == 0 && + if (probe_kernel_address(rom + offset + 0x8, list) == 0 && + probe_kernel_address(rom + offset + 0xc, rev) == 0 && rev >= 3 && list && probe_list(pdev, vendor, rom + offset + list)) { oprom = res; @@ -183,14 +183,14 @@ static int __init romsignature(const unsigned char *rom) const unsigned short * const ptr = (const unsigned short *)rom; unsigned short sig; - return get_kernel_nofault(sig, ptr) == 0 && sig == ROMSIGNATURE; + return probe_kernel_address(ptr, sig) == 0 && sig == ROMSIGNATURE; } static int __init romchecksum(const unsigned char *rom, unsigned long length) { unsigned char sum, c; - for (sum = 0; length && get_kernel_nofault(c, rom++) == 0; length--) + for (sum = 0; length && probe_kernel_address(rom++, c) == 0; length--) sum += c; return !length && !sum; } @@ -211,7 +211,7 @@ void __init probe_roms(void) video_rom_resource.start = start; - if (get_kernel_nofault(c, rom + 2) != 0) + if (probe_kernel_address(rom + 2, c) != 0) continue; /* 0 < length <= 0x7f * 512, historically */ @@ -249,7 +249,7 @@ void __init probe_roms(void) if (!romsignature(rom)) continue; - if (get_kernel_nofault(c, rom + 2) != 0) + if (probe_kernel_address(rom + 2, c) != 0) continue; /* 0 < length <= 0x7f * 512, historically */ diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index fed833b60d93..4bb0f8447112 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -165,7 +165,7 @@ int is_valid_bugaddr(unsigned long addr) if (addr < TASK_SIZE_MAX) return 0; - if (get_kernel_nofault(ud, (unsigned short *)addr)) + if (probe_kernel_address((unsigned short *)addr, ud)) return 0; return ud == INSN_UD0 || ud == INSN_UD2; diff --git a/arch/x86/kernel/umip.c b/arch/x86/kernel/umip.c index b97323edb4f4..548fefed71ee 100644 --- a/arch/x86/kernel/umip.c +++ b/arch/x86/kernel/umip.c @@ -155,26 +155,15 @@ static int identify_insn(struct insn *insn) if (!insn->modrm.nbytes) return -EINVAL; - /* The instructions of interest have 2-byte opcodes: 0F 00 or 0F 01. */ - if (insn->opcode.nbytes < 2 || insn->opcode.bytes[0] != 0xf) + /* All the instructions of interest start with 0x0f. */ + if (insn->opcode.bytes[0] != 0xf) return -EINVAL; if (insn->opcode.bytes[1] == 0x1) { switch (X86_MODRM_REG(insn->modrm.value)) { case 0: - /* The reg form of 0F 01 /0 encodes VMX instructions. */ - if (X86_MODRM_MOD(insn->modrm.value) == 3) - return -EINVAL; - return UMIP_INST_SGDT; case 1: - /* - * The reg form of 0F 01 /1 encodes MONITOR/MWAIT, - * STAC/CLAC, and ENCLS. - */ - if (X86_MODRM_MOD(insn->modrm.value) == 3) - return -EINVAL; - return UMIP_INST_SIDT; case 4: return UMIP_INST_SMSW; diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 90c495b87070..1a9fa2903852 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -5605,11 +5605,12 @@ void init_decode_cache(struct x86_emulate_ctxt *ctxt) ctxt->mem_read.end = 0; } -int x86_emulate_insn(struct x86_emulate_ctxt *ctxt, bool check_intercepts) +int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) { const struct x86_emulate_ops *ops = ctxt->ops; int rc = X86EMUL_CONTINUE; int saved_dst_type = ctxt->dst.type; + unsigned emul_flags; ctxt->mem_read.pos = 0; @@ -5624,6 +5625,7 @@ int x86_emulate_insn(struct x86_emulate_ctxt *ctxt, bool check_intercepts) goto done; } + emul_flags = ctxt->ops->get_hflags(ctxt); if (unlikely(ctxt->d & (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) { if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) || @@ -5657,7 +5659,7 @@ int x86_emulate_insn(struct x86_emulate_ctxt *ctxt, bool check_intercepts) fetch_possible_mmx_operand(ctxt, &ctxt->dst); } - if (unlikely(check_intercepts) && ctxt->intercept) { + if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) { rc = emulator_check_intercept(ctxt, ctxt->intercept, X86_ICPT_PRE_EXCEPT); if (rc != X86EMUL_CONTINUE) @@ -5686,7 +5688,7 @@ int x86_emulate_insn(struct x86_emulate_ctxt *ctxt, bool check_intercepts) goto done; } - if (unlikely(check_intercepts) && (ctxt->d & Intercept)) { + if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) { rc = emulator_check_intercept(ctxt, ctxt->intercept, X86_ICPT_POST_EXCEPT); if (rc != X86EMUL_CONTINUE) @@ -5740,7 +5742,7 @@ int x86_emulate_insn(struct x86_emulate_ctxt *ctxt, bool check_intercepts) special_insn: - if (unlikely(check_intercepts) && (ctxt->d & Intercept)) { + if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) { rc = emulator_check_intercept(ctxt, ctxt->intercept, X86_ICPT_POST_MEMACCESS); if (rc != X86EMUL_CONTINUE) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 9c53bc25aa36..8eb62dbb3a18 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -6855,14 +6855,7 @@ restart: /* Save the faulting GPA (cr2) in the address field */ ctxt->exception.address = cr2_or_gpa; - /* - * Check L1's instruction intercepts when emulating instructions for - * L2, unless KVM is re-emulating a previously decoded instruction, - * e.g. to complete userspace I/O, in which case KVM has already - * checked the intercepts. - */ - r = x86_emulate_insn(ctxt, is_guest_mode(vcpu) && - !(emulation_type & EMULTYPE_NO_DECODE)); + r = x86_emulate_insn(ctxt); if (r == EMULATION_INTERCEPTED) return 1; diff --git a/arch/x86/mm/Makefile b/arch/x86/mm/Makefile index bbc68a54795e..84373dc9b341 100644 --- a/arch/x86/mm/Makefile +++ b/arch/x86/mm/Makefile @@ -13,7 +13,7 @@ CFLAGS_REMOVE_mem_encrypt_identity.o = -pg endif obj-y := init.o init_$(BITS).o fault.o ioremap.o extable.o pageattr.o mmap.o \ - pat.o pgtable.o physaddr.o setup_nx.o tlb.o cpu_entry_area.o maccess.o + pat.o pgtable.o physaddr.o setup_nx.o tlb.o cpu_entry_area.o # Make sure __phys_addr has no stackprotector nostackp := $(call cc-option, -fno-stack-protector) diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index e6dc014ece01..b1b5b0856730 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -9,7 +9,6 @@ #include /* oops_begin/end, ... */ #include /* search_exception_tables */ #include /* max_low_pfn */ -#include /* kfence_handle_page_fault */ #include /* NOKPROBE_SYMBOL, ... */ #include /* kmmio_handler, ... */ #include /* perf_sw_event */ @@ -98,7 +97,7 @@ check_prefetch_opcode(struct pt_regs *regs, unsigned char *instr, return !instr_lo || (instr_lo>>1) == 1; case 0x00: /* Prefetch instruction is 0x0F0D or 0x0F18 */ - if (get_kernel_nofault(opcode, instr)) + if (probe_kernel_address(instr, opcode)) return 0; *prefetch = (instr_lo == 0xF) && @@ -132,7 +131,7 @@ is_prefetch(struct pt_regs *regs, unsigned long error_code, unsigned long addr) while (instr < max_instr) { unsigned char opcode; - if (get_kernel_nofault(opcode, instr)) + if (probe_kernel_address(instr, opcode)) break; instr++; @@ -441,7 +440,7 @@ static int bad_address(void *p) { unsigned long dummy; - return get_kernel_nofault(dummy, (unsigned long *)p); + return probe_kernel_address((unsigned long *)p, dummy); } static void dump_pagetable(unsigned long address) @@ -590,7 +589,7 @@ static void show_ldttss(const struct desc_ptr *gdt, const char *name, u16 index) return; } - if (copy_from_kernel_nofault(&desc, (void *)(gdt->address + offset), + if (probe_kernel_read(&desc, (void *)(gdt->address + offset), sizeof(struct ldttss_desc))) { pr_alert("%s: 0x%hx -- GDT entry is not readable\n", name, index); @@ -802,11 +801,6 @@ no_context(struct pt_regs *regs, unsigned long error_code, if (IS_ENABLED(CONFIG_EFI)) efi_recover_from_page_fault(address); - /* Only not-present faults should be handled by KFENCE. */ - if (!(error_code & X86_PF_PROT) && - kfence_handle_page_fault(address, error_code & X86_PF_WRITE, regs)) - return; - oops: /* * Oops. The kernel tried to access some bad page. We'll have to diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c index cb99d1ebe150..0a74407ef92e 100644 --- a/arch/x86/mm/init_32.c +++ b/arch/x86/mm/init_32.c @@ -752,7 +752,7 @@ static void __init test_wp_bit(void) __set_fixmap(FIX_WP_TEST, __pa_symbol(empty_zero_page), PAGE_KERNEL_RO); - if (copy_to_kernel_nofault((char *)fix_to_virt(FIX_WP_TEST), &z, 1)) { + if (probe_kernel_write((char *)fix_to_virt(FIX_WP_TEST), &z, 1)) { clear_fixmap(FIX_WP_TEST); printk(KERN_CONT "Ok.\n"); return; diff --git a/arch/x86/mm/maccess.c b/arch/x86/mm/maccess.c deleted file mode 100644 index 92ec176a7293..000000000000 --- a/arch/x86/mm/maccess.c +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include - -#ifdef CONFIG_X86_64 -static __always_inline u64 canonical_address(u64 vaddr, u8 vaddr_bits) -{ - return ((s64)vaddr << (64 - vaddr_bits)) >> (64 - vaddr_bits); -} - -bool copy_from_kernel_nofault_allowed(const void *unsafe_src, size_t size) -{ - unsigned long vaddr = (unsigned long)unsafe_src; - - /* - * Range covering the highest possible canonical userspace address - * as well as non-canonical address range. For the canonical range - * we also need to include the userspace guard page. - */ - return vaddr >= TASK_SIZE_MAX + PAGE_SIZE && - canonical_address(vaddr, boot_cpu_data.x86_virt_bits) == vaddr; -} -#else -bool copy_from_kernel_nofault_allowed(const void *unsafe_src, size_t size) -{ - return (unsigned long)unsafe_src >= TASK_SIZE_MAX; -} -#endif diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c index 81e651757946..55f62dca28aa 100644 --- a/arch/x86/net/bpf_jit_comp.c +++ b/arch/x86/net/bpf_jit_comp.c @@ -9,13 +9,9 @@ #include #include #include -#include -#include -#include + #include #include -#include -#include static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len) { @@ -100,7 +96,6 @@ static int bpf_size_to_x86_bytes(int bpf_size) /* Pick a register outside of BPF range for JIT internal work */ #define AUX_REG (MAX_BPF_JIT_REG + 1) -#define X86_REG_R9 (MAX_BPF_JIT_REG + 2) /* * The following table maps BPF registers to x86-64 registers. @@ -109,8 +104,8 @@ static int bpf_size_to_x86_bytes(int bpf_size) * register in load/store instructions, it always needs an * extra byte of encoding and is callee saved. * - * x86-64 register R9 is not used by BPF programs, but can be used by BPF - * trampoline. x86-64 register R10 is used for blinding (if enabled). + * Also x86-64 register R9 is unused. x86-64 register R10 is + * used for blinding (if enabled). */ static const int reg2hex[] = { [BPF_REG_0] = 0, /* RAX */ @@ -126,20 +121,6 @@ static const int reg2hex[] = { [BPF_REG_FP] = 5, /* RBP readonly */ [BPF_REG_AX] = 2, /* R10 temp register */ [AUX_REG] = 3, /* R11 temp register */ - [X86_REG_R9] = 1, /* R9 register, 6th function argument */ -}; - -static const int reg2pt_regs[] = { - [BPF_REG_0] = offsetof(struct pt_regs, ax), - [BPF_REG_1] = offsetof(struct pt_regs, di), - [BPF_REG_2] = offsetof(struct pt_regs, si), - [BPF_REG_3] = offsetof(struct pt_regs, dx), - [BPF_REG_4] = offsetof(struct pt_regs, cx), - [BPF_REG_5] = offsetof(struct pt_regs, r8), - [BPF_REG_6] = offsetof(struct pt_regs, bx), - [BPF_REG_7] = offsetof(struct pt_regs, r13), - [BPF_REG_8] = offsetof(struct pt_regs, r14), - [BPF_REG_9] = offsetof(struct pt_regs, r15), }; /* @@ -154,7 +135,6 @@ static bool is_ereg(u32 reg) BIT(BPF_REG_7) | BIT(BPF_REG_8) | BIT(BPF_REG_9) | - BIT(X86_REG_R9) | BIT(BPF_REG_AX)); } @@ -219,174 +199,33 @@ struct jit_context { #define BPF_MAX_INSN_SIZE 128 #define BPF_INSN_SAFETY 64 -/* Number of bytes emit_patch() needs to generate instructions */ -#define X86_PATCH_SIZE 5 -/* Number of bytes that will be skipped on tailcall */ -#define X86_TAIL_CALL_OFFSET 11 - -static void push_callee_regs(u8 **pprog, bool *callee_regs_used) -{ - u8 *prog = *pprog; - int cnt = 0; - - if (callee_regs_used[0]) - EMIT1(0x53); /* push rbx */ - if (callee_regs_used[1]) - EMIT2(0x41, 0x55); /* push r13 */ - if (callee_regs_used[2]) - EMIT2(0x41, 0x56); /* push r14 */ - if (callee_regs_used[3]) - EMIT2(0x41, 0x57); /* push r15 */ - *pprog = prog; -} - -static void pop_callee_regs(u8 **pprog, bool *callee_regs_used) -{ - u8 *prog = *pprog; - int cnt = 0; - - if (callee_regs_used[3]) - EMIT2(0x41, 0x5F); /* pop r15 */ - if (callee_regs_used[2]) - EMIT2(0x41, 0x5E); /* pop r14 */ - if (callee_regs_used[1]) - EMIT2(0x41, 0x5D); /* pop r13 */ - if (callee_regs_used[0]) - EMIT1(0x5B); /* pop rbx */ - *pprog = prog; -} +#define PROLOGUE_SIZE 20 /* - * Emit x86-64 prologue code for BPF program. - * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes - * while jumping to another program + * Emit x86-64 prologue code for BPF program and check its size. + * bpf_tail_call helper will skip it while jumping into another program */ -static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf, - bool tail_call_reachable, bool is_subprog) +static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf) { u8 *prog = *pprog; - int cnt = X86_PATCH_SIZE; + int cnt = 0; - /* BPF trampoline can be made to work without these nops, - * but let's waste 5 bytes for now and optimize later - */ - memcpy(prog, ideal_nops[NOP_ATOMIC5], cnt); - prog += cnt; - if (!ebpf_from_cbpf) { - if (tail_call_reachable && !is_subprog) - EMIT2(0x31, 0xC0); /* xor eax, eax */ - else - EMIT2(0x66, 0x90); /* nop2 */ - } EMIT1(0x55); /* push rbp */ EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */ /* sub rsp, rounded_stack_depth */ EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8)); - if (tail_call_reachable) - EMIT1(0x50); /* push rax */ + EMIT1(0x53); /* push rbx */ + EMIT2(0x41, 0x55); /* push r13 */ + EMIT2(0x41, 0x56); /* push r14 */ + EMIT2(0x41, 0x57); /* push r15 */ + if (!ebpf_from_cbpf) { + /* zero init tail_call_cnt */ + EMIT2(0x6a, 0x00); + BUILD_BUG_ON(cnt != PROLOGUE_SIZE); + } *pprog = prog; } -static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode) -{ - u8 *prog = *pprog; - int cnt = 0; - s64 offset; - - offset = func - (ip + X86_PATCH_SIZE); - if (!is_simm32(offset)) { - pr_err("Target call %p is out of range\n", func); - return -ERANGE; - } - EMIT1_off32(opcode, offset); - *pprog = prog; - return 0; -} - -static int emit_call(u8 **pprog, void *func, void *ip) -{ - return emit_patch(pprog, func, ip, 0xE8); -} - -static int emit_jump(u8 **pprog, void *func, void *ip) -{ - return emit_patch(pprog, func, ip, 0xE9); -} - -static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t, - void *old_addr, void *new_addr, - const bool text_live) -{ - const u8 *nop_insn = ideal_nops[NOP_ATOMIC5]; - u8 old_insn[X86_PATCH_SIZE]; - u8 new_insn[X86_PATCH_SIZE]; - u8 *prog; - int ret; - - memcpy(old_insn, nop_insn, X86_PATCH_SIZE); - if (old_addr) { - prog = old_insn; - ret = t == BPF_MOD_CALL ? - emit_call(&prog, old_addr, ip) : - emit_jump(&prog, old_addr, ip); - if (ret) - return ret; - } - - memcpy(new_insn, nop_insn, X86_PATCH_SIZE); - if (new_addr) { - prog = new_insn; - ret = t == BPF_MOD_CALL ? - emit_call(&prog, new_addr, ip) : - emit_jump(&prog, new_addr, ip); - if (ret) - return ret; - } - - ret = -EBUSY; - mutex_lock(&text_mutex); - if (memcmp(ip, old_insn, X86_PATCH_SIZE)) - goto out; - ret = 1; - if (memcmp(ip, new_insn, X86_PATCH_SIZE)) { - if (text_live) - text_poke_bp(ip, new_insn, X86_PATCH_SIZE, NULL); - else - memcpy(ip, new_insn, X86_PATCH_SIZE); - ret = 0; - } -out: - mutex_unlock(&text_mutex); - return ret; -} - -int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t, - void *old_addr, void *new_addr) -{ - if (!is_kernel_text((long)ip) && - !is_bpf_text_address((long)ip)) - /* BPF poking in modules is not supported */ - return -EINVAL; - - return __bpf_arch_text_poke(ip, t, old_addr, new_addr, true); -} - -static int get_pop_bytes(bool *callee_regs_used) -{ - int bytes = 0; - - if (callee_regs_used[3]) - bytes += 2; - if (callee_regs_used[2]) - bytes += 2; - if (callee_regs_used[1]) - bytes += 2; - if (callee_regs_used[0]) - bytes += 1; - - return bytes; -} - /* * Generate the following code: * @@ -401,26 +240,12 @@ static int get_pop_bytes(bool *callee_regs_used) * goto *(prog->bpf_func + prologue_size); * out: */ -static void emit_bpf_tail_call_indirect(u8 **pprog, bool *callee_regs_used, - u32 stack_depth) +static void emit_bpf_tail_call(u8 **pprog) { - int tcc_off = -4 - round_up(stack_depth, 8); u8 *prog = *pprog; - int pop_bytes = 0; - int off1 = 49; - int off2 = 38; - int off3 = 16; + int label1, label2, label3; int cnt = 0; - /* count the additional bytes used for popping callee regs from stack - * that need to be taken into account for each of the offsets that - * are used for bailing out of the tail call - */ - pop_bytes = get_pop_bytes(callee_regs_used); - off1 += pop_bytes; - off2 += pop_bytes; - off3 += pop_bytes; - /* * rdi - pointer to ctx * rsi - pointer to bpf_array @@ -434,160 +259,54 @@ static void emit_bpf_tail_call_indirect(u8 **pprog, bool *callee_regs_used, EMIT2(0x89, 0xD2); /* mov edx, edx */ EMIT3(0x39, 0x56, /* cmp dword ptr [rsi + 16], edx */ offsetof(struct bpf_array, map.max_entries)); -#define OFFSET1 (off1 + RETPOLINE_RCX_BPF_JIT_SIZE) /* Number of bytes to jump */ +#define OFFSET1 (41 + RETPOLINE_RAX_BPF_JIT_SIZE) /* Number of bytes to jump */ EMIT2(X86_JBE, OFFSET1); /* jbe out */ + label1 = cnt; /* * if (tail_call_cnt > MAX_TAIL_CALL_CNT) * goto out; */ - EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */ + EMIT2_off32(0x8B, 0x85, -36 - MAX_BPF_STACK); /* mov eax, dword ptr [rbp - 548] */ EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */ -#define OFFSET2 (off2 + RETPOLINE_RCX_BPF_JIT_SIZE) +#define OFFSET2 (30 + RETPOLINE_RAX_BPF_JIT_SIZE) EMIT2(X86_JA, OFFSET2); /* ja out */ + label2 = cnt; EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */ - EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */ + EMIT2_off32(0x89, 0x85, -36 - MAX_BPF_STACK); /* mov dword ptr [rbp -548], eax */ /* prog = array->ptrs[index]; */ - EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6, /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */ + EMIT4_off32(0x48, 0x8B, 0x84, 0xD6, /* mov rax, [rsi + rdx * 8 + offsetof(...)] */ offsetof(struct bpf_array, ptrs)); /* * if (prog == NULL) * goto out; */ - EMIT3(0x48, 0x85, 0xC9); /* test rcx,rcx */ -#define OFFSET3 (off3 + RETPOLINE_RCX_BPF_JIT_SIZE) + EMIT3(0x48, 0x85, 0xC0); /* test rax,rax */ +#define OFFSET3 (8 + RETPOLINE_RAX_BPF_JIT_SIZE) EMIT2(X86_JE, OFFSET3); /* je out */ + label3 = cnt; - *pprog = prog; - pop_callee_regs(pprog, callee_regs_used); - prog = *pprog; - - EMIT1(0x58); /* pop rax */ - EMIT3_off32(0x48, 0x81, 0xC4, /* add rsp, sd */ - round_up(stack_depth, 8)); - - /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */ - EMIT4(0x48, 0x8B, 0x49, /* mov rcx, qword ptr [rcx + 32] */ + /* goto *(prog->bpf_func + prologue_size); */ + EMIT4(0x48, 0x8B, 0x40, /* mov rax, qword ptr [rax + 32] */ offsetof(struct bpf_prog, bpf_func)); - EMIT4(0x48, 0x83, 0xC1, /* add rcx, X86_TAIL_CALL_OFFSET */ - X86_TAIL_CALL_OFFSET); + EMIT4(0x48, 0x83, 0xC0, PROLOGUE_SIZE); /* add rax, prologue_size */ + /* - * Now we're ready to jump into next BPF program + * Wow we're ready to jump into next BPF program * rdi == ctx (1st arg) - * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET + * rax == prog->bpf_func + prologue_size */ - RETPOLINE_RCX_BPF_JIT(); + RETPOLINE_RAX_BPF_JIT(); /* out: */ + BUILD_BUG_ON(cnt - label1 != OFFSET1); + BUILD_BUG_ON(cnt - label2 != OFFSET2); + BUILD_BUG_ON(cnt - label3 != OFFSET3); *pprog = prog; } -static void emit_bpf_tail_call_direct(struct bpf_jit_poke_descriptor *poke, - u8 **pprog, int addr, u8 *image, - bool *callee_regs_used, u32 stack_depth) -{ - int tcc_off = -4 - round_up(stack_depth, 8); - u8 *prog = *pprog; - int pop_bytes = 0; - int off1 = 27; - int poke_off; - int cnt = 0; - - /* count the additional bytes used for popping callee regs to stack - * that need to be taken into account for jump offset that is used for - * bailing out from of the tail call when limit is reached - */ - pop_bytes = get_pop_bytes(callee_regs_used); - off1 += pop_bytes; - - /* - * total bytes for: - * - nop5/ jmpq $off - * - pop callee regs - * - sub rsp, $val - * - pop rax - */ - poke_off = X86_PATCH_SIZE + pop_bytes + 7 + 1; - - /* - * if (tail_call_cnt > MAX_TAIL_CALL_CNT) - * goto out; - */ - EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */ - EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */ - EMIT2(X86_JA, off1); /* ja out */ - EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */ - EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */ - - poke->tailcall_bypass = image + (addr - poke_off - X86_PATCH_SIZE); - poke->adj_off = X86_TAIL_CALL_OFFSET; - poke->tailcall_target = image + (addr - X86_PATCH_SIZE); - poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE; - - emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE, - poke->tailcall_bypass); - - *pprog = prog; - pop_callee_regs(pprog, callee_regs_used); - prog = *pprog; - EMIT1(0x58); /* pop rax */ - EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8)); - - memcpy(prog, ideal_nops[NOP_ATOMIC5], X86_PATCH_SIZE); - prog += X86_PATCH_SIZE; - /* out: */ - - *pprog = prog; -} - -static void bpf_tail_call_direct_fixup(struct bpf_prog *prog) -{ - struct bpf_jit_poke_descriptor *poke; - struct bpf_array *array; - struct bpf_prog *target; - int i, ret; - - for (i = 0; i < prog->aux->size_poke_tab; i++) { - poke = &prog->aux->poke_tab[i]; - if (poke->aux && poke->aux != prog->aux) - continue; - - WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable)); - - if (poke->reason != BPF_POKE_REASON_TAIL_CALL) - continue; - - array = container_of(poke->tail_call.map, struct bpf_array, map); - mutex_lock(&array->aux->poke_mutex); - target = array->ptrs[poke->tail_call.key]; - if (target) { - /* Plain memcpy is used when image is not live yet - * and still not locked as read-only. Once poke - * location is active (poke->tailcall_target_stable), - * any parallel bpf_arch_text_poke() might occur - * still on the read-write image until we finally - * locked it as read-only. Both modifications on - * the given image are under text_mutex to avoid - * interference. - */ - ret = __bpf_arch_text_poke(poke->tailcall_target, - BPF_MOD_JUMP, NULL, - (u8 *)target->bpf_func + - poke->adj_off, false); - BUG_ON(ret < 0); - ret = __bpf_arch_text_poke(poke->tailcall_bypass, - BPF_MOD_JUMP, - (u8 *)poke->tailcall_target + - X86_PATCH_SIZE, NULL, false); - BUG_ON(ret < 0); - } - WRITE_ONCE(poke->tailcall_target_stable, true); - mutex_unlock(&array->aux->poke_mutex); - } -} - static void emit_mov_imm32(u8 **pprog, bool sign_propagate, u32 dst_reg, const u32 imm32) { @@ -671,139 +390,19 @@ static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg) *pprog = prog; } -/* LDX: dst_reg = *(u8*)(src_reg + off) */ -static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) -{ - u8 *prog = *pprog; - int cnt = 0; - - switch (size) { - case BPF_B: - /* Emit 'movzx rax, byte ptr [rax + off]' */ - EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6); - break; - case BPF_H: - /* Emit 'movzx rax, word ptr [rax + off]' */ - EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7); - break; - case BPF_W: - /* Emit 'mov eax, dword ptr [rax+0x14]' */ - if (is_ereg(dst_reg) || is_ereg(src_reg)) - EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B); - else - EMIT1(0x8B); - break; - case BPF_DW: - /* Emit 'mov rax, qword ptr [rax+0x14]' */ - EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B); - break; - } - /* - * If insn->off == 0 we can save one extra byte, but - * special case of x86 R13 which always needs an offset - * is not worth the hassle - */ - if (is_imm8(off)) - EMIT2(add_2reg(0x40, src_reg, dst_reg), off); - else - EMIT1_off32(add_2reg(0x80, src_reg, dst_reg), off); - *pprog = prog; -} - -/* STX: *(u8*)(dst_reg + off) = src_reg */ -static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) -{ - u8 *prog = *pprog; - int cnt = 0; - - switch (size) { - case BPF_B: - /* Emit 'mov byte ptr [rax + off], al' */ - if (is_ereg(dst_reg) || is_ereg(src_reg) || - /* We have to add extra byte for x86 SIL, DIL regs */ - src_reg == BPF_REG_1 || src_reg == BPF_REG_2) - EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88); - else - EMIT1(0x88); - break; - case BPF_H: - if (is_ereg(dst_reg) || is_ereg(src_reg)) - EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89); - else - EMIT2(0x66, 0x89); - break; - case BPF_W: - if (is_ereg(dst_reg) || is_ereg(src_reg)) - EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89); - else - EMIT1(0x89); - break; - case BPF_DW: - EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89); - break; - } - if (is_imm8(off)) - EMIT2(add_2reg(0x40, dst_reg, src_reg), off); - else - EMIT1_off32(add_2reg(0x80, dst_reg, src_reg), off); - *pprog = prog; -} - -static bool ex_handler_bpf(const struct exception_table_entry *x, - struct pt_regs *regs, int trapnr, - unsigned long error_code, unsigned long fault_addr) -{ - u32 reg = x->fixup >> 8; - - /* jump over faulting load and clear dest register */ - *(unsigned long *)((void *)regs + reg) = 0; - regs->ip += x->fixup & 0xff; - return true; -} - -static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt, - bool *regs_used, bool *tail_call_seen) -{ - int i; - - for (i = 1; i <= insn_cnt; i++, insn++) { - if (insn->code == (BPF_JMP | BPF_TAIL_CALL)) - *tail_call_seen = true; - if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6) - regs_used[0] = true; - if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7) - regs_used[1] = true; - if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8) - regs_used[2] = true; - if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9) - regs_used[3] = true; - } -} - static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, int oldproglen, struct jit_context *ctx) { - bool tail_call_reachable = bpf_prog->aux->tail_call_reachable; struct bpf_insn *insn = bpf_prog->insnsi; - bool callee_regs_used[4] = {}; int insn_cnt = bpf_prog->len; - bool tail_call_seen = false; bool seen_exit = false; u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY]; - int i, cnt = 0, excnt = 0; + int i, cnt = 0; int proglen = 0; u8 *prog = temp; - detect_reg_usage(insn, insn_cnt, callee_regs_used, - &tail_call_seen); - - /* tail call's presence in current prog implies it is reachable */ - tail_call_reachable |= tail_call_seen; - emit_prologue(&prog, bpf_prog->aux->stack_depth, - bpf_prog_was_classic(bpf_prog), tail_call_reachable, - bpf_prog->aux->func_idx != 0); - push_callee_regs(&prog, callee_regs_used); + bpf_prog_was_classic(bpf_prog)); addrs[0] = prog - temp; for (i = 1; i <= insn_cnt; i++, insn++) { @@ -1168,64 +767,63 @@ st: if (is_imm8(insn->off)) /* STX: *(u8*)(dst_reg + off) = src_reg */ case BPF_STX | BPF_MEM | BPF_B: + /* Emit 'mov byte ptr [rax + off], al' */ + if (is_ereg(dst_reg) || is_ereg_8l(src_reg)) + /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */ + EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88); + else + EMIT1(0x88); + goto stx; case BPF_STX | BPF_MEM | BPF_H: + if (is_ereg(dst_reg) || is_ereg(src_reg)) + EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89); + else + EMIT2(0x66, 0x89); + goto stx; case BPF_STX | BPF_MEM | BPF_W: + if (is_ereg(dst_reg) || is_ereg(src_reg)) + EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89); + else + EMIT1(0x89); + goto stx; case BPF_STX | BPF_MEM | BPF_DW: - emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); + EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89); +stx: if (is_imm8(insn->off)) + EMIT2(add_2reg(0x40, dst_reg, src_reg), insn->off); + else + EMIT1_off32(add_2reg(0x80, dst_reg, src_reg), + insn->off); break; /* LDX: dst_reg = *(u8*)(src_reg + off) */ case BPF_LDX | BPF_MEM | BPF_B: - case BPF_LDX | BPF_PROBE_MEM | BPF_B: + /* Emit 'movzx rax, byte ptr [rax + off]' */ + EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6); + goto ldx; case BPF_LDX | BPF_MEM | BPF_H: - case BPF_LDX | BPF_PROBE_MEM | BPF_H: + /* Emit 'movzx rax, word ptr [rax + off]' */ + EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7); + goto ldx; case BPF_LDX | BPF_MEM | BPF_W: - case BPF_LDX | BPF_PROBE_MEM | BPF_W: + /* Emit 'mov eax, dword ptr [rax+0x14]' */ + if (is_ereg(dst_reg) || is_ereg(src_reg)) + EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B); + else + EMIT1(0x8B); + goto ldx; case BPF_LDX | BPF_MEM | BPF_DW: - case BPF_LDX | BPF_PROBE_MEM | BPF_DW: - emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); - if (BPF_MODE(insn->code) == BPF_PROBE_MEM) { - struct exception_table_entry *ex; - u8 *_insn = image + proglen; - s64 delta; - - if (!bpf_prog->aux->extable) - break; - - if (excnt >= bpf_prog->aux->num_exentries) { - pr_err("ex gen bug\n"); - return -EFAULT; - } - ex = &bpf_prog->aux->extable[excnt++]; - - delta = _insn - (u8 *)&ex->insn; - if (!is_simm32(delta)) { - pr_err("extable->insn doesn't fit into 32-bit\n"); - return -EFAULT; - } - ex->insn = delta; - - delta = (u8 *)ex_handler_bpf - (u8 *)&ex->handler; - if (!is_simm32(delta)) { - pr_err("extable->handler doesn't fit into 32-bit\n"); - return -EFAULT; - } - ex->handler = delta; - - if (dst_reg > BPF_REG_9) { - pr_err("verifier error\n"); - return -EFAULT; - } - /* - * Compute size of x86 insn and its target dest x86 register. - * ex_handler_bpf() will use lower 8 bits to adjust - * pt_regs->ip to jump over this x86 instruction - * and upper bits to figure out which pt_regs to zero out. - * End result: x86 insn "mov rbx, qword ptr [rax+0x14]" - * of 4 bytes will be ignored and rbx will be zero inited. - */ - ex->fixup = (prog - temp) | (reg2pt_regs[dst_reg] << 8); - } + /* Emit 'mov rax, qword ptr [rax+0x14]' */ + EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B); +ldx: /* + * If insn->off == 0 we can save one extra byte, but + * special case of x86 R13 which always needs an offset + * is not worth the hassle + */ + if (is_imm8(insn->off)) + EMIT2(add_2reg(0x40, src_reg, dst_reg), insn->off); + else + EMIT1_off32(add_2reg(0x80, src_reg, dst_reg), + insn->off); break; /* STX XADD: lock *(u32*)(dst_reg + off) += src_reg */ @@ -1248,27 +846,17 @@ xadd: if (is_imm8(insn->off)) /* call */ case BPF_JMP | BPF_CALL: func = (u8 *) __bpf_call_base + imm32; - if (tail_call_reachable) { - EMIT3_off32(0x48, 0x8B, 0x85, - -(bpf_prog->aux->stack_depth + 8)); - if (!imm32 || emit_call(&prog, func, image + addrs[i - 1] + 7)) - return -EINVAL; - } else { - if (!imm32 || emit_call(&prog, func, image + addrs[i - 1])) - return -EINVAL; + jmp_offset = func - (image + addrs[i]); + if (!imm32 || !is_simm32(jmp_offset)) { + pr_err("unsupported BPF func %d addr %p image %p\n", + imm32, func, image); + return -EINVAL; } + EMIT1_off32(0xE8, jmp_offset); break; case BPF_JMP | BPF_TAIL_CALL: - if (imm32) - emit_bpf_tail_call_direct(&bpf_prog->aux->poke_tab[imm32 - 1], - &prog, addrs[i], image, - callee_regs_used, - bpf_prog->aux->stack_depth); - else - emit_bpf_tail_call_indirect(&prog, - callee_regs_used, - bpf_prog->aux->stack_depth); + emit_bpf_tail_call(&prog); break; /* cond jump */ @@ -1340,16 +928,6 @@ xadd: if (is_imm8(insn->off)) case BPF_JMP32 | BPF_JSLT | BPF_K: case BPF_JMP32 | BPF_JSGE | BPF_K: case BPF_JMP32 | BPF_JSLE | BPF_K: - /* test dst_reg, dst_reg to save one extra byte */ - if (imm32 == 0) { - if (BPF_CLASS(insn->code) == BPF_JMP) - EMIT1(add_2mod(0x48, dst_reg, dst_reg)); - else if (is_ereg(dst_reg)) - EMIT1(add_2mod(0x40, dst_reg, dst_reg)); - EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg)); - goto emit_cond_jmp; - } - /* cmp dst_reg, imm8/32 */ if (BPF_CLASS(insn->code) == BPF_JMP) EMIT1(add_1mod(0x48, dst_reg)); @@ -1451,9 +1029,12 @@ emit_jmp: seen_exit = true; /* Update cleanup_addr */ ctx->cleanup_addr = proglen; - pop_callee_regs(&prog, callee_regs_used); - if (tail_call_reachable) - EMIT1(0x59); /* pop rcx, get rid of tail_call_cnt */ + if (!bpf_prog_was_classic(bpf_prog)) + EMIT1(0x5B); /* get rid of tail_call_cnt */ + EMIT2(0x41, 0x5F); /* pop r15 */ + EMIT2(0x41, 0x5E); /* pop r14 */ + EMIT2(0x41, 0x5D); /* pop r13 */ + EMIT1(0x5B); /* pop rbx */ EMIT1(0xC9); /* leave */ EMIT1(0xC3); /* ret */ break; @@ -1495,588 +1076,9 @@ emit_jmp: addrs[i] = proglen; prog = temp; } - - if (image && excnt != bpf_prog->aux->num_exentries) { - pr_err("extable is not populated\n"); - return -EFAULT; - } return proglen; } -static void save_regs(const struct btf_func_model *m, u8 **prog, int nr_args, - int stack_size) -{ - int i; - /* Store function arguments to stack. - * For a function that accepts two pointers the sequence will be: - * mov QWORD PTR [rbp-0x10],rdi - * mov QWORD PTR [rbp-0x8],rsi - */ - for (i = 0; i < min(nr_args, 6); i++) - emit_stx(prog, bytes_to_bpf_size(m->arg_size[i]), - BPF_REG_FP, - i == 5 ? X86_REG_R9 : BPF_REG_1 + i, - -(stack_size - i * 8)); -} - -static void restore_regs(const struct btf_func_model *m, u8 **prog, int nr_args, - int stack_size) -{ - int i; - - /* Restore function arguments from stack. - * For a function that accepts two pointers the sequence will be: - * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10] - * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8] - */ - for (i = 0; i < min(nr_args, 6); i++) - emit_ldx(prog, bytes_to_bpf_size(m->arg_size[i]), - i == 5 ? X86_REG_R9 : BPF_REG_1 + i, - BPF_REG_FP, - -(stack_size - i * 8)); -} - -static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog, - struct bpf_prog *p, int stack_size, bool save_ret) -{ - u8 *prog = *pprog; - int cnt = 0; - - if (p->aux->sleepable) { - if (emit_call(&prog, __bpf_prog_enter_sleepable, prog)) - return -EINVAL; - } else { - if (emit_call(&prog, __bpf_prog_enter, prog)) - return -EINVAL; - /* remember prog start time returned by __bpf_prog_enter */ - emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0); - } - - /* arg1: lea rdi, [rbp - stack_size] */ - EMIT4(0x48, 0x8D, 0x7D, -stack_size); - /* arg2: progs[i]->insnsi for interpreter */ - if (!p->jited) - emit_mov_imm64(&prog, BPF_REG_2, - (long) p->insnsi >> 32, - (u32) (long) p->insnsi); - /* call JITed bpf program or interpreter */ - if (emit_call(&prog, p->bpf_func, prog)) - return -EINVAL; - - /* - * BPF_TRAMP_MODIFY_RETURN trampolines can modify the return - * of the previous call which is then passed on the stack to - * the next BPF program. - * - * BPF_TRAMP_FENTRY trampoline may need to return the return - * value of BPF_PROG_TYPE_STRUCT_OPS prog. - */ - if (save_ret) - emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); - - if (p->aux->sleepable) { - if (emit_call(&prog, __bpf_prog_exit_sleepable, prog)) - return -EINVAL; - } else { - /* arg1: mov rdi, progs[i] */ - emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, - (u32) (long) p); - /* arg2: mov rsi, rbx <- start time in nsec */ - emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6); - if (emit_call(&prog, __bpf_prog_exit, prog)) - return -EINVAL; - } - - *pprog = prog; - return 0; -} - -static void emit_nops(u8 **pprog, unsigned int len) -{ - unsigned int i, noplen; - u8 *prog = *pprog; - int cnt = 0; - - while (len > 0) { - noplen = len; - - if (noplen > ASM_NOP_MAX) - noplen = ASM_NOP_MAX; - - for (i = 0; i < noplen; i++) - EMIT1(ideal_nops[noplen][i]); - len -= noplen; - } - - *pprog = prog; -} - -static void emit_align(u8 **pprog, u32 align) -{ - u8 *target, *prog = *pprog; - - target = PTR_ALIGN(prog, align); - if (target != prog) - emit_nops(&prog, target - prog); - - *pprog = prog; -} - -static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond) -{ - u8 *prog = *pprog; - int cnt = 0; - s64 offset; - - offset = func - (ip + 2 + 4); - if (!is_simm32(offset)) { - pr_err("Target %p is out of range\n", func); - return -EINVAL; - } - EMIT2_off32(0x0F, jmp_cond + 0x10, offset); - *pprog = prog; - return 0; -} - -static int emit_mod_ret_check_imm8(u8 **pprog, int value) -{ - u8 *prog = *pprog; - int cnt = 0; - - if (!is_imm8(value)) - return -EINVAL; - - if (value == 0) - EMIT2(0x85, add_2reg(0xC0, BPF_REG_0, BPF_REG_0)); - else - EMIT3(0x83, add_1reg(0xF8, BPF_REG_0), value); - - *pprog = prog; - return 0; -} - -static int invoke_bpf(const struct btf_func_model *m, u8 **pprog, - struct bpf_tramp_progs *tp, int stack_size, - bool save_ret) -{ - u8 *prog = *pprog; - int cnt = 0, i; - - for (i = 0; i < tp->nr_progs; i++) { - if (invoke_bpf_prog(m, &prog, tp->progs[i], stack_size, - save_ret)) - return -EINVAL; - } - *pprog = prog; - return 0; -} - -static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog, - struct bpf_tramp_progs *tp, int stack_size, - u8 **branches) -{ - u8 *prog = *pprog; - int i; - - /* The first fmod_ret program will receive a garbage return value. - * Set this to 0 to avoid confusing the program. - */ - emit_mov_imm32(&prog, false, BPF_REG_0, 0); - emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); - for (i = 0; i < tp->nr_progs; i++) { - if (invoke_bpf_prog(m, &prog, tp->progs[i], stack_size, true)) - return -EINVAL; - - /* Generate a branch: - * - * if (ret != 0) - * goto do_fexit; - * - * If needed this can be extended to any integer value which can - * be passed by user-space when the program is loaded. - */ - if (emit_mod_ret_check_imm8(&prog, 0)) - return -EINVAL; - - /* Save the location of the branch and Generate 6 nops - * (4 bytes for an offset and 2 bytes for the jump) These nops - * are replaced with a conditional jump once do_fexit (i.e. the - * start of the fexit invocation) is finalized. - */ - branches[i] = prog; - emit_nops(&prog, 4 + 2); - } - - *pprog = prog; - return 0; -} - -static bool is_valid_bpf_tramp_flags(unsigned int flags) -{ - if ((flags & BPF_TRAMP_F_RESTORE_REGS) && - (flags & BPF_TRAMP_F_SKIP_FRAME)) - return false; - - /* - * BPF_TRAMP_F_RET_FENTRY_RET is only used by bpf_struct_ops, - * and it must be used alone. - */ - if ((flags & BPF_TRAMP_F_RET_FENTRY_RET) && - (flags & ~BPF_TRAMP_F_RET_FENTRY_RET)) - return false; - - return true; -} - -/* Example: - * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev); - * its 'struct btf_func_model' will be nr_args=2 - * The assembly code when eth_type_trans is executing after trampoline: - * - * push rbp - * mov rbp, rsp - * sub rsp, 16 // space for skb and dev - * push rbx // temp regs to pass start time - * mov qword ptr [rbp - 16], rdi // save skb pointer to stack - * mov qword ptr [rbp - 8], rsi // save dev pointer to stack - * call __bpf_prog_enter // rcu_read_lock and preempt_disable - * mov rbx, rax // remember start time in bpf stats are enabled - * lea rdi, [rbp - 16] // R1==ctx of bpf prog - * call addr_of_jited_FENTRY_prog - * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off - * mov rsi, rbx // prog start time - * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math - * mov rdi, qword ptr [rbp - 16] // restore skb pointer from stack - * mov rsi, qword ptr [rbp - 8] // restore dev pointer from stack - * pop rbx - * leave - * ret - * - * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be - * replaced with 'call generated_bpf_trampoline'. When it returns - * eth_type_trans will continue executing with original skb and dev pointers. - * - * The assembly code when eth_type_trans is called from trampoline: - * - * push rbp - * mov rbp, rsp - * sub rsp, 24 // space for skb, dev, return value - * push rbx // temp regs to pass start time - * mov qword ptr [rbp - 24], rdi // save skb pointer to stack - * mov qword ptr [rbp - 16], rsi // save dev pointer to stack - * call __bpf_prog_enter // rcu_read_lock and preempt_disable - * mov rbx, rax // remember start time if bpf stats are enabled - * lea rdi, [rbp - 24] // R1==ctx of bpf prog - * call addr_of_jited_FENTRY_prog // bpf prog can access skb and dev - * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off - * mov rsi, rbx // prog start time - * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math - * mov rdi, qword ptr [rbp - 24] // restore skb pointer from stack - * mov rsi, qword ptr [rbp - 16] // restore dev pointer from stack - * call eth_type_trans+5 // execute body of eth_type_trans - * mov qword ptr [rbp - 8], rax // save return value - * call __bpf_prog_enter // rcu_read_lock and preempt_disable - * mov rbx, rax // remember start time in bpf stats are enabled - * lea rdi, [rbp - 24] // R1==ctx of bpf prog - * call addr_of_jited_FEXIT_prog // bpf prog can access skb, dev, return value - * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off - * mov rsi, rbx // prog start time - * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math - * mov rax, qword ptr [rbp - 8] // restore eth_type_trans's return value - * pop rbx - * leave - * add rsp, 8 // skip eth_type_trans's frame - * ret // return to its caller - */ -int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end, - const struct btf_func_model *m, u32 flags, - struct bpf_tramp_progs *tprogs, - void *orig_call) -{ - int ret, i, cnt = 0, nr_args = m->nr_args; - int stack_size = nr_args * 8; - struct bpf_tramp_progs *fentry = &tprogs[BPF_TRAMP_FENTRY]; - struct bpf_tramp_progs *fexit = &tprogs[BPF_TRAMP_FEXIT]; - struct bpf_tramp_progs *fmod_ret = &tprogs[BPF_TRAMP_MODIFY_RETURN]; - u8 **branches = NULL; - u8 *prog; - bool save_ret; - - /* x86-64 supports up to 6 arguments. 7+ can be added in the future */ - if (nr_args > 6) - return -ENOTSUPP; - - if (!is_valid_bpf_tramp_flags(flags)) - return -EINVAL; - - /* room for return value of orig_call or fentry prog */ - save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET); - if (save_ret) - stack_size += 8; - - if (flags & BPF_TRAMP_F_SKIP_FRAME) - /* skip patched call instruction and point orig_call to actual - * body of the kernel function. - */ - orig_call += X86_PATCH_SIZE; - - prog = image; - - EMIT1(0x55); /* push rbp */ - EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */ - EMIT4(0x48, 0x83, 0xEC, stack_size); /* sub rsp, stack_size */ - EMIT1(0x53); /* push rbx */ - - save_regs(m, &prog, nr_args, stack_size); - - if (flags & BPF_TRAMP_F_CALL_ORIG) { - /* arg1: mov rdi, im */ - emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im); - if (emit_call(&prog, __bpf_tramp_enter, prog)) { - ret = -EINVAL; - goto cleanup; - } - } - - if (fentry->nr_progs) - if (invoke_bpf(m, &prog, fentry, stack_size, - flags & BPF_TRAMP_F_RET_FENTRY_RET)) - return -EINVAL; - - if (fmod_ret->nr_progs) { - branches = kcalloc(fmod_ret->nr_progs, sizeof(u8 *), - GFP_KERNEL); - if (!branches) - return -ENOMEM; - - if (invoke_bpf_mod_ret(m, &prog, fmod_ret, stack_size, - branches)) { - ret = -EINVAL; - goto cleanup; - } - } - - if (flags & BPF_TRAMP_F_CALL_ORIG) { - restore_regs(m, &prog, nr_args, stack_size); - - /* call original function */ - if (emit_call(&prog, orig_call, prog)) { - ret = -EINVAL; - goto cleanup; - } - /* remember return value in a stack for bpf prog to access */ - emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); - im->ip_after_call = prog; - emit_nops(&prog, 5); - } - - if (fmod_ret->nr_progs) { - /* From Intel 64 and IA-32 Architectures Optimization - * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler - * Coding Rule 11: All branch targets should be 16-byte - * aligned. - */ - emit_align(&prog, 16); - /* Update the branches saved in invoke_bpf_mod_ret with the - * aligned address of do_fexit. - */ - for (i = 0; i < fmod_ret->nr_progs; i++) - emit_cond_near_jump(&branches[i], prog, branches[i], - X86_JNE); - } - - if (fexit->nr_progs) - if (invoke_bpf(m, &prog, fexit, stack_size, false)) { - ret = -EINVAL; - goto cleanup; - } - - if (flags & BPF_TRAMP_F_RESTORE_REGS) - restore_regs(m, &prog, nr_args, stack_size); - - /* This needs to be done regardless. If there were fmod_ret programs, - * the return value is only updated on the stack and still needs to be - * restored to R0. - */ - if (flags & BPF_TRAMP_F_CALL_ORIG) { - im->ip_epilogue = prog; - /* arg1: mov rdi, im */ - emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im); - if (emit_call(&prog, __bpf_tramp_exit, prog)) { - ret = -EINVAL; - goto cleanup; - } - } - /* restore return value of orig_call or fentry prog back into RAX */ - if (save_ret) - emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8); - - EMIT1(0x5B); /* pop rbx */ - EMIT1(0xC9); /* leave */ - if (flags & BPF_TRAMP_F_SKIP_FRAME) - /* skip our return address and return to parent */ - EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */ - EMIT1(0xC3); /* ret */ - /* Make sure the trampoline generation logic doesn't overflow */ - if (WARN_ON_ONCE(prog > (u8 *)image_end - BPF_INSN_SAFETY)) { - ret = -EFAULT; - goto cleanup; - } - ret = prog - (u8 *)image; - -cleanup: - kfree(branches); - return ret; -} - -static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond) -{ - u8 *prog = *pprog; - int cnt = 0; - s64 offset; - - offset = func - (ip + 2 + 4); - if (!is_simm32(offset)) { - pr_err("Target %p is out of range\n", func); - return -EINVAL; - } - EMIT2_off32(0x0F, jmp_cond + 0x10, offset); - *pprog = prog; - return 0; -} - -static void emit_nops(u8 **pprog, unsigned int len) -{ - unsigned int i, noplen; - u8 *prog = *pprog; - int cnt = 0; - - while (len > 0) { - noplen = len; - - if (noplen > ASM_NOP_MAX) - noplen = ASM_NOP_MAX; - - for (i = 0; i < noplen; i++) - EMIT1(ideal_nops[noplen][i]); - len -= noplen; - } - - *pprog = prog; -} - -static int emit_fallback_jump(u8 **pprog) -{ - u8 *prog = *pprog; - int err = 0; - -#ifdef CONFIG_RETPOLINE - /* Note that this assumes the the compiler uses external - * thunks for indirect calls. Both clang and GCC use the same - * naming convention for external thunks. - */ - err = emit_jump(&prog, __x86_indirect_thunk_rdx, prog); -#else - int cnt = 0; - - EMIT2(0xFF, 0xE2); /* jmp rdx */ -#endif - *pprog = prog; - return err; -} - -static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs) -{ - u8 *jg_reloc, *jg_target, *prog = *pprog; - int pivot, err, jg_bytes = 1, cnt = 0; - s64 jg_offset; - - if (a == b) { - /* Leaf node of recursion, i.e. not a range of indices - * anymore. - */ - EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */ - if (!is_simm32(progs[a])) - return -1; - EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), - progs[a]); - err = emit_cond_near_jump(&prog, /* je func */ - (void *)progs[a], prog, - X86_JE); - if (err) - return err; - - err = emit_fallback_jump(&prog); /* jmp thunk/indirect */ - if (err) - return err; - - *pprog = prog; - return 0; - } - - /* Not a leaf node, so we pivot, and recursively descend into - * the lower and upper ranges. - */ - pivot = (b - a) / 2; - EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */ - if (!is_simm32(progs[a + pivot])) - return -1; - EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]); - - if (pivot > 2) { /* jg upper_part */ - /* Require near jump. */ - jg_bytes = 4; - EMIT2_off32(0x0F, X86_JG + 0x10, 0); - } else { - EMIT2(X86_JG, 0); - } - jg_reloc = prog; - - err = emit_bpf_dispatcher(&prog, a, a + pivot, /* emit lower_part */ - progs); - if (err) - return err; - - /* From Intel 64 and IA-32 Architectures Optimization - * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler - * Coding Rule 11: All branch targets should be 16-byte - * aligned. - */ - jg_target = PTR_ALIGN(prog, 16); - if (jg_target != prog) - emit_nops(&prog, jg_target - prog); - jg_offset = prog - jg_reloc; - emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes); - - err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */ - b, progs); - if (err) - return err; - - *pprog = prog; - return 0; -} - -static int cmp_ips(const void *a, const void *b) -{ - const s64 *ipa = a; - const s64 *ipb = b; - - if (*ipa > *ipb) - return 1; - if (*ipa < *ipb) - return -1; - return 0; -} - -int arch_prepare_bpf_dispatcher(void *image, s64 *funcs, int num_funcs) -{ - u8 *prog = image; - - sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL); - return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs); -} - struct x64_jit_data { struct bpf_binary_header *header; int *addrs; @@ -2174,24 +1176,12 @@ out_image: break; } if (proglen == oldproglen) { - /* - * The number of entries in extable is the number of BPF_LDX - * insns that access kernel memory via "pointer to BTF type". - * The verifier changed their opcode from LDX|MEM|size - * to LDX|PROBE_MEM|size to make JITing easier. - */ - u32 align = __alignof__(struct exception_table_entry); - u32 extable_size = prog->aux->num_exentries * - sizeof(struct exception_table_entry); - - /* allocate module memory for x86 insns and extable */ - header = bpf_jit_binary_alloc(roundup(proglen, align) + extable_size, - &image, align, jit_fill_hole); + header = bpf_jit_binary_alloc(proglen, &image, + 1, jit_fill_hole); if (!header) { prog = orig_prog; goto out_addrs; } - prog->aux->extable = (void *) image + roundup(proglen, align); } oldproglen = proglen; cond_resched(); @@ -2202,7 +1192,6 @@ out_image: if (image) { if (!prog->is_func || extra_pass) { - bpf_tail_call_direct_fixup(prog); bpf_jit_binary_lock_ro(header); } else { jit_data->addrs = addrs; diff --git a/arch/x86/pci/pcbios.c b/arch/x86/pci/pcbios.c index 4f15280732ed..9c97d814125e 100644 --- a/arch/x86/pci/pcbios.c +++ b/arch/x86/pci/pcbios.c @@ -302,7 +302,7 @@ static const struct pci_raw_ops *__init pci_find_bios(void) check <= (union bios32 *) __va(0xffff0); ++check) { long sig; - if (get_kernel_nofault(sig, &check->fields.signature)) + if (probe_kernel_address(&check->fields.signature, sig)) continue; if (check->fields.signature != BIOS32_SIGNATURE) diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index adbfe469655b..65cf405cd975 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -384,7 +384,7 @@ static void set_aliased_prot(void *v, pgprot_t prot) preempt_disable(); - copy_from_kernel_nofault(&dummy, v, 1); + probe_kernel_read(&dummy, v, 1); if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0)) BUG(); diff --git a/arch/xtensa/include/asm/seccomp.h b/arch/xtensa/include/asm/seccomp.h deleted file mode 100644 index f1cb6b0a9e1f..000000000000 --- a/arch/xtensa/include/asm/seccomp.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _ASM_SECCOMP_H -#define _ASM_SECCOMP_H - -#include - -#define SECCOMP_ARCH_NATIVE AUDIT_ARCH_XTENSA -#define SECCOMP_ARCH_NATIVE_NR NR_syscalls -#define SECCOMP_ARCH_NATIVE_NAME "xtensa" - -#endif /* _ASM_SECCOMP_H */ diff --git a/arch/xtensa/kernel/syscalls/syscall.tbl b/arch/xtensa/kernel/syscalls/syscall.tbl index c522c79b887b..efb08d731a01 100644 --- a/arch/xtensa/kernel/syscalls/syscall.tbl +++ b/arch/xtensa/kernel/syscalls/syscall.tbl @@ -406,9 +406,8 @@ 433 common fspick sys_fspick 434 common pidfd_open sys_pidfd_open 435 common clone3 sys_clone3 -436 common close_range sys_close_range +# 436 reserved for close_range # 437 reserved for openat2 # 438 reserved for pidfd_getfd # 439 reserved for faccessat2 440 common process_madvise sys_process_madvise -441 common epoll_pwait2 sys_epoll_pwait2 diff --git a/block/blk-core.c b/block/blk-core.c index c565130ddf75..74f7a2a4f295 100644 --- a/block/blk-core.c +++ b/block/blk-core.c @@ -504,6 +504,8 @@ struct request_queue *blk_alloc_queue_node(gfp_t gfp_mask, int node_id) if (!q->stats) goto fail_stats; + q->backing_dev_info->ra_pages = VM_READAHEAD_PAGES; + q->backing_dev_info->io_pages = VM_READAHEAD_PAGES; q->backing_dev_info->capabilities = BDI_CAP_CGROUP_WRITEBACK; q->backing_dev_info->name = "block"; q->node = node_id; diff --git a/block/blk-mq-sysfs.c b/block/blk-mq-sysfs.c index 532afcb67241..7abd66d1228a 100644 --- a/block/blk-mq-sysfs.c +++ b/block/blk-mq-sysfs.c @@ -241,11 +241,9 @@ static void blk_mq_unregister_hctx(struct blk_mq_hw_ctx *hctx) return; hctx_for_each_ctx(hctx, ctx, i) - if (ctx->kobj.state_in_sysfs) - kobject_del(&ctx->kobj); + kobject_del(&ctx->kobj); - if (hctx->kobj.state_in_sysfs) - kobject_del(&hctx->kobj); + kobject_del(&hctx->kobj); } static int blk_mq_register_hctx(struct blk_mq_hw_ctx *hctx) diff --git a/block/blk-settings.c b/block/blk-settings.c index d4870441a38a..13be635300a8 100644 --- a/block/blk-settings.c +++ b/block/blk-settings.c @@ -505,8 +505,7 @@ static unsigned int blk_round_down_sectors(unsigned int sectors, unsigned int lb int blk_stack_limits(struct queue_limits *t, struct queue_limits *b, sector_t start) { - unsigned int top, bottom, alignment; - int ret = 0; + unsigned int top, bottom, alignment, ret = 0; t->max_sectors = min_not_zero(t->max_sectors, b->max_sectors); t->max_hw_sectors = min_not_zero(t->max_hw_sectors, b->max_hw_sectors); diff --git a/crypto/essiv.c b/crypto/essiv.c index 8a74cc34ac50..aa6b89e91ac8 100644 --- a/crypto/essiv.c +++ b/crypto/essiv.c @@ -203,14 +203,9 @@ static int essiv_aead_crypt(struct aead_request *req, bool enc) const struct essiv_tfm_ctx *tctx = crypto_aead_ctx(tfm); struct essiv_aead_request_ctx *rctx = aead_request_ctx(req); struct aead_request *subreq = &rctx->aead_req; - int ivsize = crypto_aead_ivsize(tfm); - int ssize = req->assoclen - ivsize; struct scatterlist *src = req->src; int err; - if (ssize < 0) - return -EINVAL; - crypto_cipher_encrypt_one(tctx->essiv_cipher, req->iv, req->iv); /* @@ -220,12 +215,19 @@ static int essiv_aead_crypt(struct aead_request *req, bool enc) */ rctx->assoc = NULL; if (req->src == req->dst || !enc) { - scatterwalk_map_and_copy(req->iv, req->dst, ssize, ivsize, 1); + scatterwalk_map_and_copy(req->iv, req->dst, + req->assoclen - crypto_aead_ivsize(tfm), + crypto_aead_ivsize(tfm), 1); } else { u8 *iv = (u8 *)aead_request_ctx(req) + tctx->ivoffset; + int ivsize = crypto_aead_ivsize(tfm); + int ssize = req->assoclen - ivsize; struct scatterlist *sg; int nents; + if (ssize < 0) + return -EINVAL; + nents = sg_nents_for_len(req->src, ssize); if (nents < 0) return -EINVAL; diff --git a/crypto/sha1_generic.c b/crypto/sha1_generic.c index a16d9787dcd2..7c57b844c382 100644 --- a/crypto/sha1_generic.c +++ b/crypto/sha1_generic.c @@ -31,10 +31,10 @@ EXPORT_SYMBOL_GPL(sha1_zero_message_hash); static void sha1_generic_block_fn(struct sha1_state *sst, u8 const *src, int blocks) { - u32 temp[SHA1_WORKSPACE_WORDS]; + u32 temp[SHA_WORKSPACE_WORDS]; while (blocks--) { - sha1_transform(sst->state, src, temp); + sha_transform(sst->state, src, temp); src += SHA1_BLOCK_SIZE; } memzero_explicit(temp, sizeof(temp)); diff --git a/drivers/acpi/acpi_dbg.c b/drivers/acpi/acpi_dbg.c index ec6868c64fdb..cc4b509bad94 100644 --- a/drivers/acpi/acpi_dbg.c +++ b/drivers/acpi/acpi_dbg.c @@ -576,11 +576,11 @@ static int acpi_aml_release(struct inode *inode, struct file *file) return 0; } -static ssize_t acpi_aml_read_user(char __user *buf, size_t len) +static int acpi_aml_read_user(char __user *buf, int len) { + int ret; struct circ_buf *crc = &acpi_aml_io.out_crc; - ssize_t ret; - size_t n; + int n; char *p; ret = acpi_aml_lock_read(crc, ACPI_AML_OUT_USER); @@ -589,7 +589,7 @@ static ssize_t acpi_aml_read_user(char __user *buf, size_t len) /* sync head before removing logs */ smp_rmb(); p = &crc->buf[crc->tail]; - n = min_t(size_t, len, circ_count_to_end(crc)); + n = min(len, circ_count_to_end(crc)); if (copy_to_user(buf, p, n)) { ret = -EFAULT; goto out; @@ -606,8 +606,8 @@ out: static ssize_t acpi_aml_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) { - ssize_t ret = 0; - ssize_t size = 0; + int ret = 0; + int size = 0; if (!count) return 0; @@ -646,11 +646,11 @@ again: return size > 0 ? size : ret; } -static ssize_t acpi_aml_write_user(const char __user *buf, size_t len) +static int acpi_aml_write_user(const char __user *buf, int len) { + int ret; struct circ_buf *crc = &acpi_aml_io.in_crc; - ssize_t ret; - size_t n; + int n; char *p; ret = acpi_aml_lock_write(crc, ACPI_AML_IN_USER); @@ -659,7 +659,7 @@ static ssize_t acpi_aml_write_user(const char __user *buf, size_t len) /* sync tail before inserting cmds */ smp_mb(); p = &crc->buf[crc->head]; - n = min_t(size_t, len, circ_space_to_end(crc)); + n = min(len, circ_space_to_end(crc)); if (copy_from_user(p, buf, n)) { ret = -EFAULT; goto out; @@ -670,14 +670,14 @@ static ssize_t acpi_aml_write_user(const char __user *buf, size_t len) ret = n; out: acpi_aml_unlock_fifo(ACPI_AML_IN_USER, ret >= 0); - return ret; + return n; } static ssize_t acpi_aml_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) { - ssize_t ret = 0; - ssize_t size = 0; + int ret = 0; + int size = 0; if (!count) return 0; diff --git a/drivers/acpi/acpi_tad.c b/drivers/acpi/acpi_tad.c index 3db173e30779..bab8583443a6 100644 --- a/drivers/acpi/acpi_tad.c +++ b/drivers/acpi/acpi_tad.c @@ -563,9 +563,6 @@ static int acpi_tad_remove(struct platform_device *pdev) pm_runtime_get_sync(dev); - if (dd->capabilities & ACPI_TAD_RT) - sysfs_remove_group(&dev->kobj, &acpi_tad_time_attr_group); - if (dd->capabilities & ACPI_TAD_DC_WAKE) sysfs_remove_group(&dev->kobj, &acpi_tad_dc_attr_group); diff --git a/drivers/acpi/acpi_video.c b/drivers/acpi/acpi_video.c index 48b1de7e3556..fd33fdbaffa9 100644 --- a/drivers/acpi/acpi_video.c +++ b/drivers/acpi/acpi_video.c @@ -2024,10 +2024,8 @@ static void acpi_video_bus_remove_notify_handler(struct acpi_video_bus *video) struct acpi_video_device *dev; mutex_lock(&video->device_list_lock); - list_for_each_entry(dev, &video->video_device_list, entry) { + list_for_each_entry(dev, &video->video_device_list, entry) acpi_video_dev_remove_notify_handler(dev); - cancel_delayed_work_sync(&dev->switch_brightness_work); - } mutex_unlock(&video->device_list_lock); acpi_video_bus_stop_devices(video); diff --git a/drivers/acpi/acpica/dsmethod.c b/drivers/acpi/acpica/dsmethod.c index 9f52d301e977..203e9ee47fdb 100644 --- a/drivers/acpi/acpica/dsmethod.c +++ b/drivers/acpi/acpica/dsmethod.c @@ -462,6 +462,7 @@ acpi_ds_call_control_method(struct acpi_thread_state *thread, struct acpi_walk_state *next_walk_state = NULL; union acpi_operand_object *obj_desc; struct acpi_evaluate_info *info; + u32 i; ACPI_FUNCTION_TRACE_PTR(ds_call_control_method, this_walk_state); @@ -545,7 +546,14 @@ acpi_ds_call_control_method(struct acpi_thread_state *thread, * Delete the operands on the previous walkstate operand stack * (they were copied to new objects) */ - acpi_ds_clear_operands(this_walk_state); + for (i = 0; i < obj_desc->method.param_count; i++) { + acpi_ut_remove_reference(this_walk_state->operands[i]); + this_walk_state->operands[i] = NULL; + } + + /* Clear the operand stack */ + + this_walk_state->num_operands = 0; ACPI_DEBUG_PRINT((ACPI_DB_DISPATCH, "**** Begin nested execution of [%4.4s] **** WalkState=%p\n", diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index 6fb6e1b25798..e1abbc1a1356 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -1508,9 +1508,6 @@ int acpi_processor_power_init(struct acpi_processor *pr) if (retval) { if (acpi_processor_registered == 0) cpuidle_unregister_driver(&acpi_idle_driver); - - per_cpu(acpi_cpuidle_device, pr->id) = NULL; - kfree(dev); return retval; } acpi_processor_registered++; diff --git a/drivers/acpi/property.c b/drivers/acpi/property.c index c25fe9b86e23..5906e247b9fa 100644 --- a/drivers/acpi/property.c +++ b/drivers/acpi/property.c @@ -1114,28 +1114,6 @@ struct fwnode_handle *acpi_get_next_subnode(const struct fwnode_handle *fwnode, return NULL; } -/* - * acpi_get_next_present_subnode - Return the next present child node handle - * @fwnode: Firmware node to find the next child node for. - * @child: Handle to one of the device's child nodes or a null handle. - * - * Like acpi_get_next_subnode(), but the device nodes returned by - * acpi_get_next_present_subnode() are guaranteed to be present. - * - * Returns: The fwnode handle of the next present sub-node. - */ -static struct fwnode_handle * -acpi_get_next_present_subnode(const struct fwnode_handle *fwnode, - struct fwnode_handle *child) -{ - do { - child = acpi_get_next_subnode(fwnode, child); - } while (is_acpi_device_node(child) && - !acpi_device_is_present(to_acpi_device_node(child))); - - return child; -} - /** * acpi_node_get_parent - Return parent fwnode of this fwnode * @fwnode: Firmware node whose parent to get @@ -1409,7 +1387,7 @@ acpi_fwnode_device_get_match_data(const struct fwnode_handle *fwnode, .property_read_string_array = \ acpi_fwnode_property_read_string_array, \ .get_parent = acpi_node_get_parent, \ - .get_next_child_node = acpi_get_next_present_subnode, \ + .get_next_child_node = acpi_get_next_subnode, \ .get_named_child_node = acpi_fwnode_get_named_child_node, \ .get_reference_args = acpi_fwnode_get_reference_args, \ .graph_get_next_endpoint = \ diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c index 640e3fecd62d..be9c70806b62 100644 --- a/drivers/acpi/video_detect.c +++ b/drivers/acpi/video_detect.c @@ -556,14 +556,6 @@ static const struct dmi_system_id video_detect_dmi_table[] = { DMI_MATCH(DMI_PRODUCT_NAME, "MS-7721"), }, }, - /* https://gitlab.freedesktop.org/drm/amd/-/issues/4512 */ - { - .callback = video_detect_force_native, - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), - DMI_MATCH(DMI_PRODUCT_NAME, "82K8"), - }, - }, { }, }; diff --git a/drivers/android/binder.c b/drivers/android/binder.c index cfe7a2aa026c..ba1411e8bc81 100644 --- a/drivers/android/binder.c +++ b/drivers/android/binder.c @@ -990,8 +990,17 @@ static int binder_inc_node_nilocked(struct binder_node *node, int strong, } else { if (!internal) node->local_weak_refs++; - if (!node->has_weak_ref && target_list && list_empty(&node->work.entry)) + if (!node->has_weak_ref && list_empty(&node->work.entry)) { + if (target_list == NULL) { + pr_err("invalid inc weak node for %d\n", + node->debug_id); + return -EINVAL; + } + /* + * See comment above + */ binder_enqueue_work_ilocked(&node->work, target_list); + } } return 0; } @@ -6923,7 +6932,7 @@ const struct file_operations binder_fops = { .owner = THIS_MODULE, .poll = binder_poll, .unlocked_ioctl = binder_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = binder_ioctl, .mmap = binder_mmap, .open = binder_open, .flush = binder_flush, diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c index c0a22c74472d..35c87e7e4ddf 100644 --- a/drivers/ata/libata-scsi.c +++ b/drivers/ata/libata-scsi.c @@ -1179,14 +1179,6 @@ static void ata_gen_ata_sense(struct ata_queued_cmd *qc) ata_scsi_set_sense(dev, cmd, NOT_READY, 0x04, 0x21); return; } - - if (ata_id_is_locked(dev->id)) { - /* Security locked */ - /* LOGICAL UNIT ACCESS NOT AUTHORIZED */ - ata_scsi_set_sense(dev, cmd, DATA_PROTECT, 0x74, 0x71); - return; - } - /* Use ata_to_sense_error() to map status register bits * onto sense key, asc & ascq. */ diff --git a/drivers/base/devcoredump.c b/drivers/base/devcoredump.c index 7c62b397f134..e9398bcffab6 100644 --- a/drivers/base/devcoredump.c +++ b/drivers/base/devcoredump.c @@ -30,46 +30,50 @@ struct devcd_entry { void *data; size_t datalen; /* - * There are 2 races for which mutex is required. + * Here, mutex is required to serialize the calls to del_wk work between + * user/kernel space which happens when devcd is added with device_add() + * and that sends uevent to user space. User space reads the uevents, + * and calls to devcd_data_write() which try to modify the work which is + * not even initialized/queued from devcoredump. * - * The first race is between device creation and userspace writing to - * schedule immediately destruction. * - * This race is handled by arming the timer before device creation, but - * when device creation fails the timer still exists. * - * To solve this, hold the mutex during device_add(), and set - * init_completed on success before releasing the mutex. + * cpu0(X) cpu1(Y) * - * That way the timer will never fire until device_add() is called, - * it will do nothing if init_completed is not set. The timer is also - * cancelled in that case. + * dev_coredump() uevent sent to user space + * device_add() ======================> user space process Y reads the + * uevents writes to devcd fd + * which results into writes to * - * The second race involves multiple parallel invocations of devcd_free(), - * add a deleted flag so only 1 can call the destructor. + * devcd_data_write() + * mod_delayed_work() + * try_to_grab_pending() + * del_timer() + * debug_assert_init() + * INIT_DELAYED_WORK() + * schedule_delayed_work() + * + * + * Also, mutex alone would not be enough to avoid scheduling of + * del_wk work after it get flush from a call to devcd_free() + * mentioned as below. + * + * disabled_store() + * devcd_free() + * mutex_lock() devcd_data_write() + * flush_delayed_work() + * mutex_unlock() + * mutex_lock() + * mod_delayed_work() + * mutex_unlock() + * So, delete_work flag is required. */ struct mutex mutex; - bool init_completed, deleted; + bool delete_work; struct module *owner; ssize_t (*read)(char *buffer, loff_t offset, size_t count, void *data, size_t datalen); void (*free)(void *data); - /* - * If nothing interferes and device_add() was returns success, - * del_wk will destroy the device after the timer fires. - * - * Multiple userspace processes can interfere in the working of the timer: - * - Writing to the coredump will reschedule the timer to run immediately, - * if still armed. - * - * This is handled by using "if (cancel_delayed_work()) { - * schedule_delayed_work() }", to prevent re-arming after having - * been previously fired. - * - Writing to /sys/class/devcoredump/disabled will destroy the - * coredump synchronously. - * This is handled by using disable_delayed_work_sync(), and then - * checking if deleted flag is set with &devcd->mutex held. - */ struct delayed_work del_wk; struct device *failing_dev; }; @@ -98,27 +102,14 @@ static void devcd_dev_release(struct device *dev) kfree(devcd); } -static void __devcd_del(struct devcd_entry *devcd) -{ - devcd->deleted = true; - device_del(&devcd->devcd_dev); - put_device(&devcd->devcd_dev); -} - static void devcd_del(struct work_struct *wk) { struct devcd_entry *devcd; - bool init_completed; devcd = container_of(wk, struct devcd_entry, del_wk.work); - /* devcd->mutex serializes against dev_coredumpm_timeout */ - mutex_lock(&devcd->mutex); - init_completed = devcd->init_completed; - mutex_unlock(&devcd->mutex); - - if (init_completed) - __devcd_del(devcd); + device_del(&devcd->devcd_dev); + put_device(&devcd->devcd_dev); } static ssize_t devcd_data_read(struct file *filp, struct kobject *kobj, @@ -138,12 +129,12 @@ static ssize_t devcd_data_write(struct file *filp, struct kobject *kobj, struct device *dev = kobj_to_dev(kobj); struct devcd_entry *devcd = dev_to_devcd(dev); - /* - * Although it's tempting to use mod_delayed work here, - * that will cause a reschedule if the timer already fired. - */ - if (cancel_delayed_work(&devcd->del_wk)) - schedule_delayed_work(&devcd->del_wk, 0); + mutex_lock(&devcd->mutex); + if (!devcd->delete_work) { + devcd->delete_work = true; + mod_delayed_work(system_wq, &devcd->del_wk, 0); + } + mutex_unlock(&devcd->mutex); return count; } @@ -171,21 +162,11 @@ static int devcd_free(struct device *dev, void *data) { struct devcd_entry *devcd = dev_to_devcd(dev); - /* - * To prevent a race with devcd_data_write(), cancel work and - * complete manually instead. - * - * We cannot rely on the return value of - * cancel_delayed_work_sync() here, because it might be in the - * middle of a cancel_delayed_work + schedule_delayed_work pair. - * - * devcd->mutex here guards against multiple parallel invocations - * of devcd_free(). - */ - cancel_delayed_work_sync(&devcd->del_wk); mutex_lock(&devcd->mutex); - if (!devcd->deleted) - __devcd_del(devcd); + if (!devcd->delete_work) + devcd->delete_work = true; + + flush_delayed_work(&devcd->del_wk); mutex_unlock(&devcd->mutex); return 0; } @@ -209,10 +190,12 @@ static ssize_t disabled_show(struct class *class, struct class_attribute *attr, * put_device() <- last reference * error = fn(dev, data) devcd_dev_release() * devcd_free(dev, data) kfree(devcd) + * mutex_lock(&devcd->mutex); * * - * In the above diagram, it looks like disabled_store() would be racing with parallelly - * running devcd_del() and result in memory abort after dropping its last reference with + * In the above diagram, It looks like disabled_store() would be racing with parallely + * running devcd_del() and result in memory abort while acquiring devcd->mutex which + * is called after kfree of devcd memory after dropping its last reference with * put_device(). However, this will not happens as fn(dev, data) runs * with its own reference to device via klist_node so it is not its last reference. * so, above situation would not occur. @@ -374,7 +357,7 @@ void dev_coredumpm(struct device *dev, struct module *owner, devcd->read = read; devcd->free = free; devcd->failing_dev = get_device(dev); - devcd->deleted = false; + devcd->delete_work = false; mutex_init(&devcd->mutex); device_initialize(&devcd->devcd_dev); @@ -383,14 +366,8 @@ void dev_coredumpm(struct device *dev, struct module *owner, atomic_inc_return(&devcd_count)); devcd->devcd_dev.class = &devcd_class; - dev_set_uevent_suppress(&devcd->devcd_dev, true); - - /* devcd->mutex prevents devcd_del() completing until init finishes */ mutex_lock(&devcd->mutex); - devcd->init_completed = false; - INIT_DELAYED_WORK(&devcd->del_wk, devcd_del); - schedule_delayed_work(&devcd->del_wk, DEVCD_TIMEOUT); - + dev_set_uevent_suppress(&devcd->devcd_dev, true); if (device_add(&devcd->devcd_dev)) goto put_device; @@ -404,20 +381,13 @@ void dev_coredumpm(struct device *dev, struct module *owner, dev_set_uevent_suppress(&devcd->devcd_dev, false); kobject_uevent(&devcd->devcd_dev.kobj, KOBJ_ADD); - - /* - * Safe to run devcd_del() now that we are done with devcd_dev. - * Alternatively we could have taken a ref on devcd_dev before - * dropping the lock. - */ - devcd->init_completed = true; + INIT_DELAYED_WORK(&devcd->del_wk, devcd_del); + schedule_delayed_work(&devcd->del_wk, DEVCD_TIMEOUT); mutex_unlock(&devcd->mutex); return; put_device: - mutex_unlock(&devcd->mutex); - cancel_delayed_work_sync(&devcd->del_wk); put_device(&devcd->devcd_dev); - + mutex_unlock(&devcd->mutex); put_module: module_put(owner); free: diff --git a/drivers/base/node.c b/drivers/base/node.c index 3b150111561d..9d9271fcfa83 100644 --- a/drivers/base/node.c +++ b/drivers/base/node.c @@ -944,10 +944,6 @@ int __register_one_node(int nid) return -ENOMEM; error = register_node(node_devices[nid], nid); - if (error) { - node_devices[nid] = NULL; - return error; - } /* link cpu under this node */ for_each_present_cpu(cpu) { diff --git a/drivers/base/regmap/regmap-slimbus.c b/drivers/base/regmap/regmap-slimbus.c index 851d7bdd6b7e..0968059f1ef5 100644 --- a/drivers/base/regmap/regmap-slimbus.c +++ b/drivers/base/regmap/regmap-slimbus.c @@ -48,7 +48,8 @@ struct regmap *__regmap_init_slimbus(struct slim_device *slimbus, if (IS_ERR(bus)) return ERR_CAST(bus); - return __regmap_init(&slimbus->dev, bus, slimbus, config, lock_key, lock_name); + return __regmap_init(&slimbus->dev, bus, &slimbus->dev, config, + lock_key, lock_name); } EXPORT_SYMBOL_GPL(__regmap_init_slimbus); @@ -62,7 +63,8 @@ struct regmap *__devm_regmap_init_slimbus(struct slim_device *slimbus, if (IS_ERR(bus)) return ERR_CAST(bus); - return __devm_regmap_init(&slimbus->dev, bus, slimbus, config, lock_key, lock_name); + return __devm_regmap_init(&slimbus->dev, bus, &slimbus, config, + lock_key, lock_name); } EXPORT_SYMBOL_GPL(__devm_regmap_init_slimbus); diff --git a/drivers/block/drbd/drbd_bitmap.c b/drivers/block/drbd/drbd_bitmap.c index df53dca5d02c..15e99697234a 100644 --- a/drivers/block/drbd/drbd_bitmap.c +++ b/drivers/block/drbd/drbd_bitmap.c @@ -396,7 +396,9 @@ static struct page **bm_realloc_pages(struct drbd_bitmap *b, unsigned long want) bytes = sizeof(struct page *)*want; new_pages = kzalloc(bytes, GFP_NOIO | __GFP_NOWARN); if (!new_pages) { - new_pages = __vmalloc(bytes, GFP_NOIO | __GFP_ZERO); + new_pages = __vmalloc(bytes, + GFP_NOIO | __GFP_ZERO, + PAGE_KERNEL); if (!new_pages) return NULL; } diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c index 3d79637a56cc..9f71f9135f9e 100644 --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c @@ -4004,11 +4004,6 @@ static void btusb_disconnect(struct usb_interface *intf) hci_unregister_dev(hdev); - if (data->oob_wake_irq) - device_init_wakeup(&data->udev->dev, false); - if (data->reset_gpio) - gpiod_put(data->reset_gpio); - if (intf == data->intf) { if (data->isoc) usb_driver_release_interface(&btusb_driver, data->isoc); @@ -4019,11 +4014,17 @@ static void btusb_disconnect(struct usb_interface *intf) usb_driver_release_interface(&btusb_driver, data->diag); usb_driver_release_interface(&btusb_driver, data->intf); } else if (intf == data->diag) { + usb_driver_release_interface(&btusb_driver, data->intf); if (data->isoc) usb_driver_release_interface(&btusb_driver, data->isoc); - usb_driver_release_interface(&btusb_driver, data->intf); } + if (data->oob_wake_irq) + device_init_wakeup(&data->udev->dev, false); + + if (data->reset_gpio) + gpiod_put(data->reset_gpio); + hci_free_dev(hdev); } diff --git a/drivers/bluetooth/hci_bcsp.c b/drivers/bluetooth/hci_bcsp.c index 8ff69111ceed..8055f63603f4 100644 --- a/drivers/bluetooth/hci_bcsp.c +++ b/drivers/bluetooth/hci_bcsp.c @@ -582,9 +582,6 @@ static int bcsp_recv(struct hci_uart *hu, const void *data, int count) struct bcsp_struct *bcsp = hu->priv; const unsigned char *ptr; - if (!test_bit(HCI_UART_REGISTERED, &hu->flags)) - return -EUNATCH; - BT_DBG("hu %p count %d rx_state %d rx_count %ld", hu, count, bcsp->rx_state, bcsp->rx_count); diff --git a/drivers/cdrom/cdrom.c b/drivers/cdrom/cdrom.c index 628d6598efe8..eebdcbef0578 100644 --- a/drivers/cdrom/cdrom.c +++ b/drivers/cdrom/cdrom.c @@ -3495,7 +3495,7 @@ static int cdrom_print_info(const char *header, int val, char *info, } static int cdrom_sysctl_info(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int pos; char *info = cdrom_sysctl_settings.info; @@ -3608,7 +3608,7 @@ static void cdrom_update_settings(void) } static int cdrom_sysctl_handler(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int ret; diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c index 979debfc811c..7ecf16753f17 100644 --- a/drivers/char/adsprpc.c +++ b/drivers/char/adsprpc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /* Uncomment this block to log an error on every VERIFY failure */ @@ -62,7 +62,6 @@ #define TZ_PIL_AUTH_QDSP6_PROC 1 #define FASTRPC_DMAHANDLE_NOMAP (16) -#define FASTRPC_MAP_DMA_HANDLE 0x20000 #define FASTRPC_ENOSUCH 39 #define DEBUGFS_SIZE 3072 @@ -444,7 +443,6 @@ struct smq_invoke_ctx { uint32_t sc_interrupted; struct fastrpc_file *fl_interrupted; uint32_t handle_interrupted; - struct timespec64 invoke_start_time; /* submission timestamp for async perf */ }; struct fastrpc_ctx_lst { @@ -1130,7 +1128,7 @@ static void fastrpc_mmap_add(struct fastrpc_mmap *map) } static int fastrpc_mmap_find(struct fastrpc_file *fl, int fd, - uintptr_t va, size_t len, int mflags, bool refs, + uintptr_t va, size_t len, int mflags, int refs, struct fastrpc_mmap **ppmap) { struct fastrpc_mmap *match = NULL, *map = NULL; @@ -1308,7 +1306,7 @@ static void fastrpc_mmap_free(struct fastrpc_mmap *map, uint32_t flags) dma_free_attrs(me->dev, map->size, (void *)map->va, (dma_addr_t)map->phys, (unsigned long)map->attr); } - } else if (map->flags & FASTRPC_DMAHANDLE_NOMAP) { + } else if (map->flags == FASTRPC_DMAHANDLE_NOMAP) { trace_fastrpc_dma_unmap(cid, map->phys, map->size); if (!IS_ERR_OR_NULL(map->table)) dma_buf_unmap_attachment(map->attach, map->table, @@ -1393,7 +1391,6 @@ static int fastrpc_mmap_create(struct fastrpc_file *fl, int fd, unsigned long flags; int err = 0, vmid, sgl_index = 0; struct scatterlist *sgl = NULL; - bool take_ref = true; if (!fl) { err = -EBADF; @@ -1407,9 +1404,7 @@ static int fastrpc_mmap_create(struct fastrpc_file *fl, int fd, } chan = &apps->channel[cid]; - if (mflags & FASTRPC_MAP_DMA_HANDLE) - take_ref = false; - if (!fastrpc_mmap_find(fl, fd, va, len, mflags, take_ref, ppmap)) + if (!fastrpc_mmap_find(fl, fd, va, len, mflags, 1, ppmap)) return 0; map = kzalloc(sizeof(*map), GFP_KERNEL); VERIFY(err, !IS_ERR_OR_NULL(map)); @@ -1447,7 +1442,7 @@ static int fastrpc_mmap_create(struct fastrpc_file *fl, int fd, if (err) goto bail; } - } else if (mflags & FASTRPC_DMAHANDLE_NOMAP) { + } else if (mflags == FASTRPC_DMAHANDLE_NOMAP) { if (map->attr & FASTRPC_ATTR_KEEP_MAP) { ADSPRPC_ERR("Invalid attribute 0x%x for fd %d\n", map->attr, fd); @@ -2507,10 +2502,10 @@ static int get_args(uint32_t kernel, struct smq_invoke_ctx *ctx) handles = REMOTE_SCALARS_INHANDLES(sc) + REMOTE_SCALARS_OUTHANDLES(sc); mutex_lock(&ctx->fl->map_mutex); for (i = bufs; i < bufs + handles; i++) { - int dmaflags = FASTRPC_MAP_DMA_HANDLE; + int dmaflags = 0; if (ctx->attrs && (ctx->attrs[i] & FASTRPC_ATTR_NOMAP)) - dmaflags |= FASTRPC_DMAHANDLE_NOMAP; + dmaflags = FASTRPC_DMAHANDLE_NOMAP; if (ctx->fds && (ctx->fds[i] != -1)) err = fastrpc_mmap_create(ctx->fl, ctx->fds[i], FASTRPC_ATTR_NOVA, 0, 0, dmaflags, @@ -2671,7 +2666,7 @@ static int get_args(uint32_t kernel, struct smq_invoke_ctx *ctx) if (ctx->maps[i]) { /* check if map still exist */ if (!fastrpc_mmap_find(ctx->fl, ctx->fds[i], 0, 0, - 0, false, &mmap)) { + 0, 0, &mmap)) { if (mmap) { pages[i].addr = mmap->phys; pages[i].size = mmap->size; @@ -2886,7 +2881,7 @@ static int put_args(uint32_t kernel, struct smq_invoke_ctx *ctx, if (!fdlist[i]) break; if (!fastrpc_mmap_find(ctx->fl, (int)fdlist[i], 0, 0, - 0, false, &mmap)) { + 0, 0, &mmap)) { if (mmap && mmap->dma_handle_refs) { mmap->dma_handle_refs = 0; fastrpc_mmap_free(mmap, 0); @@ -3369,15 +3364,6 @@ static int fastrpc_internal_invoke(struct fastrpc_file *fl, uint32_t mode, inv_args(ctx); PERF_END); - /* - * Store submission timestamp in ctx before sending to DSP. - * For async invokes, perf->invoke will be updated in the collector - * thread (fastrpc_wait_on_async_queue) where ctx is still valid, - * measuring full end-to-end latency consistent with the sync path. - */ - if (fl->profile && isasyncinvoke) - ctx->invoke_start_time = invoket; - PERF(fl->profile, GET_COUNTER(perf_counter, PERF_LINK), VERIFY(err, 0 == (err = fastrpc_invoke_send(ctx, kernel, invoke->handle))); @@ -3439,6 +3425,9 @@ static int fastrpc_internal_invoke(struct fastrpc_file *fl, uint32_t mode, err = -ECONNRESET; invoke_end: + if (fl->profile && !interrupted && isasyncinvoke) + fastrpc_update_invoke_count(invoke->handle, perf_counter, + &invoket); return err; } @@ -3508,15 +3497,6 @@ bail: async_res->result = ierr; if (ctx) { if (fl->profile && ctx->perf && ctx->handle > FASTRPC_STATIC_HANDLE_MAX) { - /* - * Update invoke/count perf counters here where ctx->perf is - * guaranteed valid. This measures full end-to-end async latency - * (submit → DSP → collect), consistent with the sync path. - * invoke_start_time was stored in ctx before fastrpc_invoke_send - * in fastrpc_internal_invoke. - */ - fastrpc_update_invoke_count(ctx->handle, perf_counter, - &ctx->invoke_start_time); trace_fastrpc_perf_counters(ctx->handle, ctx->sc, ctx->perf->count, ctx->perf->flush, ctx->perf->map, ctx->perf->copy, ctx->perf->link, ctx->perf->getargs, @@ -4981,7 +4961,7 @@ static int fastrpc_internal_munmap_fd(struct fastrpc_file *fl, } mutex_lock(&fl->internal_map_mutex); mutex_lock(&fl->map_mutex); - err = fastrpc_mmap_find(fl, ud->fd, ud->va, ud->len, 0, false, &map); + err = fastrpc_mmap_find(fl, ud->fd, ud->va, ud->len, 0, 0, &map); if (err) { ADSPRPC_ERR( "mapping not found to unmap fd 0x%x, va 0x%llx, len 0x%x, err %d\n", diff --git a/drivers/char/mem.c b/drivers/char/mem.c index df8d821f2c00..c5025ae6a37e 100644 --- a/drivers/char/mem.c +++ b/drivers/char/mem.c @@ -171,7 +171,7 @@ static ssize_t read_mem(struct file *file, char __user *buf, if (!ptr) goto failed; - probe = copy_from_kernel_nofault(bounce, ptr, sz); + probe = probe_kernel_read(bounce, ptr, sz); unxlate_dev_mem_ptr(p, ptr); if (probe) goto failed; diff --git a/drivers/char/misc.c b/drivers/char/misc.c index 90929fb2b56e..ca5141ed5ef3 100644 --- a/drivers/char/misc.c +++ b/drivers/char/misc.c @@ -113,8 +113,7 @@ static int misc_open(struct inode *inode, struct file *file) } } - /* Only request module for fixed minor code */ - if (!new_fops && minor < MISC_DYNAMIC_MINOR) { + if (!new_fops) { mutex_unlock(&misc_mtx); request_module("char-major-%d-%d", MISC_MAJOR, minor); mutex_lock(&misc_mtx); @@ -125,11 +124,10 @@ static int misc_open(struct inode *inode, struct file *file) break; } } + if (!new_fops) + goto fail; } - if (!new_fops) - goto fail; - /* * Place the miscdevice in the file's * private_data so it can be used by the diff --git a/drivers/char/random.c b/drivers/char/random.c index e7fc274a9608..fdb144aaf9d1 100644 --- a/drivers/char/random.c +++ b/drivers/char/random.c @@ -799,11 +799,16 @@ early_param("random.trust_cpu", parse_trust_cpu); early_param("random.trust_bootloader", parse_trust_bootloader); /* - * This is called extremely early, before time keeping functionality is - * available, but arch randomness is. Interrupts are not yet enabled. + * The first collection of entropy occurs at system boot while interrupts + * are still turned off. Here we push in latent entropy, RDSEED, a timestamp, + * utsname(), and the command line. Depending on the above configuration knob, + * RDSEED may be considered sufficient for initialization. Note that much + * earlier setup may already have pushed entropy into the input pool by the + * time we get here. */ -void __init random_init_early(const char *command_line) +int __init random_init(const char *command_line) { + ktime_t now = ktime_get_real(); unsigned int i, arch_bits; unsigned long entropy; @@ -816,41 +821,22 @@ void __init random_init_early(const char *command_line) i < BLAKE2S_BLOCK_SIZE; i += sizeof(entropy)) { if (!arch_get_random_seed_long_early(&entropy) && !arch_get_random_long_early(&entropy)) { + entropy = random_get_entropy(); arch_bits -= sizeof(entropy) * 8; - continue; } _mix_pool_bytes(&entropy, sizeof(entropy)); } - + _mix_pool_bytes(&now, sizeof(now)); + _mix_pool_bytes(utsname(), sizeof(*(utsname()))); _mix_pool_bytes(command_line, strlen(command_line)); + add_latent_entropy(); - /* Reseed if already seeded by earlier phases. */ if (crng_ready()) crng_reseed(); else if (trust_cpu) _credit_init_bits(arch_bits); -} -/* - * This is called a little bit after the prior function, and now there is - * access to timestamps counters. Interrupts are not yet enabled. - */ -void __init random_init(void) -{ - unsigned long entropy = random_get_entropy(); - ktime_t now = ktime_get_real(); - - _mix_pool_bytes(utsname(), sizeof(*(utsname()))); - _mix_pool_bytes(&now, sizeof(now)); - _mix_pool_bytes(&entropy, sizeof(entropy)); - add_latent_entropy(); - - /* Reseed if already seeded by earlier phases. */ - if (crng_ready()) - crng_reseed(); - - WARN(!entropy, "Missing cycle counter and fallback timer; RNG " - "entropy collection will consequently suffer."); + return 0; } /* @@ -1460,7 +1446,7 @@ static u8 sysctl_bootid[UUID_SIZE]; * UUID. The difference is in whether table->data is NULL; if it is, * then a new UUID is generated and returned to the user. */ -static int proc_do_uuid(struct ctl_table *table, int write, void *buf, +static int proc_do_uuid(struct ctl_table *table, int write, void __user *buf, size_t *lenp, loff_t *ppos) { u8 tmp_uuid[UUID_SIZE], *uuid; @@ -1491,7 +1477,7 @@ static int proc_do_uuid(struct ctl_table *table, int write, void *buf, } /* The same as proc_dointvec, but writes don't change anything. */ -static int proc_do_rointvec(struct ctl_table *table, int write, void *buf, +static int proc_do_rointvec(struct ctl_table *table, int write, void __user *buf, size_t *lenp, loff_t *ppos) { return write ? 0 : proc_dointvec(table, 0, buf, lenp, ppos); diff --git a/drivers/char/tpm/tpm_tis_core.c b/drivers/char/tpm/tpm_tis_core.c index b538db3052b7..a084f732c180 100644 --- a/drivers/char/tpm/tpm_tis_core.c +++ b/drivers/char/tpm/tpm_tis_core.c @@ -633,10 +633,16 @@ static void tpm_tis_gen_interrupt(struct tpm_chip *chip) cap_t cap; int ret; + ret = request_locality(chip, 0); + if (ret < 0) + return; + if (chip->flags & TPM_CHIP_FLAG_TPM2) ret = tpm2_get_tpm_pt(chip, 0x100, &cap2, desc); else ret = tpm1_getcap(chip, TPM_CAP_PROP_TIS_TIMEOUT, &cap, desc, 0); + + release_locality(chip, 0); } /* Register the IRQ and issue a command that will cause an interrupt. If an @@ -659,16 +665,10 @@ static int tpm_tis_probe_irq_single(struct tpm_chip *chip, u32 intmask, } priv->irq = irq; - rc = request_locality(chip, 0); - if (rc < 0) - return rc; - rc = tpm_tis_read8(priv, TPM_INT_VECTOR(priv->locality), &original_int_vec); - if (rc < 0) { - release_locality(chip, priv->locality); + if (rc < 0) return rc; - } rc = tpm_tis_write8(priv, TPM_INT_VECTOR(priv->locality), irq); if (rc < 0) @@ -700,14 +700,12 @@ restore_irqs: * will call disable_irq which undoes all of the above. */ if (!(chip->flags & TPM_CHIP_FLAG_IRQ)) { - tpm_tis_write8(priv, TPM_INT_VECTOR(priv->locality), - original_int_vec); - rc = -1; + tpm_tis_write8(priv, original_int_vec, + TPM_INT_VECTOR(priv->locality)); + return -1; } - release_locality(chip, priv->locality); - - return rc; + return 0; } /* Try to find the IRQ the TPM is using. This is for legacy x86 systems that diff --git a/drivers/clk/nxp/clk-lpc18xx-cgu.c b/drivers/clk/nxp/clk-lpc18xx-cgu.c index ab8741fe57c9..8b686da5577b 100644 --- a/drivers/clk/nxp/clk-lpc18xx-cgu.c +++ b/drivers/clk/nxp/clk-lpc18xx-cgu.c @@ -374,25 +374,23 @@ static unsigned long lpc18xx_pll0_recalc_rate(struct clk_hw *hw, return 0; } -static int lpc18xx_pll0_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) +static long lpc18xx_pll0_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) { unsigned long m; - if (req->best_parent_rate < req->rate) { + if (*prate < rate) { pr_warn("%s: pll dividers not supported\n", __func__); return -EINVAL; } - m = DIV_ROUND_UP_ULL(req->best_parent_rate, req->rate * 2); - if (m == 0 || m > LPC18XX_PLL0_MSEL_MAX) { - pr_warn("%s: unable to support rate %lu\n", __func__, req->rate); + m = DIV_ROUND_UP_ULL(*prate, rate * 2); + if (m <= 0 && m > LPC18XX_PLL0_MSEL_MAX) { + pr_warn("%s: unable to support rate %lu\n", __func__, rate); return -EINVAL; } - req->rate = 2 * req->best_parent_rate * m; - - return 0; + return 2 * *prate * m; } static int lpc18xx_pll0_set_rate(struct clk_hw *hw, unsigned long rate, @@ -408,7 +406,7 @@ static int lpc18xx_pll0_set_rate(struct clk_hw *hw, unsigned long rate, } m = DIV_ROUND_UP_ULL(parent_rate, rate * 2); - if (m == 0 || m > LPC18XX_PLL0_MSEL_MAX) { + if (m <= 0 && m > LPC18XX_PLL0_MSEL_MAX) { pr_warn("%s: unable to support rate %lu\n", __func__, rate); return -EINVAL; } @@ -449,7 +447,7 @@ static int lpc18xx_pll0_set_rate(struct clk_hw *hw, unsigned long rate, static const struct clk_ops lpc18xx_pll0_ops = { .recalc_rate = lpc18xx_pll0_recalc_rate, - .determine_rate = lpc18xx_pll0_determine_rate, + .round_rate = lpc18xx_pll0_round_rate, .set_rate = lpc18xx_pll0_set_rate, }; diff --git a/drivers/clocksource/clps711x-timer.c b/drivers/clocksource/clps711x-timer.c index bbceb0289d45..e95fdc49c226 100644 --- a/drivers/clocksource/clps711x-timer.c +++ b/drivers/clocksource/clps711x-timer.c @@ -78,33 +78,24 @@ static int __init clps711x_timer_init(struct device_node *np) unsigned int irq = irq_of_parse_and_map(np, 0); struct clk *clock = of_clk_get(np, 0); void __iomem *base = of_iomap(np, 0); - int ret = 0; if (!base) return -ENOMEM; - if (!irq) { - ret = -EINVAL; - goto unmap_io; - } - if (IS_ERR(clock)) { - ret = PTR_ERR(clock); - goto unmap_io; - } + if (!irq) + return -EINVAL; + if (IS_ERR(clock)) + return PTR_ERR(clock); switch (of_alias_get_id(np, "timer")) { case CLPS711X_CLKSRC_CLOCKSOURCE: clps711x_clksrc_init(clock, base); break; case CLPS711X_CLKSRC_CLOCKEVENT: - ret = _clps711x_clkevt_init(clock, base, irq); - break; + return _clps711x_clkevt_init(clock, base, irq); default: - ret = -EINVAL; - break; + return -EINVAL; } -unmap_io: - iounmap(base); - return ret; + return 0; } TIMER_OF_DECLARE(clps711x, "cirrus,ep7209-timer", clps711x_timer_init); diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer-vf-pit.c index c37afdfb477f..fef0bb4e0c8c 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -35,30 +35,30 @@ static unsigned long cycle_per_jiffy; static inline void pit_timer_enable(void) { - writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL); + __raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL); } static inline void pit_timer_disable(void) { - writel(0, clkevt_base + PITTCTRL); + __raw_writel(0, clkevt_base + PITTCTRL); } static inline void pit_irq_acknowledge(void) { - writel(PITTFLG_TIF, clkevt_base + PITTFLG); + __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); } static u64 notrace pit_read_sched_clock(void) { - return ~readl(clksrc_base + PITCVAL); + return ~__raw_readl(clksrc_base + PITCVAL); } static int __init pit_clocksource_init(unsigned long rate) { /* set the max load value and start the clock source counter */ - writel(0, clksrc_base + PITTCTRL); - writel(~0UL, clksrc_base + PITLDVAL); - writel(PITTCTRL_TEN, clksrc_base + PITTCTRL); + __raw_writel(0, clksrc_base + PITTCTRL); + __raw_writel(~0UL, clksrc_base + PITLDVAL); + __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL); sched_clock_register(pit_read_sched_clock, 32, rate); return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate, @@ -76,7 +76,7 @@ static int pit_set_next_event(unsigned long delta, * hardware requirement. */ pit_timer_disable(); - writel(delta - 1, clkevt_base + PITLDVAL); + __raw_writel(delta - 1, clkevt_base + PITLDVAL); pit_timer_enable(); return 0; @@ -132,8 +132,8 @@ static struct irqaction pit_timer_irq = { static int __init pit_clockevent_init(unsigned long rate, int irq) { - writel(0, clkevt_base + PITTCTRL); - writel(PITTFLG_TIF, clkevt_base + PITTFLG); + __raw_writel(0, clkevt_base + PITTCTRL); + __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); BUG_ON(setup_irq(irq, &pit_timer_irq)); @@ -189,7 +189,7 @@ static int __init pit_timer_init(struct device_node *np) cycle_per_jiffy = clk_rate / (HZ); /* enable the pit module */ - writel(~PITMCR_MDIS, timer_base + PITMCR); + __raw_writel(~PITMCR_MDIS, timer_base + PITMCR); ret = pit_clocksource_init(clk_rate); if (ret) diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index ab6f3bef978b..06302eaa3e94 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -1092,10 +1092,10 @@ static void update_qos_request(enum freq_qos_req_type type) continue; req = policy->driver_data; - if (!req) { - cpufreq_cpu_put(policy); + cpufreq_cpu_put(policy); + + if (!req) continue; - } if (hwp_active) intel_pstate_get_hwp_max(i, &turbo_max, &max_state); @@ -1114,8 +1114,6 @@ static void update_qos_request(enum freq_qos_req_type type) if (freq_qos_update_request(req, freq) < 0) pr_warn("Failed to update freq constraint: CPU%d\n", i); - - cpufreq_cpu_put(policy); } } diff --git a/drivers/cpufreq/longhaul.c b/drivers/cpufreq/longhaul.c index a9887011f1fa..92d92e67ae0a 100644 --- a/drivers/cpufreq/longhaul.c +++ b/drivers/cpufreq/longhaul.c @@ -956,9 +956,6 @@ static void __exit longhaul_exit(void) struct cpufreq_policy *policy = cpufreq_cpu_get(0); int i; - if (unlikely(!policy)) - return; - for (i = 0; i < numscales; i++) { if (mults[i] == maxmult) { struct cpufreq_freqs freqs; diff --git a/drivers/cpuidle/governors/menu.c b/drivers/cpuidle/governors/menu.c index 29c941933840..658c9a03d006 100644 --- a/drivers/cpuidle/governors/menu.c +++ b/drivers/cpuidle/governors/menu.c @@ -261,17 +261,20 @@ again: * * This can deal with workloads that have long pauses interspersed * with sporadic activity with a bunch of short pauses. - * - * However, if the number of remaining samples is too small to exclude - * any more outliers, allow the deepest available idle state to be - * selected because there are systems where the time spent by CPUs in - * deep idle states is correlated to the maximum frequency the CPUs - * can get to. On those systems, shallow idle states should be avoided - * unless there is a clear indication that the given CPU is most likley - * going to be woken up shortly. */ - if (divisor * 4 <= INTERVALS * 3) + if (divisor * 4 <= INTERVALS * 3) { + /* + * If there are sufficiently many data points still under + * consideration after the outliers have been eliminated, + * returning without a prediction would be a mistake because it + * is likely that the next interval will not exceed the current + * maximum, so return the latter in that case. + */ + if (divisor >= INTERVALS / 2) + return max; + return UINT_MAX; + } thresh = max - 1; goto again; diff --git a/drivers/crypto/atmel-tdes.c b/drivers/crypto/atmel-tdes.c index 674e1ca8383a..1a6c86ae6148 100644 --- a/drivers/crypto/atmel-tdes.c +++ b/drivers/crypto/atmel-tdes.c @@ -565,7 +565,7 @@ static int atmel_tdes_crypt_start(struct atmel_tdes_dev *dd) if (err && (dd->flags & TDES_FLAGS_FAST)) { dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE); - dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE); + dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_TO_DEVICE); } return err; diff --git a/drivers/crypto/msm/qcedev_smmu.c b/drivers/crypto/msm/qcedev_smmu.c index 7039bce67c5c..8d4844becc85 100644 --- a/drivers/crypto/msm/qcedev_smmu.c +++ b/drivers/crypto/msm/qcedev_smmu.c @@ -329,6 +329,10 @@ int qcedev_check_and_map_buffer(void *handle, mapped_size = binfo->ion_buf.mapped_buf_size; atomic_inc(&binfo->ref_count); + /* Add buffer mapping information to regd buffer list */ + mutex_lock(&qce_hndl->registeredbufs.lock); + list_add_tail(&binfo->list, &qce_hndl->registeredbufs.list); + mutex_unlock(&qce_hndl->registeredbufs.lock); } /* Make sure the offset is within the mapped range */ @@ -340,13 +344,6 @@ int qcedev_check_and_map_buffer(void *handle, goto unmap; } - if (!found) { - /* Add buffer mapping information to regd buffer list */ - mutex_lock(&qce_hndl->registeredbufs.lock); - list_add_tail(&binfo->list, &qce_hndl->registeredbufs.list); - mutex_unlock(&qce_hndl->registeredbufs.lock); - } - /* return the mapped virtual address adjusted by offset */ *vaddr += offset; @@ -355,6 +352,9 @@ int qcedev_check_and_map_buffer(void *handle, unmap: if (!found) { qcedev_unmap_buffer(handle, mem_client, binfo); + mutex_lock(&qce_hndl->registeredbufs.lock); + list_del(&binfo->list); + mutex_unlock(&qce_hndl->registeredbufs.lock); } error: diff --git a/drivers/crypto/qat/qat_common/adf_ctl_drv.c b/drivers/crypto/qat/qat_common/adf_ctl_drv.c index ef0e482ee04f..abc7a7f64d64 100644 --- a/drivers/crypto/qat/qat_common/adf_ctl_drv.c +++ b/drivers/crypto/qat/qat_common/adf_ctl_drv.c @@ -68,7 +68,7 @@ static long adf_ctl_ioctl(struct file *fp, unsigned int cmd, unsigned long arg); static const struct file_operations adf_ctl_ops = { .owner = THIS_MODULE, .unlocked_ioctl = adf_ctl_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = adf_ctl_ioctl, }; struct adf_ctl_drv_info { diff --git a/drivers/dax/super.c b/drivers/dax/super.c index c54bb58de20c..5005b92b197d 100644 --- a/drivers/dax/super.c +++ b/drivers/dax/super.c @@ -348,26 +348,6 @@ size_t dax_copy_to_iter(struct dax_device *dax_dev, pgoff_t pgoff, void *addr, } EXPORT_SYMBOL_GPL(dax_copy_to_iter); -int dax_zero_page_range(struct dax_device *dax_dev, pgoff_t pgoff, - size_t nr_pages) -{ - if (!dax_alive(dax_dev)) - return -ENXIO; - - if (!dax_dev->ops->zero_page_range) - return -EOPNOTSUPP; - /* - * There are no callers that want to zero more than one page as of now. - * Once users are there, this check can be removed after the - * device mapper code has been updated to split ranges across targets. - */ - if (nr_pages != 1) - return -EIO; - - return dax_dev->ops->zero_page_range(dax_dev, pgoff, nr_pages); -} -EXPORT_SYMBOL_GPL(dax_zero_page_range); - #ifdef CONFIG_ARCH_HAS_PMEM_API void arch_wb_cache_pmem(void *addr, size_t size); void dax_flush(struct dax_device *dax_dev, void *addr, size_t size) diff --git a/drivers/devfreq/arm-memlat-mon.c b/drivers/devfreq/arm-memlat-mon.c index 1ab4a88e4fa0..4fc8f76918e4 100644 --- a/drivers/devfreq/arm-memlat-mon.c +++ b/drivers/devfreq/arm-memlat-mon.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2014-2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved. */ #define pr_fmt(fmt) "arm-memlat-mon: " fmt @@ -126,7 +126,6 @@ struct memlat_mon { * @mons: All of the memlat_mon structs representing * the different voters who share this cpu_grp. * @mons_lock: A lock used to protect the @mons. - * @init_mons_lock: A lock used to protect the @mons in probe routine. */ struct memlat_cpu_grp { cpumask_t cpus; @@ -144,7 +143,6 @@ struct memlat_cpu_grp { unsigned int num_active_mons; struct memlat_mon *mons; struct mutex mons_lock; - struct mutex init_mons_lock; spinlock_t mon_active_lock; }; @@ -519,15 +517,11 @@ static int memlat_event_hotplug_going_down(unsigned int cpu) return ret; } -/* - * Note: We must be holding cpus_read_lock() before calling this function - * since we are using cpuslocked version of function inside it - */ static int memlat_event_cpu_hp_init(void) { int ret = 0; - ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN, + ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "MEMLAT_EVENT", memlat_event_hotplug_coming_up, memlat_event_hotplug_going_down); @@ -857,7 +851,6 @@ static int memlat_cpu_grp_probe(struct platform_device *pdev) return -ENOMEM; mutex_init(&cpu_grp->mons_lock); - mutex_init(&cpu_grp->init_mons_lock); spin_lock_init(&cpu_grp->mon_active_lock); cpu_grp->update_ms = DEFAULT_UPDATE_MS; @@ -893,7 +886,7 @@ static int memlat_mon_probe(struct platform_device *pdev, bool is_compute) return -ENODEV; } - mutex_lock(&cpu_grp->init_mons_lock); + mutex_lock(&cpu_grp->mons_lock); mon = &cpu_grp->mons[cpu_grp->num_inited_mons]; spin_lock_irqsave(&cpu_grp->mon_active_lock, flags); mon->is_active = false; @@ -1010,7 +1003,7 @@ static int memlat_mon_probe(struct platform_device *pdev, bool is_compute) cpu_grp->num_inited_mons++; unlock_out: - mutex_unlock(&cpu_grp->init_mons_lock); + mutex_unlock(&cpu_grp->mons_lock); return ret; } diff --git a/drivers/devfreq/bimc-bwmon.c b/drivers/devfreq/bimc-bwmon.c index f7be1c0353d2..668477348ae9 100644 --- a/drivers/devfreq/bimc-bwmon.c +++ b/drivers/devfreq/bimc-bwmon.c @@ -882,7 +882,7 @@ int __suspend_bw_hwmon(struct bw_hwmon *hw, enum mon_reg_type type) struct bwmon *m = to_bwmon(hw); mon_irq_disable(m, type); - disable_irq(m->irq); + free_irq(m->irq, m); mon_disable(m, type); mon_irq_clear(m, type); @@ -908,6 +908,7 @@ static __always_inline int __resume_bw_hwmon(struct bw_hwmon *hw, enum mon_reg_type type) { struct bwmon *m = to_bwmon(hw); + int ret; irq_handler_t handler; switch (type) { @@ -923,7 +924,15 @@ int __resume_bw_hwmon(struct bw_hwmon *hw, enum mon_reg_type type) } mon_clear(m, false, type); - enable_irq(m->irq); + ret = request_threaded_irq(m->irq, handler, bwmon_intr_thread, + IRQF_ONESHOT | IRQF_SHARED, + dev_name(m->dev), m); + if (ret < 0) { + dev_err(m->dev, "Unable to register interrupt handler! (%d)\n", + ret); + return ret; + } + mon_irq_enable(m, type); mon_enable(m, type); diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index 81709add4b0e..88afaed2cb61 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -70,28 +70,28 @@ static struct devfreq *find_device_devfreq(struct device *dev) return ERR_PTR(-ENODEV); } -static long find_available_min_freq(struct devfreq *devfreq) +static unsigned long find_available_min_freq(struct devfreq *devfreq) { struct dev_pm_opp *opp; - long min_freq = 0; + unsigned long min_freq = 0; opp = dev_pm_opp_find_freq_ceil(devfreq->dev.parent, &min_freq); if (IS_ERR(opp)) - min_freq = PTR_ERR(opp); + min_freq = 0; else dev_pm_opp_put(opp); return min_freq; } -static long find_available_max_freq(struct devfreq *devfreq) +static unsigned long find_available_max_freq(struct devfreq *devfreq) { struct dev_pm_opp *opp; - long max_freq = LONG_MAX; + unsigned long max_freq = ULONG_MAX; opp = dev_pm_opp_find_freq_floor(devfreq->dev.parent, &max_freq); if (IS_ERR(opp)) - max_freq = PTR_ERR(opp); + max_freq = 0; else dev_pm_opp_put(opp); @@ -318,7 +318,7 @@ static int devfreq_set_target(struct devfreq *devfreq, unsigned long new_freq, devfreq->previous_freq = new_freq; - if (devfreq->suspend_freq >= devfreq->scaling_min_freq) + if (devfreq->suspend_freq) devfreq->resume_freq = new_freq; return err; @@ -552,23 +552,18 @@ static int devfreq_notifier_call(struct notifier_block *nb, unsigned long type, { struct devfreq *devfreq = container_of(nb, struct devfreq, nb); int err = -EINVAL; - long freq; mutex_lock(&devfreq->lock); - freq = find_available_min_freq(devfreq); - if (freq < 0) { - devfreq->scaling_min_freq = 0; + devfreq->scaling_min_freq = find_available_min_freq(devfreq); + if (!devfreq->scaling_min_freq) goto out; - } - devfreq->scaling_min_freq = freq; - freq = find_available_max_freq(devfreq); - if (freq < 0) { + devfreq->scaling_max_freq = find_available_max_freq(devfreq); + if (!devfreq->scaling_max_freq) { devfreq->scaling_max_freq = ULONG_MAX; goto out; } - devfreq->scaling_max_freq = freq; err = update_devfreq(devfreq); @@ -621,7 +616,6 @@ struct devfreq *devfreq_add_device(struct device *dev, struct devfreq *devfreq; struct devfreq_governor *governor; int err = 0; - long freq; if (!dev || !profile || !governor_name) { dev_err(dev, "%s: Invalid parameters.\n", __func__); @@ -666,21 +660,21 @@ struct devfreq *devfreq_add_device(struct device *dev, mutex_lock(&devfreq->lock); } - freq = find_available_min_freq(devfreq); - if (freq < 0) { + devfreq->scaling_min_freq = find_available_min_freq(devfreq); + if (!devfreq->scaling_min_freq) { mutex_unlock(&devfreq->lock); err = -EINVAL; goto err_dev; } - devfreq->min_freq = devfreq->scaling_min_freq = freq; + devfreq->min_freq = devfreq->scaling_min_freq; - freq = find_available_max_freq(devfreq); - if (freq < 0) { + devfreq->scaling_max_freq = find_available_max_freq(devfreq); + if (!devfreq->scaling_max_freq) { mutex_unlock(&devfreq->lock); err = -EINVAL; goto err_dev; } - devfreq->max_freq = devfreq->scaling_max_freq = freq; + devfreq->max_freq = devfreq->scaling_max_freq; devfreq->suspend_freq = dev_pm_opp_get_suspend_opp_freq(dev); atomic_set(&devfreq->suspend_count, 0); @@ -912,7 +906,7 @@ int devfreq_suspend_device(struct devfreq *devfreq) return ret; } - if (devfreq->suspend_freq >= devfreq->scaling_min_freq) { + if (devfreq->suspend_freq) { mutex_lock(&devfreq->lock); ret = devfreq_set_target(devfreq, devfreq->suspend_freq, 0); mutex_unlock(&devfreq->lock); diff --git a/drivers/devfreq/governor_bw_hwmon.c b/drivers/devfreq/governor_bw_hwmon.c index 261b40843ff3..2acdb0a3fe5a 100644 --- a/drivers/devfreq/governor_bw_hwmon.c +++ b/drivers/devfreq/governor_bw_hwmon.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. */ #define pr_fmt(fmt) "bw-hwmon: " fmt @@ -80,8 +80,6 @@ static DEFINE_MUTEX(list_lock); static int use_cnt; static DEFINE_MUTEX(state_lock); -static DEFINE_MUTEX(event_handle_lock); - #define show_attr(name) \ static ssize_t name##_show(struct device *dev, \ struct device_attribute *attr, char *buf) \ @@ -867,7 +865,7 @@ static int devfreq_bw_hwmon_ev_handler(struct devfreq *df, struct hwmon_node *node; struct bw_hwmon *hw; - mutex_lock(&event_handle_lock); + mutex_lock(&state_lock); switch (event) { case DEVFREQ_GOV_START: @@ -941,7 +939,7 @@ static int devfreq_bw_hwmon_ev_handler(struct devfreq *df, } out: - mutex_unlock(&event_handle_lock); + mutex_unlock(&state_lock); return ret; } diff --git a/drivers/dio/dio.c b/drivers/dio/dio.c index 1414a1c81834..d07bceb3e34b 100644 --- a/drivers/dio/dio.c +++ b/drivers/dio/dio.c @@ -141,8 +141,7 @@ int __init dio_find(int deviceid) else va = ioremap(pa, PAGE_SIZE); - if (copy_from_kernel_nofault(&i, - (unsigned char *)va + DIO_IDOFF, 1)) { + if (probe_kernel_read(&i, (unsigned char *)va + DIO_IDOFF, 1)) { if (scode >= DIOII_SCBASE) iounmap(va); continue; /* no board present at that select code */ @@ -215,8 +214,7 @@ static int __init dio_init(void) else va = ioremap(pa, PAGE_SIZE); - if (copy_from_kernel_nofault(&i, - (unsigned char *)va + DIO_IDOFF, 1)) { + if (probe_kernel_read(&i, (unsigned char *)va + DIO_IDOFF, 1)) { if (scode >= DIOII_SCBASE) iounmap(va); continue; /* no board present at that select code */ diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c index 6541c28ede73..9b774277b75e 100644 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@ -468,7 +468,9 @@ static const struct file_operations dma_buf_fops = { .llseek = dma_buf_llseek, .poll = dma_buf_poll, .unlocked_ioctl = dma_buf_ioctl, - .compat_ioctl = compat_ptr_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = dma_buf_ioctl, +#endif .show_fdinfo = dma_buf_show_fdinfo, }; diff --git a/drivers/dma-buf/sw_sync.c b/drivers/dma-buf/sw_sync.c index 7f5ed1aa7a9f..7e7356970d5f 100644 --- a/drivers/dma-buf/sw_sync.c +++ b/drivers/dma-buf/sw_sync.c @@ -408,5 +408,5 @@ const struct file_operations sw_sync_debugfs_fops = { .open = sw_sync_debugfs_open, .release = sw_sync_debugfs_release, .unlocked_ioctl = sw_sync_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = sw_sync_ioctl, }; diff --git a/drivers/dma-buf/sync_file.c b/drivers/dma-buf/sync_file.c index f0c822952c20..992c15c016dd 100644 --- a/drivers/dma-buf/sync_file.c +++ b/drivers/dma-buf/sync_file.c @@ -481,5 +481,5 @@ static const struct file_operations sync_file_fops = { .release = sync_file_release, .poll = sync_file_poll, .unlocked_ioctl = sync_file_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = sync_file_ioctl, }; diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index 6cbb018c215a..25d65f64cd50 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -474,25 +474,6 @@ dw_edma_device_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t paddr, return dw_edma_device_transfer(&xfer); } -static void dw_hdma_set_callback_result(struct virt_dma_desc *vd, - enum dmaengine_tx_result result) -{ - u32 residue = 0; - struct dw_edma_desc *desc; - struct dmaengine_result *res; - - if (!vd->tx.callback_result) - return; - - desc = vd2dw_edma_desc(vd); - if (desc) - residue = desc->alloc_sz - desc->xfer_sz; - - res = &vd->tx_result; - res->result = result; - res->residue = residue; -} - static void dw_edma_done_interrupt(struct dw_edma_chan *chan) { struct dw_edma_desc *desc; @@ -508,8 +489,6 @@ static void dw_edma_done_interrupt(struct dw_edma_chan *chan) case EDMA_REQ_NONE: desc = vd2dw_edma_desc(vd); if (!desc->chunks_alloc) { - dw_hdma_set_callback_result(vd, - DMA_TRANS_NOERROR); list_del(&vd->node); vchan_cookie_complete(vd); } @@ -548,7 +527,6 @@ static void dw_edma_abort_interrupt(struct dw_edma_chan *chan) spin_lock_irqsave(&chan->vc.lock, flags); vd = vchan_next_desc(&chan->vc); if (vd) { - dw_hdma_set_callback_result(vd, DMA_TRANS_ABORTED); list_del(&vd->node); vchan_cookie_complete(vd); } diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c index 0e570303d1da..827a1a9907b6 100644 --- a/drivers/dma/mv_xor.c +++ b/drivers/dma/mv_xor.c @@ -1013,7 +1013,7 @@ static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan) dma_async_device_unregister(&mv_chan->dmadev); - dma_free_wc(dev, MV_XOR_POOL_SIZE, + dma_free_coherent(dev, MV_XOR_POOL_SIZE, mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); dma_unmap_single(dev, mv_chan->dummy_src_addr, MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); @@ -1164,7 +1164,7 @@ mv_xor_channel_add(struct mv_xor_device *xordev, err_free_irq: free_irq(mv_chan->irq, mv_chan); err_free_dma: - dma_free_wc(&pdev->dev, MV_XOR_POOL_SIZE, + dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE, mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); err_unmap_dst: dma_unmap_single(dma_dev->dev, mv_chan->dummy_dst_addr, diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c index eb9aea7851ff..44e2e7de129e 100644 --- a/drivers/dma/qcom/gpi.c +++ b/drivers/dma/qcom/gpi.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2525,12 +2524,6 @@ struct dma_async_tx_descriptor *gpi_prep_slave_sg(struct dma_chan *chan, for_each_sg(sgl, sg, sg_len, i) { tre = sg_virt(sg); - if (!tre) { - kfree(gpi_desc); - GPII_ERR(gpii, gpii_chan->chid, "TRE address is null\n"); - return NULL; - } - if (sg_len == 1) { tre_type = MSM_GPI_TRE_TYPE(((struct msm_gpi_tre *)tre)); diff --git a/drivers/dma/sh/shdma-base.c b/drivers/dma/sh/shdma-base.c index 2cbc886d2211..c51de498b5b4 100644 --- a/drivers/dma/sh/shdma-base.c +++ b/drivers/dma/sh/shdma-base.c @@ -129,25 +129,12 @@ static dma_cookie_t shdma_tx_submit(struct dma_async_tx_descriptor *tx) const struct shdma_ops *ops = sdev->ops; dev_dbg(schan->dev, "Bring up channel %d\n", schan->id); - - ret = ops->setup_xfer(schan, schan->slave_id); - if (ret < 0) { - dev_err(schan->dev, "setup_xfer failed: %d\n", ret); - - /* Remove chunks from the queue and mark them as idle */ - list_for_each_entry_safe(chunk, c, &schan->ld_queue, node) { - if (chunk->cookie == cookie) { - chunk->mark = DESC_IDLE; - list_move(&chunk->node, &schan->ld_free); - } - } - - schan->pm_state = SHDMA_PM_ESTABLISHED; - ret = pm_runtime_put(schan->dev); - - spin_unlock_irq(&schan->chan_lock); - return ret; - } + /* + * TODO: .xfer_setup() might fail on some platforms. + * Make it int then, on error remove chunks from the + * queue again + */ + ops->setup_xfer(schan, schan->slave_id); if (schan->pm_state == SHDMA_PM_PENDING) shdma_chan_xfer_ld_queue(schan); diff --git a/drivers/dma/sh/shdmac.c b/drivers/dma/sh/shdmac.c index 2b9774ae7fd3..5aafe548ca5f 100644 --- a/drivers/dma/sh/shdmac.c +++ b/drivers/dma/sh/shdmac.c @@ -301,30 +301,21 @@ static bool sh_dmae_channel_busy(struct shdma_chan *schan) return dmae_is_busy(sh_chan); } -static int sh_dmae_setup_xfer(struct shdma_chan *schan, int slave_id) +static void sh_dmae_setup_xfer(struct shdma_chan *schan, + int slave_id) { struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, shdma_chan); - int ret = 0; if (slave_id >= 0) { const struct sh_dmae_slave_config *cfg = sh_chan->config; - ret = dmae_set_dmars(sh_chan, cfg->mid_rid); - if (ret < 0) - goto END; - - ret = dmae_set_chcr(sh_chan, cfg->chcr); - if (ret < 0) - goto END; - + dmae_set_dmars(sh_chan, cfg->mid_rid); + dmae_set_chcr(sh_chan, cfg->chcr); } else { dmae_init(sh_chan); } - -END: - return ret; } /* diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c index 6e2f38a15efe..3bd8259aa030 100644 --- a/drivers/edac/altera_edac.c +++ b/drivers/edac/altera_edac.c @@ -1247,22 +1247,10 @@ altr_check_ocram_deps_init(struct altr_edac_device_dev *device) if (ret) return ret; - /* - * Verify that OCRAM has been initialized. - * During a warm reset, OCRAM contents are retained, but the control - * and status registers are reset to their default values. Therefore, - * ECC must be explicitly re-enabled in the control register. - * Error condition: if INITCOMPLETEA is clear and ECC_EN is already set. - */ + /* Verify OCRAM has been initialized */ if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA, - (base + ALTR_A10_ECC_INITSTAT_OFST))) { - if (!ecc_test_bits(ALTR_A10_ECC_EN, - (base + ALTR_A10_ECC_CTRL_OFST))) - ecc_set_bits(ALTR_A10_ECC_EN, - (base + ALTR_A10_ECC_CTRL_OFST)); - else - return -ENODEV; - } + (base + ALTR_A10_ECC_INITSTAT_OFST))) + return -ENODEV; /* Enable IRQ on Single Bit Error */ writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST)); @@ -1432,7 +1420,7 @@ static const struct edac_device_prv_data a10_enetecc_data = { .ue_set_mask = ALTR_A10_ECC_TDERRA, .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, .ecc_irq_handler = altr_edac_a10_ecc_irq, - .inject_fops = &altr_edac_a10_device_inject_fops, + .inject_fops = &altr_edac_a10_device_inject2_fops, }; #endif /* CONFIG_EDAC_ALTERA_ETHERNET */ @@ -1522,7 +1510,7 @@ static const struct edac_device_prv_data a10_usbecc_data = { .ue_set_mask = ALTR_A10_ECC_TDERRA, .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, .ecc_irq_handler = altr_edac_a10_ecc_irq, - .inject_fops = &altr_edac_a10_device_inject_fops, + .inject_fops = &altr_edac_a10_device_inject2_fops, }; #endif /* CONFIG_EDAC_ALTERA_USB */ diff --git a/drivers/extcon/extcon-adc-jack.c b/drivers/extcon/extcon-adc-jack.c index 26b083ccc94b..0317b614b680 100644 --- a/drivers/extcon/extcon-adc-jack.c +++ b/drivers/extcon/extcon-adc-jack.c @@ -162,8 +162,6 @@ static int adc_jack_remove(struct platform_device *pdev) { struct adc_jack_data *data = platform_get_drvdata(pdev); - if (data->wakeup_source) - device_init_wakeup(&pdev->dev, false); free_irq(data->irq, data); cancel_work_sync(&data->handler.work); diff --git a/drivers/firmware/arm_scmi/scmi_pm_domain.c b/drivers/firmware/arm_scmi/scmi_pm_domain.c index 5a9794bbe2c2..b0c8962b9885 100644 --- a/drivers/firmware/arm_scmi/scmi_pm_domain.c +++ b/drivers/firmware/arm_scmi/scmi_pm_domain.c @@ -53,7 +53,7 @@ static int scmi_pd_power_off(struct generic_pm_domain *domain) static int scmi_pm_domain_probe(struct scmi_device *sdev) { - int num_domains, i, ret; + int num_domains, i; struct device *dev = &sdev->dev; struct device_node *np = dev->of_node; struct scmi_pm_domain *scmi_pd; @@ -106,18 +106,9 @@ static int scmi_pm_domain_probe(struct scmi_device *sdev) scmi_pd_data->domains = domains; scmi_pd_data->num_domains = num_domains; - ret = of_genpd_add_provider_onecell(np, scmi_pd_data); - if (ret) - goto err_rm_genpds; - dev_set_drvdata(dev, scmi_pd_data); - return 0; -err_rm_genpds: - for (i = num_domains - 1; i >= 0; i--) - pm_genpd_remove(domains[i]); - - return ret; + return of_genpd_add_provider_onecell(np, scmi_pd_data); } static void scmi_pm_domain_remove(struct scmi_device *sdev) diff --git a/drivers/firmware/meson/meson_sm.c b/drivers/firmware/meson/meson_sm.c index f4a101016444..a63ce2815d7d 100644 --- a/drivers/firmware/meson/meson_sm.c +++ b/drivers/firmware/meson/meson_sm.c @@ -223,16 +223,11 @@ EXPORT_SYMBOL(meson_sm_call_write); struct meson_sm_firmware *meson_sm_get(struct device_node *sm_node) { struct platform_device *pdev = of_find_device_by_node(sm_node); - struct meson_sm_firmware *fw; if (!pdev) return NULL; - fw = platform_get_drvdata(pdev); - - put_device(&pdev->dev); - - return fw; + return platform_get_drvdata(pdev); } EXPORT_SYMBOL_GPL(meson_sm_get); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 753408bb4a2c..06c88dbc5a4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1572,9 +1572,10 @@ int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd, struct amdgpu_device *adev; adev = (struct amdgpu_device *)kgd; - if (atomic_read_acquire(&adev->gmc.vm_fault_info_updated) == 1) { + if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) { *mem = *adev->gmc.vm_fault_info; - atomic_set_release(&adev->gmc.vm_fault_info_updated, 0); + mb(); + atomic_set(&adev->gmc.vm_fault_info_updated, 0); } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index f517cfa25309..0c3d9bc3a641 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1042,7 +1042,7 @@ static int gmc_v7_0_sw_init(void *handle) GFP_KERNEL); if (!adev->gmc.vm_fault_info) return -ENOMEM; - atomic_set_release(&adev->gmc.vm_fault_info_updated, 0); + atomic_set(&adev->gmc.vm_fault_info_updated, 0); return 0; } @@ -1272,7 +1272,7 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) - && !atomic_read_acquire(&adev->gmc.vm_fault_info_updated)) { + && !atomic_read(&adev->gmc.vm_fault_info_updated)) { struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, @@ -1288,7 +1288,8 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, info->prot_read = protections & 0x8 ? true : false; info->prot_write = protections & 0x10 ? true : false; info->prot_exec = protections & 0x20 ? true : false; - atomic_set_release(&adev->gmc.vm_fault_info_updated, 1); + mb(); + atomic_set(&adev->gmc.vm_fault_info_updated, 1); } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index d38171931a3e..2975331a7b86 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1175,7 +1175,7 @@ static int gmc_v8_0_sw_init(void *handle) GFP_KERNEL); if (!adev->gmc.vm_fault_info) return -ENOMEM; - atomic_set_release(&adev->gmc.vm_fault_info_updated, 0); + atomic_set(&adev->gmc.vm_fault_info_updated, 0); return 0; } @@ -1464,7 +1464,7 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) - && !atomic_read_acquire(&adev->gmc.vm_fault_info_updated)) { + && !atomic_read(&adev->gmc.vm_fault_info_updated)) { struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, @@ -1480,7 +1480,8 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, info->prot_read = protections & 0x8 ? true : false; info->prot_write = protections & 0x10 ? true : false; info->prot_exec = protections & 0x20 ? true : false; - atomic_set_release(&adev->gmc.vm_fault_info_updated, 1); + mb(); + atomic_set(&adev->gmc.vm_fault_info_updated, 1); } return 0; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index fb5fca3d2149..a845eda14ece 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -49,7 +49,7 @@ static const char kfd_dev_name[] = "kfd"; static const struct file_operations kfd_fops = { .owner = THIS_MODULE, .unlocked_ioctl = kfd_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = kfd_ioctl, .open = kfd_open, .mmap = kfd_mmap, }; @@ -1796,10 +1796,8 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) unsigned int usize, asize; int retcode = -EINVAL; - if (nr >= AMDKFD_CORE_IOCTL_COUNT) { - retcode = -ENOTTY; + if (nr >= AMDKFD_CORE_IOCTL_COUNT) goto err_i1; - } if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) { u32 amdkfd_size; @@ -1812,10 +1810,8 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) asize = amdkfd_size; cmd = ioctl->cmd; - } else { - retcode = -ENOTTY; + } else goto err_i1; - } dev_dbg(kfd_device, "ioctl cmd 0x%x (#%d), arg 0x%lx\n", cmd, nr, arg); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index f6012c378b46..c89326125d71 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -105,14 +105,7 @@ #define KFD_KERNEL_QUEUE_SIZE 2048 -/* KFD_UNMAP_LATENCY_MS is the timeout CP waiting for SDMA preemption. One XCC - * can be associated to 2 SDMA engines. queue_preemption_timeout_ms is the time - * driver waiting for CP returning the UNMAP_QUEUE fence. Thus the math is - * queue_preemption_timeout_ms = sdma_preemption_time * 2 + cp workload - * The format here makes CP workload 10% of total timeout - */ -#define KFD_UNMAP_LATENCY_MS \ - ((queue_preemption_timeout_ms - queue_preemption_timeout_ms / 10) >> 1) +#define KFD_UNMAP_LATENCY_MS (4000) /* * 512 = 0x200 diff --git a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c index 9991150c8201..194af3979679 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c @@ -346,7 +346,7 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state, u32 link_target, link_dwords; bool switch_context = gpu->exec_state != exec_state; bool switch_mmu_context = gpu->mmu_context != mmu_context; - unsigned int new_flush_seq = READ_ONCE(mmu_context->flush_seq); + unsigned int new_flush_seq = READ_ONCE(gpu->mmu_context->flush_seq); bool need_flush = switch_mmu_context || gpu->flush_seq != new_flush_seq; bool has_blt = !!(gpu->identity.minor_features5 & chipMinorFeatures5_BLT_ENGINE); diff --git a/drivers/gpu/drm/etnaviv/etnaviv_dump.c b/drivers/gpu/drm/etnaviv/etnaviv_dump.c index 898f84a0fc30..8e86cbe52ef8 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_dump.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_dump.c @@ -159,8 +159,8 @@ void etnaviv_core_dump(struct etnaviv_gem_submit *submit) file_size += sizeof(*iter.hdr) * n_obj; /* Allocate the file in vmalloc memory, it's likely to be big */ - iter.start = __vmalloc(file_size, GFP_KERNEL | __GFP_NOWARN | - __GFP_NORETRY); + iter.start = __vmalloc(file_size, GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY, + PAGE_KERNEL); if (!iter.start) { mutex_unlock(&submit->mmu_context->lock); dev_warn(gpu->dev, "failed to allocate devcoredump file\n"); diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index 1c212ba0d753..afca5fc46020 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -51,6 +51,7 @@ struct decon_context { void __iomem *regs; unsigned long irq_flags; bool i80_if; + bool suspended; wait_queue_head_t wait_vsync_queue; atomic_t wait_vsync_event; @@ -84,6 +85,9 @@ static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx; + if (ctx->suspended) + return; + atomic_set(&ctx->wait_vsync_event, 1); /* @@ -151,6 +155,9 @@ static void decon_commit(struct exynos_drm_crtc *crtc) struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; u32 val, clkdiv; + if (ctx->suspended) + return; + /* nothing to do if we haven't set the mode yet */ if (mode->htotal == 0 || mode->vtotal == 0) return; @@ -212,6 +219,9 @@ static int decon_enable_vblank(struct exynos_drm_crtc *crtc) struct decon_context *ctx = crtc->ctx; u32 val; + if (ctx->suspended) + return -EPERM; + if (!test_and_set_bit(0, &ctx->irq_flags)) { val = readl(ctx->regs + VIDINTCON0); @@ -234,6 +244,9 @@ static void decon_disable_vblank(struct exynos_drm_crtc *crtc) struct decon_context *ctx = crtc->ctx; u32 val; + if (ctx->suspended) + return; + if (test_and_clear_bit(0, &ctx->irq_flags)) { val = readl(ctx->regs + VIDINTCON0); @@ -356,6 +369,9 @@ static void decon_atomic_begin(struct exynos_drm_crtc *crtc) struct decon_context *ctx = crtc->ctx; int i; + if (ctx->suspended) + return; + for (i = 0; i < WINDOWS_NR; i++) decon_shadow_protect_win(ctx, i, true); } @@ -375,6 +391,9 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, unsigned int cpp = fb->format->cpp[0]; unsigned int pitch = fb->pitches[0]; + if (ctx->suspended) + return; + /* * SHADOWCON/PRTCON register is used for enabling timing. * @@ -462,6 +481,9 @@ static void decon_disable_plane(struct exynos_drm_crtc *crtc, unsigned int win = plane->index; u32 val; + if (ctx->suspended) + return; + /* protect windows */ decon_shadow_protect_win(ctx, win, true); @@ -480,6 +502,9 @@ static void decon_atomic_flush(struct exynos_drm_crtc *crtc) struct decon_context *ctx = crtc->ctx; int i; + if (ctx->suspended) + return; + for (i = 0; i < WINDOWS_NR; i++) decon_shadow_protect_win(ctx, i, false); exynos_crtc_handle_event(crtc); @@ -506,6 +531,9 @@ static void decon_enable(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx; + if (!ctx->suspended) + return; + pm_runtime_get_sync(ctx->dev); decon_init(ctx); @@ -515,6 +543,8 @@ static void decon_enable(struct exynos_drm_crtc *crtc) decon_enable_vblank(ctx->crtc); decon_commit(ctx->crtc); + + ctx->suspended = false; } static void decon_disable(struct exynos_drm_crtc *crtc) @@ -522,6 +552,9 @@ static void decon_disable(struct exynos_drm_crtc *crtc) struct decon_context *ctx = crtc->ctx; int i; + if (ctx->suspended) + return; + /* * We need to make sure that all windows are disabled before we * suspend that connector. Otherwise we might try to scan from @@ -531,6 +564,8 @@ static void decon_disable(struct exynos_drm_crtc *crtc) decon_disable_plane(crtc, &ctx->planes[i]); pm_runtime_put_sync(ctx->dev); + + ctx->suspended = true; } static const struct exynos_drm_crtc_ops decon_crtc_ops = { @@ -648,6 +683,7 @@ static int decon_probe(struct platform_device *pdev) return -ENOMEM; ctx->dev = dev; + ctx->suspended = true; i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); if (i80_if_timings) diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index b046da2a5cb2..e67ead37d63e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -1122,7 +1122,7 @@ done: nvif_vmm_put(vmm, &old_mem->vma[1]); nvif_vmm_put(vmm, &old_mem->vma[0]); } - return ret; + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/nvkm/core/enum.c b/drivers/gpu/drm/nouveau/nvkm/core/enum.c index a23b40b27b81..b9581feb24cc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/enum.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/enum.c @@ -44,7 +44,7 @@ nvkm_snprintbf(char *data, int size, const struct nvkm_bitfield *bf, u32 value) bool space = false; while (size >= 1 && bf->name) { if (value & bf->mask) { - int this = scnprintf(data, size, "%s%s", + int this = snprintf(data, size, "%s%s", space ? " " : "", bf->name); size -= this; data += this; diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index 637a4f2a30af..a85470213b27 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c @@ -1411,7 +1411,7 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel, unsigned block_align, unsigned height_align, unsigned base_align, unsigned *l0_size, unsigned *mipmap_size) { - unsigned offset, i; + unsigned offset, i, level; unsigned width, height, depth, size; unsigned blocksize; unsigned nbx, nby; @@ -1423,7 +1423,7 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel, w0 = r600_mip_minify(w0, 0); h0 = r600_mip_minify(h0, 0); d0 = r600_mip_minify(d0, 0); - for (i = 0, offset = 0; i < nlevels; i++) { + for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) { width = r600_mip_minify(w0, i); nbx = r600_fmt_get_nblocksx(format, width); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c index d31e9d380967..0d29fe6f6035 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c @@ -3216,11 +3216,6 @@ static int vmw_cmd_check(struct vmw_private *dev_priv, cmd_id = header->id; - if (header->size > SVGA_CMD_MAX_DATASIZE) { - VMW_DEBUG_USER("SVGA3D command: %d is too big.\n", - cmd_id + SVGA_3D_CMD_BASE); - return -E2BIG; - } *size = header->size + sizeof(SVGA3dCmdHeader); cmd_id -= SVGA_3D_CMD_BASE; diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_validation.c b/drivers/gpu/drm/vmwgfx/vmwgfx_validation.c index a18b9bb0631c..f611b2290a1b 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_validation.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_validation.c @@ -339,10 +339,8 @@ int vmw_validation_add_resource(struct vmw_validation_context *ctx, } } node->res = vmw_resource_reference_unless_doomed(res); - if (!node->res) { - hash_del_rcu(&node->hash.head); + if (!node->res) return -ESRCH; - } node->first_usage = 1; if (!res->dev_priv->has_mob) { diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c index a37aa033ed98..3a898033c178 100644 --- a/drivers/gpu/msm/adreno.c +++ b/drivers/gpu/msm/adreno.c @@ -1743,12 +1743,6 @@ static int adreno_pm_suspend(struct device *dev) status = ops->pm_suspend(adreno_dev); mutex_unlock(&device->mutex); - if (status) - return status; - - kthread_flush_worker(device->events_worker); - flush_workqueue(kgsl_driver.mem_workqueue); - return status; } diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index 93bebbdb24fc..048e33de599c 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -2524,7 +2523,6 @@ int a6xx_perfcounter_update(struct adreno_device *adreno_dev, struct cpu_gpu_lock *lock = ptr; u32 *data = ptr + sizeof(*lock); int i, offset = 0; - u32 pending_pairs = 2; /* No of pairs to add: and */ if (cpu_gpu_lock(lock)) { cpu_gpu_unlock(lock); @@ -2548,13 +2546,6 @@ int a6xx_perfcounter_update(struct adreno_device *adreno_dev, offset += 2; } - /* Ensure there is enough space in the reglist buffer for new pairs */ - if ((offset + (pending_pairs * 2)) >= - (adreno_dev->pwrup_reglist->size / sizeof(u32))) { - cpu_gpu_unlock(lock); - return -ENOSPC; - } - /* * For all targets A6XX_RBBM_PERFCTR_CNTL needs to be the last entry, * so overwrite the existing A6XX_RBBM_PERFCNTL_CTRL and add it back to diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c index 07b1e1d24f45..8a4ea1752b24 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu.c +++ b/drivers/gpu/msm/adreno_a6xx_gmu.c @@ -593,7 +593,7 @@ static int find_vma_block(struct a6xx_gmu_device *gmu, u32 addr, u32 size) { int i; - for (i = 0; i < gmu->num_vmas; i++) { + for (i = 0; i < GMU_MEM_TYPE_MAX; i++) { struct gmu_vma_entry *vma = &gmu->vma[i]; if ((addr >= vma->start) && @@ -2685,13 +2685,10 @@ int a6xx_gmu_probe(struct kgsl_device *device, if (ret) goto error; - if (adreno_is_a650_family(adreno_dev)) { + if (adreno_is_a650_family(adreno_dev)) gmu->vma = a6xx_gmu_vma; - gmu->num_vmas = ARRAY_SIZE(a6xx_gmu_vma); - } else { + else gmu->vma = a6xx_gmu_vma_legacy; - gmu->num_vmas = ARRAY_SIZE(a6xx_gmu_vma_legacy); - } /* Map and reserve GMU CSRs registers */ ret = a6xx_gmu_reg_probe(adreno_dev); diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.h b/drivers/gpu/msm/adreno_a6xx_gmu.h index b671771c46b4..d39597683ec9 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu.h +++ b/drivers/gpu/msm/adreno_a6xx_gmu.h @@ -187,8 +187,6 @@ struct a6xx_gmu_device { /** @global_entries: To keep track of number of gmu buffers */ u32 global_entries; struct gmu_vma_entry *vma; - /** @num_vmas: Number of entries in the @vma array */ - u32 num_vmas; unsigned int log_wptr_retention; /** @cm3_fault: whether gmu received a cm3 fault interrupt */ atomic_t cm3_fault; diff --git a/drivers/gpu/msm/adreno_a6xx_rpmh.c b/drivers/gpu/msm/adreno_a6xx_rpmh.c index c7a4b3297e45..0594304d64ee 100644 --- a/drivers/gpu/msm/adreno_a6xx_rpmh.c +++ b/drivers/gpu/msm/adreno_a6xx_rpmh.c @@ -120,7 +120,6 @@ static void tcs_cmd_data(struct bcm *bcms, int count, u32 ab, u32 ib, u32 *data) { int i; - u64 total_width; for (i = 0; i < count; i++) { bool valid = true; @@ -146,11 +145,8 @@ static void tcs_cmd_data(struct bcm *bcms, int count, u32 ab, u32 ib, /* Multiple the bandwidth by the width of the connection */ avg = ((u64) ab) * bcms[i].width; - total_width = bcms[i].buswidth * bcms[i].channels; - /* And then divide by the total width across channels */ - if (total_width) - do_div(avg, (u32) total_width); + do_div(avg, bcms[i].buswidth * bcms[i].channels); peak = ((u64) ib) * bcms[i].width; do_div(peak, bcms[i].buswidth); diff --git a/drivers/gpu/msm/governor_gpubw_mon.c b/drivers/gpu/msm/governor_gpubw_mon.c index af437abf107e..fabcd56b3776 100644 --- a/drivers/gpu/msm/governor_gpubw_mon.c +++ b/drivers/gpu/msm/governor_gpubw_mon.c @@ -101,7 +101,7 @@ static int devfreq_gpubw_get_target(struct devfreq *df, int act_level; int norm_max_cycles; int norm_cycles; - int wait_active_percent = 0; + int wait_active_percent; int gpu_percent; /* * Normalized AB should at max usage be the gpu_bimc frequency in MHz. @@ -132,9 +132,8 @@ static int devfreq_gpubw_get_target(struct devfreq *df, (unsigned int) priv->bus.total_time; norm_cycles = (unsigned int)(priv->bus.ram_time + priv->bus.ram_wait) / (unsigned int) priv->bus.total_time; - if (priv->bus.ram_time) - wait_active_percent = (100 * (unsigned int)priv->bus.ram_wait) / - (unsigned int) priv->bus.ram_time; + wait_active_percent = (100 * (unsigned int)priv->bus.ram_wait) / + (unsigned int) priv->bus.ram_time; gpu_percent = (100 * (unsigned int)priv->bus.gpu_time) / (unsigned int) priv->bus.total_time; diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c index 99c3207530c5..60368d1ffcba 100644 --- a/drivers/gpu/msm/kgsl.c +++ b/drivers/gpu/msm/kgsl.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2008-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -349,14 +349,12 @@ static void kgsl_destroy_ion(struct kgsl_memdesc *memdesc) if (meta != NULL) { remove_dmabuf_list(meta); - dma_buf_unmap_attachment(meta->attach, memdesc->sgt, DMA_BIDIRECTIONAL); dma_buf_detach(meta->dmabuf, meta->attach); dma_buf_put(meta->dmabuf); kfree(meta); } memdesc->sgt = NULL; - entry->priv_data = NULL; } static const struct kgsl_memdesc_ops kgsl_dmabuf_ops = { @@ -687,11 +685,11 @@ int kgsl_context_init(struct kgsl_device_private *dev_priv, if (id == -ENOSPC) { /* * Before declaring that there are no contexts left try - * flushing the event worker just in case there are + * flushing the event workqueue just in case there are * detached contexts waiting to finish */ - kthread_flush_worker(device->events_worker); + flush_workqueue(device->events_wq); id = _kgsl_get_context_id(device); } @@ -2997,7 +2995,7 @@ static int kgsl_setup_dma_buf(struct kgsl_device *device, { int ret = 0; struct scatterlist *s; - struct sg_table *sg_table = NULL; + struct sg_table *sg_table; struct dma_buf_attachment *attach = NULL; struct kgsl_dma_buf_meta *meta; @@ -3039,6 +3037,8 @@ static int kgsl_setup_dma_buf(struct kgsl_device *device, goto out; } + dma_buf_unmap_attachment(attach, sg_table, DMA_BIDIRECTIONAL); + meta->table = sg_table; entry->priv_data = meta; entry->memdesc.sgt = sg_table; @@ -3093,9 +3093,6 @@ skip_access_check: out: if (ret) { - if (!IS_ERR_OR_NULL(sg_table)) - dma_buf_unmap_attachment(attach, sg_table, DMA_BIDIRECTIONAL); - if (!IS_ERR_OR_NULL(attach)) dma_buf_detach(dmabuf, attach); @@ -4057,9 +4054,9 @@ static unsigned long _gpu_set_svm_region(struct kgsl_process_private *private, return addr; } -unsigned long kgsl_get_align(struct kgsl_memdesc *memdesc) +static unsigned long get_align(struct kgsl_mem_entry *entry) { - u32 bit = kgsl_memdesc_get_align(memdesc); + int bit = kgsl_memdesc_get_align(&entry->memdesc); if (bit >= ilog2(SZ_2M)) return SZ_2M; @@ -4068,7 +4065,7 @@ unsigned long kgsl_get_align(struct kgsl_memdesc *memdesc) else if (bit >= ilog2(SZ_64K)) return SZ_64K; - return PAGE_SIZE; + return SZ_4K; } static unsigned long set_svm_area(struct file *file, @@ -4101,7 +4098,7 @@ static unsigned long get_svm_unmapped_area(struct file *file, { struct kgsl_device_private *dev_priv = file->private_data; struct kgsl_process_private *private = dev_priv->process_priv; - unsigned long align = kgsl_get_align(&entry->memdesc); + unsigned long align = get_align(entry); unsigned long ret, iova; u64 start = 0, end = 0; struct vm_area_struct *vma; @@ -4528,16 +4525,15 @@ int kgsl_device_platform_probe(struct kgsl_device *device) device->pwrctrl.interrupt_num = status; disable_irq(device->pwrctrl.interrupt_num); - device->events_worker = kthread_create_worker(0, "kgsl-events"); + device->events_wq = alloc_workqueue("kgsl-events", + WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS | WQ_HIGHPRI, 0); - if (IS_ERR(device->events_worker)) { - status = PTR_ERR(device->events_worker); - dev_err(device->dev, "Failed to create events worker ret=%d\n", status); + if (!device->events_wq) { + dev_err(device->dev, "Failed to allocate events workqueue\n"); + status = -ENOMEM; goto error_pwrctrl_close; } - sched_set_fifo(device->events_worker->task); - /* This can return -EPROBE_DEFER */ status = kgsl_mmu_probe(device); if (status != 0) @@ -4562,8 +4558,10 @@ int kgsl_device_platform_probe(struct kgsl_device *device) return 0; error_pwrctrl_close: - if (!IS_ERR(device->events_worker)) - kthread_destroy_worker(device->events_worker); + if (device->events_wq) { + destroy_workqueue(device->events_wq); + device->events_wq = NULL; + } kgsl_pwrctrl_close(device); error: @@ -4573,7 +4571,10 @@ error: void kgsl_device_platform_remove(struct kgsl_device *device) { - kthread_destroy_worker(device->events_worker); + if (device->events_wq) { + destroy_workqueue(device->events_wq); + device->events_wq = NULL; + } kgsl_device_snapshot_close(device); diff --git a/drivers/gpu/msm/kgsl.h b/drivers/gpu/msm/kgsl.h index e86051f9aa57..0f0721522574 100644 --- a/drivers/gpu/msm/kgsl.h +++ b/drivers/gpu/msm/kgsl.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2008-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __KGSL_H #define __KGSL_H @@ -295,7 +295,7 @@ typedef void (*kgsl_event_func)(struct kgsl_device *, struct kgsl_event_group *, * @priv: Private data passed to the callback function * @node: List node for the kgsl_event_group list * @created: Jiffies when the event was created - * @work: kthread_work struct for dispatching the callback + * @work: Work struct for dispatching the callback * @result: KGSL event result type to pass to the callback * group: The event group this event belongs to */ @@ -307,7 +307,7 @@ struct kgsl_event { void *priv; struct list_head node; unsigned int created; - struct kthread_work work; + struct work_struct work; int result; struct kgsl_event_group *group; }; @@ -473,8 +473,6 @@ void kgsl_mmu_remove_global(struct kgsl_device *device, struct kgsl_memdesc *memdesc); /* Helper functions */ -unsigned long kgsl_get_align(struct kgsl_memdesc *memdesc); - int kgsl_request_irq(struct platform_device *pdev, const char *name, irq_handler_t handler, void *data); diff --git a/drivers/gpu/msm/kgsl_debugfs.c b/drivers/gpu/msm/kgsl_debugfs.c index 1298f6247c9e..a90636a16f82 100644 --- a/drivers/gpu/msm/kgsl_debugfs.c +++ b/drivers/gpu/msm/kgsl_debugfs.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2002,2008-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -147,7 +146,7 @@ static const char *memtype_str(int memtype) static char get_alignflag(const struct kgsl_memdesc *m) { - u32 align = kgsl_memdesc_get_align(m); + int align = kgsl_memdesc_get_align(m); if (align >= ilog2(SZ_1M)) return 'L'; diff --git a/drivers/gpu/msm/kgsl_device.h b/drivers/gpu/msm/kgsl_device.h index 0b4a6c01d1d0..3d3cfdab5128 100644 --- a/drivers/gpu/msm/kgsl_device.h +++ b/drivers/gpu/msm/kgsl_device.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __KGSL_DEVICE_H #define __KGSL_DEVICE_H @@ -294,7 +293,7 @@ struct kgsl_device { struct kgsl_pwrscale pwrscale; int reset_counter; /* Track how many GPU core resets have occurred */ - struct kthread_worker *events_worker; + struct workqueue_struct *events_wq; /* Number of active contexts seen globally for this device */ int active_context_count; diff --git a/drivers/gpu/msm/kgsl_events.c b/drivers/gpu/msm/kgsl_events.c index 674a3dc13e2c..891c662ea339 100644 --- a/drivers/gpu/msm/kgsl_events.c +++ b/drivers/gpu/msm/kgsl_events.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2011-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -22,17 +21,17 @@ static inline void signal_event(struct kgsl_device *device, { list_del(&event->node); event->result = result; - kthread_queue_work(device->events_worker, &event->work); + queue_work(device->events_wq, &event->work); } /** * _kgsl_event_worker() - Work handler for processing GPU event callbacks - * @work: Pointer to the kthread_work for the event + * @work: Pointer to the work_struct for the event * - * Each event callback has its own kthread_work struct and is run on a event specific - * worker thread. This is the worker that queues up the event callback function. + * Each event callback has its own work struct and is run on a event specific + * workqeuue. This is the worker that queues up the event callback function. */ -static void _kgsl_event_worker(struct kthread_work *work) +static void _kgsl_event_worker(struct work_struct *work) { struct kgsl_event *event = container_of(work, struct kgsl_event, work); int id = KGSL_CONTEXT_ID(event->context); @@ -269,7 +268,7 @@ int kgsl_add_event(struct kgsl_device *device, struct kgsl_event_group *group, event->created = jiffies; event->group = group; - kthread_init_work(&event->work, _kgsl_event_worker); + INIT_WORK(&event->work, _kgsl_event_worker); trace_kgsl_register_event(KGSL_CONTEXT_ID(context), timestamp, func); @@ -284,7 +283,7 @@ int kgsl_add_event(struct kgsl_device *device, struct kgsl_event_group *group, if (timestamp_cmp(retired, timestamp) >= 0) { event->result = KGSL_EVENT_RETIRED; - kthread_queue_work(device->events_worker, &event->work); + queue_work(device->events_wq, &event->work); spin_unlock(&group->lock); return 0; } diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c index 25a5750e452a..690ffe008811 100644 --- a/drivers/gpu/msm/kgsl_iommu.c +++ b/drivers/gpu/msm/kgsl_iommu.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2011-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2229,7 +2229,8 @@ static int kgsl_iommu_get_gpuaddr(struct kgsl_pagetable *pagetable, size = kgsl_memdesc_footprint(memdesc); - align = kgsl_get_align(memdesc); + align = max_t(uint64_t, 1 << kgsl_memdesc_get_align(memdesc), + PAGE_SIZE); if (memdesc->flags & KGSL_MEMFLAGS_FORCE_32BIT) { start = pt->compat_va_start; diff --git a/drivers/gpu/msm/kgsl_sharedmem.h b/drivers/gpu/msm/kgsl_sharedmem.h index 1f55ffcfb265..389fd86078ff 100644 --- a/drivers/gpu/msm/kgsl_sharedmem.h +++ b/drivers/gpu/msm/kgsl_sharedmem.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2002,2007-2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #ifndef __KGSL_SHAREDMEM_H #define __KGSL_SHAREDMEM_H @@ -158,7 +157,7 @@ void kgsl_free_globals(struct kgsl_device *device); * * Returns the alignment requested, as power of 2 exponent. */ -static inline u32 +static inline int kgsl_memdesc_get_align(const struct kgsl_memdesc *memdesc) { return MEMFLAGS(memdesc->flags, KGSL_MEMALIGN_MASK, diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index 78287d3870f2..e21fe418ef0d 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -303,9 +303,6 @@ #define USB_DEVICE_ID_CODEMERCS_IOW_FIRST 0x1500 #define USB_DEVICE_ID_CODEMERCS_IOW_LAST 0x15ff -#define USB_VENDOR_ID_COOLER_MASTER 0x2516 -#define USB_DEVICE_ID_COOLER_MASTER_MICE_DONGLE 0x01b7 - #define USB_VENDOR_ID_CORSAIR 0x1b1c #define USB_DEVICE_ID_CORSAIR_K90 0x1b02 @@ -1359,8 +1356,8 @@ #define USB_VENDOR_ID_SIGNOTEC 0x2133 #define USB_DEVICE_ID_SIGNOTEC_VIEWSONIC_PD1011 0x0018 -#define USB_VENDOR_ID_JIELI_SDK_DEFAULT 0x4c4a -#define USB_DEVICE_ID_JIELI_SDK_4155 0x4155 +#define USB_VENDOR_ID_SMARTLINKTECHNOLOGY 0x4c4a +#define USB_DEVICE_ID_SMARTLINKTECHNOLOGY_4155 0x4155 #define USB_VENDOR_ID_QVR5 0x045e #define USB_VENDOR_ID_QVR32A 0x04b4 diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c index ac7dc35b1e89..477b082aa6a8 100644 --- a/drivers/hid/hid-logitech-hidpp.c +++ b/drivers/hid/hid-logitech-hidpp.c @@ -3743,12 +3743,10 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id) if (hidpp->quirks & HIDPP_QUIRK_CLASS_G920) { ret = hidpp_ff_init(hidpp, &data); - if (ret) { + if (ret) hid_warn(hidpp->hid_dev, "Unable to initialize force feedback support, errno %d\n", ret); - ret = 0; - } } return ret; diff --git a/drivers/hid/hid-quirks.c b/drivers/hid/hid-quirks.c index c7695eb15f54..71fdac9c9306 100644 --- a/drivers/hid/hid-quirks.c +++ b/drivers/hid/hid-quirks.c @@ -57,7 +57,6 @@ static const struct hid_device_id hid_quirks[] = { { HID_USB_DEVICE(USB_VENDOR_ID_CH, USB_DEVICE_ID_CH_FLIGHT_SIM_YOKE), HID_QUIRK_NOGET }, { HID_USB_DEVICE(USB_VENDOR_ID_CH, USB_DEVICE_ID_CH_PRO_PEDALS), HID_QUIRK_NOGET }, { HID_USB_DEVICE(USB_VENDOR_ID_CH, USB_DEVICE_ID_CH_PRO_THROTTLE), HID_QUIRK_NOGET }, - { HID_USB_DEVICE(USB_VENDOR_ID_COOLER_MASTER, USB_DEVICE_ID_COOLER_MASTER_MICE_DONGLE), HID_QUIRK_ALWAYS_POLL }, { HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_K65RGB), HID_QUIRK_NO_INIT_REPORTS }, { HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_K65RGB_RAPIDFIRE), HID_QUIRK_NO_INIT_REPORTS | HID_QUIRK_ALWAYS_POLL }, { HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_K70RGB), HID_QUIRK_NO_INIT_REPORTS }, @@ -895,6 +894,7 @@ static const struct hid_device_id hid_ignore_list[] = { #endif { HID_USB_DEVICE(USB_VENDOR_ID_YEALINK, USB_DEVICE_ID_YEALINK_P1K_P4K_B2K) }, { HID_USB_DEVICE(USB_VENDOR_ID_QUANTA, USB_DEVICE_ID_QUANTA_HP_5MP_CAMERA_5473) }, + { HID_USB_DEVICE(USB_VENDOR_ID_SMARTLINKTECHNOLOGY, USB_DEVICE_ID_SMARTLINKTECHNOLOGY_4155) }, { } }; @@ -1043,18 +1043,6 @@ bool hid_ignore(struct hid_device *hdev) strlen(elan_acpi_id[i].id))) return true; break; - case USB_VENDOR_ID_JIELI_SDK_DEFAULT: - /* - * Multiple USB devices with identical IDs (mic & touchscreen). - * The touch screen requires hid core processing, but the - * microphone does not. They can be distinguished by manufacturer - * and serial number. - */ - if (hdev->product == USB_DEVICE_ID_JIELI_SDK_4155 && - strncmp(hdev->name, "SmartlinkTechnology", 19) == 0 && - strncmp(hdev->uniq, "20201111000001", 14) == 0) - return true; - break; } if (hdev->type == HID_TYPE_USBMOUSE && diff --git a/drivers/hid/hidraw.c b/drivers/hid/hidraw.c index 97a4eb4ca1fb..f8ef6268f3f2 100644 --- a/drivers/hid/hidraw.c +++ b/drivers/hid/hidraw.c @@ -472,7 +472,9 @@ static const struct file_operations hidraw_ops = { .release = hidraw_release, .unlocked_ioctl = hidraw_ioctl, .fasync = hidraw_fasync, - .compat_ioctl = compat_ptr_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = hidraw_ioctl, +#endif .llseek = noop_llseek, }; diff --git a/drivers/hwmon/dell-smm-hwmon.c b/drivers/hwmon/dell-smm-hwmon.c index 51d0f5e88ebc..785e7a07bb29 100644 --- a/drivers/hwmon/dell-smm-hwmon.c +++ b/drivers/hwmon/dell-smm-hwmon.c @@ -1016,13 +1016,6 @@ static const struct dmi_system_id i8k_dmi_table[] __initconst = { }, .driver_data = (void *)&i8k_config_data[DELL_PRECISION_490], }, - { - .ident = "Dell OptiPlex 7040", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), - DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "OptiPlex 7040"), - }, - }, { .ident = "Dell Precision", .matches = { diff --git a/drivers/hwtracing/coresight/coresight-byte-cntr.c b/drivers/hwtracing/coresight/coresight-byte-cntr.c index a58649c839dc..d85b769ea9ce 100644 --- a/drivers/hwtracing/coresight/coresight-byte-cntr.c +++ b/drivers/hwtracing/coresight/coresight-byte-cntr.c @@ -80,7 +80,7 @@ static ssize_t tmc_etr_byte_cntr_read(struct file *fp, char __user *data, size_t len, loff_t *ppos) { struct byte_cntr *byte_cntr_data = fp->private_data; - char *bufp = NULL; + char *bufp; int ret = 0; if (!data) return -EINVAL; diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c index fd5ffe13c703..75313c80f132 100644 --- a/drivers/i2c/busses/i2c-designware-platdrv.c +++ b/drivers/i2c/busses/i2c-designware-platdrv.c @@ -414,7 +414,6 @@ static int dw_i2c_plat_probe(struct platform_device *pdev) exit_probe: dw_i2c_plat_pm_cleanup(dev); - i2c_dw_prepare_clk(dev, false); exit_reset: reset_control_assert(dev->rst); return ret; diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c index 2b56ad08efed..5587e7c549c4 100644 --- a/drivers/i2c/busses/i2c-mt65xx.c +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -782,7 +782,6 @@ static int mtk_i2c_transfer(struct i2c_adapter *adap, { int ret; int left_num = num; - bool write_then_read_en = false; struct mtk_i2c *i2c = i2c_get_adapdata(adap); ret = mtk_i2c_clock_enable(i2c); @@ -796,7 +795,6 @@ static int mtk_i2c_transfer(struct i2c_adapter *adap, if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) && msgs[0].addr == msgs[1].addr) { i2c->auto_restart = 0; - write_then_read_en = true; } } @@ -820,10 +818,12 @@ static int mtk_i2c_transfer(struct i2c_adapter *adap, else i2c->op = I2C_MASTER_WR; - if (write_then_read_en) { - /* combined two messages into one transaction */ - i2c->op = I2C_MASTER_WRRD; - left_num--; + if (!i2c->auto_restart) { + if (num > 1) { + /* combined two messages into one transaction */ + i2c->op = I2C_MASTER_WRRD; + left_num--; + } } /* always use DMA mode. */ @@ -831,10 +831,7 @@ static int mtk_i2c_transfer(struct i2c_adapter *adap, if (ret < 0) goto err_exit; - if (i2c->op == I2C_MASTER_WRRD) - msgs += 2; - else - msgs++; + msgs++; } /* the return value is number of executed messages */ ret = num; diff --git a/drivers/iio/adc/spear_adc.c b/drivers/iio/adc/spear_adc.c index f2c4d590de0a..592b97c464da 100644 --- a/drivers/iio/adc/spear_adc.c +++ b/drivers/iio/adc/spear_adc.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -30,9 +29,9 @@ /* Bit definitions for SPEAR_ADC_STATUS */ #define SPEAR_ADC_STATUS_START_CONVERSION BIT(0) -#define SPEAR_ADC_STATUS_CHANNEL_NUM_MASK GENMASK(3, 1) +#define SPEAR_ADC_STATUS_CHANNEL_NUM(x) ((x) << 1) #define SPEAR_ADC_STATUS_ADC_ENABLE BIT(4) -#define SPEAR_ADC_STATUS_AVG_SAMPLE_MASK GENMASK(8, 5) +#define SPEAR_ADC_STATUS_AVG_SAMPLE(x) ((x) << 5) #define SPEAR_ADC_STATUS_VREF_INTERNAL BIT(9) #define SPEAR_ADC_DATA_MASK 0x03ff @@ -149,8 +148,8 @@ static int spear_adc_read_raw(struct iio_dev *indio_dev, case IIO_CHAN_INFO_RAW: mutex_lock(&indio_dev->mlock); - status = FIELD_PREP(SPEAR_ADC_STATUS_CHANNEL_NUM_MASK, chan->channel) | - FIELD_PREP(SPEAR_ADC_STATUS_AVG_SAMPLE_MASK, st->avg_samples) | + status = SPEAR_ADC_STATUS_CHANNEL_NUM(chan->channel) | + SPEAR_ADC_STATUS_AVG_SAMPLE(st->avg_samples) | SPEAR_ADC_STATUS_START_CONVERSION | SPEAR_ADC_STATUS_ADC_ENABLE; if (st->vref_external == 0) diff --git a/drivers/iio/dac/ad5360.c b/drivers/iio/dac/ad5360.c index 5a3ae91726f9..2ac428b957e3 100644 --- a/drivers/iio/dac/ad5360.c +++ b/drivers/iio/dac/ad5360.c @@ -259,7 +259,7 @@ static int ad5360_update_ctrl(struct iio_dev *indio_dev, unsigned int set, unsigned int clr) { struct ad5360_state *st = iio_priv(indio_dev); - int ret; + unsigned int ret; mutex_lock(&indio_dev->mlock); diff --git a/drivers/iio/dac/ad5421.c b/drivers/iio/dac/ad5421.c index 8cae84586abb..63063e85cd0a 100644 --- a/drivers/iio/dac/ad5421.c +++ b/drivers/iio/dac/ad5421.c @@ -183,7 +183,7 @@ static int ad5421_update_ctrl(struct iio_dev *indio_dev, unsigned int set, unsigned int clr) { struct ad5421_state *st = iio_priv(indio_dev); - int ret; + unsigned int ret; mutex_lock(&indio_dev->mlock); diff --git a/drivers/iio/frequency/adf4350.c b/drivers/iio/frequency/adf4350.c index 00207d924e88..ae0ca09ae062 100644 --- a/drivers/iio/frequency/adf4350.c +++ b/drivers/iio/frequency/adf4350.c @@ -137,19 +137,6 @@ static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq) if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq) return -EINVAL; - st->r4_rf_div_sel = 0; - - /* - * !\TODO: The below computation is making sure we get a power of 2 - * shift (st->r4_rf_div_sel) so that freq becomes higher or equal to - * ADF4350_MIN_VCO_FREQ. This might be simplified with fls()/fls_long() - * and friends. - */ - while (freq < ADF4350_MIN_VCO_FREQ) { - freq <<= 1; - st->r4_rf_div_sel++; - } - if (freq > ADF4350_MAX_FREQ_45_PRESC) { prescaler = ADF4350_REG1_PRESCALER; mdiv = 75; @@ -158,6 +145,13 @@ static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq) mdiv = 23; } + st->r4_rf_div_sel = 0; + + while (freq < ADF4350_MIN_VCO_FREQ) { + freq <<= 1; + st->r4_rf_div_sel++; + } + /* * Allow a predefined reference division factor * if not set, compute our own diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index 243a1600096a..485b2e6748c5 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -1612,7 +1612,7 @@ static const struct file_operations iio_buffer_fileops = { .owner = THIS_MODULE, .llseek = noop_llseek, .unlocked_ioctl = iio_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = iio_ioctl, }; static int iio_check_unique_scan_index(struct iio_dev *indio_dev) diff --git a/drivers/iio/inkern.c b/drivers/iio/inkern.c index 6bdd175df021..6374d5091555 100644 --- a/drivers/iio/inkern.c +++ b/drivers/iio/inkern.c @@ -627,7 +627,7 @@ static int iio_convert_raw_to_processed_unlocked(struct iio_channel *chan, * If no channel scaling is available apply consumer scale to * raw value and return. */ - *processed = raw64 * scale; + *processed = raw * scale; return 0; } diff --git a/drivers/infiniband/core/addr.c b/drivers/infiniband/core/addr.c index 48de2285922f..c9e63c692b6e 100644 --- a/drivers/infiniband/core/addr.c +++ b/drivers/infiniband/core/addr.c @@ -459,10 +459,14 @@ static int addr_resolve_neigh(const struct dst_entry *dst, { int ret = 0; - if (ndev_flags & IFF_LOOPBACK) + if (ndev_flags & IFF_LOOPBACK) { memcpy(addr->dst_dev_addr, addr->src_dev_addr, MAX_ADDR_LEN); - else - ret = fetch_ha(dst, addr, dst_in, seq); + } else { + if (!(ndev_flags & IFF_NOARP)) { + /* If the device doesn't do ARP internally */ + ret = fetch_ha(dst, addr, dst_in, seq); + } + } return ret; } diff --git a/drivers/infiniband/core/sa_query.c b/drivers/infiniband/core/sa_query.c index b05df8694a4a..11ab6390eda4 100644 --- a/drivers/infiniband/core/sa_query.c +++ b/drivers/infiniband/core/sa_query.c @@ -1036,8 +1036,6 @@ int ib_nl_handle_set_timeout(struct sk_buff *skb, if (timeout > IB_SA_LOCAL_SVC_TIMEOUT_MAX) timeout = IB_SA_LOCAL_SVC_TIMEOUT_MAX; - spin_lock_irqsave(&ib_nl_request_lock, flags); - delta = timeout - sa_local_svc_timeout_ms; if (delta < 0) abs_delta = -delta; @@ -1045,6 +1043,7 @@ int ib_nl_handle_set_timeout(struct sk_buff *skb, abs_delta = delta; if (delta != 0) { + spin_lock_irqsave(&ib_nl_request_lock, flags); sa_local_svc_timeout_ms = timeout; list_for_each_entry(query, &ib_nl_request_list, list) { if (delta < 0 && abs_delta > query->timeout) @@ -1062,10 +1061,9 @@ int ib_nl_handle_set_timeout(struct sk_buff *skb, if (delay) mod_delayed_work(ib_nl_wq, &ib_nl_timed_work, (unsigned long)delay); + spin_unlock_irqrestore(&ib_nl_request_lock, flags); } - spin_unlock_irqrestore(&ib_nl_request_lock, flags); - settimeout_out: return 0; } diff --git a/drivers/infiniband/core/uverbs_main.c b/drivers/infiniband/core/uverbs_main.c index d46ea235c216..af6dedabd6a5 100644 --- a/drivers/infiniband/core/uverbs_main.c +++ b/drivers/infiniband/core/uverbs_main.c @@ -1135,7 +1135,7 @@ static const struct file_operations uverbs_fops = { .release = ib_uverbs_close, .llseek = no_llseek, .unlocked_ioctl = ib_uverbs_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = ib_uverbs_ioctl, }; static const struct file_operations uverbs_mmap_fops = { @@ -1146,7 +1146,7 @@ static const struct file_operations uverbs_mmap_fops = { .release = ib_uverbs_close, .llseek = no_llseek, .unlocked_ioctl = ib_uverbs_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = ib_uverbs_ioctl, }; static int ib_uverbs_get_nl_info(struct ib_device *ibdev, void *client_data, diff --git a/drivers/infiniband/sw/siw/siw_verbs.c b/drivers/infiniband/sw/siw/siw_verbs.c index b5a845985ba4..236f9efaa75c 100644 --- a/drivers/infiniband/sw/siw/siw_verbs.c +++ b/drivers/infiniband/sw/siw/siw_verbs.c @@ -779,7 +779,7 @@ int siw_post_send(struct ib_qp *base_qp, const struct ib_send_wr *wr, struct siw_wqe *wqe = tx_wqe(qp); unsigned long flags; - int rv = 0, imm_err = 0; + int rv = 0; if (wr && !qp->kernel_verbs) { siw_dbg_qp(qp, "wr must be empty for user mapped sq\n"); @@ -965,17 +965,9 @@ int siw_post_send(struct ib_qp *base_qp, const struct ib_send_wr *wr, * Send directly if SQ processing is not in progress. * Eventual immediate errors (rv < 0) do not affect the involved * RI resources (Verbs, 8.3.1) and thus do not prevent from SQ - * processing, if new work is already pending. But rv and pointer - * to failed work request must be passed to caller. + * processing, if new work is already pending. But rv must be passed + * to caller. */ - if (unlikely(rv < 0)) { - /* - * Immediate error - */ - siw_dbg_qp(qp, "Immediate error %d\n", rv); - imm_err = rv; - *bad_wr = wr; - } if (wqe->wr_status != SIW_WR_IDLE) { spin_unlock_irqrestore(&qp->sq_lock, flags); goto skip_direct_sending; @@ -1000,10 +992,15 @@ skip_direct_sending: up_read(&qp->state_lock); - if (unlikely(imm_err)) - return imm_err; + if (rv >= 0) + return 0; + /* + * Immediate error + */ + siw_dbg_qp(qp, "error %d\n", rv); - return (rv >= 0) ? 0 : rv; + *bad_wr = wr; + return rv; } /* diff --git a/drivers/input/keyboard/cros_ec_keyb.c b/drivers/input/keyboard/cros_ec_keyb.c index fbf891642ad6..cae262b6ff39 100644 --- a/drivers/input/keyboard/cros_ec_keyb.c +++ b/drivers/input/keyboard/cros_ec_keyb.c @@ -244,12 +244,6 @@ static int cros_ec_keyb_work(struct notifier_block *nb, case EC_MKBP_EVENT_KEY_MATRIX: pm_wakeup_event(ckdev->dev, 0); - if (!ckdev->idev) { - dev_warn_once(ckdev->dev, - "Unexpected key matrix event\n"); - return NOTIFY_OK; - } - if (ckdev->ec->event_size != ckdev->cols) { dev_err(ckdev->dev, "Discarded incomplete key matrix event.\n"); diff --git a/drivers/input/misc/ati_remote2.c b/drivers/input/misc/ati_remote2.c index 946bf75aa106..8a36d78fed63 100644 --- a/drivers/input/misc/ati_remote2.c +++ b/drivers/input/misc/ati_remote2.c @@ -639,7 +639,7 @@ static int ati_remote2_urb_init(struct ati_remote2 *ar2) return -ENOMEM; pipe = usb_rcvintpipe(udev, ar2->ep[i]->bEndpointAddress); - maxp = usb_maxpacket(udev, pipe); + maxp = usb_maxpacket(udev, pipe, usb_pipeout(pipe)); maxp = maxp > 4 ? 4 : maxp; usb_fill_int_urb(ar2->urb[i], udev, pipe, ar2->buf[i], maxp, diff --git a/drivers/input/misc/cm109.c b/drivers/input/misc/cm109.c index dba8b09ebda5..c872ba579b03 100644 --- a/drivers/input/misc/cm109.c +++ b/drivers/input/misc/cm109.c @@ -749,7 +749,7 @@ static int cm109_usb_probe(struct usb_interface *intf, /* get a handle to the interrupt data pipe */ pipe = usb_rcvintpipe(udev, endpoint->bEndpointAddress); - ret = usb_maxpacket(udev, pipe); + ret = usb_maxpacket(udev, pipe, usb_pipeout(pipe)); if (ret != USB_PKT_LEN) dev_err(&intf->dev, "invalid payload size %d, expected %d\n", ret, USB_PKT_LEN); diff --git a/drivers/input/misc/ets_bix_mmi/etxxx_fp.c b/drivers/input/misc/ets_bix_mmi/etxxx_fp.c index e5caee6a476d..1384c113b690 100755 --- a/drivers/input/misc/ets_bix_mmi/etxxx_fp.c +++ b/drivers/input/misc/ets_bix_mmi/etxxx_fp.c @@ -1543,7 +1543,7 @@ egistec_probe_failed: return status; } -static int __init egisfp_init(void) +int __init egisfp_init(void) { int status; INFO_PRINT(" %s : module init \n", __func__); @@ -1556,7 +1556,7 @@ static int __init egisfp_init(void) INFO_PRINT(" %s : module init OK ! \n", __func__); return status; } -static void __exit egisfp_exit(void) +void __exit egisfp_exit(void) { INFO_PRINT("module exit \n"); platform_driver_unregister(&egisfp_driver); diff --git a/drivers/input/misc/powermate.c b/drivers/input/misc/powermate.c index db2ba89adaef..6b1b95d58e6b 100644 --- a/drivers/input/misc/powermate.c +++ b/drivers/input/misc/powermate.c @@ -374,7 +374,7 @@ static int powermate_probe(struct usb_interface *intf, const struct usb_device_i /* get a handle to the interrupt data pipe */ pipe = usb_rcvintpipe(udev, endpoint->bEndpointAddress); - maxp = usb_maxpacket(udev, pipe); + maxp = usb_maxpacket(udev, pipe, usb_pipeout(pipe)); if (maxp < POWERMATE_PAYLOAD_SIZE_MIN || maxp > POWERMATE_PAYLOAD_SIZE_MAX) { printk(KERN_WARNING "powermate: Expected payload of %d--%d bytes, found %d bytes!\n", diff --git a/drivers/input/misc/rbs_fod_mmi/etxxx_fp.c b/drivers/input/misc/rbs_fod_mmi/etxxx_fp.c index fdee9e03ebc4..b4e4068acd8b 100644 --- a/drivers/input/misc/rbs_fod_mmi/etxxx_fp.c +++ b/drivers/input/misc/rbs_fod_mmi/etxxx_fp.c @@ -1473,7 +1473,7 @@ egistec_probe_failed: return status; } -static int __init egisfp_init(void) +int __init egisfp_init(void) { int status; INFO_PRINT(" %s : module init \n", __func__); @@ -1486,7 +1486,7 @@ static int __init egisfp_init(void) INFO_PRINT(" %s : module init OK ! \n", __func__); return status; } -static void __exit egisfp_exit(void) +void __exit egisfp_exit(void) { INFO_PRINT("module exit \n"); platform_driver_unregister(&egisfp_driver); diff --git a/drivers/input/misc/rbs_fps_mmi/etxxx_fp.c b/drivers/input/misc/rbs_fps_mmi/etxxx_fp.c index 9ca505d7575b..f75ffeedd2e3 100644 --- a/drivers/input/misc/rbs_fps_mmi/etxxx_fp.c +++ b/drivers/input/misc/rbs_fps_mmi/etxxx_fp.c @@ -1389,7 +1389,7 @@ egistec_probe_failed: return status; } -static int __init egisfp_init(void) +int __init egisfp_init(void) { int status; INFO_PRINT(" %s : module init \n", __func__); @@ -1402,7 +1402,7 @@ static int __init egisfp_init(void) INFO_PRINT(" %s : module init OK ! \n", __func__); return status; } -static void __exit egisfp_exit(void) +void __exit egisfp_exit(void) { INFO_PRINT("module exit \n"); platform_driver_unregister(&egisfp_driver); diff --git a/drivers/input/misc/uinput.c b/drivers/input/misc/uinput.c index 83f5918e96e9..4d9c71b9584e 100644 --- a/drivers/input/misc/uinput.c +++ b/drivers/input/misc/uinput.c @@ -774,7 +774,6 @@ static int uinput_ff_upload_to_user(char __user *buffer, if (in_compat_syscall()) { struct uinput_ff_upload_compat ff_up_compat; - memset(&ff_up_compat, 0, sizeof(ff_up_compat)); ff_up_compat.request_id = ff_up->request_id; ff_up_compat.retval = ff_up->retval; /* diff --git a/drivers/input/misc/yealink.c b/drivers/input/misc/yealink.c index 69420781db30..8ab01c7601b1 100644 --- a/drivers/input/misc/yealink.c +++ b/drivers/input/misc/yealink.c @@ -905,7 +905,7 @@ static int usb_probe(struct usb_interface *intf, const struct usb_device_id *id) /* get a handle to the interrupt data pipe */ pipe = usb_rcvintpipe(udev, endpoint->bEndpointAddress); - ret = usb_maxpacket(udev, pipe); + ret = usb_maxpacket(udev, pipe, usb_pipeout(pipe)); if (ret != USB_PKT_LEN) dev_err(&intf->dev, "invalid payload size %d, expected %zd\n", ret, USB_PKT_LEN); diff --git a/drivers/input/serio/hp_sdc.c b/drivers/input/serio/hp_sdc.c index 13eacf6ab431..654252361653 100644 --- a/drivers/input/serio/hp_sdc.c +++ b/drivers/input/serio/hp_sdc.c @@ -1021,7 +1021,7 @@ static int __init hp_sdc_register(void) hp_sdc.base_io = (unsigned long) 0xf0428000; hp_sdc.data_io = (unsigned long) hp_sdc.base_io + 1; hp_sdc.status_io = (unsigned long) hp_sdc.base_io + 3; - if (!copy_from_kernel_nofault(&i, (unsigned char *)hp_sdc.data_io, 1)) + if (!probe_kernel_read(&i, (unsigned char *)hp_sdc.data_io, 1)) hp_sdc.dev = (void *)1; hp_sdc.dev_err = hp_sdc_init(); #endif diff --git a/drivers/input/tablet/acecad.c b/drivers/input/tablet/acecad.c index 56c7e471ac32..a38d1fe97334 100644 --- a/drivers/input/tablet/acecad.c +++ b/drivers/input/tablet/acecad.c @@ -130,7 +130,7 @@ static int usb_acecad_probe(struct usb_interface *intf, const struct usb_device_ return -ENODEV; pipe = usb_rcvintpipe(dev, endpoint->bEndpointAddress); - maxp = usb_maxpacket(dev, pipe); + maxp = usb_maxpacket(dev, pipe, usb_pipeout(pipe)); acecad = kzalloc(sizeof(struct usb_acecad), GFP_KERNEL); input_dev = input_allocate_device(); diff --git a/drivers/input/tablet/pegasus_notetaker.c b/drivers/input/tablet/pegasus_notetaker.c index 64a5ce546229..38f087404f7a 100644 --- a/drivers/input/tablet/pegasus_notetaker.c +++ b/drivers/input/tablet/pegasus_notetaker.c @@ -63,9 +63,6 @@ #define BUTTON_PRESSED 0xb5 #define COMMAND_VERSION 0xa9 -/* 1 Status + 1 Color + 2 X + 2 Y = 6 bytes */ -#define NOTETAKER_PACKET_SIZE 6 - /* in xy data packet */ #define BATTERY_NO_REPORT 0x40 #define BATTERY_LOW 0x41 @@ -299,13 +296,7 @@ static int pegasus_probe(struct usb_interface *intf, pegasus->intf = intf; pipe = usb_rcvintpipe(dev, endpoint->bEndpointAddress); - pegasus->data_len = usb_maxpacket(dev, pipe); - if (pegasus->data_len < NOTETAKER_PACKET_SIZE) { - dev_err(&intf->dev, "packet size is too small (%d)\n", - pegasus->data_len); - error = -EINVAL; - goto err_free_mem; - } + pegasus->data_len = usb_maxpacket(dev, pipe, usb_pipeout(pipe)); pegasus->data = usb_alloc_coherent(dev, pegasus->data_len, GFP_KERNEL, &pegasus->data_dma); diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index 6eaeaefb4e7f..7e234defdc6b 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -1333,8 +1333,6 @@ source "drivers/input/touchscreen/synaptics_dsx/Kconfig" source "drivers/input/touchscreen/nt36xxx/Kconfig" -source "drivers/input/touchscreen/chipone_tddi_mmi/Kconfig" - source "drivers/input/touchscreen/chipone_tddi_v2_mmi/Kconfig" source "drivers/input/touchscreen/focaltech_0flash_v2_mmi/Kconfig" diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index 5fb2875e98bd..32a9a17a8867 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -116,7 +116,6 @@ obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_TCM) += synaptics_tcm/ obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_DSX) += synaptics_dsx/ obj-$(CONFIG_TOUCHSCREEN_NT36XXX) += nt36xxx/ -obj-$(CONFIG_TOUCHSCREEN_CHIPONE_TDDI) += chipone_tddi_mmi/ obj-$(CONFIG_TOUCHSCREEN_CHIPONE_V2_MMI) += chipone_tddi_v2_mmi/ obj-$(CONFIG_TOUCHSCREEN_FTS_0FLASH_MMI_V2) += focaltech_0flash_v2_mmi/ obj-$(CONFIG_TOUCHSCREEN_FTS_V3) += focaltech_touch_v3/ diff --git a/drivers/input/touchscreen/chipone_tddi_mmi/Kbuild b/drivers/input/touchscreen/chipone_tddi_mmi/Kbuild index 4f6f559957d3..f6b80347f77f 100644 --- a/drivers/input/touchscreen/chipone_tddi_mmi/Kbuild +++ b/drivers/input/touchscreen/chipone_tddi_mmi/Kbuild @@ -1,6 +1,12 @@ -ccflags-$(CONFIG_TOUCHSCREEN_CHIPONE_TDDI_ESD) += -DCONFIG_CTS_ESD_PROTECTION +# add -Wall to try to catch everything we can. +EXTRA_CFLAGS += -Wall +EXTRA_CFLAGS += -I$(ANDROID_BUILD_TOP)/motorola/kernel/modules/include \ + -I$(ANDROID_BUILD_TOP)/motorola/kernel/modules/drivers/input/touchscreen/chipone_tddi_mmi +ifneq ($(filter m y,$(CONFIG_CHIPONE_ESD)),) +EXTRA_CFLAGS += -DCONFIG_CTS_ESD_PROTECTION +endif -obj-$(CONFIG_TOUCHSCREEN_CHIPONE_TDDI) := chipone_tddi_mmi.o +obj-m := chipone_tddi_mmi.o chipone_tddi_mmi-objs += cts_i2c_driver.o chipone_tddi_mmi-objs += cts_core.o diff --git a/drivers/input/touchscreen/chipone_tddi_mmi/Kconfig b/drivers/input/touchscreen/chipone_tddi_mmi/Kconfig deleted file mode 100644 index b9e57e39ea35..000000000000 --- a/drivers/input/touchscreen/chipone_tddi_mmi/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -config TOUCHSCREEN_CHIPONE_TDDI - tristate "CHIPONE TDDI Touchscreen" - default n - help - Say Y here if you have a Chipone flash touchscreen connected - to your system by SPI bus. - - If unsure, say N. - -config TOUCHSCREEN_CHIPONE_TDDI_ESD - bool "ESD Detection" - depends on TOUCHSCREEN_CHIPONE_TDDI - default n - help - Say Y here if you want to have ESD Detection support. - - If unsure, say N. diff --git a/drivers/input/touchscreen/touchscreen_mmi/touchscreen_mmi_notif.c b/drivers/input/touchscreen/touchscreen_mmi/touchscreen_mmi_notif.c index 4d4319bb175e..5caa363a95bc 100644 --- a/drivers/input/touchscreen/touchscreen_mmi/touchscreen_mmi_notif.c +++ b/drivers/input/touchscreen/touchscreen_mmi/touchscreen_mmi_notif.c @@ -187,17 +187,15 @@ static void ts_mmi_panel_cb(enum panel_event_notifier_tag tag, dev_dbg(DEV_MMI, "%s: %s Notify_type=%d, early=%d, ctrl_dsi=%d\n", __func__, EVENT_PRE_DISPLAY_OFF ? "EVENT_PRE_DISPLAY_OFF" : - (EVENT_DISPLAY_LP ? "EVENT_DISPLAY_LP" : (EVENT_DISPLAY_OFF ? "EVENT_DISPLAY_OFF" : (EVENT_PRE_DISPLAY_ON ? "EVENT_PRE_DISPLAY_ON" : - (EVENT_DISPLAY_ON ? "EVENT_DISPLAY_ON" : "Unknown")))), + (EVENT_DISPLAY_ON ? "EVENT_DISPLAY_ON" : "Unknown"))), event, (evdata.early_trigger ? 1 : 0), touch_cdev->pdata.ctrl_dsi); panel_event = EVENT_PRE_DISPLAY_OFF ? TS_MMI_EVENT_PRE_DISPLAY_OFF : - (EVENT_DISPLAY_LP ? TS_MMI_EVENT_PRE_DISPLAY_OFF : (EVENT_DISPLAY_OFF ? TS_MMI_EVENT_DISPLAY_OFF : (EVENT_PRE_DISPLAY_ON ? TS_MMI_EVENT_PRE_DISPLAY_ON : - (EVENT_DISPLAY_ON ? TS_MMI_EVENT_DISPLAY_ON : TS_MMI_EVENT_UNKNOWN)))); + (EVENT_DISPLAY_ON ? TS_MMI_EVENT_DISPLAY_ON : TS_MMI_EVENT_UNKNOWN))); ts_mmi_panel_event_handle(touch_cdev, panel_event); @@ -220,20 +218,18 @@ static int ts_mmi_panel_cb(struct notifier_block *nb, dev_dbg(DEV_MMI,"%s: %s event(%lu), ctrl_dsi=%d, idx=%d\n", __func__, EVENT_PRE_DISPLAY_OFF ? "EVENT_PRE_DISPLAY_OFF" : - (EVENT_DISPLAY_LP ? "EVENT_DISPLAY_LP" : (EVENT_DISPLAY_OFF ? "EVENT_DISPLAY_OFF" : (EVENT_PRE_DISPLAY_ON ? "EVENT_PRE_DISPLAY_ON" : - (EVENT_DISPLAY_ON ? "EVENT_DISPLAY_ON" : "Unknown")))), + (EVENT_DISPLAY_ON ? "EVENT_DISPLAY_ON" : "Unknown"))), event, touch_cdev->pdata.ctrl_dsi, idx); if (touch_cdev->pdata.ctrl_dsi != idx) return 0; panel_event = EVENT_PRE_DISPLAY_OFF ? TS_MMI_EVENT_PRE_DISPLAY_OFF : - (EVENT_DISPLAY_LP ? TS_MMI_EVENT_PRE_DISPLAY_OFF : (EVENT_DISPLAY_OFF ? TS_MMI_EVENT_DISPLAY_OFF : (EVENT_PRE_DISPLAY_ON ? TS_MMI_EVENT_PRE_DISPLAY_ON : - (EVENT_DISPLAY_ON ? TS_MMI_EVENT_DISPLAY_ON : TS_MMI_EVENT_UNKNOWN)))); + (EVENT_DISPLAY_ON ? TS_MMI_EVENT_DISPLAY_ON : TS_MMI_EVENT_UNKNOWN))); ret = ts_mmi_panel_event_handle(touch_cdev, panel_event); diff --git a/drivers/iommu/dma-mapping-fast.c b/drivers/iommu/dma-mapping-fast.c index 947ba3ca140d..3dbaef99d89c 100644 --- a/drivers/iommu/dma-mapping-fast.c +++ b/drivers/iommu/dma-mapping-fast.c @@ -244,12 +244,8 @@ static void fast_smmu_unmap_page(struct device *dev, dma_addr_t iova, } spin_lock_irqsave(&mapping->lock, flags); - - if (unlikely(!av8l_fast_unmap_public(mapping->pgtbl_ops, iova, len))) - goto fail; - + av8l_fast_unmap_public(mapping->pgtbl_ops, iova, len); __fast_smmu_free_iova(mapping, iova, len); -fail: spin_unlock_irqrestore(&mapping->lock, flags); trace_unmap(to_msm_iommu_domain(mapping->domain), iova - offset, len, @@ -389,8 +385,7 @@ static void fast_smmu_unmap_sg(struct device *dev, len = ALIGN(sg_dma_address(sg) + sg_dma_len(sg) - (start - offset), FAST_PAGE_SIZE); - if (unlikely(!av8l_fast_unmap_public(mapping->pgtbl_ops, start, len))) - return; + av8l_fast_unmap_public(mapping->pgtbl_ops, start, len); spin_lock_irqsave(&mapping->lock, flags); __fast_smmu_free_iova(mapping, start, len); @@ -658,10 +653,7 @@ static void fast_smmu_free(struct device *dev, size_t size, size = ALIGN(size, FAST_PAGE_SIZE); spin_lock_irqsave(&mapping->lock, flags); - - if (unlikely(!av8l_fast_unmap_public(mapping->pgtbl_ops, dma_handle, size))) - goto fail; - + av8l_fast_unmap_public(mapping->pgtbl_ops, dma_handle, size); __fast_smmu_free_iova(mapping, dma_handle, size); spin_unlock_irqrestore(&mapping->lock, flags); @@ -682,11 +674,6 @@ static void fast_smmu_free(struct device *dev, size_t size, if (page) dma_free_contiguous(dev, page, size); - - return; - -fail: - spin_unlock_irqrestore(&mapping->lock, flags); } static int fast_smmu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, diff --git a/drivers/iommu/io-pgtable-fast.c b/drivers/iommu/io-pgtable-fast.c index 67ca5c20c521..a9159c012106 100644 --- a/drivers/iommu/io-pgtable-fast.c +++ b/drivers/iommu/io-pgtable-fast.c @@ -127,14 +127,7 @@ #define PTE_SH_IDX(pte) (pte & AV8L_FAST_PTE_SH_MASK) -#define iopte_pmd_offset(pmds, base, iova) \ -({ \ - typeof(iova) __iova = (iova); \ - typeof(base) __base = (base); \ - typeof(pmds) __pmds = (pmds); \ - (__iova < __base) ? ERR_PTR(-EINVAL) : \ - __pmds + ((__iova - ALIGN_DOWN(__base, SZ_2M)) >> AV8L_FAST_PAGE_SHIFT); \ -}) +#define iopte_pmd_offset(pmds, base, iova) (pmds + ((iova - base) >> 12)) static inline dma_addr_t av8l_dma_addr(void *addr) { @@ -209,12 +202,6 @@ void av8l_fast_clear_stale_ptes(struct io_pgtable_ops *ops, u64 base, struct io_pgtable *iop = iof_pgtable_ops_to_pgtable(ops); av8l_fast_iopte *pmdp = iopte_pmd_offset(data->pmds, data->base, base); - if (IS_ERR(pmdp)) { - pr_err("Invalid iova : 0x%lx, as it is less than base : 0x%llx\n", - iova, data->base); - return; - } - for (i = base >> AV8L_FAST_PAGE_SHIFT; i <= (end >> AV8L_FAST_PAGE_SHIFT); ++i) { if (!(*pmdp & AV8L_FAST_PTE_VALID)) { @@ -267,12 +254,6 @@ static int av8l_fast_map(struct io_pgtable_ops *ops, unsigned long iova, unsigned long i, nptes = size >> AV8L_FAST_PAGE_SHIFT; av8l_fast_iopte pte; - if (IS_ERR(ptep)) { - pr_err("Invalid iova : 0x%lx, as it is less than base : 0x%llx\n", - iova, data->base); - return -EINVAL; - } - pte = av8l_fast_prot_to_pte(data, prot); paddr &= AV8L_FAST_PTE_ADDR_MASK; for (i = 0; i < nptes; i++, paddr += SZ_4K) { @@ -305,12 +286,6 @@ __av8l_fast_unmap(struct io_pgtable_ops *ops, unsigned long iova, ptep = iopte_pmd_offset(data->pmds, data->base, iova); nptes = size >> AV8L_FAST_PAGE_SHIFT; - if (IS_ERR(ptep)) { - pr_err("Invalid iova : 0x%lx, as it is less than base : 0x%llx\n", - iova, data->base); - return 0; - } - memset(ptep, val, sizeof(*ptep) * nptes); av8l_clean_range(&iop->cfg, ptep, ptep + nptes); if (!allow_stale_tlb) @@ -320,10 +295,10 @@ __av8l_fast_unmap(struct io_pgtable_ops *ops, unsigned long iova, } /* caller must take care of tlb cache maintenance */ -size_t av8l_fast_unmap_public(struct io_pgtable_ops *ops, unsigned long iova, +void av8l_fast_unmap_public(struct io_pgtable_ops *ops, unsigned long iova, size_t size) { - return __av8l_fast_unmap(ops, iova, size, true); + __av8l_fast_unmap(ops, iova, size, true); } static size_t av8l_fast_unmap(struct io_pgtable_ops *ops, unsigned long iova, @@ -408,12 +383,6 @@ static bool av8l_fast_iova_coherent(struct io_pgtable_ops *ops, struct av8l_fast_io_pgtable *data = iof_pgtable_ops_to_data(ops); av8l_fast_iopte *ptep = iopte_pmd_offset(data->pmds, data->base, iova); - if (IS_ERR(ptep)) { - pr_err("Invalid iova : 0x%lx, as it is less than base : 0x%llx\n", - iova, data->base); - return false; - } - return ((PTE_MAIR_IDX(*ptep) == AV8L_FAST_MAIR_ATTR_IDX_CACHE) && ((PTE_SH_IDX(*ptep) == AV8L_FAST_PTE_SH_OS) || (PTE_SH_IDX(*ptep) == AV8L_FAST_PTE_SH_IS))); diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c index 1a209869b7f5..2468b285c77c 100644 --- a/drivers/irqchip/irq-gic-v2m.c +++ b/drivers/irqchip/irq-gic-v2m.c @@ -178,19 +178,14 @@ static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, { msi_alloc_info_t *info = args; struct v2m_data *v2m = NULL, *tmp; - int hwirq, i, err = 0; - unsigned long offset; - unsigned long align_mask = nr_irqs - 1; + int hwirq, offset, i, err = 0; spin_lock(&v2m_lock); list_for_each_entry(tmp, &v2m_nodes, entry) { - unsigned long align_off = tmp->spi_start - (tmp->spi_start & ~align_mask); - - offset = bitmap_find_next_zero_area_off(tmp->bm, tmp->nr_spis, 0, - nr_irqs, align_mask, align_off); - if (offset < tmp->nr_spis) { + offset = bitmap_find_free_region(tmp->bm, tmp->nr_spis, + get_count_order(nr_irqs)); + if (offset >= 0) { v2m = tmp; - bitmap_set(v2m->bm, offset, nr_irqs); break; } } diff --git a/drivers/isdn/hardware/mISDN/hfcsusb.c b/drivers/isdn/hardware/mISDN/hfcsusb.c index 217968f010be..111a597ef23c 100644 --- a/drivers/isdn/hardware/mISDN/hfcsusb.c +++ b/drivers/isdn/hardware/mISDN/hfcsusb.c @@ -1904,13 +1904,13 @@ out: mISDN_freebchannel(&hw->bch[1]); mISDN_freebchannel(&hw->bch[0]); mISDN_freedchannel(&hw->dch); + kfree(hw); return err; } static int hfcsusb_probe(struct usb_interface *intf, const struct usb_device_id *id) { - int err; struct hfcsusb *hw; struct usb_device *dev = interface_to_usbdev(intf); struct usb_host_interface *iface = intf->cur_altsetting; @@ -2101,28 +2101,20 @@ hfcsusb_probe(struct usb_interface *intf, const struct usb_device_id *id) if (!hw->ctrl_urb) { pr_warn("%s: No memory for control urb\n", driver_info->vend_name); - err = -ENOMEM; - goto err_free_hw; + kfree(hw); + return -ENOMEM; } pr_info("%s: %s: detected \"%s\" (%s, if=%d alt=%d)\n", hw->name, __func__, driver_info->vend_name, conf_str[small_match], ifnum, alt_used); - if (setup_instance(hw, dev->dev.parent)) { - err = -EIO; - goto err_free_urb; - } + if (setup_instance(hw, dev->dev.parent)) + return -EIO; hw->intf = intf; usb_set_intfdata(hw->intf, hw); return 0; - -err_free_urb: - usb_free_urb(hw->ctrl_urb); -err_free_hw: - kfree(hw); - return err; } /* function called when an active device is removed */ diff --git a/drivers/lightnvm/pblk-init.c b/drivers/lightnvm/pblk-init.c index 6e677ff62cc9..9a967a2e83dd 100644 --- a/drivers/lightnvm/pblk-init.c +++ b/drivers/lightnvm/pblk-init.c @@ -145,8 +145,9 @@ static int pblk_l2p_init(struct pblk *pblk, bool factory_init) int ret = 0; map_size = pblk_trans_map_size(pblk); - pblk->trans_map = __vmalloc(map_size, GFP_KERNEL | __GFP_NOWARN | - __GFP_RETRY_MAYFAIL | __GFP_HIGHMEM); + pblk->trans_map = __vmalloc(map_size, GFP_KERNEL | __GFP_NOWARN + | __GFP_RETRY_MAYFAIL | __GFP_HIGHMEM, + PAGE_KERNEL); if (!pblk->trans_map) { pblk_err(pblk, "failed to allocate L2P (need %zu of memory)\n", map_size); diff --git a/drivers/macintosh/mac_hid.c b/drivers/macintosh/mac_hid.c index 28b8581b44dd..7af0c536d568 100644 --- a/drivers/macintosh/mac_hid.c +++ b/drivers/macintosh/mac_hid.c @@ -183,7 +183,8 @@ static void mac_hid_stop_emulation(void) } static int mac_hid_toggle_emumouse(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { int *valp = table->data; int old_val = *valp; diff --git a/drivers/mailbox/zynqmp-ipi-mailbox.c b/drivers/mailbox/zynqmp-ipi-mailbox.c index dcabf38859ec..bb7bb1738647 100644 --- a/drivers/mailbox/zynqmp-ipi-mailbox.c +++ b/drivers/mailbox/zynqmp-ipi-mailbox.c @@ -618,8 +618,11 @@ static void zynqmp_ipi_free_mboxes(struct zynqmp_ipi_pdata *pdata) i = pdata->num_mboxes; for (; i >= 0; i--) { ipi_mbox = &pdata->ipi_mboxes[i]; - if (device_is_registered(&ipi_mbox->dev)) - device_unregister(&ipi_mbox->dev); + if (ipi_mbox->dev.parent) { + mbox_controller_unregister(&ipi_mbox->mbox); + if (device_is_registered(&ipi_mbox->dev)) + device_unregister(&ipi_mbox->dev); + } } } diff --git a/drivers/md/dm-bufio.c b/drivers/md/dm-bufio.c index 97f4f5879fb7..e8c37d9a652d 100644 --- a/drivers/md/dm-bufio.c +++ b/drivers/md/dm-bufio.c @@ -400,13 +400,13 @@ static void *alloc_buffer_data(struct dm_bufio_client *c, gfp_t gfp_mask, */ if (gfp_mask & __GFP_NORETRY) { unsigned noio_flag = memalloc_noio_save(); - void *ptr = __vmalloc(c->block_size, gfp_mask); + void *ptr = __vmalloc(c->block_size, gfp_mask, PAGE_KERNEL); memalloc_noio_restore(noio_flag); return ptr; } - return __vmalloc(c->block_size, gfp_mask); + return __vmalloc(c->block_size, gfp_mask, PAGE_KERNEL); } /* diff --git a/drivers/md/dm-integrity.c b/drivers/md/dm-integrity.c index 38791b7e59ba..15580ba773e7 100644 --- a/drivers/md/dm-integrity.c +++ b/drivers/md/dm-integrity.c @@ -116,7 +116,7 @@ struct journal_sector { commit_id_t commit_id; }; -#define MAX_TAG_SIZE 255 +#define MAX_TAG_SIZE (JOURNAL_SECTOR_DATA - JOURNAL_MAC_PER_SECTOR - offsetof(struct journal_entry, last_bytes[MAX_SECTORS_PER_BLOCK])) #define METADATA_PADDING_SECTORS 8 diff --git a/drivers/md/dm.c b/drivers/md/dm.c index c84eb6a2e708..454c29f7ede3 100644 --- a/drivers/md/dm.c +++ b/drivers/md/dm.c @@ -2747,7 +2747,7 @@ static int __dm_suspend(struct mapped_device *md, struct dm_table *map, { bool do_lockfs = suspend_flags & DM_SUSPEND_LOCKFS_FLAG; bool noflush = suspend_flags & DM_SUSPEND_NOFLUSH_FLAG; - int r = 0; + int r; lockdep_assert_held(&md->suspend_lock); @@ -2800,7 +2800,7 @@ static int __dm_suspend(struct mapped_device *md, struct dm_table *map, * Stop md->queue before flushing md->wq in case request-based * dm defers requests to md->wq from md->queue. */ - if (map && dm_request_based(md)) + if (dm_request_based(md)) dm_stop_queue(md->queue); flush_workqueue(md->wq); @@ -2810,8 +2810,7 @@ static int __dm_suspend(struct mapped_device *md, struct dm_table *map, * We call dm_wait_for_completion to wait for all existing requests * to finish. */ - if (map) - r = dm_wait_for_completion(md, task_state); + r = dm_wait_for_completion(md, task_state); if (!r) set_bit(dmf_suspended_flag, &md->flags); diff --git a/drivers/media/i2c/ir-kbd-i2c.c b/drivers/media/i2c/ir-kbd-i2c.c index 0c1c54b5a6f5..56674173524f 100644 --- a/drivers/media/i2c/ir-kbd-i2c.c +++ b/drivers/media/i2c/ir-kbd-i2c.c @@ -284,9 +284,9 @@ static int get_key_avermedia_cardbus(struct IR_i2c *ir, enum rc_proto *protocol, static int ir_key_poll(struct IR_i2c *ir) { - enum rc_proto protocol = 0; - u32 scancode = 0; - u8 toggle = 0; + enum rc_proto protocol; + u32 scancode; + u8 toggle; int rc; dev_dbg(&ir->rc->dev, "%s\n", __func__); diff --git a/drivers/media/i2c/mt9v111.c b/drivers/media/i2c/mt9v111.c index 4dc56a9fd0b3..bb41bea950ac 100644 --- a/drivers/media/i2c/mt9v111.c +++ b/drivers/media/i2c/mt9v111.c @@ -534,8 +534,8 @@ static int mt9v111_calc_frame_rate(struct mt9v111_dev *mt9v111, static int mt9v111_hw_config(struct mt9v111_dev *mt9v111) { struct i2c_client *c = mt9v111->client; + unsigned int ret; u16 outfmtctrl2; - int ret; /* Force device reset. */ ret = __mt9v111_hw_reset(mt9v111); diff --git a/drivers/media/i2c/rj54n1cb0c.c b/drivers/media/i2c/rj54n1cb0c.c index b35b3e428686..4cc51e001874 100644 --- a/drivers/media/i2c/rj54n1cb0c.c +++ b/drivers/media/i2c/rj54n1cb0c.c @@ -1332,13 +1332,10 @@ static int rj54n1_probe(struct i2c_client *client, V4L2_CID_GAIN, 0, 127, 1, 66); v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops, V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1); - - if (rj54n1->hdl.error) { - ret = rj54n1->hdl.error; - goto err_free_ctrl; - } - rj54n1->subdev.ctrl_handler = &rj54n1->hdl; + if (rj54n1->hdl.error) + return rj54n1->hdl.error; + rj54n1->clk_div = clk_div; rj54n1->rect.left = RJ54N1_COLUMN_SKIP; rj54n1->rect.top = RJ54N1_ROW_SKIP; diff --git a/drivers/media/i2c/tc358743.c b/drivers/media/i2c/tc358743.c index e9297a758fe1..2dad35568586 100644 --- a/drivers/media/i2c/tc358743.c +++ b/drivers/media/i2c/tc358743.c @@ -2200,10 +2200,10 @@ static int tc358743_probe(struct i2c_client *client) err_work_queues: cec_unregister_adapter(state->cec_adap); if (!state->i2c_client->irq) { - del_timer_sync(&state->timer); + del_timer(&state->timer); flush_work(&state->work_i2c_poll); } - cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); + cancel_delayed_work(&state->delayed_work_enable_hotplug); mutex_destroy(&state->confctl_mutex); err_hdl: media_entity_cleanup(&sd->entity); diff --git a/drivers/media/mc/mc-devnode.c b/drivers/media/mc/mc-devnode.c index f8257aa5fc58..f249199dc616 100644 --- a/drivers/media/mc/mc-devnode.c +++ b/drivers/media/mc/mc-devnode.c @@ -50,6 +50,11 @@ static void media_devnode_release(struct device *cd) { struct media_devnode *devnode = to_media_devnode(cd); + mutex_lock(&media_devnode_lock); + /* Mark device node number as free */ + clear_bit(devnode->minor, media_devnode_nums); + mutex_unlock(&media_devnode_lock); + /* Release media_devnode and perform other cleanups as needed. */ if (devnode->release) devnode->release(devnode); @@ -278,7 +283,6 @@ void media_devnode_unregister(struct media_devnode *devnode) /* Delete the cdev on this minor as well */ cdev_device_del(&devnode->cdev, &devnode->dev); devnode->media_dev = NULL; - clear_bit(devnode->minor, media_devnode_nums); mutex_unlock(&media_devnode_lock); put_device(&devnode->dev); diff --git a/drivers/media/pci/b2c2/flexcop-pci.c b/drivers/media/pci/b2c2/flexcop-pci.c index 976e5dead34f..c9e6c7d66376 100644 --- a/drivers/media/pci/b2c2/flexcop-pci.c +++ b/drivers/media/pci/b2c2/flexcop-pci.c @@ -411,7 +411,7 @@ static void flexcop_pci_remove(struct pci_dev *pdev) struct flexcop_pci *fc_pci = pci_get_drvdata(pdev); if (irq_chk_intv > 0) - cancel_delayed_work_sync(&fc_pci->irq_check_work); + cancel_delayed_work(&fc_pci->irq_check_work); flexcop_pci_dma_exit(fc_pci); flexcop_device_exit(fc_pci->fc_dev); diff --git a/drivers/media/pci/cx18/cx18-queue.c b/drivers/media/pci/cx18/cx18-queue.c index 9b247ecf48d5..2f5df471dada 100644 --- a/drivers/media/pci/cx18/cx18-queue.c +++ b/drivers/media/pci/cx18/cx18-queue.c @@ -379,22 +379,14 @@ int cx18_stream_alloc(struct cx18_stream *s) break; } - buf->dma_handle = dma_map_single(&s->cx->pci_dev->dev, - buf->buf, s->buf_size, - s->dma); - if (dma_mapping_error(&s->cx->pci_dev->dev, buf->dma_handle)) { - kfree(buf->buf); - kfree(mdl); - kfree(buf); - break; - } - INIT_LIST_HEAD(&mdl->list); INIT_LIST_HEAD(&mdl->buf_list); mdl->id = s->mdl_base_idx; /* a somewhat safe value */ cx18_enqueue(s, mdl, &s->q_idle); INIT_LIST_HEAD(&buf->list); + buf->dma_handle = pci_map_single(s->cx->pci_dev, + buf->buf, s->buf_size, s->dma); cx18_buf_sync_for_cpu(s, buf); list_add_tail(&buf->list, &s->buf_pool); } diff --git a/drivers/media/pci/ivtv/ivtv-alsa-pcm.c b/drivers/media/pci/ivtv/ivtv-alsa-pcm.c index 0b6b77aa29dd..9e6019a159f4 100644 --- a/drivers/media/pci/ivtv/ivtv-alsa-pcm.c +++ b/drivers/media/pci/ivtv/ivtv-alsa-pcm.c @@ -150,12 +150,14 @@ static int snd_ivtv_pcm_capture_open(struct snd_pcm_substream *substream) s = &itv->streams[IVTV_ENC_STREAM_TYPE_PCM]; + v4l2_fh_init(&item.fh, &s->vdev); item.itv = itv; item.type = s->type; /* See if the stream is available */ if (ivtv_claim_stream(&item, item.type)) { /* No, it's already in use */ + v4l2_fh_exit(&item.fh); snd_ivtv_unlock(itvsc); return -EBUSY; } diff --git a/drivers/media/pci/ivtv/ivtv-driver.c b/drivers/media/pci/ivtv/ivtv-driver.c index e0d9b8f8c986..3f3f40ea890b 100644 --- a/drivers/media/pci/ivtv/ivtv-driver.c +++ b/drivers/media/pci/ivtv/ivtv-driver.c @@ -843,7 +843,7 @@ static int ivtv_setup_pci(struct ivtv *itv, struct pci_dev *pdev, IVTV_ERR("Can't enable device!\n"); return -EIO; } - if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) { + if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { IVTV_ERR("No suitable DMA available.\n"); return -EIO; } diff --git a/drivers/media/pci/ivtv/ivtv-driver.h b/drivers/media/pci/ivtv/ivtv-driver.h index 8a48b4533a02..90f38552bd36 100644 --- a/drivers/media/pci/ivtv/ivtv-driver.h +++ b/drivers/media/pci/ivtv/ivtv-driver.h @@ -325,7 +325,6 @@ struct ivtv_queue { }; struct ivtv; /* forward reference */ -struct ivtv_open_id; struct ivtv_stream { /* These first four fields are always set, even if the stream @@ -335,7 +334,7 @@ struct ivtv_stream { const char *name; /* name of the stream */ int type; /* stream type */ - struct ivtv_open_id *id; /* pointer to the streaming ivtv_open_id */ + struct v4l2_fh *fh; /* pointer to the streaming filehandle */ spinlock_t qlock; /* locks access to the queues */ unsigned long s_flags; /* status flags, see above */ int dma; /* can be PCI_DMA_TODEVICE, PCI_DMA_FROMDEVICE or PCI_DMA_NONE */ diff --git a/drivers/media/pci/ivtv/ivtv-fileops.c b/drivers/media/pci/ivtv/ivtv-fileops.c index 7ed0d2d85253..4202c3a47d33 100644 --- a/drivers/media/pci/ivtv/ivtv-fileops.c +++ b/drivers/media/pci/ivtv/ivtv-fileops.c @@ -38,16 +38,16 @@ int ivtv_claim_stream(struct ivtv_open_id *id, int type) if (test_and_set_bit(IVTV_F_S_CLAIMED, &s->s_flags)) { /* someone already claimed this stream */ - if (s->id == id) { + if (s->fh == &id->fh) { /* yes, this file descriptor did. So that's OK. */ return 0; } - if (s->id == NULL && (type == IVTV_DEC_STREAM_TYPE_VBI || + if (s->fh == NULL && (type == IVTV_DEC_STREAM_TYPE_VBI || type == IVTV_ENC_STREAM_TYPE_VBI)) { /* VBI is handled already internally, now also assign the file descriptor to this stream for external reading of the stream. */ - s->id = id; + s->fh = &id->fh; IVTV_DEBUG_INFO("Start Read VBI\n"); return 0; } @@ -55,7 +55,7 @@ int ivtv_claim_stream(struct ivtv_open_id *id, int type) IVTV_DEBUG_INFO("Stream %d is busy\n", type); return -EBUSY; } - s->id = id; + s->fh = &id->fh; if (type == IVTV_DEC_STREAM_TYPE_VBI) { /* Enable reinsertion interrupt */ ivtv_clear_irq_mask(itv, IVTV_IRQ_DEC_VBI_RE_INSERT); @@ -93,7 +93,7 @@ void ivtv_release_stream(struct ivtv_stream *s) struct ivtv *itv = s->itv; struct ivtv_stream *s_vbi; - s->id = NULL; + s->fh = NULL; if ((s->type == IVTV_DEC_STREAM_TYPE_VBI || s->type == IVTV_ENC_STREAM_TYPE_VBI) && test_bit(IVTV_F_S_INTERNAL_USE, &s->s_flags)) { /* this stream is still in use internally */ @@ -125,7 +125,7 @@ void ivtv_release_stream(struct ivtv_stream *s) /* was already cleared */ return; } - if (s_vbi->id) { + if (s_vbi->fh) { /* VBI stream still claimed by a file descriptor */ return; } @@ -349,7 +349,7 @@ static ssize_t ivtv_read(struct ivtv_stream *s, char __user *ubuf, size_t tot_co size_t tot_written = 0; int single_frame = 0; - if (atomic_read(&itv->capturing) == 0 && s->id == NULL) { + if (atomic_read(&itv->capturing) == 0 && s->fh == NULL) { /* shouldn't happen */ IVTV_DEBUG_WARN("Stream %s not initialized before read\n", s->name); return -EIO; @@ -819,7 +819,7 @@ void ivtv_stop_capture(struct ivtv_open_id *id, int gop_end) id->type == IVTV_ENC_STREAM_TYPE_VBI) && test_bit(IVTV_F_S_INTERNAL_USE, &s->s_flags)) { /* Also used internally, don't stop capturing */ - s->id = NULL; + s->fh = NULL; } else { ivtv_stop_v4l2_encode_stream(s, gop_end); @@ -903,7 +903,7 @@ int ivtv_v4l2_close(struct file *filp) v4l2_fh_exit(fh); /* Easy case first: this stream was never claimed by us */ - if (s->id != id) + if (s->fh != &id->fh) goto close_done; /* 'Unclaim' this stream */ diff --git a/drivers/media/pci/ivtv/ivtv-irq.c b/drivers/media/pci/ivtv/ivtv-irq.c index 404335e5aff4..b7aaa8b4a784 100644 --- a/drivers/media/pci/ivtv/ivtv-irq.c +++ b/drivers/media/pci/ivtv/ivtv-irq.c @@ -305,7 +305,7 @@ static void dma_post(struct ivtv_stream *s) ivtv_process_vbi_data(itv, buf, 0, s->type); s->q_dma.bytesused += buf->bytesused; } - if (s->id == NULL) { + if (s->fh == NULL) { ivtv_queue_move(s, &s->q_dma, NULL, &s->q_free, 0); return; } @@ -330,7 +330,7 @@ static void dma_post(struct ivtv_stream *s) set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags); } - if (s->id) + if (s->fh) wake_up(&s->waitq); } @@ -351,7 +351,7 @@ void ivtv_dma_stream_dec_prepare(struct ivtv_stream *s, u32 offset, int lock) /* Insert buffer block for YUV if needed */ if (s->type == IVTV_DEC_STREAM_TYPE_YUV && f->offset_y) { - if (yi->blanking_ptr) { + if (yi->blanking_dmaptr) { s->sg_pending[idx].src = yi->blanking_dmaptr; s->sg_pending[idx].dst = offset; s->sg_pending[idx].size = 720 * 16; diff --git a/drivers/media/pci/ivtv/ivtv-queue.c b/drivers/media/pci/ivtv/ivtv-queue.c index f9b192ab7e7c..7ac4615e92ea 100644 --- a/drivers/media/pci/ivtv/ivtv-queue.c +++ b/drivers/media/pci/ivtv/ivtv-queue.c @@ -188,7 +188,7 @@ int ivtv_stream_alloc(struct ivtv_stream *s) return 0; IVTV_DEBUG_INFO("Allocate %s%s stream: %d x %d buffers (%dkB total)\n", - s->dma != DMA_NONE ? "DMA " : "", + s->dma != PCI_DMA_NONE ? "DMA " : "", s->name, s->buffers, s->buf_size, s->buffers * s->buf_size / 1024); s->sg_pending = kzalloc(SGsize, GFP_KERNEL|__GFP_NOWARN); @@ -218,9 +218,8 @@ int ivtv_stream_alloc(struct ivtv_stream *s) return -ENOMEM; } if (ivtv_might_use_dma(s)) { - s->sg_handle = dma_map_single(&itv->pdev->dev, s->sg_dma, - sizeof(struct ivtv_sg_element), - DMA_TO_DEVICE); + s->sg_handle = pci_map_single(itv->pdev, s->sg_dma, + sizeof(struct ivtv_sg_element), PCI_DMA_TODEVICE); ivtv_stream_sync_for_cpu(s); } @@ -238,7 +237,7 @@ int ivtv_stream_alloc(struct ivtv_stream *s) } INIT_LIST_HEAD(&buf->list); if (ivtv_might_use_dma(s)) { - buf->dma_handle = dma_map_single(&s->itv->pdev->dev, + buf->dma_handle = pci_map_single(s->itv->pdev, buf->buf, s->buf_size + 256, s->dma); ivtv_buf_sync_for_cpu(s, buf); } @@ -261,8 +260,8 @@ void ivtv_stream_free(struct ivtv_stream *s) /* empty q_free */ while ((buf = ivtv_dequeue(s, &s->q_free))) { if (ivtv_might_use_dma(s)) - dma_unmap_single(&s->itv->pdev->dev, buf->dma_handle, - s->buf_size + 256, s->dma); + pci_unmap_single(s->itv->pdev, buf->dma_handle, + s->buf_size + 256, s->dma); kfree(buf->buf); kfree(buf); } @@ -270,9 +269,8 @@ void ivtv_stream_free(struct ivtv_stream *s) /* Free SG Array/Lists */ if (s->sg_dma != NULL) { if (s->sg_handle != IVTV_DMA_UNMAPPED) { - dma_unmap_single(&s->itv->pdev->dev, s->sg_handle, - sizeof(struct ivtv_sg_element), - DMA_TO_DEVICE); + pci_unmap_single(s->itv->pdev, s->sg_handle, + sizeof(struct ivtv_sg_element), PCI_DMA_TODEVICE); s->sg_handle = IVTV_DMA_UNMAPPED; } kfree(s->sg_pending); diff --git a/drivers/media/pci/ivtv/ivtv-streams.c b/drivers/media/pci/ivtv/ivtv-streams.c index 8b3f6ce6adf8..200d2100dbff 100644 --- a/drivers/media/pci/ivtv/ivtv-streams.c +++ b/drivers/media/pci/ivtv/ivtv-streams.c @@ -100,7 +100,7 @@ static struct { { /* IVTV_ENC_STREAM_TYPE_MPG */ "encoder MPG", VFL_TYPE_GRABBER, 0, - DMA_FROM_DEVICE, 0, + PCI_DMA_FROMDEVICE, 0, V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_TUNER | V4L2_CAP_AUDIO | V4L2_CAP_READWRITE, &ivtv_v4l2_enc_fops @@ -108,7 +108,7 @@ static struct { { /* IVTV_ENC_STREAM_TYPE_YUV */ "encoder YUV", VFL_TYPE_GRABBER, IVTV_V4L2_ENC_YUV_OFFSET, - DMA_FROM_DEVICE, 0, + PCI_DMA_FROMDEVICE, 0, V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_TUNER | V4L2_CAP_AUDIO | V4L2_CAP_READWRITE, &ivtv_v4l2_enc_fops @@ -116,7 +116,7 @@ static struct { { /* IVTV_ENC_STREAM_TYPE_VBI */ "encoder VBI", VFL_TYPE_VBI, 0, - DMA_FROM_DEVICE, 0, + PCI_DMA_FROMDEVICE, 0, V4L2_CAP_VBI_CAPTURE | V4L2_CAP_SLICED_VBI_CAPTURE | V4L2_CAP_TUNER | V4L2_CAP_AUDIO | V4L2_CAP_READWRITE, &ivtv_v4l2_enc_fops @@ -124,42 +124,42 @@ static struct { { /* IVTV_ENC_STREAM_TYPE_PCM */ "encoder PCM", VFL_TYPE_GRABBER, IVTV_V4L2_ENC_PCM_OFFSET, - DMA_FROM_DEVICE, 0, + PCI_DMA_FROMDEVICE, 0, V4L2_CAP_TUNER | V4L2_CAP_AUDIO | V4L2_CAP_READWRITE, &ivtv_v4l2_enc_fops }, { /* IVTV_ENC_STREAM_TYPE_RAD */ "encoder radio", VFL_TYPE_RADIO, 0, - DMA_NONE, 1, + PCI_DMA_NONE, 1, V4L2_CAP_RADIO | V4L2_CAP_TUNER, &ivtv_v4l2_radio_fops }, { /* IVTV_DEC_STREAM_TYPE_MPG */ "decoder MPG", VFL_TYPE_GRABBER, IVTV_V4L2_DEC_MPG_OFFSET, - DMA_TO_DEVICE, 0, + PCI_DMA_TODEVICE, 0, V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_AUDIO | V4L2_CAP_READWRITE, &ivtv_v4l2_dec_fops }, { /* IVTV_DEC_STREAM_TYPE_VBI */ "decoder VBI", VFL_TYPE_VBI, IVTV_V4L2_DEC_VBI_OFFSET, - DMA_NONE, 1, + PCI_DMA_NONE, 1, V4L2_CAP_SLICED_VBI_CAPTURE | V4L2_CAP_READWRITE, &ivtv_v4l2_enc_fops }, { /* IVTV_DEC_STREAM_TYPE_VOUT */ "decoder VOUT", VFL_TYPE_VBI, IVTV_V4L2_DEC_VOUT_OFFSET, - DMA_NONE, 1, + PCI_DMA_NONE, 1, V4L2_CAP_SLICED_VBI_OUTPUT | V4L2_CAP_AUDIO | V4L2_CAP_READWRITE, &ivtv_v4l2_dec_fops }, { /* IVTV_DEC_STREAM_TYPE_YUV */ "decoder YUV", VFL_TYPE_GRABBER, IVTV_V4L2_DEC_YUV_OFFSET, - DMA_TO_DEVICE, 0, + PCI_DMA_TODEVICE, 0, V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_AUDIO | V4L2_CAP_READWRITE, &ivtv_v4l2_dec_fops } @@ -179,7 +179,7 @@ static void ivtv_stream_init(struct ivtv *itv, int type) s->vdev.device_caps = ivtv_stream_info[type].v4l2_caps; if (ivtv_stream_info[type].pio) - s->dma = DMA_NONE; + s->dma = PCI_DMA_NONE; else s->dma = ivtv_stream_info[type].dma; s->buf_size = itv->stream_buf_size[type]; @@ -217,7 +217,7 @@ static int ivtv_prep_dev(struct ivtv *itv, int type) /* User explicitly selected 0 buffers for these streams, so don't create them. */ - if (ivtv_stream_info[type].dma != DMA_NONE && + if (ivtv_stream_info[type].dma != PCI_DMA_NONE && itv->options.kilobytes[type] == 0) { IVTV_INFO("Disabled %s device\n", ivtv_stream_info[type].name); return 0; diff --git a/drivers/media/pci/ivtv/ivtv-udma.c b/drivers/media/pci/ivtv/ivtv-udma.c index 7dff08696304..5f8883031c9c 100644 --- a/drivers/media/pci/ivtv/ivtv-udma.c +++ b/drivers/media/pci/ivtv/ivtv-udma.c @@ -81,10 +81,8 @@ void ivtv_udma_alloc(struct ivtv *itv) { if (itv->udma.SG_handle == 0) { /* Map DMA Page Array Buffer */ - itv->udma.SG_handle = dma_map_single(&itv->pdev->dev, - itv->udma.SGarray, - sizeof(itv->udma.SGarray), - DMA_TO_DEVICE); + itv->udma.SG_handle = pci_map_single(itv->pdev, itv->udma.SGarray, + sizeof(itv->udma.SGarray), PCI_DMA_TODEVICE); ivtv_udma_sync_for_cpu(itv); } } @@ -140,8 +138,7 @@ int ivtv_udma_setup(struct ivtv *itv, unsigned long ivtv_dest_addr, } /* Map SG List */ - dma->SG_length = dma_map_sg(&itv->pdev->dev, dma->SGlist, - dma->page_count, DMA_TO_DEVICE); + dma->SG_length = pci_map_sg(itv->pdev, dma->SGlist, dma->page_count, PCI_DMA_TODEVICE); /* Fill SG Array with new values */ ivtv_udma_fill_sg_array (dma, ivtv_dest_addr, 0, -1); @@ -166,8 +163,7 @@ void ivtv_udma_unmap(struct ivtv *itv) /* Unmap Scatterlist */ if (dma->SG_length) { - dma_unmap_sg(&itv->pdev->dev, dma->SGlist, dma->page_count, - DMA_TO_DEVICE); + pci_unmap_sg(itv->pdev, dma->SGlist, dma->page_count, PCI_DMA_TODEVICE); dma->SG_length = 0; } /* sync DMA */ @@ -186,14 +182,13 @@ void ivtv_udma_free(struct ivtv *itv) /* Unmap SG Array */ if (itv->udma.SG_handle) { - dma_unmap_single(&itv->pdev->dev, itv->udma.SG_handle, - sizeof(itv->udma.SGarray), DMA_TO_DEVICE); + pci_unmap_single(itv->pdev, itv->udma.SG_handle, + sizeof(itv->udma.SGarray), PCI_DMA_TODEVICE); } /* Unmap Scatterlist */ if (itv->udma.SG_length) { - dma_unmap_sg(&itv->pdev->dev, itv->udma.SGlist, - itv->udma.page_count, DMA_TO_DEVICE); + pci_unmap_sg(itv->pdev, itv->udma.SGlist, itv->udma.page_count, PCI_DMA_TODEVICE); } for (i = 0; i < IVTV_DMA_SG_OSD_ENT; i++) { diff --git a/drivers/media/pci/ivtv/ivtv-yuv.c b/drivers/media/pci/ivtv/ivtv-yuv.c index 1b101b032a35..cd2fe2d444c0 100644 --- a/drivers/media/pci/ivtv/ivtv-yuv.c +++ b/drivers/media/pci/ivtv/ivtv-yuv.c @@ -118,14 +118,13 @@ static int ivtv_yuv_prep_user_dma(struct ivtv *itv, struct ivtv_user_dma *dma, dma->page_count = 0; return -ENOMEM; } - dma->SG_length = dma_map_sg(&itv->pdev->dev, dma->SGlist, - dma->page_count, DMA_TO_DEVICE); + dma->SG_length = pci_map_sg(itv->pdev, dma->SGlist, dma->page_count, PCI_DMA_TODEVICE); /* Fill SG Array with new values */ ivtv_udma_fill_sg_array(dma, y_buffer_offset, uv_buffer_offset, y_size); /* If we've offset the y plane, ensure top area is blanked */ - if (f->offset_y && yi->blanking_ptr) { + if (f->offset_y && yi->blanking_dmaptr) { dma->SGarray[dma->SG_length].size = cpu_to_le32(720*16); dma->SGarray[dma->SG_length].src = cpu_to_le32(yi->blanking_dmaptr); dma->SGarray[dma->SG_length].dst = cpu_to_le32(IVTV_DECODER_OFFSET + yuv_offset[frame]); @@ -926,15 +925,7 @@ static void ivtv_yuv_init(struct ivtv *itv) /* We need a buffer for blanking when Y plane is offset - non-fatal if we can't get one */ yi->blanking_ptr = kzalloc(720 * 16, GFP_ATOMIC|__GFP_NOWARN); if (yi->blanking_ptr) { - yi->blanking_dmaptr = dma_map_single(&itv->pdev->dev, - yi->blanking_ptr, - 720 * 16, DMA_TO_DEVICE); - if (dma_mapping_error(&itv->pdev->dev, yi->blanking_dmaptr)) { - kfree(yi->blanking_ptr); - yi->blanking_ptr = NULL; - yi->blanking_dmaptr = 0; - IVTV_DEBUG_WARN("Failed to dma_map yuv blanking buffer\n"); - } + yi->blanking_dmaptr = pci_map_single(itv->pdev, yi->blanking_ptr, 720*16, PCI_DMA_TODEVICE); } else { yi->blanking_dmaptr = 0; IVTV_DEBUG_WARN("Failed to allocate yuv blanking buffer\n"); @@ -1278,8 +1269,7 @@ void ivtv_yuv_close(struct ivtv *itv) if (yi->blanking_ptr) { kfree(yi->blanking_ptr); yi->blanking_ptr = NULL; - dma_unmap_single(&itv->pdev->dev, yi->blanking_dmaptr, - 720 * 16, DMA_TO_DEVICE); + pci_unmap_single(itv->pdev, yi->blanking_dmaptr, 720*16, PCI_DMA_TODEVICE); } /* Invalidate the old dimension information */ diff --git a/drivers/media/platform/msm/cvp/cvp.c b/drivers/media/platform/msm/cvp/cvp.c index 76f7444a43b8..87adb4fbd975 100644 --- a/drivers/media/platform/msm/cvp/cvp.c +++ b/drivers/media/platform/msm/cvp/cvp.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -135,8 +135,6 @@ static int msm_cvp_initialize_core(struct platform_device *pdev, INIT_LIST_HEAD(&core->instances); mutex_init(&core->lock); mutex_init(&core->clk_lock); - mutex_init(&core->idr_mtx); - idr_init(&core->sess_idr); core->state = CVP_CORE_UNINIT; for (i = SYS_MSG_INDEX(SYS_MSG_START); @@ -508,8 +506,6 @@ static int msm_cvp_remove(struct platform_device *pdev) msm_cvp_free_platform_resources(&core->resources); sysfs_remove_group(&pdev->dev.kobj, &msm_cvp_core_attr_group); dev_set_drvdata(&pdev->dev, NULL); - idr_destroy(&core->sess_idr); - mutex_destroy(&core->idr_mtx); mutex_destroy(&core->lock); mutex_destroy(&core->clk_lock); kfree(core); diff --git a/drivers/media/platform/msm/cvp/cvp_hfi.c b/drivers/media/platform/msm/cvp/cvp_hfi.c index df430d2235f7..22340456d275 100644 --- a/drivers/media/platform/msm/cvp/cvp_hfi.c +++ b/drivers/media/platform/msm/cvp/cvp_hfi.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -30,7 +29,6 @@ #include "cvp_hfi_helper.h" #include "cvp_hfi_io.h" #include "msm_cvp_dsp.h" -#include "msm_cvp.h" #define FIRMWARE_SIZE 0X00A00000 #define REG_ADDR_OFFSET_BITMASK 0x000FFFFF @@ -471,7 +469,6 @@ static int __dsp_suspend(struct iris_hfi_device *device, bool force, u32 flags) { int rc; struct cvp_hal_session *temp; - struct msm_cvp_inst *inst = NULL; if (msm_cvp_dsp_disable) return 0; @@ -483,10 +480,9 @@ static int __dsp_suspend(struct iris_hfi_device *device, bool force, u32 flags) /* don't suspend if cvp session is not paused */ if (!(temp->flags & SESSION_PAUSE)) { - inst = (struct msm_cvp_inst *)temp->session_id; dprintk(CVP_DSP, "%s: cvp session %x not paused\n", - __func__, inst->sess_id); + __func__, hash32_ptr(temp)); return -EBUSY; } } @@ -2228,17 +2224,12 @@ static void __session_clean(struct cvp_hal_session *session) { struct cvp_hal_session *temp, *next; struct iris_hfi_device *device; - struct msm_cvp_core *core = NULL; - struct msm_cvp_inst *inst = NULL; - void *tmp = NULL; if (!session || !session->device) { dprintk(CVP_WARN, "%s: invalid params\n", __func__); return; } device = session->device; - core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list); - inst = (struct msm_cvp_inst *) session->session_id; dprintk(CVP_SESS, "deleted the session: %pK\n", session); /* * session might have been removed from the device list in @@ -2250,13 +2241,6 @@ static void __session_clean(struct cvp_hal_session *session) break; } } - /* Remove the IDR id assigned to this session */ - mutex_lock(&core->idr_mtx); - tmp = idr_remove(&core->sess_idr, inst->sess_id); - if (tmp != session) - dprintk(CVP_WARN, "%s: session\n", __func__); - mutex_unlock(&core->idr_mtx); - /* Poison the session handle with zeros */ *session = (struct cvp_hal_session){ {0} }; kfree(session); @@ -2294,9 +2278,6 @@ static int iris_hfi_session_init(void *device, void *session_id, struct cvp_hfi_cmd_sys_session_init_packet pkt; struct iris_hfi_device *dev; struct cvp_hal_session *s; - struct msm_cvp_core *core; - struct msm_cvp_inst *inst; - int id = 0; if (!device || !new_session) { dprintk(CVP_ERR, "%s - invalid input\n", __func__); @@ -2304,8 +2285,6 @@ static int iris_hfi_session_init(void *device, void *session_id, } dev = device; - core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list); - inst = session_id; mutex_lock(&dev->lock); s = kzalloc(sizeof(*s), GFP_KERNEL); @@ -2316,35 +2295,15 @@ static int iris_hfi_session_init(void *device, void *session_id, s->session_id = session_id; s->device = dev; - - mutex_lock(&core->idr_mtx); - idr_preload(GFP_KERNEL); - - /* Need to think if we can use core->lock or dev->lock or need a - * different new lock for this? - */ - id = idr_alloc(&core->sess_idr, (void *)s, 0x7FFF0000, INT_MAX, GFP_NOWAIT); - idr_preload_end(); - mutex_unlock(&core->idr_mtx); - if (id < 0) { - dprintk(CVP_ERR, - "%s: idr allocation failed for session %pK of inst %pK\n", - __func__, s, session_id); - goto err_session_init_fail; - } - dprintk(CVP_SESS, - "%s: inst %pK, session %pK, idr_id = 0x%x\n", __func__, session_id, s, id); + "%s: inst %pK, session %pK\n", __func__, session_id, s); list_add_tail(&s->list, &dev->sess_head); __set_default_sys_properties(device); - inst->sess_id = id; - if (call_hfi_pkt_op(dev, session_init, &pkt, s)) { dprintk(CVP_ERR, "session_init: failed to create packet\n"); - inst->sess_id = 0x0000DEAD; goto err_session_init_fail; } @@ -2358,7 +2317,6 @@ static int iris_hfi_session_init(void *device, void *session_id, err_session_init_fail: if (s) __session_clean(s); - inst->sess_id = 0; *new_session = NULL; mutex_unlock(&dev->lock); return -EINVAL; @@ -2920,11 +2878,9 @@ static struct cvp_hal_session *__get_session(struct iris_hfi_device *device, u32 session_id) { struct cvp_hal_session *temp = NULL; - struct msm_cvp_inst *inst = NULL; list_for_each_entry(temp, &device->sess_head, list) { - inst = (struct msm_cvp_inst *)temp->session_id; - if (session_id == inst->sess_id) + if (session_id == hash32_ptr(temp)) return temp; } @@ -3103,7 +3059,6 @@ static int __response_handler(struct iris_hfi_device *device) /* Process the packet types that we're interested in */ process_system_msg(info, device, raw_packet); - /* This session_id is a double pointer to the idr_id of session */ session_id = get_session_id(info); /* * hfi_process_msg_packet provides a session_id that's a hashed @@ -3115,6 +3070,11 @@ static int __response_handler(struct iris_hfi_device *device) if (session_id) { struct cvp_hal_session *session = NULL; + if (upper_32_bits((uintptr_t)*session_id) != 0) { + dprintk(CVP_ERR, + "Upper 32-bits != 0 for sess_id=%pK\n", + *session_id); + } session = __get_session(device, (u32)(uintptr_t)*session_id); if (!session) { diff --git a/drivers/media/platform/msm/cvp/cvp_hfi_api.h b/drivers/media/platform/msm/cvp/cvp_hfi_api.h index 0606cbd865e1..0a5ae01af744 100644 --- a/drivers/media/platform/msm/cvp/cvp_hfi_api.h +++ b/drivers/media/platform/msm/cvp/cvp_hfi_api.h @@ -357,8 +357,10 @@ struct cvp_hfi_device { int (*validate_session)(void *sess, const char *func); }; -typedef void (*hfi_cmd_response_callback) (u32 cmd, void *data); -typedef void (*msm_cvp_callback) (u32 response, void *callback); +typedef void (*hfi_cmd_response_callback) (enum hal_command_response cmd, + void *data); +typedef void (*msm_cvp_callback) (enum hal_command_response response, + void *callback); struct cvp_hfi_device *cvp_hfi_initialize(enum msm_cvp_hfi_type hfi_type, u32 device_id, struct msm_cvp_platform_resources *res, diff --git a/drivers/media/platform/msm/cvp/hfi_packetization.c b/drivers/media/platform/msm/cvp/hfi_packetization.c index edb6caaf1d34..107e2d744fff 100644 --- a/drivers/media/platform/msm/cvp/hfi_packetization.c +++ b/drivers/media/platform/msm/cvp/hfi_packetization.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include "hfi_packetization.h" @@ -209,7 +208,7 @@ inline int cvp_create_pkt_cmd_sys_session_init( pkt->size = sizeof(struct cvp_hfi_cmd_sys_session_init_packet); pkt->packet_type = HFI_CMD_SYS_SESSION_INIT; - pkt->session_id = inst->sess_id; + pkt->session_id = hash32_ptr(session); pkt->session_type = inst->prop.type; pkt->session_kmask = inst->prop.kernel_mask; pkt->session_prio = inst->prop.priority; @@ -267,14 +266,13 @@ int cvp_create_pkt_cmd_session_cmd(struct cvp_hal_session_cmd_pkt *pkt, int pkt_type, struct cvp_hal_session *session) { int rc = 0; - struct msm_cvp_inst *inst = session->session_id; if (!pkt) return -EINVAL; pkt->size = sizeof(struct cvp_hal_session_cmd_pkt); pkt->packet_type = pkt_type; - pkt->session_id = inst->sess_id; + pkt->session_id = hash32_ptr(session); return rc; } @@ -307,14 +305,13 @@ int cvp_create_pkt_cmd_session_set_buffers( { int rc = 0; struct cvp_hfi_cmd_session_set_buffers_packet *pkt; - struct msm_cvp_inst *inst = session->session_id; - if (!cmd || !session || !inst) + if (!cmd || !session) return -EINVAL; pkt = (struct cvp_hfi_cmd_session_set_buffers_packet *)cmd; pkt->packet_type = HFI_CMD_SESSION_CVP_SET_BUFFERS; - pkt->session_id = inst->sess_id; + pkt->session_id = hash32_ptr(session); pkt->buf_type.iova = iova; pkt->buf_type.size = size; pkt->size = sizeof(struct cvp_hfi_cmd_session_set_buffers_packet); @@ -327,14 +324,13 @@ int cvp_create_pkt_cmd_session_release_buffers( struct cvp_hal_session *session) { struct cvp_session_release_buffers_packet *pkt; - struct msm_cvp_inst *inst = session->session_id; - if (!cmd || !session || !inst) + if (!cmd || !session) return -EINVAL; pkt = (struct cvp_session_release_buffers_packet *)cmd; pkt->packet_type = HFI_CMD_SESSION_CVP_RELEASE_BUFFERS; - pkt->session_id = inst->sess_id; + pkt->session_id = hash32_ptr(session); pkt->num_buffers = 1; pkt->buffer_type = 0; pkt->size = sizeof(struct cvp_session_release_buffers_packet) + @@ -351,7 +347,6 @@ int cvp_create_pkt_cmd_session_send( int def_idx; struct cvp_hal_session_cmd_pkt *ptr = (struct cvp_hal_session_cmd_pkt *)in_pkt; - struct msm_cvp_inst *inst = session->session_id; if (!out_pkt || !in_pkt || !session) return -EINVAL; @@ -359,7 +354,7 @@ int cvp_create_pkt_cmd_session_send( if (ptr->size > MAX_HFI_PKT_SIZE * sizeof(unsigned int)) goto error_hfi_packet; - if (ptr->session_id != inst->sess_id) + if (ptr->session_id != hash32_ptr(session)) goto error_hfi_packet; def_idx = get_pkt_index(ptr); diff --git a/drivers/media/platform/msm/cvp/hfi_response_handler.c b/drivers/media/platform/msm/cvp/hfi_response_handler.c index 3e0d3b717dc1..61a5aadbe34a 100644 --- a/drivers/media/platform/msm/cvp/hfi_response_handler.c +++ b/drivers/media/platform/msm/cvp/hfi_response_handler.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -462,7 +462,7 @@ static struct msm_cvp_inst *cvp_get_inst_from_id(struct msm_cvp_core *core, retry: if (mutex_trylock(&core->lock)) { list_for_each_entry(inst, &core->instances, list) { - if (inst->sess_id == session_id) { + if (hash32_ptr(inst->session) == session_id) { match = true; break; } diff --git a/drivers/media/platform/msm/cvp/msm_cvp.c b/drivers/media/platform/msm/cvp/msm_cvp.c index 346f21641519..fefc06d6aee2 100644 --- a/drivers/media/platform/msm/cvp/msm_cvp.c +++ b/drivers/media/platform/msm/cvp/msm_cvp.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include "msm_cvp.h" @@ -15,47 +14,6 @@ struct cvp_power_level { unsigned long bw_sum; }; -void *get_sessObj_from_idr(struct msm_cvp_inst *inst) -{ - void *sessObj = NULL; - struct msm_cvp_core *core = NULL; - - if (!inst || !inst->core) { - dprintk(CVP_ERR, "%s: invalid params\n", __func__); - return NULL; - } - - core = inst->core; - mutex_lock(&core->idr_mtx); - sessObj = idr_find(&core->sess_idr, inst->sess_id); - mutex_unlock(&core->idr_mtx); - if (!sessObj) - dprintk(CVP_ERR, "%s: Could not find the sess obj for given idr id\n", - __func__); - - return sessObj; -} - -u32 get_sessId_from_idr(void *session) -{ - void *ptr = NULL; - u32 sess_id = -1; - struct msm_cvp_core *core = NULL; - - core = list_first_entry(&cvp_driver->cores, struct msm_cvp_core, list); - if (!session || !core) - return -EINVAL; - mutex_lock(&core->idr_mtx); - idr_for_each_entry(&core->sess_idr, ptr, sess_id) { - if (ptr == session) { - mutex_unlock(&core->idr_mtx); - return sess_id; - } - } - mutex_unlock(&core->idr_mtx); - return sess_id; -} - static int msm_cvp_get_session_info(struct msm_cvp_inst *inst, struct cvp_kmd_session_info *session) { @@ -72,7 +30,7 @@ static int msm_cvp_get_session_info(struct msm_cvp_inst *inst, return -ECONNRESET; s->cur_cmd_type = CVP_KMD_GET_SESSION_INFO; - session->session_id = inst->sess_id; + session->session_id = hash32_ptr(inst->session); dprintk(CVP_SESS, "%s: id 0x%x\n", __func__, session->session_id); s->cur_cmd_type = 0; @@ -741,13 +699,6 @@ static int msm_cvp_session_process_hfi_fence(struct msm_cvp_inst *inst, f->output_index = kfc->output_index; } - if (f->num_fences >= (MAX_HFI_FENCE_SIZE / 2)) { - dprintk(CVP_ERR, "%s: Max number of fences exceeded! Max number supported: %d", - __func__, (MAX_HFI_FENCE_SIZE / 2)); - cvp_free_fence_data(f); - msm_cvp_unmap_frame(inst, pkt->client_data.kdata); - goto exit; - } dprintk(CVP_SYNX, "%s: frameID %llu ktid %llu\n", __func__, f->frame_id, pkt->client_data.kdata); @@ -1276,7 +1227,7 @@ static int msm_cvp_session_stop(struct msm_cvp_inst *inst, sq->state = QUEUE_STOP; pr_info(CVP_DBG_TAG "Stop session: %pK session_id = %d\n", - "sess", inst, inst->sess_id); + "sess", inst, hash32_ptr(inst->session)); spin_unlock(&sq->lock); wake_up_all(&inst->session_queue.wq); @@ -1300,7 +1251,7 @@ int msm_cvp_session_queue_stop(struct msm_cvp_inst *inst) sq->state = QUEUE_STOP; dprintk(CVP_SESS, "Stop session queue: %pK session_id = %d\n", - inst, inst->sess_id); + inst, hash32_ptr(inst->session)); spin_unlock(&sq->lock); wake_up_all(&inst->session_queue.wq); @@ -1600,7 +1551,7 @@ static void cvp_clean_fence_queue(struct msm_cvp_inst *inst, int synx_state) ktid = f->pkt->client_data.kdata & (FENCE_BIT - 1); dprintk(CVP_SYNX, "%s: (%#x) flush frame %llu %llu wait_list\n", - __func__, inst->sess_id, ktid, f->frame_id); + __func__, hash32_ptr(inst->session), ktid, f->frame_id); list_del_init(&f->list); msm_cvp_unmap_frame(inst, f->pkt->client_data.kdata); @@ -1613,7 +1564,7 @@ static void cvp_clean_fence_queue(struct msm_cvp_inst *inst, int synx_state) ktid = f->pkt->client_data.kdata & (FENCE_BIT - 1); dprintk(CVP_SYNX, "%s: (%#x)flush frame %llu %llu sched_list\n", - __func__, inst->sess_id, ktid, f->frame_id); + __func__, hash32_ptr(inst->session), ktid, f->frame_id); cvp_cancel_synx(inst, CVP_INPUT_SYNX, f, synx_state); } @@ -1661,14 +1612,14 @@ static int cvp_flush_all(struct msm_cvp_inst *inst) return -ECONNRESET; dprintk(CVP_SESS, "session %llx (%#x)flush all starts\n", - inst, inst->sess_id); + inst, hash32_ptr(inst->session)); q = &inst->fence_cmd_queue; hdev = inst->core->device; cvp_clean_fence_queue(inst, SYNX_STATE_SIGNALED_CANCEL); dprintk(CVP_SESS, "%s: (%#x) send flush to fw\n", - __func__, inst->sess_id); + __func__, hash32_ptr(inst->session)); /* Send flush to FW */ rc = call_hfi_op(hdev, session_flush, (void *)inst->session); @@ -1685,7 +1636,7 @@ static int cvp_flush_all(struct msm_cvp_inst *inst) __func__, rc); dprintk(CVP_SESS, "%s: (%#x) received flush from fw\n", - __func__, inst->sess_id); + __func__, hash32_ptr(inst->session)); exit: rc = cvp_drain_fence_sched_list(inst); @@ -1908,10 +1859,10 @@ int msm_cvp_session_deinit(struct msm_cvp_inst *inst) return -EINVAL; } dprintk(CVP_SESS, "%s: inst %pK (%#x)\n", __func__, - inst, inst->sess_id); + inst, hash32_ptr(inst->session)); - session = (struct cvp_hal_session *)get_sessObj_from_idr(inst); - if (!session || session != inst->session) + session = (struct cvp_hal_session *)inst->session; + if (!session) return rc; rc = msm_cvp_comm_try_state(inst, MSM_CVP_CLOSE_DONE); @@ -1932,7 +1883,7 @@ int msm_cvp_session_init(struct msm_cvp_inst *inst) } dprintk(CVP_SESS, "%s: inst %pK (%#x)\n", __func__, - inst, inst->sess_id); + inst, hash32_ptr(inst->session)); /* set default frequency */ inst->clk_data.core_id = 0; diff --git a/drivers/media/platform/msm/cvp/msm_cvp.h b/drivers/media/platform/msm/cvp/msm_cvp.h index b8ae6068de35..b21864b46f1c 100644 --- a/drivers/media/platform/msm/cvp/msm_cvp.h +++ b/drivers/media/platform/msm/cvp/msm_cvp.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #ifndef _MSM_CVP_H_ @@ -35,6 +34,4 @@ int msm_cvp_session_init(struct msm_cvp_inst *inst); int msm_cvp_session_deinit(struct msm_cvp_inst *inst); int msm_cvp_session_queue_stop(struct msm_cvp_inst *inst); int cvp_stop_clean_fence_queue(struct msm_cvp_inst *inst); -void *get_sessObj_from_idr(struct msm_cvp_inst *inst); -u32 get_sessId_from_idr(void *session); #endif diff --git a/drivers/media/platform/msm/cvp/msm_cvp_buf.c b/drivers/media/platform/msm/cvp/msm_cvp_buf.c index c16eed33efd3..995c111edb7d 100644 --- a/drivers/media/platform/msm/cvp/msm_cvp_buf.c +++ b/drivers/media/platform/msm/cvp/msm_cvp_buf.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "msm_cvp_common.h" @@ -14,7 +14,7 @@ do { \ clear_bit(idx, &inst->dma_cache.usage_bitmap); \ dprintk(CVP_MEM, "clear %x bit %d dma_cache bitmap 0x%llx\n", \ - inst->sess_id, smem->bitmap_index, \ + hash32_ptr(inst->session), smem->bitmap_index, \ inst->dma_cache.usage_bitmap); \ } while (0) @@ -22,7 +22,7 @@ do { \ set_bit(idx, &inst->dma_cache.usage_bitmap); \ dprintk(CVP_MEM, "Set %x bit %d dma_cache bitmap 0x%llx\n", \ - inst->sess_id, idx, \ + hash32_ptr(inst->session), idx, \ inst->dma_cache.usage_bitmap); \ } while (0) @@ -36,7 +36,7 @@ void print_smem(u32 tag, const char *str, struct msm_cvp_inst *inst, if (smem->dma_buf) { dprintk(tag, "%s: %x : %s size %d flags %#x iova %#x idx %d ref %d", - str, inst->sess_id, smem->dma_buf->name, + str, hash32_ptr(inst->session), smem->dma_buf->name, smem->size, smem->flags, smem->device_addr, smem->bitmap_index, smem->refcount); } @@ -51,13 +51,13 @@ static void print_internal_buffer(u32 tag, const char *str, if (cbuf->smem->dma_buf) { dprintk(tag, "%s: %x : fd %d off %d %s size %d iova %#x", - str, inst->sess_id, cbuf->fd, + str, hash32_ptr(inst->session), cbuf->fd, cbuf->offset, cbuf->smem->dma_buf->name, cbuf->size, cbuf->smem->device_addr); } else { dprintk(tag, "%s: %x : idx %2d fd %d off %d size %d iova %#x", - str, inst->sess_id, cbuf->fd, + str, hash32_ptr(inst->session), cbuf->fd, cbuf->offset, cbuf->size, cbuf->smem->device_addr); } } @@ -77,7 +77,7 @@ void print_client_buffer(u32 tag, const char *str, dprintk(tag, "%s: %x : idx %2d fd %d off %d size %d type %d flags 0x%x\n", - str, inst->sess_id, cbuf->index, cbuf->fd, + str, hash32_ptr(inst->session), cbuf->index, cbuf->fd, cbuf->offset, cbuf->size, cbuf->type, cbuf->flags); } @@ -154,7 +154,7 @@ int msm_cvp_map_buf_dsp(struct msm_cvp_inst *inst, struct cvp_kmd_buffer *buf) } if (buf->index) { - rc = cvp_dsp_register_buffer(inst->sess_id, buf->fd, + rc = cvp_dsp_register_buffer(hash32_ptr(session), buf->fd, smem->dma_buf->size, buf->size, buf->offset, buf->index, (uint32_t)smem->device_addr); if (rc) { @@ -227,7 +227,7 @@ int msm_cvp_unmap_buf_dsp(struct msm_cvp_inst *inst, struct cvp_kmd_buffer *buf) } if (buf->index) { - rc = cvp_dsp_deregister_buffer(inst->sess_id, buf->fd, + rc = cvp_dsp_deregister_buffer(hash32_ptr(session), buf->fd, cbuf->smem->dma_buf->size, buf->size, buf->offset, buf->index, (uint32_t)cbuf->smem->device_addr); if (rc) { @@ -545,7 +545,7 @@ void msm_cvp_unmap_frame(struct msm_cvp_inst *inst, u64 ktid) ktid &= (FENCE_BIT - 1); dprintk(CVP_MEM, "%s: (%#x) unmap frame %llu\n", - __func__, inst->sess_id, ktid); + __func__, hash32_ptr(inst->session), ktid); found = false; mutex_lock(&inst->frames.lock); @@ -587,7 +587,7 @@ int msm_cvp_unmap_user_persist(struct msm_cvp_inst *inst, smem = pbuf->smem; dprintk(CVP_MEM, "unmap persist: %x %d %d %#x", - inst->sess_id, pbuf->fd, + hash32_ptr(inst->session), pbuf->fd, pbuf->size, smem->device_addr); if (smem->bitmap_index >= MAX_DMABUF_NUMS) { @@ -785,7 +785,7 @@ int msm_cvp_session_deinit_buffers(struct msm_cvp_inst *inst) list_for_each_entry_safe(cbuf, dummy, &inst->cvpdspbufs.list, list) { print_internal_buffer(CVP_MEM, "remove dspbufs", inst, cbuf); - rc = cvp_dsp_deregister_buffer(inst->sess_id, + rc = cvp_dsp_deregister_buffer(hash32_ptr(session), cbuf->fd, cbuf->smem->dma_buf->size, cbuf->size, cbuf->offset, cbuf->index, (uint32_t)cbuf->smem->device_addr); @@ -955,7 +955,7 @@ int cvp_release_arp_buffers(struct msm_cvp_inst *inst) if (buf->ownership == DRIVER) { dprintk(CVP_MEM, "%s: %x : fd %d %s size %d", - "free arp", inst->sess_id, buf->fd, + "free arp", hash32_ptr(inst->session), buf->fd, smem->dma_buf->name, buf->size); msm_cvp_smem_free(smem); kmem_cache_free(cvp_driver->smem_cache, smem); diff --git a/drivers/media/platform/msm/cvp/msm_cvp_common.c b/drivers/media/platform/msm/cvp/msm_cvp_common.c index 75c9fe378f7b..69787e51cc3d 100644 --- a/drivers/media/platform/msm/cvp/msm_cvp_common.c +++ b/drivers/media/platform/msm/cvp/msm_cvp_common.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -196,31 +195,23 @@ struct msm_cvp_inst *cvp_get_inst_validate(struct msm_cvp_core *core, { int rc = 0; struct cvp_hfi_device *hdev; - struct msm_cvp_inst *inst; - void *sessObj = NULL; + struct msm_cvp_inst *s; - inst = cvp_get_inst(core, session_id); - if (!inst) { - dprintk(CVP_ERR, "%s Inst doesn't exit\n", + s = cvp_get_inst(core, session_id); + if (!s) { + dprintk(CVP_ERR, "%s session doesn't exit\n", __builtin_return_address(0)); return NULL; } - sessObj = get_sessObj_from_idr(inst); - if (!sessObj || sessObj != inst->session) { - dprintk(CVP_ERR, - "Either sessionObj is null or not matching with inst->session\n"); - return NULL; - } - - hdev = inst->core->device; - rc = call_hfi_op(hdev, validate_session, sessObj, __func__); + hdev = s->core->device; + rc = call_hfi_op(hdev, validate_session, s->session, __func__); if (rc) { - cvp_put_inst(inst); - inst = NULL; + cvp_put_inst(s); + s = NULL; } - return inst; + return s; } static void cvp_handle_session_cmd_done(enum hal_command_response cmd, @@ -495,7 +486,7 @@ static void handle_session_init_done(enum hal_command_response cmd, void *data) } dprintk(CVP_SESS, "%s: cvp session %#x\n", __func__, - inst->sess_id); + hash32_ptr(inst->session)); signal_session_msg_receipt(cmd, inst); cvp_put_inst(inst); @@ -577,7 +568,7 @@ static void handle_session_error(enum hal_command_response cmd, void *data) hdev = inst->core->device; dprintk(CVP_ERR, "Session error received for inst %pK session %x\n", - inst, inst->sess_id); + inst, hash32_ptr(inst->session)); if (response->status == CVP_ERR_MAX_CLIENTS) { dprintk(CVP_WARN, "Too many clients, rejecting %pK", inst); @@ -767,7 +758,7 @@ static void handle_session_close(enum hal_command_response cmd, void *data) cvp_put_inst(inst); } -void cvp_handle_cmd_response(u32 cmd, void *data) +void cvp_handle_cmd_response(enum hal_command_response cmd, void *data) { dprintk(CVP_HFI, "Command response = %d\n", cmd); switch (cmd) { @@ -910,7 +901,7 @@ static int msm_comm_session_abort(struct msm_cvp_inst *inst) abort_completion = SESSION_MSG_INDEX(HAL_SESSION_ABORT_DONE); dprintk(CVP_WARN, "%s: inst %pK session %x\n", __func__, - inst, inst->sess_id); + inst, hash32_ptr(inst->session)); rc = call_hfi_op(hdev, session_abort, (void *)inst->session); if (rc) { dprintk(CVP_ERR, @@ -923,7 +914,7 @@ static int msm_comm_session_abort(struct msm_cvp_inst *inst) inst->core->resources.msm_cvp_hw_rsp_timeout)); if (!rc) { dprintk(CVP_ERR, "%s: inst %pK session %x abort timed out\n", - __func__, inst, inst->sess_id); + __func__, inst, hash32_ptr(inst->session)); call_hfi_op(hdev, flush_debug_queue, hdev->hfi_device_data); dump_hfi_queue(hdev->hfi_device_data); msm_cvp_comm_generate_sys_error(inst); @@ -1277,7 +1268,7 @@ int msm_cvp_comm_try_state(struct msm_cvp_inst *inst, int state) } dprintk(CVP_SESS, "Trying to move inst: %pK (%#x) from: %#x to %#x\n", - inst, inst->sess_id, inst->state, state); + inst, hash32_ptr(inst->session), inst->state, state); mutex_lock(&inst->sync_lock); if (inst->state == MSM_CVP_CORE_INVALID) { @@ -1290,7 +1281,7 @@ int msm_cvp_comm_try_state(struct msm_cvp_inst *inst, int state) flipped_state = get_flipped_state(inst->state, state); dprintk(CVP_SESS, "inst: %pK (%#x) flipped_state = %#x %x\n", - inst, inst->sess_id, flipped_state, state); + inst, hash32_ptr(inst->session), flipped_state, state); switch (flipped_state) { case MSM_CVP_CORE_UNINIT_DONE: case MSM_CVP_CORE_INIT: @@ -1500,7 +1491,7 @@ int msm_cvp_comm_kill_session(struct msm_cvp_inst *inst) return 0; } dprintk(CVP_WARN, "%s: inst %pK, session %x state %d\n", __func__, - inst, inst->sess_id, inst->state); + inst, hash32_ptr(inst->session), inst->state); /* * We're internally forcibly killing the session, if fw is aware of * the session send session_abort to firmware to clean up and release @@ -1512,7 +1503,7 @@ int msm_cvp_comm_kill_session(struct msm_cvp_inst *inst) if (rc) { dprintk(CVP_ERR, "%s: inst %pK session %x abort failed\n", - __func__, inst, inst->sess_id); + __func__, inst, hash32_ptr(inst->session)); change_cvp_inst_state(inst, MSM_CVP_CORE_INVALID); } else { change_cvp_inst_state(inst, MSM_CVP_CORE_UNINIT); diff --git a/drivers/media/platform/msm/cvp/msm_cvp_core.c b/drivers/media/platform/msm/cvp/msm_cvp_core.c index b98d43730988..5347eade1782 100644 --- a/drivers/media/platform/msm/cvp/msm_cvp_core.c +++ b/drivers/media/platform/msm/cvp/msm_cvp_core.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -166,7 +165,7 @@ void *msm_cvp_open(int core_id, int session_type) list_for_each_entry(inst, &core->instances, list) dprintk(CVP_ERR, "inst %pK, cmd %d id %d\n", inst, inst->cur_cmd_type, - inst->sess_id); + hash32_ptr(inst->session)); mutex_unlock(&core->lock); return NULL; @@ -370,7 +369,7 @@ int msm_cvp_destroy(struct msm_cvp_inst *inst) synx_uninitialize(inst->synx_session_id); pr_info(CVP_DBG_TAG "Closed cvp instance: %pK session_id = %d\n", - "sess", inst, inst->sess_id); + "sess", inst, hash32_ptr(inst->session)); if (inst->cur_cmd_type) dprintk(CVP_ERR, "deleted instance has pending cmd %d\n", inst->cur_cmd_type); diff --git a/drivers/media/platform/msm/cvp/msm_cvp_internal.h b/drivers/media/platform/msm/cvp/msm_cvp_internal.h index 8bd02fce164e..533e16cfce56 100644 --- a/drivers/media/platform/msm/cvp/msm_cvp_internal.h +++ b/drivers/media/platform/msm/cvp/msm_cvp_internal.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #ifndef _MSM_CVP_INTERNAL_H_ @@ -291,8 +290,6 @@ struct msm_cvp_core { unsigned long curr_freq; struct cvp_cycle_info dyn_clk; atomic64_t kernel_trans_id; - struct idr sess_idr; - struct mutex idr_mtx; }; struct msm_cvp_inst { @@ -304,7 +301,6 @@ struct msm_cvp_inst { struct cvp_session_queue session_queue_fence; struct cvp_session_event event_handler; void *session; - u32 sess_id; enum instance_state state; struct msm_cvp_list freqs; struct msm_cvp_list persistbufs; @@ -326,7 +322,7 @@ struct msm_cvp_inst { extern struct msm_cvp_drv *cvp_driver; -void cvp_handle_cmd_response(u32 cmd, void *data); +void cvp_handle_cmd_response(enum hal_command_response cmd, void *data); int msm_cvp_trigger_ssr(struct msm_cvp_core *core, enum hal_ssr_trigger_type type); int msm_cvp_noc_error_info(struct msm_cvp_core *core); diff --git a/drivers/media/platform/msm/cvp/msm_cvp_synx.c b/drivers/media/platform/msm/cvp/msm_cvp_synx.c index 4580c582174b..f70fb4013058 100644 --- a/drivers/media/platform/msm/cvp/msm_cvp_synx.c +++ b/drivers/media/platform/msm/cvp/msm_cvp_synx.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include "msm_cvp_common.h" @@ -21,7 +20,7 @@ void cvp_dump_fence_queue(struct msm_cvp_inst *inst) ssid = inst->synx_session_id; mutex_lock(&q->lock); dprintk(CVP_WARN, "inst %x fence q mode %d, ssid %d\n", - inst->sess_id, q->mode, ssid.client_id); + hash32_ptr(inst->session), q->mode, ssid.client_id); dprintk(CVP_WARN, "fence cmdq wait list:\n"); list_for_each_entry(f, &q->wait_list, list) { diff --git a/drivers/media/platform/qcom/venus/hfi_msgs.c b/drivers/media/platform/qcom/venus/hfi_msgs.c index 990c53398b9b..5694d18b43d5 100644 --- a/drivers/media/platform/qcom/venus/hfi_msgs.c +++ b/drivers/media/platform/qcom/venus/hfi_msgs.c @@ -27,10 +27,8 @@ static void event_seq_changed(struct venus_core *core, struct venus_inst *inst, struct hfi_colour_space *colour_info; struct hfi_buffer_requirements *bufreq; struct hfi_extradata_input_crop *crop; - struct hfi_dpb_counts *dpb_count; - u32 ptype, rem_bytes; - u32 size_read = 0; u8 *data_ptr; + u32 ptype; inst->error = HFI_ERR_NONE; @@ -40,120 +38,80 @@ static void event_seq_changed(struct venus_core *core, struct venus_inst *inst, break; default: inst->error = HFI_ERR_SESSION_INVALID_PARAMETER; - inst->ops->event_notify(inst, EVT_SYS_EVENT_CHANGE, &event); - return; + goto done; } event.event_type = pkt->event_data1; num_properties_changed = pkt->event_data2; - if (!num_properties_changed) - goto error; + if (!num_properties_changed) { + inst->error = HFI_ERR_SESSION_INSUFFICIENT_RESOURCES; + goto done; + } data_ptr = (u8 *)&pkt->ext_event_data[0]; - rem_bytes = pkt->shdr.hdr.size - sizeof(*pkt); - do { - if (rem_bytes < sizeof(u32)) - goto error; ptype = *((u32 *)data_ptr); - - data_ptr += sizeof(u32); - rem_bytes -= sizeof(u32); - switch (ptype) { case HFI_PROPERTY_PARAM_FRAME_SIZE: - if (rem_bytes < sizeof(struct hfi_framesize)) - goto error; - + data_ptr += sizeof(u32); frame_sz = (struct hfi_framesize *)data_ptr; event.width = frame_sz->width; event.height = frame_sz->height; - size_read = sizeof(struct hfi_framesize); + data_ptr += sizeof(*frame_sz); break; case HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT: - if (rem_bytes < sizeof(struct hfi_profile_level)) - goto error; - + data_ptr += sizeof(u32); profile_level = (struct hfi_profile_level *)data_ptr; event.profile = profile_level->profile; event.level = profile_level->level; - size_read = sizeof(struct hfi_profile_level); + data_ptr += sizeof(*profile_level); break; case HFI_PROPERTY_PARAM_VDEC_PIXEL_BITDEPTH: - if (rem_bytes < sizeof(struct hfi_bit_depth)) - goto error; - + data_ptr += sizeof(u32); pixel_depth = (struct hfi_bit_depth *)data_ptr; event.bit_depth = pixel_depth->bit_depth; - size_read = sizeof(struct hfi_bit_depth); + data_ptr += sizeof(*pixel_depth); break; case HFI_PROPERTY_PARAM_VDEC_PIC_STRUCT: - if (rem_bytes < sizeof(struct hfi_pic_struct)) - goto error; - + data_ptr += sizeof(u32); pic_struct = (struct hfi_pic_struct *)data_ptr; event.pic_struct = pic_struct->progressive_only; - size_read = sizeof(struct hfi_pic_struct); + data_ptr += sizeof(*pic_struct); break; case HFI_PROPERTY_PARAM_VDEC_COLOUR_SPACE: - if (rem_bytes < sizeof(struct hfi_colour_space)) - goto error; - + data_ptr += sizeof(u32); colour_info = (struct hfi_colour_space *)data_ptr; event.colour_space = colour_info->colour_space; - size_read = sizeof(struct hfi_colour_space); + data_ptr += sizeof(*colour_info); break; case HFI_PROPERTY_CONFIG_VDEC_ENTROPY: - if (rem_bytes < sizeof(u32)) - goto error; - + data_ptr += sizeof(u32); event.entropy_mode = *(u32 *)data_ptr; - size_read = sizeof(u32); + data_ptr += sizeof(u32); break; case HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS: - if (rem_bytes < sizeof(struct hfi_buffer_requirements)) - goto error; - + data_ptr += sizeof(u32); bufreq = (struct hfi_buffer_requirements *)data_ptr; event.buf_count = HFI_BUFREQ_COUNT_MIN(bufreq, ver); data_ptr += sizeof(*bufreq); - event.buf_count = hfi_bufreq_get_count_min(bufreq, ver); - size_read = sizeof(struct hfi_buffer_requirements); break; case HFI_INDEX_EXTRADATA_INPUT_CROP: - if (rem_bytes < sizeof(struct hfi_extradata_input_crop)) - goto error; - + data_ptr += sizeof(u32); crop = (struct hfi_extradata_input_crop *)data_ptr; event.input_crop.left = crop->left; event.input_crop.top = crop->top; event.input_crop.width = crop->width; event.input_crop.height = crop->height; - size_read = sizeof(struct hfi_extradata_input_crop); - break; - case HFI_PROPERTY_PARAM_VDEC_DPB_COUNTS: - if (rem_bytes < sizeof(struct hfi_dpb_counts)) - goto error; - - dpb_count = (struct hfi_dpb_counts *)data_ptr; - event.buf_count = dpb_count->fw_min_cnt; - size_read = sizeof(struct hfi_dpb_counts); + data_ptr += sizeof(*crop); break; default: - size_read = 0; break; } - data_ptr += size_read; - rem_bytes -= size_read; num_properties_changed--; } while (num_properties_changed > 0); - inst->ops->event_notify(inst, EVT_SYS_EVENT_CHANGE, &event); - return; - -error: - inst->error = HFI_ERR_SESSION_INSUFFICIENT_RESOURCES; +done: inst->ops->event_notify(inst, EVT_SYS_EVENT_CHANGE, &event); } diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c index 23c47d92c071..1f42130cc865 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c @@ -14,7 +14,8 @@ #include "s5p_mfc_opr.h" #include "s5p_mfc_cmd_v6.h" -static int s5p_mfc_cmd_host2risc_v6(struct s5p_mfc_dev *dev, int cmd) +static int s5p_mfc_cmd_host2risc_v6(struct s5p_mfc_dev *dev, int cmd, + struct s5p_mfc_cmd_args *args) { mfc_debug(2, "Issue the command: %d\n", cmd); @@ -30,6 +31,7 @@ static int s5p_mfc_cmd_host2risc_v6(struct s5p_mfc_dev *dev, int cmd) static int s5p_mfc_sys_init_cmd_v6(struct s5p_mfc_dev *dev) { + struct s5p_mfc_cmd_args h2r_args; struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv; int ret; @@ -39,23 +41,33 @@ static int s5p_mfc_sys_init_cmd_v6(struct s5p_mfc_dev *dev) mfc_write(dev, dev->ctx_buf.dma, S5P_FIMV_CONTEXT_MEM_ADDR_V6); mfc_write(dev, buf_size->dev_ctx, S5P_FIMV_CONTEXT_MEM_SIZE_V6); - return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_SYS_INIT_V6); + return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_SYS_INIT_V6, + &h2r_args); } static int s5p_mfc_sleep_cmd_v6(struct s5p_mfc_dev *dev) { - return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_SLEEP_V6); + struct s5p_mfc_cmd_args h2r_args; + + memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args)); + return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_SLEEP_V6, + &h2r_args); } static int s5p_mfc_wakeup_cmd_v6(struct s5p_mfc_dev *dev) { - return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_WAKEUP_V6); + struct s5p_mfc_cmd_args h2r_args; + + memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args)); + return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_WAKEUP_V6, + &h2r_args); } /* Open a new instance and get its number */ static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx) { struct s5p_mfc_dev *dev = ctx->dev; + struct s5p_mfc_cmd_args h2r_args; int codec_type; mfc_debug(2, "Requested codec mode: %d\n", ctx->codec_mode); @@ -117,20 +129,23 @@ static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx) mfc_write(dev, ctx->ctx.size, S5P_FIMV_CONTEXT_MEM_SIZE_V6); mfc_write(dev, 0, S5P_FIMV_D_CRC_CTRL_V6); /* no crc */ - return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_OPEN_INSTANCE_V6); + return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_OPEN_INSTANCE_V6, + &h2r_args); } /* Close instance */ static int s5p_mfc_close_inst_cmd_v6(struct s5p_mfc_ctx *ctx) { struct s5p_mfc_dev *dev = ctx->dev; + struct s5p_mfc_cmd_args h2r_args; int ret = 0; dev->curr_ctx = ctx->num; if (ctx->state != MFCINST_FREE) { mfc_write(dev, ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6); ret = s5p_mfc_cmd_host2risc_v6(dev, - S5P_FIMV_H2R_CMD_CLOSE_INSTANCE_V6); + S5P_FIMV_H2R_CMD_CLOSE_INSTANCE_V6, + &h2r_args); } else { ret = -EINVAL; } @@ -138,15 +153,9 @@ static int s5p_mfc_close_inst_cmd_v6(struct s5p_mfc_ctx *ctx) return ret; } -static int s5p_mfc_cmd_host2risc_v6_args(struct s5p_mfc_dev *dev, int cmd, - struct s5p_mfc_cmd_args *ignored) -{ - return s5p_mfc_cmd_host2risc_v6(dev, cmd); -} - /* Initialize cmd function pointers for MFC v6 */ static struct s5p_mfc_hw_cmds s5p_mfc_cmds_v6 = { - .cmd_host2risc = s5p_mfc_cmd_host2risc_v6_args, + .cmd_host2risc = s5p_mfc_cmd_host2risc_v6, .sys_init_cmd = s5p_mfc_sys_init_cmd_v6, .sleep_cmd = s5p_mfc_sleep_cmd_v6, .wakeup_cmd = s5p_mfc_wakeup_cmd_v6, diff --git a/drivers/media/rc/bpf-lirc.c b/drivers/media/rc/bpf-lirc.c index 48a5b49cc4f7..e90971a277bf 100644 --- a/drivers/media/rc/bpf-lirc.c +++ b/drivers/media/rc/bpf-lirc.c @@ -115,7 +115,7 @@ lirc_mode2_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) case BPF_FUNC_get_prandom_u32: return &bpf_get_prandom_u32_proto; case BPF_FUNC_trace_printk: - if (perfmon_capable()) + if (capable(CAP_SYS_ADMIN)) return bpf_get_trace_printk_proto(); /* fall through */ default: diff --git a/drivers/media/rc/imon.c b/drivers/media/rc/imon.c index 6e73304a1e7c..38f6dd12d870 100644 --- a/drivers/media/rc/imon.c +++ b/drivers/media/rc/imon.c @@ -83,7 +83,6 @@ struct imon_usb_dev_descr { __u16 flags; #define IMON_NO_FLAGS 0 #define IMON_NEED_20MS_PKT_DELAY 1 -#define IMON_SUPPRESS_REPEATED_KEYS 2 struct imon_panel_key_table key_table[]; }; @@ -150,27 +149,8 @@ struct imon_context { struct timer_list ttimer; /* touch screen timer */ int touch_x; /* x coordinate on touchscreen */ int touch_y; /* y coordinate on touchscreen */ - const struct imon_usb_dev_descr *dev_descr; - /* device description with key */ - /* table for front panels */ - /* - * Fields for deferring free_imon_context(). - * - * Since reference to "struct imon_context" is stored into - * "struct file"->private_data, we need to remember - * how many file descriptors might access this "struct imon_context". - */ - refcount_t users; - /* - * Use a flag for telling display_open()/vfd_write()/lcd_write() that - * imon_disconnect() was already called. - */ - bool disconnected; - /* - * We need to wait for RCU grace period in order to allow - * display_open() to safely check ->disconnected and increment ->users. - */ - struct rcu_head rcu; + struct imon_usb_dev_descr *dev_descr; /* device description with key + table for front panels */ }; #define TOUCH_TIMEOUT (HZ/30) @@ -178,18 +158,18 @@ struct imon_context { /* vfd character device file operations */ static const struct file_operations vfd_fops = { .owner = THIS_MODULE, - .open = display_open, - .write = vfd_write, - .release = display_close, + .open = &display_open, + .write = &vfd_write, + .release = &display_close, .llseek = noop_llseek, }; /* lcd character device file operations */ static const struct file_operations lcd_fops = { .owner = THIS_MODULE, - .open = display_open, - .write = lcd_write, - .release = display_close, + .open = &display_open, + .write = &lcd_write, + .release = &display_close, .llseek = noop_llseek, }; @@ -335,32 +315,6 @@ static const struct imon_usb_dev_descr imon_DH102 = { } }; -/* imon ultrabay front panel key table */ -static const struct imon_usb_dev_descr ultrabay_table = { - .flags = IMON_SUPPRESS_REPEATED_KEYS, - .key_table = { - { 0x0000000f0000ffeell, KEY_MEDIA }, /* Go */ - { 0x000000000100ffeell, KEY_UP }, - { 0x000000000001ffeell, KEY_DOWN }, - { 0x000000160000ffeell, KEY_ENTER }, - { 0x0000001f0000ffeell, KEY_AUDIO }, /* Music */ - { 0x000000200000ffeell, KEY_VIDEO }, /* Movie */ - { 0x000000210000ffeell, KEY_CAMERA }, /* Photo */ - { 0x000000270000ffeell, KEY_DVD }, /* DVD */ - { 0x000000230000ffeell, KEY_TV }, /* TV */ - { 0x000000050000ffeell, KEY_PREVIOUS }, /* Previous */ - { 0x000000070000ffeell, KEY_REWIND }, - { 0x000000040000ffeell, KEY_STOP }, - { 0x000000020000ffeell, KEY_PLAYPAUSE }, - { 0x000000080000ffeell, KEY_FASTFORWARD }, - { 0x000000060000ffeell, KEY_NEXT }, /* Next */ - { 0x000100000000ffeell, KEY_VOLUMEUP }, - { 0x010000000000ffeell, KEY_VOLUMEDOWN }, - { 0x000000010000ffeell, KEY_MUTE }, - { 0, KEY_RESERVED }, - } -}; - /* * USB Device ID for iMON USB Control Boards * @@ -457,6 +411,9 @@ static struct usb_driver imon_driver = { .id_table = imon_usb_id_table, }; +/* to prevent races between open() and disconnect(), probing, etc */ +static DEFINE_MUTEX(driver_lock); + /* Module bookkeeping bits */ MODULE_AUTHOR(MOD_AUTHOR); MODULE_DESCRIPTION(MOD_DESC); @@ -496,11 +453,9 @@ static void free_imon_context(struct imon_context *ictx) struct device *dev = ictx->dev; usb_free_urb(ictx->tx_urb); - WARN_ON(ictx->dev_present_intf0); usb_free_urb(ictx->rx_urb_intf0); - WARN_ON(ictx->dev_present_intf1); usb_free_urb(ictx->rx_urb_intf1); - kfree_rcu(ictx, rcu); + kfree(ictx); dev_dbg(dev, "%s: iMON context freed\n", __func__); } @@ -516,6 +471,9 @@ static int display_open(struct inode *inode, struct file *file) int subminor; int retval = 0; + /* prevent races with disconnect */ + mutex_lock(&driver_lock); + subminor = iminor(inode); interface = usb_find_interface(&imon_driver, subminor); if (!interface) { @@ -523,22 +481,17 @@ static int display_open(struct inode *inode, struct file *file) retval = -ENODEV; goto exit; } - - rcu_read_lock(); ictx = usb_get_intfdata(interface); - if (!ictx || ictx->disconnected || !refcount_inc_not_zero(&ictx->users)) { - rcu_read_unlock(); + + if (!ictx) { pr_err("no context found for minor %d\n", subminor); retval = -ENODEV; goto exit; } - rcu_read_unlock(); mutex_lock(&ictx->lock); - if (ictx->disconnected) { - retval = -ENODEV; - } else if (!ictx->display_supported) { + if (!ictx->display_supported) { pr_err("display not supported by device\n"); retval = -ENODEV; } else if (ictx->display_isopen) { @@ -552,10 +505,8 @@ static int display_open(struct inode *inode, struct file *file) mutex_unlock(&ictx->lock); - if (retval && refcount_dec_and_test(&ictx->users)) - free_imon_context(ictx); - exit: + mutex_unlock(&driver_lock); return retval; } @@ -565,9 +516,16 @@ exit: */ static int display_close(struct inode *inode, struct file *file) { - struct imon_context *ictx = file->private_data; + struct imon_context *ictx = NULL; int retval = 0; + ictx = file->private_data; + + if (!ictx) { + pr_err("no context for device\n"); + return -ENODEV; + } + mutex_lock(&ictx->lock); if (!ictx->display_supported) { @@ -582,8 +540,6 @@ static int display_close(struct inode *inode, struct file *file) } mutex_unlock(&ictx->lock); - if (refcount_dec_and_test(&ictx->users)) - free_imon_context(ictx); return retval; } @@ -600,11 +556,6 @@ static int send_packet(struct imon_context *ictx) int retval = 0; struct usb_ctrlrequest *control_req = NULL; - lockdep_assert_held(&ictx->lock); - - if (ictx->disconnected) - return -ENODEV; - /* Check if we need to use control or interrupt urb */ if (!ictx->tx_control) { pipe = usb_sndintpipe(ictx->usbdev_intf0, @@ -652,15 +603,12 @@ static int send_packet(struct imon_context *ictx) smp_rmb(); /* ensure later readers know we're not busy */ pr_err_ratelimited("error submitting urb(%d)\n", retval); } else { - /* Wait for transmission to complete (or abort or timeout) */ - retval = wait_for_completion_interruptible_timeout(&ictx->tx.finished, 10 * HZ); - if (retval <= 0) { + /* Wait for transmission to complete (or abort) */ + retval = wait_for_completion_interruptible( + &ictx->tx.finished); + if (retval) { usb_kill_urb(ictx->tx_urb); pr_err_ratelimited("task interrupted\n"); - if (retval < 0) - ictx->tx.status = retval; - else - ictx->tx.status = -ETIMEDOUT; } ictx->tx.busy = false; @@ -960,18 +908,19 @@ static ssize_t vfd_write(struct file *file, const char __user *buf, int offset; int seq; int retval = 0; - struct imon_context *ictx = file->private_data; + struct imon_context *ictx; static const unsigned char vfd_packet6[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF }; + ictx = file->private_data; + if (!ictx) { + pr_err_ratelimited("no context for device\n"); + return -ENODEV; + } + if (mutex_lock_interruptible(&ictx->lock)) return -ERESTARTSYS; - if (ictx->disconnected) { - retval = -ENODEV; - goto exit; - } - if (!ictx->dev_present_intf0) { pr_err_ratelimited("no iMON device present\n"); retval = -ENODEV; @@ -1044,15 +993,16 @@ static ssize_t lcd_write(struct file *file, const char __user *buf, size_t n_bytes, loff_t *pos) { int retval = 0; - struct imon_context *ictx = file->private_data; + struct imon_context *ictx; + + ictx = file->private_data; + if (!ictx) { + pr_err_ratelimited("no context for device\n"); + return -ENODEV; + } mutex_lock(&ictx->lock); - if (ictx->disconnected) { - retval = -ENODEV; - goto exit; - } - if (!ictx->display_supported) { pr_err_ratelimited("no iMON display present\n"); retval = -ENODEV; @@ -1140,7 +1090,7 @@ static int imon_ir_change_protocol(struct rc_dev *rc, u64 *rc_proto) int retval; struct imon_context *ictx = rc->priv; struct device *dev = ictx->dev; - const bool unlock = mutex_trylock(&ictx->lock); + bool unlock = false; unsigned char ir_proto_packet[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86 }; @@ -1167,6 +1117,8 @@ static int imon_ir_change_protocol(struct rc_dev *rc, u64 *rc_proto) memcpy(ictx->usb_tx_buf, &ir_proto_packet, sizeof(ir_proto_packet)); + unlock = mutex_trylock(&ictx->lock); + retval = send_packet(ictx); if (retval) goto out; @@ -1309,11 +1261,9 @@ static u32 imon_mce_key_lookup(struct imon_context *ictx, u32 scancode) static u32 imon_panel_key_lookup(struct imon_context *ictx, u64 code) { - const struct imon_panel_key_table *key_table; - u32 keycode = KEY_RESERVED; int i; - - key_table = ictx->dev_descr->key_table; + u32 keycode = KEY_RESERVED; + struct imon_panel_key_table *key_table = ictx->dev_descr->key_table; for (i = 0; key_table[i].hw_code != 0; i++) { if (key_table[i].hw_code == (code | 0xffee)) { @@ -1597,6 +1547,7 @@ static void imon_incoming_packet(struct imon_context *ictx, u32 kc; u64 scancode; int press_type = 0; + long msec; ktime_t t; static ktime_t prev_time; u8 ktype; @@ -1698,16 +1649,14 @@ static void imon_incoming_packet(struct imon_context *ictx, spin_lock_irqsave(&ictx->kc_lock, flags); t = ktime_get(); - /* KEY repeats from knob and panel that need to be suppressed */ - if (ictx->kc == KEY_MUTE || - ictx->dev_descr->flags & IMON_SUPPRESS_REPEATED_KEYS) { - if (ictx->kc == ictx->last_keycode && - ktime_ms_delta(t, prev_time) < ictx->idev->rep[REP_DELAY]) { + /* KEY_MUTE repeats from knob need to be suppressed */ + if (ictx->kc == KEY_MUTE && ictx->kc == ictx->last_keycode) { + msec = ktime_ms_delta(t, prev_time); + if (msec < ictx->idev->rep[REP_DELAY]) { spin_unlock_irqrestore(&ictx->kc_lock, flags); return; } } - prev_time = t; kc = ictx->kc; @@ -1762,6 +1711,14 @@ static void usb_rx_callback_intf0(struct urb *urb) if (!ictx) return; + /* + * if we get a callback before we're done configuring the hardware, we + * can't yet process the data, as there's nowhere to send it, but we + * still need to submit a new rx URB to avoid wedging the hardware + */ + if (!ictx->dev_present_intf0) + goto out; + switch (urb->status) { case -ENOENT: /* usbcore unlink successful! */ return; @@ -1770,29 +1727,16 @@ static void usb_rx_callback_intf0(struct urb *urb) break; case 0: - /* - * if we get a callback before we're done configuring the hardware, we - * can't yet process the data, as there's nowhere to send it, but we - * still need to submit a new rx URB to avoid wedging the hardware - */ - if (ictx->dev_present_intf0) - imon_incoming_packet(ictx, urb, intfnum); + imon_incoming_packet(ictx, urb, intfnum); break; - case -ECONNRESET: - case -EILSEQ: - case -EPROTO: - case -EPIPE: - dev_warn(ictx->dev, "imon %s: status(%d)\n", - __func__, urb->status); - return; - default: dev_warn(ictx->dev, "imon %s: status(%d): ignored\n", __func__, urb->status); break; } +out: usb_submit_urb(ictx->rx_urb_intf0, GFP_ATOMIC); } @@ -1808,6 +1752,14 @@ static void usb_rx_callback_intf1(struct urb *urb) if (!ictx) return; + /* + * if we get a callback before we're done configuring the hardware, we + * can't yet process the data, as there's nowhere to send it, but we + * still need to submit a new rx URB to avoid wedging the hardware + */ + if (!ictx->dev_present_intf1) + goto out; + switch (urb->status) { case -ENOENT: /* usbcore unlink successful! */ return; @@ -1816,29 +1768,16 @@ static void usb_rx_callback_intf1(struct urb *urb) break; case 0: - /* - * if we get a callback before we're done configuring the hardware, we - * can't yet process the data, as there's nowhere to send it, but we - * still need to submit a new rx URB to avoid wedging the hardware - */ - if (ictx->dev_present_intf1) - imon_incoming_packet(ictx, urb, intfnum); + imon_incoming_packet(ictx, urb, intfnum); break; - case -ECONNRESET: - case -EILSEQ: - case -EPROTO: - case -EPIPE: - dev_warn(ictx->dev, "imon %s: status(%d)\n", - __func__, urb->status); - return; - default: dev_warn(ictx->dev, "imon %s: status(%d): ignored\n", __func__, urb->status); break; } +out: usb_submit_urb(ictx->rx_urb_intf1, GFP_ATOMIC); } @@ -1905,14 +1844,6 @@ static void imon_get_ffdc_type(struct imon_context *ictx) dev_info(ictx->dev, "0xffdc iMON Inside, iMON IR"); ictx->display_supported = false; break; - /* Soundgraph iMON UltraBay */ - case 0x98: - dev_info(ictx->dev, "0xffdc iMON UltraBay, LCD + IR"); - detected_display_type = IMON_DISPLAY_TYPE_LCD; - allowed_protos = RC_PROTO_BIT_IMON | RC_PROTO_BIT_RC6_MCE; - ictx->dev_descr = &ultrabay_table; - break; - default: dev_info(ictx->dev, "Unknown 0xffdc device, defaulting to VFD and iMON IR"); detected_display_type = IMON_DISPLAY_TYPE_VFD; @@ -2044,12 +1975,10 @@ out: static struct input_dev *imon_init_idev(struct imon_context *ictx) { - const struct imon_panel_key_table *key_table; + struct imon_panel_key_table *key_table = ictx->dev_descr->key_table; struct input_dev *idev; int ret, i; - key_table = ictx->dev_descr->key_table; - idev = input_allocate_device(); if (!idev) goto out; @@ -2432,6 +2361,7 @@ static int imon_probe(struct usb_interface *interface, int ifnum, sysfs_err; int ret = 0; struct imon_context *ictx = NULL; + struct imon_context *first_if_ctx = NULL; u16 vendor, product; usbdev = usb_get_dev(interface_to_usbdev(interface)); @@ -2443,12 +2373,17 @@ static int imon_probe(struct usb_interface *interface, dev_dbg(dev, "%s: found iMON device (%04x:%04x, intf%d)\n", __func__, vendor, product, ifnum); + /* prevent races probing devices w/multiple interfaces */ + mutex_lock(&driver_lock); + first_if = usb_ifnum_to_if(usbdev, 0); if (!first_if) { ret = -ENODEV; goto fail; } + first_if_ctx = usb_get_intfdata(first_if); + if (ifnum == 0) { ictx = imon_init_intf0(interface, id); if (!ictx) { @@ -2456,11 +2391,9 @@ static int imon_probe(struct usb_interface *interface, ret = -ENODEV; goto fail; } - refcount_set(&ictx->users, 1); } else { /* this is the secondary interface on the device */ - struct imon_context *first_if_ctx = usb_get_intfdata(first_if); /* fail early if first intf failed to register */ if (!first_if_ctx) { @@ -2474,13 +2407,14 @@ static int imon_probe(struct usb_interface *interface, ret = -ENODEV; goto fail; } - refcount_inc(&ictx->users); } usb_set_intfdata(interface, ictx); if (ifnum == 0) { + mutex_lock(&ictx->lock); + if (product == 0xffdc && ictx->rf_device) { sysfs_err = sysfs_create_group(&interface->dev.kobj, &imon_rf_attr_group); @@ -2491,17 +2425,21 @@ static int imon_probe(struct usb_interface *interface, if (ictx->display_supported) imon_init_display(ictx, interface); + + mutex_unlock(&ictx->lock); } dev_info(dev, "iMON device (%04x:%04x, intf%d) on usb<%d:%d> initialized\n", vendor, product, ifnum, usbdev->bus->busnum, usbdev->devnum); + mutex_unlock(&driver_lock); usb_put_dev(usbdev); return 0; fail: + mutex_unlock(&driver_lock); usb_put_dev(usbdev); dev_err(dev, "unable to register, err %d\n", ret); @@ -2517,12 +2455,10 @@ static void imon_disconnect(struct usb_interface *interface) struct device *dev; int ifnum; + /* prevent races with multi-interface device probing and display_open */ + mutex_lock(&driver_lock); + ictx = usb_get_intfdata(interface); - - mutex_lock(&ictx->lock); - ictx->disconnected = true; - mutex_unlock(&ictx->lock); - dev = ictx->dev; ifnum = interface->cur_altsetting->desc.bInterfaceNumber; @@ -2563,9 +2499,11 @@ static void imon_disconnect(struct usb_interface *interface) } } - if (refcount_dec_and_test(&ictx->users)) + if (!ictx->dev_present_intf0 && !ictx->dev_present_intf1) free_imon_context(ictx); + mutex_unlock(&driver_lock); + dev_dbg(dev, "%s: iMON device (intf%d) disconnected\n", __func__, ifnum); } diff --git a/drivers/media/rc/lirc_dev.c b/drivers/media/rc/lirc_dev.c index 1d554bba567e..7de97c26b622 100644 --- a/drivers/media/rc/lirc_dev.c +++ b/drivers/media/rc/lirc_dev.c @@ -724,7 +724,9 @@ static const struct file_operations lirc_fops = { .owner = THIS_MODULE, .write = ir_lirc_transmit_ir, .unlocked_ioctl = ir_lirc_ioctl, - .compat_ioctl = compat_ptr_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = ir_lirc_ioctl, +#endif .read = ir_lirc_read, .poll = ir_lirc_poll, .open = ir_lirc_open, @@ -744,7 +746,7 @@ int ir_lirc_register(struct rc_dev *dev) const char *rx_type, *tx_type; int err, minor; - minor = ida_alloc_max(&lirc_ida, RC_DEV_MAX - 1, GFP_KERNEL); + minor = ida_simple_get(&lirc_ida, 0, RC_DEV_MAX, GFP_KERNEL); if (minor < 0) return minor; @@ -760,11 +762,11 @@ int ir_lirc_register(struct rc_dev *dev) cdev_init(&dev->lirc_cdev, &lirc_fops); - get_device(&dev->dev); - err = cdev_device_add(&dev->lirc_cdev, &dev->lirc_dev); if (err) - goto out_put_device; + goto out_ida; + + get_device(&dev->dev); switch (dev->driver_type) { case RC_DRIVER_SCANCODE: @@ -788,9 +790,8 @@ int ir_lirc_register(struct rc_dev *dev) return 0; -out_put_device: - put_device(&dev->lirc_dev); - ida_free(&lirc_ida, minor); +out_ida: + ida_simple_remove(&lirc_ida, minor); return err; } @@ -808,7 +809,7 @@ void ir_lirc_unregister(struct rc_dev *dev) spin_unlock_irqrestore(&dev->lirc_fh_lock, flags); cdev_device_del(&dev->lirc_cdev, &dev->lirc_dev); - ida_free(&lirc_ida, MINOR(dev->lirc_dev.devt)); + ida_simple_remove(&lirc_ida, MINOR(dev->lirc_dev.devt)); } int __init lirc_dev_init(void) diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c index e5cbe8c50ce1..ee80f38970bc 100644 --- a/drivers/media/rc/rc-main.c +++ b/drivers/media/rc/rc-main.c @@ -1861,7 +1861,7 @@ int rc_register_device(struct rc_dev *dev) if (!dev) return -EINVAL; - minor = ida_alloc_max(&rc_ida, RC_DEV_MAX - 1, GFP_KERNEL); + minor = ida_simple_get(&rc_ida, 0, RC_DEV_MAX, GFP_KERNEL); if (minor < 0) return minor; @@ -1944,7 +1944,7 @@ out_rx_free: out_raw: ir_raw_event_free(dev); out_minor: - ida_free(&rc_ida, minor); + ida_simple_remove(&rc_ida, minor); return rc; } EXPORT_SYMBOL_GPL(rc_register_device); @@ -2004,7 +2004,7 @@ void rc_unregister_device(struct rc_dev *dev) device_del(&dev->dev); - ida_free(&rc_ida, dev->minor); + ida_simple_remove(&rc_ida, dev->minor); if (!dev->managed_alloc) rc_free_device(dev); diff --git a/drivers/media/rc/redrat3.c b/drivers/media/rc/redrat3.c index 5a9702ccd54e..c39227661047 100644 --- a/drivers/media/rc/redrat3.c +++ b/drivers/media/rc/redrat3.c @@ -423,7 +423,7 @@ static int redrat3_send_cmd(int cmd, struct redrat3_dev *rr3) static int redrat3_enable_detector(struct redrat3_dev *rr3) { struct device *dev = rr3->dev; - int ret; + u8 ret; ret = redrat3_send_cmd(RR3_RC_DET_ENABLE, rr3); if (ret != 0) diff --git a/drivers/media/tuners/xc4000.c b/drivers/media/tuners/xc4000.c index c8aa193e04e7..849df4d1c573 100644 --- a/drivers/media/tuners/xc4000.c +++ b/drivers/media/tuners/xc4000.c @@ -1089,12 +1089,12 @@ fail: static void xc_debug_dump(struct xc4000_priv *priv) { - u16 adc_envelope = 0; + u16 adc_envelope; u32 freq_error_hz = 0; - u16 lock_status = 0; + u16 lock_status; u32 hsync_freq_hz = 0; - u16 frame_lines = 0; - u16 quality = 0; + u16 frame_lines; + u16 quality; u16 signal = 0; u16 noise = 0; u8 hw_majorversion = 0, hw_minorversion = 0; diff --git a/drivers/media/tuners/xc5000.c b/drivers/media/tuners/xc5000.c index b756b05835e0..65b886338557 100644 --- a/drivers/media/tuners/xc5000.c +++ b/drivers/media/tuners/xc5000.c @@ -58,7 +58,7 @@ struct xc5000_priv { struct dvb_frontend *fe; struct delayed_work timer_sleep; - bool inited; + const struct firmware *firmware; }; /* Misc Defines */ @@ -622,14 +622,14 @@ static int xc5000_fwupload(struct dvb_frontend *fe, static void xc_debug_dump(struct xc5000_priv *priv) { - u16 adc_envelope = 0; + u16 adc_envelope; u32 freq_error_hz = 0; - u16 lock_status = 0; + u16 lock_status; u32 hsync_freq_hz = 0; - u16 frame_lines = 0; - u16 quality = 0; - u16 snr = 0; - u16 totalgain = 0; + u16 frame_lines; + u16 quality; + u16 snr; + u16 totalgain; u8 hw_majorversion = 0, hw_minorversion = 0; u8 fw_majorversion = 0, fw_minorversion = 0; u16 fw_buildversion = 0; @@ -1110,19 +1110,23 @@ static int xc_load_fw_and_init_tuner(struct dvb_frontend *fe, int force) if (!force && xc5000_is_firmware_loaded(fe) == 0) return 0; - ret = request_firmware(&fw, desired_fw->name, - priv->i2c_props.adap->dev.parent); - if (ret) { - pr_err("xc5000: Upload failed. rc %d\n", ret); - return ret; - } - dprintk(1, "firmware read %zu bytes.\n", fw->size); + if (!priv->firmware) { + ret = request_firmware(&fw, desired_fw->name, + priv->i2c_props.adap->dev.parent); + if (ret) { + pr_err("xc5000: Upload failed. rc %d\n", ret); + return ret; + } + dprintk(1, "firmware read %zu bytes.\n", fw->size); - if (fw->size != desired_fw->size) { - pr_err("xc5000: Firmware file with incorrect size\n"); - release_firmware(fw); - return -EINVAL; - } + if (fw->size != desired_fw->size) { + pr_err("xc5000: Firmware file with incorrect size\n"); + release_firmware(fw); + return -EINVAL; + } + priv->firmware = fw; + } else + fw = priv->firmware; /* Try up to 5 times to load firmware */ for (i = 0; i < 5; i++) { @@ -1200,7 +1204,6 @@ static int xc_load_fw_and_init_tuner(struct dvb_frontend *fe, int force) } err: - release_firmware(fw); if (!ret) printk(KERN_INFO "xc5000: Firmware %s loaded and running.\n", desired_fw->name); @@ -1271,7 +1274,7 @@ static int xc5000_resume(struct dvb_frontend *fe) /* suspended before firmware is loaded. Avoid firmware load in resume path. */ - if (!priv->inited) + if (!priv->firmware) return 0; return xc5000_set_params(fe); @@ -1290,8 +1293,6 @@ static int xc5000_init(struct dvb_frontend *fe) if (debug) xc_debug_dump(priv); - priv->inited = true; - return 0; } @@ -1304,7 +1305,11 @@ static void xc5000_release(struct dvb_frontend *fe) mutex_lock(&xc5000_list_mutex); if (priv) { - cancel_delayed_work_sync(&priv->timer_sleep); + cancel_delayed_work(&priv->timer_sleep); + if (priv->firmware) { + release_firmware(priv->firmware); + priv->firmware = NULL; + } hybrid_tuner_release_state(priv); } diff --git a/drivers/memory/samsung/exynos-srom.c b/drivers/memory/samsung/exynos-srom.c index 0f182698ccc6..c27c6105c66d 100644 --- a/drivers/memory/samsung/exynos-srom.c +++ b/drivers/memory/samsung/exynos-srom.c @@ -47,9 +47,9 @@ struct exynos_srom { struct exynos_srom_reg_dump *reg_offset; }; -static struct exynos_srom_reg_dump * -exynos_srom_alloc_reg_dump(const unsigned long *rdump, - unsigned long nr_rdump) +static struct exynos_srom_reg_dump *exynos_srom_alloc_reg_dump( + const unsigned long *rdump, + unsigned long nr_rdump) { struct exynos_srom_reg_dump *rd; unsigned int i; @@ -116,23 +116,25 @@ static int exynos_srom_probe(struct platform_device *pdev) } srom = devm_kzalloc(&pdev->dev, - sizeof(struct exynos_srom), GFP_KERNEL); + sizeof(struct exynos_srom), GFP_KERNEL); if (!srom) return -ENOMEM; srom->dev = dev; - srom->reg_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(srom->reg_base)) { + srom->reg_base = of_iomap(np, 0); + if (!srom->reg_base) { dev_err(&pdev->dev, "iomap of exynos srom controller failed\n"); - return PTR_ERR(srom->reg_base); + return -ENOMEM; } platform_set_drvdata(pdev, srom); srom->reg_offset = exynos_srom_alloc_reg_dump(exynos_srom_offsets, - ARRAY_SIZE(exynos_srom_offsets)); - if (!srom->reg_offset) + ARRAY_SIZE(exynos_srom_offsets)); + if (!srom->reg_offset) { + iounmap(srom->reg_base); return -ENOMEM; + } for_each_child_of_node(np, child) { if (exynos_srom_configure_bank(srom, child)) { @@ -155,16 +157,16 @@ static int exynos_srom_probe(struct platform_device *pdev) #ifdef CONFIG_PM_SLEEP static void exynos_srom_save(void __iomem *base, - struct exynos_srom_reg_dump *rd, - unsigned int num_regs) + struct exynos_srom_reg_dump *rd, + unsigned int num_regs) { for (; num_regs > 0; --num_regs, ++rd) rd->value = readl(base + rd->offset); } static void exynos_srom_restore(void __iomem *base, - const struct exynos_srom_reg_dump *rd, - unsigned int num_regs) + const struct exynos_srom_reg_dump *rd, + unsigned int num_regs) { for (; num_regs > 0; --num_regs, ++rd) writel(rd->value, base + rd->offset); @@ -175,7 +177,7 @@ static int exynos_srom_suspend(struct device *dev) struct exynos_srom *srom = dev_get_drvdata(dev); exynos_srom_save(srom->reg_base, srom->reg_offset, - ARRAY_SIZE(exynos_srom_offsets)); + ARRAY_SIZE(exynos_srom_offsets)); return 0; } @@ -184,7 +186,7 @@ static int exynos_srom_resume(struct device *dev) struct exynos_srom *srom = dev_get_drvdata(dev); exynos_srom_restore(srom->reg_base, srom->reg_offset, - ARRAY_SIZE(exynos_srom_offsets)); + ARRAY_SIZE(exynos_srom_offsets)); return 0; } #endif diff --git a/drivers/memstick/core/memstick.c b/drivers/memstick/core/memstick.c index 7b8483f8d6f4..e24ab362e51a 100644 --- a/drivers/memstick/core/memstick.c +++ b/drivers/memstick/core/memstick.c @@ -369,9 +369,7 @@ int memstick_set_rw_addr(struct memstick_dev *card) { card->next_request = h_memstick_set_rw_addr; memstick_new_req(card->host); - if (!wait_for_completion_timeout(&card->mrq_complete, - msecs_to_jiffies(500))) - card->current_mrq.error = -ETIMEDOUT; + wait_for_completion(&card->mrq_complete); return card->current_mrq.error; } @@ -405,9 +403,7 @@ static struct memstick_dev *memstick_alloc_card(struct memstick_host *host) card->next_request = h_memstick_read_dev_id; memstick_new_req(host); - if (!wait_for_completion_timeout(&card->mrq_complete, - msecs_to_jiffies(500))) - card->current_mrq.error = -ETIMEDOUT; + wait_for_completion(&card->mrq_complete); if (card->current_mrq.error) goto err_out; diff --git a/drivers/mfd/intel_soc_pmic_chtdc_ti.c b/drivers/mfd/intel_soc_pmic_chtdc_ti.c index c629624fd4a5..64b5c3cc30e7 100644 --- a/drivers/mfd/intel_soc_pmic_chtdc_ti.c +++ b/drivers/mfd/intel_soc_pmic_chtdc_ti.c @@ -81,9 +81,8 @@ static struct mfd_cell chtdc_ti_dev[] = { static const struct regmap_config chtdc_ti_regmap_config = { .reg_bits = 8, .val_bits = 8, - .max_register = 0xff, - /* The hardware does not support reading multiple registers at once */ - .use_single_read = true, + .max_register = 128, + .cache_type = REGCACHE_NONE, }; static const struct regmap_irq chtdc_ti_irqs[] = { diff --git a/drivers/mfd/madera-core.c b/drivers/mfd/madera-core.c index bfd116f5a58d..29540cbf7593 100644 --- a/drivers/mfd/madera-core.c +++ b/drivers/mfd/madera-core.c @@ -431,7 +431,7 @@ int madera_dev_init(struct madera *madera) struct device *dev = madera->dev; unsigned int hwid; int (*patch_fn)(struct madera *) = NULL; - const struct mfd_cell *mfd_devs = NULL; + const struct mfd_cell *mfd_devs; int n_devs = 0; int i, ret; @@ -616,7 +616,7 @@ int madera_dev_init(struct madera *madera) goto err_reset; } - if (!n_devs || !mfd_devs) { + if (!n_devs) { dev_err(madera->dev, "Device ID 0x%x not a %s\n", hwid, madera->type_name); ret = -ENODEV; diff --git a/drivers/mfd/stmpe-i2c.c b/drivers/mfd/stmpe-i2c.c index d52bb3ea7fb6..cd2f45257dc1 100644 --- a/drivers/mfd/stmpe-i2c.c +++ b/drivers/mfd/stmpe-i2c.c @@ -139,4 +139,3 @@ module_exit(stmpe_exit); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("STMPE MFD I2C Interface Driver"); MODULE_AUTHOR("Rabin Vincent "); -MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/stmpe.c b/drivers/mfd/stmpe.c index 70ca3fe4e99e..7f758fb60c1f 100644 --- a/drivers/mfd/stmpe.c +++ b/drivers/mfd/stmpe.c @@ -1494,9 +1494,6 @@ int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum) int stmpe_remove(struct stmpe *stmpe) { - if (stmpe->domain) - irq_domain_remove(stmpe->domain); - if (!IS_ERR(stmpe->vio) && regulator_is_enabled(stmpe->vio)) regulator_disable(stmpe->vio); if (!IS_ERR(stmpe->vcc) && regulator_is_enabled(stmpe->vcc)) diff --git a/drivers/mfd/vexpress-sysreg.c b/drivers/mfd/vexpress-sysreg.c index 1463cf43687d..c68ff56dbdb1 100644 --- a/drivers/mfd/vexpress-sysreg.c +++ b/drivers/mfd/vexpress-sysreg.c @@ -160,7 +160,6 @@ static int vexpress_sysreg_probe(struct platform_device *pdev) struct gpio_chip *mmc_gpio_chip; int master; u32 dt_hbi; - int ret; mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!mem) @@ -196,10 +195,7 @@ static int vexpress_sysreg_probe(struct platform_device *pdev) bgpio_init(mmc_gpio_chip, &pdev->dev, 0x4, base + SYS_MCI, NULL, NULL, NULL, NULL, 0); mmc_gpio_chip->ngpio = 2; - - ret = gpiochip_add_data(mmc_gpio_chip, NULL); - if (ret) - return ret; + gpiochip_add_data(mmc_gpio_chip, NULL); return mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO, vexpress_sysreg_cells, diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index 198d22d73724..f1bfaad2ce27 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -379,21 +379,9 @@ static int olaps_cmp(const void *a, const void *b) return st == 0 ? ed : st; } -/** - * fastrpc_get_buff_overlaps - Detect and handle buffer overlaps in RPC args - * @ctx: The invoke context containing buffer information - * - * This function detects overlapping memory regions in the RPC arguments and - * adjusts the memory mapping accordingly. It handles ION and non-ION buffers - * separately to prevent incorrect overlap detection between different buf types. - * For each buffer type: - * - If a buffer overlaps with a previous buffer of the same type, it adjusts - * the mapping to avoid the overlap - * - If no overlap is detected, it uses the full buffer range - */ static void fastrpc_get_buff_overlaps(struct fastrpc_invoke_ctx *ctx) { - u64 ion_buf_end_pos = 0, non_ion_buf_end_pos = 0; + u64 max_end = 0; int i; for (i = 0; i < ctx->nbufs; ++i) { @@ -405,29 +393,24 @@ static void fastrpc_get_buff_overlaps(struct fastrpc_invoke_ctx *ctx) sort(ctx->olaps, ctx->nbufs, sizeof(*ctx->olaps), olaps_cmp, NULL); for (i = 0; i < ctx->nbufs; ++i) { - /* Separate ION and non-ION buffers; fd <= 0 indicates non-ION */ - u64 *last_buf_end = (ctx->args[ctx->olaps[i].raix].fd <= 0) ? - &non_ion_buf_end_pos : &ion_buf_end_pos; - - if (ctx->olaps[i].start < *last_buf_end) { - /* Overlap detected within same buffer type */ - ctx->olaps[i].mstart = *last_buf_end; + /* Falling inside previous range */ + if (ctx->olaps[i].start < max_end) { + ctx->olaps[i].mstart = max_end; ctx->olaps[i].mend = ctx->olaps[i].end; - ctx->olaps[i].offset = *last_buf_end - ctx->olaps[i].start; + ctx->olaps[i].offset = max_end - ctx->olaps[i].start; - if (ctx->olaps[i].end > *last_buf_end) { - *last_buf_end = ctx->olaps[i].end; + if (ctx->olaps[i].end > max_end) { + max_end = ctx->olaps[i].end; } else { ctx->olaps[i].mend = 0; ctx->olaps[i].mstart = 0; } } else { - /* No overlap, assign full range */ ctx->olaps[i].mend = ctx->olaps[i].end; ctx->olaps[i].mstart = ctx->olaps[i].start; ctx->olaps[i].offset = 0; - *last_buf_end = ctx->olaps[i].end; + max_end = ctx->olaps[i].end; } } } @@ -727,12 +710,8 @@ static u64 fastrpc_get_payload_size(struct fastrpc_invoke_ctx *ctx, int metalen) if (ctx->args[i].fd == 0 || ctx->args[i].fd == -1) { - if (ctx->olaps[oix].offset == 0) { - /* Check for overflow before align. */ - if (size > (ULLONG_MAX - (FASTRPC_ALIGN - 1))) - return 0; + if (ctx->olaps[oix].offset == 0) size = ALIGN(size, FASTRPC_ALIGN); - } size += (ctx->olaps[oix].mend - ctx->olaps[oix].mstart); } @@ -830,22 +809,6 @@ static int fastrpc_get_args(u32 kernel, struct fastrpc_invoke_ctx *ctx) PAGE_SHIFT; pages[i].size = (pg_end - pg_start + 1) * PAGE_SIZE; - /* - * Check for page range overflow and validate page - * range is not greater than map buffer range. - * This prevents potential buffer overflow - * and memory corruption that could be exploited. - */ - if (pages[i].addr > (ULLONG_MAX - pages[i].size) || - (pages[i].addr + pages[i].size) > - (ctx->maps[i]->phys + ctx->maps[i]->size)) { - err = -EFAULT; - dev_err(dev, - "Invalid buffer addr 0x%llx len 0x%llx IPA 0x%llx size 0x%llx fd %d\n", - ctx->args[i].ptr, len, ctx->maps[i]->phys, - ctx->maps[i]->size, ctx->maps[i]->fd); - goto bail; - } } else { if (ctx->olaps[oix].offset == 0) { diff --git a/drivers/misc/genwqe/card_ddcb.c b/drivers/misc/genwqe/card_ddcb.c index e53bdd5f04ea..026c6ca24540 100644 --- a/drivers/misc/genwqe/card_ddcb.c +++ b/drivers/misc/genwqe/card_ddcb.c @@ -918,7 +918,7 @@ int __genwqe_execute_raw_ddcb(struct genwqe_dev *cd, } if (cmd->asv_length > DDCB_ASV_LENGTH) { dev_err(&pci_dev->dev, "[%s] err: wrong asv_length of %d\n", - __func__, cmd->asv_length); + __func__, cmd->asiv_length); return -EINVAL; } rc = __genwqe_enqueue_ddcb(cd, req, f_flags); diff --git a/drivers/misc/kgdbts.c b/drivers/misc/kgdbts.c index 59e235731d5d..2f8858105733 100644 --- a/drivers/misc/kgdbts.c +++ b/drivers/misc/kgdbts.c @@ -829,7 +829,7 @@ static void run_plant_and_detach_test(int is_early) char before[BREAK_INSTR_SIZE]; char after[BREAK_INSTR_SIZE]; - copy_from_kernel_nofault(before, (char *)kgdbts_break_test, + probe_kernel_read(before, (char *)kgdbts_break_test, BREAK_INSTR_SIZE); init_simple_test(); ts.tst = plant_and_detach_test; @@ -837,8 +837,8 @@ static void run_plant_and_detach_test(int is_early) /* Activate test with initial breakpoint */ if (!is_early) kgdb_breakpoint(); - copy_from_kernel_nofault(after, (char *)kgdbts_break_test, - BREAK_INSTR_SIZE); + probe_kernel_read(after, (char *)kgdbts_break_test, + BREAK_INSTR_SIZE); if (memcmp(before, after, BREAK_INSTR_SIZE)) { printk(KERN_CRIT "kgdbts: ERROR kgdb corrupted memory\n"); panic("kgdb memory corruption"); diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c index ee37da507d78..943037fe50be 100644 --- a/drivers/misc/qseecom.c +++ b/drivers/misc/qseecom.c @@ -3,7 +3,7 @@ * QTI Secure Execution Environment Communicator (QSEECOM) driver * * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #define pr_fmt(fmt) "QSEECOM: %s: " fmt, __func__ @@ -2066,8 +2066,8 @@ static int qseecom_set_client_mem_param(struct qseecom_dev_handle *data, if ((req.ifd_data_fd <= 0) || (req.virt_sb_base == NULL) || (req.sb_len == 0)) { - pr_err("Invalid input(s)ion_fd(%d), sb_len(%d), paddr: 0x%llx\n", - req.ifd_data_fd, req.sb_len, virt_to_phys(req.virt_sb_base)); + pr_err("Invalid input(s)ion_fd(%d), sb_len(%d), vaddr(0x%pK)\n", + req.ifd_data_fd, req.sb_len, req.virt_sb_base); return -EFAULT; } if (!access_ok((void __user *)req.virt_sb_base, diff --git a/drivers/misc/vmw_vmci/vmci_host.c b/drivers/misc/vmw_vmci/vmci_host.c index c7c98d50d9fe..6eddb805642e 100644 --- a/drivers/misc/vmw_vmci/vmci_host.c +++ b/drivers/misc/vmw_vmci/vmci_host.c @@ -968,7 +968,7 @@ static const struct file_operations vmuser_fops = { .release = vmci_host_close, .poll = vmci_host_poll, .unlocked_ioctl = vmci_host_unlocked_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = vmci_host_unlocked_ioctl, }; static struct miscdevice vmci_host_miscdev = { diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c index 266c1a92a745..771f6dca4e32 100644 --- a/drivers/mmc/core/sdio.c +++ b/drivers/mmc/core/sdio.c @@ -868,11 +868,7 @@ static void mmc_sdio_remove(struct mmc_host *host) */ static int mmc_sdio_alive(struct mmc_host *host) { - if (!mmc_host_is_spi(host)) - return mmc_select_card(host->card); - else - return mmc_io_rw_direct(host->card, 0, 0, SDIO_CCCR_CCCR, 0, - NULL); + return mmc_select_card(host->card); } /* diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index 0a79b718cf17..23fd93407ece 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -185,11 +185,7 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, clk &= ~0xff; } - clock = clk & CLK_CTL_DIV_MASK; - if (clock != 0xff) - host->mmc->actual_clock /= (1 << (ffs(clock) + 1)); - - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clock); + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) usleep_range(10000, 11000); diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index f4153c400bf5..73f187f39735 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -84,7 +84,6 @@ #define CORE_IO_PAD_PWR_SWITCH_EN BIT(15) #define CORE_IO_PAD_PWR_SWITCH BIT(16) #define CORE_HC_SELECT_IN_EN BIT(18) -#define CORE_HC_SELECT_IN_SDR50 (4 << 19) #define CORE_HC_SELECT_IN_HS400 (6 << 19) #define CORE_HC_SELECT_IN_MASK (7 << 19) @@ -1432,10 +1431,6 @@ static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host) { struct mmc_ios *ios = &host->mmc->ios; - if (ios->timing == MMC_TIMING_UHS_SDR50 && - host->flags & SDHCI_SDR50_NEEDS_TUNING) - return true; - /* * Tuning is required for SDR104, HS200 and HS400 cards and * if clock frequency is greater than 100MHz in these modes. @@ -1505,8 +1500,8 @@ static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode) u32 core_vendor_spec; struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); - const struct sdhci_msm_offset *msm_offset = msm_host->offset; - u32 config; + const struct sdhci_msm_offset *msm_offset = + sdhci_priv_msm_offset(host); if (!sdhci_msm_is_tuning_needed(host)) { msm_host->use_cdr = false; @@ -1523,14 +1518,6 @@ static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode) */ msm_host->tuning_done = 0; - if (ios.timing == MMC_TIMING_UHS_SDR50 && - host->flags & SDHCI_SDR50_NEEDS_TUNING) { - config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); - config &= ~CORE_HC_SELECT_IN_MASK; - config |= CORE_HC_SELECT_IN_EN | CORE_HC_SELECT_IN_SDR50; - writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); - } - /* * For HS400 tuning in HS200 timing requires: * - select MCLK/2 in VENDOR_SPEC diff --git a/drivers/mtd/devices/msm_qpic_nand.c b/drivers/mtd/devices/msm_qpic_nand.c index eb45e4908968..329e7ebbd191 100644 --- a/drivers/mtd/devices/msm_qpic_nand.c +++ b/drivers/mtd/devices/msm_qpic_nand.c @@ -2,7 +2,7 @@ /* * Copyright (C) 2007 Google, Inc. * Copyright (c) 2012-2021 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "msm_qpic_nand.h" @@ -1944,7 +1944,7 @@ free_dma: if (last_pos < ecc_bytes_percw_in_bits) num_zero_bits++; - if (num_zero_bits > info->flash_dev.ecc_capability) { + if (num_zero_bits > 4) { *erased_page = false; goto free_mem; } @@ -1955,8 +1955,8 @@ free_dma: num_zero_bits = last_pos = next_pos = 0; ecc_temp += chip->ecc_parity_bytes; } - if ((n == cwperpage) && - (num_zero_bits <= info->flash_dev.ecc_capability)) + + if ((n == cwperpage) && (num_zero_bits <= 4)) *erased_page = true; free_mem: kfree(ecc); @@ -2163,33 +2163,6 @@ static int msm_nand_read_pagescope(struct mtd_info *mtd, loff_t from, goto free_dma; /* Check for flash status errors */ pageerr = rawerr = 0; - - /* - * PAGE_ERASED bit will set only if all - * CODEWORD_ERASED bit of all codewords - * of the page is set. - * - * PAGE_ERASED bit is a 'logical and' of all - * CODEWORD_ERASED bit of all codewords i.e. - * even if one codeword is detected as not - * an erased codeword, PAGE_ERASED bit will unset. - */ - for (n = rw_params.start_sector; n < cwperpage; n++) { - if ((dma_buffer->result[n].erased_cw_status & - (1 << PAGE_ERASED)) && - (dma_buffer->result[n].buffer_status & - NUM_ERRORS)) { - err = msm_nand_is_erased_page_ps(mtd, - from, ops, - &rw_params, - &erased_page); - if (err) - goto free_dma; - if (erased_page) - rawerr = -EIO; - break; - } - } for (n = rw_params.start_sector; n < cwperpage; n++) { if (dma_buffer->result[n].flash_status & (FS_OP_ERR | FS_MPU_ERR)) { @@ -2581,7 +2554,7 @@ free_dma: if (last_pos < ecc_bytes_percw_in_bits) num_zero_bits++; - if (num_zero_bits > info->flash_dev.ecc_capability) { + if (num_zero_bits > 4) { *erased_page = false; goto free_mem; } @@ -2593,8 +2566,7 @@ free_dma: ecc_temp += chip->ecc_parity_bytes; } - if ((n == cwperpage) && - (num_zero_bits <= info->flash_dev.ecc_capability)) + if ((n == cwperpage) && (num_zero_bits <= 4)) *erased_page = true; free_mem: kfree(ecc); @@ -2788,33 +2760,6 @@ static int msm_nand_read_oob(struct mtd_info *mtd, loff_t from, goto free_dma; /* Check for flash status errors */ pageerr = rawerr = 0; - - /* - * PAGE_ERASED bit will set only if all - * CODEWORD_ERASED bit of all codewords - * of the page is set. - * - * PAGE_ERASED bit is a 'logical and' of all - * CODEWORD_ERASED bit of all codewords i.e. - * even if one codeword is detected as not - * an erased codeword, PAGE_ERASED bit will unset. - */ - for (n = rw_params.start_sector; n < cwperpage; n++) { - if ((dma_buffer->result[n].erased_cw_status & - (1 << PAGE_ERASED)) && - (dma_buffer->result[n].buffer_status & - NUM_ERRORS)) { - err = msm_nand_is_erased_page(mtd, - from, ops, - &rw_params, - &erased_page); - if (err) - goto free_dma; - if (erased_page) - rawerr = -EIO; - break; - } - } for (n = rw_params.start_sector; n < cwperpage; n++) { if (dma_buffer->result[n].flash_status & (FS_OP_ERR | FS_MPU_ERR)) { diff --git a/drivers/mtd/devices/msm_qpic_nand.h b/drivers/mtd/devices/msm_qpic_nand.h index 0297ad9697c4..cc1df16f5b3d 100644 --- a/drivers/mtd/devices/msm_qpic_nand.h +++ b/drivers/mtd/devices/msm_qpic_nand.h @@ -154,10 +154,7 @@ #define RESET_ERASED_DET (1 << AUTO_DETECT_RES) #define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES) #define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC) -#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC | SET_N_MAX_ZEROS) -#define N_MAX_ZEROS 2 -#define MAX_ECC_BIT_FLIPS 4 -#define SET_N_MAX_ZEROS (MAX_ECC_BIT_FLIPS << N_MAX_ZEROS) +#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC) #define MSM_NAND_ERASED_CW_DETECT_STATUS(info) MSM_NAND_REG(info, 0x300EC) #define PAGE_ALL_ERASED 7 @@ -166,7 +163,6 @@ #define CODEWORD_ERASED 4 #define ERASED_PAGE ((1 << PAGE_ALL_ERASED) | (1 << PAGE_ERASED)) #define ERASED_CW ((1 << CODEWORD_ALL_ERASED) | (1 << CODEWORD_ERASED)) -#define NUM_ERRORS 0x1f #define MSM_NAND_CTRL(info) MSM_NAND_REG(info, 0x30F00) #define BAM_MODE_EN 0 diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index bccbde286233..83012d74dcd5 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -1948,8 +1948,6 @@ static struct backing_dev_info * __init mtd_bdi_init(char *name) bdi = bdi_alloc(GFP_KERNEL); if (!bdi) return ERR_PTR(-ENOMEM); - bdi->ra_pages = 0; - bdi->io_pages = 0; bdi->name = name; /* diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c index f093587e330d..c44b64542818 100644 --- a/drivers/mtd/nand/raw/fsmc_nand.c +++ b/drivers/mtd/nand/raw/fsmc_nand.c @@ -861,14 +861,10 @@ static int fsmc_nand_probe_config_dt(struct platform_device *pdev, if (!of_property_read_u32(np, "bank-width", &val)) { if (val == 2) { nand->options |= NAND_BUSWIDTH_16; - } else if (val == 1) { - nand->options |= NAND_BUSWIDTH_AUTO; - } else { + } else if (val != 1) { dev_err(&pdev->dev, "invalid bank-width %u\n", val); return -EINVAL; } - } else { - nand->options |= NAND_BUSWIDTH_AUTO; } if (of_get_property(np, "nand-skip-bbtscan", NULL)) diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index e10ff219aa5e..7bdc558d8560 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -496,7 +496,6 @@ static int cqspi_read_setup(struct spi_nor *nor) reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; reg |= (nor->addr_width - 1); writel(reg, reg_base + CQSPI_REG_SIZE); - readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */ return 0; } @@ -524,7 +523,6 @@ static int cqspi_indirect_read_execute(struct spi_nor *nor, u8 *rxbuf, reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTRD_START_MASK, reg_base + CQSPI_REG_INDIRECTRD); - readl(reg_base + CQSPI_REG_INDIRECTRD); /* Flush posted write. */ while (remaining > 0) { if (!wait_for_completion_timeout(&cqspi->transfer_complete, @@ -610,7 +608,6 @@ static int cqspi_write_setup(struct spi_nor *nor) reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; reg |= (nor->addr_width - 1); writel(reg, reg_base + CQSPI_REG_SIZE); - readl(reg_base + CQSPI_REG_SIZE); /* Flush posted write. */ return 0; } @@ -636,8 +633,6 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor, loff_t to_addr, reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTWR_START_MASK, reg_base + CQSPI_REG_INDIRECTWR); - readl(reg_base + CQSPI_REG_INDIRECTWR); /* Flush posted write. */ - /* * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access * Controller programming sequence, couple of cycles of diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c index ee7964bac8b8..851d26e6f0e1 100644 --- a/drivers/mtd/ubi/io.c +++ b/drivers/mtd/ubi/io.c @@ -1308,7 +1308,7 @@ static int self_check_write(struct ubi_device *ubi, const void *buf, int pnum, if (!ubi_dbg_chk_io(ubi)) return 0; - buf1 = __vmalloc(len, GFP_NOFS); + buf1 = __vmalloc(len, GFP_NOFS, PAGE_KERNEL); if (!buf1) { ubi_err(ubi, "cannot allocate memory to check writes"); return 0; @@ -1372,7 +1372,7 @@ int ubi_self_check_all_ff(struct ubi_device *ubi, int pnum, int offset, int len) if (!ubi_dbg_chk_io(ubi)) return 0; - buf = __vmalloc(len, GFP_NOFS); + buf = __vmalloc(len, GFP_NOFS, PAGE_KERNEL); if (!buf) { ubi_err(ubi, "cannot allocate memory to check for 0xFFs"); return 0; diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c index 99c7231bda73..3b235a269c1b 100644 --- a/drivers/net/bonding/bond_main.c +++ b/drivers/net/bonding/bond_main.c @@ -2331,7 +2331,7 @@ static void bond_mii_monitor(struct work_struct *work) { struct bonding *bond = container_of(work, struct bonding, mii_work.work); - bool should_notify_peers; + bool should_notify_peers = false; bool commit; unsigned long delay; struct slave *slave; @@ -2343,33 +2343,30 @@ static void bond_mii_monitor(struct work_struct *work) goto re_arm; rcu_read_lock(); - should_notify_peers = bond_should_notify_peers(bond); commit = !!bond_miimon_inspect(bond); + if (bond->send_peer_notif) { + rcu_read_unlock(); + if (rtnl_trylock()) { + bond->send_peer_notif--; + rtnl_unlock(); + } + } else { + rcu_read_unlock(); + } - rcu_read_unlock(); - - if (commit || bond->send_peer_notif) { + if (commit) { /* Race avoidance with bond_close cancel of workqueue */ if (!rtnl_trylock()) { delay = 1; + should_notify_peers = false; goto re_arm; } - if (commit) { - bond_for_each_slave(bond, slave, iter) { - bond_commit_link_state(slave, - BOND_SLAVE_NOTIFY_LATER); - } - bond_miimon_commit(bond); - } - - if (bond->send_peer_notif) { - bond->send_peer_notif--; - if (should_notify_peers) - call_netdevice_notifiers(NETDEV_NOTIFY_PEERS, - bond->dev); + bond_for_each_slave(bond, slave, iter) { + bond_commit_link_state(slave, BOND_SLAVE_NOTIFY_LATER); } + bond_miimon_commit(bond); rtnl_unlock(); /* might sleep, hold no other locks */ } @@ -2377,6 +2374,13 @@ static void bond_mii_monitor(struct work_struct *work) re_arm: if (bond->params.miimon) queue_delayed_work(bond->wq, &bond->mii_work, delay); + + if (should_notify_peers) { + if (!rtnl_trylock()) + return; + call_netdevice_notifiers(NETDEV_NOTIFY_PEERS, bond->dev); + rtnl_unlock(); + } } static int bond_upper_dev_walk(struct net_device *upper, void *data) diff --git a/drivers/net/can/usb/gs_usb.c b/drivers/net/can/usb/gs_usb.c index 17ea2be8abee..1a24c1d9dd8f 100644 --- a/drivers/net/can/usb/gs_usb.c +++ b/drivers/net/can/usb/gs_usb.c @@ -156,6 +156,10 @@ struct gs_host_frame { #define GS_MAX_TX_URBS 10 /* Only launch a max of GS_MAX_RX_URBS usb requests at a time. */ #define GS_MAX_RX_URBS 30 +/* Maximum number of interfaces the driver supports per device. + * Current hardware only supports 2 interfaces. The future may vary. + */ +#define GS_MAX_INTF 2 struct gs_tx_context { struct gs_can *dev; @@ -186,11 +190,10 @@ struct gs_can { /* usb interface struct */ struct gs_usb { + struct gs_can *canch[GS_MAX_INTF]; struct usb_anchor rx_submitted; struct usb_device *udev; u8 active_channels; - u8 channel_cnt; - struct gs_can *canch[]; }; /* 'allocate' a tx context. @@ -318,7 +321,7 @@ static void gs_usb_receive_bulk_callback(struct urb *urb) } /* device reports out of range channel id */ - if (hf->channel >= usbcan->channel_cnt) + if (hf->channel >= GS_MAX_INTF) goto device_detach; dev = usbcan->canch[hf->channel]; @@ -406,7 +409,7 @@ static void gs_usb_receive_bulk_callback(struct urb *urb) /* USB failure take down all interfaces */ if (rc == -ENODEV) { device_detach: - for (rc = 0; rc < usbcan->channel_cnt; rc++) { + for (rc = 0; rc < GS_MAX_INTF; rc++) { if (usbcan->canch[rc]) netif_device_detach(usbcan->canch[rc]->netdev); } @@ -988,22 +991,20 @@ static int gs_usb_probe(struct usb_interface *intf, icount = dconf->icount + 1; dev_info(&intf->dev, "Configuring for %d interfaces\n", icount); - if (icount > type_max(typeof(dev->channel_cnt))) { + if (icount > GS_MAX_INTF) { dev_err(&intf->dev, - "Driver cannot handle more that %u CAN interfaces\n", - type_max(typeof(dev->channel_cnt))); + "Driver cannot handle more that %d CAN interfaces\n", + GS_MAX_INTF); kfree(dconf); return -EINVAL; } - dev = kzalloc(struct_size(dev, canch, icount), GFP_KERNEL); + dev = kzalloc(sizeof(*dev), GFP_KERNEL); if (!dev) { kfree(dconf); return -ENOMEM; } - dev->channel_cnt = icount; - init_usb_anchor(&dev->rx_submitted); usb_set_intfdata(intf, dev); @@ -1044,7 +1045,7 @@ static void gs_usb_disconnect(struct usb_interface *intf) return; } - for (i = 0; i < dev->channel_cnt; i++) + for (i = 0; i < GS_MAX_INTF; i++) if (dev->canch[i]) gs_destroy_candev(dev->canch[i]); diff --git a/drivers/net/dsa/b53/b53_common.c b/drivers/net/dsa/b53/b53_common.c index 6a583e220bf8..fea28b24a1a0 100644 --- a/drivers/net/dsa/b53/b53_common.c +++ b/drivers/net/dsa/b53/b53_common.c @@ -347,11 +347,11 @@ static void b53_set_forwarding(struct b53_device *dev, int enable) * frames should be flooded or not. */ b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); - mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IP_MC; + mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN; b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); } else { b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt); - mgmt |= B53_IP_MC; + mgmt |= B53_IP_MCAST_25; b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); } } @@ -1026,8 +1026,6 @@ static void b53_force_link(struct b53_device *dev, int port, int link) if (port == dev->cpu_port) { off = B53_PORT_OVERRIDE_CTRL; val = PORT_OVERRIDE_EN; - } else if (is5325(dev)) { - return; } else { off = B53_GMII_PORT_OVERRIDE_CTRL(port); val = GMII_PO_EN; @@ -1043,8 +1041,7 @@ static void b53_force_link(struct b53_device *dev, int port, int link) } static void b53_force_port_config(struct b53_device *dev, int port, - int speed, int duplex, - bool tx_pause, bool rx_pause) + int speed, int duplex, int pause) { u8 reg, val, off; @@ -1052,8 +1049,6 @@ static void b53_force_port_config(struct b53_device *dev, int port, if (port == dev->cpu_port) { off = B53_PORT_OVERRIDE_CTRL; val = PORT_OVERRIDE_EN; - } else if (is5325(dev)) { - return; } else { off = B53_GMII_PORT_OVERRIDE_CTRL(port); val = GMII_PO_EN; @@ -1066,10 +1061,6 @@ static void b53_force_port_config(struct b53_device *dev, int port, else reg &= ~PORT_OVERRIDE_FULL_DUPLEX; - reg &= ~(0x3 << GMII_PO_SPEED_S); - if (is5301x(dev) || is58xx(dev)) - reg &= ~PORT_OVERRIDE_SPEED_2000M; - switch (speed) { case 2000: reg |= PORT_OVERRIDE_SPEED_2000M; @@ -1088,24 +1079,10 @@ static void b53_force_port_config(struct b53_device *dev, int port, return; } - if (is5325(dev)) - reg &= ~PORT_OVERRIDE_LP_FLOW_25; - else - reg &= ~(PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW); - - if (rx_pause) { - if (is5325(dev)) - reg |= PORT_OVERRIDE_LP_FLOW_25; - else - reg |= PORT_OVERRIDE_RX_FLOW; - } - - if (tx_pause) { - if (is5325(dev)) - reg |= PORT_OVERRIDE_LP_FLOW_25; - else - reg |= PORT_OVERRIDE_TX_FLOW; - } + if (pause & MLO_PAUSE_RX) + reg |= PORT_OVERRIDE_RX_FLOW; + if (pause & MLO_PAUSE_TX) + reg |= PORT_OVERRIDE_TX_FLOW; b53_write8(dev, B53_CTRL_PAGE, off, reg); } @@ -1116,24 +1093,22 @@ static void b53_adjust_link(struct dsa_switch *ds, int port, struct b53_device *dev = ds->priv; struct ethtool_eee *p = &dev->ports[port].eee; u8 rgmii_ctrl = 0, reg = 0, off; - bool tx_pause = false; - bool rx_pause = false; + int pause = 0; if (!phy_is_pseudo_fixed_link(phydev)) return; /* Enable flow control on BCM5301x's CPU port */ if (is5301x(dev) && port == dev->cpu_port) - tx_pause = rx_pause = true; + pause = MLO_PAUSE_TXRX_MASK; if (phydev->pause) { if (phydev->asym_pause) - tx_pause = true; - rx_pause = true; + pause |= MLO_PAUSE_TX; + pause |= MLO_PAUSE_RX; } - b53_force_port_config(dev, port, phydev->speed, phydev->duplex, - tx_pause, rx_pause); + b53_force_port_config(dev, port, phydev->speed, phydev->duplex, pause); b53_force_link(dev, port, phydev->link); if (is531x5(dev) && phy_interface_is_rgmii(phydev)) { @@ -1195,7 +1170,7 @@ static void b53_adjust_link(struct dsa_switch *ds, int port, } else if (is5301x(dev)) { if (port != dev->cpu_port) { b53_force_port_config(dev, dev->cpu_port, 2000, - DUPLEX_FULL, true, true); + DUPLEX_FULL, MLO_PAUSE_TXRX_MASK); b53_force_link(dev, dev->cpu_port, 1); } } @@ -1285,9 +1260,7 @@ void b53_phylink_mac_config(struct dsa_switch *ds, int port, if (mode == MLO_AN_FIXED) { b53_force_port_config(dev, port, state->speed, - state->duplex, - !!(state->pause & MLO_PAUSE_TX), - !!(state->pause & MLO_PAUSE_RX)); + state->duplex, state->pause); return; } @@ -1643,7 +1616,7 @@ static int b53_arl_search_wait(struct b53_device *dev) do { b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); if (!(reg & ARL_SRCH_STDN)) - return -ENOENT; + return 0; if (reg & ARL_SRCH_VLID) return 0; diff --git a/drivers/net/dsa/b53/b53_regs.h b/drivers/net/dsa/b53/b53_regs.h index 95f70248c194..ea6897c3f6f7 100644 --- a/drivers/net/dsa/b53/b53_regs.h +++ b/drivers/net/dsa/b53/b53_regs.h @@ -92,7 +92,6 @@ #define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S) #define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S) #define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S) -#define PORT_OVERRIDE_LP_FLOW_25 BIT(3) /* BCM5325 only */ #define PORT_OVERRIDE_RV_MII_25 BIT(4) /* BCM5325 only */ #define PORT_OVERRIDE_RX_FLOW BIT(4) #define PORT_OVERRIDE_TX_FLOW BIT(5) @@ -104,7 +103,8 @@ /* IP Multicast control (8 bit) */ #define B53_IP_MULTICAST_CTRL 0x21 -#define B53_IP_MC BIT(0) +#define B53_IP_MCAST_25 BIT(0) +#define B53_IPMC_FWD_EN BIT(1) #define B53_UC_FWD_EN BIT(6) #define B53_MC_FWD_EN BIT(7) diff --git a/drivers/net/ethernet/amazon/ena/ena_ethtool.c b/drivers/net/ethernet/amazon/ena/ena_ethtool.c index 5f037e9db023..ae631b8770fc 100644 --- a/drivers/net/ethernet/amazon/ena/ena_ethtool.c +++ b/drivers/net/ethernet/amazon/ena/ena_ethtool.c @@ -633,10 +633,7 @@ static u32 ena_get_rxfh_indir_size(struct net_device *netdev) static u32 ena_get_rxfh_key_size(struct net_device *netdev) { - struct ena_adapter *adapter = netdev_priv(netdev); - struct ena_rss *rss = &adapter->ena_dev->rss; - - return rss->hash_key ? ENA_HASH_KEY_SIZE : 0; + return ENA_HASH_KEY_SIZE; } static int ena_indirection_table_get(struct ena_adapter *adapter, u32 *indir) diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c index 1fa7eb75d1a3..de10e7e3a68d 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c @@ -1247,6 +1247,7 @@ static void xgbe_free_rx_data(struct xgbe_prv_data *pdata) static int xgbe_phy_reset(struct xgbe_prv_data *pdata) { + pdata->phy_link = -1; pdata->phy_speed = SPEED_UNKNOWN; return pdata->phy_if.phy_reset(pdata); diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c index 6dd95e7d81e4..3819b23c927d 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c @@ -1637,7 +1637,6 @@ static int xgbe_phy_init(struct xgbe_prv_data *pdata) pdata->phy.duplex = DUPLEX_FULL; } - pdata->phy_link = 0; pdata->phy.link = 0; pdata->phy.pause_autoneg = pdata->pause_autoneg; diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index 7e62b361a6c8..2a12a4144261 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -3213,8 +3213,13 @@ static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) bnxt_init_rxbd_pages(ring, type); if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) { - bpf_prog_add(bp->xdp_prog, 1); - rxr->xdp_prog = bp->xdp_prog; + rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1); + if (IS_ERR(rxr->xdp_prog)) { + int rc = PTR_ERR(rxr->xdp_prog); + + rxr->xdp_prog = NULL; + return rc; + } } prod = rxr->rx_prod; for (i = 0; i < bp->rx_ring_size; i++) { diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c index 3ea966d85ea3..55aa87771333 100644 --- a/drivers/net/ethernet/broadcom/tg3.c +++ b/drivers/net/ethernet/broadcom/tg3.c @@ -5827,7 +5827,7 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset) u32 current_speed = SPEED_UNKNOWN; u8 current_duplex = DUPLEX_UNKNOWN; bool current_link_up = false; - u32 local_adv = 0, remote_adv = 0, sgsr; + u32 local_adv, remote_adv, sgsr; if ((tg3_asic_rev(tp) == ASIC_REV_5719 || tg3_asic_rev(tp) == ASIC_REV_5720) && @@ -5968,6 +5968,9 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset) else current_duplex = DUPLEX_HALF; + local_adv = 0; + remote_adv = 0; + if (bmcr & BMCR_ANENABLE) { u32 common; diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 873b0acecd1b..a635c9af26c3 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -277,9 +277,9 @@ static void macb_set_hwaddr(struct macb *bp) u32 bottom; u16 top; - bottom = get_unaligned_le32(bp->dev->dev_addr); + bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr)); macb_or_gem_writel(bp, SA1B, bottom); - top = get_unaligned_le16(bp->dev->dev_addr + 4); + top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); macb_or_gem_writel(bp, SA1T, top); /* Clear unused address register sets */ diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_main.c b/drivers/net/ethernet/cavium/thunder/nicvf_main.c index 2b45d00f8040..e861567b2c49 100644 --- a/drivers/net/ethernet/cavium/thunder/nicvf_main.c +++ b/drivers/net/ethernet/cavium/thunder/nicvf_main.c @@ -1876,8 +1876,13 @@ static int nicvf_xdp_setup(struct nicvf *nic, struct bpf_prog *prog) if (nic->xdp_prog) { /* Attach BPF program */ - bpf_prog_add(nic->xdp_prog, nic->rx_queues - 1); - bpf_attached = true; + nic->xdp_prog = bpf_prog_add(nic->xdp_prog, nic->rx_queues - 1); + if (!IS_ERR(nic->xdp_prog)) { + bpf_attached = true; + } else { + ret = PTR_ERR(nic->xdp_prog); + nic->xdp_prog = NULL; + } } /* Calculate Tx queues needed for XDP and network stack */ diff --git a/drivers/net/ethernet/dlink/dl2k.c b/drivers/net/ethernet/dlink/dl2k.c index 855328ae6ea5..b4a8d4f12087 100644 --- a/drivers/net/ethernet/dlink/dl2k.c +++ b/drivers/net/ethernet/dlink/dl2k.c @@ -233,15 +233,13 @@ rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent) pci_set_drvdata (pdev, dev); - ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE, &ring_dma, - GFP_KERNEL); + ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma); if (!ring_space) goto err_out_iounmap; np->tx_ring = ring_space; np->tx_ring_dma = ring_dma; - ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE, &ring_dma, - GFP_KERNEL); + ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma); if (!ring_space) goto err_out_unmap_tx; np->rx_ring = ring_space; @@ -292,11 +290,9 @@ rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent) return 0; err_out_unmap_rx: - dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring, - np->rx_ring_dma); + pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma); err_out_unmap_tx: - dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring, - np->tx_ring_dma); + pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma); err_out_iounmap: #ifdef MEM_MAPPING pci_iounmap(pdev, np->ioaddr); @@ -450,9 +446,8 @@ static void free_list(struct net_device *dev) for (i = 0; i < RX_RING_SIZE; i++) { skb = np->rx_skbuff[i]; if (skb) { - dma_unmap_single(&np->pdev->dev, - desc_to_dma(&np->rx_ring[i]), - skb->len, DMA_FROM_DEVICE); + pci_unmap_single(np->pdev, desc_to_dma(&np->rx_ring[i]), + skb->len, PCI_DMA_FROMDEVICE); dev_kfree_skb(skb); np->rx_skbuff[i] = NULL; } @@ -462,9 +457,8 @@ static void free_list(struct net_device *dev) for (i = 0; i < TX_RING_SIZE; i++) { skb = np->tx_skbuff[i]; if (skb) { - dma_unmap_single(&np->pdev->dev, - desc_to_dma(&np->tx_ring[i]), - skb->len, DMA_TO_DEVICE); + pci_unmap_single(np->pdev, desc_to_dma(&np->tx_ring[i]), + skb->len, PCI_DMA_TODEVICE); dev_kfree_skb(skb); np->tx_skbuff[i] = NULL; } @@ -508,34 +502,26 @@ static int alloc_list(struct net_device *dev) for (i = 0; i < RX_RING_SIZE; i++) { /* Allocated fixed size of skbuff */ struct sk_buff *skb; - dma_addr_t addr; skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz); np->rx_skbuff[i] = skb; - if (!skb) - goto err_free_list; - - addr = dma_map_single(&np->pdev->dev, skb->data, - np->rx_buf_sz, DMA_FROM_DEVICE); - if (dma_mapping_error(&np->pdev->dev, addr)) - goto err_kfree_skb; + if (!skb) { + free_list(dev); + return -ENOMEM; + } np->rx_ring[i].next_desc = cpu_to_le64(np->rx_ring_dma + ((i + 1) % RX_RING_SIZE) * sizeof(struct netdev_desc)); /* Rubicon now supports 40 bits of addressing space. */ - np->rx_ring[i].fraginfo = cpu_to_le64(addr); + np->rx_ring[i].fraginfo = + cpu_to_le64(pci_map_single( + np->pdev, skb->data, np->rx_buf_sz, + PCI_DMA_FROMDEVICE)); np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48); } return 0; - -err_kfree_skb: - dev_kfree_skb(np->rx_skbuff[i]); - np->rx_skbuff[i] = NULL; -err_free_list: - free_list(dev); - return -ENOMEM; } static void rio_hw_init(struct net_device *dev) @@ -697,8 +683,9 @@ rio_timer (struct timer_list *t) } np->rx_skbuff[entry] = skb; np->rx_ring[entry].fraginfo = - cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data, - np->rx_buf_sz, DMA_FROM_DEVICE)); + cpu_to_le64 (pci_map_single + (np->pdev, skb->data, np->rx_buf_sz, + PCI_DMA_FROMDEVICE)); } np->rx_ring[entry].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48); @@ -752,8 +739,9 @@ start_xmit (struct sk_buff *skb, struct net_device *dev) ((u64)np->vlan << 32) | ((u64)skb->priority << 45); } - txdesc->fraginfo = cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data, - skb->len, DMA_TO_DEVICE)); + txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data, + skb->len, + PCI_DMA_TODEVICE)); txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48); /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode @@ -850,9 +838,9 @@ rio_free_tx (struct net_device *dev, int irq) if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone))) break; skb = np->tx_skbuff[entry]; - dma_unmap_single(&np->pdev->dev, - desc_to_dma(&np->tx_ring[entry]), skb->len, - DMA_TO_DEVICE); + pci_unmap_single (np->pdev, + desc_to_dma(&np->tx_ring[entry]), + skb->len, PCI_DMA_TODEVICE); if (irq) dev_consume_skb_irq(skb); else @@ -977,25 +965,25 @@ receive_packet (struct net_device *dev) /* Small skbuffs for short packets */ if (pkt_len > copy_thresh) { - dma_unmap_single(&np->pdev->dev, - desc_to_dma(desc), - np->rx_buf_sz, - DMA_FROM_DEVICE); + pci_unmap_single (np->pdev, + desc_to_dma(desc), + np->rx_buf_sz, + PCI_DMA_FROMDEVICE); skb_put (skb = np->rx_skbuff[entry], pkt_len); np->rx_skbuff[entry] = NULL; } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) { - dma_sync_single_for_cpu(&np->pdev->dev, - desc_to_dma(desc), - np->rx_buf_sz, - DMA_FROM_DEVICE); + pci_dma_sync_single_for_cpu(np->pdev, + desc_to_dma(desc), + np->rx_buf_sz, + PCI_DMA_FROMDEVICE); skb_copy_to_linear_data (skb, np->rx_skbuff[entry]->data, pkt_len); skb_put (skb, pkt_len); - dma_sync_single_for_device(&np->pdev->dev, - desc_to_dma(desc), - np->rx_buf_sz, - DMA_FROM_DEVICE); + pci_dma_sync_single_for_device(np->pdev, + desc_to_dma(desc), + np->rx_buf_sz, + PCI_DMA_FROMDEVICE); } skb->protocol = eth_type_trans (skb, dev); #if 0 @@ -1028,8 +1016,9 @@ receive_packet (struct net_device *dev) } np->rx_skbuff[entry] = skb; np->rx_ring[entry].fraginfo = - cpu_to_le64(dma_map_single(&np->pdev->dev, skb->data, - np->rx_buf_sz, DMA_FROM_DEVICE)); + cpu_to_le64 (pci_map_single + (np->pdev, skb->data, np->rx_buf_sz, + PCI_DMA_FROMDEVICE)); } np->rx_ring[entry].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48); @@ -1829,10 +1818,10 @@ rio_remove1 (struct pci_dev *pdev) struct netdev_private *np = netdev_priv(dev); unregister_netdev (dev); - dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring, - np->rx_ring_dma); - dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring, - np->tx_ring_dma); + pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, + np->rx_ring_dma); + pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, + np->tx_ring_dma); #ifdef MEM_MAPPING pci_iounmap(pdev, np->ioaddr); #endif diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c index a142dfea8da9..ce235def334f 100644 --- a/drivers/net/ethernet/emulex/benet/be_main.c +++ b/drivers/net/ethernet/emulex/benet/be_main.c @@ -1298,8 +1298,7 @@ static void be_xmit_flush(struct be_adapter *adapter, struct be_tx_obj *txo) (adapter->bmc_filt_mask & BMC_FILT_MULTICAST) static bool be_send_pkt_to_bmc(struct be_adapter *adapter, - struct sk_buff **skb, - struct be_wrb_params *wrb_params) + struct sk_buff **skb) { struct ethhdr *eh = (struct ethhdr *)(*skb)->data; bool os2bmc = false; @@ -1363,7 +1362,7 @@ done: * to BMC, asic expects the vlan to be inline in the packet. */ if (os2bmc) - *skb = be_insert_vlan_in_pkt(adapter, *skb, wrb_params); + *skb = be_insert_vlan_in_pkt(adapter, *skb, NULL); return os2bmc; } @@ -1390,7 +1389,7 @@ static netdev_tx_t be_xmit(struct sk_buff *skb, struct net_device *netdev) /* if os2bmc is enabled and if the pkt is destined to bmc, * enqueue the pkt a 2nd time with mgmt bit set. */ - if (be_send_pkt_to_bmc(adapter, &skb, &wrb_params)) { + if (be_send_pkt_to_bmc(adapter, &skb)) { BE_WRB_F_SET(wrb_params.features, OS2BMC, 1); wrb_cnt = be_xmit_enqueue(adapter, txo, skb, &wrb_params); if (unlikely(!wrb_cnt)) diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c index da1edc873b32..8649578b54c1 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c @@ -1772,8 +1772,11 @@ static int setup_xdp(struct net_device *dev, struct bpf_prog *prog) if (prog && !xdp_mtu_valid(priv, dev->mtu)) return -EINVAL; - if (prog) - bpf_prog_add(prog, priv->num_channels); + if (prog) { + prog = bpf_prog_add(prog, priv->num_channels); + if (IS_ERR(prog)) + return PTR_ERR(prog); + } up = netif_running(dev); need_update = (!!priv->xdp_prog != !!prog); diff --git a/drivers/net/ethernet/freescale/enetc/enetc.h b/drivers/net/ethernet/freescale/enetc/enetc.h index 6203d117d0d2..b8801a2b6a02 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc.h +++ b/drivers/net/ethernet/freescale/enetc/enetc.h @@ -27,7 +27,7 @@ struct enetc_tx_swbd { }; #define ENETC_RX_MAXFRM_SIZE ENETC_MAC_MAXFRM_SIZE -#define ENETC_RXB_TRUESIZE (PAGE_SIZE >> 1) +#define ENETC_RXB_TRUESIZE 2048 /* PAGE_SIZE >> 1 */ #define ENETC_RXB_PAD NET_SKB_PAD /* add extra space if needed */ #define ENETC_RXB_DMA_SIZE \ (SKB_WITH_OVERHEAD(ENETC_RXB_TRUESIZE) - ENETC_RXB_PAD) diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c index cd2fd2926f2f..7b2ab0cc562c 100644 --- a/drivers/net/ethernet/freescale/fec_main.c +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -1530,8 +1530,6 @@ fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) ndev->stats.rx_packets++; pkt_len = fec16_to_cpu(bdp->cbd_datlen); ndev->stats.rx_bytes += pkt_len; - if (fep->quirks & FEC_QUIRK_HAS_RACC) - ndev->stats.rx_bytes -= 2; index = fec_enet_get_bd_index(bdp, &rxq->bd); skb = rxq->rx_skbuff[index]; diff --git a/drivers/net/ethernet/freescale/fsl_pq_mdio.c b/drivers/net/ethernet/freescale/fsl_pq_mdio.c index 565a8bfe5692..c6481bd61239 100644 --- a/drivers/net/ethernet/freescale/fsl_pq_mdio.c +++ b/drivers/net/ethernet/freescale/fsl_pq_mdio.c @@ -482,12 +482,10 @@ static int fsl_pq_mdio_probe(struct platform_device *pdev) "missing 'reg' property in node %pOF\n", tbi); err = -EBUSY; - of_node_put(tbi); goto error; } set_tbipa(*prop, pdev, data->get_tbipa, priv->map, &res); - of_node_put(tbi); } } diff --git a/drivers/net/ethernet/intel/fm10k/fm10k_common.c b/drivers/net/ethernet/intel/fm10k/fm10k_common.c index 1f919a50c765..f51a63fca513 100644 --- a/drivers/net/ethernet/intel/fm10k/fm10k_common.c +++ b/drivers/net/ethernet/intel/fm10k/fm10k_common.c @@ -447,16 +447,17 @@ void fm10k_update_hw_stats_q(struct fm10k_hw *hw, struct fm10k_hw_stats_q *q, /** * fm10k_unbind_hw_stats_q - Unbind the queue counters from their queues * @q: pointer to the ring of hardware statistics queue + * @idx: index pointing to the start of the ring iteration * @count: number of queues to iterate over * * Function invalidates the index values for the queues so any updates that * may have happened are ignored and the base for the queue stats is reset. **/ -void fm10k_unbind_hw_stats_q(struct fm10k_hw_stats_q *q, u32 count) +void fm10k_unbind_hw_stats_q(struct fm10k_hw_stats_q *q, u32 idx, u32 count) { u32 i; - for (i = 0; i < count; i++, q++) { + for (i = 0; i < count; i++, idx++, q++) { q->rx_stats_idx = 0; q->tx_stats_idx = 0; } diff --git a/drivers/net/ethernet/intel/fm10k/fm10k_common.h b/drivers/net/ethernet/intel/fm10k/fm10k_common.h index 13fca6a91a01..4c48fb73b3e7 100644 --- a/drivers/net/ethernet/intel/fm10k/fm10k_common.h +++ b/drivers/net/ethernet/intel/fm10k/fm10k_common.h @@ -43,6 +43,6 @@ u32 fm10k_read_hw_stats_32b(struct fm10k_hw *hw, u32 addr, void fm10k_update_hw_stats_q(struct fm10k_hw *hw, struct fm10k_hw_stats_q *q, u32 idx, u32 count); #define fm10k_unbind_hw_stats_32b(s) ((s)->base_h = 0) -void fm10k_unbind_hw_stats_q(struct fm10k_hw_stats_q *q, u32 count); +void fm10k_unbind_hw_stats_q(struct fm10k_hw_stats_q *q, u32 idx, u32 count); s32 fm10k_get_host_state_generic(struct fm10k_hw *hw, bool *host_ready); #endif /* _FM10K_COMMON_H_ */ diff --git a/drivers/net/ethernet/intel/fm10k/fm10k_pf.c b/drivers/net/ethernet/intel/fm10k/fm10k_pf.c index 40c5bdb3ac2c..be07bfdb0bb4 100644 --- a/drivers/net/ethernet/intel/fm10k/fm10k_pf.c +++ b/drivers/net/ethernet/intel/fm10k/fm10k_pf.c @@ -1509,7 +1509,7 @@ static void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw, fm10k_unbind_hw_stats_32b(&stats->nodesc_drop); /* Unbind Queue Statistics */ - fm10k_unbind_hw_stats_q(stats->q, hw->mac.max_queues); + fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues); /* Reinitialize bases for all stats */ fm10k_update_hw_stats_pf(hw, stats); diff --git a/drivers/net/ethernet/intel/fm10k/fm10k_vf.c b/drivers/net/ethernet/intel/fm10k/fm10k_vf.c index 6a3aebd56e6c..dc8ccd378ec9 100644 --- a/drivers/net/ethernet/intel/fm10k/fm10k_vf.c +++ b/drivers/net/ethernet/intel/fm10k/fm10k_vf.c @@ -465,7 +465,7 @@ static void fm10k_rebind_hw_stats_vf(struct fm10k_hw *hw, struct fm10k_hw_stats *stats) { /* Unbind Queue Statistics */ - fm10k_unbind_hw_stats_q(stats->q, hw->mac.max_queues); + fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues); /* Reinitialize bases for all stats */ fm10k_update_hw_stats_vf(hw, stats); diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c index 9d0f197a1448..ff213cbe84ca 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c +++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c @@ -2194,7 +2194,7 @@ static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf, int i40e_xmit_xdp_tx_ring(struct xdp_buff *xdp, struct i40e_ring *xdp_ring) { - struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); + struct xdp_frame *xdpf = convert_to_xdp_frame(xdp); if (unlikely(!xdpf)) return I40E_XDP_CONSUMED; diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c index 4222590b2767..3a188576f4c8 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c @@ -2225,7 +2225,7 @@ static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, case XDP_PASS: break; case XDP_TX: - xdpf = xdp_convert_buff_to_frame(xdp); + xdpf = convert_to_xdp_frame(xdp); if (unlikely(!xdpf)) { result = IXGBE_XDP_CONSUMED; break; diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.c index a6e40dbca5d8..c68eb5dddf5b 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.c @@ -161,7 +161,7 @@ static int ixgbe_run_xdp_zc(struct ixgbe_adapter *adapter, case XDP_PASS: break; case XDP_TX: - xdpf = xdp_convert_buff_to_frame(xdp); + xdpf = convert_to_xdp_frame(xdp); if (unlikely(!xdpf)) { result = IXGBE_XDP_CONSUMED; break; diff --git a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c index 29f57d511a1c..91334229c120 100644 --- a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c +++ b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c @@ -1175,9 +1175,9 @@ static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv, mlx4_unregister_mac(mdev->dev, priv->port, mac); hlist_del_rcu(&entry->hlist); + kfree_rcu(entry, rcu); en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n", entry->mac, priv->port); - kfree_rcu(entry, rcu); ++removed; } } @@ -2307,7 +2307,11 @@ int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv, lockdep_is_held(&priv->mdev->state_lock)); if (xdp_prog && carry_xdp_prog) { - bpf_prog_add(xdp_prog, tmp->rx_ring_num); + xdp_prog = bpf_prog_add(xdp_prog, tmp->rx_ring_num); + if (IS_ERR(xdp_prog)) { + mlx4_en_free_resources(tmp); + return PTR_ERR(xdp_prog); + } for (i = 0; i < tmp->rx_ring_num; i++) rcu_assign_pointer(tmp->rx_ring[i]->xdp_prog, xdp_prog); @@ -2801,9 +2805,11 @@ static int mlx4_xdp_set(struct net_device *dev, struct bpf_prog *prog) * program for a new one. */ if (priv->tx_ring_num[TX_XDP] == xdp_ring_num) { - if (prog) - bpf_prog_add(prog, priv->rx_ring_num - 1); - + if (prog) { + prog = bpf_prog_add(prog, priv->rx_ring_num - 1); + if (IS_ERR(prog)) + return PTR_ERR(prog); + } mutex_lock(&mdev->state_lock); for (i = 0; i < priv->rx_ring_num; i++) { old_prog = rcu_dereference_protected( @@ -2824,8 +2830,13 @@ static int mlx4_xdp_set(struct net_device *dev, struct bpf_prog *prog) if (!tmp) return -ENOMEM; - if (prog) - bpf_prog_add(prog, priv->rx_ring_num - 1); + if (prog) { + prog = bpf_prog_add(prog, priv->rx_ring_num - 1); + if (IS_ERR(prog)) { + err = PTR_ERR(prog); + goto out; + } + } mutex_lock(&mdev->state_lock); memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile)); @@ -2875,6 +2886,7 @@ static int mlx4_xdp_set(struct net_device *dev, struct bpf_prog *prog) unlock_out: mutex_unlock(&mdev->state_lock); +out: kfree(tmp); return err; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/port_buffer.h b/drivers/net/ethernet/mellanox/mlx5/core/en/port_buffer.h index 34f55b81a0de..7b852b87a609 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/port_buffer.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/port_buffer.h @@ -64,11 +64,23 @@ struct mlx5e_port_buffer { struct mlx5e_bufferx_reg buffer[MLX5E_MAX_BUFFER]; }; +#ifdef CONFIG_MLX5_CORE_EN_DCB int mlx5e_port_manual_buffer_config(struct mlx5e_priv *priv, u32 change, unsigned int mtu, struct ieee_pfc *pfc, u32 *buffer_size, u8 *prio2buffer); +#else +static inline int +mlx5e_port_manual_buffer_config(struct mlx5e_priv *priv, + u32 change, unsigned int mtu, + void *pfc, + u32 *buffer_size, + u8 *prio2buffer) +{ + return 0; +} +#endif int mlx5e_port_query_buffer(struct mlx5e_priv *priv, struct mlx5e_port_buffer *port_buffer); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c b/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c index 86f4b58373f2..f049e0ac308a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c @@ -64,7 +64,7 @@ mlx5e_xmit_xdp_buff(struct mlx5e_xdpsq *sq, struct mlx5e_rq *rq, struct xdp_frame *xdpf; dma_addr_t dma_addr; - xdpf = xdp_convert_buff_to_frame(xdp); + xdpf = convert_to_xdp_frame(xdp); if (unlikely(!xdpf)) return false; @@ -97,10 +97,10 @@ mlx5e_xmit_xdp_buff(struct mlx5e_xdpsq *sq, struct mlx5e_rq *rq, xdpi.frame.xdpf = xdpf; xdpi.frame.dma_addr = dma_addr; } else { - /* Driver assumes that xdp_convert_buff_to_frame returns - * an xdp_frame that points to the same memory region as - * the original xdp_buff. It allows to map the memory only - * once and to use the DMA_BIDIRECTIONAL mode. + /* Driver assumes that convert_to_xdp_frame returns an xdp_frame + * that points to the same memory region as the original + * xdp_buff. It allows to map the memory only once and to use + * the DMA_BIDIRECTIONAL mode. */ xdpi.mode = MLX5E_XDP_XMIT_MODE_PAGE; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c b/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c index 4acab31f53ac..f1952e14c804 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c @@ -579,35 +579,26 @@ static int mlx5e_dcbnl_ieee_setmaxrate(struct net_device *netdev, struct mlx5_core_dev *mdev = priv->mdev; u8 max_bw_value[IEEE_8021QAZ_MAX_TCS]; u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS]; - __u64 upper_limit_mbps; - __u64 upper_limit_gbps; + __u64 upper_limit_mbps = roundup(255 * MLX5E_100MB, MLX5E_1GB); int i; memset(max_bw_value, 0, sizeof(max_bw_value)); memset(max_bw_unit, 0, sizeof(max_bw_unit)); - upper_limit_mbps = 255 * MLX5E_100MB; - upper_limit_gbps = 255 * MLX5E_1GB; for (i = 0; i <= mlx5_max_tc(mdev); i++) { if (!maxrate->tc_maxrate[i]) { max_bw_unit[i] = MLX5_BW_NO_LIMIT; continue; } - if (maxrate->tc_maxrate[i] <= upper_limit_mbps) { + if (maxrate->tc_maxrate[i] < upper_limit_mbps) { max_bw_value[i] = div_u64(maxrate->tc_maxrate[i], MLX5E_100MB); max_bw_value[i] = max_bw_value[i] ? max_bw_value[i] : 1; max_bw_unit[i] = MLX5_100_MBPS_UNIT; - } else if (max_bw_value[i] <= upper_limit_gbps) { + } else { max_bw_value[i] = div_u64(maxrate->tc_maxrate[i], MLX5E_1GB); max_bw_unit[i] = MLX5_GBPS_UNIT; - } else { - netdev_err(netdev, - "tc_%d maxrate %llu Kbps exceeds limit %llu\n", - i, maxrate->tc_maxrate[i], - upper_limit_gbps); - return -EINVAL; } } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 06605d566ce5..41bd16cc9d0f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -42,6 +42,7 @@ #include "eswitch.h" #include "en.h" #include "en/txrx.h" +#include "en/port_buffer.h" #include "en_tc.h" #include "en_rep.h" #include "en_accel/ipsec.h" @@ -448,9 +449,12 @@ static int mlx5e_alloc_rq(struct mlx5e_channel *c, rq->stats = &c->priv->channel_stats[c->ix].rq; INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work); - if (params->xdp_prog) - bpf_prog_inc(params->xdp_prog); - rq->xdp_prog = params->xdp_prog; + rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL; + if (IS_ERR(rq->xdp_prog)) { + err = PTR_ERR(rq->xdp_prog); + rq->xdp_prog = NULL; + goto err_rq_wq_destroy; + } rq_xdp_ix = rq->ix; if (xsk) @@ -2891,9 +2895,11 @@ int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv) struct mlx5e_params *params = &priv->channels.params; struct net_device *netdev = priv->netdev; struct mlx5_core_dev *mdev = priv->mdev; - u16 mtu; + u16 mtu, prev_mtu; int err; + mlx5e_query_mtu(mdev, params, &prev_mtu); + err = mlx5e_set_mtu(mdev, params, params->sw_mtu); if (err) return err; @@ -2903,6 +2909,18 @@ int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv) netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n", __func__, mtu, params->sw_mtu); + if (mtu != prev_mtu && MLX5_BUFFER_SUPPORTED(mdev)) { + err = mlx5e_port_manual_buffer_config(priv, 0, mtu, + NULL, NULL, NULL); + if (err) { + netdev_warn(netdev, "%s: Failed to set Xon/Xoff values with MTU %d (err %d), setting back to previous MTU %d\n", + __func__, mtu, err, prev_mtu); + + mlx5e_set_mtu(mdev, params, prev_mtu); + return err; + } + } + params->sw_mtu = mtu; return 0; } @@ -4564,11 +4582,16 @@ static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog) /* no need for full reset when exchanging programs */ reset = (!priv->channels.params.xdp_prog || !prog); - if (was_opened && !reset) + if (was_opened && !reset) { /* num_channels is invariant here, so we can take the * batched reference right upfront. */ - bpf_prog_add(prog, priv->channels.num); + prog = bpf_prog_add(prog, priv->channels.num); + if (IS_ERR(prog)) { + err = PTR_ERR(prog); + goto unlock; + } + } if (was_opened && reset) { struct mlx5e_channels new_channels = {}; diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c index 4eeebcb50ab6..498de6ef6870 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c @@ -542,10 +542,8 @@ int mlxsw_sp_flower_stats(struct mlxsw_sp *mlxsw_sp, return -EINVAL; rule = mlxsw_sp_acl_rule_lookup(mlxsw_sp, ruleset, f->cookie); - if (!rule) { - err = -EINVAL; - goto err_rule_get_stats; - } + if (!rule) + return -EINVAL; err = mlxsw_sp_acl_rule_get_stats(mlxsw_sp, rule, &packets, &bytes, &lastuse); diff --git a/drivers/net/ethernet/netronome/nfp/bpf/offload.c b/drivers/net/ethernet/netronome/nfp/bpf/offload.c index 6201f9299b2f..409b636c7647 100644 --- a/drivers/net/ethernet/netronome/nfp/bpf/offload.c +++ b/drivers/net/ethernet/netronome/nfp/bpf/offload.c @@ -46,7 +46,9 @@ nfp_map_ptr_record(struct nfp_app_bpf *bpf, struct nfp_prog *nfp_prog, /* Grab a single ref to the map for our record. The prog destroy ndo * happens after free_used_maps(). */ - bpf_map_inc(map); + map = bpf_map_inc(map, false); + if (IS_ERR(map)) + return PTR_ERR(map); record = kmalloc(sizeof(*record), GFP_KERNEL); if (!record) { @@ -111,9 +113,7 @@ static int nfp_map_ptrs_record(struct nfp_app_bpf *bpf, struct nfp_prog *nfp_prog, struct bpf_prog *prog) { - int i, cnt, err = 0; - - mutex_lock(&prog->aux->used_maps_mutex); + int i, cnt, err; /* Quickly count the maps we will have to remember */ cnt = 0; @@ -121,15 +121,13 @@ nfp_map_ptrs_record(struct nfp_app_bpf *bpf, struct nfp_prog *nfp_prog, if (bpf_map_offload_neutral(prog->aux->used_maps[i])) cnt++; if (!cnt) - goto out; + return 0; nfp_prog->map_records = kmalloc_array(cnt, sizeof(nfp_prog->map_records[0]), GFP_KERNEL); - if (!nfp_prog->map_records) { - err = -ENOMEM; - goto out; - } + if (!nfp_prog->map_records) + return -ENOMEM; for (i = 0; i < prog->aux->used_map_cnt; i++) if (bpf_map_offload_neutral(prog->aux->used_maps[i])) { @@ -137,14 +135,12 @@ nfp_map_ptrs_record(struct nfp_app_bpf *bpf, struct nfp_prog *nfp_prog, prog->aux->used_maps[i]); if (err) { nfp_map_ptrs_forget(bpf, nfp_prog); - goto out; + return err; } } WARN_ON(cnt != nfp_prog->map_records_cnt); -out: - mutex_unlock(&prog->aux->used_maps_mutex); - return err; + return 0; } static int diff --git a/drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c b/drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c index 6e1707ef391d..ff8810357181 100644 --- a/drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c +++ b/drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c @@ -914,7 +914,7 @@ static u32 nfp_net_get_rxfh_key_size(struct net_device *netdev) struct nfp_net *nn = netdev_priv(netdev); if (!(nn->cap & NFP_NET_CFG_CTRL_RSS_ANY)) - return 0; + return -EOPNOTSUPP; return nfp_net_rss_key_sz(nn); } diff --git a/drivers/net/ethernet/qlogic/qede/qede_main.c b/drivers/net/ethernet/qlogic/qede/qede_main.c index 4bbcf15572fc..1133f6fe21a0 100644 --- a/drivers/net/ethernet/qlogic/qede/qede_main.c +++ b/drivers/net/ethernet/qlogic/qede/qede_main.c @@ -216,7 +216,7 @@ static struct pci_driver qede_pci_driver = { }; static struct qed_eth_cb_ops qede_ll_ops = { - .common = { + { #ifdef CONFIG_RFS_ACCEL .arfs_filter_op = qede_arfs_filter_op, #endif @@ -2124,8 +2124,12 @@ static int qede_start_queues(struct qede_dev *edev, bool clear_stats) if (rc) goto out; - bpf_prog_add(edev->xdp_prog, 1); - fp->rxq->xdp_prog = edev->xdp_prog; + fp->rxq->xdp_prog = bpf_prog_add(edev->xdp_prog, 1); + if (IS_ERR(fp->rxq->xdp_prog)) { + rc = PTR_ERR(fp->rxq->xdp_prog); + fp->rxq->xdp_prog = NULL; + goto out; + } } if (fp->type & QEDE_FASTPATH_TX) { diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 0976916d6db1..3cc312a526d9 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1593,35 +1593,15 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) } skb_tx_timestamp(skb); - + /* Descriptor type must be set after all the above writes */ + dma_wmb(); if (num_tx_desc > 1) { desc->die_dt = DT_FEND; desc--; - /* When using multi-descriptors, DT_FEND needs to get written - * before DT_FSTART, but the compiler may reorder the memory - * writes in an attempt to optimize the code. - * Use a dma_wmb() barrier to make sure DT_FEND and DT_FSTART - * are written exactly in the order shown in the code. - * This is particularly important for cases where the DMA engine - * is already running when we are running this code. If the DMA - * sees DT_FSTART without the corresponding DT_FEND it will enter - * an error condition. - */ - dma_wmb(); desc->die_dt = DT_FSTART; } else { - /* Descriptor type must be set after all the above writes */ - dma_wmb(); desc->die_dt = DT_FSINGLE; } - - /* Before ringing the doorbell we need to make sure that the latest - * writes have been committed to memory, otherwise it could delay - * things until the doorbell is rang again. - * This is in replacement of the read operation mentioned in the HW - * manuals. - */ - dma_wmb(); ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); priv->cur_tx[q] += num_tx_desc; diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c index 113774999d57..f808e60b4ee4 100644 --- a/drivers/net/ethernet/renesas/sh_eth.c +++ b/drivers/net/ethernet/renesas/sh_eth.c @@ -2397,7 +2397,6 @@ static int sh_eth_set_ringparam(struct net_device *ndev, return 0; } -#ifdef CONFIG_PM_SLEEP static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) { struct sh_eth_private *mdp = netdev_priv(ndev); @@ -2424,7 +2423,6 @@ static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) return 0; } -#endif static const struct ethtool_ops sh_eth_ethtool_ops = { .get_regs_len = sh_eth_get_regs_len, @@ -2440,10 +2438,8 @@ static const struct ethtool_ops sh_eth_ethtool_ops = { .set_ringparam = sh_eth_set_ringparam, .get_link_ksettings = phy_ethtool_get_link_ksettings, .set_link_ksettings = phy_ethtool_set_link_ksettings, -#ifdef CONFIG_PM_SLEEP .get_wol = sh_eth_get_wol, .set_wol = sh_eth_set_wol, -#endif }; /* network device open function */ diff --git a/drivers/net/ethernet/socionext/netsec.c b/drivers/net/ethernet/socionext/netsec.c index 88d75690ffbf..634aa85ceab7 100644 --- a/drivers/net/ethernet/socionext/netsec.c +++ b/drivers/net/ethernet/socionext/netsec.c @@ -867,7 +867,7 @@ static u32 netsec_xdp_queue_one(struct netsec_priv *priv, static u32 netsec_xdp_xmit_back(struct netsec_priv *priv, struct xdp_buff *xdp) { struct netsec_desc_ring *tx_ring = &priv->desc_ring[NETSEC_RING_TX]; - struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); + struct xdp_frame *xdpf = convert_to_xdp_frame(xdp); u32 ret; if (unlikely(!xdpf)) diff --git a/drivers/net/ethernet/ti/netcp_core.c b/drivers/net/ethernet/ti/netcp_core.c index 5c850cc3fae4..5dbb4ed1b132 100644 --- a/drivers/net/ethernet/ti/netcp_core.c +++ b/drivers/net/ethernet/ti/netcp_core.c @@ -1339,10 +1339,10 @@ int netcp_txpipe_open(struct netcp_tx_pipe *tx_pipe) tx_pipe->dma_channel = knav_dma_open_channel(dev, tx_pipe->dma_chan_name, &config); - if (!tx_pipe->dma_channel) { + if (IS_ERR(tx_pipe->dma_channel)) { dev_err(dev, "failed opening tx chan(%s)\n", tx_pipe->dma_chan_name); - ret = -EINVAL; + ret = PTR_ERR(tx_pipe->dma_channel); goto err; } @@ -1360,7 +1360,7 @@ int netcp_txpipe_open(struct netcp_tx_pipe *tx_pipe) return 0; err: - if (tx_pipe->dma_channel) + if (!IS_ERR_OR_NULL(tx_pipe->dma_channel)) knav_dma_close_channel(tx_pipe->dma_channel); tx_pipe->dma_channel = NULL; return ret; @@ -1679,10 +1679,10 @@ static int netcp_setup_navigator_resources(struct net_device *ndev) netcp->rx_channel = knav_dma_open_channel(netcp->netcp_device->device, netcp->dma_chan_name, &config); - if (!netcp->rx_channel) { + if (IS_ERR(netcp->rx_channel)) { dev_err(netcp->ndev_dev, "failed opening rx chan(%s\n", netcp->dma_chan_name); - ret = -EINVAL; + ret = PTR_ERR(netcp->rx_channel); goto fail; } diff --git a/drivers/net/geneve.c b/drivers/net/geneve.c index cb2fc0200768..c59351d2c7d7 100644 --- a/drivers/net/geneve.c +++ b/drivers/net/geneve.c @@ -1828,11 +1828,9 @@ static int geneve_netdevice_event(struct notifier_block *unused, event == NETDEV_UDP_TUNNEL_DROP_INFO) { geneve_offload_rx_ports(dev, event == NETDEV_UDP_TUNNEL_PUSH_INFO); } else if (event == NETDEV_UNREGISTER) { - if (!dev->udp_tunnel_nic_info) - geneve_offload_rx_ports(dev, false); + geneve_offload_rx_ports(dev, false); } else if (event == NETDEV_REGISTER) { - if (!dev->udp_tunnel_nic_info) - geneve_offload_rx_ports(dev, true); + geneve_offload_rx_ports(dev, true); } return NOTIFY_DONE; diff --git a/drivers/net/loopback.c b/drivers/net/loopback.c index f56545075cb6..1dd5044cc643 100644 --- a/drivers/net/loopback.c +++ b/drivers/net/loopback.c @@ -68,6 +68,7 @@ EXPORT_SYMBOL(blackhole_netdev); static netdev_tx_t loopback_xmit(struct sk_buff *skb, struct net_device *dev) { + struct pcpu_lstats *lb_stats; int len; skb_tx_timestamp(skb); @@ -84,20 +85,27 @@ static netdev_tx_t loopback_xmit(struct sk_buff *skb, skb->protocol = eth_type_trans(skb, dev); + /* it's OK to use per_cpu_ptr() because BHs are off */ + lb_stats = this_cpu_ptr(dev->lstats); + len = skb->len; - if (likely(netif_rx(skb) == NET_RX_SUCCESS)) - dev_lstats_add(dev, len); + if (likely(netif_rx(skb) == NET_RX_SUCCESS)) { + u64_stats_update_begin(&lb_stats->syncp); + lb_stats->bytes += len; + lb_stats->packets++; + u64_stats_update_end(&lb_stats->syncp); + } return NETDEV_TX_OK; } -void dev_lstats_read(struct net_device *dev, u64 *packets, u64 *bytes) +static void loopback_get_stats64(struct net_device *dev, + struct rtnl_link_stats64 *stats) { + u64 bytes = 0; + u64 packets = 0; int i; - *packets = 0; - *bytes = 0; - for_each_possible_cpu(i) { const struct pcpu_lstats *lb_stats; u64 tbytes, tpackets; @@ -106,22 +114,12 @@ void dev_lstats_read(struct net_device *dev, u64 *packets, u64 *bytes) lb_stats = per_cpu_ptr(dev->lstats, i); do { start = u64_stats_fetch_begin_irq(&lb_stats->syncp); - tpackets = lb_stats->packets; tbytes = lb_stats->bytes; + tpackets = lb_stats->packets; } while (u64_stats_fetch_retry_irq(&lb_stats->syncp, start)); - *bytes += tbytes; - *packets += tpackets; + bytes += tbytes; + packets += tpackets; } -} -EXPORT_SYMBOL(dev_lstats_read); - -static void loopback_get_stats64(struct net_device *dev, - struct rtnl_link_stats64 *stats) -{ - u64 packets, bytes; - - dev_lstats_read(dev, &packets, &bytes); - stats->rx_packets = packets; stats->tx_packets = packets; stats->rx_bytes = bytes; diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index c8a01672884b..1375beb3cf83 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -337,12 +337,6 @@ static int dp83867_config_init(struct phy_device *phydev) return ret; } - /* Although the DP83867 reports EEE capability through the - * MDIO_PCS_EEE_ABLE and MDIO_AN_EEE_ADV registers, the feature - * is not actually implemented in hardware. - */ - phydev->eee_broken_modes = MDIO_EEE_100TX | MDIO_EEE_1000T; - if (phy_interface_is_rgmii(phydev)) { val = phy_read(phydev, MII_DP83867_PHYCTRL); if (val < 0) diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c index bdce184759ef..931b9a6c5dc5 100644 --- a/drivers/net/phy/mdio_bus.c +++ b/drivers/net/phy/mdio_bus.c @@ -89,11 +89,8 @@ int mdiobus_register_device(struct mdio_device *mdiodev) return err; err = mdiobus_register_reset(mdiodev); - if (err) { - gpiod_put(mdiodev->reset_gpio); - mdiodev->reset_gpio = NULL; + if (err) return err; - } /* Assert the reset signal */ mdio_device_reset(mdiodev, 1); diff --git a/drivers/net/tun.c b/drivers/net/tun.c index 71c56c745e7d..1a6b4cdc3bd5 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -1407,7 +1407,7 @@ resample: static int tun_xdp_tx(struct net_device *dev, struct xdp_buff *xdp) { - struct xdp_frame *frame = xdp_convert_buff_to_frame(xdp); + struct xdp_frame *frame = convert_to_xdp_frame(xdp); if (unlikely(!frame)) return -EOVERFLOW; @@ -1801,7 +1801,7 @@ static struct sk_buff *tun_build_skb(struct tun_struct *tun, } if (err == XDP_REDIRECT) - xdp_do_flush(); + xdp_do_flush_map(); if (err != XDP_PASS) goto out; @@ -2657,7 +2657,7 @@ static int tun_sendmsg(struct socket *sock, struct msghdr *m, size_t total_len) } if (flush) - xdp_do_flush(); + xdp_do_flush_map(); rcu_read_unlock(); local_bh_enable(); diff --git a/drivers/net/usb/asix_devices.c b/drivers/net/usb/asix_devices.c index 196c48fd5119..ef548beba684 100644 --- a/drivers/net/usb/asix_devices.c +++ b/drivers/net/usb/asix_devices.c @@ -230,9 +230,7 @@ static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf) int i; unsigned long gpio_bits = dev->driver_info->data; - ret = usbnet_get_endpoints(dev, intf); - if (ret) - goto out; + usbnet_get_endpoints(dev,intf); /* Toggle the GPIOs in a manufacturer/model specific way */ for (i = 2; i >= 0; i--) { @@ -683,9 +681,7 @@ static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf) u32 phyid; struct asix_common_private *priv; - ret = usbnet_get_endpoints(dev, intf); - if (ret) - return ret; + usbnet_get_endpoints(dev, intf); /* Maybe the boot loader passed the MAC address via device tree */ if (!eth_platform_get_mac_address(&dev->udev->dev, buf)) { @@ -1067,9 +1063,7 @@ static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf) int ret; u8 buf[ETH_ALEN] = {0}; - ret = usbnet_get_endpoints(dev, intf); - if (ret) - return ret; + usbnet_get_endpoints(dev,intf); /* Get the MAC address */ ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0); diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c index 274b15d2a2cc..acf1321657ec 100644 --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c @@ -229,12 +229,6 @@ static int qmimux_rx_fixup(struct usbnet *dev, struct sk_buff *skb) return 0; skbn->dev = net; - /* Raw IP packets don't have a MAC header, but other subsystems - * (like xfrm) may still access MAC header offsets, so they must - * be initialized. - */ - skb_reset_mac_header(skbn); - switch (skb->data[offset + qmimux_hdr_sz] & 0xf0) { case 0x40: skbn->protocol = htons(ETH_P_IP); diff --git a/drivers/net/usb/rtl8150.c b/drivers/net/usb/rtl8150.c index 9460ef391c09..387091cb9134 100644 --- a/drivers/net/usb/rtl8150.c +++ b/drivers/net/usb/rtl8150.c @@ -676,6 +676,7 @@ static void rtl8150_set_multicast(struct net_device *netdev) rtl8150_t *dev = netdev_priv(netdev); u16 rx_creg = 0x9e; + netif_stop_queue(netdev); if (netdev->flags & IFF_PROMISC) { rx_creg |= 0x0001; dev_info(&netdev->dev, "%s: promiscuous mode\n", netdev->name); @@ -689,25 +690,18 @@ static void rtl8150_set_multicast(struct net_device *netdev) rx_creg &= 0x00fc; } async_set_registers(dev, RCR, sizeof(rx_creg), rx_creg); + netif_wake_queue(netdev); } static netdev_tx_t rtl8150_start_xmit(struct sk_buff *skb, struct net_device *netdev) { rtl8150_t *dev = netdev_priv(netdev); - int res; - unsigned int count; - - /* pad the frame and ensure terminating USB packet, datasheet 9.2.3 */ - count = max_t(unsigned int, skb->len, ETH_ZLEN); - if (count % 64 == 0) - count++; - if (skb_padto(skb, count)) { - netdev->stats.tx_dropped++; - return NETDEV_TX_OK; - } + int count, res; netif_stop_queue(netdev); + count = (skb->len < 60) ? 60 : skb->len; + count = (count & 0x3f) ? count : count + 1; dev->tx_skb = skb; usb_fill_bulk_urb(dev->tx_urb, dev->udev, usb_sndbulkpipe(dev->udev, 2), skb->data, count, write_bulk_callback, dev); diff --git a/drivers/net/usb/usbnet.c b/drivers/net/usb/usbnet.c index 7ecc3a21bc71..c6637fa70a7d 100644 --- a/drivers/net/usb/usbnet.c +++ b/drivers/net/usb/usbnet.c @@ -1630,8 +1630,6 @@ void usbnet_disconnect (struct usb_interface *intf) net = dev->net; unregister_netdev (net); - cancel_work_sync(&dev->kevent); - while ((urb = usb_get_from_anchor(&dev->deferred))) { dev_kfree_skb(urb->context); kfree(urb->sg); diff --git a/drivers/net/veth.c b/drivers/net/veth.c index 8bb1bb4ddb05..cae7247a397a 100644 --- a/drivers/net/veth.c +++ b/drivers/net/veth.c @@ -34,23 +34,16 @@ #define VETH_RING_SIZE 256 #define VETH_XDP_HEADROOM (XDP_PACKET_HEADROOM + NET_IP_ALIGN) +/* Separating two types of XDP xmit */ +#define VETH_XDP_TX BIT(0) +#define VETH_XDP_REDIR BIT(1) + #define VETH_XDP_TX_BULK_SIZE 16 -struct veth_stats { - u64 rx_drops; - /* xdp */ - u64 xdp_packets; - u64 xdp_bytes; - u64 xdp_redirect; - u64 xdp_drops; - u64 xdp_tx; - u64 xdp_tx_err; - u64 peer_tq_xdp_xmit; - u64 peer_tq_xdp_xmit_err; -}; - struct veth_rq_stats { - struct veth_stats vs; + u64 xdp_packets; + u64 xdp_bytes; + u64 xdp_drops; struct u64_stats_sync syncp; }; @@ -87,27 +80,16 @@ struct veth_q_stat_desc { size_t offset; }; -#define VETH_RQ_STAT(m) offsetof(struct veth_stats, m) +#define VETH_RQ_STAT(m) offsetof(struct veth_rq_stats, m) static const struct veth_q_stat_desc veth_rq_stats_desc[] = { { "xdp_packets", VETH_RQ_STAT(xdp_packets) }, { "xdp_bytes", VETH_RQ_STAT(xdp_bytes) }, - { "drops", VETH_RQ_STAT(rx_drops) }, - { "xdp_redirect", VETH_RQ_STAT(xdp_redirect) }, { "xdp_drops", VETH_RQ_STAT(xdp_drops) }, - { "xdp_tx", VETH_RQ_STAT(xdp_tx) }, - { "xdp_tx_errors", VETH_RQ_STAT(xdp_tx_err) }, }; #define VETH_RQ_STATS_LEN ARRAY_SIZE(veth_rq_stats_desc) -static const struct veth_q_stat_desc veth_tq_stats_desc[] = { - { "xdp_xmit", VETH_RQ_STAT(peer_tq_xdp_xmit) }, - { "xdp_xmit_errors", VETH_RQ_STAT(peer_tq_xdp_xmit_err) }, -}; - -#define VETH_TQ_STATS_LEN ARRAY_SIZE(veth_tq_stats_desc) - static struct { const char string[ETH_GSTRING_LEN]; } ethtool_stats_keys[] = { @@ -142,19 +124,11 @@ static void veth_get_strings(struct net_device *dev, u32 stringset, u8 *buf) for (i = 0; i < dev->real_num_rx_queues; i++) { for (j = 0; j < VETH_RQ_STATS_LEN; j++) { snprintf(p, ETH_GSTRING_LEN, - "rx_queue_%u_%.18s", + "rx_queue_%u_%.11s", i, veth_rq_stats_desc[j].desc); p += ETH_GSTRING_LEN; } } - for (i = 0; i < dev->real_num_tx_queues; i++) { - for (j = 0; j < VETH_TQ_STATS_LEN; j++) { - snprintf(p, ETH_GSTRING_LEN, - "tx_queue_%u_%.18s", - i, veth_tq_stats_desc[j].desc); - p += ETH_GSTRING_LEN; - } - } break; } } @@ -164,8 +138,7 @@ static int veth_get_sset_count(struct net_device *dev, int sset) switch (sset) { case ETH_SS_STATS: return ARRAY_SIZE(ethtool_stats_keys) + - VETH_RQ_STATS_LEN * dev->real_num_rx_queues + - VETH_TQ_STATS_LEN * dev->real_num_tx_queues; + VETH_RQ_STATS_LEN * dev->real_num_rx_queues; default: return -EOPNOTSUPP; } @@ -174,7 +147,7 @@ static int veth_get_sset_count(struct net_device *dev, int sset) static void veth_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) { - struct veth_priv *rcv_priv, *priv = netdev_priv(dev); + struct veth_priv *priv = netdev_priv(dev); struct net_device *peer = rtnl_dereference(priv->peer); int i, j, idx; @@ -182,7 +155,7 @@ static void veth_get_ethtool_stats(struct net_device *dev, idx = 1; for (i = 0; i < dev->real_num_rx_queues; i++) { const struct veth_rq_stats *rq_stats = &priv->rq[i].stats; - const void *stats_base = (void *)&rq_stats->vs; + const void *stats_base = (void *)rq_stats; unsigned int start; size_t offset; @@ -195,26 +168,6 @@ static void veth_get_ethtool_stats(struct net_device *dev, } while (u64_stats_fetch_retry_irq(&rq_stats->syncp, start)); idx += VETH_RQ_STATS_LEN; } - - if (!peer) - return; - - rcv_priv = netdev_priv(peer); - for (i = 0; i < peer->real_num_rx_queues; i++) { - const struct veth_rq_stats *rq_stats = &rcv_priv->rq[i].stats; - const void *base = (void *)&rq_stats->vs; - unsigned int start, tx_idx = idx; - size_t offset; - - tx_idx += (i % dev->real_num_tx_queues) * VETH_TQ_STATS_LEN; - do { - start = u64_stats_fetch_begin_irq(&rq_stats->syncp); - for (j = 0; j < VETH_TQ_STATS_LEN; j++) { - offset = veth_tq_stats_desc[j].offset; - data[tx_idx + j] += *(u64 *)(base + offset); - } - } while (u64_stats_fetch_retry_irq(&rq_stats->syncp, start)); - } } static const struct ethtool_ops veth_ethtool_ops = { @@ -234,14 +187,14 @@ static bool veth_is_xdp_frame(void *ptr) return (unsigned long)ptr & VETH_XDP_FLAG; } -static struct xdp_frame *veth_ptr_to_xdp(void *ptr) +static void *veth_ptr_to_xdp(void *ptr) { return (void *)((unsigned long)ptr & ~VETH_XDP_FLAG); } -static void *veth_xdp_to_ptr(struct xdp_frame *xdp) +static void *veth_xdp_to_ptr(void *ptr) { - return (void *)((unsigned long)xdp | VETH_XDP_FLAG); + return (void *)((unsigned long)ptr | VETH_XDP_FLAG); } static void veth_ptr_free(void *ptr) @@ -307,8 +260,14 @@ static netdev_tx_t veth_xmit(struct sk_buff *skb, struct net_device *dev) skb_tx_timestamp(skb); if (likely(veth_forward_skb(rcv, skb, rq, rcv_xdp) == NET_RX_SUCCESS)) { - if (!rcv_xdp) - dev_lstats_add(dev, length); + if (!rcv_xdp) { + struct pcpu_lstats *stats = this_cpu_ptr(dev->lstats); + + u64_stats_update_begin(&stats->syncp); + stats->bytes += length; + stats->packets++; + u64_stats_update_end(&stats->syncp); + } } else { drop: atomic64_inc(&priv->dropped); @@ -323,42 +282,51 @@ drop: return ret; } -static u64 veth_stats_tx(struct net_device *dev, u64 *packets, u64 *bytes) +static u64 veth_stats_tx(struct pcpu_lstats *result, struct net_device *dev) { struct veth_priv *priv = netdev_priv(dev); + int cpu; - dev_lstats_read(dev, packets, bytes); - return atomic64_read(&priv->dropped); -} - -static void veth_stats_rx(struct veth_stats *result, struct net_device *dev) -{ - struct veth_priv *priv = netdev_priv(dev); - int i; - - result->peer_tq_xdp_xmit_err = 0; - result->xdp_packets = 0; - result->xdp_tx_err = 0; - result->xdp_bytes = 0; - result->rx_drops = 0; - for (i = 0; i < dev->num_rx_queues; i++) { - u64 packets, bytes, drops, xdp_tx_err, peer_tq_xdp_xmit_err; - struct veth_rq_stats *stats = &priv->rq[i].stats; + result->packets = 0; + result->bytes = 0; + for_each_possible_cpu(cpu) { + struct pcpu_lstats *stats = per_cpu_ptr(dev->lstats, cpu); + u64 packets, bytes; unsigned int start; do { start = u64_stats_fetch_begin_irq(&stats->syncp); - peer_tq_xdp_xmit_err = stats->vs.peer_tq_xdp_xmit_err; - xdp_tx_err = stats->vs.xdp_tx_err; - packets = stats->vs.xdp_packets; - bytes = stats->vs.xdp_bytes; - drops = stats->vs.rx_drops; + packets = stats->packets; + bytes = stats->bytes; + } while (u64_stats_fetch_retry_irq(&stats->syncp, start)); + result->packets += packets; + result->bytes += bytes; + } + return atomic64_read(&priv->dropped); +} + +static void veth_stats_rx(struct veth_rq_stats *result, struct net_device *dev) +{ + struct veth_priv *priv = netdev_priv(dev); + int i; + + result->xdp_packets = 0; + result->xdp_bytes = 0; + result->xdp_drops = 0; + for (i = 0; i < dev->num_rx_queues; i++) { + struct veth_rq_stats *stats = &priv->rq[i].stats; + u64 packets, bytes, drops; + unsigned int start; + + do { + start = u64_stats_fetch_begin_irq(&stats->syncp); + packets = stats->xdp_packets; + bytes = stats->xdp_bytes; + drops = stats->xdp_drops; } while (u64_stats_fetch_retry_irq(&stats->syncp, start)); - result->peer_tq_xdp_xmit_err += peer_tq_xdp_xmit_err; - result->xdp_tx_err += xdp_tx_err; result->xdp_packets += packets; result->xdp_bytes += bytes; - result->rx_drops += drops; + result->xdp_drops += drops; } } @@ -367,29 +335,26 @@ static void veth_get_stats64(struct net_device *dev, { struct veth_priv *priv = netdev_priv(dev); struct net_device *peer; - struct veth_stats rx; - u64 packets, bytes; + struct veth_rq_stats rx; + struct pcpu_lstats tx; - tot->tx_dropped = veth_stats_tx(dev, &packets, &bytes); - tot->tx_bytes = bytes; - tot->tx_packets = packets; + tot->tx_dropped = veth_stats_tx(&tx, dev); + tot->tx_bytes = tx.bytes; + tot->tx_packets = tx.packets; veth_stats_rx(&rx, dev); - tot->tx_dropped += rx.xdp_tx_err; - tot->rx_dropped = rx.rx_drops + rx.peer_tq_xdp_xmit_err; + tot->rx_dropped = rx.xdp_drops; tot->rx_bytes = rx.xdp_bytes; tot->rx_packets = rx.xdp_packets; rcu_read_lock(); peer = rcu_dereference(priv->peer); if (peer) { - veth_stats_tx(peer, &packets, &bytes); - tot->rx_bytes += bytes; - tot->rx_packets += packets; + tot->rx_dropped += veth_stats_tx(&tx, peer); + tot->rx_bytes += tx.bytes; + tot->rx_packets += tx.packets; veth_stats_rx(&rx, peer); - tot->tx_dropped += rx.peer_tq_xdp_xmit_err; - tot->rx_dropped += rx.xdp_tx_err; tot->tx_bytes += rx.xdp_bytes; tot->tx_packets += rx.xdp_packets; } @@ -406,6 +371,10 @@ static struct sk_buff *veth_build_skb(void *head, int headroom, int len, { struct sk_buff *skb; + if (!buflen) { + buflen = SKB_DATA_ALIGN(headroom + len) + + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); + } skb = build_skb(head, buflen); if (!skb) return NULL; @@ -421,31 +390,25 @@ static int veth_select_rxq(struct net_device *dev) return smp_processor_id() % dev->real_num_rx_queues; } -static struct net_device *veth_peer_dev(struct net_device *dev) -{ - struct veth_priv *priv = netdev_priv(dev); - - /* Callers must be under RCU read side. */ - return rcu_dereference(priv->peer); -} - static int veth_xdp_xmit(struct net_device *dev, int n, - struct xdp_frame **frames, - u32 flags, bool ndo_xmit) + struct xdp_frame **frames, u32 flags) { struct veth_priv *rcv_priv, *priv = netdev_priv(dev); - int i, ret = -ENXIO, drops = 0; struct net_device *rcv; + int i, ret, drops = n; unsigned int max_len; struct veth_rq *rq; - if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) - return -EINVAL; + if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) { + ret = -EINVAL; + goto drop; + } - rcu_read_lock(); rcv = rcu_dereference(priv->peer); - if (unlikely(!rcv)) - goto out; + if (unlikely(!rcv)) { + ret = -ENXIO; + goto drop; + } rcv_priv = netdev_priv(rcv); rq = &rcv_priv->rq[veth_select_rxq(rcv)]; @@ -453,9 +416,12 @@ static int veth_xdp_xmit(struct net_device *dev, int n, * side. This means an XDP program is loaded on the peer and the peer * device is up. */ - if (!rcu_access_pointer(rq->xdp_prog)) - goto out; + if (!rcu_access_pointer(rq->xdp_prog)) { + ret = -ENXIO; + goto drop; + } + drops = 0; max_len = rcv->mtu + rcv->hard_header_len + VLAN_HLEN; spin_lock(&rq->xdp_ring.producer_lock); @@ -474,89 +440,65 @@ static int veth_xdp_xmit(struct net_device *dev, int n, if (flags & XDP_XMIT_FLUSH) __veth_xdp_flush(rq); - ret = n - drops; - if (ndo_xmit) { - u64_stats_update_begin(&rq->stats.syncp); - rq->stats.vs.peer_tq_xdp_xmit += n - drops; - rq->stats.vs.peer_tq_xdp_xmit_err += drops; - u64_stats_update_end(&rq->stats.syncp); - } + if (likely(!drops)) + return n; -out: - rcu_read_unlock(); + ret = n - drops; +drop: + atomic64_add(drops, &priv->dropped); return ret; } -static int veth_ndo_xdp_xmit(struct net_device *dev, int n, - struct xdp_frame **frames, u32 flags) -{ - int err; - - err = veth_xdp_xmit(dev, n, frames, flags, true); - if (err < 0) { - struct veth_priv *priv = netdev_priv(dev); - - atomic64_add(n, &priv->dropped); - } - - return err; -} - -static void veth_xdp_flush_bq(struct veth_rq *rq, struct veth_xdp_tx_bq *bq) +static void veth_xdp_flush_bq(struct net_device *dev, struct veth_xdp_tx_bq *bq) { int sent, i, err = 0; - sent = veth_xdp_xmit(rq->dev, bq->count, bq->q, 0, false); + sent = veth_xdp_xmit(dev, bq->count, bq->q, 0); if (sent < 0) { err = sent; sent = 0; for (i = 0; i < bq->count; i++) xdp_return_frame(bq->q[i]); } - trace_xdp_bulk_tx(rq->dev, sent, bq->count - sent, err); - - u64_stats_update_begin(&rq->stats.syncp); - rq->stats.vs.xdp_tx += sent; - rq->stats.vs.xdp_tx_err += bq->count - sent; - u64_stats_update_end(&rq->stats.syncp); + trace_xdp_bulk_tx(dev, sent, bq->count - sent, err); bq->count = 0; } -static void veth_xdp_flush(struct veth_rq *rq, struct veth_xdp_tx_bq *bq) +static void veth_xdp_flush(struct net_device *dev, struct veth_xdp_tx_bq *bq) { - struct veth_priv *rcv_priv, *priv = netdev_priv(rq->dev); + struct veth_priv *rcv_priv, *priv = netdev_priv(dev); struct net_device *rcv; - struct veth_rq *rcv_rq; + struct veth_rq *rq; rcu_read_lock(); - veth_xdp_flush_bq(rq, bq); + veth_xdp_flush_bq(dev, bq); rcv = rcu_dereference(priv->peer); if (unlikely(!rcv)) goto out; rcv_priv = netdev_priv(rcv); - rcv_rq = &rcv_priv->rq[veth_select_rxq(rcv)]; + rq = &rcv_priv->rq[veth_select_rxq(rcv)]; /* xdp_ring is initialized on receive side? */ - if (unlikely(!rcu_access_pointer(rcv_rq->xdp_prog))) + if (unlikely(!rcu_access_pointer(rq->xdp_prog))) goto out; - __veth_xdp_flush(rcv_rq); + __veth_xdp_flush(rq); out: rcu_read_unlock(); } -static int veth_xdp_tx(struct veth_rq *rq, struct xdp_buff *xdp, +static int veth_xdp_tx(struct net_device *dev, struct xdp_buff *xdp, struct veth_xdp_tx_bq *bq) { - struct xdp_frame *frame = xdp_convert_buff_to_frame(xdp); + struct xdp_frame *frame = convert_to_xdp_frame(xdp); if (unlikely(!frame)) return -EOVERFLOW; if (unlikely(bq->count == VETH_XDP_TX_BULK_SIZE)) - veth_xdp_flush_bq(rq, bq); + veth_xdp_flush_bq(dev, bq); bq->q[bq->count++] = frame; @@ -565,8 +507,8 @@ static int veth_xdp_tx(struct veth_rq *rq, struct xdp_buff *xdp, static struct sk_buff *veth_xdp_rcv_one(struct veth_rq *rq, struct xdp_frame *frame, - struct veth_xdp_tx_bq *bq, - struct veth_stats *stats) + unsigned int *xdp_xmit, + struct veth_xdp_tx_bq *bq) { void *hard_start = frame->data - frame->headroom; int len = frame->len, delta = 0; @@ -584,7 +526,10 @@ static struct sk_buff *veth_xdp_rcv_one(struct veth_rq *rq, struct xdp_buff xdp; u32 act; - xdp_convert_frame_to_buff(frame, &xdp); + xdp.data_hard_start = hard_start; + xdp.data = frame->data; + xdp.data_end = frame->data + frame->len; + xdp.data_meta = frame->data - frame->metasize; xdp.rxq = &rq->xdp_rxq; act = bpf_prog_run_xdp(xdp_prog, &xdp); @@ -597,13 +542,12 @@ static struct sk_buff *veth_xdp_rcv_one(struct veth_rq *rq, case XDP_TX: orig_frame = *frame; xdp.rxq->mem = frame->mem; - if (unlikely(veth_xdp_tx(rq, &xdp, bq) < 0)) { + if (unlikely(veth_xdp_tx(rq->dev, &xdp, bq) < 0)) { trace_xdp_exception(rq->dev, xdp_prog, act); frame = &orig_frame; - stats->rx_drops++; goto err_xdp; } - stats->xdp_tx++; + *xdp_xmit |= VETH_XDP_TX; rcu_read_unlock(); goto xdp_xmit; case XDP_REDIRECT: @@ -611,10 +555,9 @@ static struct sk_buff *veth_xdp_rcv_one(struct veth_rq *rq, xdp.rxq->mem = frame->mem; if (xdp_do_redirect(rq->dev, &xdp, xdp_prog)) { frame = &orig_frame; - stats->rx_drops++; goto err_xdp; } - stats->xdp_redirect++; + *xdp_xmit |= VETH_XDP_REDIR; rcu_read_unlock(); goto xdp_xmit; default: @@ -624,17 +567,15 @@ static struct sk_buff *veth_xdp_rcv_one(struct veth_rq *rq, trace_xdp_exception(rq->dev, xdp_prog, act); /* fall through */ case XDP_DROP: - stats->xdp_drops++; goto err_xdp; } } rcu_read_unlock(); headroom = sizeof(struct xdp_frame) + frame->headroom - delta; - skb = veth_build_skb(hard_start, headroom, len, frame->frame_sz); + skb = veth_build_skb(hard_start, headroom, len, 0); if (!skb) { xdp_return_frame(frame); - stats->rx_drops++; goto err; } @@ -650,10 +591,9 @@ xdp_xmit: return NULL; } -static struct sk_buff *veth_xdp_rcv_skb(struct veth_rq *rq, - struct sk_buff *skb, - struct veth_xdp_tx_bq *bq, - struct veth_stats *stats) +static struct sk_buff *veth_xdp_rcv_skb(struct veth_rq *rq, struct sk_buff *skb, + unsigned int *xdp_xmit, + struct veth_xdp_tx_bq *bq) { u32 pktlen, headroom, act, metalen; void *orig_data, *orig_data_end; @@ -697,8 +637,9 @@ static struct sk_buff *veth_xdp_rcv_skb(struct veth_rq *rq, goto drop; } - nskb = veth_build_skb(head, VETH_XDP_HEADROOM + mac_len, - skb->len, PAGE_SIZE); + nskb = veth_build_skb(head, + VETH_XDP_HEADROOM + mac_len, skb->len, + PAGE_SIZE); if (!nskb) { page_frag_free(head); goto drop; @@ -716,11 +657,6 @@ static struct sk_buff *veth_xdp_rcv_skb(struct veth_rq *rq, xdp.data_end = xdp.data + pktlen; xdp.data_meta = xdp.data; xdp.rxq = &rq->xdp_rxq; - - /* SKB "head" area always have tailroom for skb_shared_info */ - xdp.frame_sz = (void *)skb_end_pointer(skb) - xdp.data_hard_start; - xdp.frame_sz += SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); - orig_data = xdp.data; orig_data_end = xdp.data_end; @@ -733,23 +669,20 @@ static struct sk_buff *veth_xdp_rcv_skb(struct veth_rq *rq, get_page(virt_to_page(xdp.data)); consume_skb(skb); xdp.rxq->mem = rq->xdp_mem; - if (unlikely(veth_xdp_tx(rq, &xdp, bq) < 0)) { + if (unlikely(veth_xdp_tx(rq->dev, &xdp, bq) < 0)) { trace_xdp_exception(rq->dev, xdp_prog, act); - stats->rx_drops++; goto err_xdp; } - stats->xdp_tx++; + *xdp_xmit |= VETH_XDP_TX; rcu_read_unlock(); goto xdp_xmit; case XDP_REDIRECT: get_page(virt_to_page(xdp.data)); consume_skb(skb); xdp.rxq->mem = rq->xdp_mem; - if (xdp_do_redirect(rq->dev, &xdp, xdp_prog)) { - stats->rx_drops++; + if (xdp_do_redirect(rq->dev, &xdp, xdp_prog)) goto err_xdp; - } - stats->xdp_redirect++; + *xdp_xmit |= VETH_XDP_REDIR; rcu_read_unlock(); goto xdp_xmit; default: @@ -759,12 +692,10 @@ static struct sk_buff *veth_xdp_rcv_skb(struct veth_rq *rq, trace_xdp_exception(rq->dev, xdp_prog, act); /* fall through */ case XDP_DROP: - stats->xdp_drops++; - goto xdp_drop; + goto drop; } rcu_read_unlock(); - /* check if bpf_xdp_adjust_head was used */ delta = orig_data - xdp.data; off = mac_len + delta; if (off > 0) @@ -772,11 +703,9 @@ static struct sk_buff *veth_xdp_rcv_skb(struct veth_rq *rq, else if (off < 0) __skb_pull(skb, -off); skb->mac_header -= delta; - - /* check if bpf_xdp_adjust_tail was used */ off = xdp.data_end - orig_data_end; if (off != 0) - __skb_put(skb, off); /* positive on grow, negative on shrink */ + __skb_put(skb, off); skb->protocol = eth_type_trans(skb, rq->dev); metalen = xdp.data - xdp.data_meta; @@ -785,8 +714,6 @@ static struct sk_buff *veth_xdp_rcv_skb(struct veth_rq *rq, out: return skb; drop: - stats->rx_drops++; -xdp_drop: rcu_read_unlock(); kfree_skb(skb); return NULL; @@ -797,14 +724,14 @@ xdp_xmit: return NULL; } -static int veth_xdp_rcv(struct veth_rq *rq, int budget, - struct veth_xdp_tx_bq *bq, - struct veth_stats *stats) +static int veth_xdp_rcv(struct veth_rq *rq, int budget, unsigned int *xdp_xmit, + struct veth_xdp_tx_bq *bq) { - int i, done = 0; + int i, done = 0, drops = 0, bytes = 0; for (i = 0; i < budget; i++) { void *ptr = __ptr_ring_consume(&rq->xdp_ring); + unsigned int xdp_xmit_one = 0; struct sk_buff *skb; if (!ptr) @@ -813,26 +740,27 @@ static int veth_xdp_rcv(struct veth_rq *rq, int budget, if (veth_is_xdp_frame(ptr)) { struct xdp_frame *frame = veth_ptr_to_xdp(ptr); - stats->xdp_bytes += frame->len; - skb = veth_xdp_rcv_one(rq, frame, bq, stats); + bytes += frame->len; + skb = veth_xdp_rcv_one(rq, frame, &xdp_xmit_one, bq); } else { skb = ptr; - stats->xdp_bytes += skb->len; - skb = veth_xdp_rcv_skb(rq, skb, bq, stats); + bytes += skb->len; + skb = veth_xdp_rcv_skb(rq, skb, &xdp_xmit_one, bq); } + *xdp_xmit |= xdp_xmit_one; if (skb) napi_gro_receive(&rq->xdp_napi, skb); + else if (!xdp_xmit_one) + drops++; done++; } u64_stats_update_begin(&rq->stats.syncp); - rq->stats.vs.xdp_redirect += stats->xdp_redirect; - rq->stats.vs.xdp_bytes += stats->xdp_bytes; - rq->stats.vs.xdp_drops += stats->xdp_drops; - rq->stats.vs.rx_drops += stats->rx_drops; - rq->stats.vs.xdp_packets += done; + rq->stats.xdp_packets += done; + rq->stats.xdp_bytes += bytes; + rq->stats.xdp_drops += drops; u64_stats_update_end(&rq->stats.syncp); return done; @@ -842,14 +770,14 @@ static int veth_poll(struct napi_struct *napi, int budget) { struct veth_rq *rq = container_of(napi, struct veth_rq, xdp_napi); - struct veth_stats stats = {}; + unsigned int xdp_xmit = 0; struct veth_xdp_tx_bq bq; int done; bq.count = 0; xdp_set_return_frame_no_direct(); - done = veth_xdp_rcv(rq, budget, &bq, &stats); + done = veth_xdp_rcv(rq, budget, &xdp_xmit, &bq); if (done < budget && napi_complete_done(napi, done)) { /* Write rx_notify_masked before reading ptr_ring */ @@ -862,10 +790,10 @@ static int veth_poll(struct napi_struct *napi, int budget) } } - if (stats.xdp_tx > 0) - veth_xdp_flush(rq, &bq); - if (stats.xdp_redirect > 0) - xdp_do_flush(); + if (xdp_xmit & VETH_XDP_TX) + veth_xdp_flush(rq->dev, &bq); + if (xdp_xmit & VETH_XDP_REDIR) + xdp_do_flush_map(); xdp_clear_return_frame_no_direct(); return done; @@ -1250,8 +1178,7 @@ static const struct net_device_ops veth_netdev_ops = { .ndo_features_check = passthru_features_check, .ndo_set_rx_headroom = veth_set_rx_headroom, .ndo_bpf = veth_xdp, - .ndo_xdp_xmit = veth_ndo_xdp_xmit, - .ndo_get_peer_dev = veth_peer_dev, + .ndo_xdp_xmit = veth_xdp_xmit, }; #define VETH_FEATURES (NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_HW_CSUM | \ diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index d1dbcffa2727..f02a67a9dabb 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -804,7 +804,7 @@ static struct sk_buff *receive_small(struct net_device *dev, break; case XDP_TX: stats->xdp_tx++; - xdpf = xdp_convert_buff_to_frame(&xdp); + xdpf = convert_to_xdp_frame(&xdp); if (unlikely(!xdpf)) goto err_xdp; err = virtnet_xdp_xmit(dev, 1, &xdpf, 0); @@ -992,7 +992,7 @@ static struct sk_buff *receive_mergeable(struct net_device *dev, break; case XDP_TX: stats->xdp_tx++; - xdpf = xdp_convert_buff_to_frame(&xdp); + xdpf = convert_to_xdp_frame(&xdp); if (unlikely(!xdpf)) goto err_xdp; err = virtnet_xdp_xmit(dev, 1, &xdpf, 0); @@ -1552,7 +1552,7 @@ static int virtnet_poll(struct napi_struct *napi, int budget) virtqueue_napi_complete(napi, rq->vq, received); if (xdp_xmit & VIRTIO_XDP_REDIR) - xdp_do_flush(); + xdp_do_flush_map(); if (xdp_xmit & VIRTIO_XDP_TX) { sq = virtnet_xdp_get_sq(vi); @@ -2580,8 +2580,11 @@ static int virtnet_xdp_set(struct net_device *dev, struct bpf_prog *prog, if (!prog && !old_prog) return 0; - if (prog) - bpf_prog_add(prog, vi->max_queue_pairs - 1); + if (prog) { + prog = bpf_prog_add(prog, vi->max_queue_pairs - 1); + if (IS_ERR(prog)) + return PTR_ERR(prog); + } /* Make sure NAPI is not using any XDP TX queues for RX. */ if (netif_running(dev)) { diff --git a/drivers/net/vxlan.c b/drivers/net/vxlan.c index e183393076b8..18844bac9375 100644 --- a/drivers/net/vxlan.c +++ b/drivers/net/vxlan.c @@ -4263,12 +4263,10 @@ static int vxlan_netdevice_event(struct notifier_block *unused, struct vxlan_net *vn = net_generic(dev_net(dev), vxlan_net_id); if (event == NETDEV_UNREGISTER) { - if (!dev->udp_tunnel_nic_info) - vxlan_offload_rx_ports(dev, false); + vxlan_offload_rx_ports(dev, false); vxlan_handle_lowerdev_unregister(vn, dev); } else if (event == NETDEV_REGISTER) { - if (!dev->udp_tunnel_nic_info) - vxlan_offload_rx_ports(dev, true); + vxlan_offload_rx_ports(dev, true); } else if (event == NETDEV_UDP_TUNNEL_PUSH_INFO || event == NETDEV_UDP_TUNNEL_DROP_INFO) { vxlan_offload_rx_ports(dev, event == NETDEV_UDP_TUNNEL_PUSH_INFO); diff --git a/drivers/net/wireless/ath/ath10k/wmi.c b/drivers/net/wireless/ath/ath10k/wmi.c index a445a192b30f..ed6316c41cb7 100644 --- a/drivers/net/wireless/ath/ath10k/wmi.c +++ b/drivers/net/wireless/ath/ath10k/wmi.c @@ -1894,7 +1894,6 @@ int ath10k_wmi_cmd_send(struct ath10k *ar, struct sk_buff *skb, u32 cmd_id) if (cmd_id == WMI_CMD_UNSUPPORTED) { ath10k_warn(ar, "wmi command %d is not supported by firmware\n", cmd_id); - dev_kfree_skb_any(skb); return ret; } diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c index 53e40ca0b971..07ba7a5113a8 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c @@ -4963,7 +4963,8 @@ brcmf_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev, brcmf_dbg(TRACE, "Action frame, cookie=%lld, len=%d, freq=%d\n", *cookie, le16_to_cpu(action_frame->len), freq); - ack = brcmf_p2p_send_action_frame(vif->ifp, af_params); + ack = brcmf_p2p_send_action_frame(cfg, cfg_to_ndev(cfg), + af_params); cfg80211_mgmt_tx_status(wdev, *cookie, buf, len, ack, GFP_KERNEL); diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.c index 1b9011a90f1b..1f5deea5a288 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.c @@ -1477,7 +1477,6 @@ int brcmf_p2p_notify_action_tx_complete(struct brcmf_if *ifp, /** * brcmf_p2p_tx_action_frame() - send action frame over fil. * - * @ifp: interface to transmit on. * @p2p: p2p info struct for vif. * @af_params: action frame data/info. * @@ -1487,11 +1486,11 @@ int brcmf_p2p_notify_action_tx_complete(struct brcmf_if *ifp, * The WLC_E_ACTION_FRAME_COMPLETE event will be received when the action * frame is transmitted. */ -static s32 brcmf_p2p_tx_action_frame(struct brcmf_if *ifp, - struct brcmf_p2p_info *p2p, +static s32 brcmf_p2p_tx_action_frame(struct brcmf_p2p_info *p2p, struct brcmf_fil_af_params_le *af_params) { struct brcmf_pub *drvr = p2p->cfg->pub; + struct brcmf_cfg80211_vif *vif; s32 err = 0; s32 timeout = 0; @@ -1501,7 +1500,8 @@ static s32 brcmf_p2p_tx_action_frame(struct brcmf_if *ifp, clear_bit(BRCMF_P2P_STATUS_ACTION_TX_COMPLETED, &p2p->status); clear_bit(BRCMF_P2P_STATUS_ACTION_TX_NOACK, &p2p->status); - err = brcmf_fil_bsscfg_data_set(ifp, "actframe", af_params, + vif = p2p->bss_idx[P2PAPI_BSSCFG_DEVICE].vif; + err = brcmf_fil_bsscfg_data_set(vif->ifp, "actframe", af_params, sizeof(*af_params)); if (err) { bphy_err(drvr, " sending action frame has failed\n"); @@ -1643,14 +1643,16 @@ static s32 brcmf_p2p_pub_af_tx(struct brcmf_cfg80211_info *cfg, /** * brcmf_p2p_send_action_frame() - send action frame . * - * @ifp: interface to transmit on. + * @cfg: driver private data for cfg80211 interface. + * @ndev: net device to transmit on. * @af_params: configuration data for action frame. */ -bool brcmf_p2p_send_action_frame(struct brcmf_if *ifp, +bool brcmf_p2p_send_action_frame(struct brcmf_cfg80211_info *cfg, + struct net_device *ndev, struct brcmf_fil_af_params_le *af_params) { - struct brcmf_cfg80211_info *cfg = ifp->drvr->config; struct brcmf_p2p_info *p2p = &cfg->p2p; + struct brcmf_if *ifp = netdev_priv(ndev); struct brcmf_fil_action_frame_le *action_frame; struct brcmf_config_af_params config_af_params; struct afx_hdl *afx_hdl = &p2p->afx_hdl; @@ -1777,7 +1779,7 @@ bool brcmf_p2p_send_action_frame(struct brcmf_if *ifp, tx_retry = 0; while (!p2p->block_gon_req_tx && (ack == false) && (tx_retry < P2P_AF_TX_MAX_RETRY)) { - ack = !brcmf_p2p_tx_action_frame(ifp, p2p, af_params); + ack = !brcmf_p2p_tx_action_frame(p2p, af_params); tx_retry++; } if (ack == false) { @@ -2135,6 +2137,7 @@ static struct wireless_dev *brcmf_p2p_create_p2pdev(struct brcmf_p2p_info *p2p, WARN_ON(p2p_ifp->bsscfgidx != bsscfgidx); + init_completion(&p2p->send_af_done); INIT_WORK(&p2p->afx_hdl.afx_work, brcmf_p2p_afx_handler); init_completion(&p2p->afx_hdl.act_frm_scan); init_completion(&p2p->wait_next_af); @@ -2387,8 +2390,6 @@ s32 brcmf_p2p_attach(struct brcmf_cfg80211_info *cfg, bool p2pdev_forced) pri_ifp = brcmf_get_ifp(cfg->pub, 0); p2p->bss_idx[P2PAPI_BSSCFG_PRIMARY].vif = pri_ifp->vif; - init_completion(&p2p->send_af_done); - if (p2pdev_forced) { err_ptr = brcmf_p2p_create_p2pdev(p2p, NULL, NULL); if (IS_ERR(err_ptr)) { diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.h b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.h index 2472b0ccb8a4..64ab9b6a677d 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.h +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/p2p.h @@ -165,7 +165,8 @@ int brcmf_p2p_notify_action_frame_rx(struct brcmf_if *ifp, int brcmf_p2p_notify_action_tx_complete(struct brcmf_if *ifp, const struct brcmf_event_msg *e, void *data); -bool brcmf_p2p_send_action_frame(struct brcmf_if *ifp, +bool brcmf_p2p_send_action_frame(struct brcmf_cfg80211_info *cfg, + struct net_device *ndev, struct brcmf_fil_af_params_le *af_params); bool brcmf_p2p_scan_finding_common_channel(struct brcmf_cfg80211_info *cfg, struct brcmf_bss_info_le *bi); diff --git a/drivers/net/wireless/cnss/Makefile b/drivers/net/wireless/cnss/Makefile index 567ef214d7dd..c1ca4c3821e6 100644 --- a/drivers/net/wireless/cnss/Makefile +++ b/drivers/net/wireless/cnss/Makefile @@ -3,9 +3,7 @@ # Makefile for CNSS platform driver # -obj-$(CONFIG_CNSS) += cnss.o - -cnss-$(CONFIG_CNSS_PCI) += cnss_pci.o -cnss-$(CONFIG_CNSS_SDIO) += cnss_sdio.o -cnss-y += cnss_common.o -obj-$(CONFIG_CNSS_LOGGER) += logger/ +obj-$(CONFIG_CNSS_PCI) += cnss_pci.o +obj-$(CONFIG_CNSS_SDIO) += cnss_sdio.o +obj-$(CONFIG_CNSS) += cnss_common.o +obj-$(CONFIG_CNSS_LOGGER) += logger/ diff --git a/drivers/net/wireless/cnss/cnss_common.c b/drivers/net/wireless/cnss/cnss_common.c index 534f81f320a6..dbdd13e0abca 100644 --- a/drivers/net/wireless/cnss/cnss_common.c +++ b/drivers/net/wireless/cnss/cnss_common.c @@ -242,21 +242,13 @@ int cnss_set_cpus_allowed_ptr(struct task_struct *task, ulong cpu) } EXPORT_SYMBOL(cnss_set_cpus_allowed_ptr); -#define ENTRIES_COUNT 32 +/* wlan prop driver cannot invoke show_stack + * function directly, so to invoke this function it + * call wcnss_dump_stack function + */ void cnss_dump_stack(struct task_struct *task) { - const int cnss_spaces = 4; - unsigned long cnss_entries[ENTRIES_COUNT] = {0}; - struct stack_trace cnss_trace = { - .nr_entries = 0, - .skip = 0, - .entries = &cnss_entries[0], - .max_entries = ENTRIES_COUNT, - }; - - save_stack_trace_tsk(task, &cnss_trace); - stack_trace_print(cnss_entries, cnss_trace.nr_entries, - cnss_spaces); + show_stack(task, NULL); } EXPORT_SYMBOL(cnss_dump_stack); diff --git a/drivers/net/wireless/cnss/cnss_pci.c b/drivers/net/wireless/cnss/cnss_pci.c index 623149274fa3..9d588b5ed6d8 100644 --- a/drivers/net/wireless/cnss/cnss_pci.c +++ b/drivers/net/wireless/cnss/cnss_pci.c @@ -31,8 +31,6 @@ #include #include #include -#include -#include #include #include #include @@ -1620,43 +1618,6 @@ static void cnss_pcie_reset_platform_ops(struct device *dev) dev->platform_data = NULL; } -#if IS_ENABLED(CONFIG_ARCH_QCOM) -/** - * cnss_pci_of_reserved_mem_device_init() - Assign reserved memory region - * to given PCI device - * @pdev: context pointer of pdev - * - * This function shall call corresponding of_reserved_mem_device* API to - * assign reserved memory region to PCI device based on where the memory is - * defined and attached to (platform device of_node or PCI device of_node) - * in device tree. - * - * Return: 0 for success, negative value for error - */ -static int cnss_pci_of_reserved_mem_device_init(struct pci_dev *pdev) -{ - struct device *dev_pci = &pdev->dev; - int ret; - - /* Use of_reserved_mem_device_init_by_idx() if reserved memory is - * attached to platform device of_node. - */ - ret = of_reserved_mem_device_init(dev_pci); - if (ret) - pr_err("Failed to init reserved mem device, err = %d\n", - ret); - if (dev_pci->cma_area) - pr_debug("CMA area is %s\n", cma_get_name(dev_pci->cma_area)); - - return ret; -} -#else -static int cnss_pci_of_reserved_mem_device_init(struct pci_dev *pdev) -{ - return 0; -} -#endif - static int cnss_wlan_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { @@ -1673,7 +1634,6 @@ static int cnss_wlan_pci_probe(struct pci_dev *pdev, atomic_set(&penv->fw_available, 0); penv->device_id = pdev->device; - cnss_pci_of_reserved_mem_device_init(pdev); if (penv->smmu_iova_len) { ret = cnss_smmu_init(&pdev->dev); if (ret) { diff --git a/drivers/net/wireless/marvell/mwifiex/cfg80211.c b/drivers/net/wireless/marvell/mwifiex/cfg80211.c index 9f9826b94ad4..40e10f6e3dbf 100644 --- a/drivers/net/wireless/marvell/mwifiex/cfg80211.c +++ b/drivers/net/wireless/marvell/mwifiex/cfg80211.c @@ -667,9 +667,10 @@ static void mwifiex_reg_notifier(struct wiphy *wiphy, return; } - /* Don't send same regdom info to firmware */ - if (strncmp(request->alpha2, adapter->country_code, - sizeof(request->alpha2)) != 0) { + /* Don't send world or same regdom info to firmware */ + if (strncmp(request->alpha2, "00", 2) && + strncmp(request->alpha2, adapter->country_code, + sizeof(request->alpha2))) { memcpy(adapter->country_code, request->alpha2, sizeof(request->alpha2)); mwifiex_send_domain_info_cmd_fw(wiphy); diff --git a/drivers/net/wireless/mediatek/mt76/mt7603/soc.c b/drivers/net/wireless/mediatek/mt76/mt7603/soc.c index 8c3603f11389..68efb300c0d8 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7603/soc.c +++ b/drivers/net/wireless/mediatek/mt76/mt7603/soc.c @@ -48,7 +48,7 @@ mt76_wmac_probe(struct platform_device *pdev) return 0; error: - mt76_free_device(mdev); + ieee80211_free_hw(mt76_hw(dev)); return ret; } diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c index 300f90a11879..ab3e4aebad39 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c @@ -297,6 +297,7 @@ static const struct usb_device_id rtl8192c_usb_ids[] = { {RTL_USB_DEVICE(0x050d, 0x1102, rtl92cu_hal_cfg)}, /*Belkin - Edimax*/ {RTL_USB_DEVICE(0x050d, 0x11f2, rtl92cu_hal_cfg)}, /*Belkin - ISY*/ {RTL_USB_DEVICE(0x06f8, 0xe033, rtl92cu_hal_cfg)}, /*Hercules - Edimax*/ + {RTL_USB_DEVICE(0x07b8, 0x8188, rtl92cu_hal_cfg)}, /*Abocom - Abocom*/ {RTL_USB_DEVICE(0x07b8, 0x8189, rtl92cu_hal_cfg)}, /*Funai - Abocom*/ {RTL_USB_DEVICE(0x0846, 0x9041, rtl92cu_hal_cfg)}, /*NetGear WNA1000M*/ {RTL_USB_DEVICE(0x0846, 0x9043, rtl92cu_hal_cfg)}, /*NG WNA1000Mv2*/ diff --git a/drivers/nvdimm/bus.c b/drivers/nvdimm/bus.c index 4600f80fb250..56f189c3129a 100644 --- a/drivers/nvdimm/bus.c +++ b/drivers/nvdimm/bus.c @@ -1229,7 +1229,7 @@ static const struct file_operations nvdimm_bus_fops = { .owner = THIS_MODULE, .open = nd_open, .unlocked_ioctl = bus_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = bus_ioctl, .llseek = noop_llseek, }; @@ -1237,7 +1237,7 @@ static const struct file_operations nvdimm_fops = { .owner = THIS_MODULE, .open = nd_open, .unlocked_ioctl = dimm_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = dimm_ioctl, .llseek = noop_llseek, }; diff --git a/drivers/nvdimm/pmem.c b/drivers/nvdimm/pmem.c index 0f94658af4e7..7e65306b2bf2 100644 --- a/drivers/nvdimm/pmem.c +++ b/drivers/nvdimm/pmem.c @@ -137,25 +137,9 @@ static blk_status_t read_pmem(struct page *page, unsigned int off, return BLK_STS_OK; } -static blk_status_t pmem_do_read(struct pmem_device *pmem, - struct page *page, unsigned int page_off, - sector_t sector, unsigned int len) -{ - blk_status_t rc; - phys_addr_t pmem_off = sector * 512 + pmem->data_offset; - void *pmem_addr = pmem->virt_addr + pmem_off; - - if (unlikely(is_bad_pmem(&pmem->bb, sector, len))) - return BLK_STS_IOERR; - - rc = read_pmem(page, page_off, pmem_addr, len); - flush_dcache_page(page); - return rc; -} - -static blk_status_t pmem_do_write(struct pmem_device *pmem, - struct page *page, unsigned int page_off, - sector_t sector, unsigned int len) +static blk_status_t pmem_do_bvec(struct pmem_device *pmem, struct page *page, + unsigned int len, unsigned int off, unsigned int op, + sector_t sector) { blk_status_t rc = BLK_STS_OK; bool bad_pmem = false; @@ -165,25 +149,34 @@ static blk_status_t pmem_do_write(struct pmem_device *pmem, if (unlikely(is_bad_pmem(&pmem->bb, sector, len))) bad_pmem = true; - /* - * Note that we write the data both before and after - * clearing poison. The write before clear poison - * handles situations where the latest written data is - * preserved and the clear poison operation simply marks - * the address range as valid without changing the data. - * In this case application software can assume that an - * interrupted write will either return the new good - * data or an error. - * - * However, if pmem_clear_poison() leaves the data in an - * indeterminate state we need to perform the write - * after clear poison. - */ - flush_dcache_page(page); - write_pmem(pmem_addr, page, page_off, len); - if (unlikely(bad_pmem)) { - rc = pmem_clear_poison(pmem, pmem_off, len); - write_pmem(pmem_addr, page, page_off, len); + if (!op_is_write(op)) { + if (unlikely(bad_pmem)) + rc = BLK_STS_IOERR; + else { + rc = read_pmem(page, off, pmem_addr, len); + flush_dcache_page(page); + } + } else { + /* + * Note that we write the data both before and after + * clearing poison. The write before clear poison + * handles situations where the latest written data is + * preserved and the clear poison operation simply marks + * the address range as valid without changing the data. + * In this case application software can assume that an + * interrupted write will either return the new good + * data or an error. + * + * However, if pmem_clear_poison() leaves the data in an + * indeterminate state we need to perform the write + * after clear poison. + */ + flush_dcache_page(page); + write_pmem(pmem_addr, page, off, len); + if (unlikely(bad_pmem)) { + rc = pmem_clear_poison(pmem, pmem_off, len); + write_pmem(pmem_addr, page, off, len); + } } return rc; @@ -205,12 +198,8 @@ static blk_qc_t pmem_make_request(struct request_queue *q, struct bio *bio) do_acct = nd_iostat_start(bio, &start); bio_for_each_segment(bvec, bio, iter) { - if (op_is_write(bio_op(bio))) - rc = pmem_do_write(pmem, bvec.bv_page, bvec.bv_offset, - iter.bi_sector, bvec.bv_len); - else - rc = pmem_do_read(pmem, bvec.bv_page, bvec.bv_offset, - iter.bi_sector, bvec.bv_len); + rc = pmem_do_bvec(pmem, bvec.bv_page, bvec.bv_len, + bvec.bv_offset, bio_op(bio), iter.bi_sector); if (rc) { bio->bi_status = rc; break; @@ -235,12 +224,9 @@ static int pmem_rw_page(struct block_device *bdev, sector_t sector, struct pmem_device *pmem = bdev->bd_queue->queuedata; blk_status_t rc; - if (op_is_write(op)) - rc = pmem_do_write(pmem, page, 0, sector, - hpage_nr_pages(page) * PAGE_SIZE); - else - rc = pmem_do_read(pmem, page, 0, sector, - hpage_nr_pages(page) * PAGE_SIZE); + rc = pmem_do_bvec(pmem, page, hpage_nr_pages(page) * PAGE_SIZE, + 0, op, sector); + /* * The ->rw_page interface is subtle and tricky. The core * retries on any error, so we can only invoke page_endio() in @@ -283,16 +269,6 @@ static const struct block_device_operations pmem_fops = { .revalidate_disk = nvdimm_revalidate_disk, }; -static int pmem_dax_zero_page_range(struct dax_device *dax_dev, pgoff_t pgoff, - size_t nr_pages) -{ - struct pmem_device *pmem = dax_get_private(dax_dev); - - return blk_status_to_errno(pmem_do_write(pmem, ZERO_PAGE(0), 0, - PFN_PHYS(pgoff) >> SECTOR_SHIFT, - PAGE_SIZE)); -} - static long pmem_dax_direct_access(struct dax_device *dax_dev, pgoff_t pgoff, long nr_pages, void **kaddr, pfn_t *pfn) { @@ -324,7 +300,6 @@ static const struct dax_operations pmem_dax_ops = { .dax_supported = generic_fsdax_supported, .copy_from_iter = pmem_copy_from_iter, .copy_to_iter = pmem_copy_to_iter, - .zero_page_range = pmem_dax_zero_page_range, }; static const struct attribute_group *pmem_attribute_groups[] = { diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c index d1a369c619dc..94c8ef4a54d3 100644 --- a/drivers/nvme/host/core.c +++ b/drivers/nvme/host/core.c @@ -3062,7 +3062,7 @@ static const struct file_operations nvme_dev_fops = { .open = nvme_dev_open, .release = nvme_dev_release, .unlocked_ioctl = nvme_dev_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = nvme_dev_ioctl, }; static ssize_t nvme_sysfs_reset(struct device *dev, diff --git a/drivers/oprofile/buffer_sync.c b/drivers/oprofile/buffer_sync.c index 4f61b1b45e0d..ac27f3d3fbb4 100644 --- a/drivers/oprofile/buffer_sync.c +++ b/drivers/oprofile/buffer_sync.c @@ -116,7 +116,7 @@ module_load_notify(struct notifier_block *self, unsigned long val, void *data) { #ifdef CONFIG_MODULES if (val != MODULE_STATE_COMING) - return NOTIFY_DONE; + return 0; /* FIXME: should we process all CPU buffers ? */ mutex_lock(&buffer_mutex); @@ -124,7 +124,7 @@ module_load_notify(struct notifier_block *self, unsigned long val, void *data) add_event_entry(MODULE_LOADED_CODE); mutex_unlock(&buffer_mutex); #endif - return NOTIFY_OK; + return 0; } diff --git a/drivers/parport/procfs.c b/drivers/parport/procfs.c index 180376c09cb4..c193d657f0ab 100644 --- a/drivers/parport/procfs.c +++ b/drivers/parport/procfs.c @@ -34,7 +34,7 @@ #define PARPORT_MAX_SPINTIME_VALUE 1000 static int do_active_device(struct ctl_table *table, int write, - void *result, size_t *lenp, loff_t *ppos) + void __user *result, size_t *lenp, loff_t *ppos) { struct parport *port = (struct parport *)table->extra1; char buffer[256]; @@ -65,13 +65,13 @@ static int do_active_device(struct ctl_table *table, int write, *lenp = len; *ppos += len; - memcpy(result, buffer, len); - return 0; + + return copy_to_user(result, buffer, len) ? -EFAULT : 0; } #ifdef CONFIG_PARPORT_1284 static int do_autoprobe(struct ctl_table *table, int write, - void *result, size_t *lenp, loff_t *ppos) + void __user *result, size_t *lenp, loff_t *ppos) { struct parport_device_info *info = table->extra2; const char *str; @@ -108,13 +108,13 @@ static int do_autoprobe(struct ctl_table *table, int write, *ppos += len; - memcpy(result, buffer, len); - return 0; + return copy_to_user (result, buffer, len) ? -EFAULT : 0; } #endif /* IEEE1284.3 support. */ static int do_hardware_base_addr(struct ctl_table *table, int write, - void *result, size_t *lenp, loff_t *ppos) + void __user *result, + size_t *lenp, loff_t *ppos) { struct parport *port = (struct parport *)table->extra1; char buffer[64]; @@ -136,12 +136,13 @@ static int do_hardware_base_addr(struct ctl_table *table, int write, *lenp = len; *ppos += len; - memcpy(result, buffer, len); - return 0; + + return copy_to_user(result, buffer, len) ? -EFAULT : 0; } static int do_hardware_irq(struct ctl_table *table, int write, - void *result, size_t *lenp, loff_t *ppos) + void __user *result, + size_t *lenp, loff_t *ppos) { struct parport *port = (struct parport *)table->extra1; char buffer[20]; @@ -163,12 +164,13 @@ static int do_hardware_irq(struct ctl_table *table, int write, *lenp = len; *ppos += len; - memcpy(result, buffer, len); - return 0; + + return copy_to_user(result, buffer, len) ? -EFAULT : 0; } static int do_hardware_dma(struct ctl_table *table, int write, - void *result, size_t *lenp, loff_t *ppos) + void __user *result, + size_t *lenp, loff_t *ppos) { struct parport *port = (struct parport *)table->extra1; char buffer[20]; @@ -190,12 +192,13 @@ static int do_hardware_dma(struct ctl_table *table, int write, *lenp = len; *ppos += len; - memcpy(result, buffer, len); - return 0; + + return copy_to_user(result, buffer, len) ? -EFAULT : 0; } static int do_hardware_modes(struct ctl_table *table, int write, - void *result, size_t *lenp, loff_t *ppos) + void __user *result, + size_t *lenp, loff_t *ppos) { struct parport *port = (struct parport *)table->extra1; char buffer[40]; @@ -232,8 +235,8 @@ do { \ *lenp = len; *ppos += len; - memcpy(result, buffer, len); - return 0; + + return copy_to_user(result, buffer, len) ? -EFAULT : 0; } #define PARPORT_PORT_DIR(CHILD) { .procname = NULL, .mode = 0555, .child = CHILD } diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 0a12fbcd29df..b28d3c4205fe 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -1294,8 +1294,8 @@ static int ks_pcie_probe(struct platform_device *pdev) return irq; } - ret = devm_request_irq(dev, irq, ks_pcie_err_irq_handler, IRQF_SHARED, - "ks-pcie-error-irq", ks_pcie); + ret = request_irq(irq, ks_pcie_err_irq_handler, IRQF_SHARED, + "ks-pcie-error-irq", ks_pcie); if (ret < 0) { dev_err(dev, "failed to request error IRQ %d\n", irq); diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 9e3588d568ce..74c0ddd43381 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -1394,7 +1394,7 @@ static int tegra_pcie_port_get_phys(struct tegra_pcie_port *port) unsigned int i; int err; - port->phys = devm_kcalloc(dev, port->lanes, sizeof(phy), GFP_KERNEL); + port->phys = devm_kcalloc(dev, sizeof(phy), port->lanes, GFP_KERNEL); if (!port->phys) return -ENOMEM; diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 5eb1af264e85..9c116cbaa95d 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -430,18 +430,15 @@ static int sriov_add_vfs(struct pci_dev *dev, u16 num_vfs) if (dev->no_vf_scan) return 0; - pci_lock_rescan_remove(); for (i = 0; i < num_vfs; i++) { rc = pci_iov_add_virtfn(dev, i); if (rc) goto failed; } - pci_unlock_rescan_remove(); return 0; failed: while (i--) pci_iov_remove_virtfn(dev, i); - pci_unlock_rescan_remove(); return rc; } @@ -564,10 +561,8 @@ static void sriov_del_vfs(struct pci_dev *dev) if (dev->no_vf_scan) return; - pci_lock_rescan_remove(); for (i = 0; i < iov->num_VFs; i++) pci_iov_remove_virtfn(dev, i); - pci_unlock_rescan_remove(); } static void sriov_disable(struct pci_dev *dev) diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c index fe50d147e74e..0153abdbbc8d 100644 --- a/drivers/pci/p2pdma.c +++ b/drivers/pci/p2pdma.c @@ -215,7 +215,7 @@ int pci_p2pdma_add_resource(struct pci_dev *pdev, int bar, size_t size, pages_free: devm_memunmap_pages(&pdev->dev, pgmap); pgmap_free: - devm_kfree(&pdev->dev, p2p_pgmap); + devm_kfree(&pdev->dev, pgmap); return error; } EXPORT_SYMBOL_GPL(pci_p2pdma_add_resource); diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index 5819f0c4dd07..a14e42d716ea 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -1628,7 +1628,6 @@ void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type) switch (err_type) { case PCI_ERS_RESULT_NONE: case PCI_ERS_RESULT_CAN_RECOVER: - case PCI_ERS_RESULT_NEED_RESET: envp[idx++] = "ERROR_EVENT=BEGIN_RECOVERY"; envp[idx++] = "DEVICE_ONLINE=0"; break; diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index e1c9330e2b1e..41cf3dece9de 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2572,7 +2572,6 @@ static void quirk_disable_msi(struct pci_dev *dev) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RDC, 0x1031, quirk_disable_msi); /* * The APC bridge device in AMD 780 family northbridges has some random diff --git a/drivers/pci/switch/switchtec.c b/drivers/pci/switch/switchtec.c index 1b30d08e1867..0b8325235852 100644 --- a/drivers/pci/switch/switchtec.c +++ b/drivers/pci/switch/switchtec.c @@ -1025,7 +1025,7 @@ static const struct file_operations switchtec_fops = { .read = switchtec_dev_read, .poll = switchtec_dev_poll, .unlocked_ioctl = switchtec_dev_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = switchtec_dev_ioctl, }; static void link_event_work(struct work_struct *work) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 91a6631af556..079701e8de18 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -75,8 +75,7 @@ struct arm_spe_pmu { #define to_spe_pmu(p) (container_of(p, struct arm_spe_pmu, pmu)) /* Convert a free-running index from perf into an SPE buffer offset */ -#define PERF_IDX2OFF(idx, buf) \ - ((idx) % ((unsigned long)(buf)->nr_pages << PAGE_SHIFT)) +#define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT)) /* Keep track of our dynamic hotplug state */ static enum cpuhp_state arm_spe_pmu_online; diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c index 04cee5a00a5b..90c4e9b5aac8 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -115,7 +115,7 @@ static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy, dlane_bps = opts->hs_clk_rate; - if (dlane_bps > 2500000000UL || dlane_bps < 80000000UL) + if (dlane_bps > 2500000000UL || dlane_bps < 160000000UL) return -EINVAL; else if (dlane_bps >= 1250000000) cfg->pll_opdiv = 1; @@ -125,8 +125,6 @@ static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy, cfg->pll_opdiv = 4; else if (dlane_bps >= 160000000) cfg->pll_opdiv = 8; - else if (dlane_bps >= 80000000) - cfg->pll_opdiv = 16; cfg->pll_fbdiv = DIV_ROUND_UP_ULL(dlane_bps * 2 * cfg->pll_opdiv * cfg->pll_ipdiv, diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c index 2da0f2ab4038..e8d1f3050487 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -187,9 +187,6 @@ static const unsigned int i2c_sda_c_pins[] = { GPIODV_28 }; static const unsigned int i2c_sck_c_dv19_pins[] = { GPIODV_19 }; static const unsigned int i2c_sda_c_dv18_pins[] = { GPIODV_18 }; -static const unsigned int i2c_sck_d_pins[] = { GPIOX_11 }; -static const unsigned int i2c_sda_d_pins[] = { GPIOX_10 }; - static const unsigned int eth_mdio_pins[] = { GPIOZ_0 }; static const unsigned int eth_mdc_pins[] = { GPIOZ_1 }; static const unsigned int eth_clk_rx_clk_pins[] = { GPIOZ_2 }; @@ -403,8 +400,6 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = { GPIO_GROUP(GPIO_TEST_N), /* Bank X */ - GROUP(i2c_sda_d, 5, 5), - GROUP(i2c_sck_d, 5, 4), GROUP(sdio_d0, 5, 31), GROUP(sdio_d1, 5, 30), GROUP(sdio_d2, 5, 29), @@ -636,10 +631,6 @@ static const char * const i2c_c_groups[] = { "i2c_sck_c", "i2c_sda_c", "i2c_sda_c_dv18", "i2c_sck_c_dv19", }; -static const char * const i2c_d_groups[] = { - "i2c_sck_d", "i2c_sda_d", -}; - static const char * const eth_groups[] = { "eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv", "eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3", @@ -760,7 +751,6 @@ static struct meson_pmx_func meson_gxl_periphs_functions[] = { FUNCTION(i2c_a), FUNCTION(i2c_b), FUNCTION(i2c_c), - FUNCTION(i2c_d), FUNCTION(eth), FUNCTION(pwm_a), FUNCTION(pwm_b), diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index b76c3f682287..9503ddf2edc7 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -324,7 +324,7 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev, while (selector < nfuncs) { const char *fname = ops->get_function_name(pctldev, selector); - if (fname && !strcmp(function, fname)) + if (!strcmp(function, fname)) return selector; selector++; diff --git a/drivers/platform/msm/Kconfig b/drivers/platform/msm/Kconfig index 5c16609c50d0..c6a38ba5686f 100644 --- a/drivers/platform/msm/Kconfig +++ b/drivers/platform/msm/Kconfig @@ -217,13 +217,4 @@ config AQFWD_IOSS aqc_ioss. If unsure, say N. -config USB_R8152_RTL - tristate "Realtek R8152 driver" - help - This option adds support for Realtek RTL8152 based USB to - Ethernet adapter. - - To compile this driver as a module, choose M here: the module - will be called r8152_rtl. If unsure, say N. - endmenu diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c index cef10b457073..c8e23ac53d2f 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c @@ -2179,11 +2179,6 @@ int ep_pcie_core_disable_endpoint(void) if (atomic_read(&dev->host_wake_pending)) { EP_PCIE_DBG(dev, "PCIe V%d: wake pending, init wakeup\n", dev->rev); - /* - * Clear the wake pending otherwise ep_pcie_core_wakeup_host_internal - * will return without WAKE toggle - */ - atomic_set(&dev->host_wake_pending, 0); ep_pcie_core_wakeup_host_internal(EP_PCIE_EVENT_PM_D3_COLD); } diff --git a/drivers/platform/msm/mhi_dev/mhi.c b/drivers/platform/msm/mhi_dev/mhi.c index 141ce1157e9c..68e52b8191c9 100644 --- a/drivers/platform/msm/mhi_dev/mhi.c +++ b/drivers/platform/msm/mhi_dev/mhi.c @@ -39,7 +39,7 @@ /* Wait time on the device for Host to set BHI_INTVEC */ #define MHI_BHI_INTVEC_MAX_CNT 200 #define MHI_BHI_INTVEC_WAIT_MS 50 -#define MHI_WAKEUP_TIMEOUT_CNT 25 +#define MHI_WAKEUP_TIMEOUT_CNT 20 #define MHI_MASK_CH_EV_LEN 32 #define MHI_RING_CMD_ID 0 #define MHI_RING_PRIMARY_EVT_ID 1 @@ -3936,9 +3936,6 @@ static void mhi_dev_enable(struct work_struct *work) "Cleared reset before waiting for M0\n"); } - if (ep_pcie_get_linkstatus(mhi->phandle) != EP_PCIE_LINK_ENABLED) - mhi_log(MHI_MSG_ERROR, "warning: PCIe BME unset error"); - while (state != MHI_DEV_M0_STATE && ((max_cnt < MHI_SUSPEND_TIMEOUT) || mhi->no_m0_timeout)) { /* Wait for Host to set the M0 state */ diff --git a/drivers/platform/msm/mhi_dev/mhi_sm.c b/drivers/platform/msm/mhi_dev/mhi_sm.c index e8d9300c7812..5669fcfbd16a 100644 --- a/drivers/platform/msm/mhi_dev/mhi_sm.c +++ b/drivers/platform/msm/mhi_dev/mhi_sm.c @@ -12,7 +12,6 @@ #include "mhi_hwio.h" #include "mhi_sm.h" #include -#include #define MHI_SM_DBG(fmt, args...) \ mhi_log(MHI_MSG_DBG, fmt, ##args) @@ -29,11 +28,7 @@ #define PCIE_EP_TIMER_US 500000000 #define MHI_IPA_DISABLE_DELAY_MS 10 #define MHI_IPA_DISABLE_COUNTER 20 -/* Maximum wait time for D state transitions to D3hot */ -#define M3_DO_WAKEUP_TIMEOUT_MS 2500 -static void wait_d3_and_wakeup(struct work_struct *work); -static int mhi_dev_sm_get_mhi_pcie_states(uint32_t *mstate, uint32_t *dstate); static inline const char *mhi_sm_dev_event_str(enum mhi_dev_event state) { @@ -101,6 +96,12 @@ static inline const char *mhi_sm_mstate_str(enum mhi_dev_state state) return str; } +enum mhi_sm_ep_pcie_state { + MHI_SM_EP_PCIE_LINK_DISABLE, + MHI_SM_EP_PCIE_D0_STATE, + MHI_SM_EP_PCIE_D3_HOT_STATE, + MHI_SM_EP_PCIE_D3_COLD_STATE, +}; static inline const char *mhi_sm_dstate_str(enum mhi_sm_ep_pcie_state state) { @@ -240,8 +241,6 @@ struct mhi_sm_dev { struct mutex mhi_state_lock; bool syserr_occurred; struct workqueue_struct *mhi_sm_wq; - struct workqueue_struct *mhi_wake_wq; - struct work_struct mhi_wake_work; atomic_t pending_device_events; atomic_t pending_pcie_events; struct mhi_sm_stats stats; @@ -741,12 +740,12 @@ exit: * mhi_sm_wakeup_host() - wakeup MHI-host *@event: MHI state chenge event * - * Sends wakeup event to MHI-host via EP-PCIe, in case MHI is in M3 state. + * Sends wekup event to MHI-host via EP-PCIe, in case MHI is in M3 state. * * Return: 0:success * negative: failure */ -static int mhi_sm_wakeup_host(void) +static int mhi_sm_wakeup_host(enum mhi_dev_event event) { int res = 0; enum ep_pcie_event pcie_event; @@ -761,8 +760,7 @@ static int mhi_sm_wakeup_host(void) } else if (mhi_sm_ctx->mhi_state == MHI_DEV_M3_STATE) { /* * Check and send D3_HOT to enable waking up the host - * using inband PME if the host is in D3_HOT state, otherwise - * send D3_COLD to wake up the host. + * using inband PME. */ if (mhi_sm_ctx->d_state == MHI_SM_EP_PCIE_D3_HOT_STATE) pcie_event = EP_PCIE_EVENT_PM_D3_HOT; @@ -914,7 +912,9 @@ static void mhi_sm_dev_event_manager(struct work_struct *work) break; case MHI_DEV_EVENT_HW_ACC_WAKEUP: case MHI_DEV_EVENT_CORE_WAKEUP: - queue_work(mhi_sm_ctx->mhi_wake_wq, &mhi_sm_ctx->mhi_wake_work); + res = mhi_sm_wakeup_host(chg_event->event); + if (res) + MHI_SM_ERR("Failed to wakeup MHI host\n"); break; case MHI_DEV_EVENT_CTRL_TRIG: case MHI_DEV_EVENT_M1_STATE: @@ -1106,6 +1106,8 @@ unlock_and_exit: int mhi_dev_sm_init(struct mhi_dev *mhi_dev) { int res; + enum ep_pcie_link_status link_state; + MHI_SM_FUNC_ENTRY(); if (!mhi_dev) { @@ -1125,19 +1127,9 @@ int mhi_dev_sm_init(struct mhi_dev *mhi_dev) if (!mhi_sm_ctx->mhi_sm_wq) { MHI_SM_ERR("Failed to create singlethread_workqueue: sm_wq\n"); res = -ENOMEM; - goto fail_init_sm_wq; + goto fail_init_wq; } - if (!mhi_sm_ctx->mhi_wake_wq) - mhi_sm_ctx->mhi_wake_wq = alloc_workqueue( - "mhi_wake_wq", WQ_HIGHPRI | WQ_UNBOUND, 1); - if (!mhi_sm_ctx->mhi_wake_wq) { - MHI_SM_ERR("Failed to create singlethread_workqueue: wake_wq\n"); - res = -ENOMEM; - goto fail_init_wake_wq; - } - INIT_WORK(&mhi_sm_ctx->mhi_wake_work, wait_d3_and_wakeup); - mutex_init(&mhi_sm_ctx->mhi_state_lock); mhi_sm_ctx->mhi_dev = mhi_dev; mhi_sm_ctx->mhi_state = MHI_DEV_RESET_STATE; @@ -1145,15 +1137,16 @@ int mhi_dev_sm_init(struct mhi_dev *mhi_dev) atomic_set(&mhi_sm_ctx->pending_device_events, 0); atomic_set(&mhi_sm_ctx->pending_pcie_events, 0); - mhi_sm_ctx->d_state = MHI_SM_EP_PCIE_D0_STATE; + link_state = ep_pcie_get_linkstatus(mhi_sm_ctx->mhi_dev->phandle); + if (link_state == EP_PCIE_LINK_ENABLED) + mhi_sm_ctx->d_state = MHI_SM_EP_PCIE_D0_STATE; + else + mhi_sm_ctx->d_state = MHI_SM_EP_PCIE_LINK_DISABLE; MHI_SM_FUNC_EXIT(); return 0; -fail_init_wake_wq: - flush_workqueue(mhi_sm_ctx->mhi_sm_wq); - destroy_workqueue(mhi_sm_ctx->mhi_sm_wq); -fail_init_sm_wq: +fail_init_wq: mhi_sm_ctx = NULL; mhi_sm_debugfs_destroy(); return res; @@ -1181,20 +1174,20 @@ int mhi_dev_sm_exit(struct mhi_dev *mhi_dev) EXPORT_SYMBOL(mhi_dev_sm_exit); /** - * mhi_dev_sm_get_mhi_pcie_states() -Get current MHI and Pcie states. + * mhi_dev_sm_get_mhi_state() -Get current MHI state. * @state: return param * - * Returns the current MHI and PCIe states of the state machine. + * Returns the current MHI state of the state machine. * * Return: 0 success * -EINVAL: invalid param * -EFAULT: state machine isn't initialized */ -static int mhi_dev_sm_get_mhi_pcie_states(uint32_t *mstate, uint32_t *dstate) +int mhi_dev_sm_get_mhi_state(enum mhi_dev_state *state) { MHI_SM_FUNC_ENTRY(); - if (!mstate || !dstate) { + if (!state) { MHI_SM_ERR("Fail: Null argument\n"); return -EINVAL; } @@ -1202,60 +1195,15 @@ static int mhi_dev_sm_get_mhi_pcie_states(uint32_t *mstate, uint32_t *dstate) MHI_SM_ERR("Fail: MHI SM is not initialized\n"); return -EFAULT; } - mutex_lock(&mhi_sm_ctx->mhi_state_lock); - *mstate = mhi_sm_ctx->mhi_state; - *dstate = mhi_sm_ctx->d_state; - mutex_unlock(&mhi_sm_ctx->mhi_state_lock); + *state = mhi_sm_ctx->mhi_state; MHI_SM_DBG("state machine states are: %s and %s\n", - mhi_sm_mstate_str(*mstate), - mhi_sm_dstate_str(*dstate)); + mhi_sm_mstate_str(*state), + mhi_sm_dstate_str(mhi_sm_ctx->d_state)); MHI_SM_FUNC_EXIT(); return 0; } - -static void wait_d3_and_wakeup(struct work_struct *work) -{ - struct mhi_sm_dev *mhi_sm_ctx = container_of(work, struct mhi_sm_dev, mhi_wake_work); - enum mhi_dev_state mstate; - enum mhi_sm_ep_pcie_state dstate; - ktime_t timeout = 0; - - if (mhi_dev_sm_get_mhi_pcie_states(&mstate, &dstate)) { - MHI_SM_ERR("Unable to read states\n"); - return; - } - /* - * Handle host wakeup in M3 + D0 states. - * When a MHI WAKE request is received while device is in D0, - * wait for D3 and wakeup the host using inband PME. - * If the MHI state changes to M0 while waiting for D3, - * exit, since both MHI and the device are in active state - */ - if (dstate == MHI_SM_EP_PCIE_D0_STATE) { - timeout = ktime_add_ms(ktime_get(), M3_DO_WAKEUP_TIMEOUT_MS); - while (1) { - mhi_dev_sm_get_mhi_pcie_states(&mstate, &dstate); - if (mstate == MHI_DEV_M0_STATE) { - MHI_SM_DBG("M0 state received\n"); - return; - } - if (dstate == MHI_SM_EP_PCIE_D3_HOT_STATE || - dstate == MHI_SM_EP_PCIE_D3_COLD_STATE) { - MHI_SM_DBG("D3 state received\n"); - goto send_host_wakeup; - } - if (ktime_after(ktime_get(), timeout)) { - MHI_SM_ERR("Neither received D3 nor M0 in stipulated time\n"); - return; - } - usleep_range(1000, 2000); - } - } -send_host_wakeup: - if (dstate == MHI_SM_EP_PCIE_D3_HOT_STATE || dstate == MHI_SM_EP_PCIE_D3_COLD_STATE) - mhi_sm_wakeup_host(); -} +EXPORT_SYMBOL(mhi_dev_sm_get_mhi_state); /** * mhi_dev_sm_set_ready() -Set MHI state to ready. @@ -1290,7 +1238,16 @@ int mhi_dev_sm_set_ready(void) goto unlock_and_exit; } - mhi_sm_ctx->d_state = MHI_SM_EP_PCIE_D0_STATE; + if (mhi_sm_ctx->d_state != MHI_SM_EP_PCIE_D0_STATE) { + if (ep_pcie_get_linkstatus(mhi_sm_ctx->mhi_dev->phandle) == + EP_PCIE_LINK_ENABLED) { + mhi_sm_ctx->d_state = MHI_SM_EP_PCIE_D0_STATE; + } else { + MHI_SM_ERR("ERROR: ep-pcie link is not enabled\n"); + res = -EPERM; + goto unlock_and_exit; + } + } /* verify that MHISTATUS is configured to RESET*/ mhi_dev_mmio_masked_read(mhi_sm_ctx->mhi_dev, diff --git a/drivers/platform/msm/mhi_dev/mhi_sm.h b/drivers/platform/msm/mhi_dev/mhi_sm.h index 24e6daf46777..e061fed208ea 100644 --- a/drivers/platform/msm/mhi_dev/mhi_sm.h +++ b/drivers/platform/msm/mhi_dev/mhi_sm.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2015,2017-2018,2020-2021 The Linux Foundation. All rights reserved.*/ +/* Copyright (c) 2015,2017-2018,2020 The Linux Foundation. All rights reserved.*/ #ifndef MHI_SM_H #define MHI_SM_H @@ -31,17 +31,11 @@ enum mhi_dev_event { MHI_DEV_EVENT_MAX }; -enum mhi_sm_ep_pcie_state { - MHI_SM_EP_PCIE_LINK_DISABLE, - MHI_SM_EP_PCIE_D0_STATE, - MHI_SM_EP_PCIE_D3_HOT_STATE, - MHI_SM_EP_PCIE_D3_COLD_STATE, -}; - int mhi_dev_sm_init(struct mhi_dev *dev); int mhi_dev_sm_exit(struct mhi_dev *dev); int mhi_dev_sm_set_ready(void); int mhi_dev_notify_sm_event(enum mhi_dev_event event); +int mhi_dev_sm_get_mhi_state(enum mhi_dev_state *state); int mhi_dev_sm_syserr(void); void mhi_dev_sm_pcie_handler(struct ep_pcie_notify *notify); diff --git a/drivers/platform/x86/wmi.c b/drivers/platform/x86/wmi.c index 2acdbf93088d..66cfc35e4e3d 100644 --- a/drivers/platform/x86/wmi.c +++ b/drivers/platform/x86/wmi.c @@ -912,7 +912,7 @@ static const struct file_operations wmi_fops = { .read = wmi_char_read, .open = wmi_char_open, .unlocked_ioctl = wmi_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = wmi_ioctl, }; static int wmi_dev_probe(struct device *dev) diff --git a/drivers/power/qpnp_adaptive_charge/qpnp_adaptive_charge.c b/drivers/power/qpnp_adaptive_charge/qpnp_adaptive_charge.c index bf2be7211d94..1394a74d7d17 100755 --- a/drivers/power/qpnp_adaptive_charge/qpnp_adaptive_charge.c +++ b/drivers/power/qpnp_adaptive_charge/qpnp_adaptive_charge.c @@ -67,7 +67,6 @@ static struct adap_chg_data { struct delayed_work reinit_work; } adap_chg_data; -int charging_enabled = 1; int upper_limit = -1; int lower_limit = -1; int blocking = 0; @@ -146,23 +145,17 @@ static void stop_charging(bool on) static void update(struct adap_chg_data *data) { - if (!charging_enabled) { - suspend_charging(false); - stop_charging(true); + data->batt_capacity = get_ps_int_prop(data->batt_psy, + POWER_SUPPLY_PROP_CAPACITY); + if (data->batt_capacity < 0) { + pr_err("Failed to get battery capacity\n"); return; } + pr_info("Batt cap is %d, upper limit is %d, lower limit is %d\n", + data->batt_capacity, upper_limit, lower_limit); + if (upper_limit != -1) { - data->batt_capacity = get_ps_int_prop(data->batt_psy, - POWER_SUPPLY_PROP_CAPACITY); - if (data->batt_capacity < 0) { - pr_err("Failed to get battery capacity\n"); - return; - } - - pr_info("Batt cap is %d, upper limit is %d, lower limit is %d\n", - data->batt_capacity, upper_limit, lower_limit); - /* If no lower limit is defined, we are in Auto Mode */ if (lower_limit == -1) { #ifdef ADAPTIVE_TOLERANCE_OPTIMIZATION @@ -212,29 +205,6 @@ static void update_work(struct work_struct *w) update(data); } -static int set_charging_enabled(const char *val, const struct kernel_param *kp) -{ - int rc; - long new_state; - - if (!adap_chg_data.init_success) - return -ENODEV; - - rc = kstrtol(val, 0, &new_state); - if (rc) - return rc; - - if (new_state != 0 && new_state != 1) - return -EINVAL; - - charging_enabled = (int)new_state; - - pr_info("charging_enabled set to %d\n", charging_enabled); - update(&adap_chg_data); - - return 0; -} - static int set_upper_limit(const char *val, const struct kernel_param *kp) { int rc; @@ -334,12 +304,6 @@ static int ps_notify_callback(struct notifier_block *nb, return 0; } -static struct kernel_param_ops charging_enabled_ops = -{ - .set = &set_charging_enabled, - .get = param_get_int, -}; - static struct kernel_param_ops upper_limit_ops = { .set = &set_upper_limit, @@ -358,12 +322,6 @@ static struct kernel_param_ops blocking_ops = .get = &get_blocking, }; -module_param_cb(charging_enabled, - &charging_enabled_ops, - &charging_enabled, - S_IRUGO | S_IWUSR -); - module_param_cb(upper_limit, &upper_limit_ops, &upper_limit, diff --git a/drivers/pps/kapi.c b/drivers/pps/kapi.c index e9389876229e..92d1b62ea239 100644 --- a/drivers/pps/kapi.c +++ b/drivers/pps/kapi.c @@ -109,13 +109,16 @@ struct pps_device *pps_register_source(struct pps_source_info *info, if (err < 0) { pr_err("%s: unable to create char device\n", info->name); - goto pps_register_source_exit; + goto kfree_pps; } dev_dbg(&pps->dev, "new PPS source %s\n", info->name); return pps; +kfree_pps: + kfree(pps); + pps_register_source_exit: pr_err("%s: unable to register source\n", info->name); diff --git a/drivers/pps/pps.c b/drivers/pps/pps.c index dbeb67ffebf3..ea966fc67d28 100644 --- a/drivers/pps/pps.c +++ b/drivers/pps/pps.c @@ -375,7 +375,6 @@ int pps_register_cdev(struct pps_device *pps) pps->info.name); err = -EBUSY; } - kfree(pps); goto out_unlock; } pps->id = err; @@ -385,11 +384,13 @@ int pps_register_cdev(struct pps_device *pps) pps->dev.devt = MKDEV(pps_major, pps->id); dev_set_drvdata(&pps->dev, pps); dev_set_name(&pps->dev, "pps%d", pps->id); - pps->dev.release = pps_device_destruct; err = device_register(&pps->dev); if (err) goto free_idr; + /* Override the release function with our own */ + pps->dev.release = pps_device_destruct; + pr_debug("source %s got cdev (%d:%d)\n", pps->info.name, pps_major, pps->id); diff --git a/drivers/pwm/pwm-berlin.c b/drivers/pwm/pwm-berlin.c index c9d11486f2c1..b91c477cc84b 100644 --- a/drivers/pwm/pwm-berlin.c +++ b/drivers/pwm/pwm-berlin.c @@ -249,7 +249,7 @@ static int berlin_pwm_suspend(struct device *dev) if (!channel) continue; - channel->enable = berlin_pwm_readl(pwm, i, BERLIN_PWM_EN); + channel->enable = berlin_pwm_readl(pwm, i, BERLIN_PWM_ENABLE); channel->ctrl = berlin_pwm_readl(pwm, i, BERLIN_PWM_CONTROL); channel->duty = berlin_pwm_readl(pwm, i, BERLIN_PWM_DUTY); channel->tcnt = berlin_pwm_readl(pwm, i, BERLIN_PWM_TCNT); @@ -280,7 +280,7 @@ static int berlin_pwm_resume(struct device *dev) berlin_pwm_writel(pwm, i, channel->ctrl, BERLIN_PWM_CONTROL); berlin_pwm_writel(pwm, i, channel->duty, BERLIN_PWM_DUTY); berlin_pwm_writel(pwm, i, channel->tcnt, BERLIN_PWM_TCNT); - berlin_pwm_writel(pwm, i, channel->enable, BERLIN_PWM_EN); + berlin_pwm_writel(pwm, i, channel->enable, BERLIN_PWM_ENABLE); } return 0; diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 7414daef81a3..7b4c770ce9d6 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -167,7 +167,7 @@ static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div, *prescale_div = (1 << clkdiv) * (hspclkdiv ? (hspclkdiv * 2) : 1); - if (*prescale_div >= rqst_prescaler) { + if (*prescale_div > rqst_prescaler) { *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) | (hspclkdiv << TBCTL_HSPCLKDIV_SHIFT); return 0; @@ -266,7 +266,7 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, pc->period_cycles[pwm->hwpwm] = period_cycles; /* Configure clock prescaler to support Low frequency PWM wave */ - if (set_prescale_div(DIV_ROUND_UP(period_cycles, PERIOD_MAX), &ps_divval, + if (set_prescale_div(period_cycles/PERIOD_MAX, &ps_divval, &tb_divval)) { dev_err(chip->dev, "Unsupported values\n"); return -EINVAL; diff --git a/drivers/regulator/fixed.c b/drivers/regulator/fixed.c index e769df09627b..3ed55c863bfd 100644 --- a/drivers/regulator/fixed.c +++ b/drivers/regulator/fixed.c @@ -264,10 +264,8 @@ static int reg_fixed_voltage_probe(struct platform_device *pdev) drvdata->dev = devm_regulator_register(&pdev->dev, &drvdata->desc, &cfg); if (IS_ERR(drvdata->dev)) { - ret = dev_err_probe(&pdev->dev, PTR_ERR(drvdata->dev), - "Failed to register regulator: %ld\n", - PTR_ERR(drvdata->dev)); - gpiod_put(cfg.ena_gpiod); + ret = PTR_ERR(drvdata->dev); + dev_err(&pdev->dev, "Failed to register regulator: %d\n", ret); return ret; } diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c index a6ddb58330eb..eaeb6aee6da5 100644 --- a/drivers/remoteproc/qcom_q6v5.c +++ b/drivers/remoteproc/qcom_q6v5.c @@ -113,6 +113,9 @@ int qcom_q6v5_wait_for_start(struct qcom_q6v5 *q6v5, int timeout) int ret; ret = wait_for_completion_timeout(&q6v5->start_done, timeout); + if (!ret) + disable_irq(q6v5->handover_irq); + return !ret ? -ETIMEDOUT : 0; } EXPORT_SYMBOL_GPL(qcom_q6v5_wait_for_start); @@ -121,11 +124,6 @@ static irqreturn_t q6v5_handover_interrupt(int irq, void *data) { struct qcom_q6v5 *q6v5 = data; - if (q6v5->handover_issued) { - dev_err(q6v5->dev, "Handover signaled, but it already happened\n"); - return IRQ_HANDLED; - } - if (q6v5->handover) q6v5->handover(q6v5); diff --git a/drivers/rpmsg/rpmsg_char.c b/drivers/rpmsg/rpmsg_char.c index c503829fb307..ac50ed757765 100644 --- a/drivers/rpmsg/rpmsg_char.c +++ b/drivers/rpmsg/rpmsg_char.c @@ -292,7 +292,7 @@ static const struct file_operations rpmsg_eptdev_fops = { .write_iter = rpmsg_eptdev_write_iter, .poll = rpmsg_eptdev_poll, .unlocked_ioctl = rpmsg_eptdev_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = rpmsg_eptdev_ioctl, }; static ssize_t name_show(struct device *dev, struct device_attribute *attr, @@ -446,7 +446,7 @@ static const struct file_operations rpmsg_ctrldev_fops = { .open = rpmsg_ctrldev_open, .release = rpmsg_ctrldev_release, .unlocked_ioctl = rpmsg_ctrldev_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = rpmsg_ctrldev_ioctl, }; static void rpmsg_ctrldev_release_device(struct device *dev) diff --git a/drivers/rtc/interface.c b/drivers/rtc/interface.c index 010e47b62f2f..da866d9e8117 100644 --- a/drivers/rtc/interface.c +++ b/drivers/rtc/interface.c @@ -442,29 +442,6 @@ static int __rtc_set_alarm(struct rtc_device *rtc, struct rtc_wkalrm *alarm) else err = rtc->ops->set_alarm(rtc->dev.parent, alarm); - /* - * Check for potential race described above. If the waiting for next - * second, and the second just ticked since the check above, either - * - * 1) It ticked after the alarm was set, and an alarm irq should be - * generated. - * - * 2) It ticked before the alarm was set, and alarm irq most likely will - * not be generated. - * - * While we cannot easily check for which of these two scenarios we - * are in, we can return -ETIME to signal that the timer has already - * expired, which is true in both cases. - */ - if ((scheduled - now) <= 1) { - err = __rtc_read_time(rtc, &tm); - if (err) - return err; - now = rtc_tm_to_time64(&tm); - if (scheduled <= now) - return -ETIME; - } - trace_rtc_set_alarm(rtc_tm_to_time64(&alarm->time), err); return err; } @@ -612,10 +589,6 @@ int rtc_update_irq_enable(struct rtc_device *rtc, unsigned int enabled) rtc->uie_rtctimer.node.expires = ktime_add(now, onesec); rtc->uie_rtctimer.period = ktime_set(1, 0); err = rtc_timer_enqueue(rtc, &rtc->uie_rtctimer); - if (!err && rtc->ops && rtc->ops->alarm_irq_enable) - err = rtc->ops->alarm_irq_enable(rtc->dev.parent, 1); - if (err) - goto out; } else { rtc_timer_remove(rtc, &rtc->uie_rtctimer); } diff --git a/drivers/rtc/rtc-x1205.c b/drivers/rtc/rtc-x1205.c index 3b3aaa7d8283..d1d5a44d9122 100644 --- a/drivers/rtc/rtc-x1205.c +++ b/drivers/rtc/rtc-x1205.c @@ -671,7 +671,7 @@ static const struct i2c_device_id x1205_id[] = { MODULE_DEVICE_TABLE(i2c, x1205_id); static const struct of_device_id x1205_dt_ids[] = { - { .compatible = "xicor,x1205", }, + { .compatible = "xircom,x1205", }, {}, }; MODULE_DEVICE_TABLE(of, x1205_dt_ids); diff --git a/drivers/s390/net/ctcm_mpc.c b/drivers/s390/net/ctcm_mpc.c index e76b6e7f80ac..d766002bc5be 100644 --- a/drivers/s390/net/ctcm_mpc.c +++ b/drivers/s390/net/ctcm_mpc.c @@ -712,6 +712,7 @@ static void mpc_rcvd_sweep_req(struct mpcg_info *mpcginfo) grp->sweep_req_pend_num--; ctcmpc_send_sweep_resp(ch); + kfree(mpcginfo); return; } diff --git a/drivers/sbus/char/display7seg.c b/drivers/sbus/char/display7seg.c index fad936eb845f..971fe074d7c9 100644 --- a/drivers/sbus/char/display7seg.c +++ b/drivers/sbus/char/display7seg.c @@ -156,7 +156,7 @@ static long d7s_ioctl(struct file *file, unsigned int cmd, unsigned long arg) static const struct file_operations d7s_fops = { .owner = THIS_MODULE, .unlocked_ioctl = d7s_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = d7s_ioctl, .open = d7s_open, .release = d7s_release, .llseek = noop_llseek, diff --git a/drivers/sbus/char/envctrl.c b/drivers/sbus/char/envctrl.c index 12d66aa61ede..a63d5e402ff2 100644 --- a/drivers/sbus/char/envctrl.c +++ b/drivers/sbus/char/envctrl.c @@ -715,7 +715,9 @@ static const struct file_operations envctrl_fops = { .owner = THIS_MODULE, .read = envctrl_read, .unlocked_ioctl = envctrl_ioctl, - .compat_ioctl = compat_ptr_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = envctrl_ioctl, +#endif .open = envctrl_open, .release = envctrl_release, .llseek = noop_llseek, diff --git a/drivers/scsi/3w-xxxx.c b/drivers/scsi/3w-xxxx.c index 211a25351e7d..75290aabd543 100644 --- a/drivers/scsi/3w-xxxx.c +++ b/drivers/scsi/3w-xxxx.c @@ -1049,7 +1049,9 @@ static int tw_chrdev_open(struct inode *inode, struct file *file) static const struct file_operations tw_fops = { .owner = THIS_MODULE, .unlocked_ioctl = tw_chrdev_ioctl, - .compat_ioctl = compat_ptr_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = tw_chrdev_ioctl, +#endif .open = tw_chrdev_open, .release = NULL, .llseek = noop_llseek, diff --git a/drivers/scsi/cxlflash/main.c b/drivers/scsi/cxlflash/main.c index 6f45074ee895..67d681c53c29 100644 --- a/drivers/scsi/cxlflash/main.c +++ b/drivers/scsi/cxlflash/main.c @@ -3593,7 +3593,7 @@ static const struct file_operations cxlflash_chr_fops = { .owner = THIS_MODULE, .open = cxlflash_chr_open, .unlocked_ioctl = cxlflash_chr_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = cxlflash_chr_ioctl, }; /** diff --git a/drivers/scsi/esas2r/esas2r_main.c b/drivers/scsi/esas2r/esas2r_main.c index 80c5a235d193..fdbda5c05aa0 100644 --- a/drivers/scsi/esas2r/esas2r_main.c +++ b/drivers/scsi/esas2r/esas2r_main.c @@ -613,7 +613,7 @@ static int __init esas2r_init(void) /* Handle ioctl calls to "/proc/scsi/esas2r/ATTOnode" */ static const struct file_operations esas2r_proc_fops = { - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = esas2r_proc_ioctl, .unlocked_ioctl = esas2r_proc_ioctl, }; diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c index 359e1f61d598..b760477b5742 100644 --- a/drivers/scsi/hpsa.c +++ b/drivers/scsi/hpsa.c @@ -6508,21 +6508,18 @@ static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp) while (left) { sz = (left > ioc->malloc_size) ? ioc->malloc_size : left; buff_size[sg_used] = sz; - - if (ioc->Request.Type.Direction & XFER_WRITE) { - buff[sg_used] = memdup_user(data_ptr, sz); - if (IS_ERR(buff[sg_used])) { - status = PTR_ERR(buff[sg_used]); - goto cleanup1; - } - } else { - buff[sg_used] = kzalloc(sz, GFP_KERNEL); - if (!buff[sg_used]) { - status = -ENOMEM; - goto cleanup1; - } + buff[sg_used] = kmalloc(sz, GFP_KERNEL); + if (buff[sg_used] == NULL) { + status = -ENOMEM; + goto cleanup1; } - + if (ioc->Request.Type.Direction & XFER_WRITE) { + if (copy_from_user(buff[sg_used], data_ptr, sz)) { + status = -EFAULT; + goto cleanup1; + } + } else + memset(buff[sg_used], 0, sz); left -= sz; data_ptr += sz; sg_used++; diff --git a/drivers/scsi/lpfc/lpfc_debugfs.h b/drivers/scsi/lpfc/lpfc_debugfs.h index 6cd5605ad00b..20f2537af511 100644 --- a/drivers/scsi/lpfc/lpfc_debugfs.h +++ b/drivers/scsi/lpfc/lpfc_debugfs.h @@ -44,9 +44,6 @@ /* hbqinfo output buffer size */ #define LPFC_HBQINFO_SIZE 8192 -/* hdwqinfo output buffer size */ -#define LPFC_HDWQINFO_SIZE 8192 - /* nvmestat output buffer size */ #define LPFC_NVMESTAT_SIZE 8192 #define LPFC_NVMEKTIME_SIZE 8192 diff --git a/drivers/scsi/lpfc/lpfc_scsi.c b/drivers/scsi/lpfc/lpfc_scsi.c index 9201c548aab4..1d58895b3943 100644 --- a/drivers/scsi/lpfc/lpfc_scsi.c +++ b/drivers/scsi/lpfc/lpfc_scsi.c @@ -5153,7 +5153,7 @@ lpfc_chk_tgt_mapped(struct lpfc_vport *vport, struct scsi_cmnd *cmnd) /** * lpfc_reset_flush_io_context - * @vport: The virtual port (scsi_host) for the flush context - * @tgt_id: If aborting by Target context - specifies the target id + * @tgt_id: If aborting by Target contect - specifies the target id * @lun_id: If aborting by Lun context - specifies the lun id * @context: specifies the context level to flush at. * @@ -5312,14 +5312,8 @@ lpfc_target_reset_handler(struct scsi_cmnd *cmnd) pnode->nlp_fcp_info &= ~NLP_FCP_2_DEVICE; spin_unlock_irq(shost->host_lock); } - status = lpfc_reset_flush_io_context(vport, tgt_id, lun_id, - LPFC_CTX_TGT); - if (status != SUCCESS) { - lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP, - "0726 Target Reset flush status x%x\n", - status); - return status; - } + lpfc_reset_flush_io_context(vport, tgt_id, lun_id, + LPFC_CTX_TGT); return FAST_IO_FAIL; } @@ -5463,7 +5457,7 @@ lpfc_host_reset_handler(struct scsi_cmnd *cmnd) int rc, ret = SUCCESS; lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP, - "3172 SCSI layer issued Host Reset\n"); + "3172 SCSI layer issued Host Reset Data:\n"); lpfc_offline_prep(phba, LPFC_MBX_WAIT); lpfc_offline(phba); diff --git a/drivers/scsi/mpt3sas/mpt3sas_transport.c b/drivers/scsi/mpt3sas/mpt3sas_transport.c index a355471cf079..ebe78ec42da8 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_transport.c +++ b/drivers/scsi/mpt3sas/mpt3sas_transport.c @@ -812,9 +812,11 @@ mpt3sas_transport_port_remove(struct MPT3SAS_ADAPTER *ioc, u64 sas_address, list_for_each_entry_safe(mpt3sas_phy, next_phy, &mpt3sas_port->phy_list, port_siblings) { if ((ioc->logging_level & MPT_DEBUG_TRANSPORT)) - ioc_info(ioc, "remove: sas_addr(0x%016llx), phy(%d)\n", - (unsigned long long) mpt3sas_port->remote_identify.sas_address, - mpt3sas_phy->phy_id); + dev_printk(KERN_INFO, &mpt3sas_port->port->dev, + "remove: sas_addr(0x%016llx), phy(%d)\n", + (unsigned long long) + mpt3sas_port->remote_identify.sas_address, + mpt3sas_phy->phy_id); mpt3sas_phy->phy_belongs_to_port = 0; if (!ioc->remove_host) sas_port_delete_phy(mpt3sas_port->port, diff --git a/drivers/scsi/mvsas/mv_defs.h b/drivers/scsi/mvsas/mv_defs.h index 3ec1c7546cdb..199ab49aa047 100644 --- a/drivers/scsi/mvsas/mv_defs.h +++ b/drivers/scsi/mvsas/mv_defs.h @@ -40,7 +40,6 @@ enum driver_configuration { MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */ MVS_OAF_SZ = 64, /* Open address frame buffer size */ MVS_QUEUE_SIZE = 64, /* Support Queue depth */ - MVS_RSVD_SLOTS = 4, MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2, }; diff --git a/drivers/scsi/mvsas/mv_init.c b/drivers/scsi/mvsas/mv_init.c index d0a6639c3542..0c5e2c610586 100644 --- a/drivers/scsi/mvsas/mv_init.c +++ b/drivers/scsi/mvsas/mv_init.c @@ -138,8 +138,8 @@ static void mvs_free(struct mvs_info *mvi) if (mvi->shost) scsi_host_put(mvi->shost); list_for_each_entry(mwq, &mvi->wq_list, entry) - cancel_delayed_work_sync(&mwq->work_q); - kfree(mvi->rsvd_tags); + cancel_delayed_work(&mwq->work_q); + kfree(mvi->tags); kfree(mvi); } @@ -284,7 +284,10 @@ static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost) printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name); goto err_out; } + mvi->tags_num = slot_nr; + /* Initialize tags */ + mvs_tag_init(mvi); return 0; err_out: return 1; @@ -367,8 +370,8 @@ static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev, mvi->sas = sha; mvi->shost = shost; - mvi->rsvd_tags = bitmap_zalloc(MVS_RSVD_SLOTS, GFP_KERNEL); - if (!mvi->rsvd_tags) + mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL); + if (!mvi->tags) goto err_out; if (MVS_CHIP_DISP->chip_ioremap(mvi)) @@ -469,8 +472,6 @@ static void mvs_post_sas_ha_init(struct Scsi_Host *shost, else can_queue = MVS_CHIP_SLOT_SZ; - can_queue -= MVS_RSVD_SLOTS; - shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG); shost->can_queue = can_queue; mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE; diff --git a/drivers/scsi/mvsas/mv_sas.c b/drivers/scsi/mvsas/mv_sas.c index 393a8ee551e4..68caeaf9e636 100644 --- a/drivers/scsi/mvsas/mv_sas.c +++ b/drivers/scsi/mvsas/mv_sas.c @@ -20,40 +20,44 @@ static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag) return 0; } -static void mvs_tag_clear(struct mvs_info *mvi, u32 tag) +void mvs_tag_clear(struct mvs_info *mvi, u32 tag) { - void *bitmap = mvi->rsvd_tags; + void *bitmap = mvi->tags; clear_bit(tag, bitmap); } -static void mvs_tag_free(struct mvs_info *mvi, u32 tag) +void mvs_tag_free(struct mvs_info *mvi, u32 tag) { - if (tag >= MVS_RSVD_SLOTS) - return; - mvs_tag_clear(mvi, tag); } -static void mvs_tag_set(struct mvs_info *mvi, unsigned int tag) +void mvs_tag_set(struct mvs_info *mvi, unsigned int tag) { - void *bitmap = mvi->rsvd_tags; + void *bitmap = mvi->tags; set_bit(tag, bitmap); } -static int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out) +inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out) { unsigned int index, tag; - void *bitmap = mvi->rsvd_tags; + void *bitmap = mvi->tags; - index = find_first_zero_bit(bitmap, MVS_RSVD_SLOTS); + index = find_first_zero_bit(bitmap, mvi->tags_num); tag = index; - if (tag >= MVS_RSVD_SLOTS) + if (tag >= mvi->tags_num) return -SAS_QUEUE_FULL; mvs_tag_set(mvi, tag); *tag_out = tag; return 0; } +void mvs_tag_init(struct mvs_info *mvi) +{ + int i; + for (i = 0; i < mvi->tags_num; ++i) + mvs_tag_clear(mvi, i); +} + static struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev) { unsigned long i = 0, j = 0, hi = 0; @@ -696,7 +700,6 @@ static int mvs_task_prep(struct sas_task *task, struct mvs_info *mvi, int is_tmf struct mvs_task_exec_info tei; struct mvs_slot_info *slot; u32 tag = 0xdeadbeef, n_elem = 0; - struct request *rq; int rc = 0; if (!dev->port) { @@ -761,14 +764,9 @@ static int mvs_task_prep(struct sas_task *task, struct mvs_info *mvi, int is_tmf n_elem = task->num_scatter; } - rq = sas_task_find_rq(task); - if (rq) { - tag = rq->tag + MVS_RSVD_SLOTS; - } else { - rc = mvs_tag_alloc(mvi, &tag); - if (rc) - goto err_out; - } + rc = mvs_tag_alloc(mvi, &tag); + if (rc) + goto err_out; slot = &mvi->slot_info[tag]; @@ -871,7 +869,7 @@ int mvs_queue_command(struct sas_task *task, gfp_t gfp_flags) static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc) { u32 slot_idx = rx_desc & RXQ_SLOT_MASK; - mvs_tag_free(mvi, slot_idx); + mvs_tag_clear(mvi, slot_idx); } static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task, diff --git a/drivers/scsi/mvsas/mv_sas.h b/drivers/scsi/mvsas/mv_sas.h index 42caca5bb874..519edc796691 100644 --- a/drivers/scsi/mvsas/mv_sas.h +++ b/drivers/scsi/mvsas/mv_sas.h @@ -370,7 +370,8 @@ struct mvs_info { u32 chip_id; const struct mvs_chip_info *chip; - unsigned long *rsvd_tags; + int tags_num; + unsigned long *tags; /* further per-slot information */ struct mvs_phy phy[MVS_MAX_PHYS]; struct mvs_port port[MVS_MAX_PHYS]; @@ -423,6 +424,11 @@ struct mvs_task_exec_info { /******************** function prototype *********************/ void mvs_get_sas_addr(void *buf, u32 buflen); +void mvs_tag_clear(struct mvs_info *mvi, u32 tag); +void mvs_tag_free(struct mvs_info *mvi, u32 tag); +void mvs_tag_set(struct mvs_info *mvi, unsigned int tag); +int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out); +void mvs_tag_init(struct mvs_info *mvi); void mvs_iounmap(void __iomem *regs); int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex); void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard); diff --git a/drivers/scsi/myrs.c b/drivers/scsi/myrs.c index 04740f623a12..bf0546fc555f 100644 --- a/drivers/scsi/myrs.c +++ b/drivers/scsi/myrs.c @@ -499,14 +499,14 @@ static bool myrs_enable_mmio_mbox(struct myrs_hba *cs, /* Temporary dma mapping, used only in the scope of this function */ mbox = dma_alloc_coherent(&pdev->dev, sizeof(union myrs_cmd_mbox), &mbox_addr, GFP_KERNEL); - if (!mbox) + if (dma_mapping_error(&pdev->dev, mbox_addr)) return false; /* These are the base addresses for the command memory mailbox array */ cs->cmd_mbox_size = MYRS_MAX_CMD_MBOX * sizeof(union myrs_cmd_mbox); cmd_mbox = dma_alloc_coherent(&pdev->dev, cs->cmd_mbox_size, &cs->cmd_mbox_addr, GFP_KERNEL); - if (!cmd_mbox) { + if (dma_mapping_error(&pdev->dev, cs->cmd_mbox_addr)) { dev_err(&pdev->dev, "Failed to map command mailbox\n"); goto out_free; } @@ -521,7 +521,7 @@ static bool myrs_enable_mmio_mbox(struct myrs_hba *cs, cs->stat_mbox_size = MYRS_MAX_STAT_MBOX * sizeof(struct myrs_stat_mbox); stat_mbox = dma_alloc_coherent(&pdev->dev, cs->stat_mbox_size, &cs->stat_mbox_addr, GFP_KERNEL); - if (!stat_mbox) { + if (dma_mapping_error(&pdev->dev, cs->stat_mbox_addr)) { dev_err(&pdev->dev, "Failed to map status mailbox\n"); goto out_free; } @@ -534,7 +534,7 @@ static bool myrs_enable_mmio_mbox(struct myrs_hba *cs, cs->fwstat_buf = dma_alloc_coherent(&pdev->dev, sizeof(struct myrs_fwstat), &cs->fwstat_addr, GFP_KERNEL); - if (!cs->fwstat_buf) { + if (dma_mapping_error(&pdev->dev, cs->fwstat_addr)) { dev_err(&pdev->dev, "Failed to map firmware health buffer\n"); cs->fwstat_buf = NULL; goto out_free; diff --git a/drivers/scsi/pm8001/pm8001_ctl.c b/drivers/scsi/pm8001/pm8001_ctl.c index 4aace2c34f06..6b85016b4db3 100644 --- a/drivers/scsi/pm8001/pm8001_ctl.c +++ b/drivers/scsi/pm8001/pm8001_ctl.c @@ -596,7 +596,7 @@ static int pm8001_set_nvmd(struct pm8001_hba_info *pm8001_ha) struct pm8001_ioctl_payload *payload; DECLARE_COMPLETION_ONSTACK(completion); u8 *ioctlbuffer; - int ret; + u32 ret; u32 length = 1024 * 5 + sizeof(*payload) - 1; if (pm8001_ha->fw_image->size > 4096) { diff --git a/drivers/scsi/pm8001/pm8001_sas.c b/drivers/scsi/pm8001/pm8001_sas.c index 45b1af5a8d74..1215fc36862d 100644 --- a/drivers/scsi/pm8001/pm8001_sas.c +++ b/drivers/scsi/pm8001/pm8001_sas.c @@ -875,7 +875,6 @@ static void pm8001_dev_gone_notify(struct domain_device *dev) unsigned long flags = 0; struct pm8001_hba_info *pm8001_ha; struct pm8001_device *pm8001_dev = dev->lldd_dev; - struct domain_device *parent_dev = dev->parent; pm8001_ha = pm8001_find_ha_by_dev(dev); spin_lock_irqsave(&pm8001_ha->lock, flags); @@ -894,13 +893,7 @@ static void pm8001_dev_gone_notify(struct domain_device *dev) spin_lock_irqsave(&pm8001_ha->lock, flags); } PM8001_CHIP_DISP->dereg_dev_req(pm8001_ha, device_id); - - /* - * The phy array only contains local phys. Thus, we cannot clear - * phy_attached for a device behind an expander. - */ - if (!(parent_dev && dev_is_expander(parent_dev->dev_type))) - pm8001_ha->phy[pm8001_dev->attached_phy].phy_attached = 0; + pm8001_ha->phy[pm8001_dev->attached_phy].phy_attached = 0; pm8001_free_dev(pm8001_dev); } else { PM8001_DISC_DBG(pm8001_ha, diff --git a/drivers/scsi/pmcraid.c b/drivers/scsi/pmcraid.c index 4dc316ca5d28..f95a970db8fd 100644 --- a/drivers/scsi/pmcraid.c +++ b/drivers/scsi/pmcraid.c @@ -3973,7 +3973,9 @@ static const struct file_operations pmcraid_fops = { .open = pmcraid_chr_open, .fasync = pmcraid_chr_fasync, .unlocked_ioctl = pmcraid_chr_ioctl, - .compat_ioctl = compat_ptr_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = pmcraid_chr_ioctl, +#endif .llseek = noop_llseek, }; diff --git a/drivers/scsi/sd_zbc.c b/drivers/scsi/sd_zbc.c index b4cf3bb21567..e0bd4cf17230 100644 --- a/drivers/scsi/sd_zbc.c +++ b/drivers/scsi/sd_zbc.c @@ -136,7 +136,8 @@ static void *sd_zbc_alloc_report_buffer(struct scsi_disk *sdkp, while (bufsize >= SECTOR_SIZE) { buf = __vmalloc(bufsize, - GFP_KERNEL | __GFP_ZERO | __GFP_NORETRY); + GFP_KERNEL | __GFP_ZERO | __GFP_NORETRY, + PAGE_KERNEL); if (buf) { *buflen = bufsize; return buf; diff --git a/drivers/scsi/sg.c b/drivers/scsi/sg.c index 3a07ac8f34f8..001a3470b3aa 100644 --- a/drivers/scsi/sg.c +++ b/drivers/scsi/sg.c @@ -2214,17 +2214,9 @@ sg_remove_sfp_usercontext(struct work_struct *work) write_lock_irqsave(&sfp->rq_list_lock, iflags); while (!list_empty(&sfp->rq_list)) { srp = list_first_entry(&sfp->rq_list, Sg_request, entry); - list_del(&srp->entry); - write_unlock_irqrestore(&sfp->rq_list_lock, iflags); - sg_finish_rem_req(srp); - /* - * sg_rq_end_io() uses srp->parentfp. Hence, only clear - * srp->parentfp after blk_mq_free_request() has been called. - */ + list_del(&srp->entry); srp->parentfp = NULL; - - write_lock_irqsave(&sfp->rq_list_lock, iflags); } write_unlock_irqrestore(&sfp->rq_list_lock, iflags); diff --git a/drivers/soc/imx/gpc.c b/drivers/soc/imx/gpc.c index 8d0d05041be3..90a8b2c0676f 100644 --- a/drivers/soc/imx/gpc.c +++ b/drivers/soc/imx/gpc.c @@ -540,8 +540,6 @@ static int imx_gpc_remove(struct platform_device *pdev) return ret; } - of_node_put(pgc_node); - return 0; } diff --git a/drivers/soc/qcom/minidump_log.c b/drivers/soc/qcom/minidump_log.c index d0a75ad90fb1..b71f782cc6ea 100644 --- a/drivers/soc/qcom/minidump_log.c +++ b/drivers/soc/qcom/minidump_log.c @@ -855,7 +855,7 @@ static void md_dump_data(unsigned long addr, int nbytes, const char *name) if (__is_lm_address(p) && kern_addr_valid((unsigned long)p) && page_accessible(page_to_pfn(virt_to_page(p))) && - !get_kernel_nofault(data, p)) + !probe_kernel_address(p, data)) seq_buf_printf(md_cntxt_seq_buf, " %08x", data); else diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index 0ee0891d4c49..be993305546b 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -219,7 +219,7 @@ static const struct tcs_request *get_req_from_tcs(struct rsc_drv *drv, return NULL; } -static void __tcs_set_trigger(struct rsc_drv *drv, int tcs_id, bool trigger) +static void __tcs_trigger(struct rsc_drv *drv, int tcs_id, bool trigger) { u32 enable; @@ -294,23 +294,26 @@ static irqreturn_t tcs_tx_done(int irq, void *p) ipc_log_string(drv->ipc_log_ctx, "IRQ response: m=%d err=%d", i, err); - /* Clear AMC trigger & enable modes and + /* + * if wake tcs was re-purposed for sending active + * votes, clear AMC trigger & enable modes and * disable interrupt for this TCS */ - __tcs_set_trigger(drv, i, false); + if (!drv->tcs[ACTIVE_TCS].num_tcs) { + __tcs_trigger(drv, i, false); + /* + * Disable interrupt for this TCS to avoid being + * spammed with interrupts coming when the solver + * sends its wake votes. + */ + enable_tcs_irq(drv, i, false); + } skip: /* Reclaim the TCS */ write_tcs_reg(drv, RSC_DRV_CMD_ENABLE, i, 0); write_tcs_reg(drv, RSC_DRV_IRQ_CLEAR, 0, BIT(i)); spin_lock(&drv->lock); clear_bit(i, drv->tcs_in_use); - /* - * Disable interrupt for WAKE TCS to avoid being - * spammed with interrupts coming when the solver - * sends its wake votes. - */ - if (!drv->tcs[ACTIVE_TCS].num_tcs) - enable_tcs_irq(drv, i, false); spin_unlock(&drv->lock); if (req) rpmh_tx_done(req, err); @@ -436,7 +439,7 @@ static int tcs_write(struct rsc_drv *drv, const struct tcs_request *msg) spin_unlock(&drv->lock); __tcs_buffer_write(drv, tcs_id, 0, msg); - __tcs_set_trigger(drv, tcs_id, true); + __tcs_trigger(drv, tcs_id, true); done_write: spin_unlock_irqrestore(&tcs->lock, flags); diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 30c0ab1c56e0..04a38617d643 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -820,7 +820,7 @@ static u32 qcom_smem_get_item_count(struct qcom_smem *smem) if (IS_ERR_OR_NULL(ptable)) return SMEM_ITEM_COUNT; - info = (struct smem_info *)&ptable->entry[le32_to_cpu(ptable->num_entries)]; + info = (struct smem_info *)&ptable->entry[ptable->num_entries]; if (memcmp(info->magic, SMEM_INFO_MAGIC, sizeof(info->magic))) return SMEM_ITEM_COUNT; diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 8cf083b95900..9db6b91b5d7b 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -1393,9 +1393,6 @@ static int qcom_socinfo_probe(struct platform_device *pdev) SOCINFO_MINOR(le32_to_cpu(info->ver))); qs->attr.soc_id = kasprintf(GFP_KERNEL, "%d", socinfo_get_id()); - if (!qs->attr.soc_id || !qs->attr.revision) - return -ENOMEM; - if (socinfo_format >= SOCINFO_VERSION(0, 16)) { machine = socinfo_machine(le32_to_cpu(info->id)); esku = socinfo_get_esku_mapping(); diff --git a/drivers/soc/ti/knav_dma.c b/drivers/soc/ti/knav_dma.c index f238ce3d32fb..981a9014c9c4 100644 --- a/drivers/soc/ti/knav_dma.c +++ b/drivers/soc/ti/knav_dma.c @@ -420,7 +420,7 @@ static int of_channel_match_helper(struct device_node *np, const char *name, * @name: slave channel name * @config: dma configuration parameters * - * Return: Pointer to appropriate DMA channel on success or NULL on error. + * Returns pointer to appropriate DMA channel on success or error. */ void *knav_dma_open_channel(struct device *dev, const char *name, struct knav_dma_cfg *config) @@ -433,13 +433,13 @@ void *knav_dma_open_channel(struct device *dev, const char *name, if (!kdev) { pr_err("keystone-navigator-dma driver not registered\n"); - return NULL; + return (void *)-EINVAL; } chan_num = of_channel_match_helper(dev->of_node, name, &instance); if (chan_num < 0) { dev_err(kdev->dev, "No DMA instance with name %s\n", name); - return NULL; + return (void *)-EINVAL; } dev_dbg(kdev->dev, "initializing %s channel %d from DMA %s\n", @@ -450,7 +450,7 @@ void *knav_dma_open_channel(struct device *dev, const char *name, if (config->direction != DMA_MEM_TO_DEV && config->direction != DMA_DEV_TO_MEM) { dev_err(kdev->dev, "bad direction\n"); - return NULL; + return (void *)-EINVAL; } /* Look for correct dma instance */ @@ -462,7 +462,7 @@ void *knav_dma_open_channel(struct device *dev, const char *name, } if (!found) { dev_err(kdev->dev, "No DMA instance with name %s\n", instance); - return NULL; + return (void *)-EINVAL; } /* Look for correct dma channel from dma instance */ @@ -483,14 +483,14 @@ void *knav_dma_open_channel(struct device *dev, const char *name, if (!found) { dev_err(kdev->dev, "channel %d is not in DMA %s\n", chan_num, instance); - return NULL; + return (void *)-EINVAL; } if (atomic_read(&chan->ref_count) >= 1) { if (!check_config(chan, config)) { dev_err(kdev->dev, "channel %d config miss-match\n", chan_num); - return NULL; + return (void *)-EINVAL; } } diff --git a/drivers/spi/spi-loopback-test.c b/drivers/spi/spi-loopback-test.c index 3edcb5bf59f7..0f571ff13237 100644 --- a/drivers/spi/spi-loopback-test.c +++ b/drivers/spi/spi-loopback-test.c @@ -403,7 +403,7 @@ static void spi_test_dump_message(struct spi_device *spi, int i; u8 b; - dev_info(&spi->dev, " spi_msg@%p\n", msg); + dev_info(&spi->dev, " spi_msg@%pK\n", msg); if (msg->status) dev_info(&spi->dev, " status: %i\n", msg->status); @@ -413,15 +413,15 @@ static void spi_test_dump_message(struct spi_device *spi, msg->actual_length); list_for_each_entry(xfer, &msg->transfers, transfer_list) { - dev_info(&spi->dev, " spi_transfer@%p\n", xfer); + dev_info(&spi->dev, " spi_transfer@%pK\n", xfer); dev_info(&spi->dev, " len: %i\n", xfer->len); - dev_info(&spi->dev, " tx_buf: %p\n", xfer->tx_buf); + dev_info(&spi->dev, " tx_buf: %pK\n", xfer->tx_buf); if (dump_data && xfer->tx_buf) spi_test_print_hex_dump(" TX: ", xfer->tx_buf, xfer->len); - dev_info(&spi->dev, " rx_buf: %p\n", xfer->rx_buf); + dev_info(&spi->dev, " rx_buf: %pK\n", xfer->rx_buf); if (dump_data && xfer->rx_buf) spi_test_print_hex_dump(" RX: ", xfer->rx_buf, @@ -514,7 +514,7 @@ static int spi_check_rx_ranges(struct spi_device *spi, /* if still not found then something has modified too much */ /* we could list the "closest" transfer here... */ dev_err(&spi->dev, - "loopback strangeness - rx changed outside of allowed range at: %p\n", + "loopback strangeness - rx changed outside of allowed range at: %pK\n", addr); /* do not return, only set ret, * so that we list all addresses @@ -652,7 +652,7 @@ static int spi_test_translate(struct spi_device *spi, } dev_err(&spi->dev, - "PointerRange [%p:%p[ not in range [%p:%p[ or [%p:%p[\n", + "PointerRange [%pK:%pK[ not in range [%pK:%pK[ or [%pK:%pK[\n", *ptr, *ptr + len, RX(0), RX(SPI_TEST_MAX_SIZE), TX(0), TX(SPI_TEST_MAX_SIZE)); diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 68e4d921b77a..afeb80f624bd 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2061,16 +2061,6 @@ static acpi_status acpi_register_spi_device(struct spi_controller *ctlr, acpi_set_modalias(adev, acpi_device_hid(adev), spi->modalias, sizeof(spi->modalias)); - /* - * This gets re-tried in spi_probe() for -EPROBE_DEFER handling in case - * the GPIO controller does not have a driver yet. This needs to be done - * here too, because this call sets the GPIO direction and/or bias. - * Setting these needs to be done even if there is no driver, in which - * case spi_probe() will never get called. - */ - if (spi->irq < 0) - spi->irq = acpi_dev_gpio_irq_get(adev, 0); - acpi_device_set_enumerated(adev); adev->power.flags.ignore_parent = true; diff --git a/drivers/staging/android/ion/heaps/msm_ion_dma_buf.c b/drivers/staging/android/ion/heaps/msm_ion_dma_buf.c index 7e9f518001e8..6bd9dd286057 100644 --- a/drivers/staging/android/ion/heaps/msm_ion_dma_buf.c +++ b/drivers/staging/android/ion/heaps/msm_ion_dma_buf.c @@ -500,12 +500,11 @@ static int ion_sgl_sync_range(struct device *dev, struct scatterlist *sgl, break; if (i > 0) { - if (!get_dma_ops(dev)) - return 0; - - pr_warn_ratelimited("Partial cmo only supported with 1 segment\n" - "is dma_set_max_seg_size being set on dev:%s\n", - dev_name(dev)); + if (get_dma_ops(dev)) { + pr_warn_ratelimited("Partial cmo only supported with 1 segment\n" + "is dma_set_max_seg_size being set on dev:%s\n", + dev_name(dev)); + } return -EINVAL; } } diff --git a/drivers/staging/android/ion/ion.c b/drivers/staging/android/ion/ion.c index 343957103791..ce974bdfc7d0 100644 --- a/drivers/staging/android/ion/ion.c +++ b/drivers/staging/android/ion/ion.c @@ -221,7 +221,9 @@ static long ion_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) static const struct file_operations ion_fops = { .owner = THIS_MODULE, .unlocked_ioctl = ion_ioctl, - .compat_ioctl = compat_ptr_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = ion_ioctl, +#endif }; static int debug_shrink_set(void *data, u64 val) diff --git a/drivers/staging/axis-fifo/axis-fifo.c b/drivers/staging/axis-fifo/axis-fifo.c index 8abcfe2725ba..4dd2c8e9b787 100644 --- a/drivers/staging/axis-fifo/axis-fifo.c +++ b/drivers/staging/axis-fifo/axis-fifo.c @@ -400,7 +400,6 @@ static ssize_t axis_fifo_read(struct file *f, char __user *buf, } bytes_available = ioread32(fifo->base_addr + XLLF_RLR_OFFSET); - words_available = bytes_available / sizeof(u32); if (!bytes_available) { dev_err(fifo->dt_device, "received a packet of length 0\n"); ret = -EIO; @@ -411,7 +410,7 @@ static ssize_t axis_fifo_read(struct file *f, char __user *buf, dev_err(fifo->dt_device, "user read buffer too small (available bytes=%zu user buffer bytes=%zu)\n", bytes_available, len); ret = -EINVAL; - goto err_flush_rx; + goto end_unlock; } if (bytes_available % sizeof(u32)) { @@ -420,9 +419,11 @@ static ssize_t axis_fifo_read(struct file *f, char __user *buf, */ dev_err(fifo->dt_device, "received a packet that isn't word-aligned\n"); ret = -EIO; - goto err_flush_rx; + goto end_unlock; } + words_available = bytes_available / sizeof(u32); + /* read data into an intermediate buffer, copying the contents * to userspace when the buffer is full */ @@ -434,23 +435,18 @@ static ssize_t axis_fifo_read(struct file *f, char __user *buf, tmp_buf[i] = ioread32(fifo->base_addr + XLLF_RDFD_OFFSET); } - words_available -= copy; if (copy_to_user(buf + copied * sizeof(u32), tmp_buf, copy * sizeof(u32))) { ret = -EFAULT; - goto err_flush_rx; + goto end_unlock; } copied += copy; + words_available -= copy; } - mutex_unlock(&fifo->read_lock); - return bytes_available; - -err_flush_rx: - while (words_available--) - ioread32(fifo->base_addr + XLLF_RDFD_OFFSET); + ret = bytes_available; end_unlock: mutex_unlock(&fifo->read_lock); @@ -498,17 +494,11 @@ static ssize_t axis_fifo_write(struct file *f, const char __user *buf, return -EINVAL; } - /* - * In 'Store-and-Forward' mode, the maximum packet that can be - * transmitted is limited by the size of the FIFO, which is - * (C_TX_FIFO_DEPTH–4)*(data interface width/8) bytes. - * - * Do not attempt to send a packet larger than 'tx_fifo_depth - 4', - * otherwise a 'Transmit Packet Overrun Error' interrupt will be - * raised, which requires a reset of the TX circuit to recover. - */ - if (words_to_write > (fifo->tx_fifo_depth - 4)) + if (words_to_write > fifo->tx_fifo_depth) { + dev_err(fifo->dt_device, "tried to write more words [%u] than slots in the fifo buffer [%u]\n", + words_to_write, fifo->tx_fifo_depth); return -EINVAL; + } if (fifo->write_flags & O_NONBLOCK) { /* diff --git a/drivers/staging/comedi/comedi_buf.c b/drivers/staging/comedi/comedi_buf.c index 3df045b25cb3..3ef3ddabf139 100644 --- a/drivers/staging/comedi/comedi_buf.c +++ b/drivers/staging/comedi/comedi_buf.c @@ -369,7 +369,7 @@ static unsigned int comedi_buf_munge(struct comedi_subdevice *s, unsigned int count = 0; const unsigned int num_sample_bytes = comedi_bytes_per_sample(s); - if (!s->munge || (async->cmd.flags & CMDF_RAWDATA) || async->cmd.chanlist_len == 0) { + if (!s->munge || (async->cmd.flags & CMDF_RAWDATA)) { async->munge_count += num_bytes; count = num_bytes; } else { diff --git a/drivers/staging/fw-api/fw/enet.h b/drivers/staging/fw-api/fw/enet.h index d8f84c595287..54a561eb1db8 100644 --- a/drivers/staging/fw-api/fw/enet.h +++ b/drivers/staging/fw-api/fw/enet.h @@ -92,8 +92,8 @@ typedef PREPACK struct { } POSTPACK vlan_hdr_t; #define ETHERTYPE_IS_EAPOL_WAPI(typeorlen) \ - ((typeorlen) == ETHERTYPE_PAE || \ - (typeorlen) == ETHERTYPE_WAI) + ((typeorlen) == ETHERTYPE_PAE || \ + (typeorlen) == ETHERTYPE_WAI) #define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600) @@ -102,11 +102,11 @@ typedef PREPACK struct { #endif #ifndef ETHERTYPE_AARP -#define ETHERTYPE_AARP 0x80f3 /* Internal QCA AARP protocol */ +#define ETHERTYPE_AARP 0x80f3 /* Internal QCA AARP protocol */ #endif #ifndef ETHERTYPE_IPX -#define ETHERTYPE_IPX 0x8137 /* IPX over DIX protocol */ +#define ETHERTYPE_IPX 0x8137 /* IPX over DIX protocol */ #endif #ifndef ETHERTYPE_ARP @@ -133,18 +133,6 @@ typedef PREPACK struct { #define ETHERTYPE_PAE 0x888E /* EAP over LAN (EAPOL) */ #endif - #ifndef EAPOL_KEY_TYPE - #define EAPOL_KEY_TYPE 0x3 /* EAP over LAN (EAPOL) */ - #endif - - #ifndef EAPOL_PAIRKEY - #define EAPOL_PAIRKEY 0x008 - #endif - - #ifndef EAPOL_GRPKEY - #define EAPOL_GRPKEY 0x00 - #endif - #ifndef ETHERTYPE_WAI #define ETHERTYPE_WAI 0x88B4 /* WAPI */ #endif diff --git a/drivers/staging/fw-api/fw/htc_services.h b/drivers/staging/fw-api/fw/htc_services.h index 3e4fca244b1e..50d57596a0b0 100644 --- a/drivers/staging/fw-api/fw/htc_services.h +++ b/drivers/staging/fw-api/fw/htc_services.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2012, 2014-2017, 2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -64,9 +64,7 @@ typedef enum { /* WMI_CONTROL_SVC_WMAC3,4: WMI service for MACs 3 and 4 (where applicable) */ #define WMI_CONTROL_SVC_WMAC3 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,9) #define WMI_CONTROL_SVC_WMAC4 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,10) -/* SMD high prio service - common for all macs */ -#define WMI_CONTROL_SMD_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,11) -#define WMI_MAX_SERVICES 12 +#define WMI_MAX_SERVICES 11 #define NMI_CONTROL_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,0) #define NMI_DATA_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,1) @@ -95,18 +93,6 @@ typedef enum { */ #define HTT_DATA3_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,2) -/* HTT_DATA4_MSG_SVC - * H2T channel to transfer MSDU/MPDU queue info from host to target - */ -#define HTT_DATA4_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,3) - -/* H2T - Telemetry channel */ -#define HTT_TELEMETRY_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,4) -/* T2H - Telemetry channel 1 */ -#define HTT_TELEMETRY1_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,5) -/* T2H - Telemetry channel 2 */ -#define HTT_TELEMETRY2_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,6) - /* raw stream service (i.e. flash, tcmd, calibration apps) */ #define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0) diff --git a/drivers/staging/fw-api/fw/htt.h b/drivers/staging/fw-api/fw/htt.h index 7234768e9b81..e9d34066ff72 100644 --- a/drivers/staging/fw-api/fw/htt.h +++ b/drivers/staging/fw-api/fw/htt.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2026 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -266,29 +266,9 @@ * 3.136 Add htt_ext_present flag in htt_tx_tcl_global_seq_metadata. * 3.137 Add more HTT_SDWF_MSDUQ_CFG_IND_ERROR codes. * 3.138 Add T2H MLO_LATENCY_REQ, H2T _RESP msg defs. - * 3.139 Add CLASS_INFO_IDX field in MLO_R_PEER_MAP msg. - * 3.140 Add H2T MPDUQ_AND_MSDUQ_INFO_HDR and MPDUQ_OF_MSDUQ_INFO defs. - * 3.141 Add H2T HTT_AST_INFO for RxOLE. - * 3.142 Add T2H GLOBAL_PEER_ID_UNMAP def, update H2T MPDUQ_OR_MSDUQ_INFO def. - * 3.143 Add T2H HAPS msg def. - * 3.144 Add svc_inst_req_type in htt_h2t_mpduq_or_msduq_info. - * 3.145 Add 3rd bit for rx_hdr_len in RX_RING_SELECTION_CFG - * 3.146 Add HTT_RXOLE_ASE_STATUS_RING def. - * 3.147 Add direct_refill flag in SRING_SETUP msg. - * 3.148 Add HTT_PEER_CFR_CAPTURE_BW_320MHZ def. - * 3.149 Add SAM fields in MPDUQ_OR_MSDUQ_INFO. - * 3.150 Add htt_reg_write_selection definitions. - * 3.151 Add HTT_H2T DAL_MODE_INFO def. - * 3.152 Add decap_type in htt_rx_peer_metadata_v1b. - * 3.153 Add passthru_pkt flag in rx_peer_metadata structs. - * 3.154 Add T2H PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP msg def. - * 3.155 Add rxmon hdrlen specs in rx_ring_selection_cfg_t. - * 3.156 Add qdata_consent_pkt flag in rx_peer_metadata_v1a and v2. - * 3.157 Add TCL_METADATA_V3 defs. - * 3.158 Add more fields in htt_tx_monitor_cfg_t. */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 158 +#define HTT_CURRENT_VERSION_MINOR 138 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -585,7 +565,6 @@ PREPACK struct htt_option_tlv_support_tx_msdu_desc_ext_t { * should be used: * V1 -> use htt_tx_tcl_metadata struct * V2 -> use htt_tx_tcl_metadata_v2 struct - * V3 -> use htt_tx_tcl_metadata_v3 struct * Old FW will only support V1. * New FW will support V2. New FW will still support V1, at least during * a transition period. @@ -611,17 +590,11 @@ PREPACK struct htt_option_tlv_support_tx_msdu_desc_ext_t { * and the FW will crash in wal_tx_de_fast.c. For version 2.1 and * above we will use htt_tx_tcl_svc_class_id_metadata.ast_index * in TCLV2 command and do the dynamic AST allocations. - * - * Apr 2026: Added HTT_OPTION_TLV_TCL_METADATA_V3. - * This version supports the updated tcl_data_cmd introduced in Boron. - * All fields are identical to V2; however, the field ordering has been - * modified to accommodate MAC requirements. */ enum HTT_OPTION_TLV_TCL_METADATA_VER_VALUES { HTT_OPTION_TLV_TCL_METADATA_V1 = 1, HTT_OPTION_TLV_TCL_METADATA_V2 = 2, - HTT_OPTION_TLV_TCL_METADATA_V3 = 3, - /* values 4-20 reserved */ + /* values 3-20 reserved */ HTT_OPTION_TLV_TCL_METADATA_V21 = 21, }; @@ -794,10 +767,7 @@ typedef enum { HTT_STATS_AST_ENTRY_TAG = 132, /* htt_ast_entry_tlv */ HTT_STATS_TX_PDEV_BE_DL_MU_OFDMA_STATS_TAG = 133, /* htt_tx_pdev_dl_be_mu_ofdma_sch_stats_tlv, TOPIC=advanced */ HTT_STATS_TX_PDEV_BE_UL_MU_OFDMA_STATS_TAG = 134, /* htt_tx_pdev_ul_be_mu_ofdma_sch_stats_tlv, TOPIC=advanced */ - HTT_STATS_TX_PDEV_RATE_BE_BN_OFDMA_TAG = 135, /* htt_stats_tx_pdev_rate_be_bn_ofdma_tlv */ - /* retain deprecated name as an alias */ - HTT_STATS_TX_PDEV_RATE_STATS_BE_OFDMA_TAG = - HTT_STATS_TX_PDEV_RATE_BE_BN_OFDMA_TAG, + HTT_STATS_TX_PDEV_RATE_STATS_BE_OFDMA_TAG = 135, /* htt_tx_pdev_rate_stats_be_ofdma_tlv */ HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_TAG = 136, /* htt_rx_pdev_ul_mumimo_trig_be_stats_tlv, TOPIC=advanced */ HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG = 137, /* htt_tx_selfgen_be_err_stats_tlv, TOPIC=advanced */ HTT_STATS_TX_SELFGEN_BE_STATS_TAG = 138, /* htt_tx_selfgen_be_stats_tlv, TOPIC=advanced */ @@ -805,10 +775,7 @@ typedef enum { HTT_STATS_TX_PDEV_BE_UL_MU_MIMO_STATS_TAG = 140, /* htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv */ HTT_STATS_RX_PDEV_BE_UL_MIMO_USER_STATS_TAG = 141, /* htt_rx_pdev_be_ul_mimo_user_stats_tlv */ HTT_STATS_RX_RING_STATS_TAG = 142, /* htt_rx_fw_ring_stats_tlv_v */ - HTT_STATS_RX_PDEV_BE_BN_UL_TRIG_TAG = 143, /* htt_stats_rx_pdev_be_bn_ul_trig_tlv, TOPIC=advanced */ - /* retain deprecated name as an alias */ - HTT_STATS_RX_PDEV_BE_UL_TRIG_STATS_TAG = - HTT_STATS_RX_PDEV_BE_BN_UL_TRIG_TAG, + HTT_STATS_RX_PDEV_BE_UL_TRIG_STATS_TAG = 143, /* htt_rx_pdev_be_ul_trigger_stats_tlv, TOPIC=advanced */ HTT_STATS_TX_PDEV_SAWF_RATE_STATS_TAG = 144, /* htt_tx_pdev_rate_stats_sawf_tlv, TOPIC=advanced */ HTT_STATS_STRM_GEN_MPDUS_TAG = 145, /* htt_stats_strm_gen_mpdus_tlv_t */ HTT_STATS_STRM_GEN_MPDUS_DETAILS_TAG = 146, /* htt_stats_strm_gen_mpdus_details_tlv_t */ @@ -839,8 +806,7 @@ typedef enum { HTT_STATS_TX_PDEV_AP_EDCA_PARAMS_STATS_TAG = 171, /* htt_tx_pdev_ap_edca_params_stats_tlv_v, TOPIC=advanced */ HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG = 172, /* htt_txbf_ofdma_ax_steer_mpdu_stats_tlv, TOPIC=advanced */ HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG = 173, /* htt_txbf_ofdma_be_steer_mpdu_stats_tlv, TOPIC=advanced */ - HTT_STATS_PEER_OFDMA_STATS_TAG = 174, /* htt_stats_peer_ofdma_stats_tlv */ - HTT_STATS_PEER_AX_OFDMA_STATS_TAG = HTT_STATS_PEER_OFDMA_STATS_TAG, /* DEPRECATED */ + HTT_STATS_PEER_AX_OFDMA_STATS_TAG = 174, /* htt_peer_ax_ofdma_stats_tlv */ HTT_STATS_TX_PDEV_MU_EDCA_PARAMS_STATS_TAG = 175, /* htt_tx_pdev_mu_edca_params_stats_tlv_v, TOPIC=advanced */ HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176, /* htt_pdev_mbssid_ctrl_frame_stats_tlv */ HTT_STATS_TX_PDEV_MLO_ABORT_TAG = 177, /* htt_tx_pdev_stats_mlo_abort_tlv_v */ @@ -874,77 +840,10 @@ typedef enum { HTT_STATS_PDEV_RTT_DELAY_TAG = 205, /* htt_stats_pdev_rtt_delay_tlv */ HTT_STATS_PDEV_AOA_TAG = 206, /* htt_stats_pdev_aoa_tlv */ HTT_STATS_PDEV_FTM_TPCCAL_TAG = 207, /* htt_stats_pdev_ftm_tpccal_tlv */ - HTT_STATS_PDEV_UL_MUMIMO_GRP_STATS_TAG = 208, /* htt_stats_pdev_ul_mumimo_grp_stats_tlv */ - HTT_STATS_PDEV_UL_MUMIMO_DENYLIST_STATS_TAG = 209, /* htt_stats_pdev_ul_mumimo_denylist_stats_tlv */ - HTT_STATS_PDEV_UL_MUMIMO_SEQ_TERM_STATS_TAG = 210, /* htt_stats_pdev_ul__mumimo_seq_term_stats_tlv */ - HTT_STATS_PDEV_UL_MUMIMO_HIST_INELIGIBILITY_TAG = 211, /* htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv */ - HTT_STATS_PHY_PAPRD_PB_TAG = 212, /* htt_stats_phy_paprd_pb_tlv */ - HTT_STATS_HDS_PROF_STATS_TAG = 213, /* htt_stat_hds_prof_stats_tlv */ - HTT_STATS_TX_PDEV_MDSB_NUM_USERS_HISTOGRAM_TAG = 214, /* htt_stats_tx_pdev_mdsb_num_users_histogram_tlv */ - /* preserve old name as an alias for the corrected name */ - HTT_STATS_TX_PDEV_MDSB_NUM_USERS_HISTOGRAM_TLV_TAG = - HTT_STATS_TX_PDEV_MDSB_NUM_USERS_HISTOGRAM_TAG, - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_TAG = 215, /* htt_stats_tx_pdev_pending_seq_cnt_on_sched_post_hist_tlv */ - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_TAG = 216, /* htt_stats_tx_pdev_pending_seq_cnt_in_hwq_hist_tlv */ - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_TAG = 217, /* htt_stats_tx_pdev_pending_seq_cnt_in_txq_hist_tlv */ - HTT_STATS_SCHED_TXQ_EARLY_COMPL_TAG = 218, /* htt_stats_sched_txq_early_compl_tlv */ - HTT_STATS_RX_PDEV_BN_UL_OFDMA_USER_TAG = 219, /* htt_stats_rx_pdev_bn_ul_ofdma_user_tlv */ - HTT_STATS_TX_SELFGEN_BN_ERR_TAG = 220, /* htt_stats_tx_selfgen_bn_err_tlv, TOPIC=advanced */ - HTT_STATS_TX_SELFGEN_BN_TAG = 221, /* htt_stats_tx_selfgen_bn_tlv, TOPIC=advanced */ - HTT_STATS_TX_SELFGEN_BN_SCHED_STATUS_TAG = 222, /* htt_stats_tx_selfgen_bn_sched_status_tlv, TOPIC=advanced */ - HTT_STATS_TX_PDEV_BN_DL_MU_OFDMA_STATS_TAG = 223, /* htt_stats_tx_pdev_bn_dl_mu_ofdma_stats_tlv, TOPIC=advanced */ - HTT_STATS_TX_PDEV_BN_UL_MU_OFDMA_STATS_TAG = 224, /* htt_stats_tx_pdev_bn_ul_mu_ofdma_stats_tlv, TOPIC=advanced */ - HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TAG = 225, /* htt_stats_rx_peer_tid_reo_queue_ba_tlv */ - HTT_STATS_TXBF_OFDMA_BN_NDPA_TAG = 226, /* htt_stats_txbf_ofdma_bn_ndpa_tlv */ - HTT_STATS_TXBF_OFDMA_BN_NDP_TAG = 227, /* htt_stats_txbf_ofdma_bn_ndp_tlv */ - HTT_STATS_TXBF_OFDMA_BN_BRP_TAG = 228, /* htt_stats_txbf_ofdma_bn_brp_tlv */ - HTT_STATS_TXBF_OFDMA_BN_STEER_TAG = 229, /* htt_stats_txbf_ofdma_bn_steer_tlv */ - HTT_STATS_TXBF_OFDMA_BN_STEER_MPDU_TAG = 230, /* htt_stats_txbf_ofdma_bn_steer_mpdu_tlv */ - HTT_STATS_TXBF_OFDMA_BN_PARBW_TAG = 231, /* htt_stats_txbf_ofdma_bn_parbw_tlv */ - HTT_STATS_OPTIONAL_CONFIGS_TAG = 232, /* htt_stats_optional_configs_tlv */ - HTT_STATS_PDEV_SAM_TAG = 233, /* htt_stats_pdev_sam_tlv */ - HTT_STATS_FTM_TAG = 234, /* htt_stats_ftm_tlv */ - HTT_STATS_PDEV_FTM_TPCCAL_EXT_TAG = 235, /* htt_stats_pdev_ftm_tpccal_ext_tlv */ - HTT_STATS_TX_PDEV_BN_RATE_TAG = 236, /* htt_stats_tx_pdev_bn_rate_tlv */ - HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BN_TAG = 237, /* htt_stats_rx_pdev_ul_mumimo_trig_bn_tlv, TOPIC=advanced */ - HTT_STATS_RX_PDEV_BN_UL_MIMO_USER_TAG = 238, /* htt_stats_rx_pdev_bn_ul_mimo_user_tlv */ - HTT_STATS_TX_PDEV_BN_UL_MU_MIMO_TAG = 239, /* htt_stats_tx_pdev_bn_ul_mu_mimo_tlv */ - /* HTT_STATS_PDEV_ANI_HIST_TAG: - * htt_stats_pdev_ani_hist_tlv - * ani_hist_type: - * 0 = 1 sec, - * 1 = granular - * 2 = 1 sec disabled - * 3 = granular disabled - */ - HTT_STATS_PDEV_ANI_HIST_TAG = 240, - HTT_STATS_ANI_SCALAR_TAG = 241, /* htt_stats_ani_scalar_tlv */ - HTT_STATS_ANI_PKT_CNT_TAG = 242, /* htt_stats_ani_pkt_cnt_tlv */ - HTT_STATS_ANI_CRC_PASS_TAG = 243, /* htt_stats_ani_crc_pass_tlv */ - HTT_STATS_ANI_PER_BLK_ERR_TAG = 244, /* htt_stats_ani_per_blk_err_tlv */ - HTT_STATS_ANI_OTA_ERR_TAG = 245, /* htt_stats_ani_ota_err_tlv */ - HTT_STATS_RESET_HISTORY_TAG = 246, /* htt_stats_reset_history_tlv */ - HTT_STATS_REGDB_CTRY_TAG = 247, /* htt_stats_regdb_ctry_tlv */ - HTT_STATS_REGDB_REGDOMAIN_TAG = 248, /* htt_stats_regdb_regdomain_tlv */ - HTT_STATS_REG_6G_TAG = 249, /* htt_stats_reg_6g_tlv*/ - HTT_STATS_REG_6G_CH_PWR_INFO_TAG = 250, /* htt_stats_reg_6g_ch_power_info_tlv */ - HTT_STATS_REG_6G_OOBE_TAG = 251, /* htt_stats_reg_6g_oobe_tlv*/ - HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_TAG = 252, /* htt_stats_tx_selfgen_resp_frame_stats_tlv */ - HTT_STATS_DPD_HALPHY_TAG = 253, /* htt_stats_dpd_halphy_tlv */ - HTT_STATS_DPD_HW_CAL_PARAMS_TAG = 254, /* htt_stats_dpd_hw_cal_params_tlv */ - HTT_STATS_DPD_HW_CAL_RESULTS_TAG = 255, /* htt_stats_dpd_hw_cal_results_tlv */ - HTT_STATS_TX_PDEV_TXOP_DUR_TAG = 256, /* htt_stats_tx_pdev_txop_dur_tlv */ - HTT_STATS_TXQ_COMBINED_SEQ_STATE_TAG = 257, /* htt_stats_txq_combined_seq_state_tlv */ - HTT_STATS_CTL_TAG = 258, /* htt_stats_ctl_tlv */ - HTT_STATS_ENHANCED_CTL_TAG = 259, /* htt_stats_enhanced_ctl_tlv */ - HTT_STATS_NPCA_TAG = 260, /* htt_stats_npca_tlv */ - HTT_STATS_SCHED_TXQ_TX_MODE_SIMPLIFIED_TAG = 261, /* htt_stats_sched_txq_tx_mode_simplified_tlv */ - HTT_STATS_SCHED_TXQ_TX_MODE_WINNER_TAG = 262, /* htt_stats_sched_txq_tx_mode_winner_tlv */ - HTT_STATS_DFS_RADAR_HISTORY_TAG = 263, /* htt_stats_dfs_radar_history_tlv */ - HTT_STATS_DFS_INI_TAG = 264, /* htt_stats_dfs_ini_tlv */ - HTT_STATS_DFS_IPC_RING_TAG = 265, /* htt_stats_dfs_ipc_ring_tlv */ - HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_TAG = 266, /* htt_stats_phy_dpd_debug_chain_v1_tlv */ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TAG = 267, /* htt_stats_phy_tpc_debug_chain_v1_tlv */ + HTT_STATS_PDEV_UL_MUMIMO_GRP_STATS_TAG = 208, /* htt_stats_pdev_ulmumimo_grp_stats_tlv */ + HTT_STATS_PDEV_UL_MUMIMO_DENYLIST_STATS_TAG = 209, /* htt_stats_pdev_ulmumimo_denylist_stats_tlv */ + HTT_STATS_PDEV_UL_MUMIMO_SEQ_TERM_STATS_TAG = 210, /* htt_stats_pdev_ulmumimo_seq_term_stats_tlv */ + HTT_STATS_PDEV_UL_MUMIMO_HIST_INELIGIBILITY_TAG = 211, /* htt_stats_pdev_ulmumimo_hist_ineligibility_tlv */ HTT_STATS_MAX_TAG, } htt_stats_tlv_tag_t; @@ -979,51 +878,47 @@ typedef htt_stats_tlv_tag_t htt_tlv_tag_t; /*=== host -> target messages ===============================================*/ enum htt_h2t_msg_type { - HTT_H2T_MSG_TYPE_VERSION_REQ = 0x0, - HTT_H2T_MSG_TYPE_TX_FRM = 0x1, - HTT_H2T_MSG_TYPE_RX_RING_CFG = 0x2, - HTT_H2T_MSG_TYPE_STATS_REQ = 0x3, - HTT_H2T_MSG_TYPE_SYNC = 0x4, - HTT_H2T_MSG_TYPE_AGGR_CFG = 0x5, - HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 0x6, - DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX = 0x7, /* no longer used */ - HTT_H2T_MSG_TYPE_WDI_IPA_CFG = 0x8, - HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ = 0x9, - HTT_H2T_MSG_TYPE_AGGR_CFG_EX = 0xa, /* per vdev amsdu subfrm limit */ - HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, - HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, - HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY = 0xd, - HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY = 0xe, - HTT_H2T_MSG_TYPE_RFS_CONFIG = 0xf, - HTT_H2T_MSG_TYPE_EXT_STATS_REQ = 0x10, - HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, - HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG = 0x12, - HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG = 0x13, - HTT_H2T_MSG_TYPE_CHAN_CALDATA = 0x14, - HTT_H2T_MSG_TYPE_RX_FISA_CFG = 0x15, - HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG = 0x16, - HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17, - HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE = 0x18, - HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG = 0x19, - HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG = 0x1a, - HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b, - HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ = 0x1c, - HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ = 0x1d, - HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ = 0x1e, - HTT_H2T_MSG_TYPE_MSI_SETUP = 0x1f, - HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ = 0x20, - HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP = 0x21, + HTT_H2T_MSG_TYPE_VERSION_REQ = 0x0, + HTT_H2T_MSG_TYPE_TX_FRM = 0x1, + HTT_H2T_MSG_TYPE_RX_RING_CFG = 0x2, + HTT_H2T_MSG_TYPE_STATS_REQ = 0x3, + HTT_H2T_MSG_TYPE_SYNC = 0x4, + HTT_H2T_MSG_TYPE_AGGR_CFG = 0x5, + HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 0x6, + DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX = 0x7, /* no longer used */ + HTT_H2T_MSG_TYPE_WDI_IPA_CFG = 0x8, + HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ = 0x9, + HTT_H2T_MSG_TYPE_AGGR_CFG_EX = 0xa, /* per vdev amsdu subfrm limit */ + HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, + HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, + HTT_H2T_MSG_TYPE_ADD_WDS_ENTRY = 0xd, + HTT_H2T_MSG_TYPE_DELETE_WDS_ENTRY = 0xe, + HTT_H2T_MSG_TYPE_RFS_CONFIG = 0xf, + HTT_H2T_MSG_TYPE_EXT_STATS_REQ = 0x10, + HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, + HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG = 0x12, + HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG = 0x13, + HTT_H2T_MSG_TYPE_CHAN_CALDATA = 0x14, + HTT_H2T_MSG_TYPE_RX_FISA_CFG = 0x15, + HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG = 0x16, + HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17, + HTT_H2T_MSG_TYPE_HOST_PADDR_SIZE = 0x18, + HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG = 0x19, + HTT_H2T_MSG_TYPE_VDEVS_TXRX_STATS_CFG = 0x1a, + HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b, + HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ = 0x1c, + HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ = 0x1d, + HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ = 0x1e, + HTT_H2T_MSG_TYPE_MSI_SETUP = 0x1f, + HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ = 0x20, + HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP = 0x21, HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET = 0x22, - HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP = 0x23, - HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP = 0x24, - HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG = 0x25, - HTT_H2T_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP = 0x26, - HTT_H2T_MSG_TYPE_SDWF_MSDUQ_RECFG_REQ = 0x27, - HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_RESP = 0x28, - HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR = 0x29, - HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO = 0x2a, - HTT_H2T_MSG_TYPE_AST_INFO = 0x2b, - HTT_H2T_MSG_TYPE_DAL_MODE_INFO = 0x2c, + HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP = 0x23, + HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP = 0x24, + HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG = 0x25, + HTT_H2T_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP = 0x26, + HTT_H2T_MSG_TYPE_SDWF_MSDUQ_RECFG_REQ = 0x27, + HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_RESP = 0x28, /* keep this last */ HTT_H2T_NUM_MSGS @@ -2967,231 +2862,6 @@ PREPACK struct htt_tx_tcl_metadata_v2 { * End V2 Version of TCL Data Command *-----------------------------------------------------------------*/ - -/*------------------------------------------------------------------ - * V3 Version of TCL Data Command - * V3 Version to support peer_id, vdev_id, svc_class_id and - * MLO global_seq all flavours of TCL Data Cmd. same fields as V2, - * but the ordering of the fields changes. - *-----------------------------------------------------------------*/ - -typedef struct { - A_UINT32 - valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ - vdev_id: 8, - pdev_id: 2, - host_inspected:1, - rsvd: 2, - /* type: vdev_id based or peer_id or svc_id or global seq based */ - type: 2, - /* padding: these 16 bits cannot be used by FW for the tcl command */ - padding: 16; -} htt_tx_tcl_vdev_metadata_v3; - -typedef struct { - A_UINT32 - valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ - peer_id: 13, - /* type: vdev_id based or peer_id or svc_id or global seq based */ - type: 2, - /* padding: these 16 bits cannot be used by FW for the tcl command */ - padding: 16; -} htt_tx_tcl_peer_metadata_v3; - -typedef struct { - A_UINT32 - valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ - svc_class_id: 8, - /* ast_index: - * Indicates to firmware the AST index to be used for AST Override - */ - ast_index: 3, - rsvd: 2, - /* type: vdev_id based or peer_id or svc_id or global seq based */ - type: 2, - /* padding: these 16 bits cannot be used by FW for the tcl command */ - padding: 16; -} htt_tx_tcl_svc_class_id_metadata_v3; - -typedef struct { - A_UINT32 - global_seq_no: 12, - host_inspected: 1, - htt_ext_present:1, - /* type: vdev_id based or peer_id or svc_id or global seq based */ - type: 2, - /* padding: these 16 bits cannot be used by FW for the tcl command */ - padding: 16; -} htt_tx_tcl_global_seq_metadata_v3; - -PREPACK struct htt_tx_tcl_metadata_v3 { - union { - htt_tx_tcl_vdev_metadata_v3 vdev_meta_v3; - htt_tx_tcl_peer_metadata_v3 peer_meta_v3; - htt_tx_tcl_svc_class_id_metadata_v3 svc_class_id_meta_v3; - htt_tx_tcl_global_seq_metadata_v3 global_seq_meta_v3; - }; -} POSTPACK; - -/* ===================================================================== - * Common fields - * ===================================================================== */ - -/* type field */ -#define HTT_TX_TCL_METADATA_TYPE_V3_M 0x0000C000 -#define HTT_TX_TCL_METADATA_TYPE_V3_S 14 - -/* valid htt ext (used by VDEV / PEER / SVC metadata) */ -#define HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID_M 0x00000001 -#define HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID_S 0 - - -/* ===================================================================== - * VDEV V3 metadata - * ===================================================================== */ - -#define HTT_TX_TCL_METADATA_V3_VDEV_ID_M 0x000001FE -#define HTT_TX_TCL_METADATA_V3_VDEV_ID_S 1 - -#define HTT_TX_TCL_METADATA_V3_PDEV_ID_M 0x00000600 -#define HTT_TX_TCL_METADATA_V3_PDEV_ID_S 9 - -#define HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_M 0x00000800 -#define HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_S 11 - - -/* ===================================================================== - * PEER V3 metadata - * ===================================================================== */ - -#define HTT_TX_TCL_METADATA_V3_PEER_ID_M 0x00003FFE -#define HTT_TX_TCL_METADATA_V3_PEER_ID_S 1 - - -/* ===================================================================== - * SVC CLASS ID metadata - * ===================================================================== */ - -#define HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_M 0x000001FE -#define HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_S 1 - -#define HTT_TX_TCL_METADATA_AST_INDEX_M 0x00000E00 -#define HTT_TX_TCL_METADATA_AST_INDEX_S 9 - - -/* ===================================================================== - * Global Sequence Number metadata - * ===================================================================== */ - -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_M 0x00000FFF -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_S 0 - -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_M 0x00001000 -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_S 12 - -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_M 0x00002000 -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_S 13 - -/*----- Get and Set V3 type field in Vdev, Peer, Svc_Class_Id, Global_seq_no */ -#define HTT_TX_TCL_METADATA_TYPE_V3_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_TYPE_V3_M) >> \ - HTT_TX_TCL_METADATA_TYPE_V3_S) -#define HTT_TX_TCL_METADATA_TYPE_V3_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_TYPE_V3, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_TYPE_V3_S)); \ - } while (0) - -#define HTT_TX_TCL_METADATA_V3_VALID_HTT_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID_M) >> \ - HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID_S) -#define HTT_TX_TCL_METADATA_V3_VALID_HTT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_VALID_HTT_EXT_ID_S)); \ - } while (0) - -/*----- Get and Set V3 type field in Vdev meta fields ----*/ -#define HTT_TX_TCL_METADATA_V3_VDEV_ID_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_VDEV_ID_M) >> \ - HTT_TX_TCL_METADATA_V3_VDEV_ID_S) -#define HTT_TX_TCL_METADATA_V3_VDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_VDEV_ID_S)); \ - } while (0) - -#define HTT_TX_TCL_METADATA_V3_PDEV_ID_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_PDEV_ID_M) >> \ - HTT_TX_TCL_METADATA_V3_PDEV_ID_S) -#define HTT_TX_TCL_METADATA_V3_PDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_PDEV_ID_S)); \ - } while (0) - -#define HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_M) >> \ - HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_S) -#define HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_HOST_INSPECTED, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_HOST_INSPECTED_S)); \ - } while (0) - -/*----- Get and Set V3 type field in Peer meta fields ----*/ -#define HTT_TX_TCL_METADATA_V3_PEER_ID_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_PEER_ID_M) >> \ - HTT_TX_TCL_METADATA_V3_PEER_ID_S) -#define HTT_TX_TCL_METADATA_V3_PEER_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_PEER_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_PEER_ID_S)); \ - } while (0) - -/*----- Get and Set V3 type field in Service Class fields ----*/ -#define HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_M) >> \ - HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_S) -#define HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_SVC_CLASS_ID_S)); \ - } while (0) - -/*----- Get and Set V3 type field in Global sequence fields ----*/ -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_M) >> \ - HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_S) -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HOST_INSPECTED_S)); \ - } while (0) - -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_M) >> \ - HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_S) -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_GLBL_SEQ_NO_S)); \ - } while (0) - -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_GET(_var) \ - (((_var) & HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_M) >> \ - HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_S) -#define HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT, _val); \ - ((_var) |= ((_val) << HTT_TX_TCL_METADATA_V3_GLBL_SEQ_HTT_EXT_PRESENT_S)); \ - } while (0) - -/*------------------------------------------------------------------ - * End V3 Version of TCL Data Command - *-----------------------------------------------------------------*/ - - typedef enum { HTT_TX_FW2WBM_TX_STATUS_OK, HTT_TX_FW2WBM_TX_STATUS_DROP, @@ -5786,8 +5456,7 @@ PREPACK struct htt_sring_setup_t { prefetch_timer_cfg: 3, response_required: 1, ipa_drop_flag: 1, - direct_refill: 1, - reserved1: 10; + reserved1: 11; A_UINT32 ipa_drop_low_threshold: 8, ipa_drop_high_threshold: 8, reserved: 16; @@ -5817,10 +5486,6 @@ enum htt_srng_ring_id { HTT_LPASS_TO_FW_RXBUF_RING, /* new LPASS to FW refill ring to recycle rx buffers */ HTT_HOST3_TO_FW_RXBUF_RING, /* used by host for EasyMesh feature */ HTT_HOST4_TO_FW_RXBUF_RING, /* fourth ring used by host to provide buffers for MGMT packets */ - HTT_RXDMA_WBM_BUF0_RING, /* used for SFE Datapath */ - HTT_RXDMA_WBM_BUF1_RING, /* used for MGMT Datapath */ - HTT_RXDMA_WBM_BUF2_RING, /* used for PPE path */ - HTT_RXOLE_ASE_STATUS_RING, /* RxOLE2SW ASE Status ring */ /* Add Other SRING which can't be directly configured by host software above this line */ }; @@ -6145,27 +5810,6 @@ enum htt_srng_ring_id { ((_var) |= ((_val) << HTT_SRING_SETUP_RESPONSE_REQUIRED_S)); \ } while (0) -#define HTT_SRING_SETUP_IPA_DROP_FLAG_M 0x00100000 -#define HTT_SRING_SETUP_IPA_DROP_FLAG_S 20 -#define HTT_SRING_SETUP_IPA_DROP_FLAG_GET(_var) \ - (((_var) & HTT_SRING_SETUP_IPA_DROP_FLAG_M) >> \ - HTT_SRING_SETUP_IPA_DROP_FLAG_S) -#define HTT_SRING_SETUP_IPA_DROP_FLAG_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_IPA_DROP_FLAG, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_IPA_DROP_FLAG_S)); \ - } while (0) - -#define HTT_SRING_SETUP_DIRECT_REFILL_M 0x00200000 -#define HTT_SRING_SETUP_DIRECT_REFILL_S 21 -#define HTT_SRING_SETUP_DIRECT_REFILL_GET(_var) \ - (((_var) & HTT_SRING_SETUP_DIRECT_REFILL_M) >> \ - HTT_SRING_SETUP_DIRECT_REFILL_S) -#define HTT_SRING_SETUP_DIRECT_REFILL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_SRING_SETUP_DIRECT_REFILL, _val); \ - ((_var) |= ((_val) << HTT_SRING_SETUP_DIRECT_REFILL_S)); \ - } while (0) /** * @brief host -> target RX ring selection config message @@ -6184,7 +5828,7 @@ enum htt_srng_ring_id { * |-----+--+--+--+--+--+-----------------+----+---+---+---+---------------| * |rsvd1|ED|DT|OV|PS|SS| ring_id | pdev_id | msg_type | * |--------------------------+-----+-----+--------------------------------| - * |rsvd2|HE|RX|RXHDL| CLD | CLC | CLM | ring_buffer_size | + * | rsvd2 |RX|RXHDL| CLD | CLC | CLM | ring_buffer_size | * |-----------------------------------------------------------------------| * | packet_type_enable_flags_0 | * |-----------------------------------------------------------------------| @@ -6218,7 +5862,6 @@ enum htt_srng_ring_id { * CLD = config_length_data * RXHDL = rx_hdr_len * RX = rxpcu_filter_enable_flag - * HE = rx_hdr_len extension * The message is interpreted as follows: * dword0 - b'0:7 - msg_type: This will be set to * 0xc (HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG) @@ -6243,11 +5886,7 @@ enum htt_srng_ring_id { * newer packet_type_enable_data_flags_* are valid or not * If not set, will use pkt_type_enable_flags for both status * and full pkt buffer configuration. - * b'30 - is_monitor_mode: specify whether monitor mode is enabled. - * Helpful to configure monitor-mode related filters. - * These filters cause throughput dip if enabled in - * non-monitor mode. - * b'31 - rsvd1: reserved for future use + * b'30:31 - rsvd1: reserved for future use * dword1 - b'0:15 - ring_buffer_size: size of bufferes referenced by rx ring, * in byte units. * Valid only for HW_TO_SW_RING and SW_TO_HW_RING @@ -6288,18 +5927,7 @@ enum htt_srng_ring_id { * be zero which means allow all frames for MD at RxOLE * host wil fiter out frames. * RxPCU (Filter IN) -> RxOLE (Filter In/Filter Out) - * b'28 - rx_hdr_len_ext: - * Extend rx_hdr_len to 3 bits with b'28 as MSb. - * Valid combined values: - * 001 - 64bytes - * 010 - 128bytes - * 011 - 256bytes - * 100 - 512bytes - * 101 - 1024bytes - * 110 - 2048bytes - * 111 - max bytes supported by HW - * default - 128 bytes - * b'29:31 - rsvd2: Reserved for future use + * b'28:31 - rsvd2: Reserved for future use * dword2 - b'0:31 - packet_type_enable_flags_0: * Enable MGMT packet from 0b0000 to 0b1001 * bits from low to high: FP, MD, MO - 3 bits @@ -6448,11 +6076,6 @@ enum htt_srng_ring_id { * dword28- b'0-31 - packet_type_enable_data_fpmo_flags_1 - filter bmap for * full pkt buffer each mode ctrl/data type/subtype for * fpmo mode - * dword29- b'0-31 - rdi_based_source_cfg - * Each bit maps to an RDI; if set, the corresponding - * ring ID is configured as a source buffer. - * Applies only to HTT_RXDMA_WBM_BUF0/1/2_RING. - * dword30- b'0-31 - wifi8 header length configurations. */ PREPACK struct htt_rx_ring_selection_cfg_t { A_UINT32 msg_type: 8, @@ -6464,16 +6087,14 @@ PREPACK struct htt_rx_ring_selection_cfg_t { drop_thresh_valid: 1, rx_mon_global_en: 1, packet_type_enable_data: 1, - is_monitor_mode: 1, - rsvd1: 1; + rsvd1: 2; A_UINT32 ring_buffer_size: 16, config_length_mgmt:3, config_length_ctrl:3, config_length_data:3, rx_hdr_len: 2, rxpcu_filter_enable_flag:1, - rx_hdr_len_ext: 1, - rsvd2: 3; + rsvd2: 4; A_UINT32 packet_type_enable_flags_0; A_UINT32 packet_type_enable_flags_1; A_UINT32 packet_type_enable_flags_2; @@ -6526,58 +6147,8 @@ PREPACK struct htt_rx_ring_selection_cfg_t { A_UINT32 packet_type_enable_data_flags_3; A_UINT32 packet_type_enable_data_fpmo_flags0; A_UINT32 packet_type_enable_data_fpmo_flags1; - - /* rdi_based_source_cfg: - * Each bit position in rdi_based_source_cfg represents RDI - * (REO Destination Indication). - * - * 1 in specific RDI position represents, for the given RDI position, - * ring id in the ring setup msg has to be configured as source buf. - * - * Below Field only applies for HTT_RXDMA_WBM_BUF0/1/2_RING - */ - A_UINT32 rdi_based_source_cfg; - - A_UINT32 rxmon_fpmo_data_hdrlen : 2, - rxmon_fpmo_ctrl_hdrlen : 2, - rxmon_fpmo_mgmt_hdrlen : 2, - rxmon_fp_data_hdrlen : 2, - rxmon_fp_ctrl_hdrlen : 2, - rxmon_fp_mgmt_hdrlen : 2, - rxmon_mo_data_hdrlen : 2, - rxmon_mo_ctrl_hdrlen : 2, - rxmon_mo_mgmt_hdrlen : 2, - rxmon_md_data_hdrlen : 2, - rxmon_md_ctrl_hdrlen : 2, - rxmon_md_mgmt_hdrlen : 2, - rxmon_enable_hdr_per_ppdu : 1, - rxmon_rsvd : 7; } POSTPACK; -/** - * Enumeration for Reg Write block index selection - * Each Enum position corresponds to respective - * UMAC_UMCMN_R0_REG_ADDR_LSB_IX_n - * UMAC_UMCMN_R0_REG_ADDR_MSB_IX_n - * UMAC_UMCMN_R2_REG_VALUE_IX_n - * - * Any value written to the value register will be copied by - * Reg Writer Block to Address written in Reg Address Register. - * - * NOTE: Only value Registers defined in the enum should be used by the Host. - * Rest are unconfigured, and if used may result in invalid memory access - */ -enum htt_reg_write_selection { - HTT_REG_WRITER_RXMON_SW2MON_BUF_RING, - HTT_REG_WRITER_TXMON_SW2MON_BUF_RING, - HTT_REG_WRITER_RXMON_M0_MON2SW_DEST_RING, - HTT_REG_WRITER_RXMON_M1_MON2SW_DEST_RING, - HTT_REG_WRITER_TXMON_M0_MON2SW_DEST_RING, - HTT_REG_WRITER_TXMON_M1_MON2SW_DEST_RING, - HTT_REG_WRITER_RXOLE2SW_ASE_DEST_RING, -}; - - #define HTT_RX_RING_SELECTION_CFG_SZ (sizeof(struct htt_rx_ring_selection_cfg_t)) #define HTT_RX_RING_SELECTION_CFG_PDEV_ID_M 0x0000ff00 @@ -6668,18 +6239,6 @@ enum htt_reg_write_selection { ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_S)); \ } while (0) -#define HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_M 0x40000000 -#define HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_S 30 -#define HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_M) >> \ - HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_S) -#define HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_IS_MONITOR_MODE_S)); \ - } while (0) - - #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M 0x0000ffff #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S 0 #define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_GET(_var) \ @@ -6726,25 +6285,14 @@ enum htt_reg_write_selection { #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M 0x06000000 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S 25 -#define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_M 0x10000000 -#define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_S 28 -#define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_CHK_M 0x7 -#define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_CHK_S 0 #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_GET(_var) \ - ((((_var) & HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_M) >> \ - (HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_S-2)) | \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S)) + (((_var) & HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M) >> \ + HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S) #define HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_CHK, _val); \ - ((_var) |= (((_val) << \ - HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S) & \ - HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_M)); \ - ((_var) |= (((_val) << \ - (HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_S-2)) & \ - HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_EXT_M)); \ - } while(0) + do { \ + HTT_CHECK_SET_VAL( HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_HDR_LEN_S));\ + } while(0) #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_M 0x08000000 #define HTT_RX_RING_SELECTION_CFG_RXPCU_FILTER_S 27 @@ -7247,150 +6795,6 @@ enum htt_reg_write_selection { } while (0) -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_M 0x00000003 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_S 0 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_M 0x0000000C -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_S 2 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_M 0x00000030 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_S 4 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_M 0x000000C0 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_S 6 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_M 0x00000300 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_S 8 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_M 0x00000C00 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_S 10 -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_M 0x00003000 -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_S 12 -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_M 0x0000C000 -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_S 14 -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_M 0x00030000 -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_S 16 -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_M 0x000C0000 -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_S 18 -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_M 0x00300000 -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_S 20 -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_M 0x00C00000 -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_S 22 -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_S) -#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_S)); \ - } while (0) - -#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_M 0x01000000 -#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_S 24 -#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_GET(_var) \ - (((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_M) >> \ - HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_S) -#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU, _val); \ - ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_S)); \ - } while (0) - - /* * Subtype based MGMT frames enable bits. * FP: Filter_Pass, MD: Monitor_Direct MO: Monitor_Other @@ -8116,10 +7520,7 @@ PREPACK struct htt_tx_monitor_cfg_t { pkt_swap: 1, tx_mon_global_en: 1, mac_addr_filter_en: 1, - addr_filter_peer_bitmap_ppdu_drop: 1, - type_based_mpdu_stat_filter_en: 1, - special_pkt_filtering_en: 1, - pkt_buf_cnt_en: 1; + rsvd1: 4; A_UINT32 ring_buffer_size: 16, config_length_mgmt: 3, config_length_ctrl: 3, @@ -8163,23 +7564,6 @@ PREPACK struct htt_tx_monitor_cfg_t { response_end_status_word_mask: 16; A_UINT32 fes_status_prot_word_mask: 11, rsvd6: 21; - A_UINT32 phy_tx_pkt_end: 8, - mac_tx_user_desc_common: 8, - mac_tx_mu_uplink_user_setup: 8, - pdg_response: 8; - A_UINT32 received_response_info: 8, - rx_response_required_info: 8, - ranging_user_details: 8, - mactx_pre_phy_desc: 8; - A_UINT32 ofdma_trigger_details: 16, - tqm_update_tx_mpdu_count_status: 16; - A_UINT32 phytx_location: 16, - rsvd7: 16; - A_UINT32 received_response_info_part2; - A_UINT32 type_en_mgmt; - A_UINT32 type_en_ctrl; - A_UINT32 type_en_data; - A_UINT32 tlv_filter_mask_in4; } POSTPACK; #define HTT_TX_MONITOR_CFG_SZ (sizeof(struct htt_tx_monitor_cfg_t)) @@ -8250,51 +7634,6 @@ PREPACK struct htt_tx_monitor_cfg_t { ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_MAC_ADDR_FILTER_EN_S)); \ } while (0) -#define HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_M 0x10000000 -#define HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_S 28 -#define HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_M) >> \ - HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_S) -#define HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_ADDR_FILTER_PEER_BITMAP_PPDU_DROP_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_M 0x20000000 -#define HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_S 29 -#define HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_M) >> \ - HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_S) -#define HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TYPE_BASED_MPDU_STAT_FILTER_EN_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_M 0x40000000 -#define HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_S 30 -#define HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_M) >> \ - HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_S) -#define HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_SPECIAL_PKT_FILTERING_EN_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_M 0x80000000 -#define HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_S 31 -#define HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_M) >> \ - HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_S) -#define HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PKT_BUF_CNT_EN_S)); \ - } while (0) - - #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_M 0x0000ffff #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_S 0 #define HTT_TX_MONITOR_CFG_RING_BUFFER_SIZE_GET(_var) \ @@ -8681,132 +8020,6 @@ PREPACK struct htt_tx_monitor_cfg_t { ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FES_STATUS_PROT_WORD_MASK_S)); \ } while (0) - -#define HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_M 0x000000ff -#define HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_S 0 -#define HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_M) >> \ - HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_S) -#define HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PHY_TX_PKT_END, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PHY_TX_PKT_END_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_M 0x0000ff00 -#define HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_S 8 -#define HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_M) >> \ - HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_S) -#define HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_MAC_TX_USER_DESC_COMMON_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_M 0x00ff0000 -#define HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_S 16 -#define HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_M) >> \ - HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_S) -#define HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_MAC_TX_MU_UPLINK_USER_SETUP_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_PDG_RESPONSE_M 0xff000000 -#define HTT_TX_MONITOR_CFG_PDG_RESPONSE_S 24 -#define HTT_TX_MONITOR_CFG_PDG_RESPONSE_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_PDG_RESPONSE_M) >> \ - HTT_TX_MONITOR_CFG_PDG_RESPONSE_S) -#define HTT_TX_MONITOR_CFG_PDG_RESPONSE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PDG_RESPONSE, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PDG_RESPONSE_S)); \ - } while (0) - - -#define HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_M 0x000000ff -#define HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_S 0 -#define HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_M) >> \ - HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_S) -#define HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RECEIVED_RESPONSE_INFO_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_M 0x0000ff00 -#define HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_S 8 -#define HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_M) >> \ - HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_S) -#define HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RX_RESPONSE_REQUIRED_INFO_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_M 0x00ff0000 -#define HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_S 16 -#define HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_M) >> \ - HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_S) -#define HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_RANGING_USER_DETAILS_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_M 0xff000000 -#define HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_S 24 -#define HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_M) >> \ - HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_S) -#define HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_MACTX_PRE_PHY_DESC_S)); \ - } while (0) - - -#define HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_M 0x0000ffff -#define HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_S 0 -#define HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_M) >> \ - HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_S) -#define HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_OFDMA_TRIGGER_DETAILS_S)); \ - } while (0) - -#define HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_M 0xffff0000 -#define HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_S 16 -#define HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_M) >> \ - HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_S) -#define HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_TQM_UPDATE_TX_MPDU_COUNT_STATUS_S)); \ - } while (0) - - -#define HTT_TX_MONITOR_CFG_PHYTX_LOCATION_M 0x0000ffff -#define HTT_TX_MONITOR_CFG_PHYTX_LOCATION_S 0 -#define HTT_TX_MONITOR_CFG_PHYTX_LOCATION_GET(_var) \ - (((_var) & HTT_TX_MONITOR_CFG_PHYTX_LOCATION_M) >> \ - HTT_TX_MONITOR_CFG_PHYTX_LOCATION_S) -#define HTT_TX_MONITOR_CFG_PHYTX_LOCATION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_PHYTX_LOCATION, _val); \ - ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_PHYTX_LOCATION_S)); \ - } while (0) - - /* * pkt_type_enable_flags */ @@ -12371,755 +11584,6 @@ PREPACK struct htt_h2t_mlo_latency_stats { ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_NUM_OF_TX_PKT_S)); \ } while (0) -/** - * @brief host -> target msg to provide MSDUQ or MPDUQ for new TID in a peer - * - * MSG_TYPE => HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR - * - * @details - * struct htt_h2t_mpduq_and_msduq_info_hdr: - * HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR message is sent by the host to - * target to tell how many mpduq and msduq info TLVs, in units of bytes, - * are present in the htt payload - * Example message contents: - *------------------------------------------------------------------- - *| htt_h2t_mpduq_and_msduq_info_hdr | - *------------------------------------------------------------------- - *| mpduq_info_tlv -> tid 0 , peer_id 1 | - *------------------------------------------------------------------- - *| mpduq_info_tlv -> tid 6, peer_id 1 | - *------------------------------------------------------------------- - *| msduq_info_tlv -> tid 0, peer_id 1 | - *------------------------------------------------------------------- - *| msduq_info_tlv -> tid 0, peer_id 1 | - *------------------------------------------------------------------- - *| msduq_info_tlv -> tid 6, peer_id 1 | - *------------------------------------------------------------------- - * - * As shown in the above exampple, a single htt buffer can hold multiple mpduq - * and msduq info tlvs, the info within the tlvs will indicate the peer and tid - * to which they belong. - */ - -/* HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR */ -PREPACK struct htt_h2t_mpduq_and_msduq_info_hdr { - A_UINT32 msg_type: 8, /* bits 7:0 */ - payload_size_bytes: 12, /* bits 19:8 */ - reserved_1a: 12; /* bits 31:20 */ -} POSTPACK; - -#define HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR_PAYLOAD_SIZE_BYTES_M 0x000FFF00 -#define HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR_PAYLOAD_SIZE_BYTES_S 8 -#define HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR_PAYLOAD_SIZE_BYTES_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR_PAYLOAD_SIZE_BYTES_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR_PAYLOAD_SIZE_BYTES_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR_PAYLOAD_SIZE_BYTES_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR_PAYLOAD_SIZE_BYTES, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_AND_MSDUQ_INFO_HDR_PAYLOAD_SIZE_BYTES_S)); \ - } while (0) - - -/** - * @brief host -> target message to provide mpduq for a tid in a peer - * - * MSG_TYPE => HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO - * - * @details - * struct htt_h2t_mpduq_or_msduq_info: - * HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO message is sent by the host to - * specify the configuration of new MPDUQ/MSDUQ for a tid in a peer. - * This message supports the following configuration information: - * 1. Info provided per MPDUQ: - * upper 32 bit address of 256 byte aligned physical address for mpduq - * mpduq number - * pn address space - * 2. Info provided per MSDUQ: - * upper 32 bit address of 256 byte aligned physical address for msduq - * msduq_number - * service class id - * - * The message is interpreted as follows for mpduq type: - * dword0 - b'7:0 - msg_type: Identifies msduq and mpduq info to FW - * This will be set to 0x2a - * (HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO) - * b'12:8 - msduq_mpduq_type: Indicate whether this TLV is for - * a MPDU queue or MSDU queue, and if for a MSDU queue, - * what type. - * For an MPDU queue, it will be fixed value of 30 based - * on enum HTT_H2T_TID_MSDUQ_MPDUQ_TYPE. - * b'16:13 - hw_link_id: Indicates which HW link the message is for. - * This HW link ID is mainly relevant for split PHY - * usecases to identify the correct link in same SOC. - * dword1 - b'31:0 - mpduq_address_39_8: 256 byte aligned mpduq physical - * address, since lowest octet is zero for 256 byte aligned - * physical addresses just passing upper 32 bits of - * 40 bit address - * dword2 - b'11:0 – peer_id - * b'16:12 – tid_num - * b'23:17 – reserved - * b'31:24 - pn_addr_32_39: Upper 8 bits of 40 bit pn physical address - * Note that the mpduq_number is formed from the combination of - * peer_id (in bits 11:0) - * tid_num (in bits 16:12) - * msduq_mpduq_type (in bits 21:17) - * dword3 - b'31:0 - pn_addr_0_31: Lower 32 bits of 40 bit pn physical address - * dword4 - b'0:0 - sam_mpduq_allocated: Indicates whether a SAM MPDUQ has - * been allocated for this TQM MPDUQ. - * b'11:1 - sam_mpduq_id: The SAM MPDUQ ID assigned by the host for - * this TQM MPDUQ. The value in this field is ignored if - * sam_mpduq_allocated is 0. - * b'13:12 - sam_mpduq_priority: The SAM priority assigned by the - * host. A SAM priority MUST ALWAYS be provided for chipsets - * that have SAM support, regardless of whether or not a SAM - * MPDUQ has been allocated. - * b'14:14 - sam_mpduq_sched_eligible: Indicates that this SAM MPDUQ - * is eligible for autonomous SAM scheduling. The value in - * this field is ignored if sam_mpduq_allocated is 0. - * b'31:15 – reserved - * Additional reserved dwords for future use cases - * - * - * The message is interpreted as follows for any msduq type: - * dword0 - b'7:0 - msg_type: Identifies msduq info to fw - * This will be set to 0x2A - * (HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO) - * b'12:8 - msduq_mpduq_type: type of the msduq based on - * enum HTT_H2T_TID_MSDUQ_MPDUQ_TYPE - * b'16:13 - hw_link_id: Indicates which HW link the message is - * intended for. - * This HW link ID is mainly relevant for split PHY - * usecases to identify the correct link in same SOC. - * dword1 - b'11:0 – peer_id - * b'16:12 – tid_num - * b'23:17 – reserved - * b'31:24 - svc_class_id : service class id of the msduq - * Note that the tx_msduq_number is formed from the combination of - * peer_id (in bits 11:0) - * tid_num (in bits 16:12) - * msduq_mpduq_type (in bits 21:17) - * dword2 - b'31:0 - msduq_address_39_8: 256 byte aligned msduq physical - * address, since lowest octet is zero for 256 byte aligned - * addresses just passing upper 32 bits of 40 bit address - * dword3 - b'0:0 - svc_inst_req_type_valid: Indicates whether - * svc_inst_req_type is valid. - * b'3:1 - svc_inst_req_type: Contains one of the values from - * HTT_SAWF_SVC_INST_REQ_TYPE. Only valid if - * svc_inst_req_type_valid is 1. - * b'4:4 - sam_msduq_allocated: Indicates whether a SAM MSDUQ has - * been allocated for this TQM MSDUQ. - * b'17:5 - sam_msduq_id: The SAM MSDUQ ID assigned by the host for - * this TQM MSDUQ. The value in this field is ignored if - * sam_msduq_allocated is 0. - * b'19:18 - sam_msduq_priority: The SAM priority assigned by the - * host. A SAM priority MUST ALWAYS be provided for chipsets - * that have SAM support, regardless of whether or not a SAM - * MSDUQ has been allocated. - * b'20:20 - sam_msduq_sched_eligible: Indicates that this SAM MSDUQ - * is eligible for autonomous SAM scheduling. The value in - * this field is ignored if sam_msduq_allocated is 0. - * b'31:21 – reserved - * Additional reserved dwords for future use cases - */ - -/* - * Enum describes the various msduq/mpduq types, - * First 8 types correspond to the standard msduq types for data - * Next come custom flows for specific purposes. - * Values 23-29 will be used for MGMT flows. - * The value 30 is reserved for mpduq type - */ -typedef enum { - HTT_H2T_TID_MSDUQ_NONUDP, /* 0 */ - HTT_H2T_TID_MSDUQ_UDP, /* 1 */ - HTT_H2T_TID_MSDUQ_CUSTOM_0, /* 2 */ - HTT_H2T_TID_MSDUQ_CUSTOM_1, /* 3 */ - HTT_H2T_TID_MSDUQ_CUSTOM_2, /* 4 */ - HTT_H2T_TID_MSDUQ_CUSTOM_3, /* 5 */ - HTT_H2T_TID_MSDUQ_CUSTOM_4, /* 6 */ - HTT_H2T_TID_MSDUQ_CUSTOM_5, /* 7 */ - - HTT_H2T_TID_MISC_MSDUQ_TYPE_START, /* 8 */ - HTT_H2T_TID_MSDUQ_HOL = HTT_H2T_TID_MISC_MSDUQ_TYPE_START, /* also 8 */ - HTT_H2T_TID_MSDUQ_MCAST, /* 9 */ - HTT_H2T_TID_MSDUQ_FAST_ROAMING, /* 10 */ - - HTT_H2T_TID_MSDUQ_DATA_TYPE_END = 23, /* 23 */ - - HTT_H2T_TID_MSDUQ_MGMT_LINK_SPECIFIC_0, /* 24 */ - HTT_H2T_TID_MSDUQ_MGMT_LINK_SPECIFIC_1, /* 25 */ - HTT_H2T_TID_MSDUQ_MGMT_LINK_SPECIFIC_2, /* 26 */ - HTT_H2T_TID_MSDUQ_MGMT_LINK_SPECIFIC_3, /* 27 */ - HTT_H2T_TID_MSDUQ_MGMT_LINK_SPECIFIC_4, /* 28 */ - HTT_H2T_TID_MSDUQ_MGMT_LINK_AGNOSTIC, /* 29 */ - - HTT_H2T_TID_MPDUQ_TYPE, /* 30 */ - HTT_H2T_TID_MSDUQ_MPDUQ_TYPE_END, /* 31 */ -} HTT_H2T_TID_MSDUQ_MPDUQ_TYPE; - -/* - * Enum to denote tid nums that can be used - * first 8 {0 - 7} numbers correspond to data access category - * {8 - 15} are for user defined usecases - * 16 is used to denote the non-qos tid - */ -typedef enum { - HTT_H2T_DEFAULT_TID_NUM = 0, - HTT_H2T_MAX_VALID_DATA_TID_NUM = 7, - HTT_H2T_NON_QOS_TID_NUM = 16, - HTT_H2T_MAX_TID_NUM = 31, -} H2T_TX_TID; - -typedef enum { - HTT_SAWF_SVC_INST_CREATE_REQ = 0, - HTT_SAWF_SVC_INST_DEACTIVATE_REQ, - HTT_SAWF_SVC_INST_REACTIVATE_REQ, - HTT_SAWF_SVC_INST_DELETE_REQ, -} HTT_SAWF_SVC_INST_REQ_TYPE; - -/* HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO */ -PREPACK struct htt_h2t_mpduq_or_msduq_info { - A_UINT32 msg_type: 8, /* bits 7:0 */ - msduq_mpduq_type: 5, /* bits 12:8 */ - hw_link_id: 4, /* bits 16:13 */ - reserved0: 15; /* bits 31:17 */ - - union { - struct { - A_UINT32 mpduq_address_39_8; /* bits 31:0 */ - A_UINT32 mpduq_number: 24, /* bits 23:0 */ - pn_addr_39_32: 8; /* bits 31:24 */ - A_UINT32 pn_addr_31_0; /* bits 31:0 */ - A_UINT32 sam_mpduq_allocated: 1, /* bit 0 */ - sam_mpduq_id: 11, /* bits 11:1 */ - sam_mpduq_priority: 2, /* bits 13:12 */ - sam_mpduq_sched_eligible: 1, /* bit 14 */ - reserved1a: 17; /* bits 31:15 */ - A_UINT32 reserved1b; /* bits 31:0 */ - A_UINT32 reserved1c; /* bits 31:0 */ - A_UINT32 reserved1d; /* bits 31:0 */ - A_UINT32 reserved1e; /* bits 31:0 */ - A_UINT32 reserved1f; /* bits 31:0 */ - }; - struct { - A_UINT32 tx_msduq_number: 24, /* bits 23:0 */ - svc_class_id: 8; /* bits 31:24 */ - A_UINT32 msduq_address_39_8; /* bits 31:0 */ - A_UINT32 svc_inst_req_type_valid: 1, /* bit 0 */ - /* svc_inst_req_type: - * contains a HTT_SAWF_SVC_INST_REQ_TYPE value - */ - svc_inst_req_type: 3, /* bits 3:1 */ - sam_msduq_allocated: 1, /* bit 4 */ - sam_msduq_id: 13, /* bits 17:5 */ - sam_msduq_priority: 2, /* bits 19:18 */ - sam_msduq_sched_eligible: 1, /* bit 20 */ - reserved2a: 11; /* bits 31:21 */ - A_UINT32 reserved2b; /* bits 31:0 */ - A_UINT32 reserved2c; /* bits 31:0 */ - A_UINT32 reserved2d; /* bits 31:0 */ - A_UINT32 reserved2e; /* bits 31:0 */ - A_UINT32 reserved2f; /* bits 31:0 */ - A_UINT32 reserved2g; /* bits 31:0 */ - }; - }; -} POSTPACK; - -/* MPDUQ/MSDUQ shared fields of HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO */ - -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE_M 0x00001F00 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE_S 8 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_MSDUQ_MPDUQ_TYPE_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_HW_LINK_ID_M 0x0001E000 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_HW_LINK_ID_S 13 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_HW_LINK_ID_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_HW_LINK_ID_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_HW_LINK_ID_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_HW_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_HW_LINK_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO_HW_LINK_ID_S)); \ - } while (0) - - -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_PEER_ID_M 0x00000FFF -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_PEER_ID_S 0 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_PEER_ID_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_PEER_ID_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_PEER_ID_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_PEER_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_PEER_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_PEER_ID_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_TID_NUM_M 0x0001F000 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_TID_NUM_S 12 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_TID_NUM_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_TID_NUM_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_TID_NUM_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_TID_NUM_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_TID_NUM, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_TID_NUM_S)); \ - } while (0) - - -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_MSDUQ_MPDUQ_TYPE_M 0x003E0000 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_MSDUQ_MPDUQ_TYPE_S 17 -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_MSDUQ_MPDUQ_TYPE_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_MSDUQ_MPDUQ_TYPE_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_MSDUQ_MPDUQ_TYPE_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_MSDUQ_MPDUQ_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_MSDUQ_MPDUQ_TYPE, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_NUMBER_MSDUQ_MPDUQ_TYPE_S)); \ - } while (0) - - -/* MPDUQ Variant of HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO */ - -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8_M 0xFFFFFFFF -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8_S 0 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_ADDRESS_39_8_S)); \ - } while (0) - - -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_NUMBER_M 0x00FFFFFF -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_NUMBER_S 0 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_NUMBER_GET(_var) \ - (((_var) & HTT_H2T_MSG_MPDUQ_INFO_MPDUQ_NUMBER_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_NUMBER_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_NUMBER_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_NUMBER, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_MPDUQ_NUMBER_S)); \ - } while (0) - - -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_39_32_M 0xFF000000 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_39_32_S 24 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_39_32_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_39_32_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_39_32_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_39_32_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_39_32, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_39_32_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_31_0_M 0xFFFFFFFF -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_31_0_S 0 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_31_0_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_31_0_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_31_0_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_31_0_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_31_0, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_PN_ADDRESS_31_0_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_M 0x00000001 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_S 0 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ALLOCATED_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_M 0x00000FFE -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_S 1 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_ID_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_M 0x00003000 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_S 12 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_PRIORITY_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_M 0x00004000 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_S 14 -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_M) >> \ - HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_S) -#define HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MPDUQ_INFO_SAM_MPDUQ_SCHED_ELIGIBLE_S)); \ - } while (0) - - -/* MSDUQ Variant of HTT_H2T_MSG_TYPE_MPDUQ_OR_MSDUQ_INFO */ - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER_M 0x00FFFFFF -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER_S 0 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_TX_MSDUQ_NUMBER_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_CLASS_ID_M 0xFF000000 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_CLASS_ID_S 24 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_CLASS_ID_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_CLASS_ID_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_CLASS_ID_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_CLASS_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_CLASS_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_CLASS_ID_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_MSDUQ_ADDRESS_39_8_M 0xFFFFFFFF -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_MSDUQ_ADDRESS_39_8_S 0 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_MSDUQ_ADDRESS_39_8_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_MSDUQ_ADDRESS_39_8_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_MSDUQ_ADDRESS_39_8_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_MSDUQ_ADDRESS_39_8_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_MSDUQ_ADDRESS_39_8, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_MSDUQ_ADDRESS_39_8_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_M 0x00000001 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_S 0 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_VALID_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_M 0x0000000E -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_S 1 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SVC_INST_REQ_TYPE_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_M 0x00000010 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_S 4 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ALLOCATED_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_M 0x0003FFE0 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_S 5 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_ID_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_M 0x000C0000 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_S 18 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_PRIORITY_S)); \ - } while (0) - -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_M 0x00100000 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_S 20 -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_GET(_var) \ - (((_var) & HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_M) >> \ - HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_S) -#define HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MSDUQ_INFO_SAM_MSDUQ_SCHED_ELIGIBLE_S)); \ - } while (0) - - -/* - * @brief host -> target HTT_AST_INFO message - * - * MSG_TYPE => HTT_H2T_MSG_TYPE_AST_INFO - * - * The message would appear as follows: - * |31 24|23 21|20|19|18|17|16|15 8|7 0| - * |--------------+-------------------------------------+-------------------| - * |ast_max_search| ast_table_size | msg_type | - * |------------------------------------------------------------------------| - * | ast_base_addr_31_0 | - * |------------------------------------------------------------------------| - * | ase_hash_key1 | - * |------------------------------------------------------------------------| - * | ase_hash_key2 | - * |------------------------------------------------------------------------| - * | ase_hash_key3 | - * |--------------------+--+--+--+--+--+----------------+-------------------| - * | reserved |L |K |J |I |H | tmo |ast_base_addr_39_32| - * |--------------------+--+--+--+--+--+----------------+-------------------| - * - * The message is interpreted as follows: - * dword0 b'7:0 - msg_type - * 0 b'23:8 - ast table size - * b'31:24 - ast max search - * dword1 - b'31:0 - ast table base address - * dword2 - b'31:0 - ase hash key 1 - * dword3 - b'31:0 - ase hash key 2 - * dword4 - b'31:0 - ase hash key 3 - * dword5 - b'7:0 - ast_base_addr_39_32 - * b'15:8 - ast_timeout_threshold - * b'16 - H - ast cache disable knob - * b'17 - I - ast cache faluires disable knob - * b'18 - J - ast cache cmd read bypass - * Bypassing the reads from memory when an entry is not - * found in cache, in case of full cache commands, - * write back or invalidate commands. - * b'19 - K - ast cache write back fx - * If this fix is disabled, then any write back command - * for a cache line will also lead to invalidation of - * that cache line. - * b'20 - L - ast cache only entry command fix - * If enabled, a new cache entry will always be created - * for requests for which matching data was found - * neither in cache nor in memory. - */ -PREPACK struct htt_ast_info_t { - A_UINT32 msg_type: 8, - ast_table_size: 16, /* number of entries in AST */ - ast_max_search: 8; - A_UINT32 ast_base_addr; /* base address of the AST table */ - A_UINT32 ase_hash_key1; - A_UINT32 ase_hash_key2; - A_UINT32 ase_hash_key3; - A_UINT32 ast_base_addr_39_32: 8, /* 7:0 */ - ast_timeout_threshold: 8, /* 15:8 */ - ast_cache_disable: 1, /* 16 */ - ast_cache_failures_disable: 1, /* 17 */ - ast_cache_cmd_read_bypass_dis: 1, /* 18 */ - ast_cache_write_back_fix_dis: 1, /* 19 */ - ast_cache_only_entry_cmd_fix_dis: 1, /* 20 */ - reserved: 11; -} POSTPACK; - - -#define HTT_AST_INFO_SZ (sizeof(struct htt_ast_info_t)) - -/* DWORD0 */ -#define HTT_AST_INFO_AST_TABLE_SIZE_M 0x00ffff00 -#define HTT_AST_INFO_AST_TABLE_SIZE_S 8 -#define HTT_AST_INFO_AST_TABLE_SIZE_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_TABLE_SIZE_M) >> \ - HTT_AST_INFO_AST_TABLE_SIZE_S) -#define HTT_AST_INFO_AST_TABLE_SIZE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_TABLE_SIZE, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_TABLE_SIZE__S)); \ - } while (0) - -#define HTT_AST_INFO_AST_MAX_SEARCH_M 0xff000000 -#define HTT_AST_INFO_AST_MAX_SEARCH_S 24 -#define HTT_AST_INFO_AST_MAX_SEARCH_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_MAX_SEARCH_M) >> \ - HTT_AST_INFO_AST_MAX_SEARCH_S) -#define HTT_AST_INFO_AST_MAX_SEARCH_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_MAX_SEARCH, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_MAX_SEARCH_S)); \ - } while (0) - - -/* DWORD5 */ - -#define HTT_AST_INFO_AST_BASE_ADDR_39_32_M 0x000000ff -#define HTT_AST_INFO_AST_BASE_ADDR_39_32_S 0 -#define HTT_AST_INFO_AST_BASE_ADDR_39_32_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_BASE_ADDR_39_32_M) >> \ - HTT_AST_INFO_AST_BASE_ADDR_39_32_S) -#define HTT_AST_INFO_AST_BASE_ADDR_39_32_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_BASE_ADDR_39_32, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_BASE_ADDR_39_32_S)); \ - } while (0) - -#define HTT_AST_INFO_AST_TIMEOUT_THRESHOLD_M 0x0000ff00 -#define HTT_AST_INFO_AST_TIMEOUT_THRESHOLD_S 8 -#define HTT_AST_INFO_AST_TIMEOUT_THRESHOLD_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_TIMEOUT_THRESHOLD_M) >> \ - HTT_AST_INFO_AST_TIMEOUT_THRESHOLD_S) -#define HTT_AST_INFO_AST_TIMEOUT_THRESHOLD_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_TIMEOUT_THRESHOLD, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_TIMEOUT_THRESHOLD_S)); \ - } while (0) - -#define HTT_AST_INFO_AST_CACHE_DISABLE_M 0x00010000 -#define HTT_AST_INFO_AST_CACHE_DISABLE_s 16 -#define HTT_AST_INFO_AST_CACHE_DISABLE_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_CACHE_DISABLE_M) >> \ - HTT_AST_INFO_AST_CACHE_DISABLE_s) -#define HTT_AST_INFO_AST_CACHE_DISABLE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_CACHE_DISABLE, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_CACHE_DISABLE_S)); \ - } while (0) - -#define HTT_AST_INFO_AST_CACHE_FALUIRES_DISABLE_M 0x00020000 -#define HTT_AST_INFO_AST_CACHE_FALUIRES_DISABLE_s 17 -#define HTT_AST_INFO_AST_CACHE_FALUIRES_DISABLE_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_CACHE_FALUIRES_DISABLE_M) >> \ - HTT_AST_INFO_AST_CACHE_FALUIRES_DISABLE_s) -#define HTT_AST_INFO_AST_CACHE_FALUIRES_DISABLE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_CACHE_FALUIRES_DISABLE, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_CACHE_FALUIRES_DISABLE_S)); \ - } while (0) - -#define HTT_AST_INFO_AST_CACHE_CMD_READ_BYPASS_DIS_M 0x00040000 -#define HTT_AST_INFO_AST_CACHE_CMD_READ_BYPASS_DIS_s 18 -#define HTT_AST_INFO_AST_CACHE_CMD_READ_BYPASS_DIS_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_CACHE_CMD_READ_BYPASS_DIS_M) >> \ - HTT_AST_INFO_AST_CACHE_CMD_READ_BYPASS_DIS_s) -#define HTT_AST_INFO_AST_CACHE_CMD_READ_BYPASS_DIS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_CACHE_CMD_READ_BYPASS_DIS, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_CACHE_CMD_READ_BYPASS_DIS_S)); \ - } while (0) - -#define HTT_AST_INFO_AST_CACHE_WRITE_BACK_FIX_DIS_M 0x00080000 -#define HTT_AST_INFO_AST_CACHE_WRITE_BACK_FIX_DIS_s 19 -#define HTT_AST_INFO_AST_CACHE_WRITE_BACK_FIX_DIS_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_CACHE_WRITE_BACK_FIX_DIS_M) >> \ - HTT_AST_INFO_AST_CACHE_WRITE_BACK_FIX_DIS_s) -#define HTT_AST_INFO_AST_CACHE_WRITE_BACK_FIX_DIS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_CACHE_WRITE_BACK_FIX_DIS, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_CACHE_WRITE_BACK_FIX_DIS_S)); \ - } while (0) - -#define HTT_AST_INFO_AST_CACHE_ONLY_ENTRY_CMD_FIX_DIS_M 0x00100000 -#define HTT_AST_INFO_AST_CACHE_ONLY_ENTRY_CMD_FIX_DIS_s 20 -#define HTT_AST_INFO_AST_CACHE_ONLY_ENTRY_CMD_FIX_DIS_GET(_var) \ - (((_var) & HTT_AST_INFO_AST_CACHE_ONLY_ENTRY_CMD_FIX_DIS_M) >> \ - HTT_AST_INFO_AST_CACHE_ONLY_ENTRY_CMD_FIX_DIS_s) -#define HTT_AST_INFO_AST_CACHE_ONLY_ENTRY_CMD_FIX_DIS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_AST_INFO_AST_CACHE_ONLY_ENTRY_CMD_FIX_DIS, _val); \ - ((_var) |= ((_val) << HTT_AST_INFO_AST_CACHE_ONLY_ENTRY_CMD_FIX_DIS_S)); \ - } while (0) - - -/* - * @brief host -> target HTT_H2T_MSG_TYPE_DAL_MODE_INFO message - * - * MSG_TYPE => HTT_H2T_MSG_TYPE_DAL_MODE_INFO (0x2C) - * - * The message would appear as follows: - * |31 16|15 8|7 0| - * |--------------------+-----------------+-------------------| - * | mode | pdev_id | msg_type | - * |----------------------------------------------------------| - * | write_data_addr_lo | - * |----------------------------------------------------------| - * | write_data_addr_hi | - * |----------------------------------------------------------| - * | write_msi_addr_lo | - * |----------------------------------------------------------| - * | write_msi_addr_hi | - * |----------------------------------------------------------| - * | write_msi_data | - * |----------------------------------------------------------| - * - * The message is interpreted as follows: - * dword0 - b'7:0 - msg_type - * b'15:8 - pdev_id - * b'31:16 - mode - * dword1 - b'31:0 - write_data_addr_lo - * dword2 - b'31:0 - write_data_addr_hi - * dword3 - b'31:0 - write_msi_addr_lo - * dword4 - b'31:0 - write_msi_addr_hi - * dword5 - b'31:0 - write_msi_data - */ -PREPACK struct htt_h2t_msg_dal_mode_info { - A_UINT32 msg_type: 8, - pdev_id: 8, - mode: 16; - A_UINT32 write_data_addr_lo; - A_UINT32 write_data_addr_hi; - A_UINT32 write_msi_addr_lo; - A_UINT32 write_msi_addr_hi; - A_UINT32 write_msi_data; -} POSTPACK; - -#define HTT_H2T_MSG_DAL_MODE_INFO_SZ (sizeof(struct htt_h2t_msg_dal_mode_info)) - -/* DWORD0 */ -#define HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_M 0x0000ff00 -#define HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_S 8 - -#define HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_GET(_var) \ - (((_var) & HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_M) >> \ - HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_S) -#define HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_DAL_MODE_INFO_PDEV_ID_S)); \ - } while (0) - -#define HTT_H2T_MSG_DAL_MODE_INFO_MODE_M 0xffff0000 -#define HTT_H2T_MSG_DAL_MODE_INFO_MODE_S 16 - -#define HTT_H2T_MSG_DAL_MODE_INFO_MODE_GET(_var) \ - (((_var) & HTT_H2T_MSG_DAL_MODE_INFO_MODE_M) >> \ - HTT_H2T_MSG_DAL_MODE_INFO_MODE_S) -#define HTT_H2T_MSG_DAL_MODE_INFO_MODE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_H2T_MSG_DAL_MODE_INFO_MODE, _val); \ - ((_var) |= ((_val) << HTT_H2T_MSG_DAL_MODE_INFO_MODE_S)); \ - } while (0) - /*=== target -> host messages ===============================================*/ @@ -13195,9 +11659,6 @@ enum htt_t2h_msg_type { HTT_T2H_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP_DONE = 0x3b, HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND = 0x3c, HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ = 0x3d, - HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP = 0x3e, - HTT_T2H_MSG_TYPE_HAPS = 0x3f, - HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP = 0x40, HTT_T2H_MSG_TYPE_TEST, @@ -16200,41 +14661,40 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t * with, so that the host can use that MLO peer ID to determine which peer * transmitted the rx frame. * - * |31 |29 27|26|25|24|23 20|19 17|16|15 8|7 0| - * |--------------------------------------------------------------------------| - * |RSVD | PRC | NUMLINK| MLO peer ID | msg type | - * |--------------------------------------------------------------------------| - * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | - * |--------------------------------------------------------------------------| - * | RSVD_25_31 |CV| CLASS_INFO_IDX | MAC addr 5 | MAC addr 4 | - * |--------------------------------------------------------------------------| - * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 0 | - * |--------------------------------------------------------------------------| - * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 1 | - * |--------------------------------------------------------------------------| - * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 2 | - * |--------------------------------------------------------------------------| - * |RSVD | - * |--------------------------------------------------------------------------| - * |RSVD | - * |--------------------------------------------------------------------------| - * | htt_tlv_hdr_t | - * |--------------------------------------------------------------------------| - * |RSVD_27_31 | CHIPID | VDEVID | SW peer ID | - * |--------------------------------------------------------------------------| - * | htt_tlv_hdr_t | - * |--------------------------------------------------------------------------| - * |RSVD_27_31 | CHIPID | VDEVID | SW peer ID | - * |--------------------------------------------------------------------------| - * | htt_tlv_hdr_t | - * |--------------------------------------------------------------------------| - * |RSVD_27_31 | CHIPID | VDEVID | SW peer ID | - * |--------------------------------------------------------------------------| + * |31 |29 27|26 24|23 20|19 17|16|15 8|7 0| + * |-------------------------------------------------------------------------| + * |RSVD | PRC |NUMLINK| MLO peer ID | msg type | + * |-------------------------------------------------------------------------| + * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | + * |-------------------------------------------------------------------------| + * | RSVD_16_31 | MAC addr 5 | MAC addr 4 | + * |-------------------------------------------------------------------------| + * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 0 | + * |-------------------------------------------------------------------------| + * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 1 | + * |-------------------------------------------------------------------------| + * |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 2 | + * |-------------------------------------------------------------------------| + * |RSVD | + * |-------------------------------------------------------------------------| + * |RSVD | + * |-------------------------------------------------------------------------| + * | htt_tlv_hdr_t | + * |-------------------------------------------------------------------------| + * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID | + * |-------------------------------------------------------------------------| + * | htt_tlv_hdr_t | + * |-------------------------------------------------------------------------| + * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID | + * |-------------------------------------------------------------------------| + * | htt_tlv_hdr_t | + * |-------------------------------------------------------------------------| + * |RSVD_27_31 |CHIPID| VDEVID | SW peer ID | + * |-------------------------------------------------------------------------| * * Where: * PRC - Primary REO CHIPID - 3 Bits Bit24,25,26 * NUMLINK - NUM_LOGICAL_LINKS - 3 Bits Bit27,28,29 - * CV - CLASSIFY_INFO_IDX_VALID - 1 Bit Bit24 * V (valid) - 1 Bit Bit17 * CHIPID - 3 Bits * TIDMASK - 8 Bits @@ -16274,16 +14734,6 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t * Purpose: Identifies which peer node the peer ID is for. * Value: upper 2 bytes of peer node's MAC address * - * - CLASS_INFO_IDX - * Bits 23:16 - * Purpose: Classify info index assists TCL-L Block in certain families of - * WLAN chips to start finding the flow from the corresponding - * entry in the FLOW LOOK UP TABLE in MLO case - * - CV (CLASS_INFO_IDX_VALID) - * Bit 24 - * Purpose: if set indicates that the CLASS_INFO_IDX is valid, - * else ignore the value reported - * * - PRIMARY_TCL_AST_IDX * Bits 15:0 * Purpose: Primary TCL AST index for this peer. @@ -16355,11 +14805,6 @@ typedef enum { #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_U16_M 0x0000ffff #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_U16_S 0 -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_M 0x00ff0000 -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_S 16 -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_M 0x01000000 -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_S 24 - #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_M 0x0000ffff #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_S 0 #define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_M 0x00010000 @@ -16408,30 +14853,6 @@ typedef enum { #define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_GET(word) \ (((word) & HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_M) >> HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S) -#define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID, value); \ - (word) |= (value) << HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S; \ - } while (0) -#define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_GET(word) \ - (((word) & HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_M) >> HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S) - -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX, value); \ - (word) |= (value) << HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_S; \ - } while (0) -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_GET(word) \ - (((word) & HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_M) >> HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_S) - -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_SET(word, value) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG, value); \ - (word) |= (value) << HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_S; \ - } while (0) -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_GET(word) \ - (((word) & HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_M) >> HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_S) - #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_SET(word, value) \ do { \ HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX, value); \ @@ -16514,8 +14935,6 @@ typedef enum { #define HTT_RX_MLO_PEER_MAP_MAC_ADDR_OFFSET 4 /* bytes */ -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_OFFSET 8 /* bytes */ -#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_OFFSET 8 /* bytes */ #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_0_OFFSET 12 /* bytes */ #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_1_OFFSET 16 /* bytes */ #define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_2_OFFSET 20 /* bytes */ @@ -20976,7 +19395,6 @@ typedef enum { HTT_PEER_CFR_CAPTURE_BW_80MHZ = 2, HTT_PEER_CFR_CAPTURE_BW_160MHZ = 3, HTT_PEER_CFR_CAPTURE_BW_80_80MHZ = 4, - HTT_PEER_CFR_CAPTURE_BW_320MHZ = 5, HTT_PEER_CFR_CAPTURE_BW_MAX, } HTT_PEER_CFR_CAPTURE_BW; @@ -22452,23 +20870,20 @@ PREPACK struct htt_rx_peer_metadata_v1 { * * The following diagram shows the format of the RX PEER METADATA V1A format. * - * |31 |29|28 26|25 22|21 14| 13 |12 0| - * |----------------------------------------------------------------------| - * |Rsvd2|PT|CHIP ID|logical_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| - * |----------------------------------------------------------------------| - * Where: - * PT = passthrough packet + * |31 29|28 26|25 22|21 14| 13 |12 0| + * |-------------------------------------------------------------------| + * |Rsvd2|CHIP ID|logical_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| + * |-------------------------------------------------------------------| */ PREPACK struct htt_rx_peer_metadata_v1a { A_UINT32 - peer_id: 13, - ml_peer_valid: 1, - vdev_id: 8, - logical_link_id: 4, - chip_id: 3, - qdata_refill: 1, - passthru_pkt: 1, - qdata_consent_pkt: 1; + peer_id: 13, + ml_peer_valid: 1, + vdev_id: 8, + logical_link_id: 4, + chip_id: 3, + qdata_refill: 1, + reserved2: 2; } POSTPACK; #define HTT_RX_PEER_META_DATA_V1A_PEER_ID_S 0 @@ -22537,28 +20952,6 @@ PREPACK struct htt_rx_peer_metadata_v1a { ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_QDATA_REFILL_S)); \ } while (0) -#define HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_S 30 -#define HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_M 0x40000000 -#define HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_M) >> HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_S) - -#define HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_PASSTHRU_PKT_S)); \ - } while (0) - -#define HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_S 31 -#define HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_M 0x80000000 -#define HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_M) >> HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_S) - -#define HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_QDATA_CONSENT_PKT_S)); \ - } while (0) - /** * @brief target -> RX PEER METADATA V1B format @@ -22569,10 +20962,10 @@ PREPACK struct htt_rx_peer_metadata_v1a { * * The following diagram shows the format of the RX PEER METADATA V1B format. * - * |31 |30 29|28 26|25 22|21 14| 13 |12 0| - * |--------------------------------------------------------------------| - * |Rsvd2|DECAP|CHIP ID|hw_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| - * |--------------------------------------------------------------------| + * |31 29|28 26|25 22|21 14| 13 |12 0| + * |--------------------------------------------------------------| + * |Rsvd2|CHIP ID|hw_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| + * |--------------------------------------------------------------| */ PREPACK struct htt_rx_peer_metadata_v1b { A_UINT32 @@ -22581,8 +20974,7 @@ PREPACK struct htt_rx_peer_metadata_v1b { vdev_id: 8, hw_link_id: 4, chip_id: 3, - decap_type: 2, - reserved2: 1; + reserved2: 3; } POSTPACK; #define HTT_RX_PEER_META_DATA_V1B_PEER_ID_S 0 @@ -22640,138 +21032,6 @@ PREPACK struct htt_rx_peer_metadata_v1b { ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S)); \ } while (0) -#define HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_S 29 -#define HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_M 0x60000000 -#define HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_M) >> HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_S) - -#define HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_DECAP_TYPE_S)); \ - } while (0) - -/* - * htt_rx_peer_metadata_v2 - HTT RX peer metadata version 2 - * - * |31 22|21|20 13|12|11 9|8 6| 5 |4 0| - * |---------+--+--------+--+-----+-----+-----+-----| - * |reserved |PT|peer |Q | Log |VDEV | ML |Peer | - * | | |session |D |Link | ID |Peer | ID | - * | | |ID |R | ID | |Valid| | - * |---------+--+--------+--+-----+-----+-----+-----| - * Where: - * QDR = queue data refill - * PT = passthrough packet - */ -PREPACK struct htt_rx_peer_metadata_v2 { - A_UINT32 - peer_id: 5, - ml_peer_valid: 1, - vdev_id: 3, - logical_link_id: 3, - qdata_refill: 1, - peer_session_id: 8, - passthru_pkt: 1, - qdata_consent_pkt: 1, - reserved: 9; -} POSTPACK; - -#define HTT_RX_PEER_META_DATA_V2_PEER_ID_S 0 -#define HTT_RX_PEER_META_DATA_V2_PEER_ID_M 0x0000001f - -#define HTT_RX_PEER_META_DATA_V2_PEER_ID_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V2_PEER_ID_M) >> \ - HTT_RX_PEER_META_DATA_V2_PEER_ID_S) -#define HTT_RX_PEER_META_DATA_V2_PEER_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_PEER_ID, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_PEER_ID_S)); \ - } while (0) - -#define HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_S 5 -#define HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_M 0x00000020 -#define HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_M) >> \ - HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_S) -#define HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_ML_PEER_VALID_S)); \ - } while (0) - -#define HTT_RX_PEER_META_DATA_V2_VDEV_ID_S 6 -#define HTT_RX_PEER_META_DATA_V2_VDEV_ID_M 0x000001c0 - -#define HTT_RX_PEER_META_DATA_V2_VDEV_ID_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V2_VDEV_ID_M) >> \ - HTT_RX_PEER_META_DATA_V2_VDEV_ID_S) -#define HTT_RX_PEER_META_DATA_V2_VDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_VDEV_ID_S)); \ - } while (0) - -#define HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_S 9 -#define HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_M 0x00000e00 - -#define HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_M) >> \ - HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_S) -#define HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_LOGICAL_LINK_ID_S)); \ - } while (0) - -#define HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_S 12 -#define HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_M 0x00001000 - -#define HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_M) >> \ - HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_S) -#define HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_QDATA_REFILL, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_QDATA_REFILL_S)); \ - } while (0) - -#define HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_S 13 -#define HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_M 0x001fe000 - -#define HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_M) >> \ - HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_S) -#define HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_PEER_SESSION_ID_S)); \ - } while (0) - -#define HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_S 21 -#define HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_M 0x00200000 - -#define HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_M) >> \ - HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_S) -#define HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_PASSTHRU_PKT_S)); \ - } while (0) - -#define HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_S 22 -#define HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_M 0x00400000 -#define HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_GET(_var) \ - (((_var) & HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_M) >> HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_S) - -#define HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT, _val); \ - ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V2_QDATA_CONSENT_PKT_S)); \ - } while (0) - - /* generic variables for masks and shifts for various fields */ extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_S; extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_M; @@ -22804,15 +21064,6 @@ extern void (*HTT_RX_PEER_META_DATA_HW_LINK_ID_SET) (A_UINT32 *var, A_UINT32 val extern A_UINT32 (*HTT_RX_PEER_META_DATA_QDATA_REFILL_GET) (A_UINT32 var); extern void (*HTT_RX_PEER_META_DATA_QDATA_REFILL_SET) (A_UINT32 *var, A_UINT32 val); -extern A_UINT32 (*HTT_RX_PEER_META_DATA_PEER_SESSION_ID_GET) (A_UINT32 var); -extern void (*HTT_RX_PEER_META_DATA_PEER_SESSION_ID_SET) (A_UINT32 *var, A_UINT32 val); - -extern A_UINT32 (*HTT_RX_PEER_META_DATA_DECAP_TYPE_GET) (A_UINT32 var); -extern void (*HTT_RX_PEER_META_DATA_DECAP_TYPE_SET) (A_UINT32 *var, A_UINT32 val); - -extern A_UINT32 (*HTT_RX_PEER_META_DATA_PASSTHRU_PKT_GET) (A_UINT32 var); -extern void (*HTT_RX_PEER_META_DATA_PASSTHRU_PKT_SET) (A_UINT32 *var, A_UINT32 val); - /* * In some systems, the host SW wants to specify priorities between @@ -22859,25 +21110,18 @@ enum HTT_MSDU_QTYPE { HTT_MSDU_QTYPE_HI_PRIO, /* Specifies MSDUQ index used for high priority flow type */ HTT_MSDU_QTYPE_LO_PRIO, /* Specifies MSDUQ index used for low priority flow type */ - HTT_MSDU_QTYPE_MAX, /* legacy limit (based on ROM compatibility) */ - - HTT_MSDU_QTYPE_LATENCY_CRIT_2, - HTT_MSDU_QTYPE_LATENCY_CRIT_3, - HTT_MSDU_QTYPE_LATENCY_CRIT_4, - HTT_MSDU_QTYPE_LATENCY_CRIT_5, /* New MSDU_QTYPE should be added above this line */ /* - * Below QTYPE_MAX_EXT will increase if additional QTYPEs are defined - * in the future. Hence HTT_MSDU_QTYPE_MAX_EXT can't be used in - * any host/target message definitions. The QTYPE_MAX_EXT value can + * Below QTYPE_MAX will increase if additional QTYPEs are defined + * in the future. Hence HTT_MSDU_QTYPE_MAX can't be used in + * any host/target message definitions. The QTYPE_MAX value can * only be used internally within the host or within the target. - * If host or target find a qtype value is >= HTT_MSDU_QTYPE_MAX_EXT + * If host or target find a qtype value is >= HTT_MSDU_QTYPE_MAX * it must regard the unexpected value as a default qtype value, * or ignore it. */ - HTT_MSDU_QTYPE_MAX_EXT, - + HTT_MSDU_QTYPE_MAX, HTT_MSDU_QTYPE_NOT_IN_USE = 255, /* corresponding MSDU index is not in use */ }; @@ -25205,228 +23449,4 @@ PREPACK struct htt_t2h_mlo_latency_req_t { } while (0) -/* MSG_TYPE => HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP - * - * The following diagram shows the format of the global peer unmap message sent - * from the target to the host. This message is used to send unmap event to host - * after tid and msduq/mpduq cleanup in FW, host cleans up msduq/mpduq based on - * message. - * - * |31 24|23 20|19 8|7 0| - * |-----------------------------------------------------------------------| - * | reserved | hw_link_id | global_peer_id | msg type | - * |-----------------------------------------------------------------------| - * @details - * struct htt_t2h_global_peer_id_unmap_t: - * - * The message is interpreted as follows: - * dword0 - b'7:0 - msg_type: Identifies a request for MLO latency stats - * This will be set to 0x3e - * (HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP) - * b'19:8 - global_peer_id : global peer id assigned by host - * b'23:20 - hw_link_id : hw link id for which unmap is being sent - * - */ - - -/* HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP */ -PREPACK struct htt_t2h_global_peer_id_unmap_t { - A_UINT32 msg_type: 8, /* bits 7:0 */ - global_peer_id: 12, /* bits 19:8 */ - hw_link_id: 4, /* bits 23:20 */ - reserved: 8; /* bits 31:16 */ -} POSTPACK; - -#define HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_GLOBAL_PEER_ID_M 0x000FFF00 -#define HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_GLOBAL_PEER_ID_S 8 -#define HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_GLOBAL_PEER_ID_GET(_var) \ - (((_var) & HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_GLOBAL_PEER_ID_M) >> \ - HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_GLOBAL_PEER_ID_S) -#define HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_GLOBAL_PEER_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_GLOBAL_PEER_ID, _val); \ - ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_GLOBAL_PEER_ID_S)); \ - } while (0) - -#define HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_HW_LINK_ID_M 0x00F00000 -#define HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_HW_LINK_ID_S 20 -#define HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_HW_LINK_ID_GET(_var) \ - (((_var) & HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_HW_LINK_ID_M) >> \ - HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_HW_LINK_ID_S) -#define HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_HW_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_HW_LINK_ID, _val); \ - ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_GLOBAL_PEER_ID_UNMAP_HW_LINK_ID_S)); \ - } while (0) - - -/* - * @brief target -> pause/unpause host tx queues based on FW indication - * MSG_TYPE => HTT_T2H_MSG_TYPE_HAPS - * - * @details * Header fields: - * - * |31 22|21 20|19 16|15 8|7 0| - * |---------+-------------+-----------+------------------+---------------| - * | RSVD |time_type |action_code| vdev_id | msg type | - * |----------------------------------------------------------------------| - * | time_high | - * |----------------------------------------------------------------------| - * | time_low | - * |----------------------------------------------------------------------| - * - * dword0 - b'7:0 - msg_type: This will be set to - * 0x3f (HTT_T2H_MSG_TYPE_HAPS) - * b'15:8 - vdev_id - * b'19:16 - action_code (HTT_T2H_HAPS_ACTION_CODE): - * b'0000: Pause - * b'0001: Pause with One-Shot Unpause - * b'0010: Unpause - * values 3-15: reserved - * b'21:20 - time_type - * b'31:22 - rsvd - * reverse action_code at time specified below - * (units are specified by the type_type bitfield) - * dword1 - b'31:0 uint32_t time_high - * dword2 - b'31:0 uint32_t time_low - */ -typedef enum { - HTT_T2H_HAPS_ACTION_PAUSE = 0x00, - HTT_T2H_HAPS_ACTION_PAUSE_WITH_ONESHOT_UNPAUSE = 0x01, - HTT_T2H_HAPS_ACTION_UNPAUSE = 0x02, -} HTT_T2H_HAPS_ACTION_CODE; - -typedef enum { - HTT_T2H_HAPS_TIME_TYPE_HOST_QTIME = 0x00, - HTT_T2H_HAPS_TIME_TYPE_TSF = 0x01, -} HTT_T2H_HAPS_TIME_TYPE; - -PREPACK struct htt_t2h_power_state_info { - uint32_t msg_type : 8, /* [7:0] */ - vdev_id : 8, /* [15:8] */ - action_code : 4, /* [19:16] */ - time_type: 2, /* [21:20] */ - rsvd: 10; /* [31:22] */ - uint32_t time_low; - uint32_t time_high; -} POSTPACK; - -#define HTT_T2H_POWER_STATE_INFO_SIZE (sizeof(struct htt_t2h_power_state_info)) - -#define HTT_T2H_POWER_STATE_INFO_HTT_VDEV_ID_M 0x0000FF00 -#define HTT_T2H_POWER_STATE_INFO_HTT_VDEV_ID_S 8 - -#define HTT_T2H_POWER_STATE_INFO_HTT_VDEV_ID_GET(_var) \ - (((_var) & HTT_T2H_POWER_STATE_INFO_HTT_VDEV_ID_M) >> \ - HTT_T2H_POWER_STATE_INFO_HTT_VDEV_ID_S) -#define HTT_T2H_POWER_STATE_INFO_HTT_VDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_POWER_STATE_INFO_HTT_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_T2H_POWER_STATE_INFO_HTT_VDEV_ID_S));\ - } while (0) - -#define HTT_T2H_POWER_STATE_INFO_HTT_ACTION_CODE_M 0x000F0000 -#define HTT_T2H_POWER_STATE_INFO_HTT_ACTION_CODE_S 16 - -#define HTT_T2H_POWER_STATE_INFO_HTT_ACTION_CODE_GET(_var) \ - (((_var) & HTT_T2H_POWER_STATE_INFO_HTT_ACTION_CODE_M) >> \ - HTT_T2H_POWER_STATE_INFO_HTT_ACTION_CODE_S) -#define HTT_T2H_POWER_STATE_INFO_HTT_ACTION_CODE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_POWER_STATE_INFO_HTT_ACTION_CODE, _val); \ - ((_var) |= ((_val) << HTT_T2H_POWER_STATE_INFO_HTT_ACTION_CODE_S));\ - } while (0) - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_TYPE_M 0x00300000 -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_TYPE_S 20 - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_TYPE_GET(_var) \ - (((_var) & HTT_T2H_POWER_STATE_INFO_HTT_TIME_TYPE_M) >> \ - HTT_T2H_POWER_STATE_INFO_HTT_TIME_TYPE_S) - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_POWER_STATE_INFO_HTT_TIME_TYPE, _val); \ - ((_var) |= ((_val) << HTT_T2H_POWER_STATE_INFO_HTT_TIME_TYPE_S));\ - } while (0) - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_HIGH_M 0xFFFFFFFF -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_HIGH_S 0 - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_HIGH_GET(_var) \ - (((_var) & HTT_T2H_POWER_STATE_INFO_HTT_TIME_HIGH_M) >> \ - HTT_T2H_POWER_STATE_INFO_HTT_TIME_HIGH_S) - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_HIGH_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_POWER_STATE_INFO_HTT_TIME_HIGH, _val); \ - ((_var) |= ((_val) << HTT_T2H_POWER_STATE_INFO_HTT_TIME_HIGH_S));\ - } while (0) - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_LOW_M 0xFFFFFFFF -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_LOW_S 0 - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_LOW_GET(_var) \ - (((_var) & HTT_T2H_POWER_STATE_INFO_HTT_TIME_LOW_M) >> \ - HTT_T2H_POWER_STATE_INFO_HTT_TIME_LOW_S) - -#define HTT_T2H_POWER_STATE_INFO_HTT_TIME_LOW_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_POWER_STATE_INFO_HTT_TIME_LOW, _val); \ - ((_var) |= ((_val) << HTT_T2H_POWER_STATE_INFO_HTT_TIME_LOW_S));\ - } while (0) - - -/* MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP - * - * The following diagram shows the format of the peer delete all global vdev - * unmap message sent from the target to the host. This message is used to - * send unmap event to host after tid and msduq/mpduq cleanup of all peers - * associated to a vdev, in FW, host cleans up msduq/mpduq based on message. - * - * |31 20|19 16|15 8|7 0| - * |------------------------+----------+-----------------+-----------------| - * | reserved |hw_link_id| global_vdev_id | msg type | - * |-----------------------------------------------------------------------| - * @details - * struct htt_t2h_peer_del_all_global_vdev_id_unmap_t: - * - * The message is interpreted as follows: - * dword0 - b'7:0 - msg_type: This will be set to 0x40 - * (HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP) - * b'15:8 - global_vdev_id : global vdev id assigned by host - * b'19:16 - hw_link_id : hw link id for which unmap is being sent - * b'31:20 - reserved - */ -/* HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP */ -PREPACK struct htt_t2h_peer_del_all_global_vdev_id_unmap_t { - A_UINT32 msg_type: 8, /* bits 7:0 */ - global_vdev_id: 8, /* bits 15:8 */ - hw_link_id: 4, /* bits 19:16 */ - reserved: 12; /* bits 31:20 */ -} POSTPACK; - -#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_M 0x0000FF00 -#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_S 8 -#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_GET(_var) \ - (((_var) & HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_M) >> \ - HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_S) -#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_GLOBAL_VDEV_ID_S)); \ - } while (0) - -#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_M 0x000F0000 -#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_S 16 -#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_GET(_var) \ - (((_var) & HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_M) >> \ - HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_S) -#define HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID, _val); \ - ((_var) |= ((_val) << HTT_T2H_MSG_TYPE_PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP_HW_LINK_ID_S)); \ - } while (0) - - #endif diff --git a/drivers/staging/fw-api/fw/htt_ppdu_stats.h b/drivers/staging/fw-api/fw/htt_ppdu_stats.h index 7f0fb14620de..d1575d7c91ba 100644 --- a/drivers/staging/fw-api/fw/htt_ppdu_stats.h +++ b/drivers/staging/fw-api/fw/htt_ppdu_stats.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2026 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -501,11 +501,6 @@ enum HTT_PPDU_STATS_SEQ_TYPE { HTT_SEQTYPE_BE_UL_MU_OFDMA_TRIG = 13, HTT_SEQTYPE_BE_UL_MU_MIMO_TRIG = 14, HTT_SEQTYPE_BE_UL_BSR_TRIG = 15, - HTT_SEQTYPE_BN_MU_MIMO = 16, - HTT_SEQTYPE_BN_MU_OFDMA = 17, - HTT_SEQTYPE_BN_UL_MU_OFDMA_TRIG = 18, - HTT_SEQTYPE_BN_UL_MU_MIMO_TRIG = 19, - HTT_SEQTYPE_BN_UL_BSR_TRIG = 20, }; typedef enum HTT_PPDU_STATS_SEQ_TYPE HTT_PPDU_STATS_SEQ_TYPE; @@ -712,58 +707,6 @@ typedef enum HTT_PPDU_STATS_SPATIAL_REUSE HTT_PPDU_STATS_SPATIAL_REUSE; (((_val) & HTT_PPDU_STATS_COMMON_TRIG_COOKIE_M) >> \ HTT_PPDU_STATS_COMMON_TRIG_COOKIE_S) -#define HTT_PPDU_STATS_COMMON_TLV_HTT_SEQ_TYPE_M 0x00000001 -#define HTT_PPDU_STATS_COMMON_TLV_HTT_SEQ_TYPE_S 0 - -#define HTT_PPDU_STATS_COMMON_TLV_HTT_SEQ_TYPE_GET(_var) \ - (((_var) & HTT_PPDU_STATS_COMMON_TLV_HTT_SEQ_TYPE_M) >> \ - HTT_PPDU_STATS_COMMON_TLV_HTT_SEQ_TYPE_S) - -#define HTT_PPDU_STATS_COMMON_TLV_HTT_SEQ_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_HTT_SEQ_TYPE, _val); \ - ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_HTT_SEQ_TYPE_S)); \ - } while (0) - -#define HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BASIC_TRIGGER_M 0x00000002 -#define HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BASIC_TRIGGER_S 1 - -#define HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BASIC_TRIGGER_GET(_var) \ - (((_var) & HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BASIC_TRIGGER_M) >> \ - HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BASIC_TRIGGER_S) - -#define HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BASIC_TRIGGER_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BASIC_TRIGGER, _val); \ - ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BASIC_TRIGGER_S)); \ - } while (0) - -#define HTT_PPDU_STATS_COMMON_TLV_IS_MANUAL_ULOFDMA_TRIGGER_M 0x00000004 -#define HTT_PPDU_STATS_COMMON_TLV_IS_MANUAL_ULOFDMA_TRIGGER_S 2 - -#define HTT_PPDU_STATS_COMMON_TLV_IS_MANUAL_ULOFDMA_TRIGGER_GET(_var) \ - (((_var) & HTT_PPDU_STATS_COMMON_TLV_IS_MANUAL_ULOFDMA_TRIGGER_M) >> \ - HTT_PPDU_STATS_COMMON_TLV_IS_MANUAL_ULOFDMA_TRIGGER_S) - -#define HTT_PPDU_STATS_COMMON_TLV_IS_MANUAL_ULOFDMA_TRIGGER_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_IS_MANUAL_ULOFDMA_TRIGGER, _val); \ - ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_IS_MANUAL_ULOFDMA_TRIGGER_S)); \ - } while (0) - -#define HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BSRP_TRIGGER_M 0x00000008 -#define HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BSRP_TRIGGER_S 3 - -#define HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BSRP_TRIGGER_GET(_var) \ - (((_var) & HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BSRP_TRIGGER_M) >> \ - HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BSRP_TRIGGER_S) - -#define HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BSRP_TRIGGER_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BSRP_TRIGGER, _val); \ - ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_IS_COMBINED_UL_BSRP_TRIGGER_S)); \ - } while (0) - enum HTT_SEQ_TYPE { WAL_PPDU_SEQ_TYPE = 0, HTT_PPDU_SEQ_TYPE = 1, @@ -959,57 +902,28 @@ typedef struct { * HTT_PPDU_SEQ_TYPE then decoder should interpret the * seq type as HTT_PPDU_STATS_SEQ_TYPE. * htt_seq_type field will be set to HTT_PPDU_SEQ_TYPE in - * BIT [1 : 1] - is_combined_ul_basic_trigger - Flag to indicate if a - * given UL OFDMA/MU-MIMO Basic trigger is sent combined - * as part of existing DL data sequence. - * BIT [2 : 2] - is_manual_ulofdma_trigger - Flag to indicate if a - * given UL OFDMA trigger is manually triggered from the Host. - * BIT [3 : 3] - is_combined_ul_bsrp_trigger - Flag to indicate if a - * given UL BSRP trigger is sent combined as part of - * an existing DL/UL data sequence - * BIT [4 : 4] - is_sta_dps_seq - Flag to indicate if a TX is to a STA with - * active Dynamic Power Save state (DPS) - * BIT [5 : 5] - is_allow_comb_sched_cmd - Flag to indicate if a given TX - * is part of a allowed combined sched_cmd sequence - * BIT [6 : 6] - is_abort_comb_sched_cmd - Flag to indicate if a given TX - * is part of a aborted combined sched_cmd sequence - * BIT [7 : 7] - is_comb_sched_cmd_pending - Flag to indicate if a the - * first sched_cmd of a combined sched_cmd sequence is - * pending in the current ring. - * BIT [31: 8] - reserved + * firmware versions where this field is defined. + * BIT [31: 1] - reserved */ union { A_UINT32 reserved__htt_seq_type; struct { A_UINT32 htt_seq_type: 1, - is_combined_ul_basic_trigger: 1, - is_manual_ulofdma_trigger: 1, - is_combined_ul_bsrp_trigger: 1, - is_sta_dps_seq: 1, - is_allow_comb_sched_cmd: 1, - is_abort_comb_sched_cmd: 1, - is_comb_sched_cmd_pending: 1, - is_sched_cmd_combined: 1, - reserved3: 23; + reserved3: 31; }; }; + /* is_manual_ulofdma_trigger: + * Flag to indicate if a given UL OFDMA trigger is manually triggered + * from the Host + */ + A_UINT32 is_manual_ulofdma_trigger; + /* is_combined_ul_bsrp_trigger: + * Flag to indicate if a given UL BSRP trigger is sent combined as + * part of existing DL/UL data sequence + */ + A_UINT32 is_combined_ul_bsrp_trigger; /* Flag to indicate if the channel chosen is 320_1 / 320_2 */ A_UINT32 chan_type_320mhz; - - /* - * BIT [15 : 0] - obss_dur_us reports the remaining OBSS dur when - * this FES started OTA. - * BIT [16 : 16] - oprim indicates M/O primary FES. - * BIT [31 : 17] - reserved - */ - union { - A_UINT32 reserved__oprim__obss_dur; - struct { - A_UINT32 obss_dur_us: 16, - oprim: 1, - reserved4: 15; - }; - }; } htt_ppdu_stats_common_tlv; #define HTT_PPDU_STATS_USER_COMMON_TLV_TID_NUM_M 0x000000ff @@ -1974,32 +1888,6 @@ typedef enum HTT_PPDU_STATS_RESP_PPDU_TYPE HTT_PPDU_STATS_RESP_PPDU_TYPE; ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_S)); \ } while (0) -#define HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_M 0x00040000 -#define HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_S 18 - -#define HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_GET(_var) \ - (((_var) & HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_M) >> \ - HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_S) - -#define HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_SET (_var , _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_RATE_TLV_2XLDPC, _val); \ - ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_2xLDPC_S)); \ - } while (0) - -#define HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_M 0x00080000 -#define HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_S 19 - -#define HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_GET(_var) \ - (((_var) & HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_M) >> \ - HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_S) - -#define HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_SET (_var , _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED, _val); \ - ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_IS_NPCA_ENABLED_S)); \ - } while (0) - typedef enum HTT_PPDU_STATS_RU_SIZE { HTT_PPDU_STATS_RU_26, HTT_PPDU_STATS_RU_52, @@ -2019,14 +1907,6 @@ typedef enum HTT_PPDU_STATS_RU_SIZE { HTT_PPDU_STATS_RU_996x4, } HTT_PPDU_STATS_RU_SIZE; -typedef enum HTT_PPDU_STATS_DRU_SIZE { - HTT_PPDU_STATS_DRU_26, - HTT_PPDU_STATS_DRU_52, - HTT_PPDU_STATS_DRU_106, - HTT_PPDU_STATS_DRU_242, - HTT_PPDU_STATS_DRU_484, -} HTT_PPDU_STATS_DRU_SIZE; - typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -2064,7 +1944,6 @@ typedef struct { * Discriminant is field ru_format: * - ru_format = 0: ru_end, ru_start * - ru_format = 1: ru_index, ru_size - * - ru_format = 2: dru_index, dru_size, dru_sbw, dru_sbw_idx * - ru_format = other: reserved for future expansion * * ru_start and ru_end are RU 26 indices @@ -2097,15 +1976,10 @@ typedef struct { * * resp_ru_size is an HTT_PPDU_STATS_RU_SIZE, resp_ru_index * is a size specific index for the given ru_size. - * - * 'is_dru' field indicates if the current RU allocation - * is a distributed RU allocation or not. - * 'dru_sbw' is the spreading BW size of current dru_size. */ union { A_UINT32 resp_ru_start__ru_end; A_UINT32 resp_ru_size__ru_index; - A_UINT32 dru_size__dru_index__dru_sbw_idx__dru_sbw__is_dru; struct { A_UINT32 resp_ru_end: 16, resp_ru_start: 16; @@ -2114,14 +1988,6 @@ typedef struct { A_UINT32 resp_ru_index: 16, resp_ru_size: 16; }; - struct { - A_UINT32 is_dru: 1, - dru_sbw: 3, - dru_sbw_idx: 2, - dru_index: 16, - dru_size: 4, - reserved5: 6; - }; }; /* BIT [ 0 : 0 ] :- resp_type_valid @@ -2209,16 +2075,11 @@ typedef struct { * punctured. * BIT 16 :- flag showing whether EHT extra LTF is applied * for current PPDU - * BIT 17 :- flag to show is_min_rate - * BIT 18 :- flag showing whether PPDU is transmitted with 2xLDPC - * BIT 19 :- flag showing whether PPDU is transmitted with NPCA enabled */ A_UINT32 punc_pattern_bitmap: 16, - extra_eht_ltf: 1, - is_min_rate: 1, - is_2xldpc: 1, - is_npca_enabled: 1, - reserved4: 12; + extra_eht_ltf: 1, + is_min_rate: 1, + reserved4: 14; } htt_ppdu_stats_user_rate_tlv; #define HTT_PPDU_STATS_USR_RATE_VALID_M 0x80000000 diff --git a/drivers/staging/fw-api/fw/htt_stats.h b/drivers/staging/fw-api/fw/htt_stats.h index 28d4c2f06ad1..5a57e7f9f171 100644 --- a/drivers/staging/fw-api/fw/htt_stats.h +++ b/drivers/staging/fw-api/fw/htt_stats.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2026 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -186,7 +186,6 @@ enum htt_dbg_ext_stats_type { * 7 bit htt_peer_sched_stats_tlv * 8 bit htt_peer_ax_ofdma_stats_tlv * 9 bit htt_peer_be_ofdma_stats_tlv - * 10 bit htt_stats_rx_peer_tid_reo_queue_ba_tlv * - config_param2: [Bit31 : Bit0] mac_addr31to0 * - config_param3: [Bit15 : Bit0] mac_addr47to32 * [Bit 16] If this bit is set, reset per peer stats @@ -681,27 +680,23 @@ enum htt_dbg_ext_stats_type { HTT_DBG_ODD_PDEV_BE_TX_MU_OFDMA_STATS = HTT_DBG_EXT_STATS_ODD_PDEV_BE_TX_MU_OFDMA, - /** HTT_DBG_EXT_STATS_ODD_UL_BE_BN_OFDMA + /** HTT_DBG_EXT_STATS_ODD_UL_BE_OFDMA * PARAMS: * - No Params * RESP MSG: * - htt_rx_pdev_be_ul_ofdma_user_stats_tlv */ - HTT_DBG_EXT_STATS_ODD_UL_BE_BN_OFDMA = 60, - /* retain deprecated names as aliases */ - HTT_DBG_EXT_STATS_ODD_UL_BE_OFDMA = - HTT_DBG_EXT_STATS_ODD_UL_BE_BN_OFDMA, + HTT_DBG_EXT_STATS_ODD_UL_BE_OFDMA = 60, + /* retain the deprecated name as an alias */ HTT_DBG_ODD_UL_BE_OFDMA_STATS = - HTT_DBG_EXT_STATS_ODD_UL_BE_BN_OFDMA, + HTT_DBG_EXT_STATS_ODD_UL_BE_OFDMA, - /** HTT_DBG_EXT_STATS_ODD_BE_BN_TXBF_OFDMA_STATS + /** HTT_DBG_EXT_STATS_ODD_BE_TXBF_OFDMA */ - HTT_DBG_EXT_STATS_ODD_BE_BN_TXBF_OFDMA_STATS = 61, - /* retain the deprecated names as aliases */ - HTT_DBG_EXT_STATS_ODD_BE_TXBF_OFDMA = - HTT_DBG_EXT_STATS_ODD_BE_BN_TXBF_OFDMA_STATS, + HTT_DBG_EXT_STATS_ODD_BE_TXBF_OFDMA = 61, + /* retain the deprecated name as an alias */ HTT_DBG_ODD_BE_TXBF_OFDMA_STATS = - HTT_DBG_EXT_STATS_ODD_BE_BN_TXBF_OFDMA_STATS, + HTT_DBG_EXT_STATS_ODD_BE_TXBF_OFDMA, /** HTT_DBG_EXT_STATS_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG * PARAMS: @@ -834,141 +829,6 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_ELIGIBLE = 74, - /** HTT_DBG_EXT_STATS_PAPRD_PB - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_phy_paprd_pb_tlv - */ - HTT_DBG_EXT_STATS_PAPRD_PB = 75, - - /** HTT_DBG_EXT_STATS_HDS_PROF - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_hds_prof_stats_tlv - */ - HTT_DBG_EXT_STATS_HDS_PROF = 76, - - /** HTT_DBG_EXT_STATS_OPTIONAL_CONFIGS - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_optional_configs_tlv - */ - HTT_DBG_EXT_STATS_OPTIONAL_CONFIGS = 77, - - /** HTT_DBG_EXT_STATS_PDEV_SAM - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_pdev_sam_tlv - */ - HTT_DBG_EXT_STATS_PDEV_SAM = 78, - - /** HTT_DBG_EXT_STATS_FTM - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_ftm_tlv - */ - HTT_DBG_EXT_STATS_FTM = 79, - - /** HTT_DBG_EXT_STATS_PDEV_FTM_TPCCAL_EXT - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_pdev_ftm_tpccal_ext_tlv - */ - HTT_DBG_EXT_STATS_PDEV_FTM_TPCCAL_EXT = 80, - - /** HTT_DBG_EXT_STATS_ANI_HISTOGRAM - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_phy_ani_hist_tlv - * */ - HTT_DBG_EXT_STATS_ANI_HISTOGRAM = 81, - - /** HTT_DBG_EXT_STATS_RESET_HISTORY - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_reset_history_tlv - */ - HTT_DBG_EXT_STATS_RESET_HISTORY = 82, - - /** HTT_DBG_EXT_STATS_REGULATORY - * PARAMS: - * - config_param0 : Regulatory stats subtype: - * htt_stats_regulatory_subtype_t - * - config_param1 : (Depends on Subtype) - * RESP MSG: - * - * if (subtype == HTT_STATS_REGULATORY_SUBTYPE_REGDB): - * config_param1 - Bitmap of Regdomains to include - * [bit 0 - 2G, - * bit 1 - 5G, - * bit 2 - unused - * bits 3-5 - 6G AP (LPI/SP/VLP) - * bits 6-8 - 6G CLIENT 1 (LPI/SP/VLP) - * bits 9-11- 6G CLIENT 2 (LPI/SP/VLP)] - * RESP Tags: - * - htt_stats_regdb_ctry_tlv - * - htt_stats_regdb_regdomain_tlv * n (based on config_param1) - * else if (subtype == HTT_STATS_REGULATORY_SUBTYPE_6GHZ): - * no params - * RESP Tags: - * - htt_stats_reg_6g_tlv - * - htt_stats_reg_6g_ch_power_info_tlv * n - * - htt_stats_reg_6g_oobe_tlv - * else if (subtype == HTT_STATS_REGULATORY_SUBTYPE_CTL): - * no params - * RESP Tags: - * - htt_stats_ctl_tlv - * - htt_stats_enhanced_ctl_tlv - * else if (subtype == HTT_STATS_REGULATORY_SUBTYPE_DFS): - * no params - * RESP Tags: - * - htt_stats_dfs_radar_history_tlv - * - htt_stats_dfs_ini_tlv - * - htt_stats_dfs_ipc_ring_tlv - */ - HTT_DBG_EXT_STATS_REGULATORY = 83, - - /** HTT_DBG_EXT_STATS_TX_SELFGEN_RESP_FRAME_STATS - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_tx_selfgen_resp_frame_stats_tlv - */ - HTT_DBG_EXT_STATS_TX_SELFGEN_RESP_FRAME_STATS = 84, - - /** HTT_DBG_EXT_STATS_DPD - * PARAMS: - * - No Params - * RESP MSG: - * - htt_stats_dpd_halphy_tlv - * - htt_stats_dpd_hw_cal_params_tlv - * - htt_stats_dpd_hw_cal_results_tlv - */ - HTT_DBG_EXT_STATS_DPD = 85, - - HTT_DBG_EXT_STATS_NPCA = 86, - - /** HTT_DBG_EXT_STATS_PHY_DPD_TPC_DEBUG - * PARAMS: - * - config_param0: subtype: htt_stats_phy_dpd_tpc_debug_subtype_t - * 0 = DPD debug, 1 = TPC debug - * - config_param1: chain bitmask (0 = default to chain 0 only) - * RESP MSG: - * if (subtype == HTT_STATS_PHY_DPD_TPC_DEBUG_SUBTYPE_DPD): - * - htt_stats_phy_dpd_debug_chain_v1_tlv (one per requested chain) - * if (subtype == HTT_STATS_PHY_DPD_TPC_DEBUG_SUBTYPE_TPC): - * - htt_stats_phy_tpc_debug_chain_v1_tlv (one per requested chain) - */ - HTT_DBG_EXT_STATS_PHY_DPD_TPC_DEBUG = 87, - /* keep this last */ HTT_DBG_NUM_EXT_STATS = 256, @@ -1041,25 +901,6 @@ typedef enum { * TLV: htt_tx_pdev_ul_be_mu_ofdma_sch_stats_tlv */ HTT_UPLOAD_BE_UL_MU_OFDMA_STATS, - - /* - * Upload BN UL MU-OFDMA + BN DL MU-OFDMA stats, - * TLV: htt_stats_tx_pdev_bn_dl_mu_ofdma_tlv and - * htt_stats_tx_pdev_bn_ul_mu_ofdma_tlv - */ - HTT_UPLOAD_BN_MU_OFDMA_STATS, - - /* - * Upload BN DL MU-OFDMA - * TLV: htt_stats_tx_pdev_bn_dl_mu_ofdma_tlv - */ - HTT_UPLOAD_BN_DL_MU_OFDMA_STATS, - - /* - * Upload BN UL MU-OFDMA - * TLV: htt_stats_tx_pdev_bn_ul_mu_ofdma_tlv - */ - HTT_UPLOAD_BN_UL_MU_OFDMA_STATS, } htt_mu_stats_upload_t; /* htt_tx_rate_stats_upload_t @@ -1074,14 +915,11 @@ typedef enum { HTT_TX_RATE_STATS_DEFAULT, /* - * Upload 11be and 11bn OFDMA TX stats + * Upload 11be OFDMA TX stats * * TLV: htt_tx_pdev_rate_stats_be_ofdma_tlv */ - HTT_TX_RATE_STATS_UPLOAD_11BE_11BN_OFDMA, - /* retain prior name as an alias */ - HTT_TX_RATE_STATS_UPLOAD_11BE_OFDMA = - HTT_TX_RATE_STATS_UPLOAD_11BE_11BN_OFDMA, + HTT_TX_RATE_STATS_UPLOAD_11BE_OFDMA, } htt_tx_rate_stats_upload_t; /* htt_rx_ul_trigger_stats_upload_t @@ -1096,14 +934,11 @@ typedef enum { HTT_RX_UL_TRIGGER_STATS_UPLOAD_11AX_OFDMA, /* - * Upload 11be and 11bn UL OFDMA RX Trigger stats + * Upload 11be UL OFDMA RX Trigger stats * * TLV: htt_rx_pdev_be_ul_trigger_stats_tlv */ - HTT_RX_UL_TRIGGER_STATS_UPLOAD_11BE_11BN_OFDMA, - /* retain prior name as an alias */ - HTT_RX_UL_TRIGGER_STATS_UPLOAD_11BE_OFDMA = - HTT_RX_UL_TRIGGER_STATS_UPLOAD_11BE_11BN_OFDMA, + HTT_RX_UL_TRIGGER_STATS_UPLOAD_11BE_OFDMA, } htt_rx_ul_trigger_stats_upload_t; /* @@ -1124,11 +959,6 @@ typedef enum { * TLV: htt_rx_pdev_ul_mumimo_trig_be_stats_tlv */ HTT_RX_UL_MUMIMO_TRIGGER_STATS_UPLOAD_11BE, - /* - * Upload 11bn UL MUMIMO RX Trigger stats - * TLV: htt_rx_pdev_ul_mumimo_trig_bn_stats_tlv - */ - HTT_RX_UL_MUMIMO_TRIGGER_STATS_UPLOAD_11BN, } htt_rx_ul_mumimo_trigger_stats_upload_t; /* htt_tx_pdev_txbf_ofdma_stats_upload_t @@ -1143,13 +973,11 @@ typedef enum { HTT_UPLOAD_AX_TXBF_OFDMA_STATS, /* - * Upload 11be and 11bn TXBF OFDMA stats + * Upload 11be TXBF OFDMA stats * * TLV: htt_tx_pdev_be_txbf_ofdma_stats_t */ - HTT_UPLOAD_BE_BN_TXBF_OFDMA_STATS, - /* retain previous name as alias */ - HTT_UPLOAD_BE_TXBF_OFDMA_STATS = HTT_UPLOAD_BE_BN_TXBF_OFDMA_STATS, + HTT_UPLOAD_BE_TXBF_OFDMA_STATS, } htt_tx_pdev_txbf_ofdma_stats_upload_t; /* htt_tx_pdev_puncture_stats_upload_t @@ -1174,15 +1002,7 @@ typedef enum { #define HTT_TX_HWQ_MAX_CMD_STALL_STATS 5 #define HTT_TX_HWQ_MAX_FES_RESULT_STATS 10 #define HTT_PDEV_STATS_PPDU_DUR_HIST_BINS 16 -#define HTT_PDEV_STATS_PPDU_DUR_HIST_EXT_BINS 6 #define HTT_PDEV_STATS_PPDU_DUR_HIST_INTERVAL_US 250 -/* Max seq ctrl can be active in txq at a given instant */ -#define HTT_PDEV_STATS_MAX_SEQ_CTRL_HIST 4 -/* For BE max active seq_ctrl that can be in HWQ */ -#define HTT_PDEV_STATS_MAX_ACTIVE_SEQ_IN_HWQ_HIST 2 -#define HTT_PDEV_STATS_TXOP_DUR_HIST_BINS 12 -#define HTT_PDEV_STATS_TXOP_DUR_HIST_INTERVAL_US 1000 -#define HTT_PDEV_STATS_MAX_DATA_TID_COUNT 8 typedef enum { HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0, @@ -1218,9 +1038,7 @@ typedef struct { #define HTT_TX_PDEV_STATS_CMN_MAC_ID_GET(_var) \ (((_var) & HTT_TX_PDEV_STATS_CMN_MAC_ID_M) >> \ HTT_TX_PDEV_STATS_CMN_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_PDEV_CMN_MAC_ID_GET(_var) \ - HTT_TX_PDEV_STATS_CMN_MAC_ID_GET(_var) + #define HTT_TX_PDEV_STATS_CMN_MAC_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_TX_PDEV_STATS_CMN_MAC_ID, _val); \ @@ -1235,13 +1053,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** Num PPDUs queued to HW */ A_UINT32 hw_queued; /** Num PPDUs reaped from HW */ @@ -1419,47 +1231,10 @@ typedef struct { /* upper 32 bits of the tx_bytes value */ A_UINT32 high_32; } bytes_sent; - /* increment array based on AC */ - A_UINT32 num_ppdu_tried_ota_per_ac[HTT_NUM_AC_WMM]; - /** Number of hardware reaped (Tx completed) packets in LPI mode */ - A_UINT32 hw_reaped_lpi; - /** Number of hardware reaped (Tx completed) packets in SP mode */ - A_UINT32 hw_reaped_sp; - /** Number of hardware reaped (Tx completed) packets in VLP mode */ - A_UINT32 hw_reaped_vlp; - A_UINT32 avg_channel_access_latency_per_ac[HTT_NUM_AC_WMM]; /* usec units */ - A_UINT32 seq_posted_per_tid[HTT_PDEV_STATS_MAX_DATA_TID_COUNT]; } htt_stats_tx_pdev_cmn_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_cmn_tlv htt_tx_pdev_stats_cmn_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - A_UINT32 pdev_id__word; - struct { - A_UINT32 - pdev_id: 8, - reserved: 24; - }; - }; - A_UINT32 pending_seq_on_sched_post_hist[HTT_PDEV_STATS_MAX_SEQ_CTRL_HIST]; -} htt_stats_tx_pdev_pending_seq_cnt_on_sched_post_hist_tlv; - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_PDEV_ID_M 0x000000ff -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_PDEV_ID_S 0 - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_PDEV_ID_GET(_var) \ - (((_var) & HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_PDEV_ID_M) >> \ - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_PDEV_ID_S) - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_PDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_PDEV_ID_S)); \ - } while (0) - - #define HTT_TX_PDEV_STATS_URRN_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { @@ -1482,13 +1257,6 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_flush_tlv htt_tx_pdev_stats_flush_tlv_v; -#define HTT_TX_PDEV_MDSB_MAX_NUM_USERS 8 -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 pdev_id; - A_UINT32 mdsb_num_users_histogram[HTT_TX_PDEV_MDSB_MAX_NUM_USERS]; -} htt_stats_tx_pdev_mdsb_num_users_histogram_tlv; - #define HTT_TX_PDEV_STATS_MLO_ABORT_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { @@ -1644,11 +1412,6 @@ typedef struct { A_UINT32 mu_mimo_num_seq_posted[HTT_STATS_NUM_NR_BINS]; A_UINT32 mu_mimo_num_ppdu_posted_per_burst[HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST_WORDS]; - /** - * Wi-Fi version identifier to differentiate stats while printing - * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value). - */ - A_UINT32 wifi_version; } htt_stats_mu_ppdu_dist_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_mu_ppdu_dist_tlv htt_pdev_mu_ppdu_dist_tlv_v; @@ -1698,7 +1461,6 @@ typedef htt_stats_pdev_ctrl_path_tx_stats_tlv htt_pdev_ctrl_path_tx_stats_tlv_v; * - HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG * - HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG * - HTT_STATS_MU_PPDU_DIST_TAG - * - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_ON_SCHED_POST_HIST_TAG */ /* NOTE: * This structure is for documentation, and cannot be safely used directly. @@ -1716,8 +1478,6 @@ typedef struct _htt_tx_pdev_stats { htt_stats_tx_pdev_tried_mpdu_cnt_hist_tlv tried_mpdu_cnt_hist_tlv; htt_stats_pdev_ctrl_path_tx_stats_tlv ctrl_path_tx_tlv; htt_stats_mu_ppdu_dist_tlv mu_ppdu_dist_tlv; - htt_stats_tx_pdev_pending_seq_cnt_on_sched_post_hist_tlv - pending_seq_cnt_on_sched_post_hist_tlv; } htt_tx_pdev_stats_t; #endif /* ATH_TARGET */ @@ -1761,17 +1521,10 @@ typedef htt_stats_hw_wd_timeout_tlv htt_hw_stats_wd_timeout_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /** - * BIT [ 7 : 0] :- mac_id + /* BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; A_UINT32 tx_abort; A_UINT32 tx_abort_fail_count; A_UINT32 rx_abort; @@ -1835,23 +1588,13 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_hw_pdev_errs_tlv htt_hw_stats_pdev_errs_tlv; -#define HTT_STATS_HW_PDEV_ERRS_MAC_ID_GET(word) \ - ((word >> 0) & 0xff) - typedef struct { htt_tlv_hdr_t tlv_hdr; - /** - * BIT [ 7 : 0] :- mac_id + /* BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; A_UINT32 last_unpause_ppdu_id; A_UINT32 hwsch_unpause_wait_tqm_write; A_UINT32 hwsch_dummy_tlv_skipped; @@ -1867,9 +1610,6 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_whal_tx_tlv htt_hw_stats_whal_tx_tlv; -#define HTT_STATS_WHAL_TX_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -1944,9 +1684,6 @@ typedef struct _htt_pdev_err_stats { #define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_GET(_var) \ (((_var) & HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_M) >> \ HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PEER_MSDU_FLOWQ_TX_FLOW_NUMBER_GET(_var) \ - HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_GET(_var) #define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_SET(_var, _val) \ do { \ @@ -1957,9 +1694,6 @@ typedef struct _htt_pdev_err_stats { #define HTT_MSDU_FLOW_STATS_TID_NUM_GET(_var) \ (((_var) & HTT_MSDU_FLOW_STATS_TID_NUM_M) >> \ HTT_MSDU_FLOW_STATS_TID_NUM_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PEER_MSDU_FLOWQ_TID_NUM_GET(_var) \ - HTT_MSDU_FLOW_STATS_TID_NUM_GET(_var) #define HTT_MSDU_FLOW_STATS_TID_NUM_SET(_var, _val) \ do { \ @@ -1970,9 +1704,6 @@ typedef struct _htt_pdev_err_stats { #define HTT_MSDU_FLOW_STATS_DROP_GET(_var) \ (((_var) & HTT_MSDU_FLOW_STATS_DROP_M) >> \ HTT_MSDU_FLOW_STATS_DROP_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PEER_MSDU_FLOWQ_DROP_RULE_GET(_var) \ - HTT_MSDU_FLOW_STATS_DROP_GET(_var) #define HTT_MSDU_FLOW_STATS_DROP_SET(_var, _val) \ do { \ @@ -1996,15 +1727,7 @@ typedef struct _htt_msdu_flow_stats_tlv { * BIT [20 : 20] :- drop_rule * BIT [31 : 21] :- reserved */ - union { - struct { - A_UINT32 tx_flow_number : 16; - A_UINT32 tid_num : 4; - A_UINT32 drop_rule : 1; - A_UINT32 reserved : 11; - }; - A_UINT32 tx_flow_no__tid_num__drop_rule; - }; + A_UINT32 tx_flow_no__tid_num__drop_rule; A_UINT32 last_cycle_enqueue_count; A_UINT32 last_cycle_dequeue_count; A_UINT32 last_cycle_drop_count; @@ -2028,9 +1751,7 @@ typedef htt_stats_peer_msdu_flowq_tlv htt_msdu_flow_stats_tlv; #define HTT_TX_TID_STATS_SW_PEER_ID_GET(_var) \ (((_var) & HTT_TX_TID_STATS_SW_PEER_ID_M) >> \ HTT_TX_TID_STATS_SW_PEER_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_TID_DETAILS_SW_PEER_ID_GET(_var) \ - HTT_TX_TID_STATS_SW_PEER_ID_GET(_var) + #define HTT_TX_TID_STATS_SW_PEER_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_SW_PEER_ID, _val); \ @@ -2040,9 +1761,7 @@ typedef htt_stats_peer_msdu_flowq_tlv htt_msdu_flow_stats_tlv; #define HTT_TX_TID_STATS_TID_NUM_GET(_var) \ (((_var) & HTT_TX_TID_STATS_TID_NUM_M) >> \ HTT_TX_TID_STATS_TID_NUM_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_TID_DETAILS_TID_NUM_GET(_var) \ - HTT_TX_TID_STATS_TID_NUM_GET(_var) + #define HTT_TX_TID_STATS_TID_NUM_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_TID_NUM, _val); \ @@ -2058,9 +1777,7 @@ typedef htt_stats_peer_msdu_flowq_tlv htt_msdu_flow_stats_tlv; #define HTT_TX_TID_STATS_NUM_SCHED_PENDING_GET(_var) \ (((_var) & HTT_TX_TID_STATS_NUM_SCHED_PENDING_M) >> \ HTT_TX_TID_STATS_NUM_SCHED_PENDING_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_TID_DETAILS_NUM_SCHED_PENDING_GET(_var) \ - HTT_TX_TID_STATS_NUM_SCHED_PENDING_GET(_var) + #define HTT_TX_TID_STATS_NUM_SCHED_PENDING_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_NUM_SCHED_PENDING, _val); \ @@ -2070,9 +1787,7 @@ typedef htt_stats_peer_msdu_flowq_tlv htt_msdu_flow_stats_tlv; #define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_GET(_var) \ (((_var) & HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_M) >> \ HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_TID_DETAILS_NUM_PPDU_IN_HWQ_GET(_var) \ - HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_GET(_var) + #define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ, _val); \ @@ -2089,26 +1804,13 @@ typedef struct _htt_tx_tid_stats_tlv { * BIT [15 : 0] :- sw_peer_id * BIT [31 : 16] :- tid_num */ - union { - struct { - A_UINT32 sw_peer_id : 16; - A_UINT32 tid_num : 16; - }; - A_UINT32 sw_peer_id__tid_num; - }; + A_UINT32 sw_peer_id__tid_num; /** * BIT [ 7 : 0] :- num_sched_pending * BIT [15 : 8] :- num_ppdu_in_hwq * BIT [31 : 16] :- reserved */ - union { - struct { - A_UINT32 num_sched_pending : 8; - A_UINT32 num_ppdu_in_hwq : 8; - A_UINT32 reserved : 16; - }; - A_UINT32 num_sched_pending__num_ppdu_in_hwq; - }; + A_UINT32 num_sched_pending__num_ppdu_in_hwq; A_UINT32 tid_flags; /** per tid # of hw_queued ppdu */ A_UINT32 hw_queued; @@ -2138,26 +1840,13 @@ typedef struct _htt_tx_tid_stats_v1_tlv { * BIT [15 : 0] :- sw_peer_id * BIT [31 : 16] :- tid_num */ - union { - struct { - A_UINT32 sw_peer_id : 16; - A_UINT32 tid_num : 16; - }; - A_UINT32 sw_peer_id__tid_num; - }; + A_UINT32 sw_peer_id__tid_num; /** * BIT [ 7 : 0] :- num_sched_pending * BIT [15 : 8] :- num_ppdu_in_hwq * BIT [31 : 16] :- reserved */ - union { - struct { - A_UINT32 num_sched_pending : 8; - A_UINT32 num_ppdu_in_hwq : 8; - A_UINT32 reserved : 16; - }; - A_UINT32 num_sched_pending__num_ppdu_in_hwq; - }; + A_UINT32 num_sched_pending__num_ppdu_in_hwq; A_UINT32 tid_flags; /** Max qdepth in bytes reached by this tid */ A_UINT32 max_qdepth_bytes; @@ -2204,21 +1893,10 @@ typedef struct _htt_tx_tid_stats_v1_tlv { */ A_UINT32 head_msdu_tqm_timestamp_us; A_UINT32 head_msdu_tqm_latency_us; - A_UINT32 pause_module_id_ext; - A_UINT32 block_module_id_ext; } htt_stats_tx_tid_details_v1_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_tid_details_v1_tlv htt_tx_tid_stats_v1_tlv; -#define HTT_STATS_TX_TID_DETAILS_V1_SW_PEER_ID_GET(word) \ - (((word) >> 0) & 0xffff) -#define HTT_STATS_TX_TID_DETAILS_V1_TID_NUM_GET(word) \ - (((word) >> 16) & 0xffff) -#define HTT_STATS_TX_TID_DETAILS_V1_NUM_SCHED_PENDING_GET(word) \ - (((word) >> 0) & 0xff) -#define HTT_STATS_TX_TID_DETAILS_V1_NUM_PPDU_IN_HWQ_GET(word) \ - (((word) >> 8) & 0xff) - #define HTT_RX_TID_STATS_SW_PEER_ID_M 0x0000ffff #define HTT_RX_TID_STATS_SW_PEER_ID_S 0 #define HTT_RX_TID_STATS_TID_NUM_M 0xffff0000 @@ -2227,9 +1905,7 @@ typedef htt_stats_tx_tid_details_v1_tlv htt_tx_tid_stats_v1_tlv; #define HTT_RX_TID_STATS_SW_PEER_ID_GET(_var) \ (((_var) & HTT_RX_TID_STATS_SW_PEER_ID_M) >> \ HTT_RX_TID_STATS_SW_PEER_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RX_TID_DETAILS_SW_PEER_ID_GET(_var) \ - HTT_RX_TID_STATS_SW_PEER_ID_GET(_var) + #define HTT_RX_TID_STATS_SW_PEER_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_RX_TID_STATS_SW_PEER_ID, _val); \ @@ -2239,9 +1915,7 @@ typedef htt_stats_tx_tid_details_v1_tlv htt_tx_tid_stats_v1_tlv; #define HTT_RX_TID_STATS_TID_NUM_GET(_var) \ (((_var) & HTT_RX_TID_STATS_TID_NUM_M) >> \ HTT_RX_TID_STATS_TID_NUM_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RX_TID_DETAILS_TID_NUM_GET(_var) \ - HTT_RX_TID_STATS_TID_NUM_GET(_var) + #define HTT_RX_TID_STATS_TID_NUM_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_RX_TID_STATS_TID_NUM, _val); \ @@ -2255,13 +1929,7 @@ typedef struct _htt_rx_tid_stats_tlv { * BIT [15 : 0] : sw_peer_id * BIT [31 : 16] : tid_num */ - union { - struct { - A_UINT32 sw_peer_id : 16; - A_UINT32 tid_num : 16; - }; - A_UINT32 sw_peer_id__tid_num; - }; + A_UINT32 sw_peer_id__tid_num; /** Stored as little endian */ A_UINT8 tid_name[MAX_HTT_TID_NAME]; /** @@ -2279,251 +1947,6 @@ typedef struct _htt_rx_tid_stats_tlv { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_tid_details_tlv htt_rx_tid_stats_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - - /* Lower 4 bytes (bytes 0-3) of the MAC address */ - A_UINT32 peer_mac_addr_31_0; - /* Upper 2 bytes (bytes 4-5) of MAC, and TID (1 byte) */ - A_UINT32 peer_mac_addr_47_32_and_tid_num; - - /** - * BIT [11: 0] : Starting Sequence number of the session, - * this changes whenever window moves - * BIT [21:12] : Points to last forwarded packet - */ - union { - A_UINT32 ssn_current_index; - struct { - A_UINT32 ssn : 12, - current_index : 10, - reserved_0 : 10; - }; - }; - - /** Current PN number */ - A_UINT32 pn_31_0; - A_UINT32 pn_63_32; - A_UINT32 pn_95_64; - A_UINT32 pn_127_96; - - /** - * Timestamp of arrival of the last MPDU for this queue (in microseconds) - */ - A_UINT32 last_rx_enqueue_timestamp_us; - - /** Timestamp of forwarding an MPDU (in microseconds) */ - A_UINT32 last_rx_dequeue_timestamp_us; - - /** The number of MPDUs, MSDUs in the queue */ - union { - A_UINT32 mpdu_msdu_cnt; - struct { - A_UINT32 current_mpdu_cnt : 16, - current_msdu_cnt : 16; - }; - }; - - /** The number of times the window moved more then 2K */ - A_UINT32 window_jump_2k_cnt; - - /** - * The number of times that REO started forwarding frames even though - * there is a hole in the bitmap. - * Forwarding reason is Timeout. - */ - A_UINT32 timeout_cnt; - - /** - * The number of times that REO started forwarding frames even though - * there is a hole in the bitmap. - * Forwarding reason is reception of BAR frame. - */ - A_UINT32 forward_due_to_bar_cnt; - - /** The number of duplicate frames that have been detected */ - A_UINT32 duplicate_cnt; - - /** - * The number of frames that have been received in order without a hole - * that prevented them from being forwarded immediately. - */ - A_UINT32 frames_in_order_cnt; - - /** The number of times a BAR frame is received. */ - A_UINT32 bar_received_cnt; - - /** - * The total number of MPDU frames that have been processed, - * this includes the duplicates. - */ - A_UINT32 mpdu_frames_processed_cnt; - - /** - * The total number of MSDU frames that have been processed, - * this includes the duplicates. - */ - A_UINT32 msdu_frames_processed_cnt; - - /** - * An approximation of the number of bytes received for - * this queue, in 64 byte units. - */ - A_UINT32 total_processed_byte_cnt; - - /** The number of MPDUs received after the window had already moved on */ - A_UINT32 late_receive_mpdu_cnt; - - /** The number of times a hole was created in the receive bitmap */ - A_UINT32 hole_cnt; - - /** - * The number of holes in the bitmap that moved due to aging - * counter expiry - */ - A_UINT32 aging_drop_mpdu_cnt; - - /** - * The number of times holes got removed from the bitmap due to - * aging counter expiry - */ - A_UINT32 aging_drop_interval_cnt; - - /** The number of ADDBA Req received */ - A_UINT32 addba_req_cnt; - - /** The number of ADDBA Resp replied for RX ADDBA Req */ - A_UINT32 addba_resp_cnt; - - /** The number of ADDBA Resp sent successfully */ - A_UINT32 addba_rsp_success_cnt; - - /** The number of ADDBA Resp sent failed */ - A_UINT32 addba_rsp_fail_cnt; - - /** The number of DELBA Req received */ - A_UINT32 delba_req_cnt; - - /** The number of DELBA Req sent successfully */ - A_UINT32 delba_tx_success_cnt; - - /** The number of DELBA Req sent failed */ - A_UINT32 delba_tx_fail_cnt; - - /** BA window size established */ - A_UINT32 ba_win_size; - - /** PN size established */ - A_UINT32 pn_size; -} htt_stats_rx_peer_tid_reo_queue_ba_tlv; - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MAC_ADDR_SET(_tlv_ptr, _mac_addr_ptr) \ - do { \ - A_UINT32 __packed_mac_47_32; \ - /* Pack MAC addr bytes [0-3] into peer_mac_addr_31_0 */ \ - (_tlv_ptr)->peer_mac_addr_31_0 = (A_UINT32) \ - (((_mac_addr_ptr)[0] << 0) | \ - ((_mac_addr_ptr)[1] << 8) | \ - ((_mac_addr_ptr)[2] << 16) | \ - ((_mac_addr_ptr)[3] << 24)); \ - /* - * Pack MAC addr bytes [4-5] into the LOWER 16 bits of - * peer_mac_addr_47_32_and_tid_num - */ \ - __packed_mac_47_32 = (A_UINT32) \ - (((_mac_addr_ptr)[4] << 0) | \ - ((_mac_addr_ptr)[5] << 8)); \ - /* - * Set lower 16 bits of peer_mac_addr_47_32_and_tid_num, - * preserving upper 16 bits (which includes the TID) if already set - */ \ - (_tlv_ptr)->peer_mac_addr_47_32_and_tid_num &= ~0x0000FFFF; /* Clear existing MAC addr bits (lower 16) */ \ - (_tlv_ptr)->peer_mac_addr_47_32_and_tid_num |= __packed_mac_47_32; \ - } while (0) -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MAC_ADDR_GET(_tlv_ptr, _dest_mac_addr_ptr) \ - do { \ - A_UINT32 __mac_31_0_val = (_tlv_ptr)->peer_mac_addr_31_0; \ - /* Extract MAC bytes [4-5] from the LOWER 16 bits of peer_mac_addr_47_32_and_tid */ \ - A_UINT32 __mac_47_32_val = ((_tlv_ptr)->peer_mac_addr_47_32_and_tid_num) & 0xFFFF; \ - (_dest_mac_addr_ptr)[0] = (A_UINT8)((__mac_31_0_val >> 0) & 0xFF); \ - (_dest_mac_addr_ptr)[1] = (A_UINT8)((__mac_31_0_val >> 8) & 0xFF); \ - (_dest_mac_addr_ptr)[2] = (A_UINT8)((__mac_31_0_val >> 16) & 0xFF); \ - (_dest_mac_addr_ptr)[3] = (A_UINT8)((__mac_31_0_val >> 24) & 0xFF); \ - (_dest_mac_addr_ptr)[4] = (A_UINT8)((__mac_47_32_val >> 0) & 0xFF); \ - (_dest_mac_addr_ptr)[5] = (A_UINT8)((__mac_47_32_val >> 8) & 0xFF); \ - } while (0) - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_M 0x00FF0000 /* Mask for TID_NUM */ -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_S 16 /* Shift for TID_NUM */ - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_GET(_var) \ - (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_M) >> \ - HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_S) - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM, _val); \ - ((_var) |= ((_val) << HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_TID_NUM_S)); \ - } while (0) - -/* Macros for ssn and current_index */ -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_M 0x00000fff -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_S 0 -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_M 0x003ff000 -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_S 12 - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_GET(_var) \ - (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_M) >> \ - HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_S) - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN, _val); \ - ((_var) |= ((_val) << HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_SSN_S)); \ - } while (0) - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_GET(_var) \ - (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_M) >> \ - HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_S) - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX, _val); \ - ((_var) |= ((_val) << HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_INDEX_S)); \ - } while (0) - -/* Macros for mpdu/msdu count */ -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_M 0x0000ffff -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_S 0 -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_M 0xffff0000 -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_S 16 - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_GET(_var) \ - (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_M) >> \ - HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_MPDU_CNT_GET(_var) \ - HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_GET(_var) -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT, _val); \ - ((_var) |= ((_val) << HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MPDU_CNT_S)); \ - } while (0) - -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_GET(_var) \ - (((_var) & HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_M) >> \ - HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_CURRENT_MSDU_CNT_GET(_var) \ - HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_GET(_var) -#define HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT, _val); \ - ((_var) |= ((_val) << HTT_STATS_RX_PEER_TID_REO_QUEUE_BA_MSDU_CNT_S)); \ - } while (0) - - #define HTT_MAX_COUNTER_NAME 8 typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -2542,9 +1965,9 @@ typedef struct { A_UINT32 mpdu_cnt; /** Number of rx MSDU */ A_UINT32 msdu_cnt; - /** lower 32 bits of pause bitmap */ + /** pause bitmap */ A_UINT32 pause_bitmap; - /** lower 32 bits of block bitmap */ + /** block bitmap */ A_UINT32 block_bitmap; /** current timestamp */ A_UINT32 current_timestamp; @@ -2574,10 +1997,6 @@ typedef struct { A_UINT32 inactive_time; /** Number of MPDUs dropped after max retries */ A_UINT32 remove_mpdus_max_retries; - /** extension with upper 32 bits of pause bitmap */ - A_UINT32 pause_bitmap_ext; - /** extension with upper 32 bits of block bitmap */ - A_UINT32 block_bitmap_ext; } htt_stats_peer_stats_cmn_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_peer_stats_cmn_tlv htt_peer_stats_cmn_tlv; @@ -2597,22 +2016,6 @@ typedef htt_stats_peer_stats_cmn_tlv htt_peer_stats_cmn_tlv; #define HTT_PEER_DETAILS_SRC_INFO_M 0x00000fff #define HTT_PEER_DETAILS_SRC_INFO_S 0 -#define HTT_PEER_DETAILS_PEER_PS_ENTRY_M 0x000000ff -#define HTT_PEER_DETAILS_PEER_PS_ENTRY_S 0 -#define HTT_PEER_DETAILS_PEER_PS_EXIT_M 0x0000ff00 -#define HTT_PEER_DETAILS_PEER_PS_EXIT_S 8 -#define HTT_PEER_DETAILS_PEER_PSPOLL_TRIGGER_M 0x00ff0000 -#define HTT_PEER_DETAILS_PEER_PSPOLL_TRIGGER_S 16 -#define HTT_PEER_DETAILS_PEER_UAPSD_TRIGGER_M 0xff000000 -#define HTT_PEER_DETAILS_PEER_UAPSD_TRIGGER_S 24 - -#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_0_M 0x000003ff -#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_0_S 0 -#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_1_M 0x000ffc00 -#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_1_S 10 -#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_2_M 0x3ff00000 -#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_2_S 20 - #define HTT_PEER_DETAILS_SET(word, httsym, val) \ do { \ @@ -2658,34 +2061,6 @@ typedef struct { rsvd1 : 20; /* [31:12] */ }; }; - - /* Dword 10 */ - union { - A_UINT32 word__peer_ps_entry__peer_ps_exit__peer_pspoll_trigger_received__peer_uapsd_trigger_received; - struct { - A_UINT32 peer_ps_entry : 8, /* [7:0] */ - peer_ps_exit : 8, /* [15:8] */ - peer_pspoll_trigger_received : 8, /* [23:16] */ - peer_uapsd_trigger_received : 8; /* [31:24] */ - }; - }; - - /* Dword 11 */ - union { - A_UINT32 word__peer_ps_histogram_0__peer_ps_histogram_1__peer_ps_histogram_2; - struct { - /* - * This word holds 3 10-bit histograms of power-save durations: - * bits 9:0 - count of durations < 200 ms - * bits 19:10 - count of durations between 200 to 500 ms - * bits 29:20 - count of durations > 500 ms - */ - A_UINT32 peer_ps_histogram_0 : 10, /* [9:0] */ - peer_ps_histogram_1 : 10, /* [19:10] */ - peer_ps_histogram_2 : 10, /* [29:20] */ - rsvd2 : 2; /* [31:30] */ - }; - }; } htt_stats_peer_details_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_peer_details_tlv htt_peer_details_tlv; @@ -2697,44 +2072,23 @@ typedef htt_stats_peer_details_tlv htt_peer_details_tlv; #define HTT_STATS_PEER_DETAILS_SRC_INFO_GET(word) ((word >> 0) & 0xfff) -#define HTT_STATS_PEER_DETAILS_PEER_PS_ENTRY_GET(word) \ - HTT_PEER_DETAILS_GET(word, PEER_PS_ENTRY) -#define HTT_STATS_PEER_DETAILS_PEER_PS_EXIT_GET(word) \ - HTT_PEER_DETAILS_GET(word, PEER_PS_EXIT) -#define HTT_STATS_PEER_DETAILS_PEER_PSPOLL_TRIGGER_GET(word) \ - HTT_PEER_DETAILS_GET(word, PEER_PSPOLL_TRIGGER) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PEER_DETAILS_PEER_PSPOLL_TRIGGER_RECEIVED_GET(word) \ - HTT_STATS_PEER_DETAILS_PEER_PSPOLL_TRIGGER_GET(word) -#define HTT_STATS_PEER_DETAILS_PEER_UAPSD_TRIGGER_GET(word) \ - HTT_PEER_DETAILS_GET(word, PEER_UAPSD_TRIGGER) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PEER_DETAILS_PEER_UAPSD_TRIGGER_RECEIVED_GET(word) \ - HTT_STATS_PEER_DETAILS_PEER_UAPSD_TRIGGER_GET(word) -#define HTT_STATS_PEER_DETAILS_PEER_PS_HISTOGRAM_0_GET(word) \ - HTT_PEER_DETAILS_GET(word, PEER_PS_HISTOGRAM_0) -#define HTT_STATS_PEER_DETAILS_PEER_PS_HISTOGRAM_1_GET(word) \ - HTT_PEER_DETAILS_GET(word, PEER_PS_HISTOGRAM_1) -#define HTT_STATS_PEER_DETAILS_PEER_PS_HISTOGRAM_2_GET(word) \ - HTT_PEER_DETAILS_GET(word, PEER_PS_HISTOGRAM_2) - typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 sw_peer_id; A_UINT32 ast_index; htt_mac_addr mac_addr; A_UINT32 - pdev_id : 2, /* bits 1:0 */ - vdev_id : 8, /* bits 9:2 */ - next_hop : 1, /* bit 10 */ - mcast : 1, /* bit 11 */ - monitor_direct : 1, /* bit 12 */ - mesh_sta : 1, /* bit 13 */ - mec : 1, /* bit 14 */ - intra_bss : 1, /* bit 15 */ - chip_id : 2, /* bit 17:16 */ - ml_peer_id : 13, /* bit 30:18 */ - on_chip : 1; /* bit 31 */ + pdev_id : 2, + vdev_id : 8, + next_hop : 1, + mcast : 1, + monitor_direct : 1, + mesh_sta : 1, + mec : 1, + intra_bss : 1, + chip_id : 2, + ml_peer_id : 13, + on_chip : 1; A_UINT32 tx_monitor_override_sta : 1, rx_monitor_override_sta : 1, @@ -2743,34 +2097,6 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_ast_entry_tlv htt_ast_entry_tlv; -#define HTT_STATS_AST_ENTRY_PDEV_ID_GET(word32) \ - ((word32 >> 0) & 0x3) -#define HTT_STATS_AST_ENTRY_VDEV_ID_GET(word32) \ - ((word32 >> 2) & 0xff) -#define HTT_STATS_AST_ENTRY_NEXT_HOP_GET(word32) \ - ((word32 >> 10) & 0x1) -#define HTT_STATS_AST_ENTRY_MCAST_GET(word32) \ - ((word32 >> 11) & 0x1) -#define HTT_STATS_AST_ENTRY_MONITOR_DIRECT_GET(word32) \ - ((word32 >> 12) & 0x1) -#define HTT_STATS_AST_ENTRY_MESH_STA_GET(word32) \ - ((word32 >> 13) & 0x1) -#define HTT_STATS_AST_ENTRY_MEC_GET(word32) \ - ((word32 >> 14) & 0x1) -#define HTT_STATS_AST_ENTRY_INTRA_BSS_GET(word32) \ - ((word32 >> 15) & 0x1) -#define HTT_STATS_AST_ENTRY_CHIP_ID_GET(word32) \ - ((word32 >> 16) & 0x3) -#define HTT_STATS_AST_ENTRY_ML_PEER_ID_GET(word32) \ - ((word32 >> 18) & 0x1fff) -#define HTT_STATS_AST_ENTRY_ON_CHIP_GET(word32) \ - ((word32 >> 31) & 0x1) - -#define HTT_STATS_AST_ENTRY_TX_MONITOR_OVERRIDE_STA_GET(word32) \ - ((word32 >> 0) & 0x1) -#define HTT_STATS_AST_ENTRY_RX_MONITOR_OVERRIDE_STA_GET(word32) \ - ((word32 >> 1) & 0x1) - typedef enum { HTT_STATS_DIRECTION_TX, HTT_STATS_DIRECTION_RX, @@ -2791,7 +2117,7 @@ typedef enum { HTT_STATS_PREAM_VHT, HTT_STATS_PREAM_HE, HTT_STATS_PREAM_EHT, - HTT_STATS_PREAM_UHR, + HTT_STATS_PREAM_RSVD1, HTT_STATS_PREAM_COUNT, } HTT_STATS_PREAM_TYPE; @@ -2882,9 +2208,6 @@ typedef struct _htt_tx_peer_rate_stats_tlv { A_UINT32 tx_bw_320mhz; /* MCS 14,15 */ A_UINT32 tx_mcs_ext_2[HTT_TX_PEER_STATS_NUM_EXTRA2_MCS_COUNTERS]; - A_UINT32 peer_tx_ppdu_cnt; - A_UINT32 peer_tx_mpdu_try_cnt; - A_UINT32 peer_tx_mpdu_success_cnt; } htt_stats_peer_tx_rate_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_peer_tx_rate_stats_tlv htt_tx_peer_rate_stats_tlv; @@ -2969,8 +2292,6 @@ typedef struct _htt_rx_peer_rate_stats_tlv { A_UINT32 rx_bw_320mhz; /* MCS 14,15 */ A_UINT32 rx_mcs_ext_2[HTT_RX_PEER_STATS_NUM_EXTRA2_MCS_COUNTERS]; - A_UINT32 tot_rx_ppdu_bytes; - A_UINT32 rx_mpdu_try_cnt; } htt_stats_peer_rx_rate_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_peer_rx_rate_stats_tlv htt_rx_peer_rate_stats_tlv; @@ -2990,10 +2311,8 @@ typedef enum { HTT_RX_TID_STATS_TLV = 5, HTT_MSDU_FLOW_STATS_TLV = 6, HTT_PEER_SCHED_STATS_TLV = 7, - HTT_PEER_OFDMA_STATS_TLV = 8, - HTT_PEER_AX_OFDMA_STATS_TLV = HTT_PEER_OFDMA_STATS_TLV, /* DEPRECATED */ - HTT_PEER_BE_OFDMA_STATS_TLV = 9, /* DEPRECATED */ - HTT_PEER_RX_REO_STATS_TLV = 10, + HTT_PEER_AX_OFDMA_STATS_TLV = 8, + HTT_PEER_BE_OFDMA_STATS_TLV = 9, HTT_PEER_STATS_MAX_TLV = 31, } htt_peer_stats_tlv_enum; @@ -3016,46 +2335,18 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_peer_sched_stats_tlv htt_peer_sched_stats_tlv; -/* Retaining the old structure defs for compatibility */ typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 peer_id; - union{ - A_UINT32 ax_basic_trig_count; /* retaining the older alias */ - A_UINT32 basic_trig_count; - }; - union{ - A_UINT32 ax_basic_trig_err; /* retaining the older alias */ - A_UINT32 basic_trig_err; - }; - union{ - A_UINT32 ax_bsr_trig_count; /* retaining the older alias */ - A_UINT32 bsr_trig_count; - }; - union{ - A_UINT32 ax_bsr_trig_err; /* retaining the older alias */ - A_UINT32 bsr_trig_err; - }; - union{ - A_UINT32 ax_mu_bar_trig_count; /* retaining the older alias */ - A_UINT32 mu_bar_trig_count; - }; - union{ - A_UINT32 ax_mu_bar_trig_err; /* retaining the older alias */ - A_UINT32 mu_bar_trig_err; - }; - union{ - A_UINT32 ax_basic_trig_with_per; /* retaining the older alias */ - A_UINT32 basic_trig_with_per; - }; - union{ - A_UINT32 ax_bsr_trig_with_per; /* retaining the older alias */ - A_UINT32 bsr_trig_with_per; - }; - union{ - A_UINT32 ax_mu_bar_trig_with_per; /* retaining the older alias */ - A_UINT32 mu_bar_trig_with_per; - }; + A_UINT32 ax_basic_trig_count; + A_UINT32 ax_basic_trig_err; + A_UINT32 ax_bsr_trig_count; + A_UINT32 ax_bsr_trig_err; + A_UINT32 ax_mu_bar_trig_count; + A_UINT32 ax_mu_bar_trig_err; + A_UINT32 ax_basic_trig_with_per; + A_UINT32 ax_bsr_trig_with_per; + A_UINT32 ax_mu_bar_trig_with_per; /* is_airtime_large_for_dl_ofdma, is_airtime_large_for_ul_ofdma * These fields contain 2 counters each. The first element in each * array counts how many times the airtime is short enough to use @@ -3067,22 +2358,13 @@ typedef struct { /* Last updated value of DL and UL queue depths for each peer per AC */ A_UINT32 last_updated_dl_qdepth[HTT_NUM_AC_WMM]; A_UINT32 last_updated_ul_qdepth[HTT_NUM_AC_WMM]; - - /* Per peer Manual UL OFDMA trigger and trigger error counts */ - union{ - A_UINT32 ax_manual_ulofdma_trig_count; /* retaining the older alias */ - A_UINT32 manual_ulofdma_trig_count; - }; - union{ - A_UINT32 ax_manual_ulofdma_trig_err_count; /* retaining the older alias */ - A_UINT32 manual_ulofdma_trig_err_count; - }; -} htt_stats_peer_ofdma_stats_tlv; + /* Per peer Manual 11ax UL OFDMA trigger and trigger error counts */ + A_UINT32 ax_manual_ulofdma_trig_count; + A_UINT32 ax_manual_ulofdma_trig_err_count; +} htt_stats_peer_ax_ofdma_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_peer_ofdma_stats_tlv htt_peer_ax_ofdma_stats_tlv; -typedef htt_stats_peer_ofdma_stats_tlv htt_stats_peer_ax_ofdma_stats_tlv; +typedef htt_stats_peer_ax_ofdma_stats_tlv htt_peer_ax_ofdma_stats_tlv; -/* DEPRECATED */ typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 peer_id; @@ -3164,8 +2446,7 @@ typedef htt_stats_peer_be_ofdma_stats_tlv htt_peer_be_ofdma_stats_tlv; * - HTT_STATS_PEER_MSDU_FLOWQ_TAG (multiple) * - HTT_STATS_TX_TID_DETAILS_V1_TAG (multiple) * - HTT_STATS_PEER_SCHED_STATS_TAG - * - HTT_STATS_PEER_OFDMA_STATS_TAG / HTT_STATS_PEER_AX_OFDMA_STATS_TAG - * - HTT_STATS_PEER_BE_OFDMA_STATS_TAG + * - HTT_STATS_PEER_AX_OFDMA_STATS_TAG */ /* NOTE: * This structure is for documentation, and cannot be safely used directly. @@ -3184,12 +2465,8 @@ typedef struct _htt_peer_stats { htt_stats_peer_msdu_flowq_tlv msdu_flowq[1]; htt_stats_tx_tid_details_v1_tlv tx_tid_stats_v1[1]; htt_stats_peer_sched_stats_tlv peer_sched_stats; - union { - htt_stats_peer_ofdma_stats_tlv peer_ofdma_stats; - /* ax_ofdma_stats: DEPRECATED, but retained as alias */ - htt_stats_peer_ax_ofdma_stats_tlv ax_ofdma_stats; - }; - htt_stats_peer_be_ofdma_stats_tlv be_ofdma_stats; /* DEPRECATED */ + htt_stats_peer_ax_ofdma_stats_tlv ax_ofdma_stats; + htt_stats_peer_be_ofdma_stats_tlv be_ofdma_stats; } htt_peer_stats_t; #endif /* ATH_TARGET */ @@ -3501,58 +2778,6 @@ typedef struct { typedef htt_stats_tx_hwq_txop_used_cnt_hist_tlv htt_tx_hwq_txop_used_cnt_hist_tlv_v; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - A_UINT32 pdev_id__word; - struct { - A_UINT32 - pdev_id: 8, - reserved: 24; - }; - }; - A_UINT32 active_seq_in_hwq_hist[HTT_PDEV_STATS_MAX_ACTIVE_SEQ_IN_HWQ_HIST]; -} htt_stats_tx_pdev_pending_seq_cnt_in_hwq_hist_tlv; - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_PDEV_ID_M 0x000000ff -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_PDEV_ID_S 0 - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_PDEV_ID_GET(_var) \ - (((_var) & HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_PDEV_ID_M) >> \ - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_PDEV_ID_S) - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_PDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_PDEV_ID_S)); \ - } while (0) - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - A_UINT32 pdev_id__word; - struct { - A_UINT32 - pdev_id: 8, - reserved: 24; - }; - }; - A_UINT32 active_seq_in_txq_hist[HTT_PDEV_STATS_MAX_SEQ_CTRL_HIST]; -} htt_stats_tx_pdev_pending_seq_cnt_in_txq_hist_tlv; - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_PDEV_ID_M 0x000000ff -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_PDEV_ID_S 0 - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_PDEV_ID_GET(_var) \ - (((_var) & HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_PDEV_ID_M) >> \ - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_PDEV_ID_S) - -#define HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_PDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_PDEV_ID_S)); \ - } while (0) - /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_HWQ * TLV_TAGS: * - HTT_STATS_STRING_TAG @@ -3563,8 +2788,6 @@ typedef struct { * - HTT_STATS_TX_HWQ_FES_STATUS_TAG * - HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG * - HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG - * - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_HWQ_HIST_TAG - * - HTT_STATS_TX_PDEV_PENDING_SEQ_CNT_IN_TXQ_HIST_TAG */ /* NOTE: * This structure is for documentation, and cannot be safely used directly. @@ -3585,10 +2808,6 @@ typedef struct _htt_tx_hwq_stats { htt_stats_tx_hwq_fes_status_tlv fes_stats_tlv; htt_stats_tx_hwq_tried_mpdu_cnt_hist_tlv tried_mpdu_tlv; htt_stats_tx_hwq_txop_used_cnt_hist_tlv txop_used_tlv; - htt_stats_tx_pdev_pending_seq_cnt_in_hwq_hist_tlv - active_pending_seq_cnt_in_hwq_hist_tlv; - htt_stats_tx_pdev_pending_seq_cnt_in_txq_hist_tlv - active_pending_seq_cnt_in_txq_hist_tlv; } htt_tx_hwq_stats_t; #endif /* ATH_TARGET */ @@ -3661,9 +2880,7 @@ typedef enum { #define HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS 4 #define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8 #define HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS 8 -#define HTT_TX_PDEV_STATS_NUM_BN_MUMIMO_USER_STATS 8 #define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74 -#define HTT_TX_PDEV_STATS_NUM_BN_OFDMA_USER_STATS 16 #define HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS 8 #define HTT_STATS_MAX_MUMIMO_GRP_SZ 8 /* @@ -3680,64 +2897,14 @@ typedef enum { #define HTT_MAX_NUM_SBT_INTR 4 -typedef enum { - HTT_RU_ALLOC_MODE_PF, - HTT_RU_ALLOC_MODE_QOS, - HTT_RU_ALLOC_MODE_STATIC, - HTT_RU_ALLOC_MODE_EQUAL, - HTT_RU_ALLOC_MODE_SIMPLIFIED, - - /* Reserving additional modes for future use */ - HTT_RU_ALLOC_MODE_RESERVED_1, - HTT_RU_ALLOC_MODE_RESERVED_2, - - HTT_RU_ALLOC_NUM_MODES -} HTT_RU_ALLOC_MODE; - -typedef enum { - HTT_TX_PDEV_STATS_BN_DRU_SIZE_26, - HTT_TX_PDEV_STATS_BN_DRU_SIZE_52, - HTT_TX_PDEV_STATS_BN_DRU_SIZE_106, - HTT_TX_PDEV_STATS_BN_DRU_SIZE_242, - HTT_TX_PDEV_STATS_BN_DRU_SIZE_484, - - HTT_TX_PDEV_STATS_NUM_BN_DRU_SIZE_COUNTERS -} HTT_TX_PDEV_STATS_BN_DRU_SIZE; - -typedef enum { - HTT_BN_UL_OFDMA_RRU_ONLY_ALLOC_MODE, - HTT_BN_UL_OFDMA_DRU_ONLY_ALLOC_MODE, - HTT_BN_UL_OFDMA_HYBRID_RU_ALLOC_MODE, - - /* Reserving additional modes for future use */ - HTT_BN_UL_OFDMA_RU_ALLOC_MODE_RESERVED_1, - HTT_BN_UL_OFDMA_RU_ALLOC_MODE_RESERVED_2, - - HTT_BN_UL_OFDMA_NUM_RU_ALLOC_MODES -} HTT_BN_UL_OFDMA_RU_ALLOC_MODE; - -typedef enum { - HTT_BN_UL_OFDMA_DRU_SBW_20MHZ, - HTT_BN_UL_OFDMA_DRU_SBW_40MHZ, - HTT_BN_UL_OFDMA_DRU_SBW_80MHZ, - - HTT_BN_UL_OFDMA_NUM_DRU_SBW_COUNT -} HTT_BN_UL_OFDMA_DRU_SBW_SIZE; - typedef struct { htt_tlv_hdr_t tlv_hdr; - /** + /* * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** BAR sent out for SU transmission */ A_UINT32 su_bar; /** SW generated RTS frame sent */ @@ -3795,17 +2962,10 @@ typedef struct { * (Smart basic triggers are only used with intervals <= 40 ms.) */ A_UINT32 smart_basic_trig_sch_histogram[HTT_MAX_NUM_SBT_INTR]; - A_UINT32 ru_alloc_mode_cnt[HTT_RU_ALLOC_NUM_MODES]; - A_UINT32 mu_bar_pipeline_seq_cnt; - A_UINT32 mu_bar_pipeline_resume_cnt; - A_UINT32 mu_bar_pipeline_resume_fail_cnt; } htt_stats_tx_selfgen_cmn_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_selfgen_cmn_stats_tlv htt_tx_selfgen_cmn_stats_tlv; -#define HTT_STATS_TX_SELFGEN_CMN_STATS_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - typedef struct { htt_tlv_hdr_t tlv_hdr; /** 11AC VHT SU NDPA frame sent over the air */ @@ -3913,22 +3073,6 @@ typedef struct { A_UINT32 ax_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM]; /** 11AX HE MU-BAR Trigger frames per AC completed with error(s) */ A_UINT32 ax_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM]; - /** 11AX HE MU Combined UL OFDMA Basic Trigger frame sent over the air */ - A_UINT32 combined_ax_ulofdma_trigger_tried[HTT_NUM_AC_WMM]; - /** 11AX HE MU Combined UL OFDMA Basic Trigger completed with error(s) */ - A_UINT32 combined_ax_ulofdma_trigger_err[HTT_NUM_AC_WMM]; - /** 11AX HE MU Standalone UL OFDMA Basic Trigger frame sent over the air */ - A_UINT32 standalone_ax_ulofdma_trigger_tried[HTT_NUM_AC_WMM]; - /** 11AX HE MU Standalone UL OFDMA Basic Trigger completed with error(s) */ - A_UINT32 standalone_ax_ulofdma_trigger_err[HTT_NUM_AC_WMM]; - /** 11AX HE MU Combined UL MU-MIMO Basic Trigger frame sent over the air */ - A_UINT32 combined_ax_ulmumimo_trigger_tried[HTT_NUM_AC_WMM]; - /** 11AX HE MU Combined UL MU-MIMO Basic Trigger completed with error(s) */ - A_UINT32 combined_ax_ulmumimo_trigger_err[HTT_NUM_AC_WMM]; - /** 11AX HE MU Standalone UL MU-MIMO Basic Trigger frame sent over the air*/ - A_UINT32 standalone_ax_ulmumimo_trigger_tried[HTT_NUM_AC_WMM]; - /** 11AX HE MU Standalone UL MU-MIMO Basic Trigger completed with error(s)*/ - A_UINT32 standalone_ax_ulmumimo_trigger_err[HTT_NUM_AC_WMM]; } htt_stats_tx_selfgen_ax_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_selfgen_ax_stats_tlv htt_tx_selfgen_ax_stats_tlv; @@ -3994,97 +3138,10 @@ typedef struct { A_UINT32 be_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM]; /** 11BE EHT MU-BAR Trigger frames per AC completed with error(s) */ A_UINT32 be_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM]; - /** 11BE EHT MU Combined UL OFDMA Basic Trigger frame sent over the air */ - A_UINT32 combined_be_ulofdma_trigger_tried[HTT_NUM_AC_WMM]; - /** 11BE EHT MU Combined UL OFDMA Basic Trigger completed with error(s) */ - A_UINT32 combined_be_ulofdma_trigger_err[HTT_NUM_AC_WMM]; - /** 11BE EHT MU Standalone UL OFDMA Basic Trigger frame sent over the air */ - A_UINT32 standalone_be_ulofdma_trigger_tried[HTT_NUM_AC_WMM]; - /** 11BE EHT MU Standalone UL OFDMA Basic Trigger completed with error(s) */ - A_UINT32 standalone_be_ulofdma_trigger_err[HTT_NUM_AC_WMM]; - /** 11BE EHT MU Combined UL MU-MIMO Basic Trigger frame sent over the air */ - A_UINT32 combined_be_ulmumimo_trigger_tried[HTT_NUM_AC_WMM]; - /** 11BE EHT MU Combined UL MU-MIMO Basic Trigger completed with error(s) */ - A_UINT32 combined_be_ulmumimo_trigger_err[HTT_NUM_AC_WMM]; - /** 11BE EHT MU Standalone UL MU-MIMO Basic Trigger frame sent over the air */ - A_UINT32 standalone_be_ulmumimo_trigger_tried[HTT_NUM_AC_WMM]; - /** 11BE EHT MU Standalone UL MU-MIMO Basic Trigger completed with error(s) */ - A_UINT32 standalone_be_ulmumimo_trigger_err[HTT_NUM_AC_WMM]; - /** - * Wi-Fi version identifier to differentiate stats while printing - * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value). - */ - A_UINT32 wifi_version; } htt_stats_tx_selfgen_be_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_selfgen_be_stats_tlv htt_tx_selfgen_be_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** 11bn UHR MU Basic Trigger frame sent over the air */ - A_UINT32 bn_basic_trigger; - /** 11bn UHR MU BSRP Trigger frame sent over the air */ - A_UINT32 bn_bsr_trigger; - /** 11bn UHR MU BAR Trigger frame sent over the air */ - A_UINT32 bn_mu_bar_trigger; - /** 11bn UHR MU RTS Trigger frame sent over the air */ - A_UINT32 bn_mu_rts_trigger; - - /** 11BN UHR MU Combined Freq. BSRP Trigger frame sent over the air */ - A_UINT32 combined_bn_bsr_trigger_tried[HTT_NUM_AC_WMM]; - /** 11BN UHR MU Combined Freq. BSRP Trigger completed with error(s) */ - A_UINT32 combined_bn_bsr_trigger_err[HTT_NUM_AC_WMM]; - /** 11BN UHR MU Standalone Freq. BSRP Trigger frame sent over the air */ - A_UINT32 standalone_bn_bsr_trigger_tried[HTT_NUM_AC_WMM]; - /** 11BN UHR MU Standalone Freq. BSRP Trigger completed with error(s) */ - A_UINT32 standalone_bn_bsr_trigger_err[HTT_NUM_AC_WMM]; - /** 11BN UHR Manual Single-User UL OFDMA Trigger frame sent over the air */ - A_UINT32 manual_bn_su_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; - /** 11BN UHR Manual Single-User UL OFDMA Trigger completed with error(s) */ - A_UINT32 manual_bn_su_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; - /** 11BN UHR Manual Multi-User UL OFDMA Trigger frame sent over the air */ - A_UINT32 manual_bn_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; - /** 11BN UHR Manual Multi-User UL OFDMA Trigger completed with error(s) */ - A_UINT32 manual_bn_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; - - /** 11BN UHR UL OFDMA RU allocation mode */ - A_UINT32 bn_basic_trig_ru_alloc_mode[HTT_BN_UL_OFDMA_NUM_RU_ALLOC_MODES]; - - /** 11bn UHR MU UL-MUMIMO Trigger frame sent over the air */ - A_UINT32 bn_ulmumimo_trigger; - /** - * 11bn UHR UL-MUMIMO Trigger frame for users 0 - 7 - * successfully sent over the air - */ - A_UINT32 bn_ul_mumimo_trigger[HTT_TX_PDEV_STATS_NUM_BN_MUMIMO_USER_STATS]; - /** 11BN UHR MU Combined UL MU-MIMO Basic Trigger frame sent over the air */ - A_UINT32 combined_bn_ulmumimo_trigger_tried[HTT_NUM_AC_WMM]; - /** 11BN UHR MU Combined UL MU-MIMO Basic Trigger completed with error(s) */ - A_UINT32 combined_bn_ulmumimo_trigger_err[HTT_NUM_AC_WMM]; - /** - * 11BN UHR MU Standalone UL MU-MIMO Basic Trigger frame - * sent over the air - */ - A_UINT32 standalone_bn_ulmumimo_trigger_tried[HTT_NUM_AC_WMM]; - /** - * 11BN UHR MU Standalone UL MU-MIMO Basic Trigger - * completed with error(s) - */ - A_UINT32 standalone_bn_ulmumimo_trigger_err[HTT_NUM_AC_WMM]; - - /** 11bn UHR BSRP trigger to DPS client sent over the air */ - A_UINT32 sta_dps_bn_bsr_trigger[HTT_NUM_AC_WMM]; - /** 11bn UHR MU RTS trigger to DPS client sent over the air */ - A_UINT32 sta_dps_bn_mu_rts_trigger[HTT_NUM_AC_WMM]; - /** 11bn UHR BSRP trigger to DPS client completed with error(s) */ - A_UINT32 sta_dps_bn_bsr_trigger_err[HTT_NUM_AC_WMM]; - /** 11bn UHR MU RTS trigger to DPS client completed with errors(s) */ - A_UINT32 sta_dps_bn_mu_rts_trigger_err[HTT_NUM_AC_WMM]; - - /** 11BN UHR UL OFDMA RU allocation mode - trigger error count */ - A_UINT32 bn_basic_trig_ru_alloc_mode_err[HTT_BN_UL_OFDMA_NUM_RU_ALLOC_MODES]; -} htt_stats_tx_selfgen_bn_tlv; - typedef struct { /* DEPRECATED */ htt_tlv_hdr_t tlv_hdr; /** 11AX HE OFDMA NDPA frame queued to the HW */ @@ -4498,165 +3555,6 @@ typedef struct { A_UINT32 be_ofdma_total_cv; } htt_stats_txbf_ofdma_be_parbw_tlv; -typedef struct { - /** 11BN UHR OFDMA NDPA frame queued to the HW */ - A_UINT32 bn_ofdma_ndpa_queued; - /** 11BN UHR OFDMA NDPA frame sent over the air */ - A_UINT32 bn_ofdma_ndpa_tried; - /** 11BN UHR OFDMA NDPA frame flushed by HW */ - A_UINT32 bn_ofdma_ndpa_flushed; - /** 11BN UHR OFDMA NDPA frame completed with error(s) */ - A_UINT32 bn_ofdma_ndpa_err; -} htt_txbf_ofdma_bn_ndpa_stats_elem_t; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * This field is populated with the num of elems in the bn_ndpa[] - * variable length array. - */ - A_UINT32 num_elems_bn_ndpa_arr; - /** - * This field will be filled by target with value of - * sizeof(htt_txbf_ofdma_bn_ndpa_stats_elem_t). - * This is for allowing host to infer how much data target has provided, - * even if it using different version of the struct than what target - * had used. - */ - A_UINT32 arr_elem_size_bn_ndpa; - HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_bn_ndpa_stats_elem_t, bn_ndpa); -} htt_stats_txbf_ofdma_bn_ndpa_tlv; - -typedef struct { - /** 11BN UHR OFDMA NDP frame queued to the HW */ - A_UINT32 bn_ofdma_ndp_queued; - /** 11BN UHR OFDMA NDPA frame sent over the air */ - A_UINT32 bn_ofdma_ndp_tried; - /** 11BN UHR OFDMA NDPA frame flushed by HW */ - A_UINT32 bn_ofdma_ndp_flushed; - /** 11BN UHR OFDMA NDPA frame completed with error(s) */ - A_UINT32 bn_ofdma_ndp_err; -} htt_txbf_ofdma_bn_ndp_stats_elem_t; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * This field is populated with the num of elems in the bn_ndp[] - * variable length array. - */ - A_UINT32 num_elems_bn_ndp_arr; - /** - * This field will be filled by target with value of - * sizeof(htt_txbf_ofdma_bn_ndp_stats_elem_t). - * This is for allowing host to infer how much data target has provided, - * even if it using different version of the struct than what target - * had used. - */ - A_UINT32 arr_elem_size_bn_ndp; - HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_bn_ndp_stats_elem_t, bn_ndp); -} htt_stats_txbf_ofdma_bn_ndp_tlv; - -typedef struct { - /** 11BN UHR OFDMA MU BRPOLL frame queued to the HW */ - A_UINT32 bn_ofdma_brpoll_queued; - /** 11BN UHR OFDMA MU BRPOLL frame sent over the air */ - A_UINT32 bn_ofdma_brpoll_tried; - /** 11BN UHR OFDMA MU BRPOLL frame flushed by HW */ - A_UINT32 bn_ofdma_brpoll_flushed; - /** 11BN UHR OFDMA MU BRPOLL frame completed with error(s) */ - A_UINT32 bn_ofdma_brp_err; - /** - * Number of CBF(s) received when 11BN UHR OFDMA MU BRPOLL frame - * completed with error(s) - */ - A_UINT32 bn_ofdma_brp_err_num_cbf_rcvd; -} htt_txbf_ofdma_bn_brp_stats_elem_t; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * This field is populated with the num of elems in the bn_brp[] - * variable length array. - */ - A_UINT32 num_elems_bn_brp_arr; - /** - * This field will be filled by target with value of - * sizeof(htt_txbf_ofdma_bn_brp_stats_elem_t). - * This is for allowing host to infer how much data target has provided, - * even if it using different version of the struct than what target - * had used - */ - A_UINT32 arr_elem_size_bn_brp; - HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_bn_brp_stats_elem_t, bn_brp); -} htt_stats_txbf_ofdma_bn_brp_tlv; - -typedef struct { - /** - * 11BN UHR OFDMA PPDUs that were sent over the air with steering - * (TXBF + OFDMA) - */ - A_UINT32 bn_ofdma_num_ppdu_steer; - /** 11BN UHR OFDMA PPDUs that were sent over the air in open loop */ - A_UINT32 bn_ofdma_num_ppdu_ol; - /** - * 11BN UHR OFDMA number of users for which CBF prefetch was initiated - * to PHY HW during TX - */ - A_UINT32 bn_ofdma_num_usrs_prefetch; - /** - * 11BN UHR OFDMA number of users for which sounding was initiated - * during TX - */ - A_UINT32 bn_ofdma_num_usrs_sound; - /** - * 11BN UHR OFDMA number of users for which sounding was forced during TX - */ - A_UINT32 bn_ofdma_num_usrs_force_sound; -} htt_txbf_ofdma_bn_steer_stats_elem_t; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * This field is populated with the num of elems in the bn_steer[] - * variable length array. - */ - A_UINT32 num_elems_bn_steer_arr; - /** - * This field will be filled by target with value of - * sizeof(htt_txbf_ofdma_bn_steer_stats_elem_t). - * This is for allowing host to infer how much data target has provided, - * even if it using different version of the struct than what target - * had used. - */ - A_UINT32 arr_elem_size_bn_steer; - HTT_STATS_VAR_LEN_ARRAY1(htt_txbf_ofdma_bn_steer_stats_elem_t, bn_steer); -} htt_stats_txbf_ofdma_bn_steer_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* 11BN UHR OFDMA MPDUs tried in rbo steering */ - A_UINT32 bn_ofdma_rbo_steer_mpdus_tried; - /* 11BN UHR OFDMA MPDUs failed in rbo steering */ - A_UINT32 bn_ofdma_rbo_steer_mpdus_failed; - /* 11BN UHR OFDMA MPDUs tried in sifs steering */ - A_UINT32 bn_ofdma_sifs_steer_mpdus_tried; - /* 11BN UHR OFDMA MPDUs failed in sifs steering */ - A_UINT32 bn_ofdma_sifs_steer_mpdus_failed; -} htt_stats_txbf_ofdma_bn_steer_mpdu_tlv; - -/* HTT_STATS_TXBF_OFDMA_BN_PARBW_TAG stats TLV: - * Sent by target in response to HTT_DBG_EXT_STATS_TXBF_OFDMA stats ID request. - */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* Num of UHR TxBF Partial Bandwidth soundings */ - A_UINT32 bn_ofdma_parbw_user_snd; - /* Num of UHR Partial Bandwidth Sounded CVs received */ - A_UINT32 bn_ofdma_parbw_cv; - /* Num of 11BN EHT Total CVs received */ - A_UINT32 bn_ofdma_total_cv; -} htt_stats_txbf_ofdma_bn_parbw_tlv; - /* STATS_TYPE : HTT_DBG_EXT_STATS_TXBF_OFDMA * TLV_TAGS: * - HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG @@ -4669,11 +3567,6 @@ typedef struct { * - HTT_STATS_TXBF_OFDMA_BE_BRP_STATS_TAG * - HTT_STATS_TXBF_OFDMA_BE_STEER_STATS_TAG * - HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG - * - HTT_STATS_TXBF_OFDMA_BN_NDPA_TAG - * - HTT_STATS_TXBF_OFDMA_BN_NDP_TAG - * - HTT_STATS_TXBF_OFDMA_BN_BRP_TAG - * - HTT_STATS_TXBF_OFDMA_BN_STEER_TAG - * - HTT_STATS_TXBF_OFDMA_BN_STEER_MPDU_TAG */ typedef struct { @@ -4826,45 +3719,10 @@ typedef struct { A_UINT32 be_mu_rts_trigger_blocked; /** 11BE EHT MU BSR Trigger frame blocked due to partner link TX/RX(eMLSR) */ A_UINT32 be_bsr_trigger_blocked; - /** - * Wi-Fi version identifier to differentiate stats while printing - * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value). - */ - A_UINT32 wifi_version; } htt_stats_tx_selfgen_be_err_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_selfgen_be_err_stats_tlv htt_tx_selfgen_be_err_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** 11BN UHR MU Basic Trigger frame completed with error(s) */ - A_UINT32 bn_basic_trigger_err; - /** 11BN UHR MU BSRP Trigger frame completed with error(s) */ - A_UINT32 bn_bsr_trigger_err; - /** 11BN UHR MU BAR Trigger frame completed with error(s) */ - A_UINT32 bn_mu_bar_trigger_err; - /** 11BN UHR MU RTS Trigger frame completed with error(s) */ - A_UINT32 bn_mu_rts_trigger_err; - - /** 11BN UHR MU OFDMA Basic Trigger frame completed with partial user response */ - A_UINT32 bn_basic_trigger_partial_resp; - /** 11BN UHR MU BSRP Trigger frame completed with partial user response */ - A_UINT32 bn_bsr_trigger_partial_resp; - /** 11BN UHR MU BAR Trigger frame completed with partial user response */ - A_UINT32 bn_mu_bar_trigger_partial_resp; - /** 11BN UHR MU RTS Trigger frame blocked due to partner link TX/RX(eMLSR) */ - A_UINT32 bn_mu_rts_trigger_blocked; - /** 11BN UHR MU BSR Trigger frame blocked due to partner link TX/RX(eMLSR) */ - A_UINT32 bn_bsr_trigger_blocked; - - /** 11BN UHR MU ULMUMIMO Trigger frame completed with error(s) */ - A_UINT32 bn_ulmumimo_trigger_err; - /** - * 11BN UHR UL-MUMIMO Trigger frame for users 0 - 7 completed with error(s) - */ - A_UINT32 bn_ul_mumimo_trigger_err[HTT_TX_PDEV_STATS_NUM_BN_MUMIMO_USER_STATS]; -} htt_stats_tx_selfgen_bn_err_tlv; - /* * Scheduler completion status reason code. * (0) HTT_TXERR_NONE - No error (Success). @@ -4991,29 +3849,11 @@ typedef struct { A_UINT32 be_ulmumimo_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; /** 11BE EHT UL MUMIMO Basic Trigger scheduler error code */ A_UINT32 be_ulmumimo_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; - /** - * Wi-Fi version identifier to differentiate stats while printing - * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value). - */ - A_UINT32 wifi_version; } htt_stats_tx_selfgen_be_sched_status_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_selfgen_be_sched_status_stats_tlv htt_tx_selfgen_be_sched_status_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** 11BN UHR MU BAR scheduler completion status reason code */ - A_UINT32 bn_mu_bar_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /** 11BN UHR MU BAR scheduler error code */ - A_UINT32 bn_mu_bar_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; - - /** 11BN UHR UL OFDMA Basic Trigger scheduler completion status reason code */ - A_UINT32 bn_basic_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; - /** 11BN UHR UL OFDMA Basic Trigger scheduler error code */ - A_UINT32 bn_basic_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; -} htt_stats_tx_selfgen_bn_sched_status_tlv; - /* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SELFGEN_INFO * TLV_TAGS: * - HTT_STATS_TX_SELFGEN_CMN_STATS_TAG @@ -5026,9 +3866,6 @@ typedef struct { * - HTT_STATS_TX_SELFGEN_BE_STATS_TAG * - HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG * - HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG - * - HTT_STATS_TX_SELFGEN_BN_TAG - * - HTT_STATS_TX_SELFGEN_BN_ERR_TAG - * - HTT_STATS_TX_SELFGEN_BN_SCHED_STATUS_TAG */ /* NOTE: * This structure is for documentation, and cannot be safely used directly. @@ -5046,9 +3883,6 @@ typedef struct { htt_stats_tx_selfgen_be_stats_tlv be_tlv; htt_stats_tx_selfgen_be_err_stats_tlv be_err_tlv; htt_stats_tx_selfgen_be_sched_status_stats_tlv be_sched_status_tlv; - htt_stats_tx_selfgen_bn_tlv bn_tlv; - htt_stats_tx_selfgen_bn_err_tlv bn_err_tlv; - htt_stats_tx_selfgen_bn_sched_status_tlv bn_sched_status_tlv; } htt_tx_pdev_selfgen_stats_t; #endif /* ATH_TARGET */ @@ -5104,11 +3938,6 @@ typedef struct { A_UINT32 be_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; /** Number of 11AC DL MU MIMO schedules posted per group size (4-7) */ A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz_ext[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; - /** - * Wi-Fi version identifier to differentiate stats while printing - * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value). - */ - A_UINT32 wifi_version; } htt_stats_tx_pdev_mu_mimo_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_mu_mimo_stats_tlv htt_tx_pdev_mu_mimo_sch_stats_tlv; @@ -5168,11 +3997,6 @@ typedef struct { A_UINT32 be_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; /** Number of 11AC DL MU MIMO schedules posted per group size (4 - 7)*/ A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz_ext[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; - /** - * Wi-Fi version identifier to differentiate stats while printing - * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value). - */ - A_UINT32 wifi_version; } htt_stats_tx_pdev_dl_mu_mimo_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_dl_mu_mimo_stats_tlv @@ -5196,15 +4020,6 @@ typedef struct { typedef htt_stats_tx_pdev_be_dl_mu_ofdma_stats_tlv htt_tx_pdev_be_dl_mu_ofdma_sch_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** Represents the count for 11BN DL MU OFDMA sequences */ - A_UINT32 bn_mu_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_BN_OFDMA_USER_STATS]; -} htt_stats_tx_pdev_bn_dl_mu_ofdma_stats_tlv; -/* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_tx_pdev_bn_dl_mu_ofdma_stats_tlv - htt_stats_tx_pdev_bn_dl_mu_ofdma_tlv; - typedef struct { htt_tlv_hdr_t tlv_hdr; /** @@ -5251,28 +4066,6 @@ typedef struct { typedef htt_stats_tx_pdev_be_ul_mu_ofdma_stats_tlv htt_tx_pdev_be_ul_mu_ofdma_sch_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * Represents the count for 11BN UL MU OFDMA sequences with Basic Triggers - */ - A_UINT32 bn_ul_mu_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_BN_OFDMA_USER_STATS]; - /** - * Represents the count for 11BN UL MU OFDMA sequences with BSRP Triggers - */ - A_UINT32 bn_ul_mu_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_BN_OFDMA_USER_STATS]; - /** - * Represents the count for 11BN UL MU OFDMA sequences with BAR Triggers - */ - A_UINT32 bn_ul_mu_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_BN_OFDMA_USER_STATS]; - /** - * TODO_BORON_OFDMA : Add array for BN_BRP number of users - */ -} htt_stats_tx_pdev_bn_ul_mu_ofdma_stats_tlv; -/* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_tx_pdev_bn_ul_mu_ofdma_stats_tlv - htt_stats_tx_pdev_bn_ul_mu_ofdma_tlv; - typedef struct { htt_tlv_hdr_t tlv_hdr; /** @@ -5303,18 +4096,6 @@ typedef struct { typedef htt_stats_tx_pdev_be_ul_mu_mimo_stats_tlv htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * Represents the count for 11BN UL MU MIMO sequences with Basic Triggers - */ - A_UINT32 bn_ul_mu_mimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; - /** - * Represents the count for 11BN UL MU MIMO sequences with BRP Triggers - */ - A_UINT32 bn_ul_mu_mimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; -} htt_stats_tx_pdev_bn_ul_mu_mimo_tlv; - typedef struct { htt_tlv_hdr_t tlv_hdr; /** 11AC DL MU MIMO number of mpdus queued to HW, per user */ @@ -5371,7 +4152,6 @@ typedef htt_stats_tx_pdev_mumimo_mpdu_stats_tlv #define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX 3 /* SCHED_TX_MODE_MU_OFDMA_AX */ #define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_BE 4 /* SCHED_TX_MODE_MU_OFDMA_BE */ #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_BE 5 /* SCHED_TX_MODE_MU_MIMO_BE */ -#define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_BN 6 /* SCHED_TX_MODE_MU_OFDMA_BN */ typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -5386,11 +4166,6 @@ typedef struct { A_UINT32 user_index; /** HTT_STATS_TX_SCHED_MODE_xxx */ A_UINT32 tx_sched_mode; - /** - * Wi-Fi version identifier to differentiate stats while printing - * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value). - */ - A_UINT32 wifi_version; } htt_stats_tx_pdev_mpdu_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_mpdu_stats_tlv htt_tx_pdev_mpdu_stats_tlv; @@ -5427,8 +4202,8 @@ typedef struct { /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /** Scheduler command posted per tx_mode (length = num tx modes) */ - HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sched_cmd_posted); + /** Scheduler command posted per tx_mode */ + A_UINT32 sched_cmd_posted[1/* length = num tx modes */]; } htt_stats_sched_txq_cmd_posted_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_sched_txq_cmd_posted_tlv htt_sched_txq_cmd_posted_tlv_v; @@ -5438,8 +4213,8 @@ typedef htt_stats_sched_txq_cmd_posted_tlv htt_sched_txq_cmd_posted_tlv_v; /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { htt_tlv_hdr_t tlv_hdr; - /** Scheduler command reaped per tx_mode (length = num tx modes) */ - HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sched_cmd_reaped); + /** Scheduler command reaped per tx_mode */ + A_UINT32 sched_cmd_reaped[1/* length = num tx modes */]; } htt_stats_sched_txq_cmd_reaped_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_sched_txq_cmd_reaped_tlv htt_sched_txq_cmd_reaped_tlv_v; @@ -5467,35 +4242,6 @@ typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 htt_stats_type; } htt_stats_error_tlv_v; -/* Multiple TLV tag values - * (HTT_STATS_UNSUPPORTED_ERROR_STATS_TAG, - * HTT_STATS_UNAVAILABLE_ERROR_STATS_TAG) - * correspond to this htt_stats_error_tlv_v struct. - * Provide aliases that have the expected names - * that are consistent with the TLV tag enum names. - */ -typedef htt_stats_error_tlv_v - htt_stats_unsupported_error_stats_tlv; -typedef htt_stats_error_tlv_v - htt_stats_unavailable_error_stats_tlv; - -/* NOTE: Variable length TLV, use length spec to infer array size */ -#define HTT_STATS_SCHED_TXQ_TX_MODE_SIMPLIFIED_TLV_SZ(_num_elems) \ - (sizeof(A_UINT32) * (_num_elems)) -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** Scheduler command posted per tx_mode (length = num tx modes+1) */ - HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sched_tx_mode_simplified); -} htt_stats_sched_txq_tx_mode_simplified_tlv; - -/* NOTE: Variable length TLV, use length spec to infer array size */ -#define HTT_STATS_SCHED_TXQ_TX_MODE_WINNER_TLV_SZ(_num_elems) \ - (sizeof(A_UINT32) * (_num_elems)) -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** Scheduler command posted per tx_mode (length = num tx modes+1) */ - HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, sched_tx_mode_winner); -} htt_stats_sched_txq_tx_mode_winner_tlv; typedef enum { HTT_SCHED_TID_SKIP_SCHED_MASK_DISABLED = 0, /* Skip the tid when WAL_TID_DISABLE_TX_SCHED_MASK is true */ @@ -5587,107 +4333,12 @@ typedef struct { * These supercycle trigger counts are not automatically reset, but * are reset upon request. */ - HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, supercycle_triggers); + A_UINT32 supercycle_triggers[1/*HTT_SCHED_SUPERCYCLE_TRIGGER_MAX*/]; } htt_stats_sched_txq_supercycle_trigger_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_sched_txq_supercycle_trigger_tlv htt_sched_txq_supercycle_triggers_tlv_v; -/* htt_tx_pdev_txq_stats_upload_t - * Enumerations for specifying which stats to upload in response to - * HTT_DBG_PDEV_TXQ_STATS. - */ -typedef enum { - /* upload all data TXQ stats */ - HTT_UPLOAD_DATA_TXQ_STATS, - /* upload MGMT/TWT TXQ stats */ - HTT_UPLOAD_MGMT_TWT_TXQ_STATS, -} htt_tx_pdev_txq_stats_upload_t; - -typedef enum { - /* Sequence combine successful */ - HTT_SCHED_COMBINED_SEQ_STATUS_SUCCESS = 0, - - /* Seq combine abort due to no prev sequence */ - HTT_SCHED_COMBINED_SEQ_STATUS_NO_ACTIVE_PREV_SEQ, - - /* Seq combine abort due to back to back allow flag set */ - HTT_SCHED_COMBINED_SEQ_STATUS_B2B_ALLOW_FLAG, - - /* combining will be disabled if sounding sequence is to be combined */ - HTT_SCHED_COMBINED_SEQ_STATUS_SOUNDING_SEQ_ABORT, - - /* Seq combine abort due to seq not constructed */ - HTT_SCHED_COMBINED_SEQ_STATUS_SEQ_NOT_CONSTRUCTED, - - /* Seq combine abort and subring change */ - HTT_SCHED_COMBINED_SEQ_STATUS_HW_PAUSED_SEQ_CONSRUCTED, - - /* Seq combine abort and indicate TAC */ - HTT_SCHED_COMBINED_SEQ_STATUS_HW_PAUSED_SEQ_NOT_CONSTRUCTED, - - /* Seq combine abort and seq restart */ - HTT_SCHED_COMBINED_SEQ_STATUS_HW_PAUSED_SEQ_POSTED, - - HTT_SCHED_COMBINED_SEQ_STATUS_MAX -} htt_sched_txq_combined_seq_status_tlv_enum; - -#define HTT_SCHED_TXQ_COMBINED_SEQ_STATE_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) - -/* NOTE: Variable length TLV, use length spec to infer array size */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * combined_seq_state counts the number of occurrences of different - * reasons for aborting combining two different sequence in TAC - * during posting - * - * Indexed by htt_sched_txq_combined_seq_status_tlv_enum. - */ - HTT_STATS_VAR_LEN_ARRAY1(A_UINT32, combined_seq_state); -} htt_stats_txq_combined_seq_state_tlv; -/* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_txq_combined_seq_state_tlv - htt_stats_sched_txq_combined_seq_state_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - A_UINT32 pdev_id__word; - struct { - A_UINT32 - pdev_id: 8, - reserved: 24; - }; - }; - A_UINT32 ist_txop_end_indicated_cnt; - A_UINT32 ist_txop_end_notify_at_cmd_status_end; - A_UINT32 ist_txop_end_notify_at_isr_end; - A_UINT32 sched_cmd_post_skip_on_seq_unavail; - A_UINT32 ist_txop_end_skip_on_seq_unavail; - A_UINT32 ist_txop_end_skip_on_mpdu_ownership; - A_UINT32 skip_early_schedule_due_to_per; - A_UINT32 sched_cmd_posted_at_hw_txop_end; - A_UINT32 sched_cmd_missed_at_hw_txop_end; - A_UINT32 sched_cmd_posted_at_sched_cmd_compl; - A_UINT32 sched_cmd_missed_at_sched_cmd_compl; - A_UINT32 num_QoS_sched_runs; -} htt_stats_sched_txq_early_compl_tlv; - -#define HTT_STATS_SCHED_TXQ_EARLY_COMPL_PDEV_ID_M 0x000000ff -#define HTT_STATS_SCHED_TXQ_EARLY_COMPL_PDEV_ID_S 0 - -#define HTT_STATS_SCHED_TXQ_EARLY_COMPL_PDEV_ID_GET(_var) \ - (((_var) & HTT_STATS_SCHED_TXQ_EARLY_COMPL_PDEV_ID_M) >> \ - HTT_STATS_SCHED_TXQ_EARLY_COMPL_PDEV_ID_S) - -#define HTT_STATS_SCHED_TXQ_EARLY_COMPL_PDEV_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_SCHED_TXQ_EARLY_COMPL_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_STATS_SCHED_TXQ_EARLY_COMPL_PDEV_ID_S)); \ - } while (0) - - #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_M 0x000000ff #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_S 0 @@ -5782,30 +4433,6 @@ typedef struct { A_UINT32 num_subcycles_with_sort; /** Num of subcycles without sort for this Txq */ A_UINT32 num_subcycles_no_sort; - /** num of times DPS client is scheduled */ - A_UINT32 num_dps_client_scheduled; - /** - * Number of first sched_cmd allowed for DL+UL/UL+DL sched_cmd combining - */ - A_UINT32 num_allowed_first_sched_command_for_combining; - /** - * Number of second sched_cmd allowed for DL+UL/UL+DL sched_cmd combining - */ - A_UINT32 num_allowed_second_command_for_combining; - /** - * Number of first sched_cmd aborted to avoid DL+UL/UL+DL sched_cmd - * combining - */ - A_UINT32 num_aborted_first_sched_command; - /** - * Number of second sched_cmd aborted to avoid DL+UL/UL+DL sched_cmd - * combining - */ - A_UINT32 num_aborted_second_sched_command; - /** Number combined sched_cmds sucessfully transmitted */ - A_UINT32 total_combined_sched_cmds_success; - /** Number combined sched_cmds failed to transmit */ - A_UINT32 total_combined_sched_cmds_failed; } htt_stats_tx_pdev_scheduler_txq_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_scheduler_txq_stats_tlv @@ -5831,13 +4458,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** Current timestamp */ A_UINT32 current_timestamp; } htt_stats_tx_sched_cmn_tlv; @@ -5851,28 +4472,22 @@ typedef struct { * - HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG * - HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG * - HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG - * - HTT_STATS_SCHED_TXQ_EARLY_COMPL_TAG */ /* NOTE: * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. */ -#ifdef ATH_TARGET typedef struct { htt_stats_tx_sched_cmn_tlv cmn_tlv; struct { - htt_stats_tx_pdev_scheduler_txq_stats_tlv txq_tlv; - htt_stats_sched_txq_cmd_posted_tlv cmd_posted_tlv; - htt_stats_sched_txq_cmd_reaped_tlv cmd_reaped_tlv; + htt_stats_tx_pdev_scheduler_txq_stats_tlv txq_tlv; + htt_stats_sched_txq_cmd_posted_tlv cmd_posted_tlv; + htt_stats_sched_txq_cmd_reaped_tlv cmd_reaped_tlv; htt_stats_sched_txq_sched_order_su_tlv sched_order_su_tlv; htt_stats_sched_txq_sched_ineligibility_tlv sched_ineligibility_tlv; - htt_stats_sched_txq_supercycle_trigger_tlv - htt_sched_txq_sched_ineligibility_tlv_esched_supercycle_trigger_tlv; - htt_stats_sched_txq_early_compl_tlv early_compl_tlv; - htt_stats_sched_txq_combined_seq_state_tlv combined_seq_state_tlv; + htt_stats_sched_txq_supercycle_trigger_tlv htt_sched_txq_sched_ineligibility_tlv_esched_supercycle_trigger_tlv; } txq[1]; } htt_stats_tx_sched_t; -#endif /* == TQM STATS == */ @@ -5964,15 +4579,6 @@ typedef struct { A_UINT32 tqm_enqueue_msdu_count; A_UINT32 tqm_dropped_msdu_count; A_UINT32 tqm_dequeue_msdu_count; - - A_UINT32 tqm_enqueue_msdu_count_ac[HTT_NUM_AC_WMM]; - A_UINT32 tqm_dropped_msdu_count_ac[HTT_NUM_AC_WMM]; - A_UINT32 tqm_dequeue_msdu_count_ac[HTT_NUM_AC_WMM]; - A_UINT32 remove_msdu_ac[HTT_NUM_AC_WMM]; - A_UINT32 remove_mpdu_ac[HTT_NUM_AC_WMM]; - A_UINT32 remove_msdu_ttl_ac[HTT_NUM_AC_WMM]; - A_UINT32 remove_mpdu_ttl_ac[HTT_NUM_AC_WMM]; - A_UINT32 remove_mpdu_retries_ac[HTT_NUM_AC_WMM]; } htt_stats_tx_tqm_pdev_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_tqm_pdev_tlv htt_tx_tqm_pdev_stats_tlv_v; @@ -5983,9 +4589,7 @@ typedef htt_stats_tx_tqm_pdev_tlv htt_tx_tqm_pdev_stats_tlv_v; #define HTT_TX_TQM_CMN_STATS_MAC_ID_GET(_var) \ (((_var) & HTT_TX_TQM_CMN_STATS_MAC_ID_M) >> \ HTT_TX_TQM_CMN_STATS_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_TQM_CMN_MAC_ID_GET(_var) \ - HTT_TX_TQM_CMN_STATS_MAC_ID_GET(_var) + #define HTT_TX_TQM_CMN_STATS_MAC_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_TX_TQM_CMN_STATS_MAC_ID, _val); \ @@ -5999,13 +4603,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; A_UINT32 max_cmdq_id; A_UINT32 list_mpdu_cnt_hist_intvl; @@ -6096,9 +4694,7 @@ typedef struct { #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_GET(_var) \ (((_var) & HTT_TX_TQM_CMDQ_STATUS_MAC_ID_M) >> \ HTT_TX_TQM_CMDQ_STATUS_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_TQM_CMDQ_STATUS_MAC_ID_GET(_var) \ - HTT_TX_TQM_CMDQ_STATUS_MAC_ID_GET(_var) + #define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_TX_TQM_CMDQ_STATUS_MAC_ID, _val); \ @@ -6108,9 +4704,7 @@ typedef struct { #define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_GET(_var) \ (((_var) & HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_M) >> \ HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_TQM_CMDQ_STATUS_CMDQ_ID_GET(_var) \ - HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_GET(_var) + #define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID, _val); \ @@ -6125,14 +4719,7 @@ typedef struct { * BIT [15 : 8] :- cmdq_id * BIT [31 : 16] :- reserved */ - union { - struct { - A_UINT32 mac_id : 8; - A_UINT32 cmdq_id : 8; - A_UINT32 reserved : 16; - }; - A_UINT32 mac_id__cmdq_id__word; - }; + A_UINT32 mac_id__cmdq_id__word; A_UINT32 sync_cmd; A_UINT32 write_cmd; A_UINT32 gen_mpdu_cmd; @@ -6368,13 +4955,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /* Global Stats */ A_UINT32 tcl2fw_entry_count; @@ -6391,38 +4972,8 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_de_cmn_tlv htt_tx_de_cmn_stats_tlv; -#define HTT_STATS_TX_DE_CMN_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - #define HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) ((dword >> 0) & 0xffff) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_RX_RING_STATS_SW2RXDMA_MAX_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_RXDMA2REO_MAX_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_REO2SW1_MAX_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_REO2SW4_MAX_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_REFILLRINGIPA_MAX_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_REFILLRINGHOST_MAX_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_SIZE_NUM_ENTRIES(dword) - #define HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) ((dword >> 16) & 0xffff) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_RX_RING_STATS_SW2RXDMA_CURR_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_RXDMA2REO_CURR_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_REO2SW1_CURR_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_REO2SW4_CURR_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_REFILLRINGIPA_CURR_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) -#define HTT_STATS_RX_RING_STATS_REFILLRINGHOST_CURR_NUM_ENTRIES_GET(dword) \ - HTT_STATS_RX_FW_RING_CURR_NUM_ENTRIES(dword) /* Rx debug info for status rings */ typedef struct { @@ -6432,54 +4983,12 @@ typedef struct { * (size of the ring in terms of entries) * BIT [16 : 31] :- current number of entries occupied in respective ring */ - union { - A_UINT32 entry_status_sw2rxdma; - struct { - A_UINT32 - max_num_entries: 16, - curr_num_entries: 16; - } sw2rxdma; - }; - union { - A_UINT32 entry_status_rxdma2reo; - struct { - A_UINT32 - max_num_entries: 16, - curr_num_entries: 16; - } rxdma2reo; - }; - union { - A_UINT32 entry_status_reo2sw1; - struct { - A_UINT32 - max_num_entries: 16, - curr_num_entries: 16; - } reo2sw1; - }; - union { - A_UINT32 entry_status_reo2sw4; - struct { - A_UINT32 - max_num_entries: 16, - curr_num_entries: 16; - } reo2sw4; - }; - union { - A_UINT32 entry_status_refillringipa; - struct { - A_UINT32 - max_num_entries: 16, - curr_num_entries: 16; - } refillringipa; - }; - union { - A_UINT32 entry_status_refillringhost; - struct { - A_UINT32 - max_num_entries: 16, - curr_num_entries: 16; - } refillringhost; - }; + A_UINT32 entry_status_sw2rxdma; + A_UINT32 entry_status_rxdma2reo; + A_UINT32 entry_status_reo2sw1; + A_UINT32 entry_status_reo2sw4; + A_UINT32 entry_status_refillringipa; + A_UINT32 entry_status_refillringhost; /** datarate - Moving Average of Number of Entries */ A_UINT32 datarate_refillringipa; A_UINT32 datarate_refillringhost; @@ -6654,47 +5163,23 @@ typedef struct { * BIT [15 : 0] :- num_elems * BIT [31 : 16] :- prefetch_tail_idx */ - union { - struct { - A_UINT32 num_elems : 16; - A_UINT32 prefetch_tail_idx : 16; - }; - A_UINT32 num_elems__prefetch_tail_idx; - }; + A_UINT32 num_elems__prefetch_tail_idx; /** * BIT [15 : 0] :- head_idx * BIT [31 : 16] :- tail_idx */ - union { - struct { - A_UINT32 head_idx : 16; - A_UINT32 tail_idx : 16; - }; - A_UINT32 head_idx__tail_idx; - }; + A_UINT32 head_idx__tail_idx; /** * BIT [15 : 0] :- shadow_head_idx * BIT [31 : 16] :- shadow_tail_idx */ - union { - struct { - A_UINT32 shadow_head_idx : 16; - A_UINT32 shadow_tail_idx : 16; - }; - A_UINT32 shadow_head_idx__shadow_tail_idx; - }; + A_UINT32 shadow_head_idx__shadow_tail_idx; A_UINT32 num_tail_incr; /** * BIT [15 : 0] :- lwm_thresh * BIT [31 : 16] :- hwm_thresh */ - union { - struct { - A_UINT32 lwm_thresh : 16; - A_UINT32 hwm_thresh : 16; - }; - A_UINT32 lwm_thresh__hwm_thresh; - }; + A_UINT32 lwm_thresh__hwm_thresh; A_UINT32 overrun_hit_count; A_UINT32 underrun_hit_count; A_UINT32 prod_blockwait_count; @@ -6711,9 +5196,6 @@ typedef htt_stats_ring_if_tlv htt_ring_if_stats_tlv; #define HTT_RING_IF_CMN_MAC_ID_GET(_var) \ (((_var) & HTT_RING_IF_CMN_MAC_ID_M) >> \ HTT_RING_IF_CMN_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RING_IF_CMN_MAC_ID_GET(_var) \ - HTT_RING_IF_CMN_MAC_ID_GET(_var) #define HTT_RING_IF_CMN_MAC_ID_SET(_var, _val) \ do { \ @@ -6728,13 +5210,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; A_UINT32 num_records; } htt_stats_ring_if_cmn_tlv; /* preserve old name alias for new name consistent with the tag name */ @@ -6800,9 +5276,7 @@ typedef htt_stats_sfm_client_tlv htt_sfm_client_tlv; #define HTT_SFM_CMN_MAC_ID_GET(_var) \ (((_var) & HTT_SFM_CMN_MAC_ID_M) >> \ HTT_SFM_CMN_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SFM_CMN_MAC_ID_GET(_var) \ - HTT_SFM_CMN_MAC_ID_GET(_var) + #define HTT_SFM_CMN_MAC_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SFM_CMN_MAC_ID, _val); \ @@ -6816,13 +5290,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** * Indicates the total number of 128 byte buffers in the CMEM * that are available for buffer sharing @@ -6881,9 +5349,7 @@ typedef struct { #define HTT_SRING_STATS_MAC_ID_GET(_var) \ (((_var) & HTT_SRING_STATS_MAC_ID_M) >> \ HTT_SRING_STATS_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_MAC_ID_GET(_var) \ - HTT_SRING_STATS_MAC_ID_GET(_var) + #define HTT_SRING_STATS_MAC_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_MAC_ID, _val); \ @@ -6893,9 +5359,7 @@ typedef struct { #define HTT_SRING_STATS_RING_ID_GET(_var) \ (((_var) & HTT_SRING_STATS_RING_ID_M) >> \ HTT_SRING_STATS_RING_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_RING_ID_GET(_var) \ - HTT_SRING_STATS_RING_ID_GET(_var) + #define HTT_SRING_STATS_RING_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_RING_ID, _val); \ @@ -6905,9 +5369,7 @@ typedef struct { #define HTT_SRING_STATS_ARENA_GET(_var) \ (((_var) & HTT_SRING_STATS_ARENA_M) >> \ HTT_SRING_STATS_ARENA_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_ARENA_GET(_var) \ - HTT_SRING_STATS_ARENA_GET(_var) + #define HTT_SRING_STATS_ARENA_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_ARENA, _val); \ @@ -6917,9 +5379,7 @@ typedef struct { #define HTT_SRING_STATS_EP_TYPE_GET(_var) \ (((_var) & HTT_SRING_STATS_EP_TYPE_M) >> \ HTT_SRING_STATS_EP_TYPE_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_EP_GET(_var) \ - HTT_SRING_STATS_EP_TYPE_GET(_var) + #define HTT_SRING_STATS_EP_TYPE_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_EP_TYPE, _val); \ @@ -6936,9 +5396,7 @@ typedef struct { #define HTT_SRING_STATS_NUM_AVAIL_WORDS_GET(_var) \ (((_var) & HTT_SRING_STATS_NUM_AVAIL_WORDS_M) >> \ HTT_SRING_STATS_NUM_AVAIL_WORDS_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_NUM_AVAIL_WORDS_GET(_var) \ - HTT_SRING_STATS_NUM_AVAIL_WORDS_GET(_var) + #define HTT_SRING_STATS_NUM_AVAIL_WORDS_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_NUM_AVAIL_WORDS, _val); \ @@ -6948,9 +5406,7 @@ typedef struct { #define HTT_SRING_STATS_NUM_VALID_WORDS_GET(_var) \ (((_var) & HTT_SRING_STATS_NUM_VALID_WORDS_M) >> \ HTT_SRING_STATS_NUM_VALID_WORDS_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_NUM_VALID_WORDS_GET(_var) \ - HTT_SRING_STATS_NUM_VALID_WORDS_GET(_var) + #define HTT_SRING_STATS_NUM_VALID_WORDS_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_NUM_VALID_WORDS, _val); \ @@ -6967,9 +5423,7 @@ typedef struct { #define HTT_SRING_STATS_HEAD_PTR_GET(_var) \ (((_var) & HTT_SRING_STATS_HEAD_PTR_M) >> \ HTT_SRING_STATS_HEAD_PTR_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_HEAD_PTR_GET(_var) \ - HTT_SRING_STATS_HEAD_PTR_GET(_var) + #define HTT_SRING_STATS_HEAD_PTR_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_HEAD_PTR, _val); \ @@ -6979,9 +5433,7 @@ typedef struct { #define HTT_SRING_STATS_TAIL_PTR_GET(_var) \ (((_var) & HTT_SRING_STATS_TAIL_PTR_M) >> \ HTT_SRING_STATS_TAIL_PTR_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_TAIL_PTR_GET(_var) \ - HTT_SRING_STATS_TAIL_PTR_GET(_var) + #define HTT_SRING_STATS_TAIL_PTR_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_TAIL_PTR, _val); \ @@ -6998,9 +5450,7 @@ typedef struct { #define HTT_SRING_STATS_CONSUMER_EMPTY_GET(_var) \ (((_var) & HTT_SRING_STATS_CONSUMER_EMPTY_M) >> \ HTT_SRING_STATS_CONSUMER_EMPTY_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_CONSUMER_EMPTY_GET(_var) \ - HTT_SRING_STATS_CONSUMER_EMPTY_GET(_var) + #define HTT_SRING_STATS_CONSUMER_EMPTY_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_CONSUMER_EMPTY, _val); \ @@ -7010,9 +5460,7 @@ typedef struct { #define HTT_SRING_STATS_PRODUCER_FULL_GET(_var) \ (((_var) & HTT_SRING_STATS_PRODUCER_FULL_M) >> \ HTT_SRING_STATS_PRODUCER_FULL_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_PRODUCER_FULL_GET(_var) \ - HTT_SRING_STATS_PRODUCER_FULL_GET(_var) + #define HTT_SRING_STATS_PRODUCER_FULL_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_PRODUCER_FULL, _val); \ @@ -7029,9 +5477,7 @@ typedef struct { #define HTT_SRING_STATS_PREFETCH_COUNT_GET(_var) \ (((_var) & HTT_SRING_STATS_PREFETCH_COUNT_M) >> \ HTT_SRING_STATS_PREFETCH_COUNT_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_PREFETCH_COUNT_GET(_var) \ - HTT_SRING_STATS_PREFETCH_COUNT_GET(_var) + #define HTT_SRING_STATS_PREFETCH_COUNT_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_PREFETCH_COUNT, _val); \ @@ -7041,9 +5487,7 @@ typedef struct { #define HTT_SRING_STATS_INTERNAL_TP_GET(_var) \ (((_var) & HTT_SRING_STATS_INTERNAL_TP_M) >> \ HTT_SRING_STATS_INTERNAL_TP_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_SRING_STATS_INTERNAL_TAIL_PTR_GET(_var) \ - HTT_SRING_STATS_INTERNAL_TP_GET(_var) + #define HTT_SRING_STATS_INTERNAL_TP_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_SRING_STATS_INTERNAL_TP, _val); \ @@ -7060,16 +5504,7 @@ typedef struct { * BIT [24 : 24] :- EP 0 -consumer, 1 - producer * BIT [31 : 25] :- reserved */ - union { - struct { - A_UINT32 mac_id : 8; - A_UINT32 ring_id : 8; - A_UINT32 arena : 8; - A_UINT32 ep : 1; - A_UINT32 reserved : 7; - }; - A_UINT32 mac_id__ring_id__arena__ep; - }; + A_UINT32 mac_id__ring_id__arena__ep; /** DWORD aligned base memory address of the ring */ A_UINT32 base_addr_lsb; A_UINT32 base_addr_msb; @@ -7083,49 +5518,25 @@ typedef struct { * BIT [15 : 0] :- num_avail_words * BIT [31 : 16] :- num_valid_words */ - union { - struct { - A_UINT32 num_avail_words : 16; - A_UINT32 num_valid_words : 16; - }; - A_UINT32 num_avail_words__num_valid_words; - }; + A_UINT32 num_avail_words__num_valid_words; /** Index of head and tail * BIT [15 : 0] :- head_ptr * BIT [31 : 16] :- tail_ptr */ - union { - struct { - A_UINT32 head_ptr : 16; - A_UINT32 tail_ptr : 16; - }; - A_UINT32 head_ptr__tail_ptr; - }; + A_UINT32 head_ptr__tail_ptr; /** Empty or full counter of rings * BIT [15 : 0] :- consumer_empty * BIT [31 : 16] :- producer_full */ - union { - struct { - A_UINT32 consumer_empty : 16; - A_UINT32 producer_full : 16; - }; - A_UINT32 consumer_empty__producer_full; - }; + A_UINT32 consumer_empty__producer_full; /** Prefetch status of consumer ring * BIT [15 : 0] :- prefetch_count * BIT [31 : 16] :- internal_tail_ptr */ - union { - struct { - A_UINT32 prefetch_count : 16; - A_UINT32 internal_tail_ptr : 16; - }; - A_UINT32 prefetch_count__internal_tail_ptr; - }; + A_UINT32 prefetch_count__internal_tail_ptr; } htt_stats_sring_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_sring_stats_tlv htt_sring_stats_tlv; @@ -7162,9 +5573,7 @@ typedef struct { #define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */ #define HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */ -#define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS_EXT 14 /* 0-13 */ #define HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 /* 14, 15 */ -#define HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS 4 /* 1.1, 3.1, 4.1, 7.1 */ #define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4 #define HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5 #define HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4 @@ -7175,7 +5584,6 @@ typedef struct { #define HTT_TX_PDEV_STATS_NUM_LTF 4 #define HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES 6 #define HTT_TX_PDEV_STATS_NUM_11BE_TRIGGER_TYPES 6 -#define HTT_TX_PDEV_STATS_NUM_11BN_TRIGGER_TYPES 6 #define HTT_TX_VDEV_STATS_NUM_SPATIAL_STREAMS 4 #define HTT_TX_NUM_OF_SOUNDING_STATS_WORDS \ (HTT_TX_PDEV_STATS_NUM_BW_COUNTERS * \ @@ -7194,19 +5602,6 @@ typedef struct { ((_var) |= ((_val) << HTT_TX_PDEV_RATE_STATS_MAC_ID_S)); \ } while (0) -#define HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_M 0x00000f00 -#define HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_S 8 - -#define HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_GET(_var) \ - (((_var) & HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_M) >> \ - HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_S) - -#define HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_PDEV_RATE_STATS_WIFI_VERSION, _val); \ - ((_var) |= ((_val) << HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_S)); \ - } while (0) - #define HTT_TX_PDEV_STATS_NUM_MCS_DROP_COUNTERS \ (HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + \ HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + \ @@ -7232,13 +5627,9 @@ typedef enum { /* 11be related updates */ #define HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS 16 /* 0...13,-2,-1 */ #define HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS 5 /* 20,40,80,160,320 MHz */ -/* 11bn MCS counters: all BE MCS indices and 4 UHR iMCS */ -#define HTT_TX_PDEV_STATS_NUM_BN_MCS_COUNTERS 20 -#define HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS 5 /* 20,40,80,160,320 MHz */ #define HTT_TX_PDEV_STATS_NUM_HE_SIG_B_MCS_COUNTERS 6 #define HTT_TX_PDEV_STATS_NUM_EHT_SIG_MCS_COUNTERS 4 -#define HTT_TX_PDEV_STATS_NUM_UHR_SIG_MCS_COUNTERS 4 typedef enum { HTT_TX_PDEV_STATS_AX_RU_SIZE_26, @@ -7271,39 +5662,14 @@ typedef enum { HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS, } HTT_TX_PDEV_STATS_BE_RU_SIZE; -#define HTT_TX_PDEV_STATS_NUM_BN_RU_SIZE_COUNTERS \ - HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS - -typedef enum { - HTT_WIFI_VER_UNKNOWN = 0, - HTT_WIFI_VER_11N = 4, - HTT_WIFI_VER_11AC = 5, - HTT_WIFI_VER_11AX = 6, - HTT_WIFI_VER_11BE = 7, - HTT_WIFI_VER_11BN = 8, -} HTT_RX_TX_PDEV_STATS_WIFI_VERSION; - typedef struct { htt_tlv_hdr_t tlv_hdr; /** * BIT [ 7 : 0] :- mac_id - * BIT [11 : 8] :- wifi_version - * BIT [31 : 12] :- reserved + * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - /* wifi_version: - * Holds a HTT_RX_TX_PDEV_STATS_WIFI_VERSION value. - * Refer to HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_GET - * / _SET macros for accessing this bitfield. - */ - wifi_version: 4, - reserved: 20; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** Number of tx ldpc packets */ A_UINT32 tx_ldpc; /** Number of tx rts packets */ @@ -7426,7 +5792,7 @@ typedef struct { A_UINT32 ax_su_embedded_trigger_data_ppdu; /** 11AX HE SU data + embedded trigger PPDU failure stats (stats for HETP ack failure PPDU cnt) */ A_UINT32 ax_su_embedded_trigger_data_ppdu_err; - /** STA side trigger stats */ + /** sta side trigger stats */ A_UINT32 trigger_type_11be[HTT_TX_PDEV_STATS_NUM_11BE_TRIGGER_TYPES]; /** Stats for Extra EHT LTF */ A_UINT32 extra_eht_ltf; @@ -7434,51 +5800,10 @@ typedef struct { A_UINT32 extra_eht_ltf_ofdma; /** 11AX HE UL_BA RU Size stats */ A_UINT32 ofdma_ba_ru_size[HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS]; - /** Number of tx 2xldpc packets */ - A_UINT32 tx_2xldpc; - A_UINT32 rc_state_probe_mismatched; - /* npca_tx_bw: NPCA bw info - * element 0: 20 MHz - * element 1: 40 MHz - * element 2: 80 MHz - * element 3: 160 MHz - * element 4: 320 MHz - */ - A_UINT32 npca_tx_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - /* npca_tx_su_punctured_mode: NPCA punctured mode info - * element 0: no puncture - * element 1: 20 MHz punctured - * element 2: 40 MHz punctured - * element 3: 80 MHz punctured - * element 4: 120 MHz punctured - */ - A_UINT32 npca_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; - /* STA side trigger stats */ - A_UINT32 trigger_type_11bn[HTT_TX_PDEV_STATS_NUM_11BN_TRIGGER_TYPES]; -#if 0 - /* NOTE: - * The tx_mcs_ext_3 field is being reverted at least temporarily, - * to work around message size limits in certain targets. - * If/when this revert becomes permanent, this "#if 0" block will - * be removed altogether. - */ - /* Stats for iMCS 1.1, 3.1, 4.1, 7.1 */ - A_UINT32 tx_mcs_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS]; -#endif - -/* - * NOTE: THIS STRUCT HAS ONLY 20 BYTES OF SPACE LEFT - * WITHIN THE TARGET'S HTT_STATS_TLV_MAX_LEN SIZE LIMIT. - */ } htt_stats_tx_pdev_rate_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_rate_stats_tlv htt_tx_pdev_rate_stats_tlv; -#define HTT_STATS_TX_PDEV_RATE_STATS_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) -#define HTT_STATS_TX_PDEV_RATE_STATS_WIFI_VERSION_GET(word) \ - (((word) >> 8) & 0xf) - typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 vdev_id; /* which vdev produced these per-Nss tx stats */ @@ -7506,11 +5831,6 @@ typedef struct { A_UINT32 be_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; /** 11BE DL MU MIMO LDPC count */ A_UINT32 be_mu_mimo_tx_ldpc; - /** - * Wi-Fi version identifier to differentiate stats while printing - * (contains enum HTT_RX_TX_PDEV_STATS_WIFI_VERSION value). - */ - A_UINT32 wifi_version; } htt_stats_tx_pdev_be_rate_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_be_rate_stats_tlv htt_tx_pdev_rate_stats_be_tlv; @@ -7564,13 +5884,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** 11BE EHT DL MU OFDMA LDPC count */ A_UINT32 be_ofdma_tx_ldpc; @@ -7588,44 +5902,17 @@ typedef struct { A_UINT32 be_ofdma_tx_ru_size[HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; /** 11BE EHT DL MU OFDMA EHT-SIG MCS stats */ A_UINT32 be_ofdma_eht_sig_mcs[HTT_TX_PDEV_STATS_NUM_EHT_SIG_MCS_COUNTERS]; - /** 11BE UHT DL MU OFDMA BA RU size stats */ A_UINT32 be_ofdma_ba_ru_size[HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; - - /** 11BN UHR DL MU OFDMA LDPC count */ - A_UINT32 bn_ofdma_tx_ldpc; - /** 11BE UHR DL MU OFDMA TX MCS stats */ - A_UINT32 bn_ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_BN_MCS_COUNTERS]; - /** - * 11BN UHR DL MU OFDMA TX NSS stats (Indicates NSS for individual users) - */ - A_UINT32 bn_ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; - /** 11BN UHR DL MU OFDMA TX BW stats */ - A_UINT32 bn_ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - /** 11BN UHR DL MU OFDMA TX guard interval stats */ - A_UINT32 bn_ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_BN_MCS_COUNTERS]; - /** 11BN UHR DL MU OFDMA TX RU Size stats */ - A_UINT32 bn_ofdma_tx_ru_size[HTT_TX_PDEV_STATS_NUM_BN_RU_SIZE_COUNTERS]; - /** 11BN UHR DL MU OFDMA UHR-SIG MCS stats */ - A_UINT32 bn_ofdma_uhr_sig_mcs[HTT_TX_PDEV_STATS_NUM_UHR_SIG_MCS_COUNTERS]; - /** 11BN UHR DL MU OFDMA BA RU size stats */ - A_UINT32 bn_ofdma_ba_ru_size[HTT_TX_PDEV_STATS_NUM_BN_RU_SIZE_COUNTERS]; -} htt_stats_tx_pdev_rate_be_bn_ofdma_tlv; -/* preserve old names as aliases */ -typedef htt_stats_tx_pdev_rate_be_bn_ofdma_tlv - htt_stats_tx_pdev_rate_stats_be_ofdma_tlv; -typedef htt_stats_tx_pdev_rate_be_bn_ofdma_tlv +} htt_stats_tx_pdev_rate_stats_be_ofdma_tlv; +/* preserve old name alias for new name consistent with the tag name */ +typedef htt_stats_tx_pdev_rate_stats_be_ofdma_tlv htt_tx_pdev_rate_stats_be_ofdma_tlv; -#define HTT_STATS_TX_PDEV_RATE_BE_BN_OFDMA_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - typedef struct { htt_tlv_hdr_t tlv_hdr; /** tx_ppdu_dur_hist: * Tx PPDU duration histogram, which holds the tx duration of PPDUs * under histogram bins of interval 250us - * - * Note that this histogram is extended by tx_ppdu_dur_hist_ext[] below. */ A_UINT32 tx_ppdu_dur_hist[HTT_PDEV_STATS_PPDU_DUR_HIST_BINS]; A_UINT32 tx_success_time_us_low; @@ -7639,83 +5926,10 @@ typedef struct { * OFDMA PPDUs under histogram bins of interval 250us */ A_UINT32 tx_ofdma_ppdu_dur_hist[HTT_PDEV_STATS_PPDU_DUR_HIST_BINS]; - /* tx_ppdu_dur_hist_ext: - * This array extends the PPDU duration histogram contained in the - * tx_ppdu_dur_hist[] array from 4 ms to 5.5 ms. - */ - A_UINT32 tx_ppdu_dur_hist_ext[HTT_PDEV_STATS_PPDU_DUR_HIST_EXT_BINS]; } htt_stats_tx_pdev_ppdu_dur_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_tx_pdev_ppdu_dur_tlv htt_tx_pdev_ppdu_dur_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** tx_txop_dur_hist: - * Tx txop duration histogram, which holds the total txop used - * under histogram bins of interval 1ms - */ - A_UINT32 tx_su_mdsb_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS]; - A_UINT32 tx_ofdma_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS]; - A_UINT32 tx_mimo_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS]; - A_UINT32 combined_sched_cmd_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS]; -} htt_stats_tx_pdev_txop_dur_tlv; - -#define HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_M 0x000000ff -#define HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_S 0 -#define HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_GET(_var) \ - (((_var) & HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_M) >> \ - HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_PDEV_BN_RATE_MAC_ID_GET(_var) \ - HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_GET(_var) -#define HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_PDEV_BN_RATE_STATS_MAC_ID, _val); \ - ((_var) |= ((_val) << HTT_TX_PDEV_BN_RATE_STATS_MAC_ID_S)); \ - } while (0) - -#define HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_M 0x00000f00 -#define HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_S 8 -#define HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_GET(_var) \ - (((_var) & HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_M) >> \ - HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_PDEV_BN_RATE_WIFI_VERSION_GET(_var) \ - HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_GET(_var) -#define HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION, _val); \ - ((_var) |= ((_val) << HTT_TX_PDEV_BN_RATE_STATS_WIFI_VERSION_S)); \ - } while (0) - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * BIT [ 7 : 0] :- mac_id - * BIT [11 : 8] :- wifi_version - * BIT [31 : 12] :- reserved - */ - union { - struct { - A_UINT32 mac_id: 8, - /* wifi_version: - * Holds a HTT_RX_TX_PDEV_STATS_WIFI_VERSION value. - * Refer to HTT_TX_PDEV_RATE_STATS_WIFI_VERSION_GET - * / _SET macros for accessing this bitfield. - */ - wifi_version: 4, - reserved: 20; - }; - A_UINT32 mac_id__word; - }; - /* Stats for iMCS 1.1, 3.1, 4.1, 7.1 */ - A_UINT32 tx_mcs_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS]; - A_UINT32 tx_gi_ext_3[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS]; - A_UINT32 tx_stbc_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS]; - /* Stats for UHR ELR */ - A_UINT32 tx_11bn_su_elr; -} htt_stats_tx_pdev_bn_rate_tlv; - /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_RATE * TLV_TAGS: * - HTT_STATS_TX_PDEV_RATE_STATS_TAG @@ -7726,12 +5940,10 @@ typedef struct { */ #ifdef ATH_TARGET typedef struct { - htt_stats_tx_pdev_bn_rate_tlv rate_bn_tlv; htt_stats_tx_pdev_rate_stats_tlv rate_tlv; htt_stats_tx_pdev_be_rate_stats_tlv rate_be_tlv; htt_stats_tx_pdev_sawf_rate_stats_tlv rate_sawf_tlv; htt_stats_tx_pdev_ppdu_dur_tlv tx_ppdu_dur_tlv; - htt_stats_tx_pdev_txop_dur_tlv tx_txop_dur_tlv; } htt_tx_pdev_rate_stats_t; #endif /* ATH_TARGET */ @@ -7742,7 +5954,6 @@ typedef struct { #define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */ #define HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */ #define HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 /* 14, 15 */ -#define HTT_RX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS 4 /* 1.1, 3.1, 4.1, 7.1 */ #define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT 14 /* 0-13 */ #define HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4 #define HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5 @@ -7758,9 +5969,6 @@ typedef struct { #define HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS 16 #define HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS 16 /* 0-13, -2, -1 */ #define HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS 5 /* 20,40,80,160,320 MHz */ -/* 802.11BN MCS: all 16 EHT MCS indices and 4 UHR iMCS */ -#define HTT_RX_PDEV_STATS_NUM_BN_MCS_COUNTERS 20 -#define HTT_RX_PDEV_STATS_NUM_BN_BW_COUNTERS 5 /* 20,40,80,160,320 MHz */ /* HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS: * RU size index 0: HTT_UL_OFDMA_V0_RU_SIZE_RU_26 @@ -7802,9 +6010,6 @@ typedef enum { HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS, } HTT_RX_PDEV_STATS_BE_RU_SIZE; -#define HTT_RX_PDEV_STATS_NUM_BN_RU_SIZE_COUNTERS \ - HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS - #define HTT_RX_PDEV_RATE_STATS_MAC_ID_M 0x000000ff #define HTT_RX_PDEV_RATE_STATS_MAC_ID_S 0 @@ -7837,13 +6042,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; A_UINT32 nsts; /** Number of rx ldpc packets */ @@ -7985,7 +6184,6 @@ typedef struct { /* Stats for MCS 12/13 */ A_UINT32 rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; - A_UINT32 rx_11bn_su_elr; /* * NOTE - this TLV is already large enough that it causes the HTT message * carrying it to be nearly at the message size limit that applies to @@ -7997,9 +6195,6 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_pdev_rate_stats_tlv htt_rx_pdev_rate_stats_tlv; -#define HTT_STATS_RX_PDEV_RATE_STATS_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - typedef struct { htt_tlv_hdr_t tlv_hdr; /** Tx PPDU duration histogram **/ @@ -8043,22 +6238,6 @@ typedef struct { } htt_rx_pdev_rate_stats_t; #endif /* ATH_TARGET */ -#define HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_M 0x0000000f -#define HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_S 0 - -#define HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_GET(_var) \ - (((_var) & HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_M) >> \ - HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RX_PDEV_RATE_EXT_STATS_WIFI_VERSION_GET(_var) \ - HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_GET(_var) - -#define HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION, _val); \ - ((_var) |= ((_val) << HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_S)); \ - } while (0) - typedef struct { htt_tlv_hdr_t tlv_hdr; /** units = dB above noise floor */ @@ -8088,29 +6267,6 @@ typedef struct { A_UINT32 reduced_rx_bw[HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; A_UINT8 rssi_chain_ext_2[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_2_COUNTERS]; /* units = dB above noise floor */ A_INT8 rx_per_chain_rssi_ext_2_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_2_COUNTERS]; - /** - * BIT [ 3 : 0] :- wifi_version - * BIT [31 : 4] :- reserved - */ - union { - struct { - A_UINT32 - /* wifi_version: - * Holds a HTT_RX_TX_PDEV_STATS_WIFI_VERSION value. - * Refer to HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_GET - * / _SET macros for accessing this bitfield. - */ - wifi_version: 4, - reserved: 28; - }; - A_UINT32 wifi_version__word; - }; - /** Number of rx 2xldpc packets */ - A_UINT32 rx_2xldpc; - A_UINT32 npca_rx_bw_ext[HTT_RX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - A_UINT32 npca_rx_su_punctured_mode[HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; - /* Stats for iMCS 1.1, 3.1, 4.1, 7.1 */ - A_UINT32 rx_mcs_ext_3[HTT_RX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS]; } htt_stats_rx_pdev_rate_ext_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_pdev_rate_ext_stats_tlv htt_rx_pdev_rate_ext_stats_tlv; @@ -8144,8 +6300,6 @@ typedef struct { #define HTT_RX_UL_MAX_UPLINK_RSSI_TRACK 5 -#define HTT_STATS_MAX_NUM_TCP_IMPLICIT_TRIG_INTR 12 - typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -8153,13 +6307,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; A_UINT32 rx_11ax_ul_ofdma; @@ -8209,27 +6357,10 @@ typedef struct { * response to basic trigger. Typically a data response is expected. */ A_UINT32 ul_ofdma_basic_trigger_rx_qos_null_only; - - /* tcp_aware_implicit_trig_hist_ms: - * Each histogram bin represents a 3 ms range: - * tcp_aware_implicit_trig_hist_ms[0] -> 0-3 ms, - * tcp_aware_implicit_trig_hist_ms[1] -> 3-6 ms, - * etc. - */ - A_UINT32 tcp_aware_implicit_trig_hist_ms[HTT_STATS_MAX_NUM_TCP_IMPLICIT_TRIG_INTR]; - - A_UINT32 ulofdma_implicit_trig_tried; - A_UINT32 ulofdma_implicit_trig_qos_null; - - /* Txop duration history from 0 to 12 ms with interval of 1000us */ - A_UINT32 ul_ofdma_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS]; } htt_stats_rx_pdev_ul_trig_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_pdev_ul_trig_stats_tlv htt_rx_pdev_ul_trigger_stats_tlv; -#define HTT_STATS_RX_PDEV_UL_TRIG_STATS_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS * TLV_TAGS: * - HTT_STATS_RX_PDEV_UL_TRIG_STATS_TAG @@ -8250,13 +6381,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; A_UINT32 rx_11be_ul_ofdma; @@ -8313,72 +6438,14 @@ typedef struct { A_UINT32 ul_mlo_proc_qdepth_params_count; A_UINT32 ul_mlo_proc_accepted_qdepth_params_count; A_UINT32 ul_mlo_proc_discarded_qdepth_params_count; - - A_UINT32 rx_11bn_ul_ofdma; - - A_UINT32 bn_ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_BN_MCS_COUNTERS]; - A_UINT32 bn_ul_ofdma_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_BN_MCS_COUNTERS]; - A_UINT32 bn_ul_ofdma_rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; - A_UINT32 bn_ul_ofdma_rx_bw[HTT_RX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - A_UINT32 bn_ul_ofdma_rx_stbc; - A_UINT32 bn_ul_ofdma_rx_ldpc; - - /* - * These are arrays to hold the number of PPDUs that we received per RU. - * E.g. PPDUs (data or non data) received in RU26 will be incremented in - * array offset 0 and similarly RU52 will be incremented in array offset 1 - */ - /** PPDU level */ - A_UINT32 bn_rx_ulofdma_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_BN_RU_SIZE_COUNTERS]; - /** PPDU level */ - A_UINT32 bn_rx_ulofdma_non_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_BN_RU_SIZE_COUNTERS]; - - /** - * STA AID array for identifying which STA the - * Target-RSSI / FD-RSSI / pwr headroom stats are for - */ - A_UINT32 bn_uplink_sta_aid[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; - /** - * Trig Target RSSI for STA AID in same index - UNIT(dBm) - */ - A_INT32 bn_uplink_sta_target_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; - /** - * Trig FD RSSI from STA AID in same index - UNIT(dBm) - */ - A_INT32 bn_uplink_sta_fd_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; - /** - * Trig power headroom for STA AID in same idx - UNIT(dB) - */ - A_UINT32 bn_uplink_sta_power_headroom[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; - - /* - * Number of UHR UL OFDMA per-user responses containing only a QoS null in - * response to basic trigger. Typically a data response is expected. - */ - A_UINT32 bn_ul_ofdma_basic_trigger_rx_qos_null_only; - - /* UL OFDMA DRU spreading BW size */ - A_UINT32 bn_ul_ofdma_rx_dru_sbw[HTT_BN_UL_OFDMA_NUM_DRU_SBW_COUNT]; - /* UL OFDMA DRU size of data PPDU */ - A_UINT32 bn_rx_ulofdma_data_dru_size_ppdu[HTT_TX_PDEV_STATS_NUM_BN_DRU_SIZE_COUNTERS]; - - A_UINT32 be_ulofdma_implicit_trig_tried; - A_UINT32 be_ulofdma_implicit_trig_qos_null; - A_UINT32 bn_ulofdma_implicit_trig_tried; - A_UINT32 bn_ulofdma_implicit_trig_qos_null; -} htt_stats_rx_pdev_be_bn_ul_trig_tlv; -/* preserve old names as aliases */ -typedef htt_stats_rx_pdev_be_bn_ul_trig_tlv - htt_stats_rx_pdev_be_ul_trig_stats_tlv; -typedef htt_stats_rx_pdev_be_bn_ul_trig_tlv +} htt_stats_rx_pdev_be_ul_trig_stats_tlv; +/* preserve old name alias for new name consistent with the tag name */ +typedef htt_stats_rx_pdev_be_ul_trig_stats_tlv htt_rx_pdev_be_ul_trigger_stats_tlv; -#define HTT_STATS_RX_PDEV_BE_BN_UL_TRIG_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS * TLV_TAGS: - * - HTT_STATS_RX_PDEV_BE_BN_UL_TRIG_TAG + * - HTT_STATS_RX_PDEV_BE_UL_TRIG_STATS_TAG * NOTE: * This structure is for documentation, and cannot be safely used directly. * Instead, use the constituent TLV structures to fill/parse. @@ -8427,22 +6494,6 @@ typedef struct { typedef htt_stats_rx_pdev_be_ul_ofdma_user_stats_tlv htt_rx_pdev_be_ul_ofdma_user_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - - A_UINT32 user_index; - /** PPDU level */ - A_UINT32 bn_rx_ulofdma_non_data_ppdu; - /** PPDU level */ - A_UINT32 bn_rx_ulofdma_data_ppdu; - /** MPDU level */ - A_UINT32 bn_rx_ulofdma_mpdu_ok; - /** MPDU level */ - A_UINT32 bn_rx_ulofdma_mpdu_fail; - A_UINT32 bn_rx_ulofdma_non_data_nusers; - A_UINT32 bn_rx_ulofdma_data_nusers; -} htt_stats_rx_pdev_bn_ul_ofdma_user_tlv; - typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -8477,39 +6528,18 @@ typedef struct { typedef htt_stats_rx_pdev_be_ul_mimo_user_stats_tlv htt_rx_pdev_be_ul_mimo_user_stats_tlv; -typedef struct { - htt_tlv_hdr_t tlv_hdr; - - A_UINT32 user_index; - /** PPDU level */ - A_UINT32 bn_rx_ulmumimo_non_data_ppdu; - /** PPDU level */ - A_UINT32 bn_rx_ulmumimo_data_ppdu; - /** MPDU level */ - A_UINT32 bn_rx_ulmumimo_mpdu_ok; - /** MPDU level */ - A_UINT32 bn_rx_ulmumimo_mpdu_fail; -} htt_stats_rx_pdev_bn_ul_mimo_user_tlv; - - /* == RX PDEV/SOC STATS == */ typedef struct { htt_tlv_hdr_t tlv_hdr; /** - * BIT [ 7 : 0] :- mac_id - * BIT [31 : 8] :- reserved + * BIT [7:0] :- mac_id + * BIT [31:8] :- reserved * * Refer to HTT_STATS_CMN_MAC_ID_GET/SET macros. */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** Number of times UL MUMIMO RX packets received */ A_UINT32 rx_11ax_ul_mumimo; @@ -8554,32 +6584,21 @@ typedef struct { * response to basic trigger. Typically a data response is expected. */ A_UINT32 ul_mumimo_basic_trigger_rx_qos_null_only; - /* Txop duration history from 0 to 12 ms with interval of 1000us */ - A_UINT32 ul_mimo_txop_dur_hist[HTT_PDEV_STATS_TXOP_DUR_HIST_BINS]; } htt_stats_rx_pdev_ul_mumimo_trig_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_pdev_ul_mumimo_trig_stats_tlv htt_rx_pdev_ul_mumimo_trig_stats_tlv; -#define HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - typedef struct { htt_tlv_hdr_t tlv_hdr; /** - * BIT [ 7 : 0] :- mac_id - * BIT [31 : 8] :- reserved + * BIT [7:0] :- mac_id + * BIT [31:8] :- reserved * * Refer to HTT_STATS_CMN_MAC_ID_GET/SET macros. */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** Number of times UL MUMIMO RX packets received */ A_UINT32 rx_11be_ul_mumimo; @@ -8626,81 +6645,15 @@ typedef struct { typedef htt_stats_rx_pdev_ul_mumimo_trig_be_stats_tlv htt_rx_pdev_ul_mumimo_trig_be_stats_tlv; -#define HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - - /** - * BIT [ 7 : 0] :- mac_id - * BIT [31 : 8] :- reserved - * - * Refer to HTT_STATS_CMN_MAC_ID_GET/SET macros. - */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; - - /** Number of times UL MUMIMO RX packets received */ - A_UINT32 rx_11bn_ul_mumimo; - - /** 11BN UHR UL MU-MIMO RX TB PPDU MCS stats */ - A_UINT32 bn_ul_mumimo_rx_mcs[HTT_RX_PDEV_STATS_NUM_BN_MCS_COUNTERS]; - /** - * 11BN UHR UL MU-MIMO RX GI & LTF stats. - * Index 0 indicates 1xLTF + 1.6 msec GI - * Index 1 indicates 2xLTF + 1.6 msec GI - * Index 2 indicates 4xLTF + 3.2 msec GI - */ - A_UINT32 bn_ul_mumimo_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_BN_MCS_COUNTERS]; - /** - * 11BN UHR UL MU-MIMO RX TB PPDU NSS stats - * (Increments the individual user NSS in the UL MU MIMO PPDU received) - */ - A_UINT32 bn_ul_mumimo_rx_nss[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; - /** 11BN UHR UL MU-MIMO RX TB PPDU BW stats */ - A_UINT32 bn_ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - /** Number of times UL MUMIMO TB PPDUs received with STBC */ - A_UINT32 bn_ul_mumimo_rx_stbc; - /** Number of times UL MUMIMO TB PPDUs received with LDPC */ - A_UINT32 bn_ul_mumimo_rx_ldpc; - - /** RSSI in dBm for Rx TB PPDUs */ - A_INT8 bn_rx_ul_mumimo_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; - /** Target RSSI programmed in UL MUMIMO triggers (units dBm) */ - A_INT8 bn_rx_ul_mumimo_target_rssi[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; - /** FD RSSI measured for Rx UL TB PPDUs (units dBm) */ - A_INT8 bn_rx_ul_mumimo_fd_rssi[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; - /** Average pilot EVM measued for RX UL TB PPDU */ - A_INT8 bn_rx_ulmumimo_pilot_evm_dB_mean[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; - /** Number of times UL MUMIMO TB PPDUs received in a punctured mode */ - A_UINT32 bn_rx_ul_mumimo_punctured_mode[HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; - /* - * Number of UHR UL MU-MIMO per-user responses containing only a QoS null - * in response to basic trigger. Typically a data response is expected. - */ - A_UINT32 bn_ul_mumimo_basic_trigger_rx_qos_null_only; -} htt_stats_rx_pdev_ul_mumimo_trig_bn_tlv; - -#define HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BN_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS * TLV_TAGS: * - HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_TAG * - HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_TAG - * - HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BN_TAG */ #ifdef ATH_TARGET typedef struct { htt_stats_rx_pdev_ul_mumimo_trig_stats_tlv ul_mumimo_trig_tlv; htt_stats_rx_pdev_ul_mumimo_trig_be_stats_tlv ul_mumimo_trig_be_tlv; - htt_stats_rx_pdev_ul_mumimo_trig_bn_tlv ul_mumimo_trig_bn_tlv; } htt_rx_pdev_ul_mumimo_trig_stats_t; #endif /* ATH_TARGET */ @@ -8884,9 +6837,7 @@ typedef struct { #define HTT_RX_PDEV_FW_STATS_MAC_ID_GET(_var) \ (((_var) & HTT_RX_PDEV_FW_STATS_MAC_ID_M) >> \ HTT_RX_PDEV_FW_STATS_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RX_PDEV_FW_STATS_MAC_ID_GET(_var) \ - HTT_RX_PDEV_FW_STATS_MAC_ID_GET(_var) + #define HTT_RX_PDEV_FW_STATS_MAC_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_RX_PDEV_FW_STATS_MAC_ID, _val); \ @@ -8900,13 +6851,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** Num PPDU status processed from HW */ A_UINT32 ppdu_recvd; /** Num MPDU across PPDUs with FCS ok */ @@ -9011,7 +6956,6 @@ typedef struct { /* upper 32 bits of the rx_bytes value */ A_UINT32 high_32; } bytes_received; - A_UINT32 rx_msdu_cnt_ac[HTT_NUM_AC_WMM]; } htt_stats_rx_pdev_fw_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_pdev_fw_stats_tlv htt_rx_pdev_fw_stats_tlv; @@ -9038,13 +6982,7 @@ typedef struct { * BIT [ 7 : 0] :- mac_id * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; /** Num of phy err */ A_UINT32 total_phy_err_cnt; /** Counts of different types of phy errs @@ -9100,9 +7038,6 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_rx_pdev_fw_stats_phy_err_tlv htt_rx_pdev_fw_stats_phy_err_tlv; -#define HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) - #define HTT_RX_PDEV_FW_RING_MPDU_ERR_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) /* NOTE: Variable length TLV, use length spec to infer array size */ @@ -10175,36 +8110,6 @@ typedef enum { HTT_STATS_RU_TYPE_SINGLE_AND_MULTI_RU = 2, } htt_stats_ru_type; -typedef enum { - HTT_TX_PER_RATE_STATS_LOW_QUEUE_DEPTH = 0, - HTT_TX_PER_RATE_STATS_HIGH_QUEUE_DEPTH = 1, - - HTT_TX_PER_RATE_STATS_NUM_QUEUE_DEPTH_COUNTERS = 2 -} HTT_TX_PER_RATE_STATS_NUM_QUEUE_DEPTH_TYPE; - -typedef enum { - HTT_TX_PER_RATE_STATS_MLO_RA_DD_NO_MCS_DROP = 0, - HTT_TX_PER_RATE_STATS_MLO_RA_DD_ONE_OR_MORE_MCS_DROP = 1, - - HTT_TX_PER_RATE_STATS_NUM_MLO_RA_DD_MCS_DROP_COUNTERS = 2 -} HTT_TX_PER_RATE_STATS_NUM_MLO_RA_DD_MCS_DROP_TYPE; - -#define HTT_PER_RATE_STATS_WIFI_VERSION_M 0x0000000f -#define HTT_PER_RATE_STATS_WIFI_VERSION_S 0 - -#define HTT_PER_RATE_STATS_WIFI_VERSION_GET(_var) \ - (((_var) & HTT_PER_RATE_STATS_WIFI_VERSION_M) >> \ - HTT_PER_RATE_STATS_WIFI_VERSION_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PER_RATE_STATS_WIFI_VERSION_GET(_var) \ - HTT_PER_RATE_STATS_WIFI_VERSION_GET(_var) - -#define HTT_PER_RATE_STATS_WIFI_VERSION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_PER_RATE_STATS_WIFI_VERSION, _val); \ - ((_var) |= ((_val) << HTT_PER_RATE_STATS_WIFI_VERSION_S)); \ - } while (0) - typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -10230,49 +8135,6 @@ typedef struct { A_UINT32 ru_type; /* refer to htt_stats_ru_type enum */ htt_tx_rate_stats_t per_ru[HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; - - htt_tx_rate_stats_t per_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; - - /* mlo_ra_queue_depth_status: - * MLO SU Tx low/high queue depth PPDU counter, - * mlo_ra_queue_depth_status[0]: lowq depth - * mlo_ra_queue_depth_status[1]: high queue depth - */ - A_UINT32 mlo_ra_queue_depth_status[HTT_TX_PER_RATE_STATS_NUM_QUEUE_DEPTH_COUNTERS]; - /* mlo_rate_drop_down: - * MLO RA MCS drop counter, - * mlo_rate_drop_down[0]: No MCS drop - * mlo_rate_drop_down[1]: MCS drop counter - */ - A_UINT32 mlo_rate_drop_down[HTT_TX_PER_RATE_STATS_NUM_MLO_RA_DD_MCS_DROP_COUNTERS]; - - /** - * BIT [ 3 : 0] :- wifi_version - * BIT [31 : 4] :- reserved - */ - union { - struct { - A_UINT32 - /* wifi_version: - * Holds a HTT_RX_TX_PDEV_STATS_WIFI_VERSION value. - * Refer to HTT_PER_RATE_STATS_WIFI_VERSION_GET - * / _SET macros for accessing this bitfield. - */ - wifi_version: 4, - reserved: 28; - }; - A_UINT32 wifi_version__word; - }; - - htt_tx_rate_stats_t npca_per_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - - htt_tx_rate_stats_t npca_per_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; - - /* PER stats for iMCS 1.1, 3.1, 4.1, 7.1 */ - htt_tx_rate_stats_t per_mcs_ext_3[HTT_TX_PDEV_STATS_NUM_EXTRA3_MCS_COUNTERS]; - - /* PER stats per DRU size */ - htt_tx_rate_stats_t per_dru[HTT_TX_PDEV_STATS_NUM_BN_DRU_SIZE_COUNTERS]; } htt_stats_per_rate_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_per_rate_stats_tlv htt_tx_rate_stats_per_tlv; @@ -11288,10 +9150,7 @@ typedef struct { A_UINT32 mu_grp_candidate_skip_1ss [HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS] [HTT_STATS_CANDIDATE_SKIP_REASON_MAX]; -} htt_stats_pdev_ul_mumimo_grp_stats_tlv; -/* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_pdev_ul_mumimo_grp_stats_tlv - htt_stats_pdev_ulmumimo_grp_stats_tlv; +} htt_stats_pdev_ulmumimo_grp_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -11302,10 +9161,7 @@ typedef struct { A_UINT32 trig_bitmap_fail_cnt; /* Num of times peer denylisted due to trigger consecutive failure */ A_UINT32 trig_consecutive_fail_cnt; -} htt_stats_pdev_ul_mumimo_denylist_stats_tlv; -/* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_pdev_ul_mumimo_denylist_stats_tlv - htt_stats_pdev_ulmumimo_denylist_stats_tlv; +} htt_stats_pdev_ulmumimo_denylist_stats_tlv; #define HTT_STATS_SEQ_EFFICIENCY_HISTOGRAM 10 typedef struct { @@ -11319,33 +9175,7 @@ typedef struct { A_UINT32 num_terminate_seq_inefficient; /* Histogram of sequence inefficiency */ A_UINT32 hist_seq_efficiency[HTT_STATS_SEQ_EFFICIENCY_HISTOGRAM]; - /* CTS2SELF sequences posted */ - A_UINT32 num_cts2self_ulmumimo_seq_posted; - /* Number of times ULMUMIMO classification is set to high */ - A_UINT32 num_ulmumimo_high_traffic; - /* Number of times ULMUMIMO classification is set to medium */ - A_UINT32 num_ulmumimo_medium_traffic; - /* Number of times ULMUMIMO classification is set to low */ - A_UINT32 num_ulmumimo_low_traffic; - /* - * Number of times ULMUMIMO sequence is terminated - * for high traffic classification - */ - A_UINT32 num_terminate_seq_high_traffic; - /* - * Number of times ULMUMIMO sequence is terminated - * for medium traffic classification - */ - A_UINT32 num_terminate_seq_medium_traffic; - /* - * Number of times ULMUMIMO sequence is terminated - * for low traffic classification - */ - A_UINT32 num_terminate_seq_low_traffic; -} htt_stats_pdev_ul_mumimo_seq_term_stats_tlv; -/* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_pdev_ul_mumimo_seq_term_stats_tlv - htt_stats_pdev_ulmumimo_seq_term_stats_tlv; +} htt_stats_pdev_ulmumimo_seq_term_stats_tlv; #define HTT_STATS_MAX_ULMUMIMO_TRIGGERS 6 #define HTT_STATS_TXOP_HISTOGRAM_BINS 24 @@ -11373,10 +9203,7 @@ typedef struct { * Checks for 8 eligible instances of ULMUMIMO in the past 32 instances. */ A_UINT32 history_ineligibility; -} htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv; -/* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv - htt_stats_pdev_ulmumimo_hist_ineligibility_tlv; +} htt_stats_pdev_ulmumimo_hist_ineligibility_tlv; /* RTT VREG MASK */ @@ -11459,9 +9286,6 @@ typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv #define HTT_STATS_TPCCAL_POSTPROC_CHANNEL_GET(_var) \ (((_var) & HTT_STATS_TPCCAL_POSTPROC_CHANNEL_M) >> \ HTT_STATS_TPCCAL_POSTPROC_CHANNEL_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_POSTPROC_CHANNEL_GET(_var) \ - HTT_STATS_TPCCAL_POSTPROC_CHANNEL_GET(_var) #define HTT_STATS_TPCCAL_POSTPROC_CHAIN_M 0x00ff0000 #define HTT_STATS_TPCCAL_POSTPROC_CHAIN_S 16 @@ -11469,9 +9293,6 @@ typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv #define HTT_STATS_TPCCAL_POSTPROC_CHAIN_GET(_var) \ (((_var) & HTT_STATS_TPCCAL_POSTPROC_CHAIN_M) >> \ HTT_STATS_TPCCAL_POSTPROC_CHAIN_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_POSTPROC_CHAIN_GET(_var) \ - HTT_STATS_TPCCAL_POSTPROC_CHAIN_GET(_var) #define HTT_STATS_TPCCAL_POSTPROC_BAND_M 0xff000000 #define HTT_STATS_TPCCAL_POSTPROC_BAND_S 24 @@ -11479,9 +9300,6 @@ typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv #define HTT_STATS_TPCCAL_POSTPROC_BAND_GET(_var) \ (((_var) & HTT_STATS_TPCCAL_POSTPROC_BAND_M) >> \ HTT_STATS_TPCCAL_POSTPROC_BAND_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_POSTPROC_BAND_GET(_var) \ - HTT_STATS_TPCCAL_POSTPROC_BAND_GET(_var) #define HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_M 0x000000ff #define HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_S 0 @@ -11489,9 +9307,6 @@ typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv #define HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_GET(_var) \ (((_var) & HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_M) >> \ HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_POSTPROC_NUMGAIN_GET(_var) \ - HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_GET(_var) #define HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_M 0x0000ff00 #define HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_S 8 @@ -11499,9 +9314,6 @@ typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv #define HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_GET(_var) \ (((_var) & HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_M) >> \ HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_POSTPROC_CALDBSTATUS_GET(_var) \ - HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_GET(_var) /* STATS_TYPE : HTT_DBG_EXT_PDEV_STATS_FTM_TPCCAL * TLV_TAGS: @@ -11509,8 +9321,6 @@ typedef htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv */ #define HTT_MAX_TPCCAL_STATS 25 #define HTT_STATS_TPC_CAL_MAX_NUM_POINTS 64 -#define HTT_STATS_NUM_CAL_GAINS_SELECTED_4_GLUT 16 -#define HTT_STATS_NUM_CAL_GAINS_SELECTED_4_PLUT 10 typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -11643,225 +9453,8 @@ typedef struct { }; }; } tpccal_stats_postproc; - - /* cal DB timeout in ms */ - A_UINT32 calDbTimeoutMs; - - struct{ - /* tgtMeasPwr uses dBm units */ - A_INT32 tgtMeasPwr[HTT_STATS_NUM_CAL_GAINS_SELECTED_4_GLUT]; - A_UINT32 tgtPdadc[HTT_STATS_NUM_CAL_GAINS_SELECTED_4_PLUT]; - } tpcTargets; } htt_stats_pdev_ftm_tpccal_tlv; -#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_PDADC_TPCCAL_PDADC_NUMGAIN_GET(word) \ - (((word) >> 0) & 0xff) - -#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_PDADC_BAND_GET(word) \ - (((word) >> 0) & 0xff) -#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_PDADC_CHANNEL_GET(word) \ - (((word) >> 8) & 0xffff) -#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_PDADC_CHAIN_GET(word) \ - (((word) >> 24) & 0xff) - -#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_TPCCALRESULT_GAINIDX_GET(word) \ - (((word) >> 0) & 0xff) -#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_TPCCALRESULT_PDADC_GET(word) \ - (((word) >> 8) & 0xff) - -#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_STATS_TPCCALRESULT_MEASPWR_GET(word) \ - (((word) >> 0) & 0xffff) - -#define HTT_STATS_TPCCAL_PDADC_LAST_IDX_M 0x000000ff -#define HTT_STATS_TPCCAL_PDADC_LAST_IDX_S 0 - -#define HTT_STATS_TPCCAL_PDADC_LAST_IDX_GET(_var) \ - (((_var) & HTT_STATS_TPCCAL_PDADC_LAST_IDX_M) >> \ - HTT_STATS_TPCCAL_PDADC_LAST_IDX_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_LAST_IDX_GET(_var) \ - HTT_STATS_TPCCAL_PDADC_LAST_IDX_GET(_var) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_EXT_TPCCAL_PDADC_LAST_IDX_GET(_var) \ - HTT_STATS_TPCCAL_PDADC_LAST_IDX_GET(_var) - -#define HTT_STATS_TPCCAL_PDADC_NUMGAIN_M 0x000000ff -#define HTT_STATS_TPCCAL_PDADC_NUMGAIN_S 0 - -#define HTT_STATS_TPCCAL_PDADC_NUMGAIN_GET(_var) \ - (((_var) & HTT_STATS_TPCCAL_PDADC_NUMGAIN_M) >> \ - HTT_STATS_TPCCAL_PDADC_NUMGAIN_S) - -#define HTT_STATS_TPCCAL_PDADC_BAND_M 0x000000ff -#define HTT_STATS_TPCCAL_PDADC_BAND_S 0 - -#define HTT_STATS_TPCCAL_PDADC_BAND_GET(_var) \ - (((_var) & HTT_STATS_TPCCAL_PDADC_BAND_M) >> \ - HTT_STATS_TPCCAL_PDADC_BAND_S) - -#define HTT_STATS_TPCCAL_PDADC_CHANNEL_M 0x00ffff00 -#define HTT_STATS_TPCCAL_PDADC_CHANNEL_S 8 - -#define HTT_STATS_TPCCAL_PDADC_CHANNEL_GET(_var) \ - (((_var) & HTT_STATS_TPCCAL_PDADC_CHANNEL_M) >> \ - HTT_STATS_TPCCAL_PDADC_CHANNEL_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_CHANNEL_GET(_var) \ - HTT_STATS_TPCCAL_PDADC_CHANNEL_GET(_var) - -#define HTT_STATS_TPCCAL_PDADC_CHAIN_M 0xff000000 -#define HTT_STATS_TPCCAL_PDADC_CHAIN_S 24 - -#define HTT_STATS_TPCCAL_PDADC_CHAIN_GET(_var) \ - (((_var) & HTT_STATS_TPCCAL_PDADC_CHAIN_M) >> \ - HTT_STATS_TPCCAL_PDADC_CHAIN_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_CHAIN_GET(_var) \ - HTT_STATS_TPCCAL_PDADC_CHAIN_GET(_var) - -#define HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_M 0x000000ff -#define HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_S 0 - -#define HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_GET(_var) \ - (((_var) & HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_M) >> \ - HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_GAININDEX_GET(_var) \ - HTT_STATS_TPCCAL_RES_PDADC_GAINIDX_GET(_var) - -#define HTT_STATS_TPCCAL_RES_PDADC_VAL_M 0x0000ff00 -#define HTT_STATS_TPCCAL_RES_PDADC_VAL_S 8 - -#define HTT_STATS_TPCCAL_RES_PDADC_VAL_GET(_var) \ - (((_var) & HTT_STATS_TPCCAL_RES_PDADC_VAL_M) >> \ - HTT_STATS_TPCCAL_RES_PDADC_VAL_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_PDADC_GET(_var) \ - HTT_STATS_TPCCAL_RES_PDADC_VAL_GET(_var) - -#define HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_M 0x0000ffff -#define HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_S 0 - -#define HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_GET(_var) \ - (((_var) & HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_M) >> \ - HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_FTM_TPCCAL_TPCCAL_STATS_MEASPWR_GET(_var) \ - HTT_STATS_TPCCAL_RES_PDADC_MEASPWR_GET(_var) - - -#define HTT_STATS_TPC_CAL_PDADC_BUF_LEN 3 - -#define HTT_STATS_FTM_TPCCAL_CALDATA (1 << 0) -#define HTT_STATS_FTM_TPCCAL_CALINFO (1 << 1) -#define HTT_STATS_FTM_TPCCAL_CALERROR (1 << 2) - -#define HTT_STATS_FTM_TPCCAL_DONE_MASK (1 << 7) - -#define HTT_STATS_FTM_TPCCALRSP_MISCFLAGS_CALERROR_GLUTS_NOT_FILLED (1 << 16) -#define HTT_STATS_FTM_TPCCALRSP_MISCFLAGS_CALERROR_PLUT_NON_LINEAR (1 << 17) -#define HTT_STATS_FTM_TPCCALRSP_MISCFLAGS_CALERROR_ATTEMPTS_EXCEEDED (1 << 18) -#define HTT_STATS_FTM_TPCCALRSP_MISCFLAGS_CALERROR_PLUT_NOT_FILLED (1 << 19) - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - - /* - * calStatus can be intrepreted with the below values: - * TPCCAL_CALDATA (1 << 0) - * TPCCAL_CALINFO (1 << 1) - * TPCCAL_CALERROR (1 << 2) - * bits 6:4 - reserved - * TPCCAL_DONE_MASK (1 << 7) - * bits 15:8 - reserved - * TPCCALRSP_MISCFLAGS_CALERROR_GLUTS_NOT_FILLED (1 << 16) - * TPCCALRSP_MISCFLAGS_CALERROR_PLUT_NON_LINEAR (1 << 17) - * TPCCALRSP_MISCFLAGS_CALERROR_ATTEMPTS_EXCEEDED (1 << 18) - * TPCCALRSP_MISCFLAGS_CALERROR_PLUT_NOT_FILLED (1 << 19) - * bits 31:20 - reserved - */ - A_UINT32 calStatus; - - /* dword__tpccal_pdadc_last_idx: - * Hold the last updated index for pdadc buffer which holds - * band,chain,chanIdx,gainIdx for pdadc non-linearity - * BIT [7 : 0] :- tpcccal_pdadc_last_idx - * BIT [31 : 8] :- rsvd - */ - union { - A_UINT32 dword__tpccal_pdadc_last_idx; - struct { - A_UINT32 tpccal_pdadc_last_idx:8, - rsvd:24; - }; - }; - - struct { - /* dword__tpccal_pdadc_numgain: - * Hold the number of gainIdx for band for which PDADC - * non-linearity is observed - * BIT [7 : 0] :- tpccal_pdadc_numgain - * BIT [31 : 8] :- rsvd1 - */ - union { - A_UINT32 dword__tpccal_pdadc_numgain; - struct { - A_UINT32 tpccal_pdadc_numgain:8, - rsvd1:24; - }; - }; - - /* - * dword__band_channel_chain: - * band, channel, chain for which pdadc is non-linear - * BIT [7 : 0] :- band - * BIT [23 : 8] :- channel - * BIT [31 : 24] :- chain - */ - union { - A_UINT32 dword__band_channel_chain; - struct { - A_UINT32 band:8, - channel:16, - chain:8; - }; - }; - } tpccal_stats_pdadc[HTT_STATS_TPC_CAL_PDADC_BUF_LEN]; - - struct { - /* dword__calres_gainIdx_pdadc: - * holds pdadc, gainindex from tpcCalResult for - * band, channel, chain, gainIdx for which pdadc is non-linear - * dword__calres_gainIdx_pdadc - * BIT [7 : 0] :- gainIdx - * BIT [15 : 8] :- pdadc - * BIT [31 : 16] :- rsvd2 - */ - union { - A_UINT32 dword__calres_gainIdx_pdadc; - struct { - A_UINT32 gainIdx:8, - pdadc:8, - rsvd2:16; - }; - }; - - /* - * dword__measPwr: - * BIT [15 : 0] :- measPwr - * BIT [31 : 16] :- rsvd3 - */ - union { - A_INT32 dword__measPwr; - struct { - A_INT32 measPwr:16, /* dBm units */ - rsvd3:16; - }; - }; - } tpccal_stats_tpcCalResult[HTT_STATS_TPC_CAL_PDADC_BUF_LEN][HTT_STATS_TPC_CAL_MAX_NUM_POINTS]; -} htt_stats_pdev_ftm_tpccal_ext_tlv; - - #define HTT_DLPAGER_STATS_MAX_HIST 10 #define HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_M 0x000000FF #define HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_S 0 @@ -12224,9 +9817,6 @@ typedef htt_stats_phy_counters_tlv htt_phy_counters_tlv; #define HTT_STATS_ANI_MODE_GET(_var) \ (((_var) & HTT_STATS_ANI_MODE_M) >> \ HTT_STATS_ANI_MODE_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_STATS_ANI_MODE_GET(_var) \ - HTT_STATS_ANI_MODE_GET(_var) #define HTT_STATS_ANI_MODE_SET(_var, _val) \ do { \ @@ -12234,16 +9824,6 @@ typedef htt_stats_phy_counters_tlv htt_phy_counters_tlv; ((_var) |= ((_val) << HTT_STATS_ANI_MODE_S)); \ } while (0) -#define HTT_STATS_CURR_EANI_MODE_M 0x000000ff -#define HTT_STATS_CURR_EANI_MODE_S 0 - -#define HTT_STATS_CURR_EANI_MODE_GET(_var) \ - (((_var) & HTT_STATS_CURR_EANI_MODE_M) >> \ - HTT_STATS_CURR_EANI_MODE_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_STATS_CUREANIMODE_GET(_var) \ - HTT_STATS_CURR_EANI_MODE_GET(_var) - typedef struct { htt_tlv_hdr_t tlv_hdr; /** per chain hw noise floor values in dBm */ @@ -12314,36 +9894,6 @@ typedef struct { reserved: 24; }; }; - - /* dl_max_ANI: - * Maximum ANI level that would be allowable for algorithm - * to choose the desense levels and its in dB units, - * higher values indicating more noise interference/more desense. - */ - A_INT32 dl_max_ANI; - - /* Minimum RSSI of connected clients - dBm units */ - A_INT32 ani_dl_max_for_rssi; - - /* - * BIT [ 7 : 0] :- curEANIMode - * BIT [31 : 8] :- rsvd - * - * curEANIMode: - * EANI_MODE_MIN_DESENSE = 0, - * EANI_MODE_MAX_DESENSE = 1, - * EANI_MODE_DEFAULT_DESENSE = 2, - * EANI_MODE_MAX, - * EANI_MODE_TYPE_INVALID = 0xFF - */ - union { - A_UINT32 dword_curEANIMode; - struct { - A_UINT32 - curEANIMode: 8, - rsvd: 24; - }; - }; } htt_stats_phy_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv; @@ -12354,223 +9904,160 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv; #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_M) >> \ HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_CALDATA_COMPRESSED_GET(_var) \ - HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_GET(_var) #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_CAL_DATA_COMPRESSED_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_M 0x00000006 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_S 1 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_M) >> \ HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_CALDATASOURCE_GET(_var) \ - HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_GET(_var) #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_CAL_DATA_SOURCE, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_CAL_DATA_SOURCE_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_XTALCAL_M 0x00000008 #define HTT_STATS_PHY_RESET_XTALCAL_S 3 #define HTT_STATS_PHY_RESET_XTALCAL_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_XTALCAL_M) >> \ HTT_STATS_PHY_RESET_XTALCAL_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_XTALCAL_GET(_var) \ - HTT_STATS_PHY_RESET_XTALCAL_GET(_var) #define HTT_STATS_PHY_RESET_XTALCAL_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_XTALCAL, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_XTALCAL_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_XTALCAL_S)); \ } while (0) - -#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_M 0x00000010 -#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_S 4 -#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_GET(_var) \ - (((_var) & HTT_STATS_PHY_RESET_TPCCAL2GFPC_M) >> \ - HTT_STATS_PHY_RESET_TPCCAL2GFPC_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_TPCCAL2GFPC_GET(_var) \ - HTT_STATS_PHY_RESET_TPCCAL2GFPC_GET(_var) -#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GFPC, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL2GFPC_S)); \ - } while (0) - -#define HTT_STATS_PHY_RESET_TPCCAL2GOPC_M 0x00000020 -#define HTT_STATS_PHY_RESET_TPCCAL2GOPC_S 5 +#define HTT_STATS_PHY_RESET_TPCCAL2GOPC_M 0x00000010 +#define HTT_STATS_PHY_RESET_TPCCAL2GOPC_S 4 #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL2GOPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL2GOPC_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_TPCCAL2GOPC_GET(_var) \ - HTT_STATS_PHY_RESET_TPCCAL2GOPC_GET(_var) #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GOPC, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL2GOPC_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL2GOPC_S)); \ } while (0) - -#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_M 0x00000040 -#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_S 6 -#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_GET(_var) \ - (((_var) & HTT_STATS_PHY_RESET_TPCCAL5GFPC_M) >> \ - HTT_STATS_PHY_RESET_TPCCAL5GFPC_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_TPCCAL5GFPC_GET(_var) \ - HTT_STATS_PHY_RESET_TPCCAL5GFPC_GET(_var) -#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_SET(_var, _val) \ +#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_M 0x00000020 +#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_S 5 +#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_GET(_var) \ + (((_var) & HTT_STATS_PHY_RESET_TPCCAL2GFPC_M) >> \ + HTT_STATS_PHY_RESET_TPCCAL2GFPC_S) +#define HTT_STATS_PHY_RESET_TPCCAL2GFPC_SET(_var, _val) \ do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GFPC, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL5GFPC_S)); \ + HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GFPC, _val); \ + ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL2GFPC_S)); \ } while (0) - -#define HTT_STATS_PHY_RESET_TPCCAL5GOPC_M 0x00000080 -#define HTT_STATS_PHY_RESET_TPCCAL5GOPC_S 7 +#define HTT_STATS_PHY_RESET_TPCCAL5GOPC_M 0x00000040 +#define HTT_STATS_PHY_RESET_TPCCAL5GOPC_S 6 #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL5GOPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL5GOPC_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_TPCCAL5GOPC_GET(_var) \ - HTT_STATS_PHY_RESET_TPCCAL5GOPC_GET(_var) #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GOPC, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL5GOPC_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL5GOPC_S)); \ } while (0) - -#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_M 0x00000100 -#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_S 8 -#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_GET(_var) \ - (((_var) & HTT_STATS_PHY_RESET_TPCCAL6GFPC_M) >> \ - HTT_STATS_PHY_RESET_TPCCAL6GFPC_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_TPCCAL6GFPC_GET(_var) \ - HTT_STATS_PHY_RESET_TPCCAL6GFPC_GET(_var) -#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_SET(_var, _val) \ +#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_M 0x00000080 +#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_S 7 +#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_GET(_var) \ + (((_var) & HTT_STATS_PHY_RESET_TPCCAL5GFPC_M) >> \ + HTT_STATS_PHY_RESET_TPCCAL5GFPC_S) +#define HTT_STATS_PHY_RESET_TPCCAL5GFPC_SET(_var, _val) \ do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GFPC, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL6GFPC_S)); \ + HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GFPC, _val); \ + ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL5GFPC_S)); \ } while (0) - -#define HTT_STATS_PHY_RESET_TPCCAL6GOPC_M 0x00000200 -#define HTT_STATS_PHY_RESET_TPCCAL6GOPC_S 9 +#define HTT_STATS_PHY_RESET_TPCCAL6GOPC_M 0x00000100 +#define HTT_STATS_PHY_RESET_TPCCAL6GOPC_S 8 #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL6GOPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL6GOPC_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_TPCCAL6GOPC_GET(_var) \ - HTT_STATS_PHY_RESET_TPCCAL6GOPC_GET(_var) #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GOPC, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_TPCCAL6GOPC_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL6GOPC_S)); \ + } while (0) +#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_M 0x00000200 +#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_S 9 +#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_GET(_var) \ + (((_var) & HTT_STATS_PHY_RESET_TPCCAL6GFPC_M) >> \ + HTT_STATS_PHY_RESET_TPCCAL6GFPC_S) +#define HTT_STATS_PHY_RESET_TPCCAL6GFPC_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GFPC, _val); \ + ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL6GFPC_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_RXGAINCAL2G_M 0x00000400 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_S 10 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL2G_M) >> \ HTT_STATS_PHY_RESET_RXGAINCAL2G_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_RXGAINCAL2G_GET(_var) \ - HTT_STATS_PHY_RESET_RXGAINCAL2G_GET(_var) #define HTT_STATS_PHY_RESET_RXGAINCAL2G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL2G, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_RXGAINCAL2G_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL2G_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_RXGAINCAL5G_M 0x00000800 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_S 11 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL5G_M) >> \ HTT_STATS_PHY_RESET_RXGAINCAL5G_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_RXGAINCAL5G_GET(_var) \ - HTT_STATS_PHY_RESET_RXGAINCAL5G_GET(_var) #define HTT_STATS_PHY_RESET_RXGAINCAL5G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL5G, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_RXGAINCAL5G_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL5G_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_RXGAINCAL6G_M 0x00001000 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_S 12 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL6G_M) >> \ HTT_STATS_PHY_RESET_RXGAINCAL6G_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_RXGAINCAL6G_GET(_var) \ - HTT_STATS_PHY_RESET_RXGAINCAL6G_GET(_var) #define HTT_STATS_PHY_RESET_RXGAINCAL6G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL6G, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_RXGAINCAL6G_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL6G_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_AOACAL2G_M 0x00002000 #define HTT_STATS_PHY_RESET_AOACAL2G_S 13 #define HTT_STATS_PHY_RESET_AOACAL2G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_AOACAL2G_M) >> \ HTT_STATS_PHY_RESET_AOACAL2G_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_AOACAL2G_GET(_var) \ - HTT_STATS_PHY_RESET_AOACAL2G_GET(_var) #define HTT_STATS_PHY_RESET_AOACAL2G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL2G, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_AOACAL2G_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL2G_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_AOACAL5G_M 0x00004000 #define HTT_STATS_PHY_RESET_AOACAL5G_S 14 #define HTT_STATS_PHY_RESET_AOACAL5G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_AOACAL5G_M) >> \ HTT_STATS_PHY_RESET_AOACAL5G_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_AOACAL5G_GET(_var) \ - HTT_STATS_PHY_RESET_AOACAL5G_GET(_var) #define HTT_STATS_PHY_RESET_AOACAL5G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL5G, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_AOACAL5G_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL5G_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_AOACAL6G_M 0x00008000 #define HTT_STATS_PHY_RESET_AOACAL6G_S 15 #define HTT_STATS_PHY_RESET_AOACAL6G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_AOACAL6G_M) >> \ HTT_STATS_PHY_RESET_AOACAL6G_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_AOACAL6G_GET(_var) \ - HTT_STATS_PHY_RESET_AOACAL6G_GET(_var) #define HTT_STATS_PHY_RESET_AOACAL6G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL6G, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_AOACAL6G_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL6G_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_M 0x00010000 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_S 16 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_XTAL_FROM_OTP_M) >> \ HTT_STATS_PHY_RESET_XTAL_FROM_OTP_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_XTAL_FROM_OTP_GET(_var) \ - HTT_STATS_PHY_RESET_XTAL_FROM_OTP_GET(_var) #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_XTAL_FROM_OTP, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_XTAL_FROM_OTP_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_XTAL_FROM_OTP_S)); \ } while (0) #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_M 0x000000FF @@ -12578,41 +10065,30 @@ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv; #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_GLUT_LINEARITY_M) >> \ HTT_STATS_PHY_RESET_GLUT_LINEARITY_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_GLUT_LINEARITY_GET(_var) \ - HTT_STATS_PHY_RESET_GLUT_LINEARITY_GET(_var) #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_GLUT_LINEARITY, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_GLUT_LINEARITY_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_GLUT_LINEARITY_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_M 0x0000FF00 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_S 8 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_PLUT_LINEARITY_M) >> \ HTT_STATS_PHY_RESET_PLUT_LINEARITY_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_PLUT_LINEARITY_GET(_var) \ - HTT_STATS_PHY_RESET_PLUT_LINEARITY_GET(_var) #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_PLUT_LINEARITY, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_PLUT_LINEARITY_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_PLUT_LINEARITY_S)); \ } while (0) - #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_M 0x00FF0000 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_S 16 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_WLANDRIVERMODE_M) >> \ HTT_STATS_PHY_RESET_WLANDRIVERMODE_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_RESET_STATS_WLANDRIVERMODE_GET(_var) \ - HTT_STATS_PHY_RESET_WLANDRIVERMODE_GET(_var) #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_WLANDRIVERMODE, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_RESET_WLANDRIVERMODE_S)); \ + ((_var) |= ((_val) << STATS_PHY_RESET_WLANDRIVERMODE_S)); \ } while (0) @@ -12959,11 +10435,6 @@ typedef struct { * tx_power_neg[9]: cnt of PPDUs with tx pwr < -9 dBm */ A_UINT32 tx_power_neg[HTT_MAX_NEGATIVE_POWER_LEVEL]; - /* - * Tx Power computed for TPC IE for Beacon and related frames, - * in 0.25 dBm units - */ - A_UINT32 tpc_ie_power; } htt_stats_phy_tpc_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_phy_tpc_stats_tlv htt_phy_tpc_stats_tlv; @@ -12993,856 +10464,6 @@ typedef struct { } htt_vdevs_txrx_stats_t; #endif /* ATH_TARGET */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** The channel number on which these stats were collected */ - A_UINT32 chan_num; - /** num of records provided */ - A_UINT32 num_records; - /** Indicates the stats collection interval - * Valid Values: - * 100 - For the 100 ms interval stats histogram - * 1000 - For 1 sec interval histogram - */ - A_UINT32 collection_interval; - /** ani_hist_type: - * single flag to differentiate histogram type - * Valid Values: - * 0 - (default) For 1 sec interval histogram - * 1 - For granular (100 ms) interval histogram - * 2 - 1 sec histogram not enabled - * 3 - Granular histogram not enabled - */ - A_UINT32 ani_hist_type; -} htt_stats_pdev_ani_hist_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 rx_ofdma_timing_err_cnt; - A_UINT32 rx_cck_fail_cnt; - A_UINT32 rx_cck1_fail_cnt; - A_UINT32 rx_cck2_fail_cnt; - A_UINT32 rx_cck7_fail_cnt; - A_UINT32 mactx_abort_cnt; - A_UINT32 macrx_abort_cnt; - A_UINT32 phytx_abort_cnt; - A_UINT32 phyrx_abort_cnt; - A_UINT32 phyrx_defer_abort_cnt; - A_UINT32 rx_sizing1_event_cnt; /* a.k.a sizing1 */ - A_UINT32 rx_sizing2_event_cnt; /* a.k.a sizing2 */ -} htt_stats_ani_scalar_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* rx_pkt_cnt - - * Received EOP (end-of-packet) count per packet type; - * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; - * [5] = GF; [6] = EHT; [7] = WUR; [8] = AZ - */ - A_UINT32 rx_pkt_cnt[9]; -} htt_stats_ani_pkt_cnt_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* rx_pkt_crc_pass_cnt - - * CRC pass count per packet type; - * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; - * [5] = GF; [6] = EHT; [7] = WUR; [8] = AZ - */ - A_UINT32 rx_pkt_crc_pass_cnt[9]; -} htt_stats_ani_crc_pass_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* per_blk_err_cnt - - * Error count per error source; - * [0] = unknown; [1] = LSIG; [2] = HTSIG; [3] = VHTSIG; [4] = HESIG; - * [5] = RXTD_OTA; [6] = RXTD_FATAL; [7] = DEMF; [8] = ROBE; - * [9] = PMI; [10] = TXFD; [11] = TXTD; [12] = PHYRF - * [13-15]=RSVD - */ - A_UINT32 per_blk_err_cnt[16]; -} htt_stats_ani_per_blk_err_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* rx_ota_err_cnt - - * RXTD OTA (over-the-air) error count per error reason; - * [0] = voting fail; [1] = weak det fail; [2] = strong sig fail; - * [3] = cck fail; [4] = power surge; - * [5] = btcf timing timeout error; [6] = btcf packet detect error; - * [7] = coarse timing timeout error - * [8-9]=RSVD - */ - A_UINT32 rx_ota_err_cnt[10]; -} htt_stats_ani_ota_err_tlv; - - -/* PAPRD and power boost stats and counters */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - - /** current pdev_id */ - A_UINT32 pdev_id; - /** DPD and PowerBoost trigger count */ - A_UINT32 total_dpd_cal_count; - A_UINT32 chan_change_dpd_cal_count; - A_UINT32 thermal_dpd_cal_count; - A_UINT32 recovery_dpd_cal_count; - A_UINT32 pb_cal_count; - /** DPD and PowerBoost Fail Count */ - A_UINT32 total_dpd_fail_count; - A_UINT32 chan_change_dpd_fail_count; - A_UINT32 thermal_dpd_fail_count; - A_UINT32 recovery_dpd_fail_count; - A_UINT32 pb_fail_count; - - /* - * DPD and Power Boost validity status - * - * BIT 0 - DPD_CAL_STATUS - * BIT 1 - PB_CAL_STATUS - * - * CAL_STATUS can be interpreted as below - * CAL_SUCCESS = 1 - * CAL_FAIL = 0 - */ - union { - A_UINT32 dpd_pb_validity_status; - struct { - A_UINT32 is_dpd_valid:1, - is_pb_valid:1, - rsvd:30; - }; - }; - - /** Last DPD cal time in ms */ - A_UINT32 last_dpd_cal_time; - - /** Last Power Boost cal time in ms */ - A_UINT32 last_pb_cal_time; - - /** Power Boost gain per BW and MCS, in 0.25 dB units - * For example, a value of 2 represents a 0.5 dB gain. - */ - A_UINT32 power_boost_gain[HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS][HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; -} htt_stats_phy_paprd_pb_tlv; - -#define HTT_STATS_PHY_PAPRD_PB_IS_DPD_VALID_GET(word) \ - (((word) >> 0) & 0x1) - -#define HTT_STATS_PHY_PAPRD_PB_IS_PB_VALID_GET(word) \ - (((word) >> 1) & 0x1) - -#define HTT_STATS_HDS_PROF_STATS_CIRCULAR_BUF_LEN 10 - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - struct { - union { - A_UINT32 channel_info; - struct { - A_UINT32 bandwidth_mhz:16, - band_center_freq1:16; /* MHz units */ - }; - }; - - union { - A_UINT32 channel_config; - struct { - A_UINT32 phyMode:8, /* phyMode - WLAN_PHY_MODE enum type */ - txChainmask:8, - rxChainmask:8, - swProfile:8; - }; - }; - - A_UINT32 channelSwitchTime; - A_UINT32 calModuleTime; - A_UINT32 iniModuleTime; - A_UINT32 tpcModuleTime; - A_UINT32 miscModuleTime; - A_UINT32 ctlModuleTime; - A_UINT32 reserved; - } channelChange_stats[HTT_STATS_HDS_PROF_STATS_CIRCULAR_BUF_LEN]; - - A_UINT32 idx; /* shows how many channel changes have occurred */ -} htt_stats_hds_prof_stats_tlv; - -#define HTT_STATS_HDS_PROF_BANDWIDTH_MHZ_GET(word) \ - ((word) & 0x0000ffff) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_BANDWIDTH_MHZ_GET(word) \ - HTT_STATS_HDS_PROF_BANDWIDTH_MHZ_GET(word) -#define HTT_STATS_HDS_PROF_BANDWIDTH_MHZ_SET(word, value) \ - ((word) |= ((value) & 0x0000ffff)) - -#define HTT_STATS_HDS_PROF_BAND_CENTER_FREQ1_GET(word) \ - (((word) & 0xffff0000) >> 16) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_BAND_CENTER_FREQ1_GET(word) \ - HTT_STATS_HDS_PROF_BAND_CENTER_FREQ1_GET(word) -#define HTT_STATS_HDS_PROF_BAND_CENTER_FREQ1_SET(word, value) \ - ((word) |= (((value) << 16) & 0xffff0000)) - -#define HTT_STATS_HDS_PROF_PHY_MODE_GET(word) \ - (((word) & 0x000000ff) >> 0) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_PHYMODE_GET(word) \ - HTT_STATS_HDS_PROF_PHY_MODE_GET(word) -#define HTT_STATS_HDS_PROF_PHY_MODE_SET(word, value) \ - ((word) |= (((value) << 0) & 0x000000ff)) - -#define HTT_STATS_HDS_PROF_TX_CHAINMASK_GET(word) \ - (((word) & 0x0000ff00) >> 8) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_TXCHAINMASK_GET(word) \ - HTT_STATS_HDS_PROF_TX_CHAINMASK_GET(word) -#define HTT_STATS_HDS_PROF_TX_CHAINMASK_SET(word, value) \ - ((word) |= (((value) << 8) & 0x0000ff00)) - -#define HTT_STATS_HDS_PROF_RX_CHAINMASK_GET(word) \ - (((word) & 0x00ff0000) >> 16) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_RXCHAINMASK_GET(word) \ - HTT_STATS_HDS_PROF_RX_CHAINMASK_GET(word) -#define HTT_STATS_HDS_PROF_RX_CHAINMASK_SET(word, value) \ - ((word) |= (((value) << 16) & 0x00ff0000)) - -#define HTT_STATS_HDS_PROF_SW_PROFILE_GET(word) \ - (((word) & 0xff000000) >> 24) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_HDS_PROF_STATS_CHANNELCHANGE_STATS_SWPROFILE_GET(word) \ - HTT_STATS_HDS_PROF_SW_PROFILE_GET(word) -#define HTT_STATS_HDS_PROF_SW_PROFILE_SET(word, value) \ - ((word) |= (((value) << 24) & 0xff000000)) - - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - A_UINT32 flags; - struct { - /* - * bit 0: Dynamic ED CCA status flag - * bit 1: LPI status flag - * bit 2: Green Tx status flag - * bit 3: ANI status flag - * bit 4: Static ANI status flag - * bit 5: ANN Powerboost status flag - * bit 6: EANI status flag - * bit 7: Spur Mitigation status flag - * bit 8: Multigain RSSI status flag - */ - A_UINT32 - is_dyn_cca_enabled: 1, /* bit 0 */ - is_lpi_enabled: 1, /* bit 1 */ - is_gtx_enabled: 1, /* bit 2 */ - is_ani_enabled: 1, /* bit 3 */ - is_static_ani_enabled: 1, /* bit 4 */ - is_ann_pbt_enabled: 1, /* bit 5 */ - is_e_ani_enabled: 1, /* bit 6 */ - is_spur_mit_enabled: 1, /* bit 7 */ - is_multigain_rssi_enabled: 1, /* bit 8 */ - is_olpc_clpc: 1, /* bit 9 */ - is_abi_en_dis: 1, /* bit 10 */ - is_str_sig_rec: 1, /* bit 11 */ - is_verbose_enabled: 1, /* bit 12 */ - is_dyn_ant_sel_supported: 1, /* bit 13 */ - is_dfs_punc_enabled: 1, /* bit 14 */ - dpd_pow_bo_status: 1, /* bit 15 */ - is_eeprom_compressed: 1, /* bit 16 */ - reserved: 15; /* bits 31:17 */ - }; - }; - - union { - A_UINT32 rxsop_config; - struct { - A_UINT32 - is_rxsop_enabled: 1, /* bit 0 */ - rxsop_config_value: 8, /* bit 8:1 */ - rxsop_reserved: 23; /* bits 31:9 */ - }; - }; - - A_UINT32 abi_max_rg_gain; /* dB units */ - A_UINT32 abi_max_lg_gain; /* dB units */ - A_UINT32 abi_max_vlg_gain; /* dB units */ - /* abi_hold_mode: - * Controls how long gain table decisions are held: - * 0: Cleared each packet - * 1: Held for timer value - * 2: Gain table choices are under CSR control - */ - A_UINT32 abi_hold_mode; - A_UINT32 abi_hold_count; - A_INT32 rssi_temp_offset; /* dB units */ - A_INT32 rssi_xlna_bypass_offset; /* dB units */ - A_INT32 rssi_cbw_offset; /* dB units */ - A_INT32 rssi_chan_freq_offset; /* dB units */ - A_UINT32 otp_version; - A_UINT32 cfr_clip_factor[4]; - union { - A_UINT32 hc__premcs__pkt_type__word32; - struct { - A_UINT32 - hc_premcs: 16, /* bits 15:0 */ - hc_pkt_type: 16; /* bits 31:16 */ - }; - }; - union { - A_UINT32 hc_nss_thr__is_rx_gain_forced__rx_gain_forced_val__word32; - struct { - A_UINT32 - hc_nss_thr: 8, /* bits 7:0 */ - is_rx_gain_forced: 8, /* bits 15:8 */ - rx_gain_forced_val: 8, /* bits 23:16 */ - reserved2: 8; /* bits 31:24 */ - }; - }; -} htt_stats_optional_configs_tlv; - -#define HTT_STATS_OPT_CONF_GET_DYN_CCA(word) \ - (((word) & 0x1) >> 0) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_DYN_CCA_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_DYN_CCA(word) -#define HTT_STATS_OPT_CONF_SET_DYN_CCA(word, value) \ - ((word) = ((word) & ~0x1) | (((value) & 0x1) << 0)) - -#define HTT_STATS_OPT_CONF_GET_LPI(word) \ - (((word) & 0x2) >> 1) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_LPI_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_LPI(word) -#define HTT_STATS_OPT_CONF_SET_LPI(word, value) \ - ((word) = ((word) & ~0x2) | (((value) & 0x1) << 1)) - -#define HTT_STATS_OPT_CONF_GET_GTX(word) \ - (((word) & 0x4) >> 2) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_GTX_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_GTX(word) -#define HTT_STATS_OPT_CONF_SET_GTX(word, value) \ - ((word) = ((word) & ~0x4) | (((value) & 0x1) << 2)) - -#define HTT_STATS_OPT_CONF_GET_ANI(word) \ - (((word) & 0x8) >> 3) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_ANI_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_ANI(word) -#define HTT_STATS_OPT_CONF_SET_ANI(word, value) \ - ((word) = ((word) & ~0x8) | (((value) & 0x1) << 3)) - -#define HTT_STATS_OPT_CONF_GET_STATIC_ANI(word) \ - (((word) & 0x10) >> 4) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_STATIC_ANI_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_STATIC_ANI(word) -#define HTT_STATS_OPT_CONF_SET_STATIC_ANI(word, value) \ - ((word) = ((word) & ~0x10) | (((value) & 0x1) << 4)) - -#define HTT_STATS_OPT_CONF_GET_ANN_PBT(word) \ - (((word) & 0x20) >> 5) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_ANN_PBT_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_ANN_PBT(word) -#define HTT_STATS_OPT_CONF_SET_ANN_PBT(word, value) \ - ((word) = ((word) & ~0x20) | (((value) & 0x1) << 5)) - -#define HTT_STATS_OPT_CONF_GET_EANI(word) \ - (((word) & 0x40) >> 6) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_E_ANI_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_EANI(word) -#define HTT_STATS_OPT_CONF_SET_EANI(word, value) \ - ((word) = ((word) & ~0x40) | (((value) & 0x1) << 6)) - -#define HTT_STATS_OPT_CONF_GET_SPUR_MIT(word) \ - (((word) & 0x80) >> 7) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_SPUR_MIT_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_SPUR_MIT(word) -#define HTT_STATS_OPT_CONF_SET_SPUR_MIT(word, value) \ - ((word) = ((word) & ~0x80) | (((value) & 0x1) << 7)) - -#define HTT_STATS_OPT_CONF_GET_MULTIGAIN_RSSI(word) \ - (((word) & 0x100) >> 8) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_MULTIGAIN_RSSI_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_MULTIGAIN_RSSI(word) -#define HTT_STATS_OPT_CONF_SET_MULTIGAIN_RSSI(word, value) \ - ((word) = ((word) & ~0x100) | (((value) & 0x1) << 8)) - -#define HTT_STATS_OPT_CONF_GET_OLPC_CLPC(word) \ - (((word) & 0x200) >> 9) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_OLPC_CLPC_GET(word) \ - HTT_STATS_OPT_CONF_GET_OLPC_CLPC(word) -#define HTT_STATS_OPT_CONF_SET_OLPC_CLPC(word, value) \ - ((word) = ((word) & ~0x200) | (((value) & 0x1) << 9)) - -#define HTT_STATS_OPT_CONF_GET_ABI_EN_DIS(word) \ - (((word) & 0x400) >> 10) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_ABI_EN_DIS_GET(word) \ - HTT_STATS_OPT_CONF_GET_ABI_EN_DIS(word) -#define HTT_STATS_OPT_CONF_SET_ABI_EN_DIS(word, value) \ - ((word) = ((word) & ~0x400) | (((value) & 0x1) << 10)) - -#define HTT_STATS_OPT_CONF_GET_STR_SIG_REC(word) \ - (((word) & 0x800) >> 11) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_STR_SIG_REC_GET(word) \ - HTT_STATS_OPT_CONF_GET_STR_SIG_REC(word) -#define HTT_STATS_OPT_CONF_SET_STR_SIG_REC(word, value) \ - ((word) = ((word) & ~0x800) | (((value) & 0x1) << 11)) - -#define HTT_STATS_OPT_CONF_GET_VERBOSE(word) \ - (((word) & 0x1000) >> 12) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_VERBOSE_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_VERBOSE(word) -#define HTT_STATS_OPT_CONF_SET_VERBOSE(word, value) \ - ((word) = ((word) & ~0x1000) | (((value) & 0x1) << 12)) - -#define HTT_STATS_OPT_CONF_GET_DYN_ANT_SEL(word) \ - (((word) & 0x2000) >> 13) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_DYN_ANT_SEL_SUPPORTED_GET(word) \ - HTT_STATS_OPT_CONF_GET_DYN_ANT_SEL(word) -#define HTT_STATS_OPT_CONF_SET_DYN_ANT_SEL(word, value) \ - ((word) = ((word) & ~0x2000) | (((value) & 0x1) << 13)) - -#define HTT_STATS_OPT_CONF_GET_DFS_PUNC(word) \ - (((word) & 0x4000) >> 14) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_DFS_PUNC_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_DFS_PUNC(word) -#define HTT_STATS_OPT_CONF_SET_DFS_PUNC(word, value) \ - ((word) = ((word) & ~0x4000) | (((value) & 0x1) << 14)) - -#define HTT_STATS_OPT_CONF_GET_DPD_POW_BO(word) \ - (((word) & 0x8000) >> 15) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_DPD_POW_BO_STATUS_GET(word) \ - HTT_STATS_OPT_CONF_GET_DPD_POW_BO(word) -#define HTT_STATS_OPT_CONF_SET_DPD_POW_BO(word, value) \ - ((word) = ((word) & ~0x8000) | (((value) & 0x1) << 15)) - -#define HTT_STATS_OPT_CONF_GET_EEPROM_COMPRESSED(word) \ - (((word) & 0x10000) >> 16) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_EEPROM_COMPRESSED_GET(word) \ - HTT_STATS_OPT_CONF_GET_EEPROM_COMPRESSED(word) -#define HTT_STATS_OPT_CONF_SET_EEPROM_COMPRESSED(word, value) \ - ((word) = ((word) & ~0x10000) | (((value) & 0x1) << 16)) - - -#define HTT_STATS_OPT_CONF_GET_RXSOP_ENABLED(word) \ - (((word) & 0x1) >> 0) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_RXSOP_ENABLED_GET(word) \ - HTT_STATS_OPT_CONF_GET_RXSOP_ENABLED(word) -#define HTT_STATS_OPT_CONF_SET_RXSOP_ENABLED(word, value) \ - ((word) = ((word) & ~0x1) | (((value) & 0x1) << 0)) - -#define HTT_STATS_OPT_CONF_GET_RXSOP_CONFIG_VALUE(word) \ - (((word) & 0x1FE) >> 1) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_RXSOP_CONFIG_VALUE_GET(word) \ - HTT_STATS_OPT_CONF_GET_RXSOP_CONFIG_VALUE(word) -#define HTT_STATS_OPT_CONF_SET_RXSOP_CONFIG_VALUE(word, value) \ - ((word) = ((word) & ~0x1FE) | (((value) & 0xFF) << 1)) - -#define HTT_STATS_OPT_CONF_GET_HC_PREMCS(word) \ - ((word) & 0xFFFF) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_HC_PREMCS_GET(word) \ - HTT_STATS_OPT_CONF_GET_HC_PREMCS(word) -#define HTT_STATS_OPT_CONF_SET_HC_PREMCS(word, value) \ - ((word) = ((value) & 0xFFFF)) - -#define HTT_STATS_OPT_CONF_GET_HC_PKT_TYPE(word) \ - (((word) & 0xFFFF0000) >> 16) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_HC_PKT_TYPE_GET(word) \ - HTT_STATS_OPT_CONF_GET_HC_PKT_TYPE(word) -#define HTT_STATS_OPT_CONF_SET_HC_PKT_TYPE(word, value) \ - ((word) = ((word) & ~0xFFFF0000) | (((value) & 0xFFFF) << 16)) - -#define HTT_STATS_OPT_CONF_GET_HC_NSS_THR(word) \ - (((word) & 0x000000FF) >> 0) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_HC_NSS_THR_GET(word) \ - HTT_STATS_OPT_CONF_GET_HC_NSS_THR(word) -#define HTT_STATS_OPT_CONF_SET_HC_NSS_THR(word, value) \ - ((word) = ((word) & ~0x000000FF) | (((value) & 0xFF) << 0)) - -#define HTT_STATS_OPT_CONF_GET_IS_RX_GAIN_FORCED(word) \ - (((word) & 0x0000FF00) >> 8) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_IS_RX_GAIN_FORCED_GET(word) \ - HTT_STATS_OPT_CONF_GET_IS_RX_GAIN_FORCED(word) -#define HTT_STATS_OPT_CONF_SET_IS_RX_GAIN_FORCED(word, value) \ - ((word) = ((word) & ~0x0000FF00) | (((value) & 0xFF) << 8)) - -#define HTT_STATS_OPT_CONF_GET_RX_GAIN_FORCED_VAL(word) \ - (((word) & 0x00FF0000) >> 16) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_OPTIONAL_CONFIGS_RX_GAIN_FORCED_VAL_GET(word) \ - HTT_STATS_OPT_CONF_GET_RX_GAIN_FORCED_VAL(word) -#define HTT_STATS_OPT_CONF_SET_RX_GAIN_FORCED_VAL(word, value) \ - ((word) = ((word) & ~0x00FF0000) | (((value) & 0xFF) << 16)) - - -/* FTM STATS */ -/* ================= dword_txparams ================= */ -#define HTT_STATS_XTAL_GAIN_IDX_M 0x000000FF -#define HTT_STATS_XTAL_GAIN_IDX_S 0 -#define HTT_STATS_GET_XTAL_GAIN_IDX(word) \ - (((word) & HTT_STATS_XTAL_GAIN_IDX_M) >> HTT_STATS_XTAL_GAIN_IDX_S) - -#define HTT_STATS_INFINITE_BURST_MODE_M 0x0000FF00 -#define HTT_STATS_INFINITE_BURST_MODE_S 8 -#define HTT_STATS_GET_INFINITE_BURST_MODE(word) \ - (((word) & HTT_STATS_INFINITE_BURST_MODE_M) >> HTT_STATS_INFINITE_BURST_MODE_S) - -#define HTT_STATS_FTM_MODE_M 0x00FF0000 -#define HTT_STATS_FTM_MODE_S 16 -#define HTT_STATS_GET_FTM_MODE(word) \ - (((word) & HTT_STATS_FTM_MODE_M) >> HTT_STATS_FTM_MODE_S) - -#define HTT_STATS_SIFS_US_M 0xFF000000 -#define HTT_STATS_SIFS_US_S 24 -#define HTT_STATS_GET_SIFS_US(word) \ - (((word) & HTT_STATS_SIFS_US_M) >> HTT_STATS_SIFS_US_S) - -/* ================= dword_txparams_ext_1 ================= */ -#define HTT_STATS_AGG_STATUS_M 0x00000001 -#define HTT_STATS_AGG_STATUS_S 0 -#define HTT_STATS_GET_AGG_STATUS(word) \ - (((word) & HTT_STATS_AGG_STATUS_M) >> HTT_STATS_AGG_STATUS_S) - -#define HTT_STATS_DPD_FLAG_M 0x00000002 -#define HTT_STATS_DPD_FLAG_S 1 -#define HTT_STATS_GET_DPD_FLAG(word) \ - (((word) & HTT_STATS_DPD_FLAG_M) >> HTT_STATS_DPD_FLAG_S) - -/* Bits [9:2] -> 8-bit field */ -#define HTT_STATS_PPDU_DUR_LAST_IDX_M 0x000003FC -#define HTT_STATS_PPDU_DUR_LAST_IDX_S 2 -#define HTT_STATS_GET_PPDU_DUR_LAST_IDX(word) \ - (((word) & HTT_STATS_PPDU_DUR_LAST_IDX_M) >> HTT_STATS_PPDU_DUR_LAST_IDX_S) - -/* ================= dword_txparams_ext_2 ================= */ -#define HTT_STATS_TARGET_TX_DUTY_M 0x000000FF -#define HTT_STATS_TARGET_TX_DUTY_S 0 -#define HTT_STATS_GET_TARGET_TX_DUTY(word) \ - (((word) & HTT_STATS_TARGET_TX_DUTY_M) >> HTT_STATS_TARGET_TX_DUTY_S) - -#define HTT_STATS_PPDU_TYPE_M 0x0000FF00 -#define HTT_STATS_PPDU_TYPE_S 8 -#define HTT_STATS_GET_PPDU_TYPE(word) \ - (((word) & HTT_STATS_PPDU_TYPE_M) >> HTT_STATS_PPDU_TYPE_S) - -#define HTT_STATS_NUM_USERS_OFDMA_M 0x00FF0000 -#define HTT_STATS_NUM_USERS_OFDMA_S 16 -#define HTT_STATS_GET_NUM_USERS_OFDMA(word) \ - (((word) & HTT_STATS_NUM_USERS_OFDMA_M) >> HTT_STATS_NUM_USERS_OFDMA_S) - -#define HTT_STATS_NUM_USERS_OFDMA_EHT_M 0xFF000000 -#define HTT_STATS_NUM_USERS_OFDMA_EHT_S 24 -#define HTT_STATS_GET_NUM_USERS_OFDMA_EHT(word) \ - (((word) & HTT_STATS_NUM_USERS_OFDMA_EHT_M) >> HTT_STATS_NUM_USERS_OFDMA_EHT_S) - -/* ================= dword_TimingStats ================= */ -#define HTT_STATS_TLV_TIMESTAMP_CNT_M 0x000000FF -#define HTT_STATS_TLV_TIMESTAMP_CNT_S 0 -#define HTT_STATS_GET_TLV_TIMESTAMP_CNT(word) \ - (((word) & HTT_STATS_TLV_TIMESTAMP_CNT_M) >> HTT_STATS_TLV_TIMESTAMP_CNT_S) - -/* ================= dword_TlvcmdInfo ================= */ -#define HTT_STATS_TLV_CMD_ENTRY_M 0x0000FFFF -#define HTT_STATS_TLV_CMD_ENTRY_S 0 -#define HTT_STATS_GET_TLV_CMD_ENTRY(word) \ - (((word) & HTT_STATS_TLV_CMD_ENTRY_M) >> HTT_STATS_TLV_CMD_ENTRY_S) - -#define HTT_STATS_TLV_CAL_TYPE_M 0x00FF0000 -#define HTT_STATS_TLV_CAL_TYPE_S 16 -#define HTT_STATS_GET_TLV_CAL_TYPE(word) \ - (((word) & HTT_STATS_TLV_CAL_TYPE_M) >> HTT_STATS_TLV_CAL_TYPE_S) - -/* ================= dword_TlvCmdParsing ================= */ -#define HTT_STATS_FLAG_TLV_CMD_PARSING_M 0x00000001 -#define HTT_STATS_FLAG_TLV_CMD_PARSING_S 0 -#define HTT_STATS_GET_FLAG_TLV_CMD_PARSING(word) \ - (((word) & HTT_STATS_FLAG_TLV_CMD_PARSING_M) >> HTT_STATS_FLAG_TLV_CMD_PARSING_S) - -#define HTT_STATS_NUM_TLV_CMD_DROPPED_M 0x000001FE -#define HTT_STATS_NUM_TLV_CMD_DROPPED_S 1 -#define HTT_STATS_GET_NUM_TLV_CMD_DROPPED(word) \ - (((word) & HTT_STATS_NUM_TLV_CMD_DROPPED_M) >> HTT_STATS_NUM_TLV_CMD_DROPPED_S) - -/* ================= dword_rxGaincalMaxNumchan ================= */ -#define HTT_STATS_RXGAINCAL_MAX_NUMCHAN_M 0x000000FF -#define HTT_STATS_RXGAINCAL_MAX_NUMCHAN_S 0 -#define HTT_STATS_GET_RXGAINCAL_MAX_NUMCHAN(word) \ - (((word) & HTT_STATS_RXGAINCAL_MAX_NUMCHAN_M) >> HTT_STATS_RXGAINCAL_MAX_NUMCHAN_S) - -/* ================= dword_rxgainCalRefISS ================= */ -#define HTT_STATS_RXGAINCAL_REF_ISS_M 0x000000FF -#define HTT_STATS_RXGAINCAL_REF_ISS_S 0 -#define HTT_STATS_GET_RXGAINCAL_REF_ISS(word) \ - (((word) & HTT_STATS_RXGAINCAL_REF_ISS_M) >> HTT_STATS_RXGAINCAL_REF_ISS_S) - - -#define HTT_STATS_FTM_TIMESTAMP_TOTAL_CNT 50 -#define HTT_STATS_FTM_PPDU_DUR_CIRCULAR_BUF_CNT 10 -#define HTT_STATS_FTM_RXGAINCAL_MAX_NUM_CHAN_TLV2 16 -#define HTT_STATS_FTM_FPC_TIMING_SHIFT 32ULL - - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - - struct { - /* TX PARAMS - * - * BIT [7 : 0] :- gain idx used for xtal cal CW tone - * BIT [15 : 8] :- infinite_bursting_mode - * BIT [23 : 16] :- ftm_mode - * BIT [31 : 24] :- sifs_us - */ - union { - A_UINT32 dword_txparams; - struct { - A_UINT32 - xtalCal_gain_idx: 8, - infinite_bursting_mode: 8, - ftm_mode: 8, - sifs_us: 8; - }; - }; - - /* dword_txparams_ext_1 - * BIT [0] :- agg_status - * BIT [1] :- dpdFlag - * BIT [9 : 2] :- ppdu_dur_buf_last_idx (last idx of ppdu duration - * circular buffer - 'actual_ppdu_dur_us') - * BIT [31 : 10] :- rsvd - */ - union { - A_UINT32 dword_txparams_ext_1; - struct { - A_UINT32 - agg_status: 1, - dpdFlag: 1, - ppdu_dur_buf_last_idx: 8, - rsvd: 22; - }; - }; - - /* Circular buffer containing actual ppdu duration_us */ - A_UINT32 actual_ppdu_dur_us[HTT_STATS_FTM_PPDU_DUR_CIRCULAR_BUF_CNT]; - - A_UINT32 target_fes_duration_us; /* TX time */ - A_UINT32 target_txoff_duration_us; /* TX OFF duration */ - A_UINT32 phy_mode; /* PHY mode selected */ - A_UINT32 pkt_len_post_truncation; /* Packet length post truncation */ - - /* dword_txparams_ext_2 - * BIT [7 : 0] :- target_tx_duty (TX ON ratio) - * BIT [15 : 8] :- PpduType - * BIT [23 : 16] :- numUsers_ofdmaTonePlan - * BIT [31 : 24] :- numUsers_ofdmaTonePlanEHT - */ - union { - A_UINT32 dword_txparams_ext_2; - struct { - A_UINT32 - target_tx_duty: 8, - PpduType: 8, - numUsers_ofdmaTonePlan: 8, - numUsers_ofdmaTonePlanEHT: 8; - }; - }; - } tx_params; - - /* CALIBRATION VERIFICATION FW ONLY TIMING STATS (uS) */ - struct { - /* - * ts_FPC - 64 bits, - * ts_FPC_low - bits[31:0] of 64 bits - * ts_FPC_high - bits[63:32] of 64 bits - */ - A_UINT32 ts_FPC_low; - A_UINT32 ts_FPC_high; - - A_UINT32 ts_calDbRegenTime; /* calDb regeneration time for FPC */ - A_UINT32 ts_OPC; - A_UINT32 ts_xtalcal; - A_UINT32 ts_rxgaincal; - A_UINT32 ts_nfcal; - A_UINT32 ts_tx_ver; - A_UINT32 ts_rx_ver; - - /* Overall channel change time for tx/rx verification */ - A_UINT32 tx_ver_OverallChanChangeTiming_ts; - A_UINT32 rx_ver_OverallChanChangeTiming_ts; - - /* dword_TimingStats: - * Number of TLVs for which TlvCmdInfo to be dumped - * BIT [7:0] :- TlvTimeStampCntFilled - * BIT [31 :8] :- rsvd1 - */ - union { - A_UINT32 dword_TimingStats; - struct { - A_UINT32 - TlvTimeStampCntFilled: 8, - rsvd1: 24; - }; - }; - - /* TLV cmd and timing info */ - struct { - A_UINT32 TlvTimeStamp_delta; /* Time of TLV CMD entry in ts */ - - /* dword_TlvcmdInfo - * TLV CMD ID and calType corresponding to TLV - * BIT [15:0] :- TlvCmd_entry - TLV cmd ID - * BIT [23 : 16] :- TlvCalType - calType - * BIT [31 : 24] :- rsvd2 - */ - union { - A_UINT32 dword_TlvcmdInfo; - struct { - A_UINT32 - TlvCmd_entry: 16, - TlvCalType: 8, - rsvd2: 8; - }; - }; - } TlvCmdTimingInfo[HTT_STATS_FTM_TIMESTAMP_TOTAL_CNT]; - } timingStats; - - /* TLV params */ - struct { - /* Total number of TLV parameters for last TLV */ - A_UINT32 LastTlv_numParams; - - /* Number of TLV params parsed for last TLV */ - A_UINT32 LastTlv_numParamsParsed; - - A_UINT32 LastTlvCmd; /* Last TLV CMD being executed */ - A_UINT32 LastTlvRspCmd; /* Last TLV CMD for which RSP is sent */ - - /* dword_TlvCmdParsing - * BIT [0] :- flagTlvCmdParsing - Flag indicating entire TLV CMD - * being parsed/dropped - * BIT [8 : 1] :- numTlvCmdDropped - count of entire TLV CMDs dropped - * BIT [31 : 9] :- rsvd3 - */ - union { - A_UINT32 dword_TlvCmdParsing; - struct { - A_UINT32 - flagTlvCmdParsing: 1, - numTlvCmdDropped: 8, - rsvd3: 23; - }; - }; - - A_UINT32 LastTlvCmdDropped; /* Last TLV CMD dropped */ - } tlvParams; - - /* RX gain cal params */ - struct{ - /* dword_rxGaincalMaxNumchan - * Num channels for which goodPktCnt for RX gain cal to be dumped - * BIT [7 : 0] :- rxGaincalMaxNumchan - * BIT [31 : 8] :- rsvd4 - */ - union { - A_UINT32 dword_rxGaincalMaxNumchan; - struct { - A_UINT32 - rxGaincalMaxNumchan: 8, - rsvd4: 24; - }; - }; - - A_UINT32 goodPktCnt[HTT_STATS_FTM_RXGAINCAL_MAX_NUM_CHAN_TLV2]; - - /* dword_rxgainCalRefISS - * Reference Input Signal Strength for Rx gain cal in dBm - * BIT [7 : 0] :- RxGainCal_refISS - * BIT [31 : 8] :- rsvd - */ - union { - A_INT32 dword_rxgainCalRefISS; - struct { - A_INT32 - RxGainCal_refISS: 8, - rsvd5: 24; - }; - }; - } rxGainCalParams; - - /* Miscellaneous params */ - - A_UINT32 bdReadRsp; -} htt_stats_ftm_tlv; - -#define HTT_STATS_FTM_TX_PARAMS_XTALCAL_GAIN_IDX_GET(word) \ - (((word) >> 0) & 0xff) -#define HTT_STATS_FTM_TX_PARAMS_INFINITE_BURSTING_MODE_GET(word) \ - (((word) >> 8) & 0xff) -#define HTT_STATS_FTM_TX_PARAMS_FTM_MODE_GET(word) \ - (((word) >> 16) & 0xff) -#define HTT_STATS_FTM_TX_PARAMS_SIFS_US_GET(word) \ - (((word) >> 24) & 0xff) - -#define HTT_STATS_FTM_TX_PARAMS_AGG_STATUS_GET(word) \ - (((word) >> 0) & 0x1) -#define HTT_STATS_FTM_TX_PARAMS_DPDFLAG_GET(word) \ - (((word) >> 1) & 0x1) -#define HTT_STATS_FTM_TX_PARAMS_PPDU_DUR_BUF_LAST_IDX_GET(word) \ - (((word) >> 2) & 0xff) - -#define HTT_STATS_FTM_TX_PARAMS_TARGET_TX_DUTY_GET(word) \ - (((word) >> 0) & 0xff) -#define HTT_STATS_FTM_TX_PARAMS_PPDUTYPE_GET(word) \ - (((word) >> 8) & 0xff) -#define HTT_STATS_FTM_TX_PARAMS_NUMUSERS_OFDMATONEPLAN_GET(word) \ - (((word) >> 16) & 0xff) -#define HTT_STATS_FTM_TX_PARAMS_NUMUSERS_OFDMATONEPLANEHT_GET(word) \ - (((word) >> 24) & 0xff) - -#define HTT_STATS_FTM_TIMINGSTATS_TLVTIMESTAMPCNTFILLED_GET(word) \ - (((word) >> 0) & 0xff) -#define HTT_STATS_FTM_TIMINGSTATS_TLVCMDTIMINGINFO_TLVCMD_ENTRY_GET(word) \ - (((word) >> 0) & 0xffff) -#define HTT_STATS_FTM_TIMINGSTATS_TLVCMDTIMINGINFO_TLVCALTYPE_GET(word) \ - (((word) >> 16) & 0xff) - -#define HTT_STATS_FTM_TIMINGSTATS_TLVCMD_ENTRY_GET(word) \ - (((word) >> 0) & 0xffff) -#define HTT_STATS_FTM_TIMINGSTATS_TLVCALTYPE_GET(word) \ - (((word) >> 16) & 0xff) - -#define HTT_STATS_FTM_TLVPARAMS_FLAGTLVCMDPARSING_GET(word) \ - (((word) >> 0) & 0x1) -#define HTT_STATS_FTM_TLVPARAMS_NUMTLVCMDDROPPED_GET(word) \ - (((word) >> 1) & 0xff) - -#define HTT_STATS_FTM_RXGAINCALPARAMS_RXGAINCALMAXNUMCHAN_GET(word) \ - (((word) >> 0) & 0xff) -#define HTT_STATS_FTM_RXGAINCALPARAMS_RXGAINCAL_REFISS_GET(word) \ - (((word) >> 0) & 0xff) - typedef struct { union { A_UINT32 word32; @@ -14247,26 +10868,6 @@ typedef struct { #define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_M 0x0FFFF000 #define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_S 12 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_M 0x00000007 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_S 0 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_M 0x00000038 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_S 3 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_M 0x000001C0 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_S 6 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_M 0x00000E00 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_S 9 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_M 0x00007000 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_S 12 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_M 0x00038000 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_S 15 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_M 0x001C0000 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_S 18 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_M 0x00E00000 -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_S 21 -#define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_M 0x07000000 -#define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_S 24 - - #define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_GET(_var) \ (((_var) & HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_M) >> \ HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_S) @@ -14309,160 +10910,6 @@ typedef struct { ((_var) |= ((_val) << HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_S)); \ } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_TID0_TQM_LINK_ID_S)); \ - } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_TID1_TQM_LINK_ID_S)); \ - } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_TID2_TQM_LINK_ID_S)); \ - } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_TID3_TQM_LINK_ID_S)); \ - } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_TID4_TQM_LINK_ID_S)); \ - } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_TID5_TQM_LINK_ID_S)); \ - } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_TID6_TQM_LINK_ID_S)); \ - } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_TID7_TQM_LINK_ID_S)); \ - } while (0) - -#define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_M) >> \ - HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_S) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK0_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK1_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK2_ID_GET(_var) \ - HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_GET(_var) -#define HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_EXT_DETAILS_MLO_MGMT_TID_TQM_LINK_ID_S)); \ - } while (0) - typedef struct { htt_tlv_hdr_t tlv_hdr; union { @@ -14474,51 +10921,6 @@ typedef struct { }; A_UINT32 msg_dword_1; }; - union { - struct { - A_UINT32 tid0_tqm_link0_id : 3, - tid1_tqm_link0_id : 3, - tid2_tqm_link0_id : 3, - tid3_tqm_link0_id : 3, - tid4_tqm_link0_id : 3, - tid5_tqm_link0_id : 3, - tid6_tqm_link0_id : 3, - tid7_tqm_link0_id : 3, - mlo_mgmt_tid_tqm_link0_id : 3, - reserved_tqm_link0 : 5; - }; - A_UINT32 msg_dword_tqm_link0; - }; - union { - struct { - A_UINT32 tid0_tqm_link1_id : 3, - tid1_tqm_link1_id : 3, - tid2_tqm_link1_id : 3, - tid3_tqm_link1_id : 3, - tid4_tqm_link1_id : 3, - tid5_tqm_link1_id : 3, - tid6_tqm_link1_id : 3, - tid7_tqm_link1_id : 3, - mlo_mgmt_tid_tqm_link1_id : 3, - reserved_tqm_link1 : 5; - }; - A_UINT32 msg_dword_tqm_link1; - }; - union { - struct { - A_UINT32 tid0_tqm_link2_id : 3, - tid1_tqm_link2_id : 3, - tid2_tqm_link2_id : 3, - tid3_tqm_link2_id : 3, - tid4_tqm_link2_id : 3, - tid5_tqm_link2_id : 3, - tid6_tqm_link2_id : 3, - tid7_tqm_link2_id : 3, - mlo_mgmt_tid_tqm_link2_id : 3, - reserved_tqm_link2 : 5; - }; - A_UINT32 msg_dword_tqm_link2; - }; } htt_stats_ml_peer_ext_details_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; @@ -14545,16 +10947,11 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; #define HTT_ML_LINK_INFO_ANCHOR_LINK_S 21 #define HTT_ML_LINK_INFO_INITIALIZED_M 0x00400000 #define HTT_ML_LINK_INFO_INITIALIZED_S 22 -#define HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_M 0x00800000 -#define HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_S 23 #define HTT_ML_LINK_INFO_SW_PEER_ID_M 0x0000ffff #define HTT_ML_LINK_INFO_SW_PEER_ID_S 0 #define HTT_ML_LINK_INFO_VDEV_ID_M 0x00ff0000 #define HTT_ML_LINK_INFO_VDEV_ID_S 16 -#define HTT_STATS_ML_LINK_INFO_PS_STATE_M 0x01000000 -#define HTT_STATS_ML_LINK_INFO_PS_STATE_S 24 - #define HTT_ML_LINK_INFO_VALID_GET(_var) \ (((_var) & HTT_ML_LINK_INFO_VALID_M) >> \ @@ -14710,21 +11107,6 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; ((_var) |= ((_val) << HTT_ML_LINK_INFO_INITIALIZED_S)); \ } while (0) - -#define HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_GET(_var) \ - (((_var) & HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_M) >> \ - HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_ML_LINK_INFO_DETAILS_BRIDGE_PEER_GET(_var) \ - HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_GET(_var) -#define HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_LINK_INFO_BRIDGE_PEER, _val); \ - ((_var) &= ~(HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_LINK_INFO_BRIDGE_PEER_S)); \ - } while (0) - - #define HTT_ML_LINK_INFO_SW_PEER_ID_GET(_var) \ (((_var) & HTT_ML_LINK_INFO_SW_PEER_ID_M) >> \ HTT_ML_LINK_INFO_SW_PEER_ID_S) @@ -14753,20 +11135,6 @@ typedef htt_stats_ml_peer_ext_details_tlv htt_ml_peer_ext_details_tlv; ((_var) |= ((_val) << HTT_ML_LINK_INFO_VDEV_ID_S)); \ } while (0) -#define HTT_STATS_ML_LINK_INFO_PS_STATE_GET(_var) \ - (((_var) & HTT_STATS_ML_LINK_INFO_PS_STATE_M) >> \ - HTT_STATS_ML_LINK_INFO_PS_STATE_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_ML_LINK_INFO_DETAILS_PS_GET(_var) \ - HTT_STATS_ML_LINK_INFO_PS_STATE_GET(_var) -#define HTT_STATS_ML_LINK_INFO_PS_STATE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_LINK_INFO_PS_STATE, _val); \ - ((_var) &= ~(HTT_STATS_ML_LINK_INFO_PS_STATE_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_LINK_INFO_PS_STATE_S)); \ - } while (0) - - typedef struct { htt_tlv_hdr_t tlv_hdr; union { @@ -14782,8 +11150,7 @@ typedef struct { master_link : 1, anchor_link : 1, initialized : 1, - bridge_peer : 1, - reserved : 8; + reserved : 9; }; A_UINT32 msg_dword_1; }; @@ -14792,8 +11159,7 @@ typedef struct { struct { A_UINT32 sw_peer_id : 16, vdev_id : 8, - ps : 1, - reserved1 : 7; + reserved1 : 8; }; A_UINT32 msg_dword_2; }; @@ -14831,8 +11197,6 @@ typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; #define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_M 0x000000ff #define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_S 0 -#define HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED_M 0x0000ff00 -#define HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED_S 8 #define HTT_ML_PEER_DETAILS_NUM_LINKS_GET(_var) \ (((_var) & HTT_ML_PEER_DETAILS_NUM_LINKS_M) >> \ @@ -15018,17 +11382,6 @@ typedef htt_stats_ml_link_info_details_tlv htt_ml_link_info_tlv; ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_S)); \ } while (0) -#define HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED_GET(_var) \ - (((_var) & HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED_M) >> \ - HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED_S) -#define HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED, _val); \ - ((_var) &= ~(HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED_M)); \ - ((_var) |= ((_val) << HTT_STATS_ML_PEER_DETAILS_STATUS_REQUIRED_S)); \ - } while (0) - - typedef struct { htt_tlv_hdr_t tlv_hdr; htt_mac_addr remote_mld_mac_addr; @@ -15061,19 +11414,8 @@ typedef struct { union { struct { - A_UINT32 participating_chips_bitmap : 8, - /* status_required: - * Bitmap of status-required flags for each chip. - * Bit 0 is always the chip with the primary link. - * The remaining bits are for the other chips, - * in increasing order of chip ID, wrapping around - * to cover the chips whose IDs are smaller than the - * primary link's chip. - * Thus, bit 1 is for the chip whose ID is next after - * the primary link's chip ID, etc. - */ - status_required : 8, - reserved1 : 16; + A_UINT32 participating_chips_bitmap : 8, + reserved1 : 24; }; A_UINT32 msg_dword_2; }; @@ -15364,16 +11706,6 @@ typedef struct { * only for UL BSR TX mode. */ A_UINT32 running_ul_scheduler_for_bsrp_cnt[HTT_NUM_AC_WMM]; - /** - * Number of instances where we populated TX mode and candidate lists - * only for DL, due to skipping UL voluntarily. - */ - A_UINT32 running_dl_scheduler_due_to_skip_ul[HTT_NUM_AC_WMM]; - /** - * Number of instances where we populated TX mode and candidate lists - * only for UL, due to skipping DL voluntarily. - */ - A_UINT32 running_ul_scheduler_due_to_skip_dl[HTT_NUM_AC_WMM]; } htt_stats_pdev_sched_algo_ofdma_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_pdev_sched_algo_ofdma_stats_tlv @@ -15389,13 +11721,7 @@ typedef struct { * read/write this bitfield. * BIT [31 : 8] :- reserved */ - union { - struct { - A_UINT32 mac_id: 8, - reserved: 24; - }; - A_UINT32 mac_id__word; - }; + A_UINT32 mac_id__word; A_UINT32 basic_trigger_across_bss; A_UINT32 basic_trigger_within_bss; A_UINT32 bsr_trigger_across_bss; @@ -15408,8 +11734,6 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_pdev_mbssid_ctrl_frame_stats_tlv htt_pdev_mbssid_ctrl_frame_stats_tlv; -#define HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_MAC_ID_GET(word) \ - (((word) >> 0) & 0xff) typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -15476,15 +11800,9 @@ typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv; #define HTT_BW_MGR_STATS_STATIC_PATTERN_M 0x00ffff00 #define HTT_BW_MGR_STATS_STATIC_PATTERN_S 8 -#define HTT_BW_MGR_STATS_WIFI_VERSION_M 0x0000000f -#define HTT_BW_MGR_STATS_WIFI_VERSION_S 0 - #define HTT_BW_MGR_STATS_MAC_ID_GET(_var) \ (((_var) & HTT_BW_MGR_STATS_MAC_ID_M) >> \ HTT_BW_MGR_STATS_MAC_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_BW_MGR_STATS_MAC_ID_GET(_var) \ - HTT_BW_MGR_STATS_MAC_ID_GET(_var) #define HTT_BW_MGR_STATS_MAC_ID_SET(_var, _val) \ do { \ @@ -15496,142 +11814,69 @@ typedef htt_stats_pdev_tdma_tlv htt_pdev_tdma_stats_tlv; #define HTT_BW_MGR_STATS_PRI20_IDX_GET(_var) \ (((_var) & HTT_BW_MGR_STATS_PRI20_IDX_M) >> \ HTT_BW_MGR_STATS_PRI20_IDX_S) -#define HTT_BW_MGR_STATS_NPCA_PRI20_IDX_GET(_var) \ - HTT_BW_MGR_STATS_PRI20_IDX_GET(_var) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_BW_MGR_STATS_PRI20_IDX_GET(_var) \ - HTT_BW_MGR_STATS_PRI20_IDX_GET(_var) #define HTT_BW_MGR_STATS_PRI20_IDX_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_PRI20_IDX, _val); \ ((_var) |= ((_val) << HTT_BW_MGR_STATS_PRI20_IDX_S)); \ } while (0) -#define HTT_BW_MGR_STATS_NPCA_PRI20_IDX_SET(_var, _val) \ - HTT_BW_MGR_STATS_PRI20_IDX_SET(_var, _val) #define HTT_BW_MGR_STATS_PRI20_FREQ_GET(_var) \ (((_var) & HTT_BW_MGR_STATS_PRI20_FREQ_M) >> \ HTT_BW_MGR_STATS_PRI20_FREQ_S) -#define HTT_BW_MGR_STATS_NPCA_PRI20_FREQ_GET(_var) \ - HTT_BW_MGR_STATS_PRI20_FREQ_GET(_var) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_BW_MGR_STATS_PRI20_FREQ_MHZ_GET(_var) \ - HTT_BW_MGR_STATS_PRI20_FREQ_GET(_var) #define HTT_BW_MGR_STATS_PRI20_FREQ_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_PRI20_FREQ, _val); \ ((_var) |= ((_val) << HTT_BW_MGR_STATS_PRI20_FREQ_S)); \ } while (0) -#define HTT_BW_MGR_STATS_NPCA_PRI20_FREQ_SET(_var, _val) \ - HTT_BW_MGR_STATS_PRI20_FREQ_SET(_var, _val) #define HTT_BW_MGR_STATS_CENTER_FREQ1_GET(_var) \ (((_var) & HTT_BW_MGR_STATS_CENTER_FREQ1_M) >> \ HTT_BW_MGR_STATS_CENTER_FREQ1_S) -#define HTT_BW_MGR_STATS_NPCA_CENTER_FREQ1_GET(_var) \ - HTT_BW_MGR_STATS_CENTER_FREQ1_GET(_var) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_BW_MGR_STATS_CENTRE_FREQ1_GET(_var) \ - HTT_BW_MGR_STATS_CENTER_FREQ1_GET(_var) #define HTT_BW_MGR_STATS_CENTER_FREQ1_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CENTER_FREQ1, _val); \ ((_var) |= ((_val) << HTT_BW_MGR_STATS_CENTER_FREQ1_S)); \ } while (0) -#define HTT_BW_MGR_STATS_NPCA_CENTER_FREQ1_SET(_var, _val) \ - HTT_BW_MGR_STATS_CENTER_FREQ1_SET(_var, _val) #define HTT_BW_MGR_STATS_CENTER_FREQ2_GET(_var) \ (((_var) & HTT_BW_MGR_STATS_CENTER_FREQ2_M) >> \ HTT_BW_MGR_STATS_CENTER_FREQ2_S) -#define HTT_BW_MGR_STATS_NPCA_CENTER_FREQ2_GET(_var) \ - HTT_BW_MGR_STATS_CENTER_FREQ2_GET(_var) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_BW_MGR_STATS_CENTRE_FREQ2_GET(_var) \ - HTT_BW_MGR_STATS_CENTER_FREQ2_GET(_var) #define HTT_BW_MGR_STATS_CENTER_FREQ2_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CENTER_FREQ2, _val); \ ((_var) |= ((_val) << HTT_BW_MGR_STATS_CENTER_FREQ2_S)); \ } while (0) -#define HTT_BW_MGR_STATS_NPCA_CENTER_FREQ2_SET(_var, _val) \ - HTT_BW_MGR_STATS_CENTER_FREQ2_SET(_var, _val) #define HTT_BW_MGR_STATS_CHAN_PHY_MODE_GET(_var) \ (((_var) & HTT_BW_MGR_STATS_CHAN_PHY_MODE_M) >> \ HTT_BW_MGR_STATS_CHAN_PHY_MODE_S) -#define HTT_BW_MGR_STATS_CHAN_NPCA_PHY_MODE_GET(_var) \ - HTT_BW_MGR_STATS_CHAN_PHY_MODE_GET(_var) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_BW_MGR_STATS_PHY_MODE_GET(_var) \ - HTT_BW_MGR_STATS_CHAN_PHY_MODE_GET(_var) #define HTT_BW_MGR_STATS_CHAN_PHY_MODE_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_CHAN_PHY_MODE, _val); \ ((_var) |= ((_val) << HTT_BW_MGR_STATS_CHAN_PHY_MODE_S)); \ } while (0) -#define HTT_BW_MGR_STATS_CHAN_NPCA_PHY_MODE_SET(_var, _val) \ - HTT_BW_MGR_STATS_CHAN_PHY_MODE_SET(_var, _val) #define HTT_BW_MGR_STATS_STATIC_PATTERN_GET(_var) \ (((_var) & HTT_BW_MGR_STATS_STATIC_PATTERN_M) >> \ HTT_BW_MGR_STATS_STATIC_PATTERN_S) -#define HTT_BW_MGR_STATS_NPCA_STATIC_PATTERN_GET(_var) \ - HTT_BW_MGR_STATS_STATIC_PATTERN_GET(_var) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_BW_MGR_STATS_STATIC_PATTERN_GET(_var) \ - HTT_BW_MGR_STATS_STATIC_PATTERN_GET(_var) #define HTT_BW_MGR_STATS_STATIC_PATTERN_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_STATIC_PATTERN, _val); \ ((_var) |= ((_val) << HTT_BW_MGR_STATS_STATIC_PATTERN_S)); \ } while (0) -#define HTT_BW_MGR_STATS_NPCA_STATIC_PATTERN_SET(_var, _val) \ - HTT_BW_MGR_STATS_STATIC_PATTERN_SET(_var, _val) -#define HTT_BW_MGR_STATS_WIFI_VERSION_GET(_var) \ - (((_var) & HTT_BW_MGR_STATS_WIFI_VERSION_M) >> \ - HTT_BW_MGR_STATS_WIFI_VERSION_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PDEV_BW_MGR_STATS_WIFI_VERSION_GET(_var) \ - HTT_BW_MGR_STATS_WIFI_VERSION_GET(_var) - -#define HTT_BW_MGR_STATS_WIFI_VERSION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_BW_MGR_STATS_WIFI_VERSION, _val); \ - ((_var) |= ((_val) << HTT_BW_MGR_STATS_WIFI_VERSION_S)); \ - } while (0) - -#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_PRI20_IDX_GET(_var) \ - (((_var) >> 8) & 0xff) - -#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_PRI20_FREQ_MHZ_GET(_var) \ - (((_var) >> 16) & 0xffff) - -#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_CENTRE_FREQ1_GET(_var) \ - (((_var) >> 0) & 0xffff) - -#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_CENTRE_FREQ2_GET(_var) \ - (((_var) >> 16) & 0xffff) - -#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_PHY_MODE_GET(_var) \ - (((_var) >> 0) & 0xff) - -#define HTT_STATS_PDEV_BW_MGR_STATS_NPCA_STATIC_PATTERN_GET(_var) \ - (((_var) >> 8) & 0xffff) - typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -15639,76 +11884,17 @@ typedef struct { * BIT [ 15 : 8] :- pri20_index * BIT [ 31 : 16] :- pri20_freq in Mhz */ - union { - struct { - A_UINT32 mac_id : 8; - A_UINT32 pri20_idx : 8; - A_UINT32 pri20_freq_mhz : 16; - }; - A_UINT32 mac_id__pri20_idx__freq; - }; + A_UINT32 mac_id__pri20_idx__freq; /* BIT [ 15 : 0] :- centre_freq1 * BIT [ 31 : 16] :- centre_freq2 */ - union { - struct { - A_UINT32 centre_freq1 : 16; - A_UINT32 centre_freq2 : 16; - }; - A_UINT32 centre_freq1__freq2; - }; + A_UINT32 centre_freq1__freq2; /* BIT [ 7 : 0] :- channel_phy_mode * BIT [ 23 : 8] :- static_pattern */ - union { - struct { - A_UINT32 phy_mode : 8; - A_UINT32 static_pattern : 16; - A_UINT32 reserved : 8; - }; - A_UINT32 phy_mode__static_pattern; - }; - - /* - * BIT [ 3 : 0] :- wifi_version - * BIT [ 7 : 4] :- Reserved - * BIT [ 15 : 8] :- NPCA_pri20_index - * BIT [ 31 : 16] :- NPCA_pri20_freq in Mhz - */ - union { - struct { - A_UINT32 wifi_version : 4; - A_UINT32 reserved2 : 4; - A_UINT32 npca_pri20_idx : 8; - A_UINT32 npca_pri20_freq_mhz : 16; - }; - A_UINT32 npca__wifi_version__pri20_idx__freq; - }; - - /* BIT [ 15 : 0] :- NPCA_centre_freq1 - * BIT [ 31 : 16] :- NPCA_centre_freq2 - */ - union { - struct { - A_UINT32 npca_centre_freq1 : 16; - A_UINT32 npca_centre_freq2 : 16; - }; - A_UINT32 npca__centre_freq1__freq2; - }; - - /* BIT [ 7 : 0] :- NPCA_channel_phy_mode - * BIT [ 23 : 8] :- NPCA_pattern - */ - union { - struct { - A_UINT32 npca_phy_mode : 8; - A_UINT32 npca_static_pattern : 16; - A_UINT32 reserved3 : 8; - }; - A_UINT32 npca__phy_mode__static_pattern; - }; + A_UINT32 phy_mode__static_pattern; } htt_stats_pdev_bw_mgr_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_pdev_bw_mgr_stats_tlv htt_pdev_bw_mgr_stats_tlv; @@ -15857,61 +12043,6 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_mlo_umac_ssr_mlo_tlv htt_mlo_umac_ssr_mlo_stats_tlv; -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_DISABLE_RXDMA_PREFETCH_GET(word) \ - (((word) >> 0) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_PMACS_HWMLOS_GET(word) \ - (((word) >> 1) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_GLOBAL_WSI_GET(word) \ - (((word) >> 2) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_PMACS_DMAC_GET(word) \ - (((word) >> 3) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_TCL_GET(word) \ - (((word) >> 4) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_TQM_GET(word) \ - (((word) >> 5) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_WBM_GET(word) \ - (((word) >> 6) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_REO_GET(word) \ - (((word) >> 7) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_PRE_RESET_HOST_GET(word) \ - (((word) >> 8) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_RESET_PREREQUISITES_GET(word) \ - (((word) >> 9) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_RESET_PRE_RING_RESET_GET(word) \ - (((word) >> 10) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_RESET_APPLY_SOFT_RESET_GET(word) \ - (((word) >> 11) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_RESET_POST_RING_RESET_GET(word) \ - (((word) >> 12) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_RESET_FW_TQM_CMDQS_GET(word) \ - (((word) >> 13) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_HOST_GET(word) \ - (((word) >> 14) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_UMAC_INTERRUPTS_GET(word) \ - (((word) >> 15) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_WBM_GET(word) \ - (((word) >> 16) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_REO_GET(word) \ - (((word) >> 17) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_TQM_GET(word) \ - (((word) >> 18) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_PMACS_DMAC_GET(word) \ - (((word) >> 19) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_TQM_SYNC_CMD_GET(word) \ - (((word) >> 20) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_GLOBAL_WSI_GET(word) \ - (((word) >> 21) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_PMACS_HWMLOS_GET(word) \ - (((word) >> 22) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_ENABLE_RXDMA_PREFETCH_GET(word) \ - (((word) >> 23) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_TCL_GET(word) \ - (((word) >> 24) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_HOST_ENQ_GET(word) \ - (((word) >> 25) & 0x1) -#define HTT_STATS_MLO_UMAC_SSR_MLO_MLO_DONE_MASK_POST_RESET_VERIFY_UMAC_RECOVERED_GET(word) \ - (((word) >> 26) & 0x1) - /* dword0 - b'0 - PRE_RESET_DISABLE_RXDMA_PREFETCH */ #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_M 0x1 #define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S 0 @@ -16528,9 +12659,6 @@ typedef htt_stats_codel_svc_class_tlv htt_codel_svc_class_stats_tlv; #define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_GET(_var) \ (((_var) & HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_M) >> \ HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_CODEL_MSDUQ_TX_FLOW_NUM_GET(_var) \ - HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_GET(_var) #define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM, _val); \ @@ -16543,9 +12671,6 @@ typedef htt_stats_codel_svc_class_tlv htt_codel_svc_class_stats_tlv; #define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_GET(_var) \ (((_var) & HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_M) >> \ HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_CODEL_MSDUQ_SVC_CLASS_ID_GET(_var) \ - HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_GET(_var) #define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID, _val); \ @@ -16558,9 +12683,6 @@ typedef htt_stats_codel_svc_class_tlv htt_codel_svc_class_stats_tlv; #define HTT_CODEL_MSDUQ_STATS_DROPS_GET(_var) \ (((_var) & HTT_CODEL_MSDUQ_STATS_DROPS_M) >> \ HTT_CODEL_MSDUQ_STATS_DROPS_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_CODEL_MSDUQ_CODEL_DROPS_GET(_var) \ - HTT_CODEL_MSDUQ_STATS_DROPS_GET(_var) #define HTT_CODEL_MSDUQ_STATS_DROPS_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_DROPS, _val); \ @@ -16573,9 +12695,6 @@ typedef htt_stats_codel_svc_class_tlv htt_codel_svc_class_stats_tlv; #define HTT_CODEL_MSDUQ_STATS_NO_DROPS_GET(_var) \ (((_var) & HTT_CODEL_MSDUQ_STATS_NO_DROPS_M) >> \ HTT_CODEL_MSDUQ_STATS_NO_DROPS_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_CODEL_MSDUQ_CODEL_NO_DROPS_GET(_var) \ - HTT_CODEL_MSDUQ_STATS_NO_DROPS_GET(_var) #define HTT_CODEL_MSDUQ_STATS_NO_DROPS_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_NO_DROPS, _val); \ @@ -16740,2406 +12859,13 @@ static INLINE A_UINT8 *htt_ctrl_path_cal_type_id_to_name(A_UINT32 cal_type_id) /*===================== Start GTX stats ====================*/ #define HTT_NUM_MCS_PER_NSS 16 - -#define HTT_NUM_EXTRA_MCS_PER_NSS 4 /* Stores iMCS index 1.1, 3.1, 4.1, 7.1 */ - -#define HTT_STATS_GTX_WIFI_VERSION_M 0x0000000f -#define HTT_STATS_GTX_WIFI_VERSION_S 0 - -#define HTT_STATS_GTX_WIFI_VERSION_GET(_var) \ - (((_var) & HTT_STATS_GTX_WIFI_VERSION_M) >> \ - HTT_STATS_GTX_WIFI_VERSION_S) -#define HTT_STATS_GTX_WIFI_VERSION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_GTX_WIFI_VERSION, _val); \ - ((_var) |= ((_val) << HTT_STATS_GTX_WIFI_VERSION_S)); \ - } while (0) - typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 gtx_enabled; /* shows whether Green Tx feature is enabled */ - - /* shows current MCS's minimum TPC in 0.25dBm units */ - A_INT32 mcs_tpc_min[HTT_NUM_MCS_PER_NSS]; - - /* shows current MCS's maximum TPC in 0.25dBm units */ - A_INT32 mcs_tpc_max[HTT_NUM_MCS_PER_NSS]; - - /* - * shows current MCS's difference between maximum and minimum TPC - * in 0.25dB units - */ - A_UINT32 mcs_tpc_diff[HTT_NUM_MCS_PER_NSS]; - /** - * BIT [ 3 : 0] :- wifi_version - * BIT [31 : 4] :- reserved - */ - union { - struct { - A_UINT32 - /* wifi_version: - * Holds a HTT_RX_TX_PDEV_STATS_WIFI_VERSION value. - * Refer to HTT_RX_EXT_PDEV_RATE_STATS_WIFI_VERSION_GET - * / _SET macros for accessing this bitfield. - */ - wifi_version: 4, - reserved: 28; - }; - A_UINT32 wifi_version__word; - }; - - /* shows current MCS's minimum TPC in 0.25dBm units for iMCS cases */ - A_INT32 mcs_tpc_min_ext[HTT_NUM_EXTRA_MCS_PER_NSS]; - - /* shows current MCS's maximum TPC in 0.25dBm units for iMCS cases */ - A_INT32 mcs_tpc_max_ext[HTT_NUM_EXTRA_MCS_PER_NSS]; - - /* - * shows current MCS's difference between maximum and minimum TPC - * in 0.25dB units for iMCS cases - */ - A_UINT32 mcs_tpc_diff_ext[HTT_NUM_EXTRA_MCS_PER_NSS]; + A_INT32 mcs_tpc_min[HTT_NUM_MCS_PER_NSS]; /* shows current MCS's minimum TPC in 0.25dBm units */ + A_INT32 mcs_tpc_max[HTT_NUM_MCS_PER_NSS]; /* shows current MCS's maximum TPC in 0.25dBm units */ + A_UINT32 mcs_tpc_diff[HTT_NUM_MCS_PER_NSS]; /* shows current MCS's difference between maximum and minimum TPC in 0.25dB unit*/ } htt_stats_gtx_tlv; /*===================== End GTX stats ====================*/ - -#define HTT_TX_PDEV_SAM_STATS_MAX_CMD_STATUS_TYPE 16 - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 pdev_id; - /* - * Number of commands posted on the FW -> SAM Command Ring. The index has - * an internal firmware meaning (this stat is primarily provided for - * internal debug), but is related to the type of command that has been - * posted. - */ - A_UINT32 cmd_posted[HTT_TX_PDEV_SAM_STATS_MAX_CMD_STATUS_TYPE]; - /* - * Number of statuses reaped on the SAM -> FW Status Ring. The index has an - * internal firmware meaning (this stat is primarily provided for internal - * debug), but is related to the type of status that is being processed. - */ - A_UINT32 status_reaped[HTT_TX_PDEV_SAM_STATS_MAX_CMD_STATUS_TYPE]; - /* - * Incremented each time a first_summary_bitmap_change_seen TLV is - * processed on the SAM -> FW Status ring. - */ - A_UINT32 first_seen_tlv_reaped; - /* - * Number of MSDUQ Empty -> Not Empty transitions observed through SAM - * Queue Bitmaps. - */ - A_UINT32 msduq_to_not_empty_cnt; - /* - * Number of MSDUQ Not Empty -> Empty transitions observed through SAM - * Queue Bitmaps. - */ - A_UINT32 msduq_to_empty_cnt; - /* - * Number of MPDUQ Empty -> Not Empty transitions observed through SAM - * Queue Bitmaps. - */ - A_UINT32 mpduq_to_not_empty_cnt; - /* - * Number of MPDUQ Not Empty -> Empty transitions observed through SAM - * Queue Bitmaps. - */ - A_UINT32 mpduq_to_empty_cnt; -} htt_stats_pdev_sam_tlv; - - -#define HTT_STATS_RESET_HISTORY_MAX_ENTRIES 10 - -/** - * @brief TLV structure for wifistats 82 (reset history) - * - * This structure holds the last 10 reset history entries. - * The entries are copied from the firmware's internal circular buffer. - */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /** - * @brief An array of structures, each holding the details of a single - * reset event. The entries are ordered chronologically from - * oldest to newest. - */ - struct { - A_UINT32 timestamp_ms; - /* reset_flags is only for debugging, not for host interpretation */ - A_UINT32 reset_flags; - /* reset_cause is only for debugging, not for host interpretation */ - A_UINT32 reset_cause; - /* reset_reason is only for debugging, not for host interpretation */ - A_UINT32 reset_reason; - A_UINT32 phy_mode; - union { - A_UINT32 channel_freq; - struct { - A_UINT32 - mhz: 16, - band_center_freq1:16; - }; - }; - union { - A_UINT32 channel_info; - struct { - A_UINT32 - flags: 16, /* only for debug, not for host interpret */ - phy_id: 8, - swprofile: 8; /* only for debug, not for host interpret */ - }; - }; - union { - A_UINT32 home_channel_info; - struct { - A_UINT32 - is_home_chan: 1, - reserved: 31; - }; - }; - A_UINT32 reserved_dwords[2]; /* reserved for future use */ - } reset_history[HTT_STATS_RESET_HISTORY_MAX_ENTRIES]; - A_UINT32 idx; /** Current write index of the circular buffer */ - A_UINT32 count; /** Total number of resets captured (up to 10) */ -} htt_stats_reset_history_tlv; - -#define HTT_STATS_RESET_HISTORY_MHZ_GET(word) \ - ((word) & 0x0000ffff) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_MHZ_GET(word) \ - HTT_STATS_RESET_HISTORY_MHZ_GET(word) -#define HTT_STATS_RESET_HISTORY_MHZ_SET(word, value) \ - ((word) |= ((value) & 0x0000ffff)) - -#define HTT_STATS_RESET_HISTORY_BAND_CENTER_FREQ1_GET(word) \ - (((word) & 0xffff0000) >> 16) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_BAND_CENTER_FREQ1_GET(word) \ - HTT_STATS_RESET_HISTORY_BAND_CENTER_FREQ1_GET(word) -#define HTT_STATS_RESET_HISTORY_BAND_CENTER_FREQ1_SET(word, value) \ - ((word) |= (((value) << 16) & 0xffff0000)) - -#define HTT_STATS_RESET_HISTORY_FLAGS_GET(word) \ - ((word) & 0x0000ffff) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_FLAGS_GET(word) \ - HTT_STATS_RESET_HISTORY_FLAGS_GET(word) -#define HTT_STATS_RESET_HISTORY_FLAGS_SET(word, value) \ - ((word) |= ((value) & 0x0000ffff)) - -#define HTT_STATS_RESET_HISTORY_PHY_ID_GET(word) \ - (((word) & 0x00ff0000) >> 16) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_PHY_ID_GET(word) \ - HTT_STATS_RESET_HISTORY_PHY_ID_GET(word) -#define HTT_STATS_RESET_HISTORY_PHY_ID_SET(word, value) \ - ((word) |= (((value) << 16) & 0x00ff0000)) - -#define HTT_STATS_RESET_HISTORY_SWPROFILE_GET(word) \ - (((word) & 0xff000000) >> 24) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_SWPROFILE_GET(word) \ - HTT_STATS_RESET_HISTORY_SWPROFILE_GET(word) -#define HTT_STATS_RESET_HISTORY_SWPROFILE_SET(word, value) \ - ((word) |= (((value) << 24) & 0xff000000)) - -#define HTT_STATS_RESET_HISTORY_IS_HOME_CHAN_GET(word) \ - (((word) & 0x00000001) >> 0) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_RESET_HISTORY_RESET_HISTORY_IS_HOME_CHAN_GET(word) \ - HTT_STATS_RESET_HISTORY_IS_HOME_CHAN_GET(word) -#define HTT_STATS_RESET_HISTORY_IS_HOME_CHAN_SET(word, value) \ - ((word) |= (((value) << 0) & 0x00000001)) - - -/*===================== Start Regulatory stats ==================== { */ - -typedef enum { - HTT_STATS_REGULATORY_SUBTYPE_REGDB = 0, - HTT_STATS_REGULATORY_SUBTYPE_6GHZ = 1, - HTT_STATS_REGULATORY_SUBTYPE_CTL = 2, - HTT_STATS_REGULATORY_SUBTYPE_DFS = 3, - HTT_STATS_REGULATORY_SUBTYPE_MAX -} htt_stats_regulatory_subtype_t; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - struct { - A_UINT32 major_version : 8, - minor_version : 8, - custom_version: 8, - rsvd : 8; - }; - A_UINT32 regdb_version; - }; - A_UINT32 country_code; - A_UINT32 alpha_code; /* [7:0]->alpha[0], [15:8]->alpha[1] and so on */ - /* RegDomain and SuperDomain IDs are from Regdb */ - A_UINT32 reg_domain_pair_id; - A_UINT32 super_domain_id; - A_UINT32 phymode_bitmap; /* WMI_REGULATORY_PHYBITMAP */ - A_UINT32 chan_priority_freq; /* in MHz */ - A_UINT32 tpc_region; - A_UINT32 max_bw_2g; /* in MHz */ - A_UINT32 max_bw_5g; /* in MHz */ - A_UINT32 max_bw_6g; /* in MHz */ -} htt_stats_regdb_ctry_tlv; - -#define HTT_STATS_GET_FIELD(mask,shift,word) (((word) & (mask)) >> (shift)) -#define HTT_STATS_SET_FIELD(mask,shift,word,value) \ - (word) = (((word) & ~((mask))) | (((value) << (shift)) & (mask))) - -#define HTT_STATS_REGDB_CTRY_GET_MAJOR_VERSION(word) \ - HTT_STATS_GET_FIELD(0xFF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_CTRY_MAJOR_VERSION_GET(word) \ - HTT_STATS_REGDB_CTRY_GET_MAJOR_VERSION(word) -#define HTT_STATS_REGDB_CTRY_SET_MAJOR_VERSION(word,value) \ - HTT_STATS_SET_FIELD(0xFF, 0, (word), (value)) - -#define HTT_STATS_REGDB_CTRY_GET_MINOR_VERSION(word) \ - HTT_STATS_GET_FIELD(0xFF00, 8, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_CTRY_MINOR_VERSION_GET(word) \ - HTT_STATS_REGDB_CTRY_GET_MINOR_VERSION(word) -#define HTT_STATS_REGDB_CTRY_SET_MINOR_VERSION(word,value) \ - HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value)) - -#define HTT_STATS_REGDB_CTRY_GET_CUSTOM_VERSION(word) \ - HTT_STATS_GET_FIELD(0xFF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_CTRY_CUSTOM_VERSION_GET(word) \ - HTT_STATS_REGDB_CTRY_GET_CUSTOM_VERSION(word) -#define HTT_STATS_REGDB_CTRY_SET_CUSTOM_VERSION(word,value) \ - HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value)) - -#define HTT_STATS_REGDB_CTRY_GET_ALPHA_CODE_CHAR(word, idx) \ - HTT_STATS_GET_FIELD((0xFF << (8*(idx))), (8*(idx)), (word)) -#define HTT_STATS_REGDB_CTRY_SET_ALPHA_CODE_CHAR(word, idx, value) \ - HTT_STATS_SET_FIELD((0xFF << (8*(idx))), (8*(idx)), (word), (value)) - -typedef struct { - union { - struct { - A_UINT32 start_freq : 16, /* in MHz */ - end_freq : 16; /* in MHz */ - }; - A_UINT32 freq_info; - }; - union { - struct { - A_UINT32 max_bw : 16, /* in MHz */ - reg_power : 8, /* in dBm */ - ant_gain : 8; /* in dB */ - }; - A_UINT32 bw_pwr_info; - }; - union { - struct { - A_UINT32 flags : 16, /* enum WMI_REGULATORY_FLAGS */ - ctl_region : 8, /* enum RegdbCtl */ - rsvd : 8; - }; - A_UINT32 flag_info; - }; - union { - struct { - A_UINT32 is_psd : 1, - rsvd1 : 15, - psd_power : 16; /* dBm / MHz */ - }; - A_UINT32 psd_power_info; - }; -} htt_stats_regdb_reg_rule_t; - -#define HTT_STATS_REGDB_REG_RULE_GET_START_FREQ(word) \ - HTT_STATS_GET_FIELD(0xFFFF, 0, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_START_FREQ(word, value) \ - HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value)) - -#define HTT_STATS_REGDB_REG_RULE_GET_END_FREQ(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_END_FREQ(word, value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - -#define HTT_STATS_REGDB_REG_RULE_GET_MAX_BW(word) \ - HTT_STATS_GET_FIELD(0xFFFF, 0, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_MAX_BW(word, value) \ - HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value)) - -#define HTT_STATS_REGDB_REG_RULE_GET_REG_POWER(word) \ - HTT_STATS_GET_FIELD(0xFF0000, 16, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_REG_POWER(word, value) \ - HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value)) - -#define HTT_STATS_REGDB_REG_RULE_GET_ANT_GAIN(word) \ - HTT_STATS_GET_FIELD(0xFF000000, 24, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_ANT_GAIN(word, value) \ - HTT_STATS_SET_FIELD(0xFF000000, 24, (word), (value)) - -#define HTT_STATS_REGDB_REG_RULE_GET_FLAGS(word) \ - HTT_STATS_GET_FIELD(0xFFFF, 0, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_FLAGS(word, value) \ - HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value)) - -#define HTT_STATS_REGDB_REG_RULE_GET_CTL_REGION(word) \ - HTT_STATS_GET_FIELD(0xFF0000, 16, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_CTL_REGION(word, value) \ - HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value)) - -#define HTT_STATS_REGDB_REG_RULE_GET_IS_PSD(word) \ - HTT_STATS_GET_FIELD(0x1, 0, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_IS_PSD(word, value) \ - HTT_STATS_SET_FIELD(0x1, 0, (word), (value)) - -#define HTT_STATS_REGDB_REG_RULE_GET_PSD_POWER(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -#define HTT_STATS_REGDB_REG_RULE_SET_PSD_POWER(word, value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - -typedef enum { - HTT_STATS_REGULATORY_REG_DMN_2G = 0, - HTT_STATS_REGULATORY_REG_DMN_5G = 1, - /* 2 is unused to allow octal grouping for 6G */ - HTT_STATS_REGULATORY_REG_DMN_6G_AP_LPI = 3, - HTT_STATS_REGULATORY_REG_DMN_6G_AP_SP = 4, - HTT_STATS_REGULATORY_REG_DMN_6G_AP_VLP = 5, - HTT_STATS_REGULATORY_REG_DMN_6G_CL1_LPI = 6, - HTT_STATS_REGULATORY_REG_DMN_6G_CL1_SP = 7, - HTT_STATS_REGULATORY_REG_DMN_6G_CL1_VLP = 8, - HTT_STATS_REGULATORY_REG_DMN_6G_CL2_LPI = 9, - HTT_STATS_REGULATORY_REG_DMN_6G_CL2_SP = 10, - HTT_STATS_REGULATORY_REG_DMN_6G_CL2_VLP = 11, -} htt_stats_regulatory_rd_type; - -#define HTT_STATS_REGULATORY_REG_DMN_6G_AP(power_mode) \ - (HTT_STATS_REGULATORY_REG_DMN_6G_AP_LPI + (power_mode)) -#define HTT_STATS_REGULATORY_REG_DMN_6G_CL(cl,power_mode) \ - (HTT_STATS_REGULATORY_REG_DMN_6G_CL1_LPI +(cl)*3 + (power_mode)) - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 rd_type; /* enum htt_stats_regulatory_rd_type */ - union { - struct { - A_UINT32 ctl_region : 8, /* enum RegdbCtl */ - cca_region : 8, /* enum CCA_REGION_MAP */ - dfs_region : 8, /* enum WMI_REG_DFS_REGION */ - domain_ctl_index : 8; - }; - A_UINT32 ctl_cca_dfs; - }; - A_UINT32 rd_code; /* from regdb.bin */ - /* - * Due to variable length array at end, this struture cannot be extended - * further. Hence use this reserved for any future parameters. - */ - A_UINT32 reserved; - union { - struct { - A_UINT32 num_rules : 16, /* number of elements in 'rules' array */ - rule_size : 16; /* size of single 'rule' in bytes */ - }; - A_UINT32 rule_num_and_size; - }; - htt_stats_regdb_reg_rule_t rules[1]; -} htt_stats_regdb_regdomain_tlv; - -#define HTT_STATS_REGDB_REGDOMAIN_GET_CTL_REGION(word) \ - HTT_STATS_GET_FIELD(0xFF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_REGDOMAIN_CTL_REGION_GET(word) \ - HTT_STATS_REGDB_REGDOMAIN_GET_CTL_REGION(word) -#define HTT_STATS_REGDB_REGDOMAIN_SET_CTL_REGION(word,value) \ - HTT_STATS_SET_FIELD(0xFF, 0, (word), (value)) - -#define HTT_STATS_REGDB_REGDOMAIN_GET_CCA_REGION(word) \ - HTT_STATS_GET_FIELD(0xFF00, 8, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_REGDOMAIN_CCA_REGION_GET(word) \ - HTT_STATS_REGDB_REGDOMAIN_GET_CCA_REGION(word) -#define HTT_STATS_REGDB_REGDOMAIN_SET_CCA_REGION(word,value) \ - HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value)) - -#define HTT_STATS_REGDB_REGDOMAIN_GET_DFS_REGION(word) \ - HTT_STATS_GET_FIELD(0xFF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_REGDOMAIN_DFS_REGION_GET(word) \ - HTT_STATS_REGDB_REGDOMAIN_GET_DFS_REGION(word) -#define HTT_STATS_REGDB_REGDOMAIN_SET_DFS_REGION(word,value) \ - HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value)) - -#define HTT_STATS_REGDB_REGDOMAIN_GET_DOMAIN_CTL_INDEX(word) \ - HTT_STATS_GET_FIELD(0xFF000000, 24, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_REGDOMAIN_DOMAIN_CTL_INDEX_GET(word) \ - HTT_STATS_REGDB_REGDOMAIN_GET_DOMAIN_CTL_INDEX(word) -#define HTT_STATS_REGDB_REGDOMAIN_SET_DOMAIN_CTL_INDEX(word,value) \ - HTT_STATS_SET_FIELD(0xFF000000, 24, (word), (value)) - - -#define HTT_STATS_REGDB_REGDOMAIN_GET_NUM_RULES(word) \ - HTT_STATS_GET_FIELD(0xFFFF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_REGDOMAIN_NUM_RULES_GET(word) \ - HTT_STATS_REGDB_REGDOMAIN_GET_NUM_RULES(word) -#define HTT_STATS_REGDB_REGDOMAIN_SET_NUM_RULES(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value)) - -#define HTT_STATS_REGDB_REGDOMAIN_GET_RULE_SIZE(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REGDB_REGDOMAIN_RULE_SIZE_GET(word) \ - HTT_STATS_REGDB_REGDOMAIN_GET_RULE_SIZE(word) -#define HTT_STATS_REGDB_REGDOMAIN_SET_RULE_SIZE(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - struct { - A_UINT32 afc_local_rsvd : 8, /* bits 7:0 */ - /* enum WMI_AFC_FEATURE_6G_DEPLOYMENT_TYPE */ - deployment_type: 8, /* bits 15:8 */ - /* Bit 0 : LPI, Bit 1 : SP, Bit 2 : VLP, others: rsvd */ - power_mode_mask: 8, /* bits 23:16 */ - reserved: 8; - }; - A_UINT32 afc_ini_params; /* AFC_INI_CONFIG */ - }; - A_UINT32 tx_allowed_reason_code; - union { - struct { - A_UINT32 set_tpc_count : 16, - set_tpc_pass_count : 16; - }; - A_UINT32 set_tpc_counters; - }; - union { - struct { - A_UINT32 - /* enum WMI_6GHZ_REG_PWRMODE_TYPE */ - current_power_mode : 4, - /* enum WMI_6GHZ_REG_PWRMODE_TYPE */ - last_best_power_mode : 4, - is_current_mode_best_power_mode : 1, - rsvd1 : 7, - best_power_mode_count : 16; - }; - A_UINT32 power_mode_stats; - }; -} htt_stats_reg_6g_tlv; - -#define HTT_STATS_REG_6G_GET_AFC_LOCAL_RSVD(word) \ - HTT_STATS_GET_FIELD(0x000000FF, 0, (word)) -#define HTT_STATS_REG_6G_SET_AFC_LOCAL_RSVD(word,value) \ - HTT_STATS_SET_FIELD(0x000000FF, 0, (word), (value)) - -#define HTT_STATS_REG_6G_GET_DEPLOYMENT_TYPE(word) \ - HTT_STATS_GET_FIELD(0x0000FF00, 8, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_DEPLOYMENT_TYPE_GET(word) \ - HTT_STATS_REG_6G_GET_DEPLOYMENT_TYPE(word) -#define HTT_STATS_REG_6G_SET_DEPLOYMENT_TYPE(word,value) \ - HTT_STATS_SET_FIELD(0x0000FF00, 8, (word), (value)) - -#define HTT_STATS_REG_6G_GET_POWER_MODE_MASK(word) \ - HTT_STATS_GET_FIELD(0x00FF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_POWER_MODE_MASK_GET(word) \ - HTT_STATS_REG_6G_GET_POWER_MODE_MASK(word) -#define HTT_STATS_REG_6G_SET_POWER_MODE_MASK(word,value) \ - HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value)) - -#define HTT_STATS_REG_6G_GET_SET_TPC_COUNT(word) \ - HTT_STATS_GET_FIELD(0xFFFF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_SET_TPC_COUNT_GET(word) \ - HTT_STATS_REG_6G_GET_SET_TPC_COUNT(word) -#define HTT_STATS_REG_6G_SET_SET_TPC_COUNT(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value)) - -#define HTT_STATS_REG_6G_GET_SET_TPC_PASS_COUNT(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_SET_TPC_PASS_COUNT_GET(word) \ - HTT_STATS_REG_6G_GET_SET_TPC_PASS_COUNT(word) -#define HTT_STATS_REG_6G_SET_SET_TPC_PASS_COUNT(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - -#define HTT_STATS_REG_6G_GET_CURRENT_POWER_MODE(word) \ - HTT_STATS_GET_FIELD(0xF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_CURRENT_POWER_MODE_GET(word) \ - HTT_STATS_REG_6G_GET_CURRENT_POWER_MODE(word) -#define HTT_STATS_REG_6G_SET_CURRENT_POWER_MODE(word,value) \ - HTT_STATS_SET_FIELD(0xF, 0, (word), (value)) - -#define HTT_STATS_REG_6G_GET_LAST_BEST_POWER_MODE(word) \ - HTT_STATS_GET_FIELD(0xF0, 4, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_LAST_BEST_POWER_MODE_GET(word) \ - HTT_STATS_REG_6G_GET_LAST_BEST_POWER_MODE(word) -#define HTT_STATS_REG_6G_SET_LAST_BEST_POWER_MODE(word,value) \ - HTT_STATS_SET_FIELD(0xF0, 4, (word), (value)) - -#define HTT_STATS_REG_6G_GET_IS_CURRENT_POWER_MODE_BEST(word) \ - HTT_STATS_GET_FIELD(0x100, 8, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_IS_CURRENT_MODE_BEST_POWER_MODE_GET(word) \ - HTT_STATS_REG_6G_GET_IS_CURRENT_POWER_MODE_BEST(word) -#define HTT_STATS_REG_6G_SET_IS_CURRENT_POWER_MODE_BEST(word,value) \ - HTT_STATS_SET_FIELD(0x100, 8, (word), (value)) - -#define HTT_STATS_REG_6G_GET_BEST_POWER_MODE_COUNT(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_BEST_POWER_MODE_COUNT_GET(word) \ - HTT_STATS_REG_6G_GET_BEST_POWER_MODE_COUNT(word) -#define HTT_STATS_REG_6G_SET_BEST_POWER_MODE_COUNT(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - -#define HTT_STATS_REG_POWER_INFO_6G_MAX_SUBBANDS 16 - - -typedef struct { - union { - struct { - A_UINT32 freq : 16, /* in MHz */ - power : 16; /* in 0.25 dBm signed */ - }; - A_UINT32 freq_power_pair; - }; - /* - * NOTE: no new fields can be added to this struct - * due to backwards-compatibility constraints. - */ -} htt_stats_reg_freq_power_pair_t; - -#define HTT_STATS_REG_FREQ_POWER_PAIR_GET_FREQ_VALUE(word) \ - HTT_STATS_GET_FIELD(0xFFFF, 0, (word)) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_TX_POWER_FREQ_PAIR_FREQ_GET(word) \ - HTT_STATS_REG_FREQ_POWER_PAIR_GET_FREQ_VALUE(word) -#define HTT_STATS_REG_6G_CH_PWR_INFO_PSD_POWER_FREQ_PAIR_FREQ_GET(word) \ - HTT_STATS_REG_FREQ_POWER_PAIR_GET_FREQ_VALUE(word) -#define HTT_STATS_REG_6G_CH_PWR_INFO_EIRP_POWER_FREQ_PAIR_FREQ_GET(word) \ - HTT_STATS_REG_FREQ_POWER_PAIR_GET_FREQ_VALUE(word) -#define HTT_STATS_REG_FREQ_POWER_PAIR_SET_FREQ_VALUE(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value)) - -#define HTT_STATS_REG_FREQ_POWER_PAIR_GET_POWER_VALUE(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -/* provide alias macros that use preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_TX_POWER_FREQ_PAIR_POWER_GET(word) \ - HTT_STATS_REG_FREQ_POWER_PAIR_GET_POWER_VALUE(word) -#define HTT_STATS_REG_6G_CH_PWR_INFO_PSD_POWER_FREQ_PAIR_POWER_GET(word) \ - HTT_STATS_REG_FREQ_POWER_PAIR_GET_POWER_VALUE(word) -#define HTT_STATS_REG_6G_CH_PWR_INFO_EIRP_POWER_FREQ_PAIR_POWER_GET(word) \ - HTT_STATS_REG_FREQ_POWER_PAIR_GET_POWER_VALUE(word) -#define HTT_STATS_REG_FREQ_POWER_PAIR_SET_POWER_VALUE(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 index; - union { - A_UINT32 power_info_word; - struct { - A_UINT32 power_type_6ghz : 8, /* enum WMI_6GHZ_REG_PWRMODE_TYPE */ - eirp_power : 8, /* in dBm */ - is_psd_power : 1, - both_psd_eirp_support : 1, - rsvd :14; - }; - }; - union { - A_UINT32 num_levels_word; - struct { - A_UINT32 num_power_levels : 8, - num_psd_levels : 8, - num_eirp_levels : 8, - unused : 8; - }; - }; - A_UINT32 puncture_bitmap; - htt_stats_reg_freq_power_pair_t - tx_power_freq_pair[HTT_STATS_REG_POWER_INFO_6G_MAX_SUBBANDS]; - htt_stats_reg_freq_power_pair_t - psd_power_freq_pair[HTT_STATS_REG_POWER_INFO_6G_MAX_SUBBANDS]; - htt_stats_reg_freq_power_pair_t - eirp_power_freq_pair[HTT_STATS_REG_POWER_INFO_6G_MAX_SUBBANDS]; -} htt_stats_reg_6g_ch_pwr_info_tlv; -/* preserve old name alias for new name consistent with the tag name */ -typedef htt_stats_reg_6g_ch_pwr_info_tlv - htt_stats_reg_6g_ch_power_info_tlv; - -#define HTT_STATS_REG_6G_GET_POWER_TYPE(word) \ - HTT_STATS_GET_FIELD(0xFF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_POWER_TYPE_6GHZ_GET(word) \ - HTT_STATS_REG_6G_GET_POWER_TYPE(word) -#define HTT_STATS_REG_6G_SET_POWER_TYPE(word,value) \ - HTT_STATS_SET_FIELD(0xFF, 0, (word), (value)) - -#define HTT_STATS_REG_6G_GET_EIRP_POWER(word) \ - HTT_STATS_GET_FIELD(0xFF00, 8, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_EIRP_POWER_GET(word) \ - HTT_STATS_REG_6G_GET_EIRP_POWER(word) -#define HTT_STATS_REG_6G_SET_EIRP_POWER(word,value) \ - HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value)) - -#define HTT_STATS_REG_6G_GET_IS_PSD(word) \ - HTT_STATS_GET_FIELD(0x10000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_IS_PSD_POWER_GET(word) \ - HTT_STATS_REG_6G_GET_IS_PSD(word) -#define HTT_STATS_REG_6G_SET_IS_PSD(word,value) \ - HTT_STATS_SET_FIELD(0x10000, 16, (word), (value)) - -#define HTT_STATS_REG_6G_GET_BOTH_PSD_EIRP_SUPPORT(word) \ - HTT_STATS_GET_FIELD(0x20000, 17, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_BOTH_PSD_EIRP_SUPPORT_GET(word) \ - HTT_STATS_REG_6G_GET_BOTH_PSD_EIRP_SUPPORT(word) -#define HTT_STATS_REG_6G_SET_BOTH_PSD_EIRP_SUPPORT(word,value) \ - HTT_STATS_SET_FIELD(0x20000, 17, (word), (value)) - -#define HTT_STATS_REG_6G_GET_NUM_POWER_LEVELS(word) \ - HTT_STATS_GET_FIELD(0xFF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_NUM_POWER_LEVELS_GET(word) \ - HTT_STATS_REG_6G_GET_NUM_POWER_LEVELS(word) -#define HTT_STATS_REG_6G_SET_NUM_POWER_LEVELS(word,value) \ - HTT_STATS_SET_FIELD(0xFF, 0, (word), (value)) - -#define HTT_STATS_REG_6G_GET_NUM_PSD_LEVELS(word) \ - HTT_STATS_GET_FIELD(0xFF00, 8, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_NUM_PSD_LEVELS_GET(word) \ - HTT_STATS_REG_6G_GET_NUM_PSD_LEVELS(word) -#define HTT_STATS_REG_6G_SET_NUM_PSD_LEVELS(word,value) \ - HTT_STATS_SET_FIELD(0xFF00, 8, (word), (value)) - -#define HTT_STATS_REG_6G_GET_NUM_EIRP_LEVELS(word) \ - HTT_STATS_GET_FIELD(0xFF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_CH_PWR_INFO_NUM_EIRP_LEVELS_GET(word) \ - HTT_STATS_REG_6G_GET_NUM_EIRP_LEVELS(word) -#define HTT_STATS_REG_6G_SET_NUM_EIRP_LEVELS(word,value) \ - HTT_STATS_SET_FIELD(0xFF0000, 16, (word), (value)) - -#define HTT_STATS_REG_OOBE_MAX_BW 5 -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_INT32 oobe_psd[HTT_STATS_REG_OOBE_MAX_BW]; /* dBm / MHz */ - union { - struct { - A_INT32 oobe_limit_offset : 16, /* in MHz */ - oobe_limit_psd : 16; /* in dBr */ - }; - A_UINT32 offset_mask_pair; - } oobe_limit[HTT_STATS_REG_OOBE_MAX_BW]; -} htt_stats_reg_6g_oobe_tlv; - -#define HTT_STATS_REG_6G_GET_OOBE_LIMIT_OFFSET(word) \ - HTT_STATS_GET_FIELD(0xFFFF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_OOBE_OOBE_LIMIT_OOBE_LIMIT_OFFSET_GET(word) \ - HTT_STATS_REG_6G_GET_OOBE_LIMIT_OFFSET(word) -#define HTT_STATS_REG_6G_SET_OOBE_LIMIT_OFFSET(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF, 0, (word), (value)) - -#define HTT_STATS_REG_6G_GET_OOBE_LIMIT_PSD(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_REG_6G_OOBE_OOBE_LIMIT_OOBE_LIMIT_PSD_GET(word) \ - HTT_STATS_REG_6G_GET_OOBE_LIMIT_PSD(word) -#define HTT_STATS_REG_6G_SET_OOBE_LIMIT_PSD(word,value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_INT32 array_gain_cap[HTT_STATS_MAX_CHAINS * ((HTT_STATS_MAX_CHAINS/2)+1)]; - union { - struct { - A_UINT32 - /** To indicate Reg rule Index picked from Reg rules */ - regRuleIndex:16, - /** To indicate Power rule Index picked from Reg rules */ - powerRuleIndex:8, - reserved:8; - }; - A_UINT32 ctl_args; - }; -} htt_stats_ctl_tlv; - -#define HTT_STATS_CTL_GET_REG_RULE_INDEX(word) \ - HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_CTL_REGRULEINDEX_GET(word) \ - HTT_STATS_CTL_GET_REG_RULE_INDEX(word) -#define HTT_STATS_CTL_SET_REG_RULE_INDEX(word,value) \ - HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value)) - -#define HTT_STATS_CTL_GET_POWER_RULE_INDEX(word) \ - HTT_STATS_GET_FIELD(0x00FF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_CTL_POWERRULEINDEX_GET(word) \ - HTT_STATS_CTL_GET_POWER_RULE_INDEX(word) -#define HTT_STATS_CTL_SET_POWER_RULE_INDEX(word,value) \ - HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value)) - - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - struct { - A_UINT32 - /** To indicate enablement of enhanced CTL */ - enhancedCtlEnable:1, - rsvd:7, - domainCtlIndex:8, /** Domain CTL Index */ - array_gain_cap_ctlRegion:8, /** Array gain CapCTLregion */ - exceptionCtlRegion:8; /** Exception CTL region */ - }; - A_UINT32 enhanced_ctl_args; - }; -} htt_stats_enhanced_ctl_tlv; - -#define HTT_STATS_ENHANCED_CTL_GET_ENHANCED_CTL_ENABLE(word) \ - HTT_STATS_GET_FIELD(0x00000001, 0, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_ENHANCED_CTL_ENHANCEDCTLENABLE_GET(word) \ - HTT_STATS_ENHANCED_CTL_GET_ENHANCED_CTL_ENABLE(word) -#define HTT_STATS_ENHANCED_CTL_SET_ENHANCED_CTL_ENABLE(word,value) \ - HTT_STATS_SET_FIELD(0x00000001, 0, (word), (value)) - -#define HTT_STATS_ENHANCED_CTL_GET_DOMAIN_CTL_INDEX(word) \ - HTT_STATS_GET_FIELD(0x0000FF00, 8, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_ENHANCED_CTL_DOMAINCTLINDEX_GET(word) \ - HTT_STATS_ENHANCED_CTL_GET_DOMAIN_CTL_INDEX(word) -#define HTT_STATS_ENHANCED_CTL_SET_DOMAIN_CTL_INDEX(word,value) \ - HTT_STATS_SET_FIELD(0x0000FF00, 8, (word), (value)) - -#define HTT_STATS_ENHANCED_CTL_GET_ARRAY_GAIN_CAP_CTL_REGION(word) \ - HTT_STATS_GET_FIELD(0x00FF0000, 16, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_ENHANCED_CTL_ARRAY_GAIN_CAP_CTLREGION_GET(word) \ - HTT_STATS_ENHANCED_CTL_GET_ARRAY_GAIN_CAP_CTL_REGION(word) -#define HTT_STATS_ENHANCED_CTL_SET_ARRAY_GAIN_CAP_CTL_REGION(word,value) \ - HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value)) - -#define HTT_STATS_ENHANCED_CTL_GET_EXCEPTION_CTL_REGION(word) \ - HTT_STATS_GET_FIELD(0xFF000000, 24, (word)) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_ENHANCED_CTL_EXCEPTIONCTLREGION_GET(word) \ - HTT_STATS_ENHANCED_CTL_GET_EXCEPTION_CTL_REGION(word) -#define HTT_STATS_ENHANCED_CTL_SET_EXCEPTION_CTL_REGION(word,value) \ - HTT_STATS_SET_FIELD(0xFF000000, 24, (word), (value)) - - -#define HTT_STATS_DFS_RADAR_HISTORY_MAX_ENTRIES 5 - -/** - * @brief TLV structure for wifistats 83 (radar history) - * This structure holds the last 5 radar history detected. - */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - struct { - union { - A_UINT32 freq_det_info; - struct { - A_UINT32 chan_freq:16, /* MHz units */ - detector_id:8, - is_chirp:1, /* Chirp radar pulse detected */ - rsvd1:7; - }; - }; - union { - A_UINT32 rssi_pulse_info; - struct { - A_UINT32 rf_pulseid:16, - radar_rssi_dbm:8, - rsvd2:8; - }; - }; - union { - A_UINT32 domain_type_info; - struct { - A_UINT32 domain:8, - type:8, - rf_radar_type:8, - rsvd3:8; - }; - }; - union { - A_UINT32 sidx_freq_info; - struct { - A_UINT32 sidx:16, - freq_offset:16; - }; - }; - union { - A_UINT32 dur_info; - struct { - A_UINT32 rf_mindur:16, /* us */ - rf_maxdur:16; /* us */ - }; - }; - union { - A_UINT32 threshold_info; - struct { - A_UINT32 rf_threshold:16, /* units = dBm */ - rsvd4:16; - }; - }; - union { - A_UINT32 pri_info; - struct { - A_UINT32 rf_minpri:16, /* us */ - rf_maxpri:16; /* us */ - }; - }; - } radar_entry_stats[HTT_STATS_DFS_RADAR_HISTORY_MAX_ENTRIES]; - A_UINT32 idx; /* next write position */ - A_UINT32 count; /* valid entries in buffer */ -} htt_stats_dfs_radar_history_tlv; - -/* - * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats - * freq_det_info (word 0) - */ -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_CHAN_FREQ_GET(word) \ - HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_CHAN_FREQ_SET(word, value) \ - HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value)) - -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_DETECTOR_ID_GET(word) \ - HTT_STATS_GET_FIELD(0x00FF0000, 16, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_DETECTOR_ID_SET(word, value) \ - HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value)) - -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_IS_CHIRP_GET(word) \ - HTT_STATS_GET_FIELD(0x01000000, 24, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_IS_CHIRP_SET(word, value) \ - HTT_STATS_SET_FIELD(0x01000000, 24, (word), (value)) - -/* - * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats - * rssi_pulse_info (word 1) - */ -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_PULSEID_GET(word) \ - HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_PULSEID_SET(word, value) \ - HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value)) - -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RADAR_RSSI_DBM_GET(word) \ - ((A_INT8)HTT_STATS_GET_FIELD(0x00FF0000, 16, (word))) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RADAR_RSSI_DBM_SET(word, value) \ - HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (A_UINT8)(value)) - -/* - * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats - * domain_type_info (word 2) - */ -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_DOMAIN_GET(word) \ - HTT_STATS_GET_FIELD(0x000000FF, 0, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_DOMAIN_SET(word, value) \ - HTT_STATS_SET_FIELD(0x000000FF, 0, (word), (value)) - -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_TYPE_GET(word) \ - HTT_STATS_GET_FIELD(0x0000FF00, 8, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_TYPE_SET(word, value) \ - HTT_STATS_SET_FIELD(0x0000FF00, 8, (word), (value)) - -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_RADAR_TYPE_GET(word) \ - HTT_STATS_GET_FIELD(0x00FF0000, 16, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_RADAR_TYPE_SET(word, value) \ - HTT_STATS_SET_FIELD(0x00FF0000, 16, (word), (value)) - -/* - * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats - * sidx_freq_info (word 3) - */ -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_SIDX_GET(word) \ - ((A_INT16)HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word))) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_SIDX_SET(word, value) \ - HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (A_UINT16)(value)) - -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_FREQ_OFFSET_GET(word) \ - ((A_INT16)HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word))) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_FREQ_OFFSET_SET(word, value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (A_UINT16)(value)) - -/* - * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats - * dur_info (word 4) - */ -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MINDUR_GET(word) \ - HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MINDUR_SET(word, value) \ - HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value)) - -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MAXDUR_GET(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MAXDUR_SET(word, value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - -/* - * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats - * threshold_info (word 5) - */ -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_THRESHOLD_GET(word) \ - HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_THRESHOLD_SET(word, value) \ - HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value)) - -/* - * Accessor macros for htt_stats_dfs_radar_history_tlv.radar_entry_stats - * pri_info (word 6) - */ -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MINPRI_GET(word) \ - HTT_STATS_GET_FIELD(0x0000FFFF, 0, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MINPRI_SET(word, value) \ - HTT_STATS_SET_FIELD(0x0000FFFF, 0, (word), (value)) - -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MAXPRI_GET(word) \ - HTT_STATS_GET_FIELD(0xFFFF0000, 16, (word)) -#define HTT_STATS_DFS_RADAR_HISTORY_RADAR_ENTRY_STATS_RF_MAXPRI_SET(word, value) \ - HTT_STATS_SET_FIELD(0xFFFF0000, 16, (word), (value)) - -/* - * Sign-extend helper for signed bitfields in DFS radar entries. - * Used for radar_rssi_dbm (8-bit), sidx (16-bit), freq_offset (16-bit). - */ -#define HTT_STATS_SIGN_EXT(val, nbits) \ - (((val) & (1u << ((nbits)-1))) ? \ - ((val) | (~0u << (nbits))) : (val)) - -/* - * Indices into htt_stats_dfs_ini_tlv.reg_val[] - * (same order as wfax_dfs_common[]) - */ -enum htt_stats_dfs_ini_reg_idx { - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_POW_DET_L = 0, /* offset 0xBC0 */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_DETECTION_U = 1, /* offset 0xBB4 */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_PULSE_THR_L = 2, /* offset 0xBF8 */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_POW_DET_U = 3, /* offset 0xBC4 */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_PULSE_THR_U = 4, /* offset 0xBFC */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_SRCH_FFT_CTRL2_0_L = 5, /* offset 0xBD8 */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_SRCH_FFT_CTRL1_U = 6, /* offset 0xBD4 */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_SRCH_FFT_CTRL2_1_L = 7, /* offset 0xBE0 */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_RADAR_DETECTION_L = 8, /* offset 0xBB0 */ - HTT_STATS_DFS_INI_WFAX_RXTD_DET0_SRCH_FFT_CTRL2_1_U = 9, /* offset 0xBE4 */ - - HTT_STATS_DFS_INI_NUM_REGS = 10 -}; - - -/* - * htt_stats_dfs_ini_tlv - DFS common register - * - * Captures current live values of the 10 wfax_dfs_common HW registers. - * reg_val[i]: current value read from hardware - * - * Use enum htt_stats_dfs_ini_reg_idx for reg_val[] index interpretation. - */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 reg_val[HTT_STATS_DFS_INI_NUM_REGS]; -} htt_stats_dfs_ini_tlv; - - -/* ======================= End DFS Channel Register Snapshot TLV ========== } */ - -/* ======================= DFS IPC Ring Stats TLV ========================= { - * Head/tail index state for the 3 DFS IPC rings read at stats query time. - * Use enum htt_stats_dfs_ipc_ring_idx for ipc_ring_stats[] index - * interpretation. - */ - -/* Indices into htt_stats_dfs_ipc_ring_tlv.ipc_ring_stats[] */ -enum htt_stats_dfs_ipc_ring_idx { - HTT_STATS_DFS_IPC_RING_DFS0 = 0, /* IPC_DFS0_RINGID (2) */ - HTT_STATS_DFS_IPC_RING_DFS1 = 1, /* IPC_DFS1_RINGID (3) */ - HTT_STATS_DFS_IPC_RING_DFS2 = 2, /* IPC_DFS2_RINGID (4) */ - - HTT_STATS_DFS_IPC_RING_COUNT = 3 /* DFS0, DFS1, DFS2 */ -}; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - struct { - A_UINT32 head_idx; - A_UINT32 shadow_head_idx; - A_UINT32 tail_idx; - A_UINT32 shadow_tail_idx; - } ipc_ring_stats[HTT_STATS_DFS_IPC_RING_COUNT]; -} htt_stats_dfs_ipc_ring_tlv; - - -/*======================= End Regulatory stats ==================== } */ - -/* - * Self response frame types. Aligning with - * WHAL_RESP_FRAMES (WHAL_MAX_RESP_FRAMES). - */ -typedef enum { - HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_11L_MBPS = 0, - HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_5_5L_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_2L_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_1L_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_11S_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_5_5S_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_CCK_2S_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_6_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_9_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_12_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_18_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_24_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_36_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_48_MBPS, - HTT_RESP_FRAME_TYPE_ACK_CTS_OFDM_54_MBPS, - HTT_RESP_FRAME_TYPE_CBF_11AC, - HTT_RESP_FRAME_TYPE_CBF_11AX, - HTT_RESP_FRAME_TYPE_CBF_11BE, - HTT_RESP_FRAME_TYPE_CBF_11AX_EXT, - HTT_RESP_FRAME_TYPE_ACK_CTS_11AX_EXT_DCM, - HTT_RESP_FRAME_TYPE_RTT_11N_MCS0, - HTT_RESP_FRAME_TYPE_RTT_11N_MCS1, - HTT_RESP_FRAME_TYPE_RTT_11N_MCS3, - HTT_RESP_FRAME_TYPE_RTT_11AC_MCS0, - HTT_RESP_FRAME_TYPE_RTT_11AC_MCS1, - HTT_RESP_FRAME_TYPE_RTT_11AC_MCS3, - HTT_RESP_FRAME_TYPE_RTT_11A_6_MBPS, - HTT_RESP_FRAME_TYPE_RTT_11A_12_MBPS, - HTT_RESP_FRAME_TYPE_RTT_11A_24_MBPS, - HTT_RESP_FRAME_TYPE_RTT_11AX_MCS0, - HTT_RESP_FRAME_TYPE_RTT_11AX_MCS1, - HTT_RESP_FRAME_TYPE_RTT_11AX_MCS3, - HTT_RESP_FRAME_TYPE_AX_BE_EXT_DEF, - HTT_RESP_FRAME_TYPE_11BE_MCS14_MCS15, - HTT_RESP_FRAME_TYPE_MAX -} HTT_RESP_FRAME_TYPES; - -/* - * This structure stores the essential fields from WHAL_RESP_FRAME_PARAMS - * that are accessed in the WHAL SELFGEN RESP FRAME STATS. - */ -typedef struct { - union { - A_UINT32 type_rate_chainmask; - struct { - A_UINT32 - /* pkt_type: - * 0 = CCK, 1 = OFDM, 2 = HT, - * 3 = VHT, 4 = HE, 5 = EHT, - */ - pkt_type : 4, /* 0-3 */ - nss : 3, /* 4-6: Number of spatial streams */ - rate_mcs : 4, /* 7-10: Rate/MCS value */ - /* bandwith: - * 0 = 20 MHz, 1 = 40 MHz, 2 = 80 MHz, 3 = 160 MHz, 4 = 320 MHz - */ - bandwidth : 3, /* 11-13 */ - chain_mask : 8, /* 14-21: Primary chain mask */ - alt_chain_mask : 8, /* 22-29: Alternate chain mask */ - reserved : 2; /* 30-31: Reserved for future use */ - }; - }; - - union { - A_UINT32 tx_pwr_alt; - struct { - A_UINT32 - tx_pwr : 8, /* 0-7: Primary TX power (dBm) */ - tx_pwr_1 : 8, /* 8-15: Secondary TX power (dBm) */ - alt_tx_pwr : 8, /* 16-23: Alternate TX power (dBm) */ - alt_tx_pwr_1 : 8; /* 24-31: Alternate secondary TX pwr (dBm) */ - }; - }; -/* - * NOTE: due to backwards-compatibility constraints, - * this struct cannot be expanded. - */ -} HTT_STATS_WHAL_SELFGEN_RESP_FRAME_ENTRY; - -/* Mask and shift definitions for type_rate_chainmask fields */ -#define HTT_STATS_WHAL_SELFGEN_PKT_TYPE_M 0x0000000F -#define HTT_STATS_WHAL_SELFGEN_PKT_TYPE_S 0 -#define HTT_STATS_WHAL_SELFGEN_NSS_M 0x00000070 -#define HTT_STATS_WHAL_SELFGEN_NSS_S 4 -#define HTT_STATS_WHAL_SELFGEN_RATE_MCS_M 0x00000780 -#define HTT_STATS_WHAL_SELFGEN_RATE_MCS_S 7 -#define HTT_STATS_WHAL_SELFGEN_BANDWIDTH_M 0x00003800 -#define HTT_STATS_WHAL_SELFGEN_BANDWIDTH_S 11 -#define HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_M 0x003FC000 -#define HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_S 14 -#define HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_M 0x3FC00000 -#define HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_S 22 - -#define HTT_STATS_WHAL_SELFGEN_PKT_TYPE_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_PKT_TYPE_M) >> \ - HTT_STATS_WHAL_SELFGEN_PKT_TYPE_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_PKT_TYPE_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_PKT_TYPE_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_PKT_TYPE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_PKT_TYPE, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_PKT_TYPE_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_NSS_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_NSS_M) >> \ - HTT_STATS_WHAL_SELFGEN_NSS_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_NSS_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_NSS_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_NSS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_NSS, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_NSS_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_RATE_MCS_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_RATE_MCS_M) >> \ - HTT_STATS_WHAL_SELFGEN_RATE_MCS_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_RATE_MCS_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_RATE_MCS_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_RATE_MCS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_RATE_MCS, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_RATE_MCS_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_BANDWIDTH_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_BANDWIDTH_M) >> \ - HTT_STATS_WHAL_SELFGEN_BANDWIDTH_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_BANDWIDTH_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_BANDWIDTH_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_BANDWIDTH_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_BANDWIDTH, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_BANDWIDTH_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_M) >> \ - HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_CHAIN_MASK_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_CHAIN_MASK, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_CHAIN_MASK_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_M) >> \ - HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_ALT_CHAIN_MASK_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_ALT_CHAIN_MASK_S)); \ - } while (0) - -/* Mask and shift definitions for tx_pwr_alt fields */ -#define HTT_STATS_WHAL_SELFGEN_TX_PWR_M 0x000000FF -#define HTT_STATS_WHAL_SELFGEN_TX_PWR_S 0 -#define HTT_STATS_WHAL_SELFGEN_TX_PWR_1_M 0x0000FF00 -#define HTT_STATS_WHAL_SELFGEN_TX_PWR_1_S 8 -#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_M 0x00FF0000 -#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_S 16 -#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_M 0xFF000000 -#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_S 24 - -#define HTT_STATS_WHAL_SELFGEN_TX_PWR_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_TX_PWR_M) >> \ - HTT_STATS_WHAL_SELFGEN_TX_PWR_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_TX_PWR_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_TX_PWR_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_TX_PWR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_TX_PWR, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_TX_PWR_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_TX_PWR_1_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_TX_PWR_1_M) >> \ - HTT_STATS_WHAL_SELFGEN_TX_PWR_1_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_TX_PWR_1_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_TX_PWR_1_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_TX_PWR_1_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_TX_PWR_1, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_TX_PWR_1_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_M) >> \ - HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_ALT_TX_PWR_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_GET(_var) \ - (((_var) & HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_M) >> \ - HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_FRAME_DATA_ALT_TX_PWR_1_GET(_var) \ - HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_GET(_var) -#define HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1, _val); \ - ((_var) |= ((_val) << HTT_STATS_WHAL_SELFGEN_ALT_TX_PWR_1_S)); \ - } while (0) - -/** - * HTT_STATS_WHAL_SELFGEN_CHANNEL_CONTEXT - Channel context information - * - * This structure stores common channel context information that is - * NOT per frame. - * It contains channel frequency, flags, and PHY mode information that applies - * to all self-generated response frames. - */ -typedef struct { - union { - A_UINT32 channel_info; - struct { - A_UINT32 - mhz : 16, /* 0-15: Channel frequency in MHz */ - /* flags: - * Channel flags, with a FW-internal definition of flag values. - * This fields is intended only for debugging, since the - * definitions of the flag values are not provided. - */ - flags : 16; /* 16-31 */ - }; - }; - A_UINT32 phy_mode; /* PHY mode (WLAN_PHY_MODE: 11a/11g/11ax/11be etc.) */ -/* - * NOTE: due to backwards-compatibility constraints, - * this struct cannot be expanded. - */ -} HTT_STATS_WHAL_SELFGEN_CHANNEL_CONTEXT; - -#define HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_M 0x0000FFFF -#define HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_S 0 -#define HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_M 0xFFFF0000 -#define HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_S 16 - -#define HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_GET(_var) \ - (((_var).channel_context.channel_info & \ - HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_M) >> \ - HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_S) -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_CHANNEL_CONTEXT_MHZ_GET(word) \ - (((word) >> 0) & 0xffff) -#define HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ, _val); \ - ((_var).channel_context.channel_info |= \ - ((_val) << HTT_STATS_WHAL_SELFGEN_CHANNEL_MHZ_S)); \ - } while (0) - -#define HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_GET(_var) \ - (((_var).channel_context.channel_info & \ - HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_M) >> \ - HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_S) -#define HTT_STATS_TX_SELFGEN_RESP_FRAME_STATS_CHANNEL_CONTEXT_FLAGS_GET(word) \ - (((word) >> 16) & 0xffff) -#define HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS, _val); \ - ((_var).channel_context.channel_info |= \ - ((_val) << HTT_STATS_WHAL_SELFGEN_CHANNEL_FLAGS_S)); \ - } while (0) - -/* - * Statistics for self-generated response frames Rate, Pkt type, Chainmask. - * Has context that was captured when it was programmed. - */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* Common channel context - NOT per frame */ - HTT_STATS_WHAL_SELFGEN_CHANNEL_CONTEXT channel_context; - /* Array indexed by WHAL_RESP_FRAMES enum values */ - HTT_STATS_WHAL_SELFGEN_RESP_FRAME_ENTRY frame_data[HTT_RESP_FRAME_TYPE_MAX]; -} htt_stats_tx_selfgen_resp_frame_stats_tlv; - - -#define HTT_STATS_NUM_DPD_CAL_TABLE 12 - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 pdev_id; - A_UINT32 dpd_cal_start_time; /* ms units */ - A_UINT32 dpd_cal_end_time; /* ms units */ - A_UINT32 total_tx_pass_cnt; - A_UINT32 total_tx_fail_cnt; - /* dpd_trigger_reason: - * The definition of trigger reasons is internal to the - * target FW, hence, this field is opaque to the host and cannot be - * interpreted; this field is intended only for manual debugging. - */ - A_UINT32 dpd_trigger_reason; - /* dpd_training_temp: units = Celsius degrees */ - A_INT32 dpd_training_temp[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; - A_INT32 cal_start_temp; /* Celsius degrees */ - A_INT32 cal_end_temp; /* Celsius degrees */ - A_UINT32 cal_channel; /* MHz */ - A_UINT32 cal_phy_mode; /* WLAN_PHY_MODE */ - A_UINT32 cal_chan_flags; /* HTT_STATS_CHANNEL_FLAGS */ - A_UINT32 mem_dpd_post_proc_trigger_cnt; - A_UINT32 mem_dpd_post_proc_complete_cnt; - /* sch_cmd_result_per_chain: - * The definition of scheduler command results is internal to the - * target FW, hence, this field is opaque to the host and cannot be - * interpreted; this field is intended only for manual debugging. - */ - A_UINT32 sch_cmd_result_per_chain[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; - /* tx_status_per_chain: 0 = success, 1 = abort, 2 = error */ - A_UINT32 tx_status_per_chain[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; - /* dpd_cal_state: - * The definition of cal states is internal to the - * target FW, hence, this field is opaque to the host and cannot be - * interpreted; this field is intended only for manual debugging. - */ - A_UINT32 dpd_cal_state; - A_UINT32 dpd_cal_status; /* 1 = success, 0 = failure */ - /* dpd_fail_reason: - * The definition of DPD cal failure reasons is internal to the - * target FW, hence, this field is opaque to the host and cannot be - * interpreted; this field is intended only for manual debugging. - */ - A_UINT32 dpd_fail_reason; -} htt_stats_dpd_halphy_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 dpd_rx_gain[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; - A_UINT32 tpc_gain_idx[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; - A_UINT32 tpc_glut[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; -} htt_stats_dpd_hw_cal_params_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* Signal Quality */ - A_UINT32 sq_value[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; - A_UINT32 sq_idx[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; - A_INT32 nmse_chain[HTT_STATS_MAX_CHAINS][HTT_STATS_NUM_DPD_CAL_TABLE]; -} htt_stats_dpd_hw_cal_results_tlv; - -typedef struct { - htt_tlv_hdr_t tlv_hdr; - A_UINT32 mu_rts_tx_success; - A_UINT32 mu_rts_tx_fail; - A_UINT32 mu_rts_rx_success; - A_UINT32 bsrp_ntb_tx_success; - A_UINT32 bsrp_ntb_tx_fail; - A_UINT32 bsrp_ntb_rx_success; - A_UINT32 bsrp_tx_success; - A_UINT32 bsrp_tx_fail; - A_UINT32 bsrp_rx_success; - A_UINT32 npca_tx_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - A_UINT32 npca_su_tx_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; - A_UINT32 npca_rx_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - A_UINT32 npca_su_rx_punctured_mode[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - A_UINT32 schd_cmd_result_npca[HTT_STATS_MAX_SCH_CMD_RESULT]; - htt_tx_rate_stats_t npca_per_bw[HTT_TX_PDEV_STATS_NUM_BN_BW_COUNTERS]; - htt_tx_rate_stats_t npca_per_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; -} htt_stats_npca_tlv; - - -/*===================== Start PHY DPD/TPC Debug stats ==================== { */ - -typedef enum { - HTT_STATS_PHY_DPD_TPC_DEBUG_SUBTYPE_DPD = 0, - HTT_STATS_PHY_DPD_TPC_DEBUG_SUBTYPE_TPC = 1, - HTT_STATS_PHY_DPD_TPC_DEBUG_SUBTYPE_MAX -} htt_stats_phy_dpd_tpc_debug_subtype_t; - -/* - * htt_stats_phy_dpd_debug_params_v1 - * Per-table DPD debug parameters. All fields packed into A_UINT32 words. - * - * Word 0: dpd_out_nmse_x10 (signed 32-bit, 1/10 dB units) - * Word 1: pa_max_avg_tx (unsigned 32-bit, dBm units) - * Word 2: dpd_training_cnt (unsigned 32-bit) - * Word 3: dpd_scaling (unsigned 32-bit) - * Word 4: BIT[15:0] dpd_training_power_db8 (signed 16-bit, 1/8 dB units) - * BIT[31:16] dpd_out_sq (unsigned 16-bit) - * Word 5: BIT[ 7:0] dpd_state - * BIT[15:8] dpd_in_glut - * BIT[23:16] dpd_in_tx_gain - * BIT[31:24] dpd_out_train_dac_gain (signed 8-bit) - * Word 6: BIT[ 7:0] dpd_in_gc (signed 8-bit) - * BIT[15:8] dpd_out_sq_idx - * BIT[23:16] dpd_out_train_rx_gain_idx - * BIT[31:24] dpd_in_kernel_sel - */ -typedef struct { - A_INT32 dpd_out_nmse_x10; - A_UINT32 pa_max_avg_tx; - A_UINT32 dpd_training_cnt; - A_UINT32 dpd_scaling; - union { - A_UINT32 dpd_training_power_db8__dpd_out_sq; - struct { - A_UINT32 - dpd_training_power_db8: 16, - dpd_out_sq: 16; - }; - }; - union { - A_UINT32 dpd_state__dpd_in_glut__dpd_in_tx_gain__dpd_out_train_dac_gain; - struct { - A_UINT32 - dpd_state: 8, - dpd_in_glut: 8, - dpd_in_tx_gain: 8, - dpd_out_train_dac_gain: 8; - }; - }; - union { - A_UINT32 dpd_in_gc__dpd_out_sq_idx__dpd_out_train_rx_gain_idx__dpd_in_kernel_sel; - struct { - A_UINT32 - dpd_in_gc: 8, - dpd_out_sq_idx: 8, - dpd_out_train_rx_gain_idx: 8, - dpd_in_kernel_sel: 8; - }; - }; -} htt_stats_phy_dpd_debug_params_v1; - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_M 0x0000ffff -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_S 0 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_M 0xffff0000 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_S 16 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_M 0x000000ff -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_S 0 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_M 0x0000ff00 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_S 8 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_M 0x00ff0000 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_S 16 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_M 0xff000000 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_S 24 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_M 0x000000ff -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_S 0 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_M 0x0000ff00 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_S 8 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_M 0x00ff0000 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_S 16 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_M 0xff000000 -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_S 24 - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_TRAINING_POWER_DB8_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_TRAINING_POWER_DB8_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_OUT_SQ_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_STATE_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_STATE_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_IN_GLUT_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GLUT_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_IN_TX_GAIN_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_TX_GAIN_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_OUT_TRAIN_DAC_GAIN_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_DAC_GAIN_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_IN_GC_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_GET(_var) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_GC_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_OUT_SQ_IDX_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_SQ_IDX_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_OUT_TRAIN_RX_GAIN_IDX_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_OUT_TRAIN_RX_GAIN_IDX_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_S) -/* provide alias macro that uses preferred naming convention */ -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_DPD_DEBUG_PARAMS_DPD_IN_KERNEL_SEL_GET(_var) \ - HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_GET(_var) -#define HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_PARAMS_IN_KERNEL_SEL_S)); \ - } while (0) - -/* - * htt_stats_phy_dpd_debug_chain_v1_tlv - * One TLV per chain. chain_idx identifies which chain this TLV carries. - * - * Word 0 (after tlv_hdr): - * BIT[ 7: 0] - chain_idx - * BIT[15: 8] - version - * BIT[31:16] - chainmask - * Word 1: - * BIT[ 7: 0] - num_gain_idx - * BIT[31: 8] - reserved - */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - union { - A_UINT32 chain_idx__version__chainmask; - struct { - A_UINT32 - chain_idx: 8, - version: 8, - chainmask: 16; - }; - }; - union { - A_UINT32 num_gain_idx__reserved; - struct { - A_UINT32 - num_gain_idx: 8, - reserved: 24; - }; - }; - htt_stats_phy_dpd_debug_params_v1 dpd_debug_params[HTT_STATS_NUM_DPD_CAL_TABLE]; -} htt_stats_phy_dpd_debug_chain_v1_tlv; - -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_M 0x000000ff -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_S 0 -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_M 0x0000ff00 -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_S 8 -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_M 0xffff0000 -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_S 16 - -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_M 0x000000ff -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_S 0 - -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_S) -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAIN_IDX_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_S) -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_VERSION_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_S) -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_CHAINMASK_S)); \ - } while (0) - -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_M) >> \ - HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_S) -#define HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_DPD_DEBUG_CHAIN_V1_NUM_GAIN_IDX_S)); \ - } while (0) - -/* - * htt_stats_phy_tpc_debug_chain_v1_tlv - * One TLV per chain. All sub-byte/sub-word fields packed into A_UINT32 words. - * - * Word 0 (after tlv_hdr): - * BIT[ 7: 0] - chain_idx - * BIT[15: 8] - version - * BIT[31:16] - chainmask - * - * Words 1-11: TPC per-chain debug params (all A_UINT32) - */ -typedef struct { - htt_tlv_hdr_t tlv_hdr; - /* - * Word 0: BIT[ 7: 0]=chain_idx - * BIT[15: 8]=version - * BIT[31:16]=chainmask - */ - union { - A_UINT32 chain_idx__version__chainmask; - struct { - A_UINT32 - chain_idx: 8, - version: 8, - chainmask: 16; - }; - }; - /* - * Word 1: BIT[7:0]=lat_glut_idx, - * BIT[15:8]=lat_tx_gain_idx, - * BIT[23:16]=lat_dac_gain(s8), - * BIT[31:24]=lat_target_power(s8) - */ - union { - A_UINT32 lat_glut_idx__lat_tx_gain_idx__lat_dac_gain__lat_target_power; - struct { - A_UINT32 - lat_glut_idx: 8, - lat_tx_gain_idx: 8, - lat_dac_gain: 8, - lat_target_power: 8; - }; - }; - /* - * Word 2: BIT[15:0]=lat_acc_clpc_error(s16), - * BIT[31:16]=lat_clpc_err(s16) - */ - union { - A_UINT32 lat_acc_clpc_error__lat_clpc_err; - struct { - A_UINT32 - lat_acc_clpc_error: 16, - lat_clpc_err: 16; - }; - }; - /* - * Word 3: BIT[15:0]=lat_meas_pwr(s16), - * BIT[23:16]=lat_wsi_temp_valid, - * BIT[31:24]=lat_wsi_full_pkt_pwr_valid - */ - union { - A_UINT32 lat_meas_pwr__lat_wsi_temp_valid__lat_wsi_full_pkt_pwr_valid; - struct { - A_UINT32 - lat_meas_pwr: 16, - lat_wsi_temp_valid: 8, - lat_wsi_full_pkt_pwr_valid: 8; - }; - }; - /* - * Word 4: BIT[7:0]=lat_wsi_pream_pwr_valid, - * BIT[23:8]=lat_wsi_temp(s16), - * BIT[31:24]=lat_wsi_full_pkt_pwr - */ - union { - A_UINT32 lat_wsi_pream_pwr_valid__lat_wsi_temp__lat_wsi_full_pkt_pwr; - struct { - A_UINT32 - lat_wsi_pream_pwr_valid: 8, - lat_wsi_temp: 16, - lat_wsi_full_pkt_pwr: 8; - }; - }; - /* - * Word 5: BIT[7:0]=lat_wsi_pream_pwr, - * BIT[15:8]=lat_wsi_tx_gain_idx, - * BIT[23:16]=lat_wsi_tpc_pdet_gain_idx, - * BIT[31:24]=lat_wsi_tpc_attn - */ - union { - A_UINT32 lat_wsi_pream_pwr__lat_wsi_tx_gain_idx__lat_wsi_tpc_pdet_gain_idx__lat_wsi_tpc_attn; - struct { - A_UINT32 - lat_wsi_pream_pwr: 8, - lat_wsi_tx_gain_idx: 8, - lat_wsi_tpc_pdet_gain_idx: 8, - lat_wsi_tpc_attn: 8; - }; - }; - /* - * Word 6: BIT[7:0]=glut_dac_gain_cal(s8), - * BIT[15:8]=glut_max_dac_gain_cal(s8), - * BIT[23:16]=dpd_dac_gain_cal(s8), - * BIT[31:24]=dpd_tx_gain_idx_cal - */ - union { - A_UINT32 glut_dac_gain_cal__glut_max_dac_gain_cal__dpd_dac_gain_cal__dpd_tx_gain_idx_cal; - struct { - A_UINT32 - glut_dac_gain_cal: 8, - glut_max_dac_gain_cal: 8, - dpd_dac_gain_cal: 8, - dpd_tx_gain_idx_cal: 8; - }; - }; - /* - * Word 7: BIT[7:0]=target_pwr_clpc_thr_corr(s8), - * BIT[15:8]=olpc_mode, - * BIT[23:16]=wsi_timeout, - * BIT[31:24]=target_pwr_clpc_thr_update(s8) - */ - union { - A_UINT32 target_pwr_clpc_thr_corr__olpc_mode__wsi_timeout__target_pwr_clpc_thr_update; - struct { - A_UINT32 - target_pwr_clpc_thr_corr: 8, - olpc_mode: 8, - wsi_timeout: 8, - target_pwr_clpc_thr_update: 8; - }; - }; - /* - * Word 8: BIT[7:0]=ro_temp_valid, - * BIT[15:8]=ro_full_pkt_pwr_valid, - * BIT[23:16]=ro_pream_pwr_valid, - * BIT[31:24]=reserved - */ - union { - A_UINT32 ro_temp_valid__ro_full_pkt_pwr_valid__ro_pream_pwr_valid; - struct { - A_UINT32 - ro_temp_valid: 8, - ro_full_pkt_pwr_valid: 8, - ro_pream_pwr_valid: 8, - reserved: 8; - }; - }; - /* - * Word 9: BIT[15:0]=ro_temp(s16), - * BIT[23:16]=ro_full_pkt_pwr, - * BIT[31:24]=ro_pream_pwr - */ - union { - A_UINT32 ro_temp__ro_full_pkt_pwr__ro_pream_pwr; - struct { - A_UINT32 - ro_temp: 16, - ro_full_pkt_pwr: 8, - ro_pream_pwr: 8; - }; - }; - /* - * Word 10: BIT[7:0]=ro_tpc_fe_sel, - * BIT[15:8]=ro_full_pkt_avg_out, - * BIT[23:16]=ro_lat_dc, - * BIT[31:24]=ro_pdacc_avg_out - */ - union { - A_UINT32 ro_tpc_fe_sel__ro_full_pkt_avg_out__ro_lat_dc__ro_pdacc_avg_out; - struct { - A_UINT32 - ro_tpc_fe_sel: 8, - ro_full_pkt_avg_out: 8, - ro_lat_dc: 8, - ro_pdacc_avg_out: 8; - }; - }; - /* - * Word 11: BIT[15:0]=temp_per_chain, - * BIT[23:16]=cal_cmd, - * BIT[31:24]=cal_time - */ - union { - A_UINT32 temp_per_chain__cal_cmd__cal_time; - struct { - A_UINT32 - temp_per_chain: 16, - cal_cmd: 8, - cal_time: 8; - }; - }; - /* - * Word 12: BIT[7:0]=cal_result, - * BIT[31:8]=reserved - */ - union { - A_UINT32 cal_result__reserved; - struct { - A_UINT32 - cal_result: 8, - reserved2: 24; - }; - }; -} htt_stats_phy_tpc_debug_chain_v1_tlv; - -/* TPC chain header GET/SET macros */ -/* word 0 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_M 0x0000ff00 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_S 8 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_M 0xffff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_S 16 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAIN_IDX_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_VERSION_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CHAINMASK_S)); \ - } while (0) - -/* word 1 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_M 0x0000ff00 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_S 8 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_S 16 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_GLUT_IDX_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TX_GAIN_IDX_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_DAC_GAIN_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_TARGET_POWER_S)); \ - } while (0) - -/* word 2 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_M 0x0000ffff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_M 0xffff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_S 16 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_ACC_CLPC_ERROR_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_CLPC_ERR_S)); \ - } while (0) - -/* word 3 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_M 0x0000ffff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_S 16 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_MEAS_PWR_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_VALID_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_VALID_S)); \ - } while (0) - -/* word 4 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_M 0x00ffff00 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_S 8 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_VALID_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TEMP_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_FULL_PKT_PWR_S)); \ - } while (0) - -/* word 5 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_M 0x0000ff00 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_S 8 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_S 16 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_PREAM_PWR_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TX_GAIN_IDX_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_PDET_GAIN_IDX_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_LAT_WSI_TPC_ATTN_S)); \ - } while (0) - -/* word 6 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_M 0x0000ff00 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_S 8 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_S 16 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_DAC_GAIN_CAL_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_GLUT_MAX_DAC_GAIN_CAL_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_DAC_GAIN_CAL_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_DPD_TX_GAIN_IDX_CAL_S)); \ - } while (0) - -/* word 7 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_M 0x0000ff00 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_S 8 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_S 16 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_CORR_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_OLPC_MODE_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_WSI_TIMEOUT_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TARGET_PWR_CLPC_THR_UPDATE_S)); \ - } while (0) - -/* word 8 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_M 0x0000ff00 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_S 8 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_S 16 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_VALID_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_VALID_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_VALID_S)); \ - } while (0) - -/* word 9 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_M 0x0000ffff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_S 16 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TEMP_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_PWR_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PREAM_PWR_S)); \ - } while (0) - -/* word 10 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_M 0x0000ff00 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_S 8 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_S 16 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_TPC_FE_SEL_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_FULL_PKT_AVG_OUT_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_LAT_DC_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_RO_PDACC_AVG_OUT_S)); \ - } while (0) - -/* word 11 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_M 0x0000ffff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_S 0 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_M 0x00ff0000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_S 16 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_M 0xff000000 -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_S 24 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_TEMP_PER_CHAIN_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_CMD_S)); \ - } while (0) - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_TIME_S)); \ - } while (0) - -/* word 12 */ -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_M 0x000000ff -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_S 0 - -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_GET(_var) \ - (((_var) & HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_M) >> \ - HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_S) -#define HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_SET(_var, _val) \ - do { \ - HTT_CHECK_SET_VAL(HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT, _val); \ - ((_var) |= ((_val) << HTT_STATS_PHY_TPC_DEBUG_CHAIN_V1_CAL_RESULT_S)); \ - } while (0) - -/*===================== End PHY DPD/TPC Debug stats ==================== } */ - - #endif /* __HTT_STATS_H__ */ diff --git a/drivers/staging/fw-api/fw/wlan_defs.h b/drivers/staging/fw-api/fw/wlan_defs.h index 2e7a28ec2a7d..2e8db1346a90 100755 --- a/drivers/staging/fw-api/fw/wlan_defs.h +++ b/drivers/staging/fw-api/fw/wlan_defs.h @@ -75,6 +75,19 @@ */ #define CONFIG_160MHZ_SUPPORT_UNDEF_WAR #endif +#else + /* + * For backwards compatibility, if CONFIG_160MHZ_SUPPORT is not defined, + * default it to 0, if this is either a host build or a Rome target build. + * This maintains the prior behavior for the host and Rome target builds. + */ + #if defined(AR6320) || !defined(ATH_TARGET) + /* + * Set a flag to indicate that at the end of the file, + * CONFIG_160MHZ_SUPPORT should be set to 0. + */ + #define CONFIG_160MHZ_SUPPORT_UNDEF_WAR + #endif #endif #ifndef SUPPORT_11AX @@ -148,18 +161,6 @@ typedef enum { MODE_11BE_EHT40_2G = 32, /* For WIN */ #endif -#if defined(SUPPORT_11BN) && SUPPORT_11BN - MODE_11BN_UHR20 = 33, - MODE_11BN_UHR40 = 34, - MODE_11BN_UHR80 = 35, - MODE_11BN_UHR80_80 = 36, - MODE_11BN_UHR160 = 37, - MODE_11BN_UHR160_160 = 38, - MODE_11BN_UHR320 = 39, - MODE_11BN_UHR20_2G = 40, - MODE_11BN_UHR40_2G = 41, -#endif - /* * MODE_UNKNOWN should not be used within the host / target interface. * Thus, it is permissible for MODE_UNKNOWN to be conditionally-defined, @@ -257,38 +258,10 @@ typedef enum { ((mode) == MODE_11BE_EHT320) || \ ((mode) == MODE_11BE_EHT20_2G) || \ ((mode) == MODE_11BE_EHT40_2G)) -#define IS_MODE_EHT_5G_6G(mode) (((mode) == MODE_11BE_EHT20) || \ - ((mode) == MODE_11BE_EHT40) || \ - ((mode) == MODE_11BE_EHT80) || \ - ((mode) == MODE_11BE_EHT80_80) || \ - ((mode) == MODE_11BE_EHT160) || \ - ((mode) == MODE_11BE_EHT160_160)|| \ - ((mode) == MODE_11BE_EHT320)) #define IS_MODE_EHT_2G(mode) (((mode) == MODE_11BE_EHT20_2G) || \ ((mode) == MODE_11BE_EHT40_2G)) #endif /* SUPPORT_11BE */ -#if defined(SUPPORT_11BN) && SUPPORT_11BN -#define IS_MODE_UHR(mode) (((mode) == MODE_11BN_UHR20) || \ - ((mode) == MODE_11BN_UHR40) || \ - ((mode) == MODE_11BN_UHR80) || \ - ((mode) == MODE_11BN_UHR80_80) || \ - ((mode) == MODE_11BN_UHR160) || \ - ((mode) == MODE_11BN_UHR160_160)|| \ - ((mode) == MODE_11BN_UHR320) || \ - ((mode) == MODE_11BN_UHR20_2G) || \ - ((mode) == MODE_11BN_UHR40_2G)) -#define IS_MODE_UHR_5G_6G(mode) (((mode) == MODE_11BN_UHR20) || \ - ((mode) == MODE_11BN_UHR40) || \ - ((mode) == MODE_11BN_UHR80) || \ - ((mode) == MODE_11BN_UHR80_80) || \ - ((mode) == MODE_11BN_UHR160) || \ - ((mode) == MODE_11BN_UHR160_160)|| \ - ((mode) == MODE_11BN_UHR320)) -#define IS_MODE_UHR_2G(mode) (((mode) == MODE_11BN_UHR20_2G) || \ - ((mode) == MODE_11BN_UHR40_2G)) -#endif /* SUPPORT_11BN */ - #define IS_MODE_VHT_2G(mode) (((mode) == MODE_11AC_VHT20_2G) || \ ((mode) == MODE_11AC_VHT40_2G) || \ ((mode) == MODE_11AC_VHT80_2G)) diff --git a/drivers/staging/fw-api/fw/wlan_module_ids.h b/drivers/staging/fw-api/fw/wlan_module_ids.h index fc65f819f510..981bbaef3451 100644 --- a/drivers/staging/fw-api/fw/wlan_module_ids.h +++ b/drivers/staging/fw-api/fw/wlan_module_ids.h @@ -196,9 +196,6 @@ typedef enum { WLAN_MODULE_C2C, /* 0x98 */ WLAN_MODULE_VBSS, /* 0x99 */ WLAN_MODULE_OPT_DATA, /* 0x9a */ - WLAN_MODULE_ASD, /* 0x9b */ - WLAN_MODULE_ENERGY_MGMT, /* 0x9c */ - WLAN_MODULE_SMD, /* 0x9d */ WLAN_MODULE_ID_MAX, WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX, diff --git a/drivers/staging/fw-api/fw/wmi_services.h b/drivers/staging/fw-api/fw/wmi_services.h index 18acd1f63fd7..b82c7bd1fc45 100644 --- a/drivers/staging/fw-api/fw/wmi_services.h +++ b/drivers/staging/fw-api/fw/wmi_services.h @@ -695,168 +695,6 @@ typedef enum { WMI_SERVICE_UMAC_MIGRATION_SUPPORT = 436, /* Indicates that FW supports UMAC migration */ WMI_SERVICE_STA_TWT_STATS_EXT = 437, /* FW supports additional info in TWT stats and ADD COMPLETION Event */ WMI_SERVICE_OPT_DP_DIAG_SUPPORT = 438, /* FW supports diag QDATA feature */ - WMI_SERVICE_MLO_ROAM_PARTNER_BRINGUP_FROM_HOST = 439, /* Indicates FW supports new design in which FW expects the host to bringup the partner link during roaming */ - WMI_SERVICE_CTRL_PATH_PEER_BA_STATS = 440, /* FW supports retrieving BlockAck stats through WMI_REQUEST_CTRL_PATH_PEER_STAT */ - WMI_SERVICE_CTRL_PATH_STA_DAR_STATS_SUPPORT = 441, /* FW supports DAR stats reporting for STA mode */ - WMI_SERVICE_APF_DATA_OFFLOAD_SUPPORT_ENABLED = 442, /* Indicates FW support for APFv6 handling offloads and disable QC data offloads */ - WMI_SERVICE_PER_VDEV_TWT_RESP_DISABLE_SUPPORT = 443, /* FW supports vdev level TWT responder disable */ - WMI_SERVICE_VENDOR_OUI_ACTION_V2 = 444, /* FW supports vendor OUI action version 2 */ - WMI_SERVICE_HW_BLACKLIST_CHAN_SUPPORT = 445, /* Indicates FW support for computing and sending the HW channel blacklist for the current country and applicable power mode */ - WMI_SERVICE_NDP_DFS_CHANNEL_SUPPORT = 446, /* FW supports forming NDP on DFS channels */ - WMI_SERVICE_WFD_R2 = 447, /* Indicates FW supports WiFi-Direct R2 */ - WMI_SERVICE_STA_MLO_RCFG_SUPPORT = 448, /* FW supports STA ML reconfig op */ - WMI_SERVICE_PDEV_SUSPEND_EVENT_SUPPORT = 449, /* FW supports PDEV_SUSPEND event */ - WMI_SERVICE_PCC_MODE = 450, /* Indicates FW support for PCC (P2P Connection Compatibility) Mode */ - WMI_SERVICE_TDLS_NSS_CONFIRM_SUPPORT = 451, /* FW supports confirmation to host requested TDLS NSS operation */ - - WMI_SERVICE_EM_PCIE_CONFIG_CBW_SUPPORT = 452, /* Indicates support for channel bandwidth based PCIe config adjustment */ - WMI_SERVICE_EM_PCIE_CONFIG_LPM_SUPPORT = 453, /* Indicates support for PCIe low power mode L0S/L1 */ - WMI_SERVICE_EM_DCVS_SUPPORT = 454, /* Indicates support for Dynamic clock and voltage scaling */ - WMI_SERVICE_EM_EDPS_SUPPORT = 455, /* Indicates support for Dynamic AP power save */ - WMI_SERVICE_EM_PUO_SUPPORT = 456, /* Indicates support for TWT based periodic unavailability operation. */ - WMI_SERVICE_EM_ECO_MODE_SUPPORT = 457, /* Indicates support for ECO mode config (LP BBF+ADC+SYNCT) */ - - WMI_SERVICE_11BN = 458, /* Indicates FW supports 802.11bn */ - WMI_SERVICE_HOST_AWARE_POWERSAVE = 459, /* FW supports indicating the powerstate of FW to host */ - WMI_SERVICE_PDEV_DIV_STATES_REPORT = 460, /* FW supports reporting antenna diversity states */ - WMI_SERVICE_EAPOL_OVER_RAW = 461, /* FW supports sending EAPOL frames in raw mode even when the vdev is brought up in nwifi/ethernet mode */ - WMI_SERVICE_MLO_SAP_LINK_REMOVAL_SUPPORT = 462, /* Indicates FW supports MLO SAP link removal operation */ - WMI_SERVICE_TX_POWER_LIMIT = 463, /* FW supports temporary tx power limit indication to HALPHY */ - WMI_SERVICE_NPCA_SUPPORT = 464, /* Indicates FW supports NPCA (Non-Primary Channel Access) */ - WMI_SERVICE_EXT_TLV_SUPPORT = 465, /* FW supports WMI_MAX_NUM_EXT_TLVS */ - WMI_SERVICE_VDEV_TRAFFIC_MONITORING = 466, /* FW supports traffic monitoring */ - WMI_SERVICE_EM_DPS_ASSISTING_ROLE_SUPPORT = 467, /* Indicates support for Energy Mgmt DPS assisting role operation */ - WMI_SERVICE_XPAN_SAP_STA_PWRSAVE_SUPPORT = 468, /* Indicates support for power optimization in XPAN + STA */ - WMI_SERVICE_CFP_SUPPORT = 469, /* FW supports control frame protection */ - WMI_SERVICE_CFP_PADDING_SUPPORT = 470, /* FW supports control frame protection padding */ - - /* Service caps related to 11BI */ - WMI_SERVICE_11BI_EPPKE_SUPPORT = 471, - WMI_SERVICE_11BI_1X_OVER_AUTH_SUPPORT = 472, - WMI_SERVICE_11BI_PMKID_PRIVACY_SUPPORT = 473, - WMI_SERVICE_11BI_DS_MAC_ADDR_SUPPORT = 474, - - WMI_SERVICE_CCK_RX_SUPPORT_5GHZ = 475, /* Indicates FW supports CCK RX in 5 GHz band */ - WMI_SERVICE_CCK_TX_SUPPORT_5GHZ = 476, /* Indicates FW supports CCK TX in 5 GHZ band */ - WMI_SERVICE_DIRECT_REFILL_SUPPORT = 477, /* Indicates FW supports direct refill for RX buffer ring */ - WMI_SERVICE_NAN_STANDARD_MODE_SUPPORT = 478, /* Indicates FW supports NAN in standard mode (supplicant-based NAN architecture model) */ - WMI_SERVICE_CONC_2VDEV_DCS_STATS_SUPPORT = 479, /* Indicate FW support for collecting DCS stats for more than 1 vdev (max 2 concurrent vdevs) */ - WMI_SERVICE_CFR_UNASSOC_RX_CAPTURE_SUPPORT = 480, /* Indicates FW supports RX-based unassociated CFR capture */ - WMI_SERVICE_CFR_ASSOC_TX_CAPTURE_SUPPORT = 481, /* Indicates FW supports TX-based CFR capture */ - WMI_SERVICE_VDEV_UNIFIED_CONNECT_DISCONNECT_SUPPORT = 482, /* Indicates FW support for unified connect and disconnect vdev cmds for link switch */ - WMI_SERVICE_ENHANCED_STATS_SUPPORT = 483, /* Indicates FW supports "enhanced stats" */ - WMI_SERVICE_RADAR_FLAGS_RSSI_DBM_SUPPORT = 484, /* Indicates FW support to add RSSI in dBm units in WMI radar event */ - WMI_SERVICE_WOW_STA_PS_PARAM_CACHE_SUPPORT = 485, /* Indicates FW support for WOW timeline optimization feature */ - WMI_SERVICE_VENDOR_OUI_SUPPORT_EXCLUSIVE_MAC_ADDRESS = 486, /* FW supports parse exclusive_mac_address in wmi_vendor_oui_ext */ - WMI_SERVICE_P2P_CANCEL_ONE_SHOT_NOA_SUPPORT = 487, /* Indicates FW support for P2P GO/GC cancel one-shot NOA feature */ - WMI_SERVICE_SMD_BSS_TRANSITION_SUPPORT = 488, /* Indicates FW supports S(eamless)M(obility)D(omain) BSS transition */ - - /* Service caps related to SMD Roaming - start */ - WMI_SERVICE_SMD_SUPPORT_ROAMING = 489, - WMI_SERVICE_SMD_SUPPORT_DL_FORWARD = 490, - WMI_SERVICE_SMD_SUPPORT_UL_FORWARD = 491, - /* Service caps related to SMD Roaming - end */ - - WMI_SERVICE_PEER_METADATA_V2_SUPPORT = 492, /* Support rx peer meta data v2 */ - /* WMI_SERVICE_HANDLE_ROAMING_WITHOUT_RSO_STOP_FOR_4WAY_HS_OFFLOAD_DISABLE: - * Indicates support to handle roaming triggers while host is doing - * the EAPOL process for 4way HS offload disable case. - * FW needs to disable the roam triggers except deauth roaming. - */ - WMI_SERVICE_HANDLE_ROAMING_WITHOUT_RSO_STOP_FOR_4WAY_HS_OFFLOAD_DISABLE = 493, - /* Indicates FW support for populating vdev operating param stats */ - WMI_SERVICE_VDEV_OPERATING_PARAMS_EVENT_SUPPORT = 494, - WMI_SERVICE_SUPPORT_WOW_OLE_DAL = 495, - /* Indicate FW support for PASSTHRU VDEV Channel Hopping Schedule */ - WMI_SERVICE_PASSTHRU_VDEV_CHAN_HOP_SCHEDULE_SUPPORT = 496, - /* - * Indicates FW support for shared memory model to pass - * ongoing TBTT count downs to Host. - */ - WMI_SERVICE_SHARED_MEM_MODEL_TBTT_COUNT_DOWN = 497, - /* Indicate FW support for IPI (Idle Power Indicate) stats collection */ - WMI_SERVICE_IDLE_POWER_INDICATE_SUPPORT = 498, - /* Indicates FW support to add Radar type and domain in WMI radar event */ - WMI_SERVICE_RADAR_FLAGS_TYPE_SUPPORT = 499, - /* Indicates FW support to perform Master migration when master peer gets deleted */ - WMI_SERVICE_ML_PEER_MASTER_MIGRATION_SUPPORT = 500, - WMI_SERVICE_NAN_AP_ASSISTED_DFS_OPERATION_SUPPORT = 501, /* Indicates FW supports NAN DFS operation */ - /* - * Indicates FW supports TDLS Stats command/event, - * used for sending TDLS connect info and TDLS data stats - */ - WMI_SERVICE_TDLS_STATS_SUPPORT = 502, - WMI_SERVICE_L3_HEADER_PADDING_ENABLE = 503, - - /* Indicates FW supports Extended OUI Action IDs */ - WMI_SERVICE_SUPPORTED_EXT_OUI_ACTION_IDS = 504, - - /* - * Indicates FW supports cloud based control for whitelist or blacklist - * AP configuration - */ - WMI_SERVICE_SUPPORT_WHITELIST_BLACKLIST_AP_CONFIG = 505, - /* - * Indicate FW support for PASSTHRU VDEV AMPDU Aggregation - * and Rate Adaptation - */ - WMI_SERVICE_PASSTHRU_VDEV_AMPDU_RA_SUPPORT = 506, - /* FW supports CalDB transmission over WMI */ - WMI_SERVICE_CALDB_OVER_WMI = 507, - /* Indicates FW Supports RTT Proximity Detection (USD ranging) */ - WMI_SERVICE_RTT_PD = 508, - /* Indicates FW support for Channel Hopping Status Report*/ - WMI_SERVICE_VDEV_CHAN_HOP_STATUS_REPORT = 509, - /* Indicates FW support for Predictive roaming */ - WMI_SERVICE_ROAMING_PREDICTIVE = 510, - - /* Services related to MAPC / C-TDMA (802.11bn) */ - WMI_SERVICE_CO_AP_CTDMA_SUPPORT = 511, - WMI_SERVICE_UHR_CO_AP_CTDMA_TB_PPDU_SUPPORT = 512, - WMI_SERVICE_UHR_CO_AP_CTDMA_TXOP_RETURN_SUPPORT = 513, - - /* - * Indicates FW supports cloud based control for Uplink Tx Beamformer - * AP configuration - */ - WMI_SERVICE_SUPPORT_UL_TX_BEAMFORMER_AP_CONFIG = 514, - - /* Indicates FW supports enable/disable TWT per vdev */ - WMI_SERVICE_STA_TWT_EN_DIS_VDEV_SUPPORT = 515, - - /* - * Indicates FW supports AWGN interference status request via - * WMI_PDEV_PARAM_AWGN_INT_STATUS_REQUEST, allowing host to query - * the current AWGN CCA segment bitmap (awgn_prev_int_seg) which - * is sent back immediately via WMI_DCS_INTERFERENCE_EVENTID. - */ - WMI_SERVICE_AWGN_INT_STATUS_REQUEST_SUPPORT = 516, - - WMI_SERVICE_WMI_ANOMALY_REPORTING = 517, - - /* - * Indicates that FW supports C-TAS power indication reporting and - * power limit enquiring through cmds WMI_SET_MODIFY_TX_PLIM_CMDID, - * WMI_GET_AVG_TX_POWER_CMDID and WMI_GET_TX_POWER_CALLING_CMDID. - */ - WMI_SERVICE_CTAS_PLIM_INDICATION_SUPPORT = 518, - - /* - * Indicates FW supports NAN in offload mode - * (supplicant-based NAN offload mode architecture). - */ - WMI_SERVICE_NAN_OFFLOAD_MODE_SUPPORT = 519, - - /* WMI_SERVICE_PDEV_SET_CUMAC_CHIP_CMD_SUPPORT: - * FW supports handling WMI_PDEV_SET_CUMAC_CHIP_CMDID. - * When this service bit is set in wmi_service_ready, the host can - * set WMI_RSRC_CFG_HOST_SERVICE_FLAG_CUMAC_CMD_SUPPORT in - * wmi_resource_config.host_service_flags to indicate it will send - * WMI_PDEV_SET_CUMAC_CHIP_CMDID to trigger wal_mlo_cumac_init(). - * If the host does not set this flag, FW will call wal_mlo_cumac_init() - * from wal_mlo_soc_init() with the default chip id. - */ - WMI_SERVICE_PDEV_SET_CUMAC_CHIP_CMD_SUPPORT = 520, WMI_MAX_EXT2_SERVICE diff --git a/drivers/staging/fw-api/fw/wmi_tlv_defs.h b/drivers/staging/fw-api/fw/wmi_tlv_defs.h index 05e4a9aaa6c5..e8c306dbcb7f 100644 --- a/drivers/staging/fw-api/fw/wmi_tlv_defs.h +++ b/drivers/staging/fw-api/fw/wmi_tlv_defs.h @@ -1200,8 +1200,6 @@ typedef enum { WMITLV_TAG_STRUC_wmi_ctrl_path_dfs_channel_stats_struct, WMITLV_TAG_STRUC_wmi_twt_ack_event_fixed_param, WMITLV_TAG_STRUC_wmi_twt_caps_param, - WMITLV_TAG_STRUC_wmi_twt_caps_params = /* alias */ - WMITLV_TAG_STRUC_wmi_twt_caps_param, WMITLV_TAG_STRUC_wmi_vdev_enable_disable_intra_bss_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_peer_enable_disable_intra_bss_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_pdev_aoa_phasedelta_evt_fixed_param, @@ -1223,8 +1221,6 @@ typedef enum { WMITLV_TAG_STRUC_wmi_dbs_or_sbs_cap_ext, WMITLV_TAG_STRUC_wmi_roam_set_param_cmd_fixed_param, WMITLV_TAG_STRUC_cust_bdf_version_capabilities, - WMITLV_TAG_STRUC_wmi_cust_bdf_version_capabilities = /* alias */ - WMITLV_TAG_STRUC_cust_bdf_version_capabilities, WMITLV_TAG_STRUC_wmi_pdev_fips_extend_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_fips_extend_cmd_init_params, WMITLV_TAG_STRUC_wmi_pdev_fips_extend_event_fixed_param, @@ -1432,8 +1428,6 @@ typedef enum { WMITLV_TAG_STRUC_wmi_dcs_obss_int_t, WMITLV_TAG_STRUC_wmi_pdev_wifi_radar_cal_completion_status_event_param, WMITLV_TAG_STRUC_wmi_sar_flags, - WMITLV_TAG_STRUC_wmi_sar_flag_tlv_param = /* alias */ - WMITLV_TAG_STRUC_wmi_sar_flags, WMITLV_TAG_STRUC_wmi_pdev_enable_xlna_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_pdev_enable_xlna_event_fixed_param, WMITLV_TAG_STRUC_wmi_reg_chan_list_cc_event_ext2_fixed_param, @@ -1464,11 +1458,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_scan_cache_result_event_fixed_param, WMITLV_TAG_STRUC_wmi_scan_cache_info, WMITLV_TAG_STRUC_wmi_POWER_BOOST_CAPABILITIES, - WMITLV_TAG_STRUC_WMI_POWER_BOOST_CAPABILITIES = /* alias */ - WMITLV_TAG_STRUC_wmi_POWER_BOOST_CAPABILITIES, WMITLV_TAG_STRUC_wmi_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES, - WMITLV_TAG_STRUC_WMI_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES = /* alias */ - WMITLV_TAG_STRUC_wmi_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES, WMITLV_TAG_STRUC_wmi_mlo_link_reconfig_start_indication_event_fixed_param, WMITLV_TAG_STRUC_wmi_mlo_link_reconfig_fixed_param, WMITLV_TAG_STRUC_wmi_mlo_link_reconfig_complete_fixed_param, @@ -1486,178 +1476,6 @@ typedef enum { WMITLV_TAG_STRUC_wmi_vdev_vbss_peer_sn_info, WMITLV_TAG_STRUC_wmi_vdev_vbss_config_event_fixed_param, WMITLV_TAG_STRUC_wmi_stats_ext_event_vdev_ext2_t, - WMITLV_TAG_STRUC_wmi_ndp_set_latency_tput_fixed_param, - WMITLV_TAG_STRUC_wmi_roam_partner_link_param, - WMITLV_TAG_STRUC_wmi_mlo_link_ttlm_complete_fixed_param, - WMITLV_TAG_STRUC_wmi_ctrl_path_sta_dar_stats_struct, - WMITLV_TAG_STRUC_wmi_bpf_set_supported_offload_bitmap_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_hw_blacklist_chan_fixed_param, - WMITLV_TAG_STRUC_wmi_hw_blacklist_chan_data, - WMITLV_TAG_STRUC_wmi_pdev_suspend_event_fixed_param, - WMITLV_TAG_STRUC_wmi_bpf_set_apf_mode_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_assoc_operating_mode_params, - WMITLV_TAG_STRUC_wmi_recv_bcn_stats, - WMITLV_TAG_STRUC_wmi_vdev_vbss_peer_dyn_info, - WMITLV_TAG_STRUC_wmi_energy_mgmt_pcie_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_energy_mgmt_pcie_lpm_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_energy_mgmt_dcvs_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_energy_mgmt_edps_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_energy_mgmt_puo_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_energy_mgmt_eco_mode_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_assoc_mgmt_mpduq_params, - WMITLV_TAG_STRUC_wmi_peer_assoc_mgmt_msduq_params, - WMITLV_TAG_STRUC_wmi_peer_assoc_hol_msduq_params, - /* for backwards-compatibility, maintain old name (with "mdsu" typo) */ - WMITLV_TAG_STRUC_wmi_peer_assoc_hol_mdsuq_params = - WMITLV_TAG_STRUC_wmi_peer_assoc_hol_msduq_params, - WMITLV_TAG_STRUC_wmi_peer_tid_rate_custom_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_co_located_chan_info, - WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_cmd_fixed_param, /* deprecated */ - WMITLV_TAG_STRUC_wmi_peer_uhr_npca_cap_params, - WMITLV_TAG_STRUC_wmi_peer_uhr_mode_update_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_npca_ap_cap_resp_event_fixed_param, /*deprecated*/ - WMITLV_TAG_STRUC_wmi_wfa_config_ml, - WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_ac_info, - WMITLV_TAG_STRUC_wmi_vdev_get_tpc_ie_power_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_tpc_ie_power_event_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_coex_stats, - WMITLV_TAG_STRUC_wmi_vdev_traffic_monitoring_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param, - WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES_EXT2, - WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, - WMITLV_TAG_STRUC_wmi_pdev_set_tx_chainmask_comp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_fw_ready_ind_event_fixed_param, - WMITLV_TAG_STRUC_wmi_wlan_mode_req_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_wlan_mode_resp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_enable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_ctrl_config_param, - WMITLV_TAG_STRUC_wmi_nan_disc_band_config_param, - WMITLV_TAG_STRUC_wmi_nan_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_enable_rsp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_next_dw_info_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_disable_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_disable_cnf_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_disable_ind_fixed_param, - WMITLV_TAG_STRUC_wmi_cfr_capture_filter_resp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_unified_connect_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_unified_connect_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_beacon_stats, - WMITLV_TAG_STRUC_wmi_vdev_congestion_stats, - WMITLV_TAG_STRUC_wmi_vdev_data_stats, - WMITLV_TAG_STRUC_wmi_em_pcie_stats, - WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, - WMITLV_TAG_STRUC_wmi_roam_smd_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_repurpose_resp_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_repurpose_request_tlv_param, - WMITLV_TAG_STRUC_wmi_vdev_repurpose_response_tlv_param, - WMITLV_TAG_STRUC_wmi_roam_smd_start_status_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_prep_resp_status_list, - WMITLV_TAG_STRUC_wmi_ipa_ring_stats_req_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_ipa_ring_stats_conf_event_fixed_param, - WMITLV_TAG_STRUC_wmi_ipa_ring_stat_entry, - WMITLV_TAG_STRUC_wmi_em_dcvs_stats, - WMITLV_TAG_STRUC_wmi_uhr_ap_dps_params, - WMITLV_TAG_STRUC_wmi_uhr_ap_npca_params, - WMITLV_TAG_STRUC_wmi_uhr_ap_duo_params, - WMITLV_TAG_STRUC_wmi_uhr_ap_pedca_params, - WMITLV_TAG_STRUC_wmi_uhr_ap_dbe_params, - WMITLV_TAG_STRUC_wmi_uhr_ap_puo_params, - WMITLV_TAG_STRUC_wmi_uhr_ap_elr_reception_params, - WMITLV_TAG_STRUC_wmi_vdev_uhr_cu_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_uhr_cu_status, - WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_event_fixed_param, - WMITLV_TAG_STRUC_wmi_cfr_capture_fix_agc_gain_config, - WMITLV_TAG_STRUC_wmi_cfr_capture_fix_agc_gain_info, - WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_power_stats_info, - WMITLV_TAG_STRUC_wmi_pdev_tx_rate_info, - WMITLV_TAG_STRUC_wmi_vdev_start_smd_params, - WMITLV_TAG_STRUC_wmi_smd_roam_config_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_smd_roam_config_event_fixed_param, - WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_complete_event_fixed_param, - WMITLV_TAG_STRUC_wmi_smd_roam_peer_tid_info, - WMITLV_TAG_STRUC_wmi_uhr_ap_mode_tup_enable_disable_update_param, - WMITLV_TAG_STRUC_wmi_scan_suppress_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_get_scan_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_soc_get_conc_info_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_get_scan_stats_resp_fixed_param, - WMITLV_TAG_STRUC_wmi_soc_get_conc_info_resp_fixed_param, - WMITLV_TAG_STRUC_wmi_conc_info, - WMITLV_TAG_STRUC_wmi_nan_local_schedule_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_peer_params_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_local_schedule_cnf_event_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cnf_event_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_peer_params_cnf_event_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_channel, - WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_fixed_param, - WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_event_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_channel_hopping_schedule_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_current_operating_param_event_fixed_param, - WMITLV_TAG_STRUC_wmi_ch_usage_add_dialog_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_coex_policy_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_coex_policy_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_channel_hopping_channel_params, - WMITLV_TAG_STRUC_wmi_uhr_rate_set, - WMITLV_TAG_STRUC_wmi_shared_mem_model_tbtt_count_down_config, - WMITLV_TAG_STRUC_wmi_vdev_create_tbtt_count_down_offset_info, - WMITLV_TAG_STRUC_wmi_vdev_start_uhr_config, - WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param, - WMITLV_TAG_STRUC_wmi_iface_ipi_stats, - WMITLV_TAG_STRUC_wmi_peer_uhr_npca_op_params, - WMITLV_TAG_STRUC_wmi_ndp_channel_info_event_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_uhr_omp_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_uhr_omp_npca_params, - WMITLV_TAG_STRUC_wmi_nan_dfs_channel_availability_ind_event_fixed_param, - WMITLV_TAG_STRUC_wmi_request_tdls_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_tdls_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_tdls_connect_info_stats, - WMITLV_TAG_STRUC_wmi_tdls_data_stats, - WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_event_fixed_param, - WMITLV_TAG_STRUC_wmi_anomaly_report_hdr, - WMITLV_TAG_STRUC_wmi_anomaly_entry_t, - WMITLV_TAG_STRUC_wmi_peer_uhr_omp_sta_dps_params, - WMITLV_TAG_STRUC_wmi_rtt_peer_meas_capabilities, - WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_peer_info, - WMITLV_TAG_STRUC_wmi_rtt_peer_meas_cancel_meas_cmd_fix_param, - WMITLV_TAG_STRUC_wmi_rtt_peer_meas_report_event_fixed_param, - WMITLV_TAG_STRUC_wmi_rtt_peer_meas_report_peer_meas_result_info, - WMITLV_TAG_STRUC_wmi_vdev_get_chan_hop_status_report_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_vdev_chan_hop_slot_status, - WMITLV_TAG_STRUC_wmi_vdev_chan_hop_status_report_event_fixed_param, - WMITLV_TAG_STRUC_wmi_peer_set_mapc_params_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_mapc_cmn_params, - WMITLV_TAG_STRUC_wmi_mapc_cotdma_params, - WMITLV_TAG_STRUC_wmi_mapc_cosr_params, - WMITLV_TAG_STRUC_wmi_mapc_cobf_params, - WMITLV_TAG_STRUC_wmi_mapc_cortwt_params, - WMITLV_TAG_STRUC_wmi_lpi_scan_result_ind_fixed_param, - WMITLV_TAG_STRUC_wmi_lpi_ap_info_t, - WMITLV_TAG_STRUC_wmi_nan_disc_service_rsp_event_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_disc_match_event_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_disc_service_req_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_disc_cancel_service_req_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_nan_disc_service_req_terminated_event_fixed_param, - WMITLV_TAG_STRUC_wmi_set_modify_tx_plim_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_get_avg_tx_power_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_get_tx_power_calling_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_modify_tx_plim_event_fixed_param, - WMITLV_TAG_STRUC_wmi_avg_tx_power_event_fixed_param, - WMITLV_TAG_STRUC_wmi_avg_tx_power_region_per_antenna_chain, - WMITLV_TAG_STRUC_wmi_plimit_table_event_fixed_param, - WMITLV_TAG_STRUC_wmi_tx_power_per_antenna_chain, - WMITLV_TAG_STRUC_wmi_athdiag_read_write_cmd_fixed_param, - WMITLV_TAG_STRUC_wmi_athdiag_read_write_event_fixed_param, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -2219,62 +2037,6 @@ typedef enum { OP(WMI_MLO_LINK_RECONFIG_COMPLETE_CMDID) \ OP(WMI_SAWF_EZMESH_HOP_COUNT_CMDID) \ OP(WMI_VDEV_VBSS_CONFIG_CMDID) \ - OP(WMI_NDP_SET_LATENCY_TPUT_CMDID) \ - OP(WMI_MLO_LINK_TTLM_COMPLETE_CMDID) \ - OP(WMI_BPF_SET_SUPPORTED_OFFLOAD_BITMAP_CMDID) \ - OP(WMI_BPF_SET_APF_MODE_CMDID) \ - OP(WMI_ENERGY_MGMT_PCIE_CONFIG_CMDID) \ - OP(WMI_ENERGY_MGMT_PCIE_LPM_CMDID) \ - OP(WMI_ENERGY_MGMT_DCVS_CONFIG_CMDID) \ - OP(WMI_ENERGY_MGMT_EDPS_CONFIG_CMDID) \ - OP(WMI_ENERGY_MGMT_PUO_CONFIG_CMDID) \ - OP(WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID) \ - OP(WMI_PEER_TID_RATE_CUSTOM_CMDID) \ - OP(WMI_PEER_UHR_MODE_UPDATE_CMDID) \ - OP(WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID) \ - OP(WMI_VDEV_GET_TPC_IE_POWER_CMDID) \ - OP(WMI_PEER_ASSOC_V2_CMDID) \ - OP(WMI_VDEV_TRAFFIC_MONITORING_CMDID) \ - OP(WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID) \ - OP(WMI_WLAN_MODE_REQ_CMDID) \ - OP(WMI_NAN_ENABLE_CMDID) \ - OP(WMI_NAN_CONFIG_CMDID) \ - OP(WMI_NAN_DISABLE_CMDID) \ - OP(WMI_VDEV_UNIFIED_CONNECT_CMDID) \ - OP(WMI_VDEV_UNIFIED_DISCONNECT_CMDID) \ - OP(WMI_ROAM_SMD_CONFIG_CMDID) \ - OP(WMI_ROAM_SMD_START_STATUS_CMDID) \ - OP(WMI_VDEV_REPURPOSE_RESP_CMDID) \ - OP(WMI_IPA_RING_STATS_REQ_CMDID) \ - OP(WMI_VDEV_UHR_CU_CMDID) \ - OP(WMI_PDEV_UHR_CU_CMDID) \ - OP(WMI_PDEV_POWER_DATAPATH_STATS_CMDID) \ - OP(WMI_SMD_ROAM_CONFIG_CMDID) \ - OP(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID) \ - OP(WMI_SCAN_SUPPRESS_CMDID) \ - OP(WMI_GET_SCAN_STATS_CMDID) \ - OP(WMI_SOC_GET_CONC_INFO_CMDID) \ - OP(WMI_NAN_LOCAL_SCHEDULE_CMDID) \ - OP(WMI_NAN_PEER_SCHEDULE_CMDID) \ - OP(WMI_NAN_PEER_PARAMS_CMDID) \ - OP(WMI_ENERGY_MGMT_OEM_DATA_CMDID) \ - OP(WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID) \ - OP(WMI_TWT_ADD_CH_USAGE_CMDID) \ - OP(WMI_COEX_GET_POLICY_STATS_CMDID) \ - OP(WMI_PDEV_SET_CUMAC_CHIP_CMDID) \ - OP(WMI_PEER_UHR_OMP_CMDID) \ - OP(WMI_REQUEST_TDLS_STATS_CMDID) \ - OP(WMI_GET_CHIPSET_LOGGING_STATS_CMDID) \ - OP(WMI_RTT_PEER_MEAS_REQ_CMDID) \ - OP(WMI_RTT_PEER_MEAS_CANCEL_CMDID) \ - OP(WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID) \ - OP(WMI_PEER_SET_MAPC_PARAMS_CMDID) \ - OP(WMI_NAN_DISC_SERVICE_REQ_CMDID) \ - OP(WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID) \ - OP(WMI_SET_MODIFY_TX_PLIM_CMDID) \ - OP(WMI_GET_AVG_TX_POWER_CMDID) \ - OP(WMI_GET_TX_POWER_CALLING_CMDID) \ - OP(WMI_ATHDIAG_READ_WRITE_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -2610,49 +2372,6 @@ typedef enum { OP(WMI_PDEV_WIFI_RADAR_CAPABILITIES_EVENTID) \ OP(WMI_VDEV_VBSS_CONFIG_EVENTID) \ OP(WMI_OPT_DP_DIAG_EVENTID) \ - OP(WMI_HW_BLACKLIST_CHAN_EVENTID) \ - OP(WMI_PDEV_SUSPEND_EVENTID) \ - OP(WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID) \ - OP(WMI_VDEV_TPC_IE_POWER_EVENTID) \ - OP(WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID) \ - OP(WMI_FW_READY_IND_EVENTID) \ - OP(WMI_WLAN_MODE_RESP_EVENTID) \ - OP(WMI_NAN_ENABLE_RSP_EVENTID) \ - OP(WMI_NAN_NEXT_DW_INFO_EVENTID) \ - OP(WMI_NAN_DISABLE_CNF_EVENTID) \ - OP(WMI_NAN_DISABLE_IND_EVENTID) \ - OP(WMI_CFR_CAPTURE_FILTER_RESP_EVENTID) \ - OP(WMI_VDEV_UNIFIED_CONNECT_EVENTID) \ - OP(WMI_VDEV_UNIFIED_DISCONNECT_EVENTID) \ - OP(WMI_IPA_RING_STATS_CONF_EVENTID) \ - OP(WMI_PDEV_UHR_CU_EVENTID) \ - OP(WMI_PDEV_POWER_DATAPATH_STATS_EVENTID) \ - OP(WMI_SMD_ROAM_CONFIG_EVENTID) \ - OP(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID) \ - OP(WMI_GET_SCAN_STATS_RESP_EVENTID) \ - OP(WMI_SOC_GET_CONC_INFO_RESP_EVENTID) \ - OP(WMI_NAN_LOCAL_SCHEDULE_CNF_EVENTID) \ - OP(WMI_NAN_PEER_SCHEDULE_CNF_EVENTID) \ - OP(WMI_NAN_PEER_PARAMS_CNF_EVENTID) \ - OP(WMI_ENERGY_MGMT_OEM_DATA_EVENTID) \ - OP(WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID) \ - OP(WMI_COEX_GET_POLICY_STATS_EVENTID) \ - OP(WMI_PDEV_SET_CUMAC_CHIP_ID_CONFIRMATION_EVENTID) \ - OP(WMI_NDP_CHANNEL_INFO_EVENTID) \ - OP(WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID) \ - OP(WMI_TDLS_STATS_EVENTID) \ - OP(WMI_GET_CHIPSET_LOGGING_STATS_EVENTID) \ - OP(WMI_ANOMALY_REPORT_EVENTID) \ - OP(WMI_RTT_PEER_MEAS_REPORT_EVENTID) \ - OP(WMI_VDEV_CHAN_HOP_STATUS_REPORT_EVENTID) \ - OP(WMI_LPI_SCAN_RESULT_EVENTID_V2) \ - OP(WMI_NAN_DISC_SERVICE_RSP_EVENTID) \ - OP(WMI_NAN_DISC_MATCH_EVENTID) \ - OP(WMI_NAN_DISC_SERVICE_REQ_TERMINATED_EVENTID) \ - OP(WMI_MODIFY_TX_PLIM_EVENTID) \ - OP(WMI_AVG_TX_POWER_EVENTID) \ - OP(WMI_PLIMIT_TABLE_EVENTID) \ - OP(WMI_ATHDIAG_READ_WRITE_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -2673,41 +2392,14 @@ WMITLV_CREATE_PARAM_STRUC(WMI_INIT_CMDID); #define WMITLV_TABLE_WMI_PEER_CREATE_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param, wmi_peer_create_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, mlo_params, WMITLV_SIZE_VAR) -/* NOTE: - * To maintain compatibility, any new TLV addition in WMI_PEER_CREATE_CMDID - * needs to also be included as a TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID and - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID. - * - * WMI_VDEV_UNIFIED_CONNECT_CMDID substitutes for 5 connection related - * cmds: - * WMI_PEER_CREATE_CMDID, - * WMI_VDEV_START_REQUEST_CMDID, - * WMI_PEER_ASSOC_CMDID, - * WMI_PEER_ASSOC_V2_CMDID, - * WMI_VDEV_UP_CMDID - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID substitutes for 4 connection related - * cmds: - * WMI_PEER_CREATE_CMDID, - * WMI_PEER_ASSOC_CMDID, - * WMI_PEER_ASSOC_V2_CMDID, - * WMI_VDEV_INSTALL_KEY - */ + WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CREATE_CMDID); /* Peer delete Cmd */ #define WMITLV_TABLE_WMI_PEER_DELETE_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_cmd_fixed_param, wmi_peer_delete_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_delete_mlo_params, mlo_params, WMITLV_SIZE_VAR) -/* NOTE: - * Any new TLV addition in WMI_PEER_DELETE_CMDID needs to be included as - * TLV in WMI_VDEV_UNIFIED_DISCONNECT_CMDID as well to maintain compatibility. - * - * WMI_VDEV_UNIFIED_DISCONNECT_CMDID substitutes for 3 disconnection related - * cmds: - * WMI_PEER_DELETE_CMDID, - * WMI_VDEV_STOP_CMDID, - * WMI_VDEV_DOWN_CMDID - */ + WMITLV_CREATE_PARAM_STRUC(WMI_PEER_DELETE_CMDID); /* Delete all peer Cmd */ @@ -3065,22 +2757,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_WMM_PARAMS_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_mlo_params, mlo_params, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_partner_link_params, partner_link_params, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, dbw_chan, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, dbw_chan_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_smd_params, smd_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_uhr_config, uhr_config, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_npca_params, npca_params, WMITLV_SIZE_VAR) -/* NOTE: - * Any new TLV addition in WMI_VDEV_START_REQUEST_CMDID needs to be included as - * TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID as well to maintain compatibility. - * - * WMI_VDEV_UNIFIED_CONNECT_CMDID substitutes for 5 connection related - * cmds: - * WMI_PEER_CREATE_CMDID, - * WMI_VDEV_START_REQUEST_CMDID, - * WMI_PEER_ASSOC_CMDID, - * WMI_PEER_ASSOC_V2_CMDID, - * WMI_VDEV_UP_CMDID - */ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, dbw_chan_info, WMITLV_SIZE_VAR) + WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_START_REQUEST_CMDID); /* Vdev restart request cmd */ @@ -3159,16 +2837,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_FD_TMPL_CMDID); #define WMITLV_TABLE_WMI_VDEV_INSTALL_KEY_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_cmd_fixed_param, wmi_vdev_install_key_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, key_data, WMITLV_SIZE_VAR) -/* NOTE: - * To maintain compatibility, any new TLV added in WMI_VDEV_INSTALL_KEY_CMDID - * needs to be included as a TLV in WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID too. - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID substitutes for 4 connection related - * cmds: - * WMI_PEER_CREATE_CMDID, - * WMI_PEER_ASSOC_CMDID, - * WMI_PEER_ASSOC_V2_CMDID, - * WMI_VDEV_INSTALL_KEY - */ + WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_INSTALL_KEY_CMDID); /* VDEV set LTF key seed Cmd */ @@ -3198,72 +2867,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_params, mlo_params, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_eht_rate_set, peer_eht_rates, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_partner_link_params, partner_link_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_tid_to_link_map, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, operating_mode_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, mgmt_mpduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, mgmt_msduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, hol_mdsuq_params, WMITLV_SIZE_VAR) -/* NOTE: - * No further TLVs can be added to this message; - * it is already at the target's WMI_MAX_NUM_TLVS limit (13). - * - * Note that the WMI_PEER_ASSOC_V2_CMDID (below) can support additional TLVs. - */ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_tid_to_link_map, WMITLV_SIZE_VAR) + WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CMDID); -/* WMI_PEER_ASSOC_V2_CMD - version 2 of the PEER_ASSOC cmd, allowing more TLVs - * This cmd message mirrors the WMI_PEER_ASSOC_CMDID message, but has the - * capacity for extra TLVs beyond those in the WMI_PEER_ASSOC_CMDID definition. - * This message can only be used if the target advertises support for - * WMI_MAX_NUM_EXT_TLVS (via the WMI_SERVICE_EXT_TLV_SUPPORT flag). - */ -#define WMITLV_TABLE_WMI_PEER_ASSOC_V2_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, wmi_peer_assoc_complete_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_legacy_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_ht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vht_rate_set, wmi_vht_rate_set, peer_vht_rates, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_he_rate_set, peer_he_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_params, mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_eht_rate_set, peer_eht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_partner_link_params, partner_link_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_tid_to_link_map, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, operating_mode_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, mgmt_mpduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, mgmt_msduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, hol_mdsuq_params, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_cap_params, peer_npca_cap_params, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, create_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, cfp_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_rate_set, peer_uhr_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_op_params, npca_op_params, WMITLV_SIZE_VAR) -/* NOTE: - * To maintain compatibility, any new TLV added in WMI_PEER_ASSOC_V2_CMDID - * needs to be also included as a TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID and - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID. - * - * WMI_VDEV_UNIFIED_CONNECT_CMDID substitutes for 5 connection related - * cmds: - * WMI_PEER_CREATE_CMDID, - * WMI_VDEV_START_REQUEST_CMDID, - * WMI_PEER_ASSOC_CMDID, - * WMI_PEER_ASSOC_V2_CMDID, - * WMI_VDEV_UP_CMDID - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID substitutes for 4 connection related - * cmds: - * WMI_PEER_CREATE_CMDID, - * WMI_PEER_ASSOC_CMDID, - * WMI_PEER_ASSOC_V2_CMDID, - * WMI_VDEV_INSTALL_KEY - */ -WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_V2_CMDID); - -#define WMITLV_TABLE_WMI_PEER_UHR_OMP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_uhr_omp_cmd_fixed_param, wmi_peer_uhr_omp_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_omp_npca_params, peer_omp_npca_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_omp_sta_dps_params, peer_omp_dps_params, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PEER_UHR_OMP_CMDID); - /* Peer Set Rate Report Condition Cmd */ #define WMITLV_TABLE_WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_set_rate_report_condition_fixed_param, wmi_peer_set_rate_report_condition_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -3484,12 +3091,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_UNIFIED_LL_GET_STA_CMDID); WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_WLM_STATS_CMDID); -/* Get chipset debug log stats Cmd */ -#define WMITLV_TABLE_WMI_GET_CHIPSET_LOGGING_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_cmd_fixed_param, wmi_get_chipset_logging_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) - -WMITLV_CREATE_PARAM_STRUC(WMI_GET_CHIPSET_LOGGING_STATS_CMDID); - /* Network list offload config Cmd */ #define WMITLV_TABLE_WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nlo_config_cmd_fixed_param, wmi_nlo_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ @@ -3834,8 +3435,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_AP_PROFILE); /* Roam sync complete Cmd */ #define WMITLV_TABLE_WMI_ROAM_SYNCH_COMPLETE(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_synch_complete_fixed_param, wmi_roam_synch_complete_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_response_tlv_param, vdev_repurpose_response_tlv, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_synch_complete_fixed_param, wmi_roam_synch_complete_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SYNCH_COMPLETE); @@ -3999,8 +3599,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_create_cmd_fixed_param, wmi_vdev_create_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_txrx_streams, cfg_txrx_streams, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_create_mlo_params, mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_create_wfdr2_mode_params, wfdr2_mode, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_create_tbtt_count_down_offset_info, offset_info, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_create_wfdr2_mode_params, wfdr2_mode, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CREATE_CMDID); @@ -4012,51 +3611,21 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DELETE_CMDID); /* Vdev up Cmd */ #define WMITLV_TABLE_WMI_VDEV_UP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_up_cmd_fixed_param, wmi_vdev_up_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_co_located_chan_info, co_located_chan_info, WMITLV_SIZE_VAR) -/* NOTE: - * Any new TLV addition in WMI_VDEV_UP_CMDID needs to be included as - * TLV in WMI_VDEV_UNIFIED_CONNECT_CMDID as well to maintain compatibility. - * - * WMI_VDEV_UNIFIED_CONNECT_CMDID substitutes for 5 connection related - * cmds: - * WMI_PEER_CREATE_CMDID, - * WMI_VDEV_START_REQUEST_CMDID, - * WMI_PEER_ASSOC_CMDID, - * WMI_PEER_ASSOC_V2_CMDID, - * WMI_VDEV_UP_CMDID - */ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_up_cmd_fixed_param, wmi_vdev_up_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UP_CMDID); /* Vdev stop cmd */ #define WMITLV_TABLE_WMI_VDEV_STOP_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stop_cmd_fixed_param, wmi_vdev_stop_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_stop_mlo_params, mlo_params, WMITLV_SIZE_VAR) -/* NOTE: - * Any new TLV addition in WMI_VDEV_STOP_CMDID needs to be included as - * TLV in WMI_VDEV_UNIFIED_DISCONNECT_CMDID as well to maintain compatibility. - * - * WMI_VDEV_UNIFIED_DISCONNECT_CMDID substitutes for 3 disconnection related - * cmds: - * WMI_PEER_DELETE_CMDID, - * WMI_VDEV_STOP_CMDID, - * WMI_VDEV_DOWN_CMDID - */ + WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STOP_CMDID); /* Vdev down Cmd */ #define WMITLV_TABLE_WMI_VDEV_DOWN_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_down_cmd_fixed_param, wmi_vdev_down_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -/* NOTE: - * Any new TLV addition in WMI_VDEV_STOP_CMDID needs to be included as - * TLV in WMI_VDEV_UNIFIED_DISCONNECT_CMDID as well to maintain compatibility. - * - * WMI_VDEV_UNIFIED_DISCONNECT_CMDID substitutes for 3 disconnection related - * cmds: - * WMI_PEER_DELETE_CMDID, - * WMI_VDEV_STOP_CMDID, - * WMI_VDEV_DOWN_CMDID - */ + WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DOWN_CMDID); /* Vdev set param Cmd */ @@ -4074,8 +3643,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UPDATE_MAC_ADDR_CMDID); #define WMITLV_TABLE_WMI_VDEV_VBSS_CONFIG_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vbss_config_cmd_fixed_param, wmi_vdev_vbss_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_pn_info, vbss_peer_pn_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_sn_info, vbss_peer_sn_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_dyn_info, vbss_peer_dyn_info, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_sn_info, vbss_peer_sn_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_VBSS_CONFIG_CMDID); /* Pdev suspend Cmd */ @@ -4095,18 +3663,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_RESUME_CMDID); WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_UPDATE_REQUEST_CMDID); -/* suppress scan Cmd */ -#define WMITLV_TABLE_WMI_SCAN_SUPPRESS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_scan_suppress_cmd_fixed_param, wmi_scan_suppress_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) - -WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_SUPPRESS_CMDID); - -/* get scan stats Cmd */ -#define WMITLV_TABLE_WMI_GET_SCAN_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_scan_stats_cmd_fixed_param, wmi_get_scan_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) - -WMITLV_CREATE_PARAM_STRUC(WMI_GET_SCAN_STATS_CMDID); - #define WMITLV_TABLE_WMI_SCAN_PROB_REQ_OUI_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_scan_prob_req_oui_cmd_fixed_param, wmi_scan_prob_req_oui_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vendor_oui, vendor_oui, WMITLV_SIZE_VAR) @@ -4119,11 +3675,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_PROB_REQ_OUI_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_CONFIG_VENDOR_OUI_ACTION_CMDID); -/* get concurrency info Cmd */ -#define WMITLV_TABLE_WMI_SOC_GET_CONC_INFO_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_soc_get_conc_info_cmd_fixed_param, wmi_soc_get_conc_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_SOC_GET_CONC_INFO_CMDID); - #define WMITLV_TABLE_WMI_CHATTER_ADD_COALESCING_FILTER_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len,WMITLV_TAG_STRUC_wmi_chatter_coalescing_add_filter_cmd_fixed_param, wmi_chatter_coalescing_add_filter_cmd_fixed_param, fixed_param,WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, chatter_pkt_coalescing_filter, coalescing_filter, WMITLV_SIZE_VAR) @@ -4429,20 +3980,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DSM_FILTER_CMDID); WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, non_tx_bssid, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_P2P_GO_DFS_AP_CONFIG_CMDID); -/* Configure roam SMD parameters */ -#define WMITLV_TABLE_WMI_ROAM_SMD_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_smd_config_cmd_fixed_param, wmi_roam_smd_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SMD_CONFIG_CMDID); - -/* SMD preparation completion status command */ -#define WMITLV_TABLE_WMI_ROAM_SMD_START_STATUS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_smd_start_status_cmd_fixed_param, wmi_roam_smd_start_status_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_response_tlv_param, vdev_repurpose_response_tlv, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, smd_transition_ie, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_prep_resp_status_list, status_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, kck, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SMD_START_STATUS_CMDID); - #define WMITLV_TABLE_WMI_ROAM_BLACKLIST_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_blacklist_event_fixed_param, wmi_roam_blacklist_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_blacklist_with_timeout_tlv_param, blacklist_with_timeout, WMITLV_SIZE_VAR) @@ -4459,22 +3996,15 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_PREAUTH_START_EVENTID); WMITLV_CREATE_PARAM_STRUC(WMI_LPI_RESULT_EVENTID); /* LPI Status Event */ -#define WMITLV_TABLE_WMI_LPI_STATUS_EVENTID(id,op,buf,len) \ +#define WMITLV_TABLE_WMI_LPI_STATUS_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_status_event_fixed_param, wmi_lpi_status_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_LPI_STATUS_EVENTID); /* LPI Handoff Event */ -#define WMITLV_TABLE_WMI_LPI_HANDOFF_EVENTID(id,op,buf,len) \ +#define WMITLV_TABLE_WMI_LPI_HANDOFF_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_handoff_event_fixed_param, wmi_lpi_handoff_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_LPI_HANDOFF_EVENTID); -/* LPI Scan Result Indication Event */ -#define WMITLV_TABLE_WMI_LPI_SCAN_RESULT_EVENTID_V2(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_scan_result_ind_fixed_param, wmi_lpi_scan_result_ind_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, freq_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_lpi_ap_info_t, ap_array, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_LPI_SCAN_RESULT_EVENTID_V2); - /* Thermal Manager Params*/ #define WMITLV_TABLE_WMI_THERMAL_MGMT_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_thermal_mgmt_cmd_fixed_param, wmi_thermal_mgmt_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -4505,132 +4035,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NAN_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_oem_data_buffer, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_NAN_OEM_DATA_CMDID); -/* NAN Enable Command */ -#define WMITLV_TABLE_WMI_NAN_ENABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_enable_cmd_fixed_param, wmi_nan_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_ctrl_config_param, nan_ctrl_config, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_disc_band_config_param, nan_disc_band_config, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_ENABLE_CMDID); - -/* NAN Config Command */ -#define WMITLV_TABLE_WMI_NAN_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_config_cmd_fixed_param, wmi_nan_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_ctrl_config_param, nan_ctrl_config, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_disc_band_config_param, nan_disc_band_config, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_availability_attributes_data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_CONFIG_CMDID); - -/* NAN Disable Command */ -#define WMITLV_TABLE_WMI_NAN_DISABLE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disable_cmd_fixed_param, wmi_nan_disable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISABLE_CMDID); - -/* NAN local Schedule Command */ -#define WMITLV_TABLE_WMI_NAN_LOCAL_SCHEDULE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_local_schedule_cmd_fixed_param, wmi_nan_local_schedule_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_schedule_chan_bitmap, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_channel, committed_channel_list, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_LOCAL_SCHEDULE_CMDID); - -/* NAN Peer Schedule Command */ -#define WMITLV_TABLE_WMI_NAN_PEER_SCHEDULE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cmd_fixed_param, wmi_nan_peer_schedule_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_schedule_chan_bitmap, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_channel, committed_channel_list, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_PEER_SCHEDULE_CMDID); - -/* NAN Peer Params Command */ -#define WMITLV_TABLE_WMI_NAN_PEER_PARAMS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_peer_params_cmd_fixed_param, wmi_nan_peer_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_caps_ie_data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_PEER_PARAMS_CMDID); - -/** - * NAN Discovery Service Request Command - * (NL80211_CMD_ADD_NAN_FUNCTION equivalent) - * - * Carries all parameters needed to register a NAN Publish, Subscribe, or - * Follow-up function with the firmware in offload mode. - * - * TLV layout (in order): - * - * [0] wmi_nan_disc_service_req_cmd_fixed_param fixed_param - * All fixed scalar fields: vdev_id, service_req_type, instance_id, ttl, - * publish_type, followup_instance_id, followup_requestor_id, - * followup_dest, sdea_ctrl, pairing_bootstrap_methods, srf_bf_idx, - * srf_include, service_req_flags, and all _len / _num count fields. - * - * [1] A_UINT8 service_id[] - * 6-byte NAN Service ID (SHA-256 of service name, first 6 bytes), - * zero-padded to 8 bytes for 4-byte WMI alignment. - * Maps to: NL80211_ATTR_NAN_FUNC_SERVICE_ID / cfg80211_nan_func.service_id - * - * [2] A_UINT8 serv_spec_info[] - * Service Specific Info — opaque application payload, max 255 bytes. - * Valid byte count given by fixed_param.serv_spec_info_len. - * Maps to: NL80211_ATTR_NAN_FUNC_SERVICE_INFO / - * cfg80211_nan_func.serv_spec_info - * - * [3] A_UINT8 srf_bf[] - * SRF (Service Range Filter) Bloom filter data. - * Valid byte count given by fixed_param.srf_bf_len. - * Maps to: NL80211_ATTR_NAN_FUNC_SRF_BF / cfg80211_nan_func.srf_bf - * - * [4] wmi_mac_addr srf_macs[] - * SRF MAC address filter list (WMITLV_TAG_ARRAY_FIXED_STRUC). - * Entry count given by fixed_param.num_srf_macs. - * Maps to: NL80211_ATTR_NAN_FUNC_SRF_MAC_ADDRS / - * cfg80211_nan_func.srf_macs - * - * [5] A_UINT8 rx_match_filter[] - * RX match filter byte stream (ieee80211 protocol order). - * Valid byte count given by fixed_param.rx_match_filter_len. - * Maps to: NL80211_ATTR_NAN_FUNC_RX_MATCH_FILTER / - * cfg80211_nan_func.rx_filters - * - * [6] A_UINT8 tx_match_filter[] - * TX match filter byte stream (ieee80211 protocol order). - * Valid byte count given by fixed_param.tx_match_filter_len. - * Maps to: NL80211_ATTR_NAN_FUNC_TX_MATCH_FILTER / - * cfg80211_nan_func.tx_filters - * - * [7] A_UINT32 cipher_suites[] - * Array of supported NAN cipher suite IDs (CSIDs). - * Entry count given by fixed_param.num_cipher_suites. - * Maps to: NL80211_ATTR_NAN_FUNC_CIPHER_SUITES / - * cfg80211_nan_func.cipher_suites - * - * [8] A_UINT8 nd_pmk[] - * NAN Data Path PMK, exactly 32 bytes when present. - * Present and valid only when - * WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_ND_PMK_VALID( - * fixed_param.service_req_flags) == 1; - * zero-length TLV otherwise. - * Maps to: NL80211_ATTR_NAN_FUNC_ND_PMK / cfg80211_nan_func.nd_pmk - */ -#define WMITLV_TABLE_WMI_NAN_DISC_SERVICE_REQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_service_req_cmd_fixed_param, wmi_nan_disc_service_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, service_id, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, serv_spec_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, srf_bf, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, srf_macs, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, rx_match_filter, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, tx_match_filter, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, cipher_suites, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nd_pmk, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, extra_nan_attrs, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISC_SERVICE_REQ_CMDID); - -/** NAN Discovery Delete Function Cmd - * - * TLV (tag length value) parameters follow the - * wmi_nan_disc_cancel_service_req_cmd_fixed_param structure. The TLV's are: - * wmi_nan_disc_cancel_service_req_cmd_fixed_param fixed_param; - */ -#define WMITLV_TABLE_WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_cancel_service_req_cmd_fixed_param, wmi_nan_disc_cancel_service_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID); - /* NAN Data Get Capabilities Cmd */ #define WMITLV_TABLE_WMI_NDI_GET_CAP_REQ_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndi_get_cap_req_fixed_param, wmi_ndi_get_cap_req_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) @@ -4695,11 +4099,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NDP_END_REQ_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_cmd_param, wmi_ndp_cmd_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_NDP_CMDID); -/* NDP Set Latency Tput Cmd */ -#define WMITLV_TABLE_WMI_NDP_SET_LATENCY_TPUT_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_set_latency_tput_fixed_param, wmi_ndp_set_latency_tput_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NDP_SET_LATENCY_TPUT_CMDID); - /* RCPI Info Request Cmd */ #define WMITLV_TABLE_WMI_REQUEST_RCPI_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_request_rcpi_cmd_fixed_param, wmi_request_rcpi_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -5104,8 +4503,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_BPF_GET_VDEV_WORK_MEMORY_CMDID); /* Enable/Disable Smart Antenna */ #define WMITLV_TABLE_WMI_PDEV_SMART_ANT_ENABLE_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_smart_ant_enable_cmd_fixed_param, wmi_pdev_smart_ant_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_smart_ant_gpio_handle, gpio_handle, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, pdev_smart_ant_param, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_smart_ant_gpio_handle, gpio_handle, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SMART_ANT_ENABLE_CMDID); /* Set Smart Antenna RX antenna */ @@ -5353,14 +4751,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MNT_FILTER_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_chip_power_stats_cmd_fixed_param, wmi_pdev_get_chip_power_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_CHIP_POWER_STATS_CMDID); -/* - * WMI command for setting the pdev power stats enable/disable - * and getting the pdev power stats - */ -#define WMITLV_TABLE_WMI_PDEV_POWER_DATAPATH_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_cmd_fixed_param, wmi_pdev_power_datapath_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_POWER_DATAPATH_STATS_CMDID); - /* WLAN GET mws conflict */ #define WMITLV_TABLE_WMI_VDEV_GET_MWS_COEX_INFO_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_info_cmd_fixed_param, wmi_vdev_get_mws_coex_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -5409,11 +4799,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_CTRL_PATH_STATS_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, mac_addr_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_HALPHY_CTRL_PATH_STATS_CMDID); -/* Request TDLS Stats cmd enabling the monitoring of TDLS stats */ -#define WMITLV_TABLE_WMI_REQUEST_TDLS_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_request_tdls_stats_cmd_fixed_param, wmi_request_tdls_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_TDLS_STATS_CMDID); - /* Host sets the current country code */ #define WMITLV_TABLE_WMI_SET_CURRENT_COUNTRY_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_set_current_country_cmd_fixed_param, wmi_set_current_country_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -5466,8 +4851,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MESH_RX_FILTER_ENABLE_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, preferred_tx_stream_list, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, preferred_rx_stream_list, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, dbw_chan, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, dbw_chan_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_npca_params, npca_params, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, dbw_chan_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID); #define WMITLV_TABLE_WMI_PDEV_UPDATE_PKT_ROUTING_CMDID(id,op,buf,len) \ @@ -5604,12 +4988,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_RUNTIME_DPD_RECAL_CMDID); WMITLV_CREATE_PARAM_STRUC(WMI_GET_TPC_POWER_CMDID); -/** Get TPC IE TX power value */ -#define WMITLV_TABLE_WMI_VDEV_GET_TPC_IE_POWER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_tpc_ie_power_cmd_fixed_param, wmi_vdev_get_tpc_ie_power_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) - -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_TPC_IE_POWER_CMDID); - /* TWT enable cmd */ #define WMITLV_TABLE_WMI_TWT_ENABLE_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_twt_enable_cmd_fixed_param, wmi_twt_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -5703,12 +5081,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CHAN_WIDTH_SWITCH_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_list, peer_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_BULK_SET_CMDID); -/* Multi Peer UHR Mode Update command */ -#define WMITLV_TABLE_WMI_PEER_UHR_MODE_UPDATE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_uhr_mode_update_cmd_fixed_param, wmi_peer_uhr_mode_update_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_cap_params, peer_npca_cap_params, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PEER_UHR_MODE_UPDATE_CMDID); - /* OBSS_PD Spatial_Reuse Set Default OBSS Thresholds */ #define WMITLV_TABLE_WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_obss_spatial_reuse_set_def_obss_thresh_cmd_fixed_param, wmi_obss_spatial_reuse_set_def_obss_thresh_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -5825,8 +5197,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_AUDIO_AGGR_GET_SCHED_METHOD_CMDID); /* CFR Capture Filter cmd */ #define WMITLV_TABLE_WMI_CFR_CAPTURE_FILTER_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_cfr_capture_filter_cmd_fixed_param, wmi_cfr_capture_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cfr_filter_group_config, filter_group_config, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cfr_capture_fix_agc_gain_config, fix_agc_gain_config, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cfr_filter_group_config, filter_group_config, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CFR_CAPTURE_FILTER_CMDID); /* VLAN config */ @@ -5906,8 +5277,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SIMULATION_TEST_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_csa, wfa_config_csa, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_ocv, wfa_config_ocv, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_saquery, wfa_config_saquery, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_ofdma, wfa_config_ofdma, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_ml, wfa_config_ml, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wfa_config_ofdma, wfa_config_ofdma, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_WFA_CONFIG_CMDID); /* SRG OBSS color Enable Bitmap */ @@ -6014,11 +5384,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_RECONFIG_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_reconfig_complete_fixed_param, wmi_mlo_link_reconfig_complete_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_RECONFIG_COMPLETE_CMDID); -/** WMI cmd to notify fw completion of link TTLM negotiation */ -#define WMITLV_TABLE_WMI_MLO_LINK_TTLM_COMPLETE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_ttlm_complete_fixed_param, wmi_mlo_link_ttlm_complete_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_TTLM_COMPLETE_CMDID); - /* Mcast ipv4 address filter list cmd */ #define WMITLV_TABLE_WMI_VDEV_IGMP_OFFLOAD_CMDID(id,op,buf,len) \ WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_igmp_offload_fixed_param, wmi_igmp_offload_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ @@ -6376,308 +5741,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_POWER_BOOST_MEM_ADDR_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_scan_cache_result_cmd_fixed_param, wmi_get_scan_cache_result_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_GET_SCAN_CACHE_RESULT_CMDID); -#define WMITLV_TABLE_WMI_SET_MODIFY_TX_PLIM_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_set_modify_tx_plim_cmd_fixed_param, wmi_set_modify_tx_plim_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_SET_MODIFY_TX_PLIM_CMDID); - -#define WMITLV_TABLE_WMI_GET_AVG_TX_POWER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_avg_tx_power_cmd_fixed_param, wmi_get_avg_tx_power_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_GET_AVG_TX_POWER_CMDID); - -#define WMITLV_TABLE_WMI_GET_TX_POWER_CALLING_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_tx_power_calling_cmd_fixed_param, wmi_get_tx_power_calling_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_GET_TX_POWER_CALLING_CMDID); - #define WMITLV_TABLE_WMI_SAWF_EZMESH_HOP_COUNT_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sawf_ezmesh_hop_count_cmd_fixed_param, wmi_sawf_ezmesh_hop_count_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SAWF_EZMESH_HOP_COUNT_CMDID); -#define WMITLV_TABLE_WMI_BPF_SET_SUPPORTED_OFFLOAD_BITMAP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bpf_set_supported_offload_bitmap_cmd_fixed_param, wmi_bpf_set_supported_offload_bitmap_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_BPF_SET_SUPPORTED_OFFLOAD_BITMAP_CMDID); - -#define WMITLV_TABLE_WMI_BPF_SET_APF_MODE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bpf_set_apf_mode_cmd_fixed_param, wmi_bpf_set_apf_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_BPF_SET_APF_MODE_CMDID); - -/* WMI cmd used to control PCIe config */ -#define WMITLV_TABLE_WMI_ENERGY_MGMT_PCIE_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_pcie_config_cmd_fixed_param, wmi_energy_mgmt_pcie_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_PCIE_CONFIG_CMDID); - -/* WMI cmd used for PCIe LPM config */ -#define WMITLV_TABLE_WMI_ENERGY_MGMT_PCIE_LPM_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_pcie_lpm_cmd_fixed_param, wmi_energy_mgmt_pcie_lpm_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_PCIE_LPM_CMDID); - -/* WMI cmd used to control DCVS config */ -#define WMITLV_TABLE_WMI_ENERGY_MGMT_DCVS_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_dcvs_config_cmd_fixed_param, wmi_energy_mgmt_dcvs_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_DCVS_CONFIG_CMDID); - -/* WMI cmd used to control Dynamic AP Power Save config */ -#define WMITLV_TABLE_WMI_ENERGY_MGMT_EDPS_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_edps_config_cmd_fixed_param, wmi_energy_mgmt_edps_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_EDPS_CONFIG_CMDID); - -/* WMI cmd used to control Scheduled AP Power Save config */ -#define WMITLV_TABLE_WMI_ENERGY_MGMT_PUO_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_puo_config_cmd_fixed_param, wmi_energy_mgmt_puo_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_PUO_CONFIG_CMDID); - -/* WMI cmd used to control Un-scheduled AP Power Save config */ -#define WMITLV_TABLE_WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_eco_mode_config_cmd_fixed_param, wmi_energy_mgmt_eco_mode_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID); - -/* peer tid rate customization cmd */ -#define WMITLV_TABLE_WMI_PEER_TID_RATE_CUSTOM_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_tid_rate_custom_cmd_fixed_param, wmi_peer_tid_rate_custom_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, rate_code, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TID_RATE_CUSTOM_CMDID); - -/* pdev per-vdev queue depth report request cmd */ -#define WMITLV_TABLE_WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param, wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID); - -/* vdev traffic monitoring request cmd */ -#define WMITLV_TABLE_WMI_VDEV_TRAFFIC_MONITORING_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_traffic_monitoring_cmd_fixed_param, wmi_vdev_traffic_monitoring_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_TRAFFIC_MONITORING_CMDID); - -/* WMI command to control Dynamic Power Save - AP Assisting role config */ -#define WMITLV_TABLE_WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param, wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID); - -/* WMI cmd to specify the driver's mode of operation */ -#define WMITLV_TABLE_WMI_WLAN_MODE_REQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlan_mode_req_cmd_fixed_param, wmi_wlan_mode_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_MODE_REQ_CMDID); - - -/* WMI command for unified connect cmd */ -#define WMITLV_TABLE_WMI_VDEV_UNIFIED_CONNECT_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_unified_connect_cmd_fixed_param, wmi_vdev_unified_connect_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param, wmi_peer_create_cmd_fixed_param, peer_create_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, peer_create_mlo_params, WMITLV_SIZE_VAR) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_start_request_cmd_fixed_param, wmi_vdev_start_request_cmd_fixed_param, vdev_start_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_channel, wmi_channel, vdev_start_chan, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_p2p_noa_descriptor, vdev_start_noa_descriptors, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_mlo_params, vdev_start_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_partner_link_params, vdev_start_partner_link_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, vdev_start_dbw_chan, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dbw_chan_info, vdev_start_dbw_chan_info, WMITLV_SIZE_VAR) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, wmi_peer_assoc_complete_cmd_fixed_param, peer_assoc_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_peer_legacy_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_peer_ht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vht_rate_set, wmi_vht_rate_set, peer_assoc_peer_vht_rates, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_he_rate_set, peer_assoc_peer_he_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_params, peer_assoc_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_eht_rate_set, peer_assoc_peer_eht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_partner_link_params, peer_assoc_partner_link_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_assoc_peer_tid_to_link_map, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, peer_assoc_operating_mode_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, peer_assoc_mgmt_mpduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, peer_assoc_mgmt_msduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, peer_assoc_hol_mdsuq_params, WMITLV_SIZE_VAR) \ - /*---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, wmi_peer_assoc_complete_cmd_fixed_param, peer_assoc_v2_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_v2_peer_legacy_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_v2_peer_ht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vht_rate_set, wmi_vht_rate_set, peer_assoc_v2_peer_vht_rates, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_he_rate_set, peer_assoc_v2_peer_he_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_params, peer_assoc_v2_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_eht_rate_set, peer_assoc_v2_peer_eht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_partner_link_params, peer_assoc_v2_partner_link_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_assoc_v2_peer_tid_to_link_map, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, peer_assoc_v2_operating_mode_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, peer_assoc_v2_mgmt_mpduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, peer_assoc_v2_mgmt_msduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, peer_assoc_v2_hol_mdsuq_params, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_cap_params, peer_assoc_v2_peer_npca_cap_params, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, peer_assoc_v2_create_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, peer_assoc_v2_cfp_params, WMITLV_SIZE_FIX) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_up_cmd_fixed_param, wmi_vdev_up_cmd_fixed_param, vdev_up_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_co_located_chan_info, vdev_up_co_located_chan_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, smd_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_start_smd_params, vdev_smd_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, peer_assoc_v2_smd_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_rate_set, peer_uhr_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_op_params, npca_op_params, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_CONNECT_CMDID); - -/* WMI command for unified disconnect cmd */ -#define WMITLV_TABLE_WMI_VDEV_UNIFIED_DISCONNECT_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_cmd_fixed_param, wmi_vdev_unified_disconnect_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_cmd_fixed_param, wmi_peer_delete_cmd_fixed_param, peer_delete_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_delete_mlo_params, peer_delete_mlo_params, WMITLV_SIZE_VAR) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stop_cmd_fixed_param, wmi_vdev_stop_cmd_fixed_param, vdev_stop_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_stop_mlo_params, vdev_stop_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_down_cmd_fixed_param, wmi_vdev_down_cmd_fixed_param, vdev_down_fixed_param, WMITLV_SIZE_FIX) - -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_DISCONNECT_CMDID); - -/** WMI cmd for response of wmi_vdev_repurpose_request_tlv_param */ -#define WMITLV_TABLE_WMI_VDEV_REPURPOSE_RESP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_repurpose_resp_cmd_fixed_param, wmi_vdev_repurpose_resp_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_response_tlv_param, vdev_repurpose_response_tlv, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_REPURPOSE_RESP_CMDID); - -/* Get IPA ring stats */ -#define WMITLV_TABLE_WMI_IPA_RING_STATS_REQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ipa_ring_stats_req_cmd_fixed_param, wmi_ipa_ring_stats_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_IPA_RING_STATS_REQ_CMDID); - -#define WMITLV_TABLE_WMI_VDEV_UHR_CU_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_uhr_cu_cmd_fixed_param, wmi_vdev_uhr_cu_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_dps_params, wmi_uhr_ap_dps_params, dps_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_npca_params, wmi_uhr_ap_npca_params, npca_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_duo_params, wmi_uhr_ap_duo_params, duo_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_pedca_params, wmi_uhr_ap_pedca_params, pedca_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_dbe_params, wmi_uhr_ap_dbe_params, dbe_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_puo_params, wmi_uhr_ap_puo_params, puo_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_uhr_ap_elr_reception_params, wmi_uhr_ap_elr_reception_params, elr_reception_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_mode_tuple_enable_disable_update_params, mode_tup_enable_disable_update_params, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UHR_CU_CMDID); - -#define WMITLV_TABLE_WMI_PDEV_UHR_CU_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_cmd_fixed_param, wmi_pdev_uhr_cu_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_dps_params, dps_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_npca_params, npca_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_duo_params, duo_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_pedca_params, pedca_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_dbe_params, dbe_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_puo_params, puo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_elr_reception_params, elr_reception_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_ap_mode_tuple_enable_disable_update_params, mode_tup_enable_disable_update_params, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UHR_CU_CMDID); - -/* WMI command for unified SMD PEER SETUP cmd */ -#define WMITLV_TABLE_WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_cmd_fixed_param, wmi_smd_roam_peer_unified_setup_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_smd_roam_peer_tid_info, smd_roam_peer_tid_info, WMITLV_SIZE_VAR) \ - /*---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param, wmi_peer_create_cmd_fixed_param, peer_create_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, peer_create_mlo_params, WMITLV_SIZE_VAR) \ - /*---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, wmi_peer_assoc_complete_cmd_fixed_param, peer_assoc_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_peer_legacy_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_peer_ht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vht_rate_set, wmi_vht_rate_set, peer_assoc_peer_vht_rates, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_he_rate_set, peer_assoc_peer_he_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_params, peer_assoc_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_eht_rate_set, peer_assoc_peer_eht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_partner_link_params, peer_assoc_partner_link_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_assoc_peer_tid_to_link_map, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, peer_assoc_operating_mode_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, peer_assoc_mgmt_mpduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, peer_assoc_mgmt_msduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, peer_assoc_hol_mdsuq_params, WMITLV_SIZE_VAR) \ - /*---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param, wmi_peer_assoc_complete_cmd_fixed_param, peer_assoc_v2_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_v2_peer_legacy_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, peer_assoc_v2_peer_ht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vht_rate_set, wmi_vht_rate_set, peer_assoc_v2_peer_vht_rates, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_he_rate_set, peer_assoc_v2_peer_he_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_params, peer_assoc_v2_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_eht_rate_set, peer_assoc_v2_peer_eht_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mlo_partner_link_params, peer_assoc_v2_partner_link_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_tid_to_link_map, peer_assoc_v2_peer_tid_to_link_map, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_operating_mode_params, peer_assoc_v2_operating_mode_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_mpduq_params, peer_assoc_v2_mgmt_mpduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_mgmt_msduq_params, peer_assoc_v2_mgmt_msduq_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_assoc_hol_msduq_params, peer_assoc_v2_hol_mdsuq_params, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_cap_params, peer_assoc_v2_peer_npca_cap_params, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_create_mlo_params, peer_assoc_v2_create_mlo_params, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params, wmi_peer_assoc_cfp_params, peer_assoc_v2_cfp_params, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params, wmi_peer_assoc_smd_params, peer_assoc_v2_smd_params, WMITLV_SIZE_FIX) \ - /*---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_cmd_fixed_param, wmi_vdev_install_key_cmd_fixed_param, key_install_fixed_param, WMITLV_SIZE_FIX)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, key_data, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_uhr_rate_set, peer_uhr_rates, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_uhr_npca_op_params, npca_op_params, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID); - -/* WMI command for unified SMD Config cmd */ -#define WMITLV_TABLE_WMI_SMD_ROAM_CONFIG_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_smd_roam_config_cmd_fixed_param, wmi_smd_roam_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_smd_roam_peer_tid_info, smd_roam_peer_tid_info, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_CONFIG_CMDID); - -/* WMI commad to config MAPC params used for co-ordinated AP features in 11bn */ -#define WMITLV_TABLE_WMI_PEER_SET_MAPC_PARAMS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_set_mapc_params_cmd_fixed_param, wmi_peer_set_mapc_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - /*--- Common MAPC params ---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mapc_cmn_params, mapc_cmn_params, WMITLV_SIZE_VAR) \ - /*--- Co-TDMA scheme params ---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mapc_cotdma_params, cotdma_params, WMITLV_SIZE_VAR) \ - /*--- Co-SR scheme params (future) ---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mapc_cosr_params, cosr_params, WMITLV_SIZE_VAR) \ - /*--- Co-BF scheme params (future) ---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mapc_cobf_params, cobf_params, WMITLV_SIZE_VAR) \ - /*--- Co-rTWT scheme params (future) ---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mapc_cortwt_params, cortwt_params, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PEER_SET_MAPC_PARAMS_CMDID); - -/* WMI Command for Energy management OEM cmd data */ -#define WMITLV_TABLE_WMI_ENERGY_MGMT_OEM_DATA_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_fixed_param, wmi_energy_mgmt_oem_data_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_OEM_DATA_CMDID); - -#define WMITLV_TABLE_WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_channel_hopping_schedule_fixed_param, wmi_vdev_channel_hopping_schedule_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) /* DEPRECATED - POPULATE WITH ZERO ELEMS */ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel_hopping_channel_params, channel_param_list, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID); - -/* WMI Command for start ch usage session */ -#define WMITLV_TABLE_WMI_TWT_ADD_CH_USAGE_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ch_usage_add_dialog_cmd_fixed_param, wmi_ch_usage_add_dialog_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_TWT_ADD_CH_USAGE_CMDID); - -/* WMI Command to request CoEx Policy Stats data */ -#define WMITLV_TABLE_WMI_COEX_GET_POLICY_STATS_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_policy_stats_cmd_fixed_param, wmi_coex_policy_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_COEX_GET_POLICY_STATS_CMDID); - -/* WMI command to set CUMAC chip ID cmd */ -#define WMITLV_TABLE_WMI_PDEV_SET_CUMAC_CHIP_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_cmd_fixed_param, wmi_pdev_set_cumac_chip_id_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_CUMAC_CHIP_CMDID); - -/* RTT Peer measurement start request */ -#define WMITLV_TABLE_WMI_RTT_PEER_MEAS_REQ_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_cmd_fixed_param, wmi_rtt_peer_meas_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_peer_meas_req_peer_info, peer_info, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PEER_MEAS_REQ_CMDID); - -/* RTT Peer measurement cancel request */ -#define WMITLV_TABLE_WMI_RTT_PEER_MEAS_CANCEL_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_peer_meas_cancel_meas_cmd_fix_param, wmi_rtt_peer_meas_cancel_meas_cmd_fix_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PEER_MEAS_CANCEL_CMDID); - -#define WMITLV_TABLE_WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_chan_hop_status_report_cmd_fixed_param, wmi_vdev_get_chan_hop_status_report_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID); - -/* Athdiag read/write command: fixed_param + optional write data TLV */ -#define WMITLV_TABLE_WMI_ATHDIAG_READ_WRITE_CMDID(id, op, buf, len) \ - WMITLV_ELEM(id, op, buf, len, \ - WMITLV_TAG_STRUC_wmi_athdiag_read_write_cmd_fixed_param, \ - wmi_athdiag_read_write_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id, op, buf, len, \ - WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_ATHDIAG_READ_WRITE_CMDID); - /************************** TLV definitions of WMI events *******************************/ @@ -6720,7 +5787,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID); /* SERVICE_READY_EXT2 event */ #define WMITLV_TABLE_WMI_SERVICE_READY_EXT2_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_service_ready_ext2_event_fixed_param, wmi_service_ready_ext2_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_service_ready_ext2_event_fixed_param, wmi_service_ready_ext2_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_DMA_RING_CAPABILITIES, dma_ring_caps, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_spectral_bin_scaling_params, wmi_bin_scaling_params, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_MAC_PHY_CAPABILITIES_EXT, mac_phy_caps, WMITLV_SIZE_VAR) \ @@ -6741,10 +5808,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_POWER_BOOST_CAPABILITIES, power_boost_capabilities, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES, rssi_accuracy_improvement_capabilities, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_ltf_length_capabilities, wr_ltf_caps, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_chain_capabilities, wr_chain_caps, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_MAC_PHY_CAPABILITIES_EXT2, mac_phy_caps2, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_shared_mem_model_tbtt_count_down_config, shared_mem_model_tbtt_count_down_config, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_peer_meas_capabilities, rtt_peer_meas_caps, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_chain_capabilities, wr_chain_caps, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID); #define WMITLV_TABLE_WMI_SPECTRAL_CAPABILITIES_EVENTID(id,op,buf,len) \ @@ -6928,30 +5992,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_QOS_NULL_FRAME_TX_COMPLETION_EVENTID); /* VDEV Start response Event */ #define WMITLV_TABLE_WMI_VDEV_START_RESP_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_start_response_event_fixed_param, wmi_vdev_start_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -/* NOTE: - * Any new TLV addition in WMI_VDEV_START_RESP_EVENTID needs to be included - * as TLV in WMI_VDEV_UNIFIED_CONNECT_EVENTID as well to maintain compatibility. - * - * WMI_VDEV_UNIFIED_CONNECT_EVENTID substitutes for 3 connection related - * events: - * WMI_PEER_CREATE_CONF_EVENTID, - * WMI_VDEV_START_RESP_EVENTID, - * WMI_PEER_ASSOC_CONF_EVENTID - */ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_START_RESP_EVENTID); /* VDEV Stopped Event */ #define WMITLV_TABLE_WMI_VDEV_STOPPED_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stopped_event_fixed_param, wmi_vdev_stopped_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -/* NOTE: - * Any new TLV addition in WMI_VDEV_STOPPED_EVENTID needs to be included as - * TLV in WMI_VDEV_UNIFIED_DISCONNECT_EVENTID as well to maintain compatibility. - * - * WMI_VDEV_UNIFIED_DISCONNECT_EVENTID substitutes for 2 disconnection related - * events: - * WMI_PEER_DELETE_RESP_EVENTID, - * WMI_VDEV_STOPPED_EVENTID - */ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STOPPED_EVENTID); /* VDEV delete response Event */ @@ -6962,17 +6007,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DELETE_RESP_EVENTID); /* VDEV Install Key Complete Event */ #define WMITLV_TABLE_WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_complete_event_fixed_param, wmi_vdev_install_key_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -/* NOTE: - * To maintain compatibility, any new TLV added in - * WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID needs to also be included as a TLV in - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID. - * - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID substitutes for - * 3 connection related events: - * WMI_PEER_CREATE_CONF_EVENTID, - * WMI_PEER_ASSOC_CONF_EVENTID, - * WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID - */ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID); /* VDEV disconnect Event */ @@ -7058,10 +6092,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_AGGR_STATE_TRIG_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, deauth_disassoc_frame, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_hw_mode_transition_event_fixed_param, hw_mode_transition_fixed_param, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_hw_mode_response_vdev_mac_entry, wmi_pdev_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_bss_info_param, bss_info_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_partner_link_param, partner_link_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_request_tlv_param, vdev_repurpose_request_tlv, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, smd_transition_ie, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_bss_info_param, bss_info_param, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_EVENTID); /* Roam Synch Event */ @@ -7080,9 +6111,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_pmk_cache_synch_tlv_param, roam_pmk_cache_synch_info, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_ml_setup_links_param, setup_links_param, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_ml_key_material_param, ml_key_material, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_band_to_mac, mac_freq_mapping, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_repurpose_request_tlv_param, vdev_repurpose_request_tlv, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, kde_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_band_to_mac, mac_freq_mapping, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SYNCH_EVENTID); /* Roam Synch key Event */ @@ -7336,9 +6365,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_HOST_SWFDA_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pmf_bcn_protect_stats, pmf_bcn_protect_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_extd_stats, vdev_extd_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_extd_stats, pdev_extd_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_telemetry_stats, pdev_telemetry_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_recv_bcn_stats, recv_bcn_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_coex_stats, coex_stats, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_telemetry_stats, pdev_telemetry_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_UPDATE_STATS_EVENTID); /* Update PN response Event */ @@ -7381,9 +6408,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_link_stats, iface_link_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wmm_ac_stats, ac, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_offload_stats, iface_offload_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_powersave_stats, iface_powersave_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_ipi_stats, iface_ipi_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, snr_histogram, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_powersave_stats, iface_powersave_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_IFACE_LINK_STATS_EVENTID); @@ -7592,95 +6617,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NAN_STARTED_CLUSTER_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_joined_cluster_event_fixed_param, wmi_nan_joined_cluster_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_NAN_JOINED_CLUSTER_EVENTID); -/* NAN Enable Response Event */ -#define WMITLV_TABLE_WMI_NAN_ENABLE_RSP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_enable_rsp_event_fixed_param, wmi_nan_enable_rsp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_ENABLE_RSP_EVENTID); - -/** NAN Discovery Service Response Event - * - * TLV (tag length value) parameters follow the - * wmi_nan_disc_service_rsp_event_fixed_param structure. The TLV's are: - * wmi_nan_disc_service_rsp_event_fixed_param fixed_param; - */ -#define WMITLV_TABLE_WMI_NAN_DISC_SERVICE_RSP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_service_rsp_event_fixed_param, wmi_nan_disc_service_rsp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISC_SERVICE_RSP_EVENTID); - -/** NAN Discovery Match Event (NL80211_CMD_NAN_MATCH equivalent) - * - * Unified event covering subscriber match, publisher replied, and follow-up - * received scenarios, discriminated by the type field in fixed_param. - * - * TLV (tag length value) parameters follow the - * wmi_nan_disc_match_event_fixed_param structure. The TLV's are: - * wmi_mac_addr peer_addr[]; - * A_UINT8 service_id[]; - * A_UINT8 serv_spec_info[]; - * A_UINT32 cipher_suites[]; - * A_UINT8 scid[]; - * A_UINT8 extra_info[]; - * A_UINT8 ies[]; - */ -#define WMITLV_TABLE_WMI_NAN_DISC_MATCH_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_match_event_fixed_param, wmi_nan_disc_match_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_addr, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, service_id, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, serv_spec_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, cipher_suites, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, scid, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, extra_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ies, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISC_MATCH_EVENTID); - -/** NAN Discovery Service Request Terminated Event - * - * TLV (tag length value) parameters follow the - * wmi_nan_disc_service_req_terminated_event_fixed_param structure. The TLV's are: - * wmi_nan_disc_service_req_terminated_event_fixed_param fixed_param; - */ -#define WMITLV_TABLE_WMI_NAN_DISC_SERVICE_REQ_TERMINATED_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_service_req_terminated_event_fixed_param, wmi_nan_disc_service_req_terminated_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISC_SERVICE_REQ_TERMINATED_EVENTID); - -/* NAN Next DW Info Event */ -#define WMITLV_TABLE_WMI_NAN_NEXT_DW_INFO_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_next_dw_info_fixed_param, wmi_nan_next_dw_info_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_NEXT_DW_INFO_EVENTID); - -/* NAN Disable Confirm Event */ -#define WMITLV_TABLE_WMI_NAN_DISABLE_CNF_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disable_cnf_fixed_param, wmi_nan_disable_cnf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISABLE_CNF_EVENTID); - -/* NAN Disable Indication Event */ -#define WMITLV_TABLE_WMI_NAN_DISABLE_IND_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disable_ind_fixed_param, wmi_nan_disable_ind_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DISABLE_IND_EVENTID); - -/* NAN Local Schedule Confirm Event */ -#define WMITLV_TABLE_WMI_NAN_LOCAL_SCHEDULE_CNF_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_local_schedule_cnf_event_fixed_param, wmi_nan_local_schedule_cnf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_LOCAL_SCHEDULE_CNF_EVENTID); - -/* NAN Peer Schedule Confirm Event */ -#define WMITLV_TABLE_WMI_NAN_PEER_SCHEDULE_CNF_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cnf_event_fixed_param, wmi_nan_peer_schedule_cnf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_PEER_SCHEDULE_CNF_EVENTID); - -/* NAN Peer Params Confirm Event */ -#define WMITLV_TABLE_WMI_NAN_PEER_PARAMS_CNF_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_peer_params_cnf_event_fixed_param, wmi_nan_peer_params_cnf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_PEER_PARAMS_CNF_EVENTID); - -/* NDP Channel Info Event */ -#define WMITLV_TABLE_WMI_NDP_CHANNEL_INFO_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_channel_info_event_fixed_param, wmi_ndp_channel_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, channel_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, nss_list, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ndp_channel_info, channel_info, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_NDP_CHANNEL_INFO_EVENTID); - /* Coex report antenna isolation event */ #define WMITLV_TABLE_WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_report_isolation_event_fixed_param, wmi_coex_report_isolation_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -7823,15 +6759,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATE_EVENTID); /* peer delete response Event */ #define WMITLV_TABLE_WMI_PEER_DELETE_RESP_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_resp_event_fixed_param, wmi_peer_delete_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -/* NOTE: - * Any new TLV addition in WMI_PEER_DELETE_RESP_EVENTID needs to be included as - * TLV in WMI_VDEV_UNIFIED_DISCONNECT_EVENTID as well to maintain compatibility. - * - * WMI_VDEV_UNIFIED_DISCONNECT_EVENTID substitutes for 2 disconnection related - * events: - * WMI_PEER_DELETE_RESP_EVENTID, - * WMI_VDEV_STOPPED_EVENTID - */ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_DELETE_RESP_EVENTID); /* delete all peer response Event */ @@ -7842,43 +6769,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DELETE_ALL_PEER_RESP_EVENTID); /* peer assoc conf Event */ #define WMITLV_TABLE_WMI_PEER_ASSOC_CONF_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param, wmi_peer_assoc_conf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -/* NOTE: - * To maintain compatibility, any new TLV added in WMI_PEER_ASSOC_CONF_EVENTID - * needs to also be included as a TLV in WMI_VDEV_UNIFIED_CONNECT_EVENTID and - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID. - * - * WMI_VDEV_UNIFIED_CONNECT_EVENTID substitutes for 3 connection related - * events: - * WMI_PEER_CREATE_CONF_EVENTID, - * WMI_VDEV_START_RESP_EVENTID, - * WMI_PEER_ASSOC_CONF_EVENTID - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID substitutes for - * 3 connection related events: - * WMI_PEER_CREATE_CONF_EVENTID, - * WMI_PEER_ASSOC_CONF_EVENTID, - * WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID - */ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CONF_EVENTID); /* peer create conf Event */ #define WMITLV_TABLE_WMI_PEER_CREATE_CONF_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_conf_event_fixed_param, wmi_peer_create_conf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -/* NOTE: - * To maintain compatibility, any new TLV added in WMI_PEER_CREATE_CONF_EVENTID - * needs to also be included as a TLV in WMI_VDEV_UNIFIED_CONNECT_EVENTID and - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID. - * - * WMI_VDEV_UNIFIED_CONNECT_EVENTID substitutes for 3 connection related - * events: - * WMI_PEER_CREATE_CONF_EVENTID, - * WMI_VDEV_START_RESP_EVENTID, - * WMI_PEER_ASSOC_CONF_EVENTID - * WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID substitutes for - * 3 connection related events: - * WMI_PEER_CREATE_CONF_EVENTID, - * WMI_PEER_ASSOC_CONF_EVENTID, - * WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID - */ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CREATE_CONF_EVENTID); /* D0-WOW Disable Ack event */ @@ -7906,11 +6801,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MDNS_STATS_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_resume_event_fixed_param, wmi_pdev_resume_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_RESUME_EVENTID); -/* pdev suspend event */ -#define WMITLV_TABLE_WMI_PDEV_SUSPEND_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_suspend_event_fixed_param, wmi_pdev_suspend_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SUSPEND_EVENTID); - /* SAP Authentication offload event */ #define WMITLV_TABLE_WMI_SAP_OFL_ADD_STA_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sap_ofl_add_sta_event_fixed_param, wmi_sap_ofl_add_sta_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ @@ -8064,9 +6954,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REG_CHAN_LIST_CC_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_regulatory_chan_priority_struct, reg_chan_priority, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_regulatory_fcc_rule_struct, reg_fcc_rule, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_reg_chan_list_cc_ext_additional_params, reg_more_data, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_regulatory_rule_meta_data, reg_meta_data, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_hw_blacklist_chan_fixed_param, hw_blacklist_chan_fixed_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_hw_blacklist_chan_data, hw_blacklist_chan_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_regulatory_rule_meta_data, reg_meta_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_REG_CHAN_LIST_CC_EXT_EVENTID); /* WMI AFC info event */ @@ -8076,17 +6964,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REG_CHAN_LIST_CC_EXT_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_afc_power_event_param, wmi_afc_power_event_param, afc_power_event_param, WMITLV_SIZE_FIX)\ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_6g_afc_frequency_info, freq_info_array, WMITLV_SIZE_VAR)\ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_6g_afc_channel_info, channel_info_array, WMITLV_SIZE_VAR)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_afc_chan_eirp_power_info, chan_eirp_power_info_array, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_hw_blacklist_chan_fixed_param, hw_blacklist_chan_fixed_param, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_hw_blacklist_chan_data, hw_blacklist_chan_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_afc_chan_eirp_power_info, chan_eirp_power_info_array, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_AFC_EVENTID); -/* HW blacklist channels for the current country code */ -#define WMITLV_TABLE_WMI_HW_BLACKLIST_CHAN_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hw_blacklist_chan_fixed_param, wmi_hw_blacklist_chan_fixed_param, hw_blacklist_chan_fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_hw_blacklist_chan_data, hw_blacklist_chan_data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_HW_BLACKLIST_CHAN_EVENTID); - /* Indicate LPI AP detect or not to Host */ #define WMITLV_TABLE_WMI_C2C_DETECT_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_c2c_detect_event_fixed_param, wmi_c2c_detect_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -8121,13 +7001,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, debug_registers, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_CHIP_POWER_STATS_EVENTID); -/* WMI event to provide pdev power stats */ -#define WMITLV_TABLE_WMI_PDEV_POWER_DATAPATH_STATS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_event_fixed_param, wmi_pdev_power_datapath_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_power_stats_info, power_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_tx_rate_info, tx_rate_stats, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_POWER_DATAPATH_STATS_EVENTID); - #define WMITLV_TABLE_WMI_VDEV_BCN_RECEPTION_STATS_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_bcn_recv_stats_event_fixed_param, wmi_vdev_bcn_recv_stats_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_BCN_RECEPTION_STATS_EVENTID); @@ -8166,10 +7039,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_ANI_OFDM_LEVEL_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tpc, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_TPC_EVENTID); -#define WMITLV_TABLE_WMI_VDEV_TPC_IE_POWER_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_tpc_ie_power_event_fixed_param, wmi_vdev_tpc_ie_power_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_TPC_IE_POWER_EVENTID); - #define WMITLV_TABLE_WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_nfcal_power_all_channels_event_fixed_param, wmi_pdev_nfcal_power_all_channels_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_nfcal_power_all_channels_nfdBr, nfdbr, WMITLV_SIZE_VAR) \ @@ -8388,13 +7257,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_vdev_bcn_tx_stats_struct, ctrl_path_vdev_bcn_tx_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_pdev_bcn_tx_stats_struct, ctrl_path_pdev_bcn_tx_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_pdev_conn_stats_struct, ctrl_path_pdev_conn_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_ml_rcfg_stats_struct, ctrl_path_ml_rcfg_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_sta_dar_stats_struct, ctrl_path_sta_dar_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_beacon_stats, vdev_beacon_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_congestion_stats, vdev_congestion_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_data_stats, vdev_data_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_em_pcie_stats, ctrl_path_em_pcie_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_em_dcvs_stats, ctrl_path_em_dcvs_stats, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_ml_rcfg_stats_struct, ctrl_path_ml_rcfg_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID); /* @@ -8419,12 +7282,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_HALPHY_CTRL_PATH_STATS_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_radio_chan_stats, radio_chan_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_RADIO_CHAN_STATS_EVENTID); -#define WMITLV_TABLE_WMI_TDLS_STATS_EVENTID(id, op, buf, len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdls_stats_event_fixed_param, wmi_tdls_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tdls_connect_info_stats, tdls_connect_info_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tdls_data_stats, tdls_data_stats, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_TDLS_STATS_EVENTID); - #define WMITLV_TABLE_WMI_PKGID_EVENTID(id, op, buf, len) \ WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_pkgid_event_fixed_param, wmi_pkgid_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PKGID_EVENTID); @@ -8672,11 +7529,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SSCAN_FW_PARAM_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sscan_evt_message_fixed_param, wmi_sscan_evt_message_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_SSCAN_EVT_MESSAGE_EVENTID); -/* Send scan related stats to host */ -#define WMITLV_TABLE_WMI_GET_SCAN_STATS_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_scan_stats_resp_fixed_param, wmi_get_scan_stats_resp_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_GET_SCAN_STATS_RESP_EVENTID); - /* Roam capability report event */ #define WMITLV_TABLE_WMI_ROAM_CAPABILITY_REPORT_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_capability_report_event_fixed_param, wmi_roam_capability_report_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -8694,12 +7546,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_CAPABILITY_REPORT_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_INT8, ctl_buf, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_TPC_STATS_EVENTID); -/* Send concurrency info to host */ -#define WMITLV_TABLE_WMI_SOC_GET_CONC_INFO_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_soc_get_conc_info_resp_fixed_param, wmi_soc_get_conc_info_resp_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_conc_info, conc_info, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_SOC_GET_CONC_INFO_RESP_EVENTID); - /* Send Bcn Latency ie related params to host */ #define WMITLV_TABLE_WMI_VDEV_BCN_LATENCY_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_bcn_latency_fixed_param, wmi_vdev_bcn_latency_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -8929,8 +7775,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PEER_EVENTID); #define WMITLV_TABLE_WMI_VDEV_VBSS_CONFIG_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vbss_config_event_fixed_param, wmi_vdev_vbss_config_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)\ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_pn_info, vbss_peer_pn_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_sn_info, vbss_peer_sn_info, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_dyn_info, vbss_peer_dyn_info, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_sn_info, vbss_peer_sn_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_VBSS_CONFIG_EVENTID); /* link switch event */ @@ -9017,157 +7862,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_POWER_BOOST_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_scan_cache_info, scan_cache_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_CACHE_RESULT_EVENTID); -#define WMITLV_TABLE_WMI_MODIFY_TX_PLIM_EVENTID(id, op , buf, len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_modify_tx_plim_event_fixed_param, wmi_modify_tx_plim_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_MODIFY_TX_PLIM_EVENTID); - -#define WMITLV_TABLE_WMI_AVG_TX_POWER_EVENTID(id, op , buf, len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_avg_tx_power_event_fixed_param, wmi_avg_tx_power_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_avg_tx_power_region_per_antenna_chain, avg_tx_power_region_per_antenna_chain, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_AVG_TX_POWER_EVENTID); - -#define WMITLV_TABLE_WMI_PLIMIT_TABLE_EVENTID(id, op , buf, len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_plimit_table_event_fixed_param, wmi_plimit_table_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tx_power_per_antenna_chain, tx_power_per_antenna_chain, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PLIMIT_TABLE_EVENTID); - -/* pdev per-vdev queue depth report event */ -#define WMITLV_TABLE_WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param, wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_ac_info, vdev_ac_info, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID); - -/* WMI Anomaly Report Event */ -#define WMITLV_TABLE_WMI_ANOMALY_REPORT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, \ - WMITLV_TAG_STRUC_wmi_anomaly_report_hdr, \ - wmi_anomaly_report_hdr, hdr, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, \ - WMITLV_TAG_ARRAY_STRUC, \ - wmi_anomaly_entry_t, entries, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_ANOMALY_REPORT_EVENTID); - -#define WMITLV_TABLE_WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_tx_chainmask_comp_event_fixed_param, wmi_pdev_set_tx_chainmask_comp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID); - -/* WMI Event to indicate Firmware is ready for mode configuration by host */ -#define WMITLV_TABLE_WMI_FW_READY_IND_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_fw_ready_ind_event_fixed_param, wmi_fw_ready_ind_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_FW_READY_IND_EVENTID); - -/* WMI Event to acknowledge the driver mode sent by host */ -#define WMITLV_TABLE_WMI_WLAN_MODE_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlan_mode_resp_event_fixed_param, wmi_wlan_mode_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_WLAN_MODE_RESP_EVENTID); - -/* CFR capture filter response event */ -#define WMITLV_TABLE_WMI_CFR_CAPTURE_FILTER_RESP_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_cfr_capture_filter_resp_event_fixed_param, wmi_cfr_capture_filter_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cfr_capture_fix_agc_gain_info, fix_agc_gain_info, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_CFR_CAPTURE_FILTER_RESP_EVENTID); - - -/* WMI command for unified connect event */ -#define WMITLV_TABLE_WMI_VDEV_UNIFIED_CONNECT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_unified_connect_event_fixed_param, wmi_vdev_unified_connect_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_conf_event_fixed_param, wmi_peer_create_conf_event_fixed_param, peer_create_fixed_param, WMITLV_SIZE_FIX) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_start_response_event_fixed_param, wmi_vdev_start_response_event_fixed_param, vdev_start_fixed_param, WMITLV_SIZE_FIX) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param, wmi_peer_assoc_conf_event_fixed_param, peer_assoc_fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_CONNECT_EVENTID); - -/* WMI command for unified disconnect event */ -#define WMITLV_TABLE_WMI_VDEV_UNIFIED_DISCONNECT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_event_fixed_param, wmi_vdev_unified_disconnect_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_resp_event_fixed_param, wmi_peer_delete_resp_event_fixed_param, peer_delete_fixed_param, WMITLV_SIZE_FIX) \ - \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_stopped_event_fixed_param, wmi_vdev_stopped_event_fixed_param, vdev_stop_fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UNIFIED_DISCONNECT_EVENTID); - -/* get IPA ring stats event */ -#define WMITLV_TABLE_WMI_IPA_RING_STATS_CONF_EVENTID(id,op,buf,len) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ipa_ring_stats_conf_event_fixed_param, wmi_ipa_ring_stats_conf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ipa_ring_stat_entry, ipa_ring_stat_entry, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_IPA_RING_STATS_CONF_EVENTID); - -#define WMITLV_TABLE_WMI_PDEV_UHR_CU_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_event_fixed_param, wmi_pdev_uhr_cu_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_uhr_cu_status, cu_status, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_UHR_CU_EVENTID); - -/* WMI unified SMD PEER SETUP event */ -#define WMITLV_TABLE_WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_complete_event_fixed_param, wmi_smd_roam_peer_unified_setup_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - /*---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_conf_event_fixed_param, wmi_peer_create_conf_event_fixed_param, peer_create_conf_fixed_param, WMITLV_SIZE_FIX) \ - /*---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param, wmi_peer_assoc_conf_event_fixed_param, peer_assoc_conf_fixed_param, WMITLV_SIZE_FIX)\ - /*---*/ \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_install_key_complete_event_fixed_param, wmi_vdev_install_key_complete_event_fixed_param, vdev_install_key_complete_fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID); - -/* WMI unified SMD Config event */ -#define WMITLV_TABLE_WMI_SMD_ROAM_CONFIG_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_smd_roam_config_event_fixed_param, wmi_smd_roam_config_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_SMD_ROAM_CONFIG_EVENTID); - -/* WMI Command for Energy management OEM cmd data */ -#define WMITLV_TABLE_WMI_ENERGY_MGMT_OEM_DATA_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_energy_mgmt_oem_data_event_fixed_param, wmi_energy_mgmt_oem_data_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_ENERGY_MGMT_OEM_DATA_EVENTID); - -/* VDEV current operating params event */ -#define WMITLV_TABLE_WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_current_operating_param_event_fixed_param, wmi_vdev_current_operating_param_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID); - -/* WMI Event to provide CoEx Policy Stats data */ -#define WMITLV_TABLE_WMI_COEX_GET_POLICY_STATS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_policy_stats_event_fixed_param, wmi_coex_policy_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_COEX_GET_POLICY_STATS_EVENTID); - -/* WMI unified set CUMAC chip ID confirmation event */ -#define WMITLV_TABLE_WMI_PDEV_SET_CUMAC_CHIP_ID_CONFIRMATION_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param, wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_CUMAC_CHIP_ID_CONFIRMATION_EVENTID); - -/* NAN DFS Channel Availability Indication Event */ -#define WMITLV_TABLE_WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_dfs_channel_availability_ind_event_fixed_param, wmi_nan_dfs_channel_availability_ind_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) -WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID); - -/* Chipset debug log stats event */ -#define WMITLV_TABLE_WMI_GET_CHIPSET_LOGGING_STATS_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_event_fixed_param, wmi_get_chipset_logging_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_GET_CHIPSET_LOGGING_STATS_EVENTID); - -/* RTT Peer measurement report event */ -#define WMITLV_TABLE_WMI_RTT_PEER_MEAS_REPORT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_peer_meas_report_event_fixed_param, wmi_rtt_peer_meas_report_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_peer_meas_report_peer_meas_result_info, peer_meas_result_info, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PEER_MEAS_REPORT_EVENTID); - -#define WMITLV_TABLE_WMI_VDEV_CHAN_HOP_STATUS_REPORT_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_chan_hop_status_report_event_fixed_param, wmi_vdev_chan_hop_status_report_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_chan_hop_slot_status, slot_status, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CHAN_HOP_STATUS_REPORT_EVENTID); - -/* Athdiag read/write event: fixed_param + optional read data TLV */ -#define WMITLV_TABLE_WMI_ATHDIAG_READ_WRITE_EVENTID(id, op, buf, len) \ - WMITLV_ELEM(id, op, buf, len, \ - WMITLV_TAG_STRUC_wmi_athdiag_read_write_event_fixed_param, \ - wmi_athdiag_read_write_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id, op, buf, len, \ - WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) -WMITLV_CREATE_PARAM_STRUC(WMI_ATHDIAG_READ_WRITE_EVENTID); - #ifdef __cplusplus } diff --git a/drivers/staging/fw-api/fw/wmi_unified.h b/drivers/staging/fw-api/fw/wmi_unified.h index 9c221dab3851..70eaf1826cf7 100644 --- a/drivers/staging/fw-api/fw/wmi_unified.h +++ b/drivers/staging/fw-api/fw/wmi_unified.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2010-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2026 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -115,8 +115,6 @@ extern "C" { } #endif -#define WMI_MAX_NUM_EXT_TLVS 50 - #define ATH_MAC_LEN 6 /**< length of MAC in bytes */ #define WMI_EVENT_STATUS_SUCCESS 0 /* Success return status to host */ #define WMI_EVENT_STATUS_FAILURE 1 /* Failure return status to host */ @@ -371,11 +369,7 @@ typedef enum { WMI_GRP_QUIET_OFL, /* 0x4a Quiet offloads */ WMI_GRP_ODD, /* 0x4b ODD */ WMI_GRP_TDMA, /* 0x4c TDMA */ - WMI_GRP_MANUAL_UL_TRIG, /* 0x4d Manual UL OFDMA Trigger */ - WMI_GRP_ENERGY_MGMT, /* 0x4e energy management */ - WMI_GRP_SMD, /* 0x4f SMD Roaming */ - WMI_GRP_CHIPSET_LOG, /* 0x50 Chipset Debug Logging */ - WMI_GRP_MAPC, /* 0x51 MAPC for co-ordinated features */ + WMI_GRP_MANUAL_UL_TRIG /* 0x4d Manual UL OFDMA Trigger */ } WMI_GRP_ID; #define WMI_CMD_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1) @@ -388,9 +382,6 @@ typedef enum { /** initialize the wlan sub system */ WMI_INIT_CMDID = 0x1, - /** WMI command to specify the driver's mode of operation */ - WMI_WLAN_MODE_REQ_CMDID, - /* Scan specific commands */ /** start scan request to FW */ @@ -412,10 +403,6 @@ typedef enum { WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID, /** Only applicable to DBS capable product */ WMI_SET_SCAN_DBS_DUTY_CYCLE_CMDID, - /** enable/disable any scan request **/ - WMI_SCAN_SUPPRESS_CMDID, - /** get scan stats**/ - WMI_GET_SCAN_STATS_CMDID, /* PDEV(physical device) specific commands */ /** set regulatorty ctl id used by FW to determine the exact ctl power limits */ @@ -608,32 +595,7 @@ typedef enum { * for Power Boost feature */ WMI_PDEV_POWER_BOOST_MEM_ADDR_CMDID, - /** - * This command is deprecated - DO NOT USE - * WMI cmd to to Enable/Disable NPCA and its capabilities - */ - WMI_PDEV_NPCA_AP_CAP_CMDID, - /** - * WMI cmd to get the per-vdev, per-access-category queue pending packets - * for the pdev - */ - WMI_PDEV_MULTI_VDEV_GET_AC_QUEUE_DEPTH_CMDID, - /* WMI_PDEV_RESERVED_CMDID: - * The value is now deprecated / reserved - it was initially erroneously - * given to WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID, but now that - * WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID has been moved to the EVENTID - * enum, this value is available to use for a future PDEV CMDID. - */ - WMI_PDEV_RESERVED_CMDID, - /** - * WMI cmd to send the detailed information of each UHR feature, - * that are applicable for critical update. - */ - WMI_PDEV_UHR_CU_CMDID, - /** WMI cmd used to enable/disable and get power and data path stats */ - WMI_PDEV_POWER_DATAPATH_STATS_CMDID, - /** WMI cmd to get the CUMAC chip ID */ - WMI_PDEV_SET_CUMAC_CHIP_CMDID, + /* VDEV (virtual device) specific commands */ /** vdev create */ @@ -761,31 +723,6 @@ typedef enum { WMI_VDEV_VBSS_CONFIG_CMDID, - WMI_VDEV_GET_TPC_IE_POWER_CMDID, - - /** data traffic monitoring */ - WMI_VDEV_TRAFFIC_MONITORING_CMDID, - - /** WMI cmd used to control DPS Assisting AP role config */ - WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID, - - /** WMI cmd for unified connect */ - WMI_VDEV_UNIFIED_CONNECT_CMDID, - - /** WMI cmd for unified disconnect */ - WMI_VDEV_UNIFIED_DISCONNECT_CMDID, - - /** WMI cmd for response of wmi_vdev_repurpose_request_tlv_param */ - WMI_VDEV_REPURPOSE_RESP_CMDID, - - /** WMI cmd for UHR critical update */ - WMI_VDEV_UHR_CU_CMDID, - - /** WMI cmd for Channel Hopping Schedule */ - WMI_VDEV_CHANNEL_HOPPING_SCHEDULE_CMDID, - - /** WMI cmd to request channel hopping per-slot status report */ - WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID, /* peer specific commands */ @@ -914,20 +851,7 @@ typedef enum { /* WMI command to setup reorder queue for multiple TIDs */ WMI_PEER_MULTIPLE_REORDER_QUEUE_SETUP_CMDID, - /** Customize MCS range for specific tid */ - WMI_PEER_TID_RATE_CUSTOM_CMDID, - - /** Peer UHR Mode Update Command **/ - WMI_PEER_UHR_MODE_UPDATE_CMDID, - - /* WMI_PEER_ASSOC_V2_CMDID: extended alternative for WMI_PEER_ASSOC_CMDID */ - WMI_PEER_ASSOC_V2_CMDID, - - /* WMI_PEER_UHR_OMP_CMDID for UHR OMP frame*/ - WMI_PEER_UHR_OMP_CMDID, - - - /*--- beacon/management specific commands ---*/ + /* beacon/management specific commands */ /** transmit beacon by reference . used for transmitting beacon on low latency interface like pcie */ WMI_BCN_TX_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MGMT), @@ -1070,10 +994,6 @@ typedef enum { WMI_ROAM_ENABLE_VENDOR_CONTROL_CMDID, /** Get firmware ini value */ WMI_ROAM_GET_VENDOR_CONTROL_PARAM_CMDID, - /** configure SMD parameters for roaming */ - WMI_ROAM_SMD_CONFIG_CMDID, - /** SMD preparation completion status command */ - WMI_ROAM_SMD_START_STATUS_CMDID, /** offload scan specific commands */ /** set offload scan AP profile */ @@ -1215,10 +1135,6 @@ typedef enum { WMI_RTT_PASN_AUTH_STATUS_CMD, /** RTT 11az PASN deauthentication cmd */ WMI_RTT_PASN_DEAUTH_CMD, - /** request to start peer measurement */ - WMI_RTT_PEER_MEAS_REQ_CMDID, - /** request to cancel an ongoing peer measurement */ - WMI_RTT_PEER_MEAS_CANCEL_CMDID, /** spectral scan command */ /** configure spectral scan */ @@ -1277,8 +1193,6 @@ typedef enum { /** request for HALPHY stats through ctrl path */ WMI_REQUEST_HALPHY_CTRL_PATH_STATS_CMDID, - /** request for TDLS connect info and TDLS data stats */ - WMI_REQUEST_TDLS_STATS_CMDID, /** ARP OFFLOAD REQUEST*/ WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_ARP_NS_OFL), @@ -1441,15 +1355,6 @@ typedef enum { /** WMI command to get scan cached result */ WMI_GET_SCAN_CACHE_RESULT_CMDID, - WMI_SET_MODIFY_TX_PLIM_CMDID, - - WMI_GET_AVG_TX_POWER_CMDID, - - WMI_GET_TX_POWER_CALLING_CMDID, - - /** WMI command for athdiag memory/register read or write */ - WMI_ATHDIAG_READ_WRITE_CMDID, - /* Offload 11k related requests */ WMI_11K_OFFLOAD_REPORT_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_11K_OFFLOAD), @@ -1566,48 +1471,6 @@ typedef enum { WMI_NAN_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_NAN), /** Command to handle OEM's NAN specific opaque data */ WMI_NAN_OEM_DATA_CMDID, - /** Command to enable NAN mode */ - WMI_NAN_ENABLE_CMDID, - /** Command to update NAN configuration */ - WMI_NAN_CONFIG_CMDID, - /** Command to disable NAN mode */ - WMI_NAN_DISABLE_CMDID, - /** - * Command to indicate our committed local discovery schedule - * (pre NAN datapath/ranging setup etc.) which FW needs to follow. - */ - WMI_NAN_LOCAL_SCHEDULE_CMDID, - /** - * Command to indicate negotiated committed schedule which FW - * has to follow with a given peer. - */ - WMI_NAN_PEER_SCHEDULE_CMDID, - /** - * Command to indicate negotiated rate control parameters with a - * given peer (during NAN datapath/ranging setup or schedule - * negotiation etc.). - */ - WMI_NAN_PEER_PARAMS_CMDID, - /** - * Command to request for NAN service discovery operations i.e. - * Publish, Subscribe, Followup to be handled by FW. - * This command carries the full NAN function parameters equivalent - * to NL80211_CMD_ADD_NAN_FUNCTION / cfg80211_nan_func, including - * service ID, SRF filters, match filters, SDEA control, security - * (cipher suites, ND-PMK), and NAN3 pairing configuration. - */ - WMI_NAN_DISC_SERVICE_REQ_CMDID, - /** - * Command to cancel an active NAN discovery service request - * (Publish or Subscribe). - * Equivalent of NL80211_CMD_DEL_NAN_FUNCTION in the cfg80211 - * offload interface. - * Host identifies the service request by instance_id (offload path) - * or cookie (standard path); FW frees the service request and sends - * WMI_NAN_DISC_SERVICE_REQ_TERMINATED_EVENTID if the service request - * was active. - */ - WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID, /** Modem power state command */ WMI_MODEM_POWER_STATE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_COEX), @@ -1622,7 +1485,6 @@ typedef enum { WMI_TAS_POWER_HISTORY_CMDID, WMI_ESL_EGID_CMDID, WMI_COEX_MULTIPLE_CONFIG_CMDID, - WMI_COEX_GET_POLICY_STATS_CMDID, /** * OBSS scan offload enable/disable commands @@ -1662,8 +1524,6 @@ typedef enum { /** IPA Offload features related commands */ WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_IPA), - /** WMI cmd to get IPA ring stats */ - WMI_IPA_RING_STATS_REQ_CMDID, /** mDNS responder offload commands */ WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MDNS_OFL), @@ -1699,8 +1559,6 @@ typedef enum { * and specifiy packets of interest for classification. */ WMI_SOC_TX_PACKET_CUSTOM_CLASSIFY_CMDID, - /** WMI cmd to get the concurrency info for all vdevs within the target */ - WMI_SOC_GET_CONC_INFO_CMDID, /* packet filter commands */ WMI_PACKET_FILTER_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_PKT_FILTER), @@ -1721,8 +1579,6 @@ typedef enum { WMI_BPF_SET_VDEV_ENABLE_CMDID, WMI_BPF_SET_VDEV_WORK_MEMORY_CMDID, WMI_BPF_GET_VDEV_WORK_MEMORY_CMDID, - WMI_BPF_SET_SUPPORTED_OFFLOAD_BITMAP_CMDID, - WMI_BPF_SET_APF_MODE_CMDID, /** WMI commands related to monitor mode. */ WMI_MNT_FILTER_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MONITOR), @@ -1745,7 +1601,6 @@ typedef enum { WMI_NDP_RESPONDER_REQ_CMDID, WMI_NDP_END_REQ_CMDID, WMI_NDP_CMDID, - WMI_NDP_SET_LATENCY_TPUT_CMDID, /** WMI commands related to HW data filtering **/ WMI_HW_DATA_FILTER_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_HW_DATA_FILTER), @@ -1766,7 +1621,6 @@ typedef enum { WMI_VDEV_SET_TWT_EDCA_PARAMS_CMDID, /* XPAN TWT */ WMI_VDEV_GET_TWT_SESSION_STATS_INFO_CMDID, WMI_TWT_VDEV_CONFIG_CMDID, - WMI_TWT_ADD_CH_USAGE_CMDID, /** WMI commands related to motion detection **/ WMI_MOTION_DET_CONFIG_PARAM_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MOTION_DET), @@ -1848,8 +1702,6 @@ typedef enum { WMI_MLO_LINK_RECONFIG_CMDID, /** WMI cmd to notify fw completion of link reconfig */ WMI_MLO_LINK_RECONFIG_COMPLETE_CMDID, - /** WMI cmd to notify fw completion of negotiated TID to LINK map */ - WMI_MLO_LINK_TTLM_COMPLETE_CMDID, /** WMI commands specific to Service Aware WiFi (SAWF) */ /** configure or reconfigure the parameters for a service class */ @@ -1871,37 +1723,6 @@ typedef enum { /** WMI Command to set Manual MU UL OFDMA trigger parameters */ WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID, - - - /** WMI commands specific to Energy Management **/ - /** WMI cmd used to control PCIe config */ - WMI_ENERGY_MGMT_PCIE_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_ENERGY_MGMT), - /** WMI cmd used to control PCIe LPM */ - WMI_ENERGY_MGMT_PCIE_LPM_CMDID, - /** WMI cmd used to control Clock and Voltage config */ - WMI_ENERGY_MGMT_DCVS_CONFIG_CMDID, - /** WMI cmd used to control AP Dynamic Power Save feature */ - WMI_ENERGY_MGMT_EDPS_CONFIG_CMDID, - /** WMI cmd used to control periodic unavailability operation */ - WMI_ENERGY_MGMT_PUO_CONFIG_CMDID, - /** WMI cmd used to control ECO mode config */ - WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID, - /** Command to Handle Energy Management OEM's opaque data */ - WMI_ENERGY_MGMT_OEM_DATA_CMDID, - - /** WMI cmd used to set the SMD Roam config */ - WMI_SMD_ROAM_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_SMD), - /** - * WMI cmd used to set up the peer on the target AP during Prep Phase - * (Combine PeerCreate,Assoc, Key Install) - */ - WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID, - - /** WMI command for host to request chipset debug log stats from FW */ - WMI_GET_CHIPSET_LOGGING_STATS_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_CHIPSET_LOG), - - /** WMI cmds for MAPC (Multi-AP Coordination) */ - WMI_PEER_SET_MAPC_PARAMS_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MAPC), } WMI_CMD_ID; typedef enum { @@ -1920,23 +1741,6 @@ typedef enum { */ WMI_IFACE_COMBINATION_IND_EVENTID, - /** WMI evt that indicates FW basic initializations are done, and FW - * is ready to receive the WLAN mode specification from the host. - * - * mode selection handshake: - * host <-- WMI_FW_READY_IND_EVENTID <---- target - * host --> WMI_WLAN_MODE_REQ_CMDID -----> target - * host <-- WMI_WLAN_MODE_RESP_EVENTID <-- target - * precedes the WLAN initialization handshake: - * host <-- WMI_SERVICE_READY_EVENTID <--- target - * host --> WMI_INIT_CMDID --------------> target - * host <-- WMI_READY_EVENTID <----------- target - */ - WMI_FW_READY_IND_EVENTID, - /* WMI evt to acknowledge the driver mode specified by host */ - WMI_WLAN_MODE_RESP_EVENTID, - - /** Scan specific events */ WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN), @@ -1949,188 +1753,157 @@ typedef enum { /** Spectral scan capabilities advertisement */ WMI_SPECTRAL_CAPABILITIES_EVENTID, - /** Send scan stats to HOST */ - WMI_GET_SCAN_STATS_RESP_EVENTID, - /* PDEV specific events */ /** TPC config for the current operating channel */ - WMI_PDEV_TPC_CONFIG_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_PDEV), /* 0 */ + WMI_PDEV_TPC_CONFIG_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_PDEV), /** Channel stats event */ - WMI_CHAN_INFO_EVENTID, /* 1 */ + WMI_CHAN_INFO_EVENTID, /** PHY Error specific WMI event */ - WMI_PHYERR_EVENTID, /* 2 */ + WMI_PHYERR_EVENTID, /** eeprom dump event */ - WMI_PDEV_DUMP_EVENTID, /* 3 */ + WMI_PDEV_DUMP_EVENTID, /** traffic pause event */ - WMI_TX_PAUSE_EVENTID, /* 4 */ + WMI_TX_PAUSE_EVENTID, /** DFS radar event */ - WMI_DFS_RADAR_EVENTID, /* 5 */ + WMI_DFS_RADAR_EVENTID, /** track L1SS entry and residency event */ - WMI_PDEV_L1SS_TRACK_EVENTID, /* 6 */ + WMI_PDEV_L1SS_TRACK_EVENTID, /** Report current temperature of the chip in Celcius degree */ - WMI_PDEV_TEMPERATURE_EVENTID, /* 7 */ + WMI_PDEV_TEMPERATURE_EVENTID, /** Extension of WMI_SERVICE_READY msg with extra target capability info */ - WMI_SERVICE_READY_EXT_EVENTID, /* 8 */ + WMI_SERVICE_READY_EXT_EVENTID, /** FIPS test mode event */ - WMI_PDEV_FIPS_EVENTID, /* 9 */ + WMI_PDEV_FIPS_EVENTID, /** Channel hopping avoidance */ - WMI_PDEV_CHANNEL_HOPPING_EVENTID, /* 10 */ + WMI_PDEV_CHANNEL_HOPPING_EVENTID, /** CCK ANI level event */ - WMI_PDEV_ANI_CCK_LEVEL_EVENTID, /* 11 */ + WMI_PDEV_ANI_CCK_LEVEL_EVENTID, /** OFDM ANI level event */ - WMI_PDEV_ANI_OFDM_LEVEL_EVENTID, /* 12 */ + WMI_PDEV_ANI_OFDM_LEVEL_EVENTID, /** Tx PPDU params */ - WMI_PDEV_TPC_EVENTID, /* 13 */ + WMI_PDEV_TPC_EVENTID, /** NF Cal Power in DBR/DBM for all channels */ - WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID, /* 14 */ + WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID, /** SOC/PDEV events */ - WMI_PDEV_SET_HW_MODE_RESP_EVENTID, /* 15 */ - WMI_PDEV_HW_MODE_TRANSITION_EVENTID, /* 16 */ - WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID, /* 17 */ + WMI_PDEV_SET_HW_MODE_RESP_EVENTID, + WMI_PDEV_HW_MODE_TRANSITION_EVENTID, + WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID, /** Report ANT DIV feature's status */ - WMI_PDEV_ANTDIV_STATUS_EVENTID, /* 18 */ + WMI_PDEV_ANTDIV_STATUS_EVENTID, /** Chip level Power stats */ - WMI_PDEV_CHIP_POWER_STATS_EVENTID, /* 19 */ + WMI_PDEV_CHIP_POWER_STATS_EVENTID, /** Power Save Failure Detected */ - WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID, /* 20 */ + WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID, /* Event to report the switch count in csa of one or more VDEVs */ - WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID, /* 21 */ + WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID, /** Report the caldata version to host */ - WMI_PDEV_CHECK_CAL_VERSION_EVENTID, /* 22 */ + WMI_PDEV_CHECK_CAL_VERSION_EVENTID, /** Report chain RSSI and antenna index to host */ - WMI_PDEV_DIV_RSSI_ANTID_EVENTID, /* 23 */ + WMI_PDEV_DIV_RSSI_ANTID_EVENTID, /** provide noise floor and cycle counts for a channel */ - WMI_PDEV_BSS_CHAN_INFO_EVENTID, /* 24 */ + WMI_PDEV_BSS_CHAN_INFO_EVENTID, /** Response received the ctl table to host */ - WMI_PDEV_UPDATE_CTLTABLE_EVENTID, /* 25 */ + WMI_PDEV_UPDATE_CTLTABLE_EVENTID, - WMI_PDEV_DMA_RING_CFG_RSP_EVENTID, /* 26 */ + WMI_PDEV_DMA_RING_CFG_RSP_EVENTID, - WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID, /* 27 */ + WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID, /** WMI Event to deliver CTL Failsafe application */ - WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID, /* 28 */ + WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID, /* Event to report the switch count in BSS color of one or more VDEVs */ - WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID, /* 29 */ + WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID, /* Event to send cold boot calibration data */ - WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID, /* 30 */ + WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID, /* Event to report a rogue ap info that is detected in fw */ - WMI_PDEV_RAP_INFO_EVENTID, /* 31 */ + WMI_PDEV_RAP_INFO_EVENTID, - WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID, /* 32 */ + WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID, /** 2nd extension of SERVICE_READY msg with extra target capability info */ - WMI_SERVICE_READY_EXT2_EVENTID, /* 33 */ + WMI_SERVICE_READY_EXT2_EVENTID, /** * vdev restart response for multiple vdevs in response to * MULTIPLE_VDEV_RESTART_REQUEST */ - WMI_PDEV_MULTIPLE_VDEV_RESTART_RESP_EVENTID, /* 34 */ + WMI_PDEV_MULTIPLE_VDEV_RESTART_RESP_EVENTID, /** WMI event in response to TPC STATS command */ - WMI_PDEV_GET_TPC_STATS_EVENTID, /* 35 */ + WMI_PDEV_GET_TPC_STATS_EVENTID, /* Event to get DPD status from HALPHY */ - WMI_PDEV_GET_DPD_STATUS_EVENTID, /* 36 */ + WMI_PDEV_GET_DPD_STATUS_EVENTID, /* Event to get Calibration status from HALPHY */ - WMI_PDEV_GET_HALPHY_CAL_STATUS_EVENTID, /* 37 */ + WMI_PDEV_GET_HALPHY_CAL_STATUS_EVENTID, /* Event to set halphy cal bitmap */ - WMI_PDEV_SET_HALPHY_CAL_BMAP_EVENTID, /* 38 */ + WMI_PDEV_SET_HALPHY_CAL_BMAP_EVENTID, /* Event to get AOA phasedelta values from HALPHY */ - WMI_PDEV_AOA_PHASEDELTA_EVENTID, /* 39 */ + WMI_PDEV_AOA_PHASEDELTA_EVENTID, - WMI_PDEV_FIPS_EXTEND_EVENTID, /* 40 */ + WMI_PDEV_FIPS_EXTEND_EVENTID, /* Event to send packet log decode information */ - WMI_PDEV_PKTLOG_DECODE_INFO_EVENTID, /* 41 */ + WMI_PDEV_PKTLOG_DECODE_INFO_EVENTID, /** * RSSI dB to dBm conversion params info event * sent to host after channel/bw/chainmask change per pdev. */ - WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID, /* 42 */ + WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID, /* Event to indicate Schedule tid queue suspended info */ - WMI_PDEV_SCHED_TIDQ_SUSP_INFO_EVENTID, /* 43 */ + WMI_PDEV_SCHED_TIDQ_SUSP_INFO_EVENTID, /* Event to send target rate to power table update status */ - WMI_PDEV_SET_TGTR2P_TABLE_EVENTID, /* 44 */ + WMI_PDEV_SET_TGTR2P_TABLE_EVENTID, /* Event to indicate completion on RF path */ - WMI_PDEV_SET_RF_PATH_RESP_EVENTID, /* 45 */ + WMI_PDEV_SET_RF_PATH_RESP_EVENTID, /* Event to get AOA phasedelta values for all gain tables from HALPHY */ - WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID, /* 46 */ + WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID, /* Event to indicate the status of WiFi Radar calibration */ - WMI_PDEV_WIFI_RADAR_CAL_COMPLETION_STATUS_EVENTID, /* 47 */ + WMI_PDEV_WIFI_RADAR_CAL_COMPLETION_STATUS_EVENTID, /* Event to indicate xLNA is enabled */ - WMI_PDEV_ENABLE_XLNA_EVENTID, /* 48 */ + WMI_PDEV_ENABLE_XLNA_EVENTID, /* Event to indicate ANN Power Boost update status from Target */ - WMI_PDEV_POWER_BOOST_EVENTID, /* 49 */ + WMI_PDEV_POWER_BOOST_EVENTID, /* * WMI event to share Wi-Fi Radar - * monostatic Wi-Fi sensing technique capabalites */ - WMI_PDEV_WIFI_RADAR_CAPABILITIES_EVENTID, /* 50 */ - - /* - * This event is deprecated - DO NOT USE - * WMI_PDEV_NPCA_AP_CAP_CMDID response event - */ - WMI_PDEV_NPCA_AP_CAP_RESP_EVENTID, /* 51 */ - - /* Event to share the per-access-category queue pending packets */ - WMI_PDEV_MULTI_VDEV_AC_QUEUE_DEPTH_EVENTID, /* 52 */ - - /* WMI event for the UHR critical Update */ - WMI_PDEV_UHR_CU_EVENTID, /* 53 */ - - /** - * WMI Event to send power and data path stats info to Host - */ - WMI_PDEV_POWER_DATAPATH_STATS_EVENTID, /* 54 */ - - /** Event to indicate CUMAC Chip ID initialization completed to host */ - WMI_PDEV_SET_CUMAC_CHIP_ID_CONFIRMATION_EVENTID, /* 55 */ - - /*** - *** add new WMI_PDEV EVENTID defs directly above here, - *** until EVENTID offset 89 is reached, then continue - *** from 90 below WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID - ***/ - WMI_PDEV_SET_TX_CHAINMASK_COMP_EVENTID = 0x405a, /* 89 */ - + WMI_PDEV_WIFI_RADAR_CAPABILITIES_EVENTID, /* VDEV specific events */ @@ -2212,15 +1985,6 @@ typedef enum { /** Connect response */ WMI_VDEV_OOB_CONNECTION_RESP_EVENTID, WMI_VDEV_VBSS_CONFIG_EVENTID, - WMI_VDEV_TPC_IE_POWER_EVENTID, - /** WMI event for unified connect */ - WMI_VDEV_UNIFIED_CONNECT_EVENTID, - /** WMI event for unified disconnect */ - WMI_VDEV_UNIFIED_DISCONNECT_EVENTID, - /** WMI event for sending vdev operating params */ - WMI_VDEV_CURRENT_OPERATING_PARAM_EVENTID, - /** channel hopping per-slot status report event */ - WMI_VDEV_CHAN_HOP_STATUS_REPORT_EVENTID, /* peer specific events */ /** FW reauet to kick out the station for reasons like inactivity,lack of response ..etc */ @@ -2399,7 +2163,6 @@ typedef enum { /* send pdev resume event to host after pdev resume. */ WMI_PDEV_RESUME_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SUSPEND), - WMI_PDEV_SUSPEND_EVENTID, /** WOW wake up host event.generated in response to WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID. will cary wake reason */ @@ -2419,8 +2182,6 @@ typedef enum { WMI_RTT_PASN_PEER_CREATE_REQ_EVENTID, /** RTT 11az PASN peer delete event */ WMI_RTT_PASN_PEER_DELETE_EVENTID, - /** RTT peer (Proximity Detection) measurement report */ - WMI_RTT_PEER_MEAS_REPORT_EVENTID, /*STATS specific events*/ /** txrx stats event requested by host */ @@ -2487,12 +2248,6 @@ typedef enum { /** FW IPA link stats Event */ WMI_IPA_LINK_STATS_EVENTID, - /* TDLS Stats event having TDLS connect info and data stats */ - WMI_TDLS_STATS_EVENTID, - - /** WMI Anomaly Report Event — single event ID for all FW anomaly types */ - WMI_ANOMALY_REPORT_EVENTID, - /* NLO specific events */ /** NLO match event after the first match */ @@ -2655,15 +2410,6 @@ typedef enum { /** WMI event for FW diagnostic data sent to host */ WMI_OPT_DP_DIAG_EVENTID, - WMI_MODIFY_TX_PLIM_EVENTID, - - WMI_AVG_TX_POWER_EVENTID, - - WMI_PLIMIT_TABLE_EVENTID, - - /** WMI event to deliver athdiag read data or write completion status */ - WMI_ATHDIAG_READ_WRITE_EVENTID, - /* GPIO Event */ WMI_GPIO_INPUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GPIO), @@ -2718,47 +2464,6 @@ typedef enum { WMI_NAN_DMESG_EVENTID, /** Event to deliver OEM's NAN specific opaque data */ WMI_NAN_OEM_DATA_EVENTID, - /** Event response to NAN enable command */ - WMI_NAN_ENABLE_RSP_EVENTID, - /** Event indicating information about next Discovery Window (DW) */ - WMI_NAN_NEXT_DW_INFO_EVENTID, - /** Event confirmation to NAN disable command */ - WMI_NAN_DISABLE_CNF_EVENTID, - /** Event notifying FW triggered NAN disable indication */ - WMI_NAN_DISABLE_IND_EVENTID, - /** Confirmation event to NAN local schedule command */ - WMI_NAN_LOCAL_SCHEDULE_CNF_EVENTID, - /** Confirmation event to NAN peer schedule command */ - WMI_NAN_PEER_SCHEDULE_CNF_EVENTID, - /* Confirmation event that FW has received WMI_NAN_PEER_PARAMS_CMDID */ - WMI_NAN_PEER_PARAMS_CNF_EVENTID, - /* Indicate negotiated committed NDP channels information. */ - WMI_NDP_CHANNEL_INFO_EVENTID, - /* Event to indicate availability of STA AP connection on DFS channel */ - WMI_NAN_DFS_CHANNEL_AVAILABILITY_IND_EVENTID, - /** - * Event response to NAN discovery service request command - * (WMI_NAN_DISC_SERVICE_REQ_CMDID); - * carries the instance_id assigned by FW and a status code indicating - * whether the Publish / Subscribe service request was accepted - */ - WMI_NAN_DISC_SERVICE_RSP_EVENTID, - /** - * NAN discovery match event; covers two match scenarios: - * subscriber found publisher (type=PUBLISH), publisher received subscribe - * (type=SUBSCRIBE). - * Equivalent of NL80211_CMD_NAN_MATCH in the cfg80211 - * offload interface. - */ - WMI_NAN_DISC_MATCH_EVENTID, - /** - * NAN discovery service request terminated event; sent when a Publish or - * Subscribe service request is cancelled by the host, expires (TTL), or is - * terminated by FW due to an error. - * Equivalent of NL80211_CMD_DEL_NAN_FUNCTION (EVENT: terminated) - * in the cfg80211 offload interface. - */ - WMI_NAN_DISC_SERVICE_REQ_TERMINATED_EVENTID, /* Coex Event */ WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_COEX), @@ -2766,17 +2471,11 @@ typedef enum { /** Dedicated BT Antenna Mode (DBAM) complete event */ WMI_COEX_DBAM_COMPLETE_EVENTID, WMI_TAS_POWER_HISTORY_EVENTID, - WMI_COEX_GET_POLICY_STATS_EVENTID, /* LPI Event */ WMI_LPI_RESULT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_LPI), WMI_LPI_STATUS_EVENTID, WMI_LPI_HANDOFF_EVENTID, - /* - * New EVTID added for FW->LOWI intra-LPASS direct scan result delivery - - * replaces QMI path when LOWI-on-FW capability is enabled. - */ - WMI_LPI_SCAN_RESULT_EVENTID_V2, /* ExtScan events */ WMI_EXTSCAN_START_STOP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_EXTSCAN), @@ -2791,9 +2490,6 @@ typedef enum { /* mDNS offload events */ WMI_MDNS_STATS_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MDNS_OFL), - /** WMI Event to send IPA ring stats to host */ - WMI_IPA_RING_STATS_CONF_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_IPA), - /* SAP Authentication offload events */ WMI_SAP_OFL_ADD_STA_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SAP_OFL), WMI_SAP_OFL_DEL_STA_EVENTID, @@ -2813,8 +2509,6 @@ typedef enum { WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SOC), WMI_SOC_HW_MODE_TRANSITION_EVENTID, WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID, - /* Event to share the concurrency info to HOST */ - WMI_SOC_GET_CONC_INFO_RESP_EVENTID, /** Motion Aided WiFi Connectivity (MAWC) events */ WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MAWC), @@ -2835,8 +2529,6 @@ typedef enum { WMI_AFC_EVENTID, WMI_REG_CHAN_LIST_CC_EXT2_EVENTID, /* DEPRECATED */ WMI_C2C_DETECT_EVENTID, - /* WMI event to send the HW channel blacklist during the CTL blob update */ - WMI_HW_BLACKLIST_CHAN_EVENTID, /** Events for TWT(Target Wake Time) of STA and AP */ WMI_TWT_ENABLE_COMPLETE_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_TWT), @@ -2875,9 +2567,6 @@ typedef enum { WMI_AUDIO_AGGR_REPORT_STATISTICS_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_AUDIO), WMI_AUDIO_AGGR_SCHED_METHOD_EVENTID, - /** WMI events related to CFR capture response event */ - WMI_CFR_CAPTURE_FILTER_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_CFR_CAPTURE), - /** Vendor defined WMI events **/ WMI_VENDOR_PDEV_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_VENDOR), WMI_VENDOR_VDEV_EVENTID, @@ -2899,9 +2588,6 @@ typedef enum { WMI_MLO_VDEV_LINK_INFO_EVENTID, /** request host to do T2LM neg to the un-disabled link */ WMI_MLO_LINK_DISABLE_REQUEST_EVENTID, - /* alias */ - WMI_MLO_LINK_TTLM_REQUEST_EVENTID = - WMI_MLO_LINK_DISABLE_REQUEST_EVENTID, /** request host to switch to new link for specified vdev */ WMI_MLO_LINK_SWITCH_REQUEST_EVENTID, /** Response event for WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID */ @@ -2932,19 +2618,6 @@ typedef enum { * WMI Event to send Manual UL OFDMA Trigger frame RX PPDU info to Host */ WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID, - - /* WMI event used during SMD Roaming */ - WMI_SMD_ROAM_CONFIG_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SMD), - /* - * WMI event to indicate the status of the SMD_ROAM_PEER_UNIFIED_SETUP_CMD - * used during SMD Roaming - */ - WMI_SMD_ROAM_PEER_UNIFIED_SETUP_COMPLETE_EVENTID, - - WMI_ENERGY_MGMT_OEM_DATA_EVENTID =WMI_CMD_GRP_START_ID(WMI_GRP_ENERGY_MGMT), - - /** WMI event to send chipset debug log stats to host */ - WMI_GET_CHIPSET_LOGGING_STATS_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_CHIPSET_LOG), } WMI_EVT_ID; /* defines for OEM message sub-types */ @@ -3012,7 +2685,6 @@ typedef enum { #define WMI_CHAN_FLAG_NAN_DISABLED 19 /* Indicates that NAN operations are disabled on this channel */ #define WMI_CHAN_FLAG_STA_DFS 20 /* Indicates if STA should process radar signals */ #define WMI_CHAN_FLAG_ALLOW_EHT 21 /* EHT (11be) is allowed on this channel */ -#define WMI_CHAN_FLAG_ALLOW_UHR 22 /* UHR (11bn) is allowed on this channel */ #define WMI_SET_CHANNEL_FLAG(pwmi_channel,flag) do { \ (pwmi_channel)->info |= ((A_UINT32) 1 << flag); \ @@ -3322,16 +2994,6 @@ typedef struct _wmi_ppe_threshold { #define WMI_MAX_EHTCAP_MAC_SIZE 2 #define WMI_MAX_EHTCAP_PHY_SIZE 3 -/* WMI_MAX_UHRCAP_MAC_SIZE: - * Kept as 4 for backwards compatibility, elements [2] and [3] are reserved. - */ -#define WMI_MAX_UHRCAP_MAC_SIZE 4 -#define WMI_MAX_UHRCAP_PHY_SIZE 8 /* as per spec recommendation */ -/* WMI_MAX_UHRCAP_DBE_SIZE: - * B0-B7 header + up to 24+24 bits EHT-MCS maps - */ -#define WMI_MAX_UHRCAP_DBE_SIZE 2 - /* * 0 – index indicated EHT-MCS map for 20Mhz only sta (4 bytes valid) * 1 – index for <= 80MHz bw (only 3 bytes are valid and other is reserved) @@ -3901,25 +3563,6 @@ typedef struct { #define WMI_TARGET_CAP_MPDU_STATS_PER_TX_NSS_SUPPORT_SET(target_cap_flags, value)\ WMI_SET_BITS(target_cap_flags, 16, 1, value) -#define WMI_TARGET_CAP_MAX_ML_STA_BSS_NUM_GET(target_cap_flags) \ - WMI_GET_BITS(target_cap_flags, 17, 3) -#define WMI_TARGET_CAP_MAX_ML_STA_BSS_NUM_SET(target_cap_flags, value) \ - WMI_SET_BITS(target_cap_flags, 17, 3, value) - -#define WMI_TARGET_CAP_MAX_ML_SAP_BSS_NUM_GET(target_cap_flags) \ - WMI_GET_BITS(target_cap_flags, 20, 3) -#define WMI_TARGET_CAP_MAX_ML_SAP_BSS_NUM_SET(target_cap_flags, value) \ - WMI_SET_BITS(target_cap_flags, 20, 3, value) - -#define WMI_TARGET_CAP_TOTAL_ML_LINKS_NUM_GET(target_cap_flags) \ - WMI_GET_BITS(target_cap_flags, 23, 3) -#define WMI_TARGET_CAP_TOTAL_ML_LINKS_NUM_SET(target_cap_flags, value) \ - WMI_SET_BITS(target_cap_flags, 23, 3, value) - -#define WMI_TARGET_CAP_FLAGS_RX_PEER_METADATA_VERSION_EXTENSION_GET(target_cap_flags) \ - WMI_GET_BITS(target_cap_flags, 26, 3) -#define WMI_TARGET_CAP_FLAGS_RX_PEER_METADATA_VERSION_EXTENSION_SET(target_cap_flags, value) \ - WMI_SET_BITS(target_cap_flags, 26, 3, value) /* * wmi_htt_msdu_idx_to_htt_msdu_qtype GET/SET APIs @@ -4032,92 +3675,6 @@ typedef enum { #define WMI_SUPPORTED_WIFI_8_CERTIFIED_GENERATION_SET(wifi_generations, value) \ WMI_SET_BITS(wifi_generations, 4, 1, value) -/* Begin SAM related capabilities */ -#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_PEER_GET(sam_capability_1) \ - WMI_GET_BITS(sam_capability_1, 0, 12) -#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_PEER_SET(sam_capability_1, value) \ - WMI_SET_BITS(sam_capability_1, 0, 12, value) - -#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_MSDUQ_GET(sam_capability_1) \ - WMI_GET_BITS(sam_capability_1, 12, 13) -#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_MSDUQ_SET(sam_capability_1, value) \ - WMI_SET_BITS(sam_capability_1, 12, 13, value) - -#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_MPDUQ_GET(sam_capability_2) \ - WMI_GET_BITS(sam_capability_2, 0, 12) -#define WMI_CAP_EXT2_SAM_NUM_SUPPORTED_MPDUQ_SET(sam_capability_2, value) \ - WMI_SET_BITS(sam_capability_2, 0, 12, value) -/* End SAM related capabilities */ - - -typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_shared_mem_model_tbtt_count_down_config.*/ - A_UINT32 tlv_header; - /* Indicates what are all the TBTT count down that FW supports */ - union { - struct { - A_UINT32 csa :1, - quiet :1, - max_chan_switch_time :1, - eht_bpcc :1, - ttlm_max_switch_time :1, - ttlm_expected_duration :1, - ml_reconfig :1, - uhr_epbcc :1, - uhr_params_update :1, - rsvd :23; - }; - A_UINT32 config_1; - }; - -} wmi_shared_mem_model_tbtt_count_down_config; - -/* wmi_shared_mem_model_tbtt_count_down_config GET/SET macros */ -#define WMI_TBTT_COUNT_DOWN_CONFIG_CSA_GET(config_1) \ - WMI_GET_BITS(config_1, 0, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_CSA_SET(config_1, value) \ - WMI_SET_BITS(config_1, 0, 1, value) - -#define WMI_TBTT_COUNT_DOWN_CONFIG_QUIET_GET(config_1) \ - WMI_GET_BITS(config_1, 1, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_QUIET_SET(config_1, value) \ - WMI_SET_BITS(config_1, 1, 1, value) - -#define WMI_TBTT_COUNT_DOWN_CONFIG_MAX_CHAN_SWITCH_TIME_GET(config_1) \ - WMI_GET_BITS(config_1, 2, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_MAX_CHAN_SWITCH_TIME_SET(config_1, value) \ - WMI_SET_BITS(config_1, 2, 1, value) - -#define WMI_TBTT_COUNT_DOWN_CONFIG_EHT_BPCC_GET(config_1) \ - WMI_GET_BITS(config_1, 3, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_EHT_BPCC_SET(config_1, value) \ - WMI_SET_BITS(config_1, 3, 1, value) - -#define WMI_TBTT_COUNT_DOWN_CONFIG_TTLM_MAX_SWITCH_TIME_GET(config_1) \ - WMI_GET_BITS(config_1, 4, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_TTLM_MAX_SWITCH_TIME_SET(config_1, value) \ - WMI_SET_BITS(config_1, 4, 1, value) - -#define WMI_TBTT_COUNT_DOWN_CONFIG_TTLM_EXPECTED_DURATION_GET(config_1) \ - WMI_GET_BITS(config_1, 5, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_TTLM_EXPECTED_DURATION_SET(config_1, value) \ - WMI_SET_BITS(config_1, 5, 1, value) - -#define WMI_TBTT_COUNT_DOWN_CONFIG_ML_RECONFIG_GET(config_1) \ - WMI_GET_BITS(config_1, 6, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_ML_RECONFIG_SET(config_1, value) \ - WMI_SET_BITS(config_1, 6, 1, value) - -#define WMI_TBTT_COUNT_DOWN_CONFIG_UHR_EPBCC_GET(config_1) \ - WMI_GET_BITS(config_1, 7, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_UHR_EPBCC_SET(config_1, value) \ - WMI_SET_BITS(config_1, 7, 1, value) - -#define WMI_TBTT_COUNT_DOWN_CONFIG_UHR_PARAMS_UPDATE_GET(config_1) \ - WMI_GET_BITS(config_1, 8, 1) -#define WMI_TBTT_COUNT_DOWN_CONFIG_UHR_PARAMS_UPDATE_SET(config_1, value) \ - WMI_SET_BITS(config_1, 8, 1, value) - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_service_ready_ext2_event_fixed_param.*/ @@ -4205,11 +3762,7 @@ typedef struct { * Bit 14 - Support for ML monitor mode * Bit 15 - Support for Qdata Tx LCE filter installation * Bit 16 - Support for MPDU stats per tx Nss capability - * Bits 19:17 - max number of ML STA BSS supported, range [0-7] - * Bits 22:20 - max number of ML SAP BSS supported, range [0-7] - * Bits 25:23 - total number of ML links supported, range [0-7] - * Bits 28:27 - extended rx peer metadata version capabilities - * Bits 31:29 - Reserved + * Bits 31:17 - Reserved */ A_UINT32 target_cap_flags; @@ -4300,54 +3853,6 @@ typedef struct { */ A_UINT32 supported_wifi_certified_generations; - /* - * max number of CFR filter groups supported by FW. - */ - A_UINT32 max_cfr_filter_groups_supp; - - /* - * The maximum number of supported SAM Peer/MSDUQ/MPDUQ elements. This does - * NOT indicate the support limits for the HW, but rather the FW limit. - * Some FW targets may not support the maximum HW capability. - * - * When the host allocates the associated SAM data structure, it should do - * so with IDs strictly less than the limit indicated below. For example if - * only 64 SAM Peers are supported by a target, then only SAM Peer IDs 0-63 - * should be utilized. - * - * If a target does not support utilizing SAM, all of these SAM - * configuration values will be 0. - */ - union { - struct { - A_UINT32 num_supported_sam_peer : 12; /* bits 0:11 */ - A_UINT32 num_supported_sam_msduq : 13; /* bits 12:24 */ - A_UINT32 sam_reserved_1 : 7; /* bits 25:31 */ - A_UINT32 num_supported_sam_mpduq : 12; /* bits 0:11 */ - A_UINT32 sam_reserved_2 : 20; /* bits 12:31 */ - }; - struct { - A_UINT32 sam_capability_1; - A_UINT32 sam_capability_2; - }; - }; - - /* - * UHR MAC Capabilities: total WMI_MAX_UHRCAP_MAC_SIZE*A_UINT32 bits - * those bits actually are max mac capabilities = cap_mac_2g | cap_mac_5g - * The actual cap mac info per mac (2g/5g) in the TLV -- - * WMI_MAC_PHY_CAPABILITIES_EXT2 - */ - A_UINT32 uhr_cap_mac_info[WMI_MAX_UHRCAP_MAC_SIZE]; - - /* - * UHR DBE Capability Parameters: - * total WMI_MAX_UHRCAP_DBE_SIZE * A_UINT32 bits - * Present only when DBE Support bit (B10) in uhr_cap_mac_info is set. - * Carries DBE Maximum Supported Bandwidth and optional EHT-MCS Maps. - */ - A_UINT32 uhr_cap_dbe_info[WMI_MAX_UHRCAP_DBE_SIZE]; - /* Followed by next TLVs: * WMI_DMA_RING_CAPABILITIES dma_ring_caps[]; * wmi_spectral_bin_scaling_params wmi_bin_scaling_params[]; @@ -4355,18 +3860,10 @@ typedef struct { * WMI_HAL_REG_CAPABILITIES_EXT2 hal_reg_caps[]; * wmi_nan_capabilities nan_cap; * WMI_SCAN_RADIO_CAPABILITIES_EXT2 wmi_scan_radio_caps[]; - * wmi_twt_caps_params twt_caps[]; * wmi_htt_msdu_idx_to_htt_msdu_qtype htt_msdu_idx_to_qtype_map[]; * wmi_dbs_or_sbs_cap_ext dbs_or_sbs_cap_ext; - * wmi_cust_bdf_version_capabilities cust_bdf_version_capabilities[]; - * wmi_sw_cal_ver_cap sw_cal_ver_cap[]; * A_INT32 hw_tx_power_signed[WMI_HW_TX_POWER_CAPS_MAX]; - * WMI_COEX_FIX_CHANNEL_CAPABILITIES coex_fix_channel_caps[]; * wmi_aux_dev_capabilities aux_dev_caps[]; - * wmi_enhanced_aoa_caps_param aoa_caps_param[]; - * wmi_enhanced_aoa_per_band_caps_param - * aoa_per_band_caps_param[]; - * wmi_sar_flag_tlv_param sar_flags[]; * WMI_POWER_BOOST_CAPABILITIES power_boost_capabilities[]; * WMI_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES * rssi_accuracy_improvement_capabilities[]; @@ -4374,10 +3871,6 @@ typedef struct { * wifi_radar_ltf_length_capabilities[]; * wmi_wifi_radar_chain_capabilities * wifi_radar_chain_capabilities[]; - * WMI_MAC_PHY_CAPABILITIES_EXT2 mac_phy_caps2[]; - * wmi_shared_mem_model_tbtt_count_down_config - * wmi_shared_mem_model_tbtt_count_down_config[]; - * wmi_rtt_peer_meas_capabilities rtt_peer_meas_caps[]; */ } wmi_service_ready_ext2_event_fixed_param; @@ -5340,24 +4833,8 @@ typedef struct { * 11 -> reserved * Refer to the below WMI_RSRC_CFG_FLAGS2_OPTIMIZE_POWER_GET/SET * macros. - * Bit 25 - enable recv_bcn_stats feature - * 0 -> disable the feature - * 1 -> enable the feature - * Refer to below WMI_RSRC_CFG_FLAGS2_RECV_BCN_STATS_ENABLED_GET/SET - * macros. - * Bits 28:26 - extension bits for specifing the format version of the - * rx peer metadata the target needs to use (to cover versions V2 and - * beyond). - * Bit 29 - enable ipi_stats feature: - * 0 -> disable the feature - * 1 -> enable the feature - * Refer to below WMI_RSRC_CFG_FLAGS2_IPI_STATS_ENABLED_GET/SET macros. - * Bit 30 - enable pcie_oob_wakeup feature: - * 0 -> disable the feature - * 1 -> enable the feature - * Refer to below WMI_RSRC_CFG_FLAGS2_PCIE_OOB_WAKEUP_GET/SET macros. * - * Bit 31 - Reserved + * Bits 31:25 - Reserved */ A_UINT32 flags2; /** @brief host_service_flags - can be used by Host to indicate @@ -5481,69 +4958,7 @@ typedef struct { * So FW will start refilling the buffers. * Refer to the below definitions of WMI_RSRC_CFG_HOST_SERVICE_FLAG * OPT_DP_CTRL_REPLENISH_REFILL_RX_BUFFER_SUPPORT_GET and _SET macros. - * Bit 18 - * This bit will be set by host to inform FW that VBSS feature is - * enabled. - * Bit 19 - * This bit will set by host to inform FW that the bypass approach - * for HLOS TID OVERRIDE feature not working needs to be supported, - * So FW will start handling the PPE2TCL enqueued packets with - * flow_override set. - * Refer to the below definitions of WMI_RSRC_CFG_HOST_SERVICE_FLAG - * OPT_DP_ENABLE_BYPASS_FOR_HLOS_TID_OVERRIDE_GET and _SET macros. - * Bit 20 - * This bit will set by host to inform FW that action OUI v2 is - * enabled by both host configuration and FW capability. - * Refer to the below definitions of - * WMI_RSRC_CFG_HOST_SERVICE_FLAG_ACTION_OUI_V2_GET and SET. - * Bit 21 - * This bit will be set by host to inform FW that HW blacklist - * channel is supported in host. Based on this flag, FW will do - * CTL generation for all the IEEE channels allowed in the VLP - * and SP power for the current county and update host in the - * below WMI Events: - * WMI_REG_CHAN_LIST_CC_EXT_EVENTID, WMI_AFC_EVENTID, and - * WMI_HW_BLACKLIST_CHAN_EVENTID - * Bit 22 - * This bit will be set by host to inform FW that AFC handling - * is supported in the default cc event id. Based on this flag, - * FW will send the AFC event in the default cc event id if the - * country supports SP regulatory rules. - * Refer to the below defintions of WMI_RSRC_CFG_HOST_SERVICE_FLAG - * AFC_TRIGGER_ON_DEFAULT_CC_EVENT_GET and _SET macros. - * Bit 23 - * This bit will set by host to inform FW that direct refill to - * SW2RxDMA ring is supported by the host and the ring which is - * directly refilled by HOST will be indicated in the - * HTT_H2T_MSG_TYPE_SRING_SETUP and FW should refill the Rx buffers - * to the secondary refill ring. - * Refer to the below definitions of WMI_RSRC_CFG_HOST_SERVICE_FLAG - * DIRECT_REFILL_SUPPORT_GET and _SET macros. - * Bit 24 - * This bit will be set by host to inform FW that HOST will be - * expecting and will be able to handle DCS stats event sent - * by FW for concurrent vdevs (event can support max 2 vdevs data). - * Bit 25 - * This bit will be set by host to inform FW that HOST will support - * SMD BSS transition. - * Refer to the below definitions of - * WMI_RSRC_CFG_HOST_SERVICE_FLAG_SMD_BSS_TRANSITION_GET and _SET - * macros. - * Bit 26 - * This bit will be set by host to inform FW that the rx management - * path directly to the host is enabled, so the FW need not forward - * rx mgmt frames to the host. - * Refer to the below definitions of - * WMI_RSRC_CFG_HOST_SERVICE_FLAG_HOST_RX_MGMT_DIRECT_ENABLE_GET and - * _SET macros. - * Bit 27 - * This bit will be set by host to inform FW that the CUMAC_CMD_ID - * will come post WMI_INIT_CMDID and the MLO_SRNG setup has to be - * done as part of this cmd. - * Refer to the below definitions of - * WMI_RSRC_CFG_HOST_SERVICE_FLAG_CUMAC_CMD_SUPPORT_GET and SET_macros. - * - * Bits 31:28 - Reserved + * Bits 31:18 - Reserved */ A_UINT32 host_service_flags; @@ -5660,93 +5075,8 @@ typedef struct { * BIT 6 : 31 Reserved */ A_UINT32 c2c_int_type_config; - - /** - * @brief apf_data_ofld_enable - * BIT 0 -> enable/disable offload support in apf - * @detail: This flag will indicate during init time - * based on the vendor img version if APF is supporting - * any offloads. - * BIT 1 : 31 Reserved - */ - union { - A_UINT32 apf_data_ofload_enable__word; - struct { - A_UINT32 - apf_data_ofld_enable: 1, - reserved: 31; - }; - }; - /** - * @brief HAPS flags setting for power save config - * bit 0 : Enable disable haps feature - * bit 1 : Sync and update qtime cnss timestamp - * BIT 2-31: Reserved - */ - A_UINT32 dp_haps_config; - - /** - * @brief nan_config_word - * BIT 0 : 7 -> Minimum lead time (in milliseconds) that firmware - * must ensure before sending WMI_NAN_NEXT_DW_INFO_EVENTID, - * as configured via host INI settings. - * BIT 8 : 31 -> Reserved - */ - union { - A_UINT32 nan_config_word; - struct { - A_UINT32 - dw_notif_lead_time: 8, - /* enable supplicant based NAN offload mode */ - enable_nan_ofld_mode: 1, - /* disable/enable temporal IOT mode */ - enable_temporal_iot_mode: 1, - reserved2: 22; - }; - }; } wmi_resource_config; -#define WMI_RSRC_CFG_APF_DATA_OFLD_ENABLE_GET(word32) \ - WMI_GET_BITS(word32, 0, 1) -#define WMI_RSRC_CFG_APF_DATA_OFLD_ENABLE_SET(word32, value) \ - WMI_SET_BITS(word32, 0, 1, value) - -#define WMI_RSRC_CFG_NAN_CONFIG_DW_NOTIF_LEAD_TIME_GET(word32) \ - WMI_GET_BITS(word32, 0, 8) -#define WMI_RSRC_CFG_NAN_CONFIG_DW_NOTIF_LEAD_TIME_SET(word32, value) \ - WMI_SET_BITS(word32, 0, 8, value) - -#define WMI_RSRC_CFG_NAN_CONFIG_ENABLE_NAN_OFLD_MODE_GET(word32) \ - WMI_GET_BITS(word32, 8, 1) -#define WMI_RSRC_CFG_NAN_CONFIG_ENABLE_NAN_OFLD_MODE_SET(word32, value) \ - WMI_SET_BITS(word32, 8, 1, value) - -#define WMI_RSRC_CFG_NAN_CONFIG_ENABLE_NAN_TEMPORAL_IOT_MODE_GET(word32) \ - WMI_GET_BITS(word32, 9, 1) -#define WMI_RSRC_CFG_NAN_CONFIG_ENABLE_NAN_TEMPORAL_IOT_MODE_SET(word32, value) \ - WMI_SET_BITS(word32, 9, 1, value) - - -/* - * WMI_NAN_DISC_COOKIE_GET / WMI_NAN_DISC_COOKIE_SET - * - * Accessor macros for the 64-bit cookie value split across - * cookie_low32 and cookie_high32 fields in WMI NAN disc structs. - * - * Usage (read): - * A_UINT64 c = WMI_NAN_DISC_COOKIE_GET(p->cookie_low32, p->cookie_high32); - * - * Usage (write): - * WMI_NAN_DISC_COOKIE_SET(p->cookie_low32, p->cookie_high32, my_cookie); - */ -#define WMI_NAN_DISC_COOKIE_GET(low32, high32) \ - (((A_UINT64)(high32) << 32) | (A_UINT64)(low32)) -#define WMI_NAN_DISC_COOKIE_SET(low32, high32, cookie64) \ - do { \ - (low32) = (A_UINT32)((cookie64) & 0xFFFFFFFFUL); \ - (high32) = (A_UINT32)(((cookie64) >> 32) & 0xFFFFFFFFUL); \ - } while (0) - #define WMI_MSDU_FLOW_AST_ENABLE_GET(msdu_flow_config0, ast_x) \ (((ast_x) == 0) ? 1 : ((msdu_flow_config0) & (1 << ((ast_x) - 1)))) #define WMI_MSDU_FLOW_AST_ENABLE_SET(msdu_flow_config0, ast_x, enable) \ @@ -6039,26 +5369,6 @@ typedef struct { #define WMI_RSRC_CFG_FLAGS2_OPTIMIZE_POWER_SET(flags2, value) \ WMI_SET_BITS(flags2, 23, 2, value) -#define WMI_RSRC_CFG_FLAGS2_RECV_BCN_STATS_ENABLED_GET(flags2) \ - WMI_GET_BITS(flags2, 25, 1) -#define WMI_RSRC_CFG_FLAGS2_RECV_BCN_STATS_ENABLED_SET(flags2, value) \ - WMI_SET_BITS(flags2, 25, 1, value) - -#define WMI_RSRC_CFG_FLAGS2_RX_PEER_METADATA_EXTENSION_GET(flags2) \ - WMI_GET_BITS(flags2, 26, 3) -#define WMI_RSRC_CFG_FLAGS2_RX_PEER_METADATA_EXTENSION_SET(flags2, value) \ - WMI_SET_BITS(flags2, 26, 3, value) - -#define WMI_RSRC_CFG_FLAGS2_IPI_STATS_ENABLED_GET(flags2) \ - WMI_GET_BITS(flags2, 29, 1) -#define WMI_RSRC_CFG_FLAGS2_IPI_STATS_ENABLED_SET(flags2, value) \ - WMI_SET_BITS(flags2, 29, 1, value) - -#define WMI_RSRC_CFG_FLAGS2_PCIE_OOB_WAKEUP_GET(flags2) \ - WMI_GET_BITS(flags2, 30, 1) -#define WMI_RSRC_CFG_FLAGS2_PCIE_OOB_WAKEUP_SET(flags2, value) \ - WMI_SET_BITS(flags2, 30, 1, value) - #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_GET(host_service_flags) \ WMI_GET_BITS(host_service_flags, 0, 1) @@ -6166,70 +5476,6 @@ typedef struct { #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_VBSS_ENABLED_SET(host_service_flags, val) \ WMI_SET_BITS(host_service_flags, 18, 1, val) -/* - * This bit is to inform that we need to enable the bypass approach - * (for HLOS TID override feature not working in the target) - * to handle flowq creation from FW when flow override is set and - * frames are recvd from PPE2TCL. - * */ -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_OPT_DP_ENABLE_BYPASS_FOR_HLOS_TID_OVERRIDE_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 19, 1) -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_OPT_DP_ENABLE_BYPASS_FOR_HLOS_TID_OVERRIDE_SET(host_service_flags, val) \ - WMI_SET_BITS(host_service_flags, 19, 1, val) - -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_ACTION_OUI_V2_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 20, 1) -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_ACTION_OUI_V2_SET(host_service_flags, val) \ - WMI_SET_BITS(host_service_flags, 20, 1, val) - -/* This bit is used to inform FW to send HW Blacklist channels to host */ -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_HOST_SUPPORT_HW_BLACKLIST_CHANNEL_SUPPORT_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 21, 1) -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_HOST_SUPPORT_HW_BLACKLIST_CHANNEL_SUPPORT_SET(host_service_flags, val) \ - WMI_SET_BITS(host_service_flags, 21, 1, val) - -/* This bit is used to inform FW to send AFC event ID in default CC event ID */ -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_AFC_TRIGGER_ON_DEFAULT_CC_EVENT_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 22, 1) -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_AFC_TRIGGER_ON_DEFAULT_CC_EVENT_SET(host_service_flags, val) \ - WMI_SET_BITS(host_service_flags, 22, 1, val) - -/* This bit is used to inform FW that HOST supports direct Rx buffers refill to the SW2RxDMA ring*/ -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_DIRECT_REFILL_SUPPORT_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 23, 1) -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_DIRECT_REFILL_SUPPORT_SET(host_service_flags, val) \ - WMI_SET_BITS(host_service_flags, 23, 1, val) - -/* This bit will be used to inform FW that HOST will be handling DCS stats for multiple vdevs (max 2) */ -#define WMI_RSRC_CFG_DCS_STATS_FOR_2VDEVS_ENABLE_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 24, 1) -#define WMI_RSRC_CFG_DCS_STATS_FOR_2VDEVS_ENABLE_SET(host_service_flags, value) \ - WMI_SET_BITS(host_service_flags, 24, 1, value) - -/* This bit will be used to inform FW that HOST enables SMD BSS transition */ -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_SMD_BSS_TRANSITION_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 25, 1) -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_SMD_BSS_TRANSITION_SET(host_service_flags, value) \ - WMI_SET_BITS(host_service_flags, 25, 1, value) - -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_HOST_RX_MGMT_DIRECT_ENABLE_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 26, 1) -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_HOST_RX_MGMT_DIRECT_ENABLE_SET(host_service_flags, value) \ - WMI_SET_BITS(host_service_flags, 26, 1, value) - -/* - * Bit 27: Host supports WMI_PDEV_SET_CUMAC_CHIP_CMDID. - * When set, FW will call the MLO CUMAC init function from the - * WMI_PDEV_SET_CUMAC_CHIP_CMDID handler instead of the MLO SoC init function. - * Requires WMI_SERVICE_PDEV_SET_CUMAC_CHIP_CMD_SUPPORT to be set in - * wmi_service_ready before the host sets this bit. - */ -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_CUMAC_CMD_SUPPORT_GET(host_service_flags) \ - WMI_GET_BITS(host_service_flags, 27, 1) -#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_CUMAC_CMD_SUPPORT_SET(host_service_flags, val) \ - WMI_SET_BITS(host_service_flags, 27, 1, val) - - #define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_GET(carrier_config) \ WMI_GET_BITS(carrier_config, 0, 1) #define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_SET(carrier_config, val) \ @@ -6280,7 +5526,6 @@ typedef enum { WMI_WIFI_STANDARD_6 = 2, WMI_WIFI_STANDARD_6E = 3, WMI_WIFI_STANDARD_7 = 4, - WMI_WIFI_STANDARD_8 = 5, } WMI_WIFI_STANDARD; typedef enum { @@ -6304,8 +5549,6 @@ typedef enum { WMI_VENDOR1_REQ1_VERSION_4_10 = 6, WMI_VENDOR1_REQ1_VERSION_4_20 = 7, WMI_VENDOR1_REQ1_VERSION_4_40 = 8, - WMI_VENDOR1_REQ1_VERSION_4_50 = 9, - WMI_VENDOR1_REQ1_VERSION_4_60 = 10, } WMI_VENDOR1_REQ1_VERSION; typedef enum { @@ -6313,8 +5556,6 @@ typedef enum { WMI_VENDOR1_REQ2_VERSION_3_01 = 1, WMI_VENDOR1_REQ2_VERSION_3_20 = 2, WMI_VENDOR1_REQ2_VERSION_3_50 = 3, - WMI_VENDOR1_REQ2_VERSION_3_61 = 4, - WMI_VENDOR1_REQ2_VERSION_3_70 = 5, } WMI_VENDOR1_REQ2_VERSION; typedef enum { @@ -6721,10 +5962,6 @@ typedef struct { typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tlv_buf_len_param */ A_UINT32 buf_len; /** Length of buf */ -/* NOTE: - * This struct cannot be expanded, due to being used as - * WMITLV_TAG_ARRAY_FIXED_STRUC in WMI_ROAM_INVOKE_CMDID. - */ /** * Following this structure is the TLV byte stream of buf of length buf_len: * A_UINT8 buf[]; @@ -7048,18 +6285,16 @@ typedef struct { #define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT 0x40000 #define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000 #define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000 +/** pause home channel when scan channel is same as home channel */ +#define WMI_SCAN_FLAG_PAUSE_HOME_CHANNEL 0x200000 +/** + * report CCA busy for each possible 20Mhz subbands of the wideband scan channel + */ +#define WMI_SCAN_FLAG_REPORT_CCA_BUSY_FOREACH_20MHZ 0x400000 + /** for adaptive scan mode using 3 bits (21 - 23 bits) */ #define WMI_SCAN_DWELL_MODE_MASK 0x00E00000 #define WMI_SCAN_DWELL_MODE_SHIFT 21 -/** pause home channel when scan channel is same as home channel (bit 24) */ -#define WMI_SCAN_FLAG_PAUSE_HOME_CHANNEL 0x01000000 -/** - * report CCA busy for each possible 20MHz subband of the wideband scan channel - * (bit 25) - */ -#define WMI_SCAN_FLAG_REPORT_CCA_BUSY_FOREACH_20MHZ 0x02000000 -/* Premium scan to receive higher MCS packets in scan channel */ -#define WMI_SCAN_FLAG_PREMIUM_SCAN 0x04000000 typedef enum { WMI_SCAN_DWELL_MODE_DEFAULT = 0, @@ -7078,11 +6313,7 @@ typedef enum { #define WMI_SCAN_GET_DWELL_MODE(flag) \ (((flag) & WMI_SCAN_DWELL_MODE_MASK) >> WMI_SCAN_DWELL_MODE_SHIFT) -/** - * WMI_SCAN_CLASS_MASK must be the same value as IEEE80211_SCAN_CLASS_MASK - * This bitmask is used to set/get values of req_type variable in - * wmi_stop_scan_cmd_fixed_param. - */ +/** WMI_SCAN_CLASS_MASK must be the same value as IEEE80211_SCAN_CLASS_MASK */ #define WMI_SCAN_CLASS_MASK 0xFF000000 /* @@ -7414,37 +6645,6 @@ typedef struct { A_UINT32 flags; } wmi_scan_event_fixed_param; -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_suppress_cmd_fixed_param */ - - /** suppress_scan: - * set to 0: to enable scan - * set to 1: to suppress scan - */ - A_UINT32 suppress_scan; - /** Scan client id, refer to enum WMI_SCAN_CLIENT_ID */ - A_UINT32 scan_client_id; -} wmi_scan_suppress_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_get_scan_stats_cmd_fixed_param */ - - /** Scan client id, refer to enum WMI_SCAN_CLIENT_ID */ - A_UINT32 scan_client_id; -} wmi_get_scan_stats_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_stats_rsp_fixed_param */ - - /** Scan client id, refer to enum WMI_SCAN_CLIENT_ID */ - A_UINT32 scan_client_id; - /** scan_count: - * Total number of scans triggered/started for a given scan_clnt_id - * which is requested by scan stats command - */ - A_UINT32 scan_count; -} wmi_get_scan_stats_resp_fixed_param; - /* WMI Diag event */ typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag is WMITLV_TAG_STRUC_wmi_diag_event_fixed_param */ @@ -8403,9 +7603,6 @@ typedef struct { #define WMI_TX_SEND_FLAG_SET_P2P_FRAME_ON_STA_VDEV 0x00000008 #define WMI_TX_SEND_FLAG_SET_P2P_FRAME_ON_STA_VDEV_GET(tx_flags) WMI_GET_BITS(tx_flags, 3, 1) #define WMI_TX_SEND_FLAG_SET_P2P_FRAME_ON_STA_VDEV_SET(tx_flags, value) WMI_SET_BITS(tx_flags, 3, 1, value) -#define WMI_TX_SEND_FLAG_SET_SMD_HIGH_PRIORITY_FRAME 0x00000010 -#define WMI_TX_SEND_FLAG_SET_SMD_HIGH_PRIORITY_FRAME_GET(tx_flags) WMI_GET_BITS(tx_flags, 4, 1) -#define WMI_TX_SEND_FLAG_SET_SMD_HIGH_PRIORITY_FRAME_SET(tx_flags, value) WMI_SET_BITS(tx_flags, 4, 1, value) typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tx_send_params */ @@ -8751,45 +7948,6 @@ typedef struct { A_UINT32 scan_start; } wmi_pdev_scan_cmd; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_soc_get_conc_info_cmd_fixed_param */ -} wmi_soc_get_conc_info_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_conc_info */ - - A_UINT32 vdev_id; - A_UINT32 type; /* interface type : WMI_VDEV_MODE */ - wmi_mac_addr bssid; - A_UINT32 freq; /* in MHz*/ - /* rssi value (in dBm) valid for STA vdev, for other INVALID_RSSI */ - A_INT32 rssi; -} wmi_conc_info; - -typedef enum { - WMI_VDEV_MODE_STA = 0, - WMI_VDEV_MODE_SAP = 1, - WMI_VDEV_MODE_MLO_STA = 2, - WMI_VDEV_MODE_MLO_SAP = 3, - WMI_VDEV_MODE_P2P_CLI = 4, - WMI_VDEV_MODE_P2P_GO = 5, - WMI_VDEV_MODE_NAN = 6, - WMI_VDEV_MODE_NDI = 7, - - WMI_VDEV_MODE_MAX -} WMI_VDEV_MODE; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_soc_get_conc_info_resp_fixed_param */ - - /* - * Following this fixed_param TLV is a variable-length TLV array: - * wmi_conc_info conc_info_list[]; - */ -} wmi_soc_get_conc_info_resp_fixed_param; - - /* WMI support for setting ratemask in target */ typedef struct { @@ -9050,14 +8208,6 @@ typedef struct { A_UINT32 sw_retry_th; /* max retry count per AC base on ac_type for the vdev mentioned in vdev id*/ } wmi_vdev_set_custom_sw_retry_th_cmd_fixed_param; -typedef enum { - /* Set when user forces the chainmask config */ - WMI_FORCE_CHM_MODE_USER_FORCE = 0, - - /* Set when there is no user force */ - WMI_FORCE_CHM_MODE_DEFAULT_CONFIG = 1, -} WMI_FORCE_CHM_MODE; - typedef struct { /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_chainmask_config_cmd_fixed_param */ A_UINT32 tlv_header; @@ -9100,7 +8250,6 @@ typedef struct { A_UINT32 fast_chain_selection; /* RSSI delta threshold to determine better chain, units: dB */ A_UINT32 better_chain_rssi_threshold; - A_UINT32 force_mode; /* holds a WMI_FORCE_CHM_MODE enum value */ } wmi_vdev_chainmask_config_cmd_fixed_param; /* @@ -9609,11 +8758,6 @@ typedef enum { WMI_SCHED_MODE_UL_OFDMA = 0x00000008, } WMI_SCHED_MODE_FLAGS; -typedef enum { - WMI_PDEV_PARAM_TEMP_TX_POWER_LIMIT_RESET = 0, - WMI_PDEV_PARAM_TEMP_TX_POWER_LIMIT_SET, -} wmi_pdev_param_set_temp_tx_power_limit; - typedef enum { /** TX chain mask */ WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1, @@ -10799,67 +9943,6 @@ typedef enum { /* To enable/disable DFS radar detection for scan radio */ WMI_PDEV_PARAM_ENABLE_SCAN_RADIO_DFS, - - /* configure CCE rules based on ethertype match */ - WMI_PDEV_PARAM_CONFIG_CUSTOM_CCE_RULE, - - /* temporary tx power limit */ - WMI_PDEV_PARAM_TEMP_TX_POWER_LIMIT, - - /* configure pdev coex stats period (millisecond units) */ - WMI_PDEV_PARAM_COEX_STATS_UPDATE_PERIOD, - - /* To enable/disable XPAN SAP + STA power optimization */ - WMI_PDEV_PARAM_XPAN_STA_PWRSAVE_ENABLE, - - /** Beacon antenna for smart antenna */ - WMI_PDEV_PARAM_SMART_ANTENNA_BEACON_ANTENNA, - - /* - * The extra early rx duration (in usec units) when - * adaptive early rx is disabled - */ - WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_EXTRA_SLEEP_SLOP, - - /* Set TAS mode after boot up */ - WMI_PDEV_PARAM_SET_TAS_MODE, - - WMI_PDEV_PARAM_L3_HEADER_PADDING_ENABLE, - - /* To enable/ disable beacon LIO update based on screen on/off */ - WMI_PDEV_PARAM_BEACON_LIO_UPDATE_ON_SCREEN_ON_OFF, - - /** - * Configure the CSA wait timeout (in ms) before blocking TX - * after radar detection - */ - WMI_PDEV_PARAM_DFS_NOL_CSA_WAIT_TIMEOUT, - - /** - * Smart antenna MPDU MCS params config. - * bit | purpose - * ------|--------- - * 0:9 | Max MPDU count for training - * 10 | MCS margin enable (0: disable, 1: enable) - * 11:13 | MCS margin value - * 14:31 | Reserved - */ - WMI_PDEV_PARAM_SMART_ANTENNA_CONFIG_MPDU_MCS_PARAMS, - - /** On-demand AWGN interference status request. - * FW reads awgn_prev_int_seg and sends WMI_DCS_INTERFERENCE_EVENTID - * with interference_type=ATH_CAP_DCS_AGWNIM only if interference is - * currently detected (bitmap != 0). A bitmap of 0 means no interference. - * param_value is reserved (set to 1 to trigger the request). - */ - WMI_PDEV_PARAM_AWGN_INT_STATUS_REQUEST, - - /** - * Disable L3 validity check in offload manager. - * 0 - L3_valid check enabled (default) - * 1 - L3_valid check disabled (frames not dropped on L3_valid=false) - */ - WMI_PDEV_PARAM_ENABLE_OFFLD_L3_VALID_CHECK, } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) @@ -10944,8 +10027,6 @@ typedef enum { #define WMI_PDEV_UPPER_CAP_DL_DIR_SET(_value, value) WMI_SET_BITS(_value, 18, 1, value) #define WMI_PDEV_UPPER_CAP_UL_DIR_GET(value) WMI_GET_BITS(value, 19, 1) #define WMI_PDEV_UPPER_CAP_UL_DIR_SET(_value, value) WMI_SET_BITS(_value, 19, 1, value) -#define WMI_PDEV_UPPER_CAP_DIR_GET(value) WMI_GET_BITS(value, 18, 1) -#define WMI_PDEV_UPPER_CAP_DIR_SET(_value, value) WMI_SET_BITS(_value, 18, 1, value) #define WMI_PDEV_RATE_DROP_NUM_MCS_GET(value) WMI_GET_BITS(value, 0, 8) #define WMI_PDEV_RATE_DROP_NUM_MCS_SET(_value, value) WMI_SET_BITS(_value, 0, 8, value) @@ -10966,22 +10047,6 @@ typedef enum { #define WMI_PDEV_RATE_MAX_NSS_PROBE_INTERVAL_GET(value) WMI_GET_BITS(value, 16, 16) #define WMI_PDEV_RATE_MAX_NSS_PROBE_INTERVAL_SET(_value, value) WMI_SET_BITS(_value, 16, 16, value) -/* WMI GET/SET macros for WMI_PDEV_PARAM_SMART_ANTENNA_CONFIG_MPDU_MCS_PARAMS */ -#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MAX_TRAIN_MPDU_GET(param) \ - WMI_GET_BITS(param, 0, 10) -#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MAX_TRAIN_MPDU_SET(_param, value) \ - WMI_SET_BITS(_param, 0, 10, value) - -#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MCS_MARGIN_EN_GET(param) \ - WMI_GET_BITS(param, 10, 1) -#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MCS_MARGIN_EN_SET(_param, value) \ - WMI_SET_BITS(_param, 10, 1, value) - -#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MCS_MARGIN_VAL_GET(param) \ - WMI_GET_BITS(param, 11, 3) -#define WMI_PDEV_SMART_ANT_MPDU_MCS_PARAMS_MCS_MARGIN_VAL_SET(_param, value) \ - WMI_SET_BITS(_param, 11, 3, value) - #define WMI_MBSSID_CTRL_FRAME_BASIC_TRIGGER ((A_UINT32) 1 << 0) #define WMI_MBSSID_CTRL_FRAME_BSR_TRIGGER ((A_UINT32) 1 << 1) #define WMI_MBSSID_CTRL_FRAME_MU_RTS_TRIGGER ((A_UINT32) 1 << 2) @@ -11056,23 +10121,6 @@ typedef struct { A_UINT32 param; } wmi_pdev_get_tpc_config_cmd_fixed_param; -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_tpc_ie_power_cmd_fixed_param */ - A_UINT32 vdev_id; - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 pdev_id; - A_UINT32 mgmt_rate; /* Values are sent as Ratecode */ -} wmi_vdev_get_tpc_ie_power_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_tpc_ie_power_event_fixed_param */ - A_UINT32 vdev_id; - A_UINT32 pdev_id; - A_INT32 tx_pwr; /* return value will be in unit of 0.25 dBm */ -} wmi_vdev_tpc_ie_power_event_fixed_param; - typedef struct { A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_pdev_div_get_rssi_antid_fixed_param */ /** pdev_id for identifying the MAC */ @@ -11483,21 +10531,6 @@ typedef struct { * ack_rssi is reported in dBm. */ A_INT32 ack_rssi; - - /* ieee_link_id_valid: - * For MLO cases, ieee_link_id_valid is set to 1, which indicates that - * the ieee_link_id field contains a valid value. - * For non-MLO and legacy cases, ieee_link_id_valid is set to 0, which - * means ignore the ieee_link_id field. - */ - A_UINT32 ieee_link_id_valid; - /* ieee_link_id: - * For MLO cases, this indicates the link on which the QoS Null frame - * is sent. - * For non-MLO cases, this is not required because the QoS Null frame - * is sent on the connected link. - */ - A_UINT32 ieee_link_id; } wmi_qos_null_frame_tx_compl_event_fixed_param; typedef struct { @@ -11567,16 +10600,6 @@ typedef struct { */ } wmi_pdev_tpc_config_event_fixed_param; - -typedef enum { - WMI_ASD_PRIMARY_ANT = 0, - WMI_ASD_DIVERSITY_ANT = 1, - WMI_ASD_THIRD_ANT = 2, - WMI_ASD_FOURTH_ANT = 3, - - WMI_ASD_MAX_ANTTYPE = 4 -} WMI_ASD_ANT_TYPE; - typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_div_rssi_antid_event_fixed_param */ A_UINT32 tlv_header; @@ -11590,17 +10613,6 @@ typedef struct { wmi_mac_addr macaddr; /* EVM value for stream0 and stream1 20Mhz, dB units */ A_INT32 chain_evm[WMI_MAX_CHAINS]; - /** num_antennas_valid: - * how many elements in the WMI_ASD_MAX_ANTTYPE arrays below - * contain valid info - */ - A_UINT32 num_antennas_valid; - /** switch count on each antenna attached to each chain */ - A_UINT32 ant_cnt[WMI_MAX_CHAINS][WMI_ASD_MAX_ANTTYPE]; - /** stay duration on each antenna attached to each chain (units: ms) */ - A_UINT32 ant_dur[WMI_MAX_CHAINS][WMI_ASD_MAX_ANTTYPE]; - /** RSSI on each antenna attached to each chain in dbm */ - A_INT32 ant_rssi[WMI_MAX_CHAINS][WMI_ASD_MAX_ANTTYPE]; } wmi_pdev_div_rssi_antid_event_fixed_param; typedef struct { @@ -11959,7 +10971,7 @@ typedef enum { } MCAST_BCAST_RATE_ID; typedef struct { - A_UINT32 rate_id; /* MCAST_BCAST_RATE_ID */ + MCAST_BCAST_RATE_ID rate_id; A_UINT32 rate; } mcast_bcast_rate; @@ -12023,27 +11035,25 @@ typedef struct { } wmi_vdev_get_twt_session_stats_info_cmd_fixed_param; typedef enum { - WMI_REQUEST_PEER_STAT = 0x000001, - WMI_REQUEST_AP_STAT = 0x000002, - WMI_REQUEST_PDEV_STAT = 0x000004, - WMI_REQUEST_VDEV_STAT = 0x000008, - WMI_REQUEST_BCNFLT_STAT = 0x000010, - WMI_REQUEST_VDEV_RATE_STAT = 0x000020, - WMI_REQUEST_INST_STAT = 0x000040, - WMI_REQUEST_MIB_STAT = 0x000080, - WMI_REQUEST_RSSI_PER_CHAIN_STAT = 0x000100, - WMI_REQUEST_CONGESTION_STAT = 0x000200, - WMI_REQUEST_PEER_EXTD_STAT = 0x000400, - WMI_REQUEST_BCN_STAT = 0x000800, - WMI_REQUEST_BCN_STAT_RESET = 0x001000, - WMI_REQUEST_PEER_EXTD2_STAT = 0x002000, - WMI_REQUEST_MIB_EXTD_STAT = 0x004000, - WMI_REQUEST_PMF_BCN_PROTECT_STAT = 0x008000, - WMI_REQUEST_VDEV_EXTD_STAT = 0x010000, - WMI_REQUEST_PDEV_EXTD_STAT = 0x020000, - WMI_REQUEST_PDEV_TELEMETRY_STAT = 0x040000, - WMI_REQUEST_VDEV_RECV_BCN_STAT = 0x080000, - WMI_REQUEST_PDEV_COEX_STAT = 0x100000, + WMI_REQUEST_PEER_STAT = 0x00001, + WMI_REQUEST_AP_STAT = 0x00002, + WMI_REQUEST_PDEV_STAT = 0x00004, + WMI_REQUEST_VDEV_STAT = 0x00008, + WMI_REQUEST_BCNFLT_STAT = 0x00010, + WMI_REQUEST_VDEV_RATE_STAT = 0x00020, + WMI_REQUEST_INST_STAT = 0x00040, + WMI_REQUEST_MIB_STAT = 0x00080, + WMI_REQUEST_RSSI_PER_CHAIN_STAT = 0x00100, + WMI_REQUEST_CONGESTION_STAT = 0x00200, + WMI_REQUEST_PEER_EXTD_STAT = 0x00400, + WMI_REQUEST_BCN_STAT = 0x00800, + WMI_REQUEST_BCN_STAT_RESET = 0x01000, + WMI_REQUEST_PEER_EXTD2_STAT = 0x02000, + WMI_REQUEST_MIB_EXTD_STAT = 0x04000, + WMI_REQUEST_PMF_BCN_PROTECT_STAT = 0x08000, + WMI_REQUEST_VDEV_EXTD_STAT = 0x10000, + WMI_REQUEST_PDEV_EXTD_STAT = 0x20000, + WMI_REQUEST_PDEV_TELEMETRY_STAT = 0x40000, } wmi_stats_id; /* @@ -12061,7 +11071,7 @@ typedef struct { typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_request_stats_cmd_fixed_param */ - A_UINT32 stats_id; /* wmi_stats_id */ + wmi_stats_id stats_id; /** unique id identifying the VDEV, generated by the caller */ A_UINT32 vdev_id; /** peer MAC address */ @@ -12753,77 +11763,6 @@ typedef struct { A_UINT32 tot_err_tim_bcn; } wmi_iface_powersave_stats; - -#define WMI_IPI_STATS_SNR_LOWER_BOUND_GET(snr_config) \ - WMI_GET_BITS(snr_config, 0, 8) -#define WMI_IPI_STATS_SNR_LOWER_BOUND_SET(snr_config, value) \ - WMI_SET_BITS(snr_config, 0, 8, value) -#define WMI_IPI_STATS_SNR_UPPER_BOUND_GET(snr_config) \ - WMI_GET_BITS(snr_config, 8, 8) -#define WMI_IPI_STATS_SNR_UPPER_BOUND_SET(snr_config, value) \ - WMI_SET_BITS(snr_config, 8, 8, value) -#define WMI_IPI_STATS_SNR_STEP_GET(snr_config) \ - WMI_GET_BITS(snr_config, 16, 8) -#define WMI_IPI_STATS_SNR_STEP_SET(snr_config, value) \ - WMI_SET_BITS(snr_config, 16, 8, value) -#define WMI_IPI_STATS_SNR_NUM_BINS_GET(snr_config) \ - WMI_GET_BITS(snr_config, 24, 8) -#define WMI_IPI_STATS_SNR_NUM_BINS_SET(snr_config, value) \ - WMI_SET_BITS(snr_config, 24, 8, value) - -/* - * Signal to Noise Ration(SNR) is measured during idle periods and reported - * as a distribution across multiple bins - */ -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_iface_ipi_stats */ - - /* - * Total time in microseconds spent on the channel during which - * these signal-to-noise measurements were collected - */ - A_UINT32 meas_dur_us; - - /* snr_config: - * Contains lower bound, upper bound, step value and total bins for the - * SNR measurements done. - * Firmware collects the SNR data into - * (((upper_bound - lower_bound)/step) + out_of_bound_bins) - * bins and sends to host. - * lower_bound - Lower value of the SNR measurement range - * upper_bound - Upper value of the SNR measurement range - * step - Each bin data range - * num_bins - Number of bins calculated as per above formula, - * represents the number of elements in TLV snr_histogram - * out_of_bound_bins(=2) - Number of bins to carry values below lower - * bound and above upper bound in corresponding bin, - * including lower and upper bound values - * E.g - 1. lower_bound = 0, upper_bound = 100 and step = 10 - * Firmware collects the SNR samples into ((100-0)/10)+2 = 12 bins - * E.g - 2. lower_bound = 10, upper_bound = 90 and step = 20 - * Firmware collects the SNR samples into ((90-10)/20)+2 = 6 bins - */ - A_UINT32 snr_config; - - /* - * This TLV is followed by a snr_histogram TLV containing a variable-length - * array of A_UINT32 to carry data from each bin. - * Bin[0] contains the number of samples with SNR < lower_bound dB - * Bin[1] contains the number of samples with SNR in range - * [lower_bound, lower_bound + step) dB - * Bin[2] contains the number of samples with SNR in range - * [lower_bound + step, lower_bound + 2*step) dB - * ... - * Bin[num_bins - 2] contains the number of samples with SNR in range - * [upper_bound - step, upper_bound) dB - * Bin[num_bins - 1] contains the number of samples with - * SNR >= upper_bound dB - * - * A_UINT32 snr_histogram[num_bins] - */ -} wmi_iface_ipi_stats; - - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ipa_link_stats */ @@ -13037,7 +11976,7 @@ typedef struct { typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stats_event_fixed_param */ - A_UINT32 stats_id; /* wmi_stats_id */ + wmi_stats_id stats_id; /** number of pdev stats event structures (wmi_pdev_stats) 0 or 1 */ A_UINT32 num_pdev_stats; /** number of vdev stats event structures (wmi_vdev_stats) 0 or max vdevs */ @@ -13105,14 +12044,6 @@ typedef struct { * wmi_pdev_telemetry_stats wmi_pdev_telemetry_stats[] * follows the other TLVs */ -/* If WMI_REQUEST_VDEV_RECV_BCN_STAT is set in stats_id, then TLV - * wmi_recv_bcn_stats wmi_recv_bcn_stats[] - * follows the other TLVs - */ -/* If WMI_REQUEST_PDEV_COEX_STAT is set in stats_id, then TLV - * wmi_pdev_coex_stats wmi_pdev_coex_stats[] - * follows the other TLVs - */ } wmi_stats_event_fixed_param; /* WLAN channel CCA stats bitmap */ @@ -13614,20 +12545,8 @@ typedef struct { * * b'31-b'29 unused / reserved * b'28 indicate the version of rate-code (1 = RATECODE_V1) - * b'27 unused / reserved - * b'26-b'19 indicate TX power (int8), with 0.25 dBm units - * b'15-b'14 indicate punctured mode as follows: - * 0: NO_PUNCTURE - * 1: PUNCTURED_20MHZ - * 2: PUNCTURED_40MHZ - * 3: PUNCTURED_80MHZ - * 4: PUNCTURED_120MHZ - * b'15-b'14 indicate the guard interval: - * 0: 800us, 1: 400us, 2: 1600us, 3: 3200us - * b'13-b'11 indicate the bandwidth: - * 0: 20MHz, 1: 40MHz, 2: 80MHz, 3: 160MHz, 4: 320MHz - * b'10-b'8 indicate the preamble: - * 0: OFDM, 1: CCK, 2: HT, 3: VHT, 4: HE, 5: EHT + * b'27-b'11 unused / reserved + * b'10-b'8 indicate the preamble (0 OFDM, 1 CCK, 2 HT, 3 VHT) * b'7-b'5 indicate the NSS (0 - 1x1, 1 - 2x2, 2 - 3x3, 3 - 4x4) * b'4-b'0 indicate the rate, which is indicated as follows: * OFDM : 0: OFDM 48 Mbps @@ -13650,9 +12569,6 @@ typedef struct { * 0..7: MCS0..MCS7 (HT) * 0..9: MCS0..MCS9 (11AC VHT) * 0..11: MCS0..MCS11 (11AX VHT) - * HE/EHT (pream == 4/5) - * 0..13: MCS0..MCS13 (11AX EHT) - * 14..15: MCS14..MCS15 (EHT) */ /** rate-code of the last transmission */ A_UINT32 last_tx_rate_code; @@ -13776,240 +12692,224 @@ typedef struct { * number of vdev active count * (WMI_PDEV_STATS_VDEV_UP_CNT_SET,GET) */ - A_UINT32 opaque_debug_num_macs_phy_vdev_up_active; - /** refer wlan_pdev ic flags */ - A_UINT32 opaque_debug_ic_flags; - /** vdev_id that are paused per pdev */ - A_UINT32 opaque_debug_paused_ap_vdev_bitmap; - /** opaque_debug_flags: - * refer to WLAN_PS_DESC_BIN_HWM_HIT or WLAN_PS_DESC_BIN_LWM_HIT - */ - A_UINT32 opaque_debug_flags; - /** wlan_pdev fields remote_peer_cnt, max_rf_chains_2G and max_rf_chains_5G - * remote_peer_cnt_max_rf_chains_2G_5G: - * This word contains the following bitfields: - * max chains supported in the 2.4 GHz band - * (WMI_PDEV_STATS_MAX_RF_CHAIN_2G_SET,GET) - * max chains supported in the 5 GHz band, - * (WMI_PDEV_STATS_MAX_RF_CHAIN_5G_SET,GET) - * number of remote peers - * (WMI_PDEV_STATS_REMOTE_PEER_CNT_SET,GET) - */ - A_UINT32 opaque_debug_remote_peer_cnt_max_rf_chains_2G_5G; - /** wlan_pdev max HT Capability info, WMI_HT_CAP defines */ - A_UINT32 opaque_debug_max_ht_cap_info; - /** wlan_pdev max VHT capability info, WMI_VHT_CAP defines */ - A_UINT32 opaque_debug_max_vht_cap_info; - /** opaque_debug_max_vht_supp_mcs: - * wlan_pdev max VHT Supported MCS which is - * vht_supp_mcs_2G or vht_supp_mcs_5G - */ - A_UINT32 opaque_debug_max_vht_supp_mcs; - /** wlan_pdev max HE capability info, WMI_HE_CAP defines */ - A_UINT32 opaque_debug_max_he_cap_info; - A_UINT32 opaque_debug_max_he_cap_info_ext; - /** the nominal chain mask for transmit */ - A_UINT32 opaque_debug_tx_chain_mask; - /** the nominal chain mask for receive */ - A_UINT32 opaque_debug_rx_chain_mask; - /** opaque_debug_ema_flags: - * This word contains the following bitfields: - * ema_flags: ema_max_vap_cnt and ema_max_profile_period from wlan_pdev - * ema_max_vap_cnt- number of maximum EMA Tx vaps (VAPs having both - * VDEV_FLAGS_EMA_MODE and VDEV_FLAGS_TRANSMIT_AP set) - * (WMI_PDEV_STATS_EMA_MAX_VAP_CNT_SET,GET) - * ema_max_profile_period - maximum profile periodicity - * (maximum number of beacons after which VAP profiles repeat) - * for any EMA VAP on any pdev. - * (WMI_PDEV_STATS_EMA_MAX_PROFILE_PERIOD_SET,GET) - */ - A_UINT32 opaque_debug_ema_flags; - /** wlan_pdev - maximum ML peers supported */ - A_UINT32 opaque_debug_num_ml_peer_entries; - /** This word contains the following bitfields: - * wlan_pdev fields - num_max_hw_links, current_chip_id and max_num_chips - * (related to MLO) - * Max number of HW links - * (WMI_PDEV_STATS_NUM_MAX_HW_LINKS_SET,GET) - * Current Chip Id - * (WMI_PDEV_STATS_CURRENT_CHIP_ID_SET,GET) - * Max number of chips - * (WMI_PDEV_STATS_MAX_NUM_CHIPS_SET,GET) - */ - A_UINT32 opaque_debug_mlo_flags; - /** Indicate beacon size in bytes */ - A_UINT32 opaque_debug_large_bcn_size; - /** proposed by the host value of MSDUQs per each LinkView peer's TID */ - A_UINT32 opaque_debug_num_of_linkview_msduqs_per_tid; - /** bcn_filter_context variables */ - A_UINT32 opaque_debug_bcns_dropped; - A_UINT32 opaque_debug_bcns_recvd; - A_UINT32 opaque_debug_bcns_delivered; - /** - * Lower 32 bits bitmap of pause ids for TIDs that are paused/unpaused - * based on module_id. - */ - A_UINT32 opaque_debug_vdev_all_tid_pause_bitmap; - /** - * Lower 32 bits bitmap of pause ids for TIDs that are blocked/unblocked - * based on module_id. - */ - A_UINT32 opaque_debug_vdev_all_tid_block_bitmap; - /** wal_pdev rx filter, WAL_RX_FILTER_FLAGS defines */ - A_UINT32 opaque_debug_rx_filter; - /** This word contains the following bitfields: - * aggr_nonaggr_retry_th: - * wal_pdev fields - agg_retry_th and non_agg_retry_th - * This value holds max retry threshold up to which a Data packet - * will be retried when ack is not received. - * agg_retry_th - Threshold value used when aggregation is enabled - * (WMI_PDEV_STATS_AGG_RETRY_TH_SET,GET) - * non_agg_retry_th - Threshold value used for non-aggregation. - * (WMI_PDEV_STATS_NON_AGG_RETRY_TH_SET) - */ - A_UINT32 opaque_debug_aggr_nonaggr_retry_th; - /** This word contains the following bitfields: - * num_max_rx_ba_sessions: - * Number of rx BA session establised - * (WMI_PDEV_STATS_NUM_RX_BA_SESSIONS_SET,GET) - * Max number of rx BA session from wal_pdev - * (WMI_PDEV_STATS_MAX_RX_BA_SESSIONS_SET,GET) - */ - A_UINT32 opaque_debug_num_max_rx_ba_sessions; - /** It holds WHAL_CHANNEL_SWITCH_FLAGS values */ - A_UINT32 opaque_debug_chan_switch_flags; - /** reset_cause holds PDEV_RESET_CONSEC_FAILURE or PDEV_RESET_TXQ_TIMEOUT */ - A_UINT32 opaque_debug_consecutive_failure_reset_cause; - /** PPDU duration limit, in us */ - A_UINT32 opaque_debug_mu_ppdu_dur_limit_us; - /** pdev reset in progress */ - A_UINT32 opaque_debug_reset_in_progress; - /** wal_dev - vdev_migrate_state refer to WAL_VDEV_MIGRATE_STATE */ - A_UINT32 opaque_debug_vdev_migrate_state; - /** opaque_debug_rts_rc_flag: - * wal_pdev rts ratecode - this value reflects whatever - * WMI_PDEV_PARAM_RTS_FIXED_RATE value the host has specified for the pdev. - */ - A_UINT32 opaque_debug_rts_rc_flag; - /* Num of peer delete in progress */ - A_UINT32 opaque_debug_num_of_peer_delete_in_progress; - /** wal_pdev total number of active vdev count */ - A_UINT32 opaque_debug_total_active_vdev_cnt; - /** wal_pdev - max number of vdevs per pdev */ - A_UINT32 opaque_debug_max_vdevs; - /* NonOccupancyList(NOL) context */ - A_UINT32 opaque_debug_dfs_nol_count; - /** NOL timeout in seconds */ - A_UINT32 opaque_debug_dfs_nol_timeout; - A_UINT32 opaque_debug_dfs_use_nol; - /** channel availability check mode, refer enum WMI_ADFS_OCAC_MODE */ - A_UINT32 opaque_debug_cac_mode; - A_UINT32 opaque_debug_dyn_ppdu_dur; /* in ms */ - /** This word contains the following bitfields: - * wal_pdev home channel info - * home_chan_mhz_flags: - * primary channel frequency in mhz - * (WMI_PDEV_STATS_HOME_CHAN_MHZ_SET,GET) - * flags to specify other channel attributes - * (WMI_PDEV_STATS_HOME_CHAN_FLAGS_SET, GET) - */ - A_UINT32 opaque_debug_home_chan_mhz_flags; - /** home channel center frequency in MHz */ - A_UINT32 opaque_debug_home_band_center_freq; - /** home channel phy_mode, refer enum WLAN_PHY_MODE */ - A_UINT32 opaque_debug_home_phy_mode; - /** This word contains the following bitfields: - * wal_pdev current channel info - * cur_chan_mhz_flags: - * primary channel frequency in mhz - * (WMI_PDEV_STATS_CUR_CHAN_MHZ_SET,GET) - * flags to specify other channel attributes - * (WMI_PDEV_STATS_CUR_CHAN_FLAGS_SET,GET) - */ - A_UINT32 opaque_debug_cur_chan_mhz_flags; - /** current channel center frequency in MHz */ - A_UINT32 opaque_debug_cur_band_center_freq; - /** current channel phy_mode, refer enum WLAN_PHY_MODE */ - A_UINT32 opaque_debug_cur_phy_mode; - /* Beacon context info */ - A_UINT32 opaque_debug_bcn_q_num_bcns_queued_to_hw; - /** beacon queue AIFS */ - A_UINT32 opaque_debug_aifs; - /** beacon queue cwmin */ - A_UINT32 opaque_debug_cwmin; - /** beacon queue cwmax */ - A_UINT32 opaque_debug_cwmax; - /** FILS discovery period in TU */ - A_UINT32 opaque_debug_fils_period; - /** Beacon interval in TU */ - A_UINT32 opaque_debug_beacon_period; - A_UINT32 opaque_debug_staggered_beacon_intvl; - /** wal_pdev tx context, refer enum WAL_TX_CTXT_FLAGS */ - A_UINT32 opaque_debug_tx_ctxt_flags; - /** opaque_debug_burst_mode_pending_isr - * wal_pdev tx_ctxt fields - burst_mode refer enum WAL_TX_BURST_MODE - * and pending_isr_status count - */ - A_UINT32 opaque_debug_burst_mode_pending_isr; - /** max burst duration from ppdu duration in us */ - A_UINT32 opaque_debug_burst_dur; - /** counter for tx hw stuck */ - A_UINT32 opaque_debug_tx_hw_stuck_cnt; - /** counter for tx consecutive lifetime expiry */ - A_UINT32 opaque_debug_consecutive_lifetime_expiries; - /** wal_pdev rx context, refer enum WAL_RX_CTXT_FLAGS */ - A_UINT32 opaque_debug_rx_ctxt_flags; - /** wal_pdev fields in rx context for rx_suspend or resume count */ - A_UINT32 opaque_debug_rx_suspend_cnt; - A_UINT32 opaque_debug_rx_resume_cnt; - A_UINT32 opaque_debug_rx_pcie_suspend_cnt; - A_UINT32 opaque_debug_rx_pcie_resume_cnt; - /** This word contains the following bitfields: - * wal_pdev fields - * pdev paused - WMI_PDEV_STATS_PAUSED_SET,GET - * pdev suspend - WMI_PDEV_STATS_SUSPENDED_SET,GET - * cac_enabed - MI_PDEV_STATS_CAC_ENABLED_SET,GET - * monitor VAP present - WMI_PDEV_STATS_IS_MONITOR_TYPE_PRESENT_SET,GET - * beacon tx mode - WMI_PDEV_STATS_BCN_TX_MODE_SET,GET - * isTXsuspended - WMI_PDEV_STATS_IS_TXSUSPENDED_SET,GET - * isSCHEDsuspended - WMI_PDEV_STATS_IS_SCHEDSUSPENDED_SET,GET - * sched_algo_resume_needed - - * WMI_PDEV_STATS_SCHED_ALGO_RESUME_NEEDED_SET,GET - * abort_reason - WMI_PDEV_STATS_ABORT_REASON_SET,GET - * atf_cfg - WMI_PDEV_STATS_ATF_CONFIG_SET,GET - * Green AP TX chainmask valid- WMI_PDEV_STATS_GAP_TX_CH_MASK_VALID_SET,GET - * Green AP RX chainmask valid- WMI_PDEV_STATS_GAP_RX_CH_MASK_VALID_SET,GET - * Green AP Phy mode valid - WMI_PDEV_STATS_GAP_PHY_MODE_VALID_SET,GET - * burst_enable - WMI_PDEV_STATS_BURST_ENABLE_SET,GET - */ - A_UINT32 opaque_debug_wal_pdev_bitfield; - /** This word contains the following bitfields: - * gap_phy_mode_freq: - * When GreenAP is enabled, phy_mode (WMI_PDEV_STATS_GAP_PHY_MODE_SET,GET) - * and center freq(MHz) (WMI_PDEV_STATS_GAP_BAND_CENTER_FREQ1_SET,GET) - * in GAP context is displayed - */ - A_UINT32 opaque_debug_gap_phy_mode_freq; - /** - * The following 5 opaque_debug_reserved_field variables are provided - * purely for debugging by technicians who have outside knowledge of - * what kind of values the target has placed into these fields. - */ - A_UINT32 opaque_debug_reserved_field_1; - A_UINT32 opaque_debug_reserved_field_2; - A_UINT32 opaque_debug_reserved_field_3; - A_UINT32 opaque_debug_reserved_field_4; - A_UINT32 opaque_debug_reserved_field_5; - /** - * Upper 32 bits bitmap of pause ids for TIDs that are paused/unpaused - * based on module_id. - */ - A_UINT32 opaque_debug_vdev_all_tid_pause_bitmap_ext; - /** - * Upper 32 bits bitmap of pause ids for TIDs that are blocked/unblocked - * based on module_id. - */ - A_UINT32 opaque_debug_vdev_all_tid_block_bitmap_ext; + A_UINT32 opaque_debug_num_macs_phy_vdev_up_active; + /** refer wlan_pdev ic flags */ + A_UINT32 opaque_debug_ic_flags; + /** vdev_id that are paused per pdev */ + A_UINT32 opaque_debug_paused_ap_vdev_bitmap; + /** opaque_debug_flags: + * refer to WLAN_PS_DESC_BIN_HWM_HIT or WLAN_PS_DESC_BIN_LWM_HIT + */ + A_UINT32 opaque_debug_flags; + /** wlan_pdev fields remote_peer_cnt, max_rf_chains_2G and max_rf_chains_5G + * remote_peer_cnt_max_rf_chains_2G_5G: + * This word contains the following bitfields: + * max chains supported in the 2.4 GHz band + * (WMI_PDEV_STATS_MAX_RF_CHAIN_2G_SET,GET) + * max chains supported in the 5 GHz band, + * (WMI_PDEV_STATS_MAX_RF_CHAIN_5G_SET,GET) + * number of remote peers + * (WMI_PDEV_STATS_REMOTE_PEER_CNT_SET,GET) + */ + A_UINT32 opaque_debug_remote_peer_cnt_max_rf_chains_2G_5G; + /** wlan_pdev max HT Capability info, WMI_HT_CAP defines */ + A_UINT32 opaque_debug_max_ht_cap_info; + /** wlan_pdev max VHT capability info, WMI_VHT_CAP defines */ + A_UINT32 opaque_debug_max_vht_cap_info; + /** opaque_debug_max_vht_supp_mcs: + * wlan_pdev max VHT Supported MCS which is + * vht_supp_mcs_2G or vht_supp_mcs_5G + */ + A_UINT32 opaque_debug_max_vht_supp_mcs; + /** wlan_pdev max HE capability info, WMI_HE_CAP defines */ + A_UINT32 opaque_debug_max_he_cap_info; + A_UINT32 opaque_debug_max_he_cap_info_ext; + /** the nominal chain mask for transmit */ + A_UINT32 opaque_debug_tx_chain_mask; + /** the nominal chain mask for receive */ + A_UINT32 opaque_debug_rx_chain_mask; + /** opaque_debug_ema_flags: + * This word contains the following bitfields: + * ema_flags: ema_max_vap_cnt and ema_max_profile_period from wlan_pdev + * ema_max_vap_cnt- number of maximum EMA Tx vaps (VAPs having both + * VDEV_FLAGS_EMA_MODE and VDEV_FLAGS_TRANSMIT_AP set) + * (WMI_PDEV_STATS_EMA_MAX_VAP_CNT_SET,GET) + * ema_max_profile_period - maximum profile periodicity + * (maximum number of beacons after which VAP profiles repeat) + * for any EMA VAP on any pdev. + * (WMI_PDEV_STATS_EMA_MAX_PROFILE_PERIOD_SET,GET) + */ + A_UINT32 opaque_debug_ema_flags; + /** wlan_pdev - maximum ML peers supported */ + A_UINT32 opaque_debug_num_ml_peer_entries; + /** This word contains the following bitfields: + * wlan_pdev fields - num_max_hw_links, current_chip_id and max_num_chips + * (related to MLO) + * Max number of HW links + * (WMI_PDEV_STATS_NUM_MAX_HW_LINKS_SET,GET) + * Current Chip Id + * (WMI_PDEV_STATS_CURRENT_CHIP_ID_SET,GET) + * Max number of chips + * (WMI_PDEV_STATS_MAX_NUM_CHIPS_SET,GET) + */ + A_UINT32 opaque_debug_mlo_flags; + /** Indicate beacon size in bytes */ + A_UINT32 opaque_debug_large_bcn_size; + /** proposed by the host value of MSDUQs per each LinkView peer's TID */ + A_UINT32 opaque_debug_num_of_linkview_msduqs_per_tid; + /** bcn_filter_context variables */ + A_UINT32 opaque_debug_bcns_dropped; + A_UINT32 opaque_debug_bcns_recvd; + A_UINT32 opaque_debug_bcns_delivered; + /** Tids that are paused/unpaused based on module_id */ + A_UINT32 opaque_debug_vdev_all_tid_pause_bitmap; + /** Tids that are blocked/unblocked based on module_id */ + A_UINT32 opaque_debug_vdev_all_tid_block_bitmap; + /** wal_pdev rx filter, WAL_RX_FILTER_FLAGS defines */ + A_UINT32 opaque_debug_rx_filter; + /** This word contains the following bitfields: + * aggr_nonaggr_retry_th: + * wal_pdev fields - agg_retry_th and non_agg_retry_th + * This value holds max retry threshold up to which a Data packet + * will be retried when ack is not received. + * agg_retry_th - Threshold value used when aggregation is enabled + * (WMI_PDEV_STATS_AGG_RETRY_TH_SET,GET) + * non_agg_retry_th - Threshold value used for non-aggregation. + * (WMI_PDEV_STATS_NON_AGG_RETRY_TH_SET) + */ + A_UINT32 opaque_debug_aggr_nonaggr_retry_th; + /** This word contains the following bitfields: + * num_max_rx_ba_sessions: + * Number of rx BA session establised + * (WMI_PDEV_STATS_NUM_RX_BA_SESSIONS_SET,GET) + * Max number of rx BA session from wal_pdev + * (WMI_PDEV_STATS_MAX_RX_BA_SESSIONS_SET,GET) + */ + A_UINT32 opaque_debug_num_max_rx_ba_sessions; + /** It holds WHAL_CHANNEL_SWITCH_FLAGS values */ + A_UINT32 opaque_debug_chan_switch_flags; + /** reset_cause holds PDEV_RESET_CONSEC_FAILURE or PDEV_RESET_TXQ_TIMEOUT */ + A_UINT32 opaque_debug_consecutive_failure_reset_cause; + /** PPDU duration limit, in us */ + A_UINT32 opaque_debug_mu_ppdu_dur_limit_us; + /** pdev reset in progress */ + A_UINT32 opaque_debug_reset_in_progress; + /** wal_dev - vdev_migrate_state refer to WAL_VDEV_MIGRATE_STATE */ + A_UINT32 opaque_debug_vdev_migrate_state; + /** opaque_debug_rts_rc_flag: + * wal_pdev rts ratecode - this value reflects whatever + * WMI_PDEV_PARAM_RTS_FIXED_RATE value the host has specified for the pdev. + */ + A_UINT32 opaque_debug_rts_rc_flag; + /* Num of peer delete in progress */ + A_UINT32 opaque_debug_num_of_peer_delete_in_progress; + /** wal_pdev total number of active vdev count */ + A_UINT32 opaque_debug_total_active_vdev_cnt; + /** wal_pdev - max number of vdevs per pdev */ + A_UINT32 opaque_debug_max_vdevs; + /* NonOccupancyList(NOL) context */ + A_UINT32 opaque_debug_dfs_nol_count; + /** NOL timeout in seconds */ + A_UINT32 opaque_debug_dfs_nol_timeout; + A_UINT32 opaque_debug_dfs_use_nol; + /** channel availability check mode, refer enum WMI_ADFS_OCAC_MODE */ + A_UINT32 opaque_debug_cac_mode; + A_UINT32 opaque_debug_dyn_ppdu_dur; /* in ms */ + /** This word contains the following bitfields: + * wal_pdev home channel info + * home_chan_mhz_flags: + * primary channel frequency in mhz + * (WMI_PDEV_STATS_HOME_CHAN_MHZ_SET,GET) + * flags to specify other channel attributes + * (WMI_PDEV_STATS_HOME_CHAN_FLAGS_SET, GET) + */ + A_UINT32 opaque_debug_home_chan_mhz_flags; + /** home channel center frequency in MHz */ + A_UINT32 opaque_debug_home_band_center_freq; + /** home channel phy_mode, refer enum WLAN_PHY_MODE */ + A_UINT32 opaque_debug_home_phy_mode; + /** This word contains the following bitfields: + * wal_pdev current channel info + * cur_chan_mhz_flags: + * primary channel frequency in mhz + * (WMI_PDEV_STATS_CUR_CHAN_MHZ_SET,GET) + * flags to specify other channel attributes + * (WMI_PDEV_STATS_CUR_CHAN_FLAGS_SET,GET) + */ + A_UINT32 opaque_debug_cur_chan_mhz_flags; + /** current channel center frequency in MHz */ + A_UINT32 opaque_debug_cur_band_center_freq; + /** current channel phy_mode, refer enum WLAN_PHY_MODE */ + A_UINT32 opaque_debug_cur_phy_mode; + /* Beacon context info */ + A_UINT32 opaque_debug_bcn_q_num_bcns_queued_to_hw; + /** beacon queue AIFS */ + A_UINT32 opaque_debug_aifs; + /** beacon queue cwmin */ + A_UINT32 opaque_debug_cwmin; + /** beacon queue cwmax */ + A_UINT32 opaque_debug_cwmax; + /** FILS discovery period in TU */ + A_UINT32 opaque_debug_fils_period; + /** Beacon interval in TU */ + A_UINT32 opaque_debug_beacon_period; + A_UINT32 opaque_debug_staggered_beacon_intvl; + /** wal_pdev tx context, refer enum WAL_TX_CTXT_FLAGS */ + A_UINT32 opaque_debug_tx_ctxt_flags; + /** opaque_debug_burst_mode_pending_isr + * wal_pdev tx_ctxt fields - burst_mode refer enum WAL_TX_BURST_MODE + * and pending_isr_status count + */ + A_UINT32 opaque_debug_burst_mode_pending_isr; + /** max burst duration from ppdu duration in us */ + A_UINT32 opaque_debug_burst_dur; + /** counter for tx hw stuck */ + A_UINT32 opaque_debug_tx_hw_stuck_cnt; + /** counter for tx consecutive lifetime expiry */ + A_UINT32 opaque_debug_consecutive_lifetime_expiries; + /** wal_pdev rx context, refer enum WAL_RX_CTXT_FLAGS */ + A_UINT32 opaque_debug_rx_ctxt_flags; + /** wal_pdev fields in rx context for rx_suspend or resume count */ + A_UINT32 opaque_debug_rx_suspend_cnt; + A_UINT32 opaque_debug_rx_resume_cnt; + A_UINT32 opaque_debug_rx_pcie_suspend_cnt; + A_UINT32 opaque_debug_rx_pcie_resume_cnt; + /** This word contains the following bitfields: + * wal_pdev fields + * pdev paused - WMI_PDEV_STATS_PAUSED_SET,GET + * pdev suspend - WMI_PDEV_STATS_SUSPENDED_SET,GET + * cac_enabed - MI_PDEV_STATS_CAC_ENABLED_SET,GET + * monitor VAP present - WMI_PDEV_STATS_IS_MONITOR_TYPE_PRESENT_SET,GET + * beacon tx mode - WMI_PDEV_STATS_BCN_TX_MODE_SET,GET + * isTXsuspended - WMI_PDEV_STATS_IS_TXSUSPENDED_SET,GET + * isSCHEDsuspended - WMI_PDEV_STATS_IS_SCHEDSUSPENDED_SET,GET + * sched_algo_resume_needed - + * WMI_PDEV_STATS_SCHED_ALGO_RESUME_NEEDED_SET,GET + * abort_reason - WMI_PDEV_STATS_ABORT_REASON_SET,GET + * atf_cfg - WMI_PDEV_STATS_ATF_CONFIG_SET,GET + * Green AP TX chainmask valid - WMI_PDEV_STATS_GAP_TX_CH_MASK_VALID_SET,GET + * Green AP RX chainmask valid - WMI_PDEV_STATS_GAP_RX_CH_MASK_VALID_SET,GET + * Green AP Phy mode valid - WMI_PDEV_STATS_GAP_PHY_MODE_VALID_SET,GET + * burst_enable - WMI_PDEV_STATS_BURST_ENABLE_SET,GET + */ + A_UINT32 opaque_debug_wal_pdev_bitfield; + /** This word contains the following bitfields: + * gap_phy_mode_freq: + * When GreenAP is enabled, phy_mode (WMI_PDEV_STATS_GAP_PHY_MODE_SET,GET) + * and center freq(MHz) (WMI_PDEV_STATS_GAP_BAND_CENTER_FREQ1_SET,GET) + * in GAP context is displayed + */ + A_UINT32 opaque_debug_gap_phy_mode_freq; + /** + * The following 5 opaque_debug_reserved_field variables are provided + * purely for debugging by technicians who have outside knowledge of + * what kind of values the target has placed into these fields. + */ + A_UINT32 opaque_debug_reserved_field_1; + A_UINT32 opaque_debug_reserved_field_2; + A_UINT32 opaque_debug_reserved_field_3; + A_UINT32 opaque_debug_reserved_field_4; + A_UINT32 opaque_debug_reserved_field_5; } wmi_ctrl_path_pdev_stats_struct; #define WMI_PDEV_STATS_NUM_MACS_GET(flag) \ @@ -14544,7 +13444,6 @@ typedef enum { WMI_CTRL_PATH_STATS_CAL_TYPE_PADROOP = 0x17, WMI_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC = 0x18, WMI_CTRL_PATH_STATS_CAL_TYPE_RXSPUR = 0x19, - WMI_CTRL_PATH_STATS_CAL_TYPE_PDADC = 0x1a, /* add new cal types above this line */ WMI_CTRL_PATH_STATS_CAL_TYPE_INVALID = 0xFF @@ -14644,7 +13543,6 @@ static INLINE A_UINT8 *wmi_ctrl_path_cal_type_id_to_name(A_UINT32 cal_type_id) WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_CAL_TYPE_PADROOP); WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC); WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_CAL_TYPE_RXSPUR); - WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_CAL_TYPE_PDADC); } return (A_UINT8 *) "WMI_CTRL_PATH_STATS_CAL_TYPE_UNKNOWN"; @@ -15026,11 +13924,6 @@ typedef struct { * Proxy mode AFC-Response payload clear count */ A_UINT32 payload_clear_count; - - /* - * payload parsing failure count due to platform memory alloc failure - */ - A_UINT32 payload_parser_mem_alloc_failure_count; } wmi_ctrl_path_afc_stats_struct; /* AT - Airtime */ @@ -15471,28 +14364,28 @@ typedef struct { */ A_UINT32 opaque_debug_keyid0_ast_index; /* opaque_debug_all_tids_block_module_bitmap: - * Lower 32 bits bitmap of block IDs requesting block of all TIDs, + * Bitmap of block IDs requesting block of all TIDs, * part of wal_peer. * Refer to enum WLAN_PAUSE_ID. * This block/pause ID can be mapped to a WLAN_MODULE_ID module ID. */ A_UINT32 opaque_debug_all_tids_block_module_bitmap; /* opaque_debug_all_tids_pause_module_bitmap: - * Lower 32 bits bitmap of pause IDs requesting block of all TIDs, + * Bitmap of pause IDs requesting block of all TIDs, * part of wal_peer. * Refer to enum WLAN_PAUSE_ID. * This pause ID can be mapped to a WLAN_MODULE_ID module ID. */ A_UINT32 opaque_debug_all_tids_pause_module_bitmap; /* opaque_debug_data_tids_block_module_bitmap: - * Lower 32 bits bitmap of block ids requesting block of data tids, + * Bitmap of block ids requesting block of data tids, * part of wal_peer. * Refer to enum WLAN_PAUSE_ID. * This block/pause ID can be mapped to a WLAN_MODULE_ID module ID. */ A_UINT32 opaque_debug_data_tids_block_module_bitmap; /* opaque_debug_data_tids_pause_module_bitmap: - * Lower 32 bits bitmap of pause ids requesting block of data tids, + * Bitmap of pause ids requesting block of data tids, * part of wal_peer. * Refer to enum WLAN_PAUSE_ID. * This pause ID can be mapped to a WLAN_MODULE_ID module ID. @@ -15885,49 +14778,6 @@ typedef struct { A_UINT32 opaque_debug_field_2; A_UINT32 opaque_debug_field_3; A_UINT32 opaque_debug_field_4; - - /* ba_stats - * This word contains the following bitfields: - * bits 15:0 - ba_tx_neg_fail: Blockack Transmit Negotiation failure - * count for the all TIDs in peer. - * Use WMI_PEER_STATS_BA_TX_NEG_FAIL_SET,GET macros. - * bits 31:16 - reserved - */ - union { - A_UINT32 ba_stats__word; - struct { - A_UINT32 ba_tx_neg_fail: 16, - reserved: 16; - }; - }; - /* opaque_debug_all_tids_block_module_bitmap_ext: - * Upper 32 bits bitmap of block IDs requesting block of all TIDs, - * part of wal_peer. - * Refer to enum WLAN_PAUSE_ID. - * This block/pause ID can be mapped to a WLAN_MODULE_ID module ID. - */ - A_UINT32 opaque_debug_all_tids_block_module_bitmap_ext; - /* opaque_debug_all_tids_pause_module_bitmap_ext: - * Upper 32 bits bitmap of pause IDs requesting pause of all TIDs, - * part of wal_peer. - * Refer to enum WLAN_PAUSE_ID. - * This pause ID can be mapped to a WLAN_MODULE_ID module ID. - */ - A_UINT32 opaque_debug_all_tids_pause_module_bitmap_ext; - /* opaque_debug_data_tids_block_module_bitmap_ext: - * Upper 32 bits bitmap of block ids requesting block of data tids, - * part of wal_peer. - * Refer to enum WLAN_PAUSE_ID. - * This block/pause ID can be mapped to a WLAN_MODULE_ID module ID. - */ - A_UINT32 opaque_debug_data_tids_block_module_bitmap_ext; - /* opaque_debug_data_tids_pause_module_bitmap_ext: - * Upper 32 bits bitmap of pause ids requesting pause of data tids, - * part of wal_peer. - * Refer to enum WLAN_PAUSE_ID. - * This pause ID can be mapped to a WLAN_MODULE_ID module ID. - */ - A_UINT32 opaque_debug_data_tids_pause_module_bitmap_ext; } wmi_ctrl_path_peer_stats_struct; #define WMI_PEER_STATS_SM_MASK_SET(flag, val) \ @@ -16252,12 +15102,6 @@ typedef struct { #define WMI_PEER_STATS_RC_CHAN_FREQ_GET(flag) \ WMI_GET_BITS(flag, 16, 16) -#define WMI_PEER_STATS_PEER_BA_TX_NEG_FAIL_SET(flag, val) \ - WMI_SET_BITS(flag, 0, 16, val) -#define WMI_PEER_STATS_PEER_BA_TX_NEG_FAIL_GET(flag) \ - WMI_GET_BITS(flag, 0, 16) -/* bits 31:16 unused/reserved */ - typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_cfr_stats_struct */ @@ -16368,109 +15212,6 @@ typedef struct { */ } wmi_radio_chan_stats_event_fixed_param; -typedef enum { - WMI_TDLS_CHANNEL_SWITCH_FRAME_TX_RX = 0x0, - WMI_TDLS_BT_COEX_INDICATION = 0x1, -} wmi_tdls_connect_info_stats_reason_code; - -typedef enum { - WMI_TDLS_FRAME_SUBTYPE_REQUEST = 0x0, - WMI_TDLS_FRAME_SUBTYPE_RESPONSE = 0x1, -} wmi_tdls_connect_info_stats_subtype; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_tdls_connect_info_stats */ - A_UINT32 tlv_header; - /* type: - * Type of frame sent to the Peer, will be having value 4, - * i.e TDLS State change - */ - A_UINT32 type; - /* subtype: - * SubType of frame sent to the Peer, eg. req/resp, - * Takes values from enum wmi_tdls_connect_info_stats_subtype. - */ - A_UINT32 subtype; - /* status: - * Completion status of this frame, required only for Tx frames - * to know if frame is sent out successfully - * 0 - status is success - * 1 - status is failure - */ - A_UINT32 status; - /* reason_code: - * Reason code for the reason of sending this TLV, eg. for TDLS - * channel switch req/resp or for BT running indication - * Takes values from enum wmi_tdls_connect_info_stats_reason_code. - */ - A_UINT32 reason_code; - /* tx_rx: - * Indicates whether we are sender or receiver of this frame, - * 1 value means Tx, 0 value means Rx. - */ - A_UINT32 tx_rx; - /* Current operating channel frequency */ - A_UINT32 op_freq_mhz; - /* Peer MAC address for which this stats is being logged */ - wmi_mac_addr peer_mac_addr; - /* The timestamp at which the WMI event is reported. */ - A_UINT32 timestamp; - /* Last known RSSI */ - A_INT32 rssi; /* dBm units */ - /* Peer Dialog token */ - A_UINT32 peer_dialog_token; -} wmi_tdls_connect_info_stats; - -/* max MCS counters supported for enhance stats */ -#define WMI_ENHANCE_STATS_MAX_MCS_COUNTERS 16 - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_tdls_data_stats */ - A_UINT32 tlv_header; - /* Current operating channel frequency */ - A_UINT32 op_freq_mhz; - /* Peer MAC address for which this stats is being logged */ - wmi_mac_addr peer_mac_addr; - /* The timestamp at which the WMI event is reported. */ - A_UINT32 timestamp; - /* Last known RSSI */ - A_INT32 rssi; /* dBm units */ - /* Last Tx Data rate */ - A_UINT32 data_rate; - /* tx_ppdus_cumulative: - * Total PPDUs Tx-ed combining all the MCS rates over the last 15 secs - */ - A_UINT32 tx_ppdus_cumulative; - /* tx_mcs_data_ppdu: - * PPDUs Txed over each MCS rate for all the supported MCS - * over the last 15 secs - */ - A_UINT32 tx_mcs_data_ppdu[WMI_ENHANCE_STATS_MAX_MCS_COUNTERS]; - /* Total PPDU Tx failures seen over the last 15 secs */ - A_UINT32 tx_ppdu_failures; - /* Total PPDUs Rx-ed combining all the MCS rates over the last 15 secs */ - A_UINT32 rx_ppdus_cumulative; - /* rx_mcs_data_ppdu: - * PPDUs Rxed over each MCS rate for all the supported MCS - * over the last 15 secs - */ - A_UINT32 rx_mcs_data_ppdu[WMI_ENHANCE_STATS_MAX_MCS_COUNTERS]; - /* Total Rx PPDU failures seen over the last 15 secs */ - A_UINT32 rx_ppdu_failures; -} wmi_tdls_data_stats; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_tdls_stats_event_fixed_param */ - A_UINT32 tlv_header; - /** VDEV identifier */ - A_UINT32 vdev_id; - /* Total TDLS Peers this VDEV is connected to */ - A_UINT32 peer_cnt; -} wmi_tdls_stats_event_fixed_param; - /** * PDEV statistics * @@ -16557,11 +15298,6 @@ typedef struct { * (end of packet) */ A_UINT32 rx_other_11ax_msdu_cnt; - /* pending_mpdu_msdus: - * count of the pending MPDUs + MSDUs for all TIDs within all peers - * for all the vdev under the specified pdev - */ - A_UINT32 pending_mpdu_msdus; } wmi_pdev_extd_stats; /** @@ -16590,30 +15326,6 @@ typedef struct{ A_UINT32 estimated_air_time_per_ac; } wmi_pdev_telemetry_stats; - -#define WMI_MAX_BCN_HISTORY 10 /* max beacon history entry */ - -typedef struct { - /* Beacon real RSSI, non-averaged rssi, dBm units; -128 means invalid */ - A_INT32 bcn_rssi; - /* Beacon tsf, 0 means invalid */ - A_UINT32 bcn_tsf; - /* NOTE: - * Due to backwards-compatibility requirements, no new fields - * can be added to this struct. - */ -} wmi_bcn_his_info; - -typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_recv_bcn_stats */ - A_UINT32 tlv_header; - /* Vdev id */ - A_UINT32 vdev_id; - /* Received History of last ten Beacon of the connected Bss */ - wmi_bcn_his_info bcn_history[WMI_MAX_BCN_HISTORY]; -} wmi_recv_bcn_stats; - - /** * VDEV statistics * @todo @@ -16654,16 +15366,6 @@ typedef struct { A_UINT32 tx_bcn_outage_cnt; /* Total number of failed beacons */ } wmi_bcn_stats; -/* - * pdev coex stats - */ -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_coex_stats */ - A_UINT32 pdev_id; - A_UINT32 cur_btc_mode; /* 0 - TDD; 1 - FDD; 2 - Hybrid; 3 - DBAM */ - A_UINT32 cur_btc_policy; /* 0 - FR; */ -} wmi_pdev_coex_stats; - #define WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_BIT 0 #define WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_MASK \ (1 << WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_BIT) @@ -16672,10 +15374,6 @@ typedef struct { #define WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE_MASK \ (1 << WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE_BIT) -#define WMI_VDEV_STATS_FLAGS_CHANNEL_STATS_PRESENT_BIT 2 -#define WMI_VDEV_STATS_FLAGS_CHANNEL_STATS_PRESENT_MASK \ - (1 << WMI_VDEV_STATS_FLAGS_CHANNEL_STATS_PRESENT_BIT) - /** * vdev extension statistics */ @@ -16698,34 +15396,10 @@ typedef struct { * 1: the "is link active" flag is valid * bit 1: WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE, * 1:link_active; 0:link_inactive - * bit 2: WMI_VDEV_STATS_FLAGS_CHANNEL_STATS_PRESENT, - * 0: new stats fields are not present. - * 1: new rx/tx/on/cca time stats fields present; * Refer to WMI_VDEV_STATS_FLAGS_ defs. */ A_UINT32 flags; A_INT32 vdev_tx_power; /* dBm units */ - /** rx_time: - * How many msecs vdev is in active receive on channel - * (32 bits number accruing over time) - */ - A_UINT32 rx_time; - /** tx_time: - * How many msecs vdev is transmitting on channel - * (32 bits number accruing over time) - */ - A_UINT32 tx_time; - /** on_time: - * How many msecs vdev is awake on channel - * (32 bits number accruing over time) - */ - A_UINT32 on_time; - /** cca_time: - * How many msecs vdev is CCA busy on channel - * (32 bits number accruing over time) - * Includes rx_time but not tx_time. - */ - A_UINT32 cca_time; } wmi_vdev_extd_stats; /** @@ -16820,15 +15494,9 @@ typedef struct { A_UINT32 opaque_debug_rx_pkt_on_channel; /* Contains the value of Target beacon transmission time offset value */ A_UINT32 opaque_debug_tbtt_offset; - /* - * Contains the value of lower 32 bits of tid pause bitmap of the peer - * from wal_vdev - */ + /* Contains the value of tid pause bitmap of the peer from wal_vdev */ A_UINT32 opaque_debug_peer_all_tid_pause_bitmap; - /* - * Contains the value of lower 32 bits of tid block bitmap of the peer - * from wal_vdev - */ + /* Contains the value of tid block bitmap of the peer from wal_vdev */ A_UINT32 opaque_debug_peer_all_tid_block_bitmap; /* Contains the value of tdls peer kickout threshold */ A_UINT32 opaque_debug_tdls_peer_kickout_th; @@ -17182,16 +15850,6 @@ typedef struct { A_UINT32 opaque_debug_field_2; A_UINT32 opaque_debug_field_3; A_UINT32 opaque_debug_field_4; - /* - * Contains the value of upper 32 bits tid pause bitmap of the peer - * from wal_vdev - */ - A_UINT32 opaque_debug_peer_all_tid_pause_bitmap_ext; - /* - * Contains the value of upper 32 bits tid block bitmap of the peer - * from wal_vdev - */ - A_UINT32 opaque_debug_peer_all_tid_block_bitmap_ext; } wmi_ctrl_path_vdev_stats_struct; @@ -17937,40 +16595,6 @@ typedef struct { A_UINT32 dot11RTSFailureCount; } wmi_ctrl_path_sta_rrm_stats_struct; -typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_sta_dar_stats_struct */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - A_UINT32 stats_granularity; /* Possible values are listed in wmi_ctrl_path_stats_granularity enum. */ - /* transmit_pwr: - * Units are dB w.r.t. a -20 dBm reference. - * For example, if the STA's tx power is 10 dBm, the transmit_pwr field's - * value will be 30. - */ - A_UINT32 transmit_pwr; - A_UINT32 cca_busy_cnt; - A_UINT32 cycle_cnt; - /* - * For the below 8-element arrays, in case of AC-level granularity, - * only the first 4 elements of the array are populated, and are indexed - * by wmi_traffic_ac enum values. - * Otherwise, for TID level granularity all 8 elements of the array will - * be filled by FW, and are indexed by the TID value. - */ - A_UINT32 success_mpdu_tx_cnt[8]; - A_UINT32 dropped_mpdu_tx_cnt[8]; - A_UINT32 rts_success_cnt[8]; - A_UINT32 rts_fail_cnt[8]; - A_UINT32 fcs_fail_cnt[8]; /* number of rx MPDUs whose FCS check failed */ - /* ack_fail_cnt: - * number of tx MPDUs nacked within a block ack, - * or for which no block ack was received. - */ - A_UINT32 ack_fail_cnt[8]; - A_UINT32 ba_nego_fail_cnt; - A_UINT32 beacon_loss_cnt; -} wmi_ctrl_path_sta_dar_stats_struct; - typedef struct { /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_vdev_bcn_stats_struct */ A_UINT32 tlv_header; @@ -18314,61 +16938,6 @@ typedef struct { #define WMI_SCAN_MODE_VDEV_FLAG_ENABLED(flag) ((flag & VDEV_FLAGS_SCAN_MODE_VAP) ? 1 : 0) - -#define WMI_VDEV_START_SMD_FLAGS_GET_ROAM_ENABLED(mlo_flags) WMI_GET_BITS(mlo_flags, 0, 1) -#define WMI_VDEV_START_SMD_FLAGS_SET_ROAM_ENABLED(mlo_flags, value) WMI_SET_BITS(mlo_flags, 0, 1, value) -#define WMI_VDEV_START_SMD_FLAGS_GET_DL_DATA_FORWARDING(mlo_flags) WMI_GET_BITS(mlo_flags, 1, 1) -#define WMI_VDEV_START_SMD_FLAGS_SET_DL_DATA_FORWARDING(mlo_flags, value) WMI_SET_BITS(mlo_flags, 1, 1, value) -#define WMI_VDEV_START_SMD_FLAGS_GET_UL_DATA_FORWARDING(mlo_flags) WMI_GET_BITS(mlo_flags, 2, 1) -#define WMI_VDEV_START_SMD_FLAGS_SET_UL_DATA_FORWARDING(mlo_flags, value) WMI_SET_BITS(mlo_flags, 2, 1, value) -#define WMI_VDEV_START_SMD_FLAGS_GET_PTK_MODE(mlo_flags) WMI_GET_BITS(mlo_flags, 3, 1) -#define WMI_VDEV_START_SMD_FLAGS_SET_PTK_MODE(mlo_flags, value) WMI_SET_BITS(mlo_flags, 3, 1, value) - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len;tag equals WMITLV_TAG_STRUC_wmi_vdev_start_smd_params*/ - /** MLD MAC address */ - wmi_mac_addr smd_macaddr; - union { - struct { - A_UINT32 roam_enabled :1, - dl_data_forwarding :1, - ul_data_forwarding :1, - ptk_mode :1, - reserved :28; - }; - A_UINT32 smd_flags; - }; -} wmi_vdev_start_smd_params; - - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len;tag equals WMITLV_TAG_STRUC_wmi_vdev_start_uhr_config*/ - union { - struct { - A_UINT32 advance_notification_interval : 8, - post_notification_interval : 8, - critical_update_indication_interval : 8, - reserved : 8; - }; - A_UINT32 uhr_cu_intervals; - }; -} wmi_vdev_start_uhr_config; - -#define WMI_VDEV_START_UHR_GET_ADVANCE_NOTIFICATION_INTERVAL(uhr_cu_intervals) \ - WMI_GET_BITS(uhr_cu_intervals, 0, 8) -#define WMI_VDEV_START_UHR_SET_ADVANCE_NOTIFICATION_INTERVAL(uhr_cu_intervals, val) \ - WMI_SET_BITS(uhr_cu_intervals, 0, 8, _val) - -#define WMI_VDEV_START_UHR_GET_POST_NOTIFICATION_INTERVAL(uhr_cu_intervals) \ - WMI_GET_BITS(uhr_cu_intervals, 8, 8) -#define WMI_VDEV_START_UHR_SET_POST_NOTIFICATION_INTERVAL(uhr_cu_intervals, val) \ - WMI_SET_BITS(uhr_cu_intervals, 8, 8, _val) - -#define WMI_VDEV_START_UHR_GET_CRITICAL_UPDATE_INDICATION_INTERVAL(uhr_cu_intervals) \ - WMI_GET_BITS(uhr_cu_intervals, 16, 8) -#define WMI_VDEV_START_UHR_SET_CRITICAL_UPDATE_INDICATION_INTERVAL(uhr_cu_intervals, val) \ - WMI_SET_BITS(uhr_cu_intervals, 16, 8, _val) - typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_create_cmd_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ @@ -18403,16 +16972,6 @@ typedef struct { * vdev_stats_id_valid field is non-zero. */ A_UINT32 vdev_stats_id; - /** cfp_enable: indicate whether control frame protection is enabled */ - A_UINT32 cfp_enable; - /* - * VDEV ID that will be assigned for both legacy and MLD VAPs. - * This will be configured to rx_meta_data in the AST entry. - * This information will then be used by host to achieve intra-bss - * forwarding for the Rx packets. - */ - A_UINT32 global_vdev_id; - /* This TLV is followed by another TLV of array of structures * wmi_vdev_txrx_streams cfg_txrx_streams[]; * wmi_vdev_create_mlo_params mlo_params[0,1]; @@ -18491,8 +17050,6 @@ typedef struct { #define WMI_MLO_FLAGS_SET_IEEE_LINK_ID_VALID(mlo_flags, value) WMI_SET_BITS(mlo_flags, 18, 1, value) #define WMI_MLO_FLAGS_GET_IEEE_LINK_ID_VALID_PARTNER(mlo_flags) WMI_GET_BITS(mlo_flags, 19, 1) #define WMI_MLO_FLAGS_SET_IEEE_LINK_ID_VALID_PARTNER(mlo_flags, value) WMI_SET_BITS(mlo_flags, 19, 1, value) -#define WMI_MLO_FLAGS_GET_SINGLE_LINK_EMLSR_EN(mlo_flags) WMI_GET_BITS(mlo_flags, 20, 1) -#define WMI_MLO_FLAGS_SET_SINGLE_LINK_EMLSR_EN(mlo_flags, value) WMI_SET_BITS(mlo_flags, 20, 1, value) /* this structure used for passing MLO flags */ typedef struct { @@ -18524,8 +17081,7 @@ typedef struct { start_as_active:1, /* indicate link should be started in active status */ mlo_ieee_link_id_valid:1, /* indicate if the ieee_link_id in wmi_vdev_start_mlo_params is valid */ mlo_ieee_link_id_valid_partner:1, /* indicate if the ieee_link_id in wmi_partner_link_params is valid */ - single_link_emlsr_en:1, /* indicate if emlsr enablement on one link is supported */ - unused: 11; + unused: 12; }; A_UINT32 mlo_flags; }; @@ -18574,123 +17130,6 @@ typedef enum { } WMI_VDEV_CREATE_WFDR2_MODES; -/* - * This TLV structure is used to pass the offsets of each TBTT count down, - * pertaining to advance notification of any BSS parameter change, - * in the host allocated DDR memory, to which FW should copy the - * current count down. - */ -typedef struct { - A_UINT32 tlv_header; /** TLV tag (WMITLV_TAG_STRUC_wmi_vdev_create_tbtt_count_down_offset_info) and len */ - /** - * host_addr_lsb - LSB 32 bits of Host DDR physical address - * host_addr_msb - MSB 32 bits of Host DDR physical address - */ - A_UINT32 host_addr_lsb; - A_UINT32 host_addr_msb; - A_UINT32 size; /** Indicates the total bytes allocated for this VAP */ - /** - * offsets should always start from 1 as 0th offset shall be reserved for - * flags. - * A_UINT32[0] = EHT CU | UHR CU - * So if the below offset infos contain zero, FW shall assume they are - * invalid. - */ - /** offsets of CSA & QUIET count down */ - union { - struct { - A_UINT32 csa : 16, - quiet : 16; - }; - A_UINT32 offset_info_1; - }; - /** offsets of EHT BPCC & ML-RECONFIG count down */ - union { - struct { - A_UINT32 eht_bpcc : 16, - reconfig : 16; - }; - A_UINT32 offset_info_2; - }; - /** - * offsets of TTLM Max Channel Switch Time & - * Expected Duration count down - */ - union { - struct { - A_UINT32 ttlm_max_chan_switch_time : 16, - ttlm_expected_duration : 16; - }; - A_UINT32 offset_info_3; - }; - /** offsets of UHR Param Update count down & EBPCC */ - union { - struct { - A_UINT32 uhr_param_update : 16, - uhr_ebpcc : 16; - }; - A_UINT32 offset_info_4; - }; - /** offsets of Max Channel Switch Timer */ - union { - struct { - A_UINT32 max_chan_switch_time : 16, - reserved_1 : 16; - }; - A_UINT32 offset_info_5; - }; -} wmi_vdev_create_tbtt_count_down_offset_info; - -/* offsets of CSA & Quiet count down */ -#define WMI_TBTT_COUNT_DOWN_OFFSET_CSA_GET(offset_info_1) \ - WMI_GET_BITS(offset_info_1, 0, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_CSA_SET(offset_info_1, value) \ - WMI_SET_BITS(offset_info_1, 0, 16, value) - -#define WMI_TBTT_COUNT_DOWN_OFFSET_QUIET_GET(offset_info_1) \ - WMI_GET_BITS(offset_info_1, 16, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_QUIET_SET(offset_info_1, value) \ - WMI_SET_BITS(offset_info_1, 16, 16, value) - -/* offsets of EHT BPCC & ML-RECONFIG count down */ -#define WMI_TBTT_COUNT_DOWN_OFFSET_EHT_BPCC_GET(offset_info_2) \ - WMI_GET_BITS(offset_info_2, 0, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_EHT_BPCC_SET(offset_info_2, value) \ - WMI_SET_BITS(offset_info_2, 0, 16, value) - -#define WMI_TBTT_COUNT_DOWN_OFFSET_RECONFIG_GET(offset_info_2) \ - WMI_GET_BITS(offset_info_2, 16, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_RECONFIG_SET(offset_info_2, value) \ - WMI_SET_BITS(offset_info_2, 16, 16, value) - -/* offsets of TTLM Max Channel Switch Time & Expected Duration count down */ -#define WMI_TBTT_COUNT_DOWN_OFFSET_TTLM_MAX_CHAN_SWITCH_TIME_GET(offset_info_3) \ - WMI_GET_BITS(offset_info_3, 0, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_TTLM_MAX_CHAN_SWITCH_TIME_SET(offset_info_3, value) \ - WMI_SET_BITS(offset_info_3, 0, 16, value) -#define WMI_TBTT_COUNT_DOWN_OFFSET_TTLM_EXPECTED_DURATION_GET(offset_info_3) \ - WMI_GET_BITS(offset_info_3, 16, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_TTLM_EXPECTED_DURATION_SET(offset_info_3, value) \ - WMI_SET_BITS(offset_info_3, 16, 16, value) - -/* offsets of UHR Param Update count down & EBPCC */ -#define WMI_TBTT_COUNT_DOWN_OFFSET_UHR_PARAM_UPDATE_GET(offset_info_4) \ - WMI_GET_BITS(offset_info_4, 0, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_UHR_PARAM_UPDATE_SET(offset_info_4, value) \ - WMI_SET_BITS(offset_info_4, 0, 16, value) - -#define WMI_TBTT_COUNT_DOWN_OFFSET_UHR_EBPCC_GET(offset_info_4) \ - WMI_GET_BITS(offset_info_4, 16, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_UHR_EBPCC_SET(offset_info_4, value) \ - WMI_SET_BITS(offset_info_4, 16, 16, value) - -/* offsets of Max Channel Switch Time */ -#define WMI_TBTT_COUNT_DOWN_OFFSET_MAX_CHAN_SWITCH_TIME_GET(offset_info_5) \ - WMI_GET_BITS(offset_info_5, 0, 16) -#define WMI_TBTT_COUNT_DOWN_OFFSET_MAX_CHAN_SWITCH_TIME_SET(offset_info_5, value) \ - WMI_SET_BITS(offset_info_5, 0, 16, value) - - /* this TLV structure used for pass mlo parameters on vdev start*/ typedef struct { A_UINT32 tlv_header; /** TLV tag and len; */ @@ -18701,7 +17140,6 @@ typedef struct { * mlo_ieee_link_id_valid bit set. */ A_UINT32 ieee_link_id; - A_UINT32 mlo_vdev_id; /* deprecated */ } wmi_vdev_start_mlo_params; /* this TLV structure used for passing mlo parameters on vdev stop */ @@ -18744,10 +17182,10 @@ typedef enum { } wmi_vdev_update_mac_addr_conf_status; /** values for vdev_type */ -#define WMI_VDEV_TYPE_AP 0x1 -#define WMI_VDEV_TYPE_STA 0x2 -#define WMI_VDEV_TYPE_IBSS 0x3 -#define WMI_VDEV_TYPE_MONITOR 0x4 +#define WMI_VDEV_TYPE_AP 0x1 +#define WMI_VDEV_TYPE_STA 0x2 +#define WMI_VDEV_TYPE_IBSS 0x3 +#define WMI_VDEV_TYPE_MONITOR 0x4 /** VDEV type is for social wifi interface.This VDEV is Currently mainly needed * by FW to execute the NAN specific WMI commands and also implement NAN specific @@ -18756,16 +17194,14 @@ typedef enum { * WMI command to create this VDEV once during initialization and host is not * expected to use any VDEV specific WMI commands on this VDEV. **/ -#define WMI_VDEV_TYPE_NAN 0x5 +#define WMI_VDEV_TYPE_NAN 0x5 -#define WMI_VDEV_TYPE_OCB 0x6 +#define WMI_VDEV_TYPE_OCB 0x6 /* NAN Data Interface */ -#define WMI_VDEV_TYPE_NDI 0x7 +#define WMI_VDEV_TYPE_NDI 0x7 -#define WMI_VDEV_TYPE_MESH_POINT 0x8 - -#define WMI_VDEV_TYPE_WIFI_PASSTHRU 0x9 +#define WMI_VDEV_TYPE_MESH_POINT 0x8 /* * Param values to be sent for WMI_VDEV_PARAM_SGI command @@ -19475,10 +17911,6 @@ typedef enum { #define WMI_HECAP_MAC_HTVHTTRIGRX_GET_D2(he_cap2) (0) #define WMI_HECAP_MAC_HTVHTTRIGRX_SET_D2(he_cap2, value) {;} -#define WMI_GET_HW_RATECODE_VERSION(_rcode) (((_rcode) >> 28) & 0x1) -#define WMI_SET_HW_RATECODE_VERSION_V1(_rcode) (((1) << 28) | (_rcode)) -#define WMI_GET_HW_RATECODE_GI_V1(_rcode) (((_rcode) >> 14) & 0x3) -#define WMI_GET_HW_RATECODE_BW_V1(_rcode) (((_rcode) >> 11) & 0x7) #define WMI_GET_HW_RATECODE_PREAM_V1(_rcode) (((_rcode) >> 8) & 0x7) #define WMI_GET_HW_RATECODE_NSS_V1(_rcode) (((_rcode) >> 5) & 0x7) #define WMI_GET_HW_RATECODE_RATE_V1(_rcode) (((_rcode) >> 0) & 0x1F) @@ -19544,9 +17976,6 @@ typedef struct { /* Target TSF value by which VDEV restart procedure should be completed in FW */ A_UINT32 target_tsf_us_lo; /* bits 31:0 */ A_UINT32 target_tsf_us_hi; /* bits 63:32 */ - A_UINT32 vdev_op_ul_nss; /* vdev operating uplink nss. 1 ~ n: 1ss ~ nss */ - A_UINT32 vdev_op_dl_nss; /* vdev operating downlink nss. 1 ~ n: 1ss ~ nss */ - A_UINT32 uhr_ops; /* refer to WMI_UHR_OPS_XXX macros */ /* The TLVs follows this structure: * wmi_channel chan; <-- WMI channel @@ -19561,12 +17990,6 @@ typedef struct { * optional TLV for dbw_chan * wmi_dbw_chan_info dbw_chan_info * optional TLV used for dbw_chan_info - * wmi_vdev_start_smd_params smd_params; - * optional TLV used for SMD - * wmi_vdev_start_uhr_config uhr_config_info - * optional TLV used if VAP is 11BN - * wmi_uhr_ap_npca_params npca_params - * optional TLV used to update NPCA information */ } wmi_vdev_start_request_cmd_fixed_param; @@ -19610,18 +18033,8 @@ enum WMI_VDEV_UP_FLAGS { * Valid only for VBSS subtype vaps. */ WMI_VDEV_UP_FLAG_VBSS_PASSIVE = 0x00000004, - /** REDUCE_OFF_DIAGONAL_NULL_THR - * The flag will be set to reduce off diagonal nulling threshold. - */ - WMI_VDEV_UP_FLAG_REDUCE_OFF_DIAGONAL_NULL_THR = 0x00000008, }; -typedef struct{ - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_co_located_chan_info */ - /* co-located link frequency discovered on connected ap */ - A_UINT32 link_freq; /* MHz units */ -} wmi_co_located_chan_info; - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_up_cmdid_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ @@ -19638,10 +18051,6 @@ typedef struct { A_UINT32 profile_num; /** flags - this is a bitwise-or combination of WMI_VDEV_UP_FLAGS values */ A_UINT32 flags; - /* The below TLVs follow this struct: - * - wmi_co_located_chan_info co_located_chan_info[]; - * Connected AP's co-located channel info - */ } wmi_vdev_up_cmd_fixed_param; typedef struct { @@ -19766,7 +18175,6 @@ typedef enum { WMI_RATE_PREAMBLE_VHT, WMI_RATE_PREAMBLE_HE, WMI_RATE_PREAMBLE_EHT, - WMI_RATE_PREAMBLE_UHR, } WMI_RATE_PREAMBLE; /** Value to disable fixed rate setting */ @@ -19785,8 +18193,6 @@ typedef enum { #define WMI_VDEV_OCE_FILS_DISCOVERY_FRAME_FEATURE_BITMAP 0x10 #define WMI_VDEV_OCE_ESP_FEATURE_BITMAP 0x20 #define WMI_VDEV_OCE_REASSOC_REJECT_FEATURE_BITMAP 0x40 -/* Enable FILS Discovery frame transmission only for 6 GHz SAP */ -#define WMI_VDEV_OCE_FILS_DISCOVERY_FRAME_6G_ONLY_FEATURE_BITMAP 0x80 /** 6 GHZ params **/ /* Control to enable/disable beacon tx in non-HT duplicate */ @@ -20902,83 +19308,6 @@ typedef enum { */ WMI_VDEV_PARAM_CONNECT_EXT_FEATURES, /* 0xC7 */ - /* Allow to tear down TWT on scan start, if corresponding INI is set */ - WMI_VDEV_PARAM_DISABLE_SCAN_START_TWT, /* 0xC8 */ - - /* - * value 0 | default value no opp | controlled from pdev level - * value 1 | disable responder for this vdev - */ - WMI_VDEV_PARAM_TWT_RESP_DISABLE, /* 0xC9 */ - - /* - * Enable or disable 2xLDPC in Fixed rate UHR data packet transmissions. - * valid values: 0 - Disable 2xLDPC, 1 - Enable 2xLDPC. - */ - WMI_VDEV_PARAM_2xLDPC, /* 0xCA */ - - /** - * Self-capability support indication for CCK RX/TX in 5GHz band. - * Use with WMI_VDEV_SET_PARAM_CMDID, value: - * BIT 0 - cck_rx_support_5ghz - * BIT 1 - cck_tx_support_5ghz - * - * Host must only set this param when enabled by ini and - * WMI_SERVICE_CCK_RX_SUPPORT_5GHZ/WMI_SERVICE_CCK_TX_SUPPORT_5GHZ - * (FW capability bits) are present. - */ - WMI_VDEV_PARAM_CCK_SUPPORT, /* 0xCB */ - - /* - * BIT 0: - * value 0 | disable D-SMPS - * value 1 | enable D-SMPS - * BIT 1: - * value 0 | disable dynamic D-SMPS base on RSSI feature - * value 1 | enable dynamic D-SMPS base on RSSI feature - */ - WMI_VDEV_PARAM_DSMPS_CONTROL, /* 0xCC */ - - /* - * Support P2P GO cancel long duration one-shot NOA - * 0 - Disable P2P GO cancel NOA feature - default value - * 1 - Enable P2P GO cancel NOA feature - */ - WMI_VDEV_PARAM_SET_GO_CANCEL_NOA, /* 0xCD */ - - /* - * WMI command to set ACK rate - * param_value refer to rate code (legacy CCK/OFDM rates) definitions - * for ACK Rates - * valid values: - * ACK_RATE_CODE_6MBPS_OFDM (0x003): Set 6Mbps OFDM ACK rate - * ACK_RATE_CODE_12MBPS_OFDM (0x002): Set 12Mbps OFDM ACK rate - * ACK_RATE_CODE_24MBPS_OFDM (0x001): Set 24Mbps OFDM ACK rate - * ... - * ACK_RATE_RESTORE_ORIGINAL (0xFFFF): Restore original rates - */ - WMI_VDEV_PARAM_ACK_RATE, /* 0xCE */ - - /* Enable TWT in Concurrency for this vdev */ - WMI_VDEV_PARAM_ENABLE_TWT_CONCURRENCY, /* 0xCF */ - - /* Use BTWT ID0 for this vdev */ - WMI_VDEV_PARAM_USE_BTWT_ID0, /* 0xD0 */ - - /* - * Enable or disable UHR ELR capability in Auto rate and - * Fixed rate UHR data packet transmissions. - * Enable or disable Enhanced Long range - * valid values: 0 - Disable ELR, 1 - Enable ELR. - */ - WMI_VDEV_PARAM_UHR_ELR, /* 0xD1 */ - - /* - * Enable or disable Non-data UHR Enhanced Long Range - * valid values: 0 - Disable ELR, 1 - Enable ELR. - */ - WMI_VDEV_PARAM_NON_DATA_UHR_ELR, /* 0xD2 */ - /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE === * The below vdev param types are used for prototyping, and are @@ -21145,16 +19474,6 @@ typedef enum { */ WMI_VDEV_PARAM_SET_SAP_PS_WITH_TWT, /* 0x8013 */ - /* - * Support RTT Bandwidth downgrade - * 0 - Disable RTT Bandwidth downgrade - * 1 - Enable RTT Bandwidth downgrade - */ - WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_BW_DOWNGRADE,/* 0x8014 */ - - /* customized txop for vendor configuration in unit of us */ - WMI_VDEV_PARAM_SU_TXOP_BURST_LIMIT_US, /* 0x8015 */ - /*=== END VDEV_PARAM_PROTOTYPE SECTION ===*/ } WMI_VDEV_PARAM; @@ -21314,46 +19633,46 @@ typedef enum { /* commands for 11ax TXBF capabilities */ -#define WMI_TXBF_CONF_11AX_SU_TX_BFER_GET(x) WMI_GET_BITS(x,0,1) +#define WMI_TXBF_CONF_11AX_SU_TX_BFER_GET(x) WMI_GET_BITS((x,0,1) #define WMI_TXBF_CONF_11AX_SU_TX_BFER_SET(x,z) WMI_SET_BITS(x,0,1,z) -#define WMI_TXBF_CONF_11AX_SU_TX_BFEE_GET(x) WMI_GET_BITS(x,1,1) +#define WMI_TXBF_CONF_11AX_SU_TX_BFEE_GET(x) WMI_GET_BITS((x,1,1) #define WMI_TXBF_CONF_11AX_SU_TX_BFEE_SET(x,z) WMI_SET_BITS(x,1,1,z) -#define WMI_TXBF_CONF_11AX_MU_TX_BFER_GET(x) WMI_GET_BITS(x,2,1) +#define WMI_TXBF_CONF_11AX_MU_TX_BFER_GET(x) WMI_GET_BITS((x,2,1) #define WMI_TXBF_CONF_11AX_MU_TX_BFER_SET(x,z) WMI_SET_BITS(x,2,1,z) -#define WMI_TXBF_CONF_11AX_BFEE_NDP_STS_LT_EQ_80_GET(x) WMI_GET_BITS(x,3,3) +#define WMI_TXBF_CONF_11AX_BFEE_NDP_STS_LT_EQ_80_GET(x) WMI_GET_BITS((x,3,3) #define WMI_TXBF_CONF_11AX_BFEE_NDP_STS_LT_EQ_80_SET(x,z) WMI_SET_BITS(x,3,3,z) -#define WMI_TXBF_CONF_11AX_NSTS_LT_EQ_80_GET(x) WMI_GET_BITS(x,6,3) +#define WMI_TXBF_CONF_11AX_NSTS_LT_EQ_80_GET(x) WMI_GET_BITS((x,6,3) #define WMI_TXBF_CONF_11AX_NSTS_LT_EQ_80_SET(x,z) WMI_SET_BITS(x,6,3,z) -#define WMI_TXBF_CONF_11AX_TX_BFEE_NDP_STS_GT_80_GET(x) WMI_GET_BITS(x,9,3) +#define WMI_TXBF_CONF_11AX_TX_BFEE_NDP_STS_GT_80_GET(x) WMI_GET_BITS((x,9,3) #define WMI_TXBF_CONF_11AX_TX_BFEE_NDP_STS_GT_80_SET(x,z) WMI_SET_BITS(x,9,3,z) -#define WMI_TXBF_CONF_11AX_NSTS_GT_80_GET(x) WMI_GET_BITS(x,12,3) +#define WMI_TXBF_CONF_11AX_NSTS_GT_80_GET(x) WMI_GET_BITS((x,12,3) #define WMI_TXBF_CONF_11AX_NSTS_GT_80_SET(x,z) WMI_SET_BITS(x,12,3,z) -#define WMI_TXBF_CONF_AX_BFER_SND_DIM_LT_EQ_80_SND_DIM_GET(x) WMI_GET_BITS(x,15,3) +#define WMI_TXBF_CONF_AX_BFER_SND_DIM_LT_EQ_80_SND_DIM_GET(x) WMI_GET_BITS((x,15,3) #define WMI_TXBF_CONF_AX_BFER_SND_DIM_LT_EQ_80_SND_DIM_SET(x,z) WMI_SET_BITS(x,15,3,z) -#define WMI_TXBF_CONF_AX_BFER_SND_DIM_GT_80_SND_DIM_GET(x) WMI_GET_BITS(x,18,3) +#define WMI_TXBF_CONF_AX_BFER_SND_DIM_GT_80_SND_DIM_GET(x) WMI_GET_BITS((x,18,3) #define WMI_TXBF_CONF_AX_BFER_SND_DIM_GT_80_SND_DIM_SET(x,z) WMI_SET_BITS(x,18,3,z) -#define WMI_TXBF_CONF_AX_SU_BFEE_NG16_FDBK_GET(x) WMI_GET_BITS(x,21,1) +#define WMI_TXBF_CONF_AX_SU_BFEE_NG16_FDBK_GET(x) WMI_GET_BITS((x,21,1) #define WMI_TXBF_CONF_AX_SU_BFEE_NG16_FDBK_SET(x,z) WMI_SET_BITS(x,21,1,z) -#define WMI_TXBF_CONF_AX_MU_BFEE_NG16_FDBK_GET(x) WMI_GET_BITS(x,22,1) +#define WMI_TXBF_CONF_AX_MU_BFEE_NG16_FDBK_GET(x) WMI_GET_BITS((x,22,1) #define WMI_TXBF_CONF_AX_MU_BFEE_NG16_FDBK_SET(x,z) WMI_SET_BITS(x,22,1,z) -#define WMI_TXBF_CONF_AX_SU_BFEE_CDBK_4_2_GET(x) WMI_GET_BITS(x,23,1) +#define WMI_TXBF_CONF_AX_SU_BFEE_CDBK_4_2_GET(x) WMI_GET_BITS((x,23,1) #define WMI_TXBF_CONF_AX_SU_BFEE_CDBK_4_2_SET(x,z) WMI_SET_BITS(x,23,1,z) -#define WMI_TXBF_CONF_AX_MU_BFEE_CDBK_7_5_GET(x) WMI_GET_BITS(x,24,1) +#define WMI_TXBF_CONF_AX_MU_BFEE_CDBK_7_5_GET(x) WMI_GET_BITS((x,24,1) #define WMI_TXBF_CONF_AX_MU_BFEE_CDBK_7_5_SET(x,z) WMI_SET_BITS(x,24,1,z) -#define WMI_TXBF_CONF_AX_FDBK_TRIG_GET(x) WMI_GET_BITS(x,25,1) +#define WMI_TXBF_CONF_AX_FDBK_TRIG_GET(x) WMI_GET_BITS((x,25,1) #define WMI_TXBF_CONF_AX_FDBK_TRIG_SET(x,z) WMI_SET_BITS(x,25,1,z) @@ -21443,7 +19762,7 @@ typedef struct { /** requestor id that requested the VDEV start request */ A_UINT32 requestor_id; /* Respose of Event type START/RESTART */ - A_UINT32 resp_type; /* WMI_START_EVENT_PARAM */ + WMI_START_EVENT_PARAM resp_type; /** status of the response */ A_UINT32 status; /** Vdev chain mask */ @@ -21526,7 +19845,6 @@ typedef struct { #define WMI_VDEV_START_RESPONSE_INCORRECT_CHANNEL_PARAMS 0x9 /** home channel params are incorrect */ #define WMI_VDEV_START_RESPONSE_GENERIC_VDEV_START_FAILURE 0xa /** generic reason code for vdev start request reject */ - /** Beacon processing related command and event structures */ typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_bcn_tx_hdr */ @@ -22002,105 +20320,91 @@ enum wmi_sta_ps_scheme_cfg { WMI_STA_PS_OPM_CONSERVATIVE = 0, WMI_STA_PS_OPM_AGGRESSIVE = 1, WMI_STA_PS_USER_DEF = 2, - WMI_STA_PS_LATENCY_DEF = 3, }; enum wmi_sta_powersave_param { - /** - * Controls how frames are retrievd from AP while STA is sleeping - * - * (see enum wmi_sta_ps_param_rx_wake_policy) - */ - WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0, +/** + * Controls how frames are retrievd from AP while STA is sleeping + * + * (see enum wmi_sta_ps_param_rx_wake_policy) + */ +WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0, - /** - * The STA will go active after this many TX - * - * (see enum wmi_sta_ps_param_tx_wake_threshold) - */ - WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1, +/** + * The STA will go active after this many TX + * + * (see enum wmi_sta_ps_param_tx_wake_threshold) + */ +WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1, - /** - * Number of PS-Poll to send before STA wakes up - * - * (see enum wmi_sta_ps_param_pspoll_count) - * - */ - WMI_STA_PS_PARAM_PSPOLL_COUNT = 2, +/** + * Number of PS-Poll to send before STA wakes up + * + * (see enum wmi_sta_ps_param_pspoll_count) + * + */ +WMI_STA_PS_PARAM_PSPOLL_COUNT = 2, - /** - * TX/RX inactivity time in msec before going to sleep. - * - * The power save SM will monitor tx/rx activity on the VDEV, if no - * activity for the specified msec of the parameter the Power save SM will - * go to sleep. - */ - WMI_STA_PS_PARAM_INACTIVITY_TIME = 3, +/** + * TX/RX inactivity time in msec before going to sleep. + * + * The power save SM will monitor tx/rx activity on the VDEV, if no + * activity for the specified msec of the parameter the Power save SM will + * go to sleep. + */ +WMI_STA_PS_PARAM_INACTIVITY_TIME = 3, - /** - * Set uapsd configuration. - * - * (see enum wmi_sta_ps_param_uapsd) - */ - WMI_STA_PS_PARAM_UAPSD = 4, +/** + * Set uapsd configuration. + * + * (see enum wmi_sta_ps_param_uapsd) + */ +WMI_STA_PS_PARAM_UAPSD = 4, - /** - * Number of PS-Poll to send before STA wakes up in QPower Mode - */ - WMI_STA_PS_PARAM_QPOWER_PSPOLL_COUNT = 5, +/** + * Number of PS-Poll to send before STA wakes up in QPower Mode + */ +WMI_STA_PS_PARAM_QPOWER_PSPOLL_COUNT = 5, - /** - * Enable OPM - */ - WMI_STA_PS_ENABLE_QPOWER = 6, - WMI_STA_PS_ENABLE_OPM = WMI_STA_PS_ENABLE_QPOWER, /* alias */ +/** + * Enable OPM + */ +WMI_STA_PS_ENABLE_QPOWER = 6, + WMI_STA_PS_ENABLE_OPM = WMI_STA_PS_ENABLE_QPOWER, /* alias */ - /** - * Number of TX frames before the entering the Active state - */ - WMI_STA_PS_PARAM_QPOWER_MAX_TX_BEFORE_WAKE = 7, +/** + * Number of TX frames before the entering the Active state + */ +WMI_STA_PS_PARAM_QPOWER_MAX_TX_BEFORE_WAKE = 7, - /** - * QPower SPEC PSPOLL interval - */ - WMI_STA_PS_PARAM_QPOWER_SPEC_PSPOLL_WAKE_INTERVAL = 8, +/** + * QPower SPEC PSPOLL interval + */ +WMI_STA_PS_PARAM_QPOWER_SPEC_PSPOLL_WAKE_INTERVAL = 8, - /** - * Max SPEC PSPOLL to be sent when the PSPOLL response has - * no-data bit set - */ - WMI_STA_PS_PARAM_QPOWER_SPEC_MAX_SPEC_NODATA_PSPOLL = 9, +/** + * Max SPEC PSPOLL to be sent when the PSPOLL response has + * no-data bit set + */ +WMI_STA_PS_PARAM_QPOWER_SPEC_MAX_SPEC_NODATA_PSPOLL = 9, - /** - * Max value of ITO reset when there is no tx-rx - * after AP has set the TIM bit - */ - WMI_STA_PS_PARAM_MAX_RESET_ITO_COUNT_ON_TIM_NO_TXRX = 10, +/** + * Max value of ITO reset when there is no tx-rx + * after AP has set the TIM bit + */ +WMI_STA_PS_PARAM_MAX_RESET_ITO_COUNT_ON_TIM_NO_TXRX = 10, - /** - * Flag to enable/disable Powersave Optimization - * in WOW - */ - WMI_STA_PS_PARAM_ENABLE_PS_OPT_IN_WOW = 11, +/** + * Flag to enable/disable Powersave Optimization + * in WOW + */ +WMI_STA_PS_PARAM_ENABLE_PS_OPT_IN_WOW = 11, - /** - * Speculative interval in ms - */ - WMI_STA_PS_PARAM_SPEC_WAKE_INTERVAL = 12, +/** + * Speculative interval in ms + */ +WMI_STA_PS_PARAM_SPEC_WAKE_INTERVAL = 12, - /** - * Value determines the ITO level to apply - */ - WMI_STA_PS_PARAM_ITO_LEVEL = 13, - - /** - * TX/RX inactivity time in msec before going to sleep in wow. - * - * The power save SM will monitor tx/rx activity on the VDEV, if no - * activity for the specified msec of the parameter the Power save SM will - * go to sleep. - */ - WMI_STA_PS_PARAM_INACTIVITY_TIME_WOW = 14, }; typedef struct { @@ -22605,7 +20909,6 @@ enum wmi_peer_type { WMI_PEER_TYPE_TRANS_BSS = 5, /* For creating BSS peer when connecting with non-transmit AP */ WMI_PEER_TYPE_PASN = 6, /* Peer is used for Pre-Association Security Negotiation */ WMI_PEER_TYPE_BRIDGE = 7, /* For creating Dummy Peer in case of 4 Link MLO */ - WMI_PEER_TYPE_MAPC = 8, /* Peer is a MAPC Co-ordinated AP */ WMI_PEER_TYPE_HOST_MAX = 127, /* Host <-> Target Peer type is assigned up to 127 */ /* Reserved from 128 - 255 for target internal use.*/ WMI_PEER_TYPE_ROAMOFFLOAD_TEMP = 128, /* Temporarily created during offload roam */ @@ -22617,12 +20920,6 @@ typedef struct { wmi_mlo_flags mlo_flags; /* only mlo enable flag need by STA mode peer create */ } wmi_peer_create_mlo_params; -#define WMI_PEER_CREATE_GET_HW_PEER_ID_VALID(flags) WMI_GET_BITS(flags,0,1) -#define WMI_PEER_CREATE_SET_HW_PEER_ID_VALID(flags) WMI_SET_BITS(flags,0,1,value) - -#define WMI_PEER_CREATE_GET_IS_11BI_PEER(flags) WMI_GET_BITS(flags,1,1) -#define WMI_PEER_CREATE_SET_IS_11BI_PEER(flags) WMI_SET_BITS(flags,1,1,value) - typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_create_cmd_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ @@ -22631,20 +20928,7 @@ typedef struct { wmi_mac_addr peer_macaddr; /** peer type: see enum values above */ A_UINT32 peer_type; - /** Peer create flags */ - union { - struct { - A_UINT32 hw_peer_id_valid :1, - is_11bi_peer :1, - reserved :30; - }; - A_UINT32 flags; - }; - /** Global sw peer id, valid only if non-zero */ - A_UINT32 sw_peer_id; - /** Global hardware id, valid only if hw_peer_id_valid is set */ - A_UINT32 hw_peer_id; -/* The TLVs follow this structure: +/* The TLVs follows this structure: * wmi_peer_create_mlo_params mlo_params[]; <-- MLO flags on peer_create * Optional TLV, only present for MLO peers. * If the peer is non-MLO, the array length should be 0. @@ -23122,20 +21406,13 @@ typedef struct { #define WMI_PEER_PARAM_UL_OFDMA_RTD 0x2B /* - * Count and Interval to send unsolicited probe response to a connected STA. - * BIT 0-23 - Interval (in us) - * BIT 24-31 - Count (Number of probe response frame to send) - * - * Count : 0 - Stop sending immediately. - * Count : 1-254 - Send a probe response periodically at given interval - * until count expires. - * Count : 255 - Send a probe response periodically at given interval - * until stopped. + * Send unsolicited probe response to a connected STA. + * 0: Send immediately and stop. + * XX: Send every XX ms continuously. + * 0xFFFFFFFF: Stop sending immediately. */ #define WMI_PEER_PARAM_UNSOL_PROBE_RESP_INTVL 0x2C -#define WMI_PEER_PARAM_SET_MESH_NODE 0x2D -#define WMI_PEER_PARAM_SET_QUALCOMM_NODE 0x2E typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param */ @@ -23344,19 +21621,14 @@ typedef struct { #define WMI_PEER_SAFEMODE_EN 0x80000000 /* Fips Mode Enabled */ /** define for peer_flags_ext */ -#define WMI_PEER_EXT_EHT 0x00000001 /* EHT enabled */ -#define WMI_PEER_EXT_320MHZ 0x00000002 /* 320Mhz enabled */ -#define WMI_PEER_EXT_DMS_CAPABLE 0x00000004 -#define WMI_PEER_EXT_HE_CAPS_6GHZ_VALID 0x00000008 /* param he_caps_6ghz is valid or not */ -#define WMI_PEER_EXT_IS_QUALCOMM_NODE 0x00000010 /* Indicates if the peer connecting is a qualcomm node */ -#define WMI_PEER_EXT_IS_MESH_NODE 0x00000020 /* Indicates if the peer connecting is a mesh node */ -#define WMI_PEER_EXT_PROTECTED_TWT 0x00000040 /* Protected TWT operation Support field in Extended RSN Capabilities element */ -#define WMI_PEER_EXT_UHR 0x00000080 /* UHR enabled */ -#define WMI_PEER_EXT_2XLDPC 0x00000100 /* Peer supports 2x LDPC (3888-bit codeword) */ - +#define WMI_PEER_EXT_EHT 0x00000001 /* EHT enabled */ +#define WMI_PEER_EXT_320MHZ 0x00000002 /* 320Mhz enabled */ +#define WMI_PEER_EXT_DMS_CAPABLE 0x00000004 +#define WMI_PEER_EXT_HE_CAPS_6GHZ_VALID 0x00000008 /* param he_caps_6ghz is valid or not */ +#define WMI_PEER_EXT_IS_QUALCOMM_NODE 0x00000010 /* Indicates if the peer connecting is a qualcomm node */ +#define WMI_PEER_EXT_IS_MESH_NODE 0x00000020 /* Indicates if the peer connecting is a mesh node */ +#define WMI_PEER_EXT_PROTECTED_TWT 0x00000040 /* Protected TWT operation Support field in Extended RSN Capabilities element */ #define WMI_PEER_EXT_F_CRIT_PROTO_HINT_ENABLED 0x40000000 -#define WMI_PEER_EXT_SMD_ASSOC 0x80000000 - /** * Peer rate capabilities. @@ -23530,175 +21802,6 @@ typedef struct { wmi_mac_addr link_macaddr; } wmi_pdev_mesh_rx_filter_enable_fixed_param; -typedef struct { - A_UINT32 tlv_header; /** TLV tag (WMITLV_TAG_STRUC_wmi_peer_assoc_operating_mode_params) and len */ - /* rx_nss: - * self rx nss indicated to AP through capability IEs or operating mode IE. - * 1 ~ n: 1ss ~ nss - */ - A_UINT32 rx_nss; - /* tx_nss: - * self tx nss indicated to AP through capability IEs or operating mode IE. - * 1 ~ n: 1ss ~ nss - */ - A_UINT32 tx_nss; - /* bw: - * self BW indicated to AP through capability IEs or operating mode IE, - * refer to wmi_channel_width for definition of the values this field - * can hold. - */ - A_UINT32 bw; -} wmi_peer_assoc_operating_mode_params; - - -typedef enum { - WMI_MGMT_TID_MSDUQ_LINK_SPECIFIC,/* legacy and link peer */ - WMI_MGMT_TID_MSDUQ_LINK_AGNOSTIC, - WMI_MGMT_TID_MSDUQ_TYPE_MAX, -} WMI_MGMT_TID_MSDUQ_TYPE; - -#define WMI_MGMT_MSDUQ_GET_LINK_ID(msduq_type) WMI_GET_BITS(msduq_type,0,3) -#define WMI_MGMT_MSDUQ_SET_LINK_ID(msduq_type) WMI_SET_BITS(msduq_type,0,3,value) -#define WMI_MGMT_MSDUQ_GET_FLOW_TYPE(msduq_type) WMI_GET_BITS(msduq_type,3,5) -#define WMI_MGMT_MSDUQ_SET_FLOW_TYPE(msduq_type) WMI_SET_BITS(msduq_type,3,5,value) - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and Len. Tag: WMITLV_TAG_STRUC_wmi_peer_assoc_mgmt_msduq_params*/ - union { - struct { - A_UINT32 link_id : 3, /* HW Link ID */ - flow_type : 5, /* WMI_MGMT_TID_MSDUQ_TYPE */ - reserved : 24; - }; - A_UINT32 msduq_type; - }; - - /* 40 bit physical address, 256 bytes alligned, LSB 8 bits are zero */ - A_UINT32 mgmt_msduq_paddr_39_8; -} wmi_peer_assoc_mgmt_msduq_params; - -typedef struct { - A_UINT32 tlv_header; /* TAG_ID : WMITLV_TAG_STRUC_wmi_peer_assoc_mgmt_mpduq_params */ - /* 40 bit physical address, 256 bytes alligned, LSB 8 bits are zero */ - A_UINT32 mgmt_mpduq_paddr_39_8; - A_UINT32 pn_paddr_31_0; - A_UINT32 pn_paddr_39_32; -} wmi_peer_assoc_mgmt_mpduq_params; - -#define WMI_HOL_QUEUE_GET_PEER_ID(mpduq_msduq_number) \ - WMI_GET_BITS(mpduq_msduq_number,0,12) -#define WMI_HOL_QUEUE_SET_PEER_ID(mpduq_msduq_number) \ - WMI_SET_BITS(mpduq_msduq_number,0,12,value) -#define WMI_HOL_QUEUE_GET_TID_NUM(mpduq_msduq_number) \ - WMI_GET_BITS(mpduq_msduq_number,12,5) -#define WMI_HOL_QUEUE_SET_TID_NUM(mpduq_msduq_number) \ - WMI_SET_BITS(mpduq_msduq_number,12,5,value) -#define WMI_HOL_QUEUE_GET_MPDUQ_TYPE(mpduq_msduq_number) \ - WMI_GET_BITS(mpduq_msduq_number,17,5) -#define WMI_HOL_MSDUQ_SET_MPDUQ_TYPE(mpduq_msduq_number) \ - WMI_SET_BITS(mpduq_msduq_number,17,5,value) -#define WMI_HOL_QUEUE_GET_MSDUQ_TYPE(mpduq_msduq_number) \ - WMI_GET_BITS(mpduq_msduq_number,22,5) -#define WMI_HOL_MSDUQ_SET_MSDUQ_TYPE(mpduq_msduq_number) \ - WMI_SET_BITS(mpduq_msduq_number,22,5,value) - -typedef struct { - A_UINT32 tlv_header; /* TAG_ID : WMITLV_TAG_STRUC_wmi_peer_assoc_hol_msduq_params */ - - /** - * A_UINT32 - * WMI_HOL_MSDUQ_GET_PEER_ID / WMI_HOL_MSDU_SET_PEER_ID - * peer_id:12, - * - * WMI_HOL_MSDUQ_GET_TID_NUM / WMI_HOL_MSDUQ_SET_TID_NUM - * tid_num:5, - * - * WMI_HOL_MPDUQ_GET_QUEUE_TYPE / WMI_HOL_MPDUQ_SET_QUEUE_TYPE - * mpduq_type:5, - * - * WMI_HOL_MSDUQ_GET_QUEUE_TYPE / WMI_HOL_MSDUQ_SET_QUEUE_TYPE - * msduq_type:5, - * - * rsvd:5; - */ - union { - struct { - A_UINT32 peer_id : 12, - tid_num : 5, - mpduq_type : 5, - msduq_type : 5, - reserved : 5; - }; - A_UINT32 mpduq_msduq_number; - }; - - /* 40 bit address, 256 bytes alligned LSB 8 bits are zero */ - A_UINT32 mpduq_paddr_39_8; - - /* 40 bit address, 256 bytes alligned LSB 8 bits are zero */ - A_UINT32 msduq_paddr_39_8; - - /* First 32 bits for pn physical address */ - A_UINT32 pn_paddr_31_0; - - /* Upper 8 bits of 40 bit pn physical address */ - A_UINT32 pn_paddr_39_32; -} wmi_peer_assoc_hol_msduq_params; -/* - * for backwards compatibility, maintain old version of the name - * (with "mdsu" typo) - */ -typedef wmi_peer_assoc_hol_msduq_params wmi_peer_assoc_hol_mdsuq_params; - -typedef struct { - A_UINT32 tlv_header; /* TAG_ID : WMITLV_TAG_STRUC_wmi_peer_assoc_cfp_params */ - - /* control frame protection enable/disable per peer */ - A_UINT32 enable_cfp; - - /* - * MIC Padding Delay Field Values: - * - * Value Delay - * ---------------- - * 0 0 us - * 1 4 us - * 2 8 us - * 3 12 us - * 4 16 us - * 5 20 us - * 6 24 us - * 7 28 us - * 8 32 us - * 9-15 Reserved - */ - A_UINT32 cfp_padding_delay; -} wmi_peer_assoc_cfp_params; /* cfp -> control frame protection */ - -#define WMI_PEER_ASSOC_SMD_FLAGS_GET_ROAM_ENABLED(mlo_flags) WMI_GET_BITS(mlo_flags, 0, 1) -#define WMI_PEER_ASSOC_SMD_FLAGS_SET_ROAM_ENABLED(mlo_flags, value) WMI_SET_BITS(mlo_flags, 0, 1, value) -#define WMI_PEER_ASSOC_SMD_FLAGS_GET_DL_DATA_FORWARDING(mlo_flags) WMI_GET_BITS(mlo_flags, 1, 1) -#define WMI_PEER_ASSOC_SMD_FLAGS_SET_DL_DATA_FORWARDING(mlo_flags, value) WMI_SET_BITS(mlo_flags, 1, 1, value) -#define WMI_PEER_ASSOC_SMD_FLAGS_GET_UL_DATA_FORWARDING(mlo_flags) WMI_GET_BITS(mlo_flags, 2, 1) -#define WMI_PEER_ASSOC_SMD_FLAGS_SET_UL_DATA_FORWARDING(mlo_flags, value) WMI_SET_BITS(mlo_flags, 2, 1, value) - -/* This TLV structure used to pass smd Parameters on peer assoc */ -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_assoc_smd_params */ - /** The SMD Identifier field indicates a unique identifier for the SMD and is in the format of a 48-bit MAC address. */ - wmi_mac_addr smd_identifier; - /** SMD capabilities defined in 802.11BN-SMD Information element */ - A_UINT32 smd_capabilities; - union { - struct { - A_UINT32 roam_enabled :1, - dl_data_forwarding :1, - ul_data_forwarding :1, - reserved :29; - }; - A_UINT32 smd_flags; - }; -} wmi_peer_assoc_smd_params; /* * PEER assoc_flags for assoc complete: @@ -23708,36 +21811,13 @@ typedef struct { #define WMI_ASSOC_FLAG_FLUSH_PEER_DATA_GET(assoc_flags) WMI_GET_BITS(assoc_flags, 0, 1) #define WMI_ASSOC_FLAG_FLUSH_PEER_DATA_SET(assoc_flags, value) WMI_GET_BITS(assoc_flags, 0, 1, value) -enum wmi_peer_new_assoc { - WMI_PEER_REASSOC = 0, /* Peer Reassoc */ - WMI_PEER_ASSOC = 1, /* Peer Assoc */ - WMI_PEER_CREATE_ASSOC = 2, /* Peer Create and Peer Assoc in single command, - * currently used for SMD case */ - - /* Host <-> Target Peer New Assoc is assigned up to 127 */ - WMI_PEER_NEW_ASSOC_MAX = 127 -}; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_uhr_rate_set */ - /** - * B0-B3 indicates max NSS that supports mcs 0-7 - * B4-B7 indicates max NSS that supports mcs 8-9 - * B8-B11 indicates max NSS that supports mcs 10-11 - * B12-B15 indicates max NSS that supports mcs 12-13 - * B16-B31 reserved - */ - A_UINT32 rx_mcs_set; /* Rx max NSS set */ - A_UINT32 tx_mcs_set; /* Tx max NSS set */ -} wmi_uhr_rate_set; - typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_assoc_complete_cmd_fixed_param */ /** peer MAC address */ wmi_mac_addr peer_macaddr; /** VDEV id */ A_UINT32 vdev_id; - /* enum wmi_peer_new_assoc: create_assoc = 2, assoc = 1, reassoc = 0 */ + /** assoc = 1 reassoc = 0 */ A_UINT32 peer_new_assoc; /** peer associd (16 bits) */ A_UINT32 peer_associd; @@ -23863,66 +21943,6 @@ typedef struct { A_UINT32 peer_eht_ops; wmi_ppe_threshold peer_eht_ppet; A_UINT32 assoc_flags; - /** maximum number of spatial streams supported by peer for tx */ - A_UINT32 peer_max_tx_nss; - /* max_downlink_nss: - * max downlink nss, intersected between self rx and peer tx. - * 1~N means 1ss~Nss - */ - A_UINT32 max_downlink_nss; - - /** Peer create flags */ - union { - struct { - A_UINT32 hw_peer_id_valid : 1, - peer_type_valid : 1, - /** - * Host sets these peer_cck [rx,tx] support_5ghz fields - * based on the intersection of AP and self-capabilities. - * Example: - * On the STA, if the peer (AP) supports CCK 5GHz RX - * and the STA supports CCK 5GHz TX, then set - * peer_cck_rx_support_5ghz = 1 - */ - peer_cck_rx_support_5ghz : 1, - peer_cck_tx_support_5ghz : 1, - sam_peer_id_valid : 1, - reserved :27; - }; - A_UINT32 flags; - }; - /** Global sw peer id, valid only if non-zero */ - A_UINT32 sw_peer_id; - /** Global hardware id, valid only if hw_peer_id_valid is set */ - A_UINT32 hw_peer_id; - /** peer type: see enum values above */ - A_UINT32 peer_type; - /** Global SAM Peer ID, valid only if sam_peer_id_valid is set */ - A_UINT32 sam_peer_id; - - /** peer_uhr_cap_mac: - * UHR mac capabilities from BSS beacon UHR cap IE, - * total WMI_MAX_UHRCAP_MAC_SIZE*A_UINT32 bits - */ - A_UINT32 peer_uhr_cap_mac[WMI_MAX_UHRCAP_MAC_SIZE]; - /** peer_uhr_cap_phy: - * UHR phy capabilities from BSS beacon UHR cap IE, - * total WMI_MAX_UHRCAP_PHY_SIZE*A_UINT32 bits - */ - A_UINT32 peer_uhr_cap_phy[WMI_MAX_UHRCAP_PHY_SIZE]; - /** refer to WMI_UHR_OPS_XXX macros */ - A_UINT32 peer_uhr_ops; - /** peer_uhr_ppet: - * UHR Packet Padding Extension (PPE) thresholds from BSS beacon UHR cap IE - */ - wmi_ppe_threshold peer_uhr_ppet; - - /** peer_uhr_cap_dbe: - * UHR DBE Capability Parameters from BSS beacon UHR cap IE, - * total WMI_MAX_UHRCAP_DBE_SIZE*A_UINT32 bits. - * Valid only when DBE Support bit (B10) in peer_uhr_cap_mac is set. - */ - A_UINT32 peer_uhr_cap_dbe[WMI_MAX_UHRCAP_DBE_SIZE]; /* Following this struct are the TLV's: * A_UINT8 peer_legacy_rates[]; @@ -23935,354 +21955,9 @@ typedef struct { * wmi_eht_rate_set peer_eht_rates; <-- EHT capabilities of the peer * wmi_peer_assoc_mlo_partner_link_params link_info[] <-- partner link info * wmi_peer_assoc_tid_to_link_map[] <-- tid to link_map info - * wmi_peer_assoc_operating_mode_params <-- operating mode param that - * host sends to AP in peer assoc req, optional TLV - * --- the below only apply to WMI_PEER_ASSOC_V2_CMD, not WMI_PEER_ASSOC_CMDID - * wmi_peer_uhr_npca_cap_params peer_npca_cap_params[]; <-- peer NPCA - * capabilities, host sends NPCA peer capabilities as an optional TLV - * wmi_peer_create_mlo_params mlo_params[]; <-- MLO flags on peer_create - * Optional TLV, only present for MLO peers. - * If the peer is non-MLO, the array length should be 0. - * Only mlo_enable flag required by MCC to decide MAC address - * to be used. - * wmi_peer_assoc_smd_params peer_assoc_smd_params; - * wmi_uhr_rate_set peer_uhr_rates; <-- UHR capabilities of the peer - * wmi_peer_uhr_npca_op_params npca_op_params[0,1] - * Only present if NPCA enable is set in peer_uhr_ops & - * NPCA support is set in peer_uhr_cap_mac of fixed_param. - * Otherwise, array length should be 0. */ } wmi_peer_assoc_complete_cmd_fixed_param; -#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_HW_PEER_ID_VALID_GET(flags) WMI_GET_BITS(flags, 0, 1) -#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_HW_PEER_ID_VALID_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value) - -#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_TYPE_VALID_GET(flags) WMI_GET_BITS(flags, 1, 1) -#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_TYPE_VALID_SET(flags, value) WMI_SET_BITS(flags, 1, 1, value) - -#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_RX_SUPPORT_5GHZ_GET(flags) WMI_GET_BITS(flags, 2, 1) -#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_RX_SUPPORT_5GHZ_SET(flags, value) WMI_SET_BITS(flags, 2, 1, value) - -#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_TX_SUPPORT_5GHZ_GET(flags) WMI_GET_BITS(flags, 3, 1) -#define WMI_PEER_ASSOC_COMPLETE_CMD_FLAG_PEER_CCK_TX_SUPPORT_5GHZ_SET(flags, value) WMI_SET_BITS(flags, 3, 1, value) - -typedef struct { - A_UINT32 tlv_header; - A_UINT32 sw_peer_id; - /* - * flags - * Bit 0 : NPCA Cap supported/Not supported - * WMI_NPCA_PEER_CAP_SUPPORTED_GET / _SET - * - * Bit 1 : NPCA Enabled / Disabled - * WMI_NPCA_PEER_CAP_ENABLED_GET / _SET - * - * Bit 2-7 : NPCA Switch Delay - * The time needed by an NPCA STA to switch from the - * BSS primary channel to the NPCA primary channel, - * in units of 4 us. - * WMI_NPCA_PEER_CAP_SWT_DELAY_GET / _SET - * - * Bit 8:13 : NPCA Switch Back Delay - * The time needed by an NPCA STA to switch from the - * NPCA primary channel to the BSS primary channel, - * in units of 4 us. - * WMI_NPCA_PEER_CAP_SWTB_DELAY_GET / _SET - * - * Bit 14:31: Reserved - */ - A_UINT32 npca_cap; -} wmi_peer_uhr_npca_cap_params; - -#define WMI_NPCA_PEER_CAP_SUPPORTED_GET(_var) WMI_GET_BITS(_var, 0, 1) -#define WMI_NPCA_PEER_CAP_SUPPORTED_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val) -#define WMI_NPCA_PEER_CAP_ENABLED_GET(_var) WMI_GET_BITS(_var, 1, 1) -#define WMI_NPCA_PEER_CAP_ENABLED_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val) -#define WMI_NPCA_PEER_CAP_SWT_DELAY_GET(_var) WMI_GET_BITS(_var, 2, 6) -#define WMI_NPCA_PEER_CAP_SWT_DELAY_SET(_var, _val) WMI_SET_BITS(_var, 2, 6, _val) -#define WMI_NPCA_PEER_CAP_SWTB_DELAY_GET(_var) WMI_GET_BITS(_var, 8, 6) -#define WMI_NPCA_PEER_CAP_SWTB_DELAY_SET(_var, _val) WMI_SET_BITS(_var, 8, 6, _val) - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_uhr_mode_update_cmd_fixed_params */ - A_UINT32 pdev_id; - /* - * Following this structure is the TLV: - * struct wmi_peer_uhr_npca_cap_params peer_npca_cap_params[num_peers]; - */ -} wmi_peer_uhr_mode_update_cmd_fixed_param; - - -/* npca_op_param macros */ -#define WMI_PEER_UHR_NPCA_OP_PARAM_PRIMARY_CHANNEL_GET(_var) \ - WMI_GET_BITS(_var, 0, 4) -#define WMI_PEER_UHR_NPCA_OP_PARAM_PRIMARY_CHANNEL_SET(_var, _val) \ - WMI_SET_BITS(_var, 0, 4, _val) - -#define WMI_PEER_UHR_NPCA_OP_PARAM_MIN_DURATION_THRESHOLD_GET(_var) \ - WMI_GET_BITS(_var, 4, 4) -#define WMI_PEER_UHR_NPCA_OP_PARAM_MIN_DURATION_THRESHOLD_SET(_var, _val) \ - WMI_SET_BITS(_var, 4, 4, _val) - -#define WMI_PEER_UHR_NPCA_OP_PARAM_SWITCH_DELAY_GET(_var) \ - WMI_GET_BITS(_var, 8, 6) -#define WMI_PEER_UHR_NPCA_OP_PARAM_SWITCH_DELAY_SET(_var, _val) \ - WMI_SET_BITS(_var, 8, 6, _val) - -#define WMI_PEER_UHR_NPCA_OP_PARAM_SWITCH_BACK_DELAY_GET(_var) \ - WMI_GET_BITS(_var, 14, 6) -#define WMI_PEER_UHR_NPCA_OP_PARAM_SWITCH_BACK_DELAY_SET(_var, _val) \ - WMI_SET_BITS(_var, 14, 6, _val) - -#define WMI_PEER_UHR_NPCA_OP_PARAM_INITIAL_QSRC_GET(_var) \ - WMI_GET_BITS(_var, 20, 2) -#define WMI_PEER_UHR_NPCA_OP_PARAM_INITIAL_QSRC_SET(_var, _val) \ - WMI_SET_BITS(_var, 20, 2, _val) - -#define WMI_PEER_UHR_NPCA_OP_PARAM_MOPLEN_NPCA_GET(_var) \ - WMI_GET_BITS(_var, 22, 1) -#define WMI_PEER_UHR_NPCA_OP_PARAM_MOPLEN_NPCA_SET(_var, _val) \ - WMI_SET_BITS(_var, 22, 1, _val) - -#define WMI_PEER_UHR_NPCA_OP_PARAM_DIS_SUBCHAN_BMAP_PRESENT_GET(_var) \ - WMI_GET_BITS(_var, 23, 1) -#define WMI_PEER_UHR_NPCA_OP_PARAM_DIS_SUBCHAN_BMAP_PRESENT_SET(_var, _val) \ - WMI_SET_BITS(_var, 23, 1, _val) - -/* npca_op_param1 macros */ -#define WMI_PEER_UHR_NPCA_OP_PARAM1_DISABLED_SUBCHAN_BITMAP_GET(_var) \ - WMI_GET_BITS(_var, 0, 16) -#define WMI_PEER_UHR_NPCA_OP_PARAM1_DISABLED_SUBCHAN_BITMAP_SET(_var, _val) \ - WMI_SET_BITS(_var, 0, 16, _val) - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_uhr_npca_op_params */ - /* - * All below fields are advertised by UHR AP in UHR NPCA Op Param Field - * in UHR Operation IE - * - * Bit 0-3 : NPCA Primary Channel. - * Indicates the channel number of a channel within BSS - * bandwidth that both STA and AP switch to for NPCA operation. - * - * Bit 4-7 : NPCA Minimum Duration Threshold (NMDT). - * FW to convert this value into microsecs using - * 512 + (NMDT * 128) usec. - * - * Bit 8-13 : NPCA Switch Delay, in units of 4 us. - * The time needed by an NPCA AP to switch from the BSS - * primary channel to the NPCA primary channel. - * - * Bit 14-19: NPCA Switch Back Delay, in units of 4 us. - * The time needed by an NPCA AP to switch from the NPCA - * primary channel to the BSS primary channel. - * - * Bit 20-21: Initial NPCA QSRC. - * Indicates the value that is used to initialize the EDCAF - * QSRC[AC] variables when an NPCA STA in the BSS switches - * to NPCA operation. - * - * Bit 22 : MOPLEN NPCA. - * Indicates which conditions can be used to initiate an - * NPCA operation. - * Value 1 means both PHYLEN and MOPLEN operations are - * permitted in BSS. - * Value 0 means only PHYLEN operation is allowed in the BSS. - * - * Bit 23 : NPCA Disabled Subchannel Bitmap Present - * - * Bit 24-31: Reserved - */ - /* Use WMI_PEER_UHR_NPCA_OP_PARAM_ GET/SET macros for each field */ - A_UINT32 npca_op_param; - - /* - * Bit 0-15 : NPCA Disabled Subchannel Bitmap. Valid only when - * WMI_PEER_UHR_NPCA_OP_PARAM_DIS_SUBCHAN_BMAP_PRESENT_GET is - * TRUE. - * The bitmap indexes 20 MHz subchannels in ascending frequency - * order, with the LSB representing the lowest frequency. - * A bit set to 1 indicates the subchannel is punctured, - * while 0 indicates it is not. - * - * Bit 16-31: Reserved - */ - /* Use WMI_PEER_UHR_NPCA_OP_PARAM1_ GET/SET macros for each field */ - A_UINT32 npca_op_param1; -} wmi_peer_uhr_npca_op_params; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_uhr_omp_cmd_fixed_param */ - A_UINT32 sw_peer_id; - A_UINT32 pdev_id; - - /* - * Variable-length TLV arrays follow this fixed param: - * wmi_peer_uhr_omp_npca_params peer_omp_npca_params[]; - * Place Holder for other TLVs - */ -} wmi_peer_uhr_omp_cmd_fixed_param; - -typedef struct{ - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_uhr_omp_npca_params */ - /* - * Bit0:3: NPCA hw_link_id - * WMI_OMP_NPCA_HW_LINK_ID_GET / _SET - * Bit4: Enable/Disable NPCA params - * WMI_OMP_NPCA_ENABLE_GET / _SET - * Bit5: Update NPCA params - * WMI_OMP_NPCA_UPDATE_GET / _SET - * Bit6:31: Reserved - */ - A_UINT32 omp_npca_caps; - /* - * Bit0:5: NPCA Switch Delay - * The time needed by an NPCA STA to switch from the - * BSS primary channel to the NPCA primary channel, - * in units of 4 us. - * WMI_OMP_NPCA_SWITCH_DELAY_GET / _SET - * - * Bit6:11: NPCA Switch Back Delay - * The time needed by an NPCA STA to switch from the - * NPCA primary channel to the BSS primary channel, - * in units of 4 - * WMI_OMP_NPCA_SWITCH_BACK_DELAY_GET / _SET - * - * Bit12:31: Reserved - */ - A_UINT32 omp_npca_param; -} wmi_peer_uhr_omp_npca_params; - -#define WMI_OMP_NPCA_HW_LINK_ID_GET(_var) WMI_GET_BITS(_var, 0, 4) -#define WMI_OMP_NPCA_HW_LINK_ID_SET(_var, _val) WMI_SET_BITS(_var, 0, 4, _val) - -#define WMI_OMP_NPCA_ENABLE_GET(_var) WMI_GET_BITS(_var, 4, 1) -#define WMI_OMP_NPCA_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 4, 1, _val) - -#define WMI_OMP_NPCA_UPDATE_GET(_var) WMI_GET_BITS(_var, 5, 1) -#define WMI_OMP_NPCA_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 5, 1, _val) - -#define WMI_OMP_NPCA_SWITCH_DELAY_GET(_var) \ - WMI_GET_BITS(_var, 0, 6) -#define WMI_OMP_NPCA_SWITCH_DELAY_SET(_var, _val) \ - WMI_SET_BITS(_var, 0, 6, _val) - -#define WMI_OMP_NPCA_SWITCH_BACK_DELAY_GET(_var) \ - WMI_GET_BITS(_var, 6, 6) -#define WMI_OMP_NPCA_SWITCH_BACK_DELAY_SET(_var, _val) \ - WMI_SET_BITS(_var, 6, 6, _val) - - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_uhr_omp_sta_dps_params */ - - /* - * Bit0:3: STA DPS hw_link_id - * WMI_OMP_STA_DPS_HW_LINK_ID_GET / _SET - * Bit4: Enable/Disable STA DPS params - * WMI_OMP_STA_DPS_ENABLE_GET / _SET - * Bit5: Update STA DPS params - * WMI_OMP_STA_DPS_UPDATE_GET / _SET - * Bit6:31: Reserved - */ - A_UINT32 omp_sta_dps_caps; - - /* - * Bit0:5: STA DPS Padding Delay - * WMI_OMP_STA_DPS_PADDING_DELAY_GET / _SET - * - * Bit6:7: Reserved - * - * Bit8:13: STA DPS Transition Delay - * WMI_OMP_STA_DPS_TRANSITION_DELAY_GET / _SET - * - * Bit14:15: Reserved - * - * Bit16: ICF Required - * WMI_OMP_STA_DPS_ICF_REQUIRED_GET / _SET - * - * Bit17: Parameterized Mode - * WMI_OMP_STA_DPS_PARAMETERIZED_MODE_GET / _SET - * - * Bit18:20: LC Mode Bandwidth - * WMI_OMP_STA_DPS_LC_MODE_BANDWIDTH_GET / _SET - * 0 : 20 MHz - * 1 : 40 MHz - * 2 : 80 MHz - * 3 : 160 MHz - * 4 : 320 MHz - * 5-7: Reserved - * - * Bit21:24: LC Mode NSS - * WMI_OMP_STA_DPS_LC_MODE_NSS_GET / _SET - * - * Bit25:28: LC Mode MCS - * WMI_OMP_STA_DPS_LC_MODE_MCS_GET / _SET - * - * Bit29: Mobile AP STA DPS Static HCM - * WMI_OMP_STA_DPS_MOBILE_AP_STATIC_HCM_GET / _SET - * - * Bit30:31: Reserved - */ - A_UINT32 omp_sta_dps_param; -} wmi_peer_uhr_omp_sta_dps_params; - -#define WMI_OMP_STA_DPS_HW_LINK_ID_GET(_var) \ - WMI_GET_BITS(_var, 0, 4) -#define WMI_OMP_STA_DPS_HW_LINK_ID_SET(_var, _val) \ - WMI_SET_BITS(_var, 0, 4, _val) - -#define WMI_OMP_STA_DPS_ENABLE_GET(_var) \ - WMI_GET_BITS(_var, 4, 1) -#define WMI_OMP_STA_DPS_ENABLE_SET(_var, _val) \ - WMI_SET_BITS(_var, 4, 1, _val) - -#define WMI_OMP_STA_DPS_UPDATE_GET(_var) \ - WMI_GET_BITS(_var, 5, 1) -#define WMI_OMP_STA_DPS_UPDATE_SET(_var, _val) \ - WMI_SET_BITS(_var, 5, 1, _val) - -#define WMI_OMP_STA_DPS_PADDING_DELAY_GET(_var) \ - WMI_GET_BITS(_var, 0, 6) -#define WMI_OMP_STA_DPS_PADDING_DELAY_SET(_var, _val) \ - WMI_SET_BITS(_var, 0, 6, _val) - -#define WMI_OMP_STA_DPS_TRANSITION_DELAY_GET(_var) \ - WMI_GET_BITS(_var, 8, 6) -#define WMI_OMP_STA_DPS_TRANSITION_DELAY_SET(_var, _val) \ - WMI_SET_BITS(_var, 8, 6, _val) - -#define WMI_OMP_STA_DPS_ICF_REQUIRED_GET(_var) \ - WMI_GET_BITS(_var, 16, 1) -#define WMI_OMP_STA_DPS_ICF_REQUIRED_SET(_var, _val) \ - WMI_SET_BITS(_var, 16, 1, _val) - -#define WMI_OMP_STA_DPS_PARAMETERIZED_MODE_GET(_var) \ - WMI_GET_BITS(_var, 17, 1) -#define WMI_OMP_STA_DPS_PARAMETERIZED_MODE_SET(_var, _val) \ - WMI_SET_BITS(_var, 17, 1, _val) - -#define WMI_OMP_STA_DPS_LC_MODE_BANDWIDTH_GET(_var) \ - WMI_GET_BITS(_var, 18, 3) -#define WMI_OMP_STA_DPS_LC_MODE_BANDWIDTH_SET(_var, _val) \ - WMI_SET_BITS(_var, 18, 3, _val) - -#define WMI_OMP_STA_DPS_LC_MODE_NSS_GET(_var) \ - WMI_GET_BITS(_var, 21, 4) -#define WMI_OMP_STA_DPS_LC_MODE_NSS_SET(_var, _val) \ - WMI_SET_BITS(_var, 21, 4, _val) - -#define WMI_OMP_STA_DPS_LC_MODE_MCS_GET(_var) \ - WMI_GET_BITS(_var, 25, 4) -#define WMI_OMP_STA_DPS_LC_MODE_MCS_SET(_var, _val) \ - WMI_SET_BITS(_var, 25, 4, _val) - -#define WMI_OMP_STA_DPS_MOBILE_AP_STATIC_HCM_GET(_var) \ - WMI_GET_BITS(_var, 29, 1) -#define WMI_OMP_STA_DPS_MOBILE_AP_STATIC_HCM_SET(_var, _val) \ - WMI_SET_BITS(_var, 29, 1, _val) - - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_ap_oper_bw_cmd_fixed_param */ A_UINT32 vdev_id; @@ -24382,19 +22057,6 @@ typedef struct { * If per_chain_noise_floor value is 0 then it should be ignored. */ A_UINT32 per_chain_noise_floor[WMI_MAX_CHAINS]; - /** - * FW will update the Noise Floor in dBr and send it to host - * if this field is set then host will display NF value in dBr - */ - A_UINT32 nf_dbr_is_valid; - /** - * Noise Floor (NF) value in dBr. If the NF is not converged then - * NF value is returned as 0 to host. Theoretical minimum NF value - * is -101 dB for 20 MHz bandwidth and the max value can be 0. - * PHY reports 0 incase of very high NF values. - * This field should be ignored unless the nf_dbr_is_valid flag is set. - */ - A_UINT32 noise_floor_in_dbr; /** * Following this structure is the optional TLV: @@ -24601,24 +22263,6 @@ typedef struct _wlan_dcs_im_tgt_stats { /** BSS rx cycle count */ A_UINT32 my_bss_rx_cycle_count; - - /*------*/ - /* vdev id and pdev id will be added accordingly in each TLV, - * when combined event for 2 vdevs in case of concurrency. - */ - - /* vdev_id_and_pdev_id_valid: - * If set, then the below vdev_id and pdev_id fields have valid values. - * If not set, then the below vdev_id and pdev_id fields must be ignored. - */ - A_UINT32 vdev_id_and_pdev_id_valid; - - /** vdev id **/ - A_UINT32 vdev_id; /* unique vdev id for DCS stats info */ - - /** pdev id **/ - A_UINT32 pdev_id; /* unique pdev id for DCS stats info */ - /*------*/ } wlan_dcs_im_tgt_stats_t; typedef struct wlan_dcs_awgn_info { @@ -24708,10 +22352,7 @@ typedef struct { * elements (not arrays). union { wlan_dcs_cw_int cw_int; wlan_dcs_im_tgt_stats_t wlan_stat; } int_event; * * wlan_dcs_cw_int cw_int[]; <-- cw_interference event - * wlan_dcs_im_tgt_stats_t wlan_stat[]; <-- wlan im interference stats, - * Contains vdev_id + pdev_id - * to specify who the stats - * are for. + * wlan_dcs_im_tgt_stats_t wlan_stat[]; <-- wlan im interference stats * wmi_dcs_awgn_int_t awgn_int[]; <-- Additive white Gaussian noise (AWGN) interference * wmi_dcs_obss_int_t obss_int[]; <-- Overlapping Basic Service Set (OBSS) interference */ @@ -24830,7 +22471,7 @@ typedef struct { /** unique id identifying the VDEV, generated by the caller */ A_UINT32 vdev_id; /** roam scan RSSI threshold */ - A_UINT32 roam_scan_rssi_thresh; /* 2 GHz threshold */ + A_UINT32 roam_scan_rssi_thresh; /** When using Hw generated beacon RSSI interrupts */ A_UINT32 roam_rssi_thresh_diff; /** 5G scan max count */ @@ -24845,15 +22486,6 @@ typedef struct { A_INT32 rssi_thresh_offset_5g; /** flags for WMI_ROAM_SCAN_RSSI_THRESHOLD Command */ A_UINT32 flags; /* see WMI_ROAM_SCAN_RSSI_THRESHOLD_FLAG defs */ - /* - * If roam_scan_rssi_thresh_5ghz and roam_scan_rssi_thresh_6ghz are 0 - * (due to the host not explicitly filling in values for these fields), - * the FW shall apply the roam_scan_rssi_thresh specification to the - * 5 GHz and 6 GHz bands, along with the 2.4 GHz band that the - * roam_scan_rssi_thresh specification is predominantly intended for. - */ - A_UINT32 roam_scan_rssi_thresh_5ghz; /* 5 GHz threshold */ - A_UINT32 roam_scan_rssi_thresh_6ghz; /* 6 GHz threshold */ /* The TLVs will follow. * wmi_roam_scan_extended_threshold_param extended_param; * wmi_roam_earlystop_rssi_thres_param earlystop_param; @@ -24871,22 +22503,14 @@ typedef struct { /** * btm_config.flags * BIT 0 : Enable/Disable the BTM offload. - * BIT 1-2 : Action on non matching candidate with cache. - * Used WMI_ROAM_BTM_OFLD_NON_MATCHING_CND_XXX + * BIT 1-2 : Action on non matching candidate with cache. Used WMI_ROAM_BTM_OFLD_NON_MATCHING_CND_XXX * BIT 3-5 : Roaming handoff decisions. Use WMI_ROAM_BTM_OFLD_CNDS_MATCH_XXX * BIT 6 : Enable/Disable solicited BTM - * BIT 7 : Roam BTM candidates based on the roam score instead of BTM - * preferred value + * BIT 7 : Roam BTM candidates based on the roam score instead of BTM preferred value * BIT 8 : BTM query preference over 11k neighbor report request * BIT 9 : Send BTM query with preferred candidates list - * BIT 10 : Forward MBO BTM Request to Host if MBO ASSOC RETRY attribute - * is set - * BIT 11 : Detect the missing band from BTM request when compared to - * roam scan results and consider them as valid candidate - * BIT 12 : Defer BTM roam scan if another roam scan is in progress. - * Applicable only when BTM Disassoc imminent and BSS termination - * is not set - * BIT 13-31 : Reserved + * BIT 10 : Forward MBO BTM Request to Host if MBO ASSOC RETRY attribute is set + * BIT 11-31 : Reserved */ #define WMI_ROAM_BTM_SET_ENABLE(flags, val) WMI_SET_BITS(flags, 0, 1, val) #define WMI_ROAM_BTM_GET_ENABLE(flags) WMI_GET_BITS(flags, 0, 1) @@ -24902,12 +22526,8 @@ typedef struct { #define WMI_ROAM_BTM_GET_BTM_QUERY_PREFERENCE_OVER_11K(flags) WMI_GET_BITS(flags, 8, 1) #define WMI_ROAM_BTM_SET_BTM_QUERY_WITH_CANDIDATE_LIST(flags, val) WMI_SET_BITS(flags, 9, 1, val) #define WMI_ROAM_BTM_GET_BTM_QUERY_WITH_CANDIDATE_LIST(flags) WMI_GET_BITS(flags, 9, 1) -#define WMI_ROAM_BTM_SET_FORWARD_MBO_ASSOC_RETRY_BTM_REQUEST_TO_HOST(flags, val) WMI_SET_BITS(flags, 10, 1, val) -#define WMI_ROAM_BTM_GET_FORWARD_MBO_ASSOC_RETRY_BTM_REQUEST_TO_HOST(flags) WMI_GET_BITS(flags, 10, 1) -#define WMI_ROAM_BTM_SET_DETECT_CANDIDATE_FROM_MISSING_BAND_IN_BTM_REQUEST(flags, val) WMI_SET_BITS(flags, 11, 1, val) -#define WMI_ROAM_BTM_GET_DETECT_CANDIDATE_FROM_MISSING_BAND_IN_BTM_REQUEST(flags) WMI_GET_BITS(flags, 11, 1) -#define WMI_ROAM_BTM_SET_DEFER_BTM_SCAN_FLAG(flags, val) WMI_SET_BITS(flags, 12, 1, val) -#define WMI_ROAM_BTM_GET_DEFER_BTM_SCAN_FLAG(flags) WMI_GET_BITS(flags, 12, 1) +#define WMI_ROAM_BTM_SET_FORWARD_MBO_ASSOC_RETRY_BTM_REQUEST_TO_HOST(flags, val) WMI_SET_BITS(flags, 10, 1, val) +#define WMI_ROAM_BTM_GET_FORWARD_MBO_ASSOC_RETRY_BTM_REQUEST_TO_HOST(flags) WMI_GET_BITS(flags, 10, 1) /** WMI_ROAM_BTM_SET_NON_MATCHING_CNDS_ACTION definition: When BTM candidate is not matched with cache by WMI_ROAM_BTM_SET_CNDS_MATCH_CONDITION, determine what to do */ @@ -25005,15 +22625,6 @@ typedef struct { A_UINT32 roam_scan_period_after_inactivity; /* units = milliseconds */ /** roam full scan period value */ A_UINT32 roam_full_scan_period; /* units = milliseconds */ - /** roam_periodic_scan_interval: - * Timer value to periodically trigger the roaming process at - * set intervals during low RSSI roaming trigger. - * Low rssi trigger (Partial/full) --> - * 10s (partial) --> - * 20s (partial) --> - * 30s (partial) and so on. - */ - A_UINT32 roam_periodic_scan_interval; /* units = seconds */ } wmi_roam_scan_period_fixed_param; /** @@ -25037,8 +22648,6 @@ typedef struct { #define WMI_ROAM_SCAN_CHAN_LIST_TYPE_NONE 0x1 #define WMI_ROAM_SCAN_CHAN_LIST_TYPE_STATIC 0x2 #define WMI_ROAM_SCAN_CHAN_LIST_TYPE_DYNAMIC 0x3 -/* Restrict RCL to Neighbor Report and BTM request channels only */ -#define WMI_ROAM_SCAN_CHAN_LIST_TYPE_NEIGHBOR_REPORT 0x4 #define WMI_ROAM_SCAN_LIST_FLAG_FLUSH_STATIC 0x1 /* Flush static roam scan channel list in FW */ #define WMI_ROAM_SCAN_LIST_FLAG_FLUSH_DYNAMIC 0x2 /* Flush dynamic roam scan channel list in FW */ @@ -25098,7 +22707,6 @@ enum { WMI_AUTH_WPA3_SAE_SHA384, WMI_AUTH_FT_RSNA_SAE_SHA384, WMI_AUTH_FT_RSNA_PSK_SHA384, - WMI_AUTH_EPPKE, /* For 11BI */ }; typedef enum { @@ -25207,11 +22815,6 @@ typedef struct { #define WMI_ROAM_SET_SECURITY_SCORE_PERCENTAGE(value32, score_pcnt, security_index) \ WMI_SET_BITS(value32, (8 * (security_index)), 8, score_pcnt) -/* Boost the APs that belong to the same SMD as the current AP.*/ -#define WLAN_ROAM_SCORE_INTRA_SMD_INDEX 0 -#define WMI_ROAM_GET_INTRA_SMD_SCORE_PERCENTAGE(value32, index) WMI_GET_BITS(value32, (8 * (index)), 8) -#define WMI_ROAM_SET_INTRA_SMD_SCORE_PERCENTAGE(value32, score_pcnt, index) WMI_SET_BITS(value32, (8 * (index)), 8, score_pcnt) - /** best_rssi_threshold: Roamable AP RSSI equal or better than this threshold, full RSSI score 100. Units in dBm. good_rssi_threshold: Below this threshold, scoring linear percentage between rssi_good_pcnt and 100. Units in dBm. @@ -25487,16 +23090,6 @@ typedef struct { * considered for the candidates for which MCC will be formed. */ A_UINT32 mcc_score_factor_pcnt; - /* Scoring weightage for privacy support like 11bi */ - A_UINT32 privacy_weightage_pcnt; - /* uhr_weightage_pcnt: - * 11bn weightage out of total score in percentage. - */ - A_UINT32 uhr_weightage_pcnt; - /* smd_weightage_pcnt: - * give weightage to candidate based on SMD support. - */ - A_UINT32 smd_weightage_pcnt; } wmi_roam_cnd_scoring_param; typedef struct { @@ -25568,16 +23161,6 @@ typedef struct { * of the currently associated AP. */ A_UINT32 bg_rssi_threshold; - /** - * IEEE value for auth algorithm - * Authentication algorithm number = 3: - * Simultaneous Authentication of Equals (SAE) - * Authentication algorithm number = 8: - * IEEE 802.1X authentication - * Authentication algorithm number = 9: - * EPPKE authentication - */ - A_UINT32 auth_algo; } wmi_ap_profile; typedef struct { @@ -25594,10 +23177,7 @@ typedef struct { * Refer WLAN_ROAM_SCORE_MAX_BAND_INDEX for possible band_idx values. */ A_UINT32 band_idx; - /** - * The below band weight (2.4 GHz, 5 GHz, 6 GHz), RSSI, and CU factor_value - * and factor_score param values are configured by vendor. - */ + /** Below RSSI/CU factor_value & factor_score param values are configured by vendor */ A_UINT32 rssi_factor_value1; A_UINT32 rssi_factor_value2; A_UINT32 rssi_factor_value3; @@ -25612,9 +23192,6 @@ typedef struct { A_UINT32 cu_factor_value2; A_UINT32 cu_factor_score1; A_UINT32 cu_factor_score2; - A_UINT32 band_weight_2GHz; - A_UINT32 band_weight_5GHz; - A_UINT32 band_weight_6GHz; } wmi_roam_cnd_vendor_scoring_param; /** Support early stop roaming scanning when finding a strong candidate AP @@ -25868,7 +23445,6 @@ typedef struct { A_UINT32 no_ack_timeout; /* In msec. duration to wait before another SW retry made if no ack seen for previous frame */ A_UINT32 roam_candidate_validity_time; /* In msec. validity duration of each entry in roam cache. If the value is 0x0, this field should be disregarded. */ A_UINT32 roam_to_current_bss_disable; /* Disable roaming to current bss */ - A_UINT32 mlo_roam_partner_bringup_by_host; } wmi_roam_offload_tlv_param; @@ -26097,76 +23673,6 @@ typedef struct { wmi_mac_addr mac_addr; } wmi_roam_bss_info_param; -typedef struct { - A_UINT32 tlv_header; - /* These params are filled in the new design done for MLO roam - * optimization; only in roam abort cases Fw deletes partner links - * at the start of roam handoff itself. - * Host needs to take care of bringing up the partner link if - * roam fails based on deleted_ieee_link_id_bmap; - * deleted_ieee_link_id_bmap represents the ieee_link_id of the - * links which were deleted at the start of roam handoff. - * This is filled only for MLO and deleted_ieee_link_id_bmap = 0 - * means no link was deleted. - */ - A_UINT32 deleted_ieee_link_id_bmap; -} wmi_roam_partner_link_param; - -/* - * useful macros defined for flags field in wmi_vdev_repurpose_request_tlv_param */ -#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_GET_REQUEST_INACTIVE(flags) \ - WMI_GET_BITS(flags, 0, 1) -#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_SET_REQUEST_INACTIVE(flags, val) \ - WMI_SET_BITS(flags, 0, 1, val) -#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_GET_REQUEST_DISCONNECT(flags) \ - WMI_GET_BITS(flags, 1, 1) -#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_SET_REQUEST_DISCONNECT(flags, val) \ - WMI_SET_BITS(flags, 1, 1, val) -#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_GET_REQUEST_CONNECT(flags) \ - WMI_GET_BITS(flags, 2, 1) -#define WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_SET_REQUEST_CONNECT(flags, val) \ - WMI_SET_BITS(flags, 2, 1, val) - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_repurpose_request_tlv_param */ - A_UINT32 repurpose_vdev_id; /* repurposed vdev_id */ - /* flags - refer WMI_VDEV_REPURPOSE_REQ_TLV_FLAGS_GET and _SET macro - * BIT 0 - - * Host shall inactive link with sending WMI_MLO_LINK_SET_ACTIVE_CMDID - * before issue WMI_VDEV_UNIFIED_DISCONNECT_CMDID if the bit is set. - * BIT 1 - - * Host shall send WMI_VDEV_UNIFIED_DISCONNECT_CMDID on the - * repurpose_vdev_id if the bit is set. - * BIT 2 - - * Host shall send WMI_VDEV_UNIFIED_CONNECT_CMDID on the - * repurpose_vdev_id if the bit is set. - */ - A_UINT32 flags; - /* bassid: - * repurposed AP bssid, valid when BIT2 is set in flags - */ - wmi_mac_addr bssid; - /* mld_addr: - * repurposed AP mld address, valid when BIT2 is set in flags - */ - wmi_mac_addr mld_addr; - /* smd_addr: - * repurposed AP smd address, valid when BIT2 is set in flags - */ - wmi_mac_addr smd_addr; -} wmi_vdev_repurpose_request_tlv_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_repurpose_resp_cmd_fixed_param */ - A_UINT32 vdev_id; -} wmi_vdev_repurpose_resp_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_repurpose_response_tlv_param */ - A_UINT32 repurpose_vdev_id; /* repurposed vdev_id */ - A_UINT32 status; /* 0 is success */ -} wmi_vdev_repurpose_response_tlv_param; - /* roam_reason: bits 0-3 */ #define WMI_ROAM_REASON_INVALID 0x0 /** invalid reason. Do not interpret reason field */ #define WMI_ROAM_REASON_BETTER_AP 0x1 /** found a better AP */ @@ -26226,9 +23732,6 @@ typedef enum (((roam_reason) & WMI_ROAM_REQUEST_HOST_HW_MODE_CHANGE_MASK) >> \ WMI_ROAM_REQUEST_HOST_HW_MODE_CHANGE_SHIFT) -#define WMI_GET_ROAM_SMD_BSS_TRANSITION(roam_reason) WMI_GET_BITS(roam_reason, 16, 1) -#define WMI_SET_ROAM_SMD_BSS_TRANSITION(roam_reason, val) WMI_SET_BITS(roam_reason, 16, 1, val) - /* Bits 0-3: stores 4 LSbs of trigger reason. * Old host will get trigger reasons <= 15 from this bitfield. * Bit 7 will be 1 always to indicate that bits 8-15 are valid. @@ -26258,7 +23761,6 @@ typedef enum #define WMI_ROAM_NOTIF_SCAN_MODE_SUCCESS_WITH_HO_FAIL 0xb /** indicate that roaming scan mode is successful but cause disconnection and subsequent ** WMI_ROAM_REASON_HO_FAILED is event expected */ #define WMI_ROAM_NOTIF_SCAN_END 0xc /** indicate roam scan end, notif_params to be sent as WMI_ROAM_TRIGGER_REASON_ID */ -#define WMI_ROAM_NOTIF_ROAM_SMD_START 0xd /** indicate that SMD BSS transtion is started, notif_params1 to be sent as requested setup ieee links bitmap for target AP MLD */ /**whenever RIC request information change, host driver should pass all ric related information to firmware (now only support tsepc) * Once, 11r roaming happens, firmware can generate RIC request in reassoc request based on this information @@ -26340,14 +23842,8 @@ typedef struct { enum wlan_roam_invoke_reason { ROAM_INVOKE_REASON_UNDEFINED = 0, /* FW will use default parameters to do roam scan, ignore other parameters like WLM, etc. */ - - /* Neighbor Unreachable Detection */ - ROAM_INVOKE_REASON_NUD_FAILURE, - + ROAM_INVOKE_REASON_NUD_FAILURE, /* Neighbor Unreachable Detection */ ROAM_INVOKE_REASON_USER_SPACE, - - /* Trigger for Out-Of-Quality (OOQ) roaming */ - ROAM_INVOKE_REASON_PREDICTIVE, }; /** WMI_ROAM_INVOKE_CMD: command to invoke roaming forcefully @@ -26980,7 +24476,6 @@ typedef enum event_type_e { WOW_P2P_NOA_EVENT, /* 32 + 14 */ WOW_XGAP_EVENT, /* 32 + 15 */ WOW_PAGE_FAULT_EVENT, /* 32 + 16 */ - WOW_ACTION_FRAME_RECV_EVENT, /* 32 + 17 */ } WOW_WAKE_EVENT_TYPE; typedef enum wake_reason_e { @@ -27082,12 +24577,6 @@ typedef enum wake_reason_e { WOW_REASON_PF_BLOCKING_LAST_TIME, /* C2C scan report LPI AP detect or not event */ WOW_REASON_C2C_DETECT_EVENT, - /* wake up the host in case of TDLS packet reception */ - WOW_REASON_TDLS_PACKET_RX, - /* wake up the host when USD is enabled */ - WOW_REASON_USD, - /* wake up the host when MLO link switch happens */ - WOW_REASON_MLO_LINK_SWITCH_EVENT, /* add new WOW_REASON_ defs before this line */ @@ -27191,18 +24680,6 @@ typedef enum { /* WoW error if close to TBTT */ WMI_WOW_NON_ACK_REASON_CLOSE_TO_TBTT = 12, - - /* WoW error if platform not ready */ - WMI_WOW_NON_ACK_REASON_PLATFORM = 13, - - /* WoW error if resume n processs */ - WMI_WOW_NON_ACK_RESUME_IN_PROCESS = 14, - - /* WoW error UT command */ - WMI_WOW_NON_ACK_REASON_UNIT_TEST_CMD = 15, - - /* WoW error if MCC lite mode active */ - WMI_WOW_NON_ACK_REASON_MCC_LITE = 16, } WMI_WOW_NACK_STATUS; typedef struct { @@ -28042,22 +25519,6 @@ typedef struct { A_UINT32 req_type; } wmi_aggr_state_trig_event_fixed_param; -/* - * WMI_KEY_FIPS_STATUS - * - * Reported to the host in WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID via - * bits[4:5] of key_flags. Use WMI_KEY_FLAGS_FIPS_COMPLIANT_GET/SET macros. - */ -typedef enum { - WMI_KEY_FIPS_NOT_APPROVED = 1, - WMI_KEY_FIPS_APPROVED = 2, -} WMI_KEY_FIPS_STATUS; - -#define WMI_KEY_FLAGS_FIPS_COMPLIANT_GET(key_flags) \ - WMI_GET_BITS(key_flags, 4, 2) -#define WMI_KEY_FLAGS_FIPS_COMPLIANT_SET(key_flags, val) \ - WMI_SET_BITS(key_flags, 4, 2, val) - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_install_key_complete_event_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ @@ -28066,19 +25527,7 @@ typedef struct { wmi_mac_addr peer_macaddr; /** key index */ A_UINT32 key_ix; - /** key flags — bit definitions (see KEY_USAGE enum in wmi.h): - * bit[0]: key usage type - * 0 = PAIRWISE_USAGE — unicast/pairwise key - * 1 = GROUP_USAGE — broadcast/multicast group key - * bit[1]: TX_USAGE (0x02) — default Tx key (static WEP only) - * bit[2]: PMK_USAGE (0x04) — PMK cache entry - * bit[3]: LTF_USAGE (0x08) — LTF key seed - * bits[4:5]: FIPS compliance status (WMI_KEY_FIPS_STATUS enum) - * 1 = WMI_KEY_FIPS_NOT_APPROVED (WEP, TKIP, WAPI) - * 2 = WMI_KEY_FIPS_APPROVED (AES-CCM/GCM/CMAC/GMAC) - * Use WMI_KEY_FLAGS_FIPS_COMPLIANT_GET/SET to access. - * bits[6:31]: reserved - */ + /** key flags */ A_UINT32 key_flags; /** Event status */ A_UINT32 status; @@ -28757,10 +26206,6 @@ typedef struct { #define WMI_MAX_VENDOR_OUI_ACTION_SUPPORTED_PER_ACTION 10 #define WMI_MAX_VENDOR_OUI_DATA_LENGTH 20 -#define WMI_MAX_EXT_ACTION_ID_OUI_COUNT_FOR_ALLOW_DISALLOW_NSS 30 -#define WMI_MAX_EXT_ACTION_ID_OUI_COUNT_FOR_UL_TX_BEAMFORMER 30 -#define WMI_MAX_VENDOR_OUI_EXT_DATA_LENGTH 64 - typedef enum { WMI_VENDOR_OUI_ACTION_CONNECTION_1X1 = 0, /* Connect in 1X1 only */ @@ -28837,42 +26282,9 @@ typedef enum */ WMI_VENDOR_OUI_ACTION_AUTH_ASSOC_6MBPS_2GHZ = 17, - /* - * Disable dynamic SMPS if OUI matches - */ - WMI_VENDOR_OUI_ACTION_DISABLE_DYNAMIC_SMPS = 18, - - /* - * Keep sending qos null frame on P2P interface when final bmiss is - * detected, if specific vendor OUI matches. - * If an ACK is received, suppress reporting the final beacon miss - * to the host to avoid triggering a disconnect. - */ - WMI_VENDOR_OUI_ACTION_FORCE_TX_NULL_FRAME_ON_P2P = 19, - /* Add any action before this line */ - WMI_VENDOR_OUI_ACTION_MAX_ACTION_ID, - - - /* - * 0-127 is reserved for action IDs for which the data is static. - * Size of the data is fixed and is not configurable. - */ - - /* Dynamic length OUIs starts below */ - - /* connection in 4 x 4 */ - WMI_VENDOR_OUI_ACTION_ALLOW_NSS_GREATER_THAN_2 = 128, - - /* connection in 2 x 2 */ - WMI_VENDOR_OUI_ACTION_DISALLOW_NSS_GREATER_THAN_2 = 129, - - WMI_VENDOR_OUI_ACTION_ENABLE_UL_TX_BEAMFORMER = 130, - - - /* Add any new dynamic length action ID before this line */ - WMI_VENDOR_OUI_ACTION_MAX_EXT_ACTION_ID + WMI_VENDOR_OUI_ACTION_MAX_ACTION_ID } wmi_vendor_oui_action_id; typedef struct { @@ -28882,25 +26294,6 @@ typedef struct { A_UINT32 total_num_vendor_oui; /* total number of OUI present in ini for all actions. ** For first command, this value will be used for allocating memory in FW accordingly */ A_UINT32 num_vendor_oui_ext; /* the number of wmi_vendor_oui_ext for action_id */ - /* total_num_vendor_oui_ext: - * Max possible OUIs which HOST can support for all the extended - * ACTION IDs: WMI_MAX_EXT_ACTION_ID_OUI_COUNT_FOR_*. - * The max ext action id should be less than - * WMI_VENDOR_OUI_ACTION_MAX_EXT_ACTION_ID and greater than - * WMI_VENDOR_OUI_ACTION_MAX_ACTION_ID - */ - A_UINT32 total_num_vendor_oui_ext; - /* num_vendor_oui_ext2: - * The number of wmi_vendor_oui_ext_2 for action_id - * (The number of OUIs that HOST could accomodate in current WMI cmd) - */ - A_UINT32 num_vendor_oui_ext2; - /* - * More data indicates that for this action_id, there are more data - * pending to be sent via the next WMI command. - */ - A_UINT32 more_data; - /* followed by TLVs, an array of structure of type wmi_vendor_oui_ext ** wmi_vendor_oui_ext vendor_oui_ext[num_vendor_oui_ext]; */ @@ -28943,50 +26336,26 @@ typedef struct { } wmi_pdev_set_rx_filter_promiscuous_cmd_fixed_param; typedef enum { - WMI_BEACON_INFO_PRESENCE_OUI_EXT = 1 << 0, - WMI_BEACON_INFO_PRESENCE_MAC_ADDRESS = 1 << 1, - WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_NSS = 1 << 2, - WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_HT = 1 << 3, - WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_VHT = 1 << 4, - WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_BAND = 1 << 5, - WMI_BEACON_INFO_PRESENCE_EXCLUSIVE_MAC_ADDRESS = 1 << 6, + WMI_BEACON_INFO_PRESENCE_OUI_EXT = 1 << 0, + WMI_BEACON_INFO_PRESENCE_MAC_ADDRESS = 1 << 1, + WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_NSS = 1 << 2, + WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_HT = 1 << 3, + WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_VHT = 1 << 4, + WMI_BEACON_INFO_PRESENCE_AP_CAPABILITY_BAND = 1 << 5, } wmi_beacon_info_presence_items; typedef struct _wmi_vendor_oui_ext { A_UINT32 tlv_header; - - /* length of data in bytes for this OUI including index byte */ - A_UINT32 buf_data_length; - - /* see enum wmi_beacon_info_presence_items */ - A_UINT32 info_presence_bit_mask; - - A_UINT32 oui_header_length; /* either 3 or 5 bytes */ - - /* oui_data_length: - * Length of oui_data to compare in beacon which follows OUI header. - * Max length is capped to WMI_MAX_VENDOR_OUI_DATA_LENGTH bytes, - * for action ids < 127. - * Max length is capped to WMI_MAX_VENDOR_OUI_EXT_DATA_LENGTH bytes, - * for action ids > 127. - */ - A_UINT32 oui_data_length; - - /* mac_address_length: - * MAC address length in bytes - * (This value will always be 6, but is explicitly specified for sake - * of uniformity and completeness). - */ - A_UINT32 mac_address_length; - + A_UINT32 buf_data_length; /* length of data in bytes for this OUI including index byte */ + A_UINT32 info_presence_bit_mask; /* see enum wmi_beacon_info_presence_items */ + A_UINT32 oui_header_length; /* either 3 or 5 bytes */ + A_UINT32 oui_data_length; /* length of oui_data to compare in beacon which follows OUI header. Max length is capped to WMI_MAX_VENDOR_OUI_DATA_LENGTH bytes */ + A_UINT32 mac_address_length; /* MAC address length in bytes + ** (This value will always be 6, + ** but is explicitly specified for sake + ** of uniformity and completeness). + */ A_UINT32 capability_data_length; /* length of capability in bytes */ - - /* exclusive_mac_address_length: - * Exclusive MAC address length in bytes - * (This value will always be 6, but is explicitly specified for sake - * of uniformity and completeness). - */ - A_UINT32 exclusive_mac_address_length; } wmi_vendor_oui_ext; #define WMI_INFO_CAPABILITY_NSS_MASK 0x0f @@ -29370,66 +26739,9 @@ typedef enum WLAN_COEX_EVENT { typedef struct { A_UINT32 tlv_header; - A_UINT32 coex_profile_evt; /* uses the enum values from WLAN_COEX_EVENT */ + A_UINT32 coex_profile_evt; //uses the enum values from WLAN_COEX_EVENT } wmi_coex_bt_activity_event_fixed_param; -typedef struct { - A_UINT32 tlv_header; -} wmi_coex_policy_stats_cmd_fixed_param; - -#define WMI_COEX_POLICY_STATS_GET_BTC_STATE(coex_stats) \ - WMI_GET_BITS(coex_stats, 0, 2) -#define WMI_COEX_POLICY_STATS_SET_BTC_STATE(coex_stats, value) \ - WMI_SET_BITS(coex_stats, 0, 2, value) - -#define WMI_COEX_POLICY_STATS_GET_UWB_STATE(coex_stats) \ - WMI_GET_BITS(coex_stats, 2, 1) -#define WMI_COEX_POLICY_STATS_SET_UWB_STATE(coex_stats, value) \ - WMI_SET_BITS(coex_stats, 2, 1, value) - -#define WMI_COEX_POLICY_STATS_GET_MWS_STATE(coex_stats) \ - WMI_GET_BITS(coex_stats, 3, 1) -#define WMI_COEX_POLICY_STATS_SET_MWS_STATE(coex_stats, value) \ - WMI_SET_BITS(coex_stats, 3, 1, value) - -#define WMI_COEX_POLICY_STATS_GET_OCS_ALGO_DC(coex_stats) \ - WMI_GET_BITS(coex_stats, 8, 8) -#define WMI_COEX_POLICY_STATS_SET_OCS_ALGO_DC(coex_stats, value) \ - WMI_SET_BITS(coex_stats, 8, 8, value) - -#define WMI_COEX_POLICY_STATS_GET_OCS_NON_WLAN_DC(coex_stats) \ - WMI_GET_BITS(coex_stats, 16, 8) -#define WMI_COEX_POLICY_STATS_SET_OCS_NON_WLAN_DC(coex_stats, value) \ - WMI_SET_BITS(coex_stats, 16, 8, value) - -typedef struct { - A_UINT32 tlv_header; - A_UINT32 mon_period; /* milliseconds units */ - /* Following is the definition for bitfields within the coex_stats word: - * bits 1:0 --> Indicates BTC_STATE (0 - Freerun, 1 - OCS, 3 - Inactive). - * bit 2 --> Indicates UWB_STATE (0 - Inactive, 1 - Active conflict). - * bit 3 --> Indicates MWS_STATE (0 - Inactive, 1 - Active conflict). - * bits 15:8 --> Indicates percentage of the time coex chose OCS policy. - * (Ranges from 0 to 100.) - * bits 23:16 --> Indicates percentage of the time DUT is off channel due - * to OCS policy. (Ranges from 0 to 100.) - */ - union { - A_UINT32 coex_stats; - struct { - A_UINT32 btc_state: 2, /* bits 1:0 */ - uwb_state: 1, /* bit 2 */ - mws_state: 1, /* bit 3 */ - reserved1: 4, /* bits 7:4 */ - ocs_algo_dc: 8, /* bits 15:8 */ - ocs_non_wlan_dc: 8, /* bits 23:16 */ - reserved2: 8; /* bits 31:24 */ - }; - }; - A_UINT32 num_data_bytes; -} wmi_coex_policy_stats_event_fixed_param; - - enum wmm_ac_downgrade_policy { WMM_AC_DOWNGRADE_DEPRIO, WMM_AC_DOWNGRADE_DROP, @@ -29597,23 +26909,7 @@ typedef struct { * 0 - need check sub channel marking * 1 - full bandwidth need put to NOL * Refer to WMI_RADAR_FLAGS_FULL_BW_NOL_GET and _SET macros - * - * Bits 1-16: - * RADAR TYPE field (currently reserved for future use) - * When implemented, this field will indicate the type of - * radar detected, and also the domain. - * For example, a value of 0x4001 means domain = 4 and radar type = 1. - * Refer to WMI_RADAR_FLAGS_RADAR_TYPE_GET and _SET macros. - * - * Bits 17-24: - * RADAR RSSI in dBm in the range of -128 to +127. - * This 8-bit value is interpreted as a twos-complement signed number - * (so for example, 0x80 = -128, 0x0 = 0, and 0x7f = 127). - * This bit field is valid only if the - * WMI_SERVICE_RADAR_FLAGS_RSSI_DBM_SUPPORT - * wmi service flag is set. - * - * [25:31] reserved + * [1:31] reserved */ A_UINT32 flags; } WMI_RADAR_FLAGS; @@ -29621,12 +26917,6 @@ typedef struct { #define WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS 0 #define WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS 1 -#define WMI_RADAR_FLAGS_RADAR_TYPE_BITPOS 1 -#define WMI_RADAR_FLAGS_RADAR_TYPE_NUM_BITS 16 - -#define WMI_RADAR_FLAGS_RSSI_DBM_BITPOS 17 -#define WMI_RADAR_FLAGS_RSSI_DBM_NUM_BITS 8 - #define WMI_RADAR_FLAGS_FULL_BW_NOL_GET(flag) \ WMI_GET_BITS(flag, \ WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS, \ @@ -29636,176 +26926,6 @@ typedef struct { WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS, \ WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS, val) -#define WMI_RADAR_FLAGS_RADAR_TYPE_GET(flag) \ - WMI_GET_BITS(flag, \ - WMI_RADAR_FLAGS_RADAR_TYPE_BITPOS, \ - WMI_RADAR_FLAGS_RADAR_TYPE_NUM_BITS) -#define WMI_RADAR_FLAGS_RADAR_TYPE_SET(flag, val) \ - WMI_SET_BITS(flag, \ - WMI_RADAR_FLAGS_RADAR_TYPE_BITPOS, \ - WMI_RADAR_FLAGS_RADAR_TYPE_NUM_BITS, val) - -#define WMI_RADAR_FLAGS_RSSI_DBM_GET(flag) \ - ((A_INT8)WMI_GET_BITS(flag, \ - WMI_RADAR_FLAGS_RSSI_DBM_BITPOS, \ - WMI_RADAR_FLAGS_RSSI_DBM_NUM_BITS)) -#define WMI_RADAR_FLAGS_RSSI_DBM_SET(flag, val) \ - WMI_SET_BITS(flag, \ - WMI_RADAR_FLAGS_RSSI_DBM_BITPOS, \ - WMI_RADAR_FLAGS_RSSI_DBM_NUM_BITS, val) - -/* Bitfield layout constants */ -#define WMI_RADAR_DOMAIN_SHIFT 12 -#define WMI_RADAR_DOMAIN_MASK 0xF000 -#define WMI_RADAR_TYPE_MASK 0x0FFF - -/* Helper Macros */ -#define WMI_MAKE_RADAR_TYPE(domain, type) \ - (((domain) << WMI_RADAR_DOMAIN_SHIFT) | ((type) & WMI_RADAR_TYPE_MASK)) - -#define WMI_GET_RADAR_DOMAIN(radar_type) \ - (((radar_type) & WMI_RADAR_DOMAIN_MASK) >> WMI_RADAR_DOMAIN_SHIFT) - -#define WMI_GET_RADAR_TYPE(radar_type) \ - ((radar_type) & WMI_RADAR_TYPE_MASK) - -#define WMI_IS_RADAR_DOMAIN(radar_type, domain) \ - (GET_RADAR_DOMAIN(radar_type) == (domain)) - -/* Regulatory Domain Codes (4 bits = 0-15) */ -#define WMI_RADAR_DOMAIN_FCC 0x0 /* United States */ -#define WMI_RADAR_DOMAIN_ETSI_301 0x1 /* Europe EN 301 893 */ -#define WMI_RADAR_DOMAIN_ETSI_302 0x2 /* Europe EN 302 502 */ -#define WMI_RADAR_DOMAIN_CHINA 0x3 /* China */ -#define WMI_RADAR_DOMAIN_KOREA 0x4 /* Korea */ -#define WMI_RADAR_DOMAIN_JAPAN_W53 0x5 /* Japan W53 band */ -#define WMI_RADAR_DOMAIN_JAPAN_W56 0x6 /* Japan W56 band */ -#define WMI_RADAR_DOMAIN_JAPAN_W564 0x7 /* Japan W56.4 band */ -#define WMI_RADAR_DOMAIN_UNDEFINED 0xF /* Undefined/Unknown */ -/* Reserved for future use: 0x8-0xE */ - -/* Radar Type Codes within each domain (12 bits = 0-4095) */ -/* ===== FCC (United States) Radar Types ===== */ -#define WMI_DFS_RADAR_FCC_TYPE_0 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x001) -#define WMI_DFS_RADAR_FCC_TYPE_1 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x002) -#define WMI_DFS_RADAR_FCC_TYPE_2 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x004) -#define WMI_DFS_RADAR_FCC_TYPE_3 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x008) -#define WMI_DFS_RADAR_FCC_TYPE_4 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x010) -#define WMI_DFS_RADAR_FCC_TYPE_5 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x020) -#define WMI_DFS_RADAR_FCC_TYPE_6 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_FCC, 0x040) - -/* ===== ETSI EN 301 893 Radar Types ===== */ -#define WMI_DFS_RADAR_ETSI301_TYPE_1 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x001) -#define WMI_DFS_RADAR_ETSI301_TYPE_2 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x002) -#define WMI_DFS_RADAR_ETSI301_TYPE_3 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x004) -#define WMI_DFS_RADAR_ETSI301_TYPE_4 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x008) -#define WMI_DFS_RADAR_ETSI301_TYPE_52 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x010) -#define WMI_DFS_RADAR_ETSI301_TYPE_62 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x020) -#define WMI_DFS_RADAR_ETSI301_TYPE_1_2 \ - /* Combined Type 1+2 */ \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x003) -#define WMI_DFS_RADAR_ETSI301_TYPE_1_2_6 \ - /* Combined Type 1+2+6 */ \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_301, 0x023) - -/* ===== ETSI EN 302 502 Radar Types ===== */ -#define WMI_DFS_RADAR_ETSI302_TYPE_1 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x001) -#define WMI_DFS_RADAR_ETSI302_TYPE_2 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x002) -#define WMI_DFS_RADAR_ETSI302_TYPE_3 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x004) -#define WMI_DFS_RADAR_ETSI302_TYPE_4 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x008) -#define WMI_DFS_RADAR_ETSI302_TYPE_5 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x010) -#define WMI_DFS_RADAR_ETSI302_TYPE_6 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x020) -#define WMI_DFS_RADAR_ETSI302_TYPE_1_2 \ - /* Combined Type 1+2 */ \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_ETSI_302, 0x003) - -/* ===== China Radar Types ===== */ -#define WMI_DFS_RADAR_CHN_TYPE_1 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x001) -#define WMI_DFS_RADAR_CHN_TYPE_2 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x002) -#define WMI_DFS_RADAR_CHN_TYPE_3 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x004) -#define WMI_DFS_RADAR_CHN_TYPE_4 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x008) -#define WMI_DFS_RADAR_CHN_TYPE_5 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x010) -#define WMI_DFS_RADAR_CHN_TYPE_6 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x020) -#define WMI_DFS_RADAR_CHN_TYPE_1_2 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x003) /* Combined Type 1+2 */ -#define WMI_DFS_RADAR_CHN_TYPE_1_2_6 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x023) /* Combined Type 1+2+6 */ -#define WMI_DFS_RADAR_CHN_TYPE_3_4 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_CHINA, 0x00C) /* Combined Type 3+4 */ - -/* ===== Korea Radar Types ===== */ -#define WMI_DFS_RADAR_KOR_TYPE_1 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_KOREA, 0x001) -#define WMI_DFS_RADAR_KOR_TYPE_2 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_KOREA, 0x002) -#define WMI_DFS_RADAR_KOR_TYPE_3 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_KOREA, 0x004) -#define WMI_DFS_RADAR_KOR_TYPE_4 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_KOREA, 0x008) - -/* ===== Japan W53 Band Radar Types ===== */ -#define WMI_DFS_RADAR_JAP_W53_FIXED_PULSE_1 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W53, 0x001) -#define WMI_DFS_RADAR_JAP_W53_FIXED_PULSE_2 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W53, 0x002) -#define WMI_DFS_RADAR_JAP_W53_VAR_PULSE_3 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W53, 0x004) -#define WMI_DFS_RADAR_JAP_W53_VAR_PULSE_4 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W53, 0x008) - -/* ===== Japan W56 Band Radar Types ===== */ -#define WMI_DFS_RADAR_JAP_W56_FIXED_PULSE_1 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x001) -#define WMI_DFS_RADAR_JAP_W56_FIXED_PULSE_2 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x002) -#define WMI_DFS_RADAR_JAP_W56_FIXED_PULSE_3 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x004) -#define WMI_DFS_RADAR_JAP_W56_VAR_PULSE_4 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x008) -#define WMI_DFS_RADAR_JAP_W56_VAR_PULSE_5 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x010) -#define WMI_DFS_RADAR_JAP_W56_VAR_PULSE_6 \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x020) -#define WMI_DFS_RADAR_JAP_W56_CHIRP \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x040) -#define WMI_DFS_RADAR_JAP_W56_FIXED_PULSE_1_2 \ - /* Combined Type 1+2 */ \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W56, 0x003) - -/* ===== Japan W56.4 Band Radar Types ===== */ -#define WMI_DFS_RADAR_JAP_W564_HOPPING \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_JAPAN_W564, 0x001) - -/* ===== Undefined/Unknown ===== */ -#define WMI_DFS_RADAR_TYPE_UNDEF \ - WMI_MAKE_RADAR_TYPE(WMI_RADAR_DOMAIN_UNDEFINED, 0xFFF) - - typedef enum { OCAC_COMPLETE = 0, OCAC_ABORT, @@ -30050,32 +27170,13 @@ typedef struct { typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tdls_peer_update_cmd_fixed_param */ - A_UINT32 tlv_header; + A_UINT32 tlv_header; /** unique id identifying the VDEV */ - A_UINT32 vdev_id; + A_UINT32 vdev_id; /** peer MAC address */ - wmi_mac_addr peer_macaddr; + wmi_mac_addr peer_macaddr; /** new TDLS state for peer (wmi_tdls_peer_state) */ - A_UINT32 peer_state; - /** need_nss_conf: - * only set to 1 when this TDLS peer is required to operating - * in particular HW mode NSS - */ - A_UINT32 need_nss_conf; - /* preferred_tx_nss: - * for peering state, it means advertised nss, - * for connected state, it means final negotiated nss. - * 1 ~ n: 1ss ~ nss - */ - A_UINT32 preferred_tx_nss; - /* preferred_rx_nss: - * for peering state, it means advertised nss, - * for connected state, it means final negotiated nss. - * 1 ~ n: 1ss ~ nss - */ - A_UINT32 preferred_rx_nss; - - + A_UINT32 peer_state; /* The TLV for wmi_tdls_peer_capabilities will follow. * wmi_tdls_peer_capabilities peer_caps; */ @@ -30137,8 +27238,6 @@ enum wmi_tdls_peer_notification { WMI_TDLS_PEER_DISCONNECTED, /** TDLS/BT role change notification for connection tracker */ WMI_TDLS_CONNECTION_TRACKER_NOTIFICATION, - /** resp to WMI_TDLS_PEER_UPDATE_CMDID as host requested */ - WMI_TDLS_PEER_UPDATE_RESP, }; enum wmi_tdls_peer_reason { @@ -30168,8 +27267,6 @@ enum wmi_tdls_peer_reason { WMI_TDLS_SCAN_STARTED_EVENT, /** TDLS module received a scan complete event, TDLS connection tracker needs to handle this */ WMI_TDLS_SCAN_COMPLETED_EVENT, - /** TDLS max supported operating NSS in current HW mode */ - WMI_TDLS_OPERATING_NSS_CONF_EVENT, }; /* WMI_TDLS_PEER_EVENTID */ @@ -30184,10 +27281,6 @@ typedef struct { A_UINT32 peer_reason; /** unique id identifying the VDEV */ A_UINT32 vdev_id; - /** operating TX NSS 1 ~ n: 1ss ~ nss */ - A_UINT32 tx_nss; - /** operating RX NSS 1 ~ n: 1ss ~ nss */ - A_UINT32 rx_nss; } wmi_tdls_peer_event_fixed_param; /* NOTE: wmi_vdev_mcc_bcn_intvl_change_event_fixed_param would be deprecated. Please @@ -30536,8 +27629,6 @@ typedef enum { WMI_STA_SMPS_PARAM_DTIM_1CHRX_ENABLE = 5, /** Enable/Disable dynamic bw feature */ WMI_STA_SMPS_PARAM_DYNAMIC_BW_SWITCH = 6, - /** Enable/Disable dynamic mode sw feature */ - WMI_STA_SMPS_PARAM_DYNAMIC_MODE_SWITCH = 7, } wmi_sta_smps_param; typedef struct { @@ -30668,8 +27759,8 @@ typedef struct #define LPI_IE_BITMAP_CHRE_RADIO_CHAIN 0x01000000 /* include radio chain and RSSI per chain information if this bit is set - for CHRE */ #define LPI_IE_BITMAP_CHRE_SEC_MODE_MRSNO_WIFI6 0x02000000 /* include MRSNO IE's sec_mode information for WiFi6 if this bit is set - for CHRE */ #define LPI_IE_BITMAP_CHRE_SEC_MODE_MRSNO_WIFI7 0x04000000 /* include MRSNO IE's sec_mode information for WiFi7 if this bit is set - for CHRE */ -#define LPI_IE_BITMAP_INTERWORKING_IE_VENUE_INFO 0x08000000 /* interworking IE venue info (2 bytes) will be filled when this bit is enabled */ +/* 0x08000000 is unused / available */ #define LPI_IE_BITMAP_CHRE_ESS 0x10000000 /* ESS capability info for CHRE */ #define LPI_IE_BITMAP_CHRE_SEC_MODE 0x20000000 /* Security capability info for CHRE */ @@ -30740,11 +27831,6 @@ typedef struct { A_UINT32 ie_len; /** Scan control flags extended (see WMI_SCAN_FLAG_EXT_xxx) */ A_UINT32 scan_ctrl_flags_ext; - /** - * dwell time in msec on active 5 GHz channels. - * If 0, dwell_time_active is used for 5 GHz channels as well. - */ - A_UINT32 dwell_time_active_5ghz; /** * TLV (tag length value) parameters follow the scan_cmd @@ -30756,388 +27842,6 @@ typedef struct { */ } wmi_lpi_start_scan_cmd_fixed_param; - -/* WMI_LPI_SCAN_RESULT_EVENTID_V2 - * TLV (tag length value) parameters follow the fixed_param structure: - * wmi_lpi_scan_result_ind_fixed_param fixed_param; - * uint32_t scanned_freq_list[]; - * wmi_lpi_ap_info_t ap_array[]; - */ - -/** - * Maximum number of AP entries accumulated in LOWI per scan - * (across all batched events). - * FW sends ~7 APs per WMI_LPI_RESULT_EVENTID event - * (limited by LPI_RESULT_EVENT_SIZE=1200 bytes); - * LOWI accumulates batches until scan_is_completed is set. - */ -#define WMI_LPI_MAX_AP_NUM 35 -/** Number of radio chains reported per AP in rssi_chain[] */ -#define WMI_LPI_MAX_RADIO_CHAIN 5 -/** Number of A_UINT32 words used to pack the 12-byte MSAP field */ -#define WMI_LPI_MAX_MSAP_LEN_W 3 - -/** - * wmi_lpi_ap_info_t - Per-AP scan record; element type for TLV #3 - * (WMITLV_TAG_ARRAY_STRUC). - * Since this is a TLV struct (starts with tlv_header), new fields can be - * appended at the end in future versions without breaking older receivers. - * - * ap_info field layout: - * bits [3:0] = ap_flags: cur_connected[0], wifi_802_11_mc[1], - * msap_supported[2], is_active[3] - * bits [16:4] = valid_mask (13 bits); - * indicates which optional fields are present - * bits [23:17] = reserved (must be set to 0 by sender; ignored by receiver) - * bits [31:24] = phy_mode (8 bits); contains a WLAN_PHY_MODE value - * (refer enum WLAN_PHY_MODE defined in wlan_defs.h) - * - * scan_info field layout: - * bits [7:0] = scan_module_id; - * identifies which scan module produced this record: - * 0 = WLS_SCAN_MODID_ANY (any/default) - * 1 = WLS_SCAN_MODID_MGMT_RX_HDR_EXTSCAN (extscan module) - * 2 = WLS_SCAN_MODID_MGMT_RX_HDR_ENLO (ENLO module) - * bits [15:8] = scan_id - * bits [23:16] = flags - * bits [31:24] = scan_cache - * - * ESS_and_SEC_info field layout: - * bits [15:0] = ess - * bits [23:16] = sec_mode; - * bitmask of security modes (WLS_AP_SECUTIRY_MODE_* values): - * 0x00=UNKNOWN - * 0x01=OPEN - * 0x02=WEP - * 0x04=PSK(WPA/WPA2) - * 0x08=EAP(Enterprise) - * 0x10=WPA3_SAE - * 0x20=WPA3_SuiteB - * 0x40=WPA3_OWE - * bits [31:24] = reserved - * - * MCS_and_NSS_info field layout: - * bits [7:0] = tx_nss - * bits [15:8] = tx_mcs - * bits [23:16] = rx_nss - * bits [31:24] = rx_mcs - */ - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_lpi_ap_info_t */ - A_UINT32 tlv_header; - /** 6-byte BSSID; uses existing wmi_mac_addr type */ - wmi_mac_addr bssid; - /** ssid: - * length + up to 32 bytes packed as 8 x A_UINT32; - * uses existing wmi_ssid type - */ - wmi_ssid ssid; - /** Primary channel frequency in MHz */ - A_UINT32 frequency; - /** RSSI in dBm */ - A_INT32 rssi; - /** Packed: - * ap_flags[3:0] | - * valid_mask[16:4] | - * phy_mode[31:24] (WLAN_PHY_MODE value); - * use WMI_LPI_AP_INFO_* macros - */ - A_UINT32 ap_info; - /** Actual dwell time on this channel in milliseconds */ - A_UINT32 dwell_time_ms; - /** TSF offset: local TSF minus AP TSF */ - A_UINT32 tsf_offset; - /** Packed: - * scan_module_id[7:0] | - * scan_id[15:8] | - * flags[23:16] | - * scan_cache[31:24]; use WMI_LPI_SCAN_INFO_* macros - */ - A_UINT32 scan_info; - /** Packed: - * ess[15:0] | - * sec_mode[23:16]; use WMI_LPI_ESS_SEC_* macros - */ - A_UINT32 ESS_and_SEC_info; - /** Packed: - * tx_nss[7:0] | - * tx_mcs[15:8] | - * rx_nss[23:16] | - * rx_mcs[31:24]; use WMI_LPI_MCS_NSS_* macros - */ - A_UINT32 MCS_and_NSS_info; - /** Bitmask of active radio chains used to discover this AP */ - A_UINT32 radio_chain_mask; - /** RSSI per radio chain in dBm; 0 if chain not active */ - A_INT32 rssi_chain[WMI_LPI_MAX_RADIO_CHAIN]; - /** TX power in dBm; valid when WMI_LPI_VALID_TX_POWER set in valid_mask */ - A_UINT32 tx_power; - /** TX rate in Mbps; valid when WMI_LPI_VALID_TX_RATE set in valid_mask */ - A_UINT32 tx_rate; - /** - * TSF timestamp bits [31:0]; - * valid when WMI_LPI_VALID_TSF set in valid_mask - */ - A_UINT32 tsf_lo; - /** - * TSF timestamp bits [63:32]; - * valid when WMI_LPI_VALID_TSF set in valid_mask - */ - A_UINT32 tsf_hi; - /** Age of measurement in milliseconds; valid when WMI_LPI_VALID_AGE set in valid_mask */ - A_UINT32 age; - /** - * MSAP data: 12 bytes packed as 3 x A_UINT32; - * valid when WMI_LPI_VALID_MSAP set in valid_mask - */ - A_UINT32 msap[WMI_LPI_MAX_MSAP_LEN_W]; - /** - * Band center frequency 1 in MHz; - * valid when WMI_LPI_VALID_CNT_FREQ1 set in valid_mask - */ - A_UINT32 band_center_freq_1; - /** - * Band center frequency 2 in MHz; - * valid when WMI_LPI_VALID_CNT_FREQ2 set in valid_mask - */ - A_UINT32 band_center_freq_2; - /** Venue info per IEEE 802.11u Table 9-62: - * bits[7:0] = venue_type (e.g. 0=unspecified, 1=assembly, 2=business, - * 3=educational, 4=factory, 5=institutional, 6=mercantile, - * 7=residential, 8=storage, 9=utility, 10=vehicular, - * 11=outdoor) - * bits[15:8] = venue_info - * (venue group/subtype per IEEE 802.11u Table 9-62) - * valid when WMI_LPI_VALID_VENUE set in valid_mask */ - A_UINT32 venue_type_and_info; -} wmi_lpi_ap_info_t; - - -/** - * wmi_lpi_scan_result_ind_fixed_param - - * Fixed params for TLV #1 of WMI_LPI_SCAN_RESULT_EVENTID_V2. - * Tag: WMITLV_TAG_STRUC_wmi_lpi_scan_result_ind_fixed_param. - * TLV #2 (freq_list) and TLV #3 (ap_array) follow this struct - * in the event buffer. - * Scan completion is signalled by WMI_LPI_STATUS_EVENTID (unchanged); - */ -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_lpi_scan_result_ind_fixed_param */ - A_UINT32 tlv_header; - /** - * Request ID echoed from the triggering scan request. - * For snoop scans, WLS substitutes the snoop subscriber's req_id. - */ - A_UINT32 req_id; - /** - * Country code from scanned_freq_list: 4 ASCII bytes packed little-endian - */ - A_UINT32 country_code; - /** Scan type performed: 0=passive, 1=active, 2=active+passive DFS */ - A_UINT32 scan_type_performed; - /** - * Radio chain preference used for this scan: - * 0=default, 1=low-latency, 2=low-power, 3=hi-accuracy - */ - A_UINT32 radio_chain_pref; -/** - * TLV (tag length value) parameters follow the fixed_param structure: - * A_UINT32 freq_list[]; // scanned frequencies in MHz; one per word - * wmi_lpi_ap_info_t ap_array[]; // per-AP scan records; - * // max WMI_LPI_MAX_AP_NUM entries - */ -} wmi_lpi_scan_result_ind_fixed_param; - -/* ---- ap_info field bit positions ---- */ -#define WMI_LPI_AP_INFO_CUR_CONNECTED_S 0 -#define WMI_LPI_AP_INFO_WIFI_MC_S 1 -#define WMI_LPI_AP_INFO_MSAP_SUPPORTED_S 2 -#define WMI_LPI_AP_INFO_IS_ACTIVE_S 3 -/* 13-bit valid_mask starts at bit 4 */ -#define WMI_LPI_AP_INFO_VALID_MASK_S 4 -/* 7-bit reserved field at bits [23:17] */ -#define WMI_LPI_AP_INFO_RESERVED_S 17 -/* 8-bit phy_mode at bits [31:24] */ -#define WMI_LPI_AP_INFO_PHY_MODE_S 24 - -/* ap_info: cur_connected (bit 0) */ -#define WMI_LPI_AP_INFO_SET_CUR_CONNECTED(pap, val) do { \ - (pap)->ap_info |= (((val) & 0x1) << WMI_LPI_AP_INFO_CUR_CONNECTED_S); \ - } while (0) -#define WMI_LPI_AP_INFO_GET_CUR_CONNECTED(pap) \ - (((pap)->ap_info >> WMI_LPI_AP_INFO_CUR_CONNECTED_S) & 0x1) - -/* ap_info: wifi_802_11_mc (bit 1) */ -#define WMI_LPI_AP_INFO_SET_WIFI_MC(pap, val) do { \ - (pap)->ap_info |= (((val) & 0x1) << WMI_LPI_AP_INFO_WIFI_MC_S); \ - } while (0) -#define WMI_LPI_AP_INFO_GET_WIFI_MC(pap) \ - (((pap)->ap_info >> WMI_LPI_AP_INFO_WIFI_MC_S) & 0x1) - -/* ap_info: msap_supported (bit 2) */ -#define WMI_LPI_AP_INFO_SET_MSAP_SUPPORTED(pap, val) do { \ - (pap)->ap_info |= (((val) & 0x1) << WMI_LPI_AP_INFO_MSAP_SUPPORTED_S); \ - } while (0) -#define WMI_LPI_AP_INFO_GET_MSAP_SUPPORTED(pap) \ - (((pap)->ap_info >> WMI_LPI_AP_INFO_MSAP_SUPPORTED_S) & 0x1) - -/* ap_info: is_active (bit 3) */ -#define WMI_LPI_AP_INFO_SET_IS_ACTIVE(pap, val) do { \ - (pap)->ap_info |= (((val) & 0x1) << WMI_LPI_AP_INFO_IS_ACTIVE_S); \ - } while (0) -#define WMI_LPI_AP_INFO_GET_IS_ACTIVE(pap) \ - (((pap)->ap_info >> WMI_LPI_AP_INFO_IS_ACTIVE_S) & 0x1) - -/* ap_info: valid_mask (bits [16:4], 13 bits) */ -#define WMI_LPI_AP_INFO_SET_VALID_MASK(pap, val) do { \ - (pap)->ap_info |= (((val) & 0x1FFF) << WMI_LPI_AP_INFO_VALID_MASK_S); \ - } while (0) -#define WMI_LPI_AP_INFO_GET_VALID_MASK(pap) \ - (((pap)->ap_info >> WMI_LPI_AP_INFO_VALID_MASK_S) & 0x1FFF) - -/* - * ap_info: reserved (bits [23:17], 7 bits) - * Sender must write 0. Receiver must ignore. - * Reserved for future per-AP flag extensions. - */ - -/* ap_info: phy_mode (bits [31:24], 8 bits) */ -#define WMI_LPI_AP_INFO_SET_PHY_MODE(pap, val) do { \ - (pap)->ap_info |= (((val) & 0xFF) << WMI_LPI_AP_INFO_PHY_MODE_S); \ - } while (0) -#define WMI_LPI_AP_INFO_GET_PHY_MODE(pap) \ - (((pap)->ap_info >> WMI_LPI_AP_INFO_PHY_MODE_S) & 0xFF) - -/* Helper: test a valid_mask bit directly in ap_info (valid_mask is at +4) */ -#define WMI_LPI_AP_INFO_VALID(pap, mask) \ - (((pap)->ap_info >> WMI_LPI_AP_INFO_VALID_MASK_S) & (mask)) - -/* valid_mask bit values (13-bit field in ap_info[16:4]) */ -#define WMI_LPI_VALID_TX_POWER 0x0001 /* tx_power field present */ -#define WMI_LPI_VALID_TX_RATE 0x0002 /* tx_rate field present */ -#define WMI_LPI_VALID_TSF 0x0004 /* tsf_lo/tsf_hi fields present */ -#define WMI_LPI_VALID_AGE 0x0008 /* age field present */ -#define WMI_LPI_VALID_WIFI_MC 0x0010 /* wifi_802_11_mc value in ap_info[1]*/ -#define WMI_LPI_VALID_MSAP 0x0020 /* msap[] field present */ -#define WMI_LPI_VALID_CNT_FREQ1 0x0040 /* band_center_freq_1 present */ -#define WMI_LPI_VALID_CNT_FREQ2 0x0080 /* band_center_freq_2 present */ -#define WMI_LPI_VALID_VENUE 0x0100 /* venue_type_and_info present */ -#define WMI_LPI_VALID_HT_SCO_BIT0 0x0200 /* HT SCO bit 0 */ -#define WMI_LPI_VALID_HT_SCO_BIT1 0x0400 /* HT SCO bit 1 */ -#define WMI_LPI_VALID_LOC_CIVIC 0x0800 /* Location Civic supported */ -#define WMI_LPI_VALID_LCI 0x1000 /* LCI supported */ - -/* ---- scan_info field bit positions ---- */ -#define WMI_LPI_SCAN_INFO_MODULE_ID_S 0 /* scan_module_id bits [7:0] */ -#define WMI_LPI_SCAN_INFO_SCAN_ID_S 8 /* scan_id bits [15:8] */ -#define WMI_LPI_SCAN_INFO_FLAGS_S 16 /* flags bits [23:16] */ -#define WMI_LPI_SCAN_INFO_CACHE_S 24 /* scan_cache bits [31:24] */ - -/* scan_info: scan_module_id (bits [7:0]) */ -#define WMI_LPI_SCAN_INFO_SET_MODULE_ID(pap, val) do { \ - (pap)->scan_info |= (((val) & 0xFF) << WMI_LPI_SCAN_INFO_MODULE_ID_S); \ - } while (0) -#define WMI_LPI_SCAN_INFO_GET_MODULE_ID(pap) \ - (((pap)->scan_info >> WMI_LPI_SCAN_INFO_MODULE_ID_S) & 0xFF) - -/* scan_info: scan_id (bits [15:8]) */ -#define WMI_LPI_SCAN_INFO_SET_SCAN_ID(pap, val) do { \ - (pap)->scan_info |= (((val) & 0xFF) << WMI_LPI_SCAN_INFO_SCAN_ID_S); \ - } while (0) -#define WMI_LPI_SCAN_INFO_GET_SCAN_ID(pap) \ - (((pap)->scan_info >> WMI_LPI_SCAN_INFO_SCAN_ID_S) & 0xFF) - -/* scan_info: flags (bits [23:16]) */ -#define WMI_LPI_SCAN_INFO_SET_FLAGS(pap, val) do { \ - (pap)->scan_info |= (((val) & 0xFF) << WMI_LPI_SCAN_INFO_FLAGS_S); \ - } while (0) -#define WMI_LPI_SCAN_INFO_GET_FLAGS(pap) \ - (((pap)->scan_info >> WMI_LPI_SCAN_INFO_FLAGS_S) & 0xFF) - -/* scan_info: scan_cache (bits [31:24]) */ -#define WMI_LPI_SCAN_INFO_SET_CACHE(pap, val) do { \ - (pap)->scan_info |= (((val) & 0xFF) << WMI_LPI_SCAN_INFO_CACHE_S); \ - } while (0) -#define WMI_LPI_SCAN_INFO_GET_CACHE(pap) \ - (((pap)->scan_info >> WMI_LPI_SCAN_INFO_CACHE_S) & 0xFF) - -/* ---- ESS_and_SEC_info field bit positions ---- */ -#define WMI_LPI_ESS_SEC_ESS_S 0 /* ess bits [15:0] */ -#define WMI_LPI_ESS_SEC_SEC_MODE_S 16 /* sec_mode bits [23:16] */ - -/* ESS_and_SEC_info: ess (bits [15:0]) */ -#define WMI_LPI_ESS_SEC_SET_ESS(pap, val) do { \ - (pap)->ESS_and_SEC_info |= (((val) & 0xFFFF) << WMI_LPI_ESS_SEC_ESS_S); \ - } while (0) -#define WMI_LPI_ESS_SEC_GET_ESS(pap) \ - (((pap)->ESS_and_SEC_info >> WMI_LPI_ESS_SEC_ESS_S) & 0xFFFF) - -/* ESS_and_SEC_info: sec_mode (bits [23:16]) */ -#define WMI_LPI_ESS_SEC_SET_SEC_MODE(pap, val) do { \ - (pap)->ESS_and_SEC_info |= (((val) & 0xFF) << WMI_LPI_ESS_SEC_SEC_MODE_S); \ - } while (0) -#define WMI_LPI_ESS_SEC_GET_SEC_MODE(pap) \ - (((pap)->ESS_and_SEC_info >> WMI_LPI_ESS_SEC_SEC_MODE_S) & 0xFF) - -/* ---- MCS_and_NSS_info field bit positions ---- */ -#define WMI_LPI_MCS_NSS_TX_NSS_S 0 /* tx_nss bits [7:0] */ -#define WMI_LPI_MCS_NSS_TX_MCS_S 8 /* tx_mcs bits [15:8] */ -#define WMI_LPI_MCS_NSS_RX_NSS_S 16 /* rx_nss bits [23:16] */ -#define WMI_LPI_MCS_NSS_RX_MCS_S 24 /* rx_mcs bits [31:24] */ - -/* MCS_and_NSS_info: tx_nss (bits [7:0]) */ -#define WMI_LPI_MCS_NSS_SET_TX_NSS(pap, val) do { \ - (pap)->MCS_and_NSS_info |= (((val) & 0xFF) << WMI_LPI_MCS_NSS_TX_NSS_S); \ - } while (0) -#define WMI_LPI_MCS_NSS_GET_TX_NSS(pap) \ - (((pap)->MCS_and_NSS_info >> WMI_LPI_MCS_NSS_TX_NSS_S) & 0xFF) - -/* MCS_and_NSS_info: tx_mcs (bits [15:8]) */ -#define WMI_LPI_MCS_NSS_SET_TX_MCS(pap, val) do { \ - (pap)->MCS_and_NSS_info |= (((val) & 0xFF) << WMI_LPI_MCS_NSS_TX_MCS_S); \ - } while (0) -#define WMI_LPI_MCS_NSS_GET_TX_MCS(pap) \ - (((pap)->MCS_and_NSS_info >> WMI_LPI_MCS_NSS_TX_MCS_S) & 0xFF) - -/* MCS_and_NSS_info: rx_nss (bits [23:16]) */ -#define WMI_LPI_MCS_NSS_SET_RX_NSS(pap, val) do { \ - (pap)->MCS_and_NSS_info |= (((val) & 0xFF) << WMI_LPI_MCS_NSS_RX_NSS_S); \ - } while (0) -#define WMI_LPI_MCS_NSS_GET_RX_NSS(pap) \ - (((pap)->MCS_and_NSS_info >> WMI_LPI_MCS_NSS_RX_NSS_S) & 0xFF) - -/* MCS_and_NSS_info: rx_mcs (bits [31:24]) */ -#define WMI_LPI_MCS_NSS_SET_RX_MCS(pap, val) do { \ - (pap)->MCS_and_NSS_info |= (((val) & 0xFF) << WMI_LPI_MCS_NSS_RX_MCS_S); \ - } while (0) -#define WMI_LPI_MCS_NSS_GET_RX_MCS(pap) \ - (((pap)->MCS_and_NSS_info >> WMI_LPI_MCS_NSS_RX_MCS_S) & 0xFF) - - -/* ---- venue_type_and_info field bit positions ---- */ -#define WMI_LPI_VENUE_TYPE_S 0 /* venue_type bits [7:0] */ -#define WMI_LPI_VENUE_INFO_S 8 /* venue_info bits [15:8] */ - -/* venue_type_and_info: venue_type (bits [7:0]) */ -#define WMI_LPI_VENUE_SET_TYPE(pap, val) do { \ - (pap)->venue_type_and_info |= (((val) & 0xFF) << WMI_LPI_VENUE_TYPE_S); \ - } while (0) -#define WMI_LPI_VENUE_GET_TYPE(pap) \ - (((pap)->venue_type_and_info >> WMI_LPI_VENUE_TYPE_S) & 0xFF) - -/* venue_type_and_info: venue_info (bits [15:8]) */ -#define WMI_LPI_VENUE_SET_INFO(pap, val) do { \ - (pap)->venue_type_and_info |= (((val) & 0xFF) << WMI_LPI_VENUE_INFO_S); \ - } while (0) -#define WMI_LPI_VENUE_GET_INFO(pap) \ - (((pap)->venue_type_and_info >> WMI_LPI_VENUE_INFO_S) & 0xFF) - -/* ========================================================================= - * End of WMI_LPI_SCAN_RESULT_EVENTID_V2 definitions - * ====================================================================== */ - - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stop_scan_cmd_fixed_param */ /** Scan requestor ID */ @@ -31192,18 +27896,14 @@ typedef enum { WMI_LPI_STATUS_MEDIUM_BUSY = 6, /** Extscan is the scan client whose scan complete event is triggered */ WMI_LPI_STATUS_EXTSCAN_CYCLE_AND_SCAN_REQ_COMPLETED = 7, - /** LPI scan is suspended*/ - WMI_LPI_STATUS_SCAN_SUSPENDED = 8, -} wmi_lpi_status; -/* preserve old name (with typo) as alias for corrected name */ -typedef wmi_lpi_status wmi_lpi_staus; +} wmi_lpi_staus; typedef struct { - A_UINT32 tlv_header; - A_UINT32 status; /* wmi_lpi_status */ + A_UINT32 tlv_header; + wmi_lpi_staus status; /** Scan requestor ID */ - A_UINT32 scan_req_id; + A_UINT32 scan_req_id; } wmi_lpi_status_event_fixed_param; typedef struct @@ -31708,7 +28408,6 @@ typedef enum { WMI_PEER_CFR_CAPTURE_BW_80MHZ = 2, WMI_PEER_CFR_CAPTURE_BW_160MHZ = 3, WMI_PEER_CFR_CAPTURE_BW_80_80MHZ = 4, - WMI_PEER_CFR_CAPTURE_BW_320MHZ = 5, WMI_PEER_CFR_CAPTURE_BW_MAX, } WMI_PEER_CFR_CAPTURE_BW; @@ -31761,12 +28460,6 @@ typedef enum { WMI_PEER_IND_OMI, /* operating mode indication */ } WMI_PEER_OPER_MODE_IND; - -#define WMI_EHT_PEER_PARAMS_MCS_DISABLE_GET(eht_peer_params) \ - WMI_GET_BITS(eht_peer_params, 0, 1) -#define WMI_EHT_PEER_PARAMS_MCS_DISABLE_SET(eht_peer_params, value) \ - WMI_SET_BITS(eht_peer_params, 0, 1, value) - typedef struct { /** TLV tag and len; tag equals * WMITLV_TAG_STRUC_wmi_peer_oper_mode_change */ @@ -31788,12 +28481,6 @@ typedef struct { * valid for peer_operating mode ind. OMI */ A_UINT32 new_disablemu; - /** eht_peer_params - * bit 0 - eht_mcs15_disable, refer to - * WMI_EHT_PEER_PARAMS_MCS_DISABLE_GET,SET macros - * bits 1 to 31 - reserved - */ - A_UINT32 eht_peer_params; } wmi_peer_oper_mode_change_event_fixed_param; /** FW response when tx failure count has reached threshold @@ -32445,519 +29132,6 @@ typedef struct { */ } wmi_nan_oem_data_cmd_fixed_param; -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_enable_cmd_param */ - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */ -/* -* TLVs following this structure: -* wmi_nan_ctrl_config_param nan_ctrl_config[]; -* wmi_nan_disc_band_config_param nan_disc_band_config[]; -*/ -} wmi_nan_enable_cmd_fixed_param; - -typedef enum { - WMI_NAN_DISC_BAND_PRI_2GHZ = 0x01, - WMI_NAN_DISC_BAND_SEC_5GHZ = 0x02, -} WMI_NAN_DISC_BANDS; - -/* Macros for parsing nan_ctrl_flags field */ -#define WMI_NAN_CTRL_FLAGS_GET_ENABLE_RANGING(param) \ - WMI_GET_BITS(param, 0, 1) -#define WMI_NAN_CTRL_FLAGS_SET_ENABLE_RANGING(param, val) \ - WMI_SET_BITS(param, 0, 1, val) -#define WMI_NAN_CTRL_FLAGS_GET_ENABLE_EARLY_DW_TERMINATION(param) \ - WMI_GET_BITS(param, 1, 1) -#define WMI_NAN_CTRL_FLAGS_SET_ENABLE_EARLY_DW_TERMINATION(param, val) \ - WMI_SET_BITS(param, 1, 1, val) - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_enable_cmd_fixed_param */ - A_UINT32 master_pref; /* Master preference value for cluster formation */ - /* Cluster ID used for synchronization. - * The value (lower 4 bytes) is sent in network byte order (big-endian). - * If set to 0, the firmware will generate a randomized cluster ID. - */ - A_UINT32 cluster_id; - /* Service ID value for publish beacon */ - A_UINT32 service_id_bcn_val; - /* Max hop count allowed for cluster joining */ - A_UINT32 hop_count_limit_val; - /* Service ID value for subscribe beacon */ - A_UINT32 subscribe_sid_beacon_val; - A_UINT32 config_tx_rx_chains; /* TX/RX chain configuration */ - /* Bitfield for NAN control options, - * use WMI_NAN_CTRL_FLAGS_SET_* and WMI_NAN_CTRL_FLAGS_GET_* macros - * for access - */ - union { - struct { - A_UINT32 - /* Enable ranging capability */ - enable_ranging: 1, - - /* Enable early termination of Discovery Window */ - enable_early_dw_termination:1, - - reserved: 30; /* reserved for future use */ - }; - A_UINT32 nan_ctrl_flags; /* 32-bit control flags word */ - }; - A_UINT32 supp_disc_bands; /* Possible values are enum WMI_NAN_DISC_BANDS */ - /* warmup_timer_value: - * NANWarmUp timer value in seconds, to be used when starting - * a NAN cluster as part of NAN enablement. - * If warmup_timer_value == 0, target needs to use default 120 sec, - * as mentioned in spec. - */ - A_UINT32 warmup_timer_value; -/* -* TLVs following this structure: -* wmi_nan_disc_band_config_param nan_disc_band_config[]; -*/ -} wmi_nan_ctrl_config_param; - -/* Macros for parsing scan_params field */ -#define WMI_NAN_DISC_SCAN_PARAMS_GET_DWELL_MS(param) \ - WMI_GET_BITS(param, 0, 16) -#define WMI_NAN_DISC_SCAN_PARAMS_SET_DWELL_MS(param, val) \ - WMI_SET_BITS(param, 0, 16, val) - -#define WMI_NAN_DISC_SCAN_PARAMS_GET_INTERVAL_SEC(param) \ - WMI_GET_BITS(param, 16, 16) -#define WMI_NAN_DISC_SCAN_PARAMS_SET_INTERVAL_SEC(param, val) \ - WMI_SET_BITS(param, 16, 16, val) - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_band_config_param */ - /* Channel frequency (in MHz) for discovery */ - A_UINT32 chan_freq; - /* Encoded scan parameters (use WMI_NAN_DISC_SCAN_PARAMS_GET/SET macros) */ - union { - struct { - A_UINT32 - dwell_ms: 16, - interval_sec: 16; - }; - A_UINT32 scan_params_word; - }; - /* - * Committed/Awake DW interval. Valid values range: 0-5. - * 0 indicates no wakeup for DW and can't be used on 2.4GHz band, - * otherwise 2^(n-1). - */ - A_UINT32 awake_dw_intval; - /* - * RSSI threshold (in dBm) indicating close proximity; used to determine - * if a received Synchronization Beacon from a peer within the - * same NAN cluster should trigger a role change from Master to Non-Master - * Sync when the peer has a higher Master Rank. - */ - A_INT32 rssi_close_val; - /* - * RSSI threshold (in dBm) indicating medium proximity; used to evaluate - * if three or more Synchronization Beacons from peers within the - * same NAN cluster justify a role change from Master to Non-Master Sync - * when those peers have higher Master Ranks. - */ - A_INT32 rssi_middle_val; - /* - * RSSI threshold (in dBm) used to determine if a peer is within proximity - * during a match event - */ - A_INT32 rssi_proximity_val; - /* Window size for RSSI averaging (based on number of beacons received) */ - A_UINT32 rssi_avg_window_size; -} wmi_nan_disc_band_config_param; - -typedef enum { - WMI_NAN_CONF_CHANGE_MASTER_PREF = 0x00000001, - WMI_NAN_CONF_CHANGE_CLUSTER_ID = 0x00000002, - WMI_NAN_CONF_CHANGE_SERVICE_ID_BCN_VAL = 0x00000004, - WMI_NAN_CONF_CHANGE_HOP_COUNT_LIMIT_VAL = 0x00000008, - WMI_NAN_CONF_CHANGE_SUBSCRIBE_SID_BCN_VAL = 0x00000010, - WMI_NAN_CONF_CHANGE_CONFIG_TX_RX_CHAINS = 0x00000020, - WMI_NAN_CONF_CHANGE_ENABLE_RANGING = 0x00000040, - WMI_NAN_CONF_CHANGE_ENABLE_EARLY_DW_TERM = 0x00000080, - WMI_NAN_CONF_CHANGE_SUPP_DISC_BANDS = 0x00000100, -} WMI_NAN_CONFIG_CHANGE_PARAM; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_config_cmd_fixed_param */ - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */ - /* Bitmap indicating which NAN configuration parameters have changed and - * need to be updated by the target firmware. Each bit corresponds to a - * specific parameter defined in WMI_NAN_CONFIG_CHANGE_PARAM. - */ - A_UINT32 nan_conf_change_bitmap; - /* nan_availability_attributes_len: - * number of valid bytes (i.e. excluding final alignment-padding) - * in the TLV nan_availability_attributes_data[] - */ - A_UINT32 nan_availability_attributes_len; -/* - * TLVs following this structure: - * wmi_nan_ctrl_config_param nan_ctrl_config[]; - * wmi_nan_disc_band_config_param nan_disc_band_config[]; - * A_UINT8 nan_availability_attributes_data[]: - * NAN availability attributes sent down (along with header) - * are sent in stream of bytes (ieee80211 protocol order). - * The host must manually byteswap these bytes within each 4-byte word - * if the host's endianness doesn't match the target's, to ensure the - * expected byte order is maintained. - */ -} wmi_nan_config_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disable_cmd_fixed_param */ - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */ -} wmi_nan_disable_cmd_fixed_param; - -#define WMI_NAN_SCHED_NOT_AVAIL_SLOT 0xFF - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_channel */ - - A_UINT32 chan_freq; /* in MHz */ - A_UINT32 center_freq1; /* Center frequency 1 in MHz */ - A_UINT32 center_freq2; /* Center frequency 2 in MHz */ - /* Channel bandwidth. Possible values are wmi_channel_width */ - A_UINT32 chan_width; - A_UINT32 rx_nss; /* advertised RX NSS */ - /* chan_entry_fields: - * opaque 6-byte bytestream (with a 2-byte alignment suffix) - * The host must manually byteswap these bytes within each 4-byte word - * if the host's endianness doesn’t match the target’s, to ensure the - * network byte order is maintained. - */ - A_UINT8 chan_entry_fields[8]; -} wmi_nan_channel; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_local_schedule_cmd_fixed_param */ - - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations (NMI vdev) */ - /** schedule_chan_bitmap_len: - * number of valid bytes (i.e. excluding final alignment-padding) - * in the TLV nan_schedule_chan_bitmap[] - */ - A_UINT32 schedule_chan_bitmap_len; -/* - * TLVs following this structure: - * - * A_UINT8 nan_schedule_chan_bitmap[]; - * A mapping of time slots to channel indexes in the schedule's - * committed_channel_list. Each slot lasts 16TUs. - * An unscheduled slot will be set to WMI_NAN_SCHED_NOT_AVAIL_SLOT. - * wmi_nan_channel committed_nan_channel_list[]; - */ -} wmi_nan_local_schedule_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cmd_fixed_param */ - - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations (NMI vdev) */ - wmi_mac_addr peer_nmi_addr; - /** schedule_chan_bitmap_len: - * number of valid bytes (i.e. excluding final alignment-padding) - * in the TLV nan_schedule_chan_bitmap[] - */ - A_UINT32 schedule_chan_bitmap_len; - A_UINT32 peer_committed_dw; - A_UINT32 peer_max_chan_switch; -/* - * TLVs following this structure: - * - * A_UINT8 nan_schedule_chan_bitmap[]: - * A mapping of time slots to channel indexes in the schedule's - * committed_channel_list. Each slot lasts 16TUs. - * An unscheduled slot will be set to WMI_NAN_SCHED_NOT_AVAIL_SLOT. - * wmi_nan_channel committed_nan_channel_list[]; - */ -} wmi_nan_peer_schedule_cmd_fixed_param; - -typedef enum { - WMI_NAN_PEER_FLAG_PMF = 0x01, - WMI_NAN_PEER_FLAG_AUTHENTICATED = 0x02, - WMI_NAN_PEER_FLAG_ASSOCIATED = 0x04, - WMI_NAN_PEER_FLAG_AUTHORIZED = 0x08, -} WMI_NAN_PEER_PARAMS_FLAGS; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_peer_params_cmd_fixed_param */ - - /* Virtual device ID used for NAN operations (either NMI or NDI VDEV) */ - A_UINT32 vdev_id; - /** peer NMI MAC address */ - wmi_mac_addr peer_nmi_addr; - /** peer NDI MAC address */ - wmi_mac_addr peer_ndi_macaddr; - /** peer_flags: - * peer station flags, for indicating PMF is enabled, - * authorization is done etc.. - * Possible values are enum WMI_NAN_PEER_PARAMS_FLAGS. - */ - A_UINT32 peer_flags; - /** peer_caps_ie_len: - * number of valid bytes (i.e. excluding final alignment-padding) - * in the TLV peer_caps_ie_data[] - */ - A_UINT32 peer_caps_ie_len; -/* - * TLVs following this structure: - * - * A_UINT8 peer_caps_ie_data[]: - * HT/VHT/HE/EHT etc. capability IEs (along with header) - * are sent in stream of bytes (ieee80211 protocol order). - * The host must manually byteswap these bytes within each 4-byte word - * if the host's endianness doesn’t match the target’s, to ensure the - * expected byte order is maintained. - */ -} wmi_nan_peer_params_cmd_fixed_param; - -/* - * NAN service request type values for - * wmi_nan_disc_service_req_cmd_fixed_param.service_req_type. - * Maps to NL80211_NAN_FUNC_PUBLISH / SUBSCRIBE / FOLLOW_UP. - */ -typedef enum { - WMI_NAN_DISC_SERVICE_REQ_PUBLISH = 1, - WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE = 2, - WMI_NAN_DISC_SERVICE_REQ_FOLLOW_UP = 3, -} WMI_NAN_DISC_SERVICE_REQ_TYPE; - -/* - * Publish type values for - * wmi_nan_disc_service_req_cmd_fixed_param.publish_type. - * Valid only when service_req_type == WMI_NAN_DISC_SERVICE_REQ_PUBLISH. - * Maps to NL80211_NAN_FUNC_PUBLISH_TYPE. - */ -typedef enum { - WMI_NAN_DISC_PUBLISH_UNSOLICITED = 0, - WMI_NAN_DISC_PUBLISH_SOLICITED = 1, - WMI_NAN_DISC_PUBLISH_UNSOLICITED_SOLICITED = 2, -} WMI_NAN_DISC_PUBLISH_TYPE; - -/* - * NAN discovery service request termination reason values for - * wmi_nan_disc_service_req_terminated_event_fixed_param.reason. - * Maps to nl80211_nan_func_term_reason. - */ -typedef enum { - /** - * Service request was cancelled by an explicit host request - * (WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID). - * Maps to NL80211_NAN_FUNC_TERM_REASON_USER_REQUEST = 0 - */ - WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_USER_REQUEST = 0, - /** - * Service request lifetime (TTL) elapsed; - * FW auto-expired the service request. - * Maps to NL80211_NAN_FUNC_TERM_REASON_TTL_EXPIRED = 1 - */ - WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_TTL_EXPIRED = 1, - /** - * FW encountered an internal error and could not maintain - * the service request. - * Also covers NAN_TERMINATED_REASON_COUNT_REACHED from the HAL path. - * Maps to NL80211_NAN_FUNC_TERM_REASON_ERROR = 2 - */ - WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_ERROR = 2, -} WMI_NAN_DISC_SERVICE_REQ_TERM_REASON; - -/* - * SDEA (Service Descriptor Extension Attribute) control field bit accessors. - * Maps to NL80211_ATTR_NAN_FUNC_SDEA_CTRL / cfg80211_nan_func.sdea_ctrl. - * Bit 2 : Data Path Required - * Bit 6 : Security Required - */ -#define WMI_NAN_DISC_SDEA_CTRL_GET_DATA_PATH_REQ(sdea) \ - WMI_GET_BITS(sdea, 2, 1) -#define WMI_NAN_DISC_SDEA_CTRL_SET_DATA_PATH_REQ(sdea, v) \ - WMI_SET_BITS(sdea, 2, 1, v) -#define WMI_NAN_DISC_SDEA_CTRL_GET_SECURITY_REQ(sdea) \ - WMI_GET_BITS(sdea, 6, 1) -#define WMI_NAN_DISC_SDEA_CTRL_SET_SECURITY_REQ(sdea, v) \ - WMI_SET_BITS(sdea, 6, 1, v) - -/* - * service_req_flags field bit accessors for - * wmi_nan_disc_service_req_cmd_fixed_param.service_req_flags. - * Packs all boolean cfg80211_nan_func fields into one A_UINT32. - * - * Bit 0 : close_range — match only with close-range peers - * (NL80211_ATTR_NAN_FUNC_CLOSE_RANGE) - * Bit 1 : publish_bcast — send in broadcast discovery beacons; - * valid only for Publish - * (NL80211_ATTR_NAN_FUNC_PUBLISH_BCAST) - * Bit 2 : subscribe_active — send active subscribe queries; - * valid only for Subscribe - * (NL80211_ATTR_NAN_FUNC_SUBSCRIBE_ACTIVE) - * Bit 3 : gtk_required — group temporal key required for - * multicast data - * (NL80211_ATTR_NAN_FUNC_GTK_REQUIRED) - * Bit 4 : pairing_setup — enable initial NAN3 pairing setup - * (NL80211_ATTR_NAN_FUNC_PAIRING_SETUP) - * Bit 5 : pairing_cache — enable persistent NAN3 pairing cache - * (NL80211_ATTR_NAN_FUNC_PAIRING_CACHE) - * Bit 6 : pairing_verify — enable NAN3 pairing re-verification - * (NL80211_ATTR_NAN_FUNC_PAIRING_VERIFY) - * Bit 7 : nd_pmk_valid — nd_pmk TLV is populated and valid - * (NL80211_ATTR_NAN_FUNC_ND_PMK) - * Bits 8-31 : reserved, must be set to 0 - */ -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_CLOSE_RANGE(f) \ - WMI_GET_BITS(f, 0, 1) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_CLOSE_RANGE(f, v) \ - WMI_SET_BITS(f, 0, 1, v) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_PUBLISH_BCAST(f) \ - WMI_GET_BITS(f, 1, 1) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_PUBLISH_BCAST(f, v) \ - WMI_SET_BITS(f, 1, 1, v) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_SUBSCRIBE_ACTIVE(f) \ - WMI_GET_BITS(f, 2, 1) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_SUBSCRIBE_ACTIVE(f, v) \ - WMI_SET_BITS(f, 2, 1, v) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_GTK_REQUIRED(f) \ - WMI_GET_BITS(f, 3, 1) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_GTK_REQUIRED(f, v) \ - WMI_SET_BITS(f, 3, 1, v) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_PAIRING_SETUP(f) \ - WMI_GET_BITS(f, 4, 1) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_PAIRING_SETUP(f, v) \ - WMI_SET_BITS(f, 4, 1, v) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_PAIRING_CACHE(f) \ - WMI_GET_BITS(f, 5, 1) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_PAIRING_CACHE(f, v) \ - WMI_SET_BITS(f, 5, 1, v) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_PAIRING_VERIFY(f) \ - WMI_GET_BITS(f, 6, 1) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_PAIRING_VERIFY(f, v) \ - WMI_SET_BITS(f, 6, 1, v) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET_ND_PMK_VALID(f) \ - WMI_GET_BITS(f, 7, 1) -#define WMI_NAN_DISC_SERVICE_REQ_FLAGS_SET_ND_PMK_VALID(f, v) \ - WMI_SET_BITS(f, 7, 1, v) - -/** - * WMI command to add a NAN discovery function - * (Publish / Subscribe / Follow-up). - * WMI equivalent of NL80211_CMD_ADD_NAN_FUNCTION / cfg80211_nan_func. - */ -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disc_service_req_cmd_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the NMI VDEV */ - A_UINT32 vdev_id; - /** - * NAN service request type: - * 1=Publish, 2=Subscribe, 3=Follow-up; - * refer to WMI_NAN_DISC_SERVICE_REQ_TYPE - */ - A_UINT32 service_req_type; - /** - * Unique cookie assigned by cfg80211 for this function. - * Split into two A_UINT32 words for endian portability. - * Use WMI_NAN_DISC_COOKIE_GET/SET macros to access as A_UINT64. - */ - A_UINT32 cookie_low32; /* lower 32 bits of 64-bit cookie value */ - A_UINT32 cookie_high32; /* upper 32 bits of 64-bit cookie value */ - /** - * Function lifetime in Discovery Windows; - * 0 = active until explicitly deleted - */ - A_UINT32 ttl; - /** - * Publish transmission mode; - * valid only when service_req_type == WMI_NAN_DISC_SERVICE_REQ_PUBLISH; - * refer to WMI_NAN_DISC_PUBLISH_TYPE - */ - A_UINT32 publish_type; - /** - * Local function instance ID to which this follow-up is associated; - * valid only when service_req_type == WMI_NAN_DISC_SERVICE_REQ_FOLLOW_UP - */ - A_UINT32 followup_instance_id; - /** - * Requestor instance ID from the prior match event; - * valid only when service_req_type == WMI_NAN_DISC_SERVICE_REQ_FOLLOW_UP - */ - A_UINT32 followup_requestor_id; - /** - * NMI MAC address of the peer to send the follow-up to; - * valid only when service_req_type == WMI_NAN_DISC_SERVICE_REQ_FOLLOW_UP - */ - wmi_mac_addr followup_dest; - /** - * SDEA control field bitmap; use WMI_NAN_DISC_SDEA_CTRL_GET/SET macros; - * bit2=Data Path Required, bit6=Security Required - */ - A_UINT32 sdea_ctrl; - /** - * Bitmap of supported NAN3 pairing bootstrap methods; - * bit0=Opportunistic, bit1=PIN - */ - A_UINT32 pairing_bootstrap_methods; - /** - * Bloom filter index for the SRF; - * valid only when TLV srf_bf[] is non-empty - */ - A_UINT32 srf_bf_idx; - /** - * SRF filter mode: - * 0=exclude listed entries, 1=include only listed entries - */ - A_UINT32 srf_include; - /** - * Packed boolean flags; use WMI_NAN_DISC_SERVICE_REQ_FLAGS_GET/SET macros; - * bit0=close_range, bit1=publish_bcast, bit2=subscribe_active, - * bit3=gtk_required, bit4=pairing_setup, bit5=pairing_cache, - * bit6=pairing_verify, bit7=nd_pmk_valid, bits8-31=reserved - */ - A_UINT32 service_req_flags; - /** Actual number of bytes in TLV serv_spec_info[]; max 255 */ - A_UINT32 serv_spec_info_len; - /** Actual number of bytes in TLV srf_bf[] */ - A_UINT32 srf_bf_len; - /** Actual number of bytes in TLV rx_match_filter[] */ - A_UINT32 rx_match_filter_len; - /** Actual number of bytes in TLV tx_match_filter[] */ - A_UINT32 tx_match_filter_len; - /** extra_nan_attrs_len: - * number of valid bytes (i.e. excluding final alignment-padding) - * in the TLV extra_nan_attrs[] - */ - A_UINT32 extra_nan_attrs_len; - /** - * TLV (tag length value) parameters follow this structure: - * A_UINT8 service_id[]; 6-byte NAN Service ID, - * zero-padded to 8 bytes - * A_UINT8 serv_spec_info[]; Service Specific Info, max 255 bytes - * A_UINT8 srf_bf[]; SRF Bloom filter data - * wmi_mac_addr srf_macs[]; SRF MAC address filter list - * A_UINT8 rx_match_filter[]; RX match filter byte stream - * A_UINT8 tx_match_filter[]; TX match filter byte stream - * A_UINT32 cipher_suites[]; NAN cipher suite ID array - * A_UINT8 nd_pmk[]; NAN Data Path PMK, 32 bytes; - * present only when bit7 of - * service_req_flags is set - * A_UINT8 extra_nan_attrs[]; extra NAN attrs like Device Cap, - * Shared Key Desc, CSIA cap etc. - * are sent in stream of bytes - * (ieee80211 protocol order). - * The host must manually byteswap - * these bytes within each 4-byte word - * if the host's endianness doesn’t - * match the target’s, to ensure the - * expected byte order is maintained. - */ -} wmi_nan_disc_service_req_cmd_fixed_param; - -typedef enum { - WMI_NAN_STATUS_NO_NAN_AVAIL_DFS_CHANNEL_DETECTED = 0x1, - WMI_NAN_STATUS_NO_DFS_BEACONS_RECEIVED = 0x2, - WMI_NAN_STATUS_STA_DISCONNECTED_FROM_DFS = 0x3, -} WMI_NAN_DFS_CHANNEL_AVAILABILITY_STATUS_TYPE; - #define WMI_NAN_GET_RANGING_INITIATOR_ROLE(flag) WMI_GET_BITS(flag, 0, 1) #define WMI_NAN_SET_RANGING_INITIATOR_ROLE(flag, val) WMI_SET_BITS(flag, 0, 1, val) #define WMI_NAN_GET_RANGING_RESPONDER_ROLE(flag) WMI_GET_BITS(flag, 1, 1) @@ -33047,7 +29221,7 @@ typedef struct { A_UINT32 tlv_header; /** Unique id identifying the VDEV */ A_UINT32 vdev_id; - /** NAN Cluster ID, 4 bytes are sent in network byte order (big-endian) */ + /** NAN Cluster ID */ A_UINT32 nan_cluster_id; } wmi_nan_started_cluster_event_fixed_param_PROTOTYPE; @@ -33061,7 +29235,7 @@ typedef struct { A_UINT32 tlv_header; /** Unique id identifying the VDEV */ A_UINT32 vdev_id; - /** NAN Cluster ID, 4 bytes are sent in network byte order (big-endian) */ + /** NAN Cluster ID */ A_UINT32 nan_cluster_id; } wmi_nan_joined_cluster_event_fixed_param_PROTOTYPE; @@ -33078,354 +29252,6 @@ typedef struct { */ } wmi_nan_dmesg_event_fixed_param; -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_enable_rsp_event_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */ - A_UINT32 status; /* Status code; 0 indicates NAN enable is success */ - A_UINT32 mac_id; /* MAC ID associated with NAN primary discovery channel */ -} wmi_nan_enable_rsp_event_fixed_param; - -/** - * WMI event response to WMI_NAN_DISC_SERVICE_REQ_CMDID. - * Sent by FW for each Publish / Subscribe / Follow-up function registration. - */ -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disc_service_rsp_event_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the NMI VDEV */ - A_UINT32 vdev_id; - /** - * Opaque cookie assigned by the driver; monotonically increasing per rdev. - * Host must store this and include it in every subsequent match event - * correlation. Equivalent of NL80211_ATTR_COOKIE in the CFG response. - * Split into two A_UINT32 words for endian portability. - * Use WMI_NAN_DISC_COOKIE_GET/SET macros to access as A_UINT64. - */ - A_UINT32 cookie_low32; /* lower 32 bits of 64-bit cookie value */ - A_UINT32 cookie_high32; /* upper 32 bits of 64-bit cookie value */ - /** - * FW/device-assigned service instance ID (1-255). - * Used in SDF frames and match events. - * Equivalent of NL80211_NAN_FUNC_INSTANCE_ID in the CFG response. - */ - A_UINT32 instance_id; - /** - * NAN service request type of the registered service request; - * refer to WMI_NAN_DISC_SERVICE_REQ_TYPE: - * 1 = WMI_NAN_DISC_SERVICE_REQ_PUBLISH - * 2 = WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE - * 3 = WMI_NAN_DISC_SERVICE_REQ_FOLLOW_UP - */ - A_UINT32 service_req_type; - /** Status code returned by FW: 0 = success, non-zero = failure */ - A_UINT32 status; -} wmi_nan_disc_service_rsp_event_fixed_param; - -/** - * WMI command to cancel an active NAN discovery service request. - * WMI equivalent of NL80211_CMD_DEL_NAN_FUNCTION / cfg80211 offload interface. - */ -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disc_cancel_service_req_cmd_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the NMI VDEV */ - A_UINT32 vdev_id; - /** - * NAN service request type being cancelled; - * refer to WMI_NAN_DISC_SERVICE_REQ_TYPE: - * 1 = WMI_NAN_DISC_SERVICE_REQ_PUBLISH - * 2 = WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE - */ - A_UINT32 service_req_type; - /** - * Instance ID of the service request to cancel (offload path); range 1-255. - * FW resolves instance_id to the internal service request object. - * Equivalent of NL80211_NAN_FUNC_INSTANCE_ID in - * NL80211_CMD_DEL_NAN_FUNCTION - */ - A_UINT32 instance_id; - /** - * Opaque cookie of the service request to cancel (standard path). - * Used when instance_id is not available; - * FW resolves cookie to service request. - * Equivalent of NL80211_ATTR_COOKIE in NL80211_CMD_DEL_NAN_FUNCTION. - * Set to 0 when instance_id is used instead. - * Split into two A_UINT32 words for endian portability. - * Use WMI_NAN_DISC_COOKIE_GET/SET macros to access as A_UINT64. - */ - A_UINT32 cookie_low32; /* lower 32 bits of 64-bit cookie value */ - A_UINT32 cookie_high32; /* upper 32 bits of 64-bit cookie value */ -} wmi_nan_disc_cancel_service_req_cmd_fixed_param; - -/** - * WMI event indicating a NAN discovery service request has been terminated. - * WMI equivalent of NL80211_CMD_DEL_NAN_FUNCTION (EVENT: terminated). - * Sent by FW when a Publish or Subscribe service request is cancelled by the - * host, expires due to TTL, or is terminated by FW due to an error. - */ -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disc_service_req_terminated_event_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the NMI VDEV */ - A_UINT32 vdev_id; - /** - * Opaque cookie of the terminated service request; assigned by FW in - * WMI_NAN_DISC_SERVICE_RSP_EVENTID. - * Equivalent of NL80211_ATTR_COOKIE in the terminated event. - * Split into two A_UINT32 words for endian portability. - * Use WMI_NAN_DISC_COOKIE_GET/SET macros to access as A_UINT64. - */ - A_UINT32 cookie_low32; /* lower 32 bits of 64-bit cookie value */ - A_UINT32 cookie_high32; /* upper 32 bits of 64-bit cookie value */ - /** - * Instance ID of the terminated service request (1-255). - * Equivalent of NL80211_NAN_FUNC_INSTANCE_ID in the terminated event - */ - A_UINT32 instance_id; - /** - * NAN service request type that was terminated; - * refer to WMI_NAN_DISC_SERVICE_REQ_TYPE: - * 1 = WMI_NAN_DISC_SERVICE_REQ_PUBLISH - * 2 = WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE - */ - A_UINT32 service_req_type; - /** - * Termination reason; refer to WMI_NAN_DISC_SERVICE_REQ_TERM_REASON enum: - * WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_USER_REQUEST (0) — - * cancelled by host - * WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_TTL_EXPIRED (1) — - * TTL elapsed - * WMI_NAN_DISC_SERVICE_REQ_TERM_REASON_ERROR (2) — - * FW internal error - */ - A_UINT32 reason; -} wmi_nan_disc_service_req_terminated_event_fixed_param; - -/** -* WMI NAN discovery match event (NL80211_CMD_NAN_MATCH equivalent). - * Covers two match scenarios, discriminated by the type field: - * type = WMI_NAN_DISC_SERVICE_REQ_PUBLISH — - * subscriber found a matching publisher - * type = WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE — - * publisher received a subscribe frame - */ -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disc_match_event_fixed_param */ - A_UINT32 tlv_header; - /** Unique id identifying the NMI VDEV */ - A_UINT32 vdev_id; - /** - * Cookie assigned by the driver in the - * WMI_NAN_DISC_SERVICE_RSP_EVENTID response; - * host uses this to correlate the match to the originating function. - * Split into two A_UINT32 words for endian portability. - * Use WMI_NAN_DISC_COOKIE_GET/SET macros to access as A_UINT64. - */ - A_UINT32 cookie_low32; /* lower 32 bits of 64-bit cookie value */ - A_UINT32 cookie_high32; /* upper 32 bits of 64-bit cookie value */ - /** Local function instance ID that triggered the match */ - A_UINT32 inst_id; - /** Peer's function instance ID */ - A_UINT32 peer_inst_id; - /** - * NAN service request type discriminating the match scenario; - * refer to WMI_NAN_DISC_SERVICE_REQ_TYPE: - * 1 = WMI_NAN_DISC_SERVICE_REQ_PUBLISH (subscriber matched a publisher) - * 2 = WMI_NAN_DISC_SERVICE_REQ_SUBSCRIBE (publisher received a subscribe) - */ - A_UINT32 type; - /** - * SDEA control field from peer; use WMI_NAN_DISC_SDEA_CTRL_GET macros; - * bit2=Data Path Required, bit6=Security Required - */ - A_UINT32 sdea_ctrl; - /** Peer's pairing bootstrap methods bitmap */ - A_UINT32 bootstrap_methods; - /** 1 = peer requires NDP (derived from SDEA bit 2); 0 = no NDP required */ - A_UINT32 data_path; - /** - * 1 = GTK protection required (derived from SDEA bit 10); - * 0 = not required - */ - A_UINT32 gtk_required; - /** 1 = peer supports pairing setup; 0 = not supported */ - A_UINT32 pairing_setup; - /** 1 = peer supports pairing cache; 0 = not supported */ - A_UINT32 pairing_cache; - /** 1 = peer supports pairing verify; 0 = not supported */ - A_UINT32 pairing_verify; - /** - * Received signal strength indicator (RSSI) in dBm; - * valid only when rssi_valid == 1 - */ - A_INT32 rssi; - /** 1 = rssi field is valid; 0 = rssi not populated */ - A_UINT32 rssi_valid; - /** Actual number of bytes in TLV peer_addr[] (always 6) */ - A_UINT32 peer_addr_len; - /** Actual number of bytes in TLV service_id[] (always 6) */ - A_UINT32 service_id_len; - /** Actual number of bytes in TLV serv_spec_info[] */ - A_UINT32 serv_spec_info_len; - /** Actual number of bytes in TLV scid[] */ - A_UINT32 scid_len; - /** - * Actual number of bytes in TLV extra_info[]; - * relevant when peer includes Extended SSI attribute - */ - A_UINT32 extra_info_len; - /** - * Actual number of bytes in TLV ies[]; - * raw IE blob parsed by supplicant: NPBA→bootstrap handler, - * Shared Key Descriptor→NIK exchange - */ - A_UINT32 ies_len; - /** - * TLV (tag length value) parameters follow this structure: - * wmi_mac_addr peer_addr[]; peer NMI address, 6 bytes (padded to 8) - * A_UINT8 service_id[]; local service ID, 6 bytes - * A_UINT8 serv_spec_info[]; service specific info from peer - * A_UINT32 cipher_suites[]; peer's NAN cipher suite ID array - * A_UINT8 scid[]; secure context ID; present when security_required == 1 - * A_UINT8 extra_info[]; extended SSI; present when extra_info_len > 0 - * A_UINT8 ies[]; raw IEs blob; present when ies_len > 0 - */ -} wmi_nan_disc_match_event_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_next_dw_info_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */ - A_UINT32 dw_chan_freq; /* DW channel freq in MHz */ -} wmi_nan_next_dw_info_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disable_cnf_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */ - A_UINT32 status; /* Status code; 0 indicates NAN enable is success */ -} wmi_nan_disable_cnf_event_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_disable_ind_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations */ -} wmi_nan_disable_ind_event_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_local_schedule_cnf_event_fixed_param */ - - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations (NMI VDEV) */ - /** Status code; 0 indicates NAN local schedule got applied successfully */ - A_UINT32 status; -} wmi_nan_local_schedule_cnf_event_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_peer_schedule_cnf_event_fixed_param */ - - A_UINT32 vdev_id; /* Virtual device ID used for NAN operations (NMI VDEV) */ - /** Status code; 0 indicates NAN peer schedule got applied successfully */ - A_UINT32 status; -} wmi_nan_peer_schedule_cnf_event_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_peer_params_cnf_event_fixed_param */ - - /** Virtual device ID used for NDP operations(either NMI or NDI VDEV) */ - A_UINT32 vdev_id; - /** peer NMI MAC address */ - wmi_mac_addr peer_nmi_addr; - /** peer NDI MAC address */ - wmi_mac_addr peer_ndi_macaddr; - /** status: - * 0 indicates NDP setup/schedule_negotiation peer params - * were applied successfully. - */ - A_UINT32 status; -} wmi_nan_peer_params_cnf_event_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_nan_dfs_channel_availability_ind_event_fixed_param */ - A_UINT32 vdev_id; - /** status: - * Status code; see WMI_NAN_DFS_CHANNEL_AVAILABILITY_STATUS_TYPE - */ - A_UINT32 status; -} wmi_nan_dfs_channel_availability_ind_event_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_channel_info_event_fixed_param */ - - A_UINT32 vdev_id; /* Virtual device ID used for NDP operations (NDI VDEV) */ - /** peer NDI MAC address */ - wmi_mac_addr peer_ndi_macaddr; - /** Number of channels on this peer */ - A_UINT32 num_ndp_channels; - /** - * TLV (tag length value) parameters follow the ndp_confirm - * structure. The TLV's are: - * wmi_channel ndp_channel_list[]; - * A_UINT32 nss_list[]; // Nss indexing should match with channel indexing, - * // since Nss is associated with the channel. - * wmi_ndp_channel_info channel_info[]; // Indexing should match with - * // channel indexing. - */ -} wmi_ndp_channel_info_event_fixed_param; - -typedef enum { - WMI_NDP_BAND_CAP_2GHZ = 0x01, - WMI_NDP_BAND_CAP_5GHZ = 0x02, - WMI_NDP_BAND_CAP_6GHZ = 0x04, -} WMI_NDP_BAND_CAP; - -/* Macros for parsing NAN device_caps fields */ -#define WMI_DEVICE_CAPS_GET_VHT_PHY_MODE(word32) \ - WMI_GET_BITS(word32, 0, 1) -#define WMI_DEVICE_CAPS_SET_VHT_PHY_MODE(word32, val) \ - WMI_SET_BITS(word32, 0, 1, val) -#define WMI_DEVICE_CAPS_GET_HE_PHY_MODE(word32) \ - WMI_GET_BITS(word32, 1, 1) -#define WMI_DEVICE_CAPS_SET_HE_PHY_MODE(word32, val) \ - WMI_SET_BITS(word32, 1, 1, val) -#define WMI_DEVICE_CAPS_GET_HE_VHT_80_80(word32) \ - WMI_GET_BITS(word32, 2, 1) -#define WMI_DEVICE_CAPS_SET_HE_VHT_80_80(word32, val) \ - WMI_SET_BITS(word32, 2, 1, val) -#define WMI_DEVICE_CAPS_GET_HE_VHT_160(word32) \ - WMI_GET_BITS(word32, 3, 1) -#define WMI_DEVICE_CAPS_SET_HE_VHT_160(word32, val) \ - WMI_SET_BITS(word32, 3, 1, val) -#define WMI_DEVICE_CAPS_GET_NUM_TX_ANT(word32) \ - WMI_GET_BITS(word32, 4, 4) -#define WMI_DEVICE_CAPS_SET_NUM_TX_ANT(word32, val) \ - WMI_SET_BITS(word32, 4, 4, val) -#define WMI_DEVICE_CAPS_GET_NUM_RX_ANT(word32) \ - WMI_GET_BITS(word32, 8, 4) -#define WMI_DEVICE_CAPS_SET_NUM_RX_ANT(word32, val) \ - WMI_SET_BITS(word32, 8, 4, val) -#define WMI_DEVICE_CAPS_GET_S3_SUPPORT(word32) \ - WMI_GET_BITS(word32, 12, 1) -#define WMI_DEVICE_CAPS_SET_S3_SUPPORT(word32, val) \ - WMI_SET_BITS(word32, 12, 1, val) -#define WMI_DEVICE_CAPS_GET_MAX_NDI_INTERFACES(word32) \ - WMI_GET_BITS(word32, 13, 3) -#define WMI_DEVICE_CAPS_SET_MAX_NDI_INTERFACES(word32, val) \ - WMI_SET_BITS(word32, 13, 3, val) -#define WMI_DEVICE_CAPS_GET_NDP_SUPPORTED_BAND(word32) \ - WMI_GET_BITS(word32, 16, 8) -#define WMI_DEVICE_CAPS_SET_NDP_SUPPORTED_BAND(word32, val) \ - WMI_SET_BITS(word32, 16, 8, val) -#define WMI_DEVICE_CAPS_GET_MAX_CHAN_SWITCH_TIME(word32) \ - WMI_GET_BITS(word32, 0, 16) -#define WMI_DEVICE_CAPS_SET_MAX_CHAN_SWITCH_TIME(word32, val) \ - WMI_SET_BITS(word32, 0, 16, val) -#define WMI_DEVICE_CAPS_GET_MAX_FAW_CHAN_PER_PEER(word32) \ - WMI_GET_BITS(word32, 16, 4) -#define WMI_DEVICE_CAPS_SET_MAX_FAW_CHAN_PER_PEER(word32, val) \ - WMI_SET_BITS(word32, 16, 4, val) - typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUCT_wmi_nan_capabilities */ A_UINT32 tlv_header; @@ -33433,35 +29259,6 @@ typedef struct { A_UINT32 max_ndp_sessions; /** Maximum number of nan pairing sessions supported by the Firmware */ A_UINT32 max_pairing_sessions; - union { - /* First 32-bit word of device capabilities */ - A_UINT32 device_caps_word0; - struct { - A_UINT32 vht_phy_mode: 1, /* Support for VHT PHY mode */ - he_phy_mode: 1, /* Support for HE PHY mode */ - he_vht_80_80: 1, /* Support for 80+80 MHz HE/VHT */ - he_vht_160: 1, /* Support for 160 MHz HE/VHT */ - num_tx_ant: 4, /* Number of TX antennas */ - num_rx_ant: 4, /* Number of RX antennas */ - s3_support: 1, /* Support for S3 power save */ - max_ndi_interfaces:3, /* Max number of NDI interfaces */ - ndp_supported_band:8, /* Supported bands for NDP - * (see WMI_NDP_BAND_CAP) */ - reserved:8; /* Reserved bits */ - }; - }; - union { - /* Second 32-bit word of device capabilities */ - A_UINT32 device_caps_word1; - struct { - A_UINT32 - /* Max channel switch time, in microseconds */ - max_chan_switch_time:16, - /* Max FAW channels to be allowed for a NDP peer */ - max_faw_chan_per_peer: 4, - reserved2: 12; /* Reserved bits */ - }; - }; } wmi_nan_capabilities; /** NAN DATA CMD's */ @@ -33682,21 +29479,6 @@ typedef struct { #define wmi_ndp_cmd_param wmi_ndp_cmd_param_PROTOTYPE -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_set_latency_tput_fixed_param */ - A_UINT32 tlv_header; - /** NDP instance id */ - A_UINT32 ndp_instance_id; - /** NDI VDEV ID */ - A_UINT32 vdev_id; - /** latency reqirement */ - A_UINT32 latency_ms; - /** throughput requirement */ - A_UINT32 tput_mbps; -} wmi_ndp_set_latency_tput_fixed_param_PROTOTYPE; - -#define wmi_ndp_set_latency_tput_fixed_param wmi_ndp_set_latency_tput_fixed_param_PROTOTYPE - /** * NDP End request */ @@ -34137,9 +29919,6 @@ enum wmi_sar_feature_state_flags { WMI_SAR_FEATURE_ON_USER_DEFINED, WMI_SAR_FEATURE_ON_SAR_V2_0, WMI_SAR_FEATURE_ON_SAR_V3, - WMI_SAR_FEATURE_ON_SAR_V3_0 = WMI_SAR_FEATURE_ON_SAR_V3, - WMI_SAR_FEATURE_ON_SAR_V4_0, - WMI_SAR_FEATURE_ON_SAR_V5_0, }; typedef struct { @@ -34291,12 +30070,6 @@ typedef struct { A_UINT8 replay_counter[GTK_REPLAY_COUNTER_BYTES]; } wmi_key_material; -#ifndef WMI_MAX_PMK_LEN -#define WMI_MAX_SMD_KDK_LEN 64 -#else -#define WMI_MAX_SMD_KDK_LEN WMI_MAX_PMK_LEN -#endif - typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_key_material_ext */ A_UINT32 tlv_header; @@ -34310,10 +30083,6 @@ typedef struct { A_UINT32 kck_len; /* length of kek in key_buffer */ A_UINT32 kek_len; - /* length of smd kdk */ - A_UINT32 smd_kdk_len; - /* smd kdk buffer */ - A_UINT8 smd_kdk_buffer[WMI_MAX_SMD_KDK_LEN]; } wmi_key_material_ext; typedef struct { @@ -34330,8 +30099,6 @@ typedef struct { * bit 7 0x1 to show bits 8-15 are valid * bits 8-15 full WMI_ROAM_TRIGGER_REASON_ID/WMI_ROAM_TRIGGER_EXT_REASON_ID * since 4 bits are not enough. - * bit 16 SMD BSS transition if it's set, see GET / SET - * ROAM_SMD_BSS_TRANSITION macros */ A_UINT32 roam_reason; /** associated AP's RSSI calculated by FW when reason code is WMI_ROAM_REASON_LOW_RSSI. not valid if roam_reason is BMISS */ @@ -34355,27 +30122,6 @@ typedef struct { A_UINT32 mac_tsf_id; /** ignore mac_tsf_id unless mac_tsf_id_valid is set */ A_UINT32 mac_tsf_id_valid; - /** - * IEEE value for auth algorithm - * Authentication algorithm number = 3: - * Simultaneous Authentication of Equals (SAE) - * Authentication algorithm number = 8: - * IEEE 802.1X authentication - * Authentication algorithm number = 9: - * EPPKE authentication - */ - A_UINT32 auth_algo; - /** smd_identifier: - * The SMD identifier of the roamed AP must not be zero in cases of - * an SMD BSS transition or a reassociation with SMD capability. - */ - wmi_mac_addr smd_identifier; - /** - * Length of KDE data which is received on EAPOL M3 frame or - * reassoc reponse frame. - * Ex: SAE PW ID KDE data - */ - A_UINT32 kde_length; /** * TLV (tag length value) parameters follows roam_synch_event * The TLV's are: @@ -34394,7 +30140,6 @@ typedef struct { * wmi_key_material_ext key_ext[]; * wmi_roam_pmk_cache_synch_tlv_param roam_pmk_cache_synch_info[]; * wmi_pdev_band_to_mac mac_freq_mapping[]; - * A_UINT8 kde_data[]; */ } wmi_roam_synch_event_fixed_param; @@ -35561,11 +31306,6 @@ typedef struct { A_UINT32 pdev_id; } wmi_pdev_resume_event_fixed_param; -/** WMI_PDEV_SUSPEND_EVENTID: generated in response to WMI_PDEV_SUSPEND_CMDID */ -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_suspend_event_fixed_param */ - A_UINT32 pdev_id; -} wmi_pdev_suspend_event_fixed_param; /** value representing all modules */ @@ -36322,7 +32062,6 @@ typedef struct { /* picks protocol type from WMI_USD_SERVICE_PROTOCOL_TYPE */ A_UINT32 protocol_type; wmi_mac_addr device_mac_addr; - wmi_mac_addr multicast_addr; } wmi_usd_service_cmd_fixed_param; typedef struct { @@ -36364,44 +32103,6 @@ typedef enum { WMI_USD_SERVICE_PROTOCOL_TYPE_CSA_MATTER = 3, } WMI_USD_SERVICE_PROTOCOL_TYPE; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_unified_connect_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; -} wmi_vdev_unified_connect_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_cmd_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; -} wmi_vdev_unified_disconnect_cmd_fixed_param; - -typedef enum { - WMI_VDEV_UNIFIED_CONNECT_EVENT_SUCCESS, - WMI_VDEV_UNIFIED_CONNECT_EVENT_FAILURE, -} WMI_VDEV_UNIFIED_CONNECT_EVENT_STATUS; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_unified_connect_event_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - A_UINT32 status; /* WMI_VDEV_UNIFIED_CONNECT_EVENT_STATUS */ -} wmi_vdev_unified_connect_event_fixed_param; - -typedef enum { - WMI_VDEV_UNIFIED_DISCONNECT_EVENT_SUCCESS, - WMI_VDEV_UNIFIED_DISCONNECT_EVENT_FAILURE, -} WMI_VDEV_UNIFIED_DISCONNECT_EVENT_STATUS; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_unified_disconnect_event_fixed_param */ - /** unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - A_UINT32 status; /* WMI_VDEV_UNIFIED_DISCONNECT_EVENT_STATUS */ -} wmi_vdev_unified_disconnect_event_fixed_param; - - #define EXPIRY_TIME_IN_TSF_TIMESTAMP_OFFSET 0 #define EXPIRY_TIME_IN_TSF_TIMESTAMP_MASK 1 @@ -37535,23 +33236,6 @@ typedef struct { A_UINT32 tid_mask; /* bits 0 to 15 = QoS TIDs, bit 16 = non-qos TID */ } wmi_peer_reorder_queue_remove_cmd_fixed_param; -/** - * This command is sent from WLAN host driver to firmware for - * customizing MCS range & retry count for specific TID of specific peer - */ -typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - wmi_mac_addr peer_macaddr; /* Peer MAC address */ - A_UINT32 tid; - /* on_off: - * Rate customization enable/disable. 1 for enable and 0 for disable. - */ - A_UINT32 on_off; - A_UINT32 bw; /* Unit MHz */ - A_UINT32 retry_count; -} wmi_peer_tid_rate_custom_cmd_fixed_param; - /* DEPRECATED - use wmi_pdev_set_mac_config_response_event_fixed_param instead */ typedef struct { @@ -38203,81 +33887,6 @@ typedef struct wmi_bpf_get_vdev_work_memory_resp_evt_s { */ } wmi_bpf_get_vdev_work_memory_resp_evt_fixed_param; - -/* APF offloads supported bitmap: - * - * BIT 0: ARP OFFLOAD - * BIT 1: NS OFFLOAD - * BIT 2: IGMP OFFLOAD - * BIT 3: ICMP OFFLOAD - * BIT 4-31: reserved -*/ -#define WMI_BPF_ARP_OFFLOAD_SUPPORT_GET(param) \ - WMI_GET_BITS(param, 0, 1) -#define WMI_BPF_ARP_OFFLOAD_SUPPORT_SET(param, value) \ - WMI_SET_BITS(param, 0, 1, value) - -#define WMI_BPF_NS_OFFLOAD_SUPPORT_GET(param) \ - WMI_GET_BITS(param, 1, 1) -#define WMI_BPF_NS_OFFLOAD_SUPPORT_SET(param, value) \ - WMI_SET_BITS(param, 1, 1, value) - -#define WMI_BPF_IGMP_OFFLOAD_SUPPORT_GET(param) \ - WMI_GET_BITS(param, 2, 1) -#define WMI_BPF_IGMP_OFFLOAD_SUPPORT_SET(param, value) \ - WMI_SET_BITS(param, 2, 1, value) - -#define WMI_BPF_ICMP_OFFLOAD_SUPPORT_GET(param) \ - WMI_GET_BITS(param, 3, 1) -#define WMI_BPF_ICMP_OFFLOAD_SUPPORT_SET(param, value) \ - WMI_SET_BITS(param, 3, 1, value) - -typedef struct wmi_bpf_set_supported_offload_bitmap_cmd_s { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* ofld_bitmap: - * Host sends bitmap for APF supported offloads. - * Refer to the above WMI_BPF_ macros for the interpretation of the bits - * within the bitmap. - */ - A_UINT32 ofld_bitmap; -} wmi_bpf_set_supported_offload_bitmap_cmd_fixed_param; - -/* APF modes: */ -typedef enum { - /* Default value: 0 */ - wmi_apf_mode_default = 0, - - /* Mode 1: value 1: APF to operate only during system suspend. */ - wmi_apf_mode_system_suspend = 1, - - /* Mode 2: value 2: - * Downgrade the APF capability of the firmware to a lower version - * (from V6 to V4). - */ - wmi_apf_mode_capability_v4 = 2, - - /* Mode combination: value 3: - * Downgrade to APFv4 and enable only in system suspend. - */ - wmi_apf_mode_system_suspend_and_capability_v4 = 3, - - /* Mode 3: value 4: Turn off APF completely. */ - wmi_apf_mode_off = 4, -} wmi_apf_modes; - -typedef struct wmi_bpf_set_apf_mode_cmd_s { - A_UINT32 tlv_header; /* tag = WMITLV_TAG_STRUC_wmi_bpf_set_apf_mode_cmd_fixed_param */ - A_UINT32 vdev_id; - /* apf_mode: - * Host indicates the APF mode (or combination of modes). - * Refer to the wmi_apf_modes enum for the interpretation of the - * apf_mode value. - */ - A_UINT32 apf_mode; /* holds a wmi_apf_modes value */ -} wmi_bpf_set_apf_mode_cmd_fixed_param; - - #define AES_BLOCK_LEN 16 /* in bytes */ #define FIPS_KEY_LENGTH_128 16 /* in bytes */ #define FIPS_KEY_LENGTH_256 32 /* in bytes */ @@ -38386,29 +33995,11 @@ typedef struct { A_UINT32 rx_antenna; /* rx antenna */ A_UINT32 tx_default_antenna; /* tx default antenna */ /* - * Following this structure are the TLVs: - * - wmi_pdev_smart_ant_gpio_handle - * - * - A_UINT32 pdev_smart_ant_param[] - * bit 0 : enable separate antenna for RTS (1:enable, 0:disable) - * Refer to WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_GET/SET - * bit 1-31: reserved + * Following this structure is the TLV: + * wmi_pdev_smart_ant_gpio_handle */ } wmi_pdev_smart_ant_enable_cmd_fixed_param; -/* - * Bit field definitions for pdev_smart_ant_param A_UINT32 - * within WMI_PDEV_SMART_ANT_ENABLE_CMDID - */ -#define WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_BIT_POS 0 -#define WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_NUM_BITS 1 - -#define WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_GET(enable_field) \ - WMI_GET_BITS(enable_field, WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_BIT_POS, WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_NUM_BITS) - -#define WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_SET(enable_field, value) \ - WMI_SET_BITS(enable_field, WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_BIT_POS, WMI_PDEV_SMART_ANT_ENABLE_SEPARATE_RTS_ANT_NUM_BITS, value) - /** GPIO pins/function values to control antennas */ typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_smart_ant_gpio_handle */ @@ -38477,35 +34068,15 @@ typedef struct { #define WMI_PER_MIN_TX_PKTS_SET(per_threshold, value) \ WMI_SET_BITS(per_threshold, WMI_PER_MIN_TX_PKTS_BIT_POS, WMI_PER_MIN_TX_PKTS_NUM_BITS, value) -#define WMI_SA_TRAIN_LATENCY_TRAFFIC_BIT_POS 25 -#define WMI_SA_TRAIN_LATENCY_TRAFFIC_NUM_BITS 1 - -#define WMI_GET_SA_TRAIN_LATENCY_TRAFFIC(per_threshold) \ - WMI_GET_BITS(per_threshold, WMI_SA_TRAIN_LATENCY_TRAFFIC_BIT_POS, WMI_SA_TRAIN_LATENCY_TRAFFIC_NUM_BITS) - -#define WMI_SET_SA_TRAIN_LATENCY_TRAFFIC(per_threshold, value) \ - WMI_SET_BITS(per_threshold, WMI_SA_TRAIN_LATENCY_TRAFFIC_BIT_POS, WMI_SA_TRAIN_LATENCY_TRAFFIC_NUM_BITS, value) - -#define WMI_SA_TRAIN_USING_QOS_NULL_BIT_POS 26 -#define WMI_SA_TRAIN_USING_QOS_NULL_NUM_BITS 1 - -#define WMI_GET_SA_TRAIN_USING_QOS_NULL(per_threshold) \ - WMI_GET_BITS(per_threshold, WMI_SA_TRAIN_USING_QOS_NULL_BIT_POS, WMI_SA_TRAIN_USING_QOS_NULL_NUM_BITS) - -#define WMI_SET_SA_TRAIN_USING_QOS_NULL(per_threshold, value) \ - WMI_SET_BITS(per_threshold, WMI_SA_TRAIN_USING_QOS_NULL_BIT_POS, WMI_SA_TRAIN_USING_QOS_NULL_NUM_BITS, value) - - #define WMI_RATE_SERIES_320_BIT_POS 0 #define WMI_RATE_SERIES_320_NUM_BITS 16 #define WMI_GET_RATE_SERIES_320(train_rate_series_ext) \ WMI_GET_BITS(train_rate_series_ext, WMI_RATE_SERIES_320_BIT_POS, WMI_RATE_SERIES_320_NUM_BITS) -#define WMI_SET_RATE_SERIES_320(train_rate_series_ext, value) \ +#define WMI_SET_RATE_SERIES_320(train_rate_series_ext) \ WMI_SET_BITS(train_rate_series_ext, WMI_RATE_SERIES_320_BIT_POS, WMI_RATE_SERIES_320_NUM_BITS, value) - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_train_antenna_param */ /* rate array */ @@ -38548,9 +34119,7 @@ typedef struct { * 0 | PER Threshold is valid * 1:8 | Per Threshold * 9:24 | min_tx_pkts Minimum number of pkts need to be checked - * 25 | enable_training_for_latency_traffic - * 26 | train_using_qos_null - * 27:31 | Reserved + * 25:31 | Reserved */ A_UINT32 per_threshold; /* @@ -38837,41 +34406,6 @@ typedef enum { * A_INT8 ICNIRP 6 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-8) (Ch117~Ch149) * A_INT8 ICNIRP 6 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-8) (Ch117~Ch149) * A_INT8 ICNIRP 6 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-8) (Ch117~Ch149) - * if version == 2 or chip is col, will have NONTAS POWER LIMIT - * ====================NONTAS POWER LIMIT VALUE====================== - * A_INT8 NONTAS 2 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) - * A_INT8 NONTAS 2 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) - * A_INT8 NONTAS 2 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) - * A_INT8 NONTAS 5 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-1, Ch32 ~ Ch48) - * A_INT8 NONTAS 5 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-1, Ch32 ~ Ch48) - * A_INT8 NONTAS 5 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-1, Ch32 ~ Ch48) - * A_INT8 NONTAS 5 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-2, Ch50 ~ Ch144) - * A_INT8 NONTAS 5 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-2, Ch50 ~ Ch144) - * A_INT8 NONTAS 5 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-2, Ch50 ~ Ch144) - * A_INT8 NONTAS 5 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-3, Ch149 ~ Ch161) - * A_INT8 NONTAS 5 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-3, Ch149 ~ Ch161) - * A_INT8 NONTAS 5 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-3, Ch149 ~ Ch161) - * A_INT8 NONTAS 5 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-4, Ch163 ~ Ch177) - * A_INT8 NONTAS 5 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-4, Ch163 ~ Ch177) - * A_INT8 NONTAS 5 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-4, Ch163 ~ Ch177) - * A_INT8 NONTAS 6 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-5) (Ch1, Ch2 ~ Ch41) - * A_INT8 NONTAS 6 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-5) (Ch1, Ch2 ~ Ch41) - * A_INT8 NONTAS 6 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-5) (Ch1, Ch2 ~ Ch41) - * A_INT8 NONTAS 6 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-5) (Ch45 ~ Ch93) - * A_INT8 NONTAS 6 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-5) (Ch45 ~ Ch93) - * A_INT8 NONTAS 6 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-5) (Ch45 ~ Ch93) - * A_INT8 NONTAS 6 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-6) (Ch97~ Ch113) - * A_INT8 NONTAS 6 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-6) (Ch97~ Ch113) - * A_INT8 NONTAS 6 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-6) (Ch97~ Ch113) - * A_INT8 NONTAS 6 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-7) (Ch117~Ch149) - * A_INT8 NONTAS 6 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-7) (Ch117~Ch149) - * A_INT8 NONTAS 6 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-7) (Ch117~Ch149) - * A_INT8 NONTAS 6 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-7) (Ch117~Ch149) - * A_INT8 NONTAS 6 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-7) (Ch117~Ch149) - * A_INT8 NONTAS 6 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-7) (Ch117~Ch149) - * A_INT8 NONTAS 6 GHz SISO (Chain0) Power Limit Value(unit: 0.25dBm) (UNII-8) (Ch117~Ch149) - * A_INT8 NONTAS 6 GHz SISO (Chain1) Power Limit Value(unit: 0.25dBm) (UNII-8) (Ch117~Ch149) - * A_INT8 NONTAS 6 GHz MIMO (Chain0 + Chain1) Power Limit Value(unit: 0.25dBm) (UNII-8) (Ch117~Ch149) */ BIOS_PARAM_TYPE_BANDEDGE_CTL_POWER, @@ -39044,21 +34578,6 @@ typedef enum { * ============================================================== */ - BIOS_PARAM_TYPE_NON_SAR_COUNTRY_CONFIG, - /* - * BIOS_PARAM_TYPE_NON_SAR_COUNTRY_CONFIG structure contains 256 bytes as below - * - * A_UINT8 country_bitmap[NON_SAR_COUNTRY_BITMAP_COUNT];//NON_SAR_COUNTRY_BITMAP_COUNT = 256, 256BYTE. - * 0-255 stand for 256 country, each country has 8 bit for configuration. - * - * ==================each bit configuration=========================== - * BIT0: Skip TAS limit config - * BIT1: Skip SAR limit config - * BIT2: Use domain GEO table. 1: Use Country GEO table - * BIT3~5: index of domain/country used which group GEO offset table - * BIT6~7: reserved - * ==================================================================== - */ BIOS_PARAM_TYPE_MAX, } bios_param_type_e; @@ -39948,43 +35467,6 @@ typedef struct { A_UINT32 pdev_id; } wmi_pdev_get_chip_power_stats_cmd_fixed_param; - -typedef enum { - /* Enable the stats by default*/ - WMI_PDEV_POWER_DATAPATH_STATS_OP_DISABLE = 0, - WMI_PDEV_POWER_DATAPATH_STATS_OP_ENBLE = 1, - WMI_PDEV_POWER_DATAPATH_STATS_OP_RETRIEVE = 2, - WMI_PDEV_POWER_DATAPATH_STATS_OP_MAX, -} WMI_PDEV_POWER_DATAPATH_STATS_OPERATION; - -typedef enum { - WMI_PDEV_POWER_STATS_TYPE = 0x00000001, - WMI_PDEV_DATAPATH_STATS_TYPE = 0x00000002, - WMI_PDEV_POWER_DATAPATH_STATS_ALL = 0x00000003, - WMI_PDEV_SOC_POWER_STATS_TYPE = 0x00000004, - WMI_PDEV_SOC_POWER_DATAPATH_STATS_ALL = 0x00000005, - - - WMI_PDEV_STATS_TYPE_MAX, -} WMI_PDEV_POWER_DATAPATH_STATS_TYPE; - -/* WMI command to enable/disable or get the power/datapath stats */ -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_cmd_fixed_param */ - - /** pdev_id for identifying the MAC - * See macros starting with WMI_PDEV_ID_ for values. - */ - A_UINT32 core_index; - - /** Operation type - distinguishes between enable/disable/retrieve */ - A_UINT32 operation; /* wmi_pdev_power_datapath_stats_operation */ - - /** Stats type bitmap - specifies which stats to enable/disable/retrieve */ - A_UINT32 stats_type_bitmap; /* wmi_pdev_power_datapath_stats_type */ -} wmi_pdev_power_datapath_stats_cmd_fixed_param; - - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_bcn_recv_stats_cmd_fixed_param */ /** VDEV identifier */ @@ -40145,131 +35627,6 @@ typedef struct { */ } wmi_pdev_chip_power_stats_event_fixed_param; - -typedef enum { - WMI_PDEV_RATE_CCK_1M, - WMI_PDEV_RATE_CCK_2M, - WMI_PDEV_RATE_CCK_5M, /* CCK 5.5Mbps */ - WMI_PDEV_RATE_CCK_11M, - WMI_PDEV_RATE_OFDM_6M, - WMI_PDEV_RATE_OFDM_9M, - WMI_PDEV_RATE_OFDM_12M, - WMI_PDEV_RATE_OFDM_18M, - WMI_PDEV_RATE_OFDM_24M, - WMI_PDEV_RATE_OFDM_36M, - WMI_PDEV_RATE_OFDM_48M, - WMI_PDEV_RATE_OFDM_54M, - WMI_PDEV_RATE_MCS0, /* includes HT MCS 0 (1ss)/8 (2ss)/16 (3ss)/24 (4ss), VHT/HE MCS 0 */ - WMI_PDEV_RATE_MCS1, /* includes HT MCS 1 (1ss)/9 (2ss)/17 (3ss)/25 (4ss), VHT/HE MCS 1 */ - WMI_PDEV_RATE_MCS2, /* includes HT MCS 2 (1ss)/10 (2ss)/18 (3ss)/26 (4ss), VHT/HE MCS 2 */ - WMI_PDEV_RATE_MCS3, /* includes HT MCS 3 (1ss)/11 (2ss)/19 (3ss)/27 (4ss), VHT/HE MCS 3 */ - WMI_PDEV_RATE_MCS4, /* includes HT MCS 4 (1ss)/12 (2ss)/20 (3ss)/28 (4ss), VHT/HE MCS 4 */ - WMI_PDEV_RATE_MCS5, /* includes HT MCS 5 (1ss)/13 (2ss)/21 (3ss)/29 (4ss), VHT/HE MCS 5 */ - WMI_PDEV_RATE_MCS6, /* includes HT MCS 6 (1ss)/14 (2ss)/22 (3ss)/30 (4ss), VHT/HE MCS 6 */ - WMI_PDEV_RATE_MCS7, /* includes HT MCS 7 (1ss)/15 (2ss)/23 (3ss)/31 (4ss), VHT/HE MCS 7 */ - WMI_PDEV_RATE_MCS8, /* includes VHT/HE MCS 8 */ - WMI_PDEV_RATE_MCS9, /* includes VHT/HE MCS 9 */ - WMI_PDEV_RATE_MCS10, /* includes VHT/HE MCS 10 */ - WMI_PDEV_RATE_MCS11, /* includes VHT/HE MCS 11 */ - WMI_PDEV_RATE_MCS12, /* includes BE MCS 12 */ - WMI_PDEV_RATE_MCS13, /* includes BE MCS 13 */ - WMI_PDEV_RATE_RATE_IDX_MAX, -} WMI_PDEV_RATE_IDX; - -#define WMI_MAX_SLEEP_LEVELS 5 - -typedef struct { - A_UINT32 tlv_header;/* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_tx_rate_info */ - - /** Common element - core_index (PDEV ID) */ - A_UINT32 core_index; - - /* An index representing a specific transmit data rate */ - A_UINT32 rate_index; - - /* - * The operating band of the transmit rate. - * 0: 2.4 GHz, 1: 5 GHz, 2: 6 GHz - */ - A_UINT32 band; - - /* - * The bandwidth of the transmit rate. - * 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 MHz, 4: 320 MHz - */ - A_UINT32 bw; - - /* - * The number of spatial streams (NSS) used for this transmit rate. - * 0: NSS1, 1: NSS2, 2: NSS3, 3: NSS4, 4: NSS5 - */ - A_UINT32 nss; - - /* - * The number of times a transmit occurred with this specific - * combination of rate index, band, bandwidth, and NSS - */ - A_UINT32 count; - A_UINT32 tx_retry_count; /* accumulated over time */ -} wmi_pdev_tx_rate_info; - -/* Power stats in event payload*/ -typedef struct { - /** Power Statistics */ - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_power_stats_info */ - - /** Common element - core_index (PDEV ID) */ - A_UINT32 core_index; - - A_UINT32 radio_on_time; /* Time radio was on (ms) */ - A_UINT32 radio_off_time; /* Time radio was off (ms) */ - A_UINT32 wlan_pwr_on_time; /* WLAN power on time (ms) */ - /* tx_time: - * ms duration the radio is in a continuous transmit state - * encompassing all packet types (management, data, action frames) - */ - A_UINT32 tx_time; - /* rx_time: - * ms duration the radio is in a continuous receiving data state - * Including all Rx packets instead of only collecting for my BSS data - */ - A_UINT32 rx_time; - - /* Number of sleep levels being sent to the host */ - A_UINT32 sleep_levels_num; - A_UINT32 sleep_time_per_levels[WMI_MAX_SLEEP_LEVELS]; /* ms */ -} wmi_pdev_power_stats_info; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_power_datapath_stats_event_fixed_param */ - - /** Status of the operation */ - A_UINT32 status; /* 0 = success, non-zero = error */ - - /** Stats type bitmap indicating which stats are included */ - A_UINT32 stats_type_bitmap; - - A_UINT32 wlan_soc_pwr_on_time; /* WLAN power on time (ms) */ - - /* wlan_soc_sleep_levels_num: - * Number of sleep levels supported. - * Could be less than WMI_MAX_SLEEP_LEVELS based on the chip. - */ - A_UINT32 wlan_soc_sleep_levels_num; - - /** soc sleep level. Same WMI_MAX_SLEEP_LEVELS is used for sizing */ - A_UINT32 wlan_soc_sleep_time_per_level[WMI_MAX_SLEEP_LEVELS]; /* ms */ - - /* - * Following this structure are the TLVs: - * wmi_pdev_power_stats_info[num_cores]; - * wmi_pdev_tx_rate_info[num_tx_rate_info] - * where num_cores and num_tx_rate_info are determined from the TLV array - * (i.e. array size / array element size) - */ -} wmi_pdev_power_datapath_stats_event_fixed_param; - - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_get_bcn_recv_stats_fixed_param */ A_UINT32 vdev_id; @@ -41050,7 +36407,7 @@ typedef enum { typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_request_wlan_stats_cmd_fixed_param */ - A_UINT32 stats_id; /* wmi_wlan_stats_id */ + wmi_wlan_stats_id stats_id; } wmi_request_wlan_stats_cmd_fixed_param; typedef enum { @@ -41106,10 +36463,6 @@ typedef enum { WMI_REQUEST_CTRL_PATH_PDEV_BCN_TX_STAT = 20, WMI_REQUEST_CTRL_PATH_PDEV_CONN_STAT = 21, WMI_REQUEST_CTRL_PATH_ML_RECONFIG_STAT = 22, - WMI_REQUEST_CTRL_PATH_STA_DAR_STAT = 23, - WMI_REQUEST_ENHANCED_STAT = 24, - WMI_REQUEST_CTRL_PATH_EM_PCIE_STAT = 25, - WMI_REQUEST_CTRL_PATH_EM_DCVS_STAT = 26, } wmi_ctrl_path_stats_id; typedef enum { @@ -41129,16 +36482,6 @@ typedef enum { WMI_REQUEST_CTRL_PATH_STAT_PERIODIC_PUBLISH = 5, } wmi_ctrl_path_stats_action; -typedef enum { - /* - * The following stats actions are mutually exclusive. - * A single stats request message can only specify one action. - */ - WMI_REQUEST_CTRL_PATH_STAT_DEFAULT = 0, /* unspecified granularity */ - WMI_REQUEST_CTRL_PATH_STAT_AC_LEVEL = 1, - WMI_REQUEST_CTRL_PATH_STAT_TID_LEVEL = 2, -} wmi_ctrl_path_stats_granularity; - typedef enum { WMI_HALPHY_CTRL_PATH_SU_STATS = 0, WMI_HALPHY_CTRL_PATH_SUTXBF_STATS, @@ -41175,13 +36518,6 @@ typedef struct { */ A_UINT32 stat_periodicity; - /** stats_granularity: - * Configures AC vs. TID granularity stats reporting, - * e.g. for STA_DAR_STATs. - * Possible values are listed in the wmi_ctrl_path_stats_granularity enum. - */ - A_UINT32 stats_granularity; /* refer to wmi_ctrl_path_stats_granularity */ - /** The below TLV arrays optionally follow this fixed_param TLV structure: * 1. A_UINT32 pdev_ids[]; * If this array is present and non-zero length, stats should only @@ -41259,16 +36595,6 @@ typedef struct { A_UINT32 reset_after_request; } wmi_request_radio_chan_stats_cmd_fixed_param; -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_request_tdls_stats_cmd_fixed_param */ - A_UINT32 tlv_header; - /** VDEV identifier */ - A_UINT32 vdev_id; - /* flag to enable or disable this feature of getting TDLS stats */ - A_UINT32 enable; -} wmi_request_tdls_stats_cmd_fixed_param; - typedef struct { /** TLV tag and len; tag equals * WMITLV_TAG_STRUC_wmi_rmc_set_leader_cmd_fixed_param */ @@ -41506,9 +36832,6 @@ typedef enum wmi_hw_mode_config_type { #define WMI_SUPPORT_11BE_GET(flags) WMI_GET_BITS(flags, 6, 1) #define WMI_SUPPORT_11BE_SET(flags, value) WMI_SET_BITS(flags, 6, 1, value) -#define WMI_SUPPORT_11BN_GET(flags) WMI_GET_BITS(flags, 7, 1) -#define WMI_SUPPORT_11BN_SET(flags, value) WMI_SET_BITS(flags, 7, 1, value) - #define WMI_MAX_MUBFEE_GET(flags) WMI_GET_BITS(flags, 28, 4) #define WMI_MAX_MUBFEE_SET(flags, value) WMI_SET_BITS(flags, 28, 4, value) @@ -41688,9 +37011,8 @@ typedef struct { supports_11ac:1, supports_11ax:1, supports_11be:1, - supports_11bn:1, - unused: 20, + unused: 21, max_mubfee: 4; /* max MU beamformees supported per MAC */ }; @@ -41954,601 +37276,6 @@ typedef struct { }; } WMI_MAC_PHY_CAPABILITIES_EXT; -/* WMI Maximum Tx/Rx NSS information */ -#define WMI_MAC_PHY_CAPABILITIES_EXT2_MAX_TX_NSS_SET(param, value) \ - WMI_SET_BITS(param, 0, 4, value) -#define WMI_MAC_PHY_CAPABILITIES_EXT2_MAX_TX_NSS_GET(dword) \ - WMI_GET_BITS(dword, 0, 4) - -#define WMI_MAC_PHY_CAPABILITIES_EXT2_MAX_RX_NSS_SET(param, value) \ - WMI_SET_BITS(param, 4, 4, value) -#define WMI_MAC_PHY_CAPABILITIES_EXT2_MAX_RX_NSS_GET(dword) \ - WMI_GET_BITS(dword, 4, 4) - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES_EXT2 */ - - /* hw_mode_id: - * Identify a particular set of HW characteristics, as specified by - * the subsequent fields. - * WMI_MAC_PHY_CAPABILITIES element must be mapped to its parent - * WMI_HW_MODE_CAPABILITIES element using hw_mode_id. - * No particular ordering of WMI_MAC_PHY_CAPABILITIES elements - * should be assumed, though in practice the elements will likely - * be ordered by hw_mode_id. - */ - A_UINT32 hw_mode_id; - - /* - * pdev_id starts with 1. pdev_id 1 => phy_id 0, pdev_id 2 => phy_id 1 - * hw_link_id: Unique link id across SOCs, got as part of QMI handshake. - * For legacy chips which do not support MLO, these top bits will always - * be set to 0, so it won't impact the legacy chips which treat pdev_id - * as 32 bits. - */ - union { - struct { - A_UINT32 pdev_id:16, - hw_link_id:16; - } pdev_to_link_map; - A_UINT32 pdev_to_link_map_word32; - }; - /* phy id. Starts with 0 */ - A_UINT32 phy_id; - A_UINT32 wireless_modes_ext; /* REGDMN MODE EXT, see REGDMN_MODE_ enum */ - - /************************************************************************** - * following new params are for 802.11bn, but under development - **************************************************************************/ - /* UHR capability mac info field of 802.11bn */ - A_UINT32 uhr_cap_mac_info_2G[WMI_MAX_UHRCAP_MAC_SIZE]; - A_UINT32 uhr_cap_mac_info_5G[WMI_MAX_UHRCAP_MAC_SIZE]; - - /* UHR capability phy field of 802.11bn, WMI_UHR_CAP defines */ - A_UINT32 uhr_cap_phy_info_2G[WMI_MAX_UHRCAP_PHY_SIZE]; - A_UINT32 uhr_cap_phy_info_5G[WMI_MAX_UHRCAP_PHY_SIZE]; - - union { - struct { - A_UINT32 npca_enabled:1, /* bit 0 */ - npca_min_dur_threshold:4, /* bits 4:1 */ - npca_switch_delay:6, /* bits 10:5 */ - npca_switch_back_delay:6, /* bits 16:11 */ - npca_qsrc:2, /* bits 18:17 */ - npca_moplen:1, /* bit 19 */ - reserved: 12; - }; - A_UINT32 npca_capability; - }; - wmi_ppe_threshold uhr_ppet2G; - wmi_ppe_threshold uhr_ppet5G; - - /* nss_info: - * Bits 3:0 - Maximum suported Tx NSS - * Bits 7:4 - Maximum suported Rx NSS - * Bits 31:8 - Reserved - */ - union { - A_UINT32 nss_info; - struct { - A_UINT32 - max_tx_nss: 4, - max_rx_nss: 4, - reserved2: 24; - }; - }; - - /* - * UHR DBE Capability Parameters of 802.11bn - * (conditional on DBE Support bit) - */ - A_UINT32 uhr_cap_dbe_info_2G[WMI_MAX_UHRCAP_DBE_SIZE]; - A_UINT32 uhr_cap_dbe_info_5G[WMI_MAX_UHRCAP_DBE_SIZE]; -} WMI_MAC_PHY_CAPABILITIES_EXT2; - -#define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_PDEV_ID_GET(pdev_to_link_map_word32) \ - WMI_GET_BITS(pdev_to_link_map_word32, 0, 16) -#define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_PDEV_ID_SET(pdev_to_link_map_word32, val) \ - WMI_SET_BITS(pdev_to_link_map_word32, 0, 16, val) - -#define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_HW_LINK_ID_GET(pdev_to_link_map_word32) \ - WMI_GET_BITS(pdev_to_link_map_word32, 16, 16) -#define WMI_CAP_EXT2_PDEV_TO_LINK_MAP_HW_LINK_ID_SET(pdev_to_link_map_word32, val) \ - WMI_SET_BITS(pdev_to_link_map_word32, 16, 16, val) - -/****** 11BN UHR PHY Capabilities Information field ******/ /* { */ - -/* Bit 0: Max Nss Rx for sounding NDP (≤ 80 MHz) */ -#define WMI_UHRCAP_PHY_MAX_NSS_RX_80_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 0, 1) -#define WMI_UHRCAP_PHY_MAX_NSS_RX_80_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 0, 1, value) - -/* Bit 1: Max Nss,total Rx for DL MU-MIMO (≤ 80 MHz) */ -#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_80_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 1, 1) -#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_80_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 1, 1, value) - -/* Bit 2: Max Nss Rx for sounding NDP (= 160 MHz) */ -#define WMI_UHRCAP_PHY_MAX_NSS_RX_160_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 2, 1) -#define WMI_UHRCAP_PHY_MAX_NSS_RX_160_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 2, 1, value) - -/* Bit 3: Max Nss,total Rx for DL MU-MIMO (= 160 MHz) */ -#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_160_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 3, 1) -#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_160_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 3, 1, value) - -/* Bit 4: Max Nss Rx for sounding NDP (= 320 MHz) */ -#define WMI_UHRCAP_PHY_MAX_NSS_RX_320_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 4, 1) -#define WMI_UHRCAP_PHY_MAX_NSS_RX_320_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 4, 1, value) - -/* Bit 5: Max Nss,total Rx for DL MU-MIMO (= 320 MHz) */ -#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_320_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 5, 1) -#define WMI_UHRCAP_PHY_MAX_NSS_DL_MU_320_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 5, 1, value) - -/* Bit 6: ELR Tx Support */ -#define WMI_UHRCAP_PHY_ELR_TX_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 6, 1) -#define WMI_UHRCAP_PHY_ELR_TX_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 6, 1, value) - -/* Bit 7: ELR Rx Support */ -#define WMI_UHRCAP_PHY_ELR_RX_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 7, 1) -#define WMI_UHRCAP_PHY_ELR_RX_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 7, 1, value) - -/* Bit 8: Partial BW DL MU-MIMO support */ -#define WMI_UHRCAP_PHY_PARTIAL_BW_DL_MU_MIMO_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 8, 1) -#define WMI_UHRCAP_PHY_PARTIAL_BW_DL_MU_MIMO_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 8, 1, value) - -/* Bit 9: Partial BW UL MU-MIMO support */ -#define WMI_UHRCAP_PHY_PARTIAL_BW_UL_MU_MIMO_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 9, 1) -#define WMI_UHRCAP_PHY_PARTIAL_BW_UL_MU_MIMO_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 9, 1, value) - -/* Bit 10: MCS 15 support */ -#define WMI_UHRCAP_PHY_MCS_15_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 10, 1) -#define WMI_UHRCAP_PHY_MCS_15_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 10, 1, value) - -/* Bit 11: 2XLDPC Tx Support */ -#define WMI_UHRCAP_PHY_2XLDPC_TX_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 11, 1) -#define WMI_UHRCAP_PHY_2XLDPC_TX_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 11, 1, value) - -/* Bit 12: 2XLDPC Rx Support */ -#define WMI_UHRCAP_PHY_2XLDPC_RX_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 12, 1) -#define WMI_UHRCAP_PHY_2XLDPC_RX_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 12, 1, value) - -/* Bits 13-14: UEQM Tx Support and Max NSS Tx */ -#define WMI_UHRCAP_PHY_UEQM_TX_MAX_NSS_TX_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 13, 2) -#define WMI_UHRCAP_PHY_UEQM_TX_MAX_NSS_TX_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 13, 2, value) - -/* Bits 15-16: UEQM Rx Support and Max NSS Rx */ -#define WMI_UHRCAP_PHY_UEQM_RX_MAX_NSS_RX_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 15, 2) -#define WMI_UHRCAP_PHY_UEQM_RX_MAX_NSS_RX_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 15, 2, value) - -/* Bit 17: Reserved */ - -/* Bit 18: Co-BF joint sounding support */ -#define WMI_UHRCAP_PHY_COBF_JOINT_SOUNDING_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 18, 1) -#define WMI_UHRCAP_PHY_COBF_JOINT_SOUNDING_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 18, 1, value) - -/* Bit 19: IM pilots tx support */ -#define WMI_UHRCAP_PHY_IM_PILOTS_TX_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 19, 1) -#define WMI_UHRCAP_PHY_IM_PILOTS_TX_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 19, 1, value) - -/* Bit 20: IM pilots rx support */ -#define WMI_UHRCAP_PHY_IM_PILOTS_RX_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 20, 1) -#define WMI_UHRCAP_PHY_IM_PILOTS_RX_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 20, 1, value) - -/* Bit 21: COSR mode 1 support */ -#define WMI_UHRCAP_PHY_COSR_MODE_1_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 21, 1) -#define WMI_UHRCAP_PHY_COSR_MODE_1_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 21, 1, value) - -/* Bit 22: COSR mode 2 support */ -#define WMI_UHRCAP_PHY_COSR_MODE_2_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 22, 1) -#define WMI_UHRCAP_PHY_COSR_MODE_2_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 22, 1, value) - -/* Bit 23: DRU DBW 20 in PBW 20 support */ -#define WMI_UHRCAP_PHY_DRU_DBW_20_PBW_20_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 23, 1) -#define WMI_UHRCAP_PHY_DRU_DBW_20_PBW_20_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 23, 1, value) - -/* Bit 24: DRU DBW 40 in PBW 40 support */ -#define WMI_UHRCAP_PHY_DRU_DBW_40_PBW_40_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 24, 1) -#define WMI_UHRCAP_PHY_DRU_DBW_40_PBW_40_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 24, 1, value) - -/* Bit 25: DRU DBW 80 in PBW 80 support */ -#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_80_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 25, 1) -#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_80_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 25, 1, value) - -/* Bit 26: DRU DBW 80 in PBW 160 MHz support */ -#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_160_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 26, 1) -#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_160_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 26, 1, value) - -/* Bit 27: DRU DBW 80 in PBW 320 MHz support */ -#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_320_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 27, 1) -#define WMI_UHRCAP_PHY_DRU_DBW_80_PBW_320_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 27, 1, value) - -/* Bit 28: DRU DBW 20 in PBW >= 80 MHz support */ -#define WMI_UHRCAP_PHY_DRU_DBW_20_PBW_80_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 28, 1) -#define WMI_UHRCAP_PHY_DRU_DBW_20_PBW_80_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 28, 1, value) - -/* Bit 29: DRU DBW 40 in PBW >= 80 MHz support */ -#define WMI_UHRCAP_PHY_DRU_DBW_40_PBW_80_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 29, 1) -#define WMI_UHRCAP_PHY_DRU_DBW_40_PBW_80_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 29, 1, value) - -/* Bit 30: DRU DBW 60 in PBW >= 80 MHz support */ -#define WMI_UHRCAP_PHY_DRU_DBW_60_PBW_80_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 30, 1) -#define WMI_UHRCAP_PHY_DRU_DBW_60_PBW_80_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 30, 1, value) - -/* Bit 31: DRU+RRU hybrid mode support */ -#define WMI_UHRCAP_PHY_DRU_RRU_HYBRID_SUPPORT_GET(uhr_cap_phy) \ - WMI_GET_BITS(uhr_cap_phy[0], 31, 1) -#define WMI_UHRCAP_PHY_DRU_RRU_HYBRID_SUPPORT_SET(uhr_cap_phy, value) \ - WMI_SET_BITS(uhr_cap_phy[0], 31, 1, value) - -/* Bits 32-39: Reserved */ - -/* - * ToDo: Bits 40-63 - */ - -/* - * ToDo: Bits 64-95 - */ - -/* - * ToDO: Bits 96-127 - */ - -/* - * ToDo: Bits 128-159 - */ - -/* - * ToDo: Bits 160-191 - */ - -/* - * ToDo: Bits 192-223 - */ - -/* - * ToDo: Bits 224-255 - */ - -/****** End of 11BN UHR PHY Capabilities Information field ******/ /* } */ - -/****** 11BN UHR MAC Capabilities Information field ******/ /* { */ - -/* Bit 0: DPS Support */ -#define WMI_UHRCAP_MAC_DPS_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 0, 1) -#define WMI_UHRCAP_MAC_DPS_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 0, 1, value) - -/* Bit 1: DPS Assisting support */ -#define WMI_UHRCAP_MAC_DPS_ASSIS_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 1, 1) -#define WMI_UHRCAP_MAC_DPS_ASSIS_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 1, 1, value) - -/* Bit 2: DPS AP Static HCM Support */ -#define WMI_UHRCAP_MAC_DPS_AP_HCM_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 2, 1) -#define WMI_UHRCAP_MAC_DPS_AP_HCM_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 2, 1, value) - -/* Bit 3: Reserved */ - -/* Bit 4: NPCA support */ -#define WMI_UHRCAP_MAC_NPCA_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 4, 1) -#define WMI_UHRCAP_MAC_NPCA_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 4, 1, value) - -/* Bit 5: Enhanced BSR support */ -#define WMI_UHRCAP_MAC_BSR_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 5, 1) -#define WMI_UHRCAP_MAC_BSR_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 5, 1, value) - -/* Bit 6: Additional Mapped TID Support */ -#define WMI_UHRCAP_MAC_ADDITIONAL_TID_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 6, 1) -#define WMI_UHRCAP_MAC_ADDITIONAL_TID_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 6, 1, value) - -/* Bit 7: EOTSP Support */ -#define WMI_UHRCAP_MAC_EOTSP_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 7, 1) -#define WMI_UHRCAP_MAC_EOTSP_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 7, 1, value) - -/* Bit 8: DSO Support */ -#define WMI_UHRCAP_MAC_DSO_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 8, 1) -#define WMI_UHRCAP_MAC_DSO_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 8, 1, value) - -/* Bit 9: P-EDCA Support */ -#define WMI_UHRCAP_MAC_P_EDCA_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 9, 1) -#define WMI_UHRCAP_MAC_P_EDCA_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 9, 1, value) - -/* Bit 10: DBE Support */ -#define WMI_UHRCAP_MAC_DBE_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 10, 1) -#define WMI_UHRCAP_MAC_DBE_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 10, 1, value) - -/* Bit 11: UL LLI Support */ -#define WMI_UHRCAP_MAC_UL_LLI_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 11, 1) -#define WMI_UHRCAP_MAC_UL_LLI_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 11, 1, value) - -/* Bit 12: Peer-to-Peer LLI Support */ -#define WMI_UHRCAP_MAC_PEER_LLI_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 12, 1) -#define WMI_UHRCAP_MAC_PEER_LLI_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 12, 1, value) - -/* Bit 13: PUO Support */ -#define WMI_UHRCAP_MAC_PUO_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 13, 1) -#define WMI_UHRCAP_MAC_PUO_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 13, 1, value) - -/* Bit 14: AP PUO Support */ -#define WMI_UHRCAP_MAC_AP_PUO_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 14, 1) -#define WMI_UHRCAP_MAC_AP_PUO_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 14, 1, value) - -/* Bit 15: DUO Support */ -#define WMI_UHRCAP_MAC_DUO_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 15, 1) -#define WMI_UHRCAP_MAC_DUO_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 15, 1, value) - -/* Bit 16: OM Control UL MU Data Disable RX Support */ -#define WMI_UHRCAP_MAC_OM_CTRL_UL_MU_DISABLE_RX_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 16, 1) -#define WMI_UHRCAP_MAC_OM_CTRL_UL_MU_DISABLE_RX_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 16, 1, value) - -/* Bit 17: AOM Support */ -#define WMI_UHRCAP_MAC_AOM_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 17, 1) -#define WMI_UHRCAP_MAC_AOM_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 17, 1, value) - -/* Bit 18: IFCS Location Support */ -#define WMI_UHRCAP_MAC_IFCS_LOC_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 18, 1) -#define WMI_UHRCAP_MAC_IFCS_LOC_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 18, 1, value) - -/* Bit 19: UHR TRS Support */ -#define WMI_UHRCAP_MAC_UHR_TRS_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 19, 1) -#define WMI_UHRCAP_MAC_UHR_TRS_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 19, 1, value) - -/* Bit 20: TXSPG Support */ -#define WMI_UHRCAP_MAC_TXSPG_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 20, 1) -#define WMI_UHRCAP_MAC_TXSPG_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 20, 1, value) - -/* Bit 21: TXOP Return Support in TXSPG */ -#define WMI_UHRCAP_MAC_TXOP_RETURN_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 21, 1) -#define WMI_UHRCAP_MAC_TXOP_RETURN_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 21, 1, value) - -/* Bit 22 - 25: UHR Operating Mode And Parameters Update Timeout - * - * UHR Operating Mode And Parameters Update Timeout Lookup Table - * - * +------------------+-----------------------------+ - * | Sub-field Value | Timeout Duration | - * +------------------+-----------------------------+ - * | 0 | 0 TUs | - * | 1 | 128 µs | - * | 2 | 256 µs | - * | 3 | 512 µs | - * | 4 | 1 TU | - * | 5 | 2 TUs | - * | 6 | 4 TUs | - * | 7 | 8 TUs | - * | 8 | 16 TUs | - * | 9 | 32 TUs | - * | 10 | 64 TUs | - * | 11 | 128 TUs | - * | 12 - 15 | Reserved for future use | - * +------------------+-----------------------------+ - */ -#define WMI_UHRCAP_MAC_UHR_OPMODE_TIMEOUT_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 22, 4) -#define WMI_UHRCAP_MAC_UHR_OPMODE_TIMEOUT_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 22, 4, value) - -/* Bit 26 - 28 : Parameter Update Adv Notification Interval */ -#define WMI_UHRCAP_MAC_PARAM_UPDATE_ADV_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[0], 26, 3) -#define WMI_UHRCAP_MAC_PARAM_UPDATE_ADV_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[0], 26, 3, value) - -/* Bit 29-33: Update Indication In TIM Interval */ -#define WMI_UHRCAP_MAC_UPDATE_IND_TIM_GET(uhr_cap_mac) \ - (WMI_GET_BITS(uhr_cap_mac[0], 29, 3) | \ - (WMI_GET_BITS(uhr_cap_mac[1], 0, 2) << 3)) -#define WMI_UHRCAP_MAC_UPDATE_IND_TIM_SET(uhr_cap_mac, value) \ - do { \ - WMI_SET_BITS(uhr_cap_mac[0], 29, 3, value & 0x7); \ - WMI_SET_BITS(uhr_cap_mac[1], 0, 2, ((value & 0x18) >> 3)); \ - } while (0) - -/* Bit 34: Bounded ESS */ -#define WMI_UHRCAP_MAC_BOUNDED_ESS_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[1], 3, 1) -#define WMI_UHRCAP_MAC_BOUNDED_ESS_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[1], 3, 1, value) - -/* Bit 35: BTM Assurance */ -#define WMI_UHRCAP_MAC_BTM_ASSURANCE_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[1], 4, 1) -#define WMI_UHRCAP_MAC_BTM_ASSURANCE_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[1], 4, 1, value) - -/* Bit 36: Co-BF Support */ -#define WMI_UHRCAP_MAC_COBF_SUPPORT_GET(uhr_cap_mac) \ - WMI_GET_BITS(uhr_cap_mac[1], 5, 1) -#define WMI_UHRCAP_MAC_COBF_SUPPORT_SET(uhr_cap_mac, value) \ - WMI_SET_BITS(uhr_cap_mac[1], 5, 1, value) - -/* Bits 37-63 --- Reserved */ - -/* - * NOTE: uhr_cap_mac[2] and uhr_cap_mac[3] (bits 64-127) are reserved. - * WMI_MAX_UHRCAP_MAC_SIZE is kept at 4 for backward compatibility. - * DBE Capability Parameters are carried in the separate uhr_cap_dbe[] - * array using WMI_UHRCAP_DBE_* macros below. - */ - -/****** End of 11BN UHR MAC Capabilities Information field ******/ /* } */ - -/****** 11BN UHR DBE Capability Parameters field ******/ /* { */ - -/* Bits B0-B2: DBE Maximum Supported Bandwidth - * - * DBE Maximum Supported Bandwidth Lookup Table - * - * +------------------+-----------------------------+ - * | Sub-field Value | DBE Bandwidth | - * +------------------+-----------------------------+ - * | 0 | Reserved | - * | 1 | 40 MHz DBE bandwidth | - * | 2 | 80 MHz DBE bandwidth | - * | 3 | 160 MHz DBE bandwidth | - * | 4 | 320 MHz DBE bandwidth | - * | 5 to 7 | Reserved | - * +------------------+-----------------------------+ - */ -#define WMI_UHRCAP_DBE_MAX_SUP_BW_GET(uhr_cap_dbe) \ - WMI_GET_BITS(uhr_cap_dbe[0], 0, 3) -#define WMI_UHRCAP_DBE_MAX_SUP_BW_SET(uhr_cap_dbe, value) \ - WMI_SET_BITS(uhr_cap_dbe[0], 0, 3, value) - -/* Bit B3: EHT-MCS Map (BW=160 MHz) Present */ -#define WMI_UHRCAP_DBE_EHT_MCS_160_PRESENT_GET(uhr_cap_dbe) \ - WMI_GET_BITS(uhr_cap_dbe[0], 3, 1) -#define WMI_UHRCAP_DBE_EHT_MCS_160_PRESENT_SET(uhr_cap_dbe, value) \ - WMI_SET_BITS(uhr_cap_dbe[0], 3, 1, value) - -/* Bit B4: EHT-MCS Map (BW=320 MHz) Present */ -#define WMI_UHRCAP_DBE_EHT_MCS_320_PRESENT_GET(uhr_cap_dbe) \ - WMI_GET_BITS(uhr_cap_dbe[0], 4, 1) -#define WMI_UHRCAP_DBE_EHT_MCS_320_PRESENT_SET(uhr_cap_dbe, value) \ - WMI_SET_BITS(uhr_cap_dbe[0], 4, 1, value) - -/* Bits B5-B7: Reserved */ - -/* Bits B8-B31: EHT-MCS Map (BW=160 MHz) — present only if B3 is set (0 or 24 bits) */ -#define WMI_UHRCAP_DBE_EHT_MCS_MAP_160_GET(uhr_cap_dbe) \ - WMI_GET_BITS(uhr_cap_dbe[0], 8, 24) -#define WMI_UHRCAP_DBE_EHT_MCS_MAP_160_SET(uhr_cap_dbe, value) \ - WMI_SET_BITS(uhr_cap_dbe[0], 8, 24, value) - -/* Bits B32-B55: EHT-MCS Map (BW=320 MHz) — present only if B4 is set (0 or 24 bits) */ -#define WMI_UHRCAP_DBE_EHT_MCS_MAP_320_GET(uhr_cap_dbe) \ - WMI_GET_BITS(uhr_cap_dbe[1], 0, 24) -#define WMI_UHRCAP_DBE_EHT_MCS_MAP_320_SET(uhr_cap_dbe, value) \ - WMI_SET_BITS(uhr_cap_dbe[1], 0, 24, value) - -/****** End of 11BN UHR DBE Capability Parameters field ******/ /* } */ - -#define WMI_CAP_EXT2_NPCA_ENABLED_GET(npca_capability) \ - WMI_GET_BITS(npca_capability, 0, 1) -#define WMI_CAP_EXT2_NPCA_ENABLED_SET(npca_capability, value) \ - WMI_SET_BITS(npca_capability, 0, 1, value) - -#define WMI_CAP_EXT2_NPCA_MIN_DUR_THRESHOLD_GET(npca_capability) \ - WMI_GET_BITS(npca_capability, 1, 4) -#define WMI_CAP_EXT2_NPCA_MIN_DUR_THRESHOLD_SET(npca_capability, value) \ - WMI_SET_BITS(npca_capability, 1, 5, value) - -#define WMI_CAP_EXT2_NPCA_SWITCH_DELAY_GET(npca_capability) \ - WMI_GET_BITS(npca_capability, 5, 6) -#define WMI_CAP_EXT2_NPCA_SWITCH_DELAY_SET(npca_capability, value) \ - WMI_SET_BITS(npca_capability, 5, 6, value) - -#define WMI_CAP_EXT2_NPCA_SWITCH_BACK_DELAY_GET(npca_capability) \ - WMI_GET_BITS(npca_capability, 11, 6) -#define WMI_CAP_EXT2_NPCA_SWITCH_BACK_DELAY_SET(npca_capability, value) \ - WMI_SET_BITS(npca_capability, 11, 6, value) - -#define WMI_CAP_EXT2_NPCA_QSRC_GET(npca_capability) \ - WMI_GET_BITS(npca_capability, 17, 2) -#define WMI_CAP_EXT2_NPCA_QSRC_SET(npca_capability, value) \ - WMI_SET_BITS(npca_capability, 17, 2, value) - -#define WMI_CAP_EXT2_NPCA_MOPLEN_GET(npca_capability) \ - WMI_GET_BITS(npca_capability, 19, 1) -#define WMI_CAP_EXT2_NPCA_MOPLEN_SET(npca_capability, value) \ - WMI_SET_BITS(npca_capability, 19, 1, value) - - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_HW_MODE_CAPABILITIES */ /* hw_mode_id - identify a particular set of HW characteristics, @@ -42766,7 +37493,6 @@ typedef struct { */ typedef enum { WMI_TWT_STA_SYNC_EVENT_CAP = 1, /* STA TWT: FW internal errors reported using sync WMI_TWT_ACK_EVENTID */ - WMI_TWT_FLEXI_SUPPORT = 2, /* Add new TWT Caps above */ WMI_TWT_MAX_CAP = 32, @@ -43254,8 +37980,6 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) /* set peer to associated state. will cary all parameters * determined during assocication time */ WMI_RETURN_STRING(WMI_PEER_ASSOC_CMDID); - /* peer assoc v2 cmd should be used for non-legacy targets */ - WMI_RETURN_STRING(WMI_PEER_ASSOC_V2_CMDID); /* add a wds (4 address ) entry. used only for testing * WDS feature on AP products */ WMI_RETURN_STRING(WMI_PEER_ADD_WDS_ENTRY_CMDID); @@ -43981,49 +38705,6 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_MLO_LINK_RECONFIG_COMPLETE_CMDID); WMI_RETURN_STRING(WMI_SAWF_EZMESH_HOP_COUNT_CMDID); WMI_RETURN_STRING(WMI_VDEV_VBSS_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_NDP_SET_LATENCY_TPUT_CMDID); - WMI_RETURN_STRING(WMI_MLO_LINK_TTLM_COMPLETE_CMDID); - WMI_RETURN_STRING(WMI_BPF_SET_SUPPORTED_OFFLOAD_BITMAP_CMDID); - WMI_RETURN_STRING(WMI_BPF_SET_APF_MODE_CMDID); - WMI_RETURN_STRING(WMI_ENERGY_MGMT_PCIE_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_ENERGY_MGMT_PCIE_LPM_CMDID); - WMI_RETURN_STRING(WMI_ENERGY_MGMT_DCVS_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_ENERGY_MGMT_EDPS_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_ENERGY_MGMT_PUO_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_ENERGY_MGMT_ECO_MODE_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_PEER_TID_RATE_CUSTOM_CMDID); - WMI_RETURN_STRING(WMI_VDEV_GET_TPC_IE_POWER_CMDID); - WMI_RETURN_STRING(WMI_VDEV_TRAFFIC_MONITORING_CMDID); - WMI_RETURN_STRING(WMI_VDEV_ENERGY_MGMT_DPS_ASSISTING_ROLE_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_WLAN_MODE_REQ_CMDID); - WMI_RETURN_STRING(WMI_NAN_ENABLE_CMDID); - WMI_RETURN_STRING(WMI_NAN_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_NAN_DISABLE_CMDID); - WMI_RETURN_STRING(WMI_ROAM_SMD_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_ROAM_SMD_START_STATUS_CMDID); - WMI_RETURN_STRING(WMI_VDEV_REPURPOSE_RESP_CMDID); - WMI_RETURN_STRING(WMI_IPA_RING_STATS_REQ_CMDID); - WMI_RETURN_STRING(WMI_PDEV_POWER_DATAPATH_STATS_CMDID); - WMI_RETURN_STRING(WMI_SMD_ROAM_CONFIG_CMDID); - WMI_RETURN_STRING(WMI_SMD_ROAM_PEER_UNIFIED_SETUP_CMDID); - WMI_RETURN_STRING(WMI_VDEV_UNIFIED_CONNECT_CMDID); - WMI_RETURN_STRING(WMI_VDEV_UNIFIED_DISCONNECT_CMDID); - WMI_RETURN_STRING(WMI_NAN_LOCAL_SCHEDULE_CMDID); - WMI_RETURN_STRING(WMI_NAN_PEER_SCHEDULE_CMDID); - WMI_RETURN_STRING(WMI_NAN_PEER_PARAMS_CMDID); - WMI_RETURN_STRING(WMI_ENERGY_MGMT_OEM_DATA_CMDID); - WMI_RETURN_STRING(WMI_TWT_ADD_CH_USAGE_CMDID); - WMI_RETURN_STRING(WMI_COEX_GET_POLICY_STATS_CMDID); - WMI_RETURN_STRING(WMI_PEER_UHR_OMP_CMDID); - WMI_RETURN_STRING(WMI_REQUEST_TDLS_STATS_CMDID); - WMI_RETURN_STRING(WMI_GET_CHIPSET_LOGGING_STATS_CMDID); - WMI_RETURN_STRING(WMI_VDEV_GET_CHAN_HOP_STATUS_REPORT_CMDID); - WMI_RETURN_STRING(WMI_NAN_DISC_SERVICE_REQ_CMDID); - WMI_RETURN_STRING(WMI_NAN_DISC_CANCEL_SERVICE_REQ_CMDID); - WMI_RETURN_STRING(WMI_SET_MODIFY_TX_PLIM_CMDID); - WMI_RETURN_STRING(WMI_GET_AVG_TX_POWER_CMDID); - WMI_RETURN_STRING(WMI_GET_TX_POWER_CALLING_CMDID); - WMI_RETURN_STRING(WMI_ATHDIAG_READ_WRITE_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; @@ -44445,10 +39126,9 @@ typedef struct { A_UINT32 num_6g_reg_rules_client_lpi[WMI_REG_CLIENT_MAX]; A_UINT32 num_6g_reg_rules_client_vlp[WMI_REG_CLIENT_MAX]; /* - * NOTE: We cannot add new parameters to the fixed param TLV though - * we have enough buffer size (WMI_SVC_MSG_SIZE) for the given WMI event. - * This is due to a crash seen in the host parsing logic of this fixed param. - * New params can be added in the same message but in other TLVs. + * NOTE: no further fields can be added into this struct, due to + * message buffer size limitations in certain targets for the + * WMI_REG_CHAN_LIST_CC_EXT_EVENT message. */ /* * This fixed_param TLV is followed by the following TLVs: @@ -44464,10 +39144,6 @@ typedef struct { * - wmi_regulatory_rule_meta_data reg_meta_data[] * struct used to fill meta information specific to new reg rules * getting added(i.e. from C2C onwards). - * - wmi_hw_blacklist_chan_fixed_param hw_blacklist_chan_fixed_param[0 or 1] - * optional TLV for reporting HW channel blacklist meta-data. - * - wmi_hw_blacklist_chan_data, hw_blacklist_chan_data[] - * optional TLV for reporting HW channel blacklist information. */ } wmi_reg_chan_list_cc_event_ext_fixed_param; @@ -44620,10 +39296,6 @@ typedef struct { * This TLV array contains zero or more TLVs of channel CFI and * EIRP power values for each of the total number of channels * per global operating class. - * 6. wmi_hw_blacklist_chan_fixed_param hw_blacklist_chan_fixed_param[] - * optional meta-data for HW channel blacklist - * 7. wmi_hw_blacklist_chan_data hw_blacklist_chan_data[] - * optional HW channel blacklist information */ } wmi_afc_event_fixed_param; @@ -44716,233 +39388,6 @@ typedef struct { A_UINT32 eirp_pwr; /* maximum permissible EIRP available for above CFI in dBm, value is stored in 0.01 dBm steps */ } wmi_afc_chan_eirp_power_info; - -typedef enum { - WMI_11BE_PUNCTURE_PATTERN_80MHZ_MINUS_20MHZ_0x1 = 0, - WMI_11BE_PUNCTURE_PATTERN_80MHZ_MINUS_20MHZ_0x2 = 1, - WMI_11BE_PUNCTURE_PATTERN_80MHZ_MINUS_20MHZ_0x4 = 2, - WMI_11BE_PUNCTURE_PATTERN_80MHZ_MINUS_20MHZ_0x8 = 3, - WMI_11BE_PUNCTURE_PATTERN_80MHZ_MAX, -} WMI_11BE_PUNCTURE_PATTERNS_80MHZ; - -typedef enum { - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_20MHZ_0x1 = 0, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_20MHZ_0x2 = 1, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_20MHZ_0x4 = 2, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_20MHZ_0x8 = 3, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_20MHZ_0x10 = 4, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_20MHZ_0x20 = 5, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_20MHZ_0x40 = 6, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_20MHZ_0x80 = 7, - - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_40MHZ_0x0C = 8, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_40MHZ_0x03 = 9, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_40MHZ_0xC0 = 10, - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MINUS_40MHZ_0x30 = 11, - - WMI_11BE_PUNCTURE_PATTERN_160MHZ_MAX, -} WMI_11BE_PUNCTURE_PATTERNS_160MHZ; - -typedef enum { - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_40MHZ_0xC = 0, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_40MHZ_0x3 = 1, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_40MHZ_0xC0 = 2, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_40MHZ_0x30 = 3, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_40MHZ_0xC00 = 4, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_40MHZ_0x300 = 5, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_40MHZ_0xC000 = 6, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_40MHZ_0x3000 = 7, - - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_80MHZ_0xF = 8, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_80MHZ_0xF0 = 9, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_80MHZ_0xF00 = 10, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_80MHZ_0xF000 = 11, - - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0xF003 = 12, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0xF00C = 13, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0xF030 = 14, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0xF0C0 = 15, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0xF300 = 16, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0xFC00 = 17, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0x003F = 18, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0x00CF = 19, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0x030F = 20, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0x0C0F = 21, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0x300F = 22, - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MINUS_120MHZ_0xC00F = 23, - - WMI_11BE_PUNCTURE_PATTERN_320MHZ_MAX, -} WMI_11BE_PUNCTURE_PATTERNS_320MHZ; - -typedef enum { - /* - * bits 16-19 of "blacklist_msg_info" in wmi_hw_blacklist_chan_fixed_param. - * This status code intimates host whether the TLV sent by - * Halphy is to update the master channel list or clear it. - */ - WMI_HW_BLACKLIST_CHAN_SP_UPDATE = 0, - WMI_HW_BLACKLIST_CHAN_VLP_UPDATE, - /* the below enums are added for future scope */ - WMI_HW_BLACKLIST_CHAN_SP_CLEAR, - WMI_HW_BLACKLIST_CHAN_VLP_CLEAR, - WMI_HW_BLACKLIST_CHAN_UPDATE_ALL, - WMI_HW_BLACKLIST_CHAN_CLEAR_ALL, - WMI_HW_BLACKLIST_CHAN_INVALID = 15, -} WMI_HW_BLACKLIST_CHAN_RESP_CMD_CODE; - -typedef enum { - /* - * bit 20, "blacklist_msg_info" flag in wmi_hw_blacklist_chan_fixed_param - * This bit field informs the host whether all the blacklist channel - * information has been sent, or if further messages will follow to - * deliver the remaining information. - */ - WMI_HW_BLACKLIST_CHAN_EVENT_DONE = 0, /* Indicates it is the last event */ - WMI_HW_BLACKLIST_CHAN_EVENT_MORE = 1, /* Indicates more evts will follow */ -} WMI_HW_BLACKLIST_CHAN_DATA_EVENT_FLAG; - -#define WMI_GET_BLACKLIST_MSG_INFO_WMI_EVT_SEQ_NUM(flag) \ - WMI_GET_BITS(flag, 0, 8) -#define WMI_SET_BLACKLIST_MSG_INFO_WMI_EVT_SEQ_NUM(flag, val) \ - WMI_SET_BITS(flag, 0, 8, val) - -#define WMI_GET_BLACKLIST_MSG_INFO_TOTAL_WMI_EVT_NUM(flag) \ - WMI_GET_BITS(flag, 8, 8) -#define WMI_SET_BLACKLIST_MSG_INFO_TOTAL_WMI_EVT_NUM(flag, val) \ - WMI_SET_BITS(flag, 8, 8, val) - -#define WMI_GET_BLACKLIST_MSG_INFO_RESP_CODE(flag) \ - WMI_GET_BITS(flag, 16, 4) -#define WMI_SET_BLACKLIST_MSG_INFO_RESP_CODE(flag, val) \ - WMI_SET_BITS(flag, 16, 4, val) - -#define WMI_GET_BLACKLIST_MSG_INFO_EVT_FLAG(flag) \ - WMI_GET_BITS(flag, 20, 1) -#define WMI_SET_BLACKLIST_MSG_INFO_EVT_FLAG(flag, val) \ - WMI_SET_BITS(flag, 20, 1, val) - -#define WMI_GET_BLACKLIST_CHANNELS_TOTAL_NUM_CHAN(flag) \ - WMI_GET_BITS(flag, 0, 16) -#define WMI_SET_BLACKLIST_CHANNELS_TOTAL_NUM_CHAN(flag, val) \ - WMI_SET_BITS(flag, 0, 16, val) - -#define WMI_GET_BLACKLIST_CHANNELS_CURRENT_NUM_CHAN(flag) \ - WMI_GET_BITS(flag, 16, 16) -#define WMI_SET_BLACKLIST_CHANNELS_CURRENT_NUM_CHAN(flag, val) \ - WMI_SET_BITS(flag, 16, 16, val) - -typedef struct { - /** TLV tag and len; - * tag equals WMITLV_TAG_STRUC_wmi_hw_blacklist_chan_fixed_param*/ - A_UINT32 tlv_header; - A_UINT32 phy_id; - union { - A_UINT32 blacklist_msg_info; - /* - * bit 7 - 0 -> Current WMI event sequence number - * bit 15 - 8 -> Total number of WMI events [For debugging only] - * bit 19 - 16 -> ENUM "WMI_HW_BLACKLIST_CHAN_RESP_CMD_CODE" - * bit 20 -> ENUM "WMI_HW_BLACKLIST_CHAN_DATA_EVENT_FLAG" - * bit 31 - 21 -> Reserved - */ - struct { - A_UINT32 - blacklist_wmi_seq_num: 8, - blacklist_wmi_total_num: 8, - blacklist_resp_code: 4, - blacklist_event_flag:1, - reserved: 11; - }; - }; - /* - * bit 15 - 0 -> Total number of HW blacklist channels - * bit 31 - 16 -> number of HW blacklist channels in current WMI - */ - union { - A_UINT32 num_hw_blacklist_channels; - struct { - A_UINT32 - total_num_chan: 16, - current_num_chan: 16; - }; - }; -} wmi_hw_blacklist_chan_fixed_param; - -#define WMI_GET_FREQ_INFO_PRI20_BITMAP(flag) \ - WMI_GET_BITS(flag, 0, 16) -#define WMI_SET_FREQ_INFO_PRI20_BITMAP(flag, val) \ - WMI_SET_BITS(flag, 0, 16, val) - -#define WMI_GET_FREQ_INFO_CHAN_CENTER_FREQ(flag) \ - WMI_GET_BITS(flag, 16, 16) -#define WMI_SET_FREQ_INFO_CHAN_CENTER_FREQ(flag, val) \ - WMI_SET_BITS(flag, 16, 16, val) - -#define WMI_GET_CHAN_LIST_META_DATA_POWER_MODE(flag) \ - WMI_GET_BITS(flag, 0, 4) -#define WMI_SET_CHAN_LIST_META_DATA_POWER_MODE(flag, val) \ - WMI_SET_BITS(flag, 0, 4, val) - -#define WMI_GET_CHAN_LIST_META_DATA_MAX_BW(flag) \ - WMI_GET_BITS(flag, 4, 8) -#define WMI_SET_CHAN_LIST_META_DATA_MAX_BW(flag, val) \ - WMI_SET_BITS(flag, 4, 8, val) - -#define WMI_GET_PUNCTURE_PATTERN_BITMAP(flag) \ - WMI_GET_BITS(flag, 0, 24) -#define WMI_SET_PUNCTURE_PATTERN_BITMAP(flag, val) \ - WMI_SET_BITS(flag, 0, 24, val) - -typedef struct { - /** TLV tag and len; - * tag equals WMITLV_TAG_STRUC_wmi_hw_blacklist_chan_data */ - A_UINT32 tlv_header; - /* - * bit 15 - 0 -> bitmap representing a set of 20MHz primary channels - * bit 31 - 16 -> channel center frequency in MHz for the given Max BW - * in "chan_list_meta_data" - */ - union { - A_UINT32 freq_info; - struct { - A_UINT32 - pri20_bitmap: 16, - chan_center_freq: 16; - }; - }; - /* - * bit 3 - 0 -> Power mode "WMI_6GHZ_REG_PWRMODE_TYPE" - * bit 11 - 4 -> Max BW with enum "wmi_channel_width" - * bit 31 - 12 -> reserved - */ - union { - A_UINT32 chan_list_meta_data; - struct { - A_UINT32 - power_mode: 4, - max_bw: 8, - reserved1: 20; - }; - }; - /* - * bit represents blacklisted puncture pattern based on enums - * WMI_11BE_PUNCTURE_PATTERNS_320MHZ, WMI_11BE_PUNCTURE_PATTERNS_160MHZ, - * WMI_11BE_PUNCTURE_PATTERNS_80MHZ - * bit 23 - 0 -> bitmap representing a set of puncture patterns of the - * given bandwidth. The bandwidth is represented by - * bits 8-15 of A_UINT32 chan_list_meta_data - * bit 31 - 24 -> reserved for future puncture patterns - */ - union { - A_UINT32 puncture_pattern_bitmap_info; - struct { - A_UINT32 - puncture_pattern_bitmap: 24, - reserved2: 8; - }; - }; -} wmi_hw_blacklist_chan_data; - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_11d_scan_start_cmd_fixed_param */ A_UINT32 vdev_id; @@ -45201,8 +39646,6 @@ typedef struct { * optional TLV for dbw_chan * wmi_dbw_chan_info dbw_chan_info * optional TLV used for dbw_chan_info - * wmi_uhr_ap_npca_params npca_params - * optional TLV used to update NPCA information */ } wmi_pdev_multiple_vdev_restart_request_cmd_fixed_param; @@ -45522,10 +39965,7 @@ typedef struct { #define WLM_FLAGS_ROAM_SUPPRESS 1 #define WLM_FLAGS_ALLOW_FINAL_BMISS_ROAM 2 -/* bit 8: Final bmiss roam will be triggered when all active links - * are final bmiss reported. - */ -#define WLM_FLAGS_ROAM_WHEN_ALL_LINKS_FBMISS 1 +/* bit 8: reserved for roaming */ /* bit 9-11 of flags is used for powersave operation */ /* bit 9: WLM_FLAGS_PS_DISABLE_BMPS, disable BMPS if bit is set */ @@ -45569,8 +40009,6 @@ typedef struct { #define WLM_FLAGS_TSF_LATENCY_COMPENSATE_ENABLED_SET(flag) WMI_SET_BITS(flag, 4, 1, val) #define WLM_FLAGS_ROAM_GET_POLICY(flag) WMI_GET_BITS(flag, 6, 2) #define WLM_FLAGS_ROAM_SET_POLICY(flag, val) WMI_SET_BITS(flag, 6, 2, val) -#define WLM_FLAGS_ROAM_GET_WHEN_ALL_LINKS_FBMISS(flag) WMI_GET_BITS(flag, 8, 1) -#define WLM_FLAGS_ROAM_SET_WHEN_ALL_LINKS_FBMISS(flag, val) WMI_SET_BITS(flag, 8, 1, val) #define WLM_FLAGS_PS_IS_BMPS_DISABLED(flag) WMI_GET_BITS(flag, 9, 1) #define WLM_FLAGS_PS_IS_CSS_CLPS_DISABLED(flag) WMI_GET_BITS(flag, 10, 1) #define WLM_FLAGS_PS_SET_CSS_CLPS_DISABLE(flag, val) WMI_SET_BITS(flag, 10, 1, val) @@ -45649,22 +40087,6 @@ typedef struct { A_UINT32 client_id_bitmask; } wmi_wlm_config_cmd_fixed_param; -typedef struct { - A_UINT32 tlv_header; - A_UINT32 vdev_id; - wmi_mac_addr peer_macaddr; - A_UINT32 responder_pm_mode; - A_UINT32 negotiation_type; - A_UINT32 twt_request; - A_UINT32 twt_setup_cmd; - A_UINT32 is_triggered; - A_UINT32 flow_type; - A_UINT32 wake_interval_exp; - A_UINT32 twt_protection; - A_UINT32 nominal_min_wake_duration; - A_UINT32 wake_interval_mantisa; -} wmi_ch_usage_add_dialog_cmd_fixed_param; - /* Broadcast TWT enable/disable for both REQUESTER and RESPONDER */ #define TWT_EN_DIS_FLAGS_GET_BTWT(flag) WMI_GET_BITS(flag, 0, 1) #define TWT_EN_DIS_FLAGS_SET_BTWT(flag, val) WMI_SET_BITS(flag, 0, 1, val) @@ -45756,32 +40178,11 @@ typedef struct { #define TWT_EN_DIS_FLAGS_SET_DIS_BTWT_AUTO_DELETE(flag, val) \ WMI_SET_BITS(flag, 7, 1, val) -/* - * Bit 8: indicates whether pdev_id is valid or vdev_id is valid. - * 0: pdev_id is valid (MAC-level TWT enable/disable) - * 1: vdev_id is valid (STA vdev-level TWT enable/disable) - */ -#define TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flag) WMI_GET_BITS(flag, 8, 1) -#define TWT_EN_DIS_FLAGS_SET_VDEV_SUPPORT(flag, val) WMI_SET_BITS(flag, 8, 1, val) - -/* bits 9-31: unused / reserved */ - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_enable_cmd_fixed_param */ - /** - * pdev_id or vdev_id depending on bit 8 of flags. - * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 0: - * pdev_id identifies the MAC. - * See macros starting with WMI_PDEV_ID_ for values. - * In non-DBDC case host should set it to 0. - * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 1: - * vdev_id is for STA vdev-level TWT enable. - * TWT enable applies only to that specific STA vdev. + /** pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. In non-DBDC case host should set it to 0 */ - union { - A_UINT32 pdev_id; - A_UINT32 vdev_id; - }; + A_UINT32 pdev_id; A_UINT32 sta_cong_timer_ms; /* STA TWT congestion timer TO value in terms of ms */ A_UINT32 mbss_support; /* Reserved */ A_UINT32 default_slot_size; /* This is the default value for the TWT slot setup by AP (units = microseconds) */ @@ -45824,70 +40225,23 @@ typedef enum _WMI_ENABLE_TWT_STATUS_T { typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_enable_complete_event_fixed_param */ - /** - * pdev_id or vdev_id depending on bit 8 of flags. - * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 0: - * pdev_id identifies the MAC. - * See macros starting with WMI_PDEV_ID_ for values. - * In non-DBDC case host should set it to 0. - * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 1: - * vdev_id is for STA vdev-level TWT enable. - * TWT enable applies only to that specific STA vdev. - */ - union { - A_UINT32 pdev_id; - A_UINT32 vdev_id; - }; + /** pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. In non-DBDC case host should set it to 0 */ + A_UINT32 pdev_id; A_UINT32 status; /* WMI_ENABLE_TWT_STATUS_T */ - /* flags: - * mirrors TWT_EN_DIS_FLAGS_* from the enable command; - * bit 8 indicates pdev vs vdev - */ - A_UINT32 flags; } wmi_twt_enable_complete_event_fixed_param; typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_disable_cmd_fixed_param */ - /** - * pdev_id or vdev_id depending on bit 8 of flags. - * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 0: - * pdev_id identifies the MAC. - * See macros starting with WMI_PDEV_ID_ for values. - * In non-DBDC case host should set it to 0. - * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 1: - * vdev_id is for STA vdev-level TWT disable. - * TWT disable applies only to that specific STA vdev. - */ - union { - A_UINT32 pdev_id; /* host should never set it to WMI_PDEV_ID_SOC */ - A_UINT32 vdev_id; - }; + /** pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. In non-DBDC case host should set it to 0 */ + A_UINT32 pdev_id; /* host should never set it to WMI_PDEV_ID_SOC */ A_UINT32 flags; /* enable/disable flags, refer to MACROs TWT_EN_DIS_FLAGS_* (TWT_EN_DIS_FLAGS_GET_BTWT etc.) */ A_UINT32 reason_code; /* refer to WMI_DISABLE_TWT_REASON_T */ } wmi_twt_disable_cmd_fixed_param; typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_disable_complete_event_fixed_param */ - /** - * pdev_id or vdev_id depending on bit 8 of flags. - * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 0: - * pdev_id identifies the MAC. - * See macros starting with WMI_PDEV_ID_ for values. - * In non-DBDC case host should set it to 0. - * When TWT_EN_DIS_FLAGS_GET_VDEV_SUPPORT(flags) == 1: - * vdev_id is for STA vdev-level TWT disable. - * TWT disable applies only to that specific STA vdev. - */ - union { - A_UINT32 pdev_id; /* host should never set it to WMI_PDEV_ID_SOC */ - A_UINT32 vdev_id; - }; + A_UINT32 pdev_id; A_UINT32 status; /* refer to WMI_DISABLE_TWT_STATUS_T enum */ - /* flags: - * mirrors TWT_EN_DIS_FLAGS_* from the enable command; - * bit 8 indicates pdev vs vdev - */ - A_UINT32 flags; } wmi_twt_disable_complete_event_fixed_param; typedef struct { @@ -46164,9 +40518,6 @@ typedef enum _WMI_DEL_TWT_STATUS_T { WMI_DEL_TWT_STATUS_CHANGE_CONGESTION_TIMEOUT, /* Congestion timeout changed */ WMI_DEL_TWT_STATUS_P2P_GO_NOA, /* P2P GO NOA */ WMI_DEL_TWT_STATUS_UNSUPPORTED_MLMR_MODE, /* Teardown due to MLMR */ - WMI_DEL_TWT_STATUS_MLO_LINK_INACTIVE, /* Teardown due to link going to inactive */ - WMI_DEL_TWT_STATUS_2G_TWT_NOT_ENABLED, /* Teardown due to 2.4 GHz TWT not enabled */ - WMI_DEL_TWT_STATUS_SCAN_STARTED, /* Teardown due to scan started */ } WMI_DEL_TWT_STATUS_T; typedef struct { @@ -46567,7 +40918,7 @@ typedef enum { typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_spectral_bin_scaling_params */ A_UINT32 pdev_id; /* ID of pdev to which the scaling parameters are to be applied */ - A_UINT32 formula_id; /* WMI_SPECTRAL_SCALING_FORMULA_ID: Represents the formula to be used */ + WMI_SPECTRAL_SCALING_FORMULA_ID formula_id; /* Represets the formula to be used */ A_UINT32 low_level_offset; /* low level offset for fine tuning the scaling factor based on RSSI and AGC gain */ A_UINT32 high_level_offset; /* high level offset for fine tuning the scaling factor based on RSSI and AGC gain */ A_UINT32 rssi_thr; /* RSSI threshold to be used to adjust the inband power of the given spectral report */ @@ -46874,11 +41225,6 @@ typedef struct { A_UINT32 vdev_id; /* 1-Enable, 0-Disable */ A_UINT32 enable; - /* self_roaming_re_enable_time: - * Allow next deauth self-roaming only when time gap is more than - * self_roaming_re_enable_time w.r.t previous deauth self-roaming. - */ - A_UINT32 self_roaming_re_enable_time; /* units = seconds */ } wmi_roam_deauth_config_cmd_fixed_param; /** IDLE roam trigger parameters */ @@ -47056,24 +41402,6 @@ typedef struct { wmi_mac_addr transmit_addr; /* AKM suite type (as defined in the IEEE 802.11 spec) */ A_UINT32 akm_suite_type; - /** - * IEEE value for auth algorithm - * Authentication algorithm number = 3: - * Simultaneous Authentication of Equals (SAE) - * Authentication algorithm number = 8: - * IEEE 802.1X authentication - * Authentication algorithm number = 9: - * EPPKE authentication - */ - A_UINT32 auth_algo; - - /* IEEE value for below ciphers */ - /** unicast cipher set */ - A_UINT32 pairwise_cipher; - /** mcast/group cipher set */ - A_UINT32 group_cipher; - /** mcast/group management frames cipher set */ - A_UINT32 group_mgmt_cipher; } wmi_roam_preauth_start_event_fixed_param; typedef struct { @@ -47185,7 +41513,6 @@ typedef enum wmi_roam_invoke_status_error { WMI_ROAM_INVOKE_STATUS_INVALID_SCAN_MODE, /* Roam scan mode is invalid */ WMI_ROAM_INVOKE_STATUS_NO_CAND_AP, /* No candidate AP found to roam to */ WMI_ROAM_INVOKE_STATUS_HO_FAIL, /* handoff failed */ - WMI_ROAM_INVOKE_STATUS_SUSTAIN_CONN, /* Sustain existing connection when MLD self roaming fails */ } wmi_roam_invoke_status_error_t; typedef struct { @@ -47426,8 +41753,6 @@ typedef enum { WMI_ROAM_FAIL_REASON_CURR_AP_STILL_OK, /* Roam scan not happen due to current network condition is fine */ WMI_ROAM_FAIL_REASON_SCAN_CANCEL, /* Roam scan canceled */ WMI_ROAM_FAIL_REASON_MLD_EXTRA_SCAN_REQUIRED, /* Roaming is not triggered for current roam scan as extra scan is required to scan all MLD links */ - WMI_ROAM_FAIL_REASON_TTLM_REQUIRED, /* Roaming is not triggered as TTLM is required */ - WMI_ROAM_FAIL_REASON_LINKRECONFIG_REQUIRED, /* Roaming is not triggered as linkreconfig is required */ WMI_ROAM_FAIL_REASON_UNKNOWN = 255, } WMI_ROAM_FAIL_REASON_ID; @@ -47612,7 +41937,7 @@ typedef struct { * rssi_dbm_abs * Last known RSSI of the current BSSID at the moment when the frame * was sent and received. - * Host should ignore this field if its value is 0. + * This RSSI value is valid for deauth / disassoc frame only. * The rssi_dbm_abs value is the absolute value of the RSSI in dBm units. * For example, if the RSSI is -40 dBm, rssi_dbm_abs will be 40. */ @@ -47651,10 +41976,6 @@ typedef enum { WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_M4, WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_GTK_M1, WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_GTK_M2, - WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_ST_PREP_REQ, - WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_ST_PREP_RESP, - WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_ST_EXEC_REQ, - WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE_ST_EXEC_RESP, } WMI_ROAM_FRAME_INFO_FRAME_TYPE_EXT_SUBTYPE; typedef enum { @@ -48179,18 +42500,6 @@ typedef enum { */ WMI_ROAM_PARAM_ROAM_LATENCY_OPTIMIZATION_BITMAP = 11, - /* - * Roam param to add RSSI penalty for non-6GHz Candidate AP - * during Roam Scan in case current connected AP is 6GHz and - * cand AP is non-6GHz. - * This RSSI penalty value (in dB units) for non-6GHz candidate AP - * will be configured via ini roam_rssi_delta_from_6ghz_to_non_6ghz. - * This configured RSSI penalty value will only be applicable for non-6GHz - * Candidate AP when the STA is connected to 6GHz Band AP and will - * not impact if STA is connected to non-6GHz Band AP - */ - WMI_ROAM_PARAM_ROAM_RSSI_PENALTY_FOR_NON_6GHZ_CAND_AP = 12, - /*=== END ROAM_PARAM_PROTOTYPE SECTION ===*/ } WMI_ROAM_PARAM; @@ -48230,114 +42539,6 @@ typedef enum { WLAN_CRYPTO_WPA3_SAE_ALLOW_MLO_HNP = 0x00020000, } wlan_crypto_roam_eht_config; -typedef enum { - /* - * Low-latency mode is suitable for applications with strict - * latency requirements and is also the default mode in the firmware. - * e.g VOIP, Online gaming. - */ - WMI_ROAM_LOWLATENCY_MODE = 0x0, - /* - * Packet-loss mode is suitable for applications that do not have - * strict latency requirements but have low tolerance for packet loss. - * e.g file transfer. - */ - WMI_ROAM_PACKETLOSSLESS_MODE = 0x1, - /* This mode is only used for WFA test purpose. */ - WMI_ROAM_MANUAL_MODE = 0x2, -} WMI_ROAM_SMD_MODE_PARAMS; - -/* - * useful macros defined for flags field in wmi_roam_smd_config_cmd_fixed_param - */ -#define WMI_SMD_CONFIG_FLAGS_GET_DISABLE_SMD_ASSOC(flags) \ - WMI_GET_BITS(flags, 0, 1) -#define WMI_SMD_CONFIG_FLAGS_SET_DISABLE_SMD_ASSOC(flags, val) \ - WMI_SET_BITS(flags, 0, 1, val) - -#define WMI_SMD_CONFIG_FLAGS_GET_DISABLE_SMD_TRANSITION(flags) \ - WMI_GET_BITS(flags, 1, 1) -#define WMI_SMD_CONFIG_FLAGS_SET_DISABLE_SMD_TRANSITION(flags, val) \ - WMI_SET_BITS(flags, 1, 1, val) - -/* - * useful macros defined for manual_conf field in - * wmi_roam_smd_config_cmd_fixed_param - */ -#define WMI_SMD_CONFIG_MANUAL_CONF_GET_EXECUTION_VIA_NEW_AP(conf) \ - WMI_GET_BITS(conf, 0, 1) -#define WMI_SMD_CONFIG_MANUAL_CONF_SET_EXECUTION_VIA_NEW_AP(conf, val) \ - WMI_SET_BITS(conf, 0, 1, val) - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_smd_config_cmd_fixed_param */ - A_UINT32 vdev_id; - - /* - * The mode used to control SMD transition involves a trade-off - * between low latency and packet loss. - * Depending on the upper-layer application, the choice may also vary. - * refer WMI_ROAM_SMD_MODE_PARAMS definition - */ - A_UINT32 prefer_mode; - /* flags: - * refer WMI_SMD_CONFIG_FLAGS_GET and _SET macros - * BIT 0 - Disable SMD association. - * BIT 1 - Disable SMD BSS transition, invalid when BIT 0 is set. - */ - A_UINT32 flags; - /* manual_conf: - * Valid only when prefer_mode is WMI_ROAM_MANUAL_MODE - * BIT 0 - SMD transition execution via new AP if set. - */ - A_UINT32 manual_conf; -} wmi_roam_smd_config_cmd_fixed_param; - -typedef enum { - WMI_SMD_START_STATUS_SUCCESS = 0, - - /* Failure that is not specifically defined */ - WMI_SMD_START_STATUS_UNSPECIFIC_FAILURE, - - /* Abort due to disconnection from upper layer */ - WMI_SMD_START_STATUS_ABORT_DISCONNECTION, - - /* Vdev repurpose failure */ - WMI_SMD_START_STATUS_VDEV_REPURPOSE_FAILURE, - - /* Preparation request frame no ACK */ - WMI_SMD_START_STATUS_PREP_REQ_TX_NO_ACK, - - /* No Preparation response frame received */ - WMI_SMD_START_STATUS_PREP_RESP_RX_TIMEOUT, -} WMI_SMD_START_STATUS_CODE; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_prep_resp_status_list */ - A_UINT32 ieee_link_id; - A_UINT32 status_code; /* same value defined in 'status code' in standard */ -} wmi_prep_resp_status_list; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_smd_start_status_cmd_fixed_param */ - - A_UINT32 vdev_id; - A_UINT32 status; /* Refer WMI_SMD_START_STATUS_CODE */ - /* kck_len: - * Valid when per AP-MLD ptk mode is used, KCK is used to - * calculate MIC in ST execution request frame. - */ - A_UINT32 kck_len; - - /* - * This fixed_param TLV is followed by the below TLVs: - * - * A_UINT8 smd_transition_ie[]; - * wmi_prep_resp_status_list status_list[]; - * A_UINT8 kck[]; - */ -} wmi_roam_smd_start_status_cmd_fixed_param; - typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_big_data_cmd_fixed_param */ A_UINT32 vdev_id; @@ -48467,9 +42668,8 @@ typedef enum { WMI_6GHZ_REG_PWRMODE_VLP = 2, /* VLP mode for AP and client products */ WMI_6GHZ_REG_PWRMODE_SP_STA = 3, /* SP client mode for AP products */ WMI_6GHZ_REG_PWRMODE_C2C = 4, /*C2C client mode for AP and client products*/ - WMI_6GHZ_REG_PWRMODE_GVP = 5, /* GVP mode for AP and client products */ - WMI_6GHZ_REG_PWRMODE_MAX = 6 + WMI_6GHZ_REG_PWRMODE_MAX = 5 } WMI_6GHZ_REG_PWRMODE_TYPE; typedef struct { @@ -50557,81 +44757,13 @@ typedef struct { /****** End of 11BE EHT MAC Capabilities Information field ******/ -/****** 11BE EHT OPS Information field - DEPRECATED ******/ -/* DEPRECATED, replaced by - * "Bit 6 is for MCS15. If bit6 is 1 then we disable mcs15" - * OLD: Bit 0 is for MCS15. If bit0 is 1 then we enable mcs15 - */ +/****** 11BE EHT OPS Information field ******/ + +/* Bit 0 is for MCS15. If bit0 is 1 then we enable mcs15 */ #define WMI_EHT_OPS_SUPMCS15_GET(eht_ops) WMI_GET_BITS(eht_ops, 0, 1) #define WMI_EHT_OPS_SUPMCS15_SET(eht_ops, value) WMI_SET_BITS(eht_ops, 0, 1, value) -/****** End of 11BE EHT OPS Information field - DEPRECATED ******/ -/****** 11BE EHT Operation Parameters field ******/ -/* Bit 0 EHT Operation Information Present */ -#define WMI_EHT_OPS_INFORMATION_PRESENT_GET(eht_ops) WMI_GET_BITS(eht_ops, 0, 1) -#define WMI_EHT_OPS_INFORMATION_PRESENT_SET(eht_ops, value) WMI_SET_BITS(eht_ops, 0, 1, value) -/* Bit 1 Disabled Subchannel Bitmap Present */ -#define WMI_EHT_OPS_DISABLED_SUBCHANNEL_BITMAP_GET(eht_ops) WMI_GET_BITS(eht_ops, 1, 1) -#define WMI_EHT_OPS_DISABLED_SUBCHANNEL_BITMAP_SET(eht_ops, value) WMI_SET_BITS(eht_ops, 1, 1, value) - -/* Bit 2 EHT default PE duration */ -#define WMI_EHT_OPS_PE_DURATION_GET(eht_ops) WMI_GET_BITS(eht_ops, 2, 1) -#define WMI_EHT_OPS_PE_DURATION_SET(eht_ops, value) WMI_SET_BITS(eht_ops, 2, 1, value) - -/* Bit 3 Group Addressed BU indication limit*/ -#define WMI_EHT_OPS_GROUP_ADDRESSED_BU_INDICATION_LIMIT_GET(eht_ops) WMI_GET_BITS(eht_ops, 3, 1) -#define WMI_EHT_OPS_GROUP_ADDRESSED_BU_INDICATION_LIMIT_SET(eht_ops, value) WMI_SET_BITS(eht_ops, 3, 1, value) - -/* Bit 4~5 Group Addressed BU indication Exponent */ -#define WMI_EHT_OPS_GROUP_ADDRESSED_BU_INDICATION_EXPONENT_GET(eht_ops) WMI_GET_BITS(eht_ops, 4, 2) -#define WMI_EHT_OPS_GROUP_ADDRESSED_BU_INDICATION_EXPONENT_SET(eht_ops, value) WMI_SET_BITS(eht_ops, 4, 2, value) - -/* Bit 6 is for MCS15. If bit6 is 1 then we disable mcs15 */ -#define WMI_EHT_OPS_MCS15_DISABLE_GET(eht_ops) WMI_GET_BITS(eht_ops, 6, 1) -#define WMI_EHT_OPS_MCS15_DISABLE_SET(eht_ops, value) WMI_SET_BITS(eht_ops, 6, 1, value) - -/* Bit 7: reserved */ -/****** End of 11BE EHT Operation Parameters field ******/ - -/****** 11BN UHR Operation Parameters field ******/ -/* Bit 0 UHR Operation Information Present */ -#define WMI_UHR_OPS_INFORMATION_PRESENT_GET(uhr_ops) \ - WMI_GET_BITS(uhr_ops, 0, 1) -#define WMI_UHR_OPS_INFORMATION_PRESENT_SET(uhr_ops, value) \ - WMI_SET_BITS(uhr_ops, 0, 1, value) - -/* Bit 1 DPS Enabled */ -#define WMI_UHR_OPS_DPS_ENABLED_GET(uhr_ops) \ - WMI_GET_BITS(uhr_ops, 1, 1) -#define WMI_UHR_OPS_DPS_ENABLED_SET(uhr_ops, value) \ - WMI_SET_BITS(uhr_ops, 1, 1, value) - -/* Bit 2 NPCA Enabled */ -#define WMI_UHR_OPS_NPCA_ENABLED_GET(uhr_ops) \ - WMI_GET_BITS(uhr_ops, 2, 1) -#define WMI_UHR_OPS_NPCA_ENABLED_SET(uhr_ops, value) \ - WMI_SET_BITS(uhr_ops, 2, 1, value) - -/* Bit 3 DBE Enabled */ -#define WMI_UHR_OPS_DBE_ENABLED_GET(uhr_ops) \ - WMI_GET_BITS(uhr_ops, 3, 1) -#define WMI_UHR_OPS_DBE_ENABLED_SET(uhr_ops, value) \ - WMI_SET_BITS(uhr_ops, 3, 1, value) - -/* Bit 4 P-EDCA Enabled */ -#define WMI_UHR_OPS_PEDCA_ENABLED_GET(uhr_ops) \ - WMI_GET_BITS(uhr_ops, 4, 1) -#define WMI_UHR_OPS_PEDCA_ENABLED_SET(uhr_ops, value) \ - WMI_SET_BITS(uhr_ops, 4, 1, value) - -/* Bit 5~7 DBE Bandwidth */ -#define WMI_UHR_OPS_DBE_BANDWIDTH_GET(uhr_ops) \ - WMI_GET_BITS(uhr_ops, 5, 3) -#define WMI_UHR_OPS_DBE_BANDWIDTH_SET(uhr_ops, value) \ - WMI_SET_BITS(uhr_ops, 5, 3, value) - -/* Bit 8~15: reserved */ -/****** End of 11BN UHR Operation Parameters field ******/ +/****** End of 11BE EHT OPS Information field ******/ typedef struct { /** TLV tag and len; tag equals @@ -50667,12 +44799,7 @@ typedef struct { A_UINT32 correlation_info_2; /* Bits 1:0: TX status (if any); values defined in enum * WMI_FRAME_TX_STATUS - * Bits 28:2: reserved (set to 0x0) - * Bit 29: frame sequence control valid flag: - * The frame_seq_ctrl word / bitfields in - * wmi_peer_cfr_capture_event_fixed_param must be ignored - * unless this flag is set. - * Bit 30: PS failed flag + * Bits 30:2: reserved (set to 0x0) * Bit 31: Status of the CFR capture of the peer * 1 (True) - Successful; 0 (False) - Not successful */ @@ -50750,41 +44877,8 @@ typedef struct { * Bits 16:31 reserved */ A_UINT32 mcs_gi_info; - - /* - * 802.11 Sequence Control field from the transmitted frame. - * Added for enhanced CFR correlation. - * - * Bits 0:3 Fragment number - * Bits 4:15 Sequence number - * Bits 16:31 Reserved (set to 0) - * - * Value is 0 if not available. - * - * NOTE: This field is appended for backward compatibility. - * Older hosts will ignore this field as they parse based on - * their known structure size. - */ - A_UINT32 frame_seq_ctrl; } wmi_peer_cfr_capture_event_fixed_param; -#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_TX 0x00000003 -#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_TX_S 0 - -/* bits 28:2 are reserved */ - -/* frame_seq_ctrl field is valid */ -#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_FRAME_SEQ_VALID 0x20000000 -#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_FRAME_SEQ_VALID_S 29 - -/* Failed to capture CFR as peer is in power save mode */ -#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_PS_FAILED 0x40000000 -#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_PS_FAILED_S 30 - -#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_OK 0x80000000 -#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_OK_S 31 - - #define WMI_CFR_MCS_GET(mcs_gi_info) \ WMI_GET_BITS(mcs_gi_info, 0, 8) @@ -50797,213 +44891,6 @@ typedef struct { #define WMI_CFR_GI_TYPE_SET(mcs_gi_info, value) \ WMI_SET_BITS(mcs_gi_info, 8, 8, value) -/* Macros to get/set fragment number from frame_seq_ctrl field */ -#define WMI_CFR_FRAME_FRAG_NUM_GET(frame_seq_ctrl) \ - WMI_GET_BITS(frame_seq_ctrl, 0, 4) -#define WMI_CFR_FRAME_FRAG_NUM_SET(frame_seq_ctrl, value) \ - WMI_SET_BITS(frame_seq_ctrl, 0, 4, value) - -/* Macros to get/set sequence number from frame_seq_ctrl field */ -#define WMI_CFR_FRAME_SEQ_NUM_GET(frame_seq_ctrl) \ - WMI_GET_BITS(frame_seq_ctrl, 4, 12) -#define WMI_CFR_FRAME_SEQ_NUM_SET(frame_seq_ctrl, value) \ - WMI_SET_BITS(frame_seq_ctrl, 4, 12, value) - -/** - * CFR capture fix agc gain status codes - * These values are sent to host in wmi_cfr_capture_filter_resp_event - */ -typedef enum { - /** Configuration successful */ - WMI_CFR_CAPTURE_FIX_AGC_GAIN_STATUS_SUCCESS = 0, - - /** RX AGC Gain index out of range */ - WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_INDEX_OUT_OF_RANGE = 1, - - /** Fixed AGC not supported in current PHY mode */ - WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_PHYMODE_REJECT = 2, - - /** Failed to disable Scan */ - WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_SCAN_DISABLE_FAILED = 3, - - /** Failed to disable ANI */ - WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_ANI_DISABLE_FAILED = 4, - - /** AGC control is already owned by another module */ - WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_AGC_CONFLICT = 5, - - /** Another CFR/AGC session is in progress */ - WMI_CFR_CAPTURE_FIX_AGC_GAIN_REASON_SESSION_BUSY = 6, -} wmi_cfr_capture_fix_agc_gain_status_t; - -typedef struct { - /* Info of the CFR capture fix AGC gain configuration based on wmi_cfr_capture_fix_agc_gain_status_t */ - A_UINT32 tlv_header; - - /* wmi_cfr_capture_fix_agc_gain_status_t */ - A_UINT32 status; - - /* RX agc gain index for cfr capture in HW */ - A_UINT32 cfr_agc_gain_index; -} wmi_cfr_capture_fix_agc_gain_info; - -/** - * CFR capture filter command response status codes - * These values are sent to host in wmi_cfr_capture_filter_resp_event - */ -typedef enum { - /** Configuration successful */ - WMI_CFR_CAPTURE_FILTER_STATUS_SUCCESS = 0, - - /** Channel not specified for unassoc mode */ - WMI_CFR_CAPTURE_FILTER_STATUS_NO_CHANNEL = 1, - - /** Invalid MAC ID */ - WMI_CFR_CAPTURE_FILTER_STATUS_INVALID_MAC_ID = 2, - - /** OCS channel request failed */ - WMI_CFR_CAPTURE_FILTER_STATUS_OCS_FAILED = 3, - - /** vdev not found */ - WMI_CFR_CAPTURE_FILTER_STATUS_NO_VDEV = 4, - - /** Invalid param */ - WMI_CFR_CAPTURE_FILTER_STATUS_INVALID_PARAM = 5, -} wmi_cfr_capture_filter_status_t; - -typedef struct { - A_UINT32 tlv_header; - /* Status of the CFR capture filter configuration based on wmi_cfr_capture_filter_status_t */ - A_UINT32 status; /* wmi_cfr_capture_filter_status_t */ - A_UINT32 pdev_id; - /* - * Fields for peer CFR capture support - - * These fields are ONLY populated for peer capture responses. - * For filter capture responses, these remain 0. - */ - A_UINT32 vdev_id; /* VDEV ID (0 for filter capture) */ - wmi_mac_addr mac_addr; /* Peer MAC address (all zeros for filter capture) */ - A_UINT32 request; /* WMI_PEER_CFR_CAPTURE_ENABLE/DISABLE (0 for filter capture) */ -} wmi_cfr_capture_filter_resp_event_fixed_param; - - -/* max beacon bmiss bitmask array size, in 32-bit words */ -#define WMI_MAX_BCN_BMISS_HISTORY_LENGTH 8 - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_beacon_stats */ - A_UINT32 vdev_id; /* ID of the vdev these beacon stats are from */ - /* length: - * Number of A_UINT32 elements within the bmiss_bitmask array which - * contain valid data. - * Array elements beyond this limit should be ignored. - */ - A_UINT32 length; - /* bmiss_bitmask: - * Beacon miss bitmask indicating which beacons got missed from up to - * the last 255 expected beacons (32*8 bits). - * Only bmiss_bitmask[0] through bmiss_bitmask[length-1] (inclusive) - * contain valid data. - */ - A_UINT32 bmiss_bitmask[WMI_MAX_BCN_BMISS_HISTORY_LENGTH]; -} wmi_vdev_beacon_stats; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_qdata_congestion_stats */ - A_UINT32 vdev_id; /* ID of the vdev these congestion stats are from */ - /* cca_busy_time: - * Number of milliseconds during which CCA is busy, - * out of total time spent on the channel - */ - A_UINT32 cca_busy_time; - /* on_time: - * Total time in milliseconds for which we were on the channel - * and monitored - */ - A_UINT32 on_time; -} wmi_vdev_congestion_stats; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_data_stats */ - A_UINT32 vdev_id; /* ID of the vdev these data stats are from */ - /* Set of TX MCS counters for data PPDUs */ - A_UINT32 tx_mcs_data_ppdu[WMI_ENHANCE_STATS_MAX_MCS_COUNTERS]; - /* Set of TX BW counters for data PPDUs */ - A_UINT32 tx_bw_data_ppdu[WMI_STATS_EXT_EVENT_VDEV_EXT_BW_COUNTERS_MAX]; - /* Set of RX MCS counters for data PPDUs */ - A_UINT32 rx_mcs_data_ppdu[WMI_ENHANCE_STATS_MAX_MCS_COUNTERS]; - /* Set of RX BW counters for data PPDUs */ - A_UINT32 rx_bw_data_ppdu[WMI_STATS_EXT_EVENT_VDEV_EXT_BW_COUNTERS_MAX]; -} wmi_vdev_data_stats; - - -#define WMI_EM_PCIE_MAX_CHIP 4 -#define WMI_EM_PCIE_MAX_NUM_MAC 3 - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_em_pcie_stats */ - A_UINT32 is_cumac; /* set to '1' if SoC has CUMAC, else set to '0' */ - A_UINT32 enable; /* set to '1' if feature enable, else set to '0' */ - /* config_type: - * feature configuration type (holds a wmi_pcie_config_type_e value) - */ - A_UINT32 config_type; - /* mlo_partner_chip_bw: - * MLO partner chip BW information, represented as a FW-internal BW enum - * (Thus, this field is intended only for interactive debugging, and not - * for interpretation by the host SW.) - */ - A_UINT32 mlo_partner_bw[WMI_EM_PCIE_MAX_CHIP]; - /* mlo_partner_nss: MLO partner chip NSS information */ - A_UINT32 mlo_partner_nss[WMI_EM_PCIE_MAX_CHIP]; - /* pdev_bw: - * Per PDEV BW, represented as a FW-internal BW enum - * (Thus, this field is intended only for interactive debugging, and not - * for interpretation by the host SW.) - */ - A_UINT32 pdev_bw[WMI_EM_PCIE_MAX_NUM_MAC]; - A_UINT32 curr_pcie_gen; /* current PCIe generation number */ - A_UINT32 curr_pcie_lanes; /* current number of PCIe lanes */ - A_UINT32 pending_pcie_gen; /* pending PCIe generation number */ - A_UINT32 pending_pcie_lanes; /* pending number of PCIe lanes */ -} wmi_em_pcie_stats; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_em_dcvs_stats */ - A_UINT32 num_mac; /* Number of active MAC */ - /* DCVS feature config (holds a wmi_dcvs_config_e value) */ - A_UINT32 dcvs_cfg; - A_UINT32 is_cumac; /* set to '1' if SoC has CUMAC, else set to '0' */ - /* pdev_curr_bw: - * Per PDEV BW, represented as a FW-internal BW enum - * (Thus, this field is intended only for interactive debugging, and not - * for interpretation by the host SW.) - */ - A_UINT32 pdev_curr_bw[WMI_EM_PCIE_MAX_NUM_MAC]; - /* pdev_sla_status: - * SLA active status per pdev. - * set to '1' if SLA connection is active per pdev, else set to '0' - */ - A_UINT32 pdev_sla_status[WMI_EM_PCIE_MAX_NUM_MAC]; - A_UINT32 ofdma_ul_user_limit; /* OFDMA UL user limit for SVS entry */ - A_UINT32 ofdma_dl_user_limit; /* OFDMA DL user limit for SVS entry */ - /* set to '1' if OFDMA user limit is applied, else set to '0' */ - A_UINT32 is_ofdma_limit_applied; - A_UINT32 cv_corr_limit; /* CV corr limit for SVS entry */ - /* set to '1' if cv corr limit is applied, else set to '0' */ - A_UINT32 is_cv_corr_limit_applied; - /* set to '1' if mu sniffer limit is applied, else set to '0' */ - A_UINT32 is_mu_sniff_limit_applied[WMI_EM_PCIE_MAX_NUM_MAC]; - A_UINT32 pending_dcvs_vote; /* pending vote level (0-SVS, 1-NOM) */ - /* pending DCVS BW, represented as a FW-internal BW enum */ - A_UINT32 pending_dcvs_bw; - A_UINT32 pending_dcvs_level_switch; /* pending DCVS level change */ - A_UINT32 current_dcvs_vote; /* current vote level (0-SVS, 1-NOM) */ - /* current, DCVS BW, represented as a FW-internal BW enum */ - A_UINT32 current_dcvs_bw; - A_UINT32 current_dcvs_level_switch; /* current DCVS level change */ -} wmi_em_dcvs_stats; - #define WMI_UNIFIED_CHAIN_PHASE_MASK 0x0000ffff #define WMI_UNIFIED_CHAIN_PHASE_GET(tlv, chain_idx) \ @@ -51081,6 +44968,15 @@ typedef struct { A_UINT32 agc_gain_tbl_index[WMI_MAX_CHAINS/WMI_CFR_AGC_GAIN_CHAINS_PER_U32]; } wmi_peer_cfr_capture_event_phase_fixed_param; +#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_OK 0x80000000 +#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_OK_S 31 + +/* Failed to capture CFR as peer is in power save mode */ +#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_PS_FAILED 0x40000000 +#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_PS_FAILED_S 30 + +#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_TX 0x00000003 +#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_TX_S 0 /** * wmi_cold_boot_cal_data config flags @@ -51741,21 +45637,6 @@ typedef struct { A_UINT32 data_subtype_filter; } wmi_cfr_filter_group_config; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_cfr_fix_agc_gain_config */ - - /* - * 0 - disable CFR fix agc gain feature - * 1 - enable CFR fix agc gain feature - */ - A_UINT32 cfr_fix_agc_gain_enable; - - /* Forced RX agc gain index for cfr capture, which is set by user in host */ - A_UINT32 force_cfr_agc_gain_index; -} wmi_cfr_capture_fix_agc_gain_config; - - #define WMI_CFR_DIRECTED_FTM_ACK_EN_BIT_POS 0 #define WMI_CFR_ALL_FTM_ACK_EN_BIT_POS 1 #define WMI_CFR_NDPA_NDP_DIRECTED_EN_BIT_POS 2 @@ -51968,17 +45849,6 @@ typedef struct { */ A_UINT32 capture_count; - /* unassoc_capture_config: - * Bit 0: Enable unassociated capture mode - * Bits 31:1 Reserved - */ - A_UINT32 unassoc_capture_config; - - /* Target channel frequency in MHz */ - A_UINT32 unassoc_channel_mhz; - - /* Target channel phy_mode */ - A_UINT32 unassoc_phy_mode; /* WLAN_PHY_MODE */ /* * A variable-length TLV array of wmi_cfr_filter_group_config will * follow this fixed_param TLV @@ -51986,10 +45856,6 @@ typedef struct { */ } wmi_cfr_capture_filter_cmd_fixed_param; -/* CFR Capture macros to get/set the unassociated capture mode enable flag */ -#define WMI_CFR_UNASSOC_CAPTURE_EN_GET(x) WMI_GET_BITS(x, 0, 1) -#define WMI_CFR_UNASSOC_CAPTURE_EN_SET(x, value) WMI_SET_BITS(x, 0, 1, value) - enum wmi_oem_data_evt_cause { WMI_OEM_DATA_EVT_CAUSE_UNSPECIFIED = 0, WMI_OEM_DATA_EVT_CAUSE_CMD_REQ = 1, @@ -52572,17 +46438,6 @@ typedef struct { A_UINT32 force_he_trigger_to_eht_sta; } wmi_wfa_config_ofdma; -typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wfa_config_ml */ - A_UINT32 tlv_header; - /* force_add_ext_mld_cap_field - * Possible values from host are: - * 0 default behavior - * 1 add ext mld cap field always when connection - */ - A_UINT32 force_add_ext_mld_cap_field; -} wmi_wfa_config_ml; - typedef struct { /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wfa_config_cmd_fixed_param */ A_UINT32 tlv_header; @@ -52594,7 +46449,6 @@ typedef struct { * wmi_wfa_config_ocv wfa_config_ocv[]; (0 or 1 elements) * wmi_wfa_config_saquery wfa_config_saquery[]; (0 or 1 elements) * wmi_wfa_config_ofdma wfa_config_ofdma[]; (0 or 1 elements) - * wmi_wfa_config_ml wmi_wfa_config_ml[]; (0 or 1 elements) */ } wmi_wfa_config_cmd_fixed_param; @@ -52849,7 +46703,6 @@ typedef enum { WMI_MLO_LINK_FORCE_REASON_TDLS = 4, /* Set force specific links because of 11BE MLO TDLS setup/teardown */ WMI_MLO_LINK_FORCE_REASON_REVERT_FAILURE = 5, /* Set force specific links for revert previous failed due to host reject */ WMI_MLO_LINK_FORCE_REASON_LINK_DELETE = 6, /* Set force specific links because link is deleted from associated link set */ - WMI_MLO_LINK_FORCE_REASON_SINGLE_LINK_EMLSR_OP = 7, /* Set force specific links because single link eMLSR operation */ } WMI_MLO_LINK_FORCE_REASON; #define WMI_MLO_CONTROL_FLAGS_GET_OVERWRITE_FORCE_ACTIVE(mlo_flags) \ @@ -53180,30 +47033,11 @@ typedef struct { /* MLD address of AP */ wmi_mac_addr mld_addr; /* any non-zero values of status indicate link reconfig failure. */ - A_UINT32 status; - /* reassoc_if_failure: - * Valid only when status is non-zero. - * FW will do reassociation if link reconfig failure. - */ - A_UINT32 reassoc_if_failure; + A_UINT32 status; + /* valid only when status is non-zero. fw will do reassociation if link reconfig failure */ + A_UINT32 reassoc_if_failure; } wmi_mlo_link_reconfig_complete_fixed_param; -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_ttlm_complete_fixed_param */ - A_UINT32 tlv_header; - /* unique id identifying the VDEV, generated by the caller */ - A_UINT32 vdev_id; - /* MLD address of AP */ - wmi_mac_addr mld_addr; - /* any non-zero values of status indicate link TTLM failure. */ - A_UINT32 status; - /* reassoc_if_failure: - * Valid only when status is non-zero. - * FW will do reassociation if link reconfig failure. - */ - A_UINT32 reassoc_if_failure; -} wmi_mlo_link_ttlm_complete_fixed_param; - #define WMI_TID_TO_LINK_MAP_TID_NUM_GET(_var) WMI_GET_BITS(_var, 0, 5) #define WMI_TID_TO_LINK_MAP_TID_NUM_SET(_var, _val) WMI_SET_BITS(_var, 0, 5, _val) @@ -53380,8 +47214,6 @@ typedef enum { WMI_MAP_SWITCH_TIMER_EXPIRED, /* Expected Duration Expired */ WMI_EXPECTED_DUR_EXPIRED, - /* Expected Duration Near to Expiry */ - WMI_EXPECTED_DUR_NEAR_TO_EXPIRY, } WMI_MLO_TID_TO_LINK_MAP_STATUS; #define WMI_BCAST_T2LM_MAX 16 /* max number of vdevs covered by T2LM stats */ @@ -54073,11 +47905,9 @@ typedef struct { } wmi_sawf_svc_class_disable_cmd_fixed_param; /* Used to store Hop count info for SDWF-Ezmesh scenario based on topology changes */ -#define WMI_SAWF_EZMESH_HOP_COUNT_SVC_ID_GET(svc_class_params) WMI_GET_BITS(svc_class_params, 0, 8) -#define WMI_SAWF_EZMESH_HOP_COUNT_SVC_ID_SET(svc_class_params, value) WMI_SET_BITS(svc_class_params, 0, 8, value) typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sawf_ezmesh_hop_count_cmd_fixed_param */ - A_UINT32 peer_id; /* deprecated field */ + A_UINT32 peer_id; A_UINT32 hop_count; /* delay_bound: * Placeholder for future functionality where delay bound will be directly @@ -54085,15 +47915,6 @@ typedef struct { * (units = ms) */ A_UINT32 delay_bound; - wmi_mac_addr mac_address; /* Mac Address of next BSTA */ - A_UINT32 vdev_id; - union { - struct { - A_UINT32 svc_id:8, - reserved:24; - }; - A_UINT32 svc_class_params; - }; } wmi_sawf_ezmesh_hop_count_cmd_fixed_param; typedef struct { @@ -54728,7 +48549,6 @@ typedef struct { #define WMI_PDEV_SET_CUSTOM_TX_PWR_MAX_2G_RATE_NUM_EXT 8 #define WMI_PDEV_SET_CUSTOM_TX_PWR_MAX_5G_6G_RATE_NUM 24 -#define WMI_PDEV_SET_CUSTOM_TX_PWR_MAX_5G_RATE_NUM_EXT 4 typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_custom_tx_power_per_mcs_cmd_fixed_param */ @@ -54754,22 +48574,22 @@ typedef struct { */ A_UINT32 bitmap_of_2GHz_band[WMI_PDEV_SET_CUSTOM_TX_PWR_MAX_CHAIN_NUM]; - /* 5GHz band has 4 chains and each chain has 24 rates and 4 extended rates. + /* 5GHz band has 4 chains and each chain has 24 rates. * bitmap_of_5GHz_band[0] -> chain 0 bitmap: - * |bit 0|bit 1|......|bit 23| bit 24 |......| bit 27 | - * |rate 0|rate 1|......|rate 23|ext rate 0|......|ext rate 3| + * |bit 0|bit 1|......|bit 23| + * |rate 0|rate 1|......|rate 23| * * bitmap_of_5GHz_band[1] -> chain 1 bitmap: - * |bit 0|bit 1|......|bit 23| bit 24 |......| bit 27 | - * |rate 0|rate 1|......|rate 23|ext rate 0|......|ext rate 3| + * |bit 0|bit 1|......|bit 23| + * |rate 0|rate 1|......|rate 23| * * bitmap_of_5GHz_band[2] -> chain 2 bitmap: - * |bit 0|bit 1|......|bit 23| bit 24 |......| bit 27 | - * |rate 0|rate 1|......|rate 23|ext rate 0|......|ext rate 3| + * |bit 0|bit 1|......|bit 23| + * |rate 0|rate 1|......|rate 23| * * bitmap_of_5GHz_band[3] -> chain 3 bitmap: - * |bit 0|bit 1|......|bit 23| bit 24 |......| bit 27 | - * |rate 0|rate 1|......|rate 23|ext rate 0|......|ext rate 3| + * |bit 0|bit 1|......|bit 23| + * |rate 0|rate 1|......|rate 23| */ A_UINT32 bitmap_of_5GHz_band[WMI_PDEV_SET_CUSTOM_TX_PWR_MAX_CHAIN_NUM]; @@ -55290,7 +49110,6 @@ typedef enum _WMI_VDEV_PAUSE_TYPE WMI_VDEV_PAUSE_TYPE_MLO_LINK = 1, WMI_VDEV_PAUSE_TYPE_TX = 2, WMI_VDEV_PAUSE_TYPE_TX_DATA = 3, - WMI_VDEV_PAUSE_TYPE_TX_RX = 4, } WMI_VDEV_PAUSE_TYPE; typedef struct { @@ -55890,9 +49709,7 @@ typedef struct { #define WMI_PEER_ACTIVE_TRAFFIC_TYPE_WEB_BROWSING_S 19 #define WMI_PEER_ACTIVE_TRAFFIC_TYPE_APERIODIC_BURST_TRAFFIC_1_M 0x00100000 #define WMI_PEER_ACTIVE_TRAFFIC_TYPE_APERIODIC_BURST_TRAFFIC_1_S 20 -#define WMI_PEER_ACTIVE_TRAFFIC_TYPE_LIVECAST_M 0x00200000 -#define WMI_PEER_ACTIVE_TRAFFIC_TYPE_LIVECAST_S 21 -/* bits 22-31 are reserved for new interactive traffic types */ +/* bits 21-31 are reserved for new interactive traffic types */ typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_active_traffic_map_cmd_fixed_param */ @@ -55998,10 +49815,7 @@ typedef struct { } wmi_mlo_link_del_param; typedef enum { - WMI_EVENT_POWER_BOOST_START_INFERENCING = 0, - /* alias */ - WMI_EVENT_POWER_BOOST_START_TRAINING = - WMI_EVENT_POWER_BOOST_START_INFERENCING, + WMI_EVENT_POWER_BOOST_START_TRAINING = 0, WMI_EVENT_POWER_BOOST_ABORT, WMI_EVENT_POWER_BOOST_COMPLETE, @@ -56011,13 +49825,9 @@ typedef enum { typedef enum { WMI_PDEV_POWER_BOOST_TS_FIRST_PASS = 0, WMI_PDEV_POWER_BOOST_TS_SECOND_PASS, - WMI_PDEV_POWER_BOOST_TS_THIRD_PASS, - WMI_PDEV_POWER_BOOST_TS_FOURTH_PASS, WMI_PDEV_POWER_BOOST_TS_MAX } wmi_pdev_power_boost_training_stage; -typedef wmi_pdev_power_boost_training_stage - wmi_pdev_power_boost_inferencing_stage; /* alias */ typedef struct { /* WMITLV_TAG_STRUC_wmi_pdev_power_boost_event_fixed_param */ @@ -56026,14 +49836,11 @@ typedef struct { A_UINT32 pdev_id; /* enum wmi_pdev_power_boost_event_type to update the power boost status */ A_UINT32 status; - /* inferencing_stage: - * The inferencing stage for which the I/Q samples are updated in DDR. - * This field holds a wmi_pdev_power_boost_inferencing_stage value. + /* training_stage: + * The training stage for which the I/Q samples are updated in DDR. + * This field holds a wmi_pdev_power_boost_training_stage value. */ - union { - A_UINT32 training_stage; /* deprecated name */ - A_UINT32 inferencing_stage; /* preferred name */ - }; + A_UINT32 training_stage; /* MCS value for which the current DPD training has been done */ A_UINT32 mcs; /* bandwidth: @@ -56058,16 +49865,6 @@ typedef struct { * in units of KB */ A_UINT32 size_kb; - /* tx_pwr: - * TX POWER of ANN PBT INFERENCING PKT (dBm units) - */ - A_INT32 tx_pwr; - /* tx_chain_idx: - * CHAIN INDEX where WMI is sent to HOST to start inferencing - */ - A_UINT32 tx_chain_idx; - /* req_id: to distinguish pdev_power_boost event instances */ - A_UINT32 req_id; } wmi_pdev_power_boost_event_fixed_param; typedef enum { @@ -56085,14 +49882,8 @@ typedef struct { A_UINT32 pdev_id; /* enum wmi_pdev_power_boost_cmd_type to update the power boost status */ A_UINT32 status; - /* - * wmi_pdev_power_boost_inferencing_stage value to indicate - * inferencing stage - */ - union { - A_UINT32 training_stage; /* deprecated name */ - A_UINT32 inferencing_stage; /* preferred name */ - }; + /* wmi_pdev_power_boost_training_stage value to indicate training stage */ + A_UINT32 training_stage; /* MCS value for which the Power Boost training has been done */ A_UINT32 mcs; /* Bandwidth in Mhz for which the Power Boost training has been done */ @@ -56120,8 +49911,6 @@ typedef struct { * training, in units of 1/4 (0.25dBm) steps. */ A_INT32 tx_mask_margin; - /* req_id: to distinguish pdev_power_boost cmd instances */ - A_UINT32 req_id; } wmi_pdev_power_boost_cmd_fixed_param; typedef struct { @@ -56142,35 +49931,6 @@ typedef struct { A_UINT32 tlv_header; } wmi_get_scan_cache_result_cmd_fixed_param; -typedef enum { - WMI_PLIM_DIRECTION_NONE = 0, - WMI_PLIM_DIRECTION_INCREASE, - WMI_PLIM_DIRECTION_DECREASE -} wmi_plim_direction_type; - -typedef struct { - /* WMITLV_TAG_STRUC_wmi_set_modify_tx_plim_cmd_fixed_param */ - A_UINT32 tlv_header; - /* Requested level for future enhancement, default value shall be 1 */ - A_UINT32 multiplier; - /* takes values from enum wmi_plim_direction_type */ - A_UINT32 direction; -} wmi_set_modify_tx_plim_cmd_fixed_param; - -typedef struct { - /* WMITLV_TAG_STRUC_wmi_get_avg_tx_power_cmd_fixed_param */ - A_UINT32 tlv_header; - /* Current active DSI (device state index) */ - A_UINT32 dsi_id; -} wmi_get_avg_tx_power_cmd_fixed_param; - -typedef struct { - /* WMITLV_TAG_STRUC_wmi_get_tx_power_calling_cmd_fixed_param */ - A_UINT32 tlv_header; - /* DSI index for which power limit info is to be fetched */ - A_UINT32 dsi_id; -} wmi_get_tx_power_calling_cmd_fixed_param; - /* Element ID 61 (HT Operation) is present (see HT 7.3.2) */ #define WIFI_CACHED_SCAN_RESULT_FLAGS_HT_OPS_PRESENT_GET(flags) WMI_GET_BITS(flags, 0, 1) #define WIFI_CACHED_SCAN_RESULT_FLAGS_HT_OPS_PRESENT_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value) @@ -56193,7 +49953,7 @@ typedef struct { typedef struct { - A_UINT32 width; /* wmi_channel_width */ + wmi_channel_width width; A_UINT32 center_frequency0; /* Frequency value in MHz */ A_UINT32 center_frequency1; /* Frequency value in MHz */ A_UINT32 primary_frequency; /* Frequency value in MHz */ @@ -56232,66 +49992,6 @@ typedef struct { */ } wmi_scan_cache_result_fixed_param; -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_modify_tx_plim_event_fixed_param */ - - A_UINT32 status; /* 0 = success, 1 = failure */ -} wmi_modify_tx_plim_event_fixed_param; - -typedef enum { - /* Invalid Chain combination */ - WMI_POWER_REGION_INVALID = 0, - - /* Avg. tx power <= PowerLimit-backoff */ - WMI_POWER_REGION_LOW = 1, - - /* PowerLimit-backoff < Avg. tx power <= PowerLimit */ - WMI_POWER_REGION_MEDIUM = 2, - - /* PowerLimit < Avg. tx power <= PowerLimit+Boost */ - WMI_POWER_REGION_HIGH = 3, - - /* Avg. tx power > PowerLimit+Boost */ - WMI_POWER_REGION_EXTRA_HIGH = 4, - -} wmi_phyrf_tas_chain_power_region_type; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_avg_tx_power_region_per_antenna_chain */ - /* Valid chain number for which chain_power_region is filled */ - A_UINT32 chain_no; - A_UINT32 chain_operating_band; /* 0: 2GHz, 1: 5GHz, 2: 6GHz */ - /* takes values from enum wmi_phyrf_tas_chain_power_region_type */ - A_UINT32 chain_power_region; -} wmi_avg_tx_power_region_per_antenna_chain; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_avg_tx_power_event_fixed_param */ - A_UINT32 status; /* 0 = success, 1 = failure */ - /* Exposure window over which TX power is averaged */ - A_UINT32 time_window_in_sec; - /* The below TLVs follow this TLV - * struct wmi_avg_tx_power_region_per_antenna_chain[]; - */ -} wmi_avg_tx_power_event_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tx_power_per_antenna_chain */ - A_UINT32 chain_no; /* Valid chain number for which power is filled */ - A_UINT32 chain_operating_band; /* 0: 2GHz, 1: 5GHz, 2: 6GHz */ - A_INT32 power; /* Power limit in units of 0.25 dBm */ -} wmi_tx_power_per_antenna_chain; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_plimit_table_event_fixed_param */ - A_UINT32 status; /* 0 = success, 1 = failure */ - A_UINT32 dsi_id; /* DSI index for which below entries are filled */ - /* The below TLVs follow this TLV - * struct wmi_tx_power_per_antenna_chain[]; - */ -} wmi_plimit_table_event_fixed_param; - - #define WMI_POWER_BOOST_CAPABILITIES_PHY_ID_GET(word32) WMI_GET_BITS(word32, 0, 4) #define WMI_POWER_BOOST_CAPABILITIES_PHY_ID_SET(word32, value) WMI_SET_BITS(word32, 0, 4, value) #define WMI_POWER_BOOST_CAPABILITIES_POWER_BOOST_ENABLE_GET(word32) WMI_GET_BITS(word32, 4, 1) @@ -56359,9 +50059,8 @@ typedef struct { }; /* * The below TLVs follow this TLV in the WMI_VDEV_VBSS_CONFIG_CMDID msg: - * - wmi_vdev_vbss_peer_pn_info[]; * - wmi_vdev_vbss_peer_sn_info[]; - * - wmi_vdev_vbss_peer_dyn_info; + * - wmi_vdev_vbss_peer_pn_info[]; */ } wmi_vdev_vbss_config_cmd_fixed_param; @@ -56394,62 +50093,15 @@ typedef struct { ssn: 16; }; }; + /* The below TLVs follow this TLV in the WMI_VDEV_VBSS_CONFIG_EVENTID msg: + * - A_UINT32 scan_freq_list[]; + * - wmi_vdev_vbss_config_event_fixed_param[]; + */ } wmi_vdev_vbss_peer_sn_info; -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_vbss_peer_dyn_info */ - union { - A_UINT32 peer_dyn_info1_word32; - struct { - /** 15:0 omi - * 31:16 eht_omi - */ - A_UINT32 - omi: 16, - eht_omi: 16; - }; - }; - union { - A_UINT32 peer_dyn_info2_word32; - struct { - /** 0:0 pm - * 1:1 emlsr - * 17:2 padding_delay - * 26:18 transition_delay - * 30:27 transition_timeout - * 31 Reserved - */ - A_UINT32 - pm : 1, - emlsr : 1, - padding_delay_us : 16, - transition_delay_us : 9, - transition_timeout_us: 4, - rsvd1 : 1; - }; - }; - union { - A_UINT32 peer_dyn_info3_word32; - struct { - /** 13:0 link_bitmap - * 31:15 Reserved - */ - A_UINT32 - link_bitmap: 14, - rsvd2 : 18; - }; - }; -} wmi_vdev_vbss_peer_dyn_info; - typedef enum { - WMI_VBSS_UNICAST_PN_INFO = 1, - WMI_VBSS_MULTICAST_PN_INFO = 2, -} wmi_vbss_pn_ctxt_id; - -typedef enum { - WMI_VBSS_GET_PEER_CONTEXT = 1, - WMI_VBSS_SET_PEER_CONTEXT = 2, - WMI_VBSS_RX_SUSPEND_PEER_CONTEXT = 3, + WMI_VBSS_GET_PEER_CONTEXT = 0x1, + WMI_VBSS_SET_PEER_CONTEXT = 0x2, } wmi_vbss_action; #define WMI_VDEV_VBSS_GET_ACTION(action) WMI_GET_BITS(action, 0, 4) @@ -56464,30 +50116,6 @@ typedef enum { #define WMI_VDEV_VBSS_SN_INFO_GET_SSN(tid_num_ssn) WMI_GET_BITS(tid_num_ssn, 16, 16) #define WMI_VDEV_VBSS_SN_INFO_SET_SSN(action, value) WMI_SET_BITS(tid_num_ssn, 16, 16, value) -#define WMI_VDEV_VBSS_DYN_INFO_GET_OMI(peer_dyn_info1) WMI_GET_BITS(omi, 0, 16) -#define WMI_VDEV_VBSS_DYN_INFO_SET_OMI(peer_dyn_info1, value) WMI_SET_BITS(omi, 0, 16, value) - -#define WMI_VDEV_VBSS_DYN_INFO_GET_EHT_OMI(peer_dyn_info1) WMI_GET_BITS(eht_omi, 16, 16) -#define WMI_VDEV_VBSS_DYN_INFO_SET_EHT_OMI(peer_dyn_info1, value) WMI_SET_BITS(eht_omi, 16, 16, value) - -#define WMI_VDEV_VBSS_DYN_INFO_GET_PM(peer_dyn_info2) WMI_GET_BITS(pm, 0, 1) -#define WMI_VDEV_VBSS_DYN_INFO_SET_PM(peer_dyn_info2, value) WMI_SET_BITS(pm, 0, 1, value) - -#define WMI_VDEV_VBSS_DYN_INFO_GET_EMLSR(peer_dyn_info2) WMI_GET_BITS(emlsr, 1, 1) -#define WMI_VDEV_VBSS_DYN_INFO_SET_EMLSR(peer_dyn_info2, value) WMI_SET_BITS(emlsr, 1, 1, value) - -#define WMI_VDEV_VBSS_DYN_INFO_GET_PADDING_DELAY(peer_dyn_info2) WMI_GET_BITS(padding_delay, 2, 16) -#define WMI_VDEV_VBSS_DYN_INFO_SET_PADDING_DELAY(peer_dyn_info2, value) WMI_SET_BITS(padding_delay, 2, 16, value) - -#define WMI_VDEV_VBSS_DYN_INFO_GET_TRANSITION_DELAY(peer_dyn_info2) WMI_GET_BITS(transition_delay, 18, 9) -#define WMI_VDEV_VBSS_DYN_INFO_SET_TRANSITION_DELAY(peer_dyn_info2, value) WMI_SET_BITS(transition_delay, 18, 9, value) - -#define WMI_VDEV_VBSS_DYN_INFO_GET_TRANSITION_TIMEOUT(peer_dyn_info2) WMI_GET_BITS(transition_timeout, 27, 4) -#define WMI_VDEV_VBSS_DYN_INFO_SET_TRANSITION_TIMEOUT(peer_dyn_info2, value) WMI_SET_BITS(transition_timeout, 27, 4, value) - -#define WMI_VDEV_VBSS_DYN_INFO_GET_LINK_BITMAP(peer_dyn_info3) WMI_GET_BITS(link_bitmap, 0, 14) -#define WMI_VDEV_VBSS_DYN_INFO_SET_LINK_BITMAP(peer_dyn_info3, value) WMI_SET_BITS(link_bitmap, 0, 14, value) - typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_vbss_config_event_fixed_param */ @@ -56502,1790 +50130,6 @@ typedef struct { } wmi_vdev_vbss_config_event_fixed_param; -typedef enum { - /* Channel bandwidth based semi static PCIe config */ - WMI_PCIE_CONFIG_TYPE_CHANNEL_BANDWIDTH, - /* Force a specific PCIe config */ - WMI_PCIE_CONFIG_TYPE_FORCED_STATIC, -} wmi_pcie_config_type_e; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_energy_mgmt_pcie_config_cmd_fixed_param */ - A_UINT32 tlv_header; - /** enable or disable PCIe config */ - A_UINT32 enable; - /* PCIe config type (holds a wmi_pcie_config_type_e value) */ - A_UINT32 config_type; - /** pcie_gen: pcie generation to be used - * pcie_lane:pcie lane config (lane number) to be used - */ - A_UINT32 pcie_gen; - A_UINT32 pcie_lane; -} wmi_energy_mgmt_pcie_config_cmd_fixed_param; - -typedef enum { - WMI_PCIE_LPM_CONFIG_TYPE_UNKNOWN, - WMI_PCIE_LPM_CONFIG_TYPE_L0S, - WMI_PCIE_LPM_CONFIG_TYPE_L1, - WMI_PCIE_LPM_CONFIG_TYPE_L0S_L1, -} wmi_pcie_lpm_config_type_e; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_energy_mgmt_pcie_lpm_cmd_fixed_param */ - A_UINT32 tlv_header; - /** enable or disable PCIe LPM */ - A_UINT32 enable; - /** PCIe LPM config type */ - A_UINT32 config_type; /* holds a wmi_pcie_lpm_config_type_e value */ -} wmi_energy_mgmt_pcie_lpm_cmd_fixed_param; - -typedef enum { - WMI_DCVS_ENABLE, /* Enable clock and voltage scaling */ - WMI_DCVS_DISABLE, /* Disable clock and voltage scaling */ - WMI_DCVS_CLOCK_SCALING_ONLY, /* Enable only clock scaling */ -} wmi_dcvs_config_e; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_energy_mgmt_dcvs_config_cmd_fixed_param */ - A_UINT32 tlv_header; - /** DCVS config - holds a wmi_dcvs_config_e value */ - A_UINT32 config; -} wmi_energy_mgmt_dcvs_config_cmd_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_energy_mgmt_dps_config_cmd_fixed_param */ - A_UINT32 tlv_header; - /** enable or disable DPS config */ - A_UINT32 enable; - /** PDEV identifier */ - A_UINT32 pdev_id; - /** Channel to be used in DPS Low cap mode, freq must match the primary home chan freq */ - wmi_channel low_cap_channel; - /** Tx chainmask to be used in DPS Low cap mode */ - A_UINT32 low_cap_tx_chainmask; - /** Rx chainmask to be used in DPS Low cap mode */ - A_UINT32 low_cap_rx_chainmask; - /** Mbps throughput after which DPS will be exited and notified to Host */ - A_UINT32 exit_thpt_thrsld_mbps; - /** number of wakeups per second after which DPS will be exited and notified to Host */ - A_UINT32 exit_wakeup_thrsld_per_second; -} wmi_energy_mgmt_edps_config_cmd_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_energy_mgmt_puo_config_cmd_fixed_param */ - A_UINT32 tlv_header; - /** enable or disable DPS config */ - A_UINT32 enable; - /** PDEV identifier */ - A_UINT32 pdev_id; - /** Channel to be used in PUO Low cap mode, freq must match the primary home chan freq */ - wmi_channel low_cap_channel; - /** Tx chainmask to be used in Low cap mode */ - A_UINT32 low_cap_tx_chainmask; - /** Rx chainmask to be used in Low cap mode */ - A_UINT32 low_cap_rx_chainmask; - /** minimum duration required between SP end and SP start to trigger entering to doze state */ - A_UINT32 min_doze_thrsld_in_us; -} wmi_energy_mgmt_puo_config_cmd_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_energy_mgmt_eco_mode_config_cmd_fixed_param */ - A_UINT32 tlv_header; - /** enable or disable DPS config */ - A_UINT32 enable; - /** PDEV identifier */ - A_UINT32 pdev_id; -} wmi_energy_mgmt_eco_mode_config_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param */ - A_UINT32 pdev_id; /** pdev ID set by the command */ -} wmi_pdev_multi_vdev_get_ac_queue_depth_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_ac_info */ - A_UINT32 vdev_id; - /** pending_packets_per_ac: - * number of MSDUs pending in MSDU and MPDU queues for the Access Category - * for the specific vdev - */ - A_UINT32 pending_packets_per_ac[WLAN_MAX_AC]; -} wmi_vdev_ac_info; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param */ - A_UINT32 pdev_id; /* pdev ID set by the command */ - /* The TLVs for the 4 AC follows with the vdev_id : - * wmi_vdev_ac_info vdev_ac_info[]; wmi_vdev_ac_info for BE/BK/VI/VO - */ -} wmi_pdev_multi_vdev_ac_queue_depth_event_fixed_param; - -typedef enum { - WMI_PDEV_SET_TX_CHAINMASK_SUCCESS = 0, - WMI_PDEV_SET_TX_CHAINMASK_FAIL_INVALID_CHAINMASK, -} WMI_PDEV_SET_TX_CHAINMASK_COMP_STATUS_TYPE; - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_tx_chainmask_comp_event_fixed_param */ - /** pdev_id for identifying the MAC - */ - A_UINT32 pdev_id; - /* - * status type WMI_PDEV_SET_TX_CHAINMASK_COMP_STATUS_TYPE - */ - A_UINT32 status; -} wmi_pdev_set_tx_chainmask_comp_event_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_vdev_traffic_monitoring_cmd_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - /** TX RX byte count value, in KB units */ - A_UINT32 data_threshold; - /** duration of traffic monitoring, in unit of sec */ - A_UINT32 traffic_monitoring_time; -} wmi_vdev_traffic_monitoring_cmd_fixed_param; - -typedef enum { - WMI_DPS_ASSISTING_ROLE_DISABLE, /* Disable - DPS: AP Assisting role */ - WMI_DPS_ASSISTING_ROLE_ENABLE, /* Enable - DPS: AP Assisting role */ -} wmi_dps_assisting_role_e; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param */ - A_UINT32 tlv_header; - /* VDEV identifier */ - A_UINT32 vdev_id; - /** holds a wmi_dps_assisting_role_e value */ - A_UINT32 config; -} wmi_vdev_energy_mgmt_dps_assisting_role_config_cmd_fixed_param; - -typedef struct { - /** TLV tag and len; */ - A_UINT32 tlv_header; - - /* content_type: - * This OEM-defined value specifies what kind of Energy Management - * data is present in the opaque "data" bytestream TLV. - */ - A_UINT32 content_type; - /* num bytes to distinguish data bytes from alignment-padding bytes */ - A_UINT32 num_bytes_valid; -} wmi_energy_mgmt_oem_data_fixed_param; - -typedef struct { - /** TLV tag and len; */ - A_UINT32 tlv_header; - - /* content_type: - * This OEM-defined value specifies what kind of Energy Management - * data is present in the opaque "data" bytestream TLV. - */ - A_UINT32 content_type; - /* num bytes to distinguish data bytes from alignment-padding bytes */ - A_UINT32 num_bytes_valid; -} wmi_energy_mgmt_oem_data_event_fixed_param; - - -/* WMI evt to indicate FW is ready */ -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_fw_ready_ind_event_fixed_param */ - A_UINT32 tlv_header; -} wmi_fw_ready_ind_event_fixed_param; - -typedef enum { - WMI_DRIVER_MODE_MISSION, - WMI_DRIVER_MODE_FTM, - WMI_DRIVER_MODE_OFF, -} WMI_DRIVER_MODE; - -/** WMI command to indicate the driver mode of operation */ -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_wlan_mode_req_cmd_fixed_param */ - A_UINT32 tlv_header; - /* This indicates driver mode of operation from host */ - A_UINT32 mode; /* refer to WMI_DRIVER_MODE enum */ -} wmi_wlan_mode_req_cmd_fixed_param; - -typedef enum { - WMI_DRIVER_MODE_RESP_SUCCESS, - WMI_DRIVER_MODE_RESP_FAILURE, -} WMI_WLAN_DRIVER_MODE_RESP_STATUS; - -typedef enum { - WMI_DRIVER_FAIL_REASON_UNKNOWN_MODE, - /* In FTM mode, initiate PHY error */ - WMI_DRIVER_FAIL_REASON_FTM_PHY_INIT_ERR, - /* For both MISSION and FTM mode, set power error */ - WMI_DRIVER_FAIL_REASON_POWER_INIT_ERR, - WMI_DRIVER_FAIL_REASON_MODE_OFF_ERR, -} WMI_WLAN_MODE_FAILURE_REASON; - -/* Host/Firmware can get/set the status bits using below macros */ -#define WMI_WLAN_DRIVER_MODE_RESP_STATUS_GET(status) WMI_GET_BITS(status, 0, 16) -#define WMI_WLAN_DRIVER_MODE_RESP_STATUS_SET(status, value) WMI_SET_BITS(status, 0, 16, value) - -#define WMI_WLAN_DRIVER_MODE_RESP_FAILURE_GET(mode) WMI_GET_BITS(mode, 16, 16) -#define WMI_WLAN_DRIVER_MODE_RESP_FAILURE_SET(mode, value) WMI_GET_BITS(mode, 16, 16, value) - -/* WMI evt to acknowledge the driver mode sent by host */ -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_wlan_mode_resp_event_fixed_param */ - A_UINT32 tlv_header; - /* The status word contains the following bitfields: - * bits 15:0 - Indicates whether the FW has accepted - * (WMI_DRIVER_MODE_RESP_SUCCESS) or rejected - * (WMI_DRIVER_MODE_RESP_FAILURE) the driver mode - * specified by the host. - * bits 31:16 - Indicates the reason if the FW has rejected - * the driver mode. - * This field is only relevant if the status is - * WMI_DRIVER_MODE_RESP_FAILURE. - */ - A_UINT32 status; -} wmi_wlan_mode_resp_event_fixed_param; - -/* Optional version for future expansion */ -typedef enum { - WMI_IPA_RING_STATS_EVENT_VERSION1 = 1, - -} WMI_IPA_RING_STATS_EVENT_VERSIONS; - -typedef struct { - A_UINT32 tlv_header; - /* version: - * For future extensions; currently 1 (WMI_IPA_RING_STATS_EVENT_VERSION1) - * Refer to WMI_IPA_RING_STATS_EVENT_VERSIONS. - */ - A_UINT32 version; - A_UINT32 ring_id; -} wmi_ipa_ring_stats_req_cmd_fixed_param; - -/* Per-ring sample (indices and sizes in entries to keep host parsing simple) */ -typedef struct { - A_UINT32 tlv_header; - A_UINT32 ring_id; /* e.g., HAL ring_id or your own enum */ - A_UINT32 hp_idx; /* head pointer index (entry index) */ - A_UINT32 tp_idx; /* tail pointer index (entry index) */ - A_UINT32 free_entries; /* how many entries free */ - A_UINT32 ring_entries; /* total entries */ -} wmi_ipa_ring_stat_entry; - -/* Event fixed params (TLV-safe layout) */ -typedef struct { - A_UINT32 tlv_header; - A_UINT32 version; /* Refer to WMI_RING_STATS_EVENT_VERSIONS */ -} wmi_ipa_ring_stats_conf_event_fixed_param; - - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_uhr_ap_dps_params */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* - * Bit0 : Mode enable - 1 / disable - 0 - * This indicates whether DPS for this VAP is enabled or disabled - * Bit1 : Mode Update - * This should be set when any of the DPS params needs an update - * Bit2-31 : Reserved - */ - A_UINT32 mode_tuple_field; - /* Add the required fields below*/ -} wmi_uhr_ap_dps_params; - -#define WMI_DPS_MODE_TUPLE_ENABLE_GET(_var) WMI_GET_BITS(_var, 0, 1) -#define WMI_DPS_MODE_TUPLE_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val) - -#define WMI_DPS_MODE_TUPLE_UPDATE_GET(_var) WMI_GET_BITS(_var, 1, 1) -#define WMI_DPS_MODE_TUPLE_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val) - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_uhr_ap_npca_params */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* - * Bit0 : Mode enable - 1 / disable - 0 - * This indicates whether NPCA for this VAP is enabled or disabled - * Bit1 : Mode Update - * This should be set when any of the NPCA params needs an update - * Bit2-31 : Reserved - */ - A_UINT32 mode_tuple_field; - /* npca_chan: - * WMI Non-Primary Channel Access channel - * Specifically, this is the "other primary" channel used if the - * "main primary" is occupied by low-bandwidth OBSS traffic. - */ - wmi_channel npca_chan; - /* NPCA punctured bitmap */ - A_UINT32 puncture_20mhz_bitmap; - /* - * Bit0-7 : NPCA Primary Channel - * WMI_NPCA_PRIM_CHAN_GET / WMI_NPCA_PRIM_CHAN_SET - * - * Bit8-11 : NPCA Minium Threshold - * The NPCA minimum duration threshold T, in units of 128 - * us, is T = 512 + NMDT x 128, where NMDT is the field - * value, which yields a minimum of 512 us and a maximum of - * 2432 us. The minimum is chosen to cover at least the - * transmission time of NPCA ICF and ICR exchange plus a - * typical Data and Ack/BA exchange using non-HT or non- - * HT duplicate PPDU format with 6 Mb/s data rate - * WMI_NPCA_AP_CAP_MIN_THRES_GET / _SET - * - * Bit12-17: NPCA Switch Delay - * The time needed by an NPCA STA to switch from the - * BSS primary channel to the NPCA primary channel, - * in units of 4 us. - * WMI_NPCA_AP_CAP_SWITCH_DELAY_GET / _SET - * - * Bit18:23: NPCA Switch Back Delay - * The time needed by an NPCA STA to switch from the - * NPCA primary channel to the BSS primary channel, - * in units of 4 us. - * WMI_NPCA_AP_CAP_SWITCH_BACK_DELAY_GET / _SET - * - * Bit24:25: The Initial NPCA QSRC field indicates the value - * that is used to initialize the EDCAF QSRC[AC] variables - * when an NPCA STA in the BSS switches to NPCA operation. - * WMI_NPCA_AP_CAP_MIN_THRES_GET / _SET - * - * Bit26 : The MOPLEN NPCA field indicates which conditions can be used - * to initiate an NPCA operation. A value of 1 in this field - * indicates that both PHYLEN NPCA operation and MOPLEN NPCA - * operations are permitted in the BSS. - * A value of 0 in this field indicates that only PHYLEN NPCA - * operation is allowed in the BSS. - * WMI_NPCA_AP_CAP_MOPLEN_GET / _SET - * - * Bit27 : The NPCA Disabled Subchannel Bitmap Present field indicates - * whether the NPCA Disabled Subchannel Bitmap field is present. - * This field indicates that the NPCA Disabled Subchannel Bitmap - * field is present. - * WMI_NPCA_AP_CAP_DISABLED_SB_PRESENT_GET / _SET - * - * Bit28-31: Reserved - */ - A_UINT32 npca_cap1; - - /* - * Bit0-15 : The NPCA Disabled Subchannel Bitmap field is a bitmap where - * the lowest numbered bit corresponds to the 20 MHz subchannel - * that lies within the BSS bandwidth and is the lowest in - * frequency of the set of all 20MHz subchannels within the BSS - * bandwidth. Each successive bit in the bitmap corresponds to - * the next higher frequency 20 MHz subchannel. A bit in the - * bitmap that lies within the BSS bandwidth is set to 1 to - * indicate that the corresponding 20MHz subchannel is - * punctured and is set to 0 to indicate that the corresponding - * 20 MHz subchannel is not punctured. A bit in the bitmap that - * falls outside of the BSS bandwidth is reserved. - * This field is present when the value of the NPCA Disabled - * Subchannel Bitmap Field Present field is equal to 1, and - * not present, otherwise. - * WMI_NPCA_AP_CAP_DISABLED_SB_GET / _SET - * - * Bit16-31: Reserved - */ - A_UINT32 npca_cap2; -} wmi_uhr_ap_npca_params; - -#define WMI_NPCA_MODE_TUPLE_ENABLE_GET(_var) WMI_GET_BITS(_var, 0, 1) -#define WMI_NPCA_MODE_TUPLE_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val) - -#define WMI_NPCA_MODE_TUPLE_UPDATE_GET(_var) WMI_GET_BITS(_var, 1, 1) -#define WMI_NPCA_MODE_TUPLE_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val) - -#define WMI_NPCA_PRIM_CHAN_GET(_var) WMI_GET_BITS(_var, 0, 8) -#define WMI_NPCA_PRIM_CHAN_SET(_var, _val) WMI_SET_BITS(_var, 0, 8, _val) - -#define WMI_NPCA_AP_CAP_MIN_THRESH_GET(_var) WMI_GET_BITS(_var, 8, 4) -#define WMI_NPCA_AP_CAP_MIN_THRESH_SET(_var, _val) WMI_SET_BITS(_var, 8, 4, _val) - -#define WMI_NPCA_AP_CAP_SWITCH_DELAY_GET(_var) WMI_GET_BITS(_var, 12, 6) -#define WMI_NPCA_AP_CAP_SWITCH_DELAY_SET(_var, _val) WMI_SET_BITS(_var, 12, 6, _val) - -#define WMI_NPCA_AP_CAP_SWITCH_BACK_DELAY_GET(_var) WMI_GET_BITS(_var, 18, 6) -#define WMI_NPCA_AP_CAP_SWITCH_BACK_DELAY_SET(_var, _val) WMI_SET_BITS(_var, 18, 6, _val) - -#define WMI_NPCA_AP_CAP_QSRC_GET(_var) WMI_GET_BITS(_var, 24, 2) -#define WMI_NPCA_AP_CAP_QSRC_SET(_var, _val) WMI_SET_BITS(_var, 24, 2, _val) - -#define WMI_NPCA_AP_CAP_MOPLEN_GET(_var) WMI_GET_BITS(_var, 26, 1) -#define WMI_NPCA_AP_CAP_MOPLEN_SET(_var, _val) WMI_SET_BITS(_var, 26, 1, _val) - -#define WMI_NPCA_AP_CAP_DISABLED_SB_PRESENT_GET(_var) WMI_GET_BITS(_var, 27, 1) -#define WMI_NPCA_AP_CAP_DISABLED_SB_PRESENT_SET(_var, _val) WMI_SET_BITS(_var, 27, 1, _val) - -#define WMI_NPCA_AP_CAP_DISABLED_SB_GET(_var) WMI_GET_BITS(_var, 0, 16) -#define WMI_NPCA_AP_CAP_DISABLED_SB_SET(_var, _val) WMI_SET_BITS(_var, 0, 16, _val) - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_uhr_ap_duo_params */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* - * Bit0 : Mode enable - 1 / disable - 0 - * This indicates whether NPCA for this VAP is enabled or disabled - * Bit1 : Mode Update - * This should be set when any of the NPCA params needs an update - * Bit2-31 : Reserved - */ - A_UINT32 mode_tuple_field; - /* Add any new required fields below */ -} wmi_uhr_ap_duo_params; - -#define WMI_UHR_AP_DUO_PARAMS_ENABLE_GET(_var) WMI_GET_BITS(_var, 0, 1) -#define WMI_UHR_AP_DUO_PARAMS_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val) - -#define WMI_UHR_AP_DUO_PARAMS_UPDATE_GET(_var) WMI_GET_BITS(_var, 1, 1) -#define WMI_UHR_AP_DUO_PARAMS_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val) - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_uhr_ap_pedca_params */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* - * - * Bit0 : Mode enable - 1 / disable - 0 - * This indicates whether NPCA for this VAP is enabled or disabled - * - * Bit1 : Mode Update - * This should be set when any of the NPCA params needs an update - * - * Bit2-31 : Reserved - */ - A_UINT32 mode_tuple_field; - /* Add any new required fields below */ -} wmi_uhr_ap_pedca_params; - -#define WMI_UHR_AP_PEDCA_PARAMS_ENABLE_GET(_var) WMI_GET_BITS(_var, 0, 1) -#define WMI_UHR_AP_PEDCA_PARAMS_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val) - -#define WMI_UHR_AP_PEDCA_PARAMS_UPDATE_GET(_var) WMI_GET_BITS(_var, 1, 1) -#define WMI_UHR_AP_PEDCA_PARAMS_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val) - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_uhr_ap_dbe_params */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* - * Bit0 : Mode enable - 1 / disable - 0 - * This indicates whether NPCA for this VAP is enabled or disabled - * Bit1 : Mode Update - * This should be set when any of the NPCA params needs an update - * Bit2-31 : Reserved - */ - A_UINT32 mode_tuple_field; - /* Add any new required fields below */ -} wmi_uhr_ap_dbe_params; - -#define WMI_UHR_AP_DBE_PARAMS_ENABLE_GET(_var) WMI_GET_BITS(_var, 0, 1) -#define WMI_UHR_AP_DBE_PARAMS_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val) - -#define WMI_UHR_AP_DBE_PARAMS_UPDATE_GET(_var) WMI_GET_BITS(_var, 1, 1) -#define WMI_UHR_AP_DBE_PARAMS_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val) - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_uhr_ap_puo_params */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* - * Bit0 : Mode enable - 1 / disable - 0 - * This indicates whether NPCA for this VAP is enabled or disabled - * Bit1 : Mode Update - * This should be set when any of the NPCA params needs an update - * Bit2-31 : Reserved - */ - A_UINT32 mode_tuple_field; - /* Add any new required fields below */ -} wmi_uhr_ap_puo_params; - -#define WMI_UHR_AP_PUO_PARAMS_ENABLE_GET(_var) WMI_GET_BITS(_var, 0, 1) -#define WMI_UHR_AP_PUO_PARAMS_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val) - -#define WMI_UHR_AP_PUO_PARAMS_UPDATE_GET(_var) WMI_GET_BITS(_var, 1, 1) -#define WMI_UHR_AP_PUO_PARAMS_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val) - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_uhr_ap_elr_reception_params */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* - * Bit0 : Mode enable - 1 / disable - 0 - * This indicates whether NPCA for this VAP is enabled or disabled - * Bit1 : Mode Update - * This should be set when any of the NPCA params needs an update - * Bit2-31 : Reserved - */ - A_UINT32 mode_tuple_field; - /* Add any new required fields below */ -} wmi_uhr_ap_elr_reception_params; - -#define WMI_UHR_AP_ELR_RECEPTION_PARAMS_ENABLE_GET(_var) WMI_GET_BITS(_var, 0, 1) -#define WMI_UHR_AP_ELR_RECEPTION_PARAMS_ENABLE_SET(_var, _val) WMI_SET_BITS(_var, 0, 1, _val) - -#define WMI_UHR_AP_ELR_RECEPTION_PARAMS_UPDATE_GET(_var) WMI_GET_BITS(_var, 1, 1) -#define WMI_UHR_AP_ELR_RECEPTION_PARAMS_UPDATE_SET(_var, _val) WMI_SET_BITS(_var, 1, 1, _val) - - -/* ---------------- Mode bit positions ---------------- */ -typedef enum { - WMI_UHR_AP_MODE_TUP_DPS = 0, - WMI_UHR_AP_MODE_TUP_NPCA = 1, - WMI_UHR_AP_MODE_TUP_DUO = 2, - WMI_UHR_AP_MODE_TUP_PEDCA = 3, - WMI_UHR_AP_MODE_TUP_DBE = 4, - WMI_UHR_AP_MODE_TUP_PUO = 5, - WMI_UHR_AP_MODE_TUP_ELR = 6, - /* Future modes -> 6..23 */ - WMI_UHR_MAX_MODES = 24 -} WMI_UHR_AP_MODE_TUP; - -typedef enum{ - WMI_UHR_AP_MODE_TUP_STATE_DISABLE = 0, - WMI_UHR_AP_MODE_TUP_STATE_ENABLE = 1, - WMI_UHR_AP_MODE_TUP_STATE_UPDATE = 2, - WMI_UHR_AP_MODE_TUP_STATE_RESERVED = 3, - WMI_UHR_AP_MODE_TUP_STATE_MAX = 4 -} WMI_UHR_AP_MODE_TUP_STATE; - -#define WMI_UHR_AP_VDEV_ID_GET(var) WMI_GET_BITS(var, 0, 8) -#define WMI_UHR_AP_VDEV_ID_SET(var, val) WMI_SET_BITS(var, 0, 8, val) - - -#define WMI_UHR_AP_MODE_TUP_DPS_GET(var) WMI_GET_BITS(var, 8, 2) -#define WMI_UHR_AP_MODE_TUP_DPS_SET(var, val) WMI_SET_BITS(var, 8, 2, val) - -#define WMI_UHR_AP_MODE_TUP_NPCA_GET(var) WMI_GET_BITS(var, 10, 2) -#define WMI_UHR_AP_MODE_TUP_NPCA_SET(var, val) WMI_SET_BITS(var, 10, 2, val) - -#define WMI_UHR_AP_MODE_TUP_DUO_GET(var) WMI_GET_BITS(var, 12, 2) -#define WMI_UHR_AP_MODE_TUP_DUO_SET(var, val) WMI_SET_BITS(var, 12, 2, val) - -#define WMI_UHR_AP_MODE_TUP_PEDCA_GET(var) WMI_GET_BITS(var, 14, 2) -#define WMI_UHR_AP_MODE_TUP_PEDCA_SET(var, val) WMI_SET_BITS(var, 14, 2, val) - -#define WMI_UHR_AP_MODE_TUP_DBE_GET(var) WMI_GET_BITS(var, 16, 2) -#define WMI_UHR_AP_MODE_TUP_DBE_SET(var, val) WMI_SET_BITS(var, 16, 2, val) - -#define WMI_UHR_AP_MODE_TUP_PUO_GET(var) WMI_GET_BITS(var, 18, 2) -#define WMI_UHR_AP_MODE_TUP_PUO_SET(var, val) WMI_SET_BITS(var, 18, 2, val) - -#define WMI_UHR_AP_MODE_TUP_ELR_GET(var) WMI_GET_BITS(var, 20, 2) -#define WMI_UHR_AP_MODE_TUP_ELR_SET(var, val) WMI_SET_BITS(var, 20, 2, val) - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_uhr_ap_mode_tuple_enable_disable_update_params */ - A_UINT32 tlv_header; - /* - * WMI_UHR_AP_MODE_TUP_DPS_GET/_NPCA/DBE/DUO/PUO/ELR/PEDCA - * Modes are defined in WMI_UHR_AP_MODE_TUP - * WMI_UHR_AP_MODE_TUP_DPS_SET/ - * similarly for DBE/DPS/DUO/PUO/ELR/PEDCA - */ - union{ - /* - * Bits 0:7 - vdev_id (8 bits) - * Bits 8:31 - mode enable/disable/update bitmap - * (24 bits, using 2 bits for each mode) - * WMI_UHR_AP_MODE_TUP_STATE - * WMI_UHR_MAX_MODES - * Bits 8:9 DPS - * Bits 10:11 NPCA - * Bits 12:13 DUO - * Bits 14:15 PEDCA - * Bits 16:17 DBE - * Bits 18:19 PUO - * Bits 20:21 ELR - * Bits 22:31 reserved - */ - A_UINT32 vdev_id_mode_tuple_enable_disable_update_bits; - struct{ - A_UINT32 vdev_id:8, - mode_tup_dps_enable_disable_update_bits: 2, - mode_tup_npca_enable_disable_update_bits: 2, - mode_tup_duo_enable_disable_update_bits: 2, - mode_tup_pedca_enable_disable_update_bits: 2, - mode_tup_dbe_enable_disable_update_bits: 2, - mode_tup_puo_enable_disable_update_bits: 2, - mode_tup_elr_enable_disable_update_bits: 2, - reserved:10; - }; - }; - /* Add any new required fields below */ -} wmi_uhr_ap_mode_tuple_enable_disable_update_params; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_vdev_uhr_cu_cmd_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* This fixed param TLV will be followed by the below TLVs - * - wmi_uhr_ap_dps_params - * - wmi_uhr_ap_npca_params - * - wmi_uhr_ap_duo_params - * - wmi_uhr_ap_pedca_params - * - wmi_uhr_ap_dbe_params - * - wmi_uhr_ap_ap_puo_params - * - wmi_uhr_ap_elr_reception_params - * - wmi_uhr_ap_mode_tuple_enable_disable_update_params[] - */ -} wmi_vdev_uhr_cu_cmd_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_cmd_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 pdev_id; - /* This fixed param TLV will be followed by the below TLVs - * - wmi_uhr_ap_dps_params[] - * - wmi_uhr_ap_npca_params[] - * - wmi_uhr_ap_duo_params[] - * - wmi_uhr_ap_pedca_params[] - * - wmi_uhr_ap_dbe_params[] - * - wmi_uhr_ap_ap_puo_params[] - * - wmi_uhr_ap_elr_reception_params[] - * - wmi_uhr_ap_mode_tuple_enable_disable_update_params[] - */ -} wmi_pdev_uhr_cu_cmd_fixed_param; - -typedef enum { - WMI_VDEV_UHR_CU_IN_PROGRESS, - WMI_VDEV_UHR_CU_ESTABLISHED, - WMI_VDEV_UHR_CU_SESSION_END, -} wmi_vdev_uhr_cu_state; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_vdev_uhr_cu_status */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* Refer wmi_vdev_uhr_cu_state*/ - A_UINT32 status; -} wmi_vdev_uhr_cu_status; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_pdev_uhr_cu_event_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 pdev_id; - - /* This fixed param TLV will be followed by the below TLVs - * - wmi_vdev_uhr_cu_status[] - */ -} wmi_pdev_uhr_cu_event_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_vdev_channel_hopping_schedule_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /* index of next channel in the channel_list tlvs to visit */ - A_UINT32 next_channel_index; - /* dwell time in TUs to stay on each channel. 1 TU = 1024 usec */ - A_UINT32 dwell_time_tu; - /* Target tsf at which this schedule should start */ - A_UINT32 target_switch_time_tsf; - - /* This fixed param TLV will be followed by the below TLVs - * - A_UINT32 channel_list[num_chan]; // in MHz - * // DEPRECATED - POPULATE WITH ZERO ELEMS. - * // Use channel_param_list instead. - * - wmi_channel_hopping_channel_params channel_param_list[num_chan]; - */ -} wmi_vdev_channel_hopping_schedule_fixed_param; - -typedef enum { - /* Channel is designated for PASSTHRU VDEV */ - WMI_CHANNEL_HOPPING_ROLE_PASSTHRU = 0, - /* Channel is designated for any other interfaces besides PASSTHRU VDEV */ - WMI_CHANNEL_HOPPING_ROLE_NON_PASSTHRU, -} wmi_channel_hopping_role; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_channel_hopping_channel_params */ - A_UINT32 tlv_header; - A_UINT32 chan_mhz; /* in MHz. Valid only when role is PASSTHRU */ - /* bandwidth: - * Holds a wmi_channel_width enum value. - * Valid only when role is PASSTHRU. - */ - A_UINT32 bandwidth; - A_UINT32 role; /* holds wmi_channel_hopping_role enum value */ -} wmi_channel_hopping_channel_params; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_chan_hop_status_report_cmd_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; -} wmi_vdev_get_chan_hop_status_report_cmd_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_chan_hop_slot_status */ - A_UINT32 tlv_header; - A_UINT32 role; /* holds wmi_channel_hopping_role enum value */ - A_UINT32 chan_mhz; - /* - * TSF of the most recent actual frequency transition leading into - * slot. Carried forward for consecutive same-frequency slots. - */ - A_UINT32 channel_switch_tsf; - A_UINT32 channel_start_tsf; /* TSF when this slot's active period began. */ - A_UINT32 channel_end_tsf; /* TSF when this slot's active period ended. */ - /** - * tx_traffic_index = (tx_duration_us / channel_spent_us) * 100 - * Range: 0 - 100 - */ - A_UINT32 tx_traffic_index; - /** - * rx_traffic_index = (rx_duration_us / channel_spent_us) * 100 - * Range: 0 - 100 - */ - A_UINT32 rx_traffic_index; -} wmi_vdev_chan_hop_slot_status; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_chan_hop_status_report_event_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 vdev_id; - /** TSF timestamp of the current channel hopping request */ - A_UINT32 hopping_request_tsf; - /* Index of the current channel in the channel hopping list */ - A_UINT32 current_channel_index; -} wmi_vdev_chan_hop_status_report_event_fixed_param; - -typedef enum { - WMI_SMD_ROAM_CONFIG_ROLE_SERVING_AP = 1, - WMI_SMD_ROAM_CONFIG_ROLE_TARGET_AP, - WMI_SMD_ROAM_CONFIG_ROLE_STA, -} wmi_smd_roam_config_role; - -typedef enum { - WMI_SMD_ROAM_CONFIG_CMD_PREP_REQ = 1, - WMI_SMD_ROAM_CONFIG_CMD_PREP_RESP, - WMI_SMD_ROAM_CONFIG_CMD_EXEC_REQ, - WMI_SMD_ROAM_CONFIG_CMD_EXEC_RESP, - WMI_SMD_ROAM_CONFIG_CMD_DYNAMIC_CONTEXT, - WMI_SMD_ROAM_CONFIG_CMD_TERMINATION, -} wmi_smd_roam_config_cmd_type; - -#define WMI_SMD_ROAM_FLAG_DL_SN_NOT_TRANSFFERED 0x01 -#define WMI_SMD_ROAM_FLAG_UL_SN_NOT_TRANSFFERED 0x02 -#define WMI_SMD_ROAM_FLAG_DISABLE_LINK 0x04 - -#define WMI_SMD_ROAM_PEER_GET_MLSN(dword) \ - WMI_GET_BITS(dword, 0, 16) -#define WMI_SMD_ROAM_PEER_SET_MLSN(dword, value) \ - WMI_SET_BITS(dword, 0, 16, value) - -#define WMI_SMD_ROAM_PEER_GET_OFFSET(dword) \ - WMI_GET_BITS(dword, 16, 16) -#define WMI_SMD_ROAM_PEER_SET_OFFSET(dword, value) \ - WMI_SET_BITS(dword, 16, 16, value) - -typedef struct { - A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_smd_roam_peer_tid_info */ - A_UINT32 tid_num; - union { - A_UINT32 mlsn__offset__word32; - struct { - A_UINT32 mlsn: 16, - offset: 16; - }; - }; - A_UINT32 tx_buffer_size; /* tx block ack window size */ - A_UINT32 rx_buffer_size; /* rx block ack window size */ -} wmi_smd_roam_peer_tid_info; - -#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_GET_ROLE(cmd_flags) WMI_GET_BITS(mlo_flags, 0, 4) -#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_SET_ROLE(cmd_flags, value) WMI_SET_BITS(mlo_flags, 0, 4, value) - -#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_GET_CMD_TYPE(cmd_flags) WMI_GET_BITS(mlo_flags, 4, 8) -#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_SET_CMD_TYPE(cmd_flags, value) WMI_SET_BITS(mlo_flags, 4, 8, value) - -#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_GET_STATUS(cmd_flags) WMI_GET_BITS(mlo_flags, 12, 8) -#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_SET_STATUS(cmd_flags, value) WMI_SET_BITS(mlo_flags, 12, 8, value) - -#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_GET_ROAM_FLAGS(cmd_flags) WMI_GET_BITS(mlo_flags, 20, 8) -#define WMI_SMD_ROAM_CONFIG_CMD_FLAGS_SET_ROAM_FLAGS(cmd_flags, value) WMI_SET_BITS(mlo_flags, 20, 8, value) - -typedef enum { - WMI_SMD_ROAM_CONFIG_CMD_SUCCESS = 0, - WMI_SMD_ROAM_CONFIG_CMD_FAILURE, -} wmi_smd_roam_config_cmd_status; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_smd_roam_config_cmd_fixed_param */ - /** global unique ID identifying vdev */ - A_UINT32 vdev_id; - /** PEER MAC address */ - wmi_mac_addr peer_mac_addr; - union { - A_UINT32 cmd_flags; - struct { - A_UINT32 role :4, /* wmi_smd_config_role */ - cmd_type :8, /* wmi_smd_config_cmd_type */ - status :8, /* wmi_smd_roam_config_cmd_status */ - roam_flags :8, /* WMI_SMD_ROAM_FLAG_* */ - reserved :4; - }; - }; - A_UINT32 dl_drain_time; /* units = milliseconds */ - /* - * Followed by per tid tlv wmi_smd_roam_peer_tid_info[]. - * Present when dynamic context is set. - */ -} wmi_smd_roam_config_cmd_fixed_param; - -#define WMI_SMD_ROAM_CONFIG_EVENT_FLAGS_GET_ROLE(event_flags) WMI_GET_BITS(mlo_flags, 0, 4) -#define WMI_SMD_ROAM_CONFIG_EVENT_FLAGS_SET_ROLE(event_flags, value) WMI_SET_BITS(mlo_flags, 0, 4, value) - -#define WMI_SMD_ROAM_CONFIG_EVENT_FLAGS_GET_CMD_TYPE(event_flags) WMI_GET_BITS(mlo_flags, 4, 8) -#define WMI_SMD_ROAM_CONFIG_EVENT_FLAGS_SET_CMD_TYPE(event_flags, value) WMI_SET_BITS(mlo_flags, 4, 8, value) - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; */ - /** global unique ID identifying vdev */ - A_UINT32 vdev_id; - /** PEER MAC address */ - wmi_mac_addr peer_mac_address; - /* maximum ST Transitory Duration */ - A_UINT32 dl_drain_time; /* units = milliseconds */ - union { - A_UINT32 event_flags; - struct { - A_UINT32 role:4, - cmd_type:8, - unused:20; - }; - }; -} wmi_smd_roam_config_event_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_cmd_fixed_param */ - - /** global unique ID identifying peer */ - A_UINT32 peer_id; - /* - * Following this struct are the TLV's: - * wmi_smd_roam_peer_tid_info smd_roam_peer_tid_info[]; <- TLV per TID - * wmi_peer_create_cmd_fixed_param peer_create_fixed_param; - * wmi_peer_create_mlo_params peer_create_mlo_params[]; - * wmi_peer_assoc_complete_cmd_fixed_param peer_assoc_fixed_param; - * A_UINT8 peer_assoc_peer_legacy_rates[]; - * A_UINT8 peer_assoc_peer_ht_rates[]; - * wmi_vht_rate_set peer_assoc_peer_vht_rates; - * wmi_he_rate_set peer_assoc_peer_he_rates[]; - * wmi_peer_assoc_mlo_params peer_assoc_mlo_params[]; - * wmi_eht_rate_set peer_assoc_peer_eht_rates[]; - * wmi_peer_assoc_mlo_partner_link_params - * peer_assoc_partner_link_params[]; - * wmi_peer_assoc_tid_to_link_map peer_assoc_peer_tid_to_link_map[]; - * wmi_peer_assoc_operating_mode_params - * peer_assoc_operating_mode_params[]; - * wmi_peer_assoc_mgmt_mpduq_params peer_assoc_mgmt_mpduq_params[]; - * wmi_peer_assoc_mgmt_msduq_params peer_assoc_mgmt_msduq_params[]; - * wmi_peer_assoc_hol_msduq_params peer_assoc_hol_mdsuq_params[]; - * wmi_peer_assoc_complete_cmd_fixed_param peer_assoc_v2_fixed_param; - * A_UINT8 peer_assoc_v2_peer_legacy_rates[]; - * A_UINT8 peer_assoc_v2_peer_ht_rates[]; - * wmi_vht_rate_set peer_assoc_v2_peer_vht_rates; - * wmi_he_rate_set peer_assoc_v2_peer_he_rates[]; - * wmi_peer_assoc_mlo_params peer_assoc_v2_mlo_params[]; - * wmi_eht_rate_set peer_assoc_v2_peer_eht_rates[]; - * wmi_peer_assoc_mlo_partner_link_params - * peer_assoc_v2_partner_link_params[]; - * wmi_peer_assoc_tid_to_link_map peer_assoc_v2_peer_tid_to_link_map[]; - * wmi_peer_assoc_operating_mode_params - * peer_assoc_v2_operating_mode_params[]; - * wmi_peer_assoc_mgmt_mpduq_params peer_assoc_v2_mgmt_mpduq_params[]; - * wmi_peer_assoc_mgmt_msduq_params peer_assoc_v2_mgmt_msduq_params[]; - * wmi_peer_assoc_hol_msduq_params peer_assoc_v2_hol_mdsuq_params[]; - * wmi_peer_uhr_npca_cap_params peer_assoc_v2_peer_npca_cap_params[]; - * wmi_peer_create_mlo_params peer_assoc_v2_create_mlo_params[]; - * wmi_peer_assoc_cfp_params peer_assoc_v2_cfp_params; - * wmi_peer_assoc_smd_params peer_assoc_v2_smd_params; - * wmi_vdev_install_key_cmd_fixed_param key_install_fixed_param; - * A_UINT8 key_data[]; - * wmi_uhr_rate_set peer_uhr_rates[]; - * wmi_peer_uhr_npca_op_params npca_op_params[0,1] - */ -} wmi_smd_roam_peer_unified_setup_cmd_fixed_param; - -typedef enum { - WMI_SMD_PEER_SETUP_SUCCESS = 0, - WMI_SMD_PEER_SETUP_FAILURE, -} wmi_smd_peer_setup_status_type; - -typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_smd_roam_peer_unified_setup_complete_event_fixed_param */ - A_UINT32 tlv_header; - /** global unique ID identifying peer */ - A_UINT32 peer_id; - A_UINT32 status; /** wmi_smd_peer_setup_status_type */ -} wmi_smd_roam_peer_unified_setup_complete_event_fixed_param; - -/* ================================================================ */ -/* WMI_PEER_SET_MAPC_PARAMS_CMDID structures */ -/* ================================================================ */ - -/* Scheme enable bitmap — indicates which scheme TLVs are present */ -#define WMI_MAPC_SCHEME_COBF (1 << 0) /* Co-BF */ -#define WMI_MAPC_SCHEME_COSR (1 << 1) /* Co-SR */ -#define WMI_MAPC_SCHEME_COTDMA (1 << 2) /* Co-TDMA */ -#define WMI_MAPC_SCHEME_CORTWT (1 << 3) /* Co-rTWT */ -#define WMI_MAPC_SCHEME_COCR (1 << 4) /* Co-CR */ - -/* - * wmi_peer_set_mapc_params_cmd_fixed_param: - * Identity + routing hint for WMI_PEER_SET_MAPC_PARAMS_CMDID. - * mapc_scheme_enable_bitmap indicates which scheme TLVs follow. - * Sent after WMI_PEER_CREATE_CMDID (peer_type=WMI_PEER_TYPE_MAPC) - * and after each MAPC Negotiation Agreement Establishment/Update. - */ -typedef struct { - A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_peer_set_mapc_params_cmd_fixed_param */ - A_UINT32 vdev_id; - wmi_mac_addr peer_macaddr; - A_UINT32 mapc_scheme_enable_bitmap; /* WMI_MAPC_SCHEME_* bitmask */ -} wmi_peer_set_mapc_params_cmd_fixed_param; - -/* - * wmi_mapc_cmn_params: - * Common MAPC params shared across all schemes. - */ -typedef struct { - A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_mapc_cmn_params */ - - /* peer's advertised MAPC capability bitmap */ - A_UINT32 mapc_capability_bitmap; - - /* APID assigned by local AP to remote C-AP */ - A_UINT32 apid_to_neighbor_peer; - - /* APID assigned by remote C-AP to local AP */ - A_UINT32 apid_from_neighbor_peer; - - /* Vendor Q2Q APID assigned to remote peer */ - A_UINT32 q2q_apid_to_neighbor_peer; - - /* Vendor Q2Q APID assigned by remote peer */ - A_UINT32 q2q_apid_from_neighbor_peer; -} wmi_mapc_cmn_params; - -/* - * wmi_mapc_cotdma_params: mapc_ctdma_profile + mapc_txop_sharing_policy - * Co-TDMA per-peer policy parameters. - */ -typedef struct { - A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_mapc_cotdma_params */ - - /* Channel info — mapc_ctdma_profile */ - A_UINT32 channel_width; /* operating channel width (MHz) */ - A_UINT32 ccfs; /* center channel frequency segment index */ - A_UINT32 bss_color; /* 802.11ax/be BSS color */ - - /* 1 = peer supports RX-driven TXOP return */ - A_UINT32 rx_txop_return_support; - - A_UINT32 disable_subchannel_bitmap; /* subchannels to disable */ - - /* TXOP sharing policy — mapc_txop_sharing_policy */ - A_UINT32 primary_ac; /* primary AC: VO=0 VI=1 BE=2 BK=3 */ - A_UINT32 nbr_ap_prio; /* Cotroller set nbr shared ap prio */ - A_UINT32 latency_sensitive_threshold_us; - A_UINT32 service_start_time; /* TSF-relative service window start (us) */ - A_UINT32 service_interval; /* periodicity (us); 0 = always available */ - A_UINT32 service_end_time; /* TSF-relative service window end (us) */ - A_UINT32 critical_traffic_dur_thresh_us; - A_UINT32 max_shared_txop_dur_us; /* per-AC max shared TXOP */ - A_UINT32 min_shared_txop_dur_us; /* per-AC min TXOP to trigger C-TDMA */ -} wmi_mapc_cotdma_params; - -/* - * Stub structures for future MAPC coordination schemes. - * Included now to reserve TLV slots in WMI_PEER_SET_MAPC_PARAMS_CMDID so that - * the TLV layout remains stable when these schemes are implemented. Host must - * send 0 array entries for each stub; FW ignores them until the feature lands. - */ - -/* Co-SR (Coordinated Spatial Reuse, 802.11bn): allows coordinated BSS-color / - * OBSS_PD threshold negotiation between C-APs to improve spatial reuse. */ -typedef struct { A_UINT32 tlv_header; } wmi_mapc_cosr_params; - -/* Co-BF (Coordinated Beamforming, 802.11bn): enables joint beamforming vector - * coordination between C-APs to suppress inter-BSS interference. */ -typedef struct { A_UINT32 tlv_header; } wmi_mapc_cobf_params; - -/* Co-rTWT (Coordinated restricted-TWT, 802.11bn): allows C-APs to align their - * restricted-TWT service periods to avoid overlapping transmissions. */ -typedef struct { A_UINT32 tlv_header; } wmi_mapc_cortwt_params; - - -typedef enum { - WMI_PDEV_SET_CUMAC_CHIP_ID_SUCCESS = 0, - WMI_PDEV_SET_CUMAC_CHIP_ID_FAILURE, -} wmi_pdev_set_cumac_chip_id_status_type; - -typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_set_cumac_chip_id_cmd_fixed_param */ - A_UINT32 tlv_header; - /** global unique ID identifying pdev */ - A_UINT32 pdev_id; - /** global unique ID identifying chip id of selected CUMAC chip */ - A_UINT32 cumac_chip_id; -} wmi_pdev_set_cumac_chip_id_cmd_fixed_param; - -typedef struct { - /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param */ - A_UINT32 tlv_header; - /** global unique ID identifying pdev */ - A_UINT32 pdev_id; - A_UINT32 status; /** wmi_pdev_set_cumac_chip_id_status_type */ -} wmi_pdev_set_cumac_chip_id_confirmation_event_fixed_param; - - -/* vdev operating param flags */ -#define WMI_VDEV_OPERATING_PARAM_SET_UPDATED_BW 0x1 -#define WMI_VDEV_OPERATING_PARAM_SET_UPDATED_NSS 0x2 -#define WMI_VDEV_OPERATING_PARAM_SET_UPDATED_CHAINS 0x4 - -typedef struct { - A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_current_operating_param_event_fixed_param */ - /* operating_param_flags: holds WMI_VDEV_OPERATING_PARAM_ values */ - A_UINT32 operating_param_flags; - A_UINT32 vdev_id; /* ID of the vdev these data stats are from */ - /* bw: current operating bandwidth (a wmi_channel_width enum value) */ - A_UINT32 bw; - /* Current operating Tx and Rx NSS */ - A_UINT32 tx_nss; - A_UINT32 rx_nss; - /* Current Tx and RX Chains of HW intersected with connection capability */ - A_UINT32 tx_chains; - A_UINT32 rx_chains; -} wmi_vdev_current_operating_param_event_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_cmd_fixed_param */ - /** unique id identifying the request */ - A_UINT32 request_id; -} wmi_get_chipset_logging_stats_cmd_fixed_param; - -typedef struct { - A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_get_chipset_logging_stats_event_fixed_param */ - /** unique id identifying the request */ - A_UINT32 request_id; - /** length in bytes of the chipset log stats data */ - A_UINT32 data_len; - /** - * Following this structure is the TLV: - * A_UINT8 data[]; <-- chipset log stats data, length given by data_len - */ -} wmi_get_chipset_logging_stats_event_fixed_param; - -/* ----------------------------------------------------------------------- - * TLV #1 — Message-level header - * ----------------------------------------------------------------------- */ -typedef struct { - A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_anomaly_report_hdr */ - A_UINT32 pdev_id; /* PDEV ID (common for all entries in batch) */ -} wmi_anomaly_report_hdr; - -/* ----------------------------------------------------------------------- - * Per-Anomaly Context Sub-Structures (all fields A_UINT32 per WMI convention) - * ----------------------------------------------------------------------- */ - -/* - * Context for WMI_ANOMALY_ID_VDEV_DELETE_REQUESTED_BEFORE_STOP - * (ID 0000–0999) - */ -typedef struct { - A_UINT32 vdev_state; /* Internal VDEV state at time of fault */ - A_UINT32 vdev_type; /* VDEV type (AP/STA/IBSS/etc.) */ -} wmi_anomaly_vdev_ctx_t; - -/* - * Context for WMI_ANOMALY_ID_DELETE_VDEV_BEFORE_DELETING_ALL_PEERS - * (ID 1000–1999) - */ -typedef struct { - A_UINT32 peer_count; /* Number of peers still associated */ - /* MAC address of first offending peer (lower 32 bits) */ - A_UINT32 peer_mac_addr_lo; - /* MAC address of first offending peer (upper 16 bits) */ - A_UINT32 peer_mac_addr_hi; - A_UINT32 peer_state; /* Internal peer state at time of fault */ -} wmi_anomaly_peer_ctx_t; - -/* - * Context for WMI_ANOMALY_ID_BEACON_TEMPLATE_SANITY_FAILED - * (ID 2000–2999) - */ -typedef struct { - A_UINT32 bcn_buf_len; /* Beacon buffer length that was received */ - A_UINT32 max_allowed_len; /* Maximum allowed beacon buffer length */ - A_UINT32 ie_offset; /* IE offset at which sanity failed */ - A_UINT32 fail_reason; /* Internal reason code for the failure */ -} wmi_anomaly_beacon_ctx_t; - -/* - * Context for halPhy bucket groups - * (ID 5000–9999) - */ -typedef struct { - A_UINT32 phy_err_code; /* Hardware PHY error code at fault time */ - A_UINT32 chain_mask; /* Active RX/TX chain mask at fault time */ - A_UINT32 cal_step; /* Calibration step index; 0 if not applicable */ - A_UINT32 hw_status; /* Raw hardware status register snapshot */ -} wmi_anomaly_halphy_ctx_t; - -/* - * Context for uCode bucket groups - * (ID 10000–14999) - */ -typedef struct { - A_UINT32 ucode_pc; /* uCode program counter at fault time */ - A_UINT32 sched_state; /* Scheduler state machine value at fault time */ - A_UINT32 txrx_status; /* TX/RX pipeline status register snapshot */ - A_UINT32 watchdog_count; /* Watchdog expiry count since last reset */ -} wmi_anomaly_ucode_ctx_t; - -/* ----------------------------------------------------------------------- - * TLV #2 — Per-Anomaly Entry (ARRAY_STRUC element) - * anomaly_id is the discriminant — tells host which union member is valid. - * ----------------------------------------------------------------------- */ -typedef struct { - A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_anomaly_entry_t */ - A_UINT32 anomaly_id; /* [31:1]=WMI_ANOMALY_ID [0]=type(0=A/1=E) */ - A_UINT32 vdev_id; /* Virtual Device ID (0xFFFFFFFF if N/A) */ - A_UINT32 priority; /* WMI_ANOMALY_PRIORITY */ - A_UINT32 related_cmd_id; /* WMI_CMD_ID (0 if N/A) */ - A_UINT32 reserved[2]; /* for future use when needed */ - union { - wmi_anomaly_vdev_ctx_t vdev; /* ID 0000–0999 */ - wmi_anomaly_peer_ctx_t peer; /* ID 1000–1999 */ - wmi_anomaly_beacon_ctx_t beacon; /* ID 2000–2999 */ - wmi_anomaly_halphy_ctx_t halphy; /* ID 5000–9999 */ - wmi_anomaly_ucode_ctx_t ucode; /* ID 10000–14999 */ - } ctx; - /* NOTE: - * No new fields can be added here - this restriction allows new fields - * to be added to the end of the wmi_anomaly_xxx_ctx_t structs instead. - */ -} wmi_anomaly_entry_t; - - -/* RTT Peer Measurement (Proximity Detection/Ranging) capabilities */ - -/* - * macros to set/get bitfields within - * wmi_rtt_peer_meas_capabilities - */ - -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_REPORT_AP_TSF_GET(flags) WMI_GET_BITS(flags, 0, 1) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_REPORT_AP_TSF_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_RANDOMIZE_MAC_GET(flags) WMI_GET_BITS(flags, 1, 1) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_RANDOMIZE_MAC_SET(flags, value) WMI_SET_BITS(flags, 1, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_SUPPORT_GET(flags) WMI_GET_BITS(flags, 2, 1) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 2, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_CONCURRENT_GET(flags) WMI_GET_BITS(flags, 3, 1) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_CONCURRENT_SET(flags, value) WMI_SET_BITS(flags, 3, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_RANDOM_MAC_CONNECTED_GET(flags) WMI_GET_BITS(flags, 4, 1) -#define WMI_RTT_PEER_MEAS_CAPS_SUPPORT_PD_RANDOM_MAC_CONNECTED_SET(flags, value) WMI_SET_BITS(flags, 4, 1, value) - -#define WMI_RTT_PEER_MEAS_CAPS_PD_MAX_PEERS_ISTA_ROLE_GET(flags) WMI_GET_BITS(flags, 0, 16) -#define WMI_RTT_PEER_MEAS_CAPS_PD_MAX_PEERS_ISTA_ROLE_SET(flags, value) WMI_SET_BITS(flags, 0, 16, value) -#define WMI_RTT_PEER_MEAS_CAPS_PD_MAX_PEERS_RSTA_ROLE_GET(flags) WMI_GET_BITS(flags, 16, 16) -#define WMI_RTT_PEER_MEAS_CAPS_PD_MAX_PEERS_RSTA_ROLE_SET(flags, value) WMI_SET_BITS(flags, 16, 16, value) - -#define WMI_RTT_PEER_MEAS_CAPS_FTM_SUPPORT_GET(flags) WMI_GET_BITS(flags, 0, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_ASAP_SUPPORT_GET(flags) WMI_GET_BITS(flags, 1, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_ASAP_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 1, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_NON_ASAP_SUPPORT_GET(flags) WMI_GET_BITS(flags, 2, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_NON_ASAP_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 2, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_REQ_LCI_SUPPORT_GET(flags) WMI_GET_BITS(flags, 3, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_REQ_LCI_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 3, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_REQ_CIVICLOC_SUPPORT_GET(flags) WMI_GET_BITS(flags, 4, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_REQ_CIVICLOC_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 4, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_TB_RANGING_SUPPORT_GET(flags) WMI_GET_BITS(flags, 5, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_TB_RANGING_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 5, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_NTB_RANGING_SUPPORT_GET(flags) WMI_GET_BITS(flags, 6, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_NTB_RANGING_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 6, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_6GHZ_SUPPORT_GET(flags) WMI_GET_BITS(flags, 7, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_6GHZ_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 7, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_RSTA_ROLE_SUPPORT_GET(flags) WMI_GET_BITS(flags, 8, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_RSTA_ROLE_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 8, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_EDCA_RESPONDER_SUPPORT_GET(flags) WMI_GET_BITS(flags, 9, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_EDCA_RESPONDER_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 9, 1, value) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_RANGE_REPORT_SUPPORT_GET(flags) WMI_GET_BITS(flags, 10, 1) -#define WMI_RTT_PEER_MEAS_CAPS_FTM_RANGE_REPORT_SUPPORT_SET(flags, value) WMI_SET_BITS(flags, 10, 1, value) - -#define WMI_RTT_PEER_MEAS_CAPS_MAX_BURST_EXPONENTS_GET(caps) WMI_GET_BITS(caps, 0, 8) -#define WMI_RTT_PEER_MEAS_CAPS_MAX_BURST_EXPONENTS_SET(caps, value) WMI_SET_BITS(caps, 0, 8, value) -#define WMI_RTT_PEER_MEAS_CAPS_MAX_FTM_PER_BURST_GET(caps) WMI_GET_BITS(caps, 8, 8) -#define WMI_RTT_PEER_MEAS_CAPS_MAX_FTM_PER_BURST_SET(caps, value) WMI_SET_BITS(caps, 8, 8, value) -#define WMI_RTT_PEER_MEAS_CAPS_MAX_TX_ANTENNAS_GET(caps) WMI_GET_BITS(caps, 16, 8) -#define WMI_RTT_PEER_MEAS_CAPS_MAX_TX_ANTENNAS_SET(caps, value) WMI_SET_BITS(caps, 16, 8, value) -#define WMI_RTT_PEER_MEAS_CAPS_MAX_RX_ANTENNAS_GET(caps) WMI_GET_BITS(caps, 24, 8) -#define WMI_RTT_PEER_MEAS_CAPS_MAX_RX_ANTENNAS_SET(caps, value) WMI_SET_BITS(caps, 24, 8, value) - -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_LTF_REP_GET(params) WMI_GET_BITS(params, 0, 3) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_LTF_REP_SET(params, value) WMI_SET_BITS(params, 0, 3, value) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_LTF_REP_GET(params) WMI_GET_BITS(params, 3, 3) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_LTF_REP_SET(params, value) WMI_SET_BITS(params, 3, 3, value) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_LTF_TOTAL_GET(params) WMI_GET_BITS(params, 6, 2) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_LTF_TOTAL_SET(params, value) WMI_SET_BITS(params, 6, 2, value) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_LTF_TOTAL_GET(params) WMI_GET_BITS(params, 8, 2) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_LTF_TOTAL_SET(params, value) WMI_SET_BITS(params, 8, 2, value) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_STS_LE80_GET(params) WMI_GET_BITS(params, 10, 3) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_STS_LE80_SET(params, value) WMI_SET_BITS(params, 10, 3, value) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_STS_GT80_GET(params) WMI_GET_BITS(params, 13, 3) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_RX_STS_GT80_SET(params, value) WMI_SET_BITS(params, 13, 3, value) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_STS_LE80_GET(params) WMI_GET_BITS(params, 16, 3) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_STS_LE80_SET(params, value) WMI_SET_BITS(params, 16, 3, value) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_STS_GT80_GET(params) WMI_GET_BITS(params, 19, 3) -#define WMI_RTT_PEER_MEAS_11AZ_PARAMS_MAX_TX_STS_GT80_SET(params, value) WMI_SET_BITS(params, 19, 3, value) - - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_capabilities */ - A_UINT32 tlv_header; - /** - * Support flag - * Bit 0 : report AP tsf - * Bit 1 : randomize mac address - * Bit 2 : Proximity Detection (PD) support i.e. USD ranging - * Bit 3 : PD concurrent ISTA and RSTA support - * Bit 4 : PD randomize mac address connected state - * Bits 31-5 : Reserved - */ - A_UINT32 support_flag; - A_UINT32 max_peers; - /** - * pd max peers - * Bits 15-0 : pd_max_peers ISTA role - * Bits 31-16 : pd_max_peers RSTA role - */ - A_UINT32 pd_max_peers; - /** - * FTM support flag - * Bit 0 : ftm supported - * Bit 1 : asap mode is supported - * Bit 2 : non-asap mode is supported - * Bit 3 : request lci - * Bit 4 : request civicloc - * Bit 5 : trigger based supported (TB ranging) - * Bit 6 : non-trigger based supported (NTB ranging) - * Bit 7 : 6 Ghz supported - * Bit 8 : Support Rsta role - * Bit 9 : Support edca responder - * Bit 10 : Support range report - * Bits 31-11 : Reserved - */ - A_UINT32 ftm_support_flag; - /** Bitmap of BW supported per wmi_channel_width enum */ - A_UINT32 supported_bw_bitmap; - /** Bitmap of Preambles supported per WMI_RATE_PREAMBLE */ - A_UINT32 supported_preamble_bitmap; - /** - * capabilities - * Bits 7-0 : Max burst exponents - * Bits 15-8 : Max FTM per burst - * Bits 23-16 : Max Tx antennas - * Bits 31-24 : Max Rx antennas - */ - A_UINT32 capabilities; - /** - * ranging 11az parameters - * Bits 2-0 : Max Tx LTF repetition - * Bits 5-3 : Max Rx LTF repetition - * Bits 7-6 : Max Rx LTF total - * Bits 9-8 : Max Tx LTF total - * Bits 12-10 : Max Rx STS LE 80 - * Bits 15-13 : Max Rx STS GT 80 - * Bits 18-16 : Max Tx STS LE 80 - * Bits 21-19 : Max Tx STS GT 80 - * Bits 31-22 : Reserved - */ - A_UINT32 ranging_11az_parameters; - /* Min allowed ranging interval supported by target in EDCA-based ranging, in ms */ - A_UINT32 min_interval_edca_ms; - /* Min allowed ranging interval supported by target in NTB (Non-Trigger Based) ranging, in ms */ - A_UINT32 min_interval_ntb_ms; -} wmi_rtt_peer_meas_capabilities; - -/* - * macros to set/get bitfields within - * wmi_rtt_peer_meas_req_peer_info - */ - -#define WMI_RTT_PEER_MEAS_REQ_FLAG_REPORT_AP_TSF_GET(flags) WMI_GET_BITS(flags, 0, 1) -#define WMI_RTT_PEER_MEAS_REQ_FLAG_REPORT_AP_TSF_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_FLAG_PD_REQUEST_GET(flags) WMI_GET_BITS(flags, 1, 1) -#define WMI_RTT_PEER_MEAS_REQ_FLAG_PD_REQUEST_SET(flags, value) WMI_SET_BITS(flags, 1, 1, value) - -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_FTM_REQUESTED_GET(flags) WMI_GET_BITS(flags, 0, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_FTM_REQUESTED_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_ASAP_MODE_GET(flags) WMI_GET_BITS(flags, 1, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_ASAP_MODE_SET(flags, value) WMI_SET_BITS(flags, 1, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_LCI_REQ_GET(flags) WMI_GET_BITS(flags, 2, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_LCI_REQ_SET(flags, value) WMI_SET_BITS(flags, 2, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_LOC_CIVIC_REQ_GET(flags) WMI_GET_BITS(flags, 3, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_LOC_CIVIC_REQ_SET(flags, value) WMI_SET_BITS(flags, 3, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_TB_RANGING_GET(flags) WMI_GET_BITS(flags, 4, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_TB_RANGING_SET(flags, value) WMI_SET_BITS(flags, 4, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_NTB_RANGING_GET(flags) WMI_GET_BITS(flags, 5, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_NTB_RANGING_SET(flags, value) WMI_SET_BITS(flags, 5, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_I2R_LMR_FEEDBACK_GET(flags) WMI_GET_BITS(flags, 6, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_I2R_LMR_FEEDBACK_SET(flags, value) WMI_SET_BITS(flags, 6, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_RSTA_ROLE_GET(flags) WMI_GET_BITS(flags, 7, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_RSTA_ROLE_SET(flags, value) WMI_SET_BITS(flags, 7, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_RANGE_REPORT_GET(flags) WMI_GET_BITS(flags, 8, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_RANGE_REPORT_SET(flags, value) WMI_SET_BITS(flags, 8, 1, value) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_SUPPRESS_PD_RESULT_GET(flags) WMI_GET_BITS(flags, 9, 1) -#define WMI_RTT_PEER_MEAS_REQ_CTRL_FLAG_SUPPRESS_PD_RESULT_SET(flags, value) WMI_SET_BITS(flags, 9, 1, value) - -#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_NUM_BURST_EXP_GET(info) WMI_GET_BITS(info, 0, 8) -#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_NUM_BURST_EXP_SET(info, value) WMI_SET_BITS(info, 0, 8, value) -#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_BURST_DURATION_GET(info) WMI_GET_BITS(info, 8, 8) -#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_BURST_DURATION_SET(info, value) WMI_SET_BITS(info, 8, 8, value) -#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_FTMS_PER_BURST_GET(info) WMI_GET_BITS(info, 16, 8) -#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_FTMS_PER_BURST_SET(info, value) WMI_SET_BITS(info, 16, 8, value) -#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_FTMR_RETRIES_GET(info) WMI_GET_BITS(info, 24, 8) -#define WMI_RTT_PEER_MEAS_REQ_BURST_INFO_FTMR_RETRIES_SET(info, value) WMI_SET_BITS(info, 24, 8, value) - -#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_NOMINAL_TIME_GET(elem) WMI_GET_BITS(elem, 0, 16) -#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_NOMINAL_TIME_SET(elem, value) WMI_SET_BITS(elem, 0, 16, value) -#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_MEAS_PER_AW_GET(elem) WMI_GET_BITS(elem, 16, 8) -#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_MEAS_PER_AW_SET(elem, value) WMI_SET_BITS(elem, 16, 8, value) -#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_AW_DURATION_GET(elem) WMI_GET_BITS(elem, 24, 8) -#define WMI_RTT_PEER_MEAS_REQ_AW_SUB_ELEM_AW_DURATION_SET(elem, value) WMI_SET_BITS(elem, 24, 8, value) - - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_peer_info */ - A_UINT32 tlv_header; - /** Destination mac address for measurement */ - wmi_mac_addr dest_mac; - /** Channel for ranging */ - wmi_channel channel; - /** - * request_flag - * Bit 0 : Report AP TSF - * Bit 1 : PD request - indicates a peer-to-peer Proximity Detection request - * Bits 31-2 : Reserved - */ - A_UINT32 request_flag; - A_UINT32 preamble; /** see WMI_RATE_PREAMBLE for possible values */ - /** - * Control flag - * Bit 0 : FTM requested - * Bit 1 : Asap mode - * Bit 2 : LCI Req = True/False - * Bit 3 : Location Civic Req = True/False - * Bit 4 : Trigger based (TB ranging) - * Bit 5 : Non-trigger based (NTB ranging) - * Bit 6 : I2R LMR Feedback - * Bit 7 : RSTA (Operate as the RSTA in the measurement) - * Bit 8 : Range Report - * Bit 9 : Suppress PD result - * Bits 31-10 : Reserved - */ - A_UINT32 control_flag; - A_UINT32 burst_period; /* units = 100 ms */ - /** - * Burst Information - * Bits 7-0 : num_burst_exponent - * Bits 15-8 : burst_duration - * units = IEEE 802.11 FTM burst dur encoding (250 us * 2^n) - * Bits 23-16 : ftms_per_burst - * Bits 31-24 : ftmr_retries - */ - A_UINT32 burst_info; - A_UINT32 min_time_between_measurements; /** In units of 100 us */ - A_UINT32 max_time_between_measurements; /** In units of 10 ms. */ - /** - * Availability window sub elements - * Bits 15-0 : nominal_time (in unit of 1 ms) - * Bits 23-16 : meas_per_aw - * Bits 31-24 : aw_duration (in unit of 1 ms) - */ - A_UINT32 availibility_sub_elem; -} wmi_rtt_peer_meas_req_peer_info; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_cmd_fixed_param */ - A_UINT32 tlv_header; - /** Unique request ID */ - A_UINT32 req_id; - A_UINT32 vdev_id; - /** Timeout (in ms) for the whole operation, if zero it means there's no timeout */ - A_UINT32 timeout; - /** Randomized mac address if randomization is enabled */ - wmi_mac_addr random_mac_addr; - /** - * This fixed param TLV will be followed by the below TLVs - * - wmi_rtt_peer_meas_req_peer_info rtt_peer_info[] - */ -} wmi_rtt_peer_meas_req_cmd_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_req_cmd_fixed_param */ - A_UINT32 tlv_header; - /** Cancel all the requests associated with this req_id */ - A_UINT32 req_id; -} wmi_rtt_peer_meas_cancel_meas_cmd_fix_param; - -typedef enum { - WMI_RTT_PEER_MEAS_STATUS_SUCCESS, /* measurement completed successfully */ - WMI_RTT_PEER_MEAS_STATUS_REFUSED, /* measurement was locally refused */ - WMI_RTT_PEER_MEAS_STATUS_TIMEOUT, /* measurement timed out */ - WMI_RTT_PEER_MEAS_STATUS_FAILURE, /* measurement failed */ -} WMI_RTT_PEER_MEAS_STATUS; - -typedef enum { - WMI_RTT_PEER_MEAS_FTM_FAILURE_UNSPECIFIED, /* unspecified failure, not used */ - WMI_RTT_PEER_MEAS_FTM_FAILURE_NO_RESPONSE, /* no response from the FTM responder */ - WMI_RTT_PEER_MEAS_FTM_FAILURE_REJECTED, /* FTM responder rejected measurement */ - WMI_RTT_PEER_MEAS_FTM_FAILURE_WRONG_CHANNEL, /* peer is on a different channel */ - WMI_RTT_PEER_MEAS_FTM_FAILURE_PEER_NOT_CAPABLE, /* peer can't actually do FTM */ - WMI_RTT_PEER_MEAS_FTM_FAILURE_INVALID_TIMESTAMP, /* invalid T1/T4 timestamps received */ - WMI_RTT_PEER_MEAS_FTM_FAILURE_PEER_BUSY, /* peer reports busy, may retry later */ - WMI_RTT_PEER_MEAS_FTM_FAILURE_BAD_CHANGED_PARAMS, /* peer changed params no longer supported */ -} WMI_RTT_PEER_MEAS_FAILURE; - -typedef enum { - WMI_PEER_MEAS_TYPE_INVALID, - WMI_PEER_MEAS_TYPE_FTM, /* Fine Timing Measurement (IEEE 802.11mc / 802.11az) */ - WMI_PEER_MEAS_TYPES, - WMI_PEER_MEAS_MAX = WMI_PEER_MEAS_TYPES - 1, -} WMI_RTT_PEER_MEAS_TYPES; - -typedef enum { - WMI_RTT_GI_UNKNOWN = 0, /* default / not available */ - WMI_RTT_GI_08_US = 1, /* 0.8 µs GI */ - WMI_RTT_GI_16_US = 2, /* 1.6 µs GI (11az ranging common) */ - WMI_RTT_GI_32_US = 3, /* 3.2 µs GI */ - WMI_RTT_GI_ZERO_POWER = 4, /* "zero power GI" (secure LTF behavior) */ -} WMI_RTT_GI_TYPE; - -typedef enum { - WMI_PEER_AUTHORIZE_CLEAR = 0, - WMI_PEER_AUTHORIZE_SECURED_MODE = 1, - WMI_PEER_AUTHORIZE_OPEN_MODE = 2, - WMI_PEER_AUTHORIZE_SW_ENCRYPTION_MODE = 3, -} WMI_PEER_AUTHORIZE_TYPE; - -/* - * macros to set/get bitfields within - * wmi_rtt_peer_meas_report_peer_meas_result_info - */ -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_FINAL_GET(flags) WMI_GET_BITS(flags, 0, 1) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_FINAL_SET(flags, value) WMI_SET_BITS(flags, 0, 1, value) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_TB_RANGING_GET(flags) WMI_GET_BITS(flags, 1, 1) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_TB_RANGING_SET(flags, value) WMI_SET_BITS(flags, 1, 1, value) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_NTB_RANGING_GET(flags) WMI_GET_BITS(flags, 2, 1) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_NTB_RANGING_SET(flags, value) WMI_SET_BITS(flags, 2, 1, value) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_AP_TSF_VALID_GET(flags) WMI_GET_BITS(flags, 3, 1) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_AP_TSF_VALID_SET(flags, value) WMI_SET_BITS(flags, 3, 1, value) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_IS_DELAYED_LMR_GET(flags) WMI_GET_BITS(flags, 4, 1) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_IS_DELAYED_LMR_SET(flags, value) WMI_SET_BITS(flags, 4, 1, value) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_MEAS_TYPE_GET(flags) WMI_GET_BITS(flags, 5, 1) -#define WMI_RTT_PEER_MEAS_REPORT_RESULT_FLAG_MEAS_TYPE_SET(flags, value) WMI_SET_BITS(flags, 5, 1, value) - -#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_BURST_INDEX_GET(info) WMI_GET_BITS(info, 0, 16) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_BURST_INDEX_SET(info, value) WMI_SET_BITS(info, 0, 16, value) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_NUM_BURSTS_EXP_GET(info) WMI_GET_BITS(info, 16, 8) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_NUM_BURSTS_EXP_SET(info, value) WMI_SET_BITS(info, 16, 8, value) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_BUSY_RETRY_TIME_GET(info) WMI_GET_BITS(info, 24, 8) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_INFO_BUSY_RETRY_TIME_SET(info, value) WMI_SET_BITS(info, 24, 8, value) - -#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_BURST_PERIOD_GET(params) WMI_GET_BITS(params, 0, 16) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_BURST_PERIOD_SET(params, value) WMI_SET_BITS(params, 0, 16, value) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_BURST_DURATION_GET(params) WMI_GET_BITS(params, 16, 8) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_BURST_DURATION_SET(params, value) WMI_SET_BITS(params, 16, 8, value) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_FTMS_PER_BURST_GET(params) WMI_GET_BITS(params, 24, 8) -#define WMI_RTT_PEER_MEAS_REPORT_BURST_PARAMS_FTMS_PER_BURST_SET(params, value) WMI_SET_BITS(params, 24, 8, value) - -#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_I2R_REP_GET(params) WMI_GET_BITS(params, 0, 8) -#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_I2R_REP_SET(params, value) WMI_SET_BITS(params, 0, 8, value) -#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_R2I_REP_GET(params) WMI_GET_BITS(params, 8, 8) -#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_R2I_REP_SET(params, value) WMI_SET_BITS(params, 8, 8, value) -#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_I2R_STS_GET(params) WMI_GET_BITS(params, 16, 8) -#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_I2R_STS_SET(params, value) WMI_SET_BITS(params, 16, 8, value) -#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_R2I_STS_GET(params) WMI_GET_BITS(params, 24, 8) -#define WMI_RTT_PEER_MEAS_REPORT_11AZ_PARAMS_MAX_R2I_STS_SET(params, value) WMI_SET_BITS(params, 24, 8, value) - -#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_NOMINAL_TIME_MS_GET(params) WMI_GET_BITS(params, 0, 16) -#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_NOMINAL_TIME_MS_SET(params, value) WMI_SET_BITS(params, 0, 16, value) -#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_MEAS_PER_AW_GET(params) WMI_GET_BITS(params, 16, 8) -#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_MEAS_PER_AW_SET(params, value) WMI_SET_BITS(params, 16, 8, value) -#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_AW_DURATION_GET(params) WMI_GET_BITS(params, 24, 8) -#define WMI_RTT_PEER_MEAS_REPORT_AW_PARAMS_AW_DURATION_SET(params, value) WMI_SET_BITS(params, 24, 8, value) - -#define WMI_RTT_PEER_MEAS_REPORT_CHAN_CODE_BW_GET(code) WMI_GET_BITS(code, 0, 8) -#define WMI_RTT_PEER_MEAS_REPORT_CHAN_CODE_BW_SET(code, value) WMI_SET_BITS(code, 0, 8, value) -#define WMI_RTT_PEER_MEAS_REPORT_CHAN_CODE_PREAMBLE_GET(code) WMI_GET_BITS(code, 8, 8) -#define WMI_RTT_PEER_MEAS_REPORT_CHAN_CODE_PREAMBLE_SET(code, value) WMI_SET_BITS(code, 8, 8, value) - -#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_MCS_IDX_GET(info) WMI_GET_BITS(info, 0, 8) -#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_MCS_IDX_SET(info, value) WMI_SET_BITS(info, 0, 8, value) -#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_NSS_GET(info) WMI_GET_BITS(info, 8, 4) -#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_NSS_SET(info, value) WMI_SET_BITS(info, 8, 4, value) -#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_BW_GET(info) WMI_GET_BITS(info, 12, 4) -#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_BW_SET(info, value) WMI_SET_BITS(info, 12, 4, value) -#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_GI_GET(info) WMI_GET_BITS(info, 16, 8) -#define WMI_RTT_PEER_MEAS_REPORT_RATE_INFO1_GI_SET(info, value) WMI_SET_BITS(info, 16, 8, value) - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_report_peer_meas_result_info */ - A_UINT32 tlv_header; - /** Destination mac address for measurement */ - wmi_mac_addr dest_mac; - /** Measurement status and reason */ - A_UINT32 status; /** refer WMI_RTT_PEER_MEAS_STATUS */ - A_UINT32 ftm_failure_reason; /** refer WMI_RTT_PEER_MEAS_STATUS */ - /** - * Result flag - * Bit 0 : final : 1 => this is last response for this peer/session - * Bit 1 : tb_ranging : 1 => if this is TB ranging - * Bit 2 : ntb_ranging : 1 => if this is NTB ranging - * Bit 3 : ap_tsf_valid : 1 => ap_tsf field is valid - * Bit 4 : is_delayed_lmr : 1 => reported LMR belongs to previous burst - * Bit 5 : meas_type : WMI_PEER_MEAS_TYPES (e.g. FTM) - * Bits 31-6 : Reserved - */ - A_UINT32 result_flag; - /** FTM Burst Counts */ - A_UINT32 num_ftmr_attempts; /** Number of FTM request frames transmitted */ - A_UINT32 num_ftmr_successes; /** Number of FTM request frames ACKed */ - /** - * Burst Info - * Bits 15-0 : burst_index [0..num_bursts-1] - * Bits 23-16 : num_bursts_exp (Negotiated num bursts exponent) - * Bits 31-24 : busy_retry_time (In seconds, if peer was busy) - */ - A_UINT32 burst_info; - /** - * Negotiated/Actual Burst Parameters - * Bits 15-0 : burst_period (In units of 100ms) - * Bits 23-16 : burst_duration (Actual burst duration negotiated) - * Bits 31-24 : ftms_per_burst (Actual FTMs per burst negotiated) - */ - A_UINT32 burst_params; - - /** AP TSF at measurement time (valid if ap_tsf_valid=1) */ - struct { - A_UINT32 ap_tsf_l32; - A_UINT32 ap_tsf_h32; - } ap_tsf; - - /** optional legacy 32-bit TSF when measurement started */ - A_UINT32 meas_start_tsf; - - /** RSSI Information */ - struct { - A_INT32 rssi_avg_dbm; - A_INT32 rssi_spread_db; - } rssi; - - /** RTT statistics (units: picoseconds) */ - struct { - union { - A_INT64 value; /* for use by target only */ - struct { - A_UINT32 value_l32; - A_UINT32 value_h32; - } part; - } rtt_avg_ps; - union { - A_INT64 value; /* for use by target only */ - struct { - A_UINT32 value_l32; - A_UINT32 value_h32; - } part; - } rtt_variance_ps; - union { - A_INT64 value; /* for use by target only */ - struct { - A_UINT32 value_l32; - A_UINT32 value_h32; - } part; - } rtt_spread_ps; - } rtt; - - /** Distance statistics (units: millimeters) */ - struct { - union { - A_INT64 value; /* for use by target only */ - struct { - A_UINT32 value_l32; - A_UINT32 value_h32; - } part; - } dist_avg_mm; - union { - A_INT64 value; /* for use by target only */ - struct { - A_UINT32 value_l32; - A_UINT32 value_h32; - } part; - } dist_variance_mm; - union { - A_INT64 value; /* for use by target only */ - struct { - A_UINT32 value_l32; - A_UINT32 value_h32; - } part; - } dist_spread_mm; - } dist; - - /** - * Negotiated/Actual 11az params - * Bits 7-0 : max_i2r_repetition - * Bits 15-8 : max_r2i_repetition - * Bits 23-16 : max_i2r_sts - * Bits 31-24 : max_r2i_sts - */ - A_UINT32 ftm_11az_params; - A_UINT32 min_time_between_measurements; /** In units of 100 us */ - A_UINT32 max_time_between_measurements; /** In units of 10 ms */ - - /** - * Negotiated/Actual avail windows params - * Bits 15-0 : nominal_time_ms (In units of 1 ms) - * Bits 23-16 : measurements_per_aw - * Bits 31-24 : aw_duration (In units of 1 ms) - */ - A_UINT32 avail_window_params; - - /** - * Negotiated/Actual FTM IE channel code - * Bits 7-0 : chan_bw (refer wmi_channel_width) - * Bits 15-8 : preamble (refer WMI_RATE_PREAMBLE) - * Bits 31-16 : reserved - */ - A_UINT32 ftm_ie_channel_code; - - /** - * Tx/Rx Rate Info - * Bits 7-0 : rateMcsIdx - OFDM/CCK rate code would be as per IEEE standard in the units of 0.5mbps - * - HT/VHT/HE it would be mcs index - * Bits 11-8 : Nss (1*1, 2*2, 3*3, 4*4) - * Bits 15-12 : Rx packet BW (0-20 Mhz, 1 - 40 Mhz, 2 - 80 Mhz, 3 - 160 Mhz, 4 - 320 Mhz) - * Bits 23-16 : gi (refer WMI_RTT_GI_TYPE) - * Bits 31-24 : Reserved - */ - A_UINT32 tx_rate_info_1; - A_UINT32 rx_rate_info_1; - - /** bits 31:0: TX/RX Bit rate in 100kbps */ - A_UINT32 tx_rate_info_2; - A_UINT32 rx_rate_info_2; -} wmi_rtt_peer_meas_report_peer_meas_result_info; - -typedef struct { - /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rtt_peer_meas_report_event_fixed_param */ - A_UINT32 tlv_header; - A_UINT32 req_id; /** Unique Identifier */ - A_UINT32 vdev_id; - /** - * This fixed param TLV will be followed by the below TLVs - * - wmi_rtt_peer_meas_report_peer_meas_result_info peer_meas_info[] - */ -} wmi_rtt_peer_meas_report_event_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_athdiag_read_write_cmd_fixed_param */ - A_UINT32 tlv_header; - /* register offset to read or write using ath diag */ - A_UINT32 offset; - /** - * Number of bytes to read from or write to 'offset'. - * - * For a read: FW returns exactly 'data_length' bytes in the event. - * For a write: Host sends exactly 'data_length' bytes in the data TLV. - */ - A_UINT32 data_length; - /** - * mem_type: - * Indicates the type of memory being accessed. - */ - A_UINT32 mem_type; - /** - * is_write: - * Distinguishes between a read and a write operation. - * - * 0 = READ FW reads 'data_length' bytes from 'offset'. - * No data TLV is appended to this command. - * - * 1 = WRITE FW writes 'data_length' bytes to 'offset'. - * A WMITLV_TAG_ARRAY_BYTE TLV with the write payload - * is appended to this command. - */ - A_UINT32 is_write; -} wmi_athdiag_read_write_cmd_fixed_param; - -typedef struct { - /** TLV tag and len; tag equals - * WMITLV_TAG_STRUC_wmi_athdiag_read_write_event_fixed_param */ - A_UINT32 tlv_header; - /** - * Number of bytes to read from or write to 'offset'. - * - * For a read: FW returns exactly 'data_length' bytes in the event. - * For a write: Host sends exactly 'data_length' bytes in the data TLV. - */ - A_UINT32 data_length; - /** - * status: - * Result of the read or write operation performed by FW. - * - * 0 = Success operation completed without error. - * non-zero = Failure FW-defined error codes. - */ - A_UINT32 status; - /** - * is_write: - * Echoed back from the corresponding WMI_ATHDIAG_READ_WRITE_CMDID. - * - * 0 = READ response data TLV with 'data_length' bytes follows - * (only when status == 0) - * 1 = WRITE response no data TLV appended; check 'status' only - */ - A_UINT32 is_write; - /* - * This fixed_param TLV is followed by the following TLVs: - * - A_UINT8 data[] (WMITLV_TAG_ARRAY_BYTE) - * For READ response (is_write == 0): read data, data_length bytes. - * Present only when status == 0. - * For WRITE response (is_write == 1): not present. - */ -} wmi_athdiag_read_write_event_fixed_param; - - /* ADD NEW DEFS HERE */ diff --git a/drivers/staging/fw-api/fw/wmi_version.h b/drivers/staging/fw-api/fw/wmi_version.h index 4efa48281edb..145e8fcc2aa4 100644 --- a/drivers/staging/fw-api/fw/wmi_version.h +++ b/drivers/staging/fw-api/fw/wmi_version.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2026 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1781 +#define __WMI_REVISION_ 1575 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work diff --git a/drivers/staging/fw-api/hw/fig/v1/HALcomdef.h b/drivers/staging/fw-api/hw/fig/v1/HALcomdef.h deleted file mode 100644 index fd5cc2f41dcb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/HALcomdef.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ -#ifndef HAL_COMDEF_H -#define HAL_COMDEF_H - -#ifndef _ARM_ASM_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "com_dtypes.h" - -#ifndef _BOOL32_DEFINED -typedef unsigned long int bool32; -#define _BOOL32_DEFINED -#endif - -#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF - - #define inp(port) (*((volatile byte *) (port))) - #define inpw(port) (*((volatile word *) (port))) - #define inpdw(port) (*((volatile dword *)(port))) - - #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) - #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) - #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) - -#ifdef __cplusplus -} -#endif - -#endif - -#endif - diff --git a/drivers/staging/fw-api/hw/fig/v1/HALhwio.h b/drivers/staging/fw-api/hw/fig/v1/HALhwio.h deleted file mode 100644 index 53f7d7ef21e5..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/HALhwio.h +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ -#ifndef HAL_HWIO_H -#define HAL_HWIO_H - -#include "HALcomdef.h" - -#define HWIO_BASE_PTR(base) base##_BASE_PTR - -#ifdef __ARMCC_VERSION - #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) -#else - #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) -#endif - -#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) -#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) -#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) -#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) - -#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) -#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) -#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) -#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) -#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) -#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) -#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) - -#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) -#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) -#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) -#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) -#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) -#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) -#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) - -#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) -#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) -#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) -#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) - -#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) -#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) -#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) -#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) - -#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) - -#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) -#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) -#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) -#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) -#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) -#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) -#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) - -#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) - -#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) -#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) -#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) -#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) - -#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) -#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) -#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) -#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) - -#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) - -#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) - -#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) -#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) -#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) -#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) - -#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) -#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) -#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) -#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) -#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) -#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) -#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) - -#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) -#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) -#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) - -#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) - -#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) - -#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) -#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) -#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) -#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) -#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) -#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) -#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) -#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) - -#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) -#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) - -#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN -#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) -#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) -#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) -#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) -#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) -#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) -#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) -#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) -#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) -#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) -#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) -#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) -#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) -#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) -#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) -#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR -#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) -#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) -#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) -#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS -#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) -#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) -#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) -#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS -#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) -#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) -#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) -#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK -#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) -#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK -#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT -#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT -#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow -#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) -#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL - -#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) -#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) -#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) -#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) -#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) -#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) -#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) -#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) -#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) -#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) -#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) -#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) -#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) -#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ - HWIO_##hwiosym##_OUTM(base, mask1, val1); \ - HWIO_##hwiosym##_OUTM(base, mask2, val2); \ - } -#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ - HWIO_##hwiosym##_OUTM(base, mask1, val1); \ - HWIO_##hwiosym##_OUTM(base, mask2, val2); \ - HWIO_##hwiosym##_OUTM(base, mask3, val3); \ - } -#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ - HWIO_##hwiosym##_OUTM(base, mask1, val1); \ - HWIO_##hwiosym##_OUTM(base, mask2, val2); \ - HWIO_##hwiosym##_OUTM(base, mask3, val3); \ - HWIO_##hwiosym##_OUTM(base, mask4, val4); \ - } - -#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) -#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) -#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) -#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) -#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) -#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) -#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) -#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) -#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) -#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) -#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) - -#define HWIO_INTLOCK() -#define HWIO_INTFREE() - -#define __inp(port) (*((volatile uint8 *) (port))) -#define __inpw(port) (*((volatile uint16 *) (port))) -#define __inpdw(port) (*((volatile uint32 *) (port))) -#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) -#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) -#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) - -#ifdef HAL_HWIO_EXTERNAL - -#undef __inp -#undef __inpw -#undef __inpdw -#undef __outp -#undef __outpw -#undef __outpdw - -#define __inp(port) __inp_extern(port) -#define __inpw(port) __inpw_extern(port) -#define __inpdw(port) __inpdw_extern(port) -#define __outp(port, val) __outp_extern(port, val) -#define __outpw(port, val) __outpw_extern(port, val) -#define __outpdw(port, val) __outpdw_extern(port, val) - -extern uint8 __inp_extern ( uint32 nAddr ); -extern uint16 __inpw_extern ( uint32 nAddr ); -extern uint32 __inpdw_extern ( uint32 nAddr ); -extern void __outp_extern ( uint32 nAddr, uint8 nData ); -extern void __outpw_extern ( uint32 nAddr, uint16 nData ); -extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); - -#endif - -#define in_byte(addr) (__inp(addr)) -#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) -#define out_byte(addr, val) __outp(addr,val) -#define out_byte_masked(io, mask, val, shadow) \ - HWIO_INTLOCK(); \ - out_byte( io, shadow); \ - shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ - HWIO_INTFREE() -#define out_byte_masked_ns(io, mask, val, current_reg_content) \ - out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ - ((uint16)((val) & (mask)))) ) - -#define in_word(addr) (__inpw(addr)) -#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) -#define out_word(addr, val) __outpw(addr,val) -#define out_word_masked(io, mask, val, shadow) \ - HWIO_INTLOCK( ); \ - shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ - out_word( io, shadow); \ - HWIO_INTFREE( ) -#define out_word_masked_ns(io, mask, val, current_reg_content) \ - out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ - ((uint16)((val) & (mask)))) ) - -#define in_dword(addr) (__inpdw(addr)) -#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) -#define out_dword(addr, val) __outpdw(addr,val) -#define out_dword_masked(io, mask, val, shadow) \ - HWIO_INTLOCK(); \ - shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ - out_dword( io, shadow); \ - HWIO_INTFREE() -#define out_dword_masked_ns(io, mask, val, current_reg_content) \ - out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ - ((uint32)((val) & (mask)))) ) - -#endif - diff --git a/drivers/staging/fw-api/hw/fig/v1/ack_report.h b/drivers/staging/fw-api/hw/fig/v1/ack_report.h deleted file mode 100644 index e78921b308fd..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/ack_report.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _ACK_REPORT_H_ -#define _ACK_REPORT_H_ - -#define NUM_OF_DWORDS_ACK_REPORT 1 - -struct ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t selfgen_response_reason : 4, - ax_trigger_type : 4, - sr_ppdu : 1, - reserved : 7, - frame_control : 16; -#else - uint32_t frame_control : 16, - reserved : 7, - sr_ppdu : 1, - ax_trigger_type : 4, - selfgen_response_reason : 4; -#endif -}; - -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f - -#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000 -#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4 -#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7 -#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0 - -#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000 -#define ACK_REPORT_SR_PPDU_LSB 8 -#define ACK_REPORT_SR_PPDU_MSB 8 -#define ACK_REPORT_SR_PPDU_MASK 0x00000100 - -#define ACK_REPORT_RESERVED_OFFSET 0x00000000 -#define ACK_REPORT_RESERVED_LSB 9 -#define ACK_REPORT_RESERVED_MSB 15 -#define ACK_REPORT_RESERVED_MASK 0x0000fe00 - -#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 -#define ACK_REPORT_FRAME_CONTROL_LSB 16 -#define ACK_REPORT_FRAME_CONTROL_MSB 31 -#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/boron_top_reg.h b/drivers/staging/fw-api/hw/fig/v1/boron_top_reg.h deleted file mode 100644 index 306398284fe3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/boron_top_reg.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef BORON_TOP_REG_H -#define BORON_TOP_REG_H - -#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C) -#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050) - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/buffer_addr_info.h b/drivers/staging/fw-api/hw/fig/v1/buffer_addr_info.h deleted file mode 100644 index d65375b54715..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/buffer_addr_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _BUFFER_ADDR_INFO_H_ -#define _BUFFER_ADDR_INFO_H_ - -#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 - -struct buffer_addr_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_addr_31_0 : 32; - uint32_t buffer_addr_39_32 : 8, - return_buffer_manager : 4, - sw_buffer_cookie : 20; -#else - uint32_t buffer_addr_31_0 : 32; - uint32_t sw_buffer_cookie : 20, - return_buffer_manager : 4, - buffer_addr_39_32 : 8; -#endif -}; - -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/ce_src_desc.h b/drivers/staging/fw-api/hw/fig/v1/ce_src_desc.h deleted file mode 100644 index 4ecaedcab2a7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/ce_src_desc.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _CE_SRC_DESC_H_ -#define _CE_SRC_DESC_H_ - -#define NUM_OF_DWORDS_CE_SRC_DESC 4 - -struct ce_src_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t src_buffer_low : 32; - uint32_t src_buffer_high : 8, - toeplitz_en : 1, - src_swap : 1, - dest_swap : 1, - gather : 1, - ce_res_0 : 1, - barrier_read : 1, - ce_res_1 : 2, - length : 16; - uint32_t fw_metadata : 16, - ce_res_2 : 16; - uint32_t ce_res_3 : 20, - ring_id : 8, - looping_count : 4; -#else - uint32_t src_buffer_low : 32; - uint32_t length : 16, - ce_res_1 : 2, - barrier_read : 1, - ce_res_0 : 1, - gather : 1, - dest_swap : 1, - src_swap : 1, - toeplitz_en : 1, - src_buffer_high : 8; - uint32_t ce_res_2 : 16, - fw_metadata : 16; - uint32_t looping_count : 4, - ring_id : 8, - ce_res_3 : 20; -#endif -}; - -#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000 -#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0 -#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31 -#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff - -#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff - -#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004 -#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8 -#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8 -#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100 - -#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004 -#define CE_SRC_DESC_SRC_SWAP_LSB 9 -#define CE_SRC_DESC_SRC_SWAP_MSB 9 -#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200 - -#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004 -#define CE_SRC_DESC_DEST_SWAP_LSB 10 -#define CE_SRC_DESC_DEST_SWAP_MSB 10 -#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400 - -#define CE_SRC_DESC_GATHER_OFFSET 0x00000004 -#define CE_SRC_DESC_GATHER_LSB 11 -#define CE_SRC_DESC_GATHER_MSB 11 -#define CE_SRC_DESC_GATHER_MASK 0x00000800 - -#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004 -#define CE_SRC_DESC_CE_RES_0_LSB 12 -#define CE_SRC_DESC_CE_RES_0_MSB 12 -#define CE_SRC_DESC_CE_RES_0_MASK 0x00001000 - -#define CE_SRC_DESC_BARRIER_READ_OFFSET 0x00000004 -#define CE_SRC_DESC_BARRIER_READ_LSB 13 -#define CE_SRC_DESC_BARRIER_READ_MSB 13 -#define CE_SRC_DESC_BARRIER_READ_MASK 0x00002000 - -#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000004 -#define CE_SRC_DESC_CE_RES_1_LSB 14 -#define CE_SRC_DESC_CE_RES_1_MSB 15 -#define CE_SRC_DESC_CE_RES_1_MASK 0x0000c000 - -#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004 -#define CE_SRC_DESC_LENGTH_LSB 16 -#define CE_SRC_DESC_LENGTH_MSB 31 -#define CE_SRC_DESC_LENGTH_MASK 0xffff0000 - -#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008 -#define CE_SRC_DESC_FW_METADATA_LSB 0 -#define CE_SRC_DESC_FW_METADATA_MSB 15 -#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff - -#define CE_SRC_DESC_CE_RES_2_OFFSET 0x00000008 -#define CE_SRC_DESC_CE_RES_2_LSB 16 -#define CE_SRC_DESC_CE_RES_2_MSB 31 -#define CE_SRC_DESC_CE_RES_2_MASK 0xffff0000 - -#define CE_SRC_DESC_CE_RES_3_OFFSET 0x0000000c -#define CE_SRC_DESC_CE_RES_3_LSB 0 -#define CE_SRC_DESC_CE_RES_3_MSB 19 -#define CE_SRC_DESC_CE_RES_3_MASK 0x000fffff - -#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c -#define CE_SRC_DESC_RING_ID_LSB 20 -#define CE_SRC_DESC_RING_ID_MSB 27 -#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000 - -#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c -#define CE_SRC_DESC_LOOPING_COUNT_LSB 28 -#define CE_SRC_DESC_LOOPING_COUNT_MSB 31 -#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/ce_stat_desc.h b/drivers/staging/fw-api/hw/fig/v1/ce_stat_desc.h deleted file mode 100644 index 0b9f9a221215..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/ce_stat_desc.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _CE_STAT_DESC_H_ -#define _CE_STAT_DESC_H_ - -#define NUM_OF_DWORDS_CE_STAT_DESC 4 - -struct ce_stat_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ce_res_5 : 8, - toeplitz_en : 1, - src_swap : 1, - dest_swap : 1, - gather : 1, - barrier_read : 1, - ce_res_6 : 3, - length : 16; - uint32_t toeplitz_hash_0 : 32; - uint32_t toeplitz_hash_1 : 32; - uint32_t fw_metadata : 16, - ce_res_7 : 4, - ring_id : 8, - looping_count : 4; -#else - uint32_t length : 16, - ce_res_6 : 3, - barrier_read : 1, - gather : 1, - dest_swap : 1, - src_swap : 1, - toeplitz_en : 1, - ce_res_5 : 8; - uint32_t toeplitz_hash_0 : 32; - uint32_t toeplitz_hash_1 : 32; - uint32_t looping_count : 4, - ring_id : 8, - ce_res_7 : 4, - fw_metadata : 16; -#endif -}; - -#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000 -#define CE_STAT_DESC_CE_RES_5_LSB 0 -#define CE_STAT_DESC_CE_RES_5_MSB 7 -#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff - -#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000 -#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8 -#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8 -#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100 - -#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000 -#define CE_STAT_DESC_SRC_SWAP_LSB 9 -#define CE_STAT_DESC_SRC_SWAP_MSB 9 -#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200 - -#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000 -#define CE_STAT_DESC_DEST_SWAP_LSB 10 -#define CE_STAT_DESC_DEST_SWAP_MSB 10 -#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400 - -#define CE_STAT_DESC_GATHER_OFFSET 0x00000000 -#define CE_STAT_DESC_GATHER_LSB 11 -#define CE_STAT_DESC_GATHER_MSB 11 -#define CE_STAT_DESC_GATHER_MASK 0x00000800 - -#define CE_STAT_DESC_BARRIER_READ_OFFSET 0x00000000 -#define CE_STAT_DESC_BARRIER_READ_LSB 12 -#define CE_STAT_DESC_BARRIER_READ_MSB 12 -#define CE_STAT_DESC_BARRIER_READ_MASK 0x00001000 - -#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000 -#define CE_STAT_DESC_CE_RES_6_LSB 13 -#define CE_STAT_DESC_CE_RES_6_MSB 15 -#define CE_STAT_DESC_CE_RES_6_MASK 0x0000e000 - -#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000 -#define CE_STAT_DESC_LENGTH_LSB 16 -#define CE_STAT_DESC_LENGTH_MSB 31 -#define CE_STAT_DESC_LENGTH_MASK 0xffff0000 - -#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff - -#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff - -#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c -#define CE_STAT_DESC_FW_METADATA_LSB 0 -#define CE_STAT_DESC_FW_METADATA_MSB 15 -#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff - -#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c -#define CE_STAT_DESC_CE_RES_7_LSB 16 -#define CE_STAT_DESC_CE_RES_7_MSB 19 -#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000 - -#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c -#define CE_STAT_DESC_RING_ID_LSB 20 -#define CE_STAT_DESC_RING_ID_MSB 27 -#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000 - -#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c -#define CE_STAT_DESC_LOOPING_COUNT_LSB 28 -#define CE_STAT_DESC_LOOPING_COUNT_MSB 31 -#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/coex_rx_status.h b/drivers/staging/fw-api/hw/fig/v1/coex_rx_status.h deleted file mode 100644 index 7d9c6b4d2057..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/coex_rx_status.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_RX_STATUS_H_ -#define _COEX_RX_STATUS_H_ - -#define NUM_OF_DWORDS_COEX_RX_STATUS 2 - -#define NUM_OF_QWORDS_COEX_RX_STATUS 1 - -struct coex_rx_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_mac_frame_status : 2, - rx_with_tx_response : 1, - rx_rate : 5, - rx_bw : 3, - single_mpdu : 1, - filter_status : 1, - ampdu : 1, - directed : 1, - reserved_0 : 1, - rx_nss : 3, - rx_rssi : 8, - rx_type : 3, - retry_bit_setting : 1, - more_data_bit_setting : 1; - uint32_t remain_rx_packet_time : 16, - rx_remaining_fes_time : 16; -#else - uint32_t more_data_bit_setting : 1, - retry_bit_setting : 1, - rx_type : 3, - rx_rssi : 8, - rx_nss : 3, - reserved_0 : 1, - directed : 1, - ampdu : 1, - filter_status : 1, - single_mpdu : 1, - rx_bw : 3, - rx_rate : 5, - rx_with_tx_response : 1, - rx_mac_frame_status : 2; - uint32_t rx_remaining_fes_time : 16, - remain_rx_packet_time : 16; -#endif -}; - -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003 - -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004 - -#define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_RATE_LSB 3 -#define COEX_RX_STATUS_RX_RATE_MSB 7 -#define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8 - -#define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_BW_LSB 8 -#define COEX_RX_STATUS_RX_BW_MSB 10 -#define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700 - -#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 -#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 -#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800 - -#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_FILTER_STATUS_LSB 12 -#define COEX_RX_STATUS_FILTER_STATUS_MSB 12 -#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000 - -#define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_AMPDU_LSB 13 -#define COEX_RX_STATUS_AMPDU_MSB 13 -#define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000 - -#define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_DIRECTED_LSB 14 -#define COEX_RX_STATUS_DIRECTED_MSB 14 -#define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000 - -#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RESERVED_0_LSB 15 -#define COEX_RX_STATUS_RESERVED_0_MSB 15 -#define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000 - -#define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_NSS_LSB 16 -#define COEX_RX_STATUS_RX_NSS_MSB 18 -#define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000 - -#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_RSSI_LSB 19 -#define COEX_RX_STATUS_RX_RSSI_MSB 26 -#define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000 - -#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_TYPE_LSB 27 -#define COEX_RX_STATUS_RX_TYPE_MSB 29 -#define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000 - -#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000 - -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000 - -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000 - -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/coex_tx_req.h b/drivers/staging/fw-api/hw/fig/v1/coex_tx_req.h deleted file mode 100644 index ed5b4c57bfd8..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/coex_tx_req.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_TX_REQ_H_ -#define _COEX_TX_REQ_H_ - -#define NUM_OF_DWORDS_COEX_TX_REQ 6 - -#define NUM_OF_QWORDS_COEX_TX_REQ 3 - -struct coex_tx_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_pwr : 8, - min_tx_pwr : 8, - nss : 3, - tx_chain_mask : 8, - bw : 3, - reserved_0 : 2; - uint32_t alt_tx_pwr : 8, - alt_min_tx_pwr : 8, - alt_nss : 3, - alt_tx_chain_mask : 8, - alt_bw : 3, - reserved_1 : 2; - uint32_t tx_pwr_1 : 8, - alt_tx_pwr_1 : 8, - wlan_request_duration : 16; - uint32_t wlan_pkt_type : 4, - coex_tx_reason : 2, - response_frame_type : 5, - wlan_low_priority_slicing_allowed : 1, - wlan_high_priority_slicing_allowed : 1, - sch_tx_burst_ongoing : 1, - coex_tx_priority : 4, - blackout_details_en : 1, - blackout_peek_duration : 8, - reserved_3a : 5; - uint32_t frequency_channel_bonding_mask : 16, - num_blackout_windows : 8, - reserved_4a : 8; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0 : 2, - bw : 3, - tx_chain_mask : 8, - nss : 3, - min_tx_pwr : 8, - tx_pwr : 8; - uint32_t reserved_1 : 2, - alt_bw : 3, - alt_tx_chain_mask : 8, - alt_nss : 3, - alt_min_tx_pwr : 8, - alt_tx_pwr : 8; - uint32_t wlan_request_duration : 16, - alt_tx_pwr_1 : 8, - tx_pwr_1 : 8; - uint32_t reserved_3a : 5, - blackout_peek_duration : 8, - blackout_details_en : 1, - coex_tx_priority : 4, - sch_tx_burst_ongoing : 1, - wlan_high_priority_slicing_allowed : 1, - wlan_low_priority_slicing_allowed : 1, - response_frame_type : 5, - coex_tx_reason : 2, - wlan_pkt_type : 4; - uint32_t reserved_4a : 8, - num_blackout_windows : 8, - frequency_channel_bonding_mask : 16; - uint32_t tlv64_padding : 32; -#endif -}; - -#define COEX_TX_REQ_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_TX_PWR_LSB 0 -#define COEX_TX_REQ_TX_PWR_MSB 7 -#define COEX_TX_REQ_TX_PWR_MASK 0x00000000000000ff - -#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_MIN_TX_PWR_LSB 8 -#define COEX_TX_REQ_MIN_TX_PWR_MSB 15 -#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define COEX_TX_REQ_NSS_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_NSS_LSB 16 -#define COEX_TX_REQ_NSS_MSB 18 -#define COEX_TX_REQ_NSS_MASK 0x0000000000070000 - -#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19 -#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26 -#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define COEX_TX_REQ_BW_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_BW_LSB 27 -#define COEX_TX_REQ_BW_MSB 29 -#define COEX_TX_REQ_BW_MASK 0x0000000038000000 - -#define COEX_TX_REQ_RESERVED_0_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_RESERVED_0_LSB 30 -#define COEX_TX_REQ_RESERVED_0_MSB 31 -#define COEX_TX_REQ_RESERVED_0_MASK 0x00000000c0000000 - -#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_TX_PWR_LSB 32 -#define COEX_TX_REQ_ALT_TX_PWR_MSB 39 -#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 40 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 47 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define COEX_TX_REQ_ALT_NSS_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_NSS_LSB 48 -#define COEX_TX_REQ_ALT_NSS_MSB 50 -#define COEX_TX_REQ_ALT_NSS_MASK 0x0007000000000000 - -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 51 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 58 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define COEX_TX_REQ_ALT_BW_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_BW_LSB 59 -#define COEX_TX_REQ_ALT_BW_MSB 61 -#define COEX_TX_REQ_ALT_BW_MASK 0x3800000000000000 - -#define COEX_TX_REQ_RESERVED_1_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_RESERVED_1_LSB 62 -#define COEX_TX_REQ_RESERVED_1_MSB 63 -#define COEX_TX_REQ_RESERVED_1_MASK 0xc000000000000000 - -#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_TX_PWR_1_LSB 0 -#define COEX_TX_REQ_TX_PWR_1_MSB 7 -#define COEX_TX_REQ_TX_PWR_1_MASK 0x00000000000000ff - -#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8 -#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15 -#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x000000000000ff00 - -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0x00000000ffff0000 - -#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 32 -#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 35 -#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f00000000 - -#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_COEX_TX_REASON_LSB 36 -#define COEX_TX_REQ_COEX_TX_REASON_MSB 37 -#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x0000003000000000 - -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 38 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 42 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c000000000 - -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 43 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 43 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x0000080000000000 - -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 44 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 44 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x0000100000000000 - -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 45 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 45 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x0000200000000000 - -#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 46 -#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 49 -#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c00000000000 - -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_LSB 50 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MSB 50 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MASK 0x0004000000000000 - -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_LSB 51 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MSB 58 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MASK 0x07f8000000000000 - -#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_RESERVED_3A_LSB 59 -#define COEX_TX_REQ_RESERVED_3A_MSB 63 -#define COEX_TX_REQ_RESERVED_3A_MASK 0xf800000000000000 - -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_LSB 0 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MSB 15 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MASK 0x000000000000ffff - -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_LSB 16 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MSB 23 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MASK 0x0000000000ff0000 - -#define COEX_TX_REQ_RESERVED_4A_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_RESERVED_4A_LSB 24 -#define COEX_TX_REQ_RESERVED_4A_MSB 31 -#define COEX_TX_REQ_RESERVED_4A_MASK 0x00000000ff000000 - -#define COEX_TX_REQ_TLV64_PADDING_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_TLV64_PADDING_LSB 32 -#define COEX_TX_REQ_TLV64_PADDING_MSB 63 -#define COEX_TX_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/coex_tx_status.h b/drivers/staging/fw-api/hw/fig/v1/coex_tx_status.h deleted file mode 100644 index c47c29c2a5ba..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/coex_tx_status.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_TX_STATUS_H_ -#define _COEX_TX_STATUS_H_ - -#define NUM_OF_DWORDS_COEX_TX_STATUS 4 - -#define NUM_OF_QWORDS_COEX_TX_STATUS 2 - -struct coex_tx_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 7, - tx_bw : 3, - tx_status_reason : 3, - tx_wait_ack : 1, - fes_tx_is_gen_frame : 1, - sch_tx_burst_ongoing : 1, - current_tx_duration : 16; - uint32_t next_rx_active_time : 16, - remaining_fes_time : 16; - uint32_t tx_antenna_mask : 8, - shared_ant_tx_pwr : 8, - other_ant_tx_pwr : 8, - reserved_2 : 8; - uint32_t tlv64_padding : 32; -#else - uint32_t current_tx_duration : 16, - sch_tx_burst_ongoing : 1, - fes_tx_is_gen_frame : 1, - tx_wait_ack : 1, - tx_status_reason : 3, - tx_bw : 3, - reserved_0a : 7; - uint32_t remaining_fes_time : 16, - next_rx_active_time : 16; - uint32_t reserved_2 : 8, - other_ant_tx_pwr : 8, - shared_ant_tx_pwr : 8, - tx_antenna_mask : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_RESERVED_0A_LSB 0 -#define COEX_TX_STATUS_RESERVED_0A_MSB 6 -#define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f - -#define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_BW_LSB 7 -#define COEX_TX_STATUS_TX_BW_MSB 9 -#define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380 - -#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10 -#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12 -#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00 - -#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13 -#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13 -#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000 - -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000 - -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000 - -#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000 - -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000 - -#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48 -#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63 -#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000 - -#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff - -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00 - -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000 - -#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_RESERVED_2_LSB 24 -#define COEX_TX_STATUS_RESERVED_2_MSB 31 -#define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000 - -#define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_TLV64_PADDING_LSB 32 -#define COEX_TX_STATUS_TLV64_PADDING_MSB 63 -#define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/com_dtypes.h b/drivers/staging/fw-api/hw/fig/v1/com_dtypes.h deleted file mode 100644 index a122ca419081..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/com_dtypes.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ -#ifndef COM_DTYPES_H -#define COM_DTYPES_H - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef T_WINNT - #ifndef WIN32 - #define WIN32 - #endif - #include -#endif - -#ifdef TRUE -#undef TRUE -#endif - -#ifdef FALSE -#undef FALSE -#endif - -#define TRUE 1 -#define FALSE 0 - -#define ON 1 -#define OFF 0 - -#ifndef NULL - #define NULL 0 -#endif - -#ifndef _ARM_ASM_ -#ifndef _BOOLEAN_DEFINED - -typedef unsigned char boolean; -#define _BOOLEAN_DEFINED -#endif - -#if defined(DALSTDDEF_H) -#define _BOOLEAN_DEFINED -#define _UINT32_DEFINED -#define _UINT16_DEFINED -#define _UINT8_DEFINED -#define _INT32_DEFINED -#define _INT16_DEFINED -#define _INT8_DEFINED -#define _UINT64_DEFINED -#define _INT64_DEFINED -#define _BYTE_DEFINED -#endif - -#ifndef _UINT32_DEFINED - -typedef unsigned int uint32; -#define _UINT32_DEFINED -#endif - -#ifndef _UINT16_DEFINED - -typedef unsigned short uint16; -#define _UINT16_DEFINED -#endif - -#ifndef _UINT8_DEFINED - -typedef unsigned char uint8; -#define _UINT8_DEFINED -#endif - -#ifndef _INT32_DEFINED - -typedef signed int int32; -#define _INT32_DEFINED -#endif - -#ifndef _INT16_DEFINED - -typedef signed short int16; -#define _INT16_DEFINED -#endif - -#ifndef _INT8_DEFINED - -typedef signed char int8; -#define _INT8_DEFINED -#endif - -#ifndef _BYTE_DEFINED - -typedef unsigned char byte; -#define _BYTE_DEFINED -#endif - -typedef unsigned short word; - -typedef unsigned long dword; - -typedef unsigned char uint1; - -typedef unsigned short uint2; - -typedef unsigned long uint4; - -typedef signed char int1; - -typedef signed short int2; - -typedef long int int4; - -typedef signed long sint31; - -typedef signed short sint15; - -typedef signed char sint7; - -typedef uint16 UWord16 ; -typedef uint32 UWord32 ; -typedef int32 Word32 ; -typedef int16 Word16 ; -typedef uint8 UWord8 ; -typedef int8 Word8 ; -typedef int32 Vect32 ; - -#if (! defined T_WINNT) && (! defined __GNUC__) - - #ifndef _INT64_DEFINED - - typedef long long int64; - #define _INT64_DEFINED - #endif - #ifndef _UINT64_DEFINED - - typedef unsigned long long uint64; - #define _UINT64_DEFINED - #endif -#else - - #if (defined __GNUC__) - #ifndef _INT64_DEFINED - typedef long long int64; - #define _INT64_DEFINED - #endif - #ifndef _UINT64_DEFINED - typedef unsigned long long uint64; - #define _UINT64_DEFINED - #endif - #else - typedef __int64 int64; - #ifndef _UINT64_DEFINED - typedef unsigned __int64 uint64; - #define _UINT64_DEFINED - #endif - #endif -#endif - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_mu_mimo_info.h b/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_mu_mimo_info.h deleted file mode 100644 index c9e20d75e648..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_mu_mimo_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_ -#define _EHT_SIG_USR_MU_MIMO_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2 - -struct eht_sig_usr_mu_mimo_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - sta_coding : 1, - sta_spatial_config : 6, - reserved_0a : 1, - rx_integrity_check_passed : 1, - subband80_cc_mask : 8; - uint32_t user_order_subband80_0 : 8, - user_order_subband80_1 : 8, - user_order_subband80_2 : 8, - user_order_subband80_3 : 8; -#else - uint32_t subband80_cc_mask : 8, - rx_integrity_check_passed : 1, - reserved_0a : 1, - sta_spatial_config : 6, - sta_coding : 1, - sta_mcs : 4, - sta_id : 11; - uint32_t user_order_subband80_3 : 8, - user_order_subband80_2 : 8, - user_order_subband80_1 : 8, - user_order_subband80_0 : 8; -#endif -}; - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000 - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000 - -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000 - -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 - -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_ofdma_info.h b/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_ofdma_info.h deleted file mode 100644 index f2520cccfde9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_ofdma_info.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_OFDMA_INFO_H_ -#define _EHT_SIG_USR_OFDMA_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2 - -struct eht_sig_usr_ofdma_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - validate_0a : 1, - nss : 4, - txbf : 1, - sta_coding : 1, - reserved_0b : 1, - rx_integrity_check_passed : 1, - subband80_cc_mask : 8; - uint32_t user_order_subband80_0 : 8, - user_order_subband80_1 : 8, - user_order_subband80_2 : 8, - user_order_subband80_3 : 8; -#else - uint32_t subband80_cc_mask : 8, - rx_integrity_check_passed : 1, - reserved_0b : 1, - sta_coding : 1, - txbf : 1, - nss : 4, - validate_0a : 1, - sta_mcs : 4, - sta_id : 11; - uint32_t user_order_subband80_3 : 8, - user_order_subband80_2 : 8, - user_order_subband80_1 : 8, - user_order_subband80_0 : 8; -#endif -}; - -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000 - -#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16 -#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19 -#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000 - -#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000 - -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000 - -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000 - -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 - -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_su_info.h b/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_su_info.h deleted file mode 100644 index 208cb4de0539..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/eht_sig_usr_su_info.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_SU_INFO_H_ -#define _EHT_SIG_USR_SU_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1 - -struct eht_sig_usr_su_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - validate_0a : 1, - nss : 4, - txbf : 1, - sta_coding : 1, - reserved_0b : 9, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0b : 9, - sta_coding : 1, - txbf : 1, - nss : 4, - validate_0a : 1, - sta_mcs : 4, - sta_id : 11; -#endif -}; - -#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000 - -#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_NSS_LSB 16 -#define EHT_SIG_USR_SU_INFO_NSS_MSB 19 -#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000 - -#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20 -#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20 -#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000 - -#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21 -#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21 -#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000 - -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000 - -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/expected_response.h b/drivers/staging/fw-api/hw/fig/v1/expected_response.h deleted file mode 100644 index b3ec83ceccf8..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/expected_response.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EXPECTED_RESPONSE_H_ -#define _EXPECTED_RESPONSE_H_ - -#define NUM_OF_DWORDS_EXPECTED_RESPONSE 6 - -#define NUM_OF_QWORDS_EXPECTED_RESPONSE 3 - -struct expected_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_ad2_31_0 : 32; - uint32_t tx_ad2_47_32 : 16, - expected_response_type : 5, - response_to_response : 3, - su_ba_user_number : 1, - response_info_part2_required : 1, - transmitted_bssid_check_en : 1, - eht___reserved_g_0022_ndp_expected : 1, - reserved_1 : 4; - uint32_t ndp_sta_partial_aid_2_8_0 : 11, - reserved_2 : 10, - ndp_sta_partial_aid1_8_0 : 11; - uint32_t ast_index : 16, - capture_ack_ba_sounding : 1, - capture_sounding_1str_20mhz : 1, - capture_sounding_1str_40mhz : 1, - capture_sounding_1str_80mhz : 1, - capture_sounding_1str_160mhz : 1, - capture_sounding_1str_240mhz : 1, - capture_sounding_1str_320mhz : 1, - reserved_3a : 9; - uint32_t fcs : 9, - expect_rx_with_blackout_details : 1, - crc : 4, - scrambler_seed : 7, - reserved_4b : 11; - uint32_t tlv64_padding : 32; -#else - uint32_t tx_ad2_31_0 : 32; - uint32_t reserved_1 : 4, - eht___reserved_g_0022_ndp_expected : 1, - transmitted_bssid_check_en : 1, - response_info_part2_required : 1, - su_ba_user_number : 1, - response_to_response : 3, - expected_response_type : 5, - tx_ad2_47_32 : 16; - uint32_t ndp_sta_partial_aid1_8_0 : 11, - reserved_2 : 10, - ndp_sta_partial_aid_2_8_0 : 11; - uint32_t reserved_3a : 9, - capture_sounding_1str_320mhz : 1, - capture_sounding_1str_240mhz : 1, - capture_sounding_1str_160mhz : 1, - capture_sounding_1str_80mhz : 1, - capture_sounding_1str_40mhz : 1, - capture_sounding_1str_20mhz : 1, - capture_ack_ba_sounding : 1, - ast_index : 16; - uint32_t reserved_4b : 11, - scrambler_seed : 7, - crc : 4, - expect_rx_with_blackout_details : 1, - fcs : 9; - uint32_t tlv64_padding : 32; -#endif -}; - -#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 -#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 -#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff - -#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32 -#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47 -#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000 - -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000 - -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000 - -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000 - -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000 - -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000 - -#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESERVED_1_LSB 60 -#define EXPECTED_RESPONSE_RESERVED_1_MSB 63 -#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf000000000000000 - -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff - -#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_RESERVED_2_LSB 11 -#define EXPECTED_RESPONSE_RESERVED_2_MSB 20 -#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800 - -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000 - -#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_AST_INDEX_LSB 32 -#define EXPECTED_RESPONSE_AST_INDEX_MSB 47 -#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000 - -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000 - -#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_RESERVED_3A_LSB 55 -#define EXPECTED_RESPONSE_RESERVED_3A_MSB 63 -#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000 - -#define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_FCS_LSB 0 -#define EXPECTED_RESPONSE_FCS_MSB 8 -#define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff - -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB 9 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB 9 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK 0x0000000000000200 - -#define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_CRC_LSB 10 -#define EXPECTED_RESPONSE_CRC_MSB 13 -#define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00 - -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000 - -#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 -#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 -#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000 - -#define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32 -#define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63 -#define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/he_sig_a_mu_dl_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_a_mu_dl_info.h deleted file mode 100644 index 84571eb65d3b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/he_sig_a_mu_dl_info.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_MU_DL_INFO_H_ -#define _HE_SIG_A_MU_DL_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 - -struct he_sig_a_mu_dl_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dl_ul_flag : 1, - mcs_of_sig_b : 3, - dcm_of_sig_b : 1, - bss_color_id : 6, - spatial_reuse : 4, - transmit_bw : 3, - num_sig_b_symbols : 4, - comp_mode_sig_b : 1, - cp_ltf_size : 2, - doppler_indication : 1, - reserved_0a : 6; - uint32_t txop_duration : 7, - reserved_1a : 1, - num_ltf_symbols : 3, - ldpc_extra_symbol : 1, - stbc : 1, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - crc : 4, - tail : 6, - reserved_1b : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0a : 6, - doppler_indication : 1, - cp_ltf_size : 2, - comp_mode_sig_b : 1, - num_sig_b_symbols : 4, - transmit_bw : 3, - spatial_reuse : 4, - bss_color_id : 6, - dcm_of_sig_b : 1, - mcs_of_sig_b : 3, - dl_ul_flag : 1; - uint32_t rx_integrity_check_passed : 1, - reserved_1b : 5, - tail : 6, - crc : 4, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - stbc : 1, - ldpc_extra_symbol : 1, - num_ltf_symbols : 3, - reserved_1a : 1, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001 - -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e - -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010 - -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0 - -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800 - -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000 - -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 - -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000 - -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000 - -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000 - -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000 - -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080 - -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700 - -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800 - -#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12 -#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12 -#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000 - -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 - -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 - -#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16 -#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19 -#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20 -#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25 -#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000 - -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/he_sig_a_mu_ul_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_a_mu_ul_info.h deleted file mode 100644 index e2d0ad73a66c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/he_sig_a_mu_ul_info.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_MU_UL_INFO_H_ -#define _HE_SIG_A_MU_UL_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 - -struct he_sig_a_mu_ul_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t format_indication : 1, - bss_color_id : 6, - spatial_reuse : 16, - reserved_0a : 1, - transmit_bw : 2, - reserved_0b : 6; - uint32_t txop_duration : 7, - reserved_1a : 9, - crc : 4, - tail : 6, - reserved_1b : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0b : 6, - transmit_bw : 2, - reserved_0a : 1, - spatial_reuse : 16, - bss_color_id : 6, - format_indication : 1; - uint32_t rx_integrity_check_passed : 1, - reserved_1b : 5, - tail : 6, - crc : 4, - reserved_1a : 9, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001 - -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e - -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000 - -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000 - -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80 - -#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16 -#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19 -#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20 -#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25 -#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000 - -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/he_sig_a_su_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_a_su_info.h deleted file mode 100644 index e4be3671016e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/he_sig_a_su_info.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_SU_INFO_H_ -#define _HE_SIG_A_SU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2 - -struct he_sig_a_su_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t format_indication : 1, - beam_change : 1, - dl_ul_flag : 1, - transmit_mcs : 4, - dcm : 1, - bss_color_id : 6, - reserved_0a : 1, - spatial_reuse : 4, - transmit_bw : 2, - cp_ltf_size : 2, - nsts : 3, - reserved_0b : 6; - uint32_t txop_duration : 7, - coding : 1, - ldpc_extra_symbol : 1, - stbc : 1, - txbf : 1, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - reserved_1a : 1, - doppler_indication : 1, - crc : 4, - tail : 6, - dot11ax_su_extended : 1, - dot11ax_ext_ru_size : 3, - rx_ndp : 1, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0b : 6, - nsts : 3, - cp_ltf_size : 2, - transmit_bw : 2, - spatial_reuse : 4, - reserved_0a : 1, - bss_color_id : 6, - dcm : 1, - transmit_mcs : 4, - dl_ul_flag : 1, - beam_change : 1, - format_indication : 1; - uint32_t rx_integrity_check_passed : 1, - rx_ndp : 1, - dot11ax_ext_ru_size : 3, - dot11ax_su_extended : 1, - tail : 6, - crc : 4, - doppler_indication : 1, - reserved_1a : 1, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - txbf : 1, - stbc : 1, - ldpc_extra_symbol : 1, - coding : 1, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001 - -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002 - -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004 - -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078 - -#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_DCM_LSB 7 -#define HE_SIG_A_SU_INFO_DCM_MSB 7 -#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080 - -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00 - -#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000 - -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000 - -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000 - -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000 - -#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_NSTS_LSB 23 -#define HE_SIG_A_SU_INFO_NSTS_MSB 25 -#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000 - -#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26 -#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31 -#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000 - -#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_CODING_LSB 7 -#define HE_SIG_A_SU_INFO_CODING_MSB 7 -#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080 - -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100 - -#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_STBC_LSB 9 -#define HE_SIG_A_SU_INFO_STBC_MSB 9 -#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200 - -#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TXBF_LSB 10 -#define HE_SIG_A_SU_INFO_TXBF_MSB 10 -#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400 - -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 - -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 - -#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000 - -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000 - -#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_CRC_LSB 16 -#define HE_SIG_A_SU_INFO_CRC_MSB 19 -#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TAIL_LSB 20 -#define HE_SIG_A_SU_INFO_TAIL_MSB 25 -#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 - -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 - -#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30 -#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30 -#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000 - -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/he_sig_b1_mu_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_b1_mu_info.h deleted file mode 100644 index a248c3dc67b3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/he_sig_b1_mu_info.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B1_MU_INFO_H_ -#define _HE_SIG_B1_MU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 - -struct he_sig_b1_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_allocation : 8, - reserved_0 : 23, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0 : 23, - ru_allocation : 8; -#endif -}; - -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff - -#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8 -#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30 -#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00 - -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/he_sig_b2_mu_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_b2_mu_info.h deleted file mode 100644 index 83d6f3bc843f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/he_sig_b2_mu_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B2_MU_INFO_H_ -#define _HE_SIG_B2_MU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2 - -struct he_sig_b2_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_spatial_config : 4, - sta_mcs : 4, - reserved_set_to_1 : 1, - sta_coding : 1, - reserved_0a : 7, - nsts : 3, - rx_integrity_check_passed : 1; - uint32_t user_order : 8, - cc_mask : 8, - reserved_1a : 16; -#else - uint32_t rx_integrity_check_passed : 1, - nsts : 3, - reserved_0a : 7, - sta_coding : 1, - reserved_set_to_1 : 1, - sta_mcs : 4, - sta_spatial_config : 4, - sta_id : 11; - uint32_t reserved_1a : 16, - cc_mask : 8, - user_order : 8; -#endif -}; - -#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0 -#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10 -#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff - -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800 - -#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15 -#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18 -#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000 - -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000 - -#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20 -#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20 -#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000 - -#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000 - -#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_NSTS_LSB 28 -#define HE_SIG_B2_MU_INFO_NSTS_MSB 30 -#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000 - -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0 -#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7 -#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff - -#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_CC_MASK_LSB 8 -#define HE_SIG_B2_MU_INFO_CC_MASK_MSB 15 -#define HE_SIG_B2_MU_INFO_CC_MASK_MASK 0x0000ff00 - -#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 16 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/he_sig_b2_ofdma_info.h b/drivers/staging/fw-api/hw/fig/v1/he_sig_b2_ofdma_info.h deleted file mode 100644 index 6357d216eb3a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/he_sig_b2_ofdma_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B2_OFDMA_INFO_H_ -#define _HE_SIG_B2_OFDMA_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2 - -struct he_sig_b2_ofdma_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - nsts : 3, - txbf : 1, - sta_mcs : 4, - sta_dcm : 1, - sta_coding : 1, - reserved_0 : 10, - rx_integrity_check_passed : 1; - uint32_t user_order : 8, - cc_mask : 8, - reserved_1a : 16; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0 : 10, - sta_coding : 1, - sta_dcm : 1, - sta_mcs : 4, - txbf : 1, - nsts : 3, - sta_id : 11; - uint32_t reserved_1a : 16, - cc_mask : 8, - user_order : 8; -#endif -}; - -#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff - -#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11 -#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13 -#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800 - -#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14 -#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14 -#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000 - -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000 - -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000 - -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000 - -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000 - -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff - -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00 - -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/ht_sig_info.h b/drivers/staging/fw-api/hw/fig/v1/ht_sig_info.h deleted file mode 100644 index d6a4a719e6e2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/ht_sig_info.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HT_SIG_INFO_H_ -#define _HT_SIG_INFO_H_ - -#define NUM_OF_DWORDS_HT_SIG_INFO 2 - -struct ht_sig_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mcs : 7, - cbw : 1, - length : 16, - reserved_0 : 8; - uint32_t smoothing : 1, - not_sounding : 1, - ht_reserved : 1, - aggregation : 1, - stbc : 2, - fec_coding : 1, - short_gi : 1, - num_ext_sp_str : 2, - crc : 8, - signal_tail : 6, - reserved_1 : 7, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0 : 8, - length : 16, - cbw : 1, - mcs : 7; - uint32_t rx_integrity_check_passed : 1, - reserved_1 : 7, - signal_tail : 6, - crc : 8, - num_ext_sp_str : 2, - short_gi : 1, - fec_coding : 1, - stbc : 2, - aggregation : 1, - ht_reserved : 1, - not_sounding : 1, - smoothing : 1; -#endif -}; - -#define HT_SIG_INFO_MCS_OFFSET 0x00000000 -#define HT_SIG_INFO_MCS_LSB 0 -#define HT_SIG_INFO_MCS_MSB 6 -#define HT_SIG_INFO_MCS_MASK 0x0000007f - -#define HT_SIG_INFO_CBW_OFFSET 0x00000000 -#define HT_SIG_INFO_CBW_LSB 7 -#define HT_SIG_INFO_CBW_MSB 7 -#define HT_SIG_INFO_CBW_MASK 0x00000080 - -#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000 -#define HT_SIG_INFO_LENGTH_LSB 8 -#define HT_SIG_INFO_LENGTH_MSB 23 -#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00 - -#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000 -#define HT_SIG_INFO_RESERVED_0_LSB 24 -#define HT_SIG_INFO_RESERVED_0_MSB 31 -#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000 - -#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004 -#define HT_SIG_INFO_SMOOTHING_LSB 0 -#define HT_SIG_INFO_SMOOTHING_MSB 0 -#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001 - -#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004 -#define HT_SIG_INFO_NOT_SOUNDING_LSB 1 -#define HT_SIG_INFO_NOT_SOUNDING_MSB 1 -#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002 - -#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004 -#define HT_SIG_INFO_HT_RESERVED_LSB 2 -#define HT_SIG_INFO_HT_RESERVED_MSB 2 -#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004 - -#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004 -#define HT_SIG_INFO_AGGREGATION_LSB 3 -#define HT_SIG_INFO_AGGREGATION_MSB 3 -#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008 - -#define HT_SIG_INFO_STBC_OFFSET 0x00000004 -#define HT_SIG_INFO_STBC_LSB 4 -#define HT_SIG_INFO_STBC_MSB 5 -#define HT_SIG_INFO_STBC_MASK 0x00000030 - -#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004 -#define HT_SIG_INFO_FEC_CODING_LSB 6 -#define HT_SIG_INFO_FEC_CODING_MSB 6 -#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040 - -#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004 -#define HT_SIG_INFO_SHORT_GI_LSB 7 -#define HT_SIG_INFO_SHORT_GI_MSB 7 -#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080 - -#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004 -#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8 -#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9 -#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300 - -#define HT_SIG_INFO_CRC_OFFSET 0x00000004 -#define HT_SIG_INFO_CRC_LSB 10 -#define HT_SIG_INFO_CRC_MSB 17 -#define HT_SIG_INFO_CRC_MASK 0x0003fc00 - -#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004 -#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18 -#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23 -#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000 - -#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004 -#define HT_SIG_INFO_RESERVED_1_LSB 24 -#define HT_SIG_INFO_RESERVED_1_MSB 30 -#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000 - -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/l_sig_a_info.h b/drivers/staging/fw-api/hw/fig/v1/l_sig_a_info.h deleted file mode 100644 index 6da0725dfee7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/l_sig_a_info.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _L_SIG_A_INFO_H_ -#define _L_SIG_A_INFO_H_ - -#define NUM_OF_DWORDS_L_SIG_A_INFO 1 - -struct l_sig_a_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rate : 4, - lsig_reserved : 1, - length : 12, - parity : 1, - tail : 6, - pkt_type : 4, - captured_implicit_sounding : 1, - reserved : 2, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved : 2, - captured_implicit_sounding : 1, - pkt_type : 4, - tail : 6, - parity : 1, - length : 12, - lsig_reserved : 1, - rate : 4; -#endif -}; - -#define L_SIG_A_INFO_RATE_OFFSET 0x00000000 -#define L_SIG_A_INFO_RATE_LSB 0 -#define L_SIG_A_INFO_RATE_MSB 3 -#define L_SIG_A_INFO_RATE_MASK 0x0000000f - -#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000 -#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4 -#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4 -#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010 - -#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000 -#define L_SIG_A_INFO_LENGTH_LSB 5 -#define L_SIG_A_INFO_LENGTH_MSB 16 -#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0 - -#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000 -#define L_SIG_A_INFO_PARITY_LSB 17 -#define L_SIG_A_INFO_PARITY_MSB 17 -#define L_SIG_A_INFO_PARITY_MASK 0x00020000 - -#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000 -#define L_SIG_A_INFO_TAIL_LSB 18 -#define L_SIG_A_INFO_TAIL_MSB 23 -#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000 - -#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000 -#define L_SIG_A_INFO_PKT_TYPE_LSB 24 -#define L_SIG_A_INFO_PKT_TYPE_MSB 27 -#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000 - -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 - -#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000 -#define L_SIG_A_INFO_RESERVED_LSB 29 -#define L_SIG_A_INFO_RESERVED_MSB 30 -#define L_SIG_A_INFO_RESERVED_MASK 0x60000000 - -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/l_sig_b_info.h b/drivers/staging/fw-api/hw/fig/v1/l_sig_b_info.h deleted file mode 100644 index f2052702e2de..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/l_sig_b_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _L_SIG_B_INFO_H_ -#define _L_SIG_B_INFO_H_ - -#define NUM_OF_DWORDS_L_SIG_B_INFO 1 - -struct l_sig_b_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rate : 4, - length : 12, - reserved : 15, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved : 15, - length : 12, - rate : 4; -#endif -}; - -#define L_SIG_B_INFO_RATE_OFFSET 0x00000000 -#define L_SIG_B_INFO_RATE_LSB 0 -#define L_SIG_B_INFO_RATE_MSB 3 -#define L_SIG_B_INFO_RATE_MASK 0x0000000f - -#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000 -#define L_SIG_B_INFO_LENGTH_LSB 4 -#define L_SIG_B_INFO_LENGTH_MSB 15 -#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0 - -#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000 -#define L_SIG_B_INFO_RESERVED_LSB 16 -#define L_SIG_B_INFO_RESERVED_MSB 30 -#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000 - -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/macrx_abort_request_info.h b/drivers/staging/fw-api/hw/fig/v1/macrx_abort_request_info.h deleted file mode 100644 index 038f4038fa59..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/macrx_abort_request_info.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACRX_ABORT_REQUEST_INFO_H_ -#define _MACRX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1 - -struct macrx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t macrx_abort_reason : 8, - reserved_0 : 8; -#else - uint16_t reserved_0 : 8, - macrx_abort_reason : 8; -#endif -}; - -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff - -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_mu_mimo.h b/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_mu_mimo.h deleted file mode 100644 index f29ca356a223..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_mu_mimo.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_ -#define _MACTX_EHT_SIG_USR_MU_MIMO_H_ - -#include "eht_sig_usr_mu_mimo_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1 - -struct mactx_eht_sig_usr_mu_mimo { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; -#else - struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; -#endif -}; - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_ofdma.h b/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_ofdma.h deleted file mode 100644 index 24bf6691978d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_ofdma.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_ -#define _MACTX_EHT_SIG_USR_OFDMA_H_ - -#include "eht_sig_usr_ofdma_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_OFDMA 1 - -struct mactx_eht_sig_usr_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; -#else - struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; -#endif -}; - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x00000000000f0000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000100000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x0000000000400000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_su.h b/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_su.h deleted file mode 100644 index 1fb82723c1ff..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_eht_sig_usr_su.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_SU_H_ -#define _MACTX_EHT_SIG_USR_SU_H_ - -#include "eht_sig_usr_su_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_SU 1 - -struct mactx_eht_sig_usr_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; - uint32_t tlv64_padding : 32; -#else - struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x00000000000f0000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x0000000000100000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x000000007fc00000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_LSB 32 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MSB 63 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_mu_dl.h deleted file mode 100644 index 438f3af6f9e7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_mu_dl.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_MU_DL_H_ -#define _MACTX_HE_SIG_A_MU_DL_H_ - -#include "he_sig_a_mu_dl_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_DL 1 - -struct mactx_he_sig_a_mu_dl { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; -#else - struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_mu_ul.h deleted file mode 100644 index 96d2b912665a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_mu_ul.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_MU_UL_H_ -#define _MACTX_HE_SIG_A_MU_UL_H_ - -#include "he_sig_a_mu_ul_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_UL 1 - -struct mactx_he_sig_a_mu_ul { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; -#else - struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_su.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_su.h deleted file mode 100644 index e51241d26559..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_a_su.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_SU_H_ -#define _MACTX_HE_SIG_A_SU_H_ - -#include "he_sig_a_su_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_SU 1 - -struct mactx_he_sig_a_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_su_info mactx_he_sig_a_su_info_details; -#else - struct he_sig_a_su_info mactx_he_sig_a_su_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b1_mu.h deleted file mode 100644 index 700528af2048..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b1_mu.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B1_MU_H_ -#define _MACTX_HE_SIG_B1_MU_H_ - -#include "he_sig_b1_mu_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1 - -struct mactx_he_sig_b1_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#else - struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b2_mu.h deleted file mode 100644 index ccc1c593fed6..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b2_mu.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B2_MU_H_ -#define _MACTX_HE_SIG_B2_MU_H_ - -#include "he_sig_b2_mu_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_MU 1 - -struct mactx_he_sig_b2_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; -#else - struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; -#endif -}; - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b2_ofdma.h deleted file mode 100644 index afc3c4b22841..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_he_sig_b2_ofdma.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B2_OFDMA_H_ -#define _MACTX_HE_SIG_B2_OFDMA_H_ - -#include "he_sig_b2_ofdma_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_OFDMA 1 - -struct mactx_he_sig_b2_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; -#else - struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; -#endif -}; - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_ht_sig.h b/drivers/staging/fw-api/hw/fig/v1/mactx_ht_sig.h deleted file mode 100644 index ec28824c590f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_ht_sig.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HT_SIG_H_ -#define _MACTX_HT_SIG_H_ - -#include "ht_sig_info.h" -#define NUM_OF_DWORDS_MACTX_HT_SIG 2 - -#define NUM_OF_QWORDS_MACTX_HT_SIG 1 - -struct mactx_ht_sig { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ht_sig_info mactx_ht_sig_info_details; -#else - struct ht_sig_info mactx_ht_sig_info_details; -#endif -}; - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 36 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 37 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 42 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 49 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_l_sig_a.h b/drivers/staging/fw-api/hw/fig/v1/mactx_l_sig_a.h deleted file mode 100644 index 061e46e28a2c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_l_sig_a.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_L_SIG_A_H_ -#define _MACTX_L_SIG_A_H_ - -#include "l_sig_a_info.h" -#define NUM_OF_DWORDS_MACTX_L_SIG_A 2 - -#define NUM_OF_QWORDS_MACTX_L_SIG_A 1 - -struct mactx_l_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_a_info mactx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_a_info mactx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_TLV64_PADDING_LSB 32 -#define MACTX_L_SIG_A_TLV64_PADDING_MSB 63 -#define MACTX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_l_sig_b.h b/drivers/staging/fw-api/hw/fig/v1/mactx_l_sig_b.h deleted file mode 100644 index 6d533acef675..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_l_sig_b.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_L_SIG_B_H_ -#define _MACTX_L_SIG_B_H_ - -#include "l_sig_b_info.h" -#define NUM_OF_DWORDS_MACTX_L_SIG_B 2 - -#define NUM_OF_QWORDS_MACTX_L_SIG_B 1 - -struct mactx_l_sig_b { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_b_info mactx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_b_info mactx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_TLV64_PADDING_LSB 32 -#define MACTX_L_SIG_B_TLV64_PADDING_MSB 63 -#define MACTX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_phy_desc.h b/drivers/staging/fw-api/hw/fig/v1/mactx_phy_desc.h deleted file mode 100644 index ee4ccdf65c28..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_phy_desc.h +++ /dev/null @@ -1,348 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_PHY_DESC_H_ -#define _MACTX_PHY_DESC_H_ - -#define NUM_OF_DWORDS_MACTX_PHY_DESC 4 - -#define NUM_OF_QWORDS_MACTX_PHY_DESC 2 - -struct mactx_phy_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 16, - bf_type : 2, - wait_sifs : 2, - dot11b_preamble_type : 1, - pkt_type : 4, - su_or_mu : 2, - mu_type : 1, - bandwidth : 3, - channel_capture : 1; - uint32_t mcs : 5, - global_ofdma_mimo_enable : 1, - stbc : 1, - dot11ax_su_extended : 1, - dot11ax_trigger_frame_embedded : 1, - tx_pwr_shared : 8, - tx_pwr_unshared : 8, - measure_power : 1, - tpc_glut_self_cal : 1, - back_to_back_transmission_expected : 1, - heavy_clip_nss : 3, - txbf_per_packet_no_csd_no_walsh : 1; - uint32_t ndp : 3, - ul_flag : 1, - triggered : 1, - ap_pkt_bw : 3, - ru_position_start : 8, - pcu_ppdu_setup_start_reason : 3, - tlv_source : 1, - reserved_2a : 1, - nss : 3, - stream_offset : 3, - reserved_2b : 2, - clpc_enable : 1, - mu_ndp : 1, - response_expected : 1; - uint32_t rx_chain_mask : 8, - rx_chain_mask_valid : 1, - ant_sel_valid : 1, - ant_sel : 1, - cp_setting : 2, - he_ppdu_subtype : 2, - active_channel : 3, - generate_phyrx_tx_start_timing : 1, - ltf_size : 2, - ru_size_updated_v2 : 4, - reserved_3c : 1, - u_sig_puncture_pattern_encoding : 6; -#else - uint32_t channel_capture : 1, - bandwidth : 3, - mu_type : 1, - su_or_mu : 2, - pkt_type : 4, - dot11b_preamble_type : 1, - wait_sifs : 2, - bf_type : 2, - reserved_0a : 16; - uint32_t txbf_per_packet_no_csd_no_walsh : 1, - heavy_clip_nss : 3, - back_to_back_transmission_expected : 1, - tpc_glut_self_cal : 1, - measure_power : 1, - tx_pwr_unshared : 8, - tx_pwr_shared : 8, - dot11ax_trigger_frame_embedded : 1, - dot11ax_su_extended : 1, - stbc : 1, - global_ofdma_mimo_enable : 1, - mcs : 5; - uint32_t response_expected : 1, - mu_ndp : 1, - clpc_enable : 1, - reserved_2b : 2, - stream_offset : 3, - nss : 3, - reserved_2a : 1, - tlv_source : 1, - pcu_ppdu_setup_start_reason : 3, - ru_position_start : 8, - ap_pkt_bw : 3, - triggered : 1, - ul_flag : 1, - ndp : 3; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_3c : 1, - ru_size_updated_v2 : 4, - ltf_size : 2, - generate_phyrx_tx_start_timing : 1, - active_channel : 3, - he_ppdu_subtype : 2, - cp_setting : 2, - ant_sel : 1, - ant_sel_valid : 1, - rx_chain_mask_valid : 1, - rx_chain_mask : 8; -#endif -}; - -#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_RESERVED_0A_LSB 0 -#define MACTX_PHY_DESC_RESERVED_0A_MSB 15 -#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff - -#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BF_TYPE_LSB 16 -#define MACTX_PHY_DESC_BF_TYPE_MSB 17 -#define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000 - -#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 -#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 -#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000 - -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000 - -#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_PKT_TYPE_LSB 21 -#define MACTX_PHY_DESC_PKT_TYPE_MSB 24 -#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000 - -#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_SU_OR_MU_LSB 25 -#define MACTX_PHY_DESC_SU_OR_MU_MSB 26 -#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000 - -#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MU_TYPE_LSB 27 -#define MACTX_PHY_DESC_MU_TYPE_MSB 27 -#define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000 - -#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BANDWIDTH_LSB 28 -#define MACTX_PHY_DESC_BANDWIDTH_MSB 30 -#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000 - -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000 - -#define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MCS_LSB 32 -#define MACTX_PHY_DESC_MCS_MSB 36 -#define MACTX_PHY_DESC_MCS_MASK 0x0000001f00000000 - -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 37 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 37 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000002000000000 - -#define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_STBC_LSB 38 -#define MACTX_PHY_DESC_STBC_MSB 38 -#define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000 - -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000 - -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000 - -#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41 -#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48 -#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000 - -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000 - -#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MEASURE_POWER_LSB 57 -#define MACTX_PHY_DESC_MEASURE_POWER_MSB 57 -#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000 - -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000 - -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000 - -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000 - -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000 - -#define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_NDP_LSB 0 -#define MACTX_PHY_DESC_NDP_MSB 2 -#define MACTX_PHY_DESC_NDP_MASK 0x0000000000000007 - -#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_UL_FLAG_LSB 3 -#define MACTX_PHY_DESC_UL_FLAG_MSB 3 -#define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000008 - -#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_TRIGGERED_LSB 4 -#define MACTX_PHY_DESC_TRIGGERED_MSB 4 -#define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000010 - -#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_AP_PKT_BW_LSB 5 -#define MACTX_PHY_DESC_AP_PKT_BW_MSB 7 -#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x00000000000000e0 - -#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RU_POSITION_START_LSB 8 -#define MACTX_PHY_DESC_RU_POSITION_START_MSB 15 -#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x000000000000ff00 - -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 16 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 18 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000070000 - -#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_TLV_SOURCE_LSB 19 -#define MACTX_PHY_DESC_TLV_SOURCE_MSB 19 -#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000080000 - -#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_2A_LSB 20 -#define MACTX_PHY_DESC_RESERVED_2A_MSB 20 -#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000100000 - -#define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_NSS_LSB 21 -#define MACTX_PHY_DESC_NSS_MSB 23 -#define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000 - -#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 -#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 -#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000 - -#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_2B_LSB 27 -#define MACTX_PHY_DESC_RESERVED_2B_MSB 28 -#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000 - -#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 -#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 -#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000 - -#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_MU_NDP_LSB 30 -#define MACTX_PHY_DESC_MU_NDP_MSB 30 -#define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000 - -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000 - -#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000 - -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000 - -#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41 -#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41 -#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000 - -#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ANT_SEL_LSB 42 -#define MACTX_PHY_DESC_ANT_SEL_MSB 42 -#define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000 - -#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_CP_SETTING_LSB 43 -#define MACTX_PHY_DESC_CP_SETTING_MSB 44 -#define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000 - -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000 - -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000 - -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000 - -#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_LTF_SIZE_LSB 51 -#define MACTX_PHY_DESC_LTF_SIZE_MSB 52 -#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000 - -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000 - -#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_3C_LSB 57 -#define MACTX_PHY_DESC_RESERVED_3C_MSB 57 -#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000 - -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_u_sig_eht_su_mu.h b/drivers/staging/fw-api/hw/fig/v1/mactx_u_sig_eht_su_mu.h deleted file mode 100644 index f46583e4c7ee..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_u_sig_eht_su_mu.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_U_SIG_EHT_SU_MU_H_ -#define _MACTX_U_SIG_EHT_SU_MU_H_ - -#include "u_sig_eht_su_mu_info.h" -#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2 - -#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_SU_MU 1 - -struct mactx_u_sig_eht_su_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; -#else - struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; -#endif -}; - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB 0 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB 2 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000001f00000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x0000000002000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 34 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 34 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 35 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 39 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f800000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 40 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 40 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x0000010000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 41 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 42 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x0000060000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 43 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 47 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f80000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 48 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 51 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 59 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 61 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x3800000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 62 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 62 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_u_sig_eht_tb.h b/drivers/staging/fw-api/hw/fig/v1/mactx_u_sig_eht_tb.h deleted file mode 100644 index 5e57312a9da2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_u_sig_eht_tb.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_U_SIG_EHT_TB_H_ -#define _MACTX_U_SIG_EHT_TB_H_ - -#include "u_sig_eht_tb_info.h" -#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2 - -#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1 - -struct mactx_u_sig_eht_tb { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; -#else - struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; -#endif -}; - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000003f00000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 34 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 34 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 35 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 42 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f800000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 43 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 47 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f80000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 48 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 51 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 58 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 62 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c00000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_user_desc_common.h b/drivers/staging/fw-api/hw/fig/v1/mactx_user_desc_common.h deleted file mode 100644 index 04124271bbc9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_user_desc_common.h +++ /dev/null @@ -1,482 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_USER_DESC_COMMON_H_ -#define _MACTX_USER_DESC_COMMON_H_ - -#include "unallocated_ru_160_info.h" -#include "ru_allocation_160_info.h" -#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 - -#define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8 - -struct mactx_user_desc_common { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t num_users : 6, - reserved_0b : 5, - ltf_size : 2, - reserved_0c : 3, - he_stf_long : 1, - reserved_0d : 7, - num_users_he_sigb_band0 : 8; - uint32_t num_ltf_symbols : 3, - reserved_1a : 5, - num_users_he_sigb_band1 : 8, - reserved_1b : 16; - uint32_t packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - packet_extension : 3, - reserved : 2, - he_sigb_dcm : 1, - reserved_2b : 7, - he_sigb_compression : 1, - reserved_2c : 15; - uint32_t he_sigb_0_mcs : 3, - reserved_3a : 13, - num_he_sigb_sym : 5, - center_ru_0 : 1, - center_ru_1 : 1, - reserved_3b : 1, - ftm_en : 1, - pe_nss : 3, - pe_ltf_size : 2, - pe_content : 1, - pe_chain_csd_en : 1; - struct ru_allocation_160_info ru_allocation_0123_details; - struct ru_allocation_160_info ru_allocation_4567_details; - struct unallocated_ru_160_info ru_allocation_160_0_details; - struct unallocated_ru_160_info ru_allocation_160_1_details; - uint32_t num_data_symbols : 16, - ndp_ru_tone_set_index : 7, - ndp_feedback_status : 1, - doppler_indication : 1, - reserved_14a : 7; - uint32_t spatial_reuse : 16, - distributed_ru : 1, - dru_spreading_bw : 2, - reserved_15a : 13; -#else - uint32_t num_users_he_sigb_band0 : 8, - reserved_0d : 7, - he_stf_long : 1, - reserved_0c : 3, - ltf_size : 2, - reserved_0b : 5, - num_users : 6; - uint32_t reserved_1b : 16, - num_users_he_sigb_band1 : 8, - reserved_1a : 5, - num_ltf_symbols : 3; - uint32_t reserved_2c : 15, - he_sigb_compression : 1, - reserved_2b : 7, - he_sigb_dcm : 1, - reserved : 2, - packet_extension : 3, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2; - uint32_t pe_chain_csd_en : 1, - pe_content : 1, - pe_ltf_size : 2, - pe_nss : 3, - ftm_en : 1, - reserved_3b : 1, - center_ru_1 : 1, - center_ru_0 : 1, - num_he_sigb_sym : 5, - reserved_3a : 13, - he_sigb_0_mcs : 3; - struct ru_allocation_160_info ru_allocation_0123_details; - struct ru_allocation_160_info ru_allocation_4567_details; - struct unallocated_ru_160_info ru_allocation_160_0_details; - struct unallocated_ru_160_info ru_allocation_160_1_details; - uint32_t reserved_14a : 7, - doppler_indication : 1, - ndp_feedback_status : 1, - ndp_ru_tone_set_index : 7, - num_data_symbols : 16; - uint32_t reserved_15a : 13, - dru_spreading_bw : 2, - distributed_ru : 1, - spatial_reuse : 16; -#endif -}; - -#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 -#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 -#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x000000000000003f - -#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x00000000000007c0 - -#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x0000000000001800 - -#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x000000000000e000 - -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x0000000000fe0000 - -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 32 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 34 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 35 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 39 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f800000000 - -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 40 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 47 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff0000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 48 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 63 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff000000000000 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x0000000000000038 - -#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 -#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 -#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x00000000000000c0 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x0000000000000100 - -#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x000000000000fe00 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0x00000000fffe0000 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 32 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 34 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x0000000700000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 35 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 47 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff800000000 - -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 48 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 52 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f000000000000 - -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 53 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 53 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x0020000000000000 - -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 54 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 54 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x0040000000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 55 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 55 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x0080000000000000 - -#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 56 -#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 56 -#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x0100000000000000 - -#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 57 -#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 59 -#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e00000000000000 - -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 60 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 61 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x3000000000000000 - -#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 62 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 62 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x4000000000000000 - -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 63 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 63 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x00000000000000ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x000000000000ff00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x0000000000ff0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 39 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 47 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 48 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 55 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 56 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff00000000000000 - -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x000000000000ffff - -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x00000000007f0000 - -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x0000000000800000 - -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x0000000001000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0x00000000fe000000 - -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 32 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 47 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_LSB 48 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MSB 48 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MASK 0x0001000000000000 - -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_LSB 49 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MSB 50 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MASK 0x0006000000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 51 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 63 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xfff8000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_user_desc_per_user.h b/drivers/staging/fw-api/hw/fig/v1/mactx_user_desc_per_user.h deleted file mode 100644 index a68b50d9d639..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_user_desc_per_user.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_USER_DESC_PER_USER_H_ -#define _MACTX_USER_DESC_PER_USER_H_ - -#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 6 - -#define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 3 - -struct mactx_user_desc_per_user { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t psdu_length : 24, - reserved_0a : 8; - uint32_t ru_start_index : 8, - ru_size : 4, - reserved_1b : 4, - ofdma_mu_mimo_enabled : 1, - nss : 3, - stream_offset : 3, - reserved_1c : 1, - mcs : 5, - dcm : 1, - reserved_1d : 2; - uint32_t fec_type : 1, - reserved_2a : 1, - qam_diff1 : 2, - qam_diff2 : 2, - qam_diff3 : 2, - user_bf_type : 2, - a_factor_ldpc2x : 2, - extra_sym_ldpc2x : 1, - cw_len_2x : 2, - reserved_2b : 1, - drop_user_cbf : 1, - a_factor_ldpc1x : 2, - extra_sym_ldpc1x : 1, - cw_len_1x : 2, - ldpc1x_used : 1, - ldpc2x_used : 1, - ldpc_extra_symbol : 1, - force_extra_symbol : 1, - ldpc_2x_codeword : 1, - reserved_2d : 5; - uint32_t sw_peer_id : 16, - per_user_subband_mask : 16; - uint32_t ldpc_num_avbits : 27, - reserved_4a : 5; - uint32_t num_cw_1x : 16, - num_cw_2x : 16; -#else - uint32_t reserved_0a : 8, - psdu_length : 24; - uint32_t reserved_1d : 2, - dcm : 1, - mcs : 5, - reserved_1c : 1, - stream_offset : 3, - nss : 3, - ofdma_mu_mimo_enabled : 1, - reserved_1b : 4, - ru_size : 4, - ru_start_index : 8; - uint32_t reserved_2d : 5, - ldpc_2x_codeword : 1, - force_extra_symbol : 1, - ldpc_extra_symbol : 1, - ldpc2x_used : 1, - ldpc1x_used : 1, - cw_len_1x : 2, - extra_sym_ldpc1x : 1, - a_factor_ldpc1x : 2, - drop_user_cbf : 1, - reserved_2b : 1, - cw_len_2x : 2, - extra_sym_ldpc2x : 1, - a_factor_ldpc2x : 2, - user_bf_type : 2, - qam_diff3 : 2, - qam_diff2 : 2, - qam_diff1 : 2, - reserved_2a : 1, - fec_type : 1; - uint32_t per_user_subband_mask : 16, - sw_peer_id : 16; - uint32_t reserved_4a : 5, - ldpc_num_avbits : 27; - uint32_t num_cw_2x : 16, - num_cw_1x : 16; -#endif -}; - -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x0000000000ffffff - -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 32 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 39 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff00000000 - -#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 40 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 43 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f0000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 44 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 47 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f00000000000 - -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 48 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 48 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x0001000000000000 - -#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_NSS_LSB 49 -#define MACTX_USER_DESC_PER_USER_NSS_MSB 51 -#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e000000000000 - -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 52 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 54 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x0070000000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 55 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 55 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x0080000000000000 - -#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_MCS_LSB 56 -#define MACTX_USER_DESC_PER_USER_MCS_MSB 60 -#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x1f00000000000000 - -#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_DCM_LSB 61 -#define MACTX_USER_DESC_PER_USER_DCM_MSB 61 -#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x2000000000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 62 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 63 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xc000000000000000 - -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x0000000000000001 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 1 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x0000000000000002 - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_LSB 2 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MSB 3 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MASK 0x000000000000000c - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_LSB 4 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MSB 5 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MASK 0x0000000000000030 - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_LSB 6 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MSB 7 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MASK 0x00000000000000c0 - -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x0000000000000300 - -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_LSB 10 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MSB 11 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MASK 0x0000000000000c00 - -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_LSB 12 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MSB 12 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MASK 0x0000000000001000 - -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_LSB 13 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MSB 14 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MASK 0x0000000000006000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 15 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x0000000000008000 - -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_LSB 17 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MSB 18 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MASK 0x0000000000060000 - -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_LSB 19 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MSB 19 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MASK 0x0000000000080000 - -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_LSB 20 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MSB 21 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MASK 0x0000000000300000 - -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_LSB 22 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MSB 22 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MASK 0x0000000000400000 - -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_LSB 23 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MSB 23 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MASK 0x0000000000800000 - -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x0000000001000000 - -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x0000000002000000 - -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_LSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MASK 0x0000000004000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 27 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0x00000000f8000000 - -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 32 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 47 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 48 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 63 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff000000000000 - -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_LSB 0 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MASK 0x0000000007ffffff - -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_LSB 27 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MASK 0x00000000f8000000 - -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_LSB 32 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MSB 47 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_LSB 48 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MSB 63 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_a.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_a.h deleted file mode 100644 index 6dec145785d6..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_a.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_A_H_ -#define _MACTX_VHT_SIG_A_H_ - -#include "vht_sig_a_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_A 1 - -struct mactx_vht_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_a_info mactx_vht_sig_a_info_details; -#else - struct vht_sig_a_info mactx_vht_sig_a_info_details; -#endif -}; - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu160.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu160.h deleted file mode 100644 index b66278da930b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu160.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU160_H_ -#define _MACTX_VHT_SIG_B_MU160_H_ - -#include "vht_sig_b_mu160_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU160 4 - -struct mactx_vht_sig_b_mu160 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; -#else - struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu20.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu20.h deleted file mode 100644 index 95feca30eaa3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu20.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU20_H_ -#define _MACTX_VHT_SIG_B_MU20_H_ - -#include "vht_sig_b_mu20_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU20 1 - -struct mactx_vht_sig_b_mu20 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; - uint32_t tlv64_padding : 32; -#else - struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x000000000000ffff - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x00000000000f0000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x000000001c000000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_LSB 32 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MSB 63 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu40.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu40.h deleted file mode 100644 index c770db089203..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu40.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU40_H_ -#define _MACTX_VHT_SIG_B_MU40_H_ - -#include "vht_sig_b_mu40_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU40 1 - -struct mactx_vht_sig_b_mu40 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; -#else - struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x00000000001e0000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x0000000018000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 32 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 48 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff00000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 49 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 52 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e000000000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 53 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 58 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 59 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf800000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu80.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu80.h deleted file mode 100644 index 9e39d240b618..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_mu80.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU80_H_ -#define _MACTX_VHT_SIG_B_MU80_H_ - -#include "vht_sig_b_mu80_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU80 2 - -struct mactx_vht_sig_b_mu80 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; -#else - struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 50 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 51 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 50 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 51 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 63 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su160.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su160.h deleted file mode 100644 index 01bc54e5ab89..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su160.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU160_H_ -#define _MACTX_VHT_SIG_B_SU160_H_ - -#include "vht_sig_b_su160_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU160 4 - -struct mactx_vht_sig_b_su160 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; -#else - struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su20.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su20.h deleted file mode 100644 index c297cc0785e3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su20.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU20_H_ -#define _MACTX_VHT_SIG_B_SU20_H_ - -#include "vht_sig_b_su20_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1 - -struct mactx_vht_sig_b_su20 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; - uint32_t tlv64_padding : 32; -#else - struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x00000000000e0000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x000000007c000000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB 32 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB 63 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su40.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su40.h deleted file mode 100644 index 002d72c430ca..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su40.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU40_H_ -#define _MACTX_VHT_SIG_B_SU40_H_ - -#include "vht_sig_b_su40_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU40 1 - -struct mactx_vht_sig_b_su40 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; -#else - struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000180000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x0000000078000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 32 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 50 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 51 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 52 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x0018000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 53 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 58 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 59 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 62 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x7800000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 63 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 63 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su80.h b/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su80.h deleted file mode 100644 index b15646f03f4a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mactx_vht_sig_b_su80.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU80_H_ -#define _MACTX_VHT_SIG_B_SU80_H_ - -#include "vht_sig_b_su80_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU80 2 - -struct mactx_vht_sig_b_su80 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; -#else - struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 52 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 52 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 62 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mlo_sta_id_details.h b/drivers/staging/fw-api/hw/fig/v1/mlo_sta_id_details.h deleted file mode 100644 index 952056890206..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mlo_sta_id_details.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MLO_STA_ID_DETAILS_H_ -#define _MLO_STA_ID_DETAILS_H_ - -#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1 - -struct mlo_sta_id_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t nstr_mlo_sta_id : 10, - block_self_ml_sync : 1, - block_partner_ml_sync : 1, - nstr_mlo_sta_id_valid : 1, - reserved_0a : 3; -#else - uint16_t reserved_0a : 3, - nstr_mlo_sta_id_valid : 1, - block_partner_ml_sync : 1, - block_self_ml_sync : 1, - nstr_mlo_sta_id : 10; -#endif -}; - -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff - -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400 - -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 - -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 - -#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13 -#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15 -#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mon_buffer_addr.h b/drivers/staging/fw-api/hw/fig/v1/mon_buffer_addr.h deleted file mode 100644 index 8cb6f5fd57b9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mon_buffer_addr.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_BUFFER_ADDR_H_ -#define _MON_BUFFER_ADDR_H_ - -#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4 - -#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2 - -struct mon_buffer_addr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t dma_length : 12, - reserved_2a : 4, - msdu_continuation : 1, - truncated : 1, - reserved_2b : 14; - uint32_t tlv64_padding : 32; -#else - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t reserved_2b : 14, - truncated : 1, - msdu_continuation : 1, - reserved_2a : 4, - dma_length : 12; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff - -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000 - -#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 -#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 -#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff - -#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 -#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 -#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000 - -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000 - -#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_TRUNCATED_LSB 17 -#define MON_BUFFER_ADDR_TRUNCATED_MSB 17 -#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000 - -#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 -#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 -#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000 - -#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32 -#define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63 -#define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mon_destination_ring.h b/drivers/staging/fw-api/hw/fig/v1/mon_destination_ring.h deleted file mode 100644 index 1f373b585fd5..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mon_destination_ring.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_DESTINATION_RING_H_ -#define _MON_DESTINATION_RING_H_ - -#define NUM_OF_DWORDS_MON_DESTINATION_RING 4 - -struct mon_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t stat_buf_virt_addr_31_0 : 32; - uint32_t stat_buf_virt_addr_63_32 : 32; - uint32_t ppdu_id : 32; - uint32_t end_offset : 12, - reserved_3a : 2, - link_info : 2, - end_reason : 2, - initiator : 1, - empty_descriptor : 1, - pkt_buffer_cnt : 8, - looping_count : 4; -#else - uint32_t stat_buf_virt_addr_31_0 : 32; - uint32_t stat_buf_virt_addr_63_32 : 32; - uint32_t ppdu_id : 32; - uint32_t looping_count : 4, - pkt_buffer_cnt : 8, - empty_descriptor : 1, - initiator : 1, - end_reason : 2, - link_info : 2, - reserved_3a : 2, - end_offset : 12; -#endif -}; - -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff - -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff - -#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008 -#define MON_DESTINATION_RING_PPDU_ID_LSB 0 -#define MON_DESTINATION_RING_PPDU_ID_MSB 31 -#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff - -#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c -#define MON_DESTINATION_RING_END_OFFSET_LSB 0 -#define MON_DESTINATION_RING_END_OFFSET_MSB 11 -#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff - -#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c -#define MON_DESTINATION_RING_RESERVED_3A_LSB 12 -#define MON_DESTINATION_RING_RESERVED_3A_MSB 13 -#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x00003000 - -#define MON_DESTINATION_RING_LINK_INFO_OFFSET 0x0000000c -#define MON_DESTINATION_RING_LINK_INFO_LSB 14 -#define MON_DESTINATION_RING_LINK_INFO_MSB 15 -#define MON_DESTINATION_RING_LINK_INFO_MASK 0x0000c000 - -#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c -#define MON_DESTINATION_RING_END_REASON_LSB 16 -#define MON_DESTINATION_RING_END_REASON_MSB 17 -#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000 - -#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c -#define MON_DESTINATION_RING_INITIATOR_LSB 18 -#define MON_DESTINATION_RING_INITIATOR_MSB 18 -#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000 - -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19 -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19 -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000 - -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_OFFSET 0x0000000c -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_LSB 20 -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MSB 27 -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MASK 0x0ff00000 - -#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c -#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28 -#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31 -#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mon_drop.h b/drivers/staging/fw-api/hw/fig/v1/mon_drop.h deleted file mode 100644 index d1135ecd0dc2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mon_drop.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_DROP_H_ -#define _MON_DROP_H_ - -#define NUM_OF_DWORDS_MON_DROP 2 - -#define NUM_OF_QWORDS_MON_DROP 1 - -struct mon_drop { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ppdu_id : 32; - uint32_t ppdu_drop_cnt : 10, - mpdu_drop_cnt : 10, - tlv_drop_cnt : 10, - end_of_ppdu_seen : 1, - reserved_1a : 1; -#else - uint32_t ppdu_id : 32; - uint32_t reserved_1a : 1, - end_of_ppdu_seen : 1, - tlv_drop_cnt : 10, - mpdu_drop_cnt : 10, - ppdu_drop_cnt : 10; -#endif -}; - -#define MON_DROP_PPDU_ID_OFFSET 0x0000000000000000 -#define MON_DROP_PPDU_ID_LSB 0 -#define MON_DROP_PPDU_ID_MSB 31 -#define MON_DROP_PPDU_ID_MASK 0x00000000ffffffff - -#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_PPDU_DROP_CNT_LSB 32 -#define MON_DROP_PPDU_DROP_CNT_MSB 41 -#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff00000000 - -#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_MPDU_DROP_CNT_LSB 42 -#define MON_DROP_MPDU_DROP_CNT_MSB 51 -#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc0000000000 - -#define MON_DROP_TLV_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_TLV_DROP_CNT_LSB 52 -#define MON_DROP_TLV_DROP_CNT_MSB 61 -#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff0000000000000 - -#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x0000000000000000 -#define MON_DROP_END_OF_PPDU_SEEN_LSB 62 -#define MON_DROP_END_OF_PPDU_SEEN_MSB 62 -#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x4000000000000000 - -#define MON_DROP_RESERVED_1A_OFFSET 0x0000000000000000 -#define MON_DROP_RESERVED_1A_LSB 63 -#define MON_DROP_RESERVED_1A_MSB 63 -#define MON_DROP_RESERVED_1A_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/mon_ingress_ring.h b/drivers/staging/fw-api/hw/fig/v1/mon_ingress_ring.h deleted file mode 100644 index 76f4e80417e0..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/mon_ingress_ring.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_INGRESS_RING_H_ -#define _MON_INGRESS_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_MON_INGRESS_RING 4 - -struct mon_ingress_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buffer_addr_info_details; - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; -#else - struct buffer_addr_info buffer_addr_info_details; - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; -#endif -}; - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff - -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/msmhwiobase.h b/drivers/staging/fw-api/hw/fig/v1/msmhwiobase.h deleted file mode 100644 index f7620cef5599..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/msmhwiobase.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef __MSMHWIOBASE_H__ -#define __MSMHWIOBASE_H__ - -#define SOC_WFSS_CE_REG_BASE 0x01b80000 -#define SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000 -#define SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000 -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/msmhwioreg.h b/drivers/staging/fw-api/hw/fig/v1/msmhwioreg.h deleted file mode 100644 index 881c73e30f58..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/msmhwioreg.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ -#ifndef __MSMHWIOREG_H__ -#define __MSMHWIOREG_H__ - -#include "msmhwiobase.h" - -#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00001000) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000408) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 -#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000004) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 -#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00003000) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000004) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000400) -#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00002000) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000004) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000400) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000058) - - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/no_ack_report.h b/drivers/staging/fw-api/hw/fig/v1/no_ack_report.h deleted file mode 100644 index 5f9660801de6..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/no_ack_report.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _NO_ACK_REPORT_H_ -#define _NO_ACK_REPORT_H_ - -#define NUM_OF_DWORDS_NO_ACK_REPORT 4 - -struct no_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t no_ack_transmit_reason : 4, - macrx_abort_reason : 4, - phyrx_abort_reason : 8, - frame_control : 16; - uint32_t rx_ppdu_duration : 24, - sr_ppdu_during_obss : 1, - selfgen_response_reason_to_sr_ppdu : 4, - reserved_1 : 3; - uint32_t pre_bt_broadcast_status_details : 12, - first_bt_broadcast_status_details : 12, - reserved_2 : 8; - uint32_t second_bt_broadcast_status_details : 12, - reserved_3 : 20; -#else - uint32_t frame_control : 16, - phyrx_abort_reason : 8, - macrx_abort_reason : 4, - no_ack_transmit_reason : 4; - uint32_t reserved_1 : 3, - selfgen_response_reason_to_sr_ppdu : 4, - sr_ppdu_during_obss : 1, - rx_ppdu_duration : 24; - uint32_t reserved_2 : 8, - first_bt_broadcast_status_details : 12, - pre_bt_broadcast_status_details : 12; - uint32_t reserved_3 : 20, - second_bt_broadcast_status_details : 12; -#endif -}; - -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f - -#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0 - -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00 - -#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 -#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16 -#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31 -#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 - -#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004 -#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0 -#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23 -#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff - -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000 - -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000 - -#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004 -#define NO_ACK_REPORT_RESERVED_1_LSB 29 -#define NO_ACK_REPORT_RESERVED_1_MSB 31 -#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000 - -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff - -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000 - -#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008 -#define NO_ACK_REPORT_RESERVED_2_LSB 24 -#define NO_ACK_REPORT_RESERVED_2_MSB 31 -#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000 - -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff - -#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c -#define NO_ACK_REPORT_RESERVED_3_LSB 12 -#define NO_ACK_REPORT_RESERVED_3_MSB 31 -#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/ofdma_trigger_details.h b/drivers/staging/fw-api/hw/fig/v1/ofdma_trigger_details.h deleted file mode 100644 index 604b52e0d464..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/ofdma_trigger_details.h +++ /dev/null @@ -1,928 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _OFDMA_TRIGGER_DETAILS_H_ -#define _OFDMA_TRIGGER_DETAILS_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 26 - -#define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 13 - -struct ofdma_trigger_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ax_trigger_source : 1, - rx_trigger_frame_user_source : 2, - received_bandwidth : 3, - txop_duration_all_ones : 1, - eht_trigger_response : 1, - pre_rssi_comb : 8, - rssi_comb : 8, - rxpcu_pcie_l0_req_duration : 8; - uint32_t he_trigger_ul_ppdu_length : 5, - he_trigger_ru_allocation : 8, - he_trigger_dl_tx_power : 5, - he_trigger_ul_target_rssi : 5, - he_trigger_ul_mcs : 2, - he_trigger_reserved : 1, - bss_color : 6; - uint32_t trigger_type : 4, - lsig_response_length : 12, - cascade_indication : 1, - carrier_sense : 1, - bandwidth : 2, - cp_ltf_size : 2, - mu_mimo_ltf_mode : 1, - number_of_ltfs : 3, - stbc : 1, - ldpc_extra_symbol : 1, - ap_tx_power_lsb_part : 4; - uint32_t ap_tx_power_msb_part : 2, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - spatial_reuse : 16, - doppler : 1, - he_siga_reserved : 9, - reserved_3b : 1; - uint32_t aid12 : 12, - ru_allocation : 9, - mcs : 4, - dcm : 1, - start_spatial_stream : 3, - number_of_spatial_stream : 3; - uint32_t target_rssi : 7, - coding_type : 1, - mpdu_mu_spacing_factor : 2, - tid_aggregation_limit : 3, - reserved_5b : 1, - prefered_ac : 2, - bar_control_ack_policy : 1, - bar_control_multi_tid : 1, - bar_control_compressed_bitmap : 1, - bar_control_reserved : 9, - bar_control_tid_info : 4; - uint32_t nr0_per_tid_info_reserved : 12, - nr0_per_tid_info_tid_value : 4, - nr0_start_seq_ctrl_frag_number : 4, - nr0_start_seq_ctrl_start_seq_number : 12; - uint32_t nr1_per_tid_info_reserved : 12, - nr1_per_tid_info_tid_value : 4, - nr1_start_seq_ctrl_frag_number : 4, - nr1_start_seq_ctrl_start_seq_number : 12; - uint32_t nr2_per_tid_info_reserved : 12, - nr2_per_tid_info_tid_value : 4, - nr2_start_seq_ctrl_frag_number : 4, - nr2_start_seq_ctrl_start_seq_number : 12; - uint32_t nr3_per_tid_info_reserved : 12, - nr3_per_tid_info_tid_value : 4, - nr3_start_seq_ctrl_frag_number : 4, - nr3_start_seq_ctrl_start_seq_number : 12; - uint32_t nr4_per_tid_info_reserved : 12, - nr4_per_tid_info_tid_value : 4, - nr4_start_seq_ctrl_frag_number : 4, - nr4_start_seq_ctrl_start_seq_number : 12; - uint32_t nr5_per_tid_info_reserved : 12, - nr5_per_tid_info_tid_value : 4, - nr5_start_seq_ctrl_frag_number : 4, - nr5_start_seq_ctrl_start_seq_number : 12; - uint32_t nr6_per_tid_info_reserved : 12, - nr6_per_tid_info_tid_value : 4, - nr6_start_seq_ctrl_frag_number : 4, - nr6_start_seq_ctrl_start_seq_number : 12; - uint32_t nr7_per_tid_info_reserved : 12, - nr7_per_tid_info_tid_value : 4, - nr7_start_seq_ctrl_frag_number : 4, - nr7_start_seq_ctrl_start_seq_number : 12; - uint32_t fb_segment_retransmission_bitmap : 8, - reserved_14a : 2, - u_sig_puncture_pattern_encoding : 6, - dot11be_puncture_bitmap : 16; - uint32_t rx_chain_mask : 8, - rx_duration_field : 16, - scrambler_seed : 7, - rx_chain_mask_type : 1; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t normalized_pre_rssi_comb : 8, - normalized_rssi_comb : 8; - uint32_t sw_peer_id : 16, - response_tx_duration : 16; - uint32_t __reserved_g_0022_trigger_subtype : 4, - tbr_trigger_common_info_79_68 : 12, - tbr_trigger_sound_reserved_20_12 : 9, - i2r_rep : 3, - tbr_trigger_sound_reserved_25_24 : 2, - reserved_18a : 1, - qos_null_only_response_tx : 1; - uint32_t tbr_trigger_sound_sac : 16, - reserved_19a : 8, - u_sig_reserved2 : 5, - reserved_19b : 3; - uint32_t eht_special_aid12 : 12, - phy_version : 3, - bandwidth_ext : 2, - eht_spatial_reuse : 8, - u_sig_reserved1 : 7; - uint32_t eht_trigger_special_user_info_71_40 : 32; - uint32_t __reserved_g_0035 : 1, - __reserved_g_0035_trigger_subtype : 4, - blackout_details_en : 1, - uhr_trig_response : 1, - mcs_ext : 1, - dso_primary20_index_select : 4, - dso_icf_reception : 1, - dru_spreading_bw : 2, - dru_indication_per_80mhz : 4, - coding_type_ext : 1, - pad_duration : 5, - ects_as_tb_ppdu : 1, - reserved_22a : 6; - uint32_t dso_cca_puncture_pattern : 16, - dso_freq_subband_channel_bonding_mask : 16; - uint32_t reserved_24a : 32; - uint32_t reserved_25a : 32; -#else - uint32_t rxpcu_pcie_l0_req_duration : 8, - rssi_comb : 8, - pre_rssi_comb : 8, - eht_trigger_response : 1, - txop_duration_all_ones : 1, - received_bandwidth : 3, - rx_trigger_frame_user_source : 2, - ax_trigger_source : 1; - uint32_t bss_color : 6, - he_trigger_reserved : 1, - he_trigger_ul_mcs : 2, - he_trigger_ul_target_rssi : 5, - he_trigger_dl_tx_power : 5, - he_trigger_ru_allocation : 8, - he_trigger_ul_ppdu_length : 5; - uint32_t ap_tx_power_lsb_part : 4, - ldpc_extra_symbol : 1, - stbc : 1, - number_of_ltfs : 3, - mu_mimo_ltf_mode : 1, - cp_ltf_size : 2, - bandwidth : 2, - carrier_sense : 1, - cascade_indication : 1, - lsig_response_length : 12, - trigger_type : 4; - uint32_t reserved_3b : 1, - he_siga_reserved : 9, - doppler : 1, - spatial_reuse : 16, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - ap_tx_power_msb_part : 2; - uint32_t number_of_spatial_stream : 3, - start_spatial_stream : 3, - dcm : 1, - mcs : 4, - ru_allocation : 9, - aid12 : 12; - uint32_t bar_control_tid_info : 4, - bar_control_reserved : 9, - bar_control_compressed_bitmap : 1, - bar_control_multi_tid : 1, - bar_control_ack_policy : 1, - prefered_ac : 2, - reserved_5b : 1, - tid_aggregation_limit : 3, - mpdu_mu_spacing_factor : 2, - coding_type : 1, - target_rssi : 7; - uint32_t nr0_start_seq_ctrl_start_seq_number : 12, - nr0_start_seq_ctrl_frag_number : 4, - nr0_per_tid_info_tid_value : 4, - nr0_per_tid_info_reserved : 12; - uint32_t nr1_start_seq_ctrl_start_seq_number : 12, - nr1_start_seq_ctrl_frag_number : 4, - nr1_per_tid_info_tid_value : 4, - nr1_per_tid_info_reserved : 12; - uint32_t nr2_start_seq_ctrl_start_seq_number : 12, - nr2_start_seq_ctrl_frag_number : 4, - nr2_per_tid_info_tid_value : 4, - nr2_per_tid_info_reserved : 12; - uint32_t nr3_start_seq_ctrl_start_seq_number : 12, - nr3_start_seq_ctrl_frag_number : 4, - nr3_per_tid_info_tid_value : 4, - nr3_per_tid_info_reserved : 12; - uint32_t nr4_start_seq_ctrl_start_seq_number : 12, - nr4_start_seq_ctrl_frag_number : 4, - nr4_per_tid_info_tid_value : 4, - nr4_per_tid_info_reserved : 12; - uint32_t nr5_start_seq_ctrl_start_seq_number : 12, - nr5_start_seq_ctrl_frag_number : 4, - nr5_per_tid_info_tid_value : 4, - nr5_per_tid_info_reserved : 12; - uint32_t nr6_start_seq_ctrl_start_seq_number : 12, - nr6_start_seq_ctrl_frag_number : 4, - nr6_per_tid_info_tid_value : 4, - nr6_per_tid_info_reserved : 12; - uint32_t nr7_start_seq_ctrl_start_seq_number : 12, - nr7_start_seq_ctrl_frag_number : 4, - nr7_per_tid_info_tid_value : 4, - nr7_per_tid_info_reserved : 12; - uint32_t dot11be_puncture_bitmap : 16, - u_sig_puncture_pattern_encoding : 6, - reserved_14a : 2, - fb_segment_retransmission_bitmap : 8; - uint32_t rx_chain_mask_type : 1, - scrambler_seed : 7, - rx_duration_field : 16, - rx_chain_mask : 8; - uint32_t normalized_rssi_comb : 8, - normalized_pre_rssi_comb : 8; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint32_t response_tx_duration : 16, - sw_peer_id : 16; - uint32_t qos_null_only_response_tx : 1, - reserved_18a : 1, - tbr_trigger_sound_reserved_25_24 : 2, - i2r_rep : 3, - tbr_trigger_sound_reserved_20_12 : 9, - tbr_trigger_common_info_79_68 : 12, - __reserved_g_0022_trigger_subtype : 4; - uint32_t reserved_19b : 3, - u_sig_reserved2 : 5, - reserved_19a : 8, - tbr_trigger_sound_sac : 16; - uint32_t u_sig_reserved1 : 7, - eht_spatial_reuse : 8, - bandwidth_ext : 2, - phy_version : 3, - eht_special_aid12 : 12; - uint32_t eht_trigger_special_user_info_71_40 : 32; - uint32_t reserved_22a : 6, - ects_as_tb_ppdu : 1, - pad_duration : 5, - coding_type_ext : 1, - dru_indication_per_80mhz : 4, - dru_spreading_bw : 2, - dso_icf_reception : 1, - dso_primary20_index_select : 4, - mcs_ext : 1, - uhr_trig_response : 1, - blackout_details_en : 1, - __reserved_g_0035_trigger_subtype : 4, - __reserved_g_0035 : 1; - uint32_t dso_freq_subband_channel_bonding_mask : 16, - dso_cca_puncture_pattern : 16; - uint32_t reserved_24a : 32; - uint32_t reserved_25a : 32; -#endif -}; - -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000001 - -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x0000000000000006 - -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x0000000000000038 - -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x0000000000000040 - -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x0000000000000080 - -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x000000000000ff00 - -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x0000000000ff0000 - -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0x00000000ff000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 32 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 36 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f00000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 37 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 44 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 45 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 49 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e00000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 50 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 54 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 55 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 56 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x0180000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 57 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 57 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x0200000000000000 - -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 58 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 63 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc00000000000000 - -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f - -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x000000000000fff0 - -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x0000000000010000 - -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x0000000000020000 - -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x00000000000c0000 - -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x0000000000300000 - -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x0000000000400000 - -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x0000000003800000 - -#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26 -#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26 -#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x0000000004000000 - -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000008000000 - -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0x00000000f0000000 - -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 32 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 33 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x0000000300000000 - -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 34 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 35 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c00000000 - -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 36 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 36 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000001000000000 - -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 37 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 52 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe000000000 - -#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 53 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 53 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x0020000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 54 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 62 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc0000000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x8000000000000000 - -#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0 -#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11 -#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x00000000001ff000 - -#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21 -#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24 -#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x0000000001e00000 - -#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25 -#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25 -#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x0000000002000000 - -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x000000001c000000 - -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0x00000000e0000000 - -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 32 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 38 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f00000000 - -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 39 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 39 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x0000008000000000 - -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 40 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 41 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x0000030000000000 - -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 42 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 44 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c0000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 45 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 45 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x0000200000000000 - -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 46 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 47 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c00000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 48 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 48 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x0001000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 49 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 49 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x0002000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 50 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 50 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x0004000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 51 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 59 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff8000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 60 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 63 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf000000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x00000000000000ff - -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x0000000000000300 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x000000000000fc00 - -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0x00000000ffff0000 - -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 32 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 39 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff00000000 - -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 40 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 55 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff0000000000 - -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 56 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 62 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f00000000000000 - -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 63 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x8000000000000000 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 - -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 - -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 48 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff000000000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x000000000000fff0 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x0000000001ff0000 - -#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x000000000e000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x0000000030000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x0000000040000000 - -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x0000000080000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 32 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 47 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 48 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 55 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff000000000000 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 56 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 60 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f00000000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 61 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe000000000000000 - -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x0000000000007000 - -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x0000000000018000 - -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x0000000001fe0000 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0x00000000fe000000 - -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 32 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 63 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff00000000 - -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_LSB 5 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MSB 5 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MASK 0x0000000000000020 - -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_LSB 6 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MSB 6 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MASK 0x0000000000000040 - -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_LSB 7 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MSB 7 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MASK 0x0000000000000080 - -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_LSB 8 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MSB 11 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MASK 0x0000000000000f00 - -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MSB 12 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MASK 0x0000000000001000 - -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_LSB 13 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MSB 14 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MASK 0x0000000000006000 - -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_LSB 15 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MSB 18 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MASK 0x0000000000078000 - -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_LSB 19 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MSB 19 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MASK 0x0000000000080000 - -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_LSB 20 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MSB 24 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MASK 0x0000000001f00000 - -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB 25 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB 25 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK 0x0000000002000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_LSB 26 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MASK 0x00000000fc000000 - -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_LSB 32 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MSB 47 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 48 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 63 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0xffff000000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_LSB 0 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MASK 0x00000000ffffffff - -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_LSB 32 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/pcu_ppdu_setup_init.h b/drivers/staging/fw-api/hw/fig/v1/pcu_ppdu_setup_init.h deleted file mode 100644 index 621b649df965..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/pcu_ppdu_setup_init.h +++ /dev/null @@ -1,2309 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PCU_PPDU_SETUP_INIT_H_ -#define _PCU_PPDU_SETUP_INIT_H_ - -#include "pdg_response_rate_setting.h" -#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58 - -#define NUM_OF_QWORDS_PCU_PPDU_SETUP_INIT 29 - -struct pcu_ppdu_setup_init { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t medium_prot_type : 3, - response_type : 5, - response_info_part2_required : 1, - response_to_response : 3, - mba_user_order : 2, - expected_mba_size : 11, - required_ul_mu_resp_user_count : 6, - transmitted_bssid_check_en : 1; - uint32_t mprot_required_bw1 : 1, - mprot_required_bw20 : 1, - mprot_required_bw40 : 1, - mprot_required_bw80 : 1, - mprot_required_bw160 : 1, - mprot_required_bw240 : 1, - mprot_required_bw320 : 1, - ppdu_allowed_bw1 : 1, - ppdu_allowed_bw20 : 1, - ppdu_allowed_bw40 : 1, - ppdu_allowed_bw80 : 1, - ppdu_allowed_bw160 : 1, - ppdu_allowed_bw240 : 1, - ppdu_allowed_bw320 : 1, - set_fc_pwr_mgt : 1, - use_cts_duration_for_data_tx : 1, - update_timestamp_64 : 1, - update_timestamp_32_lower : 1, - update_timestamp_32_upper : 1, - reserved_1a : 13; - uint32_t insert_timestamp_offset_0 : 16, - insert_timestamp_offset_1 : 16; - uint32_t max_bw40_try_count : 4, - max_bw80_try_count : 4, - max_bw160_try_count : 4, - max_bw240_try_count : 4, - max_bw320_try_count : 4, - insert_wur_timestamp_offset : 6, - update_wur_timestamp : 1, - wur_embedded_bssid_present : 1, - insert_wur_fcs : 1, - reserved_3b : 3; - struct pdg_response_rate_setting response_to_response_rate_info_bw20; - struct pdg_response_rate_setting response_to_response_rate_info_bw40; - struct pdg_response_rate_setting response_to_response_rate_info_bw80; - struct pdg_response_rate_setting response_to_response_rate_info_bw160; - struct pdg_response_rate_setting response_to_response_rate_info_bw240; - struct pdg_response_rate_setting response_to_response_rate_info_bw320; - uint32_t r2r_hw_response_tx_duration : 16, - r2r_rx_duration_field : 16; - uint32_t r2r_group_id : 6, - r2r_response_frame_type : 4, - r2r_sta_partial_aid : 11, - use_address_fields_for_protection : 1, - r2r_set_required_response_time : 1, - reserved_29a : 3, - r2r_bw20_active_channel : 3, - r2r_bw40_active_channel : 3; - uint32_t r2r_bw80_active_channel : 3, - r2r_bw160_active_channel : 3, - r2r_bw240_active_channel : 3, - r2r_bw320_active_channel : 3, - r2r_bw20 : 3, - r2r_bw40 : 3, - r2r_bw80 : 3, - r2r_bw160 : 3, - r2r_bw240 : 3, - r2r_bw320 : 3, - tx_with_blackout_details : 1, - expect_rx_with_blackout_details : 1; - uint32_t mu_response_expected_bitmap_31_0 : 32; - uint32_t mu_response_expected_bitmap_36_32 : 5, - mu_expected_response_cbf_count : 6, - mu_expected_response_sta_count : 6, - transmit_includes_multidestination : 1, - insert_prev_tx_start_timing_info : 1, - insert_current_tx_start_timing_info : 1, - tx_start_transmit_time_byte_offset : 12; - uint32_t protection_frame_ad1_31_0 : 32; - uint32_t protection_frame_ad1_47_32 : 16, - protection_frame_ad2_15_0 : 16; - uint32_t protection_frame_ad2_47_16 : 32; - uint32_t dynamic_medium_prot_threshold : 24, - dynamic_medium_prot_type : 1, - reserved_54a : 7; - uint32_t protection_frame_ad3_31_0 : 32; - uint32_t protection_frame_ad3_47_32 : 16, - protection_frame_ad4_15_0 : 16; - uint32_t protection_frame_ad4_47_16 : 32; -#else - uint32_t transmitted_bssid_check_en : 1, - required_ul_mu_resp_user_count : 6, - expected_mba_size : 11, - mba_user_order : 2, - response_to_response : 3, - response_info_part2_required : 1, - response_type : 5, - medium_prot_type : 3; - uint32_t reserved_1a : 13, - update_timestamp_32_upper : 1, - update_timestamp_32_lower : 1, - update_timestamp_64 : 1, - use_cts_duration_for_data_tx : 1, - set_fc_pwr_mgt : 1, - ppdu_allowed_bw320 : 1, - ppdu_allowed_bw240 : 1, - ppdu_allowed_bw160 : 1, - ppdu_allowed_bw80 : 1, - ppdu_allowed_bw40 : 1, - ppdu_allowed_bw20 : 1, - ppdu_allowed_bw1 : 1, - mprot_required_bw320 : 1, - mprot_required_bw240 : 1, - mprot_required_bw160 : 1, - mprot_required_bw80 : 1, - mprot_required_bw40 : 1, - mprot_required_bw20 : 1, - mprot_required_bw1 : 1; - uint32_t insert_timestamp_offset_1 : 16, - insert_timestamp_offset_0 : 16; - uint32_t reserved_3b : 3, - insert_wur_fcs : 1, - wur_embedded_bssid_present : 1, - update_wur_timestamp : 1, - insert_wur_timestamp_offset : 6, - max_bw320_try_count : 4, - max_bw240_try_count : 4, - max_bw160_try_count : 4, - max_bw80_try_count : 4, - max_bw40_try_count : 4; - struct pdg_response_rate_setting response_to_response_rate_info_bw20; - struct pdg_response_rate_setting response_to_response_rate_info_bw40; - struct pdg_response_rate_setting response_to_response_rate_info_bw80; - struct pdg_response_rate_setting response_to_response_rate_info_bw160; - struct pdg_response_rate_setting response_to_response_rate_info_bw240; - struct pdg_response_rate_setting response_to_response_rate_info_bw320; - uint32_t r2r_rx_duration_field : 16, - r2r_hw_response_tx_duration : 16; - uint32_t r2r_bw40_active_channel : 3, - r2r_bw20_active_channel : 3, - reserved_29a : 3, - r2r_set_required_response_time : 1, - use_address_fields_for_protection : 1, - r2r_sta_partial_aid : 11, - r2r_response_frame_type : 4, - r2r_group_id : 6; - uint32_t expect_rx_with_blackout_details : 1, - tx_with_blackout_details : 1, - r2r_bw320 : 3, - r2r_bw240 : 3, - r2r_bw160 : 3, - r2r_bw80 : 3, - r2r_bw40 : 3, - r2r_bw20 : 3, - r2r_bw320_active_channel : 3, - r2r_bw240_active_channel : 3, - r2r_bw160_active_channel : 3, - r2r_bw80_active_channel : 3; - uint32_t mu_response_expected_bitmap_31_0 : 32; - uint32_t tx_start_transmit_time_byte_offset : 12, - insert_current_tx_start_timing_info : 1, - insert_prev_tx_start_timing_info : 1, - transmit_includes_multidestination : 1, - mu_expected_response_sta_count : 6, - mu_expected_response_cbf_count : 6, - mu_response_expected_bitmap_36_32 : 5; - uint32_t protection_frame_ad1_31_0 : 32; - uint32_t protection_frame_ad2_15_0 : 16, - protection_frame_ad1_47_32 : 16; - uint32_t protection_frame_ad2_47_16 : 32; - uint32_t reserved_54a : 7, - dynamic_medium_prot_type : 1, - dynamic_medium_prot_threshold : 24; - uint32_t protection_frame_ad3_31_0 : 32; - uint32_t protection_frame_ad4_15_0 : 16, - protection_frame_ad3_47_32 : 16; - uint32_t protection_frame_ad4_47_16 : 32; -#endif -}; - -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB 0 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB 2 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK 0x0000000000000007 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK 0x00000000000000f8 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0000000000000100 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK 0x0000000000000e00 - -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB 12 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB 13 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK 0x0000000000003000 - -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB 14 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB 24 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK 0x0000000001ffc000 - -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB 25 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB 30 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK 0x000000007e000000 - -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB 31 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB 31 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB 32 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB 32 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB 33 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB 33 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK 0x0000000200000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB 34 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB 34 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK 0x0000000400000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB 35 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB 35 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK 0x0000000800000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB 36 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB 36 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK 0x0000001000000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB 37 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB 37 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK 0x0000002000000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB 38 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB 38 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK 0x0000004000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB 39 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB 39 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB 40 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB 40 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK 0x0000010000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB 41 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB 41 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK 0x0000020000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB 42 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB 42 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB 43 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB 43 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB 44 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB 44 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB 45 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB 45 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB 46 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB 46 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB 47 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB 47 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB 48 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB 48 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK 0x0001000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB 49 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB 49 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK 0x0002000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB 50 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB 50 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK 0x0004000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK 0xfff8000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB 0 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB 15 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB 32 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB 35 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB 36 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB 39 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB 40 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB 43 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK 0x00000f0000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB 44 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB 47 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK 0x0000f00000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB 48 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB 51 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK 0x000f000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB 52 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB 57 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB 58 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB 58 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB 59 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB 59 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK 0x0800000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB 60 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB 60 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK 0x1000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK 0xe000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB 15 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB 16 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB 31 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB 37 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK 0x0000003f00000000 - -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB 38 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB 41 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK 0x000003c000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB 42 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB 52 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK 0x001ffc0000000000 - -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB 53 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB 53 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB 54 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB 54 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK 0x0040000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB 55 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK 0x0380000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB 58 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB 60 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK 0x1c00000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB 61 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB 63 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK 0xe000000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB 0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB 2 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK 0x0000000000000007 - -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB 3 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB 5 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK 0x0000000000000038 - -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB 6 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB 8 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK 0x00000000000001c0 - -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB 9 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB 11 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK 0x0000000000000e00 - -#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB 12 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB 14 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK 0x0000000000007000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB 15 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB 17 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK 0x0000000000038000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB 18 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB 20 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB 21 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB 23 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK 0x0000000000e00000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB 24 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB 26 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK 0x0000000007000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB 27 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB 29 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_LSB 30 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MSB 30 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB 31 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB 31 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB 4 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB 5 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB 10 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK 0x00000000000007e0 - -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB 11 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB 16 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK 0x000000000001f800 - -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB 17 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB 17 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK 0x0000000000020000 - -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB 18 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB 18 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK 0x0000000000040000 - -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB 19 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB 19 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB 20 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB 31 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK 0x00000000fff00000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB 15 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB 16 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB 31 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB 0 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB 23 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK 0x0000000000ffffff - -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB 24 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB 24 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK 0x00000000fe000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB 15 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB 16 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB 31 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/pdg_response.h b/drivers/staging/fw-api/hw/fig/v1/pdg_response.h deleted file mode 100644 index a730a445ed10..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/pdg_response.h +++ /dev/null @@ -1,503 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_RESPONSE_H_ -#define _PDG_RESPONSE_H_ - -#include "pdg_response_rate_setting.h" -#define NUM_OF_DWORDS_PDG_RESPONSE 14 - -#define NUM_OF_QWORDS_PDG_RESPONSE 7 - -struct pdg_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct pdg_response_rate_setting hw_response_rate_info; - uint32_t hw_response_tx_duration : 16, - rx_duration_field : 16; - uint32_t punctured_response_transmission : 1, - cca_subband_channel_bonding_mask : 16, - scrambler_seed_override : 2, - response_density_valid : 1, - response_density : 5, - more_data : 1, - duration_indication : 1, - blackout_details_en : 1, - reserved_8a : 1, - bandwidth : 3; - uint32_t ack_id : 16, - block_ack_bitmap : 16; - uint32_t response_frame_type : 4, - ack_id_ext : 10, - ftm_en : 1, - group_id : 6, - sta_partial_aid : 11; - uint32_t ndp_ba_start_seq_ctrl : 12, - active_channel : 3, - txop_duration_all_ones : 1, - frame_length : 16; - uint32_t dso_primary20_index_select : 4, - dso_freq_subband_channel_bonding_mask : 16, - pad_duration : 5, - reserved_12a : 7; - uint32_t tlv64_padding : 32; -#else - struct pdg_response_rate_setting hw_response_rate_info; - uint32_t rx_duration_field : 16, - hw_response_tx_duration : 16; - uint32_t bandwidth : 3, - reserved_8a : 1, - blackout_details_en : 1, - duration_indication : 1, - more_data : 1, - response_density : 5, - response_density_valid : 1, - scrambler_seed_override : 2, - cca_subband_channel_bonding_mask : 16, - punctured_response_transmission : 1; - uint32_t block_ack_bitmap : 16, - ack_id : 16; - uint32_t sta_partial_aid : 11, - group_id : 6, - ftm_en : 1, - ack_id_ext : 10, - response_frame_type : 4; - uint32_t frame_length : 16, - txop_duration_all_ones : 1, - active_channel : 3, - ndp_ba_start_seq_ctrl : 12; - uint32_t reserved_12a : 7, - pad_duration : 5, - dso_freq_subband_channel_bonding_mask : 16, - dso_primary20_index_select : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x0000000000000001 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x000000001e000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x0000000020000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x0000000040000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x0000000080000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 48 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 50 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x0007000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 58 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 59 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 61 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x3800000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 62 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 62 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MSB 3 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MASK 0x000000000000000f - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x0000000000000070 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x0000000000000080 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x000000000000ff00 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 36 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 37 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000e000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 41 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x0000030000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 46 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00007c0000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_LSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 48 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 55 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 56 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x0000000000000001 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0x00000000f8000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 41 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 43 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 45 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 46 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 50 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 52 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 57 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f0000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff00000000 - -#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 48 -#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 63 -#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff000000000000 - -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x0000000000000001 - -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000000000001fffe - -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x0000000000060000 - -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x0000000000080000 - -#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20 -#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24 -#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x0000000001f00000 - -#define PDG_RESPONSE_MORE_DATA_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_MORE_DATA_LSB 25 -#define PDG_RESPONSE_MORE_DATA_MSB 25 -#define PDG_RESPONSE_MORE_DATA_MASK 0x0000000002000000 - -#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_DURATION_INDICATION_LSB 26 -#define PDG_RESPONSE_DURATION_INDICATION_MSB 26 -#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x0000000004000000 - -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_LSB 27 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MSB 27 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MASK 0x0000000008000000 - -#define PDG_RESPONSE_RESERVED_8A_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_RESERVED_8A_LSB 28 -#define PDG_RESPONSE_RESERVED_8A_MSB 28 -#define PDG_RESPONSE_RESERVED_8A_MASK 0x0000000010000000 - -#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BANDWIDTH_LSB 29 -#define PDG_RESPONSE_BANDWIDTH_MSB 31 -#define PDG_RESPONSE_BANDWIDTH_MASK 0x00000000e0000000 - -#define PDG_RESPONSE_ACK_ID_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_ACK_ID_LSB 32 -#define PDG_RESPONSE_ACK_ID_MSB 47 -#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff00000000 - -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 48 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 63 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff000000000000 - -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x000000000000000f - -#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_ACK_ID_EXT_LSB 4 -#define PDG_RESPONSE_ACK_ID_EXT_MSB 13 -#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x0000000000003ff0 - -#define PDG_RESPONSE_FTM_EN_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_FTM_EN_LSB 14 -#define PDG_RESPONSE_FTM_EN_MSB 14 -#define PDG_RESPONSE_FTM_EN_MASK 0x0000000000004000 - -#define PDG_RESPONSE_GROUP_ID_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_GROUP_ID_LSB 15 -#define PDG_RESPONSE_GROUP_ID_MSB 20 -#define PDG_RESPONSE_GROUP_ID_MASK 0x00000000001f8000 - -#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21 -#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31 -#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0x00000000ffe00000 - -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 32 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 43 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff00000000 - -#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 44 -#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 46 -#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x0000700000000000 - -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 47 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 47 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x0000800000000000 - -#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_FRAME_LENGTH_LSB 48 -#define PDG_RESPONSE_FRAME_LENGTH_MSB 63 -#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff000000000000 - -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_LSB 0 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MSB 3 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MASK 0x000000000000000f - -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 4 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 19 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x00000000000ffff0 - -#define PDG_RESPONSE_PAD_DURATION_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_PAD_DURATION_LSB 20 -#define PDG_RESPONSE_PAD_DURATION_MSB 24 -#define PDG_RESPONSE_PAD_DURATION_MASK 0x0000000001f00000 - -#define PDG_RESPONSE_RESERVED_12A_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_RESERVED_12A_LSB 25 -#define PDG_RESPONSE_RESERVED_12A_MSB 31 -#define PDG_RESPONSE_RESERVED_12A_MASK 0x00000000fe000000 - -#define PDG_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_TLV64_PADDING_LSB 32 -#define PDG_RESPONSE_TLV64_PADDING_MSB 63 -#define PDG_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/pdg_response_rate_setting.h b/drivers/staging/fw-api/hw/fig/v1/pdg_response_rate_setting.h deleted file mode 100644 index eb123386f2bf..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/pdg_response_rate_setting.h +++ /dev/null @@ -1,409 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_RESPONSE_RATE_SETTING_H_ -#define _PDG_RESPONSE_RATE_SETTING_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7 - -struct pdg_response_rate_setting { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 1, - tx_antenna_sector_ctrl : 24, - pkt_type : 4, - smoothing : 1, - ldpc : 1, - stbc : 1; - uint32_t alt_tx_pwr : 8, - alt_min_tx_pwr : 8, - alt_nss : 3, - alt_tx_chain_mask : 8, - alt_bw : 3, - stf_ltf_3db_boost : 1, - force_extra_symbol : 1; - uint32_t reserved_2a : 4, - nss : 3, - dpd_enable : 1, - tx_pwr : 8, - min_tx_pwr : 8, - tx_chain_mask : 8; - uint32_t alt_rate_mcs : 5, - reserved_3a : 3, - sgi : 2, - rate_mcs : 5, - ldpc_2x_codeword : 1, - tx_pwr_1 : 8, - alt_tx_pwr_1 : 8; - uint32_t aggregation : 1, - dot11ax_bss_color_id : 6, - dot11ax_spatial_reuse : 4, - dot11ax_cp_ltf_size : 2, - dot11ax_dcm : 1, - dot11ax_doppler_indication : 1, - dot11ax_su_extended : 1, - dot11ax_min_packet_extension : 2, - dot11ax_pe_nss : 3, - dot11ax_pe_content : 1, - dot11ax_pe_ltf_size : 2, - dot11ax_chain_csd_en : 1, - dot11ax_pe_chain_csd_en : 1, - dot11ax_dl_ul_flag : 1, - reserved_4a : 5; - uint32_t dot11ax_ext_ru_start_index : 4, - dot11ax_ext_ru_size : 4, - eht_duplicate_mode : 2, - he_sigb_dcm : 1, - he_sigb_0_mcs : 3, - num_he_sigb_sym : 5, - required_response_time_source : 1, - reserved_5a : 6, - u_sig_puncture_pattern_encoding : 6; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t required_response_time : 12, - dot11be_params_placeholder : 4; -#else - uint32_t stbc : 1, - ldpc : 1, - smoothing : 1, - pkt_type : 4, - tx_antenna_sector_ctrl : 24, - reserved_0a : 1; - uint32_t force_extra_symbol : 1, - stf_ltf_3db_boost : 1, - alt_bw : 3, - alt_tx_chain_mask : 8, - alt_nss : 3, - alt_min_tx_pwr : 8, - alt_tx_pwr : 8; - uint32_t tx_chain_mask : 8, - min_tx_pwr : 8, - tx_pwr : 8, - dpd_enable : 1, - nss : 3, - reserved_2a : 4; - uint32_t alt_tx_pwr_1 : 8, - tx_pwr_1 : 8, - ldpc_2x_codeword : 1, - rate_mcs : 5, - sgi : 2, - reserved_3a : 3, - alt_rate_mcs : 5; - uint32_t reserved_4a : 5, - dot11ax_dl_ul_flag : 1, - dot11ax_pe_chain_csd_en : 1, - dot11ax_chain_csd_en : 1, - dot11ax_pe_ltf_size : 2, - dot11ax_pe_content : 1, - dot11ax_pe_nss : 3, - dot11ax_min_packet_extension : 2, - dot11ax_su_extended : 1, - dot11ax_doppler_indication : 1, - dot11ax_dcm : 1, - dot11ax_cp_ltf_size : 2, - dot11ax_spatial_reuse : 4, - dot11ax_bss_color_id : 6, - aggregation : 1; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_5a : 6, - required_response_time_source : 1, - num_he_sigb_sym : 5, - he_sigb_0_mcs : 3, - he_sigb_dcm : 1, - eht_duplicate_mode : 2, - dot11ax_ext_ru_size : 4, - dot11ax_ext_ru_start_index : 4; - uint32_t dot11be_params_placeholder : 4, - required_response_time : 12; - struct mlo_sta_id_details mlo_sta_id_details_rx; -#endif -}; - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001 - -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe - -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000 - -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000 - -#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30 -#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30 -#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000 - -#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31 -#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff - -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00 - -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000 - -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000 - -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MSB 3 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MASK 0x0000000f - -#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4 -#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6 -#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070 - -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080 - -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00 - -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000 - -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 4 -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000001f - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 5 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000e0 - -#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300 - -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 14 -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00007c00 - -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_LSB 15 -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MASK 0x00008000 - -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000 - -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 - -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300 - -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400 - -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800 - -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000 - -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000 - -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 - -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/pdg_tx_req.h b/drivers/staging/fw-api/hw/fig/v1/pdg_tx_req.h deleted file mode 100644 index 6baf640807da..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/pdg_tx_req.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_TX_REQ_H_ -#define _PDG_TX_REQ_H_ - -#define NUM_OF_DWORDS_PDG_TX_REQ 2 - -#define NUM_OF_QWORDS_PDG_TX_REQ 1 - -struct pdg_tx_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_reason : 2, - use_puncture_pattern : 2, - req_bw : 3, - puncture_pattern_number : 6, - reserved_0b : 1, - req_paprd : 1, - duration_field_boundary_valid : 1, - duration_field_boundary : 16; - uint32_t puncture_subband_mask : 16, - reserved_0c : 16; -#else - uint32_t duration_field_boundary : 16, - duration_field_boundary_valid : 1, - req_paprd : 1, - reserved_0b : 1, - puncture_pattern_number : 6, - req_bw : 3, - use_puncture_pattern : 2, - tx_reason : 2; - uint32_t reserved_0c : 16, - puncture_subband_mask : 16; -#endif -}; - -#define PDG_TX_REQ_TX_REASON_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_TX_REASON_LSB 0 -#define PDG_TX_REQ_TX_REASON_MSB 1 -#define PDG_TX_REQ_TX_REASON_MASK 0x0000000000000003 - -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x000000000000000c - -#define PDG_TX_REQ_REQ_BW_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_REQ_BW_LSB 4 -#define PDG_TX_REQ_REQ_BW_MSB 6 -#define PDG_TX_REQ_REQ_BW_MASK 0x0000000000000070 - -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x0000000000001f80 - -#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_RESERVED_0B_LSB 13 -#define PDG_TX_REQ_RESERVED_0B_MSB 13 -#define PDG_TX_REQ_RESERVED_0B_MASK 0x0000000000002000 - -#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_REQ_PAPRD_LSB 14 -#define PDG_TX_REQ_REQ_PAPRD_MSB 14 -#define PDG_TX_REQ_REQ_PAPRD_MASK 0x0000000000004000 - -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x0000000000008000 - -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0x00000000ffff0000 - -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 32 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 47 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff00000000 - -#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_RESERVED_0C_LSB 48 -#define PDG_TX_REQ_RESERVED_0C_MSB 63 -#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_abort_request_info.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_abort_request_info.h deleted file mode 100644 index 1f3bf4b817b9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_abort_request_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_ABORT_REQUEST_INFO_H_ -#define _PHYRX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 - -struct phyrx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phyrx_abort_reason : 8, - phy_enters_nap_state : 1, - phy_enters_defer_state : 1, - gain_change_by_main : 1, - gain_change_by_bt : 1, - main_tx_indication : 1, - bt_tx_indication : 1, - concurrent_mode : 1, - reserved_0 : 1, - receive_duration : 16; -#else - uint32_t receive_duration : 16, - reserved_0 : 1, - concurrent_mode : 1, - bt_tx_indication : 1, - main_tx_indication : 1, - gain_change_by_bt : 1, - gain_change_by_main : 1, - phy_enters_defer_state : 1, - phy_enters_nap_state : 1, - phyrx_abort_reason : 8; -#endif -}; - -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff - -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100 - -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 - -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_LSB 10 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MSB 10 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MASK 0x00000400 - -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_LSB 11 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MSB 11 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MASK 0x00000800 - -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_LSB 12 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MSB 12 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MASK 0x00001000 - -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_LSB 13 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MSB 13 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MASK 0x00002000 - -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_LSB 14 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MSB 14 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MASK 0x00004000 - -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 15 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x00008000 - -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_common_user_info.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_common_user_info.h deleted file mode 100644 index 1aac5bf9fd32..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_common_user_info.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_COMMON_USER_INFO_H_ -#define _PHYRX_COMMON_USER_INFO_H_ - -#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4 - -#define NUM_OF_QWORDS_PHYRX_COMMON_USER_INFO 2 - -struct phyrx_common_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t receive_duration : 16, - reserved_0a : 16; - uint32_t u_sig_puncture_pattern_encoding : 6, - eht___reserved_g_0022_ndp : 1, - reserved_1a : 8, - obss_nav_update_enable : 1, - obss_nav_value : 16; - uint32_t eht_or_uhr_ppdu_type : 2, - bss_color_id : 6, - dl_ul_flag : 1, - txop_duration : 7, - cp_setting : 2, - ltf_size : 2, - spatial_reuse : 4, - rx_ndp : 1, - dot11bn_su_elr : 1, - reserved_2a : 6; - uint32_t eht_duplicate : 2, - eht_or_uhr_sig_cmn_field_type : 2, - doppler_indication : 1, - sta_id : 11, - puncture_bitmap : 16; -#else - uint32_t reserved_0a : 16, - receive_duration : 16; - uint32_t obss_nav_value : 16, - obss_nav_update_enable : 1, - reserved_1a : 8, - eht___reserved_g_0022_ndp : 1, - u_sig_puncture_pattern_encoding : 6; - uint32_t reserved_2a : 6, - dot11bn_su_elr : 1, - rx_ndp : 1, - spatial_reuse : 4, - ltf_size : 2, - cp_setting : 2, - txop_duration : 7, - dl_ul_flag : 1, - bss_color_id : 6, - eht_or_uhr_ppdu_type : 2; - uint32_t puncture_bitmap : 16, - sta_id : 11, - doppler_indication : 1, - eht_or_uhr_sig_cmn_field_type : 2, - eht_duplicate : 2; -#endif -}; - -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x000000000000ffff - -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0x00000000ffff0000 - -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 32 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 37 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f00000000 - -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 39 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 46 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0x00007f8000000000 - -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_LSB 47 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MSB 47 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MASK 0x0000800000000000 - -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_LSB 48 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MSB 63 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MASK 0xffff000000000000 - -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_LSB 0 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MSB 1 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MASK 0x0000000000000003 - -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x00000000000000fc - -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x0000000000000100 - -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x000000000000fe00 - -#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x0000000000030000 - -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x00000000000c0000 - -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x0000000000f00000 - -#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24 -#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24 -#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x0000000001000000 - -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_LSB 25 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MSB 25 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MASK 0x0000000002000000 - -#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB 26 -#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB 31 -#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK 0x00000000fc000000 - -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 32 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 33 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x0000000300000000 - -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_LSB 34 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MSB 35 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MASK 0x0000000c00000000 - -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 36 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 36 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x0000001000000000 - -#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 37 -#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 47 -#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe000000000 - -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 48 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 63 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_mu_dl.h deleted file mode 100644 index da4f1691b9f7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_mu_dl.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_MU_DL_H_ -#define _PHYRX_HE_SIG_A_MU_DL_H_ - -#include "he_sig_a_mu_dl_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_DL 1 - -struct phyrx_he_sig_a_mu_dl { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; -#else - struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_mu_ul.h deleted file mode 100644 index ff9cf72a7237..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_mu_ul.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_MU_UL_H_ -#define _PHYRX_HE_SIG_A_MU_UL_H_ - -#include "he_sig_a_mu_ul_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_UL 1 - -struct phyrx_he_sig_a_mu_ul { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; -#else - struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_su.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_su.h deleted file mode 100644 index abca58673a90..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_a_su.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_SU_H_ -#define _PHYRX_HE_SIG_A_SU_H_ - -#include "he_sig_a_su_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_SU 1 - -struct phyrx_he_sig_a_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; -#else - struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b1_mu.h deleted file mode 100644 index ae784469331b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b1_mu.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B1_MU_H_ -#define _PHYRX_HE_SIG_B1_MU_H_ - -#include "he_sig_b1_mu_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1 - -struct phyrx_he_sig_b1_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#else - struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b2_mu.h deleted file mode 100644 index 6035ecffde5d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b2_mu.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B2_MU_H_ -#define _PHYRX_HE_SIG_B2_MU_H_ - -#include "he_sig_b2_mu_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_MU 1 - -struct phyrx_he_sig_b2_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; -#else - struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; -#endif -}; - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b2_ofdma.h deleted file mode 100644 index 126a9559e155..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_he_sig_b2_ofdma.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_ -#define _PHYRX_HE_SIG_B2_OFDMA_H_ - -#include "he_sig_b2_ofdma_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_OFDMA 1 - -struct phyrx_he_sig_b2_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; -#else - struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; -#endif -}; - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_ht_sig.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_ht_sig.h deleted file mode 100644 index 4dd90653d431..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_ht_sig.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HT_SIG_H_ -#define _PHYRX_HT_SIG_H_ - -#include "ht_sig_info.h" -#define NUM_OF_DWORDS_PHYRX_HT_SIG 2 - -#define NUM_OF_QWORDS_PHYRX_HT_SIG 1 - -struct phyrx_ht_sig { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ht_sig_info phyrx_ht_sig_info_details; -#else - struct ht_sig_info phyrx_ht_sig_info_details; -#endif -}; - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 36 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 37 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 42 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 49 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_l_sig_a.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_l_sig_a.h deleted file mode 100644 index 2e70822f5d06..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_l_sig_a.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_L_SIG_A_H_ -#define _PHYRX_L_SIG_A_H_ - -#include "l_sig_a_info.h" -#define NUM_OF_DWORDS_PHYRX_L_SIG_A 2 - -#define NUM_OF_QWORDS_PHYRX_L_SIG_A 1 - -struct phyrx_l_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_a_info phyrx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_a_info phyrx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_TLV64_PADDING_LSB 32 -#define PHYRX_L_SIG_A_TLV64_PADDING_MSB 63 -#define PHYRX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_l_sig_b.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_l_sig_b.h deleted file mode 100644 index 461edd24dd4e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_l_sig_b.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_L_SIG_B_H_ -#define _PHYRX_L_SIG_B_H_ - -#include "l_sig_b_info.h" -#define NUM_OF_DWORDS_PHYRX_L_SIG_B 2 - -#define NUM_OF_QWORDS_PHYRX_L_SIG_B 1 - -struct phyrx_l_sig_b { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_b_info phyrx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_b_info phyrx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_TLV64_PADDING_LSB 32 -#define PHYRX_L_SIG_B_TLV64_PADDING_MSB 63 -#define PHYRX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_location.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_location.h deleted file mode 100644 index 15a8413e304a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_location.h +++ /dev/null @@ -1,332 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_LOCATION_H_ -#define _PHYRX_LOCATION_H_ - -#include "rx_location_info.h" -#define NUM_OF_DWORDS_PHYRX_LOCATION 28 - -#define NUM_OF_QWORDS_PHYRX_LOCATION 14 - -struct phyrx_location { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_location_info rx_location_info_details; -#else - struct rx_location_info rx_location_info_details; -#endif -}; - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x0000000000000001 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x0000000000000002 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x00000000000000f0 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x000000000000ff00 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x0000000000ff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0x00000000ff000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 39 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 40 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff0000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 55 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 56 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff00000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0x00000000ffffffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 39 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 40 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff0000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 51 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 52 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 55 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f0000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 56 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff00000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000000000ff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000000ff000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x0000000000000018 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0x00000000ffffffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000000000000018 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x00000000000000ff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x000000000000ff00 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_other_receive_info_ru_details.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_other_receive_info_ru_details.h deleted file mode 100644 index a6090f721e1d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_other_receive_info_ru_details.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ -#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ - -#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4 - -#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2 - -struct phyrx_other_receive_info_ru_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_details_channel_0 : 32; - uint32_t ru_details_channel_1 : 32; - uint32_t spare : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t ru_details_channel_0 : 32; - uint32_t ru_details_channel_1 : 32; - uint32_t spare : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0x00000000ffffffff - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff00000000 - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x0000000000000008 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0x00000000ffffffff - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000008 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_pkt_end.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_pkt_end.h deleted file mode 100644 index 1d1675edc0e1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_pkt_end.h +++ /dev/null @@ -1,427 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_PKT_END_H_ -#define _PHYRX_PKT_END_H_ - -#include "phyrx_pkt_end_info.h" -#define NUM_OF_DWORDS_PHYRX_PKT_END 24 - -#define NUM_OF_QWORDS_PHYRX_PKT_END 12 - -struct phyrx_pkt_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct phyrx_pkt_end_info rx_pkt_end_details; -#else - struct phyrx_pkt_end_info rx_pkt_end_details; -#endif -}; - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x0000000000000002 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x0000000000000004 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x0000000000000008 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x0000000000000010 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x0000000000000020 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x00000000000000c0 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0x00000000ffff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB 44 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB 53 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK 0x003ff00000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_LSB 54 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xffc0000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000000000000058 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000000000000058 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_pkt_end_info.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_pkt_end_info.h deleted file mode 100644 index a21edc94d24e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_pkt_end_info.h +++ /dev/null @@ -1,450 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_PKT_END_INFO_H_ -#define _PHYRX_PKT_END_INFO_H_ - -#include "receive_rssi_info.h" -#include "rx_timing_info.h" -#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24 - -struct phyrx_pkt_end_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t __reserved_g_0001 : 1, - location_info_valid : 1, - timing_info_valid : 1, - rssi_info_valid : 1, - reserved_0a : 1, - frameless_frame_received : 1, - reserved_0b : 2, - rssi_comb : 8, - reserved_0c : 16; - struct rx_timing_info rx_timing_info_details; - struct receive_rssi_info post_rssi_info_details; - uint32_t phy_sw_status_31_0 : 32; - uint32_t phy_sw_status_63_32 : 32; -#else - uint32_t reserved_0c : 16, - rssi_comb : 8, - reserved_0b : 2, - frameless_frame_received : 1, - reserved_0a : 1, - rssi_info_valid : 1, - timing_info_valid : 1, - location_info_valid : 1, - __reserved_g_0001 : 1; - struct rx_timing_info rx_timing_info_details; - struct receive_rssi_info post_rssi_info_details; - uint32_t phy_sw_status_31_0 : 32; - uint32_t phy_sw_status_63_32 : 32; -#endif -}; - -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002 - -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004 - -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008 - -#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4 -#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4 -#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010 - -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 - -#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6 -#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7 -#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0 - -#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8 -#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15 -#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16 -#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31 -#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000 - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB 12 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB 21 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK 0x003ff000 - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_LSB 22 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xffc00000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_rssi_legacy.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_rssi_legacy.h deleted file mode 100644 index 820ced6212ca..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_rssi_legacy.h +++ /dev/null @@ -1,806 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_RSSI_LEGACY_H_ -#define _PHYRX_RSSI_LEGACY_H_ - -#include "receive_rssi_info.h" -#include "receive_pkt_start_info.h" -#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42 - -#define NUM_OF_QWORDS_PHYRX_RSSI_LEGACY 21 - -struct phyrx_rssi_legacy { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_pkt_start_info rx_pkt_start_details; - uint32_t sw_phy_meta_data : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 32; - struct receive_rssi_info pre_rssi_info_details; - struct receive_rssi_info preamble_rssi_info_details; - uint32_t pre_rssi_comb : 8, - rssi_comb : 8, - normalized_pre_rssi_comb : 8, - normalized_rssi_comb : 8; - uint32_t rssi_comb_ppdu : 8, - rssi_db_to_dbm_offset : 8, - rssi_for_spatial_reuse : 8, - rssi_for_trigger_resp : 8; -#else - struct receive_pkt_start_info rx_pkt_start_details; - uint32_t sw_phy_meta_data : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 32; - struct receive_rssi_info pre_rssi_info_details; - struct receive_rssi_info preamble_rssi_info_details; - uint32_t normalized_rssi_comb : 8, - normalized_pre_rssi_comb : 8, - rssi_comb : 8, - pre_rssi_comb : 8; - uint32_t rssi_for_trigger_resp : 8, - rssi_for_spatial_reuse : 8, - rssi_db_to_dbm_offset : 8, - rssi_comb_ppdu : 8; -#endif -}; - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_LSB 0 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MSB 3 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MASK 0x000000000000000f - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_LSB 4 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MSB 4 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x0000000000000010 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB 5 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB 7 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK 0x00000000000000e0 - -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB 8 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB 15 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_LSB 16 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MSB 31 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_LSB 32 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MSB 63 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_LSB 32 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MSB 39 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_LSB 40 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MSB 40 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MASK 0x0000010000000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_LSB 41 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MSB 63 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MASK 0xfffffe0000000000 - -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x0000000000000010 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 0 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 31 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x0000000000000010 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 32 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 63 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x0000000000000018 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000000000000018 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 32 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 63 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 32 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 39 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 40 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 47 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 48 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 55 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 56 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 63 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_user_info.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_user_info.h deleted file mode 100644 index d3dc8b6b2414..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_user_info.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_USER_INFO_H_ -#define _PHYRX_USER_INFO_H_ - -#include "receive_user_info.h" -#define NUM_OF_DWORDS_PHYRX_USER_INFO 8 - -#define NUM_OF_QWORDS_PHYRX_USER_INFO 4 - -struct phyrx_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_user_info receive_user_info_details; -#else - struct receive_user_info receive_user_info_details; -#endif -}; - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 36 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000001f00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 37 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 38 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000006000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 1 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x0000000000000002 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB 2 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB 3 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK 0x000000000000000c - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB 4 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB 5 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK 0x0000000000000030 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB 6 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB 7 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK 0x00000000000000c0 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 62 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc000000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phyrx_vht_sig_a.h b/drivers/staging/fw-api/hw/fig/v1/phyrx_vht_sig_a.h deleted file mode 100644 index e47f0e35adeb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phyrx_vht_sig_a.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_VHT_SIG_A_H_ -#define _PHYRX_VHT_SIG_A_H_ - -#include "vht_sig_a_info.h" -#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2 - -#define NUM_OF_QWORDS_PHYRX_VHT_SIG_A 1 - -struct phyrx_vht_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_a_info phyrx_vht_sig_a_info_details; -#else - struct vht_sig_a_info phyrx_vht_sig_a_info_details; -#endif -}; - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phytx_abort_request_info.h b/drivers/staging/fw-api/hw/fig/v1/phytx_abort_request_info.h deleted file mode 100644 index e4800f6a2d97..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phytx_abort_request_info.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_ABORT_REQUEST_INFO_H_ -#define _PHYTX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1 - -struct phytx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t phytx_abort_reason : 8, - user_number : 6, - reserved : 2; -#else - uint16_t reserved : 2, - user_number : 6, - phytx_abort_reason : 8; -#endif -}; - -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff - -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00 - -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phytx_pkt_end.h b/drivers/staging/fw-api/hw/fig/v1/phytx_pkt_end.h deleted file mode 100644 index 55911ea9edb3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phytx_pkt_end.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_PKT_END_H_ -#define _PHYTX_PKT_END_H_ - -#define NUM_OF_WORDS_PHYTX_PKT_END 28 - -#define NUM_OF_DWORDS_PHYTX_PKT_END 14 - -struct phytx_pkt_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t start_of_frame_timestamp_15_0 : 16; - uint16_t start_of_frame_timestamp_31_16 : 16; - uint16_t end_of_frame_timestamp_15_0 : 16; - uint16_t end_of_frame_timestamp_31_16 : 16; - uint16_t tx_group_delay : 12, - timing_status : 2, - phyrx_entered_nap_state : 1, - dpdtrain_done : 1; - uint16_t transmit_delay : 16; - uint16_t tpc_dbg_info_cmn_15_0 : 16; - uint16_t tpc_dbg_info_cmn_31_16 : 16; - uint16_t tpc_dbg_info_cmn_47_32 : 16; - uint16_t tpc_dbg_info_chn1_15_0 : 16; - uint16_t tpc_dbg_info_chn1_31_16 : 16; - uint16_t tpc_dbg_info_chn1_47_32 : 16; - uint16_t tpc_dbg_info_chn1_63_48 : 16; - uint16_t tpc_dbg_info_chn1_79_64 : 16; - uint16_t tpc_dbg_info_chn2_15_0 : 16; - uint16_t tpc_dbg_info_chn2_31_16 : 16; - uint16_t tpc_dbg_info_chn2_47_32 : 16; - uint16_t tpc_dbg_info_chn2_63_48 : 16; - uint16_t tpc_dbg_info_chn2_79_64 : 16; - uint16_t phytx_tx_end_sw_info_15_0 : 16; - uint16_t phytx_tx_end_sw_info_31_16 : 16; - uint16_t phytx_tx_end_sw_info_47_32 : 16; - uint16_t phytx_tx_end_sw_info_63_48 : 16; - uint16_t beamform_masked_user_bitmap_15_0 : 16; - uint16_t beamform_masked_user_bitmap_31_16 : 16; - uint16_t beamform_masked_user_bitmap_36_32 : 5, - reserved_23 : 11; - uint16_t reserved_26 : 16; - uint16_t reserved_27 : 16; -#else - uint16_t start_of_frame_timestamp_15_0 : 16; - uint16_t start_of_frame_timestamp_31_16 : 16; - uint16_t end_of_frame_timestamp_15_0 : 16; - uint16_t end_of_frame_timestamp_31_16 : 16; - uint16_t dpdtrain_done : 1, - phyrx_entered_nap_state : 1, - timing_status : 2, - tx_group_delay : 12; - uint16_t transmit_delay : 16; - uint16_t tpc_dbg_info_cmn_15_0 : 16; - uint16_t tpc_dbg_info_cmn_31_16 : 16; - uint16_t tpc_dbg_info_cmn_47_32 : 16; - uint16_t tpc_dbg_info_chn1_15_0 : 16; - uint16_t tpc_dbg_info_chn1_31_16 : 16; - uint16_t tpc_dbg_info_chn1_47_32 : 16; - uint16_t tpc_dbg_info_chn1_63_48 : 16; - uint16_t tpc_dbg_info_chn1_79_64 : 16; - uint16_t tpc_dbg_info_chn2_15_0 : 16; - uint16_t tpc_dbg_info_chn2_31_16 : 16; - uint16_t tpc_dbg_info_chn2_47_32 : 16; - uint16_t tpc_dbg_info_chn2_63_48 : 16; - uint16_t tpc_dbg_info_chn2_79_64 : 16; - uint16_t phytx_tx_end_sw_info_15_0 : 16; - uint16_t phytx_tx_end_sw_info_31_16 : 16; - uint16_t phytx_tx_end_sw_info_47_32 : 16; - uint16_t phytx_tx_end_sw_info_63_48 : 16; - uint16_t beamform_masked_user_bitmap_15_0 : 16; - uint16_t beamform_masked_user_bitmap_31_16 : 16; - uint16_t reserved_23 : 11, - beamform_masked_user_bitmap_36_32 : 5; - uint16_t reserved_26 : 16; - uint16_t reserved_27 : 16; -#endif -}; - -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000000 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000002 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 0 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 15 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000004 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000006 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 0 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 15 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TX_GROUP_DELAY_OFFSET 0x00000008 -#define PHYTX_PKT_END_TX_GROUP_DELAY_LSB 0 -#define PHYTX_PKT_END_TX_GROUP_DELAY_MSB 11 -#define PHYTX_PKT_END_TX_GROUP_DELAY_MASK 0x00000fff - -#define PHYTX_PKT_END_TIMING_STATUS_OFFSET 0x00000008 -#define PHYTX_PKT_END_TIMING_STATUS_LSB 12 -#define PHYTX_PKT_END_TIMING_STATUS_MSB 13 -#define PHYTX_PKT_END_TIMING_STATUS_MASK 0x00003000 - -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_OFFSET 0x00000008 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_LSB 14 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MSB 14 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MASK 0x00004000 - -#define PHYTX_PKT_END_DPDTRAIN_DONE_OFFSET 0x00000008 -#define PHYTX_PKT_END_DPDTRAIN_DONE_LSB 15 -#define PHYTX_PKT_END_DPDTRAIN_DONE_MSB 15 -#define PHYTX_PKT_END_DPDTRAIN_DONE_MASK 0x00008000 - -#define PHYTX_PKT_END_TRANSMIT_DELAY_OFFSET 0x0000000a -#define PHYTX_PKT_END_TRANSMIT_DELAY_LSB 0 -#define PHYTX_PKT_END_TRANSMIT_DELAY_MSB 15 -#define PHYTX_PKT_END_TRANSMIT_DELAY_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000c -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000e -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_OFFSET 0x00000010 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x00000012 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x00000014 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x00000016 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x00000018 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000001a -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000001c -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000001e -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x00000020 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x00000022 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x00000024 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x00000026 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x00000028 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000002a -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000002c -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000002e -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x00000030 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 15 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x00000032 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 4 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x0000001f - -#define PHYTX_PKT_END_RESERVED_23_OFFSET 0x00000032 -#define PHYTX_PKT_END_RESERVED_23_LSB 5 -#define PHYTX_PKT_END_RESERVED_23_MSB 15 -#define PHYTX_PKT_END_RESERVED_23_MASK 0x0000ffe0 - -#define PHYTX_PKT_END_RESERVED_26_OFFSET 0x00000034 -#define PHYTX_PKT_END_RESERVED_26_LSB 0 -#define PHYTX_PKT_END_RESERVED_26_MSB 15 -#define PHYTX_PKT_END_RESERVED_26_MASK 0x0000ffff - -#define PHYTX_PKT_END_RESERVED_27_OFFSET 0x00000036 -#define PHYTX_PKT_END_RESERVED_27_LSB 0 -#define PHYTX_PKT_END_RESERVED_27_MSB 15 -#define PHYTX_PKT_END_RESERVED_27_MASK 0x0000ffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/phytx_ppdu_header_info_request.h b/drivers/staging/fw-api/hw/fig/v1/phytx_ppdu_header_info_request.h deleted file mode 100644 index 7fbecae41236..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/phytx_ppdu_header_info_request.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ -#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ - -#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2 - -#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1 - -struct phytx_ppdu_header_info_request { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t request_type : 5, - reserved : 11; - uint16_t tlv32_padding : 16; -#else - uint16_t reserved : 11, - request_type : 5; - uint16_t tlv32_padding : 16; -#endif -}; - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0 - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/receive_pkt_start_info.h b/drivers/staging/fw-api/hw/fig/v1/receive_pkt_start_info.h deleted file mode 100644 index 7f7c81449a15..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/receive_pkt_start_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_PKT_START_INFO_H_ -#define _RECEIVE_PKT_START_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_PKT_START_INFO 4 - -struct receive_pkt_start_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reception_type : 4, - rx_chain_mask_type : 1, - receive_bandwidth : 3, - rx_chain_mask : 8, - phy_ppdu_id : 16; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t preamble_time_to_rxframe : 8, - standalone_sniffer_mode : 1, - reserved_3a : 23; -#else - uint32_t phy_ppdu_id : 16, - rx_chain_mask : 8, - receive_bandwidth : 3, - rx_chain_mask_type : 1, - reception_type : 4; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t reserved_3a : 23, - standalone_sniffer_mode : 1, - preamble_time_to_rxframe : 8; -#endif -}; - -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_LSB 0 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MSB 3 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MASK 0x0000000f - -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_LSB 4 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MSB 4 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MASK 0x00000010 - -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_LSB 5 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MSB 7 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MASK 0x000000e0 - -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_LSB 8 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MSB 15 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MASK 0x0000ff00 - -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_LSB 16 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MSB 31 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MASK 0xffff0000 - -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff - -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff - -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_LSB 0 -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MSB 7 -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff - -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_LSB 8 -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MSB 8 -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MASK 0x00000100 - -#define RECEIVE_PKT_START_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_RESERVED_3A_LSB 9 -#define RECEIVE_PKT_START_INFO_RESERVED_3A_MSB 31 -#define RECEIVE_PKT_START_INFO_RESERVED_3A_MASK 0xfffffe00 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/receive_rssi_info.h b/drivers/staging/fw-api/hw/fig/v1/receive_rssi_info.h deleted file mode 100644 index 9aaa98217d99..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/receive_rssi_info.h +++ /dev/null @@ -1,465 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_RSSI_INFO_H_ -#define _RECEIVE_RSSI_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16 - -struct receive_rssi_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rssi_pri20_chain0 : 8, - rssi_ext20_chain0 : 8, - rssi_ext40_low20_chain0 : 8, - rssi_ext40_high20_chain0 : 8; - uint32_t rssi_ext80_low20_chain0 : 8, - rssi_ext80_low_high20_chain0 : 8, - rssi_ext80_high_low20_chain0 : 8, - rssi_ext80_high20_chain0 : 8; - uint32_t rssi_ext160_0_chain0 : 8, - rssi_ext160_1_chain0 : 8, - rssi_ext160_2_chain0 : 8, - rssi_ext160_3_chain0 : 8; - uint32_t rssi_ext160_4_chain0 : 8, - rssi_ext160_5_chain0 : 8, - rssi_ext160_6_chain0 : 8, - rssi_ext160_7_chain0 : 8; - uint32_t rssi_pri20_chain1 : 8, - rssi_ext20_chain1 : 8, - rssi_ext40_low20_chain1 : 8, - rssi_ext40_high20_chain1 : 8; - uint32_t rssi_ext80_low20_chain1 : 8, - rssi_ext80_low_high20_chain1 : 8, - rssi_ext80_high_low20_chain1 : 8, - rssi_ext80_high20_chain1 : 8; - uint32_t rssi_ext160_0_chain1 : 8, - rssi_ext160_1_chain1 : 8, - rssi_ext160_2_chain1 : 8, - rssi_ext160_3_chain1 : 8; - uint32_t rssi_ext160_4_chain1 : 8, - rssi_ext160_5_chain1 : 8, - rssi_ext160_6_chain1 : 8, - rssi_ext160_7_chain1 : 8; - uint32_t rssi_pri20_chain2 : 8, - rssi_ext20_chain2 : 8, - rssi_ext40_low20_chain2 : 8, - rssi_ext40_high20_chain2 : 8; - uint32_t rssi_ext80_low20_chain2 : 8, - rssi_ext80_low_high20_chain2 : 8, - rssi_ext80_high_low20_chain2 : 8, - rssi_ext80_high20_chain2 : 8; - uint32_t rssi_ext160_0_chain2 : 8, - rssi_ext160_1_chain2 : 8, - rssi_ext160_2_chain2 : 8, - rssi_ext160_3_chain2 : 8; - uint32_t rssi_ext160_4_chain2 : 8, - rssi_ext160_5_chain2 : 8, - rssi_ext160_6_chain2 : 8, - rssi_ext160_7_chain2 : 8; - uint32_t rssi_pri20_chain3 : 8, - rssi_ext20_chain3 : 8, - rssi_ext40_low20_chain3 : 8, - rssi_ext40_high20_chain3 : 8; - uint32_t rssi_ext80_low20_chain3 : 8, - rssi_ext80_low_high20_chain3 : 8, - rssi_ext80_high_low20_chain3 : 8, - rssi_ext80_high20_chain3 : 8; - uint32_t rssi_ext160_0_chain3 : 8, - rssi_ext160_1_chain3 : 8, - rssi_ext160_2_chain3 : 8, - rssi_ext160_3_chain3 : 8; - uint32_t rssi_ext160_4_chain3 : 8, - rssi_ext160_5_chain3 : 8, - rssi_ext160_6_chain3 : 8, - rssi_ext160_7_chain3 : 8; -#else - uint32_t rssi_ext40_high20_chain0 : 8, - rssi_ext40_low20_chain0 : 8, - rssi_ext20_chain0 : 8, - rssi_pri20_chain0 : 8; - uint32_t rssi_ext80_high20_chain0 : 8, - rssi_ext80_high_low20_chain0 : 8, - rssi_ext80_low_high20_chain0 : 8, - rssi_ext80_low20_chain0 : 8; - uint32_t rssi_ext160_3_chain0 : 8, - rssi_ext160_2_chain0 : 8, - rssi_ext160_1_chain0 : 8, - rssi_ext160_0_chain0 : 8; - uint32_t rssi_ext160_7_chain0 : 8, - rssi_ext160_6_chain0 : 8, - rssi_ext160_5_chain0 : 8, - rssi_ext160_4_chain0 : 8; - uint32_t rssi_ext40_high20_chain1 : 8, - rssi_ext40_low20_chain1 : 8, - rssi_ext20_chain1 : 8, - rssi_pri20_chain1 : 8; - uint32_t rssi_ext80_high20_chain1 : 8, - rssi_ext80_high_low20_chain1 : 8, - rssi_ext80_low_high20_chain1 : 8, - rssi_ext80_low20_chain1 : 8; - uint32_t rssi_ext160_3_chain1 : 8, - rssi_ext160_2_chain1 : 8, - rssi_ext160_1_chain1 : 8, - rssi_ext160_0_chain1 : 8; - uint32_t rssi_ext160_7_chain1 : 8, - rssi_ext160_6_chain1 : 8, - rssi_ext160_5_chain1 : 8, - rssi_ext160_4_chain1 : 8; - uint32_t rssi_ext40_high20_chain2 : 8, - rssi_ext40_low20_chain2 : 8, - rssi_ext20_chain2 : 8, - rssi_pri20_chain2 : 8; - uint32_t rssi_ext80_high20_chain2 : 8, - rssi_ext80_high_low20_chain2 : 8, - rssi_ext80_low_high20_chain2 : 8, - rssi_ext80_low20_chain2 : 8; - uint32_t rssi_ext160_3_chain2 : 8, - rssi_ext160_2_chain2 : 8, - rssi_ext160_1_chain2 : 8, - rssi_ext160_0_chain2 : 8; - uint32_t rssi_ext160_7_chain2 : 8, - rssi_ext160_6_chain2 : 8, - rssi_ext160_5_chain2 : 8, - rssi_ext160_4_chain2 : 8; - uint32_t rssi_ext40_high20_chain3 : 8, - rssi_ext40_low20_chain3 : 8, - rssi_ext20_chain3 : 8, - rssi_pri20_chain3 : 8; - uint32_t rssi_ext80_high20_chain3 : 8, - rssi_ext80_high_low20_chain3 : 8, - rssi_ext80_low_high20_chain3 : 8, - rssi_ext80_low20_chain3 : 8; - uint32_t rssi_ext160_3_chain3 : 8, - rssi_ext160_2_chain3 : 8, - rssi_ext160_1_chain3 : 8, - rssi_ext160_0_chain3 : 8; - uint32_t rssi_ext160_7_chain3 : 8, - rssi_ext160_6_chain3 : 8, - rssi_ext160_5_chain3 : 8, - rssi_ext160_4_chain3 : 8; -#endif -}; - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/receive_user_info.h b/drivers/staging/fw-api/hw/fig/v1/receive_user_info.h deleted file mode 100644 index 23daabab5dc8..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/receive_user_info.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_USER_INFO_H_ -#define _RECEIVE_USER_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8 - -struct receive_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - user_rssi : 8, - pkt_type : 4, - stbc : 1, - reception_type : 3; - uint32_t rate_mcs : 5, - sgi : 2, - __reserved_g_0004 : 1, - mimo_ss_bitmap : 8, - receive_bandwidth : 3, - reserved_1b : 5, - dl_ofdma_user_index : 8; - uint32_t dl_ofdma_content_channel : 1, - reserved_2a : 1, - qam_diff1 : 2, - qam_diff2 : 2, - qam_diff3 : 2, - nss : 3, - stream_offset : 3, - sta_dcm : 1, - ldpc : 1, - ru_type_80_0 : 4, - ru_type_80_1 : 4, - ru_type_80_2 : 4, - ru_type_80_3 : 4; - uint32_t ru_start_index_80_0 : 6, - reserved_3a : 2, - ru_start_index_80_1 : 6, - reserved_3b : 2, - ru_start_index_80_2 : 6, - reserved_3c : 2, - ru_start_index_80_3 : 6, - reserved_3d : 2; - uint32_t user_fd_rssi_seg0 : 32; - uint32_t user_fd_rssi_seg1 : 32; - uint32_t user_fd_rssi_seg2 : 32; - uint32_t user_fd_rssi_seg3 : 32; -#else - uint32_t reception_type : 3, - stbc : 1, - pkt_type : 4, - user_rssi : 8, - phy_ppdu_id : 16; - uint32_t dl_ofdma_user_index : 8, - reserved_1b : 5, - receive_bandwidth : 3, - mimo_ss_bitmap : 8, - __reserved_g_0004 : 1, - sgi : 2, - rate_mcs : 5; - uint32_t ru_type_80_3 : 4, - ru_type_80_2 : 4, - ru_type_80_1 : 4, - ru_type_80_0 : 4, - ldpc : 1, - sta_dcm : 1, - stream_offset : 3, - nss : 3, - qam_diff3 : 2, - qam_diff2 : 2, - qam_diff1 : 2, - reserved_2a : 1, - dl_ofdma_content_channel : 1; - uint32_t reserved_3d : 2, - ru_start_index_80_3 : 6, - reserved_3c : 2, - ru_start_index_80_2 : 6, - reserved_3b : 2, - ru_start_index_80_1 : 6, - reserved_3a : 2, - ru_start_index_80_0 : 6; - uint32_t user_fd_rssi_seg0 : 32; - uint32_t user_fd_rssi_seg1 : 32; - uint32_t user_fd_rssi_seg2 : 32; - uint32_t user_fd_rssi_seg3 : 32; -#endif -}; - -#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff - -#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_USER_RSSI_LSB 16 -#define RECEIVE_USER_INFO_USER_RSSI_MSB 23 -#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000 - -#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24 -#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27 -#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000 - -#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_STBC_LSB 28 -#define RECEIVE_USER_INFO_STBC_MSB 28 -#define RECEIVE_USER_INFO_STBC_MASK 0x10000000 - -#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000 - -#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RATE_MCS_LSB 0 -#define RECEIVE_USER_INFO_RATE_MCS_MSB 4 -#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000001f - -#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_SGI_LSB 5 -#define RECEIVE_USER_INFO_SGI_MSB 6 -#define RECEIVE_USER_INFO_SGI_MASK 0x00000060 - -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00 - -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000 - -#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19 -#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23 -#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000 - -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000 - -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 - -#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1 -#define RECEIVE_USER_INFO_RESERVED_2A_MSB 1 -#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x00000002 - -#define RECEIVE_USER_INFO_QAM_DIFF1_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF1_LSB 2 -#define RECEIVE_USER_INFO_QAM_DIFF1_MSB 3 -#define RECEIVE_USER_INFO_QAM_DIFF1_MASK 0x0000000c - -#define RECEIVE_USER_INFO_QAM_DIFF2_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF2_LSB 4 -#define RECEIVE_USER_INFO_QAM_DIFF2_MSB 5 -#define RECEIVE_USER_INFO_QAM_DIFF2_MASK 0x00000030 - -#define RECEIVE_USER_INFO_QAM_DIFF3_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF3_LSB 6 -#define RECEIVE_USER_INFO_QAM_DIFF3_MSB 7 -#define RECEIVE_USER_INFO_QAM_DIFF3_MASK 0x000000c0 - -#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_NSS_LSB 8 -#define RECEIVE_USER_INFO_NSS_MSB 10 -#define RECEIVE_USER_INFO_NSS_MASK 0x00000700 - -#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11 -#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13 -#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800 - -#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_STA_DCM_LSB 14 -#define RECEIVE_USER_INFO_STA_DCM_MSB 14 -#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000 - -#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_LDPC_LSB 15 -#define RECEIVE_USER_INFO_LDPC_MSB 15 -#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f - -#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6 -#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7 -#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00 - -#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14 -#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15 -#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000 - -#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22 -#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23 -#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000 - -#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30 -#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31 -#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000 - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/received_response_user_15_8.h b/drivers/staging/fw-api/hw/fig/v1/received_response_user_15_8.h deleted file mode 100644 index 6cf8117ff02f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/received_response_user_15_8.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_15_8_H_ -#define _RECEIVED_RESPONSE_USER_15_8_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_15_8 32 - -struct received_response_user_15_8 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user8; - struct received_response_user_info received_response_details_user9; - struct received_response_user_info received_response_details_user10; - struct received_response_user_info received_response_details_user11; - struct received_response_user_info received_response_details_user12; - struct received_response_user_info received_response_details_user13; - struct received_response_user_info received_response_details_user14; - struct received_response_user_info received_response_details_user15; -#else - struct received_response_user_info received_response_details_user8; - struct received_response_user_info received_response_details_user9; - struct received_response_user_info received_response_details_user10; - struct received_response_user_info received_response_details_user11; - struct received_response_user_info received_response_details_user12; - struct received_response_user_info received_response_details_user13; - struct received_response_user_info received_response_details_user14; - struct received_response_user_info received_response_details_user15; -#endif -}; - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/received_response_user_23_16.h b/drivers/staging/fw-api/hw/fig/v1/received_response_user_23_16.h deleted file mode 100644 index ff56f4d96472..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/received_response_user_23_16.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_23_16_H_ -#define _RECEIVED_RESPONSE_USER_23_16_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_23_16 32 - -struct received_response_user_23_16 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user16; - struct received_response_user_info received_response_details_user17; - struct received_response_user_info received_response_details_user18; - struct received_response_user_info received_response_details_user19; - struct received_response_user_info received_response_details_user20; - struct received_response_user_info received_response_details_user21; - struct received_response_user_info received_response_details_user22; - struct received_response_user_info received_response_details_user23; -#else - struct received_response_user_info received_response_details_user16; - struct received_response_user_info received_response_details_user17; - struct received_response_user_info received_response_details_user18; - struct received_response_user_info received_response_details_user19; - struct received_response_user_info received_response_details_user20; - struct received_response_user_info received_response_details_user21; - struct received_response_user_info received_response_details_user22; - struct received_response_user_info received_response_details_user23; -#endif -}; - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/received_response_user_31_24.h b/drivers/staging/fw-api/hw/fig/v1/received_response_user_31_24.h deleted file mode 100644 index aaa90838daa9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/received_response_user_31_24.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_31_24_H_ -#define _RECEIVED_RESPONSE_USER_31_24_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_31_24 32 - -struct received_response_user_31_24 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user24; - struct received_response_user_info received_response_details_user25; - struct received_response_user_info received_response_details_user26; - struct received_response_user_info received_response_details_user27; - struct received_response_user_info received_response_details_user28; - struct received_response_user_info received_response_details_user29; - struct received_response_user_info received_response_details_user30; - struct received_response_user_info received_response_details_user31; -#else - struct received_response_user_info received_response_details_user24; - struct received_response_user_info received_response_details_user25; - struct received_response_user_info received_response_details_user26; - struct received_response_user_info received_response_details_user27; - struct received_response_user_info received_response_details_user28; - struct received_response_user_info received_response_details_user29; - struct received_response_user_info received_response_details_user30; - struct received_response_user_info received_response_details_user31; -#endif -}; - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/received_response_user_36_32.h b/drivers/staging/fw-api/hw/fig/v1/received_response_user_36_32.h deleted file mode 100644 index 3f33fdab635e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/received_response_user_36_32.h +++ /dev/null @@ -1,705 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_36_32_H_ -#define _RECEIVED_RESPONSE_USER_36_32_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_36_32 20 - -struct received_response_user_36_32 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user32; - struct received_response_user_info received_response_details_user33; - struct received_response_user_info received_response_details_user34; - struct received_response_user_info received_response_details_user35; - struct received_response_user_info received_response_details_user36; -#else - struct received_response_user_info received_response_details_user32; - struct received_response_user_info received_response_details_user33; - struct received_response_user_info received_response_details_user34; - struct received_response_user_info received_response_details_user35; - struct received_response_user_info received_response_details_user36; -#endif -}; - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/received_response_user_7_0.h b/drivers/staging/fw-api/hw/fig/v1/received_response_user_7_0.h deleted file mode 100644 index f785aca46840..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/received_response_user_7_0.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_7_0_H_ -#define _RECEIVED_RESPONSE_USER_7_0_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_7_0 32 - -struct received_response_user_7_0 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user0; - struct received_response_user_info received_response_details_user1; - struct received_response_user_info received_response_details_user2; - struct received_response_user_info received_response_details_user3; - struct received_response_user_info received_response_details_user4; - struct received_response_user_info received_response_details_user5; - struct received_response_user_info received_response_details_user6; - struct received_response_user_info received_response_details_user7; -#else - struct received_response_user_info received_response_details_user0; - struct received_response_user_info received_response_details_user1; - struct received_response_user_info received_response_details_user2; - struct received_response_user_info received_response_details_user3; - struct received_response_user_info received_response_details_user4; - struct received_response_user_info received_response_details_user5; - struct received_response_user_info received_response_details_user6; - struct received_response_user_info received_response_details_user7; -#endif -}; - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/received_response_user_info.h b/drivers/staging/fw-api/hw/fig/v1/received_response_user_info.h deleted file mode 100644 index 3c3faf119635..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/received_response_user_info.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_INFO_H_ -#define _RECEIVED_RESPONSE_USER_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8 - -struct received_response_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mpdu_fcs_pass_count : 12, - mpdu_fcs_fail_count : 12, - qosnull_frame_count : 4, - reserved_0a : 3, - user_info_valid : 1; - uint32_t null_delimiter_count : 22, - reserved_1a : 9, - ht_control_valid : 1; - uint32_t ht_control : 32; - uint32_t qos_control_valid : 16, - eosp : 16; - uint32_t qos_control_15_8_tid_0 : 8, - qos_control_15_8_tid_1 : 8, - qos_control_15_8_tid_2 : 8, - qos_control_15_8_tid_3 : 8; - uint32_t qos_control_15_8_tid_4 : 8, - qos_control_15_8_tid_5 : 8, - qos_control_15_8_tid_6 : 8, - qos_control_15_8_tid_7 : 8; - uint32_t qos_control_15_8_tid_8 : 8, - qos_control_15_8_tid_9 : 8, - qos_control_15_8_tid_10 : 8, - qos_control_15_8_tid_11 : 8; - uint32_t qos_control_15_8_tid_12 : 8, - qos_control_15_8_tid_13 : 8, - qos_control_15_8_tid_14 : 8, - qos_control_15_8_tid_15 : 8; -#else - uint32_t user_info_valid : 1, - reserved_0a : 3, - qosnull_frame_count : 4, - mpdu_fcs_fail_count : 12, - mpdu_fcs_pass_count : 12; - uint32_t ht_control_valid : 1, - reserved_1a : 9, - null_delimiter_count : 22; - uint32_t ht_control : 32; - uint32_t eosp : 16, - qos_control_valid : 16; - uint32_t qos_control_15_8_tid_3 : 8, - qos_control_15_8_tid_2 : 8, - qos_control_15_8_tid_1 : 8, - qos_control_15_8_tid_0 : 8; - uint32_t qos_control_15_8_tid_7 : 8, - qos_control_15_8_tid_6 : 8, - qos_control_15_8_tid_5 : 8, - qos_control_15_8_tid_4 : 8; - uint32_t qos_control_15_8_tid_11 : 8, - qos_control_15_8_tid_10 : 8, - qos_control_15_8_tid_9 : 8, - qos_control_15_8_tid_8 : 8; - uint32_t qos_control_15_8_tid_15 : 8, - qos_control_15_8_tid_14 : 8, - qos_control_15_8_tid_13 : 8, - qos_control_15_8_tid_12 : 8; -#endif -}; - -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff - -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 - -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000 - -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000 - -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000 - -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff - -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000 - -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000 - -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff - -#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c -#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/received_trigger_info.h b/drivers/staging/fw-api/hw/fig/v1/received_trigger_info.h deleted file mode 100644 index 16d10249d075..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/received_trigger_info.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_TRIGGER_INFO_H_ -#define _RECEIVED_TRIGGER_INFO_H_ - -#include "received_trigger_info_details.h" -#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 6 - -#define NUM_OF_QWORDS_RECEIVED_TRIGGER_INFO 3 - -struct received_trigger_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_trigger_info_details received_trigger_details; -#else - struct received_trigger_info_details received_trigger_details; -#endif -}; - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000010 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000001e0 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x00000000003ffe00 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x0000000000400000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x0000000000800000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x0000000001000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_LSB 29 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MSB 30 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MASK 0x0000000060000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x0000000080000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 47 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 48 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 59 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_LSB 61 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MSB 61 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MASK 0x2000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB 62 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB 62 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK 0x4000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0x8000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x000000000000ffff - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0x00000000ffff0000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 48 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 56 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 61 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xe000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK 0x0000000100000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_LSB 33 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MSB 36 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MASK 0x0000001e00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_LSB 37 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MSB 39 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MASK 0x000000e000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_LSB 40 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MASK 0xffffff0000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/received_trigger_info_details.h b/drivers/staging/fw-api/hw/fig/v1/received_trigger_info_details.h deleted file mode 100644 index ebffe439b3b2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/received_trigger_info_details.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_ -#define _RECEIVED_TRIGGER_INFO_DETAILS_H_ - -#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 6 - -struct received_trigger_info_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t trigger_type : 4, - ax_trigger_source : 1, - ax_trigger_type : 4, - trigger_source_sta_full_aid : 13, - frame_control_valid : 1, - qos_control_valid : 1, - he_control_info_valid : 1, - __reserved_g_0022_trigger_subtype : 4, - txop_sharing_mode : 2, - tid_aggregation_limit_is_zero : 1; - uint32_t phy_ppdu_id : 16, - lsig_response_length : 12, - __reserved_g_0035 : 1, - scsid_valid : 1, - ects_as_tb_ppdu : 1, - reserved_1a : 1; - uint32_t frame_control : 16, - qos_control : 16; - uint32_t sw_peer_id : 16, - txop_sharing_allocation_duration : 9, - __reserved_g_0035_trigger_subtype : 4, - reserved_3a : 3; - uint32_t he_control : 32; - uint32_t txop_sharing_duration_from_durid : 1, - frame_durationid_lower_4 : 4, - frame_durationid_upper_3 : 3, - reserved_5a : 24; -#else - uint32_t tid_aggregation_limit_is_zero : 1, - txop_sharing_mode : 2, - __reserved_g_0022_trigger_subtype : 4, - he_control_info_valid : 1, - qos_control_valid : 1, - frame_control_valid : 1, - trigger_source_sta_full_aid : 13, - ax_trigger_type : 4, - ax_trigger_source : 1, - trigger_type : 4; - uint32_t reserved_1a : 1, - ects_as_tb_ppdu : 1, - scsid_valid : 1, - __reserved_g_0035 : 1, - lsig_response_length : 12, - phy_ppdu_id : 16; - uint32_t qos_control : 16, - frame_control : 16; - uint32_t reserved_3a : 3, - __reserved_g_0035_trigger_subtype : 4, - txop_sharing_allocation_duration : 9, - sw_peer_id : 16; - uint32_t he_control : 32; - uint32_t reserved_5a : 24, - frame_durationid_upper_3 : 3, - frame_durationid_lower_4 : 4, - txop_sharing_duration_from_durid : 1; -#endif -}; - -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f - -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 - -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_LSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MASK 0x20000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_LSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MASK 0x40000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0x80000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xe0000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK 0x00000001 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_LSB 1 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MASK 0x0000001e - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_LSB 5 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MSB 7 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MASK 0x000000e0 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_LSB 8 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MASK 0xffffff00 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/reo_destination_ring.h b/drivers/staging/fw-api/hw/fig/v1/reo_destination_ring.h deleted file mode 100644 index 5147635121c1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/reo_destination_ring.h +++ /dev/null @@ -1,305 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_DESTINATION_RING_H_ -#define _REO_DESTINATION_RING_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_mpdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_REO_DESTINATION_RING 8 - -struct reo_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t release_source_module : 3, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_delink_error : 1, - sw_buffer_cookie : 20; - uint32_t msdu_link_desc_index : 4, - reserved_6a : 28; - uint32_t reo_dest_buffer_type : 1, - reo_push_reason : 2, - reo_error_code : 5, - captured_msdu_data_size : 4, - sw_exception : 1, - src_link_id : 3, - reo_destination_struct_signature : 4, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t sw_buffer_cookie : 20, - reo_delink_error : 1, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - release_source_module : 3; - uint32_t reserved_6a : 28, - msdu_link_desc_index : 4; - uint32_t looping_count : 4, - ring_id : 8, - reo_destination_struct_signature : 4, - src_link_id : 3, - sw_exception : 1, - captured_msdu_data_size : 4, - reo_error_code : 5, - reo_push_reason : 2, - reo_dest_buffer_type : 1; -#endif -}; - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_OFFSET 0x00000014 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_LSB 3 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MSB 3 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MASK 0x00000008 - -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_LSB 4 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MSB 5 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MASK 0x00000030 - -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_LSB 6 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MSB 10 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MASK 0x000007c0 - -#define REO_DESTINATION_RING_REO_DELINK_ERROR_OFFSET 0x00000014 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_LSB 11 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_MSB 11 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_MASK 0x00000800 - -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_OFFSET 0x00000018 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_LSB 0 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MSB 3 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MASK 0x0000000f - -#define REO_DESTINATION_RING_RESERVED_6A_OFFSET 0x00000018 -#define REO_DESTINATION_RING_RESERVED_6A_LSB 4 -#define REO_DESTINATION_RING_RESERVED_6A_MSB 31 -#define REO_DESTINATION_RING_RESERVED_6A_MASK 0xfffffff0 - -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0 -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0 -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001 - -#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1 -#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2 -#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006 - -#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3 -#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7 -#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8 - -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8 -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11 -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 - -#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c -#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12 -#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12 -#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000 - -#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13 -#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15 -#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000 - -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 - -#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_RING_ID_LSB 20 -#define REO_DESTINATION_RING_RING_ID_MSB 27 -#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000 - -#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28 -#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31 -#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/reo_destination_ring_with_pn.h b/drivers/staging/fw-api/hw/fig/v1/reo_destination_ring_with_pn.h deleted file mode 100644 index b486a8658388..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/reo_destination_ring_with_pn.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_DESTINATION_RING_WITH_PN_H_ -#define _REO_DESTINATION_RING_WITH_PN_H_ - -#include "rx_msdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8 - -struct reo_destination_ring_with_pn { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - uint32_t msdu_count : 8, - prev_pn_23_0 : 24; - uint32_t prev_pn_47_24 : 24, - prev_pn_127_48_info : 2, - reserved_3a : 6; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t release_source_module : 3, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_delink_error : 1, - sw_buffer_cookie : 20; - uint32_t msdu_link_desc_index : 4, - reserved_6a : 28; - uint32_t reo_dest_buffer_type : 1, - reo_push_reason : 2, - reo_error_code : 5, - captured_msdu_data_size : 4, - sw_exception : 1, - src_link_id : 3, - reo_destination_struct_signature : 4, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - uint32_t prev_pn_23_0 : 24, - msdu_count : 8; - uint32_t reserved_3a : 6, - prev_pn_127_48_info : 2, - prev_pn_47_24 : 24; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t sw_buffer_cookie : 20, - reo_delink_error : 1, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - release_source_module : 3; - uint32_t reserved_6a : 28, - msdu_link_desc_index : 4; - uint32_t looping_count : 4, - ring_id : 8, - reo_destination_struct_signature : 4, - src_link_id : 3, - sw_exception : 1, - captured_msdu_data_size : 4, - reo_error_code : 5, - reo_push_reason : 2, - reo_dest_buffer_type : 1; -#endif -}; - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK 0x000000ff - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET 0x00000008 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK 0xffffff00 - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MSB 23 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MASK 0x00ffffff - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_LSB 24 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MSB 25 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MASK 0x03000000 - -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_LSB 26 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MASK 0xfc000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MSB 3 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MASK 0x00000008 - -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_LSB 4 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MSB 5 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MASK 0x00000030 - -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_LSB 6 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MSB 10 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MASK 0x000007c0 - -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_LSB 11 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MASK 0x00000800 - -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_OFFSET 0x00000018 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MSB 3 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MASK 0x0000000f - -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_OFFSET 0x00000018 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_LSB 4 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MASK 0xfffffff0 - -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB 0 -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK 0x00000001 - -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB 1 -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK 0x00000006 - -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK 0x000000f8 - -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 - -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK 0x00001000 - -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB 13 -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB 15 -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK 0x0000e000 - -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 - -#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB 20 -#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB 27 -#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK 0x0ff00000 - -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB 28 -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/reo_entrance_ring.h b/drivers/staging/fw-api/hw/fig/v1/reo_entrance_ring.h deleted file mode 100644 index 800244f712be..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/reo_entrance_ring.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_ENTRANCE_RING_H_ -#define _REO_ENTRANCE_RING_H_ - -#include "rx_mpdu_details.h" -#define NUM_OF_DWORDS_REO_ENTRANCE_RING 16 - -struct reo_entrance_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_mpdu_details reo_level_mpdu_frame_info; - uint32_t rx_reo_queue_desc_addr_31_0 : 32; - uint32_t rx_reo_queue_desc_addr_39_32 : 8, - rounded_mpdu_byte_count : 14, - reo_destination_indication : 5, - frameless_bar : 1, - reserved_7a : 4; - uint32_t rxdma_push_reason : 2, - rxdma_error_code : 5, - mpdu_fragment_number : 4, - sw_exception : 1, - sw_exception_mpdu_delink : 1, - sw_exception_destination_ring_valid : 1, - sw_exception_destination_ring : 5, - mpdu_sequence_number : 12, - no_ack : 1; - uint32_t phy_ppdu_id : 16, - src_link_id : 3, - reserved_9a : 13; - uint32_t receive_queue_number : 16, - fw_reorder_push_reason : 2, - fw_reorder_error_code : 5, - reserved_10a : 9; - uint32_t reserved_11a : 32; - uint32_t reserved_12a : 32; - uint32_t reserved_13a : 32; - uint32_t reserved_14a : 32; - uint32_t reserved_15a : 20, - ring_id : 8, - looping_count : 4; -#else - struct rx_mpdu_details reo_level_mpdu_frame_info; - uint32_t rx_reo_queue_desc_addr_31_0 : 32; - uint32_t reserved_7a : 4, - frameless_bar : 1, - reo_destination_indication : 5, - rounded_mpdu_byte_count : 14, - rx_reo_queue_desc_addr_39_32 : 8; - uint32_t no_ack : 1, - mpdu_sequence_number : 12, - sw_exception_destination_ring : 5, - sw_exception_destination_ring_valid : 1, - sw_exception_mpdu_delink : 1, - sw_exception : 1, - mpdu_fragment_number : 4, - rxdma_error_code : 5, - rxdma_push_reason : 2; - uint32_t reserved_9a : 13, - src_link_id : 3, - phy_ppdu_id : 16; - uint32_t reserved_10a : 9, - fw_reorder_error_code : 5, - fw_reorder_push_reason : 2, - receive_queue_number : 16; - uint32_t reserved_11a : 32; - uint32_t reserved_12a : 32; - uint32_t reserved_13a : 32; - uint32_t reserved_14a : 32; - uint32_t looping_count : 4, - ring_id : 8, - reserved_15a : 20; -#endif -}; - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET 0x00000010 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB 15 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB 16 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB 17 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK 0x00030000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB 18 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB 21 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB 22 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffc00000 - -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff - -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff - -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8 -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21 -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 - -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22 -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26 -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000 - -#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27 -#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27 -#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000 - -#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_RESERVED_7A_LSB 28 -#define REO_ENTRANCE_RING_RESERVED_7A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0xf0000000 - -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003 - -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c - -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 - -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000 - -#define REO_ENTRANCE_RING_NO_ACK_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_NO_ACK_LSB 31 -#define REO_ENTRANCE_RING_NO_ACK_MSB 31 -#define REO_ENTRANCE_RING_NO_ACK_MASK 0x80000000 - -#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16 -#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18 -#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000 - -#define REO_ENTRANCE_RING_RESERVED_9A_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_RESERVED_9A_LSB 19 -#define REO_ENTRANCE_RING_RESERVED_9A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_9A_MASK 0xfff80000 - -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_LSB 0 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MSB 15 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_LSB 16 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MSB 17 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MASK 0x00030000 - -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_LSB 18 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MSB 22 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MASK 0x007c0000 - -#define REO_ENTRANCE_RING_RESERVED_10A_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_RESERVED_10A_LSB 23 -#define REO_ENTRANCE_RING_RESERVED_10A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_10A_MASK 0xff800000 - -#define REO_ENTRANCE_RING_RESERVED_11A_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_RESERVED_11A_LSB 0 -#define REO_ENTRANCE_RING_RESERVED_11A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_11A_MASK 0xffffffff - -#define REO_ENTRANCE_RING_RESERVED_12A_OFFSET 0x00000030 -#define REO_ENTRANCE_RING_RESERVED_12A_LSB 0 -#define REO_ENTRANCE_RING_RESERVED_12A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_12A_MASK 0xffffffff - -#define REO_ENTRANCE_RING_RESERVED_13A_OFFSET 0x00000034 -#define REO_ENTRANCE_RING_RESERVED_13A_LSB 0 -#define REO_ENTRANCE_RING_RESERVED_13A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_13A_MASK 0xffffffff - -#define REO_ENTRANCE_RING_RESERVED_14A_OFFSET 0x00000038 -#define REO_ENTRANCE_RING_RESERVED_14A_LSB 0 -#define REO_ENTRANCE_RING_RESERVED_14A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_14A_MASK 0xffffffff - -#define REO_ENTRANCE_RING_RESERVED_15A_OFFSET 0x0000003c -#define REO_ENTRANCE_RING_RESERVED_15A_LSB 0 -#define REO_ENTRANCE_RING_RESERVED_15A_MSB 19 -#define REO_ENTRANCE_RING_RESERVED_15A_MASK 0x000fffff - -#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000003c -#define REO_ENTRANCE_RING_RING_ID_LSB 20 -#define REO_ENTRANCE_RING_RING_ID_MSB 27 -#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000 - -#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000003c -#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28 -#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31 -#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/response_end_status.h b/drivers/staging/fw-api/hw/fig/v1/response_end_status.h deleted file mode 100644 index 30c6c65e043a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/response_end_status.h +++ /dev/null @@ -1,256 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RESPONSE_END_STATUS_H_ -#define _RESPONSE_END_STATUS_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_RESPONSE_END_STATUS 10 - -#define NUM_OF_QWORDS_RESPONSE_END_STATUS 5 - -struct response_end_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t __reserved_g_0046 : 1, - __reserved_g_0043 : 1, - __reserved_g_0041 : 1, - global_data_underflow_warning : 1, - response_transmit_status : 4, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - generated_response : 3, - mba_user_count : 7, - mba_fake_bitmap_count : 7, - coex_based_tx_bw : 3, - trig_response_related : 1, - __reserved_g_0035 : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t cbf_segment_request_mask : 8, - cbf_segment_sent_mask : 8; - uint32_t underflow_mpdu_count : 9, - data_underflow_warning : 2, - reserved_2b : 10, - only_null_delim_sent : 1, - brp_info_valid : 1, - __reserved_g_0068 : 1, - __reserved_g_0056 : 1, - __reserved_g_0039 : 1, - __reserved_g_0040 : 1, - __reserved_g_0063 : 1, - __reserved_g_0061 : 1, - __reserved_g_0059 : 1, - __reserved_g_0057 : 1, - __reserved_g_0042 : 1; - uint32_t mu_response_bitmap_31_0 : 32; - uint32_t mu_response_bitmap_36_32 : 5, - reserved_4a : 27; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t addr3_47_32 : 16, - __reserved_g_0022 : 1, - secure : 1, - __reserved_g_0022_ftm_frame_sent : 1, - reserved_20a : 13; -#else - uint32_t __reserved_g_0035 : 1, - trig_response_related : 1, - coex_based_tx_bw : 3, - mba_fake_bitmap_count : 7, - mba_user_count : 7, - generated_response : 3, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - response_transmit_status : 4, - global_data_underflow_warning : 1, - __reserved_g_0041 : 1, - __reserved_g_0043 : 1, - __reserved_g_0046 : 1; - uint32_t cbf_segment_sent_mask : 8, - cbf_segment_request_mask : 8; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t __reserved_g_0042 : 1, - __reserved_g_0057 : 1, - __reserved_g_0059 : 1, - __reserved_g_0061 : 1, - __reserved_g_0063 : 1, - __reserved_g_0040 : 1, - __reserved_g_0039 : 1, - __reserved_g_0056 : 1, - __reserved_g_0068 : 1, - brp_info_valid : 1, - only_null_delim_sent : 1, - reserved_2b : 10, - data_underflow_warning : 2, - underflow_mpdu_count : 9; - uint32_t mu_response_bitmap_31_0 : 32; - uint32_t reserved_4a : 27, - mu_response_bitmap_36_32 : 5; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t reserved_20a : 13, - __reserved_g_0022_ftm_frame_sent : 1, - secure : 1, - __reserved_g_0022 : 1, - addr3_47_32 : 16; -#endif -}; - -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008 - -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0 - -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200 - -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00 - -#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000 - -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000 - -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000 - -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000 - -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000 - -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff - -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 - -#define RESPONSE_END_STATUS_RESERVED_2B_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_RESERVED_2B_LSB 11 -#define RESPONSE_END_STATUS_RESERVED_2B_MSB 20 -#define RESPONSE_END_STATUS_RESERVED_2B_MASK 0x00000000001ff800 - -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000 - -#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000 - -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f - -#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_RESERVED_4A_LSB 5 -#define RESPONSE_END_STATUS_RESERVED_4A_MSB 31 -#define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x00000000ffffffe0 - -#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_ADDR1_31_0_LSB 32 -#define RESPONSE_END_STATUS_ADDR1_31_0_MSB 63 -#define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR1_47_32_LSB 0 -#define RESPONSE_END_STATUS_ADDR1_47_32_MSB 15 -#define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x000000000000ffff - -#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR2_15_0_LSB 16 -#define RESPONSE_END_STATUS_ADDR2_15_0_MSB 31 -#define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0x00000000ffff0000 - -#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR2_47_16_LSB 32 -#define RESPONSE_END_STATUS_ADDR2_47_16_MSB 63 -#define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_ADDR3_31_0_LSB 0 -#define RESPONSE_END_STATUS_ADDR3_31_0_MSB 31 -#define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0x00000000ffffffff - -#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_ADDR3_47_32_LSB 32 -#define RESPONSE_END_STATUS_ADDR3_47_32_MSB 47 -#define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x0000ffff00000000 - -#define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_SECURE_LSB 49 -#define RESPONSE_END_STATUS_SECURE_MSB 49 -#define RESPONSE_END_STATUS_SECURE_MASK 0x0002000000000000 - -#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_RESERVED_20A_LSB 51 -#define RESPONSE_END_STATUS_RESERVED_20A_MSB 63 -#define RESPONSE_END_STATUS_RESERVED_20A_MASK 0xfff8000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/response_start_status.h b/drivers/staging/fw-api/hw/fig/v1/response_start_status.h deleted file mode 100644 index b8b96e8d9f3d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/response_start_status.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RESPONSE_START_STATUS_H_ -#define _RESPONSE_START_STATUS_H_ - -#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 - -#define NUM_OF_QWORDS_RESPONSE_START_STATUS 1 - -struct response_start_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t generated_response : 3, - __reserved_g_0012 : 2, - trig_response_related : 1, - response_sta_count : 7, - reserved : 19; - uint32_t phy_ppdu_id : 16, - sw_peer_id : 16; -#else - uint32_t reserved : 19, - response_sta_count : 7, - trig_response_related : 1, - __reserved_g_0012 : 2, - generated_response : 3; - uint32_t sw_peer_id : 16, - phy_ppdu_id : 16; -#endif -}; - -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x0000000000000007 - -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000000000020 - -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x0000000000001fc0 - -#define RESPONSE_START_STATUS_RESERVED_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_RESERVED_LSB 13 -#define RESPONSE_START_STATUS_RESERVED_MSB 31 -#define RESPONSE_START_STATUS_RESERVED_MASK 0x00000000ffffe000 - -#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 32 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 47 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff00000000 - -#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_SW_PEER_ID_LSB 48 -#define RESPONSE_START_STATUS_SW_PEER_ID_MSB 63 -#define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/ru_allocation_160_info.h b/drivers/staging/fw-api/hw/fig/v1/ru_allocation_160_info.h deleted file mode 100644 index 57d51dc44f8a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/ru_allocation_160_info.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RU_ALLOCATION_160_INFO_H_ -#define _RU_ALLOCATION_160_INFO_H_ - -#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4 - -struct ru_allocation_160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_allocation_band0_0 : 9, - ru_allocation_band0_1 : 9, - reserved_0a : 6, - ru_allocations_01_subband80_mask : 4, - ru_allocations_23_subband80_mask : 4; - uint32_t ru_allocation_band0_2 : 9, - ru_allocation_band0_3 : 9, - reserved_1a : 14; - uint32_t ru_allocation_band1_0 : 9, - ru_allocation_band1_1 : 9, - reserved_2a : 14; - uint32_t ru_allocation_band1_2 : 9, - ru_allocation_band1_3 : 9, - reserved_3a : 14; -#else - uint32_t ru_allocations_23_subband80_mask : 4, - ru_allocations_01_subband80_mask : 4, - reserved_0a : 6, - ru_allocation_band0_1 : 9, - ru_allocation_band0_0 : 9; - uint32_t reserved_1a : 14, - ru_allocation_band0_3 : 9, - ru_allocation_band0_2 : 9; - uint32_t reserved_2a : 14, - ru_allocation_band1_1 : 9, - ru_allocation_band1_0 : 9; - uint32_t reserved_3a : 14, - ru_allocation_band1_3 : 9, - ru_allocation_band1_2 : 9; -#endif -}; - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB 23 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK 0x00fc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK 0xfffc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK 0xfffc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK 0xfffc0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_attention.h b/drivers/staging/fw-api/hw/fig/v1/rx_attention.h deleted file mode 100644 index cac7c2fb52c3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_attention.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_ATTENTION_H_ -#define _RX_ATTENTION_H_ - -#define NUM_OF_DWORDS_RX_ATTENTION 4 - -#define NUM_OF_QWORDS_RX_ATTENTION 2 - -struct rx_attention { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t first_mpdu : 1, - reserved_1a : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - a_msdu_error : 1, - fragment_flag : 1, - order : 1, - cce_match : 1, - overflow_err : 1, - msdu_length_err : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - sa_idx_invalid : 1, - da_idx_invalid : 1, - reserved_1b : 1, - rx_in_tx_decrypt_byp : 1, - encrypt_required : 1, - directed : 1, - buffer_fragment : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - fcs_err : 1; - uint32_t flow_idx_timeout : 1, - flow_idx_invalid : 1, - wifi_parser_error : 1, - amsdu_parser_error : 1, - sa_idx_timeout : 1, - da_idx_timeout : 1, - msdu_limit_error : 1, - da_is_valid : 1, - da_is_mcbc : 1, - sa_is_valid : 1, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - reserved_2 : 17, - msdu_done : 1; - uint32_t tlv64_padding : 32; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t fcs_err : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - buffer_fragment : 1, - directed : 1, - encrypt_required : 1, - rx_in_tx_decrypt_byp : 1, - reserved_1b : 1, - da_idx_invalid : 1, - sa_idx_invalid : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - msdu_length_err : 1, - overflow_err : 1, - cce_match : 1, - order : 1, - fragment_flag : 1, - a_msdu_error : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - reserved_1a : 1, - first_mpdu : 1; - uint32_t msdu_done : 1, - reserved_2 : 17, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - sa_is_valid : 1, - da_is_mcbc : 1, - da_is_valid : 1, - msdu_limit_error : 1, - da_idx_timeout : 1, - sa_idx_timeout : 1, - amsdu_parser_error : 1, - wifi_parser_error : 1, - flow_idx_invalid : 1, - flow_idx_timeout : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_0_LSB 9 -#define RX_ATTENTION_RESERVED_0_MSB 15 -#define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_PHY_PPDU_ID_LSB 16 -#define RX_ATTENTION_PHY_PPDU_ID_MSB 31 -#define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FIRST_MPDU_LSB 32 -#define RX_ATTENTION_FIRST_MPDU_MSB 32 -#define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000 - -#define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_1A_LSB 33 -#define RX_ATTENTION_RESERVED_1A_MSB 33 -#define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000 - -#define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MCAST_BCAST_LSB 34 -#define RX_ATTENTION_MCAST_BCAST_MSB 34 -#define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000 - -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000 - -#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000 - -#define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_POWER_MGMT_LSB 37 -#define RX_ATTENTION_POWER_MGMT_MSB 37 -#define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000 - -#define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000 -#define RX_ATTENTION_NON_QOS_LSB 38 -#define RX_ATTENTION_NON_QOS_MSB 38 -#define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000 - -#define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000 -#define RX_ATTENTION_NULL_DATA_LSB 39 -#define RX_ATTENTION_NULL_DATA_MSB 39 -#define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000 - -#define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MGMT_TYPE_LSB 40 -#define RX_ATTENTION_MGMT_TYPE_MSB 40 -#define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000 - -#define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000 -#define RX_ATTENTION_CTRL_TYPE_LSB 41 -#define RX_ATTENTION_CTRL_TYPE_MSB 41 -#define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000 - -#define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MORE_DATA_LSB 42 -#define RX_ATTENTION_MORE_DATA_MSB 42 -#define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000 - -#define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000 -#define RX_ATTENTION_EOSP_LSB 43 -#define RX_ATTENTION_EOSP_MSB 43 -#define RX_ATTENTION_EOSP_MASK 0x0000080000000000 - -#define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_A_MSDU_ERROR_LSB 44 -#define RX_ATTENTION_A_MSDU_ERROR_MSB 44 -#define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000 - -#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FRAGMENT_FLAG_LSB 45 -#define RX_ATTENTION_FRAGMENT_FLAG_MSB 45 -#define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000 - -#define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000 -#define RX_ATTENTION_ORDER_LSB 46 -#define RX_ATTENTION_ORDER_MSB 46 -#define RX_ATTENTION_ORDER_MASK 0x0000400000000000 - -#define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000 -#define RX_ATTENTION_CCE_MATCH_LSB 47 -#define RX_ATTENTION_CCE_MATCH_MSB 47 -#define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000 - -#define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_OVERFLOW_ERR_LSB 48 -#define RX_ATTENTION_OVERFLOW_ERR_MSB 48 -#define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000 - -#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49 -#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49 -#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000 - -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000 - -#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000 -#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51 -#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51 -#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000 - -#define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_SA_IDX_INVALID_LSB 52 -#define RX_ATTENTION_SA_IDX_INVALID_MSB 52 -#define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000 - -#define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DA_IDX_INVALID_LSB 53 -#define RX_ATTENTION_DA_IDX_INVALID_MSB 53 -#define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000 - -#define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_1B_LSB 54 -#define RX_ATTENTION_RESERVED_1B_MSB 54 -#define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000 - -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000 - -#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000 -#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56 -#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56 -#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000 - -#define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DIRECTED_LSB 57 -#define RX_ATTENTION_DIRECTED_MSB 57 -#define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000 - -#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58 -#define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58 -#define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000 - -#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59 -#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59 -#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000 - -#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_TKIP_MIC_ERR_LSB 60 -#define RX_ATTENTION_TKIP_MIC_ERR_MSB 60 -#define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000 - -#define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DECRYPT_ERR_LSB 61 -#define RX_ATTENTION_DECRYPT_ERR_MSB 61 -#define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000 - -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000 - -#define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FCS_ERR_LSB 63 -#define RX_ATTENTION_FCS_ERR_MSB 63 -#define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000 - -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001 - -#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 -#define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 -#define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002 - -#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 -#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 -#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004 - -#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008 - -#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 -#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 -#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010 - -#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 -#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 -#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020 - -#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040 - -#define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IS_VALID_LSB 7 -#define RX_ATTENTION_DA_IS_VALID_MSB 7 -#define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080 - -#define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IS_MCBC_LSB 8 -#define RX_ATTENTION_DA_IS_MCBC_MSB 8 -#define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100 - -#define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_SA_IS_VALID_LSB 9 -#define RX_ATTENTION_SA_IS_VALID_MSB 9 -#define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200 - -#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00 - -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000 - -#define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008 -#define RX_ATTENTION_RESERVED_2_LSB 14 -#define RX_ATTENTION_RESERVED_2_MSB 30 -#define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000 - -#define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008 -#define RX_ATTENTION_MSDU_DONE_LSB 31 -#define RX_ATTENTION_MSDU_DONE_MSB 31 -#define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000 - -#define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008 -#define RX_ATTENTION_TLV64_PADDING_LSB 32 -#define RX_ATTENTION_TLV64_PADDING_MSB 63 -#define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_flow_search_entry.h b/drivers/staging/fw-api/hw/fig/v1/rx_flow_search_entry.h deleted file mode 100644 index 25f1f81c439f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_flow_search_entry.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FLOW_SEARCH_ENTRY_H_ -#define _RX_FLOW_SEARCH_ENTRY_H_ - -#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 - -struct rx_flow_search_entry { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t src_ip_127_96 : 32; - uint32_t src_ip_95_64 : 32; - uint32_t src_ip_63_32 : 32; - uint32_t src_ip_31_0 : 32; - uint32_t dest_ip_127_96 : 32; - uint32_t dest_ip_95_64 : 32; - uint32_t dest_ip_63_32 : 32; - uint32_t dest_ip_31_0 : 32; - uint32_t src_port : 16, - dest_port : 16; - uint32_t l4_protocol : 8, - valid : 1, - reserved_9 : 4, - service_code : 9, - priority_valid : 1, - use_ppe : 1, - reo_destination_indication : 5, - msdu_drop : 1, - reo_destination_handler : 2; - uint32_t metadata : 32; - uint32_t aggregation_count : 7, - lro_eligible : 1, - msdu_count : 24; - uint32_t msdu_byte_count : 32; - uint32_t timestamp : 32; - uint32_t cumulative_ip_length_pmac1 : 16, - cumulative_ip_length : 16; - uint32_t tcp_sequence_number : 32; -#else - uint32_t src_ip_127_96 : 32; - uint32_t src_ip_95_64 : 32; - uint32_t src_ip_63_32 : 32; - uint32_t src_ip_31_0 : 32; - uint32_t dest_ip_127_96 : 32; - uint32_t dest_ip_95_64 : 32; - uint32_t dest_ip_63_32 : 32; - uint32_t dest_ip_31_0 : 32; - uint32_t dest_port : 16, - src_port : 16; - uint32_t reo_destination_handler : 2, - msdu_drop : 1, - reo_destination_indication : 5, - use_ppe : 1, - priority_valid : 1, - service_code : 9, - reserved_9 : 4, - valid : 1, - l4_protocol : 8; - uint32_t metadata : 32; - uint32_t msdu_count : 24, - lro_eligible : 1, - aggregation_count : 7; - uint32_t msdu_byte_count : 32; - uint32_t timestamp : 32; - uint32_t cumulative_ip_length : 16, - cumulative_ip_length_pmac1 : 16; - uint32_t tcp_sequence_number : 32; -#endif -}; - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000 - -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff - -#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8 -#define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8 -#define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100 - -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 12 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x00001e00 - -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB 13 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB 21 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK 0x003fe000 - -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB 22 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB 22 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK 0x00400000 - -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000 - -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000 - -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000 - -#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028 -#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6 -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f - -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7 -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7 -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8 -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET 0x00000038 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB 15 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK 0x0000ffff - -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 - -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_frame_1k_bitmap_ack.h b/drivers/staging/fw-api/hw/fig/v1/rx_frame_1k_bitmap_ack.h deleted file mode 100644 index a43548b14a07..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_frame_1k_bitmap_ack.h +++ /dev/null @@ -1,362 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_1K_BITMAP_ACK_H_ -#define _RX_FRAME_1K_BITMAP_ACK_H_ - -#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38 - -#define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19 - -struct rx_frame_1k_bitmap_ack { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 5, - ba_bitmap_size : 2, - gen_mlo_notification : 1, - reserved_0b : 2, - ba_tid : 4, - sta_full_aid : 13, - reserved_0c : 5; - uint32_t mlo_sta_id : 10, - ba_size_1024_allowed : 1, - ba_size_512_allowed : 1, - reserved_1a : 20; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_ctrl : 16, - ba_ts_seq : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; - uint32_t ba_ts_bitmap_287_256 : 32; - uint32_t ba_ts_bitmap_319_288 : 32; - uint32_t ba_ts_bitmap_351_320 : 32; - uint32_t ba_ts_bitmap_383_352 : 32; - uint32_t ba_ts_bitmap_415_384 : 32; - uint32_t ba_ts_bitmap_447_416 : 32; - uint32_t ba_ts_bitmap_479_448 : 32; - uint32_t ba_ts_bitmap_511_480 : 32; - uint32_t ba_ts_bitmap_543_512 : 32; - uint32_t ba_ts_bitmap_575_544 : 32; - uint32_t ba_ts_bitmap_607_576 : 32; - uint32_t ba_ts_bitmap_639_608 : 32; - uint32_t ba_ts_bitmap_671_640 : 32; - uint32_t ba_ts_bitmap_703_672 : 32; - uint32_t ba_ts_bitmap_735_704 : 32; - uint32_t ba_ts_bitmap_767_736 : 32; - uint32_t ba_ts_bitmap_799_768 : 32; - uint32_t ba_ts_bitmap_831_800 : 32; - uint32_t ba_ts_bitmap_863_832 : 32; - uint32_t ba_ts_bitmap_895_864 : 32; - uint32_t ba_ts_bitmap_927_896 : 32; - uint32_t ba_ts_bitmap_959_928 : 32; - uint32_t ba_ts_bitmap_991_960 : 32; - uint32_t ba_ts_bitmap_1023_992 : 32; -#else - uint32_t reserved_0c : 5, - sta_full_aid : 13, - ba_tid : 4, - reserved_0b : 2, - gen_mlo_notification : 1, - ba_bitmap_size : 2, - reserved_0a : 5; - uint32_t reserved_1a : 20, - ba_size_512_allowed : 1, - ba_size_1024_allowed : 1, - mlo_sta_id : 10; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_seq : 16, - ba_ts_ctrl : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; - uint32_t ba_ts_bitmap_287_256 : 32; - uint32_t ba_ts_bitmap_319_288 : 32; - uint32_t ba_ts_bitmap_351_320 : 32; - uint32_t ba_ts_bitmap_383_352 : 32; - uint32_t ba_ts_bitmap_415_384 : 32; - uint32_t ba_ts_bitmap_447_416 : 32; - uint32_t ba_ts_bitmap_479_448 : 32; - uint32_t ba_ts_bitmap_511_480 : 32; - uint32_t ba_ts_bitmap_543_512 : 32; - uint32_t ba_ts_bitmap_575_544 : 32; - uint32_t ba_ts_bitmap_607_576 : 32; - uint32_t ba_ts_bitmap_639_608 : 32; - uint32_t ba_ts_bitmap_671_640 : 32; - uint32_t ba_ts_bitmap_703_672 : 32; - uint32_t ba_ts_bitmap_735_704 : 32; - uint32_t ba_ts_bitmap_767_736 : 32; - uint32_t ba_ts_bitmap_799_768 : 32; - uint32_t ba_ts_bitmap_831_800 : 32; - uint32_t ba_ts_bitmap_863_832 : 32; - uint32_t ba_ts_bitmap_895_864 : 32; - uint32_t ba_ts_bitmap_927_896 : 32; - uint32_t ba_ts_bitmap_959_928 : 32; - uint32_t ba_ts_bitmap_991_960 : 32; - uint32_t ba_ts_bitmap_1023_992 : 32; -#endif -}; - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x000000000000001f - -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 - -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB 7 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB 7 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK 0x0000000000000080 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 8 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x0000000000000300 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 - -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0x00000000f8000000 - -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MSB 41 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MASK 0x000003ff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB 42 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB 42 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK 0x0000040000000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB 43 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB 43 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK 0x0000080000000000 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_LSB 44 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MASK 0xfffff00000000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 47 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 48 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 47 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 48 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff000000000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000020 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000028 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000030 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x0000000000000038 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x0000000000000038 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000000000000040 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x0000000000000040 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x0000000000000048 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x0000000000000048 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000000000000050 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x0000000000000050 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x0000000000000058 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x0000000000000058 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000000000000060 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x0000000000000060 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x0000000000000068 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x0000000000000068 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000000000000070 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x0000000000000070 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x0000000000000078 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x0000000000000078 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000000000000080 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x0000000000000080 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x0000000000000088 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x0000000000000088 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000000000000090 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x0000000000000090 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_frame_bitmap_ack.h b/drivers/staging/fw-api/hw/fig/v1/rx_frame_bitmap_ack.h deleted file mode 100644 index 0b68486b038e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_frame_bitmap_ack.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_BITMAP_ACK_H_ -#define _RX_FRAME_BITMAP_ACK_H_ - -#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14 - -#define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7 - -struct rx_frame_bitmap_ack { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t no_bitmap_available : 1, - explicit_ack : 1, - explict_ack_type : 3, - ba_bitmap_size : 2, - gen_mlo_notification : 1, - reserved_0a : 2, - ba_tid : 4, - sta_full_aid : 13, - reserved_0b : 5; - uint32_t mlo_sta_id : 10, - ba_size_1024_allowed : 1, - ba_size_512_allowed : 1, - ba_size_256_allowed : 1, - ba_size_128_allowed : 1, - ba_size_64_allowed : 1, - ba_size_32_allowed : 1, - reserved_1a : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_ctrl : 16, - ba_ts_seq : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; -#else - uint32_t reserved_0b : 5, - sta_full_aid : 13, - ba_tid : 4, - reserved_0a : 2, - gen_mlo_notification : 1, - ba_bitmap_size : 2, - explict_ack_type : 3, - explicit_ack : 1, - no_bitmap_available : 1; - uint32_t reserved_1a : 16, - ba_size_32_allowed : 1, - ba_size_64_allowed : 1, - ba_size_128_allowed : 1, - ba_size_256_allowed : 1, - ba_size_512_allowed : 1, - ba_size_1024_allowed : 1, - mlo_sta_id : 10; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_seq : 16, - ba_ts_ctrl : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; -#endif -}; - -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x0000000000000001 - -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x0000000000000002 - -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x000000000000001c - -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 - -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB 7 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB 7 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK 0x0000000000000080 - -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 8 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x0000000000000300 - -#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 -#define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 -#define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 - -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 - -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0x00000000f8000000 - -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_LSB 32 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MSB 41 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MASK 0x000003ff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB 42 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB 42 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK 0x0000040000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB 43 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB 43 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK 0x0000080000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_LSB 44 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MSB 44 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MASK 0x0000100000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_LSB 45 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MSB 45 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MASK 0x0000200000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_LSB 46 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MSB 46 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MASK 0x0000400000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_LSB 47 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MSB 47 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MASK 0x0000800000000000 - -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_LSB 48 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MSB 63 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 0 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 31 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 32 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 47 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 48 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 63 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 0 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 31 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 47 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 48 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000020 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000028 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000030 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_frame_bitmap_req.h b/drivers/staging/fw-api/hw/fig/v1/rx_frame_bitmap_req.h deleted file mode 100644 index 24f8ddd1c57c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_frame_bitmap_req.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_BITMAP_REQ_H_ -#define _RX_FRAME_BITMAP_REQ_H_ - -#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 2 - -#define NUM_OF_QWORDS_RX_FRAME_BITMAP_REQ 1 - -struct rx_frame_bitmap_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t explicit_user_request : 1, - user_request_type : 1, - user_number : 6, - sw_peer_id : 16, - tid_specific_request : 1, - requested_tid : 4, - reserved_0 : 3; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0 : 3, - requested_tid : 4, - tid_specific_request : 1, - sw_peer_id : 16, - user_number : 6, - user_request_type : 1, - explicit_user_request : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB 0 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB 0 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK 0x0000000000000001 - -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB 1 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB 1 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK 0x0000000000000002 - -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB 2 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB 7 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK 0x00000000000000fc - -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB 8 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB 23 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK 0x0000000000ffff00 - -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB 24 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB 24 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK 0x0000000001000000 - -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB 25 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB 28 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK 0x000000001e000000 - -#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB 29 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB 31 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK 0x00000000e0000000 - -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_LSB 32 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MSB 63 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_location_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_location_info.h deleted file mode 100644 index ee000f6d4cda..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_location_info.h +++ /dev/null @@ -1,453 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_LOCATION_INFO_H_ -#define _RX_LOCATION_INFO_H_ - -#define NUM_OF_DWORDS_RX_LOCATION_INFO 28 - -struct rx_location_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_location_info_valid : 1, - rtt_hw_ifft_mode : 1, - rtt___reserved_g_0020_mode : 2, - reserved_0 : 4, - rtt_num_fac : 8, - rtt_rx_chain_mask : 8, - rtt_num_streams : 8; - uint32_t rtt_first_selected_chain : 8, - rtt_second_selected_chain : 8, - rtt_cfr_status : 8, - rtt_cir_status : 8; - uint32_t rtt_che_buffer_pointer_low32 : 32; - uint32_t rtt_che_buffer_pointer_high8 : 8, - reserved_3 : 8, - rtt_pkt_bw_vht : 4, - rtt_pkt_bw_leg : 4, - rtt_mcs_rate : 8; - uint32_t rtt_cfo_measurement : 16, - rtt_preamble_type : 8, - rtt_gi_type : 8; - uint32_t rx_start_ts : 32; - uint32_t rx_start_ts_upper : 32; - uint32_t rx_end_ts : 32; - uint32_t gain_chain0 : 16, - gain_chain1 : 16; - uint32_t gain_chain2 : 16, - gain_chain3 : 16; - uint32_t gain_report_status : 8, - rtt_timing_backoff_sel : 8, - rtt_fac_combined : 16; - uint32_t rtt_fac_0 : 16, - rtt_fac_1 : 16; - uint32_t rtt_fac_2 : 16, - rtt_fac_3 : 16; - uint32_t rtt_fac_4 : 16, - rtt_fac_5 : 16; - uint32_t rtt_fac_6 : 16, - rtt_fac_7 : 16; - uint32_t rtt_fac_8 : 16, - rtt_fac_9 : 16; - uint32_t rtt_fac_10 : 16, - rtt_fac_11 : 16; - uint32_t rtt_fac_12 : 16, - rtt_fac_13 : 16; - uint32_t rtt_fac_14 : 16, - rtt_fac_15 : 16; - uint32_t rtt_fac_16 : 16, - rtt_fac_17 : 16; - uint32_t rtt_fac_18 : 16, - rtt_fac_19 : 16; - uint32_t rtt_fac_20 : 16, - rtt_fac_21 : 16; - uint32_t rtt_fac_22 : 16, - rtt_fac_23 : 16; - uint32_t rtt_fac_24 : 16, - rtt_fac_25 : 16; - uint32_t rtt_fac_26 : 16, - rtt_fac_27 : 16; - uint32_t rtt_fac_28 : 16, - rtt_fac_29 : 16; - uint32_t rtt_fac_30 : 16, - rtt_fac_31 : 16; - uint32_t reserved_27a : 32; -#else - uint32_t rtt_num_streams : 8, - rtt_rx_chain_mask : 8, - rtt_num_fac : 8, - reserved_0 : 4, - rtt___reserved_g_0020_mode : 2, - rtt_hw_ifft_mode : 1, - rx_location_info_valid : 1; - uint32_t rtt_cir_status : 8, - rtt_cfr_status : 8, - rtt_second_selected_chain : 8, - rtt_first_selected_chain : 8; - uint32_t rtt_che_buffer_pointer_low32 : 32; - uint32_t rtt_mcs_rate : 8, - rtt_pkt_bw_leg : 4, - rtt_pkt_bw_vht : 4, - reserved_3 : 8, - rtt_che_buffer_pointer_high8 : 8; - uint32_t rtt_gi_type : 8, - rtt_preamble_type : 8, - rtt_cfo_measurement : 16; - uint32_t rx_start_ts : 32; - uint32_t rx_start_ts_upper : 32; - uint32_t rx_end_ts : 32; - uint32_t gain_chain1 : 16, - gain_chain0 : 16; - uint32_t gain_chain3 : 16, - gain_chain2 : 16; - uint32_t rtt_fac_combined : 16, - rtt_timing_backoff_sel : 8, - gain_report_status : 8; - uint32_t rtt_fac_1 : 16, - rtt_fac_0 : 16; - uint32_t rtt_fac_3 : 16, - rtt_fac_2 : 16; - uint32_t rtt_fac_5 : 16, - rtt_fac_4 : 16; - uint32_t rtt_fac_7 : 16, - rtt_fac_6 : 16; - uint32_t rtt_fac_9 : 16, - rtt_fac_8 : 16; - uint32_t rtt_fac_11 : 16, - rtt_fac_10 : 16; - uint32_t rtt_fac_13 : 16, - rtt_fac_12 : 16; - uint32_t rtt_fac_15 : 16, - rtt_fac_14 : 16; - uint32_t rtt_fac_17 : 16, - rtt_fac_16 : 16; - uint32_t rtt_fac_19 : 16, - rtt_fac_18 : 16; - uint32_t rtt_fac_21 : 16, - rtt_fac_20 : 16; - uint32_t rtt_fac_23 : 16, - rtt_fac_22 : 16; - uint32_t rtt_fac_25 : 16, - rtt_fac_24 : 16; - uint32_t rtt_fac_27 : 16, - rtt_fac_26 : 16; - uint32_t rtt_fac_29 : 16, - rtt_fac_28 : 16; - uint32_t rtt_fac_31 : 16, - rtt_fac_30 : 16; - uint32_t reserved_27a : 32; -#endif -}; - -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB 0 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB 0 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK 0x00000001 - -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB 1 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB 1 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK 0x00000002 - -#define RX_LOCATION_INFO_RESERVED_0_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RESERVED_0_LSB 4 -#define RX_LOCATION_INFO_RESERVED_0_MSB 7 -#define RX_LOCATION_INFO_RESERVED_0_MASK 0x000000f0 - -#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB 8 -#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB 15 -#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB 16 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB 23 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB 24 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB 31 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB 0 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB 7 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff - -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB 8 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB 15 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB 16 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB 23 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB 24 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB 31 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff - -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff - -#define RX_LOCATION_INFO_RESERVED_3_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RESERVED_3_LSB 8 -#define RX_LOCATION_INFO_RESERVED_3_MSB 15 -#define RX_LOCATION_INFO_RESERVED_3_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB 16 -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB 19 -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK 0x000f0000 - -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB 20 -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB 23 -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK 0x00f00000 - -#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB 24 -#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB 31 -#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB 0 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB 15 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB 16 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB 23 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB 24 -#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB 31 -#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK 0xff000000 - -#define RX_LOCATION_INFO_RX_START_TS_OFFSET 0x00000014 -#define RX_LOCATION_INFO_RX_START_TS_LSB 0 -#define RX_LOCATION_INFO_RX_START_TS_MSB 31 -#define RX_LOCATION_INFO_RX_START_TS_MASK 0xffffffff - -#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET 0x00000018 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB 0 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB 31 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK 0xffffffff - -#define RX_LOCATION_INFO_RX_END_TS_OFFSET 0x0000001c -#define RX_LOCATION_INFO_RX_END_TS_LSB 0 -#define RX_LOCATION_INFO_RX_END_TS_MSB 31 -#define RX_LOCATION_INFO_RX_END_TS_MASK 0xffffffff - -#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET 0x00000020 -#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB 0 -#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB 15 -#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK 0x0000ffff - -#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET 0x00000020 -#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB 16 -#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB 31 -#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK 0xffff0000 - -#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET 0x00000024 -#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB 0 -#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB 15 -#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK 0x0000ffff - -#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET 0x00000024 -#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB 16 -#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB 31 -#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK 0xffff0000 - -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET 0x00000028 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB 0 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB 7 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK 0x000000ff - -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB 8 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB 15 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET 0x00000028 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET 0x0000002c -#define RX_LOCATION_INFO_RTT_FAC_0_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_0_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_0_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET 0x0000002c -#define RX_LOCATION_INFO_RTT_FAC_1_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_1_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_1_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET 0x00000030 -#define RX_LOCATION_INFO_RTT_FAC_2_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_2_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_2_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET 0x00000030 -#define RX_LOCATION_INFO_RTT_FAC_3_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_3_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_3_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET 0x00000034 -#define RX_LOCATION_INFO_RTT_FAC_4_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_4_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_4_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET 0x00000034 -#define RX_LOCATION_INFO_RTT_FAC_5_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_5_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_5_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET 0x00000038 -#define RX_LOCATION_INFO_RTT_FAC_6_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_6_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_6_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET 0x00000038 -#define RX_LOCATION_INFO_RTT_FAC_7_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_7_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_7_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET 0x0000003c -#define RX_LOCATION_INFO_RTT_FAC_8_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_8_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_8_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET 0x0000003c -#define RX_LOCATION_INFO_RTT_FAC_9_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_9_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_9_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET 0x00000040 -#define RX_LOCATION_INFO_RTT_FAC_10_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_10_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_10_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET 0x00000040 -#define RX_LOCATION_INFO_RTT_FAC_11_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_11_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_11_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET 0x00000044 -#define RX_LOCATION_INFO_RTT_FAC_12_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_12_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_12_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET 0x00000044 -#define RX_LOCATION_INFO_RTT_FAC_13_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_13_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_13_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET 0x00000048 -#define RX_LOCATION_INFO_RTT_FAC_14_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_14_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_14_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET 0x00000048 -#define RX_LOCATION_INFO_RTT_FAC_15_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_15_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_15_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET 0x0000004c -#define RX_LOCATION_INFO_RTT_FAC_16_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_16_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_16_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET 0x0000004c -#define RX_LOCATION_INFO_RTT_FAC_17_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_17_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_17_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET 0x00000050 -#define RX_LOCATION_INFO_RTT_FAC_18_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_18_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_18_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET 0x00000050 -#define RX_LOCATION_INFO_RTT_FAC_19_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_19_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_19_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET 0x00000054 -#define RX_LOCATION_INFO_RTT_FAC_20_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_20_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_20_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET 0x00000054 -#define RX_LOCATION_INFO_RTT_FAC_21_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_21_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_21_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET 0x00000058 -#define RX_LOCATION_INFO_RTT_FAC_22_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_22_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_22_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET 0x00000058 -#define RX_LOCATION_INFO_RTT_FAC_23_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_23_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_23_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET 0x0000005c -#define RX_LOCATION_INFO_RTT_FAC_24_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_24_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_24_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET 0x0000005c -#define RX_LOCATION_INFO_RTT_FAC_25_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_25_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_25_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET 0x00000060 -#define RX_LOCATION_INFO_RTT_FAC_26_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_26_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_26_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET 0x00000060 -#define RX_LOCATION_INFO_RTT_FAC_27_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_27_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_27_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET 0x00000064 -#define RX_LOCATION_INFO_RTT_FAC_28_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_28_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_28_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET 0x00000064 -#define RX_LOCATION_INFO_RTT_FAC_29_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_29_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_29_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET 0x00000068 -#define RX_LOCATION_INFO_RTT_FAC_30_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_30_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_30_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET 0x00000068 -#define RX_LOCATION_INFO_RTT_FAC_31_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_31_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_31_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RESERVED_27A_OFFSET 0x0000006c -#define RX_LOCATION_INFO_RESERVED_27A_LSB 0 -#define RX_LOCATION_INFO_RESERVED_27A_MSB 31 -#define RX_LOCATION_INFO_RESERVED_27A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_desc_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_desc_info.h deleted file mode 100644 index 30f538fb1228..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_desc_info.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_DESC_INFO_H_ -#define _RX_MPDU_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 - -struct rx_mpdu_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t msdu_count : 8, - fragment_flag : 1, - mpdu_retry_bit : 1, - ampdu_flag : 1, - bar_frame : 1, - pn_fields_contain_valid_info : 1, - raw_mpdu : 1, - more_fragment_flag : 1, - src_info : 12, - mpdu_qos_control_valid : 1, - tid : 4; - uint32_t peer_meta_data : 32; -#else - uint32_t tid : 4, - mpdu_qos_control_valid : 1, - src_info : 12, - more_fragment_flag : 1, - raw_mpdu : 1, - pn_fields_contain_valid_info : 1, - bar_frame : 1, - ampdu_flag : 1, - mpdu_retry_bit : 1, - fragment_flag : 1, - msdu_count : 8; - uint32_t peer_meta_data : 32; -#endif -}; - -#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB 7 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK 0x000000ff - -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB 8 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB 8 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK 0x00000100 - -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB 9 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB 9 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK 0x00000200 - -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB 10 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB 10 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK 0x00000400 - -#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB 11 -#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB 11 -#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK 0x00000800 - -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB 13 -#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB 13 -#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK 0x00002000 - -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_SRC_INFO_LSB 15 -#define RX_MPDU_DESC_INFO_SRC_INFO_MSB 26 -#define RX_MPDU_DESC_INFO_SRC_INFO_MASK 0x07ff8000 - -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB 27 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB 27 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define RX_MPDU_DESC_INFO_TID_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_TID_LSB 28 -#define RX_MPDU_DESC_INFO_TID_MSB 31 -#define RX_MPDU_DESC_INFO_TID_MASK 0xf0000000 - -#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET 0x00000004 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB 0 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB 31 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_details.h b/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_details.h deleted file mode 100644 index d2d96a0a9996..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_details.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_DETAILS_H_ -#define _RX_MPDU_DETAILS_H_ - -#include "rx_mpdu_ext_desc_info.h" -#include "rx_mpdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MPDU_DETAILS 6 - -struct rx_mpdu_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info msdu_link_desc_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_mpdu_ext_desc_info rx_mpdu_ext_desc_info_details; -#else - struct buffer_addr_info msdu_link_desc_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_mpdu_ext_desc_info rx_mpdu_ext_desc_info_details; -#endif -}; - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET 0x00000010 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB 15 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK 0x0000ffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB 16 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB 17 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK 0x00030000 - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB 18 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB 21 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB 22 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_end.h b/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_end.h deleted file mode 100644 index b811f3622720..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_end.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_END_H_ -#define _RX_MPDU_END_H_ - -#define NUM_OF_DWORDS_RX_MPDU_END 4 - -#define NUM_OF_QWORDS_RX_MPDU_END 2 - -struct rx_mpdu_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t reserved_1a : 11, - unsup_ktype_short_frame : 1, - rx_in_tx_decrypt_byp : 1, - overflow_err : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - pn_fields_contain_valid_info : 1, - fcs_err : 1, - msdu_length_err : 1, - reserved1c : 6, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - reserved_1b : 1; - uint32_t reserved_2a : 15, - rxpcu_mgmt_sequence_nr_valid : 1, - rxpcu_mgmt_sequence_nr : 16; - uint32_t __reserved_g_0002 : 32; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_1b : 1, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - reserved1c : 6, - msdu_length_err : 1, - fcs_err : 1, - pn_fields_contain_valid_info : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - overflow_err : 1, - rx_in_tx_decrypt_byp : 1, - unsup_ktype_short_frame : 1, - reserved_1a : 11; - uint32_t rxpcu_mgmt_sequence_nr : 16, - rxpcu_mgmt_sequence_nr_valid : 1, - reserved_2a : 15; - uint32_t __reserved_g_0002 : 32; -#endif -}; - -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED_0_LSB 9 -#define RX_MPDU_END_RESERVED_0_MSB 15 -#define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MPDU_END_PHY_PPDU_ID_LSB 16 -#define RX_MPDU_END_PHY_PPDU_ID_MSB 31 -#define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED_1A_LSB 32 -#define RX_MPDU_END_RESERVED_1A_MSB 42 -#define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff00000000 - -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000 - -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000 - -#define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_OVERFLOW_ERR_LSB 45 -#define RX_MPDU_END_OVERFLOW_ERR_MSB 45 -#define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000 - -#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46 -#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46 -#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000 - -#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_TKIP_MIC_ERR_LSB 47 -#define RX_MPDU_END_TKIP_MIC_ERR_MSB 47 -#define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000 - -#define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_DECRYPT_ERR_LSB 48 -#define RX_MPDU_END_DECRYPT_ERR_MSB 48 -#define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000 - -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000 - -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000 - -#define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_FCS_ERR_LSB 51 -#define RX_MPDU_END_FCS_ERR_MSB 51 -#define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000 - -#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52 -#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52 -#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000 - -#define RX_MPDU_END_RESERVED1C_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED1C_LSB 53 -#define RX_MPDU_END_RESERVED1C_MSB 58 -#define RX_MPDU_END_RESERVED1C_MASK 0x07e0000000000000 - -#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000 - -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000 - -#define RX_MPDU_END_RESERVED_1B_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED_1B_LSB 63 -#define RX_MPDU_END_RESERVED_1B_MSB 63 -#define RX_MPDU_END_RESERVED_1B_MASK 0x8000000000000000 - -#define RX_MPDU_END_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_MPDU_END_RESERVED_2A_LSB 0 -#define RX_MPDU_END_RESERVED_2A_MSB 14 -#define RX_MPDU_END_RESERVED_2A_MASK 0x0000000000007fff - -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000 - -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_ext_desc_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_ext_desc_info.h deleted file mode 100644 index 83f4df333c88..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_ext_desc_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_EXT_DESC_INFO_H_ -#define _RX_MPDU_EXT_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MPDU_EXT_DESC_INFO 2 - -struct rx_mpdu_ext_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pn_31_0 : 32; - uint32_t pn_47_32 : 16, - pn_127_48_info : 2, - msdu_link_desc_index : 4, - reserved_1a : 10; -#else - uint32_t pn_31_0 : 32; - uint32_t reserved_1a : 10, - msdu_link_desc_index : 4, - pn_127_48_info : 2, - pn_47_32 : 16; -#endif -}; - -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_OFFSET 0x00000000 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_LSB 0 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MSB 31 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_LSB 0 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MSB 15 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MASK 0x0000ffff - -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_LSB 16 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MSB 17 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MASK 0x00030000 - -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_LSB 18 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MSB 21 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_LSB 22 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MSB 31 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_info.h deleted file mode 100644 index b742b6ce733b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_info.h +++ /dev/null @@ -1,958 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_INFO_H_ -#define _RX_MPDU_INFO_H_ - -#include "rxpt_classify_info.h" -#define NUM_OF_DWORDS_RX_MPDU_INFO 30 - -struct rx_mpdu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rxpt_classify_info rxpt_classify_info_details; - uint32_t epd_en : 1, - all_frames_shall_be_encrypted : 1, - encrypt_type : 4, - wep_key_width_for_variable_key : 2, - __reserved_g_0003 : 2, - bssid_hit : 1, - bssid_number : 4, - tid : 4, - reserved_7a : 13; - uint32_t rx_reo_queue_desc_addr_31_0 : 32; - uint32_t rx_reo_queue_desc_addr_39_32 : 8, - receive_queue_number : 16, - pre_delim_err_warning : 1, - first_delim_err : 1, - reserved_2a : 6; - uint32_t pn_31_0 : 32; - uint32_t pn_63_32 : 32; - uint32_t pn_95_64 : 32; - uint32_t pn_127_96 : 32; - uint32_t mpdu_frame_control_valid : 1, - mpdu_duration_valid : 1, - mac_addr_ad1_valid : 1, - mac_addr_ad2_valid : 1, - mac_addr_ad3_valid : 1, - mac_addr_ad4_valid : 1, - mpdu_sequence_control_valid : 1, - mpdu_qos_control_valid : 1, - mpdu_ht_control_valid : 1, - frame_encryption_info_valid : 1, - mpdu_fragment_number : 4, - more_fragment_flag : 1, - reserved_11a : 1, - fr_ds : 1, - to_ds : 1, - encrypted : 1, - mpdu_retry : 1, - mpdu_sequence_number : 12; - uint32_t peer_meta_data : 32; - uint32_t ast_index : 16, - sw_peer_id : 16; - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - ndp_frame : 1, - phy_err : 1, - phy_err_during_mpdu_header : 1, - protocol_version_err : 1, - ast_based_lookup_valid : 1, - __reserved_g_0022 : 1, - __reserved_g_0035 : 1, - phy_ppdu_id : 16; - uint32_t key_id_octet : 8, - new_peer_entry : 1, - decrypt_needed : 1, - decap_type : 2, - rx_insert_vlan_c_tag_padding : 1, - rx_insert_vlan_s_tag_padding : 1, - strip_vlan_c_tag_decap : 1, - strip_vlan_s_tag_decap : 1, - pre_delim_count : 12, - ampdu_flag : 1, - bar_frame : 1, - raw_mpdu : 1, - reserved_12 : 1; - uint32_t mpdu_length : 14, - first_mpdu : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - fragment_flag : 1, - order : 1, - u_apsd_trigger : 1, - encrypt_required : 1, - directed : 1, - amsdu_present : 1, - reserved_13 : 1; - uint32_t mpdu_frame_control_field : 16, - mpdu_duration_field : 16; - uint32_t mac_addr_ad1_31_0 : 32; - uint32_t mac_addr_ad1_47_32 : 16, - mac_addr_ad2_15_0 : 16; - uint32_t mac_addr_ad2_47_16 : 32; - uint32_t mac_addr_ad3_31_0 : 32; - uint32_t mac_addr_ad3_47_32 : 16, - mpdu_sequence_control_field : 16; - uint32_t mac_addr_ad4_31_0 : 32; - uint32_t mac_addr_ad4_47_32 : 16, - mpdu_qos_control_field : 16; - uint32_t mpdu_ht_control_field : 32; - uint32_t vdev_id : 8, - service_code : 9, - priority_valid : 1, - src_info : 12, - reserved_23a : 1, - __reserved_g_0006 : 1; - uint32_t __reserved_g_0007 : 32; - uint32_t __reserved_g_0008 : 16, - __reserved_g_0009 : 16; - uint32_t __reserved_g_0010 : 32; - uint32_t authorized_to_send_wds : 1, - disallow_mcbc_da_in_unicast_mpdu : 1, - fromtods_00_fnf_check_dis : 1, - fromtods_01_fnf_check_dis : 1, - fromtods_10_fnf_check_dis : 1, - fromtods_11_fnf_check_dis : 1, - rx_misc_config : 3, - a_msdu_fromtods_10_ad3 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_11_ad4 : 2, - multi_link_addr_fromtods_00_raw_en : 1, - multi_link_addr_fromtods_non00_raw_en : 1, - multi_link_addr_ad3_valid : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_ad1_trans_dis : 1, - data_fromtods_00_ad3 : 2, - mgmt_fromtods_00_ad3 : 2, - multi_link_addr_mgmt_en : 1, - multi_link_addr_ctrl_en : 1, - reserved_27a : 5; - uint32_t multi_link_addr_ad3_31_0 : 32; - uint32_t multi_link_addr_ad3_47_32 : 16, - reserved_29a : 16; -#else - struct rxpt_classify_info rxpt_classify_info_details; - uint32_t reserved_7a : 13, - tid : 4, - bssid_number : 4, - bssid_hit : 1, - __reserved_g_0003 : 2, - wep_key_width_for_variable_key : 2, - encrypt_type : 4, - all_frames_shall_be_encrypted : 1, - epd_en : 1; - uint32_t rx_reo_queue_desc_addr_31_0 : 32; - uint32_t reserved_2a : 6, - first_delim_err : 1, - pre_delim_err_warning : 1, - receive_queue_number : 16, - rx_reo_queue_desc_addr_39_32 : 8; - uint32_t pn_31_0 : 32; - uint32_t pn_63_32 : 32; - uint32_t pn_95_64 : 32; - uint32_t pn_127_96 : 32; - uint32_t mpdu_sequence_number : 12, - mpdu_retry : 1, - encrypted : 1, - to_ds : 1, - fr_ds : 1, - reserved_11a : 1, - more_fragment_flag : 1, - mpdu_fragment_number : 4, - frame_encryption_info_valid : 1, - mpdu_ht_control_valid : 1, - mpdu_qos_control_valid : 1, - mpdu_sequence_control_valid : 1, - mac_addr_ad4_valid : 1, - mac_addr_ad3_valid : 1, - mac_addr_ad2_valid : 1, - mac_addr_ad1_valid : 1, - mpdu_duration_valid : 1, - mpdu_frame_control_valid : 1; - uint32_t peer_meta_data : 32; - uint32_t sw_peer_id : 16, - ast_index : 16; - uint32_t phy_ppdu_id : 16, - __reserved_g_0035 : 1, - __reserved_g_0022 : 1, - ast_based_lookup_valid : 1, - protocol_version_err : 1, - phy_err_during_mpdu_header : 1, - phy_err : 1, - ndp_frame : 1, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_12 : 1, - raw_mpdu : 1, - bar_frame : 1, - ampdu_flag : 1, - pre_delim_count : 12, - strip_vlan_s_tag_decap : 1, - strip_vlan_c_tag_decap : 1, - rx_insert_vlan_s_tag_padding : 1, - rx_insert_vlan_c_tag_padding : 1, - decap_type : 2, - decrypt_needed : 1, - new_peer_entry : 1, - key_id_octet : 8; - uint32_t reserved_13 : 1, - amsdu_present : 1, - directed : 1, - encrypt_required : 1, - u_apsd_trigger : 1, - order : 1, - fragment_flag : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - first_mpdu : 1, - mpdu_length : 14; - uint32_t mpdu_duration_field : 16, - mpdu_frame_control_field : 16; - uint32_t mac_addr_ad1_31_0 : 32; - uint32_t mac_addr_ad2_15_0 : 16, - mac_addr_ad1_47_32 : 16; - uint32_t mac_addr_ad2_47_16 : 32; - uint32_t mac_addr_ad3_31_0 : 32; - uint32_t mpdu_sequence_control_field : 16, - mac_addr_ad3_47_32 : 16; - uint32_t mac_addr_ad4_31_0 : 32; - uint32_t mpdu_qos_control_field : 16, - mac_addr_ad4_47_32 : 16; - uint32_t mpdu_ht_control_field : 32; - uint32_t __reserved_g_0006 : 1, - reserved_23a : 1, - src_info : 12, - priority_valid : 1, - service_code : 9, - vdev_id : 8; - uint32_t __reserved_g_0007 : 32; - uint32_t __reserved_g_0009 : 16, - __reserved_g_0008 : 16; - uint32_t __reserved_g_0010 : 32; - uint32_t reserved_27a : 5, - multi_link_addr_ctrl_en : 1, - multi_link_addr_mgmt_en : 1, - mgmt_fromtods_00_ad3 : 2, - data_fromtods_00_ad3 : 2, - multi_link_addr_ad1_trans_dis : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_ad3_valid : 1, - multi_link_addr_fromtods_non00_raw_en : 1, - multi_link_addr_fromtods_00_raw_en : 1, - a_msdu_fromtods_11_ad4 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_10_ad3 : 2, - rx_misc_config : 3, - fromtods_11_fnf_check_dis : 1, - fromtods_10_fnf_check_dis : 1, - fromtods_01_fnf_check_dis : 1, - fromtods_00_fnf_check_dis : 1, - disallow_mcbc_da_in_unicast_mpdu : 1, - authorized_to_send_wds : 1; - uint32_t multi_link_addr_ad3_31_0 : 32; - uint32_t reserved_29a : 16, - multi_link_addr_ad3_47_32 : 16; -#endif -}; - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x00400000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xff800000 - -#define RX_MPDU_INFO_EPD_EN_OFFSET 0x00000004 -#define RX_MPDU_INFO_EPD_EN_LSB 0 -#define RX_MPDU_INFO_EPD_EN_MSB 0 -#define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 - -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x00000004 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 - -#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x00000004 -#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 -#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 -#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c - -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x00000004 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 - -#define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x00000004 -#define RX_MPDU_INFO_BSSID_HIT_LSB 10 -#define RX_MPDU_INFO_BSSID_HIT_MSB 10 -#define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 - -#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x00000004 -#define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 -#define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 -#define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 - -#define RX_MPDU_INFO_TID_OFFSET 0x00000004 -#define RX_MPDU_INFO_TID_LSB 15 -#define RX_MPDU_INFO_TID_MSB 18 -#define RX_MPDU_INFO_TID_MASK 0x00078000 - -#define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x00000004 -#define RX_MPDU_INFO_RESERVED_7A_LSB 19 -#define RX_MPDU_INFO_RESERVED_7A_MSB 31 -#define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 - -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000008 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000c -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 - -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000c -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 - -#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x0000000c -#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 -#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 -#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 - -#define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x0000000c -#define RX_MPDU_INFO_RESERVED_2A_LSB 26 -#define RX_MPDU_INFO_RESERVED_2A_MSB 31 -#define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 - -#define RX_MPDU_INFO_PN_31_0_OFFSET 0x00000010 -#define RX_MPDU_INFO_PN_31_0_LSB 0 -#define RX_MPDU_INFO_PN_31_0_MSB 31 -#define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000014 -#define RX_MPDU_INFO_PN_63_32_LSB 0 -#define RX_MPDU_INFO_PN_63_32_MSB 31 -#define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000018 -#define RX_MPDU_INFO_PN_95_64_LSB 0 -#define RX_MPDU_INFO_PN_95_64_MSB 31 -#define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_127_96_OFFSET 0x0000001c -#define RX_MPDU_INFO_PN_127_96_LSB 0 -#define RX_MPDU_INFO_PN_127_96_MSB 31 -#define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff - -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 - -#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 - -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 - -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 - -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 - -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 - -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 - -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 - -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 - -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 - -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 - -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000020 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_INFO_RESERVED_11A_OFFSET 0x00000020 -#define RX_MPDU_INFO_RESERVED_11A_LSB 15 -#define RX_MPDU_INFO_RESERVED_11A_MSB 15 -#define RX_MPDU_INFO_RESERVED_11A_MASK 0x00008000 - -#define RX_MPDU_INFO_FR_DS_OFFSET 0x00000020 -#define RX_MPDU_INFO_FR_DS_LSB 16 -#define RX_MPDU_INFO_FR_DS_MSB 16 -#define RX_MPDU_INFO_FR_DS_MASK 0x00010000 - -#define RX_MPDU_INFO_TO_DS_OFFSET 0x00000020 -#define RX_MPDU_INFO_TO_DS_LSB 17 -#define RX_MPDU_INFO_TO_DS_MSB 17 -#define RX_MPDU_INFO_TO_DS_MASK 0x00020000 - -#define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x00000020 -#define RX_MPDU_INFO_ENCRYPTED_LSB 18 -#define RX_MPDU_INFO_ENCRYPTED_MSB 18 -#define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 - -#define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_RETRY_LSB 19 -#define RX_MPDU_INFO_MPDU_RETRY_MSB 19 -#define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 - -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 - -#define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000024 -#define RX_MPDU_INFO_PEER_META_DATA_LSB 0 -#define RX_MPDU_INFO_PEER_META_DATA_MSB 31 -#define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff - -#define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 -#define RX_MPDU_INFO_AST_INDEX_LSB 0 -#define RX_MPDU_INFO_AST_INDEX_MSB 15 -#define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff - -#define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 -#define RX_MPDU_INFO_SW_PEER_ID_LSB 16 -#define RX_MPDU_INFO_SW_PEER_ID_MSB 31 -#define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 - -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000002c -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 - -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x0000002c -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc - -#define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x0000002c -#define RX_MPDU_INFO_NDP_FRAME_LSB 9 -#define RX_MPDU_INFO_NDP_FRAME_MSB 9 -#define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 - -#define RX_MPDU_INFO_PHY_ERR_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_ERR_LSB 10 -#define RX_MPDU_INFO_PHY_ERR_MSB 10 -#define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 - -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 - -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x0000002c -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 - -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x0000002c -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 - -#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 -#define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 -#define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 - -#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 -#define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 -#define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 -#define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff - -#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 - -#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 -#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 -#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 -#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 - -#define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 -#define RX_MPDU_INFO_DECAP_TYPE_LSB 10 -#define RX_MPDU_INFO_DECAP_TYPE_MSB 11 -#define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 - -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 - -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 - -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 - -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 - -#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 - -#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 -#define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 -#define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 -#define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 - -#define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 -#define RX_MPDU_INFO_BAR_FRAME_LSB 29 -#define RX_MPDU_INFO_BAR_FRAME_MSB 29 -#define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 - -#define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 -#define RX_MPDU_INFO_RAW_MPDU_LSB 30 -#define RX_MPDU_INFO_RAW_MPDU_MSB 30 -#define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 - -#define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 -#define RX_MPDU_INFO_RESERVED_12_LSB 31 -#define RX_MPDU_INFO_RESERVED_12_MSB 31 -#define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 - -#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 -#define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 -#define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 -#define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff - -#define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 -#define RX_MPDU_INFO_FIRST_MPDU_LSB 14 -#define RX_MPDU_INFO_FIRST_MPDU_MSB 14 -#define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 - -#define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 -#define RX_MPDU_INFO_MCAST_BCAST_LSB 15 -#define RX_MPDU_INFO_MCAST_BCAST_MSB 15 -#define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 - -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 - -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 - -#define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 -#define RX_MPDU_INFO_POWER_MGMT_LSB 18 -#define RX_MPDU_INFO_POWER_MGMT_MSB 18 -#define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 - -#define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 -#define RX_MPDU_INFO_NON_QOS_LSB 19 -#define RX_MPDU_INFO_NON_QOS_MSB 19 -#define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 - -#define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 -#define RX_MPDU_INFO_NULL_DATA_LSB 20 -#define RX_MPDU_INFO_NULL_DATA_MSB 20 -#define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 - -#define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 -#define RX_MPDU_INFO_MGMT_TYPE_LSB 21 -#define RX_MPDU_INFO_MGMT_TYPE_MSB 21 -#define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 - -#define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 -#define RX_MPDU_INFO_CTRL_TYPE_LSB 22 -#define RX_MPDU_INFO_CTRL_TYPE_MSB 22 -#define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 - -#define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 -#define RX_MPDU_INFO_MORE_DATA_LSB 23 -#define RX_MPDU_INFO_MORE_DATA_MSB 23 -#define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 - -#define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 -#define RX_MPDU_INFO_EOSP_LSB 24 -#define RX_MPDU_INFO_EOSP_MSB 24 -#define RX_MPDU_INFO_EOSP_MASK 0x01000000 - -#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 -#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 -#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 -#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 - -#define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 -#define RX_MPDU_INFO_ORDER_LSB 26 -#define RX_MPDU_INFO_ORDER_MSB 26 -#define RX_MPDU_INFO_ORDER_MASK 0x04000000 - -#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 -#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 -#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 -#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 - -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 - -#define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 -#define RX_MPDU_INFO_DIRECTED_LSB 29 -#define RX_MPDU_INFO_DIRECTED_MSB 29 -#define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 - -#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 -#define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 -#define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 -#define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 - -#define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 -#define RX_MPDU_INFO_RESERVED_13_LSB 31 -#define RX_MPDU_INFO_RESERVED_13_MSB 31 -#define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 - -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff - -#define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c -#define RX_MPDU_INFO_VDEV_ID_LSB 0 -#define RX_MPDU_INFO_VDEV_ID_MSB 7 -#define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff - -#define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c -#define RX_MPDU_INFO_SERVICE_CODE_LSB 8 -#define RX_MPDU_INFO_SERVICE_CODE_MSB 16 -#define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 - -#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c -#define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 -#define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 -#define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 - -#define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c -#define RX_MPDU_INFO_SRC_INFO_LSB 18 -#define RX_MPDU_INFO_SRC_INFO_MSB 29 -#define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 - -#define RX_MPDU_INFO_RESERVED_23A_OFFSET 0x0000005c -#define RX_MPDU_INFO_RESERVED_23A_LSB 30 -#define RX_MPDU_INFO_RESERVED_23A_MSB 30 -#define RX_MPDU_INFO_RESERVED_23A_MASK 0x40000000 - -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 - -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET 0x0000006c -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB 1 -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB 1 -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK 0x00000002 - -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_LSB 2 -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MSB 2 -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MASK 0x00000004 - -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_LSB 3 -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MSB 3 -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MASK 0x00000008 - -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_LSB 4 -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MSB 4 -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MASK 0x00000010 - -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_LSB 5 -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MSB 5 -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MASK 0x00000020 - -#define RX_MPDU_INFO_RX_MISC_CONFIG_OFFSET 0x0000006c -#define RX_MPDU_INFO_RX_MISC_CONFIG_LSB 6 -#define RX_MPDU_INFO_RX_MISC_CONFIG_MSB 8 -#define RX_MPDU_INFO_RX_MISC_CONFIG_MASK 0x000001c0 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_LSB 9 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MSB 10 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MASK 0x00000600 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_LSB 11 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MSB 12 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MASK 0x00001800 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_LSB 13 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MSB 14 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MASK 0x00006000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_LSB 15 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_MSB 15 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_MASK 0x00008000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_LSB 16 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_MSB 16 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_MASK 0x00010000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_VALID_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_VALID_LSB 17 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_VALID_MSB 17 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_VALID_MASK 0x00020000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 18 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 18 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x00040000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 19 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 19 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x00080000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 20 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 20 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x00100000 - -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_LSB 21 -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MSB 22 -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MASK 0x00600000 - -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_LSB 23 -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MSB 24 -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MASK 0x01800000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_EN_LSB 25 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_EN_MSB 25 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_EN_MASK 0x02000000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_CTRL_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_CTRL_EN_LSB 26 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_CTRL_EN_MSB 26 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_CTRL_EN_MASK 0x04000000 - -#define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c -#define RX_MPDU_INFO_RESERVED_27A_LSB 27 -#define RX_MPDU_INFO_RESERVED_27A_MSB 31 -#define RX_MPDU_INFO_RESERVED_27A_MASK 0xf8000000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_31_0_OFFSET 0x00000070 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_47_32_OFFSET 0x00000074 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_47_32_LSB 0 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_47_32_MSB 15 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD3_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 -#define RX_MPDU_INFO_RESERVED_29A_LSB 16 -#define RX_MPDU_INFO_RESERVED_29A_MSB 31 -#define RX_MPDU_INFO_RESERVED_29A_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_link_ptr.h b/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_link_ptr.h deleted file mode 100644 index e9d7e83a92cc..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_link_ptr.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_LINK_PTR_H_ -#define _RX_MPDU_LINK_PTR_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 - -struct rx_mpdu_link_ptr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info mpdu_link_desc_addr_info; -#else - struct buffer_addr_info mpdu_link_desc_addr_info; -#endif -}; - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_start.h b/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_start.h deleted file mode 100644 index 3f98c5b7377d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_mpdu_start.h +++ /dev/null @@ -1,702 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_START_H_ -#define _RX_MPDU_START_H_ - -#include "rx_mpdu_info.h" -#define NUM_OF_DWORDS_RX_MPDU_START 30 - -#define NUM_OF_QWORDS_RX_MPDU_START 15 - -struct rx_mpdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_mpdu_info rx_mpdu_info_details; -#else - struct rx_mpdu_info rx_mpdu_info_details; -#endif -}; - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x000000000000001f - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x0000000000000060 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x0000000000000080 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x0000000000000400 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x0000000000003800 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x000000000001c000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x0000000000020000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x0000000000040000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x0000000000080000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x0000000000100000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x0000000000200000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x0000000000400000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0x00000000ff800000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x0000000100000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x0000000200000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 38 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x0000040000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x0000780000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK 0x0007800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff8000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff0000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x0100000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc00000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000000000010 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x0000000000000010 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x0000000000000018 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000000000000018 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x0000000000000001 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB 1 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x0000000000000002 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB 2 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x0000000000000004 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB 3 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x0000000000000008 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x0000000000000010 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x0000000000000020 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x0000000000000040 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x0000000000000080 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x0000000000003c00 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x0000000000004000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x0000000000008000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x0000000000010000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x0000000000020000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x0000000000040000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x0000000000080000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x00000000fff00000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000300000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x0000020000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x0000040000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x0000080000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x0000100000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x0000200000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x00000000000000ff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB 11 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x0000000000000c00 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x0000000000001000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x0000000000002000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x0000000000004000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x0000000000008000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB 27 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x000000000fff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB 28 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x0000000010000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB 29 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x0000000020000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB 30 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x0000000040000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x0000000080000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x0000400000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x0000800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x0001000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x0004000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x0008000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x0010000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x0020000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x0040000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x0080000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x0100000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x0400000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x0800000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 60 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB 60 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x1000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x2000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x4000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x8000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK 0x000000ff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK 0x0001ff0000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK 0x3ffc000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_LSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MASK 0x4000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK 0x0000000100000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK 0x0000000200000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MASK 0x0000000400000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_LSB 35 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MSB 35 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MASK 0x0000000800000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_LSB 36 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MSB 36 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MASK 0x0000001000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_LSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MASK 0x0000002000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_LSB 38 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MASK 0x000001c000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_LSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MASK 0x0000060000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MASK 0x0000180000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_LSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MASK 0x0000600000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_RAW_EN_MASK 0x0000800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_NON00_RAW_EN_MASK 0x0001000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_VALID_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_VALID_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_VALID_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_VALID_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x0004000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x0008000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x0010000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_LSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MASK 0x0060000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_LSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MASK 0x0180000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_EN_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_EN_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_EN_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_CTRL_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_CTRL_EN_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_CTRL_EN_MSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_CTRL_EN_MASK 0x0400000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK 0xf800000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_31_0_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_47_32_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD3_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_desc_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_msdu_desc_info.h deleted file mode 100644 index 88569b653b64..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_desc_info.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_DESC_INFO_H_ -#define _RX_MSDU_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 - -struct rx_msdu_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t first_msdu_in_mpdu_flag : 1, - last_msdu_in_mpdu_flag : 1, - msdu_continuation : 1, - msdu_length : 14, - msdu_drop : 1, - sa_is_valid : 1, - da_is_valid : 1, - da_is_mcbc : 1, - l3_header_padding_msb : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - fr_ds : 1, - to_ds : 1, - intra_bss : 1, - dest_chip_id : 2, - decap_format : 2, - __reserved_g_0015 : 1; -#else - uint32_t __reserved_g_0015 : 1, - decap_format : 2, - dest_chip_id : 2, - intra_bss : 1, - to_ds : 1, - fr_ds : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - l3_header_padding_msb : 1, - da_is_mcbc : 1, - da_is_valid : 1, - sa_is_valid : 1, - msdu_drop : 1, - msdu_length : 14, - msdu_continuation : 1, - last_msdu_in_mpdu_flag : 1, - first_msdu_in_mpdu_flag : 1; -#endif -}; - -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 -#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 -#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_FR_DS_LSB 24 -#define RX_MSDU_DESC_INFO_FR_DS_MSB 24 -#define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 - -#define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_TO_DS_LSB 25 -#define RX_MSDU_DESC_INFO_TO_DS_MSB 25 -#define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 - -#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 -#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 -#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_details.h b/drivers/staging/fw-api/hw/fig/v1/rx_msdu_details.h deleted file mode 100644 index 0b763a473ce6..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_details.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_DETAILS_H_ -#define _RX_MSDU_DETAILS_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_msdu_ext_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 - -struct rx_msdu_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buffer_addr_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; -#else - struct buffer_addr_info buffer_addr_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; -#endif -}; - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xe0000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_end.h b/drivers/staging/fw-api/hw/fig/v1/rx_msdu_end.h deleted file mode 100644 index 34753b47edc7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_end.h +++ /dev/null @@ -1,1087 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_END_H_ -#define _RX_MSDU_END_H_ - -#define NUM_OF_DWORDS_RX_MSDU_END 32 - -#define NUM_OF_QWORDS_RX_MSDU_END 16 - -struct rx_msdu_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t ip_hdr_chksum : 16, - reported_mpdu_length : 14, - reserved_1a : 2; - uint32_t reserved_2a : 8, - cce_super_rule : 6, - cce_classify_not_done_truncate : 1, - cce_classify_not_done_cce_dis : 1, - cumulative_l3_checksum : 16; - uint32_t rule_indication_31_0 : 32; - uint32_t ipv6_options_crc : 32; - uint32_t da_offset : 6, - sa_offset : 6, - da_offset_valid : 1, - sa_offset_valid : 1, - reserved_5a : 2, - l3_type : 16; - uint32_t rule_indication_63_32 : 32; - uint32_t tcp_seq_number : 32; - uint32_t tcp_ack_number : 32; - uint32_t tcp_flag : 9, - lro_eligible : 1, - reserved_9a : 6, - window_size : 16; - uint32_t sa_sw_peer_id : 16, - sa_idx_timeout : 1, - da_idx_timeout : 1, - to_ds : 1, - tid : 4, - sa_is_valid : 1, - da_is_valid : 1, - da_is_mcbc : 1, - l3_header_padding : 2, - first_msdu : 1, - last_msdu : 1, - fr_ds : 1, - ip_chksum_fail_copy : 1; - uint32_t sa_idx : 16, - da_idx_or_sw_peer_id : 16; - uint32_t msdu_drop : 1, - reo_destination_indication : 5, - flow_idx : 20, - use_ppe : 1, - __reserved_g_0003 : 2, - vlan_ctag_stripped : 1, - vlan_stag_stripped : 1, - fragment_flag : 1; - uint32_t fse_metadata : 32; - uint32_t cce_metadata : 16, - tcp_udp_chksum : 16; - uint32_t aggregation_count : 8, - flow_aggregation_continuation : 1, - fisa_timeout : 1, - tcp_udp_chksum_fail_copy : 1, - msdu_limit_error : 1, - flow_idx_timeout : 1, - flow_idx_invalid : 1, - cce_match : 1, - amsdu_parser_error : 1, - cumulative_ip_length : 16; - uint32_t key_id_octet : 8, - reserved_16a : 24; - uint32_t reserved_17a : 6, - service_code : 9, - priority_valid : 1, - intra_bss : 1, - dest_chip_id : 2, - multicast_echo : 1, - wds_learning_event : 1, - wds_roaming_event : 1, - wds_keep_alive_event : 1, - __reserved_g_0015 : 1, - reserved_17b : 8; - uint32_t msdu_length : 14, - stbc : 1, - ipsec_esp : 1, - l3_offset : 7, - ipsec_ah : 1, - l4_offset : 8; - uint32_t msdu_number : 8, - decap_format : 2, - ipv4_proto : 1, - ipv6_proto : 1, - tcp_proto : 1, - udp_proto : 1, - ip_frag : 1, - tcp_only_ack : 1, - da_is_bcast_mcast : 1, - toeplitz_hash_sel : 2, - ip_fixed_header_valid : 1, - ip_extn_header_valid : 1, - tcp_udp_header_valid : 1, - mesh_control_present : 1, - ldpc : 1, - ip4_protocol_ip6_next_header : 8; - uint32_t vlan_ctag_ci : 16, - vlan_stag_ci : 16; - uint32_t peer_meta_data : 32; - uint32_t user_rssi : 8, - pkt_type : 4, - sgi : 2, - rate_mcs : 5, - receive_bandwidth : 3, - reception_type : 3, - mimo_ss_bitmap : 6, - msdu_done_copy : 1; - uint32_t flow_id_toeplitz : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t reserved_28a : 16, - sa_15_0 : 16; - uint32_t sa_47_16 : 32; - uint32_t first_mpdu : 1, - reserved_30a : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - a_msdu_error : 1, - reserved_30b : 1, - order : 1, - wifi_parser_error : 1, - overflow_err : 1, - msdu_length_err : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - sa_idx_invalid : 1, - da_idx_invalid : 1, - amsdu_addr_mismatch : 1, - rx_in_tx_decrypt_byp : 1, - encrypt_required : 1, - directed : 1, - buffer_fragment : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - fcs_err : 1; - uint32_t reserved_31a : 10, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - reserved_31b : 17, - msdu_done : 1; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_1a : 2, - reported_mpdu_length : 14, - ip_hdr_chksum : 16; - uint32_t cumulative_l3_checksum : 16, - cce_classify_not_done_cce_dis : 1, - cce_classify_not_done_truncate : 1, - cce_super_rule : 6, - reserved_2a : 8; - uint32_t rule_indication_31_0 : 32; - uint32_t ipv6_options_crc : 32; - uint32_t l3_type : 16, - reserved_5a : 2, - sa_offset_valid : 1, - da_offset_valid : 1, - sa_offset : 6, - da_offset : 6; - uint32_t rule_indication_63_32 : 32; - uint32_t tcp_seq_number : 32; - uint32_t tcp_ack_number : 32; - uint32_t window_size : 16, - reserved_9a : 6, - lro_eligible : 1, - tcp_flag : 9; - uint32_t ip_chksum_fail_copy : 1, - fr_ds : 1, - last_msdu : 1, - first_msdu : 1, - l3_header_padding : 2, - da_is_mcbc : 1, - da_is_valid : 1, - sa_is_valid : 1, - tid : 4, - to_ds : 1, - da_idx_timeout : 1, - sa_idx_timeout : 1, - sa_sw_peer_id : 16; - uint32_t da_idx_or_sw_peer_id : 16, - sa_idx : 16; - uint32_t fragment_flag : 1, - vlan_stag_stripped : 1, - vlan_ctag_stripped : 1, - __reserved_g_0003 : 2, - use_ppe : 1, - flow_idx : 20, - reo_destination_indication : 5, - msdu_drop : 1; - uint32_t fse_metadata : 32; - uint32_t tcp_udp_chksum : 16, - cce_metadata : 16; - uint32_t cumulative_ip_length : 16, - amsdu_parser_error : 1, - cce_match : 1, - flow_idx_invalid : 1, - flow_idx_timeout : 1, - msdu_limit_error : 1, - tcp_udp_chksum_fail_copy : 1, - fisa_timeout : 1, - flow_aggregation_continuation : 1, - aggregation_count : 8; - uint32_t reserved_16a : 24, - key_id_octet : 8; - uint32_t reserved_17b : 8, - __reserved_g_0015 : 1, - wds_keep_alive_event : 1, - wds_roaming_event : 1, - wds_learning_event : 1, - multicast_echo : 1, - dest_chip_id : 2, - intra_bss : 1, - priority_valid : 1, - service_code : 9, - reserved_17a : 6; - uint32_t l4_offset : 8, - ipsec_ah : 1, - l3_offset : 7, - ipsec_esp : 1, - stbc : 1, - msdu_length : 14; - uint32_t ip4_protocol_ip6_next_header : 8, - ldpc : 1, - mesh_control_present : 1, - tcp_udp_header_valid : 1, - ip_extn_header_valid : 1, - ip_fixed_header_valid : 1, - toeplitz_hash_sel : 2, - da_is_bcast_mcast : 1, - tcp_only_ack : 1, - ip_frag : 1, - udp_proto : 1, - tcp_proto : 1, - ipv6_proto : 1, - ipv4_proto : 1, - decap_format : 2, - msdu_number : 8; - uint32_t vlan_stag_ci : 16, - vlan_ctag_ci : 16; - uint32_t peer_meta_data : 32; - uint32_t msdu_done_copy : 1, - mimo_ss_bitmap : 6, - reception_type : 3, - receive_bandwidth : 3, - rate_mcs : 5, - sgi : 2, - pkt_type : 4, - user_rssi : 8; - uint32_t flow_id_toeplitz : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t sa_15_0 : 16, - reserved_28a : 16; - uint32_t sa_47_16 : 32; - uint32_t fcs_err : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - buffer_fragment : 1, - directed : 1, - encrypt_required : 1, - rx_in_tx_decrypt_byp : 1, - amsdu_addr_mismatch : 1, - da_idx_invalid : 1, - sa_idx_invalid : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - msdu_length_err : 1, - overflow_err : 1, - wifi_parser_error : 1, - order : 1, - reserved_30b : 1, - a_msdu_error : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - reserved_30a : 1, - first_mpdu : 1; - uint32_t msdu_done : 1, - reserved_31b : 17, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - reserved_31a : 10; -#endif -}; - -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RESERVED_0_LSB 9 -#define RX_MSDU_END_RESERVED_0_MSB 15 -#define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_END_PHY_PPDU_ID_LSB 16 -#define RX_MSDU_END_PHY_PPDU_ID_MSB 31 -#define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000 -#define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32 -#define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47 -#define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000 - -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000 - -#define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RESERVED_1A_LSB 62 -#define RX_MSDU_END_RESERVED_1A_MSB 63 -#define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000 - -#define RX_MSDU_END_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_MSDU_END_RESERVED_2A_LSB 0 -#define RX_MSDU_END_RESERVED_2A_MSB 7 -#define RX_MSDU_END_RESERVED_2A_MASK 0x00000000000000ff - -#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 -#define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 -#define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00 - -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000 - -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000 - -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008 -#define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32 -#define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63 -#define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000 - -#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000010 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff - -#define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010 -#define RX_MSDU_END_DA_OFFSET_LSB 32 -#define RX_MSDU_END_DA_OFFSET_MSB 37 -#define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000 - -#define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010 -#define RX_MSDU_END_SA_OFFSET_LSB 38 -#define RX_MSDU_END_SA_OFFSET_MSB 43 -#define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000 - -#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010 -#define RX_MSDU_END_DA_OFFSET_VALID_LSB 44 -#define RX_MSDU_END_DA_OFFSET_VALID_MSB 44 -#define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000 - -#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010 -#define RX_MSDU_END_SA_OFFSET_VALID_LSB 45 -#define RX_MSDU_END_SA_OFFSET_VALID_MSB 45 -#define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000 - -#define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010 -#define RX_MSDU_END_RESERVED_5A_LSB 46 -#define RX_MSDU_END_RESERVED_5A_MSB 47 -#define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000 - -#define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_END_L3_TYPE_LSB 48 -#define RX_MSDU_END_L3_TYPE_MSB 63 -#define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000 - -#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000018 -#define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 -#define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 -#define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32 -#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63 -#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 - -#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020 -#define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 -#define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 -#define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020 -#define RX_MSDU_END_TCP_FLAG_LSB 32 -#define RX_MSDU_END_TCP_FLAG_MSB 40 -#define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000 - -#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020 -#define RX_MSDU_END_LRO_ELIGIBLE_LSB 41 -#define RX_MSDU_END_LRO_ELIGIBLE_MSB 41 -#define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000 - -#define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020 -#define RX_MSDU_END_RESERVED_9A_LSB 42 -#define RX_MSDU_END_RESERVED_9A_MSB 47 -#define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000 - -#define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020 -#define RX_MSDU_END_WINDOW_SIZE_LSB 48 -#define RX_MSDU_END_WINDOW_SIZE_MSB 63 -#define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000 - -#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 -#define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 -#define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x000000000000ffff - -#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 -#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 -#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000 - -#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 -#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 -#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000 - -#define RX_MSDU_END_TO_DS_OFFSET 0x0000000000000028 -#define RX_MSDU_END_TO_DS_LSB 18 -#define RX_MSDU_END_TO_DS_MSB 18 -#define RX_MSDU_END_TO_DS_MASK 0x0000000000040000 - -#define RX_MSDU_END_TID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_TID_LSB 19 -#define RX_MSDU_END_TID_MSB 22 -#define RX_MSDU_END_TID_MASK 0x0000000000780000 - -#define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IS_VALID_LSB 23 -#define RX_MSDU_END_SA_IS_VALID_MSB 23 -#define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000 - -#define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IS_VALID_LSB 24 -#define RX_MSDU_END_DA_IS_VALID_MSB 24 -#define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000 - -#define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IS_MCBC_LSB 25 -#define RX_MSDU_END_DA_IS_MCBC_MSB 25 -#define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000 - -#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028 -#define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 -#define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 -#define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000 - -#define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028 -#define RX_MSDU_END_FIRST_MSDU_LSB 28 -#define RX_MSDU_END_FIRST_MSDU_MSB 28 -#define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000 - -#define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028 -#define RX_MSDU_END_LAST_MSDU_LSB 29 -#define RX_MSDU_END_LAST_MSDU_MSB 29 -#define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000 - -#define RX_MSDU_END_FR_DS_OFFSET 0x0000000000000028 -#define RX_MSDU_END_FR_DS_LSB 30 -#define RX_MSDU_END_FR_DS_MSB 30 -#define RX_MSDU_END_FR_DS_MASK 0x0000000040000000 - -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000 - -#define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IDX_LSB 32 -#define RX_MSDU_END_SA_IDX_MSB 47 -#define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000 - -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000 - -#define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030 -#define RX_MSDU_END_MSDU_DROP_LSB 0 -#define RX_MSDU_END_MSDU_DROP_MSB 0 -#define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001 - -#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e - -#define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FLOW_IDX_LSB 6 -#define RX_MSDU_END_FLOW_IDX_MSB 25 -#define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0 - -#define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030 -#define RX_MSDU_END_USE_PPE_LSB 26 -#define RX_MSDU_END_USE_PPE_MSB 26 -#define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000 - -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x0000000000000030 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x0000000020000000 - -#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x0000000000000030 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x0000000040000000 - -#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 -#define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 -#define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000080000000 - -#define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FSE_METADATA_LSB 32 -#define RX_MSDU_END_FSE_METADATA_MSB 63 -#define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CCE_METADATA_LSB 0 -#define RX_MSDU_END_CCE_METADATA_MSB 15 -#define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff - -#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000038 -#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 -#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 -#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_AGGREGATION_COUNT_LSB 32 -#define RX_MSDU_END_AGGREGATION_COUNT_MSB 39 -#define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000 - -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000 - -#define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FISA_TIMEOUT_LSB 41 -#define RX_MSDU_END_FISA_TIMEOUT_MSB 41 -#define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000 - -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000038 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 42 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 42 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000040000000000 - -#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000038 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 43 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 43 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000080000000000 - -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 44 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 44 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000100000000000 - -#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_IDX_INVALID_LSB 45 -#define RX_MSDU_END_FLOW_IDX_INVALID_MSB 45 -#define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000200000000000 - -#define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CCE_MATCH_LSB 46 -#define RX_MSDU_END_CCE_MATCH_MSB 46 -#define RX_MSDU_END_CCE_MATCH_MASK 0x0000400000000000 - -#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000038 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 47 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 47 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000800000000000 - -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 48 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 63 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff000000000000 - -#define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000040 -#define RX_MSDU_END_KEY_ID_OCTET_LSB 0 -#define RX_MSDU_END_KEY_ID_OCTET_MSB 7 -#define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff - -#define RX_MSDU_END_RESERVED_16A_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_16A_LSB 8 -#define RX_MSDU_END_RESERVED_16A_MSB 31 -#define RX_MSDU_END_RESERVED_16A_MASK 0x00000000ffffff00 - -#define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_17A_LSB 32 -#define RX_MSDU_END_RESERVED_17A_MSB 37 -#define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000 - -#define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040 -#define RX_MSDU_END_SERVICE_CODE_LSB 38 -#define RX_MSDU_END_SERVICE_CODE_MSB 46 -#define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000 - -#define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040 -#define RX_MSDU_END_PRIORITY_VALID_LSB 47 -#define RX_MSDU_END_PRIORITY_VALID_MSB 47 -#define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000 - -#define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040 -#define RX_MSDU_END_INTRA_BSS_LSB 48 -#define RX_MSDU_END_INTRA_BSS_MSB 48 -#define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000 - -#define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040 -#define RX_MSDU_END_DEST_CHIP_ID_LSB 49 -#define RX_MSDU_END_DEST_CHIP_ID_MSB 50 -#define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000 - -#define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040 -#define RX_MSDU_END_MULTICAST_ECHO_LSB 51 -#define RX_MSDU_END_MULTICAST_ECHO_MSB 51 -#define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000 - -#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52 -#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52 -#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000 - -#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53 -#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53 -#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000 - -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000 - -#define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_17B_LSB 56 -#define RX_MSDU_END_RESERVED_17B_MSB 63 -#define RX_MSDU_END_RESERVED_17B_MASK 0xff00000000000000 - -#define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MSDU_LENGTH_LSB 0 -#define RX_MSDU_END_MSDU_LENGTH_MSB 13 -#define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff - -#define RX_MSDU_END_STBC_OFFSET 0x0000000000000048 -#define RX_MSDU_END_STBC_LSB 14 -#define RX_MSDU_END_STBC_MSB 14 -#define RX_MSDU_END_STBC_MASK 0x0000000000004000 - -#define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPSEC_ESP_LSB 15 -#define RX_MSDU_END_IPSEC_ESP_MSB 15 -#define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000 - -#define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048 -#define RX_MSDU_END_L3_OFFSET_LSB 16 -#define RX_MSDU_END_L3_OFFSET_MSB 22 -#define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000 - -#define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPSEC_AH_LSB 23 -#define RX_MSDU_END_IPSEC_AH_MSB 23 -#define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000 - -#define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048 -#define RX_MSDU_END_L4_OFFSET_LSB 24 -#define RX_MSDU_END_L4_OFFSET_MSB 31 -#define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000 - -#define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MSDU_NUMBER_LSB 32 -#define RX_MSDU_END_MSDU_NUMBER_MSB 39 -#define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000 - -#define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048 -#define RX_MSDU_END_DECAP_FORMAT_LSB 40 -#define RX_MSDU_END_DECAP_FORMAT_MSB 41 -#define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000 - -#define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPV4_PROTO_LSB 42 -#define RX_MSDU_END_IPV4_PROTO_MSB 42 -#define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000 - -#define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPV6_PROTO_LSB 43 -#define RX_MSDU_END_IPV6_PROTO_MSB 43 -#define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000 - -#define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_PROTO_LSB 44 -#define RX_MSDU_END_TCP_PROTO_MSB 44 -#define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000 - -#define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_UDP_PROTO_LSB 45 -#define RX_MSDU_END_UDP_PROTO_MSB 45 -#define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000 - -#define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_FRAG_LSB 46 -#define RX_MSDU_END_IP_FRAG_MSB 46 -#define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000 - -#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_ONLY_ACK_LSB 47 -#define RX_MSDU_END_TCP_ONLY_ACK_MSB 47 -#define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000 - -#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000 - -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000 - -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000 - -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000 - -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000 - -#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000 - -#define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048 -#define RX_MSDU_END_LDPC_LSB 55 -#define RX_MSDU_END_LDPC_MSB 55 -#define RX_MSDU_END_LDPC_MASK 0x0080000000000000 - -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000 - -#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000050 -#define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 -#define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 -#define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff - -#define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000050 -#define RX_MSDU_END_VLAN_STAG_CI_LSB 16 -#define RX_MSDU_END_VLAN_STAG_CI_MSB 31 -#define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_PEER_META_DATA_OFFSET 0x0000000000000050 -#define RX_MSDU_END_PEER_META_DATA_LSB 32 -#define RX_MSDU_END_PEER_META_DATA_MSB 63 -#define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058 -#define RX_MSDU_END_USER_RSSI_LSB 0 -#define RX_MSDU_END_USER_RSSI_MSB 7 -#define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff - -#define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058 -#define RX_MSDU_END_PKT_TYPE_LSB 8 -#define RX_MSDU_END_PKT_TYPE_MSB 11 -#define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00 - -#define RX_MSDU_END_SGI_OFFSET 0x0000000000000058 -#define RX_MSDU_END_SGI_LSB 12 -#define RX_MSDU_END_SGI_MSB 13 -#define RX_MSDU_END_SGI_MASK 0x0000000000003000 - -#define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RATE_MCS_LSB 14 -#define RX_MSDU_END_RATE_MCS_MSB 18 -#define RX_MSDU_END_RATE_MCS_MASK 0x000000000007c000 - -#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 19 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 21 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x0000000000380000 - -#define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RECEPTION_TYPE_LSB 22 -#define RX_MSDU_END_RECEPTION_TYPE_MSB 24 -#define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000001c00000 - -#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058 -#define RX_MSDU_END_MIMO_SS_BITMAP_LSB 25 -#define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 -#define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x000000007e000000 - -#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x0000000000000058 -#define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 -#define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 -#define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x0000000080000000 - -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000058 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000 - -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff - -#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060 -#define RX_MSDU_END_SW_PHY_META_DATA_LSB 32 -#define RX_MSDU_END_SW_PHY_META_DATA_MSB 63 -#define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000068 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000068 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 32 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 63 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 - -#define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070 -#define RX_MSDU_END_RESERVED_28A_LSB 0 -#define RX_MSDU_END_RESERVED_28A_MSB 15 -#define RX_MSDU_END_RESERVED_28A_MASK 0x000000000000ffff - -#define RX_MSDU_END_SA_15_0_OFFSET 0x0000000000000070 -#define RX_MSDU_END_SA_15_0_LSB 16 -#define RX_MSDU_END_SA_15_0_MSB 31 -#define RX_MSDU_END_SA_15_0_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_SA_47_16_OFFSET 0x0000000000000070 -#define RX_MSDU_END_SA_47_16_LSB 32 -#define RX_MSDU_END_SA_47_16_MSB 63 -#define RX_MSDU_END_SA_47_16_MASK 0xffffffff00000000 - -#define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078 -#define RX_MSDU_END_FIRST_MPDU_LSB 0 -#define RX_MSDU_END_FIRST_MPDU_MSB 0 -#define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001 - -#define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_30A_LSB 1 -#define RX_MSDU_END_RESERVED_30A_MSB 1 -#define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002 - -#define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MCAST_BCAST_LSB 2 -#define RX_MSDU_END_MCAST_BCAST_MSB 2 -#define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004 - -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008 - -#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010 - -#define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_POWER_MGMT_LSB 5 -#define RX_MSDU_END_POWER_MGMT_MSB 5 -#define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020 - -#define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078 -#define RX_MSDU_END_NON_QOS_LSB 6 -#define RX_MSDU_END_NON_QOS_MSB 6 -#define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040 - -#define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078 -#define RX_MSDU_END_NULL_DATA_LSB 7 -#define RX_MSDU_END_NULL_DATA_MSB 7 -#define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080 - -#define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MGMT_TYPE_LSB 8 -#define RX_MSDU_END_MGMT_TYPE_MSB 8 -#define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100 - -#define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_CTRL_TYPE_LSB 9 -#define RX_MSDU_END_CTRL_TYPE_MSB 9 -#define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200 - -#define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MORE_DATA_LSB 10 -#define RX_MSDU_END_MORE_DATA_MSB 10 -#define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400 - -#define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078 -#define RX_MSDU_END_EOSP_LSB 11 -#define RX_MSDU_END_EOSP_MSB 11 -#define RX_MSDU_END_EOSP_MASK 0x0000000000000800 - -#define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_A_MSDU_ERROR_LSB 12 -#define RX_MSDU_END_A_MSDU_ERROR_MSB 12 -#define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000 - -#define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_30B_LSB 13 -#define RX_MSDU_END_RESERVED_30B_MSB 13 -#define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000002000 - -#define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078 -#define RX_MSDU_END_ORDER_LSB 14 -#define RX_MSDU_END_ORDER_MSB 14 -#define RX_MSDU_END_ORDER_MASK 0x0000000000004000 - -#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 -#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 -#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000008000 - -#define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_OVERFLOW_ERR_LSB 16 -#define RX_MSDU_END_OVERFLOW_ERR_MSB 16 -#define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000 - -#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 -#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 -#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000 - -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000 - -#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078 -#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 -#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 -#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000 - -#define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078 -#define RX_MSDU_END_SA_IDX_INVALID_LSB 20 -#define RX_MSDU_END_SA_IDX_INVALID_MSB 20 -#define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000 - -#define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DA_IDX_INVALID_LSB 21 -#define RX_MSDU_END_DA_IDX_INVALID_MSB 21 -#define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000 - -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x0000000000400000 - -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000 - -#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 -#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 -#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000 - -#define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DIRECTED_LSB 25 -#define RX_MSDU_END_DIRECTED_MSB 25 -#define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000 - -#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 -#define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 -#define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000 - -#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 -#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 -#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000 - -#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 -#define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 -#define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000 - -#define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DECRYPT_ERR_LSB 29 -#define RX_MSDU_END_DECRYPT_ERR_MSB 29 -#define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000 - -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000 - -#define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_FCS_ERR_LSB 31 -#define RX_MSDU_END_FCS_ERR_MSB 31 -#define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000 - -#define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_31A_LSB 32 -#define RX_MSDU_END_RESERVED_31A_MSB 41 -#define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000 - -#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000 - -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000 - -#define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_31B_LSB 46 -#define RX_MSDU_END_RESERVED_31B_MSB 62 -#define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc00000000000 - -#define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MSDU_DONE_LSB 63 -#define RX_MSDU_END_MSDU_DONE_MSB 63 -#define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_ext_desc_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_msdu_ext_desc_info.h deleted file mode 100644 index 70bda69ddfec..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_ext_desc_info.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_EXT_DESC_INFO_H_ -#define _RX_MSDU_EXT_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1 - -struct rx_msdu_ext_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reo_destination_indication : 5, - service_code : 9, - priority_valid : 1, - data_offset : 12, - src_link_id : 3, - reserved_0a : 2; -#else - uint32_t reserved_0a : 2, - src_link_id : 3, - data_offset : 12, - priority_valid : 1, - service_code : 9, - reo_destination_indication : 5; -#endif -}; - -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_link.h b/drivers/staging/fw-api/hw/fig/v1/rx_msdu_link.h deleted file mode 100644 index c54357dae2ef..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_link.h +++ /dev/null @@ -1,2051 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_LINK_H_ -#define _RX_MSDU_LINK_H_ - -#include "uniform_descriptor_header.h" -#include "buffer_addr_info.h" -#include "rx_msdu_details.h" -#define NUM_OF_DWORDS_RX_MSDU_LINK 64 - -struct rx_msdu_link { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct uniform_descriptor_header descriptor_header; - struct buffer_addr_info next_msdu_link_desc_addr_info; - uint32_t reserved_3a : 32; - struct rx_msdu_details msdu_0; - struct rx_msdu_details msdu_1; - struct rx_msdu_details msdu_2; - struct rx_msdu_details msdu_3; - struct rx_msdu_details msdu_4; - struct rx_msdu_details msdu_5; - struct rx_msdu_details msdu_6; - struct rx_msdu_details msdu_7; - struct rx_msdu_details msdu_8; - struct rx_msdu_details msdu_9; - struct rx_msdu_details msdu_10; - struct rx_msdu_details msdu_11; - struct rx_msdu_details msdu_12; - struct rx_msdu_details msdu_13; - struct rx_msdu_details msdu_14; -#else - struct uniform_descriptor_header descriptor_header; - struct buffer_addr_info next_msdu_link_desc_addr_info; - uint32_t reserved_3a : 32; - struct rx_msdu_details msdu_0; - struct rx_msdu_details msdu_1; - struct rx_msdu_details msdu_2; - struct rx_msdu_details msdu_3; - struct rx_msdu_details msdu_4; - struct rx_msdu_details msdu_5; - struct rx_msdu_details msdu_6; - struct rx_msdu_details msdu_7; - struct rx_msdu_details msdu_8; - struct rx_msdu_details msdu_9; - struct rx_msdu_details msdu_10; - struct rx_msdu_details msdu_11; - struct rx_msdu_details msdu_12; - struct rx_msdu_details msdu_13; - struct rx_msdu_details msdu_14; -#endif -}; - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB 0 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB 3 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_RESERVED_3A_OFFSET 0x0000000c -#define RX_MSDU_LINK_RESERVED_3A_LSB 0 -#define RX_MSDU_LINK_RESERVED_3A_MSB 31 -#define RX_MSDU_LINK_RESERVED_3A_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000010 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000080 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000090 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000a0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000b0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000c0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000d0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000e0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000f0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_start.h b/drivers/staging/fw-api/hw/fig/v1/rx_msdu_start.h deleted file mode 100644 index e1e99c027c85..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_msdu_start.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_START_H_ -#define _RX_MSDU_START_H_ - -#define NUM_OF_DWORDS_RX_MSDU_START 10 - -#define NUM_OF_QWORDS_RX_MSDU_START 5 - -struct rx_msdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - rate_mcs : 5, - reserved_0 : 2, - phy_ppdu_id : 16; - uint32_t msdu_length : 14, - stbc : 1, - ipsec_esp : 1, - l3_offset : 7, - ipsec_ah : 1, - l4_offset : 8; - uint32_t msdu_number : 8, - decap_format : 2, - ipv4_proto : 1, - ipv6_proto : 1, - tcp_proto : 1, - udp_proto : 1, - ip_frag : 1, - tcp_only_ack : 1, - da_is_bcast_mcast : 1, - toeplitz_hash_sel : 2, - ip_fixed_header_valid : 1, - ip_extn_header_valid : 1, - tcp_udp_header_valid : 1, - mesh_control_present : 1, - ldpc : 1, - ip4_protocol_ip6_next_header : 8; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t flow_id_toeplitz : 32; - uint32_t user_rssi : 8, - pkt_type : 4, - sgi : 2, - reserved_5a : 4, - receive_bandwidth : 3, - reception_type : 3, - mimo_ss_bitmap : 8; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t vlan_ctag_ci : 16, - vlan_stag_ci : 16; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 2, - rate_mcs : 5, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t l4_offset : 8, - ipsec_ah : 1, - l3_offset : 7, - ipsec_esp : 1, - stbc : 1, - msdu_length : 14; - uint32_t ip4_protocol_ip6_next_header : 8, - ldpc : 1, - mesh_control_present : 1, - tcp_udp_header_valid : 1, - ip_extn_header_valid : 1, - ip_fixed_header_valid : 1, - toeplitz_hash_sel : 2, - da_is_bcast_mcast : 1, - tcp_only_ack : 1, - ip_frag : 1, - udp_proto : 1, - tcp_proto : 1, - ipv6_proto : 1, - ipv4_proto : 1, - decap_format : 2, - msdu_number : 8; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t flow_id_toeplitz : 32; - uint32_t mimo_ss_bitmap : 8, - reception_type : 3, - receive_bandwidth : 3, - reserved_5a : 4, - sgi : 2, - pkt_type : 4, - user_rssi : 8; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t vlan_stag_ci : 16, - vlan_ctag_ci : 16; -#endif -}; - -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MSDU_START_RATE_MCS_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RATE_MCS_LSB 9 -#define RX_MSDU_START_RATE_MCS_MSB 13 -#define RX_MSDU_START_RATE_MCS_MASK 0x0000000000003e00 - -#define RX_MSDU_START_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RESERVED_0_LSB 14 -#define RX_MSDU_START_RESERVED_0_MSB 15 -#define RX_MSDU_START_RESERVED_0_MASK 0x000000000000c000 - -#define RX_MSDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_START_PHY_PPDU_ID_LSB 16 -#define RX_MSDU_START_PHY_PPDU_ID_MSB 31 -#define RX_MSDU_START_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MSDU_START_MSDU_LENGTH_OFFSET 0x0000000000000000 -#define RX_MSDU_START_MSDU_LENGTH_LSB 32 -#define RX_MSDU_START_MSDU_LENGTH_MSB 45 -#define RX_MSDU_START_MSDU_LENGTH_MASK 0x00003fff00000000 - -#define RX_MSDU_START_STBC_OFFSET 0x0000000000000000 -#define RX_MSDU_START_STBC_LSB 46 -#define RX_MSDU_START_STBC_MSB 46 -#define RX_MSDU_START_STBC_MASK 0x0000400000000000 - -#define RX_MSDU_START_IPSEC_ESP_OFFSET 0x0000000000000000 -#define RX_MSDU_START_IPSEC_ESP_LSB 47 -#define RX_MSDU_START_IPSEC_ESP_MSB 47 -#define RX_MSDU_START_IPSEC_ESP_MASK 0x0000800000000000 - -#define RX_MSDU_START_L3_OFFSET_OFFSET 0x0000000000000000 -#define RX_MSDU_START_L3_OFFSET_LSB 48 -#define RX_MSDU_START_L3_OFFSET_MSB 54 -#define RX_MSDU_START_L3_OFFSET_MASK 0x007f000000000000 - -#define RX_MSDU_START_IPSEC_AH_OFFSET 0x0000000000000000 -#define RX_MSDU_START_IPSEC_AH_LSB 55 -#define RX_MSDU_START_IPSEC_AH_MSB 55 -#define RX_MSDU_START_IPSEC_AH_MASK 0x0080000000000000 - -#define RX_MSDU_START_L4_OFFSET_OFFSET 0x0000000000000000 -#define RX_MSDU_START_L4_OFFSET_LSB 56 -#define RX_MSDU_START_L4_OFFSET_MSB 63 -#define RX_MSDU_START_L4_OFFSET_MASK 0xff00000000000000 - -#define RX_MSDU_START_MSDU_NUMBER_OFFSET 0x0000000000000008 -#define RX_MSDU_START_MSDU_NUMBER_LSB 0 -#define RX_MSDU_START_MSDU_NUMBER_MSB 7 -#define RX_MSDU_START_MSDU_NUMBER_MASK 0x00000000000000ff - -#define RX_MSDU_START_DECAP_FORMAT_OFFSET 0x0000000000000008 -#define RX_MSDU_START_DECAP_FORMAT_LSB 8 -#define RX_MSDU_START_DECAP_FORMAT_MSB 9 -#define RX_MSDU_START_DECAP_FORMAT_MASK 0x0000000000000300 - -#define RX_MSDU_START_IPV4_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IPV4_PROTO_LSB 10 -#define RX_MSDU_START_IPV4_PROTO_MSB 10 -#define RX_MSDU_START_IPV4_PROTO_MASK 0x0000000000000400 - -#define RX_MSDU_START_IPV6_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IPV6_PROTO_LSB 11 -#define RX_MSDU_START_IPV6_PROTO_MSB 11 -#define RX_MSDU_START_IPV6_PROTO_MASK 0x0000000000000800 - -#define RX_MSDU_START_TCP_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_PROTO_LSB 12 -#define RX_MSDU_START_TCP_PROTO_MSB 12 -#define RX_MSDU_START_TCP_PROTO_MASK 0x0000000000001000 - -#define RX_MSDU_START_UDP_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_UDP_PROTO_LSB 13 -#define RX_MSDU_START_UDP_PROTO_MSB 13 -#define RX_MSDU_START_UDP_PROTO_MASK 0x0000000000002000 - -#define RX_MSDU_START_IP_FRAG_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_FRAG_LSB 14 -#define RX_MSDU_START_IP_FRAG_MSB 14 -#define RX_MSDU_START_IP_FRAG_MASK 0x0000000000004000 - -#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_ONLY_ACK_LSB 15 -#define RX_MSDU_START_TCP_ONLY_ACK_MSB 15 -#define RX_MSDU_START_TCP_ONLY_ACK_MASK 0x0000000000008000 - -#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000008 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB 16 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB 16 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK 0x0000000000010000 - -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB 17 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB 18 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK 0x0000000000060000 - -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB 19 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB 19 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK 0x0000000000080000 - -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB 20 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB 20 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK 0x0000000000100000 - -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB 21 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB 21 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK 0x0000000000200000 - -#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000008 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB 22 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB 22 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK 0x0000000000400000 - -#define RX_MSDU_START_LDPC_OFFSET 0x0000000000000008 -#define RX_MSDU_START_LDPC_LSB 23 -#define RX_MSDU_START_LDPC_MSB 23 -#define RX_MSDU_START_LDPC_MASK 0x0000000000800000 - -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0x00000000ff000000 - -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB 32 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB 63 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 - -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000010 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB 0 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB 31 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK 0x00000000ffffffff - -#define RX_MSDU_START_USER_RSSI_OFFSET 0x0000000000000010 -#define RX_MSDU_START_USER_RSSI_LSB 32 -#define RX_MSDU_START_USER_RSSI_MSB 39 -#define RX_MSDU_START_USER_RSSI_MASK 0x000000ff00000000 - -#define RX_MSDU_START_PKT_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_START_PKT_TYPE_LSB 40 -#define RX_MSDU_START_PKT_TYPE_MSB 43 -#define RX_MSDU_START_PKT_TYPE_MASK 0x00000f0000000000 - -#define RX_MSDU_START_SGI_OFFSET 0x0000000000000010 -#define RX_MSDU_START_SGI_LSB 44 -#define RX_MSDU_START_SGI_MSB 45 -#define RX_MSDU_START_SGI_MASK 0x0000300000000000 - -#define RX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RESERVED_5A_LSB 46 -#define RX_MSDU_START_RESERVED_5A_MSB 49 -#define RX_MSDU_START_RESERVED_5A_MASK 0x0003c00000000000 - -#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB 50 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB 52 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK 0x001c000000000000 - -#define RX_MSDU_START_RECEPTION_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RECEPTION_TYPE_LSB 53 -#define RX_MSDU_START_RECEPTION_TYPE_MSB 55 -#define RX_MSDU_START_RECEPTION_TYPE_MASK 0x00e0000000000000 - -#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET 0x0000000000000010 -#define RX_MSDU_START_MIMO_SS_BITMAP_LSB 56 -#define RX_MSDU_START_MIMO_SS_BITMAP_MSB 63 -#define RX_MSDU_START_MIMO_SS_BITMAP_MASK 0xff00000000000000 - -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000018 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000018 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 - -#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000020 -#define RX_MSDU_START_SW_PHY_META_DATA_LSB 0 -#define RX_MSDU_START_SW_PHY_META_DATA_MSB 31 -#define RX_MSDU_START_SW_PHY_META_DATA_MASK 0x00000000ffffffff - -#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET 0x0000000000000020 -#define RX_MSDU_START_VLAN_CTAG_CI_LSB 32 -#define RX_MSDU_START_VLAN_CTAG_CI_MSB 47 -#define RX_MSDU_START_VLAN_CTAG_CI_MASK 0x0000ffff00000000 - -#define RX_MSDU_START_VLAN_STAG_CI_OFFSET 0x0000000000000020 -#define RX_MSDU_START_VLAN_STAG_CI_LSB 48 -#define RX_MSDU_START_VLAN_STAG_CI_MSB 63 -#define RX_MSDU_START_VLAN_STAG_CI_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_ack_report.h b/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_ack_report.h deleted file mode 100644 index 345b14ea4255..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_ack_report.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_ACK_REPORT_H_ -#define _RX_PPDU_ACK_REPORT_H_ - -#include "ack_report.h" -#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 2 - -#define NUM_OF_QWORDS_RX_PPDU_ACK_REPORT 1 - -struct rx_ppdu_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ack_report ack_report_details; - uint32_t tlv64_padding : 32; -#else - struct ack_report ack_report_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB 0 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB 3 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK 0x000000000000000f - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB 4 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB 7 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000000f0 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB 8 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB 8 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK 0x0000000000000100 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB 9 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB 15 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK 0x000000000000fe00 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 - -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_LSB 32 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MSB 63 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_end_user_stats.h b/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_end_user_stats.h deleted file mode 100644 index 51db8f35a6ab..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_end_user_stats.h +++ /dev/null @@ -1,679 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_END_USER_STATS_H_ -#define _RX_PPDU_END_USER_STATS_H_ - -#include "rx_rxpcu_classification_overview.h" -#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30 - -#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 15 - -struct rx_ppdu_end_user_stats { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t sta_full_aid : 13, - mcs : 5, - nss : 3, - expected_response_ack_or_ba : 1, - reserved_1a : 10; - uint32_t sw_peer_id : 16, - mpdu_cnt_fcs_err : 11, - sw2rxdma0_buf_source_used : 1, - fw2rxdma0_buf_source_used : 1, - sw2rxdma1_buf_source_used : 1, - sw2rxdma2_buf_source_used : 1, - fw2rxdma1_buf_source_used : 1; - uint32_t mpdu_cnt_fcs_ok : 11, - frame_control_info_valid : 1, - qos_control_info_valid : 1, - ht_control_info_valid : 1, - data_sequence_control_info_valid : 1, - ht_control_info_null_valid : 1, - rxdma2fw0_ring_used : 1, - rxdma2fw1_ring_used : 1, - rxdma2fwreo_0_ring_used : 1, - rxdma2fwreo_1_ring_used : 1, - reserved_3a : 1, - ht_control_field_pkt_type : 4, - reserved_3b : 7; - uint32_t ast_index : 16, - frame_control_field : 16; - uint32_t first_data_seq_ctrl : 16, - qos_control_field : 16; - uint32_t ht_control_field : 32; - uint32_t fcs_ok_bitmap_31_0 : 32; - uint32_t fcs_ok_bitmap_63_32 : 32; - uint32_t udp_msdu_count : 16, - tcp_msdu_count : 16; - uint32_t other_msdu_count : 16, - tcp_ack_msdu_count : 16; - uint32_t sw_response_reference_ptr : 32; - uint32_t received_qos_data_tid_bitmap : 16, - received_qos_data_tid_eosp_bitmap : 16; - uint32_t qosctrl_15_8_tid0 : 8, - qosctrl_15_8_tid1 : 8, - qosctrl_15_8_tid2 : 8, - qosctrl_15_8_tid3 : 8; - uint32_t qosctrl_15_8_tid4 : 8, - qosctrl_15_8_tid5 : 8, - qosctrl_15_8_tid6 : 8, - qosctrl_15_8_tid7 : 8; - uint32_t qosctrl_15_8_tid8 : 8, - qosctrl_15_8_tid9 : 8, - qosctrl_15_8_tid10 : 8, - qosctrl_15_8_tid11 : 8; - uint32_t qosctrl_15_8_tid12 : 8, - qosctrl_15_8_tid13 : 8, - qosctrl_15_8_tid14 : 8, - qosctrl_15_8_tid15 : 8; - uint32_t mpdu_ok_byte_count : 25, - ampdu_delim_ok_count_6_0 : 7; - uint32_t ampdu_delim_err_count : 25, - ampdu_delim_ok_count_13_7 : 7; - uint32_t mpdu_err_byte_count : 25, - ampdu_delim_ok_count_20_14 : 7; - uint32_t non_consecutive_delimiter_err : 16, - retried_msdu_count : 16; - uint32_t ht_control_null_field : 32; - uint32_t sw_response_reference_ptr_ext : 32; - uint32_t corrupted_due_to_fifo_delay : 1, - frame_control_info_null_valid : 1, - frame_control_field_null : 16, - retried_mpdu_count : 11, - reserved_23a : 3; - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_24a : 4, - frame_control_info_mgmt_ctrl_valid : 1, - mac_addr_ad2_valid : 1, - mcast_bcast : 1, - frame_control_field_mgmt_ctrl : 16; - uint32_t user_ppdu_len : 24, - reserved_25a : 8; - uint32_t mac_addr_ad2_31_0 : 32; - uint32_t mac_addr_ad2_47_32 : 16, - amsdu_msdu_count : 16; - uint32_t non_amsdu_msdu_count : 16, - ucast_msdu_count : 16; - uint32_t bcast_msdu_count : 16, - mcast_bcast_msdu_count : 16; -#else - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t reserved_1a : 10, - expected_response_ack_or_ba : 1, - nss : 3, - mcs : 5, - sta_full_aid : 13; - uint32_t fw2rxdma1_buf_source_used : 1, - sw2rxdma2_buf_source_used : 1, - sw2rxdma1_buf_source_used : 1, - fw2rxdma0_buf_source_used : 1, - sw2rxdma0_buf_source_used : 1, - mpdu_cnt_fcs_err : 11, - sw_peer_id : 16; - uint32_t reserved_3b : 7, - ht_control_field_pkt_type : 4, - reserved_3a : 1, - rxdma2fwreo_1_ring_used : 1, - rxdma2fwreo_0_ring_used : 1, - rxdma2fw1_ring_used : 1, - rxdma2fw0_ring_used : 1, - ht_control_info_null_valid : 1, - data_sequence_control_info_valid : 1, - ht_control_info_valid : 1, - qos_control_info_valid : 1, - frame_control_info_valid : 1, - mpdu_cnt_fcs_ok : 11; - uint32_t frame_control_field : 16, - ast_index : 16; - uint32_t qos_control_field : 16, - first_data_seq_ctrl : 16; - uint32_t ht_control_field : 32; - uint32_t fcs_ok_bitmap_31_0 : 32; - uint32_t fcs_ok_bitmap_63_32 : 32; - uint32_t tcp_msdu_count : 16, - udp_msdu_count : 16; - uint32_t tcp_ack_msdu_count : 16, - other_msdu_count : 16; - uint32_t sw_response_reference_ptr : 32; - uint32_t received_qos_data_tid_eosp_bitmap : 16, - received_qos_data_tid_bitmap : 16; - uint32_t qosctrl_15_8_tid3 : 8, - qosctrl_15_8_tid2 : 8, - qosctrl_15_8_tid1 : 8, - qosctrl_15_8_tid0 : 8; - uint32_t qosctrl_15_8_tid7 : 8, - qosctrl_15_8_tid6 : 8, - qosctrl_15_8_tid5 : 8, - qosctrl_15_8_tid4 : 8; - uint32_t qosctrl_15_8_tid11 : 8, - qosctrl_15_8_tid10 : 8, - qosctrl_15_8_tid9 : 8, - qosctrl_15_8_tid8 : 8; - uint32_t qosctrl_15_8_tid15 : 8, - qosctrl_15_8_tid14 : 8, - qosctrl_15_8_tid13 : 8, - qosctrl_15_8_tid12 : 8; - uint32_t ampdu_delim_ok_count_6_0 : 7, - mpdu_ok_byte_count : 25; - uint32_t ampdu_delim_ok_count_13_7 : 7, - ampdu_delim_err_count : 25; - uint32_t ampdu_delim_ok_count_20_14 : 7, - mpdu_err_byte_count : 25; - uint32_t retried_msdu_count : 16, - non_consecutive_delimiter_err : 16; - uint32_t ht_control_null_field : 32; - uint32_t sw_response_reference_ptr_ext : 32; - uint32_t reserved_23a : 3, - retried_mpdu_count : 11, - frame_control_field_null : 16, - frame_control_info_null_valid : 1, - corrupted_due_to_fifo_delay : 1; - uint32_t frame_control_field_mgmt_ctrl : 16, - mcast_bcast : 1, - mac_addr_ad2_valid : 1, - frame_control_info_mgmt_ctrl_valid : 1, - reserved_24a : 4, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_25a : 8, - user_ppdu_len : 24; - uint32_t mac_addr_ad2_31_0 : 32; - uint32_t amsdu_msdu_count : 16, - mac_addr_ad2_47_32 : 16; - uint32_t ucast_msdu_count : 16, - non_amsdu_msdu_count : 16; - uint32_t mcast_bcast_msdu_count : 16, - bcast_msdu_count : 16; -#endif -}; - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 32 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 44 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff00000000 - -#define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_MCS_LSB 45 -#define RX_PPDU_END_USER_STATS_MCS_MSB 49 -#define RX_PPDU_END_USER_STATS_MCS_MASK 0x0003e00000000000 - -#define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_NSS_LSB 50 -#define RX_PPDU_END_USER_STATS_NSS_MSB 52 -#define RX_PPDU_END_USER_STATS_NSS_MASK 0x001c000000000000 - -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 53 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 53 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x0020000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 54 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffc0000000000000 - -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x0000000007ff0000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000008000000 - -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_LSB 28 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MSB 28 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000010000000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000020000000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_LSB 30 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MSB 30 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MASK 0x0000000040000000 - -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_LSB 31 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MSB 31 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000080000000 - -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 42 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff00000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 43 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 43 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x0000080000000000 - -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 44 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 44 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x0000100000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 45 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 45 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x0000200000000000 - -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 46 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 46 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x0000400000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 47 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 47 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x0000800000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_LSB 48 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MSB 48 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MASK 0x0001000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_LSB 49 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MSB 49 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MASK 0x0002000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_LSB 50 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MSB 50 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MASK 0x0004000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_LSB 51 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MSB 51 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MASK 0x0008000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_LSB 52 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_MSB 52 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_MASK 0x0010000000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 53 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 56 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e0000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 57 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 -#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 -#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 32 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 47 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 48 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 63 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 32 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 63 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 47 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 32 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 63 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 32 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 39 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff00000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 40 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 47 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff0000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 48 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 55 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 56 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 63 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x00000000000000ff - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x000000000000ff00 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x0000000000ff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0x00000000ff000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 32 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 39 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff00000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 40 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 47 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff0000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 48 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 55 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 56 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 63 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x00000000000000ff - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x000000000000ff00 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x0000000000ff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0x00000000ff000000 - -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 56 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff00000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 57 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 63 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x0000000001ffffff - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0x00000000fe000000 - -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 56 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff00000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 57 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 63 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 32 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 63 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 33 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 33 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x0000000200000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 34 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 49 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc00000000 - -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 50 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 60 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 61 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe000000000000000 - -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB 2 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB 8 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB 9 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB 12 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK 0x0000000000001e00 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB 13 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB 13 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK 0x0000000000002000 - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB 14 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB 14 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK 0x0000000000004000 - -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB 15 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB 15 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK 0x0000000000008000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB 16 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB 31 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB 32 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB 55 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK 0x00ffffff00000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB 56 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB 0 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB 31 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB 32 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB 47 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB 15 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB 47 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_end_user_stats_ext.h b/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_end_user_stats_ext.h deleted file mode 100644 index 0a11202db481..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_end_user_stats_ext.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_END_USER_STATS_EXT_H_ -#define _RX_PPDU_END_USER_STATS_EXT_H_ - -#include "rx_rxpcu_classification_overview.h" -#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8 - -#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS_EXT 4 - -struct rx_ppdu_end_user_stats_ext { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t fcs_ok_bitmap_95_64 : 32; - uint32_t fcs_ok_bitmap_127_96 : 32; - uint32_t fcs_ok_bitmap_159_128 : 32; - uint32_t fcs_ok_bitmap_191_160 : 32; - uint32_t fcs_ok_bitmap_223_192 : 32; - uint32_t fcs_ok_bitmap_255_224 : 32; - uint32_t corrupted_due_to_fifo_delay : 1, - reserved_7a : 31; -#else - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t fcs_ok_bitmap_95_64 : 32; - uint32_t fcs_ok_bitmap_127_96 : 32; - uint32_t fcs_ok_bitmap_159_128 : 32; - uint32_t fcs_ok_bitmap_191_160 : 32; - uint32_t fcs_ok_bitmap_223_192 : 32; - uint32_t fcs_ok_bitmap_255_224 : 32; - uint32_t reserved_7a : 31, - corrupted_due_to_fifo_delay : 1; -#endif -}; - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 - -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB 33 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK 0xfffffffe00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_no_ack_report.h b/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_no_ack_report.h deleted file mode 100644 index d9c54c04df32..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_no_ack_report.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_NO_ACK_REPORT_H_ -#define _RX_PPDU_NO_ACK_REPORT_H_ - -#include "no_ack_report.h" -#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4 - -#define NUM_OF_QWORDS_RX_PPDU_NO_ACK_REPORT 2 - -struct rx_ppdu_no_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct no_ack_report no_ack_report_details; -#else - struct no_ack_report no_ack_report_details; -#endif -}; - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB 0 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB 3 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK 0x000000000000000f - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB 4 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB 7 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000f0 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB 8 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB 15 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000000000ff00 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB 32 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB 55 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK 0x00ffffff00000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB 56 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB 56 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK 0x0100000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 57 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 60 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e00000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB 61 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB 63 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000000fff - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000fff000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB 24 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB 31 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK 0x00000000ff000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 32 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 43 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff00000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB 44 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB 63 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK 0xfffff00000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_start.h b/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_start.h deleted file mode 100644 index 19765eb4409b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_start.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_START_H_ -#define _RX_PPDU_START_H_ - -#define NUM_OF_DWORDS_RX_PPDU_START 6 - -#define NUM_OF_QWORDS_RX_PPDU_START 3 - -struct rx_ppdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - preamble_time_to_rxframe : 8, - reserved_0a : 8; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t rxframe_assert_timestamp : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 8, - preamble_time_to_rxframe : 8, - phy_ppdu_id : 16; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t rxframe_assert_timestamp : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_START_PHY_PPDU_ID_LSB 0 -#define RX_PPDU_START_PHY_PPDU_ID_MSB 15 -#define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000 - -#define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_PPDU_START_RESERVED_0A_LSB 24 -#define RX_PPDU_START_RESERVED_0A_MSB 31 -#define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000 - -#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000 -#define RX_PPDU_START_SW_PHY_META_DATA_LSB 32 -#define RX_PPDU_START_SW_PHY_META_DATA_MSB 63 -#define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000 - -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 - -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff - -#define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010 -#define RX_PPDU_START_TLV64_PADDING_LSB 32 -#define RX_PPDU_START_TLV64_PADDING_MSB 63 -#define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_start_user_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_start_user_info.h deleted file mode 100644 index e0caf9b2ac24..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_ppdu_start_user_info.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_START_USER_INFO_H_ -#define _RX_PPDU_START_USER_INFO_H_ - -#include "receive_user_info.h" -#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8 - -#define NUM_OF_QWORDS_RX_PPDU_START_USER_INFO 4 - -struct rx_ppdu_start_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_user_info receive_user_info_details; -#else - struct receive_user_info receive_user_info_details; -#endif -}; - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 36 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000001f00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 37 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 38 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000006000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 1 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x0000000000000002 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB 2 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB 3 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK 0x000000000000000c - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB 4 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB 5 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK 0x0000000000000030 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB 6 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB 7 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK 0x00000000000000c0 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 62 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc000000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_preamble.h b/drivers/staging/fw-api/hw/fig/v1/rx_preamble.h deleted file mode 100644 index 807463753865..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_preamble.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PREAMBLE_H_ -#define _RX_PREAMBLE_H_ - -#define NUM_OF_DWORDS_RX_PREAMBLE 2 - -#define NUM_OF_QWORDS_RX_PREAMBLE 1 - -struct rx_preamble { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t num_users : 6, - pkt_type : 4, - direction : 1, - reserved_0a : 21; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 21, - direction : 1, - pkt_type : 4, - num_users : 6; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PREAMBLE_NUM_USERS_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_NUM_USERS_LSB 0 -#define RX_PREAMBLE_NUM_USERS_MSB 5 -#define RX_PREAMBLE_NUM_USERS_MASK 0x000000000000003f - -#define RX_PREAMBLE_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_PKT_TYPE_LSB 6 -#define RX_PREAMBLE_PKT_TYPE_MSB 9 -#define RX_PREAMBLE_PKT_TYPE_MASK 0x00000000000003c0 - -#define RX_PREAMBLE_DIRECTION_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_DIRECTION_LSB 10 -#define RX_PREAMBLE_DIRECTION_MSB 10 -#define RX_PREAMBLE_DIRECTION_MASK 0x0000000000000400 - -#define RX_PREAMBLE_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_RESERVED_0A_LSB 11 -#define RX_PREAMBLE_RESERVED_0A_MSB 31 -#define RX_PREAMBLE_RESERVED_0A_MASK 0x00000000fffff800 - -#define RX_PREAMBLE_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_TLV64_PADDING_LSB 32 -#define RX_PREAMBLE_TLV64_PADDING_MSB 63 -#define RX_PREAMBLE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_response_required_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_response_required_info.h deleted file mode 100644 index 9d5364537a1c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_response_required_info.h +++ /dev/null @@ -1,750 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_RESPONSE_REQUIRED_INFO_H_ -#define _RX_RESPONSE_REQUIRED_INFO_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16 - -#define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8 - -struct rx_response_required_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - su_or_uplink_mu_reception : 1, - trigger_frame_received : 1, - __reserved_g_0012 : 2, - tb___reserved_g_0022_response_required : 2, - mac_security : 1, - filter_pass_monitor_ovrd : 1, - ast_search_incomplete : 1, - r2r_end_status_to_follow : 1, - __reserved_g_0016_listen_cca_check_at_phy_desc : 1, - __reserved_g_0016_listen_indication : 1, - three_or_more_type_subtypes : 1, - wait_sifs_config_valid : 1, - wait_sifs : 2; - uint32_t general_frame_control : 16, - second_frame_control : 16; - uint32_t duration : 16, - pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5, - sgi : 2, - stbc : 1, - ldpc : 1, - ampdu : 1, - rts_ta_grp_bit : 1; - uint32_t ctrl_frame_soliciting_resp : 1, - ast_fail_for_dot11ax_su_ext : 1, - service_dynamic : 1, - m_pkt : 1, - sta_partial_aid : 12, - group_id : 6, - ctrl_resp_pwr_mgmt : 1, - response_indication : 2, - ndp_indication : 1, - ndp_frame_type : 3, - second_frame_control_valid : 1, - ack_ba_resp_more_data : 1, - vht_ack : 1; - uint32_t sta_aid : 11, - interference : 1, - ects_as_tb_ppdu : 1, - reserved_4a : 3, - ack_id_ext : 10, - agc_cbw : 3, - service_cbw : 3; - uint32_t response_sta_count : 7, - __reserved_g_0035 : 1, - blackout_details_en : 1, - reserved : 2, - ht_vht_sig_cbw : 3, - cts_cbw : 3, - response_ack_count : 7, - response_assoc_ack_count : 7, - txop_duration_all_ones : 1; - uint32_t response_ba32_count : 7, - response_ba64_count : 7, - response_ba128_count : 7, - response_ba256_count : 7, - multi_tid : 1, - sw_response_tlv_from_crypto : 1, - dot11ax_dl_ul_flag : 1, - emlsr_main_tlv_if : 1; - uint32_t sw_response_frame_length : 16, - response_ba512_count : 7, - response_ba1024_count : 7, - reserved_7a : 2; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t dot11ax_received_format_indication : 1, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_bss_color_id : 6, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_cp_size : 2, - dot11ax_received_ltf_size : 2, - dot11ax_received_coding : 1, - dot11ax_received_dcm : 1, - dot11ax_received_doppler_indication : 1, - dot11ax_received_ext_ru_size : 4, - ftm_fields_valid : 1, - ftm_pe_nss : 3, - ftm_pe_ltf_size : 2, - ftm_pe_content : 1, - ftm_chain_csd_en : 1, - ftm_pe_chain_csd_en : 1; - uint32_t dot11ax_response_rate_source : 8, - dot11ax_ext_response_rate_source : 8, - sw_peer_id : 16; - uint32_t dot11be_puncture_bitmap : 16, - dot11be_response : 1, - punctured_response : 1, - eht_duplicate_mode : 2, - force_extra_symbol : 1, - ctrl_pkt_protect : 1, - mac_hdr_protect : 1, - reserved_13a : 3, - u_sig_puncture_pattern_encoding : 6; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t he_a_control_response_time : 12, - reserved_after_struct16 : 4; - uint32_t dso_primary20_index_select : 4, - dso_freq_subband_channel_bonding_mask : 16, - pad_duration : 5, - reserved_15a : 7; -#else - uint32_t wait_sifs : 2, - wait_sifs_config_valid : 1, - three_or_more_type_subtypes : 1, - __reserved_g_0016_listen_indication : 1, - __reserved_g_0016_listen_cca_check_at_phy_desc : 1, - r2r_end_status_to_follow : 1, - ast_search_incomplete : 1, - filter_pass_monitor_ovrd : 1, - mac_security : 1, - tb___reserved_g_0022_response_required : 2, - __reserved_g_0012 : 2, - trigger_frame_received : 1, - su_or_uplink_mu_reception : 1, - phy_ppdu_id : 16; - uint32_t second_frame_control : 16, - general_frame_control : 16; - uint32_t rts_ta_grp_bit : 1, - ampdu : 1, - ldpc : 1, - stbc : 1, - sgi : 2, - rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4, - duration : 16; - uint32_t vht_ack : 1, - ack_ba_resp_more_data : 1, - second_frame_control_valid : 1, - ndp_frame_type : 3, - ndp_indication : 1, - response_indication : 2, - ctrl_resp_pwr_mgmt : 1, - group_id : 6, - sta_partial_aid : 12, - m_pkt : 1, - service_dynamic : 1, - ast_fail_for_dot11ax_su_ext : 1, - ctrl_frame_soliciting_resp : 1; - uint32_t service_cbw : 3, - agc_cbw : 3, - ack_id_ext : 10, - reserved_4a : 3, - ects_as_tb_ppdu : 1, - interference : 1, - sta_aid : 11; - uint32_t txop_duration_all_ones : 1, - response_assoc_ack_count : 7, - response_ack_count : 7, - cts_cbw : 3, - ht_vht_sig_cbw : 3, - reserved : 2, - blackout_details_en : 1, - __reserved_g_0035 : 1, - response_sta_count : 7; - uint32_t emlsr_main_tlv_if : 1, - dot11ax_dl_ul_flag : 1, - sw_response_tlv_from_crypto : 1, - multi_tid : 1, - response_ba256_count : 7, - response_ba128_count : 7, - response_ba64_count : 7, - response_ba32_count : 7; - uint32_t reserved_7a : 2, - response_ba1024_count : 7, - response_ba512_count : 7, - sw_response_frame_length : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ftm_pe_chain_csd_en : 1, - ftm_chain_csd_en : 1, - ftm_pe_content : 1, - ftm_pe_ltf_size : 2, - ftm_pe_nss : 3, - ftm_fields_valid : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_received_doppler_indication : 1, - dot11ax_received_dcm : 1, - dot11ax_received_coding : 1, - dot11ax_received_ltf_size : 2, - dot11ax_received_cp_size : 2, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_bss_color_id : 6, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_format_indication : 1; - uint32_t sw_peer_id : 16, - dot11ax_ext_response_rate_source : 8, - dot11ax_response_rate_source : 8; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_13a : 3, - mac_hdr_protect : 1, - ctrl_pkt_protect : 1, - force_extra_symbol : 1, - eht_duplicate_mode : 2, - punctured_response : 1, - dot11be_response : 1, - dot11be_puncture_bitmap : 16; - uint32_t reserved_after_struct16 : 4, - he_a_control_response_time : 12; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint32_t reserved_15a : 7, - pad_duration : 5, - dso_freq_subband_channel_bonding_mask : 16, - dso_primary20_index_select : 4; -#endif -}; - -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x0000000000010000 - -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x0000000000020000 - -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x0000000000400000 - -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x0000000000800000 - -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x0000000001000000 - -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000002000000 - -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0x00000000c0000000 - -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x000000000000ffff - -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x00000000000f0000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000100000 - -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x0000000003e00000 - -#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 26 -#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x000000000c000000 - -#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 30 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x0000000040000000 - -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x0000000080000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 32 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x0000000100000000 - -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 33 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 33 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x0000000200000000 - -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 34 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 34 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x0000000400000000 - -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 35 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 35 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x0000000800000000 - -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 36 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff000000000 - -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 53 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 54 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x0040000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 56 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x0180000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 57 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 57 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x0200000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 58 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 60 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 61 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x2000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MASK 0x4000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MSB 10 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MASK 0x00000000000007ff - -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_LSB 11 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MSB 11 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MASK 0x0000000000000800 - -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_LSB 12 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MSB 12 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MASK 0x0000000000001000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_LSB 13 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MASK 0x000000000000e000 - -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x0000000003ff0000 - -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x000000001c000000 - -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0x00000000e0000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 38 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f00000000 - -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_LSB 40 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MSB 40 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MASK 0x0000010000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 41 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 42 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x0000060000000000 - -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 43 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 45 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x0000380000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 46 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c00000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 56 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x000000000000007f - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x0000000000003f80 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x00000000001fc000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x000000000fe00000 - -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000040000000 - -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_LSB 31 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MASK 0x0000000080000000 - -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f80000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 49 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 55 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x0080000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 56 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 58 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x0700000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 59 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 60 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x1800000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 61 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x2000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x4000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x00000000000000ff - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x000000000000ff00 - -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0x00000000ffff0000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 49 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 50 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 51 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 52 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 52 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x0010000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_LSB 53 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MSB 53 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MASK 0x0020000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_LSB 54 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MASK 0x0040000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 57 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x0380000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0x00000000f0000000 - -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MSB 35 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MASK 0x0000000f00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 36 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 51 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000ffff000000000 - -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_LSB 52 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MSB 56 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MASK 0x01f0000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_LSB 57 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MASK 0xfe00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_rxpcu_classification_overview.h b/drivers/staging/fw-api/hw/fig/v1/rx_rxpcu_classification_overview.h deleted file mode 100644 index 92489a5f5b2d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_rxpcu_classification_overview.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ -#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ - -#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 - -struct rx_rxpcu_classification_overview { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t filter_pass_mpdus : 1, - filter_pass_mpdus_fcs_ok : 1, - monitor_direct_mpdus : 1, - monitor_direct_mpdus_fcs_ok : 1, - monitor_other_mpdus : 1, - monitor_other_mpdus_fcs_ok : 1, - phyrx_abort_received : 1, - filter_pass_monitor_ovrd_mpdus : 1, - filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, - reserved_0 : 7, - phy_ppdu_id : 16; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, - filter_pass_monitor_ovrd_mpdus : 1, - phyrx_abort_received : 1, - monitor_other_mpdus_fcs_ok : 1, - monitor_other_mpdus : 1, - monitor_direct_mpdus_fcs_ok : 1, - monitor_direct_mpdus : 1, - filter_pass_mpdus_fcs_ok : 1, - filter_pass_mpdus : 1; -#endif -}; - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB 0 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB 0 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK 0x00000001 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK 0x00000004 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK 0x00000010 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK 0x00000040 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB 9 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB 15 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK 0x0000fe00 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB 16 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB 31 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_start_param.h b/drivers/staging/fw-api/hw/fig/v1/rx_start_param.h deleted file mode 100644 index bb2b87e3cc97..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_start_param.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_START_PARAM_H_ -#define _RX_START_PARAM_H_ - -#define NUM_OF_DWORDS_RX_START_PARAM 2 - -#define NUM_OF_QWORDS_RX_START_PARAM 1 - -struct rx_start_param { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pkt_type : 4, - reserved_0a : 12, - remaining_rx_time : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t remaining_rx_time : 16, - reserved_0a : 12, - pkt_type : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_START_PARAM_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_START_PARAM_PKT_TYPE_LSB 0 -#define RX_START_PARAM_PKT_TYPE_MSB 3 -#define RX_START_PARAM_PKT_TYPE_MASK 0x000000000000000f - -#define RX_START_PARAM_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_START_PARAM_RESERVED_0A_LSB 4 -#define RX_START_PARAM_RESERVED_0A_MSB 15 -#define RX_START_PARAM_RESERVED_0A_MASK 0x000000000000fff0 - -#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET 0x0000000000000000 -#define RX_START_PARAM_REMAINING_RX_TIME_LSB 16 -#define RX_START_PARAM_REMAINING_RX_TIME_MSB 31 -#define RX_START_PARAM_REMAINING_RX_TIME_MASK 0x00000000ffff0000 - -#define RX_START_PARAM_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_START_PARAM_TLV64_PADDING_LSB 32 -#define RX_START_PARAM_TLV64_PADDING_MSB 63 -#define RX_START_PARAM_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_timing_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_timing_info.h deleted file mode 100644 index ea6780e25c55..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_timing_info.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_TIMING_INFO_H_ -#define _RX_TIMING_INFO_H_ - -#define NUM_OF_DWORDS_RX_TIMING_INFO 5 - -struct rx_timing_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_timestamp_1_lower_32 : 32; - uint32_t phy_timestamp_1_upper_32 : 32; - uint32_t phy_timestamp_2_lower_32 : 32; - uint32_t phy_timestamp_2_upper_32 : 32; - uint32_t residual_phase_offset : 12, - sub_usec_ts_rx_end : 10, - reserved : 10; -#else - uint32_t phy_timestamp_1_lower_32 : 32; - uint32_t phy_timestamp_1_upper_32 : 32; - uint32_t phy_timestamp_2_lower_32 : 32; - uint32_t phy_timestamp_2_upper_32 : 32; - uint32_t reserved : 10, - sub_usec_ts_rx_end : 10, - residual_phase_offset : 12; -#endif -}; - -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000000 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000004 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x00000008 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000c -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000010 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_LSB 0 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MSB 11 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff - -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_OFFSET 0x00000010 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_LSB 12 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MSB 21 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MASK 0x003ff000 - -#define RX_TIMING_INFO_RESERVED_OFFSET 0x00000010 -#define RX_TIMING_INFO_RESERVED_LSB 22 -#define RX_TIMING_INFO_RESERVED_MSB 31 -#define RX_TIMING_INFO_RESERVED_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rx_trig_info.h b/drivers/staging/fw-api/hw/fig/v1/rx_trig_info.h deleted file mode 100644 index b6b074118bea..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rx_trig_info.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_TRIG_INFO_H_ -#define _RX_TRIG_INFO_H_ - -#define NUM_OF_DWORDS_RX_TRIG_INFO 2 - -#define NUM_OF_QWORDS_RX_TRIG_INFO 1 - -struct rx_trig_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_trigger_frame_type : 2, - trigger_resp_type : 3, - reserved_0 : 27; - uint32_t ppdu_duration : 16, - unique_destination_id : 16; -#else - uint32_t reserved_0 : 27, - trigger_resp_type : 3, - rx_trigger_frame_type : 2; - uint32_t unique_destination_id : 16, - ppdu_duration : 16; -#endif -}; - -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x0000000000000003 - -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x000000000000001c - -#define RX_TRIG_INFO_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_RESERVED_0_LSB 5 -#define RX_TRIG_INFO_RESERVED_0_MSB 31 -#define RX_TRIG_INFO_RESERVED_0_MASK 0x00000000ffffffe0 - -#define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_PPDU_DURATION_LSB 32 -#define RX_TRIG_INFO_PPDU_DURATION_MSB 47 -#define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff00000000 - -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 48 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 63 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rxpcu_early_rx_indication.h b/drivers/staging/fw-api/hw/fig/v1/rxpcu_early_rx_indication.h deleted file mode 100644 index d2dc464cf1cf..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rxpcu_early_rx_indication.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_EARLY_RX_INDICATION_H_ -#define _RXPCU_EARLY_RX_INDICATION_H_ - -#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 2 - -#define NUM_OF_QWORDS_RXPCU_EARLY_RX_INDICATION 1 - -struct rxpcu_early_rx_indication { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5, - dot11ax_received_ext_ru_size : 4, - reserved_0a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 18, - dot11ax_received_ext_ru_size : 4, - rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB 0 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB 3 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK 0x000000000000000f - -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB 4 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB 4 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK 0x0000000000000010 - -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB 5 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB 9 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK 0x00000000000003e0 - -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 10 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 13 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0000000000003c00 - -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB 14 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB 31 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK 0x00000000ffffc000 - -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_LSB 32 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MSB 63 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rxpcu_ppdu_end_info.h b/drivers/staging/fw-api/hw/fig/v1/rxpcu_ppdu_end_info.h deleted file mode 100644 index 2d53435fb817..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rxpcu_ppdu_end_info.h +++ /dev/null @@ -1,925 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_PPDU_END_INFO_H_ -#define _RXPCU_PPDU_END_INFO_H_ - -#include "phyrx_abort_request_info.h" -#include "macrx_abort_request_info.h" -#include "rxpcu_ppdu_end_layout_info.h" -#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 32 - -#define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 16 - -struct rxpcu_ppdu_end_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t wb_timestamp_lower_32 : 32; - uint32_t wb_timestamp_upper_32 : 32; - uint32_t rx_antenna : 24, - tx_ht_vht_ack : 1, - unsupported_mu_nc : 1, - otp_txbf_disable : 1, - previous_tlv_corrupted : 1, - phyrx_abort_request_info_valid : 1, - macrx_abort_request_info_valid : 1, - coex_wan_tx_from_start_of_rx_ratid1 : 1, - coex_wan_tx_after_start_of_rx_ratid1 : 1; - uint32_t coex_bt_tx_from_start_of_rx : 1, - coex_bt_tx_after_start_of_rx : 1, - coex_wan_tx_from_start_of_rx : 1, - coex_wan_tx_after_start_of_rx : 1, - coex_wlan_tx_from_start_of_rx : 1, - coex_wlan_tx_after_start_of_rx : 1, - mpdu_delimiter_errors_seen : 1, - __reserved_g_0012 : 2, - dialog_token : 8, - follow_up_dialog_token : 8, - bb_captured_channel : 1, - bb_captured_reason : 3, - bb_captured_timeout : 1, - __reserved_g_0066 : 1, - __reserved_g_0067 : 1; - uint32_t before_mpdu_count_passing_fcs : 10, - before_mpdu_count_failing_fcs : 10, - after_mpdu_count_passing_fcs : 10, - reserved_4 : 2; - uint32_t after_mpdu_count_failing_fcs : 10, - reserved_5 : 22; - uint32_t phy_timestamp_tx_lower_32 : 32; - uint32_t phy_timestamp_tx_upper_32 : 32; - uint32_t bb_length : 16, - bb_data : 1, - reserved_8 : 3, - first_bt_broadcast_status_details : 12; - uint32_t rx_ppdu_duration : 24, - reserved_9 : 8; - uint32_t ast_index : 16, - ast_index_valid : 1, - reserved_10 : 3, - second_bt_broadcast_status_details : 12; - struct phyrx_abort_request_info phyrx_abort_request_info_details; - struct macrx_abort_request_info macrx_abort_request_info_details; - uint16_t pre_bt_broadcast_status_details : 12, - reserved_12a : 4; - uint32_t non_qos_sn_info_valid : 1, - rts_or_trig_protected_ppdu : 1, - rts_or_trig_prot_type : 2, - reserved_13a : 2, - non_qos_sn_highest : 12, - non_qos_sn_highest_retry_setting : 1, - non_qos_sn_lowest : 12, - non_qos_sn_lowest_retry_setting : 1; - uint32_t qos_sn_1_info_valid : 1, - reserved_14a : 1, - qos_sn_1_tid : 4, - qos_sn_1_highest : 12, - qos_sn_1_highest_retry_setting : 1, - qos_sn_1_lowest : 12, - qos_sn_1_lowest_retry_setting : 1; - uint32_t qos_sn_2_info_valid : 1, - reserved_15a : 1, - qos_sn_2_tid : 4, - qos_sn_2_highest : 12, - qos_sn_2_highest_retry_setting : 1, - qos_sn_2_lowest : 12, - qos_sn_2_lowest_retry_setting : 1; - struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; - uint32_t corrupted_due_to_fifo_delay : 1, - qos_sn_1_more_frag_state : 1, - qos_sn_1_frag_num_state : 4, - qos_sn_2_more_frag_state : 1, - qos_sn_2_frag_num_state : 4, - rts_or_trig_prot_non_11a : 1, - rts_or_trig_prot_rate_mcs : 4, - rts_or_trig_prot_peer_addr_15_0 : 16; - uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; - uint32_t rts_or_trig_rx_count : 32; - uint32_t cts_or_null_tx_count : 32; - uint32_t coex_tracker2_tx_from_start_of_rx : 1, - coex_tracker2_tx_after_start_of_rx : 1, - coex_tracker3_tx_from_start_of_rx : 1, - coex_tracker3_tx_after_start_of_rx : 1, - coex_tracker4_tx_from_start_of_rx : 1, - coex_tracker4_tx_after_start_of_rx : 1, - coex_tracker5_tx_from_start_of_rx : 1, - coex_tracker5_tx_after_start_of_rx : 1, - coex_tracker6_tx_from_start_of_rx : 1, - coex_tracker6_tx_after_start_of_rx : 1, - reserved_30a : 22; - uint32_t rx_ppdu_end_marker : 32; -#else - uint32_t wb_timestamp_lower_32 : 32; - uint32_t wb_timestamp_upper_32 : 32; - uint32_t coex_wan_tx_after_start_of_rx_ratid1 : 1, - coex_wan_tx_from_start_of_rx_ratid1 : 1, - macrx_abort_request_info_valid : 1, - phyrx_abort_request_info_valid : 1, - previous_tlv_corrupted : 1, - otp_txbf_disable : 1, - unsupported_mu_nc : 1, - tx_ht_vht_ack : 1, - rx_antenna : 24; - uint32_t __reserved_g_0067 : 1, - __reserved_g_0066 : 1, - bb_captured_timeout : 1, - bb_captured_reason : 3, - bb_captured_channel : 1, - follow_up_dialog_token : 8, - dialog_token : 8, - __reserved_g_0012 : 2, - mpdu_delimiter_errors_seen : 1, - coex_wlan_tx_after_start_of_rx : 1, - coex_wlan_tx_from_start_of_rx : 1, - coex_wan_tx_after_start_of_rx : 1, - coex_wan_tx_from_start_of_rx : 1, - coex_bt_tx_after_start_of_rx : 1, - coex_bt_tx_from_start_of_rx : 1; - uint32_t reserved_4 : 2, - after_mpdu_count_passing_fcs : 10, - before_mpdu_count_failing_fcs : 10, - before_mpdu_count_passing_fcs : 10; - uint32_t reserved_5 : 22, - after_mpdu_count_failing_fcs : 10; - uint32_t phy_timestamp_tx_lower_32 : 32; - uint32_t phy_timestamp_tx_upper_32 : 32; - uint32_t first_bt_broadcast_status_details : 12, - reserved_8 : 3, - bb_data : 1, - bb_length : 16; - uint32_t reserved_9 : 8, - rx_ppdu_duration : 24; - uint32_t second_bt_broadcast_status_details : 12, - reserved_10 : 3, - ast_index_valid : 1, - ast_index : 16; - struct phyrx_abort_request_info phyrx_abort_request_info_details; - uint32_t reserved_12a : 4, - pre_bt_broadcast_status_details : 12; - struct macrx_abort_request_info macrx_abort_request_info_details; - uint32_t non_qos_sn_lowest_retry_setting : 1, - non_qos_sn_lowest : 12, - non_qos_sn_highest_retry_setting : 1, - non_qos_sn_highest : 12, - reserved_13a : 2, - rts_or_trig_prot_type : 2, - rts_or_trig_protected_ppdu : 1, - non_qos_sn_info_valid : 1; - uint32_t qos_sn_1_lowest_retry_setting : 1, - qos_sn_1_lowest : 12, - qos_sn_1_highest_retry_setting : 1, - qos_sn_1_highest : 12, - qos_sn_1_tid : 4, - reserved_14a : 1, - qos_sn_1_info_valid : 1; - uint32_t qos_sn_2_lowest_retry_setting : 1, - qos_sn_2_lowest : 12, - qos_sn_2_highest_retry_setting : 1, - qos_sn_2_highest : 12, - qos_sn_2_tid : 4, - reserved_15a : 1, - qos_sn_2_info_valid : 1; - struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; - uint32_t rts_or_trig_prot_peer_addr_15_0 : 16, - rts_or_trig_prot_rate_mcs : 4, - rts_or_trig_prot_non_11a : 1, - qos_sn_2_frag_num_state : 4, - qos_sn_2_more_frag_state : 1, - qos_sn_1_frag_num_state : 4, - qos_sn_1_more_frag_state : 1, - corrupted_due_to_fifo_delay : 1; - uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; - uint32_t rts_or_trig_rx_count : 32; - uint32_t cts_or_null_tx_count : 32; - uint32_t reserved_30a : 22, - coex_tracker6_tx_after_start_of_rx : 1, - coex_tracker6_tx_from_start_of_rx : 1, - coex_tracker5_tx_after_start_of_rx : 1, - coex_tracker5_tx_from_start_of_rx : 1, - coex_tracker4_tx_after_start_of_rx : 1, - coex_tracker4_tx_from_start_of_rx : 1, - coex_tracker3_tx_after_start_of_rx : 1, - coex_tracker3_tx_from_start_of_rx : 1, - coex_tracker2_tx_after_start_of_rx : 1, - coex_tracker2_tx_from_start_of_rx : 1; - uint32_t rx_ppdu_end_marker : 32; -#endif -}; - -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 32 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 63 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x0000000000ffffff - -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x0000000001000000 - -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x0000000002000000 - -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x0000000004000000 - -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x0000000008000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000010000000 - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000020000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_LSB 30 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MSB 30 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MASK 0x0000000040000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_LSB 31 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MSB 31 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MASK 0x0000000080000000 - -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 32 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 32 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 33 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 33 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 34 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 34 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x0000000400000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 35 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 35 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x0000000800000000 - -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 36 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 36 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x0000001000000000 - -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 37 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 37 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x0000002000000000 - -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 38 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 38 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x0000004000000000 - -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 41 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 48 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe0000000000 - -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 49 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 56 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 57 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 57 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x0200000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 58 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 60 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c00000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 61 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 61 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x2000000000000000 - -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x00000000000003ff - -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x00000000000ffc00 - -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x000000003ff00000 - -#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 -#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0x00000000c0000000 - -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 32 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 41 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 42 -#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 63 -#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc0000000000 - -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x0000000000000018 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000000000000018 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 32 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 63 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x000000000000ffff - -#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 -#define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 -#define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x0000000000010000 - -#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 -#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 -#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x00000000000e0000 - -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 - -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 32 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 55 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 56 -#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 63 -#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff00000000000000 - -#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 -#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 -#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x000000000000ffff - -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x0000000000010000 - -#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 -#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 -#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x00000000000e0000 - -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_LSB 42 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MSB 42 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MASK 0x0000040000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_LSB 43 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MSB 43 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MASK 0x0000080000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_LSB 44 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MSB 44 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MASK 0x0000100000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_LSB 45 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MSB 45 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MASK 0x0000200000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_LSB 46 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MSB 46 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MASK 0x0000400000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 47 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 47 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000800000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 48 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 63 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff000000000000 - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x000000000000ff00 - -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x000000000fff0000 - -#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0x00000000f0000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 32 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 32 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_LSB 33 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MSB 33 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_LSB 34 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MSB 35 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MASK 0x0000000c00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 36 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 37 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x0000003000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 38 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 49 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 50 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 50 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 51 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 62 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff8000000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 63 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 63 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x000000000000003c - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x000000000003ffc0 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x0000000000040000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x000000007ff80000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x0000000080000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 32 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 32 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 33 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 33 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 34 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 37 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c00000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 38 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 49 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 50 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 50 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 51 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 62 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff8000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 63 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 63 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x0000000000000003 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x00000000000000fc - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x0000000000003f00 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x00000000000fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x0000000003f00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 37 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 50 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 62 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0x00000000f0000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 60 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x000000000000007f - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x0000000000003f80 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0x00000000e0000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 57 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x00000000000000ff - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0x00000000ff000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 40 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff0000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x0000000000000060 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x0000000000000060 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x000000000000003c - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x0000000000000040 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x0000000000000780 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_LSB 11 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MSB 11 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MASK 0x0000000000000800 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_LSB 12 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MSB 15 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MASK 0x000000000000f000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_LSB 16 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MSB 31 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MASK 0x00000000ffff0000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_LSB 32 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MSB 63 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_OFFSET 0x0000000000000070 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_LSB 0 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MSB 31 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_OFFSET 0x0000000000000070 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_LSB 32 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MSB 63 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_LSB 0 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MSB 0 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_LSB 1 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MSB 1 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_LSB 2 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MSB 2 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MASK 0x0000000000000004 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_LSB 3 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MSB 3 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MASK 0x0000000000000008 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_LSB 4 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MSB 4 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MASK 0x0000000000000010 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_LSB 5 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MSB 5 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MASK 0x0000000000000020 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_LSB 6 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MSB 6 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MASK 0x0000000000000040 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_LSB 7 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MSB 7 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MASK 0x0000000000000080 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_LSB 8 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MSB 8 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MASK 0x0000000000000100 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_LSB 9 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MSB 9 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MASK 0x0000000000000200 - -#define RXPCU_PPDU_END_INFO_RESERVED_30A_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_LSB 10 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_MASK 0x00000000fffffc00 - -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 32 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 63 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rxpcu_ppdu_end_layout_info.h b/drivers/staging/fw-api/hw/fig/v1/rxpcu_ppdu_end_layout_info.h deleted file mode 100644 index 9d54e91522ec..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rxpcu_ppdu_end_layout_info.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_ -#define _RXPCU_PPDU_END_LAYOUT_INFO_H_ - -#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10 - -struct rxpcu_ppdu_end_layout_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rssi_legacy_offset : 2, - l_sig_a_offset : 6, - l_sig_b_offset : 6, - ht_sig_offset : 6, - vht_sig_a_offset : 6, - repeat_l_sig_a_offset : 6; - uint32_t he_sig_a_su_offset : 6, - he_sig_a_mu_dl_offset : 6, - he_sig_a_mu_ul_offset : 6, - generic_u_sig_offset : 6, - rssi_ht_offset : 7, - reserved_1a : 1; - uint32_t vht_sig_b_su20_offset : 7, - vht_sig_b_su40_offset : 7, - vht_sig_b_su80_offset : 7, - vht_sig_b_su160_offset : 7, - reserved_2a : 4; - uint32_t vht_sig_b_mu20_offset : 7, - vht_sig_b_mu40_offset : 7, - vht_sig_b_mu80_offset : 7, - vht_sig_b_mu160_offset : 7, - reserved_3a : 4; - uint32_t he_sig_b1_mu_offset : 7, - he_sig_b2_mu_offset : 7, - he_sig_b2_ofdma_offset : 7, - first_generic_eht_sig_offset : 7, - multiple_generic_eht_sig_included : 1, - reserved_4a : 3; - uint32_t common_user_info_offset : 7, - first_debug_info_offset : 8, - multiple_debug_info_included : 1, - first_other_receive_info_offset : 8, - multiple_other_receive_info_included : 1, - reserved_5a : 7; - uint32_t data_done_offset : 8, - generated_cbf_details_offset : 8, - pkt_end_part1_offset : 8, - location_offset : 8; - uint32_t __reserved_g_0011 : 8, - pkt_end_offset : 8, - abort_request_ack_offset : 8, - reserved_7a : 8; - uint32_t reserved_8a : 32; - uint32_t reserved_9a : 32; -#else - uint32_t repeat_l_sig_a_offset : 6, - vht_sig_a_offset : 6, - ht_sig_offset : 6, - l_sig_b_offset : 6, - l_sig_a_offset : 6, - rssi_legacy_offset : 2; - uint32_t reserved_1a : 1, - rssi_ht_offset : 7, - generic_u_sig_offset : 6, - he_sig_a_mu_ul_offset : 6, - he_sig_a_mu_dl_offset : 6, - he_sig_a_su_offset : 6; - uint32_t reserved_2a : 4, - vht_sig_b_su160_offset : 7, - vht_sig_b_su80_offset : 7, - vht_sig_b_su40_offset : 7, - vht_sig_b_su20_offset : 7; - uint32_t reserved_3a : 4, - vht_sig_b_mu160_offset : 7, - vht_sig_b_mu80_offset : 7, - vht_sig_b_mu40_offset : 7, - vht_sig_b_mu20_offset : 7; - uint32_t reserved_4a : 3, - multiple_generic_eht_sig_included : 1, - first_generic_eht_sig_offset : 7, - he_sig_b2_ofdma_offset : 7, - he_sig_b2_mu_offset : 7, - he_sig_b1_mu_offset : 7; - uint32_t reserved_5a : 7, - multiple_other_receive_info_included : 1, - first_other_receive_info_offset : 8, - multiple_debug_info_included : 1, - first_debug_info_offset : 8, - common_user_info_offset : 7; - uint32_t location_offset : 8, - pkt_end_part1_offset : 8, - generated_cbf_details_offset : 8, - data_done_offset : 8; - uint32_t reserved_7a : 8, - abort_request_ack_offset : 8, - pkt_end_offset : 8, - __reserved_g_0011 : 8; - uint32_t reserved_8a : 32; - uint32_t reserved_9a : 32; -#endif -}; - -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003 - -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc - -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff - -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/rxpt_classify_info.h b/drivers/staging/fw-api/hw/fig/v1/rxpt_classify_info.h deleted file mode 100644 index 7fc572ae2474..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/rxpt_classify_info.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPT_CLASSIFY_INFO_H_ -#define _RXPT_CLASSIFY_INFO_H_ - -#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 - -struct rxpt_classify_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reo_destination_indication : 5, - lmac_peer_id_msb : 2, - use_flow_id_toeplitz_clfy : 1, - pkt_selection_fp_ucast_data : 1, - pkt_selection_fp_mcast_data : 1, - pkt_selection_fp_1000 : 1, - rxdma0_source_ring_selection : 3, - rxdma0_destination_ring_selection : 3, - mcast_echo_drop_enable : 1, - wds_learning_detect_en : 1, - intrabss_check_en : 1, - use_ppe : 1, - ppe_routing_enable : 1, - cce_source_sel_en : 1, - reserved_0b : 9; -#else - uint32_t reserved_0b : 9, - cce_source_sel_en : 1, - ppe_routing_enable : 1, - use_ppe : 1, - intrabss_check_en : 1, - wds_learning_detect_en : 1, - mcast_echo_drop_enable : 1, - rxdma0_destination_ring_selection : 3, - rxdma0_source_ring_selection : 3, - pkt_selection_fp_1000 : 1, - pkt_selection_fp_mcast_data : 1, - pkt_selection_fp_ucast_data : 1, - use_flow_id_toeplitz_clfy : 1, - lmac_peer_id_msb : 2, - reo_destination_indication : 5; -#endif -}; - -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB 0 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB 4 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB 5 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB 6 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK 0x00000060 - -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB 10 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB 10 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK 0x00000400 - -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 - -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 - -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 - -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB 18 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB 18 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK 0x00040000 - -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB 19 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB 19 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK 0x00080000 - -#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_USE_PPE_LSB 20 -#define RXPT_CLASSIFY_INFO_USE_PPE_MSB 20 -#define RXPT_CLASSIFY_INFO_USE_PPE_MASK 0x00100000 - -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB 21 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB 21 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK 0x00200000 - -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_LSB 22 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MSB 22 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MASK 0x00400000 - -#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB 23 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB 31 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK 0xff800000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/seq_hwio.h b/drivers/staging/fw-api/hw/fig/v1/seq_hwio.h deleted file mode 100644 index 69111d08d535..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/seq_hwio.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef __SEQ_H__ -#define __SEQ_H__ - -#include "HALhwio.h" - -#define SEQ_INH(base, regtype, reg) \ - SEQ_##regtype##_INH(base, reg) - -#define SEQ_INMH(base, regtype, reg, mask) \ - SEQ_##regtype##_INMH(base, reg, mask) - -#define SEQ_INFH(base, regtype, reg, fld) \ - (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) - -#define SEQ_OUTH(base, regtype, reg, val) \ - SEQ_##regtype##_OUTH(base, reg, val) - -#define SEQ_OUTMH(base, regtype, reg, mask, val) \ - SEQ_##regtype##_OUTMH(base, reg, mask, val) - -#define SEQ_OUTFH(base, regtype, reg, fld, val) \ - SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) - -typedef enum { - SEC, - MS, - US, - NS -} SEQ_TimeUnit; - -extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); - -extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); - -#endif - diff --git a/drivers/staging/fw-api/hw/fig/v1/tcl_assist_cmd.h b/drivers/staging/fw-api/hw/fig/v1/tcl_assist_cmd.h deleted file mode 100644 index f7a5bd5287cb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tcl_assist_cmd.h +++ /dev/null @@ -1,411 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TCL_ASSIST_CMD_H_ -#define _TCL_ASSIST_CMD_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_TCL_ASSIST_CMD 16 - -struct tcl_assist_cmd { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_addr_info; - uint32_t buf_or_ext_desc_type : 1, - bank_id : 6, - vdev_id : 8, - data_length : 14, - to_fw_tqm : 2, - reserved_2a : 1; - uint32_t reserved_3a : 25, - metadata_length : 7; - uint32_t txpt_classify_info_index : 8, - txpt_classify_info_sel : 5, - txpt_classify_info_override : 1, - flow_override_enable : 1, - flow_select : 1, - hlos_tid : 4, - hlos_tid_overwrite : 1, - tos_tc_value : 8, - reserved_4a : 3; - uint32_t reserved_5a : 16, - l3_type : 16; - uint32_t l4_protocol : 8, - l4_port : 16, - l4_port_type : 1, - da_is_bcast_mcast : 1, - da_is_bcast : 1, - reserved_6a : 5; - uint32_t ip_address_31_0 : 32; - uint32_t ip_address_63_32 : 32; - uint32_t ip_address_95_64 : 32; - uint32_t ip_address_127_96 : 32; - uint32_t ip_da_or_sa : 1, - encap_length_change : 6, - encap_length_decrease : 1, - encap_length_override : 1, - type_or_length : 1, - snap_oui_zero_or_f8 : 1, - snap_oui_not_zero_and_not_f8 : 1, - msdu_color : 2, - tx_notify_frame : 3, - tqm_no_drop : 1, - reserved_11a : 12, - l3_checksum_enable : 1, - l4_checksum_enable : 1; - uint32_t buffer_timestamp : 19, - buffer_timestamp_valid : 1, - s_vlan_tag_present : 1, - c_vlan_tag_present : 1, - wmac_hdr_len : 7, - reserved_12a : 3; - uint32_t tcl_cmd_number : 32; - uint32_t reserved_14a : 32; - uint32_t reserved_15a : 20, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_addr_info; - uint32_t reserved_2a : 1, - to_fw_tqm : 2, - data_length : 14, - vdev_id : 8, - bank_id : 6, - buf_or_ext_desc_type : 1; - uint32_t metadata_length : 7, - reserved_3a : 25; - uint32_t reserved_4a : 3, - tos_tc_value : 8, - hlos_tid_overwrite : 1, - hlos_tid : 4, - flow_select : 1, - flow_override_enable : 1, - txpt_classify_info_override : 1, - txpt_classify_info_sel : 5, - txpt_classify_info_index : 8; - uint32_t l3_type : 16, - reserved_5a : 16; - uint32_t reserved_6a : 5, - da_is_bcast : 1, - da_is_bcast_mcast : 1, - l4_port_type : 1, - l4_port : 16, - l4_protocol : 8; - uint32_t ip_address_31_0 : 32; - uint32_t ip_address_63_32 : 32; - uint32_t ip_address_95_64 : 32; - uint32_t ip_address_127_96 : 32; - uint32_t l4_checksum_enable : 1, - l3_checksum_enable : 1, - reserved_11a : 12, - tqm_no_drop : 1, - tx_notify_frame : 3, - msdu_color : 2, - snap_oui_not_zero_and_not_f8 : 1, - snap_oui_zero_or_f8 : 1, - type_or_length : 1, - encap_length_override : 1, - encap_length_decrease : 1, - encap_length_change : 6, - ip_da_or_sa : 1; - uint32_t reserved_12a : 3, - wmac_hdr_len : 7, - c_vlan_tag_present : 1, - s_vlan_tag_present : 1, - buffer_timestamp_valid : 1, - buffer_timestamp : 19; - uint32_t tcl_cmd_number : 32; - uint32_t reserved_14a : 32; - uint32_t looping_count : 4, - ring_id : 8, - reserved_15a : 20; -#endif -}; - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_LSB 0 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MSB 0 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000001 - -#define TCL_ASSIST_CMD_BANK_ID_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_BANK_ID_LSB 1 -#define TCL_ASSIST_CMD_BANK_ID_MSB 6 -#define TCL_ASSIST_CMD_BANK_ID_MASK 0x0000007e - -#define TCL_ASSIST_CMD_VDEV_ID_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_VDEV_ID_LSB 7 -#define TCL_ASSIST_CMD_VDEV_ID_MSB 14 -#define TCL_ASSIST_CMD_VDEV_ID_MASK 0x00007f80 - -#define TCL_ASSIST_CMD_DATA_LENGTH_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_DATA_LENGTH_LSB 15 -#define TCL_ASSIST_CMD_DATA_LENGTH_MSB 28 -#define TCL_ASSIST_CMD_DATA_LENGTH_MASK 0x1fff8000 - -#define TCL_ASSIST_CMD_TO_FW_TQM_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_TO_FW_TQM_LSB 29 -#define TCL_ASSIST_CMD_TO_FW_TQM_MSB 30 -#define TCL_ASSIST_CMD_TO_FW_TQM_MASK 0x60000000 - -#define TCL_ASSIST_CMD_RESERVED_2A_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_RESERVED_2A_LSB 31 -#define TCL_ASSIST_CMD_RESERVED_2A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_2A_MASK 0x80000000 - -#define TCL_ASSIST_CMD_RESERVED_3A_OFFSET 0x0000000c -#define TCL_ASSIST_CMD_RESERVED_3A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_3A_MSB 24 -#define TCL_ASSIST_CMD_RESERVED_3A_MASK 0x01ffffff - -#define TCL_ASSIST_CMD_METADATA_LENGTH_OFFSET 0x0000000c -#define TCL_ASSIST_CMD_METADATA_LENGTH_LSB 25 -#define TCL_ASSIST_CMD_METADATA_LENGTH_MSB 31 -#define TCL_ASSIST_CMD_METADATA_LENGTH_MASK 0xfe000000 - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_LSB 0 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MSB 7 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MASK 0x000000ff - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_LSB 8 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MSB 12 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MASK 0x00001f00 - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_LSB 13 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MSB 13 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MASK 0x00002000 - -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_LSB 14 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MSB 14 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00004000 - -#define TCL_ASSIST_CMD_FLOW_SELECT_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_FLOW_SELECT_LSB 15 -#define TCL_ASSIST_CMD_FLOW_SELECT_MSB 15 -#define TCL_ASSIST_CMD_FLOW_SELECT_MASK 0x00008000 - -#define TCL_ASSIST_CMD_HLOS_TID_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_HLOS_TID_LSB 16 -#define TCL_ASSIST_CMD_HLOS_TID_MSB 19 -#define TCL_ASSIST_CMD_HLOS_TID_MASK 0x000f0000 - -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_LSB 20 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MSB 20 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MASK 0x00100000 - -#define TCL_ASSIST_CMD_TOS_TC_VALUE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_LSB 21 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_MSB 28 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_MASK 0x1fe00000 - -#define TCL_ASSIST_CMD_RESERVED_4A_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_RESERVED_4A_LSB 29 -#define TCL_ASSIST_CMD_RESERVED_4A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_4A_MASK 0xe0000000 - -#define TCL_ASSIST_CMD_RESERVED_5A_OFFSET 0x00000014 -#define TCL_ASSIST_CMD_RESERVED_5A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_5A_MSB 15 -#define TCL_ASSIST_CMD_RESERVED_5A_MASK 0x0000ffff - -#define TCL_ASSIST_CMD_L3_TYPE_OFFSET 0x00000014 -#define TCL_ASSIST_CMD_L3_TYPE_LSB 16 -#define TCL_ASSIST_CMD_L3_TYPE_MSB 31 -#define TCL_ASSIST_CMD_L3_TYPE_MASK 0xffff0000 - -#define TCL_ASSIST_CMD_L4_PROTOCOL_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PROTOCOL_LSB 0 -#define TCL_ASSIST_CMD_L4_PROTOCOL_MSB 7 -#define TCL_ASSIST_CMD_L4_PROTOCOL_MASK 0x000000ff - -#define TCL_ASSIST_CMD_L4_PORT_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PORT_LSB 8 -#define TCL_ASSIST_CMD_L4_PORT_MSB 23 -#define TCL_ASSIST_CMD_L4_PORT_MASK 0x00ffff00 - -#define TCL_ASSIST_CMD_L4_PORT_TYPE_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_LSB 24 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_MSB 24 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_MASK 0x01000000 - -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_LSB 25 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MSB 25 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MASK 0x02000000 - -#define TCL_ASSIST_CMD_DA_IS_BCAST_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_DA_IS_BCAST_LSB 26 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MSB 26 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MASK 0x04000000 - -#define TCL_ASSIST_CMD_RESERVED_6A_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_RESERVED_6A_LSB 27 -#define TCL_ASSIST_CMD_RESERVED_6A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_6A_MASK 0xf8000000 - -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_OFFSET 0x0000001c -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_OFFSET 0x00000020 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_OFFSET 0x00000024 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_OFFSET 0x00000028 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_DA_OR_SA_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_IP_DA_OR_SA_LSB 0 -#define TCL_ASSIST_CMD_IP_DA_OR_SA_MSB 0 -#define TCL_ASSIST_CMD_IP_DA_OR_SA_MASK 0x00000001 - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_LSB 1 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MSB 6 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MASK 0x0000007e - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_LSB 7 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MSB 7 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MASK 0x00000080 - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_LSB 8 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MSB 8 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MASK 0x00000100 - -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_LSB 9 -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MSB 9 -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MASK 0x00000200 - -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_LSB 10 -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MSB 10 -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MASK 0x00000400 - -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_LSB 11 -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MSB 11 -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MASK 0x00000800 - -#define TCL_ASSIST_CMD_MSDU_COLOR_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_MSDU_COLOR_LSB 12 -#define TCL_ASSIST_CMD_MSDU_COLOR_MSB 13 -#define TCL_ASSIST_CMD_MSDU_COLOR_MASK 0x00003000 - -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_LSB 14 -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MSB 16 -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MASK 0x0001c000 - -#define TCL_ASSIST_CMD_TQM_NO_DROP_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TQM_NO_DROP_LSB 17 -#define TCL_ASSIST_CMD_TQM_NO_DROP_MSB 17 -#define TCL_ASSIST_CMD_TQM_NO_DROP_MASK 0x00020000 - -#define TCL_ASSIST_CMD_RESERVED_11A_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_RESERVED_11A_LSB 18 -#define TCL_ASSIST_CMD_RESERVED_11A_MSB 29 -#define TCL_ASSIST_CMD_RESERVED_11A_MASK 0x3ffc0000 - -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_LSB 30 -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MSB 30 -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MASK 0x40000000 - -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_LSB 31 -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MSB 31 -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MASK 0x80000000 - -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_LSB 0 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MSB 18 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MASK 0x0007ffff - -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_LSB 19 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MSB 19 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x00080000 - -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_LSB 20 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MSB 20 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MASK 0x00100000 - -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_LSB 21 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MSB 21 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MASK 0x00200000 - -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_LSB 22 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MSB 28 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MASK 0x1fc00000 - -#define TCL_ASSIST_CMD_RESERVED_12A_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_RESERVED_12A_LSB 29 -#define TCL_ASSIST_CMD_RESERVED_12A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_12A_MASK 0xe0000000 - -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_OFFSET 0x00000034 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_LSB 0 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MSB 31 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MASK 0xffffffff - -#define TCL_ASSIST_CMD_RESERVED_14A_OFFSET 0x00000038 -#define TCL_ASSIST_CMD_RESERVED_14A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_14A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_14A_MASK 0xffffffff - -#define TCL_ASSIST_CMD_RESERVED_15A_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_RESERVED_15A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_15A_MSB 19 -#define TCL_ASSIST_CMD_RESERVED_15A_MASK 0x000fffff - -#define TCL_ASSIST_CMD_RING_ID_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_RING_ID_LSB 20 -#define TCL_ASSIST_CMD_RING_ID_MSB 27 -#define TCL_ASSIST_CMD_RING_ID_MASK 0x0ff00000 - -#define TCL_ASSIST_CMD_LOOPING_COUNT_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_LOOPING_COUNT_LSB 28 -#define TCL_ASSIST_CMD_LOOPING_COUNT_MSB 31 -#define TCL_ASSIST_CMD_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tcl_status_ring.h b/drivers/staging/fw-api/hw/fig/v1/tcl_status_ring.h deleted file mode 100644 index 5a24217c95d5..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tcl_status_ring.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TCL_STATUS_RING_H_ -#define _TCL_STATUS_RING_H_ - -#define NUM_OF_DWORDS_TCL_STATUS_RING 8 - -struct tcl_status_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t gse_ctrl : 4, - ase_fse_sel : 1, - cache_op_res : 2, - index_search_en : 1, - msdu_cnt_n : 24; - uint32_t msdu_byte_cnt_n : 32; - uint32_t msdu_timestmp_n : 32; - uint32_t cmd_meta_data_31_0 : 32; - uint32_t cmd_meta_data_63_32 : 32; - uint32_t hash_indx_val : 20, - cache_set_num : 4, - reserved_5a : 8; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 20, - ring_id : 8, - looping_count : 4; -#else - uint32_t msdu_cnt_n : 24, - index_search_en : 1, - cache_op_res : 2, - ase_fse_sel : 1, - gse_ctrl : 4; - uint32_t msdu_byte_cnt_n : 32; - uint32_t msdu_timestmp_n : 32; - uint32_t cmd_meta_data_31_0 : 32; - uint32_t cmd_meta_data_63_32 : 32; - uint32_t reserved_5a : 8, - cache_set_num : 4, - hash_indx_val : 20; - uint32_t reserved_6a : 32; - uint32_t looping_count : 4, - ring_id : 8, - reserved_7a : 20; -#endif -}; - -#define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 -#define TCL_STATUS_RING_GSE_CTRL_LSB 0 -#define TCL_STATUS_RING_GSE_CTRL_MSB 3 -#define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f - -#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 -#define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 -#define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 -#define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 - -#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 -#define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 -#define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 -#define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 - -#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 - -#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 -#define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 -#define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 -#define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 - -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff - -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff - -#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c -#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 -#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 -#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff - -#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff - -#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 -#define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 -#define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 -#define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff - -#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 -#define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 -#define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 -#define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 - -#define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 -#define TCL_STATUS_RING_RESERVED_5A_LSB 24 -#define TCL_STATUS_RING_RESERVED_5A_MSB 31 -#define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 - -#define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 -#define TCL_STATUS_RING_RESERVED_6A_LSB 0 -#define TCL_STATUS_RING_RESERVED_6A_MSB 31 -#define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff - -#define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c -#define TCL_STATUS_RING_RESERVED_7A_LSB 0 -#define TCL_STATUS_RING_RESERVED_7A_MSB 19 -#define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff - -#define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c -#define TCL_STATUS_RING_RING_ID_LSB 20 -#define TCL_STATUS_RING_RING_ID_MSB 27 -#define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 - -#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 -#define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 -#define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tlv_hdr.h b/drivers/staging/fw-api/hw/fig/v1/tlv_hdr.h deleted file mode 100644 index a2defe7be508..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tlv_hdr.h +++ /dev/null @@ -1,634 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TLV_HDR_H_ -#define _TLV_HDR_H_ - -#define _TLV_USERID_WIDTH_ 6 - -#define _TLV_MRV_EN_LEN_WIDTH_ 9 -#define _TLV_MRV_DIS_LEN_WIDTH_ 12 - -#define _TLV_DATA_WIDTH_ 32 -#define _TLV_64_DATA_WIDTH_ 64 -#define _TLV_CDATA_WIDTH_ 32 -#define _TLV_77_DATA_WIDTH_ 77 -#define _TLV_CDATA_77_WIDTH_ 64 - -#define _TLV_TAG_WIDTH_ 10 -#define _TLV_CTAG_WIDTH_ 6 - -struct tlv_mlo_usr_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mlo_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_32_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_32_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : 6; -#else - uint32_t tlv_reserved : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_64_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_64_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_c_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata_lower_52 : 52; - uint64_t tlv_cdata_upper_12 : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - tlv_cdata_upper_12 : 12; - uint64_t tlv_cdata_lower_52 : 52, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_; -#endif -}; - -struct tlv_mlo_usr_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mlo_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_reserved : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mac_usr_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mac_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_reserved : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_usr_c_77_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata_lower_20 : 20; - uint32_t tlv_cdata_middle_32 : 32; - uint32_t tlv_cdata_upper_12 : 12, - tlv_compression : 1, - pad_77to96_bit : 19; - uint32_t pad_96to128_bit : 32; -#else - uint32_t tlv_cdata_lower_20 : 20, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_; - uint32_t tlv_cdata_middle_32 : 32; - uint32_t pad_77to96_bit : 20, - tlv_compression : 1, - tlv_cdata_upper_12 : 12; - uint32_t pad_96to128_bit : 32; -#endif -}; - -struct tlv_usr_32_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_reserved : 32; -#else - uint64_t tlv_reserved : 32, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_32_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : 6, - pad_32to64_bit : 32; -#else - uint64_t pad_32to64_bit : 32, - tlv_reserved : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_77_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint32_t pad_64to75_bit : 12, - tlv_compression : 1, - pad_77to95_bit : 19; -#else - uint32_t pad_77to95_bit : 19, - tlv_compression : 1, - pad_64to75_bit : 12; - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_77_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint32_t pad_64to75_bit : 12, - tlv_compression : 1, - pad_77to96_bit : 19; -#else - uint32_t pad_77to96_bit : 19, - tlv_compression : 1, - pad_64to75_bit : 12; - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_c_44_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata : _TLV_CDATA_WIDTH_, - pad_44to64_bit : 20; -#else - uint64_t tlv_cdata_lower_20 : 20, - pad_44to64_bit : 20, - tlv_cdata_upper_12 : 12; - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_, -#endif -}; - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tlv_tag_def.h b/drivers/staging/fw-api/hw/fig/v1/tlv_tag_def.h deleted file mode 100644 index 8189c6ec5601..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tlv_tag_def.h +++ /dev/null @@ -1,1976 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TLV_TAG_DEF_ -#define _TLV_TAG_DEF_ - -typedef enum tlv_tag_def { - WIFIMACTX_CBF_START_E = 0 , - WIFIPHYRX_DATA_E = 1 , - WIFIPHYRX_CBF_DATA_RESP_E = 2 , - WIFIPHYRX_ABORT_REQUEST_E = 3 , - WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 , - WIFIMACTX_DATA_RESP_E = 5 , - WIFIMACTX_CBF_DATA_E = 6 , - WIFIMACTX_CBF_DONE_E = 7 , - WIFIPHYRX_LMR_DATA_RESP_E = 8 , - WIFIRXPCU_TO_UCODE_START_E = 9 , - WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 , - WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 , - WIFIRXPCU_TO_UCODE_FCS_STATUS_E = 12 , - WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 , - WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 , - WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 , - WIFIRXPCU_TO_UCODE_END_E = 16 , - WIFIPHYRX_RSSI_LEGACY_20MHZ_E = 17 , - WIFIPHYRX_NC_ABORT_REQUEST_E = 18 , - WIFIPHYRX_PKT_END_20MHZ_E = 19 , - WIFIPHYRX_NC_DATA_E = 20 , - WIFIMACRX_CBF_READ_REQUEST_E = 64 , - WIFIMACRX_CBF_DATA_REQUEST_E = 65 , - WIFIMACRX_EXPECT_NDP_RECEPTION_E = 66 , - WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 67 , - WIFIMACRX_NDP_TIMEOUT_E = 68 , - WIFIMACRX_ABORT_ACK_E = 69 , - WIFIMACRX_REQ_IMPLICIT_FB_E = 70 , - WIFIMACRX_CHAIN_MASK_E = 71 , - WIFIMACRX_NAP_USER_E = 72 , - WIFIMACRX_ABORT_REQUEST_E = 73 , - WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 74 , - WIFIPHYTX_ABORT_ACK_E = 75 , - WIFIPHYTX_ABORT_REQUEST_E = 76 , - WIFIPHYTX_PKT_END_E = 77 , - WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 78 , - WIFIPHYTX_REQUEST_CTRL_INFO_E = 79 , - WIFIPHYTX_DATA_REQUEST_E = 80 , - WIFIPHYTX_BF_CV_LOADING_DONE_E = 81 , - WIFIPHYTX_NAP_ACK_E = 82 , - WIFIPHYTX_NAP_DONE_E = 83 , - WIFIPHYTX_OFF_ACK_E = 84 , - WIFIPHYTX_ON_ACK_E = 85 , - WIFIPHYTX_SYNTH_OFF_ACK_E = 86 , - WIFIPHYTX_DEBUG16_E = 87 , - WIFIMACTX_ABORT_REQUEST_E = 88 , - WIFIMACTX_ABORT_ACK_E = 89 , - WIFIMACTX_PKT_END_E = 90 , - WIFIMACTX_PRE_PHY_DESC_E = 91 , - WIFIMACTX_BF_PARAMS_COMMON_E = 92 , - WIFIMACTX_BF_PARAMS_PER_USER_E = 93 , - WIFIMACTX_PREFETCH_CV_E = 94 , - WIFIMACTX_USER_DESC_COMMON_E = 95 , - WIFIMACTX_USER_DESC_PER_USER_E = 96 , - WIFIEXAMPLE_USER_TLV_16_E = 97 , - WIFIEXAMPLE_TLV_16_E = 98 , - WIFIMACTX_PHY_OFF_E = 99 , - WIFIMACTX_PHY_ON_E = 100 , - WIFIMACTX_SYNTH_OFF_E = 101 , - WIFIMACTX_EXPECT_CBF_COMMON_E = 102 , - WIFIMACTX_EXPECT_CBF_PER_USER_E = 103 , - WIFIMACTX_PHY_DESC_E = 104 , - WIFIMACTX_L_SIG_A_E = 105 , - WIFIMACTX_L_SIG_B_E = 106 , - WIFIMACTX_HT_SIG_E = 107 , - WIFIMACTX_VHT_SIG_A_E = 108 , - WIFIMACTX_VHT_SIG_B_SU20_E = 109 , - WIFIMACTX_VHT_SIG_B_SU40_E = 110 , - WIFIMACTX_VHT_SIG_B_SU80_E = 111 , - WIFIMACTX_VHT_SIG_B_SU160_E = 112 , - WIFIMACTX_VHT_SIG_B_MU20_E = 113 , - WIFIMACTX_VHT_SIG_B_MU40_E = 114 , - WIFIMACTX_VHT_SIG_B_MU80_E = 115 , - WIFIMACTX_VHT_SIG_B_MU160_E = 116 , - WIFIMACTX_SERVICE_E = 117 , - WIFIMACTX_HE_SIG_A_SU_E = 118 , - WIFIMACTX_HE_SIG_A_MU_DL_E = 119 , - WIFIMACTX_HE_SIG_A_MU_UL_E = 120 , - WIFIMACTX_HE_SIG_B1_MU_E = 121 , - WIFIMACTX_HE_SIG_B2_MU_E = 122 , - WIFIMACTX_HE_SIG_B2_OFDMA_E = 123 , - WIFIMACTX_DELETE_CV_E = 124 , - WIFIMACTX_MU_UPLINK_COMMON_E = 125 , - WIFIMACTX_MU_UPLINK_USER_SETUP_E = 126 , - WIFIMACTX_OTHER_TRANSMIT_INFO_E = 127 , - WIFIMACTX_PHY_NAP_E = 128 , - WIFIMACTX_DEBUG_E = 129 , - WIFIPHYRX_ABORT_ACK_E = 130 , - WIFIPHYRX_GENERATED_CBF_DETAILS_E = 131 , - WIFIPHYRX_RSSI_LEGACY_E = 132 , - WIFIPHYRX_RSSI_HT_E = 133 , - WIFIPHYRX_USER_INFO_E = 134 , - WIFIPHYRX_PKT_END_E = 135 , - WIFIPHYRX_DEBUG_E = 136 , - WIFIPHYRX_CBF_TRANSFER_DONE_E = 137 , - WIFIPHYRX_CBF_TRANSFER_ABORT_E = 138 , - WIFIPHYRX_L_SIG_A_E = 139 , - WIFIPHYRX_L_SIG_B_E = 140 , - WIFIPHYRX_HT_SIG_E = 141 , - WIFIPHYRX_VHT_SIG_A_E = 142 , - WIFIPHYRX_VHT_SIG_B_SU20_E = 143 , - WIFIPHYRX_VHT_SIG_B_SU40_E = 144 , - WIFIPHYRX_VHT_SIG_B_SU80_E = 145 , - WIFIPHYRX_VHT_SIG_B_SU160_E = 146 , - WIFIPHYRX_VHT_SIG_B_MU20_E = 147 , - WIFIPHYRX_VHT_SIG_B_MU40_E = 148 , - WIFIPHYRX_VHT_SIG_B_MU80_E = 149 , - WIFIPHYRX_VHT_SIG_B_MU160_E = 150 , - WIFIPHYRX_HE_SIG_A_SU_E = 151 , - WIFIPHYRX_HE_SIG_A_MU_DL_E = 152 , - WIFIPHYRX_HE_SIG_A_MU_UL_E = 153 , - WIFIPHYRX_HE_SIG_B1_MU_E = 154 , - WIFIPHYRX_HE_SIG_B2_MU_E = 155 , - WIFIPHYRX_HE_SIG_B2_OFDMA_E = 156 , - WIFIPHYRX_OTHER_RECEIVE_INFO_E = 157 , - WIFIPHYRX_COMMON_USER_INFO_E = 158 , - WIFIPHYRX_DATA_DONE_E = 159 , - WIFICOEX_TX_REQ_E = 160 , - WIFIDUMMY_E = 161 , - WIFIEXAMPLE_TLV_32_NAME_E = 162 , - WIFIMPDU_LIMIT_E = 163 , - WIFINA_LENGTH_END_E = 164 , - WIFIOLE_BUF_STATUS_E = 165 , - WIFIPCU_PPDU_SETUP_DONE_E = 166 , - WIFIPCU_PPDU_SETUP_END_E = 167 , - WIFIPCU_PPDU_SETUP_INIT_E = 168 , - WIFIPCU_PPDU_SETUP_START_E = 169 , - WIFIPDG_FES_SETUP_E = 170 , - WIFIPDG_RESPONSE_E = 171 , - WIFIPDG_TX_REQ_E = 172 , - WIFISCH_WAIT_INSTR_E = 173 , - WIFIMACTX_SWITCH_TO_MAIN_E = 174 , - WIFIPHYTX_LINK_STATE_E = 175 , - WIFIAUX_PPDU_END_E = 176 , - WIFITQM_GEN_MPDU_LENGTH_LIST_E = 177 , - WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 178 , - WIFITQM_GEN_MPDUS_E = 179 , - WIFITQM_GEN_MPDUS_STATUS_E = 180 , - WIFITQM_REMOVE_MPDU_E = 181 , - WIFITQM_REMOVE_MPDU_STATUS_E = 182 , - WIFITQM_REMOVE_MSDU_E = 183 , - WIFITQM_REMOVE_MSDU_STATUS_E = 184 , - WIFITQM_UPDATE_TX_MPDU_COUNT_E = 185 , - WIFITQM_WRITE_CMD_E = 186 , - WIFIOFDMA_TRIGGER_DETAILS_E = 187 , - WIFITX_DATA_E = 188 , - WIFITX_FES_SETUP_E = 189 , - WIFIRX_PACKET_E = 190 , - WIFIEXPECTED_RESPONSE_E = 191 , - WIFITX_MPDU_END_E = 192 , - WIFITX_MPDU_START_E = 193 , - WIFITX_MSDU_END_E = 194 , - WIFITX_MSDU_START_E = 195 , - WIFITX_SW_MODE_SETUP_E = 196 , - WIFITXPCU_BUFFER_STATUS_E = 197 , - WIFITXPCU_USER_BUFFER_STATUS_E = 198 , - WIFIDATA_TO_TIME_CONFIG_E = 199 , - WIFIEXAMPLE_USER_TLV_32_E = 200 , - WIFIMPDU_INFO_E = 201 , - WIFIPDG_USER_SETUP_E = 202 , - WIFITX_11AH_SETUP_E = 203 , - WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 204 , - WIFITX_PEER_ENTRY_E = 205 , - WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 206 , - WIFIEXAMPLE_USER_TLV_44_E = 207 , - WIFITX_FLUSH_E = 208 , - WIFITX_FLUSH_REQ_E = 209 , - WIFITQM_WRITE_CMD_STATUS_E = 210 , - WIFITQM_GET_MPDU_QUEUE_STATS_E = 211 , - WIFITQM_GET_MSDU_FLOW_STATS_E = 212 , - WIFIEXAMPLE_USER_CTLV_44_E = 213 , - WIFITX_FES_STATUS_START_E = 214 , - WIFITX_FES_STATUS_USER_PPDU_E = 215 , - WIFITX_FES_STATUS_USER_RESPONSE_E = 216 , - WIFITX_FES_STATUS_END_E = 217 , - WIFIRX_TRIG_INFO_E = 218 , - WIFIRXPCU_TX_SETUP_CLEAR_E = 219 , - WIFIRX_FRAME_BITMAP_REQ_E = 220 , - WIFIRX_FRAME_BITMAP_ACK_E = 221 , - WIFICOEX_RX_STATUS_E = 222 , - WIFIRX_START_PARAM_E = 223 , - WIFIRX_PPDU_START_E = 224 , - WIFIRX_PPDU_END_E = 225 , - WIFIRX_MPDU_START_E = 226 , - WIFIRX_MPDU_END_E = 227 , - WIFIRX_MSDU_START_E = 228 , - WIFIRX_MSDU_END_E = 229 , - WIFIRX_ATTENTION_E = 230 , - WIFIRECEIVED_RESPONSE_INFO_E = 231 , - WIFIRX_PHY_SLEEP_E = 232 , - WIFIRX_HEADER_E = 233 , - WIFIRX_PEER_ENTRY_E = 234 , - WIFIRX_FLUSH_E = 235 , - WIFIRX_RESPONSE_REQUIRED_INFO_E = 236 , - WIFIRX_FRAMELESS_BAR_DETAILS_E = 237 , - WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 238 , - WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 239 , - WIFITX_CBF_INFO_E = 240 , - WIFIPCU_PPDU_SETUP_USER_E = 241 , - WIFIRX_MPDU_PCU_START_E = 242 , - WIFIRX_PM_INFO_E = 243 , - WIFIRX_USER_PPDU_END_E = 244 , - WIFIRX_PRE_PPDU_START_E = 245 , - WIFIRX_PREAMBLE_E = 246 , - WIFITX_FES_SETUP_COMPLETE_E = 247 , - WIFITX_LAST_MPDU_FETCHED_E = 248 , - WIFITXDMA_STOP_REQUEST_E = 249 , - WIFIRXPCU_SETUP_E = 250 , - WIFIRXPCU_USER_SETUP_E = 251 , - WIFITX_FES_STATUS_ACK_OR_BA_E = 252 , - WIFITQM_ACKED_MPDU_E = 253 , - WIFICOEX_TX_RESP_E = 254 , - WIFICOEX_TX_STATUS_E = 255 , - WIFIMACTX_COEX_PHY_CTRL_E = 256 , - WIFICOEX_STATUS_BROADCAST_E = 257 , - WIFIRESPONSE_START_STATUS_E = 258 , - WIFIRESPONSE_END_STATUS_E = 259 , - WIFICRYPTO_STATUS_E = 260 , - WIFIRECEIVED_TRIGGER_INFO_E = 261 , - WIFICOEX_TX_STOP_CTRL_E = 262 , - WIFIRX_PPDU_ACK_REPORT_E = 263 , - WIFIRX_PPDU_NO_ACK_REPORT_E = 264 , - WIFISCH_COEX_STATUS_E = 265 , - WIFISCHEDULER_COMMAND_STATUS_E = 266 , - WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 267 , - WIFITX_FES_STATUS_PROT_E = 268 , - WIFITX_FES_STATUS_START_PPDU_E = 269 , - WIFITX_FES_STATUS_START_PROT_E = 270 , - WIFITXPCU_PHYTX_DEBUG32_E = 271 , - WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 272 , - WIFITX_MPDU_COUNT_TRANSFER_END_E = 273 , - WIFIWHO_ANCHOR_OFFSET_E = 274 , - WIFIWHO_ANCHOR_VALUE_E = 275 , - WIFIWHO_CCE_INFO_E = 276 , - WIFIWHO_COMMIT_E = 277 , - WIFIWHO_COMMIT_DONE_E = 278 , - WIFIWHO_FLUSH_E = 279 , - WIFIWHO_L2_LLC_E = 280 , - WIFIWHO_L2_PAYLOAD_E = 281 , - WIFIWHO_L3_CHECKSUM_E = 282 , - WIFIWHO_L3_INFO_E = 283 , - WIFIWHO_L4_CHECKSUM_E = 284 , - WIFIWHO_L4_INFO_E = 285 , - WIFIWHO_MSDU_E = 286 , - WIFIWHO_MSDU_MISC_E = 287 , - WIFIWHO_PACKET_DATA_E = 288 , - WIFIWHO_PACKET_HDR_E = 289 , - WIFIWHO_PPDU_END_E = 290 , - WIFIWHO_PPDU_START_E = 291 , - WIFIWHO_TSO_E = 292 , - WIFIWHO_WMAC_HEADER_PV0_E = 293 , - WIFIWHO_WMAC_HEADER_PV1_E = 294 , - WIFIWHO_WMAC_IV_E = 295 , - WIFIMPDU_INFO_END_E = 296 , - WIFIMPDU_INFO_BITMAP_E = 297 , - WIFITX_QUEUE_EXTENSION_E = 298 , - WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 299 , - WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 300 , - WIFITQM_ACKED_MPDU_STATUS_E = 301 , - WIFITQM_ADD_MSDU_STATUS_E = 302 , - WIFITQM_LIST_GEN_DONE_E = 303 , - WIFIWHO_TERMINATE_E = 304 , - WIFITX_LAST_MPDU_END_E = 305 , - WIFITX_CV_DATA_E = 306 , - WIFIPPDU_TX_END_E = 307 , - WIFIPROT_TX_END_E = 308 , - WIFIMPDU_INFO_GLOBAL_END_E = 309 , - WIFITQM_SCH_INSTR_GLOBAL_END_E = 310 , - WIFIRX_PPDU_END_USER_STATS_E = 311 , - WIFIRX_PPDU_END_USER_STATS_EXT_E = 312 , - WIFIREO_GET_QUEUE_STATS_E = 313 , - WIFIREO_FLUSH_QUEUE_E = 314 , - WIFIREO_FLUSH_CACHE_E = 315 , - WIFIREO_UNBLOCK_CACHE_E = 316 , - WIFIREO_GET_QUEUE_STATS_STATUS_E = 317 , - WIFIREO_FLUSH_QUEUE_STATUS_E = 318 , - WIFIREO_FLUSH_CACHE_STATUS_E = 319 , - WIFIREO_UNBLOCK_CACHE_STATUS_E = 320 , - WIFITQM_FLUSH_CACHE_E = 321 , - WIFITQM_UNBLOCK_CACHE_E = 322 , - WIFITQM_FLUSH_CACHE_STATUS_E = 323 , - WIFITQM_UNBLOCK_CACHE_STATUS_E = 324 , - WIFIRX_PPDU_END_STATUS_DONE_E = 325 , - WIFIRX_STATUS_BUFFER_DONE_E = 326 , - WIFISCHEDULER_MLO_SW_MSG_STATUS_E = 327 , - WIFISCHEDULER_TXOP_DURATION_TRIGGER_E = 328 , - WIFITX_DATA_SYNC_E = 329 , - WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 330 , - WIFITQM_GET_MPDU_HEAD_INFO_E = 331 , - WIFITQM_SYNC_CMD_E = 332 , - WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 333 , - WIFITQM_SYNC_CMD_STATUS_E = 334 , - WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 335 , - WIFITCC_TQM_WRAPPER_CMD_E = 336 , - WIFIREO_FLUSH_TIMEOUT_LIST_E = 337 , - WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 338 , - WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 339 , - WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 340 , - WIFIEXAMPLE_USER_TLV_32_NAME_E = 341 , - WIFIRX_PPDU_START_USER_INFO_E = 342 , - WIFIRX_RING_MASK_E = 343 , - WIFICOEX_MAC_NAP_E = 344 , - WIFIRXPCU_PPDU_END_INFO_E = 345 , - WIFIWHO_MESH_CONTROL_E = 346 , - WIFIPDG_SW_MODE_BW_START_E = 347 , - WIFIPDG_SW_MODE_BW_END_E = 348 , - WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 349 , - WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 350 , - WIFISCHEDULER_END_E = 351 , - WIFIRX_PPDU_START_DROPPED_E = 352 , - WIFIRX_PPDU_END_DROPPED_E = 353 , - WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 354 , - WIFIRX_MPDU_START_DROPPED_E = 355 , - WIFIRX_MSDU_START_DROPPED_E = 356 , - WIFIRX_MSDU_END_DROPPED_E = 357 , - WIFIRX_MPDU_END_DROPPED_E = 358 , - WIFIRX_ATTENTION_DROPPED_E = 359 , - WIFITXPCU_USER_SETUP_E = 360 , - WIFIRXPCU_USER_SETUP_EXT_E = 361 , - WIFICMD_PART_0_END_E = 362 , - WIFIMACTX_SYNTH_ON_E = 363 , - WIFISCH_CRITICAL_TLV_REFERENCE_E = 364 , - WIFITQM_MPDU_GLOBAL_START_E = 365 , - WIFIEXAMPLE_TLV_32_E = 366 , - WIFITQM_UPDATE_TX_MSDU_FLOW_E = 367 , - WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 368 , - WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 369 , - WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 370 , - WIFIREO_UPDATE_RX_REO_QUEUE_E = 371 , - WIFITQM_2_SCH_MPDU_AVAILABLE_E = 372 , - WIFIPDG_TRIG_RESPONSE_E = 373 , - WIFITRIGGER_RESPONSE_TX_DONE_E = 374 , - WIFIABORT_FROM_PHYRX_DETAILS_E = 375 , - WIFISCH_TQM_CMD_WRAPPER_E = 376 , - WIFIMPDUS_AVAILABLE_E = 377 , - WIFIRECEIVED_RESPONSE_INFO_PART2_E = 378 , - WIFIPHYRX_TX_START_TIMING_E = 379 , - WIFITXPCU_PREAMBLE_DONE_E = 380 , - WIFINDP_PREAMBLE_DONE_E = 381 , - WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 382 , - WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 383 , - WIFIMACTX_CLEAR_PREV_TX_INFO_E = 384 , - WIFITX_PUNCTURE_SETUP_E = 385 , - WIFIR2R_STATUS_END_E = 386 , - WIFIMACTX_PREFETCH_CV_COMMON_E = 387 , - WIFIEND_OF_FLUSH_MARKER_E = 388 , - WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 389 , - WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 390 , - WIFIRECEIVED_RESPONSE_USER_7_0_E = 391 , - WIFIRECEIVED_RESPONSE_USER_15_8_E = 392 , - WIFIRECEIVED_RESPONSE_USER_23_16_E = 393 , - WIFIRECEIVED_RESPONSE_USER_31_24_E = 394 , - WIFIRECEIVED_RESPONSE_USER_36_32_E = 395 , - WIFITX_LOOPBACK_SETUP_E = 396 , - WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 397 , - WIFISCH_WAIT_INSTR_TX_PATH_E = 398 , - WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 399 , - WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 400 , - WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 401 , - WIFITX_WUR_DATA_E = 402 , - WIFIRX_PPDU_END_START_E = 403 , - WIFIRX_PPDU_END_MIDDLE_E = 404 , - WIFIRX_PPDU_END_LAST_E = 405 , - WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 406 , - WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 407 , - WIFISRP_INFO_E = 408 , - WIFIOBSS_SR_INFO_E = 409 , - WIFISCHEDULER_SW_MSG_STATUS_E = 410 , - WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 411 , - WIFIRXPCU_SETUP_COMPLETE_E = 412 , - WIFIMACTX_MCC_SWITCH_E = 413 , - WIFIMACTX_MCC_SWITCH_BACK_E = 414 , - WIFIPHYTX_MCC_SWITCH_ACK_E = 415 , - WIFIPHYTX_MCC_SWITCH_BACK_ACK_E = 416 , - WIFIPHYTX_EMLSR_PRE_SWITCH_ACK_E = 417 , - WIFILMR_TX_END_E = 418 , - WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 419 , - WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 420 , - WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 421 , - WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 422 , - WIFISCH_TLV_WRAPPER_E = 423 , - WIFISCHEDULER_STATUS_WRAPPER_E = 424 , - WIFIMPDU_INFO_6X_E = 425 , - WIFIMACTX___RESERVED_G_0013 = 426 , - WIFIMACTX_U_SIG_EHT_SU_MU_E = 427 , - WIFIMACTX_U_SIG_EHT_TB_E = 428 , - WIFICOEX_TLV_ACC_TLV_TAG0_CFG_E = 429 , - WIFICOEX_TLV_ACC_TLV_TAG1_CFG_E = 430 , - WIFICOEX_TLV_ACC_TLV_TAG2_CFG_E = 431 , - WIFIPHYRX_U_SIG_EHT_SU_MU_E = 432 , - WIFIPHYRX_U_SIG_EHT_TB_E = 433 , - WIFICOEX_TLV_ACC_TLV_TAG3_CFG_E = 434 , - WIFICOEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 435 , - WIFITX_PUNCTURE_6PATTERNS_SETUP_E = 436 , - WIFIMACRX_LMR_READ_REQUEST_E = 437 , - WIFIMACRX_LMR_DATA_REQUEST_E = 438 , - WIFIPHYRX_LMR_TRANSFER_DONE_E = 439 , - WIFIPHYRX_LMR_TRANSFER_ABORT_E = 440 , - WIFIPHYRX_LMR_READ_REQUEST_ACK_E = 441 , - WIFIMACRX_SECURE_LTF_SEQ_PTR_E = 442 , - WIFIPHYRX_USER_INFO_MU_UL_E = 443 , - WIFIMPDU_QUEUE_OVERVIEW_E = 444 , - WIFISCHEDULER_NAV_INFO_E = 445 , - WIFIMACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E = 446 , - WIFILMR_PEER_ENTRY_E = 447 , - WIFILMR_MPDU_START_E = 448 , - WIFILMR_DATA_E = 449 , - WIFILMR_MPDU_END_E = 450 , - WIFIREO_GET_QUEUE_1K_STATS_STATUS_E = 451 , - WIFIRX_FRAME_1K_BITMAP_ACK_E = 452 , - WIFITX_FES_STATUS_1K_BA_E = 453 , - WIFITQM_ACKED_1K_MPDU_E = 454 , - WIFIMACRX_INBSS_OBSS_IND_E = 455 , - WIFIPHYRX_LOCATION_E = 456 , - WIFIMLO_TX_NOTIFICATION_SU_E = 457 , - WIFIMLO_TX_NOTIFICATION_MU_E = 458 , - WIFIMLO_TX_REQ_SU_E = 459 , - WIFIMLO_TX_REQ_MU_E = 460 , - WIFIMLO_TX_RESP_E = 461 , - WIFIMLO_RX_NOTIFICATION_E = 462 , - WIFIMLO_BKOFF_TRUNC_REQ_E = 463 , - WIFIMLO_TBTT_NOTIFICATION_E = 464 , - WIFIMLO_MESSAGE_E = 465 , - WIFIMLO_TS_SYNC_MSG_E = 466 , - WIFIMLO_FES_SETUP_E = 467 , - WIFIMLO_PDG_FES_SETUP_SU_E = 468 , - WIFIMLO_PDG_FES_SETUP_MU_E = 469 , - WIFIMPDU_INFO_1K_BITMAP_E = 470 , - WIFIMON_BUFFER_ADDR_E = 471 , - WIFITX_FRAG_STATE_E = 472 , - WIFIMACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 473 , - WIFIMACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 474 , - WIFIMACTX_EHT_SIG_USR_OFDMA_E = 475 , - WIFIMACTX_U_SIG_UHR_SU_MU_E = 476 , - WIFIMACTX_U_SIG_UHR_TB_E = 477 , - WIFITX_MPDU_COMPRESSED_DETAILS_TLV_E = 478 , - WIFITX_MSDU_COMPRESSED_DETAILS_TLV_E = 479 , - WIFITX_MSDU_COMPONENT_DETAILS_TLV_E = 480 , - WIFIPHYRX_EHT_SIG_USR_OFDMA_E = 481 , - WIFISCHEDULER_IU_TEMPLATE_ID_E = 482 , - WIFIPHYRX_PKT_END_PART1_E = 483 , - WIFIMACTX_EXPECT_NDP_RECEPTION_E = 484 , - WIFIMACTX_SECURE_LTF_SEQ_PTR_E = 485 , - WIFITX_MPDU_LENGTH_AND_RESTRICTIONS_E = 486 , - WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E = 487 , - WIFIPHYRX___RESERVED_G_0014 = 488 , - WIFIPHYTX_LOCATION_E = 489 , - WIFIPHYTX___RESERVED_G_0014 = 490 , - WIFIMPDU_LENGTH_STRUCTS_START_E = 491 , - WIFIMACTX_EHT_SIG_USR_SU_E = 492 , - WIFIMACTX_EHT_SIG_USR_MU_MIMO_E = 493 , - WIFIPHYRX_EHT_SIG_USR_SU_E = 494 , - WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E = 495 , - WIFIPHYRX_GENERIC_U_SIG_E = 496 , - WIFIPHYRX_GENERIC_EHT_OR_UHR_SIG_E = 497 , - WIFIOVERWRITE_RESP_START_E = 498 , - WIFIOVERWRITE_RESP_PREAMBLE_INFO_E = 499 , - WIFIOVERWRITE_RESP_FRAME_INFO_E = 500 , - WIFIOVERWRITE_RESP_END_E = 501 , - WIFIRXPCU_EARLY_RX_INDICATION_E = 502 , - WIFIMON_DROP_E = 503 , - WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E = 504 , - WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 505 , - WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E = 506 , - WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 507 , - WIFIMACTX_PREFETCH_CV_DMA_E = 508 , - WIFIMACTX_PREFETCH_CV_PER_USER_E = 509 , - WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 510 , - WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E = 511 , - WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E = 512 , - WIFIRANGING_USER_DETAILS_E = 513 , - WIFIPHYTX_CV_CORR_STATUS_E = 514 , - WIFIPHYTX_CV_CORR_COMMON_E = 515 , - WIFIPHYTX_CV_CORR_USER_E = 516 , - WIFIMACTX_CV_CORR_COMMON_E = 517 , - WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E = 518 , - WIFIBW_PUNCTURE_EVAL_WRAPPER_E = 519 , - WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E = 520 , - WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E = 521 , - WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E = 522 , - WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 523 , - WIFIRX_PPDU_END_USER_STATS_EXT2_E = 524 , - WIFIFW2SW_MON_E = 525 , - WIFIWSI_DIRECT_MESSAGE_E = 526 , - WIFIMACTX_EMLSR_PRE_SWITCH_E = 527 , - WIFIMACTX_EMLSR_SWITCH_E = 528 , - WIFIMACTX_EMLSR_SWITCH_BACK_E = 529 , - WIFIPHYTX_EMLSR_SWITCH_ACK_E = 530 , - WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E = 531 , - WIFIEAD_COMMAND_E = 532 , - WIFIEAD_LEGACY_STATUS_CONTROL_E = 533 , - WIFIEAD_LEGACY_INTERRUPT_CONTROL_E = 534 , - WIFITPI_TX_INITIALIZATION_CONFIG_E = 535 , - WIFITPI_ENABLE_RESPONSE_TIMEOUT_E = 536 , - WIFITPI_LEGACY_STATUS_CONTROL_E = 537 , - WIFITPI_LEGACY_INTERRUPT_CONTROL_E = 538 , - WIFITPI_MPDU_START_E = 539 , - WIFITPI_MPDU_CONTINUATION_E = 540 , - WIFITPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E = 541 , - WIFITPI_SEND_TLV_TO_PHYTX_E = 542 , - WIFITPI_TX_START_TIME_ARRIVED_E = 543 , - WIFITPI_STATUS_E = 544 , - WIFITPI_ERROR_STATUS_E = 545 , - WIFITPI_TIMESTAMP_STATUS_E = 546 , - WIFIRPI_SEND_TLV_TO_PHYRX_E = 547 , - WIFIRPI_LEGACY_STATUS_CONTROL_E = 548 , - WIFIRPI_LEGACY_INTERRUPT_CONTROL_E = 549 , - WIFIRPI_STATUS_E = 550 , - WIFIRPI_ERROR_STATUS_E = 551 , - WIFIRPI_TIMESTAMP_STATUS_E = 552 , - WIFIRPI_RX_FRAME_UPDATE_STATUS_E = 553 , - WIFITCC_PUSH_TRANSMIT_COMMAND_E = 554 , - WIFITCC_TLV_FETCH_E = 555 , - WIFITCC_LEGACY_STATUS_CONTROL_E = 556 , - WIFITCC_LEGACY_INTERRUPT_CONTROL_E = 557 , - WIFITCC_STATUS_E = 558 , - WIFITCC_ERROR_STATUS_E = 559 , - WIFITCC_TIMESTAMP_STATUS_E = 560 , - WIFITCC_PRE_BACKOFF_CMD_AVAILABLE_E = 561 , - WIFITCC_SCHEDULER_CMD_E = 562 , - WIFITCC_BURST_CMD_AVAILABLE_E = 563 , - WIFIRPI_NON_DATA_CTLV_44_FROM_PHYRX_E = 564 , - WIFIEAD_RING_AIR_TIME_REFERENCE_E = 565 , - WIFIRPI_FETCH_INFO_FROM_EXT_MEM_E = 566 , - WIFIRPI_WRITE_INFO_TO_EXT_MEM_E = 567 , - WIFIRPI_INIT_CBF_DATA_RESP_ADDR_E = 568 , - WIFIRPI_INIT_LMR_DATA_RESP_ADDR_E = 569 , - WIFITPI_SEND_CBF_DATA_TO_PHYTX_E = 570 , - WIFITPI_SEND_CTLV_44_TO_PHYTX_E = 571 , - WIFITCC_FES_END_MESSAGE_E = 572 , - WIFITPI_TX_FRAME_UPDATE_STATUS_E = 573 , - WIFITPI_DISABLE_RESPONSE_TIMEOUT_E = 574 , - WIFIEAD_MPDU_DATA_FETCH_CONTINUATION_E = 575 , - WIFIEAD_MSDU_STATUS_START_E = 576 , - WIFIEAD_MSDU_STATUS_DETAILS_E = 577 , - WIFIMACTX_UHR_SIG_USR_SU_E = 578 , - WIFIMACTX_UHR_SIG_USR_MU_MIMO_E = 579 , - WIFIMACTX_UHR_SIG_USR_OFDMA_E = 580 , - WIFIMACTX_ELR_SIG_UHR_SU_E = 581 , - WIFICOEX_BLACKOUT_DETAILS_E = 582 , - WIFIPEER_BLACKOUT_DETAILS_E = 583 , - WIFIMACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E = 584 , - WIFIHDR_CTRL_PROT_PEER_ENTRY_E = 585 , - WIFIHDR_CTRL_PROT_MPDU_START_E = 586 , - WIFIHDR_CTRL_PROT_DATA_E = 587 , - WIFIHDR_CTRL_PROT_MPDU_END_E = 588 , - WIFIHDR_CTRL_PROT_MIC_STATUS_E = 589 , - WIFIHDR_CTRL_PROT_PEER_INFO_E = 590 , - WIFIHDR_CTRL_PROT_PEER_ENTRY_DONE_E = 591 , - WIFIMACTX_U_SIG_UHR_ELR_SU_E = 592 , - WIFIMACTX_U_SIG_UHR_COBF_E = 593 , - WIFIMACTX_UHR_SIG_USR_COBF_E = 594 , - WIFISPARE_REUSE_TAG_0_E = 595 , - WIFISPARE_REUSE_TAG_1_E = 596 , - WIFISPARE_REUSE_TAG_2_E = 597 , - WIFISPARE_REUSE_TAG_3_E = 598 , - WIFISPARE_REUSE_TAG_4_E = 599 , - WIFISPARE_REUSE_TAG_5_E = 600 , - WIFISPARE_REUSE_TAG_6_E = 601 , - WIFISPARE_REUSE_TAG_7_E = 602 , - WIFISPARE_REUSE_TAG_8_E = 603 , - WIFISPARE_REUSE_TAG_9_E = 604 , - WIFISPARE_REUSE_TAG_10_E = 605 , - WIFISPARE_REUSE_TAG_11_E = 606 , - WIFISPARE_REUSE_TAG_12_E = 607 , - WIFISPARE_REUSE_TAG_13_E = 608 , - WIFISPARE_REUSE_TAG_14_E = 609 , - WIFISPARE_REUSE_TAG_15_E = 610 , - WIFISPARE_REUSE_TAG_16_E = 611 , - WIFISPARE_REUSE_TAG_17_E = 612 , - WIFISPARE_REUSE_TAG_18_E = 613 , - WIFISPARE_REUSE_TAG_19_E = 614 , - WIFISPARE_REUSE_TAG_20_E = 615 , - WIFISPARE_REUSE_TAG_21_E = 616 , - WIFISPARE_REUSE_TAG_22_E = 617 , - WIFISPARE_REUSE_TAG_23_E = 618 , - WIFISPARE_REUSE_TAG_24_E = 619 , - WIFISPARE_REUSE_TAG_25_E = 620 , - WIFISPARE_REUSE_TAG_26_E = 621 , - WIFISPARE_REUSE_TAG_27_E = 622 , - WIFISPARE_REUSE_TAG_28_E = 623 , - WIFISPARE_REUSE_TAG_29_E = 624 , - WIFISPARE_REUSE_TAG_30_E = 625 , - WIFISPARE_REUSE_TAG_31_E = 626 , - WIFISPARE_REUSE_TAG_32_E = 627 , - WIFISPARE_REUSE_TAG_33_E = 628 , - WIFISPARE_REUSE_TAG_34_E = 629 , - WIFISPARE_REUSE_TAG_35_E = 630 , - WIFISPARE_REUSE_TAG_36_E = 631 , - WIFISPARE_REUSE_TAG_37_E = 632 , - WIFISPARE_REUSE_TAG_38_E = 633 , - WIFISPARE_REUSE_TAG_39_E = 634 , - WIFISPARE_REUSE_TAG_40_E = 635 , - WIFISPARE_REUSE_TAG_41_E = 636 , - WIFISPARE_REUSE_TAG_42_E = 637 , - WIFISPARE_REUSE_TAG_43_E = 638 , - WIFISPARE_REUSE_TAG_44_E = 639 , - WIFISPARE_REUSE_TAG_45_E = 640 , - WIFISPARE_REUSE_TAG_46_E = 641 , - WIFISPARE_REUSE_TAG_47_E = 642 , - WIFISPARE_REUSE_TAG_48_E = 643 , - WIFISPARE_REUSE_TAG_49_E = 644 , - WIFISPARE_REUSE_TAG_50_E = 645 , - WIFISPARE_REUSE_TAG_51_E = 646 , - WIFISPARE_REUSE_TAG_52_E = 647 , - WIFISPARE_REUSE_TAG_53_E = 648 , - WIFISPARE_REUSE_TAG_54_E = 649 , - WIFISPARE_REUSE_TAG_55_E = 650 , - WIFISPARE_REUSE_TAG_56_E = 651 , - WIFISPARE_REUSE_TAG_57_E = 652 , - WIFISPARE_REUSE_TAG_58_E = 653 , - WIFISPARE_REUSE_TAG_59_E = 654 , - WIFISPARE_REUSE_TAG_60_E = 655 , - WIFISPARE_REUSE_TAG_61_E = 656 , - WIFISPARE_REUSE_TAG_62_E = 657 , - WIFISPARE_REUSE_TAG_63_E = 658 , - WIFISPARE_REUSE_TAG_64_E = 659 , - WIFISPARE_REUSE_TAG_65_E = 660 , - WIFISPARE_REUSE_TAG_66_E = 661 , - WIFISPARE_REUSE_TAG_67_E = 662 , - WIFISPARE_REUSE_TAG_68_E = 663 , - WIFISPARE_REUSE_TAG_69_E = 664 , - WIFISPARE_REUSE_TAG_70_E = 665 , - WIFISPARE_REUSE_TAG_71_E = 666 , - WIFISPARE_REUSE_TAG_72_E = 667 , - WIFISPARE_REUSE_TAG_73_E = 668 , - WIFISPARE_REUSE_TAG_74_E = 669 , - WIFISPARE_REUSE_TAG_75_E = 670 , - WIFISPARE_REUSE_TAG_76_E = 671 , - WIFISPARE_REUSE_TAG_77_E = 672 , - WIFISPARE_REUSE_TAG_78_E = 673 , - WIFISPARE_REUSE_TAG_79_E = 674 , - WIFISPARE_REUSE_TAG_80_E = 675 , - WIFISPARE_REUSE_TAG_81_E = 676 , - WIFISPARE_REUSE_TAG_82_E = 677 , - WIFISPARE_REUSE_TAG_83_E = 678 , - WIFISPARE_REUSE_TAG_84_E = 679 , - WIFISPARE_REUSE_TAG_85_E = 680 , - WIFISPARE_REUSE_TAG_86_E = 681 , - WIFISPARE_REUSE_TAG_87_E = 682 , - WIFISPARE_REUSE_TAG_88_E = 683 , - WIFISPARE_REUSE_TAG_89_E = 684 , - WIFISPARE_REUSE_TAG_90_E = 685 , - WIFISPARE_REUSE_TAG_91_E = 686 , - WIFISPARE_REUSE_TAG_92_E = 687 , - WIFISPARE_REUSE_TAG_93_E = 688 , - WIFISPARE_REUSE_TAG_94_E = 689 , - WIFISPARE_REUSE_TAG_95_E = 690 , - WIFISPARE_REUSE_TAG_96_E = 691 , - WIFISPARE_REUSE_TAG_97_E = 692 , - WIFISPARE_REUSE_TAG_98_E = 693 , - WIFISPARE_REUSE_TAG_99_E = 694 , - WIFISPARE_REUSE_TAG_100_E = 695 , - WIFISPARE_REUSE_TAG_101_E = 696 , - WIFISPARE_REUSE_TAG_102_E = 697 , - WIFISPARE_REUSE_TAG_103_E = 698 , - WIFISPARE_REUSE_TAG_104_E = 699 , - WIFISPARE_REUSE_TAG_105_E = 700 , - WIFISPARE_REUSE_TAG_106_E = 701 , - WIFISPARE_REUSE_TAG_107_E = 702 , - WIFISPARE_REUSE_TAG_108_E = 703 , - WIFISPARE_REUSE_TAG_109_E = 704 , - WIFISPARE_REUSE_TAG_110_E = 705 , - WIFISPARE_REUSE_TAG_111_E = 706 , - WIFISPARE_REUSE_TAG_112_E = 707 , - WIFISPARE_REUSE_TAG_113_E = 708 , - WIFISPARE_REUSE_TAG_114_E = 709 , - WIFISPARE_REUSE_TAG_115_E = 710 , - WIFISPARE_REUSE_TAG_116_E = 711 , - WIFISPARE_REUSE_TAG_117_E = 712 , - WIFISPARE_REUSE_TAG_118_E = 713 , - WIFISPARE_REUSE_TAG_119_E = 714 , - WIFISPARE_REUSE_TAG_120_E = 715 , - WIFISPARE_REUSE_TAG_121_E = 716 , - WIFISPARE_REUSE_TAG_122_E = 717 , - WIFISPARE_REUSE_TAG_123_E = 718 , - WIFISPARE_REUSE_TAG_124_E = 719 , - WIFISPARE_REUSE_TAG_125_E = 720 , - WIFISPARE_REUSE_TAG_126_E = 721 , - WIFISPARE_REUSE_TAG_127_E = 722 , - WIFISPARE_REUSE_TAG_128_E = 723 , - WIFISPARE_REUSE_TAG_129_E = 724 , - WIFISPARE_REUSE_TAG_130_E = 725 , - WIFISPARE_REUSE_TAG_131_E = 726 , - WIFISPARE_REUSE_TAG_132_E = 727 , - WIFISPARE_REUSE_TAG_133_E = 728 , - WIFISPARE_REUSE_TAG_134_E = 729 , - WIFISPARE_REUSE_TAG_135_E = 730 , - WIFISPARE_REUSE_TAG_136_E = 731 , - WIFISPARE_REUSE_TAG_137_E = 732 , - WIFISPARE_REUSE_TAG_138_E = 733 , - WIFISPARE_REUSE_TAG_139_E = 734 , - WIFISPARE_REUSE_TAG_140_E = 735 , - WIFISPARE_REUSE_TAG_141_E = 736 , - WIFISPARE_REUSE_TAG_142_E = 737 , - WIFISPARE_REUSE_TAG_143_E = 738 , - WIFISPARE_REUSE_TAG_144_E = 739 , - WIFISPARE_REUSE_TAG_145_E = 740 , - WIFISPARE_REUSE_TAG_146_E = 741 , - WIFISPARE_REUSE_TAG_147_E = 742 , - WIFISPARE_REUSE_TAG_148_E = 743 , - WIFISPARE_REUSE_TAG_149_E = 744 , - WIFISPARE_REUSE_TAG_150_E = 745 , - WIFISPARE_REUSE_TAG_151_E = 746 , - WIFISPARE_REUSE_TAG_152_E = 747 , - WIFISPARE_REUSE_TAG_153_E = 748 , - WIFISPARE_REUSE_TAG_154_E = 749 , - WIFISPARE_REUSE_TAG_155_E = 750 , - WIFISPARE_REUSE_TAG_156_E = 751 , - WIFISPARE_REUSE_TAG_157_E = 752 , - WIFISPARE_REUSE_TAG_158_E = 753 , - WIFISPARE_REUSE_TAG_159_E = 754 , - WIFISPARE_REUSE_TAG_160_E = 755 , - WIFISPARE_REUSE_TAG_161_E = 756 , - WIFISPARE_REUSE_TAG_162_E = 757 , - WIFISPARE_REUSE_TAG_163_E = 758 , - WIFISPARE_REUSE_TAG_164_E = 759 , - WIFISPARE_REUSE_TAG_165_E = 760 , - WIFISPARE_REUSE_TAG_166_E = 761 , - WIFISPARE_REUSE_TAG_167_E = 762 , - WIFISPARE_REUSE_TAG_168_E = 763 , - WIFISPARE_REUSE_TAG_169_E = 764 , - WIFISPARE_REUSE_TAG_170_E = 765 , - WIFISPARE_REUSE_TAG_171_E = 766 , - WIFISPARE_REUSE_TAG_172_E = 767 , - WIFISPARE_REUSE_TAG_173_E = 768 , - WIFISPARE_REUSE_TAG_174_E = 769 , - WIFISPARE_REUSE_TAG_175_E = 770 , - WIFISPARE_REUSE_TAG_176_E = 771 , - WIFISPARE_REUSE_TAG_177_E = 772 , - WIFISPARE_REUSE_TAG_178_E = 773 , - WIFISPARE_REUSE_TAG_179_E = 774 , - WIFISPARE_REUSE_TAG_180_E = 775 , - WIFISPARE_REUSE_TAG_181_E = 776 , - WIFISPARE_REUSE_TAG_182_E = 777 , - WIFISPARE_REUSE_TAG_183_E = 778 , - WIFISPARE_REUSE_TAG_184_E = 779 , - WIFISPARE_REUSE_TAG_185_E = 780 , - WIFISPARE_REUSE_TAG_186_E = 781 , - WIFISPARE_REUSE_TAG_187_E = 782 , - WIFISPARE_REUSE_TAG_188_E = 783 , - WIFISPARE_REUSE_TAG_189_E = 784 , - WIFISPARE_REUSE_TAG_190_E = 785 , - WIFISPARE_REUSE_TAG_191_E = 786 , - WIFISPARE_REUSE_TAG_192_E = 787 , - WIFISPARE_REUSE_TAG_193_E = 788 , - WIFISPARE_REUSE_TAG_194_E = 789 , - WIFISPARE_REUSE_TAG_195_E = 790 , - WIFISPARE_REUSE_TAG_196_E = 791 , - WIFISPARE_REUSE_TAG_197_E = 792 , - WIFISPARE_REUSE_TAG_198_E = 793 , - WIFISPARE_REUSE_TAG_199_E = 794 , - WIFISPARE_REUSE_TAG_200_E = 795 , - WIFISPARE_REUSE_TAG_201_E = 796 , - WIFISPARE_REUSE_TAG_202_E = 797 , - WIFISPARE_REUSE_TAG_203_E = 798 , - WIFISPARE_REUSE_TAG_204_E = 799 , - WIFISPARE_REUSE_TAG_205_E = 800 , - WIFISPARE_REUSE_TAG_206_E = 801 , - WIFISPARE_REUSE_TAG_207_E = 802 , - WIFISPARE_REUSE_TAG_208_E = 803 , - WIFISPARE_REUSE_TAG_209_E = 804 , - WIFISPARE_REUSE_TAG_210_E = 805 , - WIFISPARE_REUSE_TAG_211_E = 806 , - WIFISPARE_REUSE_TAG_212_E = 807 , - WIFISPARE_REUSE_TAG_213_E = 808 , - WIFISPARE_REUSE_TAG_214_E = 809 , - WIFISPARE_REUSE_TAG_215_E = 810 , - WIFISPARE_REUSE_TAG_216_E = 811 , - WIFISPARE_REUSE_TAG_217_E = 812 , - WIFISPARE_REUSE_TAG_218_E = 813 , - WIFISPARE_REUSE_TAG_219_E = 814 , - WIFISPARE_REUSE_TAG_220_E = 815 , - WIFISPARE_REUSE_TAG_221_E = 816 , - WIFISPARE_REUSE_TAG_222_E = 817 , - WIFISPARE_REUSE_TAG_223_E = 818 , - WIFISPARE_REUSE_TAG_224_E = 819 , - WIFISPARE_REUSE_TAG_225_E = 820 , - WIFISPARE_REUSE_TAG_226_E = 821 , - WIFISPARE_REUSE_TAG_227_E = 822 , - WIFISPARE_REUSE_TAG_228_E = 823 , - WIFISPARE_REUSE_TAG_229_E = 824 , - WIFISPARE_REUSE_TAG_230_E = 825 , - WIFISPARE_REUSE_TAG_231_E = 826 , - WIFISPARE_REUSE_TAG_232_E = 827 , - WIFISPARE_REUSE_TAG_233_E = 828 , - WIFISPARE_REUSE_TAG_234_E = 829 , - WIFISPARE_REUSE_TAG_235_E = 830 , - WIFISPARE_REUSE_TAG_236_E = 831 , - WIFISPARE_REUSE_TAG_237_E = 832 , - WIFISPARE_REUSE_TAG_238_E = 833 , - WIFISPARE_REUSE_TAG_239_E = 834 , - WIFISPARE_REUSE_TAG_240_E = 835 , - WIFISPARE_REUSE_TAG_241_E = 836 , - WIFISPARE_REUSE_TAG_242_E = 837 , - WIFISPARE_REUSE_TAG_243_E = 838 , - WIFISPARE_REUSE_TAG_244_E = 839 , - WIFISPARE_REUSE_TAG_245_E = 840 , - WIFISPARE_REUSE_TAG_246_E = 841 , - WIFISPARE_REUSE_TAG_247_E = 842 , - WIFISPARE_REUSE_TAG_248_E = 843 , - WIFISPARE_REUSE_TAG_249_E = 844 , - WIFISPARE_REUSE_TAG_250_E = 845 , - WIFISPARE_REUSE_TAG_251_E = 846 , - WIFISPARE_REUSE_TAG_252_E = 847 , - WIFISPARE_REUSE_TAG_253_E = 848 , - WIFISPARE_REUSE_TAG_254_E = 849 , - WIFISPARE_REUSE_TAG_255_E = 850 , - WIFISPARE_REUSE_TAG_256_E = 851 , - WIFISPARE_REUSE_TAG_257_E = 852 , - WIFISPARE_REUSE_TAG_258_E = 853 , - WIFISPARE_REUSE_TAG_259_E = 854 , - WIFISPARE_REUSE_TAG_260_E = 855 , - WIFISPARE_REUSE_TAG_261_E = 856 , - WIFISPARE_REUSE_TAG_262_E = 857 , - WIFISPARE_REUSE_TAG_263_E = 858 , - WIFISPARE_REUSE_TAG_264_E = 859 , - WIFISPARE_REUSE_TAG_265_E = 860 , - WIFISPARE_REUSE_TAG_266_E = 861 , - WIFISPARE_REUSE_TAG_267_E = 862 , - WIFISPARE_REUSE_TAG_268_E = 863 , - WIFISPARE_REUSE_TAG_269_E = 864 , - WIFISPARE_REUSE_TAG_270_E = 865 , - WIFISPARE_REUSE_TAG_271_E = 866 , - WIFISPARE_REUSE_TAG_272_E = 867 , - WIFISPARE_REUSE_TAG_273_E = 868 , - WIFISPARE_REUSE_TAG_274_E = 869 , - WIFISPARE_REUSE_TAG_275_E = 870 , - WIFISPARE_REUSE_TAG_276_E = 871 , - WIFISPARE_REUSE_TAG_277_E = 872 , - WIFISPARE_REUSE_TAG_278_E = 873 , - WIFISPARE_REUSE_TAG_279_E = 874 , - WIFISPARE_REUSE_TAG_280_E = 875 , - WIFISPARE_REUSE_TAG_281_E = 876 , - WIFISPARE_REUSE_TAG_282_E = 877 , - WIFISPARE_REUSE_TAG_283_E = 878 , - WIFISPARE_REUSE_TAG_284_E = 879 , - WIFISPARE_REUSE_TAG_285_E = 880 , - WIFISPARE_REUSE_TAG_286_E = 881 , - WIFISPARE_REUSE_TAG_287_E = 882 , - WIFISPARE_REUSE_TAG_288_E = 883 , - WIFISPARE_REUSE_TAG_289_E = 884 , - WIFISPARE_REUSE_TAG_290_E = 885 , - WIFISPARE_REUSE_TAG_291_E = 886 , - WIFISPARE_REUSE_TAG_292_E = 887 , - WIFISPARE_REUSE_TAG_293_E = 888 , - WIFISPARE_REUSE_TAG_294_E = 889 , - WIFISPARE_REUSE_TAG_295_E = 890 , - WIFISPARE_REUSE_TAG_296_E = 891 , - WIFISPARE_REUSE_TAG_297_E = 892 , - WIFISPARE_REUSE_TAG_298_E = 893 , - WIFISPARE_REUSE_TAG_299_E = 894 , - WIFISPARE_REUSE_TAG_300_E = 895 , - WIFISPARE_REUSE_TAG_301_E = 896 , - WIFISPARE_REUSE_TAG_302_E = 897 , - WIFISPARE_REUSE_TAG_303_E = 898 , - WIFISPARE_REUSE_TAG_304_E = 899 , - WIFISPARE_REUSE_TAG_305_E = 900 , - WIFISPARE_REUSE_TAG_306_E = 901 , - WIFISPARE_REUSE_TAG_307_E = 902 , - WIFISPARE_REUSE_TAG_308_E = 903 , - WIFISPARE_REUSE_TAG_309_E = 904 , - WIFISPARE_REUSE_TAG_310_E = 905 , - WIFISPARE_REUSE_TAG_311_E = 906 , - WIFISPARE_REUSE_TAG_312_E = 907 , - WIFISPARE_REUSE_TAG_313_E = 908 , - WIFISPARE_REUSE_TAG_314_E = 909 , - WIFISPARE_REUSE_TAG_315_E = 910 , - WIFISPARE_REUSE_TAG_316_E = 911 , - WIFISPARE_REUSE_TAG_317_E = 912 , - WIFISPARE_REUSE_TAG_318_E = 913 , - WIFISPARE_REUSE_TAG_319_E = 914 , - WIFISPARE_REUSE_TAG_320_E = 915 , - WIFISPARE_REUSE_TAG_321_E = 916 , - WIFISPARE_REUSE_TAG_322_E = 917 , - WIFISPARE_REUSE_TAG_323_E = 918 , - WIFISPARE_REUSE_TAG_324_E = 919 , - WIFISPARE_REUSE_TAG_325_E = 920 , - WIFISPARE_REUSE_TAG_326_E = 921 , - WIFISPARE_REUSE_TAG_327_E = 922 , - WIFISPARE_REUSE_TAG_328_E = 923 , - WIFISPARE_REUSE_TAG_329_E = 924 , - WIFISPARE_REUSE_TAG_330_E = 925 , - WIFISPARE_REUSE_TAG_331_E = 926 , - WIFISPARE_REUSE_TAG_332_E = 927 , - WIFISPARE_REUSE_TAG_333_E = 928 , - WIFISPARE_REUSE_TAG_334_E = 929 , - WIFISPARE_REUSE_TAG_335_E = 930 , - WIFISPARE_REUSE_TAG_336_E = 931 , - WIFISPARE_REUSE_TAG_337_E = 932 , - WIFISPARE_REUSE_TAG_338_E = 933 , - WIFISPARE_REUSE_TAG_339_E = 934 , - WIFISPARE_REUSE_TAG_340_E = 935 , - WIFISPARE_REUSE_TAG_341_E = 936 , - WIFISPARE_REUSE_TAG_342_E = 937 , - WIFISPARE_REUSE_TAG_343_E = 938 , - WIFISPARE_REUSE_TAG_344_E = 939 , - WIFISPARE_REUSE_TAG_345_E = 940 , - WIFISPARE_REUSE_TAG_346_E = 941 , - WIFISPARE_REUSE_TAG_347_E = 942 , - WIFISPARE_REUSE_TAG_348_E = 943 , - WIFISPARE_REUSE_TAG_349_E = 944 , - WIFISPARE_REUSE_TAG_350_E = 945 , - WIFISPARE_REUSE_TAG_351_E = 946 , - WIFISPARE_REUSE_TAG_352_E = 947 , - WIFISPARE_REUSE_TAG_353_E = 948 , - WIFISPARE_REUSE_TAG_354_E = 949 , - WIFISPARE_REUSE_TAG_355_E = 950 , - WIFISPARE_REUSE_TAG_356_E = 951 , - WIFISPARE_REUSE_TAG_357_E = 952 , - WIFISPARE_REUSE_TAG_358_E = 953 , - WIFISPARE_REUSE_TAG_359_E = 954 , - WIFISPARE_REUSE_TAG_360_E = 955 , - WIFISPARE_REUSE_TAG_361_E = 956 , - WIFISPARE_REUSE_TAG_362_E = 957 , - WIFISPARE_REUSE_TAG_363_E = 958 , - WIFISPARE_REUSE_TAG_364_E = 959 , - WIFISPARE_REUSE_TAG_365_E = 960 , - WIFISPARE_REUSE_TAG_366_E = 961 , - WIFISPARE_REUSE_TAG_367_E = 962 , - WIFISPARE_REUSE_TAG_368_E = 963 , - WIFISPARE_REUSE_TAG_369_E = 964 , - WIFISPARE_REUSE_TAG_370_E = 965 , - WIFISPARE_REUSE_TAG_371_E = 966 , - WIFISPARE_REUSE_TAG_372_E = 967 , - WIFISPARE_REUSE_TAG_373_E = 968 , - WIFISPARE_REUSE_TAG_374_E = 969 , - WIFISPARE_REUSE_TAG_375_E = 970 , - WIFISPARE_REUSE_TAG_376_E = 971 , - WIFISPARE_REUSE_TAG_377_E = 972 , - WIFISPARE_REUSE_TAG_378_E = 973 , - WIFISPARE_REUSE_TAG_379_E = 974 , - WIFISPARE_REUSE_TAG_380_E = 975 , - WIFISPARE_REUSE_TAG_381_E = 976 , - WIFISPARE_REUSE_TAG_382_E = 977 , - WIFISPARE_REUSE_TAG_383_E = 978 , - WIFISPARE_REUSE_TAG_384_E = 979 , - WIFISPARE_REUSE_TAG_385_E = 980 , - WIFISPARE_REUSE_TAG_386_E = 981 , - WIFISPARE_REUSE_TAG_387_E = 982 , - WIFISPARE_REUSE_TAG_388_E = 983 , - WIFISPARE_REUSE_TAG_389_E = 984 , - WIFISPARE_REUSE_TAG_390_E = 985 , - WIFISPARE_REUSE_TAG_391_E = 986 , - WIFISPARE_REUSE_TAG_392_E = 987 , - WIFISPARE_REUSE_TAG_393_E = 988 , - WIFISPARE_REUSE_TAG_394_E = 989 , - WIFISPARE_REUSE_TAG_395_E = 990 , - WIFISPARE_REUSE_TAG_396_E = 991 , - WIFISPARE_REUSE_TAG_397_E = 992 , - WIFISPARE_REUSE_TAG_398_E = 993 , - WIFISPARE_REUSE_TAG_399_E = 994 , - WIFISPARE_REUSE_TAG_400_E = 995 , - WIFISPARE_REUSE_TAG_401_E = 996 , - WIFISPARE_REUSE_TAG_402_E = 997 , - WIFISPARE_REUSE_TAG_403_E = 998 , - WIFISPARE_REUSE_TAG_404_E = 999 , - WIFISPARE_REUSE_TAG_405_E = 1000 , - WIFISPARE_REUSE_TAG_406_E = 1001 , - WIFISPARE_REUSE_TAG_407_E = 1002 , - WIFISPARE_REUSE_TAG_408_E = 1003 , - WIFISPARE_REUSE_TAG_409_E = 1004 , - WIFISPARE_REUSE_TAG_410_E = 1005 , - WIFISPARE_REUSE_TAG_411_E = 1006 , - WIFISPARE_REUSE_TAG_412_E = 1007 , - WIFISPARE_REUSE_TAG_413_E = 1008 , - WIFISPARE_REUSE_TAG_414_E = 1009 , - WIFISPARE_REUSE_TAG_415_E = 1010 , - WIFISPARE_REUSE_TAG_416_E = 1011 , - WIFISPARE_REUSE_TAG_417_E = 1012 , - WIFISPARE_REUSE_TAG_418_E = 1013 , - WIFISPARE_REUSE_TAG_419_E = 1014 , - WIFISPARE_REUSE_TAG_420_E = 1015 , - WIFISPARE_REUSE_TAG_421_E = 1016 , - WIFISPARE_REUSE_TAG_422_E = 1017 , - WIFISPARE_REUSE_TAG_423_E = 1018 , - WIFISPARE_REUSE_TAG_424_E = 1019 , - WIFISPARE_REUSE_TAG_425_E = 1020 , - WIFISPARE_REUSE_TAG_426_E = 1021 -} tlv_tag_def__e; - -typedef enum { - WIFI_EXT_PHYRX_DATA_E = 1 , - WIFI_EXT_PHYRX_ABORT_REQUEST_E = 3 , - WIFI_EXT_MACTX_DATA_RESP_E = 5 , - WIFI_EXT_MACTX_CBF_DONE_E = 7 , - WIFI_EXT_RXPCU_TO_UCODE_START_E = 9 , - WIFI_EXT_RXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 , - WIFI_EXT_RXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 , - WIFI_EXT_RXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 , - WIFI_EXT_PHYRX_RSSI_LEGACY_20MHZ_E = 17 , - WIFI_EXT_PHYRX_PKT_END_20MHZ_E = 19 , - WIFI_EXT_MACRX_CBF_DATA_REQUEST_E = 65 , - WIFI_EXT_MACRX_FREEZE_CAPTURE_CHANNEL_E = 67 , - WIFI_EXT_MACRX_ABORT_ACK_E = 69 , - WIFI_EXT_MACRX_CHAIN_MASK_E = 71 , - WIFI_EXT_MACRX_ABORT_REQUEST_E = 73 , - WIFI_EXT_PHYTX_ABORT_ACK_E = 75 , - WIFI_EXT_PHYTX_PKT_END_E = 77 , - WIFI_EXT_PHYTX_REQUEST_CTRL_INFO_E = 79 , - WIFI_EXT_PHYTX_BF_CV_LOADING_DONE_E = 81 , - WIFI_EXT_PHYTX_NAP_DONE_E = 83 , - WIFI_EXT_PHYTX_ON_ACK_E = 85 , - WIFI_EXT_PHYTX_DEBUG16_E = 87 , - WIFI_EXT_MACTX_ABORT_ACK_E = 89 , - WIFI_EXT_MACTX_PRE_PHY_DESC_E = 91 , - WIFI_EXT_MACTX_BF_PARAMS_PER_USER_E = 93 , - WIFI_EXT_MACTX_USER_DESC_COMMON_E = 95 , - WIFI_EXT_EXAMPLE_USER_TLV_16_E = 97 , - WIFI_EXT_MACTX_PHY_OFF_E = 99 , - WIFI_EXT_MACTX_SYNTH_OFF_E = 101 , - WIFI_EXT_MACTX_EXPECT_CBF_PER_USER_E = 103 , - WIFI_EXT_MACTX_L_SIG_A_E = 105 , - WIFI_EXT_MACTX_HT_SIG_E = 107 , - WIFI_EXT_MACTX_VHT_SIG_B_SU20_E = 109 , - WIFI_EXT_MACTX_VHT_SIG_B_SU80_E = 111 , - WIFI_EXT_MACTX_VHT_SIG_B_MU20_E = 113 , - WIFI_EXT_MACTX_VHT_SIG_B_MU80_E = 115 , - WIFI_EXT_MACTX_SERVICE_E = 117 , - WIFI_EXT_MACTX_HE_SIG_A_MU_DL_E = 119 , - WIFI_EXT_MACTX_HE_SIG_B1_MU_E = 121 , - WIFI_EXT_MACTX_HE_SIG_B2_OFDMA_E = 123 , - WIFI_EXT_MACTX_MU_UPLINK_COMMON_E = 125 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_E = 127 , - WIFI_EXT_MACTX_DEBUG_E = 129 , - WIFI_EXT_PHYRX_GENERATED_CBF_DETAILS_E = 131 , - WIFI_EXT_PHYRX_RSSI_HT_E = 133 , - WIFI_EXT_PHYRX_PKT_END_E = 135 , - WIFI_EXT_PHYRX_CBF_TRANSFER_DONE_E = 137 , - WIFI_EXT_PHYRX_L_SIG_A_E = 139 , - WIFI_EXT_PHYRX_HT_SIG_E = 141 , - WIFI_EXT_PHYRX_VHT_SIG_B_SU20_E = 143 , - WIFI_EXT_PHYRX_VHT_SIG_B_SU80_E = 145 , - WIFI_EXT_PHYRX_VHT_SIG_B_MU20_E = 147 , - WIFI_EXT_PHYRX_VHT_SIG_B_MU80_E = 149 , - WIFI_EXT_PHYRX_HE_SIG_A_SU_E = 151 , - WIFI_EXT_PHYRX_HE_SIG_A_MU_UL_E = 153 , - WIFI_EXT_PHYRX_HE_SIG_B2_MU_E = 155 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_E = 157 , - WIFI_EXT_PHYRX_DATA_DONE_E = 159 , - WIFI_EXT_DUMMY_E = 161 , - WIFI_EXT_MPDU_LIMIT_E = 163 , - WIFI_EXT_OLE_BUF_STATUS_E = 165 , - WIFI_EXT_PCU_PPDU_SETUP_END_E = 167 , - WIFI_EXT_PCU_PPDU_SETUP_START_E = 169 , - WIFI_EXT_PDG_RESPONSE_E = 171 , - WIFI_EXT_SCH_WAIT_INSTR_E = 173 , - WIFI_EXT_PHYTX_LINK_STATE_E = 175 , - WIFI_EXT_TQM_GEN_MPDU_LENGTH_LIST_E = 177 , - WIFI_EXT_TQM_GEN_MPDUS_E = 179 , - WIFI_EXT_TQM_REMOVE_MPDU_E = 181 , - WIFI_EXT_TQM_REMOVE_MSDU_E = 183 , - WIFI_EXT_TQM_UPDATE_TX_MPDU_COUNT_E = 185 , - WIFI_EXT_OFDMA_TRIGGER_DETAILS_E = 187 , - WIFI_EXT_TX_FES_SETUP_E = 189 , - WIFI_EXT_EXPECTED_RESPONSE_E = 191 , - WIFI_EXT_TX_MPDU_START_E = 193 , - WIFI_EXT_TX_MSDU_START_E = 195 , - WIFI_EXT_TXPCU_BUFFER_STATUS_E = 197 , - WIFI_EXT_DATA_TO_TIME_CONFIG_E = 199 , - WIFI_EXT_MPDU_INFO_E = 201 , - WIFI_EXT_TX_11AH_SETUP_E = 203 , - WIFI_EXT_TX_PEER_ENTRY_E = 205 , - WIFI_EXT_EXAMPLE_USER_TLV_44_E = 207 , - WIFI_EXT_TX_FLUSH_REQ_E = 209 , - WIFI_EXT_TQM_GET_MPDU_QUEUE_STATS_E = 211 , - WIFI_EXT_EXAMPLE_USER_CTLV_44_E = 213 , - WIFI_EXT_TX_FES_STATUS_USER_PPDU_E = 215 , - WIFI_EXT_TX_FES_STATUS_END_E = 217 , - WIFI_EXT_RXPCU_TX_SETUP_CLEAR_E = 219 , - WIFI_EXT_RX_FRAME_BITMAP_ACK_E = 221 , - WIFI_EXT_RX_START_PARAM_E = 223 , - WIFI_EXT_RX_PPDU_END_E = 225 , - WIFI_EXT_RX_MPDU_END_E = 227 , - WIFI_EXT_RX_MSDU_END_E = 229 , - WIFI_EXT_RECEIVED_RESPONSE_INFO_E = 231 , - WIFI_EXT_RX_HEADER_E = 233 , - WIFI_EXT_RX_FLUSH_E = 235 , - WIFI_EXT_RX_FRAMELESS_BAR_DETAILS_E = 237 , - WIFI_EXT_TQM_GET_MSDU_FLOW_STATS_STATUS_E = 239 , - WIFI_EXT_PCU_PPDU_SETUP_USER_E = 241 , - WIFI_EXT_RX_PM_INFO_E = 243 , - WIFI_EXT_RX_PRE_PPDU_START_E = 245 , - WIFI_EXT_TX_FES_SETUP_COMPLETE_E = 247 , - WIFI_EXT_TXDMA_STOP_REQUEST_E = 249 , - WIFI_EXT_RXPCU_USER_SETUP_E = 251 , - WIFI_EXT_TQM_ACKED_MPDU_E = 253 , - WIFI_EXT_COEX_TX_STATUS_E = 255 , - WIFI_EXT_COEX_STATUS_BROADCAST_E = 257 , - WIFI_EXT_RESPONSE_END_STATUS_E = 259 , - WIFI_EXT_RECEIVED_TRIGGER_INFO_E = 261 , - WIFI_EXT_RX_PPDU_ACK_REPORT_E = 263 , - WIFI_EXT_SCH_COEX_STATUS_E = 265 , - WIFI_EXT_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 267 , - WIFI_EXT_TX_FES_STATUS_START_PPDU_E = 269 , - WIFI_EXT_TXPCU_PHYTX_DEBUG32_E = 271 , - WIFI_EXT_TX_MPDU_COUNT_TRANSFER_END_E = 273 , - WIFI_EXT_WHO_ANCHOR_VALUE_E = 275 , - WIFI_EXT_WHO_COMMIT_E = 277 , - WIFI_EXT_WHO_FLUSH_E = 279 , - WIFI_EXT_WHO_L2_PAYLOAD_E = 281 , - WIFI_EXT_WHO_L3_INFO_E = 283 , - WIFI_EXT_WHO_L4_INFO_E = 285 , - WIFI_EXT_WHO_MSDU_MISC_E = 287 , - WIFI_EXT_WHO_PACKET_HDR_E = 289 , - WIFI_EXT_WHO_PPDU_START_E = 291 , - WIFI_EXT_WHO_WMAC_HEADER_PV0_E = 293 , - WIFI_EXT_WHO_WMAC_IV_E = 295 , - WIFI_EXT_MPDU_INFO_BITMAP_E = 297 , - WIFI_EXT_SCHEDULER_SELFGEN_RESPONSE_STATUS_E = 299 , - WIFI_EXT_TQM_ACKED_MPDU_STATUS_E = 301 , - WIFI_EXT_TQM_LIST_GEN_DONE_E = 303 , - WIFI_EXT_TX_LAST_MPDU_END_E = 305 , - WIFI_EXT_PPDU_TX_END_E = 307 , - WIFI_EXT_MPDU_INFO_GLOBAL_END_E = 309 , - WIFI_EXT_RX_PPDU_END_USER_STATS_E = 311 , - WIFI_EXT_REO_GET_QUEUE_STATS_E = 313 , - WIFI_EXT_REO_FLUSH_CACHE_E = 315 , - WIFI_EXT_REO_GET_QUEUE_STATS_STATUS_E = 317 , - WIFI_EXT_REO_FLUSH_CACHE_STATUS_E = 319 , - WIFI_EXT_TQM_FLUSH_CACHE_E = 321 , - WIFI_EXT_TQM_FLUSH_CACHE_STATUS_E = 323 , - WIFI_EXT_RX_PPDU_END_STATUS_DONE_E = 325 , - WIFI_EXT_SCHEDULER_MLO_SW_MSG_STATUS_E = 327 , - WIFI_EXT_TX_DATA_SYNC_E = 329 , - WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_E = 331 , - WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_STATUS_E = 333 , - WIFI_EXT_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 335 , - WIFI_EXT_REO_FLUSH_TIMEOUT_LIST_E = 337 , - WIFI_EXT_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 339 , - WIFI_EXT_EXAMPLE_USER_TLV_32_NAME_E = 341 , - WIFI_EXT_RX_RING_MASK_E = 343 , - WIFI_EXT_RXPCU_PPDU_END_INFO_E = 345 , - WIFI_EXT_PDG_SW_MODE_BW_START_E = 347 , - WIFI_EXT_PDG_WAIT_FOR_MAC_REQUEST_E = 349 , - WIFI_EXT_SCHEDULER_END_E = 351 , - WIFI_EXT_RX_PPDU_END_DROPPED_E = 353 , - WIFI_EXT_RX_MPDU_START_DROPPED_E = 355 , - WIFI_EXT_RX_MSDU_END_DROPPED_E = 357 , - WIFI_EXT_RX_ATTENTION_DROPPED_E = 359 , - WIFI_EXT_RXPCU_USER_SETUP_EXT_E = 361 , - WIFI_EXT_MACTX_SYNTH_ON_E = 363 , - WIFI_EXT_TQM_MPDU_GLOBAL_START_E = 365 , - WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_E = 367 , - WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 369 , - WIFI_EXT_REO_UPDATE_RX_REO_QUEUE_E = 371 , - WIFI_EXT_PDG_TRIG_RESPONSE_E = 373 , - WIFI_EXT_ABORT_FROM_PHYRX_DETAILS_E = 375 , - WIFI_EXT_MPDUS_AVAILABLE_E = 377 , - WIFI_EXT_PHYRX_TX_START_TIMING_E = 379 , - WIFI_EXT_NDP_PREAMBLE_DONE_E = 381 , - WIFI_EXT_SCH_TQM_CMD_WRAPPER_CONT_DROP_E = 383 , - WIFI_EXT_TX_PUNCTURE_SETUP_E = 385 , - WIFI_EXT_MACTX_PREFETCH_CV_COMMON_E = 387 , - WIFI_EXT_MACTX_MU_UPLINK_COMMON_PUNC_E = 389 , - WIFI_EXT_RECEIVED_RESPONSE_USER_7_0_E = 391 , - WIFI_EXT_RECEIVED_RESPONSE_USER_23_16_E = 393 , - WIFI_EXT_RECEIVED_RESPONSE_USER_36_32_E = 395 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 397 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 399 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 401 , - WIFI_EXT_RX_PPDU_END_START_E = 403 , - WIFI_EXT_RX_PPDU_END_LAST_E = 405 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 407 , - WIFI_EXT_OBSS_SR_INFO_E = 409 , - WIFI_EXT_HWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 411 , - WIFI_EXT_MACTX_MCC_SWITCH_E = 413 , - WIFI_EXT_PHYTX_MCC_SWITCH_ACK_E = 415 , - WIFI_EXT_PHYTX_EMLSR_PRE_SWITCH_ACK_E = 417 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 419 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 421 , - WIFI_EXT_SCH_TLV_WRAPPER_E = 423 , - WIFI_EXT_MPDU_INFO_6X_E = 425 , - WIFI_EXT_MACTX_U_SIG_EHT_SU_MU_E = 427 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG0_CFG_E = 429 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG2_CFG_E = 431 , - WIFI_EXT_PHYRX_U_SIG_EHT_TB_E = 433 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 435 , - WIFI_EXT_MACRX_LMR_READ_REQUEST_E = 437 , - WIFI_EXT_PHYRX_LMR_TRANSFER_DONE_E = 439 , - WIFI_EXT_PHYRX_LMR_READ_REQUEST_ACK_E = 441 , - WIFI_EXT_PHYRX_USER_INFO_MU_UL_E = 443 , - WIFI_EXT_SCHEDULER_NAV_INFO_E = 445 , - WIFI_EXT_LMR_PEER_ENTRY_E = 447 , - WIFI_EXT_LMR_DATA_E = 449 , - WIFI_EXT_REO_GET_QUEUE_1K_STATS_STATUS_E = 451 , - WIFI_EXT_TX_FES_STATUS_1K_BA_E = 453 , - WIFI_EXT_MACRX_INBSS_OBSS_IND_E = 455 , - WIFI_EXT_MLO_TX_NOTIFICATION_SU_E = 457 , - WIFI_EXT_MLO_TX_REQ_SU_E = 459 , - WIFI_EXT_MLO_TX_RESP_E = 461 , - WIFI_EXT_MLO_BKOFF_TRUNC_REQ_E = 463 , - WIFI_EXT_MLO_MESSAGE_E = 465 , - WIFI_EXT_MLO_FES_SETUP_E = 467 , - WIFI_EXT_MLO_PDG_FES_SETUP_MU_E = 469 , - WIFI_EXT_MON_BUFFER_ADDR_E = 471 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 473 , - WIFI_EXT_MACTX_EHT_SIG_USR_OFDMA_E = 475 , - WIFI_EXT_MACTX_U_SIG_UHR_TB_E = 477 , - WIFI_EXT_TX_MSDU_COMPRESSED_DETAILS_TLV_E = 479 , - WIFI_EXT_PHYRX_EHT_SIG_USR_OFDMA_E = 481 , - WIFI_EXT_PHYRX_PKT_END_PART1_E = 483 , - WIFI_EXT_MACTX_SECURE_LTF_SEQ_PTR_E = 485 , - WIFI_EXT_MLO_PDG_BKOFF_TRUNC_NOTIFY_E = 487 , - WIFI_EXT_PHYTX_LOCATION_E = 489 , - WIFI_EXT_MPDU_LENGTH_STRUCTS_START_E = 491 , - WIFI_EXT_MACTX_EHT_SIG_USR_MU_MIMO_E = 493 , - WIFI_EXT_PHYRX_EHT_SIG_USR_MU_MIMO_E = 495 , - WIFI_EXT_PHYRX_GENERIC_EHT_OR_UHR_SIG_E = 497 , - WIFI_EXT_OVERWRITE_RESP_PREAMBLE_INFO_E = 499 , - WIFI_EXT_OVERWRITE_RESP_END_E = 501 , - WIFI_EXT_MON_DROP_E = 503 , - WIFI_EXT_MACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 505 , - WIFI_EXT_MACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 507 , - WIFI_EXT_MACTX_PREFETCH_CV_PER_USER_E = 509 , - WIFI_EXT_MACTX_BF_PARAMS_UPDATE_COMMON_E = 511 , - WIFI_EXT_RANGING_USER_DETAILS_E = 513 , - WIFI_EXT_PHYTX_CV_CORR_COMMON_E = 515 , - WIFI_EXT_MACTX_CV_CORR_COMMON_E = 517 , - WIFI_EXT_BW_PUNCTURE_EVAL_WRAPPER_E = 519 , - WIFI_EXT_MACTX_TX_NOTIFICATION_FOR_PHY_E = 521 , - WIFI_EXT_MACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 523 , - WIFI_EXT_FW2SW_MON_E = 525 , - WIFI_EXT_MACTX_EMLSR_PRE_SWITCH_E = 527 , - WIFI_EXT_MACTX_EMLSR_SWITCH_BACK_E = 529 , - WIFI_EXT_PHYTX_EMLSR_SWITCH_BACK_ACK_E = 531 , - WIFI_EXT_EAD_LEGACY_STATUS_CONTROL_E = 533 , - WIFI_EXT_TPI_TX_INITIALIZATION_CONFIG_E = 535 , - WIFI_EXT_TPI_LEGACY_STATUS_CONTROL_E = 537 , - WIFI_EXT_TPI_MPDU_START_E = 539 , - WIFI_EXT_TPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E = 541 , - WIFI_EXT_TPI_TX_START_TIME_ARRIVED_E = 543 , - WIFI_EXT_TPI_ERROR_STATUS_E = 545 , - WIFI_EXT_RPI_SEND_TLV_TO_PHYRX_E = 547 , - WIFI_EXT_RPI_LEGACY_INTERRUPT_CONTROL_E = 549 , - WIFI_EXT_RPI_ERROR_STATUS_E = 551 , - WIFI_EXT_RPI_RX_FRAME_UPDATE_STATUS_E = 553 , - WIFI_EXT_TCC_TLV_FETCH_E = 555 , - WIFI_EXT_TCC_LEGACY_INTERRUPT_CONTROL_E = 557 , - WIFI_EXT_TCC_ERROR_STATUS_E = 559 , - WIFI_EXT_TCC_PRE_BACKOFF_CMD_AVAILABLE_E = 561 , - WIFI_EXT_TCC_BURST_CMD_AVAILABLE_E = 563 , - WIFI_EXT_EAD_RING_AIR_TIME_REFERENCE_E = 565 , - WIFI_EXT_RPI_WRITE_INFO_TO_EXT_MEM_E = 567 , - WIFI_EXT_RPI_INIT_LMR_DATA_RESP_ADDR_E = 569 , - WIFI_EXT_TPI_SEND_CTLV_44_TO_PHYTX_E = 571 , - WIFI_EXT_TPI_TX_FRAME_UPDATE_STATUS_E = 573 , - WIFI_EXT_EAD_MPDU_DATA_FETCH_CONTINUATION_E = 575 , - WIFI_EXT_EAD_MSDU_STATUS_DETAILS_E = 577 , - WIFI_EXT_MACTX_UHR_SIG_USR_MU_MIMO_E = 579 , - WIFI_EXT_MACTX_ELR_SIG_UHR_SU_E = 581 , - WIFI_EXT_PEER_BLACKOUT_DETAILS_E = 583 , - WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_E = 585 , - WIFI_EXT_HDR_CTRL_PROT_DATA_E = 587 , - WIFI_EXT_HDR_CTRL_PROT_MIC_STATUS_E = 589 , - WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_DONE_E = 591 , - WIFI_EXT_MACTX_U_SIG_UHR_COBF_E = 593 , - WIFI_EXT_SPARE_REUSE_TAG_0_E = 595 , - WIFI_EXT_SPARE_REUSE_TAG_2_E = 597 , - WIFI_EXT_SPARE_REUSE_TAG_4_E = 599 , - WIFI_EXT_SPARE_REUSE_TAG_6_E = 601 , - WIFI_EXT_SPARE_REUSE_TAG_8_E = 603 , - WIFI_EXT_SPARE_REUSE_TAG_10_E = 605 , - WIFI_EXT_SPARE_REUSE_TAG_12_E = 607 , - WIFI_EXT_SPARE_REUSE_TAG_14_E = 609 , - WIFI_EXT_SPARE_REUSE_TAG_16_E = 611 , - WIFI_EXT_SPARE_REUSE_TAG_18_E = 613 , - WIFI_EXT_SPARE_REUSE_TAG_20_E = 615 , - WIFI_EXT_SPARE_REUSE_TAG_22_E = 617 , - WIFI_EXT_SPARE_REUSE_TAG_24_E = 619 , - WIFI_EXT_SPARE_REUSE_TAG_26_E = 621 , - WIFI_EXT_SPARE_REUSE_TAG_28_E = 623 , - WIFI_EXT_SPARE_REUSE_TAG_30_E = 625 , - WIFI_EXT_SPARE_REUSE_TAG_32_E = 627 , - WIFI_EXT_SPARE_REUSE_TAG_34_E = 629 , - WIFI_EXT_SPARE_REUSE_TAG_36_E = 631 , - WIFI_EXT_SPARE_REUSE_TAG_38_E = 633 , - WIFI_EXT_SPARE_REUSE_TAG_40_E = 635 , - WIFI_EXT_SPARE_REUSE_TAG_42_E = 637 , - WIFI_EXT_SPARE_REUSE_TAG_44_E = 639 , - WIFI_EXT_SPARE_REUSE_TAG_46_E = 641 , - WIFI_EXT_SPARE_REUSE_TAG_48_E = 643 , - WIFI_EXT_SPARE_REUSE_TAG_50_E = 645 , - WIFI_EXT_SPARE_REUSE_TAG_52_E = 647 , - WIFI_EXT_SPARE_REUSE_TAG_54_E = 649 , - WIFI_EXT_SPARE_REUSE_TAG_56_E = 651 , - WIFI_EXT_SPARE_REUSE_TAG_58_E = 653 , - WIFI_EXT_SPARE_REUSE_TAG_60_E = 655 , - WIFI_EXT_SPARE_REUSE_TAG_62_E = 657 , - WIFI_EXT_SPARE_REUSE_TAG_64_E = 659 , - WIFI_EXT_SPARE_REUSE_TAG_66_E = 661 , - WIFI_EXT_SPARE_REUSE_TAG_68_E = 663 , - WIFI_EXT_SPARE_REUSE_TAG_70_E = 665 , - WIFI_EXT_SPARE_REUSE_TAG_72_E = 667 , - WIFI_EXT_SPARE_REUSE_TAG_74_E = 669 , - WIFI_EXT_SPARE_REUSE_TAG_76_E = 671 , - WIFI_EXT_SPARE_REUSE_TAG_78_E = 673 , - WIFI_EXT_SPARE_REUSE_TAG_80_E = 675 , - WIFI_EXT_SPARE_REUSE_TAG_82_E = 677 , - WIFI_EXT_SPARE_REUSE_TAG_84_E = 679 , - WIFI_EXT_SPARE_REUSE_TAG_86_E = 681 , - WIFI_EXT_SPARE_REUSE_TAG_88_E = 683 , - WIFI_EXT_SPARE_REUSE_TAG_90_E = 685 , - WIFI_EXT_SPARE_REUSE_TAG_92_E = 687 , - WIFI_EXT_SPARE_REUSE_TAG_94_E = 689 , - WIFI_EXT_SPARE_REUSE_TAG_96_E = 691 , - WIFI_EXT_SPARE_REUSE_TAG_98_E = 693 , - WIFI_EXT_SPARE_REUSE_TAG_100_E = 695 , - WIFI_EXT_SPARE_REUSE_TAG_102_E = 697 , - WIFI_EXT_SPARE_REUSE_TAG_104_E = 699 , - WIFI_EXT_SPARE_REUSE_TAG_106_E = 701 , - WIFI_EXT_SPARE_REUSE_TAG_108_E = 703 , - WIFI_EXT_SPARE_REUSE_TAG_110_E = 705 , - WIFI_EXT_SPARE_REUSE_TAG_112_E = 707 , - WIFI_EXT_SPARE_REUSE_TAG_114_E = 709 , - WIFI_EXT_SPARE_REUSE_TAG_116_E = 711 , - WIFI_EXT_SPARE_REUSE_TAG_118_E = 713 , - WIFI_EXT_SPARE_REUSE_TAG_120_E = 715 , - WIFI_EXT_SPARE_REUSE_TAG_122_E = 717 , - WIFI_EXT_SPARE_REUSE_TAG_124_E = 719 , - WIFI_EXT_SPARE_REUSE_TAG_126_E = 721 , - WIFI_EXT_SPARE_REUSE_TAG_128_E = 723 , - WIFI_EXT_SPARE_REUSE_TAG_130_E = 725 , - WIFI_EXT_SPARE_REUSE_TAG_132_E = 727 , - WIFI_EXT_SPARE_REUSE_TAG_134_E = 729 , - WIFI_EXT_SPARE_REUSE_TAG_136_E = 731 , - WIFI_EXT_SPARE_REUSE_TAG_138_E = 733 , - WIFI_EXT_SPARE_REUSE_TAG_140_E = 735 , - WIFI_EXT_SPARE_REUSE_TAG_142_E = 737 , - WIFI_EXT_SPARE_REUSE_TAG_144_E = 739 , - WIFI_EXT_SPARE_REUSE_TAG_146_E = 741 , - WIFI_EXT_SPARE_REUSE_TAG_148_E = 743 , - WIFI_EXT_SPARE_REUSE_TAG_150_E = 745 , - WIFI_EXT_SPARE_REUSE_TAG_152_E = 747 , - WIFI_EXT_SPARE_REUSE_TAG_154_E = 749 , - WIFI_EXT_SPARE_REUSE_TAG_156_E = 751 , - WIFI_EXT_SPARE_REUSE_TAG_158_E = 753 , - WIFI_EXT_SPARE_REUSE_TAG_160_E = 755 , - WIFI_EXT_SPARE_REUSE_TAG_162_E = 757 , - WIFI_EXT_SPARE_REUSE_TAG_164_E = 759 , - WIFI_EXT_SPARE_REUSE_TAG_166_E = 761 , - WIFI_EXT_SPARE_REUSE_TAG_168_E = 763 , - WIFI_EXT_SPARE_REUSE_TAG_170_E = 765 , - WIFI_EXT_SPARE_REUSE_TAG_172_E = 767 , - WIFI_EXT_SPARE_REUSE_TAG_174_E = 769 , - WIFI_EXT_SPARE_REUSE_TAG_176_E = 771 , - WIFI_EXT_SPARE_REUSE_TAG_178_E = 773 , - WIFI_EXT_SPARE_REUSE_TAG_180_E = 775 , - WIFI_EXT_SPARE_REUSE_TAG_182_E = 777 , - WIFI_EXT_SPARE_REUSE_TAG_184_E = 779 , - WIFI_EXT_SPARE_REUSE_TAG_186_E = 781 , - WIFI_EXT_SPARE_REUSE_TAG_188_E = 783 , - WIFI_EXT_SPARE_REUSE_TAG_190_E = 785 , - WIFI_EXT_SPARE_REUSE_TAG_192_E = 787 , - WIFI_EXT_SPARE_REUSE_TAG_194_E = 789 , - WIFI_EXT_SPARE_REUSE_TAG_196_E = 791 , - WIFI_EXT_SPARE_REUSE_TAG_198_E = 793 , - WIFI_EXT_SPARE_REUSE_TAG_200_E = 795 , - WIFI_EXT_SPARE_REUSE_TAG_202_E = 797 , - WIFI_EXT_SPARE_REUSE_TAG_204_E = 799 , - WIFI_EXT_SPARE_REUSE_TAG_206_E = 801 , - WIFI_EXT_SPARE_REUSE_TAG_208_E = 803 , - WIFI_EXT_SPARE_REUSE_TAG_210_E = 805 , - WIFI_EXT_SPARE_REUSE_TAG_212_E = 807 , - WIFI_EXT_SPARE_REUSE_TAG_214_E = 809 , - WIFI_EXT_SPARE_REUSE_TAG_216_E = 811 , - WIFI_EXT_SPARE_REUSE_TAG_218_E = 813 , - WIFI_EXT_SPARE_REUSE_TAG_220_E = 815 , - WIFI_EXT_SPARE_REUSE_TAG_222_E = 817 , - WIFI_EXT_SPARE_REUSE_TAG_224_E = 819 , - WIFI_EXT_SPARE_REUSE_TAG_226_E = 821 , - WIFI_EXT_SPARE_REUSE_TAG_228_E = 823 , - WIFI_EXT_SPARE_REUSE_TAG_230_E = 825 , - WIFI_EXT_SPARE_REUSE_TAG_232_E = 827 , - WIFI_EXT_SPARE_REUSE_TAG_234_E = 829 , - WIFI_EXT_SPARE_REUSE_TAG_236_E = 831 , - WIFI_EXT_SPARE_REUSE_TAG_238_E = 833 , - WIFI_EXT_SPARE_REUSE_TAG_240_E = 835 , - WIFI_EXT_SPARE_REUSE_TAG_242_E = 837 , - WIFI_EXT_SPARE_REUSE_TAG_244_E = 839 , - WIFI_EXT_SPARE_REUSE_TAG_246_E = 841 , - WIFI_EXT_SPARE_REUSE_TAG_248_E = 843 , - WIFI_EXT_SPARE_REUSE_TAG_250_E = 845 , - WIFI_EXT_SPARE_REUSE_TAG_252_E = 847 , - WIFI_EXT_SPARE_REUSE_TAG_254_E = 849 , - WIFI_EXT_SPARE_REUSE_TAG_256_E = 851 , - WIFI_EXT_SPARE_REUSE_TAG_258_E = 853 , - WIFI_EXT_SPARE_REUSE_TAG_260_E = 855 , - WIFI_EXT_SPARE_REUSE_TAG_262_E = 857 , - WIFI_EXT_SPARE_REUSE_TAG_264_E = 859 , - WIFI_EXT_SPARE_REUSE_TAG_266_E = 861 , - WIFI_EXT_SPARE_REUSE_TAG_268_E = 863 , - WIFI_EXT_SPARE_REUSE_TAG_270_E = 865 , - WIFI_EXT_SPARE_REUSE_TAG_272_E = 867 , - WIFI_EXT_SPARE_REUSE_TAG_274_E = 869 , - WIFI_EXT_SPARE_REUSE_TAG_276_E = 871 , - WIFI_EXT_SPARE_REUSE_TAG_278_E = 873 , - WIFI_EXT_SPARE_REUSE_TAG_280_E = 875 , - WIFI_EXT_SPARE_REUSE_TAG_282_E = 877 , - WIFI_EXT_SPARE_REUSE_TAG_284_E = 879 , - WIFI_EXT_SPARE_REUSE_TAG_286_E = 881 , - WIFI_EXT_SPARE_REUSE_TAG_288_E = 883 , - WIFI_EXT_SPARE_REUSE_TAG_290_E = 885 , - WIFI_EXT_SPARE_REUSE_TAG_292_E = 887 , - WIFI_EXT_SPARE_REUSE_TAG_294_E = 889 , - WIFI_EXT_SPARE_REUSE_TAG_296_E = 891 , - WIFI_EXT_SPARE_REUSE_TAG_298_E = 893 , - WIFI_EXT_SPARE_REUSE_TAG_300_E = 895 , - WIFI_EXT_SPARE_REUSE_TAG_302_E = 897 , - WIFI_EXT_SPARE_REUSE_TAG_304_E = 899 , - WIFI_EXT_SPARE_REUSE_TAG_306_E = 901 , - WIFI_EXT_SPARE_REUSE_TAG_308_E = 903 , - WIFI_EXT_SPARE_REUSE_TAG_310_E = 905 , - WIFI_EXT_SPARE_REUSE_TAG_312_E = 907 , - WIFI_EXT_SPARE_REUSE_TAG_314_E = 909 , - WIFI_EXT_SPARE_REUSE_TAG_316_E = 911 , - WIFI_EXT_SPARE_REUSE_TAG_318_E = 913 , - WIFI_EXT_SPARE_REUSE_TAG_320_E = 915 , - WIFI_EXT_SPARE_REUSE_TAG_322_E = 917 , - WIFI_EXT_SPARE_REUSE_TAG_324_E = 919 , - WIFI_EXT_SPARE_REUSE_TAG_326_E = 921 , - WIFI_EXT_SPARE_REUSE_TAG_328_E = 923 , - WIFI_EXT_SPARE_REUSE_TAG_330_E = 925 , - WIFI_EXT_SPARE_REUSE_TAG_332_E = 927 , - WIFI_EXT_SPARE_REUSE_TAG_334_E = 929 , - WIFI_EXT_SPARE_REUSE_TAG_336_E = 931 , - WIFI_EXT_SPARE_REUSE_TAG_338_E = 933 , - WIFI_EXT_SPARE_REUSE_TAG_340_E = 935 , - WIFI_EXT_SPARE_REUSE_TAG_342_E = 937 , - WIFI_EXT_SPARE_REUSE_TAG_344_E = 939 , - WIFI_EXT_SPARE_REUSE_TAG_346_E = 941 , - WIFI_EXT_SPARE_REUSE_TAG_348_E = 943 , - WIFI_EXT_SPARE_REUSE_TAG_350_E = 945 , - WIFI_EXT_SPARE_REUSE_TAG_352_E = 947 , - WIFI_EXT_SPARE_REUSE_TAG_354_E = 949 , - WIFI_EXT_SPARE_REUSE_TAG_356_E = 951 , - WIFI_EXT_SPARE_REUSE_TAG_358_E = 953 , - WIFI_EXT_SPARE_REUSE_TAG_360_E = 955 , - WIFI_EXT_SPARE_REUSE_TAG_362_E = 957 , - WIFI_EXT_SPARE_REUSE_TAG_364_E = 959 , - WIFI_EXT_SPARE_REUSE_TAG_366_E = 961 , - WIFI_EXT_SPARE_REUSE_TAG_368_E = 963 , - WIFI_EXT_SPARE_REUSE_TAG_370_E = 965 , - WIFI_EXT_SPARE_REUSE_TAG_372_E = 967 , - WIFI_EXT_SPARE_REUSE_TAG_374_E = 969 , - WIFI_EXT_SPARE_REUSE_TAG_376_E = 971 , - WIFI_EXT_SPARE_REUSE_TAG_378_E = 973 , - WIFI_EXT_SPARE_REUSE_TAG_380_E = 975 , - WIFI_EXT_SPARE_REUSE_TAG_382_E = 977 , - WIFI_EXT_SPARE_REUSE_TAG_384_E = 979 , - WIFI_EXT_SPARE_REUSE_TAG_386_E = 981 , - WIFI_EXT_SPARE_REUSE_TAG_388_E = 983 , - WIFI_EXT_SPARE_REUSE_TAG_390_E = 985 , - WIFI_EXT_SPARE_REUSE_TAG_392_E = 987 , - WIFI_EXT_SPARE_REUSE_TAG_394_E = 989 , - WIFI_EXT_SPARE_REUSE_TAG_396_E = 991 , - WIFI_EXT_SPARE_REUSE_TAG_398_E = 993 , - WIFI_EXT_SPARE_REUSE_TAG_400_E = 995 , - WIFI_EXT_SPARE_REUSE_TAG_402_E = 997 , - WIFI_EXT_SPARE_REUSE_TAG_404_E = 999 , - WIFI_EXT_SPARE_REUSE_TAG_406_E = 1001 , - WIFI_EXT_SPARE_REUSE_TAG_408_E = 1003 , - WIFI_EXT_SPARE_REUSE_TAG_410_E = 1005 , - WIFI_EXT_SPARE_REUSE_TAG_412_E = 1007 , - WIFI_EXT_SPARE_REUSE_TAG_414_E = 1009 , - WIFI_EXT_SPARE_REUSE_TAG_416_E = 1011 , - WIFI_EXT_SPARE_REUSE_TAG_418_E = 1013 , - WIFI_EXT_SPARE_REUSE_TAG_420_E = 1015 , - WIFI_EXT_SPARE_REUSE_TAG_422_E = 1017 , - WIFI_EXT_SPARE_REUSE_TAG_424_E = 1019 , - WIFI_EXT_SPARE_REUSE_TAG_426_E = 1021 -} ext_tlv_tag_def__e; - -typedef enum { - WIFI_N_EXT_MACTX_CBF_START_E = 0 , - WIFI_N_EXT_PHYRX_CBF_DATA_RESP_E = 2 , - WIFI_N_EXT_PHYRX_USER_ABORT_NOTIFICATION_E = 4 , - WIFI_N_EXT_MACTX_CBF_DATA_E = 6 , - WIFI_N_EXT_PHYRX_LMR_DATA_RESP_E = 8 , - WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 , - WIFI_N_EXT_RXPCU_TO_UCODE_FCS_STATUS_E = 12 , - WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 , - WIFI_N_EXT_RXPCU_TO_UCODE_END_E = 16 , - WIFI_N_EXT_PHYRX_NC_ABORT_REQUEST_E = 18 , - WIFI_N_EXT_PHYRX_NC_DATA_E = 20 , - WIFI_N_EXT_MACRX_CBF_READ_REQUEST_E = 64 , - WIFI_N_EXT_MACRX_EXPECT_NDP_RECEPTION_E = 66 , - WIFI_N_EXT_MACRX_NDP_TIMEOUT_E = 68 , - WIFI_N_EXT_MACRX_REQ_IMPLICIT_FB_E = 70 , - WIFI_N_EXT_MACRX_NAP_USER_E = 72 , - WIFI_N_EXT_PHYTX_OTHER_TRANSMIT_INFO16_E = 74 , - WIFI_N_EXT_PHYTX_ABORT_REQUEST_E = 76 , - WIFI_N_EXT_PHYTX_PPDU_HEADER_INFO_REQUEST_E = 78 , - WIFI_N_EXT_PHYTX_DATA_REQUEST_E = 80 , - WIFI_N_EXT_PHYTX_NAP_ACK_E = 82 , - WIFI_N_EXT_PHYTX_OFF_ACK_E = 84 , - WIFI_N_EXT_PHYTX_SYNTH_OFF_ACK_E = 86 , - WIFI_N_EXT_MACTX_ABORT_REQUEST_E = 88 , - WIFI_N_EXT_MACTX_PKT_END_E = 90 , - WIFI_N_EXT_MACTX_BF_PARAMS_COMMON_E = 92 , - WIFI_N_EXT_MACTX_PREFETCH_CV_E = 94 , - WIFI_N_EXT_MACTX_USER_DESC_PER_USER_E = 96 , - WIFI_N_EXT_EXAMPLE_TLV_16_E = 98 , - WIFI_N_EXT_MACTX_PHY_ON_E = 100 , - WIFI_N_EXT_MACTX_EXPECT_CBF_COMMON_E = 102 , - WIFI_N_EXT_MACTX_PHY_DESC_E = 104 , - WIFI_N_EXT_MACTX_L_SIG_B_E = 106 , - WIFI_N_EXT_MACTX_VHT_SIG_A_E = 108 , - WIFI_N_EXT_MACTX_VHT_SIG_B_SU40_E = 110 , - WIFI_N_EXT_MACTX_VHT_SIG_B_SU160_E = 112 , - WIFI_N_EXT_MACTX_VHT_SIG_B_MU40_E = 114 , - WIFI_N_EXT_MACTX_VHT_SIG_B_MU160_E = 116 , - WIFI_N_EXT_MACTX_HE_SIG_A_SU_E = 118 , - WIFI_N_EXT_MACTX_HE_SIG_A_MU_UL_E = 120 , - WIFI_N_EXT_MACTX_HE_SIG_B2_MU_E = 122 , - WIFI_N_EXT_MACTX_DELETE_CV_E = 124 , - WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_E = 126 , - WIFI_N_EXT_MACTX_PHY_NAP_E = 128 , - WIFI_N_EXT_PHYRX_ABORT_ACK_E = 130 , - WIFI_N_EXT_PHYRX_RSSI_LEGACY_E = 132 , - WIFI_N_EXT_PHYRX_USER_INFO_E = 134 , - WIFI_N_EXT_PHYRX_DEBUG_E = 136 , - WIFI_N_EXT_PHYRX_CBF_TRANSFER_ABORT_E = 138 , - WIFI_N_EXT_PHYRX_L_SIG_B_E = 140 , - WIFI_N_EXT_PHYRX_VHT_SIG_A_E = 142 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_SU40_E = 144 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_SU160_E = 146 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_MU40_E = 148 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_MU160_E = 150 , - WIFI_N_EXT_PHYRX_HE_SIG_A_MU_DL_E = 152 , - WIFI_N_EXT_PHYRX_HE_SIG_B1_MU_E = 154 , - WIFI_N_EXT_PHYRX_HE_SIG_B2_OFDMA_E = 156 , - WIFI_N_EXT_PHYRX_COMMON_USER_INFO_E = 158 , - WIFI_N_EXT_COEX_TX_REQ_E = 160 , - WIFI_N_EXT_EXAMPLE_TLV_32_NAME_E = 162 , - WIFI_N_EXT_NA_LENGTH_END_E = 164 , - WIFI_N_EXT_PCU_PPDU_SETUP_DONE_E = 166 , - WIFI_N_EXT_PCU_PPDU_SETUP_INIT_E = 168 , - WIFI_N_EXT_PDG_FES_SETUP_E = 170 , - WIFI_N_EXT_PDG_TX_REQ_E = 172 , - WIFI_N_EXT_MACTX_SWITCH_TO_MAIN_E = 174 , - WIFI_N_EXT_AUX_PPDU_END_E = 176 , - WIFI_N_EXT_TQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 178 , - WIFI_N_EXT_TQM_GEN_MPDUS_STATUS_E = 180 , - WIFI_N_EXT_TQM_REMOVE_MPDU_STATUS_E = 182 , - WIFI_N_EXT_TQM_REMOVE_MSDU_STATUS_E = 184 , - WIFI_N_EXT_TQM_WRITE_CMD_E = 186 , - WIFI_N_EXT_TX_DATA_E = 188 , - WIFI_N_EXT_RX_PACKET_E = 190 , - WIFI_N_EXT_TX_MPDU_END_E = 192 , - WIFI_N_EXT_TX_MSDU_END_E = 194 , - WIFI_N_EXT_TX_SW_MODE_SETUP_E = 196 , - WIFI_N_EXT_TXPCU_USER_BUFFER_STATUS_E = 198 , - WIFI_N_EXT_EXAMPLE_USER_TLV_32_E = 200 , - WIFI_N_EXT_PDG_USER_SETUP_E = 202 , - WIFI_N_EXT_REO_UPDATE_RX_REO_QUEUE_STATUS_E = 204 , - WIFI_N_EXT_TX_RAW_OR_NATIVE_FRAME_SETUP_E = 206 , - WIFI_N_EXT_TX_FLUSH_E = 208 , - WIFI_N_EXT_TQM_WRITE_CMD_STATUS_E = 210 , - WIFI_N_EXT_TQM_GET_MSDU_FLOW_STATS_E = 212 , - WIFI_N_EXT_TX_FES_STATUS_START_E = 214 , - WIFI_N_EXT_TX_FES_STATUS_USER_RESPONSE_E = 216 , - WIFI_N_EXT_RX_TRIG_INFO_E = 218 , - WIFI_N_EXT_RX_FRAME_BITMAP_REQ_E = 220 , - WIFI_N_EXT_COEX_RX_STATUS_E = 222 , - WIFI_N_EXT_RX_PPDU_START_E = 224 , - WIFI_N_EXT_RX_MPDU_START_E = 226 , - WIFI_N_EXT_RX_MSDU_START_E = 228 , - WIFI_N_EXT_RX_ATTENTION_E = 230 , - WIFI_N_EXT_RX_PHY_SLEEP_E = 232 , - WIFI_N_EXT_RX_PEER_ENTRY_E = 234 , - WIFI_N_EXT_RX_RESPONSE_REQUIRED_INFO_E = 236 , - WIFI_N_EXT_TQM_GET_MPDU_QUEUE_STATS_STATUS_E = 238 , - WIFI_N_EXT_TX_CBF_INFO_E = 240 , - WIFI_N_EXT_RX_MPDU_PCU_START_E = 242 , - WIFI_N_EXT_RX_USER_PPDU_END_E = 244 , - WIFI_N_EXT_RX_PREAMBLE_E = 246 , - WIFI_N_EXT_TX_LAST_MPDU_FETCHED_E = 248 , - WIFI_N_EXT_RXPCU_SETUP_E = 250 , - WIFI_N_EXT_TX_FES_STATUS_ACK_OR_BA_E = 252 , - WIFI_N_EXT_COEX_TX_RESP_E = 254 , - WIFI_N_EXT_MACTX_COEX_PHY_CTRL_E = 256 , - WIFI_N_EXT_RESPONSE_START_STATUS_E = 258 , - WIFI_N_EXT_CRYPTO_STATUS_E = 260 , - WIFI_N_EXT_COEX_TX_STOP_CTRL_E = 262 , - WIFI_N_EXT_RX_PPDU_NO_ACK_REPORT_E = 264 , - WIFI_N_EXT_SCHEDULER_COMMAND_STATUS_E = 266 , - WIFI_N_EXT_TX_FES_STATUS_PROT_E = 268 , - WIFI_N_EXT_TX_FES_STATUS_START_PROT_E = 270 , - WIFI_N_EXT_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 272 , - WIFI_N_EXT_WHO_ANCHOR_OFFSET_E = 274 , - WIFI_N_EXT_WHO_CCE_INFO_E = 276 , - WIFI_N_EXT_WHO_COMMIT_DONE_E = 278 , - WIFI_N_EXT_WHO_L2_LLC_E = 280 , - WIFI_N_EXT_WHO_L3_CHECKSUM_E = 282 , - WIFI_N_EXT_WHO_L4_CHECKSUM_E = 284 , - WIFI_N_EXT_WHO_MSDU_E = 286 , - WIFI_N_EXT_WHO_PACKET_DATA_E = 288 , - WIFI_N_EXT_WHO_PPDU_END_E = 290 , - WIFI_N_EXT_WHO_TSO_E = 292 , - WIFI_N_EXT_WHO_WMAC_HEADER_PV1_E = 294 , - WIFI_N_EXT_MPDU_INFO_END_E = 296 , - WIFI_N_EXT_TX_QUEUE_EXTENSION_E = 298 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 300 , - WIFI_N_EXT_TQM_ADD_MSDU_STATUS_E = 302 , - WIFI_N_EXT_WHO_TERMINATE_E = 304 , - WIFI_N_EXT_TX_CV_DATA_E = 306 , - WIFI_N_EXT_PROT_TX_END_E = 308 , - WIFI_N_EXT_TQM_SCH_INSTR_GLOBAL_END_E = 310 , - WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT_E = 312 , - WIFI_N_EXT_REO_FLUSH_QUEUE_E = 314 , - WIFI_N_EXT_REO_UNBLOCK_CACHE_E = 316 , - WIFI_N_EXT_REO_FLUSH_QUEUE_STATUS_E = 318 , - WIFI_N_EXT_REO_UNBLOCK_CACHE_STATUS_E = 320 , - WIFI_N_EXT_TQM_UNBLOCK_CACHE_E = 322 , - WIFI_N_EXT_TQM_UNBLOCK_CACHE_STATUS_E = 324 , - WIFI_N_EXT_RX_STATUS_BUFFER_DONE_E = 326 , - WIFI_N_EXT_SCHEDULER_TXOP_DURATION_TRIGGER_E = 328 , - WIFI_N_EXT_PHYRX_CBF_READ_REQUEST_ACK_E = 330 , - WIFI_N_EXT_TQM_SYNC_CMD_E = 332 , - WIFI_N_EXT_TQM_SYNC_CMD_STATUS_E = 334 , - WIFI_N_EXT_TCC_TQM_WRAPPER_CMD_E = 336 , - WIFI_N_EXT_REO_FLUSH_TIMEOUT_LIST_STATUS_E = 338 , - WIFI_N_EXT_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 340 , - WIFI_N_EXT_RX_PPDU_START_USER_INFO_E = 342 , - WIFI_N_EXT_COEX_MAC_NAP_E = 344 , - WIFI_N_EXT_WHO_MESH_CONTROL_E = 346 , - WIFI_N_EXT_PDG_SW_MODE_BW_END_E = 348 , - WIFI_N_EXT_PDG_WAIT_FOR_PHY_REQUEST_E = 350 , - WIFI_N_EXT_RX_PPDU_START_DROPPED_E = 352 , - WIFI_N_EXT_RX_PPDU_END_STATUS_DONE_DROPPED_E = 354 , - WIFI_N_EXT_RX_MSDU_START_DROPPED_E = 356 , - WIFI_N_EXT_RX_MPDU_END_DROPPED_E = 358 , - WIFI_N_EXT_TXPCU_USER_SETUP_E = 360 , - WIFI_N_EXT_CMD_PART_0_END_E = 362 , - WIFI_N_EXT_SCH_CRITICAL_TLV_REFERENCE_E = 364 , - WIFI_N_EXT_EXAMPLE_TLV_32_E = 366 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 368 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 370 , - WIFI_N_EXT_TQM_2_SCH_MPDU_AVAILABLE_E = 372 , - WIFI_N_EXT_TRIGGER_RESPONSE_TX_DONE_E = 374 , - WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_E = 376 , - WIFI_N_EXT_RECEIVED_RESPONSE_INFO_PART2_E = 378 , - WIFI_N_EXT_TXPCU_PREAMBLE_DONE_E = 380 , - WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_RBO_DROP_E = 382 , - WIFI_N_EXT_MACTX_CLEAR_PREV_TX_INFO_E = 384 , - WIFI_N_EXT_R2R_STATUS_END_E = 386 , - WIFI_N_EXT_END_OF_FLUSH_MARKER_E = 388 , - WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_PUNC_E = 390 , - WIFI_N_EXT_RECEIVED_RESPONSE_USER_15_8_E = 392 , - WIFI_N_EXT_RECEIVED_RESPONSE_USER_31_24_E = 394 , - WIFI_N_EXT_TX_LOOPBACK_SETUP_E = 396 , - WIFI_N_EXT_SCH_WAIT_INSTR_TX_PATH_E = 398 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 400 , - WIFI_N_EXT_TX_WUR_DATA_E = 402 , - WIFI_N_EXT_RX_PPDU_END_MIDDLE_E = 404 , - WIFI_N_EXT_MACTX_BACKOFF_BASED_TRANSMISSION_E = 406 , - WIFI_N_EXT_SRP_INFO_E = 408 , - WIFI_N_EXT_SCHEDULER_SW_MSG_STATUS_E = 410 , - WIFI_N_EXT_RXPCU_SETUP_COMPLETE_E = 412 , - WIFI_N_EXT_MACTX_MCC_SWITCH_BACK_E = 414 , - WIFI_N_EXT_PHYTX_MCC_SWITCH_BACK_ACK_E = 416 , - WIFI_N_EXT_LMR_TX_END_E = 418 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 420 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 422 , - WIFI_N_EXT_SCHEDULER_STATUS_WRAPPER_E = 424 , - WIFI_N_EXT_MACTX___RESERVED_G_0013 = 426 , - WIFI_N_EXT_MACTX_U_SIG_EHT_TB_E = 428 , - WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG1_CFG_E = 430 , - WIFI_N_EXT_PHYRX_U_SIG_EHT_SU_MU_E = 432 , - WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG3_CFG_E = 434 , - WIFI_N_EXT_TX_PUNCTURE_6PATTERNS_SETUP_E = 436 , - WIFI_N_EXT_MACRX_LMR_DATA_REQUEST_E = 438 , - WIFI_N_EXT_PHYRX_LMR_TRANSFER_ABORT_E = 440 , - WIFI_N_EXT_MACRX_SECURE_LTF_SEQ_PTR_E = 442 , - WIFI_N_EXT_MPDU_QUEUE_OVERVIEW_E = 444 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E = 446 , - WIFI_N_EXT_LMR_MPDU_START_E = 448 , - WIFI_N_EXT_LMR_MPDU_END_E = 450 , - WIFI_N_EXT_RX_FRAME_1K_BITMAP_ACK_E = 452 , - WIFI_N_EXT_TQM_ACKED_1K_MPDU_E = 454 , - WIFI_N_EXT_PHYRX_LOCATION_E = 456 , - WIFI_N_EXT_MLO_TX_NOTIFICATION_MU_E = 458 , - WIFI_N_EXT_MLO_TX_REQ_MU_E = 460 , - WIFI_N_EXT_MLO_RX_NOTIFICATION_E = 462 , - WIFI_N_EXT_MLO_TBTT_NOTIFICATION_E = 464 , - WIFI_N_EXT_MLO_TS_SYNC_MSG_E = 466 , - WIFI_N_EXT_MLO_PDG_FES_SETUP_SU_E = 468 , - WIFI_N_EXT_MPDU_INFO_1K_BITMAP_E = 470 , - WIFI_N_EXT_TX_FRAG_STATE_E = 472 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 474 , - WIFI_N_EXT_MACTX_U_SIG_UHR_SU_MU_E = 476 , - WIFI_N_EXT_TX_MPDU_COMPRESSED_DETAILS_TLV_E = 478 , - WIFI_N_EXT_TX_MSDU_COMPONENT_DETAILS_TLV_E = 480 , - WIFI_N_EXT_SCHEDULER_IU_TEMPLATE_ID_E = 482 , - WIFI_N_EXT_MACTX_EXPECT_NDP_RECEPTION_E = 484 , - WIFI_N_EXT_TX_MPDU_LENGTH_AND_RESTRICTIONS_E = 486 , - WIFI_N_EXT_PHYRX___RESERVED_G_0014 = 488 , - WIFI_N_EXT_PHYTX___RESERVED_G_0014 = 490 , - WIFI_N_EXT_MACTX_EHT_SIG_USR_SU_E = 492 , - WIFI_N_EXT_PHYRX_EHT_SIG_USR_SU_E = 494 , - WIFI_N_EXT_PHYRX_GENERIC_U_SIG_E = 496 , - WIFI_N_EXT_OVERWRITE_RESP_START_E = 498 , - WIFI_N_EXT_OVERWRITE_RESP_FRAME_INFO_E = 500 , - WIFI_N_EXT_RXPCU_EARLY_RX_INDICATION_E = 502 , - WIFI_N_EXT_MACRX_MU_UPLINK_COMMON_SNIFF_E = 504 , - WIFI_N_EXT_MACRX_MU_UPLINK_USER_SEL_SNIFF_E = 506 , - WIFI_N_EXT_MACTX_PREFETCH_CV_DMA_E = 508 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 510 , - WIFI_N_EXT_MACTX_BF_PARAMS_UPDATE_PER_USER_E = 512 , - WIFI_N_EXT_PHYTX_CV_CORR_STATUS_E = 514 , - WIFI_N_EXT_PHYTX_CV_CORR_USER_E = 516 , - WIFI_N_EXT_MACTX_CV_CORR_MAC_INFO_GROUP_E = 518 , - WIFI_N_EXT_MACTX_RX_NOTIFICATION_FOR_PHY_E = 520 , - WIFI_N_EXT_MACTX_MU_UPLINK_COMMON_PER_BW_E = 522 , - WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT2_E = 524 , - WIFI_N_EXT_WSI_DIRECT_MESSAGE_E = 526 , - WIFI_N_EXT_MACTX_EMLSR_SWITCH_E = 528 , - WIFI_N_EXT_PHYTX_EMLSR_SWITCH_ACK_E = 530 , - WIFI_N_EXT_EAD_COMMAND_E = 532 , - WIFI_N_EXT_EAD_LEGACY_INTERRUPT_CONTROL_E = 534 , - WIFI_N_EXT_TPI_ENABLE_RESPONSE_TIMEOUT_E = 536 , - WIFI_N_EXT_TPI_LEGACY_INTERRUPT_CONTROL_E = 538 , - WIFI_N_EXT_TPI_MPDU_CONTINUATION_E = 540 , - WIFI_N_EXT_TPI_SEND_TLV_TO_PHYTX_E = 542 , - WIFI_N_EXT_TPI_STATUS_E = 544 , - WIFI_N_EXT_TPI_TIMESTAMP_STATUS_E = 546 , - WIFI_N_EXT_RPI_LEGACY_STATUS_CONTROL_E = 548 , - WIFI_N_EXT_RPI_STATUS_E = 550 , - WIFI_N_EXT_RPI_TIMESTAMP_STATUS_E = 552 , - WIFI_N_EXT_TCC_PUSH_TRANSMIT_COMMAND_E = 554 , - WIFI_N_EXT_TCC_LEGACY_STATUS_CONTROL_E = 556 , - WIFI_N_EXT_TCC_STATUS_E = 558 , - WIFI_N_EXT_TCC_TIMESTAMP_STATUS_E = 560 , - WIFI_N_EXT_TCC_SCHEDULER_CMD_E = 562 , - WIFI_N_EXT_RPI_NON_DATA_CTLV_44_FROM_PHYRX_E = 564 , - WIFI_N_EXT_RPI_FETCH_INFO_FROM_EXT_MEM_E = 566 , - WIFI_N_EXT_RPI_INIT_CBF_DATA_RESP_ADDR_E = 568 , - WIFI_N_EXT_TPI_SEND_CBF_DATA_TO_PHYTX_E = 570 , - WIFI_N_EXT_TCC_FES_END_MESSAGE_E = 572 , - WIFI_N_EXT_TPI_DISABLE_RESPONSE_TIMEOUT_E = 574 , - WIFI_N_EXT_EAD_MSDU_STATUS_START_E = 576 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_SU_E = 578 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_OFDMA_E = 580 , - WIFI_N_EXT_COEX_BLACKOUT_DETAILS_E = 582 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E = 584 , - WIFI_N_EXT_HDR_CTRL_PROT_MPDU_START_E = 586 , - WIFI_N_EXT_HDR_CTRL_PROT_MPDU_END_E = 588 , - WIFI_N_EXT_HDR_CTRL_PROT_PEER_INFO_E = 590 , - WIFI_N_EXT_MACTX_U_SIG_UHR_ELR_SU_E = 592 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_COBF_E = 594 , - WIFI_N_EXT_SPARE_REUSE_TAG_1_E = 596 , - WIFI_N_EXT_SPARE_REUSE_TAG_3_E = 598 , - WIFI_N_EXT_SPARE_REUSE_TAG_5_E = 600 , - WIFI_N_EXT_SPARE_REUSE_TAG_7_E = 602 , - WIFI_N_EXT_SPARE_REUSE_TAG_9_E = 604 , - WIFI_N_EXT_SPARE_REUSE_TAG_11_E = 606 , - WIFI_N_EXT_SPARE_REUSE_TAG_13_E = 608 , - WIFI_N_EXT_SPARE_REUSE_TAG_15_E = 610 , - WIFI_N_EXT_SPARE_REUSE_TAG_17_E = 612 , - WIFI_N_EXT_SPARE_REUSE_TAG_19_E = 614 , - WIFI_N_EXT_SPARE_REUSE_TAG_21_E = 616 , - WIFI_N_EXT_SPARE_REUSE_TAG_23_E = 618 , - WIFI_N_EXT_SPARE_REUSE_TAG_25_E = 620 , - WIFI_N_EXT_SPARE_REUSE_TAG_27_E = 622 , - WIFI_N_EXT_SPARE_REUSE_TAG_29_E = 624 , - WIFI_N_EXT_SPARE_REUSE_TAG_31_E = 626 , - WIFI_N_EXT_SPARE_REUSE_TAG_33_E = 628 , - WIFI_N_EXT_SPARE_REUSE_TAG_35_E = 630 , - WIFI_N_EXT_SPARE_REUSE_TAG_37_E = 632 , - WIFI_N_EXT_SPARE_REUSE_TAG_39_E = 634 , - WIFI_N_EXT_SPARE_REUSE_TAG_41_E = 636 , - WIFI_N_EXT_SPARE_REUSE_TAG_43_E = 638 , - WIFI_N_EXT_SPARE_REUSE_TAG_45_E = 640 , - WIFI_N_EXT_SPARE_REUSE_TAG_47_E = 642 , - WIFI_N_EXT_SPARE_REUSE_TAG_49_E = 644 , - WIFI_N_EXT_SPARE_REUSE_TAG_51_E = 646 , - WIFI_N_EXT_SPARE_REUSE_TAG_53_E = 648 , - WIFI_N_EXT_SPARE_REUSE_TAG_55_E = 650 , - WIFI_N_EXT_SPARE_REUSE_TAG_57_E = 652 , - WIFI_N_EXT_SPARE_REUSE_TAG_59_E = 654 , - WIFI_N_EXT_SPARE_REUSE_TAG_61_E = 656 , - WIFI_N_EXT_SPARE_REUSE_TAG_63_E = 658 , - WIFI_N_EXT_SPARE_REUSE_TAG_65_E = 660 , - WIFI_N_EXT_SPARE_REUSE_TAG_67_E = 662 , - WIFI_N_EXT_SPARE_REUSE_TAG_69_E = 664 , - WIFI_N_EXT_SPARE_REUSE_TAG_71_E = 666 , - WIFI_N_EXT_SPARE_REUSE_TAG_73_E = 668 , - WIFI_N_EXT_SPARE_REUSE_TAG_75_E = 670 , - WIFI_N_EXT_SPARE_REUSE_TAG_77_E = 672 , - WIFI_N_EXT_SPARE_REUSE_TAG_79_E = 674 , - WIFI_N_EXT_SPARE_REUSE_TAG_81_E = 676 , - WIFI_N_EXT_SPARE_REUSE_TAG_83_E = 678 , - WIFI_N_EXT_SPARE_REUSE_TAG_85_E = 680 , - WIFI_N_EXT_SPARE_REUSE_TAG_87_E = 682 , - WIFI_N_EXT_SPARE_REUSE_TAG_89_E = 684 , - WIFI_N_EXT_SPARE_REUSE_TAG_91_E = 686 , - WIFI_N_EXT_SPARE_REUSE_TAG_93_E = 688 , - WIFI_N_EXT_SPARE_REUSE_TAG_95_E = 690 , - WIFI_N_EXT_SPARE_REUSE_TAG_97_E = 692 , - WIFI_N_EXT_SPARE_REUSE_TAG_99_E = 694 , - WIFI_N_EXT_SPARE_REUSE_TAG_101_E = 696 , - WIFI_N_EXT_SPARE_REUSE_TAG_103_E = 698 , - WIFI_N_EXT_SPARE_REUSE_TAG_105_E = 700 , - WIFI_N_EXT_SPARE_REUSE_TAG_107_E = 702 , - WIFI_N_EXT_SPARE_REUSE_TAG_109_E = 704 , - WIFI_N_EXT_SPARE_REUSE_TAG_111_E = 706 , - WIFI_N_EXT_SPARE_REUSE_TAG_113_E = 708 , - WIFI_N_EXT_SPARE_REUSE_TAG_115_E = 710 , - WIFI_N_EXT_SPARE_REUSE_TAG_117_E = 712 , - WIFI_N_EXT_SPARE_REUSE_TAG_119_E = 714 , - WIFI_N_EXT_SPARE_REUSE_TAG_121_E = 716 , - WIFI_N_EXT_SPARE_REUSE_TAG_123_E = 718 , - WIFI_N_EXT_SPARE_REUSE_TAG_125_E = 720 , - WIFI_N_EXT_SPARE_REUSE_TAG_127_E = 722 , - WIFI_N_EXT_SPARE_REUSE_TAG_129_E = 724 , - WIFI_N_EXT_SPARE_REUSE_TAG_131_E = 726 , - WIFI_N_EXT_SPARE_REUSE_TAG_133_E = 728 , - WIFI_N_EXT_SPARE_REUSE_TAG_135_E = 730 , - WIFI_N_EXT_SPARE_REUSE_TAG_137_E = 732 , - WIFI_N_EXT_SPARE_REUSE_TAG_139_E = 734 , - WIFI_N_EXT_SPARE_REUSE_TAG_141_E = 736 , - WIFI_N_EXT_SPARE_REUSE_TAG_143_E = 738 , - WIFI_N_EXT_SPARE_REUSE_TAG_145_E = 740 , - WIFI_N_EXT_SPARE_REUSE_TAG_147_E = 742 , - WIFI_N_EXT_SPARE_REUSE_TAG_149_E = 744 , - WIFI_N_EXT_SPARE_REUSE_TAG_151_E = 746 , - WIFI_N_EXT_SPARE_REUSE_TAG_153_E = 748 , - WIFI_N_EXT_SPARE_REUSE_TAG_155_E = 750 , - WIFI_N_EXT_SPARE_REUSE_TAG_157_E = 752 , - WIFI_N_EXT_SPARE_REUSE_TAG_159_E = 754 , - WIFI_N_EXT_SPARE_REUSE_TAG_161_E = 756 , - WIFI_N_EXT_SPARE_REUSE_TAG_163_E = 758 , - WIFI_N_EXT_SPARE_REUSE_TAG_165_E = 760 , - WIFI_N_EXT_SPARE_REUSE_TAG_167_E = 762 , - WIFI_N_EXT_SPARE_REUSE_TAG_169_E = 764 , - WIFI_N_EXT_SPARE_REUSE_TAG_171_E = 766 , - WIFI_N_EXT_SPARE_REUSE_TAG_173_E = 768 , - WIFI_N_EXT_SPARE_REUSE_TAG_175_E = 770 , - WIFI_N_EXT_SPARE_REUSE_TAG_177_E = 772 , - WIFI_N_EXT_SPARE_REUSE_TAG_179_E = 774 , - WIFI_N_EXT_SPARE_REUSE_TAG_181_E = 776 , - WIFI_N_EXT_SPARE_REUSE_TAG_183_E = 778 , - WIFI_N_EXT_SPARE_REUSE_TAG_185_E = 780 , - WIFI_N_EXT_SPARE_REUSE_TAG_187_E = 782 , - WIFI_N_EXT_SPARE_REUSE_TAG_189_E = 784 , - WIFI_N_EXT_SPARE_REUSE_TAG_191_E = 786 , - WIFI_N_EXT_SPARE_REUSE_TAG_193_E = 788 , - WIFI_N_EXT_SPARE_REUSE_TAG_195_E = 790 , - WIFI_N_EXT_SPARE_REUSE_TAG_197_E = 792 , - WIFI_N_EXT_SPARE_REUSE_TAG_199_E = 794 , - WIFI_N_EXT_SPARE_REUSE_TAG_201_E = 796 , - WIFI_N_EXT_SPARE_REUSE_TAG_203_E = 798 , - WIFI_N_EXT_SPARE_REUSE_TAG_205_E = 800 , - WIFI_N_EXT_SPARE_REUSE_TAG_207_E = 802 , - WIFI_N_EXT_SPARE_REUSE_TAG_209_E = 804 , - WIFI_N_EXT_SPARE_REUSE_TAG_211_E = 806 , - WIFI_N_EXT_SPARE_REUSE_TAG_213_E = 808 , - WIFI_N_EXT_SPARE_REUSE_TAG_215_E = 810 , - WIFI_N_EXT_SPARE_REUSE_TAG_217_E = 812 , - WIFI_N_EXT_SPARE_REUSE_TAG_219_E = 814 , - WIFI_N_EXT_SPARE_REUSE_TAG_221_E = 816 , - WIFI_N_EXT_SPARE_REUSE_TAG_223_E = 818 , - WIFI_N_EXT_SPARE_REUSE_TAG_225_E = 820 , - WIFI_N_EXT_SPARE_REUSE_TAG_227_E = 822 , - WIFI_N_EXT_SPARE_REUSE_TAG_229_E = 824 , - WIFI_N_EXT_SPARE_REUSE_TAG_231_E = 826 , - WIFI_N_EXT_SPARE_REUSE_TAG_233_E = 828 , - WIFI_N_EXT_SPARE_REUSE_TAG_235_E = 830 , - WIFI_N_EXT_SPARE_REUSE_TAG_237_E = 832 , - WIFI_N_EXT_SPARE_REUSE_TAG_239_E = 834 , - WIFI_N_EXT_SPARE_REUSE_TAG_241_E = 836 , - WIFI_N_EXT_SPARE_REUSE_TAG_243_E = 838 , - WIFI_N_EXT_SPARE_REUSE_TAG_245_E = 840 , - WIFI_N_EXT_SPARE_REUSE_TAG_247_E = 842 , - WIFI_N_EXT_SPARE_REUSE_TAG_249_E = 844 , - WIFI_N_EXT_SPARE_REUSE_TAG_251_E = 846 , - WIFI_N_EXT_SPARE_REUSE_TAG_253_E = 848 , - WIFI_N_EXT_SPARE_REUSE_TAG_255_E = 850 , - WIFI_N_EXT_SPARE_REUSE_TAG_257_E = 852 , - WIFI_N_EXT_SPARE_REUSE_TAG_259_E = 854 , - WIFI_N_EXT_SPARE_REUSE_TAG_261_E = 856 , - WIFI_N_EXT_SPARE_REUSE_TAG_263_E = 858 , - WIFI_N_EXT_SPARE_REUSE_TAG_265_E = 860 , - WIFI_N_EXT_SPARE_REUSE_TAG_267_E = 862 , - WIFI_N_EXT_SPARE_REUSE_TAG_269_E = 864 , - WIFI_N_EXT_SPARE_REUSE_TAG_271_E = 866 , - WIFI_N_EXT_SPARE_REUSE_TAG_273_E = 868 , - WIFI_N_EXT_SPARE_REUSE_TAG_275_E = 870 , - WIFI_N_EXT_SPARE_REUSE_TAG_277_E = 872 , - WIFI_N_EXT_SPARE_REUSE_TAG_279_E = 874 , - WIFI_N_EXT_SPARE_REUSE_TAG_281_E = 876 , - WIFI_N_EXT_SPARE_REUSE_TAG_283_E = 878 , - WIFI_N_EXT_SPARE_REUSE_TAG_285_E = 880 , - WIFI_N_EXT_SPARE_REUSE_TAG_287_E = 882 , - WIFI_N_EXT_SPARE_REUSE_TAG_289_E = 884 , - WIFI_N_EXT_SPARE_REUSE_TAG_291_E = 886 , - WIFI_N_EXT_SPARE_REUSE_TAG_293_E = 888 , - WIFI_N_EXT_SPARE_REUSE_TAG_295_E = 890 , - WIFI_N_EXT_SPARE_REUSE_TAG_297_E = 892 , - WIFI_N_EXT_SPARE_REUSE_TAG_299_E = 894 , - WIFI_N_EXT_SPARE_REUSE_TAG_301_E = 896 , - WIFI_N_EXT_SPARE_REUSE_TAG_303_E = 898 , - WIFI_N_EXT_SPARE_REUSE_TAG_305_E = 900 , - WIFI_N_EXT_SPARE_REUSE_TAG_307_E = 902 , - WIFI_N_EXT_SPARE_REUSE_TAG_309_E = 904 , - WIFI_N_EXT_SPARE_REUSE_TAG_311_E = 906 , - WIFI_N_EXT_SPARE_REUSE_TAG_313_E = 908 , - WIFI_N_EXT_SPARE_REUSE_TAG_315_E = 910 , - WIFI_N_EXT_SPARE_REUSE_TAG_317_E = 912 , - WIFI_N_EXT_SPARE_REUSE_TAG_319_E = 914 , - WIFI_N_EXT_SPARE_REUSE_TAG_321_E = 916 , - WIFI_N_EXT_SPARE_REUSE_TAG_323_E = 918 , - WIFI_N_EXT_SPARE_REUSE_TAG_325_E = 920 , - WIFI_N_EXT_SPARE_REUSE_TAG_327_E = 922 , - WIFI_N_EXT_SPARE_REUSE_TAG_329_E = 924 , - WIFI_N_EXT_SPARE_REUSE_TAG_331_E = 926 , - WIFI_N_EXT_SPARE_REUSE_TAG_333_E = 928 , - WIFI_N_EXT_SPARE_REUSE_TAG_335_E = 930 , - WIFI_N_EXT_SPARE_REUSE_TAG_337_E = 932 , - WIFI_N_EXT_SPARE_REUSE_TAG_339_E = 934 , - WIFI_N_EXT_SPARE_REUSE_TAG_341_E = 936 , - WIFI_N_EXT_SPARE_REUSE_TAG_343_E = 938 , - WIFI_N_EXT_SPARE_REUSE_TAG_345_E = 940 , - WIFI_N_EXT_SPARE_REUSE_TAG_347_E = 942 , - WIFI_N_EXT_SPARE_REUSE_TAG_349_E = 944 , - WIFI_N_EXT_SPARE_REUSE_TAG_351_E = 946 , - WIFI_N_EXT_SPARE_REUSE_TAG_353_E = 948 , - WIFI_N_EXT_SPARE_REUSE_TAG_355_E = 950 , - WIFI_N_EXT_SPARE_REUSE_TAG_357_E = 952 , - WIFI_N_EXT_SPARE_REUSE_TAG_359_E = 954 , - WIFI_N_EXT_SPARE_REUSE_TAG_361_E = 956 , - WIFI_N_EXT_SPARE_REUSE_TAG_363_E = 958 , - WIFI_N_EXT_SPARE_REUSE_TAG_365_E = 960 , - WIFI_N_EXT_SPARE_REUSE_TAG_367_E = 962 , - WIFI_N_EXT_SPARE_REUSE_TAG_369_E = 964 , - WIFI_N_EXT_SPARE_REUSE_TAG_371_E = 966 , - WIFI_N_EXT_SPARE_REUSE_TAG_373_E = 968 , - WIFI_N_EXT_SPARE_REUSE_TAG_375_E = 970 , - WIFI_N_EXT_SPARE_REUSE_TAG_377_E = 972 , - WIFI_N_EXT_SPARE_REUSE_TAG_379_E = 974 , - WIFI_N_EXT_SPARE_REUSE_TAG_381_E = 976 , - WIFI_N_EXT_SPARE_REUSE_TAG_383_E = 978 , - WIFI_N_EXT_SPARE_REUSE_TAG_385_E = 980 , - WIFI_N_EXT_SPARE_REUSE_TAG_387_E = 982 , - WIFI_N_EXT_SPARE_REUSE_TAG_389_E = 984 , - WIFI_N_EXT_SPARE_REUSE_TAG_391_E = 986 , - WIFI_N_EXT_SPARE_REUSE_TAG_393_E = 988 , - WIFI_N_EXT_SPARE_REUSE_TAG_395_E = 990 , - WIFI_N_EXT_SPARE_REUSE_TAG_397_E = 992 , - WIFI_N_EXT_SPARE_REUSE_TAG_399_E = 994 , - WIFI_N_EXT_SPARE_REUSE_TAG_401_E = 996 , - WIFI_N_EXT_SPARE_REUSE_TAG_403_E = 998 , - WIFI_N_EXT_SPARE_REUSE_TAG_405_E = 1000 , - WIFI_N_EXT_SPARE_REUSE_TAG_407_E = 1002 , - WIFI_N_EXT_SPARE_REUSE_TAG_409_E = 1004 , - WIFI_N_EXT_SPARE_REUSE_TAG_411_E = 1006 , - WIFI_N_EXT_SPARE_REUSE_TAG_413_E = 1008 , - WIFI_N_EXT_SPARE_REUSE_TAG_415_E = 1010 , - WIFI_N_EXT_SPARE_REUSE_TAG_417_E = 1012 , - WIFI_N_EXT_SPARE_REUSE_TAG_419_E = 1014 , - WIFI_N_EXT_SPARE_REUSE_TAG_421_E = 1016 , - WIFI_N_EXT_SPARE_REUSE_TAG_423_E = 1018 , - WIFI_N_EXT_SPARE_REUSE_TAG_425_E = 1020 -} non_ext_tlv_tag_def__e; - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tqm2sw_completion_ring.h b/drivers/staging/fw-api/hw/fig/v1/tqm2sw_completion_ring.h deleted file mode 100644 index f67deea1f6a1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tqm2sw_completion_ring.h +++ /dev/null @@ -1,262 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TQM2SW_COMPLETION_RING_H_ -#define _TQM2SW_COMPLETION_RING_H_ - -#include "tx_rate_stats_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_TQM2SW_COMPLETION_RING 8 - -struct tqm2sw_completion_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_desc_virt_addr_or_addr_info; - uint32_t release_source_module : 3, - cache_id : 1, - reserved_2a : 2, - buffer_or_desc_type : 3, - return_buffer_manager : 4, - tqm_release_reason : 4, - rbm_override_valid : 1, - sw_buffer_cookie_11_0 : 12, - cookie_conversion_status : 1, - tqm_completion_error : 1; - uint32_t tqm_status_number : 24, - transmit_count : 7, - sw_release_details_valid : 1; - uint32_t ack_frame_rssi : 8, - first_msdu : 1, - last_msdu : 1, - fw_tx_notify_frame : 3, - buffer_timestamp : 19; - struct tx_rate_stats_info tx_rate_stats; - uint32_t sw_peer_id : 16, - tid : 4, - sw_buffer_cookie_19_12 : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_desc_virt_addr_or_addr_info; - uint32_t tqm_completion_error : 1, - cookie_conversion_status : 1, - sw_buffer_cookie_11_0 : 12, - rbm_override_valid : 1, - tqm_release_reason : 4, - return_buffer_manager : 4, - buffer_or_desc_type : 3, - reserved_2a : 2, - cache_id : 1, - release_source_module : 3; - uint32_t sw_release_details_valid : 1, - transmit_count : 7, - tqm_status_number : 24; - uint32_t buffer_timestamp : 19, - fw_tx_notify_frame : 3, - last_msdu : 1, - first_msdu : 1, - ack_frame_rssi : 8; - struct tx_rate_stats_info tx_rate_stats; - uint32_t looping_count : 4, - sw_buffer_cookie_19_12 : 8, - tid : 4, - sw_peer_id : 16; -#endif -}; - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define TQM2SW_COMPLETION_RING_CACHE_ID_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_CACHE_ID_LSB 3 -#define TQM2SW_COMPLETION_RING_CACHE_ID_MSB 3 -#define TQM2SW_COMPLETION_RING_CACHE_ID_MASK 0x00000008 - -#define TQM2SW_COMPLETION_RING_RESERVED_2A_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_LSB 4 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_MSB 5 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_MASK 0x00000030 - -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_LSB 6 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MSB 8 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_LSB 9 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MSB 12 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MASK 0x00001e00 - -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_LSB 13 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MSB 16 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MASK 0x0001e000 - -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_LSB 17 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MSB 17 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MASK 0x00020000 - -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_LSB 18 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MSB 29 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 - -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_LSB 30 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MSB 30 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MASK 0x40000000 - -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_LSB 31 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MSB 31 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MASK 0x80000000 - -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_LSB 0 -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MSB 23 -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MASK 0x00ffffff - -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_LSB 24 -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MSB 30 -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MASK 0x7f000000 - -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_LSB 31 -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MSB 31 -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 - -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_LSB 0 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MSB 7 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MASK 0x000000ff - -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_LSB 8 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MSB 8 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MASK 0x00000100 - -#define TQM2SW_COMPLETION_RING_LAST_MSDU_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_LSB 9 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_MSB 9 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_MASK 0x00000200 - -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_LSB 10 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MSB 12 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 - -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_LSB 13 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MSB 31 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MASK 0xffffe000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_LSB 1 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MSB 3 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MSB 16 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0001f000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_LSB 17 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MSB 19 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MASK 0x000e0000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 20 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 20 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00100000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_LSB 21 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MSB 24 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MASK 0x01e00000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_LSB 25 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MSB 28 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MASK 0x1e000000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff - -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_LSB 0 -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MSB 15 -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MASK 0x0000ffff - -#define TQM2SW_COMPLETION_RING_TID_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_TID_LSB 16 -#define TQM2SW_COMPLETION_RING_TID_MSB 19 -#define TQM2SW_COMPLETION_RING_TID_MASK 0x000f0000 - -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_LSB 20 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MSB 27 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 - -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_LSB 28 -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MSB 31 -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_cbf_info.h b/drivers/staging/fw-api/hw/fig/v1/tx_cbf_info.h deleted file mode 100644 index fed064ce95a8..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_cbf_info.h +++ /dev/null @@ -1,454 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_CBF_INFO_H_ -#define _TX_CBF_INFO_H_ - -#define NUM_OF_DWORDS_TX_CBF_INFO 16 - -#define NUM_OF_QWORDS_TX_CBF_INFO 8 - -struct tx_cbf_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sw_peer_id : 16, - pre_cbf_duration : 16; - uint32_t brpoll_info_valid : 1, - trigger_brpoll_info_valid : 1, - npda_info_11ac_valid : 1, - npda_info_11ax_valid : 1, - dot11ax_su_extended : 1, - bandwidth : 3, - brpoll_info : 8, - cbf_response_table_base_index : 8, - peer_index : 3, - pkt_type : 4, - txop_duration_all_ones : 1; - uint32_t trigger_brpoll_common_info_15_0 : 16, - trigger_brpoll_common_info_31_16 : 16; - uint32_t trigger_brpoll_user_info_15_0 : 16, - trigger_brpoll_user_info_31_16 : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t addr3_47_32 : 16, - sta_partial_aid : 11, - __reserved_g_0035 : 1, - reserved_8a : 3, - cbf_resp_pwr_mgmt : 1; - uint32_t group_id : 6, - rssi_comb : 8, - reserved_9a : 2, - vht_ndpa_sta_info : 16; - uint32_t he_eht_sta_info_15_0 : 16, - he_eht_sta_info_31_16 : 16; - uint32_t dot11ax_received_format_indication : 1, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_bss_color_id : 6, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_cp_size : 2, - dot11ax_received_ltf_size : 2, - dot11ax_received_coding : 1, - dot11ax_received_dcm : 1, - dot11ax_received_doppler_indication : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_dl_ul_flag : 1, - reserved_11a : 8; - uint32_t sw_response_frame_length : 16, - sw_response_tlv_from_crypto : 1, - wait_sifs_config_valid : 1, - wait_sifs : 2, - __reserved_g_0022 : 1, - secure : 1, - tb___reserved_g_0022_response_required : 2, - emlsr_main_tlv_if : 1, - reserved_12a : 1, - u_sig_puncture_pattern_encoding : 6; - uint32_t dot11be_puncture_bitmap : 16, - dot11be_response : 1, - punctured_response : 1, - npda_info_11be_valid : 1, - eht_duplicate_mode : 2, - reserved_13a : 11; - uint32_t eht_sta_info_39_32 : 8, - unassociated___reserved_g_0022_peer : 1, - reserved_14a : 23; - uint32_t tlv64_padding : 32; -#else - uint32_t pre_cbf_duration : 16, - sw_peer_id : 16; - uint32_t txop_duration_all_ones : 1, - pkt_type : 4, - peer_index : 3, - cbf_response_table_base_index : 8, - brpoll_info : 8, - bandwidth : 3, - dot11ax_su_extended : 1, - npda_info_11ax_valid : 1, - npda_info_11ac_valid : 1, - trigger_brpoll_info_valid : 1, - brpoll_info_valid : 1; - uint32_t trigger_brpoll_common_info_31_16 : 16, - trigger_brpoll_common_info_15_0 : 16; - uint32_t trigger_brpoll_user_info_31_16 : 16, - trigger_brpoll_user_info_15_0 : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t cbf_resp_pwr_mgmt : 1, - reserved_8a : 3, - __reserved_g_0035 : 1, - sta_partial_aid : 11, - addr3_47_32 : 16; - uint32_t vht_ndpa_sta_info : 16, - reserved_9a : 2, - rssi_comb : 8, - group_id : 6; - uint32_t he_eht_sta_info_31_16 : 16, - he_eht_sta_info_15_0 : 16; - uint32_t reserved_11a : 8, - dot11ax_dl_ul_flag : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_received_doppler_indication : 1, - dot11ax_received_dcm : 1, - dot11ax_received_coding : 1, - dot11ax_received_ltf_size : 2, - dot11ax_received_cp_size : 2, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_bss_color_id : 6, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_format_indication : 1; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_12a : 1, - emlsr_main_tlv_if : 1, - tb___reserved_g_0022_response_required : 2, - secure : 1, - __reserved_g_0022 : 1, - wait_sifs : 2, - wait_sifs_config_valid : 1, - sw_response_tlv_from_crypto : 1, - sw_response_frame_length : 16; - uint32_t reserved_13a : 11, - eht_duplicate_mode : 2, - npda_info_11be_valid : 1, - punctured_response : 1, - dot11be_response : 1, - dot11be_puncture_bitmap : 16; - uint32_t reserved_14a : 23, - unassociated___reserved_g_0022_peer : 1, - eht_sta_info_39_32 : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_CBF_INFO_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_SW_PEER_ID_LSB 0 -#define TX_CBF_INFO_SW_PEER_ID_MSB 15 -#define TX_CBF_INFO_SW_PEER_ID_MASK 0x000000000000ffff - -#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PRE_CBF_DURATION_LSB 16 -#define TX_CBF_INFO_PRE_CBF_DURATION_MSB 31 -#define TX_CBF_INFO_PRE_CBF_DURATION_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB 32 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB 32 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK 0x0000000100000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB 33 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB 33 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK 0x0000000200000000 - -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB 34 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB 34 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK 0x0000000400000000 - -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB 35 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB 35 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK 0x0000000800000000 - -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB 36 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB 36 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000001000000000 - -#define TX_CBF_INFO_BANDWIDTH_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BANDWIDTH_LSB 37 -#define TX_CBF_INFO_BANDWIDTH_MSB 39 -#define TX_CBF_INFO_BANDWIDTH_MASK 0x000000e000000000 - -#define TX_CBF_INFO_BRPOLL_INFO_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BRPOLL_INFO_LSB 40 -#define TX_CBF_INFO_BRPOLL_INFO_MSB 47 -#define TX_CBF_INFO_BRPOLL_INFO_MASK 0x0000ff0000000000 - -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB 48 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB 55 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK 0x00ff000000000000 - -#define TX_CBF_INFO_PEER_INDEX_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PEER_INDEX_LSB 56 -#define TX_CBF_INFO_PEER_INDEX_MSB 58 -#define TX_CBF_INFO_PEER_INDEX_MASK 0x0700000000000000 - -#define TX_CBF_INFO_PKT_TYPE_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PKT_TYPE_LSB 59 -#define TX_CBF_INFO_PKT_TYPE_MSB 62 -#define TX_CBF_INFO_PKT_TYPE_MASK 0x7800000000000000 - -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB 63 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB 63 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB 0 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB 15 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK 0x000000000000ffff - -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB 16 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB 31 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB 32 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB 47 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB 48 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB 63 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK 0xffff000000000000 - -#define TX_CBF_INFO_ADDR1_31_0_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR1_31_0_LSB 0 -#define TX_CBF_INFO_ADDR1_31_0_MSB 31 -#define TX_CBF_INFO_ADDR1_31_0_MASK 0x00000000ffffffff - -#define TX_CBF_INFO_ADDR1_47_32_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR1_47_32_LSB 32 -#define TX_CBF_INFO_ADDR1_47_32_MSB 47 -#define TX_CBF_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_ADDR2_15_0_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR2_15_0_LSB 48 -#define TX_CBF_INFO_ADDR2_15_0_MSB 63 -#define TX_CBF_INFO_ADDR2_15_0_MASK 0xffff000000000000 - -#define TX_CBF_INFO_ADDR2_47_16_OFFSET 0x0000000000000018 -#define TX_CBF_INFO_ADDR2_47_16_LSB 0 -#define TX_CBF_INFO_ADDR2_47_16_MSB 31 -#define TX_CBF_INFO_ADDR2_47_16_MASK 0x00000000ffffffff - -#define TX_CBF_INFO_ADDR3_31_0_OFFSET 0x0000000000000018 -#define TX_CBF_INFO_ADDR3_31_0_LSB 32 -#define TX_CBF_INFO_ADDR3_31_0_MSB 63 -#define TX_CBF_INFO_ADDR3_31_0_MASK 0xffffffff00000000 - -#define TX_CBF_INFO_ADDR3_47_32_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_ADDR3_47_32_LSB 0 -#define TX_CBF_INFO_ADDR3_47_32_MSB 15 -#define TX_CBF_INFO_ADDR3_47_32_MASK 0x000000000000ffff - -#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_STA_PARTIAL_AID_LSB 16 -#define TX_CBF_INFO_STA_PARTIAL_AID_MSB 26 -#define TX_CBF_INFO_STA_PARTIAL_AID_MASK 0x0000000007ff0000 - -#define TX_CBF_INFO_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RESERVED_8A_LSB 28 -#define TX_CBF_INFO_RESERVED_8A_MSB 30 -#define TX_CBF_INFO_RESERVED_8A_MASK 0x0000000070000000 - -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB 31 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB 31 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK 0x0000000080000000 - -#define TX_CBF_INFO_GROUP_ID_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_GROUP_ID_LSB 32 -#define TX_CBF_INFO_GROUP_ID_MSB 37 -#define TX_CBF_INFO_GROUP_ID_MASK 0x0000003f00000000 - -#define TX_CBF_INFO_RSSI_COMB_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RSSI_COMB_LSB 38 -#define TX_CBF_INFO_RSSI_COMB_MSB 45 -#define TX_CBF_INFO_RSSI_COMB_MASK 0x00003fc000000000 - -#define TX_CBF_INFO_RESERVED_9A_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RESERVED_9A_LSB 46 -#define TX_CBF_INFO_RESERVED_9A_MSB 47 -#define TX_CBF_INFO_RESERVED_9A_MASK 0x0000c00000000000 - -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB 48 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB 63 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK 0xffff000000000000 - -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB 0 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB 15 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK 0x000000000000ffff - -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB 16 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB 31 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB 48 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB 48 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB 49 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB 49 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 - -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB 55 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB 55 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0080000000000000 - -#define TX_CBF_INFO_RESERVED_11A_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_RESERVED_11A_LSB 56 -#define TX_CBF_INFO_RESERVED_11A_MSB 63 -#define TX_CBF_INFO_RESERVED_11A_MASK 0xff00000000000000 - -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x000000000000ffff - -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 16 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 16 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000000010000 - -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB 17 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB 17 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000000020000 - -#define TX_CBF_INFO_WAIT_SIFS_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_WAIT_SIFS_LSB 18 -#define TX_CBF_INFO_WAIT_SIFS_MSB 19 -#define TX_CBF_INFO_WAIT_SIFS_MASK 0x00000000000c0000 - -#define TX_CBF_INFO_SECURE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SECURE_LSB 21 -#define TX_CBF_INFO_SECURE_MSB 21 -#define TX_CBF_INFO_SECURE_MASK 0x0000000000200000 - -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_LSB 24 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MSB 24 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MASK 0x0000000001000000 - -#define TX_CBF_INFO_RESERVED_12A_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_RESERVED_12A_LSB 25 -#define TX_CBF_INFO_RESERVED_12A_MSB 25 -#define TX_CBF_INFO_RESERVED_12A_MASK 0x0000000002000000 - -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB 48 -#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB 48 -#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 - -#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB 49 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB 49 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 - -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB 50 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB 50 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK 0x0004000000000000 - -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB 51 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB 52 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK 0x0018000000000000 - -#define TX_CBF_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_RESERVED_13A_LSB 53 -#define TX_CBF_INFO_RESERVED_13A_MSB 63 -#define TX_CBF_INFO_RESERVED_13A_MASK 0xffe0000000000000 - -#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB 0 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB 7 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK 0x00000000000000ff - -#define TX_CBF_INFO_RESERVED_14A_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_RESERVED_14A_LSB 9 -#define TX_CBF_INFO_RESERVED_14A_MSB 31 -#define TX_CBF_INFO_RESERVED_14A_MASK 0x00000000fffffe00 - -#define TX_CBF_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_TLV64_PADDING_LSB 32 -#define TX_CBF_INFO_TLV64_PADDING_MSB 63 -#define TX_CBF_INFO_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_setup.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_setup.h deleted file mode 100644 index 24151f70fecd..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_setup.h +++ /dev/null @@ -1,550 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_SETUP_H_ -#define _TX_FES_SETUP_H_ - -#define NUM_OF_DWORDS_TX_FES_SETUP 10 - -#define NUM_OF_QWORDS_TX_FES_SETUP 5 - -struct tx_fes_setup { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t schedule_id : 32; - uint32_t fes_in_11ax_trigger_response_config : 1, - bo_based_tid_aggregation_limit : 4, - __reserved_g_0022 : 1, - expect_i2r_lmr : 1, - transmit_start_reason : 3, - use_alt_power_sr : 1, - static_2_pwr_mode_status : 1, - obss_srg_opport_transmit_status : 1, - srp_based_transmit_status : 1, - obss_pd_based_transmit_status : 1, - puncture_from_all_allowed_modes : 1, - schedule_cmd_ring_id : 5, - fes_control_mode : 2, - number_of_users : 6, - mu_type : 1, - ofdma_triggered_response : 1, - response_to_response_cmd : 1; - uint32_t schedule_try : 4, - reserved_2a : 1, - subband_antenna_selection_en : 1, - txbf : 1, - allow_txop_exceed_in_1st_pkt : 1, - ignore_bw_available : 1, - ignore_tbtt : 1, - static_bandwidth : 3, - set_txop_duration_all_ones : 1, - transmission_contains_mu_rts : 1, - bw_restricted_frames_embedded : 1, - ast_index : 16; - uint32_t cv_id : 8, - trigger_resp_txpdu_ppdu_boundary : 2, - rxpcu_setup_complete_present : 1, - rbo_must_have_data_user_limit : 4, - mu_ndp : 1, - bf_type : 2, - cbf_nc_index_mask : 1, - cbf_nc_index : 3, - cbf_nr_index_mask : 1, - cbf_nr_index : 3, - secure___reserved_g_0022_ista : 1, - ndpa : 1, - wait_sifs : 2, - cbf_feedback_type_mask : 1, - cbf_feedback_type : 1; - uint32_t cbf_sounding_token : 6, - cbf_sounding_token_mask : 1, - cbf_bw_mask : 1, - cbf_bw : 3, - use_static_bw : 1, - coex_nack_count : 5, - sch_tx_burst_ongoing : 1, - gen_tqm_update_mpdu_count_tlv : 1, - rts_tx_over___reserved_g_0016 : 1, - ndp_frame : 3, - optimal_bw_retry_count : 4, - fes_continuation_ratio_threshold : 5; - uint32_t transmit_cca_bitmap : 32; - uint32_t tb___reserved_g_0022 : 1, - __reserved_g_0022_trigger_subtype : 4, - min_cts2self_count : 4, - max_cts2self_count : 4, - wifi_radar_enable : 1, - reserved_6a : 1, - wait_for_chksum_done : 1, - txrx_self_test_enable : 1, - rtt_self_cal_enable : 1, - secure___reserved_g_0022_rsta : 1, - hip_edca_prot_enable : 1, - hip_edca_prot_required : 1, - hip_edca_mini_contention_gap : 8, - last_command_in_burst : 1, - retain_peer_blackout_details : 1, - enable_hw_qos_null : 1; - uint32_t monitor_override_sta_31_0 : 32; - uint32_t monitor_override_sta_36_32 : 5, - enable_qos_null_switch_for_eosp : 1, - __reserved_g_0035 : 1, - secure___reserved_g_0035_smr : 1, - __reserved_g_0035_type : 2, - __reserved_g_0035_trigger_subtype : 4, - reserved_8a : 18; - uint32_t fw2sw_info : 32; -#else - uint32_t schedule_id : 32; - uint32_t response_to_response_cmd : 1, - ofdma_triggered_response : 1, - mu_type : 1, - number_of_users : 6, - fes_control_mode : 2, - schedule_cmd_ring_id : 5, - puncture_from_all_allowed_modes : 1, - obss_pd_based_transmit_status : 1, - srp_based_transmit_status : 1, - obss_srg_opport_transmit_status : 1, - static_2_pwr_mode_status : 1, - use_alt_power_sr : 1, - transmit_start_reason : 3, - expect_i2r_lmr : 1, - __reserved_g_0022 : 1, - bo_based_tid_aggregation_limit : 4, - fes_in_11ax_trigger_response_config : 1; - uint32_t ast_index : 16, - bw_restricted_frames_embedded : 1, - transmission_contains_mu_rts : 1, - set_txop_duration_all_ones : 1, - static_bandwidth : 3, - ignore_tbtt : 1, - ignore_bw_available : 1, - allow_txop_exceed_in_1st_pkt : 1, - txbf : 1, - subband_antenna_selection_en : 1, - reserved_2a : 1, - schedule_try : 4; - uint32_t cbf_feedback_type : 1, - cbf_feedback_type_mask : 1, - wait_sifs : 2, - ndpa : 1, - secure___reserved_g_0022_ista : 1, - cbf_nr_index : 3, - cbf_nr_index_mask : 1, - cbf_nc_index : 3, - cbf_nc_index_mask : 1, - bf_type : 2, - mu_ndp : 1, - rbo_must_have_data_user_limit : 4, - rxpcu_setup_complete_present : 1, - trigger_resp_txpdu_ppdu_boundary : 2, - cv_id : 8; - uint32_t fes_continuation_ratio_threshold : 5, - optimal_bw_retry_count : 4, - ndp_frame : 3, - rts_tx_over___reserved_g_0016 : 1, - gen_tqm_update_mpdu_count_tlv : 1, - sch_tx_burst_ongoing : 1, - coex_nack_count : 5, - use_static_bw : 1, - cbf_bw : 3, - cbf_bw_mask : 1, - cbf_sounding_token_mask : 1, - cbf_sounding_token : 6; - uint32_t transmit_cca_bitmap : 32; - uint32_t enable_hw_qos_null : 1, - retain_peer_blackout_details : 1, - last_command_in_burst : 1, - hip_edca_mini_contention_gap : 8, - hip_edca_prot_required : 1, - hip_edca_prot_enable : 1, - secure___reserved_g_0022_rsta : 1, - rtt_self_cal_enable : 1, - txrx_self_test_enable : 1, - wait_for_chksum_done : 1, - reserved_6a : 1, - wifi_radar_enable : 1, - max_cts2self_count : 4, - min_cts2self_count : 4, - __reserved_g_0022_trigger_subtype : 4, - tb___reserved_g_0022 : 1; - uint32_t monitor_override_sta_31_0 : 32; - uint32_t reserved_8a : 18, - __reserved_g_0035_trigger_subtype : 4, - __reserved_g_0035_type : 2, - secure___reserved_g_0035_smr : 1, - __reserved_g_0035 : 1, - enable_qos_null_switch_for_eosp : 1, - monitor_override_sta_36_32 : 5; - uint32_t fw2sw_info : 32; -#endif -}; - -#define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SCHEDULE_ID_LSB 0 -#define TX_FES_SETUP_SCHEDULE_ID_MSB 31 -#define TX_FES_SETUP_SCHEDULE_ID_MASK 0x00000000ffffffff - -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 32 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 32 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x0000000100000000 - -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 33 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 36 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e00000000 - -#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 38 -#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 38 -#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x0000004000000000 - -#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 39 -#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 41 -#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x0000038000000000 - -#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 42 -#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 42 -#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x0000040000000000 - -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 43 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 43 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x0000080000000000 - -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 44 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 44 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000100000000000 - -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 45 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 45 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000200000000000 - -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 46 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 46 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000400000000000 - -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 47 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 47 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x0000800000000000 - -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 48 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 52 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 - -#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_FES_CONTROL_MODE_LSB 53 -#define TX_FES_SETUP_FES_CONTROL_MODE_MSB 54 -#define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x0060000000000000 - -#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_NUMBER_OF_USERS_LSB 55 -#define TX_FES_SETUP_NUMBER_OF_USERS_MSB 60 -#define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f80000000000000 - -#define TX_FES_SETUP_MU_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_MU_TYPE_LSB 61 -#define TX_FES_SETUP_MU_TYPE_MSB 61 -#define TX_FES_SETUP_MU_TYPE_MASK 0x2000000000000000 - -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 62 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 62 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x4000000000000000 - -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 63 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 63 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x8000000000000000 - -#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 -#define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 -#define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x000000000000000f - -#define TX_FES_SETUP_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RESERVED_2A_LSB 4 -#define TX_FES_SETUP_RESERVED_2A_MSB 4 -#define TX_FES_SETUP_RESERVED_2A_MASK 0x0000000000000010 - -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_LSB 5 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MSB 5 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MASK 0x0000000000000020 - -#define TX_FES_SETUP_TXBF_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TXBF_LSB 6 -#define TX_FES_SETUP_TXBF_MSB 6 -#define TX_FES_SETUP_TXBF_MASK 0x0000000000000040 - -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x0000000000000080 - -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x0000000000000100 - -#define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_IGNORE_TBTT_LSB 9 -#define TX_FES_SETUP_IGNORE_TBTT_MSB 9 -#define TX_FES_SETUP_IGNORE_TBTT_MASK 0x0000000000000200 - -#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 -#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 -#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x0000000000001c00 - -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x0000000000002000 - -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x0000000000004000 - -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x0000000000008000 - -#define TX_FES_SETUP_AST_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_AST_INDEX_LSB 16 -#define TX_FES_SETUP_AST_INDEX_MSB 31 -#define TX_FES_SETUP_AST_INDEX_MASK 0x00000000ffff0000 - -#define TX_FES_SETUP_CV_ID_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CV_ID_LSB 32 -#define TX_FES_SETUP_CV_ID_MSB 39 -#define TX_FES_SETUP_CV_ID_MASK 0x000000ff00000000 - -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 40 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 41 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x0000030000000000 - -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 42 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 42 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x0000040000000000 - -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 43 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 46 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x0000780000000000 - -#define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_MU_NDP_LSB 47 -#define TX_FES_SETUP_MU_NDP_MSB 47 -#define TX_FES_SETUP_MU_NDP_MASK 0x0000800000000000 - -#define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_BF_TYPE_LSB 48 -#define TX_FES_SETUP_BF_TYPE_MSB 49 -#define TX_FES_SETUP_BF_TYPE_MASK 0x0003000000000000 - -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 50 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 50 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x0004000000000000 - -#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NC_INDEX_LSB 51 -#define TX_FES_SETUP_CBF_NC_INDEX_MSB 53 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x0038000000000000 - -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 54 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 54 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x0040000000000000 - -#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NR_INDEX_LSB 55 -#define TX_FES_SETUP_CBF_NR_INDEX_MSB 57 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x0380000000000000 - -#define TX_FES_SETUP_NDPA_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_NDPA_LSB 59 -#define TX_FES_SETUP_NDPA_MSB 59 -#define TX_FES_SETUP_NDPA_MASK 0x0800000000000000 - -#define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_WAIT_SIFS_LSB 60 -#define TX_FES_SETUP_WAIT_SIFS_MSB 61 -#define TX_FES_SETUP_WAIT_SIFS_MASK 0x3000000000000000 - -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 62 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 62 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x4000000000000000 - -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 63 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 63 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x8000000000000000 - -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x000000000000003f - -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x0000000000000040 - -#define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_BW_MASK_LSB 7 -#define TX_FES_SETUP_CBF_BW_MASK_MSB 7 -#define TX_FES_SETUP_CBF_BW_MASK_MASK 0x0000000000000080 - -#define TX_FES_SETUP_CBF_BW_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_BW_LSB 8 -#define TX_FES_SETUP_CBF_BW_MSB 10 -#define TX_FES_SETUP_CBF_BW_MASK 0x0000000000000700 - -#define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_USE_STATIC_BW_LSB 11 -#define TX_FES_SETUP_USE_STATIC_BW_MSB 11 -#define TX_FES_SETUP_USE_STATIC_BW_MASK 0x0000000000000800 - -#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 -#define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 -#define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x000000000001f000 - -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x0000000000020000 - -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x0000000000040000 - -#define TX_FES_SETUP_NDP_FRAME_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_NDP_FRAME_LSB 20 -#define TX_FES_SETUP_NDP_FRAME_MSB 22 -#define TX_FES_SETUP_NDP_FRAME_MASK 0x0000000000700000 - -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x0000000007800000 - -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0x00000000f8000000 - -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 32 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 63 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff00000000 - -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x00000000000001e0 - -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x0000000000001e00 - -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x0000000000002000 - -#define TX_FES_SETUP_RESERVED_6A_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RESERVED_6A_LSB 14 -#define TX_FES_SETUP_RESERVED_6A_MSB 14 -#define TX_FES_SETUP_RESERVED_6A_MASK 0x0000000000004000 - -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_LSB 15 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MSB 15 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MASK 0x0000000000008000 - -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_LSB 16 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MSB 16 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MASK 0x0000000000010000 - -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_LSB 17 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MSB 17 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MASK 0x0000000000020000 - -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_LSB 19 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MSB 19 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MASK 0x0000000000080000 - -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_LSB 20 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MSB 20 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MASK 0x0000000000100000 - -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_LSB 21 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MSB 28 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MASK 0x000000001fe00000 - -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_LSB 29 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MSB 29 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MASK 0x0000000020000000 - -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_LSB 30 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MSB 30 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MASK 0x0000000040000000 - -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_LSB 31 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MSB 31 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MASK 0x0000000080000000 - -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 32 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 63 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff00000000 - -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x000000000000001f - -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_LSB 5 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MSB 5 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MASK 0x0000000000000020 - -#define TX_FES_SETUP_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_RESERVED_8A_LSB 14 -#define TX_FES_SETUP_RESERVED_8A_MSB 31 -#define TX_FES_SETUP_RESERVED_8A_MASK 0x00000000ffffc000 - -#define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_FW2SW_INFO_LSB 32 -#define TX_FES_SETUP_FW2SW_INFO_MSB 63 -#define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_1k_ba.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_1k_ba.h deleted file mode 100644 index 4409dc03ac03..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_1k_ba.h +++ /dev/null @@ -1,313 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_1K_BA_H_ -#define _TX_FES_STATUS_1K_BA_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 - -#define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17 - -struct tx_fes_status_1k_ba { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ack_ba_status_type : 1, - ba_type : 1, - ba_tid : 4, - unexpected_ack_or_ba : 1, - response_timeout : 1, - ack_frame_rssi : 8, - ssn : 12, - reserved_0b : 4; - uint32_t sw_peer_id : 16, - reserved_1a : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; - uint32_t ba_bitmap_287_256 : 32; - uint32_t ba_bitmap_319_288 : 32; - uint32_t ba_bitmap_351_320 : 32; - uint32_t ba_bitmap_383_352 : 32; - uint32_t ba_bitmap_415_384 : 32; - uint32_t ba_bitmap_447_416 : 32; - uint32_t ba_bitmap_479_448 : 32; - uint32_t ba_bitmap_511_480 : 32; - uint32_t ba_bitmap_543_512 : 32; - uint32_t ba_bitmap_575_544 : 32; - uint32_t ba_bitmap_607_576 : 32; - uint32_t ba_bitmap_639_608 : 32; - uint32_t ba_bitmap_671_640 : 32; - uint32_t ba_bitmap_703_672 : 32; - uint32_t ba_bitmap_735_704 : 32; - uint32_t ba_bitmap_767_736 : 32; - uint32_t ba_bitmap_799_768 : 32; - uint32_t ba_bitmap_831_800 : 32; - uint32_t ba_bitmap_863_832 : 32; - uint32_t ba_bitmap_895_864 : 32; - uint32_t ba_bitmap_927_896 : 32; - uint32_t ba_bitmap_959_928 : 32; - uint32_t ba_bitmap_991_960 : 32; - uint32_t ba_bitmap_1023_992 : 32; -#else - uint32_t reserved_0b : 4, - ssn : 12, - ack_frame_rssi : 8, - response_timeout : 1, - unexpected_ack_or_ba : 1, - ba_tid : 4, - ba_type : 1, - ack_ba_status_type : 1; - uint32_t reserved_1a : 16, - sw_peer_id : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; - uint32_t ba_bitmap_287_256 : 32; - uint32_t ba_bitmap_319_288 : 32; - uint32_t ba_bitmap_351_320 : 32; - uint32_t ba_bitmap_383_352 : 32; - uint32_t ba_bitmap_415_384 : 32; - uint32_t ba_bitmap_447_416 : 32; - uint32_t ba_bitmap_479_448 : 32; - uint32_t ba_bitmap_511_480 : 32; - uint32_t ba_bitmap_543_512 : 32; - uint32_t ba_bitmap_575_544 : 32; - uint32_t ba_bitmap_607_576 : 32; - uint32_t ba_bitmap_639_608 : 32; - uint32_t ba_bitmap_671_640 : 32; - uint32_t ba_bitmap_703_672 : 32; - uint32_t ba_bitmap_735_704 : 32; - uint32_t ba_bitmap_767_736 : 32; - uint32_t ba_bitmap_799_768 : 32; - uint32_t ba_bitmap_831_800 : 32; - uint32_t ba_bitmap_863_832 : 32; - uint32_t ba_bitmap_895_864 : 32; - uint32_t ba_bitmap_927_896 : 32; - uint32_t ba_bitmap_959_928 : 32; - uint32_t ba_bitmap_991_960 : 32; - uint32_t ba_bitmap_1023_992 : 32; -#endif -}; - -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 - -#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 -#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 -#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002 - -#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 -#define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 -#define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c - -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 - -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 - -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_SSN_LSB 16 -#define TX_FES_STATUS_1K_BA_SSN_MSB 27 -#define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000 - -#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000 - -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_ack_or_ba.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_ack_or_ba.h deleted file mode 100644 index 678c639141ba..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_ack_or_ba.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_ACK_OR_BA_H_ -#define _TX_FES_STATUS_ACK_OR_BA_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10 - -#define NUM_OF_QWORDS_TX_FES_STATUS_ACK_OR_BA 5 - -struct tx_fes_status_ack_or_ba { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ack_ba_status_type : 1, - ba_type : 1, - ba_tid : 4, - unexpected_ack_or_ba : 1, - response_timeout : 1, - ack_frame_rssi : 8, - ssn : 12, - reserved_0b : 4; - uint32_t sw_peer_id : 16, - reserved_1a : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; -#else - uint32_t reserved_0b : 4, - ssn : 12, - ack_frame_rssi : 8, - response_timeout : 1, - unexpected_ack_or_ba : 1, - ba_tid : 4, - ba_type : 1, - ack_ba_status_type : 1; - uint32_t reserved_1a : 16, - sw_peer_id : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; -#endif -}; - -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB 0 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 - -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB 1 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB 1 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK 0x0000000000000002 - -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB 2 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB 5 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK 0x000000000000003c - -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB 6 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB 6 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 - -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB 7 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB 7 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 - -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB 8 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB 15 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB 16 -#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB 27 -#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK 0x000000000fff0000 - -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB 28 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK 0x00000000f0000000 - -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB 47 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB 48 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK 0xffff000000000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_end.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_end.h deleted file mode 100644 index b1cccb06c7e1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_end.h +++ /dev/null @@ -1,581 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_END_H_ -#define _TX_FES_STATUS_END_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_END 12 - -#define NUM_OF_QWORDS_TX_FES_STATUS_END 6 - -struct tx_fes_status_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t prot___reserved_g_0046 : 1, - prot___reserved_g_0086 : 1, - prot___reserved_g_0043 : 1, - prot___reserved_g_0053 : 1, - prot___reserved_g_0041 : 1, - __reserved_g_0082 : 1, - __reserved_g_0046 : 1, - __reserved_g_0086 : 1, - __reserved_g_0043 : 1, - __reserved_g_0053 : 1, - __reserved_g_0041 : 1, - __reserved_g_0083 : 1, - global_data_underflow_warning : 1, - global_fes_transmit_result : 4, - cbf_bw_received_valid : 1, - cbf_bw_received : 3, - actual_received_ack_type : 4, - sta_response_count : 6, - more_data_received : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t reserved_after_struct16 : 4, - brp_info_valid : 1, - qos_null_switch_done_for_eosp : 1, - reserved_1a : 5, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - fes_in_11ax_trigger_response_config : 1, - null_delim_inserted_before_mpdus : 1, - only_null_delim_sent : 1; - uint32_t terminate___reserved_g_0022_sequence : 1, - reserved_2b : 5, - response_type : 5, - r2r_end_status_to_follow : 1, - reserved_5a : 3, - __reserved_g_0055 : 1, - __reserved_g_0084 : 1, - prot___reserved_g_0042 : 1, - prot___reserved_g_0052 : 1, - __reserved_g_0042 : 1, - __reserved_g_0052 : 1, - reserved_2c : 11; - uint32_t beamform_masked_user_bitmap_15_0 : 16, - beamform_masked_user_bitmap_31_16 : 16; - uint32_t cbf_segment_request_mask : 8, - cbf_segment_sent_mask : 8, - highest_achieved_data_null_ratio : 5, - use_alt_power_sr : 1, - static_2_pwr_mode_status : 1, - obss_srg_opport_transmit_status : 1, - srp_based_transmit_status : 1, - obss_pd_based_transmit_status : 1, - beamform_masked_user_bitmap_36_32 : 5, - pdg_mpdu_ready : 1; - uint32_t pdg_mpdu_count : 16, - pdg_est_mpdu_tx_count : 16; - uint32_t pdg_overview_length : 24, - txop_duration : 7, - pdg_dropped_mpdu_warning : 1; - uint32_t packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - packet_extension : 3, - fec_type : 1, - stbc : 1, - num_data_symbols : 16, - ru_size : 4, - reserved_17a : 4; - uint32_t num_ltf_symbols : 3, - ltf_size : 2, - cp_setting : 2, - reserved_18a : 5, - dcm : 1, - ldpc_extra_symbol : 1, - force_extra_symbol : 1, - reserved_18b : 1, - tx_pwr_shared : 8, - tx_pwr_unshared : 8; - uint32_t __reserved_g_0022_active_user_map : 16, - __reserved_g_0022_sent_dummy_tx : 1, - __reserved_g_0022_ftm_frame_sent : 1, - __reserved_g_0068 : 1, - __reserved_g_0069 : 1, - prot___reserved_g_0068 : 1, - prot___reserved_g_0069 : 1, - __reserved_g_0056 : 1, - __reserved_g_0085 : 1, - cv_corr_status : 8; - uint32_t current_tx_duration : 16, - reserved_21a : 4, - hw_qos_null_bitmap : 8, - hw_qos_null_setup_missing : 1, - reserved_21b : 3; - uint32_t reserved_22b : 4, - prot___reserved_g_0040 : 1, - prot___reserved_g_0080 : 1, - __reserved_g_0040 : 1, - __reserved_g_0080 : 1, - prot___reserved_g_0063 : 1, - prot___reserved_g_0078 : 1, - __reserved_g_0063 : 1, - __reserved_g_0078 : 1, - prot___reserved_g_0061 : 1, - prot___reserved_g_0076 : 1, - __reserved_g_0061 : 1, - __reserved_g_0076 : 1, - prot___reserved_g_0059 : 1, - prot___reserved_g_0074 : 1, - __reserved_g_0059 : 1, - __reserved_g_0074 : 1, - prot___reserved_g_0057 : 1, - prot___reserved_g_0072 : 1, - __reserved_g_0057 : 1, - __reserved_g_0072 : 1, - coex_signaling_status : 8; -#else - uint32_t more_data_received : 1, - sta_response_count : 6, - actual_received_ack_type : 4, - cbf_bw_received : 3, - cbf_bw_received_valid : 1, - global_fes_transmit_result : 4, - global_data_underflow_warning : 1, - __reserved_g_0083 : 1, - __reserved_g_0041 : 1, - __reserved_g_0053 : 1, - __reserved_g_0043 : 1, - __reserved_g_0086 : 1, - __reserved_g_0046 : 1, - __reserved_g_0082 : 1, - prot___reserved_g_0041 : 1, - prot___reserved_g_0053 : 1, - prot___reserved_g_0043 : 1, - prot___reserved_g_0086 : 1, - prot___reserved_g_0046 : 1; - uint32_t only_null_delim_sent : 1, - null_delim_inserted_before_mpdus : 1, - fes_in_11ax_trigger_response_config : 1, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - reserved_1a : 5, - qos_null_switch_done_for_eosp : 1, - brp_info_valid : 1, - reserved_after_struct16 : 4; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t reserved_2c : 11, - __reserved_g_0052 : 1, - __reserved_g_0042 : 1, - prot___reserved_g_0052 : 1, - prot___reserved_g_0042 : 1, - __reserved_g_0084 : 1, - __reserved_g_0055 : 1, - reserved_5a : 3, - r2r_end_status_to_follow : 1, - response_type : 5, - reserved_2b : 5, - terminate___reserved_g_0022_sequence : 1; - uint32_t beamform_masked_user_bitmap_31_16 : 16, - beamform_masked_user_bitmap_15_0 : 16; - uint32_t pdg_mpdu_ready : 1, - beamform_masked_user_bitmap_36_32 : 5, - obss_pd_based_transmit_status : 1, - srp_based_transmit_status : 1, - obss_srg_opport_transmit_status : 1, - static_2_pwr_mode_status : 1, - use_alt_power_sr : 1, - highest_achieved_data_null_ratio : 5, - cbf_segment_sent_mask : 8, - cbf_segment_request_mask : 8; - uint32_t pdg_est_mpdu_tx_count : 16, - pdg_mpdu_count : 16; - uint32_t pdg_dropped_mpdu_warning : 1, - txop_duration : 7, - pdg_overview_length : 24; - uint32_t reserved_17a : 4, - ru_size : 4, - num_data_symbols : 16, - stbc : 1, - fec_type : 1, - packet_extension : 3, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2; - uint32_t tx_pwr_unshared : 8, - tx_pwr_shared : 8, - reserved_18b : 1, - force_extra_symbol : 1, - ldpc_extra_symbol : 1, - dcm : 1, - reserved_18a : 5, - cp_setting : 2, - ltf_size : 2, - num_ltf_symbols : 3; - uint32_t cv_corr_status : 8, - __reserved_g_0085 : 1, - __reserved_g_0056 : 1, - prot___reserved_g_0069 : 1, - prot___reserved_g_0068 : 1, - __reserved_g_0069 : 1, - __reserved_g_0068 : 1, - __reserved_g_0022_ftm_frame_sent : 1, - __reserved_g_0022_sent_dummy_tx : 1, - __reserved_g_0022_active_user_map : 16; - uint32_t reserved_21b : 3, - hw_qos_null_setup_missing : 1, - hw_qos_null_bitmap : 8, - reserved_21a : 4, - current_tx_duration : 16; - uint32_t coex_signaling_status : 8, - __reserved_g_0072 : 1, - __reserved_g_0057 : 1, - prot___reserved_g_0072 : 1, - prot___reserved_g_0057 : 1, - __reserved_g_0074 : 1, - __reserved_g_0059 : 1, - prot___reserved_g_0074 : 1, - prot___reserved_g_0059 : 1, - __reserved_g_0076 : 1, - __reserved_g_0061 : 1, - prot___reserved_g_0076 : 1, - prot___reserved_g_0061 : 1, - __reserved_g_0078 : 1, - __reserved_g_0063 : 1, - prot___reserved_g_0078 : 1, - prot___reserved_g_0063 : 1, - __reserved_g_0080 : 1, - __reserved_g_0040 : 1, - prot___reserved_g_0080 : 1, - prot___reserved_g_0040 : 1, - reserved_22b : 4; -#endif -}; - -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000001000 - -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x000000000001e000 - -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x0000000000020000 - -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x00000000001c0000 - -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x0000000001e00000 - -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x000000007e000000 - -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_LSB 31 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MSB 31 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 48 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 51 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f000000000000 - -#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 52 -#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 52 -#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x0010000000000000 - -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_LSB 53 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MSB 53 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MASK 0x0020000000000000 - -#define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_RESERVED_1A_LSB 54 -#define TX_FES_STATUS_END_RESERVED_1A_MSB 58 -#define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07c0000000000000 - -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 59 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 59 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x0800000000000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 60 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 60 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x1000000000000000 - -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 61 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 61 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x2000000000000000 - -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 62 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 62 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x4000000000000000 - -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 63 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 63 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x8000000000000000 - -#define TX_FES_STATUS_END_RESERVED_2B_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_RESERVED_2B_LSB 1 -#define TX_FES_STATUS_END_RESERVED_2B_MSB 5 -#define TX_FES_STATUS_END_RESERVED_2B_MASK 0x000000000000003e - -#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 6 -#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 10 -#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x00000000000007c0 - -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 11 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 11 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000000000800 - -#define TX_FES_STATUS_END_RESERVED_5A_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_RESERVED_5A_LSB 12 -#define TX_FES_STATUS_END_RESERVED_5A_MSB 14 -#define TX_FES_STATUS_END_RESERVED_5A_MASK 0x0000000000007000 - -#define TX_FES_STATUS_END_RESERVED_2C_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_RESERVED_2C_LSB 21 -#define TX_FES_STATUS_END_RESERVED_2C_MSB 31 -#define TX_FES_STATUS_END_RESERVED_2C_MASK 0x00000000ffe00000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 32 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 47 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 48 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 63 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0xffff000000000000 - -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 0 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 7 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x00000000000000ff - -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 8 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 15 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 16 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 20 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x00000000001f0000 - -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 21 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 21 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x0000000000200000 - -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 22 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 22 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x0000000000400000 - -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 23 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 23 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000000000800000 - -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 24 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 24 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000000001000000 - -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 25 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 25 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000000002000000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 26 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 30 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x000000007c000000 - -#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 31 -#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 31 -#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 32 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 47 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 48 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 63 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0xffff000000000000 - -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 0 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 23 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x0000000000ffffff - -#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_TXOP_DURATION_LSB 24 -#define TX_FES_STATUS_END_TXOP_DURATION_MSB 30 -#define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x000000007f000000 - -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 31 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 31 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 32 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 33 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000300000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 34 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 34 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000400000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 35 -#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 37 -#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x0000003800000000 - -#define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_FEC_TYPE_LSB 38 -#define TX_FES_STATUS_END_FEC_TYPE_MSB 38 -#define TX_FES_STATUS_END_FEC_TYPE_MASK 0x0000004000000000 - -#define TX_FES_STATUS_END_STBC_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_STBC_LSB 39 -#define TX_FES_STATUS_END_STBC_MSB 39 -#define TX_FES_STATUS_END_STBC_MASK 0x0000008000000000 - -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 40 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 55 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x00ffff0000000000 - -#define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_RU_SIZE_LSB 56 -#define TX_FES_STATUS_END_RU_SIZE_MSB 59 -#define TX_FES_STATUS_END_RU_SIZE_MASK 0x0f00000000000000 - -#define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_RESERVED_17A_LSB 60 -#define TX_FES_STATUS_END_RESERVED_17A_MSB 63 -#define TX_FES_STATUS_END_RESERVED_17A_MASK 0xf000000000000000 - -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 0 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 2 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x0000000000000007 - -#define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_LTF_SIZE_LSB 3 -#define TX_FES_STATUS_END_LTF_SIZE_MSB 4 -#define TX_FES_STATUS_END_LTF_SIZE_MASK 0x0000000000000018 - -#define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_CP_SETTING_LSB 5 -#define TX_FES_STATUS_END_CP_SETTING_MSB 6 -#define TX_FES_STATUS_END_CP_SETTING_MASK 0x0000000000000060 - -#define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_RESERVED_18A_LSB 7 -#define TX_FES_STATUS_END_RESERVED_18A_MSB 11 -#define TX_FES_STATUS_END_RESERVED_18A_MASK 0x0000000000000f80 - -#define TX_FES_STATUS_END_DCM_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_DCM_LSB 12 -#define TX_FES_STATUS_END_DCM_MSB 12 -#define TX_FES_STATUS_END_DCM_MASK 0x0000000000001000 - -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 13 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 13 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x0000000000002000 - -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 14 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 14 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x0000000000004000 - -#define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_RESERVED_18B_LSB 15 -#define TX_FES_STATUS_END_RESERVED_18B_MSB 15 -#define TX_FES_STATUS_END_RESERVED_18B_MASK 0x0000000000008000 - -#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 16 -#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 23 -#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x0000000000ff0000 - -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 24 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 31 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0x00000000ff000000 - -#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 56 -#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 63 -#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0xff00000000000000 - -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 0 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 15 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x000000000000ffff - -#define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_21A_LSB 16 -#define TX_FES_STATUS_END_RESERVED_21A_MSB 19 -#define TX_FES_STATUS_END_RESERVED_21A_MASK 0x00000000000f0000 - -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_LSB 20 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MSB 27 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MASK 0x000000000ff00000 - -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_LSB 28 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MSB 28 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MASK 0x0000000010000000 - -#define TX_FES_STATUS_END_RESERVED_21B_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_21B_LSB 29 -#define TX_FES_STATUS_END_RESERVED_21B_MSB 31 -#define TX_FES_STATUS_END_RESERVED_21B_MASK 0x00000000e0000000 - -#define TX_FES_STATUS_END_RESERVED_22B_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_22B_LSB 32 -#define TX_FES_STATUS_END_RESERVED_22B_MSB 35 -#define TX_FES_STATUS_END_RESERVED_22B_MASK 0x0000000f00000000 - -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_LSB 56 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MSB 63 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_prot.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_prot.h deleted file mode 100644 index 702cc1add940..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_prot.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_PROT_H_ -#define _TX_FES_STATUS_PROT_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 4 - -#define NUM_OF_QWORDS_TX_FES_STATUS_PROT 2 - -struct tx_fes_status_prot { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t success : 1, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - reserved_0 : 19, - pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5; - uint32_t frame_type : 2, - frame_subtype : 4, - rx_pwr_mgmt : 1, - status : 1, - duration_field : 16, - reserved_1a : 2, - agc_cbw : 3, - service_cbw : 3; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t reserved_2a : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4, - reserved_0 : 19, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - success : 1; - uint32_t service_cbw : 3, - agc_cbw : 3, - reserved_1a : 2, - duration_field : 16, - status : 1, - rx_pwr_mgmt : 1, - frame_subtype : 4, - frame_type : 2; - uint32_t reserved_2a : 16; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_SUCCESS_LSB 0 -#define TX_FES_STATUS_PROT_SUCCESS_MSB 0 -#define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001 - -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004 - -#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 -#define TX_FES_STATUS_PROT_RESERVED_0_MSB 21 -#define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000003ffff8 - -#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PKT_TYPE_LSB 22 -#define TX_FES_STATUS_PROT_PKT_TYPE_MSB 25 -#define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000003c00000 - -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 26 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 26 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000004000000 - -#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RATE_MCS_LSB 27 -#define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 -#define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f8000000 - -#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32 -#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33 -#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000 - -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000 - -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000 - -#define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_STATUS_LSB 39 -#define TX_FES_STATUS_PROT_STATUS_MSB 39 -#define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000 - -#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40 -#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55 -#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000 - -#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56 -#define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57 -#define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000 - -#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_AGC_CBW_LSB 58 -#define TX_FES_STATUS_PROT_AGC_CBW_MSB 60 -#define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000 - -#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61 -#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63 -#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00000000000000ff - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x0000000000003f00 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x000000000000c000 - -#define TX_FES_STATUS_PROT_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_RESERVED_2A_LSB 16 -#define TX_FES_STATUS_PROT_RESERVED_2A_MSB 31 -#define TX_FES_STATUS_PROT_RESERVED_2A_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_PROT_TLV64_PADDING_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_PROT_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_PROT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start.h deleted file mode 100644 index bc8e06ec59fb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_H_ -#define _TX_FES_STATUS_START_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START 4 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START 2 - -struct tx_fes_status_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t schedule_id : 32; - uint32_t reserved_1a : 8, - transmit_start_reason : 3, - disabled_user_bitmap_36_32 : 5, - schedule_cmd_ring_id : 5, - fes_control_mode : 2, - schedule_try : 4, - medium_prot_type : 3, - reserved_1b : 2; - uint32_t optimal_bw_try_count : 4, - number_of_users : 7, - coex_nack_count : 5, - cca_ed0 : 16; - uint32_t disabled_user_bitmap_31_0 : 32; -#else - uint32_t schedule_id : 32; - uint32_t reserved_1b : 2, - medium_prot_type : 3, - schedule_try : 4, - fes_control_mode : 2, - schedule_cmd_ring_id : 5, - disabled_user_bitmap_36_32 : 5, - transmit_start_reason : 3, - reserved_1a : 8; - uint32_t cca_ed0 : 16, - coex_nack_count : 5, - number_of_users : 7, - optimal_bw_try_count : 4; - uint32_t disabled_user_bitmap_31_0 : 32; -#endif -}; - -#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_ID_LSB 0 -#define TX_FES_STATUS_START_SCHEDULE_ID_MSB 31 -#define TX_FES_STATUS_START_SCHEDULE_ID_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_RESERVED_1A_LSB 32 -#define TX_FES_STATUS_START_RESERVED_1A_MSB 39 -#define TX_FES_STATUS_START_RESERVED_1A_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB 40 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB 42 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK 0x0000070000000000 - -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB 43 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB 47 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK 0x0000f80000000000 - -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB 48 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB 52 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 - -#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB 53 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB 54 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK 0x0060000000000000 - -#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB 55 -#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB 58 -#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK 0x0780000000000000 - -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB 59 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB 61 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK 0x3800000000000000 - -#define TX_FES_STATUS_START_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_RESERVED_1B_LSB 62 -#define TX_FES_STATUS_START_RESERVED_1B_MSB 63 -#define TX_FES_STATUS_START_RESERVED_1B_MASK 0xc000000000000000 - -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB 0 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB 3 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK 0x000000000000000f - -#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB 4 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB 10 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK 0x00000000000007f0 - -#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB 11 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB 15 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK 0x000000000000f800 - -#define TX_FES_STATUS_START_CCA_ED0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_CCA_ED0_LSB 16 -#define TX_FES_STATUS_START_CCA_ED0_MSB 31 -#define TX_FES_STATUS_START_CCA_ED0_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB 32 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB 63 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start_ppdu.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start_ppdu.h deleted file mode 100644 index a87b3b0a0ccc..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start_ppdu.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_PPDU_H_ -#define _TX_FES_STATUS_START_PPDU_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START_PPDU 3 - -struct tx_fes_status_start_ppdu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ppdu_timestamp_lower_32 : 32; - uint32_t ppdu_timestamp_upper_32 : 32; - uint32_t subband_mask : 16, - ndp_frame : 3, - reserved_2b : 1, - coex_based_tx_bw : 3, - coex_based_ant_mask : 8, - reserved_2c : 1; - uint32_t coex_based_tx_pwr_shared_ant : 8, - coex_based_tx_pwr_ant : 8, - concurrent_bt_tx : 1, - concurrent_wlan_tx : 1, - concurrent_wan_tx : 1, - concurrent_wan_rx : 1, - coex_pwr_reduction_bt : 1, - coex_pwr_reduction_wlan : 1, - coex_pwr_reduction_wan : 1, - coex_result_alt_based : 1, - request_packet_bw : 3, - response_type : 5; - uint32_t concurrent_rx_activity_tracker1 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - coex_pwr_reduction_wan_ratid1 : 1, - reserved_4a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t ppdu_timestamp_lower_32 : 32; - uint32_t ppdu_timestamp_upper_32 : 32; - uint32_t reserved_2c : 1, - coex_based_ant_mask : 8, - coex_based_tx_bw : 3, - reserved_2b : 1, - ndp_frame : 3, - subband_mask : 16; - uint32_t response_type : 5, - request_packet_bw : 3, - coex_result_alt_based : 1, - coex_pwr_reduction_wan : 1, - coex_pwr_reduction_wlan : 1, - coex_pwr_reduction_bt : 1, - concurrent_wan_rx : 1, - concurrent_wan_tx : 1, - concurrent_wlan_tx : 1, - concurrent_bt_tx : 1, - coex_based_tx_pwr_ant : 8, - coex_based_tx_pwr_shared_ant : 8; - uint32_t reserved_4a : 18, - coex_pwr_reduction_wan_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker1 : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB 0 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB 31 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB 32 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB 63 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB 0 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB 15 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK 0x000000000000ffff - -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB 16 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB 18 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK 0x0000000000070000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB 19 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB 19 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK 0x0000000000080000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB 20 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB 22 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK 0x0000000000700000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB 23 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB 30 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK 0x0000000080000000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB 32 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB 39 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB 40 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB 47 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK 0x0000ff0000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB 48 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB 48 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK 0x0001000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB 49 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB 49 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB 50 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB 50 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK 0x0004000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB 51 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB 51 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK 0x0008000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB 52 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB 52 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB 53 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB 53 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB 54 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB 54 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB 55 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB 55 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK 0x0080000000000000 - -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB 56 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB 58 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK 0x0700000000000000 - -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB 59 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB 63 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK 0xf800000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB 0 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB 0 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK 0x0000000000000001 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB 1 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB 1 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK 0x0000000000000002 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB 2 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB 2 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK 0x0000000000000004 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB 3 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB 3 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK 0x0000000000000008 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB 4 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB 4 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK 0x0000000000000010 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB 5 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB 5 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK 0x0000000000000020 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB 6 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB 6 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK 0x0000000000000040 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB 7 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB 7 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK 0x0000000000000080 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB 8 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB 8 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK 0x0000000000000100 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB 9 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB 9 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK 0x0000000000000200 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB 10 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB 10 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK 0x0000000000000400 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_LSB 11 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MSB 11 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MASK 0x0000000000000800 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_LSB 12 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MSB 12 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MASK 0x0000000000001000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_LSB 13 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MSB 13 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MASK 0x0000000000002000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_LSB 14 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MASK 0x00000000ffffc000 - -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start_prot.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start_prot.h deleted file mode 100644 index aca9ac5eb28b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_start_prot.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_PROT_H_ -#define _TX_FES_STATUS_START_PROT_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START_PROT 3 - -struct tx_fes_status_start_prot { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t prot_timestamp_lower_32 : 32; - uint32_t prot_timestamp_upper_32 : 32; - uint32_t subband_mask : 16, - reserved_2b : 4, - prot_coex_based_tx_bw : 3, - prot_coex_based_ant_mask : 8, - prot_coex_result_alt_based : 1; - uint32_t prot_coex_tx_pwr_shared_ant : 8, - prot_coex_tx_pwr_ant : 8, - prot_concurrent_bt_tx : 1, - prot_concurrent_wlan_tx : 1, - prot_concurrent_wan_tx : 1, - prot_concurrent_wan_rx : 1, - prot_coex_pwr_reduction_bt : 1, - prot_coex_pwr_reduction_wlan : 1, - prot_coex_pwr_reduction_wan : 1, - prot_request_packet_bw : 3, - response_type : 5, - reserved_3a : 1; - uint32_t concurrent_rx_activity_tracker1 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - coex_pwr_reduction_wan_ratid1 : 1, - reserved_4a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t prot_timestamp_lower_32 : 32; - uint32_t prot_timestamp_upper_32 : 32; - uint32_t prot_coex_result_alt_based : 1, - prot_coex_based_ant_mask : 8, - prot_coex_based_tx_bw : 3, - reserved_2b : 4, - subband_mask : 16; - uint32_t reserved_3a : 1, - response_type : 5, - prot_request_packet_bw : 3, - prot_coex_pwr_reduction_wan : 1, - prot_coex_pwr_reduction_wlan : 1, - prot_coex_pwr_reduction_bt : 1, - prot_concurrent_wan_rx : 1, - prot_concurrent_wan_tx : 1, - prot_concurrent_wlan_tx : 1, - prot_concurrent_bt_tx : 1, - prot_coex_tx_pwr_ant : 8, - prot_coex_tx_pwr_shared_ant : 8; - uint32_t reserved_4a : 18, - coex_pwr_reduction_wan_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker1 : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB 0 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB 31 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB 32 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB 63 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB 0 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB 15 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK 0x000000000000ffff - -#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB 16 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB 19 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK 0x00000000000f0000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB 20 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB 22 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK 0x0000000000700000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB 23 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB 30 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB 31 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB 31 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK 0x0000000080000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB 32 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB 39 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB 40 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB 47 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK 0x0000ff0000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB 48 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB 48 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK 0x0001000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB 49 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB 49 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB 50 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB 50 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK 0x0004000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB 51 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB 51 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK 0x0008000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB 52 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB 52 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB 53 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB 53 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB 54 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB 54 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB 55 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB 57 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK 0x0380000000000000 - -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB 58 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB 62 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK 0x7c00000000000000 - -#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB 63 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB 63 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK 0x8000000000000000 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB 0 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB 0 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK 0x0000000000000001 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB 1 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB 1 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK 0x0000000000000002 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB 2 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB 2 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK 0x0000000000000004 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB 3 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB 3 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK 0x0000000000000008 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB 4 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB 4 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK 0x0000000000000010 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB 5 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB 5 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK 0x0000000000000020 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB 6 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB 6 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK 0x0000000000000040 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB 7 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB 7 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK 0x0000000000000080 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB 8 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB 8 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK 0x0000000000000100 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB 9 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB 9 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK 0x0000000000000200 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB 10 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB 10 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK 0x0000000000000400 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_LSB 11 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MSB 11 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MASK 0x0000000000000800 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_LSB 12 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MSB 12 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MASK 0x0000000000001000 - -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_LSB 13 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MSB 13 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MASK 0x0000000000002000 - -#define TX_FES_STATUS_START_PROT_RESERVED_4A_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_LSB 14 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_MSB 31 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_MASK 0x00000000ffffc000 - -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_user_ppdu.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_user_ppdu.h deleted file mode 100644 index dad9a040ff46..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_user_ppdu.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_USER_PPDU_H_ -#define _TX_FES_STATUS_USER_PPDU_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3 - -struct tx_fes_status_user_ppdu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t underflow_mpdu_count : 9, - data_underflow_warning : 2, - bw_drop_underflow_warning : 1, - qc_eosp_setting : 1, - mpdu_tx_count : 11, - user_blocked : 1, - pre_trig_response_delim_count : 7; - uint32_t underflow_byte_count : 16, - coex_abort_mpdu_count_valid : 1, - coex_abort_mpdu_count : 9, - transmitted_tid : 4, - txdma_dropped_mpdu_warning : 1, - cv_corr_user_valid_in_phy : 1; - uint32_t duration : 16, - num_eof_delim_added : 16; - uint32_t psdu_octet : 24, - qos_buf_state : 8; - uint32_t num_null_delim_added : 22, - fc_more_data_setting : 1, - fc_pwr_mgt_setting : 1, - nss : 3, - mcs : 5; - uint32_t ht_control : 32; -#else - uint32_t pre_trig_response_delim_count : 7, - user_blocked : 1, - mpdu_tx_count : 11, - qc_eosp_setting : 1, - bw_drop_underflow_warning : 1, - data_underflow_warning : 2, - underflow_mpdu_count : 9; - uint32_t cv_corr_user_valid_in_phy : 1, - txdma_dropped_mpdu_warning : 1, - transmitted_tid : 4, - coex_abort_mpdu_count : 9, - coex_abort_mpdu_count_valid : 1, - underflow_byte_count : 16; - uint32_t num_eof_delim_added : 16, - duration : 16; - uint32_t qos_buf_state : 8, - psdu_octet : 24; - uint32_t mcs : 5, - nss : 3, - fc_pwr_mgt_setting : 1, - fc_more_data_setting : 1, - num_null_delim_added : 22; - uint32_t ht_control : 32; -#endif -}; - -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff - -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 - -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x0000000000000800 - -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x0000000000001000 - -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 13 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x0000000000ffe000 - -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x0000000001000000 - -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0x00000000fe000000 - -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 32 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 47 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 48 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 48 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x0001000000000000 - -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 49 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 57 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe000000000000 - -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 58 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 61 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c00000000000000 - -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 62 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 62 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x4000000000000000 - -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 63 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 63 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x8000000000000000 - -#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 -#define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 -#define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x000000000000ffff - -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 32 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 55 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff00000000 - -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 56 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 63 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff00000000000000 - -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x00000000003fffff - -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 22 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 22 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x0000000000400000 - -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 23 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 23 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x0000000000800000 - -#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_NSS_LSB 24 -#define TX_FES_STATUS_USER_PPDU_NSS_MSB 26 -#define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x0000000007000000 - -#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_MCS_LSB 27 -#define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 -#define TX_FES_STATUS_USER_PPDU_MCS_MASK 0x00000000f8000000 - -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 32 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 63 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_user_response.h b/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_user_response.h deleted file mode 100644 index a4562d64a9ec..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_fes_status_user_response.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_USER_RESPONSE_H_ -#define _TX_FES_STATUS_USER_RESPONSE_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2 - -#define NUM_OF_QWORDS_TX_FES_STATUS_USER_RESPONSE 1 - -struct tx_fes_status_user_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t fes_transmit_result : 4, - reserved_0 : 28; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t pre_padding_fcs_overwritten : 1, - reserved_after_struct16 : 15; -#else - uint32_t reserved_0 : 28, - fes_transmit_result : 4; - uint32_t reserved_after_struct16 : 15, - pre_padding_fcs_overwritten : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; -#endif -}; - -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB 0 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB 3 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK 0x000000000000000f - -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB 4 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB 31 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK 0x00000000fffffff0 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_LSB 48 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MSB 48 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MASK 0x0001000000000000 - -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB 49 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB 63 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK 0xfffe000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_flush_req.h b/drivers/staging/fw-api/hw/fig/v1/tx_flush_req.h deleted file mode 100644 index af502ec619eb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_flush_req.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FLUSH_REQ_H_ -#define _TX_FLUSH_REQ_H_ - -#define NUM_OF_DWORDS_TX_FLUSH_REQ 2 - -#define NUM_OF_QWORDS_TX_FLUSH_REQ 1 - -struct tx_flush_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t flush_req_reason : 8, - phytx_abort_reason : 8, - flush_req_user_number_or_link_id : 6, - mlo_abort_reason : 5, - reserved_0a : 5; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 5, - mlo_abort_reason : 5, - flush_req_user_number_or_link_id : 6, - phytx_abort_reason : 8, - flush_req_reason : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x00000000000000ff - -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x000000000000ff00 - -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x00000000003f0000 - -#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x0000000007c00000 - -#define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_RESERVED_0A_LSB 27 -#define TX_FLUSH_REQ_RESERVED_0A_MSB 31 -#define TX_FLUSH_REQ_RESERVED_0A_MASK 0x00000000f8000000 - -#define TX_FLUSH_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_TLV64_PADDING_LSB 32 -#define TX_FLUSH_REQ_TLV64_PADDING_MSB 63 -#define TX_FLUSH_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_mpdu_start.h b/drivers/staging/fw-api/hw/fig/v1/tx_mpdu_start.h deleted file mode 100644 index a68fab7a4f2a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_mpdu_start.h +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MPDU_START_H_ -#define _TX_MPDU_START_H_ - -#define NUM_OF_DWORDS_TX_MPDU_START 10 - -#define NUM_OF_QWORDS_TX_MPDU_START 5 - -struct tx_mpdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mpdu_length : 14, - frame_not_from_tqm : 1, - vht_control_present : 1, - mpdu_header_length : 8, - retry_count : 7, - wds : 1; - uint32_t pn_31_0 : 32; - uint32_t pn_47_32 : 16, - mpdu_sequence_number : 12, - raw_already_encrypted : 1, - frame_type : 2, - txdma_dropped_mpdu_warning : 1; - uint32_t iv_byte_0 : 8, - iv_byte_1 : 8, - iv_byte_2 : 8, - iv_byte_3 : 8; - uint32_t iv_byte_4 : 8, - iv_byte_5 : 8, - iv_byte_6 : 8, - iv_byte_7 : 8; - uint32_t iv_byte_8 : 8, - iv_byte_9 : 8, - iv_byte_10 : 8, - iv_byte_11 : 8; - uint32_t iv_byte_12 : 8, - iv_byte_13 : 8, - iv_byte_14 : 8, - iv_byte_15 : 8; - uint32_t iv_byte_16 : 8, - iv_byte_17 : 8, - iv_len : 5, - icv_len : 5, - vht_control_offset : 6; - uint32_t mpdu_type : 1, - transmit_bw_restriction : 1, - allowed_transmit_bw : 4, - tx_notify_frame : 3, - reserved_8a : 23; - uint32_t tlv64_padding : 32; -#else - uint32_t wds : 1, - retry_count : 7, - mpdu_header_length : 8, - vht_control_present : 1, - frame_not_from_tqm : 1, - mpdu_length : 14; - uint32_t pn_31_0 : 32; - uint32_t txdma_dropped_mpdu_warning : 1, - frame_type : 2, - raw_already_encrypted : 1, - mpdu_sequence_number : 12, - pn_47_32 : 16; - uint32_t iv_byte_3 : 8, - iv_byte_2 : 8, - iv_byte_1 : 8, - iv_byte_0 : 8; - uint32_t iv_byte_7 : 8, - iv_byte_6 : 8, - iv_byte_5 : 8, - iv_byte_4 : 8; - uint32_t iv_byte_11 : 8, - iv_byte_10 : 8, - iv_byte_9 : 8, - iv_byte_8 : 8; - uint32_t iv_byte_15 : 8, - iv_byte_14 : 8, - iv_byte_13 : 8, - iv_byte_12 : 8; - uint32_t vht_control_offset : 6, - icv_len : 5, - iv_len : 5, - iv_byte_17 : 8, - iv_byte_16 : 8; - uint32_t reserved_8a : 23, - tx_notify_frame : 3, - allowed_transmit_bw : 4, - transmit_bw_restriction : 1, - mpdu_type : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x0000000000000000 -#define TX_MPDU_START_MPDU_LENGTH_LSB 0 -#define TX_MPDU_START_MPDU_LENGTH_MSB 13 -#define TX_MPDU_START_MPDU_LENGTH_MASK 0x0000000000003fff - -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x0000000000000000 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x0000000000004000 - -#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x0000000000000000 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x0000000000008000 - -#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x0000000000000000 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_RETRY_COUNT_OFFSET 0x0000000000000000 -#define TX_MPDU_START_RETRY_COUNT_LSB 24 -#define TX_MPDU_START_RETRY_COUNT_MSB 30 -#define TX_MPDU_START_RETRY_COUNT_MASK 0x000000007f000000 - -#define TX_MPDU_START_WDS_OFFSET 0x0000000000000000 -#define TX_MPDU_START_WDS_LSB 31 -#define TX_MPDU_START_WDS_MSB 31 -#define TX_MPDU_START_WDS_MASK 0x0000000080000000 - -#define TX_MPDU_START_PN_31_0_OFFSET 0x0000000000000000 -#define TX_MPDU_START_PN_31_0_LSB 32 -#define TX_MPDU_START_PN_31_0_MSB 63 -#define TX_MPDU_START_PN_31_0_MASK 0xffffffff00000000 - -#define TX_MPDU_START_PN_47_32_OFFSET 0x0000000000000008 -#define TX_MPDU_START_PN_47_32_LSB 0 -#define TX_MPDU_START_PN_47_32_MSB 15 -#define TX_MPDU_START_PN_47_32_MASK 0x000000000000ffff - -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000008 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x000000000fff0000 - -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x0000000000000008 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x0000000010000000 - -#define TX_MPDU_START_FRAME_TYPE_OFFSET 0x0000000000000008 -#define TX_MPDU_START_FRAME_TYPE_LSB 29 -#define TX_MPDU_START_FRAME_TYPE_MSB 30 -#define TX_MPDU_START_FRAME_TYPE_MASK 0x0000000060000000 - -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000008 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 - -#define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_0_LSB 32 -#define TX_MPDU_START_IV_BYTE_0_MSB 39 -#define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_1_LSB 40 -#define TX_MPDU_START_IV_BYTE_1_MSB 47 -#define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_2_LSB 48 -#define TX_MPDU_START_IV_BYTE_2_MSB 55 -#define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff000000000000 - -#define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_3_LSB 56 -#define TX_MPDU_START_IV_BYTE_3_MSB 63 -#define TX_MPDU_START_IV_BYTE_3_MASK 0xff00000000000000 - -#define TX_MPDU_START_IV_BYTE_4_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_4_LSB 0 -#define TX_MPDU_START_IV_BYTE_4_MSB 7 -#define TX_MPDU_START_IV_BYTE_4_MASK 0x00000000000000ff - -#define TX_MPDU_START_IV_BYTE_5_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_5_LSB 8 -#define TX_MPDU_START_IV_BYTE_5_MSB 15 -#define TX_MPDU_START_IV_BYTE_5_MASK 0x000000000000ff00 - -#define TX_MPDU_START_IV_BYTE_6_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_6_LSB 16 -#define TX_MPDU_START_IV_BYTE_6_MSB 23 -#define TX_MPDU_START_IV_BYTE_6_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_IV_BYTE_7_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_7_LSB 24 -#define TX_MPDU_START_IV_BYTE_7_MSB 31 -#define TX_MPDU_START_IV_BYTE_7_MASK 0x00000000ff000000 - -#define TX_MPDU_START_IV_BYTE_8_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_8_LSB 32 -#define TX_MPDU_START_IV_BYTE_8_MSB 39 -#define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_9_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_9_LSB 40 -#define TX_MPDU_START_IV_BYTE_9_MSB 47 -#define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_BYTE_10_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_10_LSB 48 -#define TX_MPDU_START_IV_BYTE_10_MSB 55 -#define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff000000000000 - -#define TX_MPDU_START_IV_BYTE_11_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_11_LSB 56 -#define TX_MPDU_START_IV_BYTE_11_MSB 63 -#define TX_MPDU_START_IV_BYTE_11_MASK 0xff00000000000000 - -#define TX_MPDU_START_IV_BYTE_12_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_12_LSB 0 -#define TX_MPDU_START_IV_BYTE_12_MSB 7 -#define TX_MPDU_START_IV_BYTE_12_MASK 0x00000000000000ff - -#define TX_MPDU_START_IV_BYTE_13_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_13_LSB 8 -#define TX_MPDU_START_IV_BYTE_13_MSB 15 -#define TX_MPDU_START_IV_BYTE_13_MASK 0x000000000000ff00 - -#define TX_MPDU_START_IV_BYTE_14_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_14_LSB 16 -#define TX_MPDU_START_IV_BYTE_14_MSB 23 -#define TX_MPDU_START_IV_BYTE_14_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_IV_BYTE_15_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_15_LSB 24 -#define TX_MPDU_START_IV_BYTE_15_MSB 31 -#define TX_MPDU_START_IV_BYTE_15_MASK 0x00000000ff000000 - -#define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_16_LSB 32 -#define TX_MPDU_START_IV_BYTE_16_MSB 39 -#define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_17_LSB 40 -#define TX_MPDU_START_IV_BYTE_17_MSB 47 -#define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_LEN_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_LEN_LSB 48 -#define TX_MPDU_START_IV_LEN_MSB 52 -#define TX_MPDU_START_IV_LEN_MASK 0x001f000000000000 - -#define TX_MPDU_START_ICV_LEN_OFFSET 0x0000000000000018 -#define TX_MPDU_START_ICV_LEN_LSB 53 -#define TX_MPDU_START_ICV_LEN_MSB 57 -#define TX_MPDU_START_ICV_LEN_MASK 0x03e0000000000000 - -#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000000000000018 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 58 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 63 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc00000000000000 - -#define TX_MPDU_START_MPDU_TYPE_OFFSET 0x0000000000000020 -#define TX_MPDU_START_MPDU_TYPE_LSB 0 -#define TX_MPDU_START_MPDU_TYPE_MSB 0 -#define TX_MPDU_START_MPDU_TYPE_MASK 0x0000000000000001 - -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x0000000000000002 - -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x0000000000000020 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x000000000000003c - -#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 -#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 -#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x00000000000001c0 - -#define TX_MPDU_START_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_MPDU_START_RESERVED_8A_LSB 9 -#define TX_MPDU_START_RESERVED_8A_MSB 31 -#define TX_MPDU_START_RESERVED_8A_MASK 0x00000000fffffe00 - -#define TX_MPDU_START_TLV64_PADDING_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TLV64_PADDING_LSB 32 -#define TX_MPDU_START_TLV64_PADDING_MSB 63 -#define TX_MPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_msdu_extension.h b/drivers/staging/fw-api/hw/fig/v1/tx_msdu_extension.h deleted file mode 100644 index f8da5593497b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_msdu_extension.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MSDU_EXTENSION_H_ -#define _TX_MSDU_EXTENSION_H_ - -#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 - -struct tx_msdu_extension { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tso_enable : 1, - reserved_0a : 6, - tcp_flag : 9, - tcp_flag_mask : 9, - reserved_0b : 7; - uint32_t l2_length : 16, - ip_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t ip_identification : 16, - udp_length : 16; - uint32_t checksum_offset : 14, - partial_checksum_en : 1, - reserved_4a : 1, - payload_start_offset : 14, - reserved_4b : 2; - uint32_t payload_end_offset : 14, - reserved_5a : 2, - wds : 1, - reserved_5b : 15; - uint32_t buf0_ptr_31_0 : 32; - uint32_t buf0_ptr_39_32 : 8, - reserved_7a : 8, - buf0_len : 16; - uint32_t buf1_ptr_31_0 : 32; - uint32_t buf1_ptr_39_32 : 8, - reserved_9a : 8, - buf1_len : 16; - uint32_t buf2_ptr_31_0 : 32; - uint32_t buf2_ptr_39_32 : 8, - reserved_11a : 8, - buf2_len : 16; - uint32_t buf3_ptr_31_0 : 32; - uint32_t buf3_ptr_39_32 : 8, - reserved_13a : 8, - buf3_len : 16; - uint32_t buf4_ptr_31_0 : 32; - uint32_t buf4_ptr_39_32 : 8, - reserved_15a : 8, - buf4_len : 16; - uint32_t buf5_ptr_31_0 : 32; - uint32_t buf5_ptr_39_32 : 8, - reserved_17a : 8, - buf5_len : 16; -#else - uint32_t reserved_0b : 7, - tcp_flag_mask : 9, - tcp_flag : 9, - reserved_0a : 6, - tso_enable : 1; - uint32_t ip_length : 16, - l2_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t udp_length : 16, - ip_identification : 16; - uint32_t reserved_4b : 2, - payload_start_offset : 14, - reserved_4a : 1, - partial_checksum_en : 1, - checksum_offset : 14; - uint32_t reserved_5b : 15, - wds : 1, - reserved_5a : 2, - payload_end_offset : 14; - uint32_t buf0_ptr_31_0 : 32; - uint32_t buf0_len : 16, - reserved_7a : 8, - buf0_ptr_39_32 : 8; - uint32_t buf1_ptr_31_0 : 32; - uint32_t buf1_len : 16, - reserved_9a : 8, - buf1_ptr_39_32 : 8; - uint32_t buf2_ptr_31_0 : 32; - uint32_t buf2_len : 16, - reserved_11a : 8, - buf2_ptr_39_32 : 8; - uint32_t buf3_ptr_31_0 : 32; - uint32_t buf3_len : 16, - reserved_13a : 8, - buf3_ptr_39_32 : 8; - uint32_t buf4_ptr_31_0 : 32; - uint32_t buf4_len : 16, - reserved_15a : 8, - buf4_ptr_39_32 : 8; - uint32_t buf5_ptr_31_0 : 32; - uint32_t buf5_len : 16, - reserved_17a : 8, - buf5_ptr_39_32 : 8; -#endif -}; - -#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0 -#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB 0 -#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001 - -#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_RESERVED_0A_LSB 1 -#define TX_MSDU_EXTENSION_RESERVED_0A_MSB 6 -#define TX_MSDU_EXTENSION_RESERVED_0A_MASK 0x0000007e - -#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TCP_FLAG_LSB 7 -#define TX_MSDU_EXTENSION_TCP_FLAG_MSB 15 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80 - -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB 24 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000 - -#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_RESERVED_0B_LSB 25 -#define TX_MSDU_EXTENSION_RESERVED_0B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_0B_MASK 0xfe000000 - -#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004 -#define TX_MSDU_EXTENSION_L2_LENGTH_LSB 0 -#define TX_MSDU_EXTENSION_L2_LENGTH_MSB 15 -#define TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff - -#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004 -#define TX_MSDU_EXTENSION_IP_LENGTH_LSB 16 -#define TX_MSDU_EXTENSION_IP_LENGTH_MSB 31 -#define TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB 31 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0 -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB 15 -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff - -#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET 0x0000000c -#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB 16 -#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB 31 -#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB 0 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB 13 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK 0x00003fff - -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB 14 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB 14 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK 0x00004000 - -#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_RESERVED_4A_LSB 15 -#define TX_MSDU_EXTENSION_RESERVED_4A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_4A_MASK 0x00008000 - -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB 16 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB 29 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK 0x3fff0000 - -#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_RESERVED_4B_LSB 30 -#define TX_MSDU_EXTENSION_RESERVED_4B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_4B_MASK 0xc0000000 - -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB 0 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB 13 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK 0x00003fff - -#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_RESERVED_5A_LSB 14 -#define TX_MSDU_EXTENSION_RESERVED_5A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_5A_MASK 0x0000c000 - -#define TX_MSDU_EXTENSION_WDS_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_WDS_LSB 16 -#define TX_MSDU_EXTENSION_WDS_MSB 16 -#define TX_MSDU_EXTENSION_WDS_MASK 0x00010000 - -#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_RESERVED_5B_LSB 17 -#define TX_MSDU_EXTENSION_RESERVED_5B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_5B_MASK 0xfffe0000 - -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_7A_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_RESERVED_7A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_7A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_7A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_BUF0_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF0_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_RESERVED_9A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_9A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_9A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_BUF1_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF1_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_RESERVED_11A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_11A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_11A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_BUF2_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF2_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_RESERVED_13A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_13A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_13A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_BUF3_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF3_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_RESERVED_15A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_15A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_15A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_BUF4_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF4_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_RESERVED_17A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_17A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_17A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_BUF5_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF5_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_msdu_start.h b/drivers/staging/fw-api/hw/fig/v1/tx_msdu_start.h deleted file mode 100644 index e62a76009f3a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_msdu_start.h +++ /dev/null @@ -1,250 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MSDU_START_H_ -#define _TX_MSDU_START_H_ - -#define NUM_OF_DWORDS_TX_MSDU_START 8 - -#define NUM_OF_QWORDS_TX_MSDU_START 4 - -struct tx_msdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t msdu_len : 14, - first_msdu : 1, - last_msdu : 1, - encap_type : 2, - epd_en : 1, - da_sa_present : 2, - ipv4_checksum_en : 1, - udp_over_ipv4_checksum_en : 1, - udp_over_ipv6_checksum_en : 1, - tcp_over_ipv4_checksum_en : 1, - tcp_over_ipv6_checksum_en : 1, - dummy_msdu_delimitation : 1, - reserved_0a : 5; - uint32_t tso_enable : 1, - reserved_1a : 6, - tcp_flag : 9, - tcp_flag_mask : 9, - mesh_enable : 1, - reserved_1b : 6; - uint32_t l2_length : 16, - ip_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t ip_identification : 16, - checksum_offset : 13, - partial_checksum_en : 1, - reserved_4 : 2; - uint32_t payload_start_offset : 14, - reserved_5a : 2, - payload_end_offset : 14, - reserved_5b : 2; - uint32_t udp_length : 16, - reserved_6 : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 5, - dummy_msdu_delimitation : 1, - tcp_over_ipv6_checksum_en : 1, - tcp_over_ipv4_checksum_en : 1, - udp_over_ipv6_checksum_en : 1, - udp_over_ipv4_checksum_en : 1, - ipv4_checksum_en : 1, - da_sa_present : 2, - epd_en : 1, - encap_type : 2, - last_msdu : 1, - first_msdu : 1, - msdu_len : 14; - uint32_t reserved_1b : 6, - mesh_enable : 1, - tcp_flag_mask : 9, - tcp_flag : 9, - reserved_1a : 6, - tso_enable : 1; - uint32_t ip_length : 16, - l2_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t reserved_4 : 2, - partial_checksum_en : 1, - checksum_offset : 13, - ip_identification : 16; - uint32_t reserved_5b : 2, - payload_end_offset : 14, - reserved_5a : 2, - payload_start_offset : 14; - uint32_t reserved_6 : 16, - udp_length : 16; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_MSDU_START_MSDU_LEN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_MSDU_LEN_LSB 0 -#define TX_MSDU_START_MSDU_LEN_MSB 13 -#define TX_MSDU_START_MSDU_LEN_MASK 0x0000000000003fff - -#define TX_MSDU_START_FIRST_MSDU_OFFSET 0x0000000000000000 -#define TX_MSDU_START_FIRST_MSDU_LSB 14 -#define TX_MSDU_START_FIRST_MSDU_MSB 14 -#define TX_MSDU_START_FIRST_MSDU_MASK 0x0000000000004000 - -#define TX_MSDU_START_LAST_MSDU_OFFSET 0x0000000000000000 -#define TX_MSDU_START_LAST_MSDU_LSB 15 -#define TX_MSDU_START_LAST_MSDU_MSB 15 -#define TX_MSDU_START_LAST_MSDU_MASK 0x0000000000008000 - -#define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_ENCAP_TYPE_LSB 16 -#define TX_MSDU_START_ENCAP_TYPE_MSB 17 -#define TX_MSDU_START_ENCAP_TYPE_MASK 0x0000000000030000 - -#define TX_MSDU_START_EPD_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_EPD_EN_LSB 18 -#define TX_MSDU_START_EPD_EN_MSB 18 -#define TX_MSDU_START_EPD_EN_MASK 0x0000000000040000 - -#define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x0000000000000000 -#define TX_MSDU_START_DA_SA_PRESENT_LSB 19 -#define TX_MSDU_START_DA_SA_PRESENT_MSB 20 -#define TX_MSDU_START_DA_SA_PRESENT_MASK 0x0000000000180000 - -#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x0000000000200000 - -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000000400000 - -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000000800000 - -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000001000000 - -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000002000000 - -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x0000000000000000 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x0000000004000000 - -#define TX_MSDU_START_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_0A_LSB 27 -#define TX_MSDU_START_RESERVED_0A_MSB 31 -#define TX_MSDU_START_RESERVED_0A_MASK 0x00000000f8000000 - -#define TX_MSDU_START_TSO_ENABLE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TSO_ENABLE_LSB 32 -#define TX_MSDU_START_TSO_ENABLE_MSB 32 -#define TX_MSDU_START_TSO_ENABLE_MASK 0x0000000100000000 - -#define TX_MSDU_START_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_1A_LSB 33 -#define TX_MSDU_START_RESERVED_1A_MSB 38 -#define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e00000000 - -#define TX_MSDU_START_TCP_FLAG_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_FLAG_LSB 39 -#define TX_MSDU_START_TCP_FLAG_MSB 47 -#define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff8000000000 - -#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_FLAG_MASK_LSB 48 -#define TX_MSDU_START_TCP_FLAG_MASK_MSB 56 -#define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff000000000000 - -#define TX_MSDU_START_MESH_ENABLE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_MESH_ENABLE_LSB 57 -#define TX_MSDU_START_MESH_ENABLE_MSB 57 -#define TX_MSDU_START_MESH_ENABLE_MASK 0x0200000000000000 - -#define TX_MSDU_START_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_1B_LSB 58 -#define TX_MSDU_START_RESERVED_1B_MSB 63 -#define TX_MSDU_START_RESERVED_1B_MASK 0xfc00000000000000 - -#define TX_MSDU_START_L2_LENGTH_OFFSET 0x0000000000000008 -#define TX_MSDU_START_L2_LENGTH_LSB 0 -#define TX_MSDU_START_L2_LENGTH_MSB 15 -#define TX_MSDU_START_L2_LENGTH_MASK 0x000000000000ffff - -#define TX_MSDU_START_IP_LENGTH_OFFSET 0x0000000000000008 -#define TX_MSDU_START_IP_LENGTH_LSB 16 -#define TX_MSDU_START_IP_LENGTH_MSB 31 -#define TX_MSDU_START_IP_LENGTH_MASK 0x00000000ffff0000 - -#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000000000008 -#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 32 -#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 63 -#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 - -#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x0000000000000010 -#define TX_MSDU_START_IP_IDENTIFICATION_LSB 0 -#define TX_MSDU_START_IP_IDENTIFICATION_MSB 15 -#define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x000000000000ffff - -#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16 -#define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28 -#define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x000000001fff0000 - -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x0000000020000000 - -#define TX_MSDU_START_RESERVED_4_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_4_LSB 30 -#define TX_MSDU_START_RESERVED_4_MSB 31 -#define TX_MSDU_START_RESERVED_4_MASK 0x00000000c0000000 - -#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 32 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 45 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff00000000 - -#define TX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_5A_LSB 46 -#define TX_MSDU_START_RESERVED_5A_MSB 47 -#define TX_MSDU_START_RESERVED_5A_MASK 0x0000c00000000000 - -#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 48 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 61 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff000000000000 - -#define TX_MSDU_START_RESERVED_5B_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_5B_LSB 62 -#define TX_MSDU_START_RESERVED_5B_MSB 63 -#define TX_MSDU_START_RESERVED_5B_MASK 0xc000000000000000 - -#define TX_MSDU_START_UDP_LENGTH_OFFSET 0x0000000000000018 -#define TX_MSDU_START_UDP_LENGTH_LSB 0 -#define TX_MSDU_START_UDP_LENGTH_MSB 15 -#define TX_MSDU_START_UDP_LENGTH_MASK 0x000000000000ffff - -#define TX_MSDU_START_RESERVED_6_OFFSET 0x0000000000000018 -#define TX_MSDU_START_RESERVED_6_LSB 16 -#define TX_MSDU_START_RESERVED_6_MSB 31 -#define TX_MSDU_START_RESERVED_6_MASK 0x00000000ffff0000 - -#define TX_MSDU_START_TLV64_PADDING_OFFSET 0x0000000000000018 -#define TX_MSDU_START_TLV64_PADDING_LSB 32 -#define TX_MSDU_START_TLV64_PADDING_MSB 63 -#define TX_MSDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_peer_entry.h b/drivers/staging/fw-api/hw/fig/v1/tx_peer_entry.h deleted file mode 100644 index c26c7f6a3e05..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_peer_entry.h +++ /dev/null @@ -1,391 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_PEER_ENTRY_H_ -#define _TX_PEER_ENTRY_H_ - -#define NUM_OF_DWORDS_TX_PEER_ENTRY 22 - -#define NUM_OF_QWORDS_TX_PEER_ENTRY 11 - -struct tx_peer_entry { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mac_addr_a_31_0 : 32; - uint32_t mac_addr_a_47_32 : 16, - mac_addr_b_15_0 : 16; - uint32_t mac_addr_b_47_16 : 32; - uint32_t use_ad_b : 1, - strip_insert_vlan_inner : 1, - strip_insert_vlan_outer : 1, - vlan_llc_mode : 1, - key_type : 4, - a_msdu_wds_ad3_ad4 : 3, - ignore_hard_filters : 1, - ignore_soft_filters : 1, - epd_output : 1, - wds : 1, - insert_or_strip : 1, - sw_filter_id : 16; - uint32_t temporal_key_31_0 : 32; - uint32_t temporal_key_63_32 : 32; - uint32_t temporal_key_95_64 : 32; - uint32_t temporal_key_127_96 : 32; - uint32_t temporal_key_159_128 : 32; - uint32_t temporal_key_191_160 : 32; - uint32_t temporal_key_223_192 : 32; - uint32_t temporal_key_255_224 : 32; - uint32_t sta_partial_aid : 11, - transmit_vif : 4, - block_this_user : 1, - mesh_amsdu_mode : 2, - use_qos_alt_mute_mask : 1, - dl_ul_direction : 1, - use_ad_c : 1, - a_msdu_11s_fromtods_10_ad3 : 2, - multi_link_addr_ad3_valid : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_ad1_trans_dis : 1, - data_fromtods_00_ad3 : 2, - mgmt_fromtods_00_ad3 : 2, - reserved_12 : 1; - uint32_t insert_vlan_outer_tci : 16, - insert_vlan_inner_tci : 16; - uint32_t __reserved_g_0007 : 32; - uint32_t __reserved_g_0008 : 16, - __reserved_g_0009 : 16; - uint32_t __reserved_g_0010 : 32; - uint32_t multi_link_addr_crypto_enable : 1, - a_msdu_fromtods_10_ad3 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_11_ad4 : 2, - reserved_17a : 9, - sw_peer_id : 16; - uint32_t mac_addr_c_31_0 : 32; - uint32_t mac_addr_c_47_32 : 16, - multi_link_addr_ad3_47_32 : 16; - uint32_t multi_link_addr_ad3_31_0 : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t mac_addr_a_31_0 : 32; - uint32_t mac_addr_b_15_0 : 16, - mac_addr_a_47_32 : 16; - uint32_t mac_addr_b_47_16 : 32; - uint32_t sw_filter_id : 16, - insert_or_strip : 1, - wds : 1, - epd_output : 1, - ignore_soft_filters : 1, - ignore_hard_filters : 1, - a_msdu_wds_ad3_ad4 : 3, - key_type : 4, - vlan_llc_mode : 1, - strip_insert_vlan_outer : 1, - strip_insert_vlan_inner : 1, - use_ad_b : 1; - uint32_t temporal_key_31_0 : 32; - uint32_t temporal_key_63_32 : 32; - uint32_t temporal_key_95_64 : 32; - uint32_t temporal_key_127_96 : 32; - uint32_t temporal_key_159_128 : 32; - uint32_t temporal_key_191_160 : 32; - uint32_t temporal_key_223_192 : 32; - uint32_t temporal_key_255_224 : 32; - uint32_t reserved_12 : 1, - mgmt_fromtods_00_ad3 : 2, - data_fromtods_00_ad3 : 2, - multi_link_addr_ad1_trans_dis : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_ad3_valid : 1, - a_msdu_11s_fromtods_10_ad3 : 2, - use_ad_c : 1, - dl_ul_direction : 1, - use_qos_alt_mute_mask : 1, - mesh_amsdu_mode : 2, - block_this_user : 1, - transmit_vif : 4, - sta_partial_aid : 11; - uint32_t insert_vlan_inner_tci : 16, - insert_vlan_outer_tci : 16; - uint32_t __reserved_g_0007 : 32; - uint32_t __reserved_g_0009 : 16, - __reserved_g_0008 : 16; - uint32_t __reserved_g_0010 : 32; - uint32_t sw_peer_id : 16, - reserved_17a : 9, - a_msdu_fromtods_11_ad4 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_10_ad3 : 2, - multi_link_addr_crypto_enable : 1; - uint32_t mac_addr_c_31_0 : 32; - uint32_t multi_link_addr_ad3_47_32 : 16, - mac_addr_c_47_32 : 16; - uint32_t multi_link_addr_ad3_31_0 : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 32 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 47 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 48 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 63 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_USE_AD_B_LSB 32 -#define TX_PEER_ENTRY_USE_AD_B_MSB 32 -#define TX_PEER_ENTRY_USE_AD_B_MASK 0x0000000100000000 - -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 33 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 33 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x0000000200000000 - -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 34 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 34 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x0000000400000000 - -#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 35 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 35 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x0000000800000000 - -#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_KEY_TYPE_LSB 36 -#define TX_PEER_ENTRY_KEY_TYPE_MSB 39 -#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f000000000 - -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 40 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 42 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x0000070000000000 - -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 43 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 43 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x0000080000000000 - -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 44 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 44 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x0000100000000000 - -#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 45 -#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 45 -#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x0000200000000000 - -#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_WDS_LSB 46 -#define TX_PEER_ENTRY_WDS_MSB 46 -#define TX_PEER_ENTRY_WDS_MASK 0x0000400000000000 - -#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 47 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 47 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x0000800000000000 - -#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 48 -#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 63 -#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x0000000000000010 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x0000000000000010 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x0000000000000018 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000000000000018 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x0000000000000020 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x0000000000000020 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x0000000000000028 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000000000000028 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x00000000000007ff - -#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 -#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 -#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x0000000000007800 - -#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x0000000000008000 - -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x0000000000030000 - -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x0000000000040000 - -#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x0000000000080000 - -#define TX_PEER_ENTRY_USE_AD_C_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_USE_AD_C_LSB 20 -#define TX_PEER_ENTRY_USE_AD_C_MSB 20 -#define TX_PEER_ENTRY_USE_AD_C_MASK 0x0000000000100000 - -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_LSB 21 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MSB 22 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MASK 0x0000000000600000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_LSB 23 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MSB 23 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MASK 0x0000000000800000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 24 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 24 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x0000000001000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 25 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 25 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x0000000002000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 26 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 26 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x0000000004000000 - -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_LSB 27 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MSB 28 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MASK 0x0000000018000000 - -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_LSB 29 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MSB 30 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MASK 0x0000000060000000 - -#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_RESERVED_12_LSB 31 -#define TX_PEER_ENTRY_RESERVED_12_MSB 31 -#define TX_PEER_ENTRY_RESERVED_12_MASK 0x0000000080000000 - -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 32 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 47 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 48 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 63 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 32 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 32 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x0000000100000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_LSB 33 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MSB 34 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MASK 0x0000000600000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_LSB 35 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MSB 36 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MASK 0x0000001800000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_LSB 37 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MSB 38 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MASK 0x0000006000000000 - -#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_RESERVED_17A_LSB 39 -#define TX_PEER_ENTRY_RESERVED_17A_MSB 47 -#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000ff8000000000 - -#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_SW_PEER_ID_LSB 48 -#define TX_PEER_ENTRY_SW_PEER_ID_MSB 63 -#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_LSB 32 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MSB 47 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_LSB 48 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MSB 63 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_OFFSET 0x0000000000000050 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_LSB 0 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MSB 31 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TLV64_PADDING_OFFSET 0x0000000000000050 -#define TX_PEER_ENTRY_TLV64_PADDING_LSB 32 -#define TX_PEER_ENTRY_TLV64_PADDING_MSB 63 -#define TX_PEER_ENTRY_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_queue_extension.h b/drivers/staging/fw-api/hw/fig/v1/tx_queue_extension.h deleted file mode 100644 index 883383a9d8f2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_queue_extension.h +++ /dev/null @@ -1,411 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_QUEUE_EXTENSION_H_ -#define _TX_QUEUE_EXTENSION_H_ - -#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 18 - -#define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 9 - -struct tx_queue_extension { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t frame_ctl : 16, - qos_ctl : 16; - uint32_t ampdu_flag : 1, - tx_notify_no_htc_override : 1, - reserved_1a : 7, - checksum_tso_disable_for_frag : 1, - key_id : 8, - qos_buf_state_overwrite : 1, - buf_state_sta_id : 1, - buf_state_source : 1, - ht_control_overwrite_enable : 1, - ht_control_overwrite_source : 4, - reserved_1b : 6; - uint32_t ul_headroom_insertion_enable : 1, - ul_headroom_offset : 5, - bqrp_insertion_enable : 1, - bqrp_offset : 5, - ul_headroom_rsvd_7_6 : 2, - bqr_rsvd_9_8 : 2, - base_pn_63_48 : 16; - uint32_t base_pn_95_64 : 32; - uint32_t base_pn_127_96 : 32; - uint32_t ht_control_field_bw20 : 32; - uint32_t ht_control_field_bw40 : 32; - uint32_t ht_control_field_bw80 : 32; - uint32_t ht_control_field_bw160 : 32; - uint32_t ht_control_overwrite_mask : 32; - uint32_t cas_control_info : 8, - cas_offset : 5, - cas_insertion_enable : 1, - reserved_10a : 2, - ht_control_overwrite_source_for_srp : 4, - ht_control_overwrite_source_for_bsrp : 4, - pre_padding_fcs_overwrite_enable : 1, - reserved_10b : 5, - mpdu_hdr_len_override_en : 1, - bar_ssn_overwrite_enable : 1; - uint32_t bar_ssn_offset : 12, - mpdu_hdr_len_override_val : 9, - reserved_11a : 11; - uint32_t ht_control_field_bw320 : 32; - uint32_t fw2sw_info : 32; - uint32_t pre_padding_fcs_overwrite_offset : 16, - icf_blackout_info_offset : 16; - uint32_t trigger_common_info_length : 6, - cmf_overwrite_offset : 14, - reserved_15a : 12; - uint32_t hdr_ctrl_prot_key_id_byte_offset : 14, - hdr_ctrl_prot_key_id_bit_offset : 3, - ctrl_pkt_protect : 1, - mac_hdr_protect : 1, - hdr_ctrl_prot_tx_peer_idx : 11, - reserved_16a : 2; - uint32_t pad_byte_offset : 16, - pad_byte_offset_valid : 1, - reserved_17a : 15; -#else - uint32_t qos_ctl : 16, - frame_ctl : 16; - uint32_t reserved_1b : 6, - ht_control_overwrite_source : 4, - ht_control_overwrite_enable : 1, - buf_state_source : 1, - buf_state_sta_id : 1, - qos_buf_state_overwrite : 1, - key_id : 8, - checksum_tso_disable_for_frag : 1, - reserved_1a : 7, - tx_notify_no_htc_override : 1, - ampdu_flag : 1; - uint32_t base_pn_63_48 : 16, - bqr_rsvd_9_8 : 2, - ul_headroom_rsvd_7_6 : 2, - bqrp_offset : 5, - bqrp_insertion_enable : 1, - ul_headroom_offset : 5, - ul_headroom_insertion_enable : 1; - uint32_t base_pn_95_64 : 32; - uint32_t base_pn_127_96 : 32; - uint32_t ht_control_field_bw20 : 32; - uint32_t ht_control_field_bw40 : 32; - uint32_t ht_control_field_bw80 : 32; - uint32_t ht_control_field_bw160 : 32; - uint32_t ht_control_overwrite_mask : 32; - uint32_t bar_ssn_overwrite_enable : 1, - mpdu_hdr_len_override_en : 1, - reserved_10b : 5, - pre_padding_fcs_overwrite_enable : 1, - ht_control_overwrite_source_for_bsrp : 4, - ht_control_overwrite_source_for_srp : 4, - reserved_10a : 2, - cas_insertion_enable : 1, - cas_offset : 5, - cas_control_info : 8; - uint32_t reserved_11a : 11, - mpdu_hdr_len_override_val : 9, - bar_ssn_offset : 12; - uint32_t ht_control_field_bw320 : 32; - uint32_t fw2sw_info : 32; - uint32_t icf_blackout_info_offset : 16, - pre_padding_fcs_overwrite_offset : 16; - uint32_t reserved_15a : 12, - cmf_overwrite_offset : 14, - trigger_common_info_length : 6; - uint32_t reserved_16a : 2, - hdr_ctrl_prot_tx_peer_idx : 11, - mac_hdr_protect : 1, - ctrl_pkt_protect : 1, - hdr_ctrl_prot_key_id_bit_offset : 3, - hdr_ctrl_prot_key_id_byte_offset : 14; - uint32_t reserved_17a : 15, - pad_byte_offset_valid : 1, - pad_byte_offset : 16; -#endif -}; - -#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 -#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 -#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x000000000000ffff - -#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 -#define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 -#define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0x00000000ffff0000 - -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 32 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 32 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x0000000100000000 - -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 33 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 33 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x0000000200000000 - -#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 34 -#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 40 -#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc00000000 - -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 41 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 41 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x0000020000000000 - -#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_KEY_ID_LSB 42 -#define TX_QUEUE_EXTENSION_KEY_ID_MSB 49 -#define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc0000000000 - -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 50 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 50 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x0004000000000000 - -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 51 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 51 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x0008000000000000 - -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 52 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 52 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x0010000000000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 53 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 53 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x0020000000000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 54 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 57 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c0000000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 58 -#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc00000000000000 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x0000000000000001 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x000000000000003e - -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x0000000000000040 - -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x0000000000000f80 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x0000000000003000 - -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x000000000000c000 - -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0x00000000ffff0000 - -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 32 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 63 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x0000000000000010 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x0000000000000010 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 63 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 63 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x0000000000000020 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x0000000000000020 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 63 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x00000000000000ff - -#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x0000000000001f00 - -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x0000000000002000 - -#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 -#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 -#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x000000000000c000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x00000000000f0000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x0000000000f00000 - -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_LSB 24 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MSB 24 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MASK 0x0000000001000000 - -#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 25 -#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 -#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x000000003e000000 - -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x0000000040000000 - -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x0000000080000000 - -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 32 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 43 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff00000000 - -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 44 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 52 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff00000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 53 -#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe0000000000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x0000000000000030 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31 -#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x0000000000000030 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 32 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 63 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_LSB 0 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MSB 15 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MASK 0x000000000000ffff - -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_LSB 16 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MSB 31 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MASK 0x00000000ffff0000 - -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_LSB 32 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MSB 37 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MASK 0x0000003f00000000 - -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_LSB 38 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MSB 51 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MASK 0x000fffc000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_15A_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_RESERVED_15A_LSB 52 -#define TX_QUEUE_EXTENSION_RESERVED_15A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_15A_MASK 0xfff0000000000000 - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_LSB 0 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MSB 13 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MASK 0x0000000000003fff - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_LSB 14 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MSB 16 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MASK 0x000000000001c000 - -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_LSB 17 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MSB 17 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MASK 0x0000000000020000 - -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_LSB 18 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MSB 18 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MASK 0x0000000000040000 - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_LSB 19 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MSB 29 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MASK 0x000000003ff80000 - -#define TX_QUEUE_EXTENSION_RESERVED_16A_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_RESERVED_16A_LSB 30 -#define TX_QUEUE_EXTENSION_RESERVED_16A_MSB 31 -#define TX_QUEUE_EXTENSION_RESERVED_16A_MASK 0x00000000c0000000 - -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_LSB 32 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MSB 47 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MASK 0x0000ffff00000000 - -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_LSB 48 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MSB 48 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MASK 0x0001000000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_17A_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_RESERVED_17A_LSB 49 -#define TX_QUEUE_EXTENSION_RESERVED_17A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_17A_MASK 0xfffe000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_rate_stats_info.h b/drivers/staging/fw-api/hw/fig/v1/tx_rate_stats_info.h deleted file mode 100644 index ce84032dd353..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_rate_stats_info.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_RATE_STATS_INFO_H_ -#define _TX_RATE_STATS_INFO_H_ - -#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 - -struct tx_rate_stats_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_rate_stats_info_valid : 1, - transmit_bw : 3, - transmit_pkt_type : 4, - transmit_stbc : 1, - transmit_ldpc : 1, - transmit_sgi : 2, - transmit_mcs : 5, - unequal_modulation_info : 3, - ofdma_transmission : 1, - reserved_0a : 4, - tones_in_ru : 4, - transmit_nss : 3; - uint32_t ppdu_transmission_tsf : 32; -#else - uint32_t transmit_nss : 3, - tones_in_ru : 4, - reserved_0a : 4, - ofdma_transmission : 1, - unequal_modulation_info : 3, - transmit_mcs : 5, - transmit_sgi : 2, - transmit_ldpc : 1, - transmit_stbc : 1, - transmit_pkt_type : 4, - transmit_bw : 3, - tx_rate_stats_info_valid : 1; - uint32_t ppdu_transmission_tsf : 32; -#endif -}; - -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB 0 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB 0 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 - -#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB 1 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB 3 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK 0x0000000e - -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB 4 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB 7 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK 0x000000f0 - -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB 8 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB 8 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK 0x00000100 - -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB 9 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB 9 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK 0x00000200 - -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB 10 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB 11 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK 0x00000c00 - -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB 12 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB 16 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK 0x0001f000 - -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_LSB 17 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MSB 19 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MASK 0x000e0000 - -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB 20 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB 20 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK 0x00100000 - -#define TX_RATE_STATS_INFO_RESERVED_0A_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_RESERVED_0A_LSB 21 -#define TX_RATE_STATS_INFO_RESERVED_0A_MSB 24 -#define TX_RATE_STATS_INFO_RESERVED_0A_MASK 0x01e00000 - -#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB 25 -#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB 28 -#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK 0x1e000000 - -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_LSB 29 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MSB 31 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MASK 0xe0000000 - -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB 0 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB 31 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/tx_raw_or_native_frame_setup.h b/drivers/staging/fw-api/hw/fig/v1/tx_raw_or_native_frame_setup.h deleted file mode 100644 index 220a82edf96d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/tx_raw_or_native_frame_setup.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ -#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ - -#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 4 - -#define NUM_OF_QWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2 - -struct tx_raw_or_native_frame_setup { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t fc_to_ds_mask : 1, - fc_from_ds_mask : 1, - fc_more_frag_mask : 1, - fc_retry_mask : 1, - fc_pwr_mgt_mask : 1, - fc_more_data_mask : 1, - fc_prot_frame_mask : 1, - fc_order_mask : 1, - duration_field_mask : 1, - sequence_control_mask : 1, - qc_tid_mask : 1, - qc_eosp_mask : 1, - qc_ack_policy_mask : 1, - qc_amsdu_mask : 1, - reserved_0a : 1, - qc_15to8_mask : 1, - iv_mask : 1, - fc_to_ds_setting : 1, - fc_from_ds_setting : 1, - fc_more_frag_setting : 1, - fc_retry_setting : 2, - fc_pwr_mgt_setting : 1, - fc_more_data_setting : 2, - fc_prot_frame_setting : 2, - fc_order_setting : 1, - qc_tid_setting : 4; - uint32_t qc_eosp_setting : 2, - qc_ack_policy_setting : 2, - qc_amsdu_setting : 1, - qc_15to8_setting : 8, - mlo_addr_override : 1, - mlo_ignore_addr3_override : 1, - sequence_control_source : 1, - fragment_number : 4, - sequence_number : 12; - uint32_t mlo_addr_override_for_ctrl : 1, - reserved_2a : 31; - uint32_t tlv64_padding : 32; -#else - uint32_t qc_tid_setting : 4, - fc_order_setting : 1, - fc_prot_frame_setting : 2, - fc_more_data_setting : 2, - fc_pwr_mgt_setting : 1, - fc_retry_setting : 2, - fc_more_frag_setting : 1, - fc_from_ds_setting : 1, - fc_to_ds_setting : 1, - iv_mask : 1, - qc_15to8_mask : 1, - reserved_0a : 1, - qc_amsdu_mask : 1, - qc_ack_policy_mask : 1, - qc_eosp_mask : 1, - qc_tid_mask : 1, - sequence_control_mask : 1, - duration_field_mask : 1, - fc_order_mask : 1, - fc_prot_frame_mask : 1, - fc_more_data_mask : 1, - fc_pwr_mgt_mask : 1, - fc_retry_mask : 1, - fc_more_frag_mask : 1, - fc_from_ds_mask : 1, - fc_to_ds_mask : 1; - uint32_t sequence_number : 12, - fragment_number : 4, - sequence_control_source : 1, - mlo_ignore_addr3_override : 1, - mlo_addr_override : 1, - qc_15to8_setting : 8, - qc_amsdu_setting : 1, - qc_ack_policy_setting : 2, - qc_eosp_setting : 2; - uint32_t reserved_2a : 31, - mlo_addr_override_for_ctrl : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK 0x0000000000000001 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK 0x0000000000000002 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB 2 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB 2 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK 0x0000000000000004 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB 3 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB 3 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK 0x0000000000000008 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB 4 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB 4 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK 0x0000000000000010 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB 5 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB 5 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK 0x0000000000000020 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB 6 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB 6 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK 0x0000000000000040 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB 7 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB 7 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK 0x0000000000000080 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB 8 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB 8 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK 0x0000000000000100 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB 9 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB 9 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK 0x0000000000000200 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB 10 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB 10 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK 0x0000000000000400 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB 11 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB 11 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK 0x0000000000000800 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB 12 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB 12 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK 0x0000000000001000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB 13 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB 13 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK 0x0000000000002000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB 14 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB 14 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK 0x0000000000004000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB 15 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB 15 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK 0x0000000000008000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB 16 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB 16 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK 0x0000000000010000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB 17 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB 17 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK 0x0000000000020000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB 18 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB 18 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK 0x0000000000040000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB 19 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB 19 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK 0x0000000000080000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB 20 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB 21 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK 0x0000000000300000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB 22 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB 22 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK 0x0000000000400000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB 23 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB 24 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK 0x0000000001800000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB 25 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB 26 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK 0x0000000006000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB 27 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB 27 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK 0x0000000008000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB 28 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB 31 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK 0x00000000f0000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB 32 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB 33 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK 0x0000000300000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB 34 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB 35 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK 0x0000000c00000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB 36 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB 36 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK 0x0000001000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB 37 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB 44 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK 0x00001fe000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB 45 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB 45 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK 0x0000200000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB 46 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB 46 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK 0x0000400000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB 47 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB 47 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK 0x0000800000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB 48 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB 51 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK 0x000f000000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB 52 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB 63 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK 0xfff0000000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_LSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MASK 0x0000000000000001 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_LSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MSB 31 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MASK 0x00000000fffffffe - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_LSB 32 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MSB 63 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/txpcu_buffer_basics.h b/drivers/staging/fw-api/hw/fig/v1/txpcu_buffer_basics.h deleted file mode 100644 index 4032a78ad617..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/txpcu_buffer_basics.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_BUFFER_BASICS_H_ -#define _TXPCU_BUFFER_BASICS_H_ - -#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1 - -struct txpcu_buffer_basics { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t available_memory : 8, - partial_tx_data_tlv_count : 8, - tx_data_tlv_count : 16; -#else - uint32_t tx_data_tlv_count : 16, - partial_tx_data_tlv_count : 8, - available_memory : 8; -#endif -}; - -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK 0x000000ff - -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 - -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/txpcu_buffer_status.h b/drivers/staging/fw-api/hw/fig/v1/txpcu_buffer_status.h deleted file mode 100644 index 847ca277267d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/txpcu_buffer_status.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_BUFFER_STATUS_H_ -#define _TXPCU_BUFFER_STATUS_H_ - -#include "txpcu_buffer_basics.h" -#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2 - -#define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1 - -struct txpcu_buffer_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct txpcu_buffer_basics txpcu_basix_buffer_info; - uint32_t reserved : 15, - msdu_end : 1, - tx_data_sync_value : 16; -#else - struct txpcu_buffer_basics txpcu_basix_buffer_info; - uint32_t tx_data_sync_value : 16, - msdu_end : 1, - reserved : 15; -#endif -}; - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 - -#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_RESERVED_LSB 32 -#define TXPCU_BUFFER_STATUS_RESERVED_MSB 46 -#define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff00000000 - -#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_MSDU_END_LSB 47 -#define TXPCU_BUFFER_STATUS_MSDU_END_MSB 47 -#define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 - -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/txpcu_user_buffer_status.h b/drivers/staging/fw-api/hw/fig/v1/txpcu_user_buffer_status.h deleted file mode 100644 index f6ad0fd73721..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/txpcu_user_buffer_status.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_USER_BUFFER_STATUS_H_ -#define _TXPCU_USER_BUFFER_STATUS_H_ - -#include "txpcu_buffer_basics.h" -#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2 - -#define NUM_OF_QWORDS_TXPCU_USER_BUFFER_STATUS 1 - -struct txpcu_user_buffer_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct txpcu_buffer_basics txpcu_basic_buffer_info; - uint32_t stored_word_count_user : 14, - reserved_1a : 1, - msdu_end : 1, - tx_data_sync_value : 16; -#else - struct txpcu_buffer_basics txpcu_basic_buffer_info; - uint32_t tx_data_sync_value : 16, - msdu_end : 1, - reserved_1a : 1, - stored_word_count_user : 14; -#endif -}; - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 - -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB 32 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB 45 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK 0x00003fff00000000 - -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB 46 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB 46 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK 0x0000400000000000 - -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB 47 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB 47 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 - -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/u_sig_eht_su_mu_info.h b/drivers/staging/fw-api/hw/fig/v1/u_sig_eht_su_mu_info.h deleted file mode 100644 index 1a08f3ab39b2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/u_sig_eht_su_mu_info.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _U_SIG_EHT_SU_MU_INFO_H_ -#define _U_SIG_EHT_SU_MU_INFO_H_ - -#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 - -struct u_sig_eht_su_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_version : 3, - transmit_bw : 3, - dl_ul_flag : 1, - bss_color_id : 6, - txop_duration : 7, - disregard_0a : 5, - validate_0b : 1, - reserved_0c : 6; - uint32_t eht_ppdu_sig_cmn_type : 2, - validate_1a : 1, - punctured_channel_information : 5, - validate_1b : 1, - mcs_of_eht_sig : 2, - num_eht_sig_symbols : 5, - crc : 4, - tail : 6, - dot11ax_su_extended : 1, - reserved_1d : 3, - rx_ndp : 1, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0c : 6, - validate_0b : 1, - disregard_0a : 5, - txop_duration : 7, - bss_color_id : 6, - dl_ul_flag : 1, - transmit_bw : 3, - phy_version : 3; - uint32_t rx_integrity_check_passed : 1, - rx_ndp : 1, - reserved_1d : 3, - dot11ax_su_extended : 1, - tail : 6, - crc : 4, - num_eht_sig_symbols : 5, - mcs_of_eht_sig : 2, - validate_1b : 1, - punctured_channel_information : 5, - validate_1a : 1, - eht_ppdu_sig_cmn_type : 2; -#endif -}; - -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 - -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 - -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 - -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 - -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 - -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 - -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 - -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 - -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 - -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 - -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 - -#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 -#define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 -#define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 - -#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 -#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 -#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 - -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 - -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 - -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 - -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/u_sig_eht_tb_info.h b/drivers/staging/fw-api/hw/fig/v1/u_sig_eht_tb_info.h deleted file mode 100644 index 8e417b38d233..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/u_sig_eht_tb_info.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _U_SIG_EHT_TB_INFO_H_ -#define _U_SIG_EHT_TB_INFO_H_ - -#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2 - -struct u_sig_eht_tb_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_version : 3, - transmit_bw : 3, - dl_ul_flag : 1, - bss_color_id : 6, - txop_duration : 7, - disregard_0a : 6, - reserved_0c : 6; - uint32_t eht_ppdu_sig_cmn_type : 2, - validate_1a : 1, - spatial_reuse : 8, - disregard_1b : 5, - crc : 4, - tail : 6, - reserved_1c : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0c : 6, - disregard_0a : 6, - txop_duration : 7, - bss_color_id : 6, - dl_ul_flag : 1, - transmit_bw : 3, - phy_version : 3; - uint32_t rx_integrity_check_passed : 1, - reserved_1c : 5, - tail : 6, - crc : 4, - disregard_1b : 5, - spatial_reuse : 8, - validate_1a : 1, - eht_ppdu_sig_cmn_type : 2; -#endif -}; - -#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007 - -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038 - -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040 - -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80 - -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000 - -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000 - -#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000 - -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 - -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004 - -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8 - -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800 - -#define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_CRC_LSB 16 -#define U_SIG_EHT_TB_INFO_CRC_MSB 19 -#define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000 - -#define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_TAIL_LSB 20 -#define U_SIG_EHT_TB_INFO_TAIL_MSB 25 -#define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000 - -#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000 - -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/unallocated_ru_160_info.h b/drivers/staging/fw-api/hw/fig/v1/unallocated_ru_160_info.h deleted file mode 100644 index ccd4a7bab9ad..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/unallocated_ru_160_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _UNALLOCATED_RU_160_INFO_H_ -#define _UNALLOCATED_RU_160_INFO_H_ - -#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1 - -struct unallocated_ru_160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t subband80_0_cc0 : 8, - subband80_0_cc1 : 8, - subband80_1_cc0 : 8, - subband80_1_cc1 : 8; -#else - uint32_t subband80_1_cc1 : 8, - subband80_1_cc0 : 8, - subband80_0_cc1 : 8, - subband80_0_cc0 : 8; -#endif -}; - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB 0 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB 7 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK 0x000000ff - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB 8 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB 15 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK 0x0000ff00 - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB 16 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB 23 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK 0x00ff0000 - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB 24 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB 31 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/uniform_descriptor_header.h b/drivers/staging/fw-api/hw/fig/v1/uniform_descriptor_header.h deleted file mode 100644 index 7a2de6ccd8df..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/uniform_descriptor_header.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ -#define _UNIFORM_DESCRIPTOR_HEADER_H_ - -#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 - -struct uniform_descriptor_header { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t owner : 4, - buffer_type : 4, - tx_mpdu_queue_number : 20, - reserved_0a : 4; -#else - uint32_t reserved_0a : 4, - tx_mpdu_queue_number : 20, - buffer_type : 4, - owner : 4; -#endif -}; - -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f - -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 - -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 - -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_a_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_a_info.h deleted file mode 100644 index acd20f43949e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_a_info.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_A_INFO_H_ -#define _VHT_SIG_A_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2 - -struct vht_sig_a_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t bandwidth : 2, - vhta_reserved_0 : 1, - stbc : 1, - group_id : 6, - n_sts : 12, - txop_ps_not_allowed : 1, - vhta_reserved_0b : 1, - reserved_0 : 8; - uint32_t gi_setting : 2, - su_mu_coding : 1, - ldpc_extra_symbol : 1, - mcs : 4, - beamformed : 1, - vhta_reserved_1 : 1, - crc : 8, - tail : 6, - reserved_1 : 7, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0 : 8, - vhta_reserved_0b : 1, - txop_ps_not_allowed : 1, - n_sts : 12, - group_id : 6, - stbc : 1, - vhta_reserved_0 : 1, - bandwidth : 2; - uint32_t rx_integrity_check_passed : 1, - reserved_1 : 7, - tail : 6, - crc : 8, - vhta_reserved_1 : 1, - beamformed : 1, - mcs : 4, - ldpc_extra_symbol : 1, - su_mu_coding : 1, - gi_setting : 2; -#endif -}; - -#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_BANDWIDTH_LSB 0 -#define VHT_SIG_A_INFO_BANDWIDTH_MSB 1 -#define VHT_SIG_A_INFO_BANDWIDTH_MASK 0x00000003 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB 2 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB 2 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK 0x00000004 - -#define VHT_SIG_A_INFO_STBC_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_STBC_LSB 3 -#define VHT_SIG_A_INFO_STBC_MSB 3 -#define VHT_SIG_A_INFO_STBC_MASK 0x00000008 - -#define VHT_SIG_A_INFO_GROUP_ID_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_GROUP_ID_LSB 4 -#define VHT_SIG_A_INFO_GROUP_ID_MSB 9 -#define VHT_SIG_A_INFO_GROUP_ID_MASK 0x000003f0 - -#define VHT_SIG_A_INFO_N_STS_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_N_STS_LSB 10 -#define VHT_SIG_A_INFO_N_STS_MSB 21 -#define VHT_SIG_A_INFO_N_STS_MASK 0x003ffc00 - -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB 22 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB 22 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB 23 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB 23 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK 0x00800000 - -#define VHT_SIG_A_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_RESERVED_0_LSB 24 -#define VHT_SIG_A_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_A_INFO_RESERVED_0_MASK 0xff000000 - -#define VHT_SIG_A_INFO_GI_SETTING_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_GI_SETTING_LSB 0 -#define VHT_SIG_A_INFO_GI_SETTING_MSB 1 -#define VHT_SIG_A_INFO_GI_SETTING_MASK 0x00000003 - -#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_SU_MU_CODING_LSB 2 -#define VHT_SIG_A_INFO_SU_MU_CODING_MSB 2 -#define VHT_SIG_A_INFO_SU_MU_CODING_MASK 0x00000004 - -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB 3 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB 3 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000008 - -#define VHT_SIG_A_INFO_MCS_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_MCS_LSB 4 -#define VHT_SIG_A_INFO_MCS_MSB 7 -#define VHT_SIG_A_INFO_MCS_MASK 0x000000f0 - -#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_BEAMFORMED_LSB 8 -#define VHT_SIG_A_INFO_BEAMFORMED_MSB 8 -#define VHT_SIG_A_INFO_BEAMFORMED_MASK 0x00000100 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB 9 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB 9 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK 0x00000200 - -#define VHT_SIG_A_INFO_CRC_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_CRC_LSB 10 -#define VHT_SIG_A_INFO_CRC_MSB 17 -#define VHT_SIG_A_INFO_CRC_MASK 0x0003fc00 - -#define VHT_SIG_A_INFO_TAIL_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_TAIL_LSB 18 -#define VHT_SIG_A_INFO_TAIL_MSB 23 -#define VHT_SIG_A_INFO_TAIL_MASK 0x00fc0000 - -#define VHT_SIG_A_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_RESERVED_1_LSB 24 -#define VHT_SIG_A_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_A_INFO_RESERVED_1_MASK 0x7f000000 - -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu160_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu160_info.h deleted file mode 100644 index 13931c5c3556..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu160_info.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU160_INFO_H_ -#define _VHT_SIG_B_MU160_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8 - -struct vht_sig_b_mu160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - mcs : 4, - tail : 6, - reserved_0 : 3; - uint32_t length_copy_a : 19, - mcs_copy_a : 4, - tail_copy_a : 6, - reserved_1 : 3; - uint32_t length_copy_b : 19, - mcs_copy_b : 4, - tail_copy_b : 6, - reserved_2 : 3; - uint32_t length_copy_c : 19, - mcs_copy_c : 4, - tail_copy_c : 6, - reserved_3 : 3; - uint32_t length_copy_d : 19, - mcs_copy_d : 4, - tail_copy_d : 6, - reserved_4 : 3; - uint32_t length_copy_e : 19, - mcs_copy_e : 4, - tail_copy_e : 6, - reserved_5 : 3; - uint32_t length_copy_f : 19, - mcs_copy_f : 4, - tail_copy_f : 6, - mu_user_number : 3; - uint32_t length_copy_g : 19, - mcs_copy_g : 4, - tail_copy_g : 6, - reserved_7 : 3; -#else - uint32_t reserved_0 : 3, - tail : 6, - mcs : 4, - length : 19; - uint32_t reserved_1 : 3, - tail_copy_a : 6, - mcs_copy_a : 4, - length_copy_a : 19; - uint32_t reserved_2 : 3, - tail_copy_b : 6, - mcs_copy_b : 4, - length_copy_b : 19; - uint32_t reserved_3 : 3, - tail_copy_c : 6, - mcs_copy_c : 4, - length_copy_c : 19; - uint32_t reserved_4 : 3, - tail_copy_d : 6, - mcs_copy_d : 4, - length_copy_d : 19; - uint32_t reserved_5 : 3, - tail_copy_e : 6, - mcs_copy_e : 4, - length_copy_e : 19; - uint32_t mu_user_number : 3, - tail_copy_f : 6, - mcs_copy_f : 4, - length_copy_f : 19; - uint32_t reserved_7 : 3, - tail_copy_g : 6, - mcs_copy_g : 4, - length_copy_g : 19; -#endif -}; - -#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_MCS_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_TAIL_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu20_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu20_info.h deleted file mode 100644 index c51ac839a757..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu20_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU20_INFO_H_ -#define _VHT_SIG_B_MU20_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1 - -struct vht_sig_b_mu20_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 16, - mcs : 4, - tail : 6, - mu_user_number : 3, - reserved_0 : 3; -#else - uint32_t reserved_0 : 3, - mu_user_number : 3, - tail : 6, - mcs : 4, - length : 16; -#endif -}; - -#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU20_INFO_LENGTH_MSB 15 -#define VHT_SIG_B_MU20_INFO_LENGTH_MASK 0x0000ffff - -#define VHT_SIG_B_MU20_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_MCS_LSB 16 -#define VHT_SIG_B_MU20_INFO_MCS_MSB 19 -#define VHT_SIG_B_MU20_INFO_MCS_MASK 0x000f0000 - -#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_TAIL_LSB 20 -#define VHT_SIG_B_MU20_INFO_TAIL_MSB 25 -#define VHT_SIG_B_MU20_INFO_TAIL_MASK 0x03f00000 - -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB 26 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB 28 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK 0x1c000000 - -#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu40_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu40_info.h deleted file mode 100644 index 0eb4c164cca1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu40_info.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU40_INFO_H_ -#define _VHT_SIG_B_MU40_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2 - -struct vht_sig_b_mu40_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 17, - mcs : 4, - tail : 6, - reserved_0 : 2, - mu_user_number : 3; - uint32_t length_copy : 17, - mcs_copy : 4, - tail_copy : 6, - reserved_1 : 5; -#else - uint32_t mu_user_number : 3, - reserved_0 : 2, - tail : 6, - mcs : 4, - length : 17; - uint32_t reserved_1 : 5, - tail_copy : 6, - mcs_copy : 4, - length_copy : 17; -#endif -}; - -#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU40_INFO_LENGTH_MSB 16 -#define VHT_SIG_B_MU40_INFO_LENGTH_MASK 0x0001ffff - -#define VHT_SIG_B_MU40_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_MCS_LSB 17 -#define VHT_SIG_B_MU40_INFO_MCS_MSB 20 -#define VHT_SIG_B_MU40_INFO_MCS_MASK 0x001e0000 - -#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_TAIL_LSB 21 -#define VHT_SIG_B_MU40_INFO_TAIL_MSB 26 -#define VHT_SIG_B_MU40_INFO_TAIL_MASK 0x07e00000 - -#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB 27 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB 28 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK 0x18000000 - -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB 0 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB 16 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK 0x0001ffff - -#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB 17 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB 20 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK 0x001e0000 - -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB 21 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB 26 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK 0x07e00000 - -#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB 27 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK 0xf8000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu80_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu80_info.h deleted file mode 100644 index 33d0f1bc08fc..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_mu80_info.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU80_INFO_H_ -#define _VHT_SIG_B_MU80_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4 - -struct vht_sig_b_mu80_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - mcs : 4, - tail : 6, - reserved_0 : 3; - uint32_t length_copy_a : 19, - mcs_copy_a : 4, - tail_copy_a : 6, - reserved_1 : 3; - uint32_t length_copy_b : 19, - mcs_copy_b : 4, - tail_copy_b : 6, - mu_user_number : 3; - uint32_t length_copy_c : 19, - mcs_copy_c : 4, - tail_copy_c : 6, - reserved_3 : 3; -#else - uint32_t reserved_0 : 3, - tail : 6, - mcs : 4, - length : 19; - uint32_t reserved_1 : 3, - tail_copy_a : 6, - mcs_copy_a : 4, - length_copy_a : 19; - uint32_t mu_user_number : 3, - tail_copy_b : 6, - mcs_copy_b : 4, - length_copy_b : 19; - uint32_t reserved_3 : 3, - tail_copy_c : 6, - mcs_copy_c : 4, - length_copy_c : 19; -#endif -}; - -#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_MCS_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_TAIL_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su160_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su160_info.h deleted file mode 100644 index 7ba503724b56..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su160_info.h +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU160_INFO_H_ -#define _VHT_SIG_B_SU160_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8 - -struct vht_sig_b_su160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 21, - vhtb_reserved : 2, - tail : 6, - reserved_0 : 2, - rx_ndp : 1; - uint32_t length_copy_a : 21, - vhtb_reserved_copy_a : 2, - tail_copy_a : 6, - reserved_1 : 2, - rx_ndp_copy_a : 1; - uint32_t length_copy_b : 21, - vhtb_reserved_copy_b : 2, - tail_copy_b : 6, - reserved_2 : 2, - rx_ndp_copy_b : 1; - uint32_t length_copy_c : 21, - vhtb_reserved_copy_c : 2, - tail_copy_c : 6, - reserved_3 : 2, - rx_ndp_copy_c : 1; - uint32_t length_copy_d : 21, - vhtb_reserved_copy_d : 2, - tail_copy_d : 6, - reserved_4 : 2, - rx_ndp_copy_d : 1; - uint32_t length_copy_e : 21, - vhtb_reserved_copy_e : 2, - tail_copy_e : 6, - reserved_5 : 2, - rx_ndp_copy_e : 1; - uint32_t length_copy_f : 21, - vhtb_reserved_copy_f : 2, - tail_copy_f : 6, - reserved_6 : 2, - rx_ndp_copy_f : 1; - uint32_t length_copy_g : 21, - vhtb_reserved_copy_g : 2, - tail_copy_g : 6, - reserved_7 : 2, - rx_ndp_copy_g : 1; -#else - uint32_t rx_ndp : 1, - reserved_0 : 2, - tail : 6, - vhtb_reserved : 2, - length : 21; - uint32_t rx_ndp_copy_a : 1, - reserved_1 : 2, - tail_copy_a : 6, - vhtb_reserved_copy_a : 2, - length_copy_a : 21; - uint32_t rx_ndp_copy_b : 1, - reserved_2 : 2, - tail_copy_b : 6, - vhtb_reserved_copy_b : 2, - length_copy_b : 21; - uint32_t rx_ndp_copy_c : 1, - reserved_3 : 2, - tail_copy_c : 6, - vhtb_reserved_copy_c : 2, - length_copy_c : 21; - uint32_t rx_ndp_copy_d : 1, - reserved_4 : 2, - tail_copy_d : 6, - vhtb_reserved_copy_d : 2, - length_copy_d : 21; - uint32_t rx_ndp_copy_e : 1, - reserved_5 : 2, - tail_copy_e : 6, - vhtb_reserved_copy_e : 2, - length_copy_e : 21; - uint32_t rx_ndp_copy_f : 1, - reserved_6 : 2, - tail_copy_f : 6, - vhtb_reserved_copy_f : 2, - length_copy_f : 21; - uint32_t rx_ndp_copy_g : 1, - reserved_7 : 2, - tail_copy_g : 6, - vhtb_reserved_copy_g : 2, - length_copy_g : 21; -#endif -}; - -#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_TAIL_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su20_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su20_info.h deleted file mode 100644 index 2c7f11ba3c21..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su20_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU20_INFO_H_ -#define _VHT_SIG_B_SU20_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1 - -struct vht_sig_b_su20_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 17, - vhtb_reserved : 3, - tail : 6, - reserved : 5, - rx_ndp : 1; -#else - uint32_t rx_ndp : 1, - reserved : 5, - tail : 6, - vhtb_reserved : 3, - length : 17; -#endif -}; - -#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU20_INFO_LENGTH_MSB 16 -#define VHT_SIG_B_SU20_INFO_LENGTH_MASK 0x0001ffff - -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB 17 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB 19 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK 0x000e0000 - -#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_TAIL_LSB 20 -#define VHT_SIG_B_SU20_INFO_TAIL_MSB 25 -#define VHT_SIG_B_SU20_INFO_TAIL_MASK 0x03f00000 - -#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_RESERVED_LSB 26 -#define VHT_SIG_B_SU20_INFO_RESERVED_MSB 30 -#define VHT_SIG_B_SU20_INFO_RESERVED_MASK 0x7c000000 - -#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su40_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su40_info.h deleted file mode 100644 index 467259003e8d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su40_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU40_INFO_H_ -#define _VHT_SIG_B_SU40_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2 - -struct vht_sig_b_su40_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - vhtb_reserved : 2, - tail : 6, - reserved : 4, - rx_ndp : 1; - uint32_t length_copy : 19, - vhtb_reserved_copy : 2, - tail_copy : 6, - reserved_copy : 4, - rx_ndp_copy : 1; -#else - uint32_t rx_ndp : 1, - reserved : 4, - tail : 6, - vhtb_reserved : 2, - length : 19; - uint32_t rx_ndp_copy : 1, - reserved_copy : 4, - tail_copy : 6, - vhtb_reserved_copy : 2, - length_copy : 19; -#endif -}; - -#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU40_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_SU40_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB 19 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB 20 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK 0x00180000 - -#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_TAIL_LSB 21 -#define VHT_SIG_B_SU40_INFO_TAIL_MSB 26 -#define VHT_SIG_B_SU40_INFO_TAIL_MASK 0x07e00000 - -#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_RESERVED_LSB 27 -#define VHT_SIG_B_SU40_INFO_RESERVED_MSB 30 -#define VHT_SIG_B_SU40_INFO_RESERVED_MASK 0x78000000 - -#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB 0 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB 18 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK 0x0007ffff - -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB 19 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB 20 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK 0x00180000 - -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB 21 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB 26 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK 0x07e00000 - -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB 27 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB 30 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK 0x78000000 - -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su80_info.h b/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su80_info.h deleted file mode 100644 index 92ceeab9b476..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/vht_sig_b_su80_info.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU80_INFO_H_ -#define _VHT_SIG_B_SU80_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4 - -struct vht_sig_b_su80_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 21, - vhtb_reserved : 2, - tail : 6, - reserved_0 : 2, - rx_ndp : 1; - uint32_t length_copy_a : 21, - vhtb_reserved_copy_a : 2, - tail_copy_a : 6, - reserved_1 : 2, - rx_ndp_copy_a : 1; - uint32_t length_copy_b : 21, - vhtb_reserved_copy_b : 2, - tail_copy_b : 6, - reserved_2 : 2, - rx_ndp_copy_b : 1; - uint32_t length_copy_c : 21, - vhtb_reserved_copy_c : 2, - tail_copy_c : 6, - reserved_3 : 2, - rx_ndp_copy_c : 1; -#else - uint32_t rx_ndp : 1, - reserved_0 : 2, - tail : 6, - vhtb_reserved : 2, - length : 21; - uint32_t rx_ndp_copy_a : 1, - reserved_1 : 2, - tail_copy_a : 6, - vhtb_reserved_copy_a : 2, - length_copy_a : 21; - uint32_t rx_ndp_copy_b : 1, - reserved_2 : 2, - tail_copy_b : 6, - vhtb_reserved_copy_b : 2, - length_copy_b : 21; - uint32_t rx_ndp_copy_c : 1, - reserved_3 : 2, - tail_copy_c : 6, - vhtb_reserved_copy_c : 2, - length_copy_c : 21; -#endif -}; - -#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_TAIL_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wbm2sw_completion_ring_rx.h b/drivers/staging/fw-api/hw/fig/v1/wbm2sw_completion_ring_rx.h deleted file mode 100644 index e40a7e796a87..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wbm2sw_completion_ring_rx.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM2SW_COMPLETION_RING_RX_H_ -#define _WBM2SW_COMPLETION_RING_RX_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_mpdu_desc_info.h" -#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 - -struct wbm2sw_completion_ring_rx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t release_source_module : 3, - bm_action : 3, - buffer_or_desc_type : 3, - return_buffer_manager : 4, - reserved_2a : 2, - cache_id : 1, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_push_reason : 2, - reo_error_code : 5, - wbm_internal_error : 1; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t buffer_phys_addr_31_0 : 32; - uint32_t buffer_phys_addr_39_32 : 8, - sw_buffer_cookie : 20, - looping_count : 4; -#else - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t wbm_internal_error : 1, - reo_error_code : 5, - reo_push_reason : 2, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - cache_id : 1, - reserved_2a : 2, - return_buffer_manager : 4, - buffer_or_desc_type : 3, - bm_action : 3, - release_source_module : 3; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t buffer_phys_addr_31_0 : 32; - uint32_t looping_count : 4, - sw_buffer_cookie : 20, - buffer_phys_addr_39_32 : 8; -#endif -}; - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 - -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 - -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 - -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 - -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 - -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 - -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 - -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 - -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff - -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 - -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wbm_buffer_ring.h b/drivers/staging/fw-api/hw/fig/v1/wbm_buffer_ring.h deleted file mode 100644 index b1532e15595b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wbm_buffer_ring.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_BUFFER_RING_H_ -#define _WBM_BUFFER_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 - -struct wbm_buffer_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_addr_info; -#else - struct buffer_addr_info buf_addr_info; -#endif -}; - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wbm_link_descriptor_ring.h b/drivers/staging/fw-api/hw/fig/v1/wbm_link_descriptor_ring.h deleted file mode 100644 index 851807aa4c1c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wbm_link_descriptor_ring.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ -#define _WBM_LINK_DESCRIPTOR_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 - -struct wbm_link_descriptor_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info desc_addr_info; -#else - struct buffer_addr_info desc_addr_info; -#endif -}; - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring.h b/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring.h deleted file mode 100644 index e86d52753912..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_H_ -#define _WBM_RELEASE_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 - -struct wbm_release_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - reserved_2a : 3, - buffer_or_desc_type : 3, - reserved_2b : 22, - wbm_internal_error : 1; - uint32_t reserved_3a : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_5a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 28, - looping_count : 4; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t wbm_internal_error : 1, - reserved_2b : 22, - buffer_or_desc_type : 3, - reserved_2a : 3, - release_source_module : 3; - uint32_t reserved_3a : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_5a : 32; - uint32_t reserved_6a : 32; - uint32_t looping_count : 4, - reserved_7a : 28; -#endif -}; - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RESERVED_2A_LSB 3 -#define WBM_RELEASE_RING_RESERVED_2A_MSB 5 -#define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 - -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RESERVED_2B_LSB 9 -#define WBM_RELEASE_RING_RESERVED_2B_MSB 30 -#define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 - -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 - -#define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c -#define WBM_RELEASE_RING_RESERVED_3A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_3A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 -#define WBM_RELEASE_RING_RESERVED_4A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_4A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 -#define WBM_RELEASE_RING_RESERVED_5A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_5A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 -#define WBM_RELEASE_RING_RESERVED_6A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_6A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c -#define WBM_RELEASE_RING_RESERVED_7A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_7A_MSB 27 -#define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff - -#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 -#define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 -#define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring_rx.h b/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring_rx.h deleted file mode 100644 index a68bc8115a82..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring_rx.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_RX_H_ -#define _WBM_RELEASE_RING_RX_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 4 - -struct wbm_release_ring_rx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - buffer_or_desc_type : 3, - reserved_2a : 14, - mpdu_sequence_number : 12; - uint32_t reserved_3a : 32; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t mpdu_sequence_number : 12, - reserved_2a : 14, - buffer_or_desc_type : 3, - release_source_module : 3; - uint32_t reserved_3a : 32; -#endif -}; - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB 3 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB 5 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x00000038 - -#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB 6 -#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB 19 -#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK 0x000fffc0 - -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_LSB 20 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MSB 31 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 - -#define WBM_RELEASE_RING_RX_RESERVED_3A_OFFSET 0x0000000c -#define WBM_RELEASE_RING_RX_RESERVED_3A_LSB 0 -#define WBM_RELEASE_RING_RX_RESERVED_3A_MSB 31 -#define WBM_RELEASE_RING_RX_RESERVED_3A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring_tx.h b/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring_tx.h deleted file mode 100644 index d1412153c6ae..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wbm_release_ring_tx.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_TX_H_ -#define _WBM_RELEASE_RING_TX_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 4 - -struct wbm_release_ring_tx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - buffer_or_desc_type : 3, - reserved_2a : 26; - uint32_t tqm_status_number : 32; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t reserved_2a : 26, - buffer_or_desc_type : 3, - release_source_module : 3; - uint32_t tqm_status_number : 32; -#endif -}; - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 3 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 5 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x00000038 - -#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 6 -#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 31 -#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0xffffffc0 - -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0 -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 31 -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwiobase.h b/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwiobase.h deleted file mode 100644 index b96752690ea3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwiobase.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ -#ifndef WCSS_SEQ_HWIOBASE_H -#define WCSS_SEQ_HWIOBASE_H - -#define UMAC_NOC_BASE 0x140000 -#define UMAC_NOC_BASE_SIZE 0x00004480 -#define UMAC_NOC_BASE_PHYS 0x00140000 - -#define PHYA0_BASE 0x300000 -#define PHYA0_BASE_SIZE 0x00300000 -#define PHYA0_BASE_PHYS 0x00300000 - -#define PHYA1_BASE 0x600000 -#define PHYA1_BASE_SIZE 0x00300000 -#define PHYA1_BASE_PHYS 0x00600000 - -#define DMAC_BASE 0x900000 -#define DMAC_BASE_SIZE 0x00080000 -#define DMAC_BASE_PHYS 0x00900000 - -#define UMAC_BASE 0xa00000 -#define UMAC_BASE_SIZE 0x0004d000 -#define UMAC_BASE_PHYS 0x00a00000 - -#define PMAC0_BASE 0xa80000 -#define PMAC0_BASE_SIZE 0x00040000 -#define PMAC0_BASE_PHYS 0x00a80000 - -#define PMAC1_BASE 0xac0000 -#define PMAC1_BASE_SIZE 0x00040000 -#define PMAC1_BASE_PHYS 0x00ac0000 - -#define WFSS_AMCSS_BASE 0xb00000 -#define WFSS_AMCSS_BASE_SIZE 0x00040000 -#define WFSS_AMCSS_BASE_PHYS 0x00b00000 - -#define CXC_BASE 0xb40000 -#define CXC_BASE_SIZE 0x00010000 -#define CXC_BASE_PHYS 0x00b40000 - -#define WFSS_PMM_BASE 0xb50000 -#define WFSS_PMM_BASE_SIZE 0x00002401 -#define WFSS_PMM_BASE_PHYS 0x00b50000 - -#define WFSS_CC_BASE 0xb60000 -#define WFSS_CC_BASE_SIZE 0x00008000 -#define WFSS_CC_BASE_PHYS 0x00b60000 - -#define WCMN_CORE_BASE 0xb68000 -#define WCMN_CORE_BASE_SIZE 0x000008a9 -#define WCMN_CORE_BASE_PHYS 0x00b68000 - -#define WIFI_CFGBUS_APB_TSLV_BASE 0xb6b000 -#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE 0x00001000 -#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS 0x00b6b000 - -#define WFSS_CFGBUS_BASE 0xb6c000 -#define WFSS_CFGBUS_BASE_SIZE 0x000000a0 -#define WFSS_CFGBUS_BASE_PHYS 0x00b6c000 - -#define WIFI_CFGBUS_AHB_TSLV_BASE 0xb6d000 -#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE 0x00001000 -#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS 0x00b6d000 - -#define UMAC_ACMT_BASE 0xb6e000 -#define UMAC_ACMT_BASE_SIZE 0x00001000 -#define UMAC_ACMT_BASE_PHYS 0x00b6e000 - -#define WCSS_CC_BASE 0xb80000 -#define WCSS_CC_BASE_SIZE 0x00010000 -#define WCSS_CC_BASE_PHYS 0x00b80000 - -#define PMM_TOP_BASE 0xb90000 -#define PMM_TOP_BASE_SIZE 0x00010000 -#define PMM_TOP_BASE_PHYS 0x00b90000 - -#define WCSS_TOP_CMN_BASE 0xba0000 -#define WCSS_TOP_CMN_BASE_SIZE 0x00004000 -#define WCSS_TOP_CMN_BASE_PHYS 0x00ba0000 - -#define WCSS_CFGBUS_BASE 0xba4000 -#define WCSS_CFGBUS_BASE_SIZE 0x00008000 -#define WCSS_CFGBUS_BASE_PHYS 0x00ba4000 - -#define MSIP_BASE 0xbb0000 -#define MSIP_BASE_SIZE 0x00010000 -#define MSIP_BASE_PHYS 0x00bb0000 - -#define RFA_BASE 0xbc0000 -#define RFA_BASE_SIZE 0x00040000 -#define RFA_BASE_PHYS 0x00bc0000 - -#define DBG_BASE 0x1000000 -#define DBG_BASE_SIZE 0x00100000 -#define DBG_BASE_PHYS 0x01000000 - -#define Q6SS_WLAN_BASE 0x1100000 -#define Q6SS_WLAN_BASE_SIZE 0x00100000 -#define Q6SS_WLAN_BASE_PHYS 0x01100000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwioreg_umac.h b/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwioreg_umac.h deleted file mode 100644 index 4fb391d29729..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwioreg_umac.h +++ /dev/null @@ -1,2475 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef WCSS_SEQ_HWIOREG_UMAC_H -#include "seq_hwio.h" -#include "wcss_seq_hwiobase.h" -#ifdef SCALE_INCLUDES -#include "HALhwio.h" -#else -#include "msmhwio.h" -#endif - -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x) ((x) + 0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x) ((x) + 0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS (0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK 0x7 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK 0x7 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x) ((x) + 0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x) ((x) + 0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS (0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK 0x1ffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR 0x00001ffe -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK 0x1ffe000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT 13 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK 0x1ffe -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT 1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK 0x1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT 0 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK 0x1000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT 12 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK 0x800 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT 11 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK 0x400 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT 10 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK 0x200 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT 9 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x) ((x) + 0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x) ((x) + 0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS (0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK 0xff000000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT 24 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK 0xff0000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT 16 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK 0xff00 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT 8 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK 0xff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n) ((base) + 0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_PHYS(base,n) ((base) + 0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_OFFS(n) (0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK 0xfff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_MAXn 31 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INI(base,n) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_BMSK 0xfff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_SHFT 0 - -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x) ((x) + 0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_PHYS(x) ((x) + 0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OFFS (0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_RMSK 0x3 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x)) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x)) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_BMSK 0x2 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_SHFT 1 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_BMSK 0x1 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_SHFT 0 - -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_OFFS(n) (0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_MAXn 63 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define WBM_REG_REG_BASE (UMAC_BASE + 0x00034000) - -#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) ((x) + 0x40) - -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) ((x) + 0x130) -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x7fc -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 2 -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x2 -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 1 - -#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) ((x) + 0x134) -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 16 -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0xffff -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) ((x) + 0x138) - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) ((x) + 0x13c) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) ((x) + 0x140) - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) ((x) + 0x144) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x1fff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) ((x) + 0x148) - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) ((x) + 0x14c) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x1fff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) ((x) + 0x150) - -#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x24c) - -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0x51c) - -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) ((x) + 0x52c) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_OFFS (0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_RMSK 0x3f -#define HWIO_WBM_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_WBM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_WBM_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_WBM_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_WBM_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_WBM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_WBM_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_BMSK 0x20 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_SHFT 5 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_BMSK 0x10 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_SHFT 4 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x) ((x) + 0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_PHYS(x) ((x) + 0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OFFS (0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RMSK 0xffffffff -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR 0x00000000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ATTR 0x3 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x) \ - in_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x)) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x), m) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUT(x, v) \ - out_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),v) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x)) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_BMSK 0xffe00000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_SHFT 21 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_BMSK 0x1f0000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_SHFT 16 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_BMSK 0xf800 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_SHFT 11 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_BMSK 0x7c0 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_SHFT 6 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_BMSK 0x3e -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_SHFT 1 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_BMSK 0x1 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_SHFT 0 - -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x3ff -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000020 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_BMSK 0x200 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_SHFT 9 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_BMSK 0x100 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_SHFT 8 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_MAXn 255 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3010) - -#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) ((x) + 0x3040) - -#define REO_REG_REG_BASE (UMAC_BASE + 0x00038000) - -#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) ((x) + 0x0) - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x) ((x) + 0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_PHYS(x) ((x) + 0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OFFS (0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR 0x76043210 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x) ((x) + 0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x) ((x) + 0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS (0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR 0x6666ba98 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x) ((x) + 0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_PHYS(x) ((x) + 0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OFFS (0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR 0x66666666 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x) ((x) + 0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_PHYS(x) ((x) + 0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OFFS (0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR 0x66666666 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) ((x) + 0x38) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) ((x) + 0x3c) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x) ((x) + 0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_PHYS(x) ((x) + 0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OFFS (0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR 0x00000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ATTR 0x3 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x), m) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),v) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x) ((x) + 0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_PHYS(x) ((x) + 0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OFFS (0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR 0x00000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ATTR 0x3 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x), m) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),v) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_SHFT 0 - -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x) ((x) + 0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_PHYS(x) ((x) + 0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OFFS (0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_RMSK 0x1ffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR 0x00000000 -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ATTR 0x3 -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x) \ - in_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x)) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x), m) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUT(x, v) \ - out_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),v) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),m,v,HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x)) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_BMSK 0x1ffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_SHFT 0 - -#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x6c) - -#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x70) -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK 0x100000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT 20 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK 0x80000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT 19 -#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 -#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff -#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 - -#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) ((x) + 0x344) - -#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) ((x) + 0x7d0) - -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) ((x) + 0x7d4) -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) ((x) + 0x7d8) - -#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) ((x) + 0x7dc) -#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x7e0) -#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x7e4) - -#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x7e8) - -#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7f4) - -#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x818) - -#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x81c) - -#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x820) - -#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x824) - -#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x828) - -#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x82c) - -#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x830) - -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x844) -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x848) - -#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0xc08) - -#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_MISC_CFG_ADDR(x) ((x) + 0x1458) -#define HWIO_REO_R0_MISC_CFG_PHYS(x) ((x) + 0x1458) -#define HWIO_REO_R0_MISC_CFG_OFFS (0x1458) -#define HWIO_REO_R0_MISC_CFG_RMSK 0x1 -#define HWIO_REO_R0_MISC_CFG_POR 0x00000000 -#define HWIO_REO_R0_MISC_CFG_POR_RMSK 0xffffffff -#define HWIO_REO_R0_MISC_CFG_ATTR 0x3 -#define HWIO_REO_R0_MISC_CFG_IN(x) \ - in_dword(HWIO_REO_R0_MISC_CFG_ADDR(x)) -#define HWIO_REO_R0_MISC_CFG_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_MISC_CFG_ADDR(x), m) -#define HWIO_REO_R0_MISC_CFG_OUT(x, v) \ - out_dword(HWIO_REO_R0_MISC_CFG_ADDR(x),v) -#define HWIO_REO_R0_MISC_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_MISC_CFG_ADDR(x),m,v,HWIO_REO_R0_MISC_CFG_IN(x)) -#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_BMSK 0x1 -#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_SHFT 0 - -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x) ((x) + 0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_PHYS(x) ((x) + 0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OFFS (0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_RMSK 0x1ff -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR 0x0000002d -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR_RMSK 0xffffffff -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ATTR 0x3 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x) \ - in_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x)) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x), m) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUT(x, v) \ - out_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),v) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),m,v,HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x)) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_BMSK 0x1fe -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_SHFT 1 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_BMSK 0x1 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_SHFT 0 - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) ((x) + 0x1468) - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) ((x) + 0x146c) - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) ((x) + 0x1470) - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) ((x) + 0x1474) - -#define HWIO_REO_R0_MISC_CTL_ADDR(x) ((x) + 0x14dc) -#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK 0x1e00000 -#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT 21 -#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x1e0000 -#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 17 - -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_REO_R0_CREDIT_ADDR(x) ((x) + 0x16d0) -#define HWIO_REO_R0_CREDIT_PHYS(x) ((x) + 0x16d0) -#define HWIO_REO_R0_CREDIT_OFFS (0x16d0) -#define HWIO_REO_R0_CREDIT_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_POR 0x00000000 -#define HWIO_REO_R0_CREDIT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_ATTR 0x3 -#define HWIO_REO_R0_CREDIT_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_ADDR(x)) -#define HWIO_REO_R0_CREDIT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_OUT(x, v) \ - out_dword(HWIO_REO_R0_CREDIT_ADDR(x),v) -#define HWIO_REO_R0_CREDIT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_CREDIT_ADDR(x),m,v,HWIO_REO_R0_CREDIT_IN(x)) -#define HWIO_REO_R0_CREDIT_VAL_BMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_VAL_SHFT 0 - -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x) ((x) + 0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_PHYS(x) ((x) + 0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OFFS (0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_RMSK 0x7 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR 0x00000002 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ATTR 0x3 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x)) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUT(x, v) \ - out_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),v) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),m,v,HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x)) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_BMSK 0x7 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_SHFT 0 - -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x) ((x) + 0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_PHYS(x) ((x) + 0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_OFFS (0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR 0x00000000 -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ATTR 0x1 -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x)) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_BMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_SHFT 0 - -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_BMSK 0x2000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_SHFT 13 - -#define HWIO_REO_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_OFFS (0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_RMSK 0x7 -#define HWIO_REO_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_REO_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_REO_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_REO_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_REO_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_REO_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_REO_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_REO_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x) ((x) + 0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_PHYS(x) ((x) + 0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_OFFS (0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_RMSK 0x3f -#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR 0x00000000 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R1_MISC_DEBUG_STATUS_ATTR 0x1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_IN(x) \ - in_dword(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x)) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x), m) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_BMSK 0x20 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_SHFT 5 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_BMSK 0x10 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_SHFT 4 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_BMSK 0x8 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_SHFT 3 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_BMSK 0x4 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_SHFT 2 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_BMSK 0x2 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_SHFT 1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_BMSK 0x1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_SHFT 0 - -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x) ((x) + 0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_PHYS(x) ((x) + 0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OFFS (0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_RMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR 0x00000000 -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR_RMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ATTR 0x3 -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x) \ - in_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x)) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x), m) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUT(x, v) \ - out_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),v) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),m,v,HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x)) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_BMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_SHFT 0 - -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_MAXn 255 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) ((x) + 0x3028) - -#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) ((x) + 0x3070) - -#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) ((x) + 0x3074) - -#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) ((x) + 0x3078) - -#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x) ((x) + 0x30b8) - -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_BMSK 0x80 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_SHFT 7 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_BMSK 0x40 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_SHFT 6 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_BMSK 0x20 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_SHFT 5 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_BMSK 0x10 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_SHFT 4 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_BMSK 0x8 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_SHFT 3 - -#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_BMSK 0x80000000 -#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_SHFT 31 - -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_BMSK 0x8000 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_SHFT 15 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_BMSK 0x4000 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_SHFT 14 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_BMSK 0x2000 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_SHFT 13 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_BMSK 0x1000 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_SHFT 12 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_BMSK 0x800 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_SHFT 11 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_BMSK 0x400 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_SHFT 10 - -#define HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_OFFS (0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_RMSK 0xf -#define HWIO_TQM_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_TQM_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TQM_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x) ((x) + 0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_PHYS(x) ((x) + 0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OFFS (0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_RMSK 0x1ffff -#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR 0x00000000 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CLKGATE_CTRL_2_ATTR 0x3 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x) \ - in_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x)) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x), m) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUT(x, v) \ - out_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),v) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),m,v,HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x)) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_BMSK 0x2 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_SHFT 1 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_BMSK 0x1 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_SHFT 0 - -#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_BMSK 0x20000000 -#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_SHFT 29 - -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x) ((x) + 0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_PHYS(x) ((x) + 0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OFFS (0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_SHFT 0 - -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x) ((x) + 0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_PHYS(x) ((x) + 0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OFFS (0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_SHFT 0 - -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x) ((x) + 0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_PHYS(x) ((x) + 0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OFFS (0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_SHFT 0 - -#define HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x) ((x) + 0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_PHYS(x) ((x) + 0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OFFS (0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_RMSK 0xfff -#define HWIO_TQM_R0_WATCHDOG_SRNG_POR 0x00000710 -#define HWIO_TQM_R0_WATCHDOG_SRNG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_WATCHDOG_SRNG_ATTR 0x3 -#define HWIO_TQM_R0_WATCHDOG_SRNG_IN(x) \ - in_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x)) -#define HWIO_TQM_R0_WATCHDOG_SRNG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x), m) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),v) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_SRNG_IN(x)) -#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_BMSK 0xfff -#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x) ((x) + 0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x) ((x) + 0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS (0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x) ((x) + 0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x) ((x) + 0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS (0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x) ((x) + 0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x) ((x) + 0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS (0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR 0x3 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK 0xffff0000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT 16 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK 0xfff0 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT 4 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK 0x8 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT 3 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK 0x4 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT 2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT 1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT 0 - -#define HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x) ((x) + 0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_PHYS(x) ((x) + 0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OFFS (0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x) ((x) + 0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_PHYS(x) ((x) + 0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OFFS (0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x) ((x) + 0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_PHYS(x) ((x) + 0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OFFS (0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x) ((x) + 0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_PHYS(x) ((x) + 0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_OFFS (0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_RMSK 0xf -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR 0x00000000 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ATTR 0x1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x)) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x), m) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_BMSK 0x8 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_SHFT 3 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_BMSK 0x4 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_SHFT 2 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_BMSK 0x2 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_SHFT 1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_BMSK 0x1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_SHFT 0 - -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x) ((x) + 0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_PHYS(x) ((x) + 0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_OFFS (0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR 0x00000000 -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ATTR 0x1 -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_IN(x) \ - in_dword(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x)) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x), m) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_SHFT 0 - -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x) ((x) + 0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_PHYS(x) ((x) + 0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_OFFS (0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR 0x00000000 -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ATTR 0x1 -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_IN(x) \ - in_dword(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x)) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x), m) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_SHFT 0 - -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0xff -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_MAXn 127 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_BMSK 0x80 -#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_SHFT 7 - -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 28 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 27 - -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 - -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 - -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 - -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 - -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 28 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 27 - -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 - -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 - -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 - -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 - -#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_BMSK 0x40 -#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_SHFT 6 - -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x) ((x) + 0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_PHYS(x) ((x) + 0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OFFS (0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_RMSK 0xf -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR 0x0000000a -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ATTR 0x3 -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x) \ - in_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x)) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x), m) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),v) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x)) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_BMSK 0xf -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_SHFT 0 - -#define HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OFFS (0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_RMSK 0x1f -#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_BMSK 0x10 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_SHFT 4 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_BMSK 0x8 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_SHFT 3 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_BMSK 0x4 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_SHFT 2 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_BMSK 0x2 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_SHFT 1 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_UMCMN_R0_LINK_ID_ADDR(x) ((x) + 0x170) -#define HWIO_UMCMN_R0_LINK_ID_PHYS(x) ((x) + 0x170) -#define HWIO_UMCMN_R0_LINK_ID_OFFS (0x170) -#define HWIO_UMCMN_R0_LINK_ID_RMSK 0xffff -#define HWIO_UMCMN_R0_LINK_ID_POR 0x000052c8 -#define HWIO_UMCMN_R0_LINK_ID_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_LINK_ID_ATTR 0x3 -#define HWIO_UMCMN_R0_LINK_ID_IN(x) \ - in_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x)) -#define HWIO_UMCMN_R0_LINK_ID_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_LINK_ID_ADDR(x), m) -#define HWIO_UMCMN_R0_LINK_ID_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x),v) -#define HWIO_UMCMN_R0_LINK_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_LINK_ID_IN(x)) -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_BMSK 0x80 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_SHFT 7 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_BMSK 0x40 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_SHFT 6 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_BMSK 0x38 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_SHFT 3 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_BMSK 0x7 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_SHFT 0 - -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK 0x4000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT 14 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK 0x2000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT 13 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK 0x1000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT 12 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK 0x800 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT 11 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK 0x400 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT 10 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK 0x200 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT 9 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK 0x100 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT 8 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK 0x80 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT 7 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK 0x40 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT 6 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK 0x20 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT 5 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK 0x10 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT 4 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK 0x8 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT 3 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK 0x4 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT 2 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK 0x2 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT 1 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK 0x1 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT 0 - -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x) ((x) + 0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_PHYS(x) ((x) + 0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OFFS (0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_RMSK 0x1 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR 0x00000000 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ATTR 0x3 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x) \ - in_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x)) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x), m) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),v) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x)) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_BMSK 0x1 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_SHFT 0 - -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x) ((x) + 0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_PHYS(x) ((x) + 0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OFFS (0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_RMSK 0x1ffff -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR 0x00000000 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ATTR 0x3 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x) \ - in_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x)) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x), m) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),v) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),m,v,HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x)) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_BMSK 0x1fe00 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_SHFT 9 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_BMSK 0x1fe -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_SHFT 1 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_BMSK 0x1 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_SHFT 0 - -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x1ff -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_BMSK 0x100 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_SHFT 8 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_BMSK 0x80 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_SHFT 7 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_BMSK 0x40 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_SHFT 6 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_BMSK 0x20 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_SHFT 5 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n) ((base) + 0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_PHYS(base,n) ((base) + 0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OFFS(n) (0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_MAXn 7 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR 0x00000000 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ATTR 0x3 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n) \ - in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), mask) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTI(base,n,val) \ - out_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),val) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),mask,val,HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n)) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_BMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_SHFT 0 - -#define MAC_TCL_REG_REG_BASE (UMAC_BASE + 0x00044000) - -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) ((x) + 0x20) -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x800000 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 23 - -#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_BMSK 0x200000 -#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_SHFT 21 - -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n) ((base) + 0X74 + (0x4*(n))) -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT 17 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT 14 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT 12 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT 8 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT 7 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT 3 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT 1 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT 0 - -#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n) ((base) + 0X174 + (0x4*(n))) -#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff - -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_BMSK 0x800000 -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_SHFT 23 - -#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_BMSK 0x40 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_SHFT 6 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_BMSK 0x20 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_SHFT 5 - -#define HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x) ((x) + 0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_PHYS(x) ((x) + 0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OFFS (0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_RMSK 0x3 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR 0x00000000 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_CLKGATE_DISABLE2_ATTR 0x3 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x) \ - in_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x)) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x), m) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUT(x, v) \ - out_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),v) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x)) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_BMSK 0x2 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_SHFT 1 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_BMSK 0x1 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_SHFT 0 - -#define HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_OFFS (0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_RMSK 0x7 -#define HWIO_TCL_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_TCL_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_TCL_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_TCL_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_TCL_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_TCL_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TCL_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0x8c8) - -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0x8cc) -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) ((x) + 0x8d0) -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) ((x) + 0x8d8) -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x8e4) - -#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x8e8) - -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x8f8) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x8fc) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x910) - -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x914) -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0x918) - -#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) ((x) + 0x940) - -#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x10000 -#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 16 - -#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x10000 -#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 16 - -#define HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_OFFS (0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_RMSK 0x1ff -#define HWIO_TCL_R1_TESTBUS_CTRL_POR 0x00000000 -#define HWIO_TCL_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CTRL_ATTR 0x3 -#define HWIO_TCL_R1_TESTBUS_CTRL_IN(x) \ - in_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x)) -#define HWIO_TCL_R1_TESTBUS_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x), m) -#define HWIO_TCL_R1_TESTBUS_CTRL_OUT(x, v) \ - out_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),v) -#define HWIO_TCL_R1_TESTBUS_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TCL_R1_TESTBUS_CTRL_IN(x)) -#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x100 -#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 8 -#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_BMSK 0xc0 -#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_SHFT 6 -#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_BMSK 0x3f -#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_SHFT 0 - -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_MAXn 511 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) ((x) + 0x2000) - -#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) ((x) + 0x2004) - -#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) ((x) + 0x2008) - -#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x) ((x) + 0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_PHYS(x) ((x) + 0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OFFS (0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_RMSK 0x7ff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR 0x000003ff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR_RMSK 0xffffffff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ATTR 0x3 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x) \ - in_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x)) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x), m) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUT(x, v) \ - out_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),v) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),m,v,HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x)) - -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_BMSK 0x400 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_SHFT 10 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_BMSK 0x200 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_SHFT 9 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_BMSK 0x100 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_SHFT 8 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_BMSK 0x80 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_SHFT 7 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_BMSK 0x40 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_SHFT 6 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_BMSK 0x20 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_SHFT 5 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_BMSK 0x10 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_SHFT 4 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_BMSK 0x8 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_SHFT 3 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_BMSK 0x4 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_SHFT 2 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_BMSK 0x2 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_SHFT 1 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_BMSK 0x1 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_SHFT 0 - -#define TQM_REG_REG_BASE (UMAC_BASE + 0x0003c000) -#define TQM_REG_REG_BASE_SIZE 0x4000 - -#define HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_PHYS(x) ((x) + 0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OFFS (0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR 0x00000000 -#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PHYS(x) ((x) + 0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OFFS (0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_RMSK 0x7ffff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR 0x00011100 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x) ((x) + 0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_PHYS(x) ((x) + 0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OFFS (0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_RMSK 0x1ff -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR 0x000001fe -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_SHFT 8 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_BMSK 0x80 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_SHFT 7 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_BMSK 0x40 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_SHFT 6 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_BMSK 0x20 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_SHFT 5 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_BMSK 0x10 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_SHFT 4 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_BMSK 0x8 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_SHFT 3 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_BMSK 0x4 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_SHFT 2 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_BMSK 0x2 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_SHFT 1 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_BMSK 0x1 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_SHFT 0 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x) ((x) + 0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PHYS(x) ((x) + 0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OFFS (0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RMSK 0x3fefff -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR 0x00080170 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ATTR 0x3 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x) \ - in_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x)) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x), m) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),v) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),m,v,HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x)) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_BMSK 0x200000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_SHFT 21 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_BMSK 0x100000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_SHFT 20 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_BMSK 0x80000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_SHFT 19 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_BMSK 0x40000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_SHFT 18 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_BMSK 0x20000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_SHFT 17 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_BMSK 0x10000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_SHFT 16 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_BMSK 0x8000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_SHFT 15 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_BMSK 0x4000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_SHFT 14 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_BMSK 0x2000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_SHFT 13 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_BMSK 0x800 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_SHFT 11 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_BMSK 0x400 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_SHFT 10 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_BMSK 0x200 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_SHFT 9 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_BMSK 0x80 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_SHFT 7 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_BMSK 0x40 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_SHFT 6 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_BMSK 0x20 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_SHFT 5 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_BMSK 0x10 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_SHFT 4 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_BMSK 0x8 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_SHFT 3 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_BMSK 0x4 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_SHFT 2 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_BMSK 0x2 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_SHFT 1 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_BMSK 0x1 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_SHFT 0 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OFFS (0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x) ((x) + 0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_PHYS(x) ((x) + 0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OFFS (0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OFFS (0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x) ((x) + 0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_PHYS(x) ((x) + 0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OFFS (0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT 0 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x) ((x) + 0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_PHYS(x) ((x) + 0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OFFS (0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR 0x00060000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ATTR 0x3 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x), m) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),v) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_BMSK 0xf0000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_SHFT 28 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_BMSK 0xf000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_SHFT 24 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_BMSK 0xf00000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_SHFT 20 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_BMSK 0xf0000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_SHFT 16 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_BMSK 0xf000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_SHFT 12 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_BMSK 0xf00 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_SHFT 8 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_BMSK 0xf0 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_SHFT 4 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_BMSK 0xf -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_SHFT 0 - -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x) ((x) + 0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_PHYS(x) ((x) + 0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OFFS (0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR 0x00060000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ATTR 0x3 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x), m) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),v) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_BMSK 0xf0000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_SHFT 28 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_BMSK 0xf000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_SHFT 24 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_BMSK 0xf00000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_SHFT 20 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_BMSK 0xf0000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_SHFT 16 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_BMSK 0xf000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_SHFT 12 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_BMSK 0xf00 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_SHFT 8 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_BMSK 0xf0 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_SHFT 4 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_BMSK 0xf -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_SHFT 0 -#endif /* WCSS_SEQ_HWIOREG_UMAC_H */ diff --git a/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwioreg_wifi_top.h b/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwioreg_wifi_top.h deleted file mode 100644 index 072ec2ed4af7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wcss_seq_hwioreg_wifi_top.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef WCSS_SEQ_HWIOREG_WIFI_TOP_H -#define WCSS_SEQ_HWIOREG_WIFI_TOP_H - -#include "wcss_seq_hwiobase.h" - -#define WFSS_PMM_REG_BASE (WFSS_PMM_BASE + 0x00000000) - -#define HWIO_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_26_ADDR(x) ((x) + 0x164) - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v1/wcss_version.h b/drivers/staging/fw-api/hw/fig/v1/wcss_version.h deleted file mode 100644 index 76c77489574d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v1/wcss_version.h +++ /dev/null @@ -1,5 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ -#define WCSS_VERSION 3150 diff --git a/drivers/staging/fw-api/hw/fig/v2/HALcomdef.h b/drivers/staging/fw-api/hw/fig/v2/HALcomdef.h deleted file mode 100644 index 60ee92e6cd2e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/HALcomdef.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef HAL_COMDEF_H -#define HAL_COMDEF_H - -#ifndef _ARM_ASM_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "com_dtypes.h" - -#ifndef _BOOL32_DEFINED -typedef unsigned long int bool32; -#define _BOOL32_DEFINED -#endif - -#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF - - #define inp(port) (*((volatile byte *) (port))) - #define inpw(port) (*((volatile word *) (port))) - #define inpdw(port) (*((volatile dword *)(port))) - - #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) - #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) - #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) - -#ifdef __cplusplus -} -#endif - -#endif - -#endif - diff --git a/drivers/staging/fw-api/hw/fig/v2/HALhwio.h b/drivers/staging/fw-api/hw/fig/v2/HALhwio.h deleted file mode 100644 index 94dd4185e173..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/HALhwio.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef HAL_HWIO_H -#define HAL_HWIO_H - -#include "HALcomdef.h" - -#define HWIO_BASE_PTR(base) base##_BASE_PTR - -#ifdef __ARMCC_VERSION - #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) -#else - #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) -#endif - -#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) -#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) -#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) -#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) - -#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) -#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) -#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) -#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) -#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) -#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) -#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) - -#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) -#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) -#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) -#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) -#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) -#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) -#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) - -#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) -#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) -#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) -#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) - -#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) -#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) -#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) -#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) - -#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) - -#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) -#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) -#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) -#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) -#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) -#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) -#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) - -#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) - -#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) -#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) -#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) -#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) - -#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) -#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) -#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) -#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) - -#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) - -#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) - -#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) -#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) -#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) -#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) - -#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) -#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) -#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) -#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) -#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) -#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) -#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) - -#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) -#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) -#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) - -#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) - -#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) - -#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) -#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) -#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) -#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) -#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) -#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) -#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) -#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) - -#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) -#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) - -#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN -#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) -#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) -#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) -#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) -#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) -#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) -#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) -#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) -#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) -#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) -#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) -#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) -#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) -#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) -#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) -#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR -#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) -#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) -#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) -#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS -#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) -#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) -#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) -#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS -#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) -#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) -#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) -#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK -#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) -#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK -#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT -#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT -#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow -#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) -#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL - -#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) -#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) -#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) -#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) -#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) -#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) -#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) -#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) -#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) -#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) -#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) -#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) -#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) -#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ - HWIO_##hwiosym##_OUTM(base, mask1, val1); \ - HWIO_##hwiosym##_OUTM(base, mask2, val2); \ - } -#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ - HWIO_##hwiosym##_OUTM(base, mask1, val1); \ - HWIO_##hwiosym##_OUTM(base, mask2, val2); \ - HWIO_##hwiosym##_OUTM(base, mask3, val3); \ - } -#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ - HWIO_##hwiosym##_OUTM(base, mask1, val1); \ - HWIO_##hwiosym##_OUTM(base, mask2, val2); \ - HWIO_##hwiosym##_OUTM(base, mask3, val3); \ - HWIO_##hwiosym##_OUTM(base, mask4, val4); \ - } - -#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) -#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) -#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) -#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) -#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) -#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) -#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) -#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) -#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) -#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) -#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) - -#define HWIO_INTLOCK() -#define HWIO_INTFREE() - -#define __inp(port) (*((volatile uint8 *) (port))) -#define __inpw(port) (*((volatile uint16 *) (port))) -#define __inpdw(port) (*((volatile uint32 *) (port))) -#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) -#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) -#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) - -#ifdef HAL_HWIO_EXTERNAL - -#undef __inp -#undef __inpw -#undef __inpdw -#undef __outp -#undef __outpw -#undef __outpdw - -#define __inp(port) __inp_extern(port) -#define __inpw(port) __inpw_extern(port) -#define __inpdw(port) __inpdw_extern(port) -#define __outp(port, val) __outp_extern(port, val) -#define __outpw(port, val) __outpw_extern(port, val) -#define __outpdw(port, val) __outpdw_extern(port, val) - -extern uint8 __inp_extern ( uint32 nAddr ); -extern uint16 __inpw_extern ( uint32 nAddr ); -extern uint32 __inpdw_extern ( uint32 nAddr ); -extern void __outp_extern ( uint32 nAddr, uint8 nData ); -extern void __outpw_extern ( uint32 nAddr, uint16 nData ); -extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); - -#endif - -#define in_byte(addr) (__inp(addr)) -#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) -#define out_byte(addr, val) __outp(addr,val) -#define out_byte_masked(io, mask, val, shadow) \ - HWIO_INTLOCK(); \ - out_byte( io, shadow); \ - shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ - HWIO_INTFREE() -#define out_byte_masked_ns(io, mask, val, current_reg_content) \ - out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ - ((uint16)((val) & (mask)))) ) - -#define in_word(addr) (__inpw(addr)) -#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) -#define out_word(addr, val) __outpw(addr,val) -#define out_word_masked(io, mask, val, shadow) \ - HWIO_INTLOCK( ); \ - shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ - out_word( io, shadow); \ - HWIO_INTFREE( ) -#define out_word_masked_ns(io, mask, val, current_reg_content) \ - out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ - ((uint16)((val) & (mask)))) ) - -#define in_dword(addr) (__inpdw(addr)) -#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) -#define out_dword(addr, val) __outpdw(addr,val) -#define out_dword_masked(io, mask, val, shadow) \ - HWIO_INTLOCK(); \ - shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ - out_dword( io, shadow); \ - HWIO_INTFREE() -#define out_dword_masked_ns(io, mask, val, current_reg_content) \ - out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ - ((uint32)((val) & (mask)))) ) - -#endif - diff --git a/drivers/staging/fw-api/hw/fig/v2/ack_report.h b/drivers/staging/fw-api/hw/fig/v2/ack_report.h deleted file mode 100644 index e78921b308fd..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/ack_report.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _ACK_REPORT_H_ -#define _ACK_REPORT_H_ - -#define NUM_OF_DWORDS_ACK_REPORT 1 - -struct ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t selfgen_response_reason : 4, - ax_trigger_type : 4, - sr_ppdu : 1, - reserved : 7, - frame_control : 16; -#else - uint32_t frame_control : 16, - reserved : 7, - sr_ppdu : 1, - ax_trigger_type : 4, - selfgen_response_reason : 4; -#endif -}; - -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f - -#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000 -#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4 -#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7 -#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0 - -#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000 -#define ACK_REPORT_SR_PPDU_LSB 8 -#define ACK_REPORT_SR_PPDU_MSB 8 -#define ACK_REPORT_SR_PPDU_MASK 0x00000100 - -#define ACK_REPORT_RESERVED_OFFSET 0x00000000 -#define ACK_REPORT_RESERVED_LSB 9 -#define ACK_REPORT_RESERVED_MSB 15 -#define ACK_REPORT_RESERVED_MASK 0x0000fe00 - -#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 -#define ACK_REPORT_FRAME_CONTROL_LSB 16 -#define ACK_REPORT_FRAME_CONTROL_MSB 31 -#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/boron_top_reg.h b/drivers/staging/fw-api/hw/fig/v2/boron_top_reg.h deleted file mode 100644 index 306398284fe3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/boron_top_reg.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef BORON_TOP_REG_H -#define BORON_TOP_REG_H - -#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C) -#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050) - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/buffer_addr_info.h b/drivers/staging/fw-api/hw/fig/v2/buffer_addr_info.h deleted file mode 100644 index d65375b54715..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/buffer_addr_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _BUFFER_ADDR_INFO_H_ -#define _BUFFER_ADDR_INFO_H_ - -#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 - -struct buffer_addr_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_addr_31_0 : 32; - uint32_t buffer_addr_39_32 : 8, - return_buffer_manager : 4, - sw_buffer_cookie : 20; -#else - uint32_t buffer_addr_31_0 : 32; - uint32_t sw_buffer_cookie : 20, - return_buffer_manager : 4, - buffer_addr_39_32 : 8; -#endif -}; - -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/ce_src_desc.h b/drivers/staging/fw-api/hw/fig/v2/ce_src_desc.h deleted file mode 100644 index 4ecaedcab2a7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/ce_src_desc.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _CE_SRC_DESC_H_ -#define _CE_SRC_DESC_H_ - -#define NUM_OF_DWORDS_CE_SRC_DESC 4 - -struct ce_src_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t src_buffer_low : 32; - uint32_t src_buffer_high : 8, - toeplitz_en : 1, - src_swap : 1, - dest_swap : 1, - gather : 1, - ce_res_0 : 1, - barrier_read : 1, - ce_res_1 : 2, - length : 16; - uint32_t fw_metadata : 16, - ce_res_2 : 16; - uint32_t ce_res_3 : 20, - ring_id : 8, - looping_count : 4; -#else - uint32_t src_buffer_low : 32; - uint32_t length : 16, - ce_res_1 : 2, - barrier_read : 1, - ce_res_0 : 1, - gather : 1, - dest_swap : 1, - src_swap : 1, - toeplitz_en : 1, - src_buffer_high : 8; - uint32_t ce_res_2 : 16, - fw_metadata : 16; - uint32_t looping_count : 4, - ring_id : 8, - ce_res_3 : 20; -#endif -}; - -#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000 -#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0 -#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31 -#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff - -#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff - -#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004 -#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8 -#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8 -#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100 - -#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004 -#define CE_SRC_DESC_SRC_SWAP_LSB 9 -#define CE_SRC_DESC_SRC_SWAP_MSB 9 -#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200 - -#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004 -#define CE_SRC_DESC_DEST_SWAP_LSB 10 -#define CE_SRC_DESC_DEST_SWAP_MSB 10 -#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400 - -#define CE_SRC_DESC_GATHER_OFFSET 0x00000004 -#define CE_SRC_DESC_GATHER_LSB 11 -#define CE_SRC_DESC_GATHER_MSB 11 -#define CE_SRC_DESC_GATHER_MASK 0x00000800 - -#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004 -#define CE_SRC_DESC_CE_RES_0_LSB 12 -#define CE_SRC_DESC_CE_RES_0_MSB 12 -#define CE_SRC_DESC_CE_RES_0_MASK 0x00001000 - -#define CE_SRC_DESC_BARRIER_READ_OFFSET 0x00000004 -#define CE_SRC_DESC_BARRIER_READ_LSB 13 -#define CE_SRC_DESC_BARRIER_READ_MSB 13 -#define CE_SRC_DESC_BARRIER_READ_MASK 0x00002000 - -#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000004 -#define CE_SRC_DESC_CE_RES_1_LSB 14 -#define CE_SRC_DESC_CE_RES_1_MSB 15 -#define CE_SRC_DESC_CE_RES_1_MASK 0x0000c000 - -#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004 -#define CE_SRC_DESC_LENGTH_LSB 16 -#define CE_SRC_DESC_LENGTH_MSB 31 -#define CE_SRC_DESC_LENGTH_MASK 0xffff0000 - -#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008 -#define CE_SRC_DESC_FW_METADATA_LSB 0 -#define CE_SRC_DESC_FW_METADATA_MSB 15 -#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff - -#define CE_SRC_DESC_CE_RES_2_OFFSET 0x00000008 -#define CE_SRC_DESC_CE_RES_2_LSB 16 -#define CE_SRC_DESC_CE_RES_2_MSB 31 -#define CE_SRC_DESC_CE_RES_2_MASK 0xffff0000 - -#define CE_SRC_DESC_CE_RES_3_OFFSET 0x0000000c -#define CE_SRC_DESC_CE_RES_3_LSB 0 -#define CE_SRC_DESC_CE_RES_3_MSB 19 -#define CE_SRC_DESC_CE_RES_3_MASK 0x000fffff - -#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c -#define CE_SRC_DESC_RING_ID_LSB 20 -#define CE_SRC_DESC_RING_ID_MSB 27 -#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000 - -#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c -#define CE_SRC_DESC_LOOPING_COUNT_LSB 28 -#define CE_SRC_DESC_LOOPING_COUNT_MSB 31 -#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/ce_stat_desc.h b/drivers/staging/fw-api/hw/fig/v2/ce_stat_desc.h deleted file mode 100644 index 0b9f9a221215..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/ce_stat_desc.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _CE_STAT_DESC_H_ -#define _CE_STAT_DESC_H_ - -#define NUM_OF_DWORDS_CE_STAT_DESC 4 - -struct ce_stat_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ce_res_5 : 8, - toeplitz_en : 1, - src_swap : 1, - dest_swap : 1, - gather : 1, - barrier_read : 1, - ce_res_6 : 3, - length : 16; - uint32_t toeplitz_hash_0 : 32; - uint32_t toeplitz_hash_1 : 32; - uint32_t fw_metadata : 16, - ce_res_7 : 4, - ring_id : 8, - looping_count : 4; -#else - uint32_t length : 16, - ce_res_6 : 3, - barrier_read : 1, - gather : 1, - dest_swap : 1, - src_swap : 1, - toeplitz_en : 1, - ce_res_5 : 8; - uint32_t toeplitz_hash_0 : 32; - uint32_t toeplitz_hash_1 : 32; - uint32_t looping_count : 4, - ring_id : 8, - ce_res_7 : 4, - fw_metadata : 16; -#endif -}; - -#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000 -#define CE_STAT_DESC_CE_RES_5_LSB 0 -#define CE_STAT_DESC_CE_RES_5_MSB 7 -#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff - -#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000 -#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8 -#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8 -#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100 - -#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000 -#define CE_STAT_DESC_SRC_SWAP_LSB 9 -#define CE_STAT_DESC_SRC_SWAP_MSB 9 -#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200 - -#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000 -#define CE_STAT_DESC_DEST_SWAP_LSB 10 -#define CE_STAT_DESC_DEST_SWAP_MSB 10 -#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400 - -#define CE_STAT_DESC_GATHER_OFFSET 0x00000000 -#define CE_STAT_DESC_GATHER_LSB 11 -#define CE_STAT_DESC_GATHER_MSB 11 -#define CE_STAT_DESC_GATHER_MASK 0x00000800 - -#define CE_STAT_DESC_BARRIER_READ_OFFSET 0x00000000 -#define CE_STAT_DESC_BARRIER_READ_LSB 12 -#define CE_STAT_DESC_BARRIER_READ_MSB 12 -#define CE_STAT_DESC_BARRIER_READ_MASK 0x00001000 - -#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000 -#define CE_STAT_DESC_CE_RES_6_LSB 13 -#define CE_STAT_DESC_CE_RES_6_MSB 15 -#define CE_STAT_DESC_CE_RES_6_MASK 0x0000e000 - -#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000 -#define CE_STAT_DESC_LENGTH_LSB 16 -#define CE_STAT_DESC_LENGTH_MSB 31 -#define CE_STAT_DESC_LENGTH_MASK 0xffff0000 - -#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff - -#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff - -#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c -#define CE_STAT_DESC_FW_METADATA_LSB 0 -#define CE_STAT_DESC_FW_METADATA_MSB 15 -#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff - -#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c -#define CE_STAT_DESC_CE_RES_7_LSB 16 -#define CE_STAT_DESC_CE_RES_7_MSB 19 -#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000 - -#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c -#define CE_STAT_DESC_RING_ID_LSB 20 -#define CE_STAT_DESC_RING_ID_MSB 27 -#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000 - -#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c -#define CE_STAT_DESC_LOOPING_COUNT_LSB 28 -#define CE_STAT_DESC_LOOPING_COUNT_MSB 31 -#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/coex_rx_status.h b/drivers/staging/fw-api/hw/fig/v2/coex_rx_status.h deleted file mode 100644 index 7d9c6b4d2057..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/coex_rx_status.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_RX_STATUS_H_ -#define _COEX_RX_STATUS_H_ - -#define NUM_OF_DWORDS_COEX_RX_STATUS 2 - -#define NUM_OF_QWORDS_COEX_RX_STATUS 1 - -struct coex_rx_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_mac_frame_status : 2, - rx_with_tx_response : 1, - rx_rate : 5, - rx_bw : 3, - single_mpdu : 1, - filter_status : 1, - ampdu : 1, - directed : 1, - reserved_0 : 1, - rx_nss : 3, - rx_rssi : 8, - rx_type : 3, - retry_bit_setting : 1, - more_data_bit_setting : 1; - uint32_t remain_rx_packet_time : 16, - rx_remaining_fes_time : 16; -#else - uint32_t more_data_bit_setting : 1, - retry_bit_setting : 1, - rx_type : 3, - rx_rssi : 8, - rx_nss : 3, - reserved_0 : 1, - directed : 1, - ampdu : 1, - filter_status : 1, - single_mpdu : 1, - rx_bw : 3, - rx_rate : 5, - rx_with_tx_response : 1, - rx_mac_frame_status : 2; - uint32_t rx_remaining_fes_time : 16, - remain_rx_packet_time : 16; -#endif -}; - -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003 - -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004 - -#define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_RATE_LSB 3 -#define COEX_RX_STATUS_RX_RATE_MSB 7 -#define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8 - -#define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_BW_LSB 8 -#define COEX_RX_STATUS_RX_BW_MSB 10 -#define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700 - -#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 -#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 -#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800 - -#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_FILTER_STATUS_LSB 12 -#define COEX_RX_STATUS_FILTER_STATUS_MSB 12 -#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000 - -#define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_AMPDU_LSB 13 -#define COEX_RX_STATUS_AMPDU_MSB 13 -#define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000 - -#define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_DIRECTED_LSB 14 -#define COEX_RX_STATUS_DIRECTED_MSB 14 -#define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000 - -#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RESERVED_0_LSB 15 -#define COEX_RX_STATUS_RESERVED_0_MSB 15 -#define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000 - -#define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_NSS_LSB 16 -#define COEX_RX_STATUS_RX_NSS_MSB 18 -#define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000 - -#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_RSSI_LSB 19 -#define COEX_RX_STATUS_RX_RSSI_MSB 26 -#define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000 - -#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_TYPE_LSB 27 -#define COEX_RX_STATUS_RX_TYPE_MSB 29 -#define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000 - -#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000 - -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000 - -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000 - -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/coex_tx_req.h b/drivers/staging/fw-api/hw/fig/v2/coex_tx_req.h deleted file mode 100644 index ed5b4c57bfd8..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/coex_tx_req.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_TX_REQ_H_ -#define _COEX_TX_REQ_H_ - -#define NUM_OF_DWORDS_COEX_TX_REQ 6 - -#define NUM_OF_QWORDS_COEX_TX_REQ 3 - -struct coex_tx_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_pwr : 8, - min_tx_pwr : 8, - nss : 3, - tx_chain_mask : 8, - bw : 3, - reserved_0 : 2; - uint32_t alt_tx_pwr : 8, - alt_min_tx_pwr : 8, - alt_nss : 3, - alt_tx_chain_mask : 8, - alt_bw : 3, - reserved_1 : 2; - uint32_t tx_pwr_1 : 8, - alt_tx_pwr_1 : 8, - wlan_request_duration : 16; - uint32_t wlan_pkt_type : 4, - coex_tx_reason : 2, - response_frame_type : 5, - wlan_low_priority_slicing_allowed : 1, - wlan_high_priority_slicing_allowed : 1, - sch_tx_burst_ongoing : 1, - coex_tx_priority : 4, - blackout_details_en : 1, - blackout_peek_duration : 8, - reserved_3a : 5; - uint32_t frequency_channel_bonding_mask : 16, - num_blackout_windows : 8, - reserved_4a : 8; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0 : 2, - bw : 3, - tx_chain_mask : 8, - nss : 3, - min_tx_pwr : 8, - tx_pwr : 8; - uint32_t reserved_1 : 2, - alt_bw : 3, - alt_tx_chain_mask : 8, - alt_nss : 3, - alt_min_tx_pwr : 8, - alt_tx_pwr : 8; - uint32_t wlan_request_duration : 16, - alt_tx_pwr_1 : 8, - tx_pwr_1 : 8; - uint32_t reserved_3a : 5, - blackout_peek_duration : 8, - blackout_details_en : 1, - coex_tx_priority : 4, - sch_tx_burst_ongoing : 1, - wlan_high_priority_slicing_allowed : 1, - wlan_low_priority_slicing_allowed : 1, - response_frame_type : 5, - coex_tx_reason : 2, - wlan_pkt_type : 4; - uint32_t reserved_4a : 8, - num_blackout_windows : 8, - frequency_channel_bonding_mask : 16; - uint32_t tlv64_padding : 32; -#endif -}; - -#define COEX_TX_REQ_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_TX_PWR_LSB 0 -#define COEX_TX_REQ_TX_PWR_MSB 7 -#define COEX_TX_REQ_TX_PWR_MASK 0x00000000000000ff - -#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_MIN_TX_PWR_LSB 8 -#define COEX_TX_REQ_MIN_TX_PWR_MSB 15 -#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define COEX_TX_REQ_NSS_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_NSS_LSB 16 -#define COEX_TX_REQ_NSS_MSB 18 -#define COEX_TX_REQ_NSS_MASK 0x0000000000070000 - -#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19 -#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26 -#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define COEX_TX_REQ_BW_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_BW_LSB 27 -#define COEX_TX_REQ_BW_MSB 29 -#define COEX_TX_REQ_BW_MASK 0x0000000038000000 - -#define COEX_TX_REQ_RESERVED_0_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_RESERVED_0_LSB 30 -#define COEX_TX_REQ_RESERVED_0_MSB 31 -#define COEX_TX_REQ_RESERVED_0_MASK 0x00000000c0000000 - -#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_TX_PWR_LSB 32 -#define COEX_TX_REQ_ALT_TX_PWR_MSB 39 -#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 40 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 47 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define COEX_TX_REQ_ALT_NSS_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_NSS_LSB 48 -#define COEX_TX_REQ_ALT_NSS_MSB 50 -#define COEX_TX_REQ_ALT_NSS_MASK 0x0007000000000000 - -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 51 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 58 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define COEX_TX_REQ_ALT_BW_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_BW_LSB 59 -#define COEX_TX_REQ_ALT_BW_MSB 61 -#define COEX_TX_REQ_ALT_BW_MASK 0x3800000000000000 - -#define COEX_TX_REQ_RESERVED_1_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_RESERVED_1_LSB 62 -#define COEX_TX_REQ_RESERVED_1_MSB 63 -#define COEX_TX_REQ_RESERVED_1_MASK 0xc000000000000000 - -#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_TX_PWR_1_LSB 0 -#define COEX_TX_REQ_TX_PWR_1_MSB 7 -#define COEX_TX_REQ_TX_PWR_1_MASK 0x00000000000000ff - -#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8 -#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15 -#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x000000000000ff00 - -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0x00000000ffff0000 - -#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 32 -#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 35 -#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f00000000 - -#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_COEX_TX_REASON_LSB 36 -#define COEX_TX_REQ_COEX_TX_REASON_MSB 37 -#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x0000003000000000 - -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 38 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 42 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c000000000 - -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 43 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 43 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x0000080000000000 - -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 44 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 44 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x0000100000000000 - -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 45 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 45 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x0000200000000000 - -#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 46 -#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 49 -#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c00000000000 - -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_LSB 50 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MSB 50 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MASK 0x0004000000000000 - -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_LSB 51 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MSB 58 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MASK 0x07f8000000000000 - -#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_RESERVED_3A_LSB 59 -#define COEX_TX_REQ_RESERVED_3A_MSB 63 -#define COEX_TX_REQ_RESERVED_3A_MASK 0xf800000000000000 - -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_LSB 0 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MSB 15 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MASK 0x000000000000ffff - -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_LSB 16 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MSB 23 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MASK 0x0000000000ff0000 - -#define COEX_TX_REQ_RESERVED_4A_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_RESERVED_4A_LSB 24 -#define COEX_TX_REQ_RESERVED_4A_MSB 31 -#define COEX_TX_REQ_RESERVED_4A_MASK 0x00000000ff000000 - -#define COEX_TX_REQ_TLV64_PADDING_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_TLV64_PADDING_LSB 32 -#define COEX_TX_REQ_TLV64_PADDING_MSB 63 -#define COEX_TX_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/coex_tx_status.h b/drivers/staging/fw-api/hw/fig/v2/coex_tx_status.h deleted file mode 100644 index c47c29c2a5ba..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/coex_tx_status.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_TX_STATUS_H_ -#define _COEX_TX_STATUS_H_ - -#define NUM_OF_DWORDS_COEX_TX_STATUS 4 - -#define NUM_OF_QWORDS_COEX_TX_STATUS 2 - -struct coex_tx_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 7, - tx_bw : 3, - tx_status_reason : 3, - tx_wait_ack : 1, - fes_tx_is_gen_frame : 1, - sch_tx_burst_ongoing : 1, - current_tx_duration : 16; - uint32_t next_rx_active_time : 16, - remaining_fes_time : 16; - uint32_t tx_antenna_mask : 8, - shared_ant_tx_pwr : 8, - other_ant_tx_pwr : 8, - reserved_2 : 8; - uint32_t tlv64_padding : 32; -#else - uint32_t current_tx_duration : 16, - sch_tx_burst_ongoing : 1, - fes_tx_is_gen_frame : 1, - tx_wait_ack : 1, - tx_status_reason : 3, - tx_bw : 3, - reserved_0a : 7; - uint32_t remaining_fes_time : 16, - next_rx_active_time : 16; - uint32_t reserved_2 : 8, - other_ant_tx_pwr : 8, - shared_ant_tx_pwr : 8, - tx_antenna_mask : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_RESERVED_0A_LSB 0 -#define COEX_TX_STATUS_RESERVED_0A_MSB 6 -#define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f - -#define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_BW_LSB 7 -#define COEX_TX_STATUS_TX_BW_MSB 9 -#define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380 - -#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10 -#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12 -#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00 - -#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13 -#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13 -#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000 - -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000 - -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000 - -#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000 - -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000 - -#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48 -#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63 -#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000 - -#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff - -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00 - -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000 - -#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_RESERVED_2_LSB 24 -#define COEX_TX_STATUS_RESERVED_2_MSB 31 -#define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000 - -#define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_TLV64_PADDING_LSB 32 -#define COEX_TX_STATUS_TLV64_PADDING_MSB 63 -#define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/com_dtypes.h b/drivers/staging/fw-api/hw/fig/v2/com_dtypes.h deleted file mode 100644 index aa7bf7a51845..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/com_dtypes.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef COM_DTYPES_H -#define COM_DTYPES_H - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef T_WINNT - #ifndef WIN32 - #define WIN32 - #endif - #include -#endif - -#ifdef TRUE -#undef TRUE -#endif - -#ifdef FALSE -#undef FALSE -#endif - -#define TRUE 1 -#define FALSE 0 - -#define ON 1 -#define OFF 0 - -#ifndef NULL - #define NULL 0 -#endif - -#ifndef _ARM_ASM_ -#ifndef _BOOLEAN_DEFINED - -typedef unsigned char boolean; -#define _BOOLEAN_DEFINED -#endif - -#if defined(DALSTDDEF_H) -#define _BOOLEAN_DEFINED -#define _UINT32_DEFINED -#define _UINT16_DEFINED -#define _UINT8_DEFINED -#define _INT32_DEFINED -#define _INT16_DEFINED -#define _INT8_DEFINED -#define _UINT64_DEFINED -#define _INT64_DEFINED -#define _BYTE_DEFINED -#endif - -#ifndef _UINT32_DEFINED - -typedef unsigned int uint32; -#define _UINT32_DEFINED -#endif - -#ifndef _UINT16_DEFINED - -typedef unsigned short uint16; -#define _UINT16_DEFINED -#endif - -#ifndef _UINT8_DEFINED - -typedef unsigned char uint8; -#define _UINT8_DEFINED -#endif - -#ifndef _INT32_DEFINED - -typedef signed int int32; -#define _INT32_DEFINED -#endif - -#ifndef _INT16_DEFINED - -typedef signed short int16; -#define _INT16_DEFINED -#endif - -#ifndef _INT8_DEFINED - -typedef signed char int8; -#define _INT8_DEFINED -#endif - -#ifndef _BYTE_DEFINED - -typedef unsigned char byte; -#define _BYTE_DEFINED -#endif - -typedef unsigned short word; - -typedef unsigned long dword; - -typedef unsigned char uint1; - -typedef unsigned short uint2; - -typedef unsigned long uint4; - -typedef signed char int1; - -typedef signed short int2; - -typedef long int int4; - -typedef signed long sint31; - -typedef signed short sint15; - -typedef signed char sint7; - -typedef uint16 UWord16 ; -typedef uint32 UWord32 ; -typedef int32 Word32 ; -typedef int16 Word16 ; -typedef uint8 UWord8 ; -typedef int8 Word8 ; -typedef int32 Vect32 ; - -#if (! defined T_WINNT) && (! defined __GNUC__) - - #ifndef _INT64_DEFINED - - typedef long long int64; - #define _INT64_DEFINED - #endif - #ifndef _UINT64_DEFINED - - typedef unsigned long long uint64; - #define _UINT64_DEFINED - #endif -#else - - #if (defined __GNUC__) - #ifndef _INT64_DEFINED - typedef long long int64; - #define _INT64_DEFINED - #endif - #ifndef _UINT64_DEFINED - typedef unsigned long long uint64; - #define _UINT64_DEFINED - #endif - #else - typedef __int64 int64; - #ifndef _UINT64_DEFINED - typedef unsigned __int64 uint64; - #define _UINT64_DEFINED - #endif - #endif -#endif - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_mu_mimo_info.h b/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_mu_mimo_info.h deleted file mode 100644 index c9e20d75e648..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_mu_mimo_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_ -#define _EHT_SIG_USR_MU_MIMO_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2 - -struct eht_sig_usr_mu_mimo_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - sta_coding : 1, - sta_spatial_config : 6, - reserved_0a : 1, - rx_integrity_check_passed : 1, - subband80_cc_mask : 8; - uint32_t user_order_subband80_0 : 8, - user_order_subband80_1 : 8, - user_order_subband80_2 : 8, - user_order_subband80_3 : 8; -#else - uint32_t subband80_cc_mask : 8, - rx_integrity_check_passed : 1, - reserved_0a : 1, - sta_spatial_config : 6, - sta_coding : 1, - sta_mcs : 4, - sta_id : 11; - uint32_t user_order_subband80_3 : 8, - user_order_subband80_2 : 8, - user_order_subband80_1 : 8, - user_order_subband80_0 : 8; -#endif -}; - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000 - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000 - -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000 - -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 - -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_ofdma_info.h b/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_ofdma_info.h deleted file mode 100644 index f2520cccfde9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_ofdma_info.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_OFDMA_INFO_H_ -#define _EHT_SIG_USR_OFDMA_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2 - -struct eht_sig_usr_ofdma_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - validate_0a : 1, - nss : 4, - txbf : 1, - sta_coding : 1, - reserved_0b : 1, - rx_integrity_check_passed : 1, - subband80_cc_mask : 8; - uint32_t user_order_subband80_0 : 8, - user_order_subband80_1 : 8, - user_order_subband80_2 : 8, - user_order_subband80_3 : 8; -#else - uint32_t subband80_cc_mask : 8, - rx_integrity_check_passed : 1, - reserved_0b : 1, - sta_coding : 1, - txbf : 1, - nss : 4, - validate_0a : 1, - sta_mcs : 4, - sta_id : 11; - uint32_t user_order_subband80_3 : 8, - user_order_subband80_2 : 8, - user_order_subband80_1 : 8, - user_order_subband80_0 : 8; -#endif -}; - -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000 - -#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16 -#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19 -#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000 - -#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000 - -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000 - -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000 - -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 - -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_su_info.h b/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_su_info.h deleted file mode 100644 index 208cb4de0539..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/eht_sig_usr_su_info.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_SU_INFO_H_ -#define _EHT_SIG_USR_SU_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1 - -struct eht_sig_usr_su_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - validate_0a : 1, - nss : 4, - txbf : 1, - sta_coding : 1, - reserved_0b : 9, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0b : 9, - sta_coding : 1, - txbf : 1, - nss : 4, - validate_0a : 1, - sta_mcs : 4, - sta_id : 11; -#endif -}; - -#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000 - -#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_NSS_LSB 16 -#define EHT_SIG_USR_SU_INFO_NSS_MSB 19 -#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000 - -#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20 -#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20 -#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000 - -#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21 -#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21 -#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000 - -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000 - -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/expected_response.h b/drivers/staging/fw-api/hw/fig/v2/expected_response.h deleted file mode 100644 index b3ec83ceccf8..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/expected_response.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EXPECTED_RESPONSE_H_ -#define _EXPECTED_RESPONSE_H_ - -#define NUM_OF_DWORDS_EXPECTED_RESPONSE 6 - -#define NUM_OF_QWORDS_EXPECTED_RESPONSE 3 - -struct expected_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_ad2_31_0 : 32; - uint32_t tx_ad2_47_32 : 16, - expected_response_type : 5, - response_to_response : 3, - su_ba_user_number : 1, - response_info_part2_required : 1, - transmitted_bssid_check_en : 1, - eht___reserved_g_0022_ndp_expected : 1, - reserved_1 : 4; - uint32_t ndp_sta_partial_aid_2_8_0 : 11, - reserved_2 : 10, - ndp_sta_partial_aid1_8_0 : 11; - uint32_t ast_index : 16, - capture_ack_ba_sounding : 1, - capture_sounding_1str_20mhz : 1, - capture_sounding_1str_40mhz : 1, - capture_sounding_1str_80mhz : 1, - capture_sounding_1str_160mhz : 1, - capture_sounding_1str_240mhz : 1, - capture_sounding_1str_320mhz : 1, - reserved_3a : 9; - uint32_t fcs : 9, - expect_rx_with_blackout_details : 1, - crc : 4, - scrambler_seed : 7, - reserved_4b : 11; - uint32_t tlv64_padding : 32; -#else - uint32_t tx_ad2_31_0 : 32; - uint32_t reserved_1 : 4, - eht___reserved_g_0022_ndp_expected : 1, - transmitted_bssid_check_en : 1, - response_info_part2_required : 1, - su_ba_user_number : 1, - response_to_response : 3, - expected_response_type : 5, - tx_ad2_47_32 : 16; - uint32_t ndp_sta_partial_aid1_8_0 : 11, - reserved_2 : 10, - ndp_sta_partial_aid_2_8_0 : 11; - uint32_t reserved_3a : 9, - capture_sounding_1str_320mhz : 1, - capture_sounding_1str_240mhz : 1, - capture_sounding_1str_160mhz : 1, - capture_sounding_1str_80mhz : 1, - capture_sounding_1str_40mhz : 1, - capture_sounding_1str_20mhz : 1, - capture_ack_ba_sounding : 1, - ast_index : 16; - uint32_t reserved_4b : 11, - scrambler_seed : 7, - crc : 4, - expect_rx_with_blackout_details : 1, - fcs : 9; - uint32_t tlv64_padding : 32; -#endif -}; - -#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 -#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 -#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff - -#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32 -#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47 -#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000 - -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000 - -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000 - -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000 - -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000 - -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000 - -#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESERVED_1_LSB 60 -#define EXPECTED_RESPONSE_RESERVED_1_MSB 63 -#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf000000000000000 - -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff - -#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_RESERVED_2_LSB 11 -#define EXPECTED_RESPONSE_RESERVED_2_MSB 20 -#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800 - -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000 - -#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_AST_INDEX_LSB 32 -#define EXPECTED_RESPONSE_AST_INDEX_MSB 47 -#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000 - -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000 - -#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_RESERVED_3A_LSB 55 -#define EXPECTED_RESPONSE_RESERVED_3A_MSB 63 -#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000 - -#define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_FCS_LSB 0 -#define EXPECTED_RESPONSE_FCS_MSB 8 -#define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff - -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB 9 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB 9 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK 0x0000000000000200 - -#define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_CRC_LSB 10 -#define EXPECTED_RESPONSE_CRC_MSB 13 -#define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00 - -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000 - -#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 -#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 -#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000 - -#define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32 -#define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63 -#define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/he_sig_a_mu_dl_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_a_mu_dl_info.h deleted file mode 100644 index 84571eb65d3b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/he_sig_a_mu_dl_info.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_MU_DL_INFO_H_ -#define _HE_SIG_A_MU_DL_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 - -struct he_sig_a_mu_dl_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dl_ul_flag : 1, - mcs_of_sig_b : 3, - dcm_of_sig_b : 1, - bss_color_id : 6, - spatial_reuse : 4, - transmit_bw : 3, - num_sig_b_symbols : 4, - comp_mode_sig_b : 1, - cp_ltf_size : 2, - doppler_indication : 1, - reserved_0a : 6; - uint32_t txop_duration : 7, - reserved_1a : 1, - num_ltf_symbols : 3, - ldpc_extra_symbol : 1, - stbc : 1, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - crc : 4, - tail : 6, - reserved_1b : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0a : 6, - doppler_indication : 1, - cp_ltf_size : 2, - comp_mode_sig_b : 1, - num_sig_b_symbols : 4, - transmit_bw : 3, - spatial_reuse : 4, - bss_color_id : 6, - dcm_of_sig_b : 1, - mcs_of_sig_b : 3, - dl_ul_flag : 1; - uint32_t rx_integrity_check_passed : 1, - reserved_1b : 5, - tail : 6, - crc : 4, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - stbc : 1, - ldpc_extra_symbol : 1, - num_ltf_symbols : 3, - reserved_1a : 1, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001 - -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e - -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010 - -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0 - -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800 - -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000 - -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 - -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000 - -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000 - -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000 - -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000 - -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080 - -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700 - -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800 - -#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12 -#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12 -#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000 - -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 - -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 - -#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16 -#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19 -#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20 -#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25 -#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000 - -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/he_sig_a_mu_ul_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_a_mu_ul_info.h deleted file mode 100644 index e2d0ad73a66c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/he_sig_a_mu_ul_info.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_MU_UL_INFO_H_ -#define _HE_SIG_A_MU_UL_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 - -struct he_sig_a_mu_ul_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t format_indication : 1, - bss_color_id : 6, - spatial_reuse : 16, - reserved_0a : 1, - transmit_bw : 2, - reserved_0b : 6; - uint32_t txop_duration : 7, - reserved_1a : 9, - crc : 4, - tail : 6, - reserved_1b : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0b : 6, - transmit_bw : 2, - reserved_0a : 1, - spatial_reuse : 16, - bss_color_id : 6, - format_indication : 1; - uint32_t rx_integrity_check_passed : 1, - reserved_1b : 5, - tail : 6, - crc : 4, - reserved_1a : 9, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001 - -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e - -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000 - -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000 - -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80 - -#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16 -#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19 -#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20 -#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25 -#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000 - -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/he_sig_a_su_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_a_su_info.h deleted file mode 100644 index e4be3671016e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/he_sig_a_su_info.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_SU_INFO_H_ -#define _HE_SIG_A_SU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2 - -struct he_sig_a_su_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t format_indication : 1, - beam_change : 1, - dl_ul_flag : 1, - transmit_mcs : 4, - dcm : 1, - bss_color_id : 6, - reserved_0a : 1, - spatial_reuse : 4, - transmit_bw : 2, - cp_ltf_size : 2, - nsts : 3, - reserved_0b : 6; - uint32_t txop_duration : 7, - coding : 1, - ldpc_extra_symbol : 1, - stbc : 1, - txbf : 1, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - reserved_1a : 1, - doppler_indication : 1, - crc : 4, - tail : 6, - dot11ax_su_extended : 1, - dot11ax_ext_ru_size : 3, - rx_ndp : 1, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0b : 6, - nsts : 3, - cp_ltf_size : 2, - transmit_bw : 2, - spatial_reuse : 4, - reserved_0a : 1, - bss_color_id : 6, - dcm : 1, - transmit_mcs : 4, - dl_ul_flag : 1, - beam_change : 1, - format_indication : 1; - uint32_t rx_integrity_check_passed : 1, - rx_ndp : 1, - dot11ax_ext_ru_size : 3, - dot11ax_su_extended : 1, - tail : 6, - crc : 4, - doppler_indication : 1, - reserved_1a : 1, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - txbf : 1, - stbc : 1, - ldpc_extra_symbol : 1, - coding : 1, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001 - -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002 - -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004 - -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078 - -#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_DCM_LSB 7 -#define HE_SIG_A_SU_INFO_DCM_MSB 7 -#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080 - -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00 - -#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000 - -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000 - -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000 - -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000 - -#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_NSTS_LSB 23 -#define HE_SIG_A_SU_INFO_NSTS_MSB 25 -#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000 - -#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26 -#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31 -#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000 - -#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_CODING_LSB 7 -#define HE_SIG_A_SU_INFO_CODING_MSB 7 -#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080 - -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100 - -#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_STBC_LSB 9 -#define HE_SIG_A_SU_INFO_STBC_MSB 9 -#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200 - -#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TXBF_LSB 10 -#define HE_SIG_A_SU_INFO_TXBF_MSB 10 -#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400 - -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 - -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 - -#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000 - -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000 - -#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_CRC_LSB 16 -#define HE_SIG_A_SU_INFO_CRC_MSB 19 -#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TAIL_LSB 20 -#define HE_SIG_A_SU_INFO_TAIL_MSB 25 -#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 - -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 - -#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30 -#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30 -#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000 - -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/he_sig_b1_mu_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_b1_mu_info.h deleted file mode 100644 index a248c3dc67b3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/he_sig_b1_mu_info.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B1_MU_INFO_H_ -#define _HE_SIG_B1_MU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 - -struct he_sig_b1_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_allocation : 8, - reserved_0 : 23, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0 : 23, - ru_allocation : 8; -#endif -}; - -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff - -#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8 -#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30 -#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00 - -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/he_sig_b2_mu_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_b2_mu_info.h deleted file mode 100644 index 83d6f3bc843f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/he_sig_b2_mu_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B2_MU_INFO_H_ -#define _HE_SIG_B2_MU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2 - -struct he_sig_b2_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_spatial_config : 4, - sta_mcs : 4, - reserved_set_to_1 : 1, - sta_coding : 1, - reserved_0a : 7, - nsts : 3, - rx_integrity_check_passed : 1; - uint32_t user_order : 8, - cc_mask : 8, - reserved_1a : 16; -#else - uint32_t rx_integrity_check_passed : 1, - nsts : 3, - reserved_0a : 7, - sta_coding : 1, - reserved_set_to_1 : 1, - sta_mcs : 4, - sta_spatial_config : 4, - sta_id : 11; - uint32_t reserved_1a : 16, - cc_mask : 8, - user_order : 8; -#endif -}; - -#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0 -#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10 -#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff - -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800 - -#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15 -#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18 -#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000 - -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000 - -#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20 -#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20 -#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000 - -#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000 - -#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_NSTS_LSB 28 -#define HE_SIG_B2_MU_INFO_NSTS_MSB 30 -#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000 - -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0 -#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7 -#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff - -#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_CC_MASK_LSB 8 -#define HE_SIG_B2_MU_INFO_CC_MASK_MSB 15 -#define HE_SIG_B2_MU_INFO_CC_MASK_MASK 0x0000ff00 - -#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 16 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/he_sig_b2_ofdma_info.h b/drivers/staging/fw-api/hw/fig/v2/he_sig_b2_ofdma_info.h deleted file mode 100644 index 6357d216eb3a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/he_sig_b2_ofdma_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B2_OFDMA_INFO_H_ -#define _HE_SIG_B2_OFDMA_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2 - -struct he_sig_b2_ofdma_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - nsts : 3, - txbf : 1, - sta_mcs : 4, - sta_dcm : 1, - sta_coding : 1, - reserved_0 : 10, - rx_integrity_check_passed : 1; - uint32_t user_order : 8, - cc_mask : 8, - reserved_1a : 16; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0 : 10, - sta_coding : 1, - sta_dcm : 1, - sta_mcs : 4, - txbf : 1, - nsts : 3, - sta_id : 11; - uint32_t reserved_1a : 16, - cc_mask : 8, - user_order : 8; -#endif -}; - -#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff - -#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11 -#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13 -#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800 - -#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14 -#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14 -#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000 - -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000 - -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000 - -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000 - -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000 - -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff - -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00 - -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/ht_sig_info.h b/drivers/staging/fw-api/hw/fig/v2/ht_sig_info.h deleted file mode 100644 index d6a4a719e6e2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/ht_sig_info.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HT_SIG_INFO_H_ -#define _HT_SIG_INFO_H_ - -#define NUM_OF_DWORDS_HT_SIG_INFO 2 - -struct ht_sig_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mcs : 7, - cbw : 1, - length : 16, - reserved_0 : 8; - uint32_t smoothing : 1, - not_sounding : 1, - ht_reserved : 1, - aggregation : 1, - stbc : 2, - fec_coding : 1, - short_gi : 1, - num_ext_sp_str : 2, - crc : 8, - signal_tail : 6, - reserved_1 : 7, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0 : 8, - length : 16, - cbw : 1, - mcs : 7; - uint32_t rx_integrity_check_passed : 1, - reserved_1 : 7, - signal_tail : 6, - crc : 8, - num_ext_sp_str : 2, - short_gi : 1, - fec_coding : 1, - stbc : 2, - aggregation : 1, - ht_reserved : 1, - not_sounding : 1, - smoothing : 1; -#endif -}; - -#define HT_SIG_INFO_MCS_OFFSET 0x00000000 -#define HT_SIG_INFO_MCS_LSB 0 -#define HT_SIG_INFO_MCS_MSB 6 -#define HT_SIG_INFO_MCS_MASK 0x0000007f - -#define HT_SIG_INFO_CBW_OFFSET 0x00000000 -#define HT_SIG_INFO_CBW_LSB 7 -#define HT_SIG_INFO_CBW_MSB 7 -#define HT_SIG_INFO_CBW_MASK 0x00000080 - -#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000 -#define HT_SIG_INFO_LENGTH_LSB 8 -#define HT_SIG_INFO_LENGTH_MSB 23 -#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00 - -#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000 -#define HT_SIG_INFO_RESERVED_0_LSB 24 -#define HT_SIG_INFO_RESERVED_0_MSB 31 -#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000 - -#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004 -#define HT_SIG_INFO_SMOOTHING_LSB 0 -#define HT_SIG_INFO_SMOOTHING_MSB 0 -#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001 - -#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004 -#define HT_SIG_INFO_NOT_SOUNDING_LSB 1 -#define HT_SIG_INFO_NOT_SOUNDING_MSB 1 -#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002 - -#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004 -#define HT_SIG_INFO_HT_RESERVED_LSB 2 -#define HT_SIG_INFO_HT_RESERVED_MSB 2 -#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004 - -#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004 -#define HT_SIG_INFO_AGGREGATION_LSB 3 -#define HT_SIG_INFO_AGGREGATION_MSB 3 -#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008 - -#define HT_SIG_INFO_STBC_OFFSET 0x00000004 -#define HT_SIG_INFO_STBC_LSB 4 -#define HT_SIG_INFO_STBC_MSB 5 -#define HT_SIG_INFO_STBC_MASK 0x00000030 - -#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004 -#define HT_SIG_INFO_FEC_CODING_LSB 6 -#define HT_SIG_INFO_FEC_CODING_MSB 6 -#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040 - -#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004 -#define HT_SIG_INFO_SHORT_GI_LSB 7 -#define HT_SIG_INFO_SHORT_GI_MSB 7 -#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080 - -#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004 -#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8 -#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9 -#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300 - -#define HT_SIG_INFO_CRC_OFFSET 0x00000004 -#define HT_SIG_INFO_CRC_LSB 10 -#define HT_SIG_INFO_CRC_MSB 17 -#define HT_SIG_INFO_CRC_MASK 0x0003fc00 - -#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004 -#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18 -#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23 -#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000 - -#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004 -#define HT_SIG_INFO_RESERVED_1_LSB 24 -#define HT_SIG_INFO_RESERVED_1_MSB 30 -#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000 - -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/l_sig_a_info.h b/drivers/staging/fw-api/hw/fig/v2/l_sig_a_info.h deleted file mode 100644 index 6da0725dfee7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/l_sig_a_info.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _L_SIG_A_INFO_H_ -#define _L_SIG_A_INFO_H_ - -#define NUM_OF_DWORDS_L_SIG_A_INFO 1 - -struct l_sig_a_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rate : 4, - lsig_reserved : 1, - length : 12, - parity : 1, - tail : 6, - pkt_type : 4, - captured_implicit_sounding : 1, - reserved : 2, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved : 2, - captured_implicit_sounding : 1, - pkt_type : 4, - tail : 6, - parity : 1, - length : 12, - lsig_reserved : 1, - rate : 4; -#endif -}; - -#define L_SIG_A_INFO_RATE_OFFSET 0x00000000 -#define L_SIG_A_INFO_RATE_LSB 0 -#define L_SIG_A_INFO_RATE_MSB 3 -#define L_SIG_A_INFO_RATE_MASK 0x0000000f - -#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000 -#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4 -#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4 -#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010 - -#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000 -#define L_SIG_A_INFO_LENGTH_LSB 5 -#define L_SIG_A_INFO_LENGTH_MSB 16 -#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0 - -#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000 -#define L_SIG_A_INFO_PARITY_LSB 17 -#define L_SIG_A_INFO_PARITY_MSB 17 -#define L_SIG_A_INFO_PARITY_MASK 0x00020000 - -#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000 -#define L_SIG_A_INFO_TAIL_LSB 18 -#define L_SIG_A_INFO_TAIL_MSB 23 -#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000 - -#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000 -#define L_SIG_A_INFO_PKT_TYPE_LSB 24 -#define L_SIG_A_INFO_PKT_TYPE_MSB 27 -#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000 - -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 - -#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000 -#define L_SIG_A_INFO_RESERVED_LSB 29 -#define L_SIG_A_INFO_RESERVED_MSB 30 -#define L_SIG_A_INFO_RESERVED_MASK 0x60000000 - -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/l_sig_b_info.h b/drivers/staging/fw-api/hw/fig/v2/l_sig_b_info.h deleted file mode 100644 index f2052702e2de..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/l_sig_b_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _L_SIG_B_INFO_H_ -#define _L_SIG_B_INFO_H_ - -#define NUM_OF_DWORDS_L_SIG_B_INFO 1 - -struct l_sig_b_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rate : 4, - length : 12, - reserved : 15, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved : 15, - length : 12, - rate : 4; -#endif -}; - -#define L_SIG_B_INFO_RATE_OFFSET 0x00000000 -#define L_SIG_B_INFO_RATE_LSB 0 -#define L_SIG_B_INFO_RATE_MSB 3 -#define L_SIG_B_INFO_RATE_MASK 0x0000000f - -#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000 -#define L_SIG_B_INFO_LENGTH_LSB 4 -#define L_SIG_B_INFO_LENGTH_MSB 15 -#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0 - -#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000 -#define L_SIG_B_INFO_RESERVED_LSB 16 -#define L_SIG_B_INFO_RESERVED_MSB 30 -#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000 - -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/macrx_abort_request_info.h b/drivers/staging/fw-api/hw/fig/v2/macrx_abort_request_info.h deleted file mode 100644 index 038f4038fa59..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/macrx_abort_request_info.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACRX_ABORT_REQUEST_INFO_H_ -#define _MACRX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1 - -struct macrx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t macrx_abort_reason : 8, - reserved_0 : 8; -#else - uint16_t reserved_0 : 8, - macrx_abort_reason : 8; -#endif -}; - -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff - -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_mu_mimo.h b/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_mu_mimo.h deleted file mode 100644 index f29ca356a223..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_mu_mimo.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_ -#define _MACTX_EHT_SIG_USR_MU_MIMO_H_ - -#include "eht_sig_usr_mu_mimo_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1 - -struct mactx_eht_sig_usr_mu_mimo { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; -#else - struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; -#endif -}; - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_ofdma.h b/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_ofdma.h deleted file mode 100644 index 24bf6691978d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_ofdma.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_ -#define _MACTX_EHT_SIG_USR_OFDMA_H_ - -#include "eht_sig_usr_ofdma_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_OFDMA 1 - -struct mactx_eht_sig_usr_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; -#else - struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; -#endif -}; - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x00000000000f0000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000100000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x0000000000400000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_su.h b/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_su.h deleted file mode 100644 index 1fb82723c1ff..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_eht_sig_usr_su.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_SU_H_ -#define _MACTX_EHT_SIG_USR_SU_H_ - -#include "eht_sig_usr_su_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_SU 1 - -struct mactx_eht_sig_usr_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; - uint32_t tlv64_padding : 32; -#else - struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x00000000000f0000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x0000000000100000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x000000007fc00000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_LSB 32 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MSB 63 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_mu_dl.h deleted file mode 100644 index 438f3af6f9e7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_mu_dl.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_MU_DL_H_ -#define _MACTX_HE_SIG_A_MU_DL_H_ - -#include "he_sig_a_mu_dl_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_DL 1 - -struct mactx_he_sig_a_mu_dl { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; -#else - struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_mu_ul.h deleted file mode 100644 index 96d2b912665a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_mu_ul.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_MU_UL_H_ -#define _MACTX_HE_SIG_A_MU_UL_H_ - -#include "he_sig_a_mu_ul_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_UL 1 - -struct mactx_he_sig_a_mu_ul { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; -#else - struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_su.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_su.h deleted file mode 100644 index e51241d26559..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_a_su.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_SU_H_ -#define _MACTX_HE_SIG_A_SU_H_ - -#include "he_sig_a_su_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_SU 1 - -struct mactx_he_sig_a_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_su_info mactx_he_sig_a_su_info_details; -#else - struct he_sig_a_su_info mactx_he_sig_a_su_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b1_mu.h deleted file mode 100644 index 700528af2048..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b1_mu.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B1_MU_H_ -#define _MACTX_HE_SIG_B1_MU_H_ - -#include "he_sig_b1_mu_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1 - -struct mactx_he_sig_b1_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#else - struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b2_mu.h deleted file mode 100644 index ccc1c593fed6..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b2_mu.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B2_MU_H_ -#define _MACTX_HE_SIG_B2_MU_H_ - -#include "he_sig_b2_mu_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_MU 1 - -struct mactx_he_sig_b2_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; -#else - struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; -#endif -}; - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b2_ofdma.h deleted file mode 100644 index afc3c4b22841..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_he_sig_b2_ofdma.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B2_OFDMA_H_ -#define _MACTX_HE_SIG_B2_OFDMA_H_ - -#include "he_sig_b2_ofdma_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_OFDMA 1 - -struct mactx_he_sig_b2_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; -#else - struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; -#endif -}; - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_ht_sig.h b/drivers/staging/fw-api/hw/fig/v2/mactx_ht_sig.h deleted file mode 100644 index ec28824c590f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_ht_sig.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HT_SIG_H_ -#define _MACTX_HT_SIG_H_ - -#include "ht_sig_info.h" -#define NUM_OF_DWORDS_MACTX_HT_SIG 2 - -#define NUM_OF_QWORDS_MACTX_HT_SIG 1 - -struct mactx_ht_sig { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ht_sig_info mactx_ht_sig_info_details; -#else - struct ht_sig_info mactx_ht_sig_info_details; -#endif -}; - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 36 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 37 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 42 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 49 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_l_sig_a.h b/drivers/staging/fw-api/hw/fig/v2/mactx_l_sig_a.h deleted file mode 100644 index 061e46e28a2c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_l_sig_a.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_L_SIG_A_H_ -#define _MACTX_L_SIG_A_H_ - -#include "l_sig_a_info.h" -#define NUM_OF_DWORDS_MACTX_L_SIG_A 2 - -#define NUM_OF_QWORDS_MACTX_L_SIG_A 1 - -struct mactx_l_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_a_info mactx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_a_info mactx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_TLV64_PADDING_LSB 32 -#define MACTX_L_SIG_A_TLV64_PADDING_MSB 63 -#define MACTX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_l_sig_b.h b/drivers/staging/fw-api/hw/fig/v2/mactx_l_sig_b.h deleted file mode 100644 index 6d533acef675..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_l_sig_b.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_L_SIG_B_H_ -#define _MACTX_L_SIG_B_H_ - -#include "l_sig_b_info.h" -#define NUM_OF_DWORDS_MACTX_L_SIG_B 2 - -#define NUM_OF_QWORDS_MACTX_L_SIG_B 1 - -struct mactx_l_sig_b { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_b_info mactx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_b_info mactx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_TLV64_PADDING_LSB 32 -#define MACTX_L_SIG_B_TLV64_PADDING_MSB 63 -#define MACTX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_phy_desc.h b/drivers/staging/fw-api/hw/fig/v2/mactx_phy_desc.h deleted file mode 100644 index ee4ccdf65c28..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_phy_desc.h +++ /dev/null @@ -1,348 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_PHY_DESC_H_ -#define _MACTX_PHY_DESC_H_ - -#define NUM_OF_DWORDS_MACTX_PHY_DESC 4 - -#define NUM_OF_QWORDS_MACTX_PHY_DESC 2 - -struct mactx_phy_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 16, - bf_type : 2, - wait_sifs : 2, - dot11b_preamble_type : 1, - pkt_type : 4, - su_or_mu : 2, - mu_type : 1, - bandwidth : 3, - channel_capture : 1; - uint32_t mcs : 5, - global_ofdma_mimo_enable : 1, - stbc : 1, - dot11ax_su_extended : 1, - dot11ax_trigger_frame_embedded : 1, - tx_pwr_shared : 8, - tx_pwr_unshared : 8, - measure_power : 1, - tpc_glut_self_cal : 1, - back_to_back_transmission_expected : 1, - heavy_clip_nss : 3, - txbf_per_packet_no_csd_no_walsh : 1; - uint32_t ndp : 3, - ul_flag : 1, - triggered : 1, - ap_pkt_bw : 3, - ru_position_start : 8, - pcu_ppdu_setup_start_reason : 3, - tlv_source : 1, - reserved_2a : 1, - nss : 3, - stream_offset : 3, - reserved_2b : 2, - clpc_enable : 1, - mu_ndp : 1, - response_expected : 1; - uint32_t rx_chain_mask : 8, - rx_chain_mask_valid : 1, - ant_sel_valid : 1, - ant_sel : 1, - cp_setting : 2, - he_ppdu_subtype : 2, - active_channel : 3, - generate_phyrx_tx_start_timing : 1, - ltf_size : 2, - ru_size_updated_v2 : 4, - reserved_3c : 1, - u_sig_puncture_pattern_encoding : 6; -#else - uint32_t channel_capture : 1, - bandwidth : 3, - mu_type : 1, - su_or_mu : 2, - pkt_type : 4, - dot11b_preamble_type : 1, - wait_sifs : 2, - bf_type : 2, - reserved_0a : 16; - uint32_t txbf_per_packet_no_csd_no_walsh : 1, - heavy_clip_nss : 3, - back_to_back_transmission_expected : 1, - tpc_glut_self_cal : 1, - measure_power : 1, - tx_pwr_unshared : 8, - tx_pwr_shared : 8, - dot11ax_trigger_frame_embedded : 1, - dot11ax_su_extended : 1, - stbc : 1, - global_ofdma_mimo_enable : 1, - mcs : 5; - uint32_t response_expected : 1, - mu_ndp : 1, - clpc_enable : 1, - reserved_2b : 2, - stream_offset : 3, - nss : 3, - reserved_2a : 1, - tlv_source : 1, - pcu_ppdu_setup_start_reason : 3, - ru_position_start : 8, - ap_pkt_bw : 3, - triggered : 1, - ul_flag : 1, - ndp : 3; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_3c : 1, - ru_size_updated_v2 : 4, - ltf_size : 2, - generate_phyrx_tx_start_timing : 1, - active_channel : 3, - he_ppdu_subtype : 2, - cp_setting : 2, - ant_sel : 1, - ant_sel_valid : 1, - rx_chain_mask_valid : 1, - rx_chain_mask : 8; -#endif -}; - -#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_RESERVED_0A_LSB 0 -#define MACTX_PHY_DESC_RESERVED_0A_MSB 15 -#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff - -#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BF_TYPE_LSB 16 -#define MACTX_PHY_DESC_BF_TYPE_MSB 17 -#define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000 - -#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 -#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 -#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000 - -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000 - -#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_PKT_TYPE_LSB 21 -#define MACTX_PHY_DESC_PKT_TYPE_MSB 24 -#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000 - -#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_SU_OR_MU_LSB 25 -#define MACTX_PHY_DESC_SU_OR_MU_MSB 26 -#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000 - -#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MU_TYPE_LSB 27 -#define MACTX_PHY_DESC_MU_TYPE_MSB 27 -#define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000 - -#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BANDWIDTH_LSB 28 -#define MACTX_PHY_DESC_BANDWIDTH_MSB 30 -#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000 - -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000 - -#define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MCS_LSB 32 -#define MACTX_PHY_DESC_MCS_MSB 36 -#define MACTX_PHY_DESC_MCS_MASK 0x0000001f00000000 - -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 37 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 37 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000002000000000 - -#define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_STBC_LSB 38 -#define MACTX_PHY_DESC_STBC_MSB 38 -#define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000 - -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000 - -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000 - -#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41 -#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48 -#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000 - -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000 - -#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MEASURE_POWER_LSB 57 -#define MACTX_PHY_DESC_MEASURE_POWER_MSB 57 -#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000 - -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000 - -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000 - -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000 - -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000 - -#define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_NDP_LSB 0 -#define MACTX_PHY_DESC_NDP_MSB 2 -#define MACTX_PHY_DESC_NDP_MASK 0x0000000000000007 - -#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_UL_FLAG_LSB 3 -#define MACTX_PHY_DESC_UL_FLAG_MSB 3 -#define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000008 - -#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_TRIGGERED_LSB 4 -#define MACTX_PHY_DESC_TRIGGERED_MSB 4 -#define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000010 - -#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_AP_PKT_BW_LSB 5 -#define MACTX_PHY_DESC_AP_PKT_BW_MSB 7 -#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x00000000000000e0 - -#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RU_POSITION_START_LSB 8 -#define MACTX_PHY_DESC_RU_POSITION_START_MSB 15 -#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x000000000000ff00 - -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 16 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 18 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000070000 - -#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_TLV_SOURCE_LSB 19 -#define MACTX_PHY_DESC_TLV_SOURCE_MSB 19 -#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000080000 - -#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_2A_LSB 20 -#define MACTX_PHY_DESC_RESERVED_2A_MSB 20 -#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000100000 - -#define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_NSS_LSB 21 -#define MACTX_PHY_DESC_NSS_MSB 23 -#define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000 - -#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 -#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 -#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000 - -#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_2B_LSB 27 -#define MACTX_PHY_DESC_RESERVED_2B_MSB 28 -#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000 - -#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 -#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 -#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000 - -#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_MU_NDP_LSB 30 -#define MACTX_PHY_DESC_MU_NDP_MSB 30 -#define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000 - -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000 - -#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000 - -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000 - -#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41 -#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41 -#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000 - -#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ANT_SEL_LSB 42 -#define MACTX_PHY_DESC_ANT_SEL_MSB 42 -#define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000 - -#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_CP_SETTING_LSB 43 -#define MACTX_PHY_DESC_CP_SETTING_MSB 44 -#define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000 - -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000 - -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000 - -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000 - -#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_LTF_SIZE_LSB 51 -#define MACTX_PHY_DESC_LTF_SIZE_MSB 52 -#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000 - -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000 - -#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_3C_LSB 57 -#define MACTX_PHY_DESC_RESERVED_3C_MSB 57 -#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000 - -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_u_sig_eht_su_mu.h b/drivers/staging/fw-api/hw/fig/v2/mactx_u_sig_eht_su_mu.h deleted file mode 100644 index f46583e4c7ee..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_u_sig_eht_su_mu.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_U_SIG_EHT_SU_MU_H_ -#define _MACTX_U_SIG_EHT_SU_MU_H_ - -#include "u_sig_eht_su_mu_info.h" -#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2 - -#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_SU_MU 1 - -struct mactx_u_sig_eht_su_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; -#else - struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; -#endif -}; - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB 0 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB 2 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000001f00000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x0000000002000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 34 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 34 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 35 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 39 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f800000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 40 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 40 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x0000010000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 41 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 42 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x0000060000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 43 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 47 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f80000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 48 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 51 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 59 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 61 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x3800000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 62 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 62 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_u_sig_eht_tb.h b/drivers/staging/fw-api/hw/fig/v2/mactx_u_sig_eht_tb.h deleted file mode 100644 index 5e57312a9da2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_u_sig_eht_tb.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_U_SIG_EHT_TB_H_ -#define _MACTX_U_SIG_EHT_TB_H_ - -#include "u_sig_eht_tb_info.h" -#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2 - -#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1 - -struct mactx_u_sig_eht_tb { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; -#else - struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; -#endif -}; - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000003f00000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 34 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 34 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 35 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 42 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f800000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 43 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 47 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f80000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 48 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 51 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 58 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 62 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c00000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_user_desc_common.h b/drivers/staging/fw-api/hw/fig/v2/mactx_user_desc_common.h deleted file mode 100644 index 04124271bbc9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_user_desc_common.h +++ /dev/null @@ -1,482 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_USER_DESC_COMMON_H_ -#define _MACTX_USER_DESC_COMMON_H_ - -#include "unallocated_ru_160_info.h" -#include "ru_allocation_160_info.h" -#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 - -#define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8 - -struct mactx_user_desc_common { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t num_users : 6, - reserved_0b : 5, - ltf_size : 2, - reserved_0c : 3, - he_stf_long : 1, - reserved_0d : 7, - num_users_he_sigb_band0 : 8; - uint32_t num_ltf_symbols : 3, - reserved_1a : 5, - num_users_he_sigb_band1 : 8, - reserved_1b : 16; - uint32_t packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - packet_extension : 3, - reserved : 2, - he_sigb_dcm : 1, - reserved_2b : 7, - he_sigb_compression : 1, - reserved_2c : 15; - uint32_t he_sigb_0_mcs : 3, - reserved_3a : 13, - num_he_sigb_sym : 5, - center_ru_0 : 1, - center_ru_1 : 1, - reserved_3b : 1, - ftm_en : 1, - pe_nss : 3, - pe_ltf_size : 2, - pe_content : 1, - pe_chain_csd_en : 1; - struct ru_allocation_160_info ru_allocation_0123_details; - struct ru_allocation_160_info ru_allocation_4567_details; - struct unallocated_ru_160_info ru_allocation_160_0_details; - struct unallocated_ru_160_info ru_allocation_160_1_details; - uint32_t num_data_symbols : 16, - ndp_ru_tone_set_index : 7, - ndp_feedback_status : 1, - doppler_indication : 1, - reserved_14a : 7; - uint32_t spatial_reuse : 16, - distributed_ru : 1, - dru_spreading_bw : 2, - reserved_15a : 13; -#else - uint32_t num_users_he_sigb_band0 : 8, - reserved_0d : 7, - he_stf_long : 1, - reserved_0c : 3, - ltf_size : 2, - reserved_0b : 5, - num_users : 6; - uint32_t reserved_1b : 16, - num_users_he_sigb_band1 : 8, - reserved_1a : 5, - num_ltf_symbols : 3; - uint32_t reserved_2c : 15, - he_sigb_compression : 1, - reserved_2b : 7, - he_sigb_dcm : 1, - reserved : 2, - packet_extension : 3, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2; - uint32_t pe_chain_csd_en : 1, - pe_content : 1, - pe_ltf_size : 2, - pe_nss : 3, - ftm_en : 1, - reserved_3b : 1, - center_ru_1 : 1, - center_ru_0 : 1, - num_he_sigb_sym : 5, - reserved_3a : 13, - he_sigb_0_mcs : 3; - struct ru_allocation_160_info ru_allocation_0123_details; - struct ru_allocation_160_info ru_allocation_4567_details; - struct unallocated_ru_160_info ru_allocation_160_0_details; - struct unallocated_ru_160_info ru_allocation_160_1_details; - uint32_t reserved_14a : 7, - doppler_indication : 1, - ndp_feedback_status : 1, - ndp_ru_tone_set_index : 7, - num_data_symbols : 16; - uint32_t reserved_15a : 13, - dru_spreading_bw : 2, - distributed_ru : 1, - spatial_reuse : 16; -#endif -}; - -#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 -#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 -#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x000000000000003f - -#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x00000000000007c0 - -#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x0000000000001800 - -#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x000000000000e000 - -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x0000000000fe0000 - -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 32 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 34 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 35 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 39 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f800000000 - -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 40 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 47 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff0000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 48 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 63 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff000000000000 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x0000000000000038 - -#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 -#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 -#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x00000000000000c0 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x0000000000000100 - -#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x000000000000fe00 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0x00000000fffe0000 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 32 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 34 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x0000000700000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 35 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 47 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff800000000 - -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 48 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 52 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f000000000000 - -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 53 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 53 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x0020000000000000 - -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 54 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 54 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x0040000000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 55 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 55 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x0080000000000000 - -#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 56 -#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 56 -#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x0100000000000000 - -#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 57 -#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 59 -#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e00000000000000 - -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 60 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 61 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x3000000000000000 - -#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 62 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 62 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x4000000000000000 - -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 63 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 63 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x00000000000000ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x000000000000ff00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x0000000000ff0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 39 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 47 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 48 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 55 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 56 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff00000000000000 - -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x000000000000ffff - -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x00000000007f0000 - -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x0000000000800000 - -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x0000000001000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0x00000000fe000000 - -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 32 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 47 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_LSB 48 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MSB 48 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MASK 0x0001000000000000 - -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_LSB 49 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MSB 50 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MASK 0x0006000000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 51 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 63 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xfff8000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_user_desc_per_user.h b/drivers/staging/fw-api/hw/fig/v2/mactx_user_desc_per_user.h deleted file mode 100644 index a68b50d9d639..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_user_desc_per_user.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_USER_DESC_PER_USER_H_ -#define _MACTX_USER_DESC_PER_USER_H_ - -#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 6 - -#define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 3 - -struct mactx_user_desc_per_user { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t psdu_length : 24, - reserved_0a : 8; - uint32_t ru_start_index : 8, - ru_size : 4, - reserved_1b : 4, - ofdma_mu_mimo_enabled : 1, - nss : 3, - stream_offset : 3, - reserved_1c : 1, - mcs : 5, - dcm : 1, - reserved_1d : 2; - uint32_t fec_type : 1, - reserved_2a : 1, - qam_diff1 : 2, - qam_diff2 : 2, - qam_diff3 : 2, - user_bf_type : 2, - a_factor_ldpc2x : 2, - extra_sym_ldpc2x : 1, - cw_len_2x : 2, - reserved_2b : 1, - drop_user_cbf : 1, - a_factor_ldpc1x : 2, - extra_sym_ldpc1x : 1, - cw_len_1x : 2, - ldpc1x_used : 1, - ldpc2x_used : 1, - ldpc_extra_symbol : 1, - force_extra_symbol : 1, - ldpc_2x_codeword : 1, - reserved_2d : 5; - uint32_t sw_peer_id : 16, - per_user_subband_mask : 16; - uint32_t ldpc_num_avbits : 27, - reserved_4a : 5; - uint32_t num_cw_1x : 16, - num_cw_2x : 16; -#else - uint32_t reserved_0a : 8, - psdu_length : 24; - uint32_t reserved_1d : 2, - dcm : 1, - mcs : 5, - reserved_1c : 1, - stream_offset : 3, - nss : 3, - ofdma_mu_mimo_enabled : 1, - reserved_1b : 4, - ru_size : 4, - ru_start_index : 8; - uint32_t reserved_2d : 5, - ldpc_2x_codeword : 1, - force_extra_symbol : 1, - ldpc_extra_symbol : 1, - ldpc2x_used : 1, - ldpc1x_used : 1, - cw_len_1x : 2, - extra_sym_ldpc1x : 1, - a_factor_ldpc1x : 2, - drop_user_cbf : 1, - reserved_2b : 1, - cw_len_2x : 2, - extra_sym_ldpc2x : 1, - a_factor_ldpc2x : 2, - user_bf_type : 2, - qam_diff3 : 2, - qam_diff2 : 2, - qam_diff1 : 2, - reserved_2a : 1, - fec_type : 1; - uint32_t per_user_subband_mask : 16, - sw_peer_id : 16; - uint32_t reserved_4a : 5, - ldpc_num_avbits : 27; - uint32_t num_cw_2x : 16, - num_cw_1x : 16; -#endif -}; - -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x0000000000ffffff - -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 32 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 39 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff00000000 - -#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 40 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 43 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f0000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 44 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 47 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f00000000000 - -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 48 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 48 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x0001000000000000 - -#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_NSS_LSB 49 -#define MACTX_USER_DESC_PER_USER_NSS_MSB 51 -#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e000000000000 - -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 52 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 54 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x0070000000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 55 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 55 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x0080000000000000 - -#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_MCS_LSB 56 -#define MACTX_USER_DESC_PER_USER_MCS_MSB 60 -#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x1f00000000000000 - -#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_DCM_LSB 61 -#define MACTX_USER_DESC_PER_USER_DCM_MSB 61 -#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x2000000000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 62 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 63 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xc000000000000000 - -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x0000000000000001 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 1 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x0000000000000002 - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_LSB 2 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MSB 3 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MASK 0x000000000000000c - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_LSB 4 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MSB 5 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MASK 0x0000000000000030 - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_LSB 6 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MSB 7 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MASK 0x00000000000000c0 - -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x0000000000000300 - -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_LSB 10 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MSB 11 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MASK 0x0000000000000c00 - -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_LSB 12 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MSB 12 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MASK 0x0000000000001000 - -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_LSB 13 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MSB 14 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MASK 0x0000000000006000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 15 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x0000000000008000 - -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_LSB 17 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MSB 18 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MASK 0x0000000000060000 - -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_LSB 19 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MSB 19 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MASK 0x0000000000080000 - -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_LSB 20 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MSB 21 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MASK 0x0000000000300000 - -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_LSB 22 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MSB 22 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MASK 0x0000000000400000 - -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_LSB 23 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MSB 23 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MASK 0x0000000000800000 - -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x0000000001000000 - -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x0000000002000000 - -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_LSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MASK 0x0000000004000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 27 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0x00000000f8000000 - -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 32 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 47 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 48 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 63 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff000000000000 - -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_LSB 0 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MASK 0x0000000007ffffff - -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_LSB 27 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MASK 0x00000000f8000000 - -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_LSB 32 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MSB 47 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_LSB 48 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MSB 63 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_a.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_a.h deleted file mode 100644 index 6dec145785d6..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_a.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_A_H_ -#define _MACTX_VHT_SIG_A_H_ - -#include "vht_sig_a_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_A 1 - -struct mactx_vht_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_a_info mactx_vht_sig_a_info_details; -#else - struct vht_sig_a_info mactx_vht_sig_a_info_details; -#endif -}; - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu160.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu160.h deleted file mode 100644 index b66278da930b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu160.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU160_H_ -#define _MACTX_VHT_SIG_B_MU160_H_ - -#include "vht_sig_b_mu160_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU160 4 - -struct mactx_vht_sig_b_mu160 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; -#else - struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu20.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu20.h deleted file mode 100644 index 95feca30eaa3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu20.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU20_H_ -#define _MACTX_VHT_SIG_B_MU20_H_ - -#include "vht_sig_b_mu20_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU20 1 - -struct mactx_vht_sig_b_mu20 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; - uint32_t tlv64_padding : 32; -#else - struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x000000000000ffff - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x00000000000f0000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x000000001c000000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_LSB 32 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MSB 63 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu40.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu40.h deleted file mode 100644 index c770db089203..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu40.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU40_H_ -#define _MACTX_VHT_SIG_B_MU40_H_ - -#include "vht_sig_b_mu40_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU40 1 - -struct mactx_vht_sig_b_mu40 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; -#else - struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x00000000001e0000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x0000000018000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 32 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 48 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff00000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 49 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 52 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e000000000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 53 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 58 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 59 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf800000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu80.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu80.h deleted file mode 100644 index 9e39d240b618..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_mu80.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU80_H_ -#define _MACTX_VHT_SIG_B_MU80_H_ - -#include "vht_sig_b_mu80_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU80 2 - -struct mactx_vht_sig_b_mu80 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; -#else - struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 50 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 51 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 50 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 51 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 63 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su160.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su160.h deleted file mode 100644 index 01bc54e5ab89..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su160.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU160_H_ -#define _MACTX_VHT_SIG_B_SU160_H_ - -#include "vht_sig_b_su160_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU160 4 - -struct mactx_vht_sig_b_su160 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; -#else - struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su20.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su20.h deleted file mode 100644 index c297cc0785e3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su20.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU20_H_ -#define _MACTX_VHT_SIG_B_SU20_H_ - -#include "vht_sig_b_su20_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1 - -struct mactx_vht_sig_b_su20 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; - uint32_t tlv64_padding : 32; -#else - struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x00000000000e0000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x000000007c000000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB 32 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB 63 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su40.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su40.h deleted file mode 100644 index 002d72c430ca..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su40.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU40_H_ -#define _MACTX_VHT_SIG_B_SU40_H_ - -#include "vht_sig_b_su40_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU40 1 - -struct mactx_vht_sig_b_su40 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; -#else - struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000180000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x0000000078000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 32 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 50 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 51 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 52 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x0018000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 53 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 58 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 59 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 62 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x7800000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 63 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 63 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su80.h b/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su80.h deleted file mode 100644 index b15646f03f4a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mactx_vht_sig_b_su80.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU80_H_ -#define _MACTX_VHT_SIG_B_SU80_H_ - -#include "vht_sig_b_su80_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU80 2 - -struct mactx_vht_sig_b_su80 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; -#else - struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 52 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 52 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 62 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mlo_sta_id_details.h b/drivers/staging/fw-api/hw/fig/v2/mlo_sta_id_details.h deleted file mode 100644 index 952056890206..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mlo_sta_id_details.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MLO_STA_ID_DETAILS_H_ -#define _MLO_STA_ID_DETAILS_H_ - -#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1 - -struct mlo_sta_id_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t nstr_mlo_sta_id : 10, - block_self_ml_sync : 1, - block_partner_ml_sync : 1, - nstr_mlo_sta_id_valid : 1, - reserved_0a : 3; -#else - uint16_t reserved_0a : 3, - nstr_mlo_sta_id_valid : 1, - block_partner_ml_sync : 1, - block_self_ml_sync : 1, - nstr_mlo_sta_id : 10; -#endif -}; - -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff - -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400 - -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 - -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 - -#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13 -#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15 -#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mon_buffer_addr.h b/drivers/staging/fw-api/hw/fig/v2/mon_buffer_addr.h deleted file mode 100644 index 8cb6f5fd57b9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mon_buffer_addr.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_BUFFER_ADDR_H_ -#define _MON_BUFFER_ADDR_H_ - -#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4 - -#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2 - -struct mon_buffer_addr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t dma_length : 12, - reserved_2a : 4, - msdu_continuation : 1, - truncated : 1, - reserved_2b : 14; - uint32_t tlv64_padding : 32; -#else - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t reserved_2b : 14, - truncated : 1, - msdu_continuation : 1, - reserved_2a : 4, - dma_length : 12; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff - -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000 - -#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 -#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 -#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff - -#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 -#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 -#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000 - -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000 - -#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_TRUNCATED_LSB 17 -#define MON_BUFFER_ADDR_TRUNCATED_MSB 17 -#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000 - -#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 -#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 -#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000 - -#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32 -#define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63 -#define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mon_destination_ring.h b/drivers/staging/fw-api/hw/fig/v2/mon_destination_ring.h deleted file mode 100644 index 1f373b585fd5..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mon_destination_ring.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_DESTINATION_RING_H_ -#define _MON_DESTINATION_RING_H_ - -#define NUM_OF_DWORDS_MON_DESTINATION_RING 4 - -struct mon_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t stat_buf_virt_addr_31_0 : 32; - uint32_t stat_buf_virt_addr_63_32 : 32; - uint32_t ppdu_id : 32; - uint32_t end_offset : 12, - reserved_3a : 2, - link_info : 2, - end_reason : 2, - initiator : 1, - empty_descriptor : 1, - pkt_buffer_cnt : 8, - looping_count : 4; -#else - uint32_t stat_buf_virt_addr_31_0 : 32; - uint32_t stat_buf_virt_addr_63_32 : 32; - uint32_t ppdu_id : 32; - uint32_t looping_count : 4, - pkt_buffer_cnt : 8, - empty_descriptor : 1, - initiator : 1, - end_reason : 2, - link_info : 2, - reserved_3a : 2, - end_offset : 12; -#endif -}; - -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff - -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff - -#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008 -#define MON_DESTINATION_RING_PPDU_ID_LSB 0 -#define MON_DESTINATION_RING_PPDU_ID_MSB 31 -#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff - -#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c -#define MON_DESTINATION_RING_END_OFFSET_LSB 0 -#define MON_DESTINATION_RING_END_OFFSET_MSB 11 -#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff - -#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c -#define MON_DESTINATION_RING_RESERVED_3A_LSB 12 -#define MON_DESTINATION_RING_RESERVED_3A_MSB 13 -#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x00003000 - -#define MON_DESTINATION_RING_LINK_INFO_OFFSET 0x0000000c -#define MON_DESTINATION_RING_LINK_INFO_LSB 14 -#define MON_DESTINATION_RING_LINK_INFO_MSB 15 -#define MON_DESTINATION_RING_LINK_INFO_MASK 0x0000c000 - -#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c -#define MON_DESTINATION_RING_END_REASON_LSB 16 -#define MON_DESTINATION_RING_END_REASON_MSB 17 -#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000 - -#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c -#define MON_DESTINATION_RING_INITIATOR_LSB 18 -#define MON_DESTINATION_RING_INITIATOR_MSB 18 -#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000 - -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19 -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19 -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000 - -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_OFFSET 0x0000000c -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_LSB 20 -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MSB 27 -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MASK 0x0ff00000 - -#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c -#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28 -#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31 -#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mon_drop.h b/drivers/staging/fw-api/hw/fig/v2/mon_drop.h deleted file mode 100644 index d1135ecd0dc2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mon_drop.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_DROP_H_ -#define _MON_DROP_H_ - -#define NUM_OF_DWORDS_MON_DROP 2 - -#define NUM_OF_QWORDS_MON_DROP 1 - -struct mon_drop { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ppdu_id : 32; - uint32_t ppdu_drop_cnt : 10, - mpdu_drop_cnt : 10, - tlv_drop_cnt : 10, - end_of_ppdu_seen : 1, - reserved_1a : 1; -#else - uint32_t ppdu_id : 32; - uint32_t reserved_1a : 1, - end_of_ppdu_seen : 1, - tlv_drop_cnt : 10, - mpdu_drop_cnt : 10, - ppdu_drop_cnt : 10; -#endif -}; - -#define MON_DROP_PPDU_ID_OFFSET 0x0000000000000000 -#define MON_DROP_PPDU_ID_LSB 0 -#define MON_DROP_PPDU_ID_MSB 31 -#define MON_DROP_PPDU_ID_MASK 0x00000000ffffffff - -#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_PPDU_DROP_CNT_LSB 32 -#define MON_DROP_PPDU_DROP_CNT_MSB 41 -#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff00000000 - -#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_MPDU_DROP_CNT_LSB 42 -#define MON_DROP_MPDU_DROP_CNT_MSB 51 -#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc0000000000 - -#define MON_DROP_TLV_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_TLV_DROP_CNT_LSB 52 -#define MON_DROP_TLV_DROP_CNT_MSB 61 -#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff0000000000000 - -#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x0000000000000000 -#define MON_DROP_END_OF_PPDU_SEEN_LSB 62 -#define MON_DROP_END_OF_PPDU_SEEN_MSB 62 -#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x4000000000000000 - -#define MON_DROP_RESERVED_1A_OFFSET 0x0000000000000000 -#define MON_DROP_RESERVED_1A_LSB 63 -#define MON_DROP_RESERVED_1A_MSB 63 -#define MON_DROP_RESERVED_1A_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/mon_ingress_ring.h b/drivers/staging/fw-api/hw/fig/v2/mon_ingress_ring.h deleted file mode 100644 index 76f4e80417e0..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/mon_ingress_ring.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_INGRESS_RING_H_ -#define _MON_INGRESS_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_MON_INGRESS_RING 4 - -struct mon_ingress_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buffer_addr_info_details; - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; -#else - struct buffer_addr_info buffer_addr_info_details; - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; -#endif -}; - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff - -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/msmhwiobase.h b/drivers/staging/fw-api/hw/fig/v2/msmhwiobase.h deleted file mode 100644 index f7620cef5599..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/msmhwiobase.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef __MSMHWIOBASE_H__ -#define __MSMHWIOBASE_H__ - -#define SOC_WFSS_CE_REG_BASE 0x01b80000 -#define SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000 -#define SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000 -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/msmhwioreg.h b/drivers/staging/fw-api/hw/fig/v2/msmhwioreg.h deleted file mode 100644 index 881c73e30f58..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/msmhwioreg.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ -#ifndef __MSMHWIOREG_H__ -#define __MSMHWIOREG_H__ - -#include "msmhwiobase.h" - -#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00001000) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000408) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 -#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000004) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 -#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00003000) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000004) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000400) -#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00002000) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000004) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000400) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000058) - - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/no_ack_report.h b/drivers/staging/fw-api/hw/fig/v2/no_ack_report.h deleted file mode 100644 index 5f9660801de6..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/no_ack_report.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _NO_ACK_REPORT_H_ -#define _NO_ACK_REPORT_H_ - -#define NUM_OF_DWORDS_NO_ACK_REPORT 4 - -struct no_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t no_ack_transmit_reason : 4, - macrx_abort_reason : 4, - phyrx_abort_reason : 8, - frame_control : 16; - uint32_t rx_ppdu_duration : 24, - sr_ppdu_during_obss : 1, - selfgen_response_reason_to_sr_ppdu : 4, - reserved_1 : 3; - uint32_t pre_bt_broadcast_status_details : 12, - first_bt_broadcast_status_details : 12, - reserved_2 : 8; - uint32_t second_bt_broadcast_status_details : 12, - reserved_3 : 20; -#else - uint32_t frame_control : 16, - phyrx_abort_reason : 8, - macrx_abort_reason : 4, - no_ack_transmit_reason : 4; - uint32_t reserved_1 : 3, - selfgen_response_reason_to_sr_ppdu : 4, - sr_ppdu_during_obss : 1, - rx_ppdu_duration : 24; - uint32_t reserved_2 : 8, - first_bt_broadcast_status_details : 12, - pre_bt_broadcast_status_details : 12; - uint32_t reserved_3 : 20, - second_bt_broadcast_status_details : 12; -#endif -}; - -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f - -#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0 - -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00 - -#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 -#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16 -#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31 -#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 - -#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004 -#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0 -#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23 -#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff - -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000 - -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000 - -#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004 -#define NO_ACK_REPORT_RESERVED_1_LSB 29 -#define NO_ACK_REPORT_RESERVED_1_MSB 31 -#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000 - -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff - -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000 - -#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008 -#define NO_ACK_REPORT_RESERVED_2_LSB 24 -#define NO_ACK_REPORT_RESERVED_2_MSB 31 -#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000 - -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff - -#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c -#define NO_ACK_REPORT_RESERVED_3_LSB 12 -#define NO_ACK_REPORT_RESERVED_3_MSB 31 -#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/ofdma_trigger_details.h b/drivers/staging/fw-api/hw/fig/v2/ofdma_trigger_details.h deleted file mode 100644 index d1e667c885d4..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/ofdma_trigger_details.h +++ /dev/null @@ -1,944 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _OFDMA_TRIGGER_DETAILS_H_ -#define _OFDMA_TRIGGER_DETAILS_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 26 - -#define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 13 - -struct ofdma_trigger_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ax_trigger_source : 1, - rx_trigger_frame_user_source : 2, - received_bandwidth : 3, - txop_duration_all_ones : 1, - eht_trigger_response : 1, - pre_rssi_comb : 8, - rssi_comb : 8, - rxpcu_pcie_l0_req_duration : 8; - uint32_t he_trigger_ul_ppdu_length : 5, - he_trigger_ru_allocation : 8, - he_trigger_dl_tx_power : 5, - he_trigger_ul_target_rssi : 5, - he_trigger_ul_mcs : 2, - he_trigger_reserved : 1, - bss_color : 6; - uint32_t trigger_type : 4, - lsig_response_length : 12, - cascade_indication : 1, - carrier_sense : 1, - bandwidth : 2, - cp_ltf_size : 2, - mu_mimo_ltf_mode : 1, - number_of_ltfs : 3, - stbc : 1, - ldpc_extra_symbol : 1, - ap_tx_power_lsb_part : 4; - uint32_t ap_tx_power_msb_part : 2, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - spatial_reuse : 16, - doppler : 1, - he_siga_reserved : 9, - reserved_3b : 1; - uint32_t aid12 : 12, - ru_allocation : 9, - mcs : 4, - dcm : 1, - start_spatial_stream : 3, - number_of_spatial_stream : 3; - uint32_t target_rssi : 7, - coding_type : 1, - mpdu_mu_spacing_factor : 2, - tid_aggregation_limit : 3, - reserved_5b : 1, - prefered_ac : 2, - bar_control_ack_policy : 1, - bar_control_multi_tid : 1, - bar_control_compressed_bitmap : 1, - bar_control_reserved : 9, - bar_control_tid_info : 4; - uint32_t nr0_per_tid_info_reserved : 12, - nr0_per_tid_info_tid_value : 4, - nr0_start_seq_ctrl_frag_number : 4, - nr0_start_seq_ctrl_start_seq_number : 12; - uint32_t nr1_per_tid_info_reserved : 12, - nr1_per_tid_info_tid_value : 4, - nr1_start_seq_ctrl_frag_number : 4, - nr1_start_seq_ctrl_start_seq_number : 12; - uint32_t nr2_per_tid_info_reserved : 12, - nr2_per_tid_info_tid_value : 4, - nr2_start_seq_ctrl_frag_number : 4, - nr2_start_seq_ctrl_start_seq_number : 12; - uint32_t nr3_per_tid_info_reserved : 12, - nr3_per_tid_info_tid_value : 4, - nr3_start_seq_ctrl_frag_number : 4, - nr3_start_seq_ctrl_start_seq_number : 12; - uint32_t nr4_per_tid_info_reserved : 12, - nr4_per_tid_info_tid_value : 4, - nr4_start_seq_ctrl_frag_number : 4, - nr4_start_seq_ctrl_start_seq_number : 12; - uint32_t nr5_per_tid_info_reserved : 12, - nr5_per_tid_info_tid_value : 4, - nr5_start_seq_ctrl_frag_number : 4, - nr5_start_seq_ctrl_start_seq_number : 12; - uint32_t nr6_per_tid_info_reserved : 12, - nr6_per_tid_info_tid_value : 4, - nr6_start_seq_ctrl_frag_number : 4, - nr6_start_seq_ctrl_start_seq_number : 12; - uint32_t nr7_per_tid_info_reserved : 12, - nr7_per_tid_info_tid_value : 4, - nr7_start_seq_ctrl_frag_number : 4, - nr7_start_seq_ctrl_start_seq_number : 12; - uint32_t fb_segment_retransmission_bitmap : 8, - reserved_14a : 2, - u_sig_puncture_pattern_encoding : 6, - dot11be_puncture_bitmap : 16; - uint32_t rx_chain_mask : 8, - rx_duration_field : 16, - scrambler_seed : 7, - rx_chain_mask_type : 1; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t normalized_pre_rssi_comb : 8, - normalized_rssi_comb : 8; - uint32_t sw_peer_id : 16, - response_tx_duration : 16; - uint32_t __reserved_g_0022_trigger_subtype : 4, - tbr_trigger_common_info_79_68 : 12, - tbr_trigger_sound_reserved_20_12 : 9, - i2r_rep : 3, - tbr_trigger_sound_reserved_25_24 : 2, - reserved_18a : 1, - qos_null_only_response_tx : 1; - uint32_t tbr_trigger_sound_sac : 16, - reserved_19a : 8, - u_sig_reserved2 : 5, - reserved_19b : 3; - uint32_t eht_special_aid12 : 12, - phy_version : 3, - bandwidth_ext : 2, - eht_spatial_reuse : 8, - u_sig_reserved1 : 7; - uint32_t eht_trigger_special_user_info_71_40 : 32; - uint32_t __reserved_g_0035 : 1, - __reserved_g_0035_trigger_subtype : 4, - blackout_details_en : 1, - uhr_trig_response : 1, - mcs_ext : 1, - dso_primary20_index_select : 4, - dso_icf_reception : 1, - dru_spreading_bw : 2, - dru_indication_per_80mhz : 4, - coding_type_ext : 1, - pad_duration : 5, - ects_as_tb_ppdu : 1, - reserved_22a : 6; - uint32_t dso_cca_puncture_pattern : 16, - dso_freq_subband_channel_bonding_mask : 16; - uint32_t __reserved_g_0017 : 1, - enable_steering : 1, - q2q_mba : 1, - reserved_24a : 29; - uint32_t reserved_25a : 32; -#else - uint32_t rxpcu_pcie_l0_req_duration : 8, - rssi_comb : 8, - pre_rssi_comb : 8, - eht_trigger_response : 1, - txop_duration_all_ones : 1, - received_bandwidth : 3, - rx_trigger_frame_user_source : 2, - ax_trigger_source : 1; - uint32_t bss_color : 6, - he_trigger_reserved : 1, - he_trigger_ul_mcs : 2, - he_trigger_ul_target_rssi : 5, - he_trigger_dl_tx_power : 5, - he_trigger_ru_allocation : 8, - he_trigger_ul_ppdu_length : 5; - uint32_t ap_tx_power_lsb_part : 4, - ldpc_extra_symbol : 1, - stbc : 1, - number_of_ltfs : 3, - mu_mimo_ltf_mode : 1, - cp_ltf_size : 2, - bandwidth : 2, - carrier_sense : 1, - cascade_indication : 1, - lsig_response_length : 12, - trigger_type : 4; - uint32_t reserved_3b : 1, - he_siga_reserved : 9, - doppler : 1, - spatial_reuse : 16, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - ap_tx_power_msb_part : 2; - uint32_t number_of_spatial_stream : 3, - start_spatial_stream : 3, - dcm : 1, - mcs : 4, - ru_allocation : 9, - aid12 : 12; - uint32_t bar_control_tid_info : 4, - bar_control_reserved : 9, - bar_control_compressed_bitmap : 1, - bar_control_multi_tid : 1, - bar_control_ack_policy : 1, - prefered_ac : 2, - reserved_5b : 1, - tid_aggregation_limit : 3, - mpdu_mu_spacing_factor : 2, - coding_type : 1, - target_rssi : 7; - uint32_t nr0_start_seq_ctrl_start_seq_number : 12, - nr0_start_seq_ctrl_frag_number : 4, - nr0_per_tid_info_tid_value : 4, - nr0_per_tid_info_reserved : 12; - uint32_t nr1_start_seq_ctrl_start_seq_number : 12, - nr1_start_seq_ctrl_frag_number : 4, - nr1_per_tid_info_tid_value : 4, - nr1_per_tid_info_reserved : 12; - uint32_t nr2_start_seq_ctrl_start_seq_number : 12, - nr2_start_seq_ctrl_frag_number : 4, - nr2_per_tid_info_tid_value : 4, - nr2_per_tid_info_reserved : 12; - uint32_t nr3_start_seq_ctrl_start_seq_number : 12, - nr3_start_seq_ctrl_frag_number : 4, - nr3_per_tid_info_tid_value : 4, - nr3_per_tid_info_reserved : 12; - uint32_t nr4_start_seq_ctrl_start_seq_number : 12, - nr4_start_seq_ctrl_frag_number : 4, - nr4_per_tid_info_tid_value : 4, - nr4_per_tid_info_reserved : 12; - uint32_t nr5_start_seq_ctrl_start_seq_number : 12, - nr5_start_seq_ctrl_frag_number : 4, - nr5_per_tid_info_tid_value : 4, - nr5_per_tid_info_reserved : 12; - uint32_t nr6_start_seq_ctrl_start_seq_number : 12, - nr6_start_seq_ctrl_frag_number : 4, - nr6_per_tid_info_tid_value : 4, - nr6_per_tid_info_reserved : 12; - uint32_t nr7_start_seq_ctrl_start_seq_number : 12, - nr7_start_seq_ctrl_frag_number : 4, - nr7_per_tid_info_tid_value : 4, - nr7_per_tid_info_reserved : 12; - uint32_t dot11be_puncture_bitmap : 16, - u_sig_puncture_pattern_encoding : 6, - reserved_14a : 2, - fb_segment_retransmission_bitmap : 8; - uint32_t rx_chain_mask_type : 1, - scrambler_seed : 7, - rx_duration_field : 16, - rx_chain_mask : 8; - uint32_t normalized_rssi_comb : 8, - normalized_pre_rssi_comb : 8; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint32_t response_tx_duration : 16, - sw_peer_id : 16; - uint32_t qos_null_only_response_tx : 1, - reserved_18a : 1, - tbr_trigger_sound_reserved_25_24 : 2, - i2r_rep : 3, - tbr_trigger_sound_reserved_20_12 : 9, - tbr_trigger_common_info_79_68 : 12, - __reserved_g_0022_trigger_subtype : 4; - uint32_t reserved_19b : 3, - u_sig_reserved2 : 5, - reserved_19a : 8, - tbr_trigger_sound_sac : 16; - uint32_t u_sig_reserved1 : 7, - eht_spatial_reuse : 8, - bandwidth_ext : 2, - phy_version : 3, - eht_special_aid12 : 12; - uint32_t eht_trigger_special_user_info_71_40 : 32; - uint32_t reserved_22a : 6, - ects_as_tb_ppdu : 1, - pad_duration : 5, - coding_type_ext : 1, - dru_indication_per_80mhz : 4, - dru_spreading_bw : 2, - dso_icf_reception : 1, - dso_primary20_index_select : 4, - mcs_ext : 1, - uhr_trig_response : 1, - blackout_details_en : 1, - __reserved_g_0035_trigger_subtype : 4, - __reserved_g_0035 : 1; - uint32_t dso_freq_subband_channel_bonding_mask : 16, - dso_cca_puncture_pattern : 16; - uint32_t reserved_24a : 29, - q2q_mba : 1, - enable_steering : 1, - __reserved_g_0017 : 1; - uint32_t reserved_25a : 32; -#endif -}; - -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000001 - -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x0000000000000006 - -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x0000000000000038 - -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x0000000000000040 - -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x0000000000000080 - -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x000000000000ff00 - -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x0000000000ff0000 - -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0x00000000ff000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 32 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 36 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f00000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 37 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 44 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 45 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 49 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e00000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 50 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 54 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 55 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 56 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x0180000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 57 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 57 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x0200000000000000 - -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 58 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 63 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc00000000000000 - -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f - -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x000000000000fff0 - -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x0000000000010000 - -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x0000000000020000 - -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x00000000000c0000 - -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x0000000000300000 - -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x0000000000400000 - -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x0000000003800000 - -#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26 -#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26 -#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x0000000004000000 - -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000008000000 - -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0x00000000f0000000 - -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 32 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 33 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x0000000300000000 - -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 34 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 35 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c00000000 - -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 36 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 36 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000001000000000 - -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 37 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 52 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe000000000 - -#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 53 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 53 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x0020000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 54 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 62 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc0000000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x8000000000000000 - -#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0 -#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11 -#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x00000000001ff000 - -#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21 -#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24 -#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x0000000001e00000 - -#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25 -#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25 -#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x0000000002000000 - -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x000000001c000000 - -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0x00000000e0000000 - -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 32 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 38 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f00000000 - -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 39 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 39 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x0000008000000000 - -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 40 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 41 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x0000030000000000 - -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 42 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 44 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c0000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 45 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 45 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x0000200000000000 - -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 46 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 47 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c00000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 48 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 48 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x0001000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 49 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 49 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x0002000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 50 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 50 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x0004000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 51 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 59 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff8000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 60 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 63 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf000000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x00000000000000ff - -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x0000000000000300 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x000000000000fc00 - -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0x00000000ffff0000 - -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 32 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 39 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff00000000 - -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 40 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 55 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff0000000000 - -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 56 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 62 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f00000000000000 - -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 63 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x8000000000000000 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 - -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 - -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 48 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff000000000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x000000000000fff0 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x0000000001ff0000 - -#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x000000000e000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x0000000030000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x0000000040000000 - -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x0000000080000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 32 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 47 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 48 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 55 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff000000000000 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 56 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 60 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f00000000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 61 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe000000000000000 - -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x0000000000007000 - -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x0000000000018000 - -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x0000000001fe0000 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0x00000000fe000000 - -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 32 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 63 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff00000000 - -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_LSB 5 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MSB 5 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MASK 0x0000000000000020 - -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_LSB 6 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MSB 6 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MASK 0x0000000000000040 - -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_LSB 7 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MSB 7 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MASK 0x0000000000000080 - -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_LSB 8 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MSB 11 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MASK 0x0000000000000f00 - -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MSB 12 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MASK 0x0000000000001000 - -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_LSB 13 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MSB 14 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MASK 0x0000000000006000 - -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_LSB 15 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MSB 18 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MASK 0x0000000000078000 - -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_LSB 19 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MSB 19 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MASK 0x0000000000080000 - -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_LSB 20 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MSB 24 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MASK 0x0000000001f00000 - -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB 25 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB 25 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK 0x0000000002000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_LSB 26 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MASK 0x00000000fc000000 - -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_LSB 32 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MSB 47 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 48 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 63 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0xffff000000000000 - -#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_LSB 1 -#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_MSB 1 -#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_MASK 0x0000000000000002 - -#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_LSB 2 -#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_MSB 2 -#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_MASK 0x0000000000000004 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_LSB 3 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MASK 0x00000000fffffff8 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_LSB 32 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/pcu_ppdu_setup_init.h b/drivers/staging/fw-api/hw/fig/v2/pcu_ppdu_setup_init.h deleted file mode 100644 index f623a25ba4d4..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/pcu_ppdu_setup_init.h +++ /dev/null @@ -1,2316 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PCU_PPDU_SETUP_INIT_H_ -#define _PCU_PPDU_SETUP_INIT_H_ - -#include "pdg_response_rate_setting.h" -#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58 - -#define NUM_OF_QWORDS_PCU_PPDU_SETUP_INIT 29 - -struct pcu_ppdu_setup_init { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t medium_prot_type : 3, - response_type : 5, - response_info_part2_required : 1, - response_to_response : 3, - mba_user_order : 2, - expected_mba_size : 11, - required_ul_mu_resp_user_count : 6, - transmitted_bssid_check_en : 1; - uint32_t mprot_required_bw1 : 1, - mprot_required_bw20 : 1, - mprot_required_bw40 : 1, - mprot_required_bw80 : 1, - mprot_required_bw160 : 1, - mprot_required_bw240 : 1, - mprot_required_bw320 : 1, - ppdu_allowed_bw1 : 1, - ppdu_allowed_bw20 : 1, - ppdu_allowed_bw40 : 1, - ppdu_allowed_bw80 : 1, - ppdu_allowed_bw160 : 1, - ppdu_allowed_bw240 : 1, - ppdu_allowed_bw320 : 1, - set_fc_pwr_mgt : 1, - use_cts_duration_for_data_tx : 1, - update_timestamp_64 : 1, - update_timestamp_32_lower : 1, - update_timestamp_32_upper : 1, - reserved_1a : 13; - uint32_t insert_timestamp_offset_0 : 16, - insert_timestamp_offset_1 : 16; - uint32_t max_bw40_try_count : 4, - max_bw80_try_count : 4, - max_bw160_try_count : 4, - max_bw240_try_count : 4, - max_bw320_try_count : 4, - insert_wur_timestamp_offset : 6, - update_wur_timestamp : 1, - wur_embedded_bssid_present : 1, - insert_wur_fcs : 1, - q2q_trigger : 1, - reserved_3b : 2; - struct pdg_response_rate_setting response_to_response_rate_info_bw20; - struct pdg_response_rate_setting response_to_response_rate_info_bw40; - struct pdg_response_rate_setting response_to_response_rate_info_bw80; - struct pdg_response_rate_setting response_to_response_rate_info_bw160; - struct pdg_response_rate_setting response_to_response_rate_info_bw240; - struct pdg_response_rate_setting response_to_response_rate_info_bw320; - uint32_t r2r_hw_response_tx_duration : 16, - r2r_rx_duration_field : 16; - uint32_t r2r_group_id : 6, - r2r_response_frame_type : 4, - r2r_sta_partial_aid : 11, - use_address_fields_for_protection : 1, - r2r_set_required_response_time : 1, - reserved_29a : 3, - r2r_bw20_active_channel : 3, - r2r_bw40_active_channel : 3; - uint32_t r2r_bw80_active_channel : 3, - r2r_bw160_active_channel : 3, - r2r_bw240_active_channel : 3, - r2r_bw320_active_channel : 3, - r2r_bw20 : 3, - r2r_bw40 : 3, - r2r_bw80 : 3, - r2r_bw160 : 3, - r2r_bw240 : 3, - r2r_bw320 : 3, - tx_with_blackout_details : 1, - expect_rx_with_blackout_details : 1; - uint32_t mu_response_expected_bitmap_31_0 : 32; - uint32_t mu_response_expected_bitmap_36_32 : 5, - mu_expected_response_cbf_count : 6, - mu_expected_response_sta_count : 6, - transmit_includes_multidestination : 1, - insert_prev_tx_start_timing_info : 1, - insert_current_tx_start_timing_info : 1, - tx_start_transmit_time_byte_offset : 12; - uint32_t protection_frame_ad1_31_0 : 32; - uint32_t protection_frame_ad1_47_32 : 16, - protection_frame_ad2_15_0 : 16; - uint32_t protection_frame_ad2_47_16 : 32; - uint32_t dynamic_medium_prot_threshold : 24, - dynamic_medium_prot_type : 1, - reserved_54a : 7; - uint32_t protection_frame_ad3_31_0 : 32; - uint32_t protection_frame_ad3_47_32 : 16, - protection_frame_ad4_15_0 : 16; - uint32_t protection_frame_ad4_47_16 : 32; -#else - uint32_t transmitted_bssid_check_en : 1, - required_ul_mu_resp_user_count : 6, - expected_mba_size : 11, - mba_user_order : 2, - response_to_response : 3, - response_info_part2_required : 1, - response_type : 5, - medium_prot_type : 3; - uint32_t reserved_1a : 13, - update_timestamp_32_upper : 1, - update_timestamp_32_lower : 1, - update_timestamp_64 : 1, - use_cts_duration_for_data_tx : 1, - set_fc_pwr_mgt : 1, - ppdu_allowed_bw320 : 1, - ppdu_allowed_bw240 : 1, - ppdu_allowed_bw160 : 1, - ppdu_allowed_bw80 : 1, - ppdu_allowed_bw40 : 1, - ppdu_allowed_bw20 : 1, - ppdu_allowed_bw1 : 1, - mprot_required_bw320 : 1, - mprot_required_bw240 : 1, - mprot_required_bw160 : 1, - mprot_required_bw80 : 1, - mprot_required_bw40 : 1, - mprot_required_bw20 : 1, - mprot_required_bw1 : 1; - uint32_t insert_timestamp_offset_1 : 16, - insert_timestamp_offset_0 : 16; - uint32_t reserved_3b : 2, - q2q_trigger : 1, - insert_wur_fcs : 1, - wur_embedded_bssid_present : 1, - update_wur_timestamp : 1, - insert_wur_timestamp_offset : 6, - max_bw320_try_count : 4, - max_bw240_try_count : 4, - max_bw160_try_count : 4, - max_bw80_try_count : 4, - max_bw40_try_count : 4; - struct pdg_response_rate_setting response_to_response_rate_info_bw20; - struct pdg_response_rate_setting response_to_response_rate_info_bw40; - struct pdg_response_rate_setting response_to_response_rate_info_bw80; - struct pdg_response_rate_setting response_to_response_rate_info_bw160; - struct pdg_response_rate_setting response_to_response_rate_info_bw240; - struct pdg_response_rate_setting response_to_response_rate_info_bw320; - uint32_t r2r_rx_duration_field : 16, - r2r_hw_response_tx_duration : 16; - uint32_t r2r_bw40_active_channel : 3, - r2r_bw20_active_channel : 3, - reserved_29a : 3, - r2r_set_required_response_time : 1, - use_address_fields_for_protection : 1, - r2r_sta_partial_aid : 11, - r2r_response_frame_type : 4, - r2r_group_id : 6; - uint32_t expect_rx_with_blackout_details : 1, - tx_with_blackout_details : 1, - r2r_bw320 : 3, - r2r_bw240 : 3, - r2r_bw160 : 3, - r2r_bw80 : 3, - r2r_bw40 : 3, - r2r_bw20 : 3, - r2r_bw320_active_channel : 3, - r2r_bw240_active_channel : 3, - r2r_bw160_active_channel : 3, - r2r_bw80_active_channel : 3; - uint32_t mu_response_expected_bitmap_31_0 : 32; - uint32_t tx_start_transmit_time_byte_offset : 12, - insert_current_tx_start_timing_info : 1, - insert_prev_tx_start_timing_info : 1, - transmit_includes_multidestination : 1, - mu_expected_response_sta_count : 6, - mu_expected_response_cbf_count : 6, - mu_response_expected_bitmap_36_32 : 5; - uint32_t protection_frame_ad1_31_0 : 32; - uint32_t protection_frame_ad2_15_0 : 16, - protection_frame_ad1_47_32 : 16; - uint32_t protection_frame_ad2_47_16 : 32; - uint32_t reserved_54a : 7, - dynamic_medium_prot_type : 1, - dynamic_medium_prot_threshold : 24; - uint32_t protection_frame_ad3_31_0 : 32; - uint32_t protection_frame_ad4_15_0 : 16, - protection_frame_ad3_47_32 : 16; - uint32_t protection_frame_ad4_47_16 : 32; -#endif -}; - -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB 0 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB 2 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK 0x0000000000000007 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK 0x00000000000000f8 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0000000000000100 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK 0x0000000000000e00 - -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB 12 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB 13 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK 0x0000000000003000 - -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB 14 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB 24 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK 0x0000000001ffc000 - -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB 25 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB 30 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK 0x000000007e000000 - -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB 31 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB 31 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB 32 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB 32 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB 33 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB 33 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK 0x0000000200000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB 34 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB 34 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK 0x0000000400000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB 35 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB 35 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK 0x0000000800000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB 36 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB 36 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK 0x0000001000000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB 37 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB 37 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK 0x0000002000000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB 38 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB 38 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK 0x0000004000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB 39 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB 39 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB 40 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB 40 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK 0x0000010000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB 41 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB 41 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK 0x0000020000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB 42 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB 42 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB 43 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB 43 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB 44 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB 44 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB 45 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB 45 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB 46 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB 46 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB 47 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB 47 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB 48 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB 48 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK 0x0001000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB 49 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB 49 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK 0x0002000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB 50 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB 50 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK 0x0004000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK 0xfff8000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB 0 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB 15 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB 32 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB 35 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB 36 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB 39 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB 40 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB 43 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK 0x00000f0000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB 44 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB 47 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK 0x0000f00000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB 48 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB 51 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK 0x000f000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB 52 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB 57 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB 58 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB 58 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB 59 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB 59 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK 0x0800000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB 60 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB 60 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK 0x1000000000000000 - -#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_LSB 61 -#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_MSB 61 -#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK 0xc000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB 15 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB 16 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB 31 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB 37 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK 0x0000003f00000000 - -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB 38 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB 41 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK 0x000003c000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB 42 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB 52 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK 0x001ffc0000000000 - -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB 53 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB 53 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB 54 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB 54 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK 0x0040000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB 55 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK 0x0380000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB 58 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB 60 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK 0x1c00000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB 61 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB 63 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK 0xe000000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB 0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB 2 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK 0x0000000000000007 - -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB 3 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB 5 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK 0x0000000000000038 - -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB 6 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB 8 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK 0x00000000000001c0 - -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB 9 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB 11 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK 0x0000000000000e00 - -#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB 12 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB 14 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK 0x0000000000007000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB 15 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB 17 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK 0x0000000000038000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB 18 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB 20 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB 21 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB 23 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK 0x0000000000e00000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB 24 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB 26 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK 0x0000000007000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB 27 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB 29 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_LSB 30 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MSB 30 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB 31 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB 31 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB 4 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB 5 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB 10 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK 0x00000000000007e0 - -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB 11 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB 16 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK 0x000000000001f800 - -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB 17 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB 17 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK 0x0000000000020000 - -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB 18 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB 18 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK 0x0000000000040000 - -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB 19 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB 19 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB 20 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB 31 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK 0x00000000fff00000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB 15 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB 16 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB 31 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB 0 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB 23 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK 0x0000000000ffffff - -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB 24 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB 24 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK 0x00000000fe000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB 15 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB 16 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB 31 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/pdg_response.h b/drivers/staging/fw-api/hw/fig/v2/pdg_response.h deleted file mode 100644 index d94c69ff2645..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/pdg_response.h +++ /dev/null @@ -1,510 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_RESPONSE_H_ -#define _PDG_RESPONSE_H_ - -#include "pdg_response_rate_setting.h" -#define NUM_OF_DWORDS_PDG_RESPONSE 14 - -#define NUM_OF_QWORDS_PDG_RESPONSE 7 - -struct pdg_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct pdg_response_rate_setting hw_response_rate_info; - uint32_t hw_response_tx_duration : 16, - rx_duration_field : 16; - uint32_t punctured_response_transmission : 1, - cca_subband_channel_bonding_mask : 16, - scrambler_seed_override : 2, - response_density_valid : 1, - response_density : 5, - more_data : 1, - duration_indication : 1, - blackout_details_en : 1, - cfp_protected_resp : 1, - bandwidth : 3; - uint32_t ack_id : 16, - block_ack_bitmap : 16; - uint32_t response_frame_type : 4, - ack_id_ext : 10, - ftm_en : 1, - group_id : 6, - sta_partial_aid : 11; - uint32_t ndp_ba_start_seq_ctrl : 12, - active_channel : 3, - txop_duration_all_ones : 1, - frame_length : 16; - uint32_t dso_primary20_index_select : 4, - dso_freq_subband_channel_bonding_mask : 16, - pad_duration : 5, - q2q_mba : 1, - reserved_12a : 6; - uint32_t tlv64_padding : 32; -#else - struct pdg_response_rate_setting hw_response_rate_info; - uint32_t rx_duration_field : 16, - hw_response_tx_duration : 16; - uint32_t bandwidth : 3, - cfp_protected_resp : 1, - blackout_details_en : 1, - duration_indication : 1, - more_data : 1, - response_density : 5, - response_density_valid : 1, - scrambler_seed_override : 2, - cca_subband_channel_bonding_mask : 16, - punctured_response_transmission : 1; - uint32_t block_ack_bitmap : 16, - ack_id : 16; - uint32_t sta_partial_aid : 11, - group_id : 6, - ftm_en : 1, - ack_id_ext : 10, - response_frame_type : 4; - uint32_t frame_length : 16, - txop_duration_all_ones : 1, - active_channel : 3, - ndp_ba_start_seq_ctrl : 12; - uint32_t reserved_12a : 6, - q2q_mba : 1, - pad_duration : 5, - dso_freq_subband_channel_bonding_mask : 16, - dso_primary20_index_select : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x0000000000000001 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x000000001e000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x0000000020000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x0000000040000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x0000000080000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 48 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 50 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x0007000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 58 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 59 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 61 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x3800000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 62 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 62 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MSB 3 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MASK 0x000000000000000f - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x0000000000000070 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x0000000000000080 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x000000000000ff00 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 36 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 37 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000e000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 41 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x0000030000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 46 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00007c0000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_LSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 48 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 55 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 56 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x0000000000000001 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0x00000000f8000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 41 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 43 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 45 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 46 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 50 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 52 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 57 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f0000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff00000000 - -#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 48 -#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 63 -#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff000000000000 - -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x0000000000000001 - -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000000000001fffe - -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x0000000000060000 - -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x0000000000080000 - -#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20 -#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24 -#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x0000000001f00000 - -#define PDG_RESPONSE_MORE_DATA_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_MORE_DATA_LSB 25 -#define PDG_RESPONSE_MORE_DATA_MSB 25 -#define PDG_RESPONSE_MORE_DATA_MASK 0x0000000002000000 - -#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_DURATION_INDICATION_LSB 26 -#define PDG_RESPONSE_DURATION_INDICATION_MSB 26 -#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x0000000004000000 - -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_LSB 27 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MSB 27 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MASK 0x0000000008000000 - -#define PDG_RESPONSE_CFP_PROTECTED_RESP_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_CFP_PROTECTED_RESP_LSB 28 -#define PDG_RESPONSE_CFP_PROTECTED_RESP_MSB 28 -#define PDG_RESPONSE_CFP_PROTECTED_RESP_MASK 0x0000000010000000 - -#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BANDWIDTH_LSB 29 -#define PDG_RESPONSE_BANDWIDTH_MSB 31 -#define PDG_RESPONSE_BANDWIDTH_MASK 0x00000000e0000000 - -#define PDG_RESPONSE_ACK_ID_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_ACK_ID_LSB 32 -#define PDG_RESPONSE_ACK_ID_MSB 47 -#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff00000000 - -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 48 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 63 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff000000000000 - -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x000000000000000f - -#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_ACK_ID_EXT_LSB 4 -#define PDG_RESPONSE_ACK_ID_EXT_MSB 13 -#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x0000000000003ff0 - -#define PDG_RESPONSE_FTM_EN_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_FTM_EN_LSB 14 -#define PDG_RESPONSE_FTM_EN_MSB 14 -#define PDG_RESPONSE_FTM_EN_MASK 0x0000000000004000 - -#define PDG_RESPONSE_GROUP_ID_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_GROUP_ID_LSB 15 -#define PDG_RESPONSE_GROUP_ID_MSB 20 -#define PDG_RESPONSE_GROUP_ID_MASK 0x00000000001f8000 - -#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21 -#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31 -#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0x00000000ffe00000 - -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 32 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 43 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff00000000 - -#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 44 -#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 46 -#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x0000700000000000 - -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 47 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 47 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x0000800000000000 - -#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_FRAME_LENGTH_LSB 48 -#define PDG_RESPONSE_FRAME_LENGTH_MSB 63 -#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff000000000000 - -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_LSB 0 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MSB 3 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MASK 0x000000000000000f - -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 4 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 19 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x00000000000ffff0 - -#define PDG_RESPONSE_PAD_DURATION_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_PAD_DURATION_LSB 20 -#define PDG_RESPONSE_PAD_DURATION_MSB 24 -#define PDG_RESPONSE_PAD_DURATION_MASK 0x0000000001f00000 - -#define PDG_RESPONSE_Q2Q_MBA_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_Q2Q_MBA_LSB 25 -#define PDG_RESPONSE_Q2Q_MBA_MSB 25 -#define PDG_RESPONSE_Q2Q_MBA_MASK 0x0000000002000000 - -#define PDG_RESPONSE_RESERVED_12A_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_RESERVED_12A_LSB 26 -#define PDG_RESPONSE_RESERVED_12A_MSB 31 -#define PDG_RESPONSE_RESERVED_12A_MASK 0x00000000fc000000 - -#define PDG_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_TLV64_PADDING_LSB 32 -#define PDG_RESPONSE_TLV64_PADDING_MSB 63 -#define PDG_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/pdg_response_rate_setting.h b/drivers/staging/fw-api/hw/fig/v2/pdg_response_rate_setting.h deleted file mode 100644 index eb123386f2bf..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/pdg_response_rate_setting.h +++ /dev/null @@ -1,409 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_RESPONSE_RATE_SETTING_H_ -#define _PDG_RESPONSE_RATE_SETTING_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7 - -struct pdg_response_rate_setting { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 1, - tx_antenna_sector_ctrl : 24, - pkt_type : 4, - smoothing : 1, - ldpc : 1, - stbc : 1; - uint32_t alt_tx_pwr : 8, - alt_min_tx_pwr : 8, - alt_nss : 3, - alt_tx_chain_mask : 8, - alt_bw : 3, - stf_ltf_3db_boost : 1, - force_extra_symbol : 1; - uint32_t reserved_2a : 4, - nss : 3, - dpd_enable : 1, - tx_pwr : 8, - min_tx_pwr : 8, - tx_chain_mask : 8; - uint32_t alt_rate_mcs : 5, - reserved_3a : 3, - sgi : 2, - rate_mcs : 5, - ldpc_2x_codeword : 1, - tx_pwr_1 : 8, - alt_tx_pwr_1 : 8; - uint32_t aggregation : 1, - dot11ax_bss_color_id : 6, - dot11ax_spatial_reuse : 4, - dot11ax_cp_ltf_size : 2, - dot11ax_dcm : 1, - dot11ax_doppler_indication : 1, - dot11ax_su_extended : 1, - dot11ax_min_packet_extension : 2, - dot11ax_pe_nss : 3, - dot11ax_pe_content : 1, - dot11ax_pe_ltf_size : 2, - dot11ax_chain_csd_en : 1, - dot11ax_pe_chain_csd_en : 1, - dot11ax_dl_ul_flag : 1, - reserved_4a : 5; - uint32_t dot11ax_ext_ru_start_index : 4, - dot11ax_ext_ru_size : 4, - eht_duplicate_mode : 2, - he_sigb_dcm : 1, - he_sigb_0_mcs : 3, - num_he_sigb_sym : 5, - required_response_time_source : 1, - reserved_5a : 6, - u_sig_puncture_pattern_encoding : 6; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t required_response_time : 12, - dot11be_params_placeholder : 4; -#else - uint32_t stbc : 1, - ldpc : 1, - smoothing : 1, - pkt_type : 4, - tx_antenna_sector_ctrl : 24, - reserved_0a : 1; - uint32_t force_extra_symbol : 1, - stf_ltf_3db_boost : 1, - alt_bw : 3, - alt_tx_chain_mask : 8, - alt_nss : 3, - alt_min_tx_pwr : 8, - alt_tx_pwr : 8; - uint32_t tx_chain_mask : 8, - min_tx_pwr : 8, - tx_pwr : 8, - dpd_enable : 1, - nss : 3, - reserved_2a : 4; - uint32_t alt_tx_pwr_1 : 8, - tx_pwr_1 : 8, - ldpc_2x_codeword : 1, - rate_mcs : 5, - sgi : 2, - reserved_3a : 3, - alt_rate_mcs : 5; - uint32_t reserved_4a : 5, - dot11ax_dl_ul_flag : 1, - dot11ax_pe_chain_csd_en : 1, - dot11ax_chain_csd_en : 1, - dot11ax_pe_ltf_size : 2, - dot11ax_pe_content : 1, - dot11ax_pe_nss : 3, - dot11ax_min_packet_extension : 2, - dot11ax_su_extended : 1, - dot11ax_doppler_indication : 1, - dot11ax_dcm : 1, - dot11ax_cp_ltf_size : 2, - dot11ax_spatial_reuse : 4, - dot11ax_bss_color_id : 6, - aggregation : 1; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_5a : 6, - required_response_time_source : 1, - num_he_sigb_sym : 5, - he_sigb_0_mcs : 3, - he_sigb_dcm : 1, - eht_duplicate_mode : 2, - dot11ax_ext_ru_size : 4, - dot11ax_ext_ru_start_index : 4; - uint32_t dot11be_params_placeholder : 4, - required_response_time : 12; - struct mlo_sta_id_details mlo_sta_id_details_rx; -#endif -}; - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001 - -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe - -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000 - -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000 - -#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30 -#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30 -#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000 - -#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31 -#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff - -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00 - -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000 - -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000 - -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MSB 3 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MASK 0x0000000f - -#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4 -#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6 -#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070 - -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080 - -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00 - -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000 - -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 4 -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000001f - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 5 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000e0 - -#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300 - -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 14 -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00007c00 - -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_LSB 15 -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MASK 0x00008000 - -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000 - -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 - -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300 - -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400 - -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800 - -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000 - -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000 - -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 - -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/pdg_tx_req.h b/drivers/staging/fw-api/hw/fig/v2/pdg_tx_req.h deleted file mode 100644 index 6baf640807da..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/pdg_tx_req.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_TX_REQ_H_ -#define _PDG_TX_REQ_H_ - -#define NUM_OF_DWORDS_PDG_TX_REQ 2 - -#define NUM_OF_QWORDS_PDG_TX_REQ 1 - -struct pdg_tx_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_reason : 2, - use_puncture_pattern : 2, - req_bw : 3, - puncture_pattern_number : 6, - reserved_0b : 1, - req_paprd : 1, - duration_field_boundary_valid : 1, - duration_field_boundary : 16; - uint32_t puncture_subband_mask : 16, - reserved_0c : 16; -#else - uint32_t duration_field_boundary : 16, - duration_field_boundary_valid : 1, - req_paprd : 1, - reserved_0b : 1, - puncture_pattern_number : 6, - req_bw : 3, - use_puncture_pattern : 2, - tx_reason : 2; - uint32_t reserved_0c : 16, - puncture_subband_mask : 16; -#endif -}; - -#define PDG_TX_REQ_TX_REASON_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_TX_REASON_LSB 0 -#define PDG_TX_REQ_TX_REASON_MSB 1 -#define PDG_TX_REQ_TX_REASON_MASK 0x0000000000000003 - -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x000000000000000c - -#define PDG_TX_REQ_REQ_BW_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_REQ_BW_LSB 4 -#define PDG_TX_REQ_REQ_BW_MSB 6 -#define PDG_TX_REQ_REQ_BW_MASK 0x0000000000000070 - -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x0000000000001f80 - -#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_RESERVED_0B_LSB 13 -#define PDG_TX_REQ_RESERVED_0B_MSB 13 -#define PDG_TX_REQ_RESERVED_0B_MASK 0x0000000000002000 - -#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_REQ_PAPRD_LSB 14 -#define PDG_TX_REQ_REQ_PAPRD_MSB 14 -#define PDG_TX_REQ_REQ_PAPRD_MASK 0x0000000000004000 - -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x0000000000008000 - -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0x00000000ffff0000 - -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 32 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 47 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff00000000 - -#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_RESERVED_0C_LSB 48 -#define PDG_TX_REQ_RESERVED_0C_MSB 63 -#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_abort_request_info.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_abort_request_info.h deleted file mode 100644 index 1f3bf4b817b9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_abort_request_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_ABORT_REQUEST_INFO_H_ -#define _PHYRX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 - -struct phyrx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phyrx_abort_reason : 8, - phy_enters_nap_state : 1, - phy_enters_defer_state : 1, - gain_change_by_main : 1, - gain_change_by_bt : 1, - main_tx_indication : 1, - bt_tx_indication : 1, - concurrent_mode : 1, - reserved_0 : 1, - receive_duration : 16; -#else - uint32_t receive_duration : 16, - reserved_0 : 1, - concurrent_mode : 1, - bt_tx_indication : 1, - main_tx_indication : 1, - gain_change_by_bt : 1, - gain_change_by_main : 1, - phy_enters_defer_state : 1, - phy_enters_nap_state : 1, - phyrx_abort_reason : 8; -#endif -}; - -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff - -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100 - -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 - -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_LSB 10 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MSB 10 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MASK 0x00000400 - -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_LSB 11 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MSB 11 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MASK 0x00000800 - -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_LSB 12 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MSB 12 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MASK 0x00001000 - -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_LSB 13 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MSB 13 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MASK 0x00002000 - -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_LSB 14 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MSB 14 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MASK 0x00004000 - -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 15 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x00008000 - -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_common_user_info.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_common_user_info.h deleted file mode 100644 index b0817f33c169..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_common_user_info.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_COMMON_USER_INFO_H_ -#define _PHYRX_COMMON_USER_INFO_H_ - -#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4 - -#define NUM_OF_QWORDS_PHYRX_COMMON_USER_INFO 2 - -struct phyrx_common_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t receive_duration : 16, - reserved_0a : 16; - uint32_t u_sig_puncture_pattern_encoding : 6, - eht___reserved_g_0022_ndp : 1, - bss_color_id_2 : 6, - reserved_1a : 2, - obss_nav_update_enable : 1, - obss_nav_value : 16; - uint32_t eht_or_uhr_ppdu_type : 2, - bss_color_id : 6, - dl_ul_flag : 1, - txop_duration : 7, - cp_setting : 2, - ltf_size : 2, - spatial_reuse : 4, - rx_ndp : 1, - dot11bn_su_elr : 1, - combining_bandwidth : 3, - bss_flag : 1, - cobf_transmission : 1, - cosr_transmission : 1; - uint32_t eht_duplicate : 2, - eht_or_uhr_sig_cmn_field_type : 2, - doppler_indication : 1, - sta_id : 11, - puncture_bitmap : 16; -#else - uint32_t reserved_0a : 16, - receive_duration : 16; - uint32_t obss_nav_value : 16, - obss_nav_update_enable : 1, - reserved_1a : 2, - bss_color_id_2 : 6, - eht___reserved_g_0022_ndp : 1, - u_sig_puncture_pattern_encoding : 6; - uint32_t cosr_transmission : 1, - cobf_transmission : 1, - bss_flag : 1, - combining_bandwidth : 3, - dot11bn_su_elr : 1, - rx_ndp : 1, - spatial_reuse : 4, - ltf_size : 2, - cp_setting : 2, - txop_duration : 7, - dl_ul_flag : 1, - bss_color_id : 6, - eht_or_uhr_ppdu_type : 2; - uint32_t puncture_bitmap : 16, - sta_id : 11, - doppler_indication : 1, - eht_or_uhr_sig_cmn_field_type : 2, - eht_duplicate : 2; -#endif -}; - -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x000000000000ffff - -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0x00000000ffff0000 - -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 32 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 37 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f00000000 - -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_2_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_2_LSB 39 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_2_MSB 44 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_2_MASK 0x00001f8000000000 - -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 45 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 46 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0x0000600000000000 - -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_LSB 47 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MSB 47 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MASK 0x0000800000000000 - -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_LSB 48 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MSB 63 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MASK 0xffff000000000000 - -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_LSB 0 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MSB 1 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MASK 0x0000000000000003 - -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x00000000000000fc - -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x0000000000000100 - -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x000000000000fe00 - -#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x0000000000030000 - -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x00000000000c0000 - -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x0000000000f00000 - -#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24 -#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24 -#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x0000000001000000 - -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_LSB 25 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MSB 25 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MASK 0x0000000002000000 - -#define PHYRX_COMMON_USER_INFO_COMBINING_BANDWIDTH_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_COMBINING_BANDWIDTH_LSB 26 -#define PHYRX_COMMON_USER_INFO_COMBINING_BANDWIDTH_MSB 28 -#define PHYRX_COMMON_USER_INFO_COMBINING_BANDWIDTH_MASK 0x000000001c000000 - -#define PHYRX_COMMON_USER_INFO_BSS_FLAG_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_BSS_FLAG_LSB 29 -#define PHYRX_COMMON_USER_INFO_BSS_FLAG_MSB 29 -#define PHYRX_COMMON_USER_INFO_BSS_FLAG_MASK 0x0000000020000000 - -#define PHYRX_COMMON_USER_INFO_COBF_TRANSMISSION_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_COBF_TRANSMISSION_LSB 30 -#define PHYRX_COMMON_USER_INFO_COBF_TRANSMISSION_MSB 30 -#define PHYRX_COMMON_USER_INFO_COBF_TRANSMISSION_MASK 0x0000000040000000 - -#define PHYRX_COMMON_USER_INFO_COSR_TRANSMISSION_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_COSR_TRANSMISSION_LSB 31 -#define PHYRX_COMMON_USER_INFO_COSR_TRANSMISSION_MSB 31 -#define PHYRX_COMMON_USER_INFO_COSR_TRANSMISSION_MASK 0x0000000080000000 - -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 32 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 33 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x0000000300000000 - -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_LSB 34 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MSB 35 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MASK 0x0000000c00000000 - -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 36 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 36 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x0000001000000000 - -#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 37 -#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 47 -#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe000000000 - -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 48 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 63 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_mu_dl.h deleted file mode 100644 index da4f1691b9f7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_mu_dl.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_MU_DL_H_ -#define _PHYRX_HE_SIG_A_MU_DL_H_ - -#include "he_sig_a_mu_dl_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_DL 1 - -struct phyrx_he_sig_a_mu_dl { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; -#else - struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_mu_ul.h deleted file mode 100644 index ff9cf72a7237..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_mu_ul.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_MU_UL_H_ -#define _PHYRX_HE_SIG_A_MU_UL_H_ - -#include "he_sig_a_mu_ul_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_UL 1 - -struct phyrx_he_sig_a_mu_ul { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; -#else - struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_su.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_su.h deleted file mode 100644 index abca58673a90..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_a_su.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_SU_H_ -#define _PHYRX_HE_SIG_A_SU_H_ - -#include "he_sig_a_su_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_SU 1 - -struct phyrx_he_sig_a_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; -#else - struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b1_mu.h deleted file mode 100644 index ae784469331b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b1_mu.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B1_MU_H_ -#define _PHYRX_HE_SIG_B1_MU_H_ - -#include "he_sig_b1_mu_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1 - -struct phyrx_he_sig_b1_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#else - struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b2_mu.h deleted file mode 100644 index 6035ecffde5d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b2_mu.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B2_MU_H_ -#define _PHYRX_HE_SIG_B2_MU_H_ - -#include "he_sig_b2_mu_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_MU 1 - -struct phyrx_he_sig_b2_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; -#else - struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; -#endif -}; - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b2_ofdma.h deleted file mode 100644 index 126a9559e155..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_he_sig_b2_ofdma.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_ -#define _PHYRX_HE_SIG_B2_OFDMA_H_ - -#include "he_sig_b2_ofdma_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_OFDMA 1 - -struct phyrx_he_sig_b2_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; -#else - struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; -#endif -}; - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_ht_sig.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_ht_sig.h deleted file mode 100644 index 4dd90653d431..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_ht_sig.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HT_SIG_H_ -#define _PHYRX_HT_SIG_H_ - -#include "ht_sig_info.h" -#define NUM_OF_DWORDS_PHYRX_HT_SIG 2 - -#define NUM_OF_QWORDS_PHYRX_HT_SIG 1 - -struct phyrx_ht_sig { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ht_sig_info phyrx_ht_sig_info_details; -#else - struct ht_sig_info phyrx_ht_sig_info_details; -#endif -}; - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 36 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 37 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 42 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 49 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_l_sig_a.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_l_sig_a.h deleted file mode 100644 index 2e70822f5d06..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_l_sig_a.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_L_SIG_A_H_ -#define _PHYRX_L_SIG_A_H_ - -#include "l_sig_a_info.h" -#define NUM_OF_DWORDS_PHYRX_L_SIG_A 2 - -#define NUM_OF_QWORDS_PHYRX_L_SIG_A 1 - -struct phyrx_l_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_a_info phyrx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_a_info phyrx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_TLV64_PADDING_LSB 32 -#define PHYRX_L_SIG_A_TLV64_PADDING_MSB 63 -#define PHYRX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_l_sig_b.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_l_sig_b.h deleted file mode 100644 index 461edd24dd4e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_l_sig_b.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_L_SIG_B_H_ -#define _PHYRX_L_SIG_B_H_ - -#include "l_sig_b_info.h" -#define NUM_OF_DWORDS_PHYRX_L_SIG_B 2 - -#define NUM_OF_QWORDS_PHYRX_L_SIG_B 1 - -struct phyrx_l_sig_b { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_b_info phyrx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_b_info phyrx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_TLV64_PADDING_LSB 32 -#define PHYRX_L_SIG_B_TLV64_PADDING_MSB 63 -#define PHYRX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_location.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_location.h deleted file mode 100644 index 15a8413e304a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_location.h +++ /dev/null @@ -1,332 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_LOCATION_H_ -#define _PHYRX_LOCATION_H_ - -#include "rx_location_info.h" -#define NUM_OF_DWORDS_PHYRX_LOCATION 28 - -#define NUM_OF_QWORDS_PHYRX_LOCATION 14 - -struct phyrx_location { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_location_info rx_location_info_details; -#else - struct rx_location_info rx_location_info_details; -#endif -}; - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x0000000000000001 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x0000000000000002 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x00000000000000f0 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x000000000000ff00 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x0000000000ff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0x00000000ff000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 39 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 40 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff0000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 55 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 56 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff00000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0x00000000ffffffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 39 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 40 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff0000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 51 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 52 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 55 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f0000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 56 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff00000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000000000ff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000000ff000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x0000000000000018 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0x00000000ffffffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000000000000018 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x00000000000000ff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x000000000000ff00 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_other_receive_info_ru_details.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_other_receive_info_ru_details.h deleted file mode 100644 index a6090f721e1d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_other_receive_info_ru_details.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ -#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ - -#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4 - -#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2 - -struct phyrx_other_receive_info_ru_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_details_channel_0 : 32; - uint32_t ru_details_channel_1 : 32; - uint32_t spare : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t ru_details_channel_0 : 32; - uint32_t ru_details_channel_1 : 32; - uint32_t spare : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0x00000000ffffffff - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff00000000 - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x0000000000000008 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0x00000000ffffffff - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000008 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_pkt_end.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_pkt_end.h deleted file mode 100644 index 1d1675edc0e1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_pkt_end.h +++ /dev/null @@ -1,427 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_PKT_END_H_ -#define _PHYRX_PKT_END_H_ - -#include "phyrx_pkt_end_info.h" -#define NUM_OF_DWORDS_PHYRX_PKT_END 24 - -#define NUM_OF_QWORDS_PHYRX_PKT_END 12 - -struct phyrx_pkt_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct phyrx_pkt_end_info rx_pkt_end_details; -#else - struct phyrx_pkt_end_info rx_pkt_end_details; -#endif -}; - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x0000000000000002 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x0000000000000004 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x0000000000000008 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x0000000000000010 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x0000000000000020 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x00000000000000c0 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0x00000000ffff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB 44 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB 53 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK 0x003ff00000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_LSB 54 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xffc0000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000000000000058 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000000000000058 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_pkt_end_info.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_pkt_end_info.h deleted file mode 100644 index a21edc94d24e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_pkt_end_info.h +++ /dev/null @@ -1,450 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_PKT_END_INFO_H_ -#define _PHYRX_PKT_END_INFO_H_ - -#include "receive_rssi_info.h" -#include "rx_timing_info.h" -#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24 - -struct phyrx_pkt_end_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t __reserved_g_0001 : 1, - location_info_valid : 1, - timing_info_valid : 1, - rssi_info_valid : 1, - reserved_0a : 1, - frameless_frame_received : 1, - reserved_0b : 2, - rssi_comb : 8, - reserved_0c : 16; - struct rx_timing_info rx_timing_info_details; - struct receive_rssi_info post_rssi_info_details; - uint32_t phy_sw_status_31_0 : 32; - uint32_t phy_sw_status_63_32 : 32; -#else - uint32_t reserved_0c : 16, - rssi_comb : 8, - reserved_0b : 2, - frameless_frame_received : 1, - reserved_0a : 1, - rssi_info_valid : 1, - timing_info_valid : 1, - location_info_valid : 1, - __reserved_g_0001 : 1; - struct rx_timing_info rx_timing_info_details; - struct receive_rssi_info post_rssi_info_details; - uint32_t phy_sw_status_31_0 : 32; - uint32_t phy_sw_status_63_32 : 32; -#endif -}; - -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002 - -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004 - -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008 - -#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4 -#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4 -#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010 - -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 - -#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6 -#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7 -#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0 - -#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8 -#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15 -#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16 -#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31 -#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000 - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB 12 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB 21 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK 0x003ff000 - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_LSB 22 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xffc00000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_rssi_legacy.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_rssi_legacy.h deleted file mode 100644 index 820ced6212ca..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_rssi_legacy.h +++ /dev/null @@ -1,806 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_RSSI_LEGACY_H_ -#define _PHYRX_RSSI_LEGACY_H_ - -#include "receive_rssi_info.h" -#include "receive_pkt_start_info.h" -#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42 - -#define NUM_OF_QWORDS_PHYRX_RSSI_LEGACY 21 - -struct phyrx_rssi_legacy { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_pkt_start_info rx_pkt_start_details; - uint32_t sw_phy_meta_data : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 32; - struct receive_rssi_info pre_rssi_info_details; - struct receive_rssi_info preamble_rssi_info_details; - uint32_t pre_rssi_comb : 8, - rssi_comb : 8, - normalized_pre_rssi_comb : 8, - normalized_rssi_comb : 8; - uint32_t rssi_comb_ppdu : 8, - rssi_db_to_dbm_offset : 8, - rssi_for_spatial_reuse : 8, - rssi_for_trigger_resp : 8; -#else - struct receive_pkt_start_info rx_pkt_start_details; - uint32_t sw_phy_meta_data : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 32; - struct receive_rssi_info pre_rssi_info_details; - struct receive_rssi_info preamble_rssi_info_details; - uint32_t normalized_rssi_comb : 8, - normalized_pre_rssi_comb : 8, - rssi_comb : 8, - pre_rssi_comb : 8; - uint32_t rssi_for_trigger_resp : 8, - rssi_for_spatial_reuse : 8, - rssi_db_to_dbm_offset : 8, - rssi_comb_ppdu : 8; -#endif -}; - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_LSB 0 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MSB 3 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MASK 0x000000000000000f - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_LSB 4 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MSB 4 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x0000000000000010 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB 5 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB 7 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK 0x00000000000000e0 - -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB 8 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB 15 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_LSB 16 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MSB 31 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_LSB 32 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MSB 63 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_LSB 32 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MSB 39 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_LSB 40 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MSB 40 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MASK 0x0000010000000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_LSB 41 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MSB 63 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MASK 0xfffffe0000000000 - -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x0000000000000010 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 0 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 31 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x0000000000000010 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 32 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 63 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x0000000000000018 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000000000000018 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 32 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 63 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 32 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 39 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 40 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 47 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 48 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 55 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 56 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 63 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_user_info.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_user_info.h deleted file mode 100644 index 784904450033..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_user_info.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_USER_INFO_H_ -#define _PHYRX_USER_INFO_H_ - -#include "receive_user_info.h" -#define NUM_OF_DWORDS_PHYRX_USER_INFO 8 - -#define NUM_OF_QWORDS_PHYRX_USER_INFO 4 - -struct phyrx_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_user_info receive_user_info_details; -#else - struct receive_user_info receive_user_info_details; -#endif -}; - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 36 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000001f00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 37 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 38 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000006000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 1 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x0000000000000002 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB 2 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB 3 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK 0x000000000000000c - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB 4 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB 5 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK 0x0000000000000030 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB 6 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB 7 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK 0x00000000000000c0 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_LSB 62 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MSB 62 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MASK 0x4000000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0x8000000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phyrx_vht_sig_a.h b/drivers/staging/fw-api/hw/fig/v2/phyrx_vht_sig_a.h deleted file mode 100644 index e47f0e35adeb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phyrx_vht_sig_a.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_VHT_SIG_A_H_ -#define _PHYRX_VHT_SIG_A_H_ - -#include "vht_sig_a_info.h" -#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2 - -#define NUM_OF_QWORDS_PHYRX_VHT_SIG_A 1 - -struct phyrx_vht_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_a_info phyrx_vht_sig_a_info_details; -#else - struct vht_sig_a_info phyrx_vht_sig_a_info_details; -#endif -}; - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phytx_abort_request_info.h b/drivers/staging/fw-api/hw/fig/v2/phytx_abort_request_info.h deleted file mode 100644 index e4800f6a2d97..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phytx_abort_request_info.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_ABORT_REQUEST_INFO_H_ -#define _PHYTX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1 - -struct phytx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t phytx_abort_reason : 8, - user_number : 6, - reserved : 2; -#else - uint16_t reserved : 2, - user_number : 6, - phytx_abort_reason : 8; -#endif -}; - -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff - -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00 - -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phytx_pkt_end.h b/drivers/staging/fw-api/hw/fig/v2/phytx_pkt_end.h deleted file mode 100644 index 55911ea9edb3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phytx_pkt_end.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_PKT_END_H_ -#define _PHYTX_PKT_END_H_ - -#define NUM_OF_WORDS_PHYTX_PKT_END 28 - -#define NUM_OF_DWORDS_PHYTX_PKT_END 14 - -struct phytx_pkt_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t start_of_frame_timestamp_15_0 : 16; - uint16_t start_of_frame_timestamp_31_16 : 16; - uint16_t end_of_frame_timestamp_15_0 : 16; - uint16_t end_of_frame_timestamp_31_16 : 16; - uint16_t tx_group_delay : 12, - timing_status : 2, - phyrx_entered_nap_state : 1, - dpdtrain_done : 1; - uint16_t transmit_delay : 16; - uint16_t tpc_dbg_info_cmn_15_0 : 16; - uint16_t tpc_dbg_info_cmn_31_16 : 16; - uint16_t tpc_dbg_info_cmn_47_32 : 16; - uint16_t tpc_dbg_info_chn1_15_0 : 16; - uint16_t tpc_dbg_info_chn1_31_16 : 16; - uint16_t tpc_dbg_info_chn1_47_32 : 16; - uint16_t tpc_dbg_info_chn1_63_48 : 16; - uint16_t tpc_dbg_info_chn1_79_64 : 16; - uint16_t tpc_dbg_info_chn2_15_0 : 16; - uint16_t tpc_dbg_info_chn2_31_16 : 16; - uint16_t tpc_dbg_info_chn2_47_32 : 16; - uint16_t tpc_dbg_info_chn2_63_48 : 16; - uint16_t tpc_dbg_info_chn2_79_64 : 16; - uint16_t phytx_tx_end_sw_info_15_0 : 16; - uint16_t phytx_tx_end_sw_info_31_16 : 16; - uint16_t phytx_tx_end_sw_info_47_32 : 16; - uint16_t phytx_tx_end_sw_info_63_48 : 16; - uint16_t beamform_masked_user_bitmap_15_0 : 16; - uint16_t beamform_masked_user_bitmap_31_16 : 16; - uint16_t beamform_masked_user_bitmap_36_32 : 5, - reserved_23 : 11; - uint16_t reserved_26 : 16; - uint16_t reserved_27 : 16; -#else - uint16_t start_of_frame_timestamp_15_0 : 16; - uint16_t start_of_frame_timestamp_31_16 : 16; - uint16_t end_of_frame_timestamp_15_0 : 16; - uint16_t end_of_frame_timestamp_31_16 : 16; - uint16_t dpdtrain_done : 1, - phyrx_entered_nap_state : 1, - timing_status : 2, - tx_group_delay : 12; - uint16_t transmit_delay : 16; - uint16_t tpc_dbg_info_cmn_15_0 : 16; - uint16_t tpc_dbg_info_cmn_31_16 : 16; - uint16_t tpc_dbg_info_cmn_47_32 : 16; - uint16_t tpc_dbg_info_chn1_15_0 : 16; - uint16_t tpc_dbg_info_chn1_31_16 : 16; - uint16_t tpc_dbg_info_chn1_47_32 : 16; - uint16_t tpc_dbg_info_chn1_63_48 : 16; - uint16_t tpc_dbg_info_chn1_79_64 : 16; - uint16_t tpc_dbg_info_chn2_15_0 : 16; - uint16_t tpc_dbg_info_chn2_31_16 : 16; - uint16_t tpc_dbg_info_chn2_47_32 : 16; - uint16_t tpc_dbg_info_chn2_63_48 : 16; - uint16_t tpc_dbg_info_chn2_79_64 : 16; - uint16_t phytx_tx_end_sw_info_15_0 : 16; - uint16_t phytx_tx_end_sw_info_31_16 : 16; - uint16_t phytx_tx_end_sw_info_47_32 : 16; - uint16_t phytx_tx_end_sw_info_63_48 : 16; - uint16_t beamform_masked_user_bitmap_15_0 : 16; - uint16_t beamform_masked_user_bitmap_31_16 : 16; - uint16_t reserved_23 : 11, - beamform_masked_user_bitmap_36_32 : 5; - uint16_t reserved_26 : 16; - uint16_t reserved_27 : 16; -#endif -}; - -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000000 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000002 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 0 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 15 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000004 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000006 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 0 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 15 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TX_GROUP_DELAY_OFFSET 0x00000008 -#define PHYTX_PKT_END_TX_GROUP_DELAY_LSB 0 -#define PHYTX_PKT_END_TX_GROUP_DELAY_MSB 11 -#define PHYTX_PKT_END_TX_GROUP_DELAY_MASK 0x00000fff - -#define PHYTX_PKT_END_TIMING_STATUS_OFFSET 0x00000008 -#define PHYTX_PKT_END_TIMING_STATUS_LSB 12 -#define PHYTX_PKT_END_TIMING_STATUS_MSB 13 -#define PHYTX_PKT_END_TIMING_STATUS_MASK 0x00003000 - -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_OFFSET 0x00000008 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_LSB 14 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MSB 14 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MASK 0x00004000 - -#define PHYTX_PKT_END_DPDTRAIN_DONE_OFFSET 0x00000008 -#define PHYTX_PKT_END_DPDTRAIN_DONE_LSB 15 -#define PHYTX_PKT_END_DPDTRAIN_DONE_MSB 15 -#define PHYTX_PKT_END_DPDTRAIN_DONE_MASK 0x00008000 - -#define PHYTX_PKT_END_TRANSMIT_DELAY_OFFSET 0x0000000a -#define PHYTX_PKT_END_TRANSMIT_DELAY_LSB 0 -#define PHYTX_PKT_END_TRANSMIT_DELAY_MSB 15 -#define PHYTX_PKT_END_TRANSMIT_DELAY_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000c -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000e -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_OFFSET 0x00000010 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x00000012 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x00000014 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x00000016 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x00000018 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000001a -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000001c -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000001e -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x00000020 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x00000022 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x00000024 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x00000026 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x00000028 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000002a -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000002c -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000002e -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x00000030 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 15 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x00000032 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 4 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x0000001f - -#define PHYTX_PKT_END_RESERVED_23_OFFSET 0x00000032 -#define PHYTX_PKT_END_RESERVED_23_LSB 5 -#define PHYTX_PKT_END_RESERVED_23_MSB 15 -#define PHYTX_PKT_END_RESERVED_23_MASK 0x0000ffe0 - -#define PHYTX_PKT_END_RESERVED_26_OFFSET 0x00000034 -#define PHYTX_PKT_END_RESERVED_26_LSB 0 -#define PHYTX_PKT_END_RESERVED_26_MSB 15 -#define PHYTX_PKT_END_RESERVED_26_MASK 0x0000ffff - -#define PHYTX_PKT_END_RESERVED_27_OFFSET 0x00000036 -#define PHYTX_PKT_END_RESERVED_27_LSB 0 -#define PHYTX_PKT_END_RESERVED_27_MSB 15 -#define PHYTX_PKT_END_RESERVED_27_MASK 0x0000ffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/phytx_ppdu_header_info_request.h b/drivers/staging/fw-api/hw/fig/v2/phytx_ppdu_header_info_request.h deleted file mode 100644 index 7fbecae41236..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/phytx_ppdu_header_info_request.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ -#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ - -#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2 - -#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1 - -struct phytx_ppdu_header_info_request { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t request_type : 5, - reserved : 11; - uint16_t tlv32_padding : 16; -#else - uint16_t reserved : 11, - request_type : 5; - uint16_t tlv32_padding : 16; -#endif -}; - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0 - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/receive_pkt_start_info.h b/drivers/staging/fw-api/hw/fig/v2/receive_pkt_start_info.h deleted file mode 100644 index 7f7c81449a15..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/receive_pkt_start_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_PKT_START_INFO_H_ -#define _RECEIVE_PKT_START_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_PKT_START_INFO 4 - -struct receive_pkt_start_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reception_type : 4, - rx_chain_mask_type : 1, - receive_bandwidth : 3, - rx_chain_mask : 8, - phy_ppdu_id : 16; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t preamble_time_to_rxframe : 8, - standalone_sniffer_mode : 1, - reserved_3a : 23; -#else - uint32_t phy_ppdu_id : 16, - rx_chain_mask : 8, - receive_bandwidth : 3, - rx_chain_mask_type : 1, - reception_type : 4; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t reserved_3a : 23, - standalone_sniffer_mode : 1, - preamble_time_to_rxframe : 8; -#endif -}; - -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_LSB 0 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MSB 3 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MASK 0x0000000f - -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_LSB 4 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MSB 4 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MASK 0x00000010 - -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_LSB 5 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MSB 7 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MASK 0x000000e0 - -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_LSB 8 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MSB 15 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MASK 0x0000ff00 - -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_LSB 16 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MSB 31 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MASK 0xffff0000 - -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff - -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff - -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_LSB 0 -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MSB 7 -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff - -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_LSB 8 -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MSB 8 -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MASK 0x00000100 - -#define RECEIVE_PKT_START_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_RESERVED_3A_LSB 9 -#define RECEIVE_PKT_START_INFO_RESERVED_3A_MSB 31 -#define RECEIVE_PKT_START_INFO_RESERVED_3A_MASK 0xfffffe00 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/receive_rssi_info.h b/drivers/staging/fw-api/hw/fig/v2/receive_rssi_info.h deleted file mode 100644 index 9aaa98217d99..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/receive_rssi_info.h +++ /dev/null @@ -1,465 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_RSSI_INFO_H_ -#define _RECEIVE_RSSI_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16 - -struct receive_rssi_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rssi_pri20_chain0 : 8, - rssi_ext20_chain0 : 8, - rssi_ext40_low20_chain0 : 8, - rssi_ext40_high20_chain0 : 8; - uint32_t rssi_ext80_low20_chain0 : 8, - rssi_ext80_low_high20_chain0 : 8, - rssi_ext80_high_low20_chain0 : 8, - rssi_ext80_high20_chain0 : 8; - uint32_t rssi_ext160_0_chain0 : 8, - rssi_ext160_1_chain0 : 8, - rssi_ext160_2_chain0 : 8, - rssi_ext160_3_chain0 : 8; - uint32_t rssi_ext160_4_chain0 : 8, - rssi_ext160_5_chain0 : 8, - rssi_ext160_6_chain0 : 8, - rssi_ext160_7_chain0 : 8; - uint32_t rssi_pri20_chain1 : 8, - rssi_ext20_chain1 : 8, - rssi_ext40_low20_chain1 : 8, - rssi_ext40_high20_chain1 : 8; - uint32_t rssi_ext80_low20_chain1 : 8, - rssi_ext80_low_high20_chain1 : 8, - rssi_ext80_high_low20_chain1 : 8, - rssi_ext80_high20_chain1 : 8; - uint32_t rssi_ext160_0_chain1 : 8, - rssi_ext160_1_chain1 : 8, - rssi_ext160_2_chain1 : 8, - rssi_ext160_3_chain1 : 8; - uint32_t rssi_ext160_4_chain1 : 8, - rssi_ext160_5_chain1 : 8, - rssi_ext160_6_chain1 : 8, - rssi_ext160_7_chain1 : 8; - uint32_t rssi_pri20_chain2 : 8, - rssi_ext20_chain2 : 8, - rssi_ext40_low20_chain2 : 8, - rssi_ext40_high20_chain2 : 8; - uint32_t rssi_ext80_low20_chain2 : 8, - rssi_ext80_low_high20_chain2 : 8, - rssi_ext80_high_low20_chain2 : 8, - rssi_ext80_high20_chain2 : 8; - uint32_t rssi_ext160_0_chain2 : 8, - rssi_ext160_1_chain2 : 8, - rssi_ext160_2_chain2 : 8, - rssi_ext160_3_chain2 : 8; - uint32_t rssi_ext160_4_chain2 : 8, - rssi_ext160_5_chain2 : 8, - rssi_ext160_6_chain2 : 8, - rssi_ext160_7_chain2 : 8; - uint32_t rssi_pri20_chain3 : 8, - rssi_ext20_chain3 : 8, - rssi_ext40_low20_chain3 : 8, - rssi_ext40_high20_chain3 : 8; - uint32_t rssi_ext80_low20_chain3 : 8, - rssi_ext80_low_high20_chain3 : 8, - rssi_ext80_high_low20_chain3 : 8, - rssi_ext80_high20_chain3 : 8; - uint32_t rssi_ext160_0_chain3 : 8, - rssi_ext160_1_chain3 : 8, - rssi_ext160_2_chain3 : 8, - rssi_ext160_3_chain3 : 8; - uint32_t rssi_ext160_4_chain3 : 8, - rssi_ext160_5_chain3 : 8, - rssi_ext160_6_chain3 : 8, - rssi_ext160_7_chain3 : 8; -#else - uint32_t rssi_ext40_high20_chain0 : 8, - rssi_ext40_low20_chain0 : 8, - rssi_ext20_chain0 : 8, - rssi_pri20_chain0 : 8; - uint32_t rssi_ext80_high20_chain0 : 8, - rssi_ext80_high_low20_chain0 : 8, - rssi_ext80_low_high20_chain0 : 8, - rssi_ext80_low20_chain0 : 8; - uint32_t rssi_ext160_3_chain0 : 8, - rssi_ext160_2_chain0 : 8, - rssi_ext160_1_chain0 : 8, - rssi_ext160_0_chain0 : 8; - uint32_t rssi_ext160_7_chain0 : 8, - rssi_ext160_6_chain0 : 8, - rssi_ext160_5_chain0 : 8, - rssi_ext160_4_chain0 : 8; - uint32_t rssi_ext40_high20_chain1 : 8, - rssi_ext40_low20_chain1 : 8, - rssi_ext20_chain1 : 8, - rssi_pri20_chain1 : 8; - uint32_t rssi_ext80_high20_chain1 : 8, - rssi_ext80_high_low20_chain1 : 8, - rssi_ext80_low_high20_chain1 : 8, - rssi_ext80_low20_chain1 : 8; - uint32_t rssi_ext160_3_chain1 : 8, - rssi_ext160_2_chain1 : 8, - rssi_ext160_1_chain1 : 8, - rssi_ext160_0_chain1 : 8; - uint32_t rssi_ext160_7_chain1 : 8, - rssi_ext160_6_chain1 : 8, - rssi_ext160_5_chain1 : 8, - rssi_ext160_4_chain1 : 8; - uint32_t rssi_ext40_high20_chain2 : 8, - rssi_ext40_low20_chain2 : 8, - rssi_ext20_chain2 : 8, - rssi_pri20_chain2 : 8; - uint32_t rssi_ext80_high20_chain2 : 8, - rssi_ext80_high_low20_chain2 : 8, - rssi_ext80_low_high20_chain2 : 8, - rssi_ext80_low20_chain2 : 8; - uint32_t rssi_ext160_3_chain2 : 8, - rssi_ext160_2_chain2 : 8, - rssi_ext160_1_chain2 : 8, - rssi_ext160_0_chain2 : 8; - uint32_t rssi_ext160_7_chain2 : 8, - rssi_ext160_6_chain2 : 8, - rssi_ext160_5_chain2 : 8, - rssi_ext160_4_chain2 : 8; - uint32_t rssi_ext40_high20_chain3 : 8, - rssi_ext40_low20_chain3 : 8, - rssi_ext20_chain3 : 8, - rssi_pri20_chain3 : 8; - uint32_t rssi_ext80_high20_chain3 : 8, - rssi_ext80_high_low20_chain3 : 8, - rssi_ext80_low_high20_chain3 : 8, - rssi_ext80_low20_chain3 : 8; - uint32_t rssi_ext160_3_chain3 : 8, - rssi_ext160_2_chain3 : 8, - rssi_ext160_1_chain3 : 8, - rssi_ext160_0_chain3 : 8; - uint32_t rssi_ext160_7_chain3 : 8, - rssi_ext160_6_chain3 : 8, - rssi_ext160_5_chain3 : 8, - rssi_ext160_4_chain3 : 8; -#endif -}; - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/receive_user_info.h b/drivers/staging/fw-api/hw/fig/v2/receive_user_info.h deleted file mode 100644 index 51617cc781c0..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/receive_user_info.h +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_USER_INFO_H_ -#define _RECEIVE_USER_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8 - -struct receive_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - user_rssi : 8, - pkt_type : 4, - stbc : 1, - reception_type : 3; - uint32_t rate_mcs : 5, - sgi : 2, - __reserved_g_0004 : 1, - mimo_ss_bitmap : 8, - receive_bandwidth : 3, - reserved_1b : 5, - dl_ofdma_user_index : 8; - uint32_t dl_ofdma_content_channel : 1, - reserved_2a : 1, - qam_diff1 : 2, - qam_diff2 : 2, - qam_diff3 : 2, - nss : 3, - stream_offset : 3, - sta_dcm : 1, - ldpc : 1, - ru_type_80_0 : 4, - ru_type_80_1 : 4, - ru_type_80_2 : 4, - ru_type_80_3 : 4; - uint32_t ru_start_index_80_0 : 6, - reserved_3a : 2, - ru_start_index_80_1 : 6, - reserved_3b : 2, - ru_start_index_80_2 : 6, - reserved_3c : 2, - ru_start_index_80_3 : 6, - ldpc_2x_codeword : 1, - reserved_3d : 1; - uint32_t user_fd_rssi_seg0 : 32; - uint32_t user_fd_rssi_seg1 : 32; - uint32_t user_fd_rssi_seg2 : 32; - uint32_t user_fd_rssi_seg3 : 32; -#else - uint32_t reception_type : 3, - stbc : 1, - pkt_type : 4, - user_rssi : 8, - phy_ppdu_id : 16; - uint32_t dl_ofdma_user_index : 8, - reserved_1b : 5, - receive_bandwidth : 3, - mimo_ss_bitmap : 8, - __reserved_g_0004 : 1, - sgi : 2, - rate_mcs : 5; - uint32_t ru_type_80_3 : 4, - ru_type_80_2 : 4, - ru_type_80_1 : 4, - ru_type_80_0 : 4, - ldpc : 1, - sta_dcm : 1, - stream_offset : 3, - nss : 3, - qam_diff3 : 2, - qam_diff2 : 2, - qam_diff1 : 2, - reserved_2a : 1, - dl_ofdma_content_channel : 1; - uint32_t reserved_3d : 1, - ldpc_2x_codeword : 1, - ru_start_index_80_3 : 6, - reserved_3c : 2, - ru_start_index_80_2 : 6, - reserved_3b : 2, - ru_start_index_80_1 : 6, - reserved_3a : 2, - ru_start_index_80_0 : 6; - uint32_t user_fd_rssi_seg0 : 32; - uint32_t user_fd_rssi_seg1 : 32; - uint32_t user_fd_rssi_seg2 : 32; - uint32_t user_fd_rssi_seg3 : 32; -#endif -}; - -#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff - -#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_USER_RSSI_LSB 16 -#define RECEIVE_USER_INFO_USER_RSSI_MSB 23 -#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000 - -#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24 -#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27 -#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000 - -#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_STBC_LSB 28 -#define RECEIVE_USER_INFO_STBC_MSB 28 -#define RECEIVE_USER_INFO_STBC_MASK 0x10000000 - -#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000 - -#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RATE_MCS_LSB 0 -#define RECEIVE_USER_INFO_RATE_MCS_MSB 4 -#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000001f - -#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_SGI_LSB 5 -#define RECEIVE_USER_INFO_SGI_MSB 6 -#define RECEIVE_USER_INFO_SGI_MASK 0x00000060 - -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00 - -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000 - -#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19 -#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23 -#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000 - -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000 - -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 - -#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1 -#define RECEIVE_USER_INFO_RESERVED_2A_MSB 1 -#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x00000002 - -#define RECEIVE_USER_INFO_QAM_DIFF1_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF1_LSB 2 -#define RECEIVE_USER_INFO_QAM_DIFF1_MSB 3 -#define RECEIVE_USER_INFO_QAM_DIFF1_MASK 0x0000000c - -#define RECEIVE_USER_INFO_QAM_DIFF2_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF2_LSB 4 -#define RECEIVE_USER_INFO_QAM_DIFF2_MSB 5 -#define RECEIVE_USER_INFO_QAM_DIFF2_MASK 0x00000030 - -#define RECEIVE_USER_INFO_QAM_DIFF3_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF3_LSB 6 -#define RECEIVE_USER_INFO_QAM_DIFF3_MSB 7 -#define RECEIVE_USER_INFO_QAM_DIFF3_MASK 0x000000c0 - -#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_NSS_LSB 8 -#define RECEIVE_USER_INFO_NSS_MSB 10 -#define RECEIVE_USER_INFO_NSS_MASK 0x00000700 - -#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11 -#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13 -#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800 - -#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_STA_DCM_LSB 14 -#define RECEIVE_USER_INFO_STA_DCM_MSB 14 -#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000 - -#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_LDPC_LSB 15 -#define RECEIVE_USER_INFO_LDPC_MSB 15 -#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f - -#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6 -#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7 -#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00 - -#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14 -#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15 -#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000 - -#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22 -#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23 -#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000 - -#define RECEIVE_USER_INFO_LDPC_2X_CODEWORD_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_LDPC_2X_CODEWORD_LSB 30 -#define RECEIVE_USER_INFO_LDPC_2X_CODEWORD_MSB 30 -#define RECEIVE_USER_INFO_LDPC_2X_CODEWORD_MASK 0x40000000 - -#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3D_LSB 31 -#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31 -#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0x80000000 - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/received_response_user_15_8.h b/drivers/staging/fw-api/hw/fig/v2/received_response_user_15_8.h deleted file mode 100644 index 6cf8117ff02f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/received_response_user_15_8.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_15_8_H_ -#define _RECEIVED_RESPONSE_USER_15_8_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_15_8 32 - -struct received_response_user_15_8 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user8; - struct received_response_user_info received_response_details_user9; - struct received_response_user_info received_response_details_user10; - struct received_response_user_info received_response_details_user11; - struct received_response_user_info received_response_details_user12; - struct received_response_user_info received_response_details_user13; - struct received_response_user_info received_response_details_user14; - struct received_response_user_info received_response_details_user15; -#else - struct received_response_user_info received_response_details_user8; - struct received_response_user_info received_response_details_user9; - struct received_response_user_info received_response_details_user10; - struct received_response_user_info received_response_details_user11; - struct received_response_user_info received_response_details_user12; - struct received_response_user_info received_response_details_user13; - struct received_response_user_info received_response_details_user14; - struct received_response_user_info received_response_details_user15; -#endif -}; - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/received_response_user_23_16.h b/drivers/staging/fw-api/hw/fig/v2/received_response_user_23_16.h deleted file mode 100644 index ff56f4d96472..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/received_response_user_23_16.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_23_16_H_ -#define _RECEIVED_RESPONSE_USER_23_16_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_23_16 32 - -struct received_response_user_23_16 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user16; - struct received_response_user_info received_response_details_user17; - struct received_response_user_info received_response_details_user18; - struct received_response_user_info received_response_details_user19; - struct received_response_user_info received_response_details_user20; - struct received_response_user_info received_response_details_user21; - struct received_response_user_info received_response_details_user22; - struct received_response_user_info received_response_details_user23; -#else - struct received_response_user_info received_response_details_user16; - struct received_response_user_info received_response_details_user17; - struct received_response_user_info received_response_details_user18; - struct received_response_user_info received_response_details_user19; - struct received_response_user_info received_response_details_user20; - struct received_response_user_info received_response_details_user21; - struct received_response_user_info received_response_details_user22; - struct received_response_user_info received_response_details_user23; -#endif -}; - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/received_response_user_31_24.h b/drivers/staging/fw-api/hw/fig/v2/received_response_user_31_24.h deleted file mode 100644 index aaa90838daa9..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/received_response_user_31_24.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_31_24_H_ -#define _RECEIVED_RESPONSE_USER_31_24_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_31_24 32 - -struct received_response_user_31_24 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user24; - struct received_response_user_info received_response_details_user25; - struct received_response_user_info received_response_details_user26; - struct received_response_user_info received_response_details_user27; - struct received_response_user_info received_response_details_user28; - struct received_response_user_info received_response_details_user29; - struct received_response_user_info received_response_details_user30; - struct received_response_user_info received_response_details_user31; -#else - struct received_response_user_info received_response_details_user24; - struct received_response_user_info received_response_details_user25; - struct received_response_user_info received_response_details_user26; - struct received_response_user_info received_response_details_user27; - struct received_response_user_info received_response_details_user28; - struct received_response_user_info received_response_details_user29; - struct received_response_user_info received_response_details_user30; - struct received_response_user_info received_response_details_user31; -#endif -}; - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/received_response_user_36_32.h b/drivers/staging/fw-api/hw/fig/v2/received_response_user_36_32.h deleted file mode 100644 index 3f33fdab635e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/received_response_user_36_32.h +++ /dev/null @@ -1,705 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_36_32_H_ -#define _RECEIVED_RESPONSE_USER_36_32_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_36_32 20 - -struct received_response_user_36_32 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user32; - struct received_response_user_info received_response_details_user33; - struct received_response_user_info received_response_details_user34; - struct received_response_user_info received_response_details_user35; - struct received_response_user_info received_response_details_user36; -#else - struct received_response_user_info received_response_details_user32; - struct received_response_user_info received_response_details_user33; - struct received_response_user_info received_response_details_user34; - struct received_response_user_info received_response_details_user35; - struct received_response_user_info received_response_details_user36; -#endif -}; - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/received_response_user_7_0.h b/drivers/staging/fw-api/hw/fig/v2/received_response_user_7_0.h deleted file mode 100644 index f785aca46840..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/received_response_user_7_0.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_7_0_H_ -#define _RECEIVED_RESPONSE_USER_7_0_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_7_0 32 - -struct received_response_user_7_0 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user0; - struct received_response_user_info received_response_details_user1; - struct received_response_user_info received_response_details_user2; - struct received_response_user_info received_response_details_user3; - struct received_response_user_info received_response_details_user4; - struct received_response_user_info received_response_details_user5; - struct received_response_user_info received_response_details_user6; - struct received_response_user_info received_response_details_user7; -#else - struct received_response_user_info received_response_details_user0; - struct received_response_user_info received_response_details_user1; - struct received_response_user_info received_response_details_user2; - struct received_response_user_info received_response_details_user3; - struct received_response_user_info received_response_details_user4; - struct received_response_user_info received_response_details_user5; - struct received_response_user_info received_response_details_user6; - struct received_response_user_info received_response_details_user7; -#endif -}; - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/received_response_user_info.h b/drivers/staging/fw-api/hw/fig/v2/received_response_user_info.h deleted file mode 100644 index 3c3faf119635..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/received_response_user_info.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_INFO_H_ -#define _RECEIVED_RESPONSE_USER_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8 - -struct received_response_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mpdu_fcs_pass_count : 12, - mpdu_fcs_fail_count : 12, - qosnull_frame_count : 4, - reserved_0a : 3, - user_info_valid : 1; - uint32_t null_delimiter_count : 22, - reserved_1a : 9, - ht_control_valid : 1; - uint32_t ht_control : 32; - uint32_t qos_control_valid : 16, - eosp : 16; - uint32_t qos_control_15_8_tid_0 : 8, - qos_control_15_8_tid_1 : 8, - qos_control_15_8_tid_2 : 8, - qos_control_15_8_tid_3 : 8; - uint32_t qos_control_15_8_tid_4 : 8, - qos_control_15_8_tid_5 : 8, - qos_control_15_8_tid_6 : 8, - qos_control_15_8_tid_7 : 8; - uint32_t qos_control_15_8_tid_8 : 8, - qos_control_15_8_tid_9 : 8, - qos_control_15_8_tid_10 : 8, - qos_control_15_8_tid_11 : 8; - uint32_t qos_control_15_8_tid_12 : 8, - qos_control_15_8_tid_13 : 8, - qos_control_15_8_tid_14 : 8, - qos_control_15_8_tid_15 : 8; -#else - uint32_t user_info_valid : 1, - reserved_0a : 3, - qosnull_frame_count : 4, - mpdu_fcs_fail_count : 12, - mpdu_fcs_pass_count : 12; - uint32_t ht_control_valid : 1, - reserved_1a : 9, - null_delimiter_count : 22; - uint32_t ht_control : 32; - uint32_t eosp : 16, - qos_control_valid : 16; - uint32_t qos_control_15_8_tid_3 : 8, - qos_control_15_8_tid_2 : 8, - qos_control_15_8_tid_1 : 8, - qos_control_15_8_tid_0 : 8; - uint32_t qos_control_15_8_tid_7 : 8, - qos_control_15_8_tid_6 : 8, - qos_control_15_8_tid_5 : 8, - qos_control_15_8_tid_4 : 8; - uint32_t qos_control_15_8_tid_11 : 8, - qos_control_15_8_tid_10 : 8, - qos_control_15_8_tid_9 : 8, - qos_control_15_8_tid_8 : 8; - uint32_t qos_control_15_8_tid_15 : 8, - qos_control_15_8_tid_14 : 8, - qos_control_15_8_tid_13 : 8, - qos_control_15_8_tid_12 : 8; -#endif -}; - -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff - -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 - -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000 - -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000 - -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000 - -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff - -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000 - -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000 - -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff - -#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c -#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/received_trigger_info.h b/drivers/staging/fw-api/hw/fig/v2/received_trigger_info.h deleted file mode 100644 index ff464f4e3bb5..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/received_trigger_info.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_TRIGGER_INFO_H_ -#define _RECEIVED_TRIGGER_INFO_H_ - -#include "received_trigger_info_details.h" -#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 6 - -#define NUM_OF_QWORDS_RECEIVED_TRIGGER_INFO 3 - -struct received_trigger_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_trigger_info_details received_trigger_details; -#else - struct received_trigger_info_details received_trigger_details; -#endif -}; - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000010 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000001e0 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x00000000003ffe00 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x0000000000400000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x0000000000800000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x0000000001000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_LSB 29 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MSB 30 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MASK 0x0000000060000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x0000000080000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 47 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 48 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 59 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_LSB 61 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MSB 61 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MASK 0x2000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB 62 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB 62 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK 0x4000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0x8000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x000000000000ffff - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0x00000000ffff0000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 48 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 56 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 62 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xc000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK 0x0000000100000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_LSB 33 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MSB 36 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MASK 0x0000001e00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_LSB 37 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MSB 39 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MASK 0x000000e000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_LSB 40 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MASK 0xffffff0000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/received_trigger_info_details.h b/drivers/staging/fw-api/hw/fig/v2/received_trigger_info_details.h deleted file mode 100644 index 071942ba26bd..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/received_trigger_info_details.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_ -#define _RECEIVED_TRIGGER_INFO_DETAILS_H_ - -#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 6 - -struct received_trigger_info_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t trigger_type : 4, - ax_trigger_source : 1, - ax_trigger_type : 4, - trigger_source_sta_full_aid : 13, - frame_control_valid : 1, - qos_control_valid : 1, - he_control_info_valid : 1, - __reserved_g_0022_trigger_subtype : 4, - txop_sharing_mode : 2, - tid_aggregation_limit_is_zero : 1; - uint32_t phy_ppdu_id : 16, - lsig_response_length : 12, - __reserved_g_0035 : 1, - scsid_valid : 1, - ects_as_tb_ppdu : 1, - reserved_1a : 1; - uint32_t frame_control : 16, - qos_control : 16; - uint32_t sw_peer_id : 16, - txop_sharing_allocation_duration : 9, - __reserved_g_0035_trigger_subtype : 4, - __reserved_g_0017 : 1, - reserved_3a : 2; - uint32_t he_control : 32; - uint32_t txop_sharing_duration_from_durid : 1, - frame_durationid_lower_4 : 4, - frame_durationid_upper_3 : 3, - reserved_5a : 24; -#else - uint32_t tid_aggregation_limit_is_zero : 1, - txop_sharing_mode : 2, - __reserved_g_0022_trigger_subtype : 4, - he_control_info_valid : 1, - qos_control_valid : 1, - frame_control_valid : 1, - trigger_source_sta_full_aid : 13, - ax_trigger_type : 4, - ax_trigger_source : 1, - trigger_type : 4; - uint32_t reserved_1a : 1, - ects_as_tb_ppdu : 1, - scsid_valid : 1, - __reserved_g_0035 : 1, - lsig_response_length : 12, - phy_ppdu_id : 16; - uint32_t qos_control : 16, - frame_control : 16; - uint32_t reserved_3a : 2, - __reserved_g_0017 : 1, - __reserved_g_0035_trigger_subtype : 4, - txop_sharing_allocation_duration : 9, - sw_peer_id : 16; - uint32_t he_control : 32; - uint32_t reserved_5a : 24, - frame_durationid_upper_3 : 3, - frame_durationid_lower_4 : 4, - txop_sharing_duration_from_durid : 1; -#endif -}; - -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f - -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 - -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_LSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MASK 0x20000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_LSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MASK 0x40000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0x80000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xc0000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK 0x00000001 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_LSB 1 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MASK 0x0000001e - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_LSB 5 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MSB 7 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MASK 0x000000e0 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_LSB 8 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MASK 0xffffff00 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/reo_destination_ring.h b/drivers/staging/fw-api/hw/fig/v2/reo_destination_ring.h deleted file mode 100644 index 5147635121c1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/reo_destination_ring.h +++ /dev/null @@ -1,305 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_DESTINATION_RING_H_ -#define _REO_DESTINATION_RING_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_mpdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_REO_DESTINATION_RING 8 - -struct reo_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t release_source_module : 3, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_delink_error : 1, - sw_buffer_cookie : 20; - uint32_t msdu_link_desc_index : 4, - reserved_6a : 28; - uint32_t reo_dest_buffer_type : 1, - reo_push_reason : 2, - reo_error_code : 5, - captured_msdu_data_size : 4, - sw_exception : 1, - src_link_id : 3, - reo_destination_struct_signature : 4, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t sw_buffer_cookie : 20, - reo_delink_error : 1, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - release_source_module : 3; - uint32_t reserved_6a : 28, - msdu_link_desc_index : 4; - uint32_t looping_count : 4, - ring_id : 8, - reo_destination_struct_signature : 4, - src_link_id : 3, - sw_exception : 1, - captured_msdu_data_size : 4, - reo_error_code : 5, - reo_push_reason : 2, - reo_dest_buffer_type : 1; -#endif -}; - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_OFFSET 0x00000014 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_LSB 3 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MSB 3 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MASK 0x00000008 - -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_LSB 4 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MSB 5 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MASK 0x00000030 - -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_LSB 6 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MSB 10 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MASK 0x000007c0 - -#define REO_DESTINATION_RING_REO_DELINK_ERROR_OFFSET 0x00000014 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_LSB 11 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_MSB 11 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_MASK 0x00000800 - -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_OFFSET 0x00000018 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_LSB 0 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MSB 3 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MASK 0x0000000f - -#define REO_DESTINATION_RING_RESERVED_6A_OFFSET 0x00000018 -#define REO_DESTINATION_RING_RESERVED_6A_LSB 4 -#define REO_DESTINATION_RING_RESERVED_6A_MSB 31 -#define REO_DESTINATION_RING_RESERVED_6A_MASK 0xfffffff0 - -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0 -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0 -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001 - -#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1 -#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2 -#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006 - -#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3 -#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7 -#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8 - -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8 -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11 -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 - -#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c -#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12 -#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12 -#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000 - -#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13 -#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15 -#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000 - -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 - -#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_RING_ID_LSB 20 -#define REO_DESTINATION_RING_RING_ID_MSB 27 -#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000 - -#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28 -#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31 -#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/reo_destination_ring_with_pn.h b/drivers/staging/fw-api/hw/fig/v2/reo_destination_ring_with_pn.h deleted file mode 100644 index b486a8658388..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/reo_destination_ring_with_pn.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_DESTINATION_RING_WITH_PN_H_ -#define _REO_DESTINATION_RING_WITH_PN_H_ - -#include "rx_msdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8 - -struct reo_destination_ring_with_pn { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - uint32_t msdu_count : 8, - prev_pn_23_0 : 24; - uint32_t prev_pn_47_24 : 24, - prev_pn_127_48_info : 2, - reserved_3a : 6; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t release_source_module : 3, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_delink_error : 1, - sw_buffer_cookie : 20; - uint32_t msdu_link_desc_index : 4, - reserved_6a : 28; - uint32_t reo_dest_buffer_type : 1, - reo_push_reason : 2, - reo_error_code : 5, - captured_msdu_data_size : 4, - sw_exception : 1, - src_link_id : 3, - reo_destination_struct_signature : 4, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - uint32_t prev_pn_23_0 : 24, - msdu_count : 8; - uint32_t reserved_3a : 6, - prev_pn_127_48_info : 2, - prev_pn_47_24 : 24; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t sw_buffer_cookie : 20, - reo_delink_error : 1, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - release_source_module : 3; - uint32_t reserved_6a : 28, - msdu_link_desc_index : 4; - uint32_t looping_count : 4, - ring_id : 8, - reo_destination_struct_signature : 4, - src_link_id : 3, - sw_exception : 1, - captured_msdu_data_size : 4, - reo_error_code : 5, - reo_push_reason : 2, - reo_dest_buffer_type : 1; -#endif -}; - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK 0x000000ff - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET 0x00000008 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK 0xffffff00 - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MSB 23 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MASK 0x00ffffff - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_LSB 24 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MSB 25 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MASK 0x03000000 - -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_LSB 26 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MASK 0xfc000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MSB 3 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MASK 0x00000008 - -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_LSB 4 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MSB 5 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MASK 0x00000030 - -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_LSB 6 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MSB 10 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MASK 0x000007c0 - -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_LSB 11 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MASK 0x00000800 - -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_OFFSET 0x00000018 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MSB 3 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MASK 0x0000000f - -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_OFFSET 0x00000018 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_LSB 4 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MASK 0xfffffff0 - -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB 0 -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK 0x00000001 - -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB 1 -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK 0x00000006 - -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK 0x000000f8 - -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 - -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK 0x00001000 - -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB 13 -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB 15 -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK 0x0000e000 - -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 - -#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB 20 -#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB 27 -#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK 0x0ff00000 - -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB 28 -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/reo_entrance_ring.h b/drivers/staging/fw-api/hw/fig/v2/reo_entrance_ring.h deleted file mode 100644 index 17a68d08ce25..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/reo_entrance_ring.h +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_ENTRANCE_RING_H_ -#define _REO_ENTRANCE_RING_H_ - -#include "rx_mpdu_details.h" -#define NUM_OF_DWORDS_REO_ENTRANCE_RING 12 - -struct reo_entrance_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_mpdu_details reo_level_mpdu_frame_info; - uint32_t rx_preamble_timestamp : 32; - uint32_t reserved_7a : 8, - rounded_mpdu_byte_count : 14, - reo_destination_indication : 5, - frameless_bar : 1, - reserved_7b : 4; - uint32_t rxdma_push_reason : 2, - rxdma_error_code : 5, - mpdu_fragment_number : 4, - sw_exception : 1, - sw_exception_mpdu_delink : 1, - sw_exception_destination_ring_valid : 1, - sw_exception_destination_ring : 5, - mpdu_sequence_number : 12, - no_ack : 1; - uint32_t phy_ppdu_id : 16, - src_link_id : 3, - reserved_9a : 5, - rx_reo_queue_desc_addr_39_32 : 8; - uint32_t receive_queue_number : 16, - fw_reorder_push_reason : 2, - fw_reorder_error_code : 5, - reo_bypass : 1, - reserved_10a : 8; - uint32_t phy_lmac_latency : 16, - reserved_15a : 4, - ring_id : 8, - looping_count : 4; -#else - struct rx_mpdu_details reo_level_mpdu_frame_info; - uint32_t rx_preamble_timestamp : 32; - uint32_t reserved_7b : 4, - frameless_bar : 1, - reo_destination_indication : 5, - rounded_mpdu_byte_count : 14, - reserved_7a : 8; - uint32_t no_ack : 1, - mpdu_sequence_number : 12, - sw_exception_destination_ring : 5, - sw_exception_destination_ring_valid : 1, - sw_exception_mpdu_delink : 1, - sw_exception : 1, - mpdu_fragment_number : 4, - rxdma_error_code : 5, - rxdma_push_reason : 2; - uint32_t rx_reo_queue_desc_addr_39_32 : 8, - reserved_9a : 5, - src_link_id : 3, - phy_ppdu_id : 16; - uint32_t reserved_10a : 8, - reo_bypass : 1, - fw_reorder_error_code : 5, - fw_reorder_push_reason : 2, - receive_queue_number : 16; - uint32_t looping_count : 4, - ring_id : 8, - reserved_15a : 4, - phy_lmac_latency : 16; -#endif -}; - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET 0x00000010 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB 15 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB 16 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB 17 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK 0x00030000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB 18 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB 21 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB 22 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffc00000 - -#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_OFFSET 0x00000018 -#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_LSB 0 -#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_MSB 31 -#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_MASK 0xffffffff - -#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_RESERVED_7A_LSB 0 -#define REO_ENTRANCE_RING_RESERVED_7A_MSB 7 -#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x000000ff - -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8 -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21 -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 - -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22 -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26 -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000 - -#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27 -#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27 -#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000 - -#define REO_ENTRANCE_RING_RESERVED_7B_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_RESERVED_7B_LSB 28 -#define REO_ENTRANCE_RING_RESERVED_7B_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_7B_MASK 0xf0000000 - -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003 - -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c - -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 - -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000 - -#define REO_ENTRANCE_RING_NO_ACK_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_NO_ACK_LSB 31 -#define REO_ENTRANCE_RING_NO_ACK_MSB 31 -#define REO_ENTRANCE_RING_NO_ACK_MASK 0x80000000 - -#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16 -#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18 -#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000 - -#define REO_ENTRANCE_RING_RESERVED_9A_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_RESERVED_9A_LSB 19 -#define REO_ENTRANCE_RING_RESERVED_9A_MSB 23 -#define REO_ENTRANCE_RING_RESERVED_9A_MASK 0x00f80000 - -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 24 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 31 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0xff000000 - -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_LSB 0 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MSB 15 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_LSB 16 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MSB 17 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MASK 0x00030000 - -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_LSB 18 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MSB 22 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MASK 0x007c0000 - -#define REO_ENTRANCE_RING_REO_BYPASS_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_REO_BYPASS_LSB 23 -#define REO_ENTRANCE_RING_REO_BYPASS_MSB 23 -#define REO_ENTRANCE_RING_REO_BYPASS_MASK 0x00800000 - -#define REO_ENTRANCE_RING_RESERVED_10A_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_RESERVED_10A_LSB 24 -#define REO_ENTRANCE_RING_RESERVED_10A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_10A_MASK 0xff000000 - -#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_LSB 0 -#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_MSB 15 -#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_RESERVED_15A_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_RESERVED_15A_LSB 16 -#define REO_ENTRANCE_RING_RESERVED_15A_MSB 19 -#define REO_ENTRANCE_RING_RESERVED_15A_MASK 0x000f0000 - -#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_RING_ID_LSB 20 -#define REO_ENTRANCE_RING_RING_ID_MSB 27 -#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000 - -#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28 -#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31 -#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/response_end_status.h b/drivers/staging/fw-api/hw/fig/v2/response_end_status.h deleted file mode 100644 index a5dda1fec669..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/response_end_status.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RESPONSE_END_STATUS_H_ -#define _RESPONSE_END_STATUS_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_RESPONSE_END_STATUS 10 - -#define NUM_OF_QWORDS_RESPONSE_END_STATUS 5 - -struct response_end_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t __reserved_g_0072 : 1, - __reserved_g_0065 : 1, - __reserved_g_0062 : 1, - global_data_underflow_warning : 1, - response_transmit_status : 4, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - generated_response : 3, - mba_user_count : 7, - mba_fake_bitmap_count : 7, - coex_based_tx_bw : 3, - trig_response_related : 1, - __reserved_g_0035 : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t cbf_segment_request_mask : 8, - cbf_segment_sent_mask : 8; - uint32_t underflow_mpdu_count : 9, - data_underflow_warning : 2, - reserved_2b : 10, - only_null_delim_sent : 1, - brp_info_valid : 1, - __reserved_g_0067 : 1, - __reserved_g_0069 : 1, - __reserved_g_0051 : 1, - __reserved_g_0049 : 1, - __reserved_g_0047 : 1, - __reserved_g_0045 : 1, - __reserved_g_0043 : 1, - __reserved_g_0041 : 1, - __reserved_g_0030 : 1; - uint32_t mu_response_bitmap_31_0 : 32; - uint32_t mu_response_bitmap_36_32 : 5, - overwritten_blackout_window_bitmap : 4, - mic_overwritten : 1, - trig_resp_cmd_found : 1, - reserved_4a : 21; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t addr3_47_32 : 16, - __reserved_g_0022 : 1, - secure : 1, - __reserved_g_0022_ftm_frame_sent : 1, - reserved_20a : 13; -#else - uint32_t __reserved_g_0035 : 1, - trig_response_related : 1, - coex_based_tx_bw : 3, - mba_fake_bitmap_count : 7, - mba_user_count : 7, - generated_response : 3, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - response_transmit_status : 4, - global_data_underflow_warning : 1, - __reserved_g_0062 : 1, - __reserved_g_0065 : 1, - __reserved_g_0072 : 1; - uint32_t cbf_segment_sent_mask : 8, - cbf_segment_request_mask : 8; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t __reserved_g_0030 : 1, - __reserved_g_0041 : 1, - __reserved_g_0043 : 1, - __reserved_g_0045 : 1, - __reserved_g_0047 : 1, - __reserved_g_0049 : 1, - __reserved_g_0051 : 1, - __reserved_g_0069 : 1, - __reserved_g_0067 : 1, - brp_info_valid : 1, - only_null_delim_sent : 1, - reserved_2b : 10, - data_underflow_warning : 2, - underflow_mpdu_count : 9; - uint32_t mu_response_bitmap_31_0 : 32; - uint32_t reserved_4a : 21, - trig_resp_cmd_found : 1, - mic_overwritten : 1, - overwritten_blackout_window_bitmap : 4, - mu_response_bitmap_36_32 : 5; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t reserved_20a : 13, - __reserved_g_0022_ftm_frame_sent : 1, - secure : 1, - __reserved_g_0022 : 1, - addr3_47_32 : 16; -#endif -}; - -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008 - -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0 - -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200 - -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00 - -#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000 - -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000 - -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000 - -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000 - -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000 - -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff - -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 - -#define RESPONSE_END_STATUS_RESERVED_2B_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_RESERVED_2B_LSB 11 -#define RESPONSE_END_STATUS_RESERVED_2B_MSB 20 -#define RESPONSE_END_STATUS_RESERVED_2B_MASK 0x00000000001ff800 - -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000 - -#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000 - -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f - -#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_LSB 5 -#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MSB 8 -#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MASK 0x00000000000001e0 - -#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_LSB 9 -#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_MSB 9 -#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_MASK 0x0000000000000200 - -#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_LSB 10 -#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_MSB 10 -#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_MASK 0x0000000000000400 - -#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_RESERVED_4A_LSB 11 -#define RESPONSE_END_STATUS_RESERVED_4A_MSB 31 -#define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x00000000fffff800 - -#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_ADDR1_31_0_LSB 32 -#define RESPONSE_END_STATUS_ADDR1_31_0_MSB 63 -#define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR1_47_32_LSB 0 -#define RESPONSE_END_STATUS_ADDR1_47_32_MSB 15 -#define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x000000000000ffff - -#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR2_15_0_LSB 16 -#define RESPONSE_END_STATUS_ADDR2_15_0_MSB 31 -#define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0x00000000ffff0000 - -#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR2_47_16_LSB 32 -#define RESPONSE_END_STATUS_ADDR2_47_16_MSB 63 -#define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_ADDR3_31_0_LSB 0 -#define RESPONSE_END_STATUS_ADDR3_31_0_MSB 31 -#define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0x00000000ffffffff - -#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_ADDR3_47_32_LSB 32 -#define RESPONSE_END_STATUS_ADDR3_47_32_MSB 47 -#define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x0000ffff00000000 - -#define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_SECURE_LSB 49 -#define RESPONSE_END_STATUS_SECURE_MSB 49 -#define RESPONSE_END_STATUS_SECURE_MASK 0x0002000000000000 - -#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_RESERVED_20A_LSB 51 -#define RESPONSE_END_STATUS_RESERVED_20A_MSB 63 -#define RESPONSE_END_STATUS_RESERVED_20A_MASK 0xfff8000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/response_start_status.h b/drivers/staging/fw-api/hw/fig/v2/response_start_status.h deleted file mode 100644 index 0a3090f219fe..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/response_start_status.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RESPONSE_START_STATUS_H_ -#define _RESPONSE_START_STATUS_H_ - -#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 - -#define NUM_OF_QWORDS_RESPONSE_START_STATUS 1 - -struct response_start_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t generated_response : 3, - __reserved_g_0012 : 2, - trig_response_related : 1, - response_sta_count : 7, - mba_for_cfp_ba : 1, - mba_for_cfp_ack : 1, - ects_response_type : 2, - eba_response_type : 2, - cfp_mba : 1, - mba_for_ll_ack : 1, - mba_for_ll_ba : 1, - reserved : 10; - uint32_t phy_ppdu_id : 16, - sw_peer_id : 16; -#else - uint32_t reserved : 10, - mba_for_ll_ba : 1, - mba_for_ll_ack : 1, - cfp_mba : 1, - eba_response_type : 2, - ects_response_type : 2, - mba_for_cfp_ack : 1, - mba_for_cfp_ba : 1, - response_sta_count : 7, - trig_response_related : 1, - __reserved_g_0012 : 2, - generated_response : 3; - uint32_t sw_peer_id : 16, - phy_ppdu_id : 16; -#endif -}; - -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x0000000000000007 - -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000000000020 - -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x0000000000001fc0 - -#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_LSB 13 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_MSB 13 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_MASK 0x0000000000002000 - -#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_LSB 14 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_MSB 14 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_MASK 0x0000000000004000 - -#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_LSB 15 -#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_MSB 16 -#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_MASK 0x0000000000018000 - -#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_LSB 17 -#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_MSB 18 -#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_MASK 0x0000000000060000 - -#define RESPONSE_START_STATUS_CFP_MBA_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_CFP_MBA_LSB 19 -#define RESPONSE_START_STATUS_CFP_MBA_MSB 19 -#define RESPONSE_START_STATUS_CFP_MBA_MASK 0x0000000000080000 - -#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_LSB 20 -#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_MSB 20 -#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_MASK 0x0000000000100000 - -#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_LSB 21 -#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_MSB 21 -#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_MASK 0x0000000000200000 - -#define RESPONSE_START_STATUS_RESERVED_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_RESERVED_LSB 22 -#define RESPONSE_START_STATUS_RESERVED_MSB 31 -#define RESPONSE_START_STATUS_RESERVED_MASK 0x00000000ffc00000 - -#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 32 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 47 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff00000000 - -#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_SW_PEER_ID_LSB 48 -#define RESPONSE_START_STATUS_SW_PEER_ID_MSB 63 -#define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/ru_allocation_160_info.h b/drivers/staging/fw-api/hw/fig/v2/ru_allocation_160_info.h deleted file mode 100644 index 57d51dc44f8a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/ru_allocation_160_info.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RU_ALLOCATION_160_INFO_H_ -#define _RU_ALLOCATION_160_INFO_H_ - -#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4 - -struct ru_allocation_160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_allocation_band0_0 : 9, - ru_allocation_band0_1 : 9, - reserved_0a : 6, - ru_allocations_01_subband80_mask : 4, - ru_allocations_23_subband80_mask : 4; - uint32_t ru_allocation_band0_2 : 9, - ru_allocation_band0_3 : 9, - reserved_1a : 14; - uint32_t ru_allocation_band1_0 : 9, - ru_allocation_band1_1 : 9, - reserved_2a : 14; - uint32_t ru_allocation_band1_2 : 9, - ru_allocation_band1_3 : 9, - reserved_3a : 14; -#else - uint32_t ru_allocations_23_subband80_mask : 4, - ru_allocations_01_subband80_mask : 4, - reserved_0a : 6, - ru_allocation_band0_1 : 9, - ru_allocation_band0_0 : 9; - uint32_t reserved_1a : 14, - ru_allocation_band0_3 : 9, - ru_allocation_band0_2 : 9; - uint32_t reserved_2a : 14, - ru_allocation_band1_1 : 9, - ru_allocation_band1_0 : 9; - uint32_t reserved_3a : 14, - ru_allocation_band1_3 : 9, - ru_allocation_band1_2 : 9; -#endif -}; - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB 23 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK 0x00fc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK 0xfffc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK 0xfffc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK 0xfffc0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_attention.h b/drivers/staging/fw-api/hw/fig/v2/rx_attention.h deleted file mode 100644 index cac7c2fb52c3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_attention.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_ATTENTION_H_ -#define _RX_ATTENTION_H_ - -#define NUM_OF_DWORDS_RX_ATTENTION 4 - -#define NUM_OF_QWORDS_RX_ATTENTION 2 - -struct rx_attention { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t first_mpdu : 1, - reserved_1a : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - a_msdu_error : 1, - fragment_flag : 1, - order : 1, - cce_match : 1, - overflow_err : 1, - msdu_length_err : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - sa_idx_invalid : 1, - da_idx_invalid : 1, - reserved_1b : 1, - rx_in_tx_decrypt_byp : 1, - encrypt_required : 1, - directed : 1, - buffer_fragment : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - fcs_err : 1; - uint32_t flow_idx_timeout : 1, - flow_idx_invalid : 1, - wifi_parser_error : 1, - amsdu_parser_error : 1, - sa_idx_timeout : 1, - da_idx_timeout : 1, - msdu_limit_error : 1, - da_is_valid : 1, - da_is_mcbc : 1, - sa_is_valid : 1, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - reserved_2 : 17, - msdu_done : 1; - uint32_t tlv64_padding : 32; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t fcs_err : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - buffer_fragment : 1, - directed : 1, - encrypt_required : 1, - rx_in_tx_decrypt_byp : 1, - reserved_1b : 1, - da_idx_invalid : 1, - sa_idx_invalid : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - msdu_length_err : 1, - overflow_err : 1, - cce_match : 1, - order : 1, - fragment_flag : 1, - a_msdu_error : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - reserved_1a : 1, - first_mpdu : 1; - uint32_t msdu_done : 1, - reserved_2 : 17, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - sa_is_valid : 1, - da_is_mcbc : 1, - da_is_valid : 1, - msdu_limit_error : 1, - da_idx_timeout : 1, - sa_idx_timeout : 1, - amsdu_parser_error : 1, - wifi_parser_error : 1, - flow_idx_invalid : 1, - flow_idx_timeout : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_0_LSB 9 -#define RX_ATTENTION_RESERVED_0_MSB 15 -#define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_PHY_PPDU_ID_LSB 16 -#define RX_ATTENTION_PHY_PPDU_ID_MSB 31 -#define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FIRST_MPDU_LSB 32 -#define RX_ATTENTION_FIRST_MPDU_MSB 32 -#define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000 - -#define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_1A_LSB 33 -#define RX_ATTENTION_RESERVED_1A_MSB 33 -#define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000 - -#define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MCAST_BCAST_LSB 34 -#define RX_ATTENTION_MCAST_BCAST_MSB 34 -#define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000 - -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000 - -#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000 - -#define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_POWER_MGMT_LSB 37 -#define RX_ATTENTION_POWER_MGMT_MSB 37 -#define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000 - -#define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000 -#define RX_ATTENTION_NON_QOS_LSB 38 -#define RX_ATTENTION_NON_QOS_MSB 38 -#define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000 - -#define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000 -#define RX_ATTENTION_NULL_DATA_LSB 39 -#define RX_ATTENTION_NULL_DATA_MSB 39 -#define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000 - -#define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MGMT_TYPE_LSB 40 -#define RX_ATTENTION_MGMT_TYPE_MSB 40 -#define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000 - -#define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000 -#define RX_ATTENTION_CTRL_TYPE_LSB 41 -#define RX_ATTENTION_CTRL_TYPE_MSB 41 -#define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000 - -#define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MORE_DATA_LSB 42 -#define RX_ATTENTION_MORE_DATA_MSB 42 -#define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000 - -#define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000 -#define RX_ATTENTION_EOSP_LSB 43 -#define RX_ATTENTION_EOSP_MSB 43 -#define RX_ATTENTION_EOSP_MASK 0x0000080000000000 - -#define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_A_MSDU_ERROR_LSB 44 -#define RX_ATTENTION_A_MSDU_ERROR_MSB 44 -#define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000 - -#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FRAGMENT_FLAG_LSB 45 -#define RX_ATTENTION_FRAGMENT_FLAG_MSB 45 -#define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000 - -#define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000 -#define RX_ATTENTION_ORDER_LSB 46 -#define RX_ATTENTION_ORDER_MSB 46 -#define RX_ATTENTION_ORDER_MASK 0x0000400000000000 - -#define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000 -#define RX_ATTENTION_CCE_MATCH_LSB 47 -#define RX_ATTENTION_CCE_MATCH_MSB 47 -#define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000 - -#define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_OVERFLOW_ERR_LSB 48 -#define RX_ATTENTION_OVERFLOW_ERR_MSB 48 -#define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000 - -#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49 -#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49 -#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000 - -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000 - -#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000 -#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51 -#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51 -#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000 - -#define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_SA_IDX_INVALID_LSB 52 -#define RX_ATTENTION_SA_IDX_INVALID_MSB 52 -#define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000 - -#define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DA_IDX_INVALID_LSB 53 -#define RX_ATTENTION_DA_IDX_INVALID_MSB 53 -#define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000 - -#define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_1B_LSB 54 -#define RX_ATTENTION_RESERVED_1B_MSB 54 -#define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000 - -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000 - -#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000 -#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56 -#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56 -#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000 - -#define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DIRECTED_LSB 57 -#define RX_ATTENTION_DIRECTED_MSB 57 -#define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000 - -#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58 -#define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58 -#define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000 - -#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59 -#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59 -#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000 - -#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_TKIP_MIC_ERR_LSB 60 -#define RX_ATTENTION_TKIP_MIC_ERR_MSB 60 -#define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000 - -#define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DECRYPT_ERR_LSB 61 -#define RX_ATTENTION_DECRYPT_ERR_MSB 61 -#define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000 - -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000 - -#define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FCS_ERR_LSB 63 -#define RX_ATTENTION_FCS_ERR_MSB 63 -#define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000 - -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001 - -#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 -#define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 -#define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002 - -#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 -#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 -#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004 - -#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008 - -#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 -#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 -#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010 - -#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 -#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 -#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020 - -#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040 - -#define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IS_VALID_LSB 7 -#define RX_ATTENTION_DA_IS_VALID_MSB 7 -#define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080 - -#define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IS_MCBC_LSB 8 -#define RX_ATTENTION_DA_IS_MCBC_MSB 8 -#define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100 - -#define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_SA_IS_VALID_LSB 9 -#define RX_ATTENTION_SA_IS_VALID_MSB 9 -#define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200 - -#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00 - -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000 - -#define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008 -#define RX_ATTENTION_RESERVED_2_LSB 14 -#define RX_ATTENTION_RESERVED_2_MSB 30 -#define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000 - -#define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008 -#define RX_ATTENTION_MSDU_DONE_LSB 31 -#define RX_ATTENTION_MSDU_DONE_MSB 31 -#define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000 - -#define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008 -#define RX_ATTENTION_TLV64_PADDING_LSB 32 -#define RX_ATTENTION_TLV64_PADDING_MSB 63 -#define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_flow_search_entry.h b/drivers/staging/fw-api/hw/fig/v2/rx_flow_search_entry.h deleted file mode 100644 index 25f1f81c439f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_flow_search_entry.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FLOW_SEARCH_ENTRY_H_ -#define _RX_FLOW_SEARCH_ENTRY_H_ - -#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 - -struct rx_flow_search_entry { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t src_ip_127_96 : 32; - uint32_t src_ip_95_64 : 32; - uint32_t src_ip_63_32 : 32; - uint32_t src_ip_31_0 : 32; - uint32_t dest_ip_127_96 : 32; - uint32_t dest_ip_95_64 : 32; - uint32_t dest_ip_63_32 : 32; - uint32_t dest_ip_31_0 : 32; - uint32_t src_port : 16, - dest_port : 16; - uint32_t l4_protocol : 8, - valid : 1, - reserved_9 : 4, - service_code : 9, - priority_valid : 1, - use_ppe : 1, - reo_destination_indication : 5, - msdu_drop : 1, - reo_destination_handler : 2; - uint32_t metadata : 32; - uint32_t aggregation_count : 7, - lro_eligible : 1, - msdu_count : 24; - uint32_t msdu_byte_count : 32; - uint32_t timestamp : 32; - uint32_t cumulative_ip_length_pmac1 : 16, - cumulative_ip_length : 16; - uint32_t tcp_sequence_number : 32; -#else - uint32_t src_ip_127_96 : 32; - uint32_t src_ip_95_64 : 32; - uint32_t src_ip_63_32 : 32; - uint32_t src_ip_31_0 : 32; - uint32_t dest_ip_127_96 : 32; - uint32_t dest_ip_95_64 : 32; - uint32_t dest_ip_63_32 : 32; - uint32_t dest_ip_31_0 : 32; - uint32_t dest_port : 16, - src_port : 16; - uint32_t reo_destination_handler : 2, - msdu_drop : 1, - reo_destination_indication : 5, - use_ppe : 1, - priority_valid : 1, - service_code : 9, - reserved_9 : 4, - valid : 1, - l4_protocol : 8; - uint32_t metadata : 32; - uint32_t msdu_count : 24, - lro_eligible : 1, - aggregation_count : 7; - uint32_t msdu_byte_count : 32; - uint32_t timestamp : 32; - uint32_t cumulative_ip_length : 16, - cumulative_ip_length_pmac1 : 16; - uint32_t tcp_sequence_number : 32; -#endif -}; - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000 - -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff - -#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8 -#define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8 -#define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100 - -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 12 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x00001e00 - -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB 13 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB 21 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK 0x003fe000 - -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB 22 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB 22 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK 0x00400000 - -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000 - -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000 - -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000 - -#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028 -#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6 -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f - -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7 -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7 -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8 -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET 0x00000038 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB 15 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK 0x0000ffff - -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 - -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_frame_1k_bitmap_ack.h b/drivers/staging/fw-api/hw/fig/v2/rx_frame_1k_bitmap_ack.h deleted file mode 100644 index a43548b14a07..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_frame_1k_bitmap_ack.h +++ /dev/null @@ -1,362 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_1K_BITMAP_ACK_H_ -#define _RX_FRAME_1K_BITMAP_ACK_H_ - -#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38 - -#define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19 - -struct rx_frame_1k_bitmap_ack { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 5, - ba_bitmap_size : 2, - gen_mlo_notification : 1, - reserved_0b : 2, - ba_tid : 4, - sta_full_aid : 13, - reserved_0c : 5; - uint32_t mlo_sta_id : 10, - ba_size_1024_allowed : 1, - ba_size_512_allowed : 1, - reserved_1a : 20; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_ctrl : 16, - ba_ts_seq : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; - uint32_t ba_ts_bitmap_287_256 : 32; - uint32_t ba_ts_bitmap_319_288 : 32; - uint32_t ba_ts_bitmap_351_320 : 32; - uint32_t ba_ts_bitmap_383_352 : 32; - uint32_t ba_ts_bitmap_415_384 : 32; - uint32_t ba_ts_bitmap_447_416 : 32; - uint32_t ba_ts_bitmap_479_448 : 32; - uint32_t ba_ts_bitmap_511_480 : 32; - uint32_t ba_ts_bitmap_543_512 : 32; - uint32_t ba_ts_bitmap_575_544 : 32; - uint32_t ba_ts_bitmap_607_576 : 32; - uint32_t ba_ts_bitmap_639_608 : 32; - uint32_t ba_ts_bitmap_671_640 : 32; - uint32_t ba_ts_bitmap_703_672 : 32; - uint32_t ba_ts_bitmap_735_704 : 32; - uint32_t ba_ts_bitmap_767_736 : 32; - uint32_t ba_ts_bitmap_799_768 : 32; - uint32_t ba_ts_bitmap_831_800 : 32; - uint32_t ba_ts_bitmap_863_832 : 32; - uint32_t ba_ts_bitmap_895_864 : 32; - uint32_t ba_ts_bitmap_927_896 : 32; - uint32_t ba_ts_bitmap_959_928 : 32; - uint32_t ba_ts_bitmap_991_960 : 32; - uint32_t ba_ts_bitmap_1023_992 : 32; -#else - uint32_t reserved_0c : 5, - sta_full_aid : 13, - ba_tid : 4, - reserved_0b : 2, - gen_mlo_notification : 1, - ba_bitmap_size : 2, - reserved_0a : 5; - uint32_t reserved_1a : 20, - ba_size_512_allowed : 1, - ba_size_1024_allowed : 1, - mlo_sta_id : 10; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_seq : 16, - ba_ts_ctrl : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; - uint32_t ba_ts_bitmap_287_256 : 32; - uint32_t ba_ts_bitmap_319_288 : 32; - uint32_t ba_ts_bitmap_351_320 : 32; - uint32_t ba_ts_bitmap_383_352 : 32; - uint32_t ba_ts_bitmap_415_384 : 32; - uint32_t ba_ts_bitmap_447_416 : 32; - uint32_t ba_ts_bitmap_479_448 : 32; - uint32_t ba_ts_bitmap_511_480 : 32; - uint32_t ba_ts_bitmap_543_512 : 32; - uint32_t ba_ts_bitmap_575_544 : 32; - uint32_t ba_ts_bitmap_607_576 : 32; - uint32_t ba_ts_bitmap_639_608 : 32; - uint32_t ba_ts_bitmap_671_640 : 32; - uint32_t ba_ts_bitmap_703_672 : 32; - uint32_t ba_ts_bitmap_735_704 : 32; - uint32_t ba_ts_bitmap_767_736 : 32; - uint32_t ba_ts_bitmap_799_768 : 32; - uint32_t ba_ts_bitmap_831_800 : 32; - uint32_t ba_ts_bitmap_863_832 : 32; - uint32_t ba_ts_bitmap_895_864 : 32; - uint32_t ba_ts_bitmap_927_896 : 32; - uint32_t ba_ts_bitmap_959_928 : 32; - uint32_t ba_ts_bitmap_991_960 : 32; - uint32_t ba_ts_bitmap_1023_992 : 32; -#endif -}; - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x000000000000001f - -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 - -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB 7 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB 7 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK 0x0000000000000080 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 8 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x0000000000000300 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 - -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0x00000000f8000000 - -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MSB 41 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MASK 0x000003ff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB 42 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB 42 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK 0x0000040000000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB 43 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB 43 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK 0x0000080000000000 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_LSB 44 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MASK 0xfffff00000000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 47 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 48 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 47 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 48 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff000000000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000020 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000028 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000030 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x0000000000000038 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x0000000000000038 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000000000000040 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x0000000000000040 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x0000000000000048 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x0000000000000048 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000000000000050 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x0000000000000050 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x0000000000000058 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x0000000000000058 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000000000000060 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x0000000000000060 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x0000000000000068 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x0000000000000068 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000000000000070 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x0000000000000070 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x0000000000000078 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x0000000000000078 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000000000000080 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x0000000000000080 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x0000000000000088 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x0000000000000088 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000000000000090 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x0000000000000090 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_frame_bitmap_ack.h b/drivers/staging/fw-api/hw/fig/v2/rx_frame_bitmap_ack.h deleted file mode 100644 index 0b68486b038e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_frame_bitmap_ack.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_BITMAP_ACK_H_ -#define _RX_FRAME_BITMAP_ACK_H_ - -#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14 - -#define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7 - -struct rx_frame_bitmap_ack { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t no_bitmap_available : 1, - explicit_ack : 1, - explict_ack_type : 3, - ba_bitmap_size : 2, - gen_mlo_notification : 1, - reserved_0a : 2, - ba_tid : 4, - sta_full_aid : 13, - reserved_0b : 5; - uint32_t mlo_sta_id : 10, - ba_size_1024_allowed : 1, - ba_size_512_allowed : 1, - ba_size_256_allowed : 1, - ba_size_128_allowed : 1, - ba_size_64_allowed : 1, - ba_size_32_allowed : 1, - reserved_1a : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_ctrl : 16, - ba_ts_seq : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; -#else - uint32_t reserved_0b : 5, - sta_full_aid : 13, - ba_tid : 4, - reserved_0a : 2, - gen_mlo_notification : 1, - ba_bitmap_size : 2, - explict_ack_type : 3, - explicit_ack : 1, - no_bitmap_available : 1; - uint32_t reserved_1a : 16, - ba_size_32_allowed : 1, - ba_size_64_allowed : 1, - ba_size_128_allowed : 1, - ba_size_256_allowed : 1, - ba_size_512_allowed : 1, - ba_size_1024_allowed : 1, - mlo_sta_id : 10; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_seq : 16, - ba_ts_ctrl : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; -#endif -}; - -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x0000000000000001 - -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x0000000000000002 - -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x000000000000001c - -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 - -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB 7 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB 7 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK 0x0000000000000080 - -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 8 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x0000000000000300 - -#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 -#define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 -#define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 - -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 - -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0x00000000f8000000 - -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_LSB 32 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MSB 41 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MASK 0x000003ff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB 42 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB 42 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK 0x0000040000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB 43 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB 43 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK 0x0000080000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_LSB 44 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MSB 44 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MASK 0x0000100000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_LSB 45 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MSB 45 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MASK 0x0000200000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_LSB 46 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MSB 46 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MASK 0x0000400000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_LSB 47 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MSB 47 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MASK 0x0000800000000000 - -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_LSB 48 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MSB 63 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 0 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 31 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 32 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 47 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 48 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 63 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 0 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 31 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 47 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 48 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000020 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000028 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000030 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_frame_bitmap_req.h b/drivers/staging/fw-api/hw/fig/v2/rx_frame_bitmap_req.h deleted file mode 100644 index 24f8ddd1c57c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_frame_bitmap_req.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_BITMAP_REQ_H_ -#define _RX_FRAME_BITMAP_REQ_H_ - -#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 2 - -#define NUM_OF_QWORDS_RX_FRAME_BITMAP_REQ 1 - -struct rx_frame_bitmap_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t explicit_user_request : 1, - user_request_type : 1, - user_number : 6, - sw_peer_id : 16, - tid_specific_request : 1, - requested_tid : 4, - reserved_0 : 3; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0 : 3, - requested_tid : 4, - tid_specific_request : 1, - sw_peer_id : 16, - user_number : 6, - user_request_type : 1, - explicit_user_request : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB 0 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB 0 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK 0x0000000000000001 - -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB 1 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB 1 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK 0x0000000000000002 - -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB 2 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB 7 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK 0x00000000000000fc - -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB 8 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB 23 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK 0x0000000000ffff00 - -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB 24 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB 24 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK 0x0000000001000000 - -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB 25 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB 28 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK 0x000000001e000000 - -#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB 29 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB 31 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK 0x00000000e0000000 - -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_LSB 32 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MSB 63 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_location_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_location_info.h deleted file mode 100644 index ee000f6d4cda..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_location_info.h +++ /dev/null @@ -1,453 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_LOCATION_INFO_H_ -#define _RX_LOCATION_INFO_H_ - -#define NUM_OF_DWORDS_RX_LOCATION_INFO 28 - -struct rx_location_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_location_info_valid : 1, - rtt_hw_ifft_mode : 1, - rtt___reserved_g_0020_mode : 2, - reserved_0 : 4, - rtt_num_fac : 8, - rtt_rx_chain_mask : 8, - rtt_num_streams : 8; - uint32_t rtt_first_selected_chain : 8, - rtt_second_selected_chain : 8, - rtt_cfr_status : 8, - rtt_cir_status : 8; - uint32_t rtt_che_buffer_pointer_low32 : 32; - uint32_t rtt_che_buffer_pointer_high8 : 8, - reserved_3 : 8, - rtt_pkt_bw_vht : 4, - rtt_pkt_bw_leg : 4, - rtt_mcs_rate : 8; - uint32_t rtt_cfo_measurement : 16, - rtt_preamble_type : 8, - rtt_gi_type : 8; - uint32_t rx_start_ts : 32; - uint32_t rx_start_ts_upper : 32; - uint32_t rx_end_ts : 32; - uint32_t gain_chain0 : 16, - gain_chain1 : 16; - uint32_t gain_chain2 : 16, - gain_chain3 : 16; - uint32_t gain_report_status : 8, - rtt_timing_backoff_sel : 8, - rtt_fac_combined : 16; - uint32_t rtt_fac_0 : 16, - rtt_fac_1 : 16; - uint32_t rtt_fac_2 : 16, - rtt_fac_3 : 16; - uint32_t rtt_fac_4 : 16, - rtt_fac_5 : 16; - uint32_t rtt_fac_6 : 16, - rtt_fac_7 : 16; - uint32_t rtt_fac_8 : 16, - rtt_fac_9 : 16; - uint32_t rtt_fac_10 : 16, - rtt_fac_11 : 16; - uint32_t rtt_fac_12 : 16, - rtt_fac_13 : 16; - uint32_t rtt_fac_14 : 16, - rtt_fac_15 : 16; - uint32_t rtt_fac_16 : 16, - rtt_fac_17 : 16; - uint32_t rtt_fac_18 : 16, - rtt_fac_19 : 16; - uint32_t rtt_fac_20 : 16, - rtt_fac_21 : 16; - uint32_t rtt_fac_22 : 16, - rtt_fac_23 : 16; - uint32_t rtt_fac_24 : 16, - rtt_fac_25 : 16; - uint32_t rtt_fac_26 : 16, - rtt_fac_27 : 16; - uint32_t rtt_fac_28 : 16, - rtt_fac_29 : 16; - uint32_t rtt_fac_30 : 16, - rtt_fac_31 : 16; - uint32_t reserved_27a : 32; -#else - uint32_t rtt_num_streams : 8, - rtt_rx_chain_mask : 8, - rtt_num_fac : 8, - reserved_0 : 4, - rtt___reserved_g_0020_mode : 2, - rtt_hw_ifft_mode : 1, - rx_location_info_valid : 1; - uint32_t rtt_cir_status : 8, - rtt_cfr_status : 8, - rtt_second_selected_chain : 8, - rtt_first_selected_chain : 8; - uint32_t rtt_che_buffer_pointer_low32 : 32; - uint32_t rtt_mcs_rate : 8, - rtt_pkt_bw_leg : 4, - rtt_pkt_bw_vht : 4, - reserved_3 : 8, - rtt_che_buffer_pointer_high8 : 8; - uint32_t rtt_gi_type : 8, - rtt_preamble_type : 8, - rtt_cfo_measurement : 16; - uint32_t rx_start_ts : 32; - uint32_t rx_start_ts_upper : 32; - uint32_t rx_end_ts : 32; - uint32_t gain_chain1 : 16, - gain_chain0 : 16; - uint32_t gain_chain3 : 16, - gain_chain2 : 16; - uint32_t rtt_fac_combined : 16, - rtt_timing_backoff_sel : 8, - gain_report_status : 8; - uint32_t rtt_fac_1 : 16, - rtt_fac_0 : 16; - uint32_t rtt_fac_3 : 16, - rtt_fac_2 : 16; - uint32_t rtt_fac_5 : 16, - rtt_fac_4 : 16; - uint32_t rtt_fac_7 : 16, - rtt_fac_6 : 16; - uint32_t rtt_fac_9 : 16, - rtt_fac_8 : 16; - uint32_t rtt_fac_11 : 16, - rtt_fac_10 : 16; - uint32_t rtt_fac_13 : 16, - rtt_fac_12 : 16; - uint32_t rtt_fac_15 : 16, - rtt_fac_14 : 16; - uint32_t rtt_fac_17 : 16, - rtt_fac_16 : 16; - uint32_t rtt_fac_19 : 16, - rtt_fac_18 : 16; - uint32_t rtt_fac_21 : 16, - rtt_fac_20 : 16; - uint32_t rtt_fac_23 : 16, - rtt_fac_22 : 16; - uint32_t rtt_fac_25 : 16, - rtt_fac_24 : 16; - uint32_t rtt_fac_27 : 16, - rtt_fac_26 : 16; - uint32_t rtt_fac_29 : 16, - rtt_fac_28 : 16; - uint32_t rtt_fac_31 : 16, - rtt_fac_30 : 16; - uint32_t reserved_27a : 32; -#endif -}; - -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB 0 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB 0 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK 0x00000001 - -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB 1 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB 1 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK 0x00000002 - -#define RX_LOCATION_INFO_RESERVED_0_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RESERVED_0_LSB 4 -#define RX_LOCATION_INFO_RESERVED_0_MSB 7 -#define RX_LOCATION_INFO_RESERVED_0_MASK 0x000000f0 - -#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB 8 -#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB 15 -#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB 16 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB 23 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB 24 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB 31 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB 0 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB 7 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff - -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB 8 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB 15 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB 16 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB 23 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB 24 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB 31 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff - -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff - -#define RX_LOCATION_INFO_RESERVED_3_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RESERVED_3_LSB 8 -#define RX_LOCATION_INFO_RESERVED_3_MSB 15 -#define RX_LOCATION_INFO_RESERVED_3_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB 16 -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB 19 -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK 0x000f0000 - -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB 20 -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB 23 -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK 0x00f00000 - -#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB 24 -#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB 31 -#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB 0 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB 15 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB 16 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB 23 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB 24 -#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB 31 -#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK 0xff000000 - -#define RX_LOCATION_INFO_RX_START_TS_OFFSET 0x00000014 -#define RX_LOCATION_INFO_RX_START_TS_LSB 0 -#define RX_LOCATION_INFO_RX_START_TS_MSB 31 -#define RX_LOCATION_INFO_RX_START_TS_MASK 0xffffffff - -#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET 0x00000018 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB 0 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB 31 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK 0xffffffff - -#define RX_LOCATION_INFO_RX_END_TS_OFFSET 0x0000001c -#define RX_LOCATION_INFO_RX_END_TS_LSB 0 -#define RX_LOCATION_INFO_RX_END_TS_MSB 31 -#define RX_LOCATION_INFO_RX_END_TS_MASK 0xffffffff - -#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET 0x00000020 -#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB 0 -#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB 15 -#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK 0x0000ffff - -#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET 0x00000020 -#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB 16 -#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB 31 -#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK 0xffff0000 - -#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET 0x00000024 -#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB 0 -#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB 15 -#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK 0x0000ffff - -#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET 0x00000024 -#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB 16 -#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB 31 -#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK 0xffff0000 - -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET 0x00000028 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB 0 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB 7 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK 0x000000ff - -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB 8 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB 15 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET 0x00000028 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET 0x0000002c -#define RX_LOCATION_INFO_RTT_FAC_0_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_0_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_0_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET 0x0000002c -#define RX_LOCATION_INFO_RTT_FAC_1_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_1_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_1_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET 0x00000030 -#define RX_LOCATION_INFO_RTT_FAC_2_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_2_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_2_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET 0x00000030 -#define RX_LOCATION_INFO_RTT_FAC_3_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_3_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_3_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET 0x00000034 -#define RX_LOCATION_INFO_RTT_FAC_4_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_4_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_4_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET 0x00000034 -#define RX_LOCATION_INFO_RTT_FAC_5_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_5_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_5_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET 0x00000038 -#define RX_LOCATION_INFO_RTT_FAC_6_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_6_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_6_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET 0x00000038 -#define RX_LOCATION_INFO_RTT_FAC_7_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_7_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_7_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET 0x0000003c -#define RX_LOCATION_INFO_RTT_FAC_8_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_8_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_8_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET 0x0000003c -#define RX_LOCATION_INFO_RTT_FAC_9_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_9_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_9_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET 0x00000040 -#define RX_LOCATION_INFO_RTT_FAC_10_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_10_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_10_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET 0x00000040 -#define RX_LOCATION_INFO_RTT_FAC_11_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_11_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_11_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET 0x00000044 -#define RX_LOCATION_INFO_RTT_FAC_12_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_12_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_12_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET 0x00000044 -#define RX_LOCATION_INFO_RTT_FAC_13_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_13_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_13_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET 0x00000048 -#define RX_LOCATION_INFO_RTT_FAC_14_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_14_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_14_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET 0x00000048 -#define RX_LOCATION_INFO_RTT_FAC_15_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_15_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_15_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET 0x0000004c -#define RX_LOCATION_INFO_RTT_FAC_16_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_16_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_16_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET 0x0000004c -#define RX_LOCATION_INFO_RTT_FAC_17_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_17_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_17_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET 0x00000050 -#define RX_LOCATION_INFO_RTT_FAC_18_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_18_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_18_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET 0x00000050 -#define RX_LOCATION_INFO_RTT_FAC_19_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_19_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_19_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET 0x00000054 -#define RX_LOCATION_INFO_RTT_FAC_20_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_20_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_20_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET 0x00000054 -#define RX_LOCATION_INFO_RTT_FAC_21_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_21_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_21_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET 0x00000058 -#define RX_LOCATION_INFO_RTT_FAC_22_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_22_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_22_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET 0x00000058 -#define RX_LOCATION_INFO_RTT_FAC_23_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_23_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_23_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET 0x0000005c -#define RX_LOCATION_INFO_RTT_FAC_24_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_24_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_24_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET 0x0000005c -#define RX_LOCATION_INFO_RTT_FAC_25_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_25_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_25_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET 0x00000060 -#define RX_LOCATION_INFO_RTT_FAC_26_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_26_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_26_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET 0x00000060 -#define RX_LOCATION_INFO_RTT_FAC_27_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_27_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_27_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET 0x00000064 -#define RX_LOCATION_INFO_RTT_FAC_28_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_28_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_28_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET 0x00000064 -#define RX_LOCATION_INFO_RTT_FAC_29_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_29_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_29_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET 0x00000068 -#define RX_LOCATION_INFO_RTT_FAC_30_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_30_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_30_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET 0x00000068 -#define RX_LOCATION_INFO_RTT_FAC_31_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_31_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_31_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RESERVED_27A_OFFSET 0x0000006c -#define RX_LOCATION_INFO_RESERVED_27A_LSB 0 -#define RX_LOCATION_INFO_RESERVED_27A_MSB 31 -#define RX_LOCATION_INFO_RESERVED_27A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_desc_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_desc_info.h deleted file mode 100644 index 30f538fb1228..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_desc_info.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_DESC_INFO_H_ -#define _RX_MPDU_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 - -struct rx_mpdu_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t msdu_count : 8, - fragment_flag : 1, - mpdu_retry_bit : 1, - ampdu_flag : 1, - bar_frame : 1, - pn_fields_contain_valid_info : 1, - raw_mpdu : 1, - more_fragment_flag : 1, - src_info : 12, - mpdu_qos_control_valid : 1, - tid : 4; - uint32_t peer_meta_data : 32; -#else - uint32_t tid : 4, - mpdu_qos_control_valid : 1, - src_info : 12, - more_fragment_flag : 1, - raw_mpdu : 1, - pn_fields_contain_valid_info : 1, - bar_frame : 1, - ampdu_flag : 1, - mpdu_retry_bit : 1, - fragment_flag : 1, - msdu_count : 8; - uint32_t peer_meta_data : 32; -#endif -}; - -#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB 7 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK 0x000000ff - -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB 8 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB 8 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK 0x00000100 - -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB 9 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB 9 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK 0x00000200 - -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB 10 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB 10 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK 0x00000400 - -#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB 11 -#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB 11 -#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK 0x00000800 - -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB 13 -#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB 13 -#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK 0x00002000 - -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_SRC_INFO_LSB 15 -#define RX_MPDU_DESC_INFO_SRC_INFO_MSB 26 -#define RX_MPDU_DESC_INFO_SRC_INFO_MASK 0x07ff8000 - -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB 27 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB 27 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define RX_MPDU_DESC_INFO_TID_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_TID_LSB 28 -#define RX_MPDU_DESC_INFO_TID_MSB 31 -#define RX_MPDU_DESC_INFO_TID_MASK 0xf0000000 - -#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET 0x00000004 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB 0 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB 31 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_details.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_details.h deleted file mode 100644 index d2d96a0a9996..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_details.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_DETAILS_H_ -#define _RX_MPDU_DETAILS_H_ - -#include "rx_mpdu_ext_desc_info.h" -#include "rx_mpdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MPDU_DETAILS 6 - -struct rx_mpdu_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info msdu_link_desc_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_mpdu_ext_desc_info rx_mpdu_ext_desc_info_details; -#else - struct buffer_addr_info msdu_link_desc_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_mpdu_ext_desc_info rx_mpdu_ext_desc_info_details; -#endif -}; - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET 0x00000010 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB 15 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK 0x0000ffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB 16 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB 17 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK 0x00030000 - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB 18 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB 21 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB 22 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_end.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_end.h deleted file mode 100644 index dc54ea129fdd..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_end.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_END_H_ -#define _RX_MPDU_END_H_ - -#define NUM_OF_DWORDS_RX_MPDU_END 4 - -#define NUM_OF_QWORDS_RX_MPDU_END 2 - -struct rx_mpdu_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t reserved_1a : 9, - cfp_mic_err : 1, - cfp_pn_chk_err : 1, - unsup_ktype_short_frame : 1, - rx_in_tx_decrypt_byp : 1, - overflow_err : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - pn_fields_contain_valid_info : 1, - fcs_err : 1, - msdu_length_err : 1, - reserved1c : 6, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - ifcs_present : 1; - uint32_t mpdu_crc_ok_intermediate_fcs : 1, - mpdu_length_intermediate_fcs : 14, - rxpcu_mgmt_sequence_nr_valid : 1, - rxpcu_mgmt_sequence_nr : 16; - uint32_t __reserved_g_0002 : 32; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t ifcs_present : 1, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - reserved1c : 6, - msdu_length_err : 1, - fcs_err : 1, - pn_fields_contain_valid_info : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - overflow_err : 1, - rx_in_tx_decrypt_byp : 1, - unsup_ktype_short_frame : 1, - cfp_pn_chk_err : 1, - cfp_mic_err : 1, - reserved_1a : 9; - uint32_t rxpcu_mgmt_sequence_nr : 16, - rxpcu_mgmt_sequence_nr_valid : 1, - mpdu_length_intermediate_fcs : 14, - mpdu_crc_ok_intermediate_fcs : 1; - uint32_t __reserved_g_0002 : 32; -#endif -}; - -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED_0_LSB 9 -#define RX_MPDU_END_RESERVED_0_MSB 15 -#define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MPDU_END_PHY_PPDU_ID_LSB 16 -#define RX_MPDU_END_PHY_PPDU_ID_MSB 31 -#define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED_1A_LSB 32 -#define RX_MPDU_END_RESERVED_1A_MSB 40 -#define RX_MPDU_END_RESERVED_1A_MASK 0x000001ff00000000 - -#define RX_MPDU_END_CFP_MIC_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_CFP_MIC_ERR_LSB 41 -#define RX_MPDU_END_CFP_MIC_ERR_MSB 41 -#define RX_MPDU_END_CFP_MIC_ERR_MASK 0x0000020000000000 - -#define RX_MPDU_END_CFP_PN_CHK_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_CFP_PN_CHK_ERR_LSB 42 -#define RX_MPDU_END_CFP_PN_CHK_ERR_MSB 42 -#define RX_MPDU_END_CFP_PN_CHK_ERR_MASK 0x0000040000000000 - -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000 - -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000 - -#define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_OVERFLOW_ERR_LSB 45 -#define RX_MPDU_END_OVERFLOW_ERR_MSB 45 -#define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000 - -#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46 -#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46 -#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000 - -#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_TKIP_MIC_ERR_LSB 47 -#define RX_MPDU_END_TKIP_MIC_ERR_MSB 47 -#define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000 - -#define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_DECRYPT_ERR_LSB 48 -#define RX_MPDU_END_DECRYPT_ERR_MSB 48 -#define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000 - -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000 - -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000 - -#define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_FCS_ERR_LSB 51 -#define RX_MPDU_END_FCS_ERR_MSB 51 -#define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000 - -#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52 -#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52 -#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000 - -#define RX_MPDU_END_RESERVED1C_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED1C_LSB 53 -#define RX_MPDU_END_RESERVED1C_MSB 58 -#define RX_MPDU_END_RESERVED1C_MASK 0x07e0000000000000 - -#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000 - -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000 - -#define RX_MPDU_END_IFCS_PRESENT_OFFSET 0x0000000000000000 -#define RX_MPDU_END_IFCS_PRESENT_LSB 63 -#define RX_MPDU_END_IFCS_PRESENT_MSB 63 -#define RX_MPDU_END_IFCS_PRESENT_MASK 0x8000000000000000 - -#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_OFFSET 0x0000000000000008 -#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_LSB 0 -#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_MSB 0 -#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_MASK 0x0000000000000001 - -#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_OFFSET 0x0000000000000008 -#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_LSB 1 -#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_MSB 14 -#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_MASK 0x0000000000007ffe - -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000 - -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_ext_desc_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_ext_desc_info.h deleted file mode 100644 index 83f4df333c88..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_ext_desc_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_EXT_DESC_INFO_H_ -#define _RX_MPDU_EXT_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MPDU_EXT_DESC_INFO 2 - -struct rx_mpdu_ext_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pn_31_0 : 32; - uint32_t pn_47_32 : 16, - pn_127_48_info : 2, - msdu_link_desc_index : 4, - reserved_1a : 10; -#else - uint32_t pn_31_0 : 32; - uint32_t reserved_1a : 10, - msdu_link_desc_index : 4, - pn_127_48_info : 2, - pn_47_32 : 16; -#endif -}; - -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_OFFSET 0x00000000 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_LSB 0 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MSB 31 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_LSB 0 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MSB 15 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MASK 0x0000ffff - -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_LSB 16 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MSB 17 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MASK 0x00030000 - -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_LSB 18 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MSB 21 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_LSB 22 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MSB 31 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_info.h deleted file mode 100644 index 7a3e9a8d525a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_info.h +++ /dev/null @@ -1,972 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_INFO_H_ -#define _RX_MPDU_INFO_H_ - -#include "rxpt_classify_info.h" -#define NUM_OF_DWORDS_RX_MPDU_INFO 30 - -struct rx_mpdu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rxpt_classify_info rxpt_classify_info_details; - uint32_t epd_en : 1, - all_frames_shall_be_encrypted : 1, - encrypt_type : 4, - wep_key_width_for_variable_key : 2, - __reserved_g_0003 : 2, - bssid_hit : 1, - bssid_number : 4, - tid : 4, - reserved_7a : 13; - uint32_t rx_reo_queue_desc_addr_31_0 : 32; - uint32_t rx_reo_queue_desc_addr_39_32 : 8, - receive_queue_number : 16, - pre_delim_err_warning : 1, - first_delim_err : 1, - reserved_2a : 6; - uint32_t pn_31_0 : 32; - uint32_t pn_63_32 : 32; - uint32_t pn_95_64 : 32; - uint32_t pn_127_96 : 32; - uint32_t mpdu_frame_control_valid : 1, - mpdu_duration_valid : 1, - mac_addr_ad1_valid : 1, - mac_addr_ad2_valid : 1, - mac_addr_ad3_valid : 1, - mac_addr_ad4_valid : 1, - mpdu_sequence_control_valid : 1, - mpdu_qos_control_valid : 1, - mpdu_ht_control_valid : 1, - frame_encryption_info_valid : 1, - mpdu_fragment_number : 4, - more_fragment_flag : 1, - protected_cbf_cqi : 1, - fr_ds : 1, - to_ds : 1, - encrypted : 1, - mpdu_retry : 1, - mpdu_sequence_number : 12; - uint32_t peer_meta_data : 32; - uint32_t ast_index : 16, - sw_peer_id : 16; - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - ndp_frame : 1, - phy_err : 1, - phy_err_during_mpdu_header : 1, - protocol_version_err : 1, - ast_based_lookup_valid : 1, - __reserved_g_0022 : 1, - __reserved_g_0035 : 1, - phy_ppdu_id : 16; - uint32_t key_id_octet : 8, - new_peer_entry : 1, - decrypt_needed : 1, - decap_type : 2, - rx_insert_vlan_c_tag_padding : 1, - rx_insert_vlan_s_tag_padding : 1, - strip_vlan_c_tag_decap : 1, - strip_vlan_s_tag_decap : 1, - pre_delim_count : 12, - ampdu_flag : 1, - bar_frame : 1, - raw_mpdu : 1, - reserved_12 : 1; - uint32_t mpdu_length : 14, - first_mpdu : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - fragment_flag : 1, - order : 1, - u_apsd_trigger : 1, - encrypt_required : 1, - directed : 1, - amsdu_present : 1, - reserved_13 : 1; - uint32_t mpdu_frame_control_field : 16, - mpdu_duration_field : 16; - uint32_t mac_addr_ad1_31_0 : 32; - uint32_t mac_addr_ad1_47_32 : 16, - mac_addr_ad2_15_0 : 16; - uint32_t mac_addr_ad2_47_16 : 32; - uint32_t mac_addr_ad3_31_0 : 32; - uint32_t mac_addr_ad3_47_32 : 16, - mpdu_sequence_control_field : 16; - uint32_t mac_addr_ad4_31_0 : 32; - uint32_t mac_addr_ad4_47_32 : 16, - mpdu_qos_control_field : 16; - uint32_t mpdu_ht_control_field : 32; - uint32_t vdev_id : 8, - service_code : 9, - priority_valid : 1, - src_info : 12, - smr_frame : 1, - __reserved_g_0029 : 1; - uint32_t __reserved_g_0060 : 32; - uint32_t __reserved_g_0057 : 16, - __reserved_g_0059 : 16; - uint32_t __reserved_g_0056 : 32; - uint32_t authorized_to_send_wds : 1, - disallow_mcbc_da_in_unicast_mpdu : 1, - fromtods_00_fnf_check_dis : 1, - fromtods_01_fnf_check_dis : 1, - fromtods_10_fnf_check_dis : 1, - fromtods_11_fnf_check_dis : 1, - rx_misc_config : 3, - a_msdu_fromtods_10_ad3 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_11_ad4 : 2, - multi_link_ds_addr_fromtods_00_raw_en : 1, - multi_link_ds_addr_fromtods_non00_raw_en : 1, - multi_link_ds_addr_ad3_valid : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_ad1_trans_dis : 1, - data_fromtods_00_ad3 : 2, - mgmt_fromtods_00_ad3 : 2, - multi_link_ds_addr_mgmt_en : 1, - multi_link_ds_addr_ctrl_en : 1, - reserved_27a : 5; - uint32_t multi_link_ds_addr_ad3_31_0 : 32; - uint32_t multi_link_ds_addr_ad3_47_32 : 16, - cfp_mic_err : 1, - cfp_pn_chk_err : 1, - reserved_29a : 14; -#else - struct rxpt_classify_info rxpt_classify_info_details; - uint32_t reserved_7a : 13, - tid : 4, - bssid_number : 4, - bssid_hit : 1, - __reserved_g_0003 : 2, - wep_key_width_for_variable_key : 2, - encrypt_type : 4, - all_frames_shall_be_encrypted : 1, - epd_en : 1; - uint32_t rx_reo_queue_desc_addr_31_0 : 32; - uint32_t reserved_2a : 6, - first_delim_err : 1, - pre_delim_err_warning : 1, - receive_queue_number : 16, - rx_reo_queue_desc_addr_39_32 : 8; - uint32_t pn_31_0 : 32; - uint32_t pn_63_32 : 32; - uint32_t pn_95_64 : 32; - uint32_t pn_127_96 : 32; - uint32_t mpdu_sequence_number : 12, - mpdu_retry : 1, - encrypted : 1, - to_ds : 1, - fr_ds : 1, - protected_cbf_cqi : 1, - more_fragment_flag : 1, - mpdu_fragment_number : 4, - frame_encryption_info_valid : 1, - mpdu_ht_control_valid : 1, - mpdu_qos_control_valid : 1, - mpdu_sequence_control_valid : 1, - mac_addr_ad4_valid : 1, - mac_addr_ad3_valid : 1, - mac_addr_ad2_valid : 1, - mac_addr_ad1_valid : 1, - mpdu_duration_valid : 1, - mpdu_frame_control_valid : 1; - uint32_t peer_meta_data : 32; - uint32_t sw_peer_id : 16, - ast_index : 16; - uint32_t phy_ppdu_id : 16, - __reserved_g_0035 : 1, - __reserved_g_0022 : 1, - ast_based_lookup_valid : 1, - protocol_version_err : 1, - phy_err_during_mpdu_header : 1, - phy_err : 1, - ndp_frame : 1, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_12 : 1, - raw_mpdu : 1, - bar_frame : 1, - ampdu_flag : 1, - pre_delim_count : 12, - strip_vlan_s_tag_decap : 1, - strip_vlan_c_tag_decap : 1, - rx_insert_vlan_s_tag_padding : 1, - rx_insert_vlan_c_tag_padding : 1, - decap_type : 2, - decrypt_needed : 1, - new_peer_entry : 1, - key_id_octet : 8; - uint32_t reserved_13 : 1, - amsdu_present : 1, - directed : 1, - encrypt_required : 1, - u_apsd_trigger : 1, - order : 1, - fragment_flag : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - first_mpdu : 1, - mpdu_length : 14; - uint32_t mpdu_duration_field : 16, - mpdu_frame_control_field : 16; - uint32_t mac_addr_ad1_31_0 : 32; - uint32_t mac_addr_ad2_15_0 : 16, - mac_addr_ad1_47_32 : 16; - uint32_t mac_addr_ad2_47_16 : 32; - uint32_t mac_addr_ad3_31_0 : 32; - uint32_t mpdu_sequence_control_field : 16, - mac_addr_ad3_47_32 : 16; - uint32_t mac_addr_ad4_31_0 : 32; - uint32_t mpdu_qos_control_field : 16, - mac_addr_ad4_47_32 : 16; - uint32_t mpdu_ht_control_field : 32; - uint32_t __reserved_g_0029 : 1, - smr_frame : 1, - src_info : 12, - priority_valid : 1, - service_code : 9, - vdev_id : 8; - uint32_t __reserved_g_0060 : 32; - uint32_t __reserved_g_0059 : 16, - __reserved_g_0057 : 16; - uint32_t __reserved_g_0056 : 32; - uint32_t reserved_27a : 5, - multi_link_ds_addr_ctrl_en : 1, - multi_link_ds_addr_mgmt_en : 1, - mgmt_fromtods_00_ad3 : 2, - data_fromtods_00_ad3 : 2, - multi_link_addr_ad1_trans_dis : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_ds_addr_ad3_valid : 1, - multi_link_ds_addr_fromtods_non00_raw_en : 1, - multi_link_ds_addr_fromtods_00_raw_en : 1, - a_msdu_fromtods_11_ad4 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_10_ad3 : 2, - rx_misc_config : 3, - fromtods_11_fnf_check_dis : 1, - fromtods_10_fnf_check_dis : 1, - fromtods_01_fnf_check_dis : 1, - fromtods_00_fnf_check_dis : 1, - disallow_mcbc_da_in_unicast_mpdu : 1, - authorized_to_send_wds : 1; - uint32_t multi_link_ds_addr_ad3_31_0 : 32; - uint32_t reserved_29a : 14, - cfp_pn_chk_err : 1, - cfp_mic_err : 1, - multi_link_ds_addr_ad3_47_32 : 16; -#endif -}; - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x00400000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xff800000 - -#define RX_MPDU_INFO_EPD_EN_OFFSET 0x00000004 -#define RX_MPDU_INFO_EPD_EN_LSB 0 -#define RX_MPDU_INFO_EPD_EN_MSB 0 -#define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 - -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x00000004 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 - -#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x00000004 -#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 -#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 -#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c - -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x00000004 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 - -#define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x00000004 -#define RX_MPDU_INFO_BSSID_HIT_LSB 10 -#define RX_MPDU_INFO_BSSID_HIT_MSB 10 -#define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 - -#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x00000004 -#define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 -#define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 -#define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 - -#define RX_MPDU_INFO_TID_OFFSET 0x00000004 -#define RX_MPDU_INFO_TID_LSB 15 -#define RX_MPDU_INFO_TID_MSB 18 -#define RX_MPDU_INFO_TID_MASK 0x00078000 - -#define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x00000004 -#define RX_MPDU_INFO_RESERVED_7A_LSB 19 -#define RX_MPDU_INFO_RESERVED_7A_MSB 31 -#define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 - -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000008 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000c -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 - -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000c -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 - -#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x0000000c -#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 -#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 -#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 - -#define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x0000000c -#define RX_MPDU_INFO_RESERVED_2A_LSB 26 -#define RX_MPDU_INFO_RESERVED_2A_MSB 31 -#define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 - -#define RX_MPDU_INFO_PN_31_0_OFFSET 0x00000010 -#define RX_MPDU_INFO_PN_31_0_LSB 0 -#define RX_MPDU_INFO_PN_31_0_MSB 31 -#define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000014 -#define RX_MPDU_INFO_PN_63_32_LSB 0 -#define RX_MPDU_INFO_PN_63_32_MSB 31 -#define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000018 -#define RX_MPDU_INFO_PN_95_64_LSB 0 -#define RX_MPDU_INFO_PN_95_64_MSB 31 -#define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_127_96_OFFSET 0x0000001c -#define RX_MPDU_INFO_PN_127_96_LSB 0 -#define RX_MPDU_INFO_PN_127_96_MSB 31 -#define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff - -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 - -#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 - -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 - -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 - -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 - -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 - -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 - -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 - -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 - -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 - -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 - -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000020 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_INFO_PROTECTED_CBF_CQI_OFFSET 0x00000020 -#define RX_MPDU_INFO_PROTECTED_CBF_CQI_LSB 15 -#define RX_MPDU_INFO_PROTECTED_CBF_CQI_MSB 15 -#define RX_MPDU_INFO_PROTECTED_CBF_CQI_MASK 0x00008000 - -#define RX_MPDU_INFO_FR_DS_OFFSET 0x00000020 -#define RX_MPDU_INFO_FR_DS_LSB 16 -#define RX_MPDU_INFO_FR_DS_MSB 16 -#define RX_MPDU_INFO_FR_DS_MASK 0x00010000 - -#define RX_MPDU_INFO_TO_DS_OFFSET 0x00000020 -#define RX_MPDU_INFO_TO_DS_LSB 17 -#define RX_MPDU_INFO_TO_DS_MSB 17 -#define RX_MPDU_INFO_TO_DS_MASK 0x00020000 - -#define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x00000020 -#define RX_MPDU_INFO_ENCRYPTED_LSB 18 -#define RX_MPDU_INFO_ENCRYPTED_MSB 18 -#define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 - -#define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_RETRY_LSB 19 -#define RX_MPDU_INFO_MPDU_RETRY_MSB 19 -#define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 - -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 - -#define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000024 -#define RX_MPDU_INFO_PEER_META_DATA_LSB 0 -#define RX_MPDU_INFO_PEER_META_DATA_MSB 31 -#define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff - -#define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 -#define RX_MPDU_INFO_AST_INDEX_LSB 0 -#define RX_MPDU_INFO_AST_INDEX_MSB 15 -#define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff - -#define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 -#define RX_MPDU_INFO_SW_PEER_ID_LSB 16 -#define RX_MPDU_INFO_SW_PEER_ID_MSB 31 -#define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 - -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000002c -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 - -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x0000002c -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc - -#define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x0000002c -#define RX_MPDU_INFO_NDP_FRAME_LSB 9 -#define RX_MPDU_INFO_NDP_FRAME_MSB 9 -#define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 - -#define RX_MPDU_INFO_PHY_ERR_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_ERR_LSB 10 -#define RX_MPDU_INFO_PHY_ERR_MSB 10 -#define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 - -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 - -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x0000002c -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 - -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x0000002c -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 - -#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 -#define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 -#define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 - -#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 -#define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 -#define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 -#define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff - -#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 - -#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 -#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 -#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 -#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 - -#define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 -#define RX_MPDU_INFO_DECAP_TYPE_LSB 10 -#define RX_MPDU_INFO_DECAP_TYPE_MSB 11 -#define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 - -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 - -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 - -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 - -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 - -#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 - -#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 -#define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 -#define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 -#define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 - -#define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 -#define RX_MPDU_INFO_BAR_FRAME_LSB 29 -#define RX_MPDU_INFO_BAR_FRAME_MSB 29 -#define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 - -#define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 -#define RX_MPDU_INFO_RAW_MPDU_LSB 30 -#define RX_MPDU_INFO_RAW_MPDU_MSB 30 -#define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 - -#define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 -#define RX_MPDU_INFO_RESERVED_12_LSB 31 -#define RX_MPDU_INFO_RESERVED_12_MSB 31 -#define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 - -#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 -#define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 -#define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 -#define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff - -#define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 -#define RX_MPDU_INFO_FIRST_MPDU_LSB 14 -#define RX_MPDU_INFO_FIRST_MPDU_MSB 14 -#define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 - -#define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 -#define RX_MPDU_INFO_MCAST_BCAST_LSB 15 -#define RX_MPDU_INFO_MCAST_BCAST_MSB 15 -#define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 - -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 - -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 - -#define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 -#define RX_MPDU_INFO_POWER_MGMT_LSB 18 -#define RX_MPDU_INFO_POWER_MGMT_MSB 18 -#define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 - -#define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 -#define RX_MPDU_INFO_NON_QOS_LSB 19 -#define RX_MPDU_INFO_NON_QOS_MSB 19 -#define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 - -#define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 -#define RX_MPDU_INFO_NULL_DATA_LSB 20 -#define RX_MPDU_INFO_NULL_DATA_MSB 20 -#define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 - -#define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 -#define RX_MPDU_INFO_MGMT_TYPE_LSB 21 -#define RX_MPDU_INFO_MGMT_TYPE_MSB 21 -#define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 - -#define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 -#define RX_MPDU_INFO_CTRL_TYPE_LSB 22 -#define RX_MPDU_INFO_CTRL_TYPE_MSB 22 -#define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 - -#define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 -#define RX_MPDU_INFO_MORE_DATA_LSB 23 -#define RX_MPDU_INFO_MORE_DATA_MSB 23 -#define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 - -#define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 -#define RX_MPDU_INFO_EOSP_LSB 24 -#define RX_MPDU_INFO_EOSP_MSB 24 -#define RX_MPDU_INFO_EOSP_MASK 0x01000000 - -#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 -#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 -#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 -#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 - -#define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 -#define RX_MPDU_INFO_ORDER_LSB 26 -#define RX_MPDU_INFO_ORDER_MSB 26 -#define RX_MPDU_INFO_ORDER_MASK 0x04000000 - -#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 -#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 -#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 -#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 - -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 - -#define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 -#define RX_MPDU_INFO_DIRECTED_LSB 29 -#define RX_MPDU_INFO_DIRECTED_MSB 29 -#define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 - -#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 -#define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 -#define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 -#define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 - -#define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 -#define RX_MPDU_INFO_RESERVED_13_LSB 31 -#define RX_MPDU_INFO_RESERVED_13_MSB 31 -#define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 - -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff - -#define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c -#define RX_MPDU_INFO_VDEV_ID_LSB 0 -#define RX_MPDU_INFO_VDEV_ID_MSB 7 -#define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff - -#define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c -#define RX_MPDU_INFO_SERVICE_CODE_LSB 8 -#define RX_MPDU_INFO_SERVICE_CODE_MSB 16 -#define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 - -#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c -#define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 -#define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 -#define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 - -#define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c -#define RX_MPDU_INFO_SRC_INFO_LSB 18 -#define RX_MPDU_INFO_SRC_INFO_MSB 29 -#define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 - -#define RX_MPDU_INFO_SMR_FRAME_OFFSET 0x0000005c -#define RX_MPDU_INFO_SMR_FRAME_LSB 30 -#define RX_MPDU_INFO_SMR_FRAME_MSB 30 -#define RX_MPDU_INFO_SMR_FRAME_MASK 0x40000000 - -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 - -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET 0x0000006c -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB 1 -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB 1 -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK 0x00000002 - -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_LSB 2 -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MSB 2 -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MASK 0x00000004 - -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_LSB 3 -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MSB 3 -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MASK 0x00000008 - -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_LSB 4 -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MSB 4 -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MASK 0x00000010 - -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_LSB 5 -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MSB 5 -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MASK 0x00000020 - -#define RX_MPDU_INFO_RX_MISC_CONFIG_OFFSET 0x0000006c -#define RX_MPDU_INFO_RX_MISC_CONFIG_LSB 6 -#define RX_MPDU_INFO_RX_MISC_CONFIG_MSB 8 -#define RX_MPDU_INFO_RX_MISC_CONFIG_MASK 0x000001c0 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_LSB 9 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MSB 10 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MASK 0x00000600 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_LSB 11 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MSB 12 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MASK 0x00001800 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_LSB 13 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MSB 14 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MASK 0x00006000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_LSB 15 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MSB 15 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MASK 0x00008000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_LSB 16 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MSB 16 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MASK 0x00010000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_LSB 17 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_MSB 17 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_MASK 0x00020000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 18 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 18 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x00040000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 19 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 19 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x00080000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 20 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 20 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x00100000 - -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_LSB 21 -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MSB 22 -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MASK 0x00600000 - -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_LSB 23 -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MSB 24 -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MASK 0x01800000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_LSB 25 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_MSB 25 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_MASK 0x02000000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_LSB 26 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_MSB 26 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_MASK 0x04000000 - -#define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c -#define RX_MPDU_INFO_RESERVED_27A_LSB 27 -#define RX_MPDU_INFO_RESERVED_27A_MSB 31 -#define RX_MPDU_INFO_RESERVED_27A_MASK 0xf8000000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_OFFSET 0x00000070 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_OFFSET 0x00000074 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_LSB 0 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_MSB 15 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_CFP_MIC_ERR_OFFSET 0x00000074 -#define RX_MPDU_INFO_CFP_MIC_ERR_LSB 16 -#define RX_MPDU_INFO_CFP_MIC_ERR_MSB 16 -#define RX_MPDU_INFO_CFP_MIC_ERR_MASK 0x00010000 - -#define RX_MPDU_INFO_CFP_PN_CHK_ERR_OFFSET 0x00000074 -#define RX_MPDU_INFO_CFP_PN_CHK_ERR_LSB 17 -#define RX_MPDU_INFO_CFP_PN_CHK_ERR_MSB 17 -#define RX_MPDU_INFO_CFP_PN_CHK_ERR_MASK 0x00020000 - -#define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 -#define RX_MPDU_INFO_RESERVED_29A_LSB 18 -#define RX_MPDU_INFO_RESERVED_29A_MSB 31 -#define RX_MPDU_INFO_RESERVED_29A_MASK 0xfffc0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_link_ptr.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_link_ptr.h deleted file mode 100644 index e9d7e83a92cc..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_link_ptr.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_LINK_PTR_H_ -#define _RX_MPDU_LINK_PTR_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 - -struct rx_mpdu_link_ptr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info mpdu_link_desc_addr_info; -#else - struct buffer_addr_info mpdu_link_desc_addr_info; -#endif -}; - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_start.h b/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_start.h deleted file mode 100644 index fc5029dc2da3..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_mpdu_start.h +++ /dev/null @@ -1,712 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_START_H_ -#define _RX_MPDU_START_H_ - -#include "rx_mpdu_info.h" -#define NUM_OF_DWORDS_RX_MPDU_START 30 - -#define NUM_OF_QWORDS_RX_MPDU_START 15 - -struct rx_mpdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_mpdu_info rx_mpdu_info_details; -#else - struct rx_mpdu_info rx_mpdu_info_details; -#endif -}; - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x000000000000001f - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x0000000000000060 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x0000000000000080 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x0000000000000400 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x0000000000003800 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x000000000001c000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x0000000000020000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x0000000000040000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x0000000000080000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x0000000000100000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x0000000000200000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x0000000000400000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0x00000000ff800000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x0000000100000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x0000000200000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 38 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x0000040000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x0000780000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK 0x0007800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff8000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff0000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x0100000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc00000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000000000010 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x0000000000000010 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x0000000000000018 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000000000000018 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x0000000000000001 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB 1 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x0000000000000002 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB 2 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x0000000000000004 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB 3 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x0000000000000008 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x0000000000000010 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x0000000000000020 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x0000000000000040 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x0000000000000080 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x0000000000003c00 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x0000000000004000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_LSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_MASK 0x0000000000008000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x0000000000010000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x0000000000020000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x0000000000040000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x0000000000080000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x00000000fff00000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000300000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x0000020000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x0000040000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x0000080000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x0000100000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x0000200000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x00000000000000ff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB 11 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x0000000000000c00 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x0000000000001000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x0000000000002000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x0000000000004000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x0000000000008000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB 27 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x000000000fff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB 28 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x0000000010000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB 29 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x0000000020000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB 30 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x0000000040000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x0000000080000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x0000400000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x0000800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x0001000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x0004000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x0008000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x0010000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x0020000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x0040000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x0080000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x0100000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x0400000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x0800000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 60 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB 60 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x1000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x2000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x4000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x8000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK 0x000000ff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK 0x0001ff0000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK 0x3ffc000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_LSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_MSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_MASK 0x4000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK 0x0000000100000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK 0x0000000200000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MASK 0x0000000400000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_LSB 35 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MSB 35 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MASK 0x0000000800000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_LSB 36 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MSB 36 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MASK 0x0000001000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_LSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MASK 0x0000002000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_LSB 38 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MASK 0x000001c000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_LSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MASK 0x0000060000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MASK 0x0000180000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_LSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MASK 0x0000600000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MASK 0x0000800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MASK 0x0001000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x0004000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x0008000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x0010000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_LSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MASK 0x0060000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_LSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MASK 0x0180000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_MSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_MASK 0x0400000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK 0xf800000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_MASK 0x0001000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK 0xfffc000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_desc_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_desc_info.h deleted file mode 100644 index 88569b653b64..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_desc_info.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_DESC_INFO_H_ -#define _RX_MSDU_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 - -struct rx_msdu_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t first_msdu_in_mpdu_flag : 1, - last_msdu_in_mpdu_flag : 1, - msdu_continuation : 1, - msdu_length : 14, - msdu_drop : 1, - sa_is_valid : 1, - da_is_valid : 1, - da_is_mcbc : 1, - l3_header_padding_msb : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - fr_ds : 1, - to_ds : 1, - intra_bss : 1, - dest_chip_id : 2, - decap_format : 2, - __reserved_g_0015 : 1; -#else - uint32_t __reserved_g_0015 : 1, - decap_format : 2, - dest_chip_id : 2, - intra_bss : 1, - to_ds : 1, - fr_ds : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - l3_header_padding_msb : 1, - da_is_mcbc : 1, - da_is_valid : 1, - sa_is_valid : 1, - msdu_drop : 1, - msdu_length : 14, - msdu_continuation : 1, - last_msdu_in_mpdu_flag : 1, - first_msdu_in_mpdu_flag : 1; -#endif -}; - -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 -#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 -#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_FR_DS_LSB 24 -#define RX_MSDU_DESC_INFO_FR_DS_MSB 24 -#define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 - -#define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_TO_DS_LSB 25 -#define RX_MSDU_DESC_INFO_TO_DS_MSB 25 -#define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 - -#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 -#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 -#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_details.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_details.h deleted file mode 100644 index 0b763a473ce6..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_details.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_DETAILS_H_ -#define _RX_MSDU_DETAILS_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_msdu_ext_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 - -struct rx_msdu_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buffer_addr_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; -#else - struct buffer_addr_info buffer_addr_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; -#endif -}; - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xe0000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_end.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_end.h deleted file mode 100644 index b05c9896b09a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_end.h +++ /dev/null @@ -1,1094 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_END_H_ -#define _RX_MSDU_END_H_ - -#define NUM_OF_DWORDS_RX_MSDU_END 32 - -#define NUM_OF_QWORDS_RX_MSDU_END 16 - -struct rx_msdu_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t ip_hdr_chksum : 16, - reported_mpdu_length : 14, - reserved_1a : 2; - uint32_t reserved_2a : 8, - cce_super_rule : 6, - cce_classify_not_done_truncate : 1, - cce_classify_not_done_cce_dis : 1, - cumulative_l3_checksum : 16; - uint32_t rule_indication_31_0 : 32; - uint32_t ipv6_options_crc : 32; - uint32_t da_offset : 6, - sa_offset : 6, - da_offset_valid : 1, - sa_offset_valid : 1, - reserved_5a : 2, - l3_type : 16; - uint32_t rule_indication_63_32 : 32; - uint32_t tcp_seq_number : 32; - uint32_t tcp_ack_number : 32; - uint32_t tcp_flag : 9, - lro_eligible : 1, - reserved_9a : 6, - window_size : 16; - uint32_t sa_sw_peer_id : 16, - sa_idx_timeout : 1, - da_idx_timeout : 1, - to_ds : 1, - tid : 4, - sa_is_valid : 1, - da_is_valid : 1, - da_is_mcbc : 1, - l3_header_padding : 2, - first_msdu : 1, - last_msdu : 1, - fr_ds : 1, - ip_chksum_fail_copy : 1; - uint32_t sa_idx : 16, - da_idx_or_sw_peer_id : 16; - uint32_t msdu_drop : 1, - reo_destination_indication : 5, - flow_idx : 20, - use_ppe : 1, - __reserved_g_0003 : 2, - vlan_ctag_stripped : 1, - vlan_stag_stripped : 1, - fragment_flag : 1; - uint32_t fse_metadata : 32; - uint32_t cce_metadata : 16, - tcp_udp_chksum : 16; - uint32_t aggregation_count : 8, - flow_aggregation_continuation : 1, - fisa_timeout : 1, - tcp_udp_chksum_fail_copy : 1, - msdu_limit_error : 1, - flow_idx_timeout : 1, - flow_idx_invalid : 1, - cce_match : 1, - amsdu_parser_error : 1, - cumulative_ip_length : 16; - uint32_t key_id_octet : 8, - reserved_16a : 24; - uint32_t reserved_17a : 6, - service_code : 9, - priority_valid : 1, - intra_bss : 1, - dest_chip_id : 2, - multicast_echo : 1, - wds_learning_event : 1, - wds_roaming_event : 1, - wds_keep_alive_event : 1, - __reserved_g_0015 : 1, - reserved_17b : 8; - uint32_t msdu_length : 14, - stbc : 1, - ipsec_esp : 1, - l3_offset : 7, - ipsec_ah : 1, - l4_offset : 8; - uint32_t msdu_number : 8, - decap_format : 2, - ipv4_proto : 1, - ipv6_proto : 1, - tcp_proto : 1, - udp_proto : 1, - ip_frag : 1, - tcp_only_ack : 1, - da_is_bcast_mcast : 1, - toeplitz_hash_sel : 2, - ip_fixed_header_valid : 1, - ip_extn_header_valid : 1, - tcp_udp_header_valid : 1, - mesh_control_present : 1, - ldpc : 1, - ip4_protocol_ip6_next_header : 8; - uint32_t vlan_ctag_ci : 16, - vlan_stag_ci : 16; - uint32_t peer_meta_data : 32; - uint32_t user_rssi : 8, - pkt_type : 4, - sgi : 2, - rate_mcs : 5, - receive_bandwidth : 3, - reception_type : 3, - mimo_ss_bitmap : 6, - msdu_done_copy : 1; - uint32_t flow_id_toeplitz : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t reserved_28a : 16, - sa_15_0 : 16; - uint32_t sa_47_16 : 32; - uint32_t first_mpdu : 1, - reserved_30a : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - a_msdu_error : 1, - reserved_30b : 1, - order : 1, - wifi_parser_error : 1, - overflow_err : 1, - msdu_length_err : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - sa_idx_invalid : 1, - da_idx_invalid : 1, - amsdu_addr_mismatch : 1, - rx_in_tx_decrypt_byp : 1, - encrypt_required : 1, - directed : 1, - buffer_fragment : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - fcs_err : 1; - uint32_t reserved_31a : 10, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - ifcs_present : 1, - reserved_31b : 16, - msdu_done : 1; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_1a : 2, - reported_mpdu_length : 14, - ip_hdr_chksum : 16; - uint32_t cumulative_l3_checksum : 16, - cce_classify_not_done_cce_dis : 1, - cce_classify_not_done_truncate : 1, - cce_super_rule : 6, - reserved_2a : 8; - uint32_t rule_indication_31_0 : 32; - uint32_t ipv6_options_crc : 32; - uint32_t l3_type : 16, - reserved_5a : 2, - sa_offset_valid : 1, - da_offset_valid : 1, - sa_offset : 6, - da_offset : 6; - uint32_t rule_indication_63_32 : 32; - uint32_t tcp_seq_number : 32; - uint32_t tcp_ack_number : 32; - uint32_t window_size : 16, - reserved_9a : 6, - lro_eligible : 1, - tcp_flag : 9; - uint32_t ip_chksum_fail_copy : 1, - fr_ds : 1, - last_msdu : 1, - first_msdu : 1, - l3_header_padding : 2, - da_is_mcbc : 1, - da_is_valid : 1, - sa_is_valid : 1, - tid : 4, - to_ds : 1, - da_idx_timeout : 1, - sa_idx_timeout : 1, - sa_sw_peer_id : 16; - uint32_t da_idx_or_sw_peer_id : 16, - sa_idx : 16; - uint32_t fragment_flag : 1, - vlan_stag_stripped : 1, - vlan_ctag_stripped : 1, - __reserved_g_0003 : 2, - use_ppe : 1, - flow_idx : 20, - reo_destination_indication : 5, - msdu_drop : 1; - uint32_t fse_metadata : 32; - uint32_t tcp_udp_chksum : 16, - cce_metadata : 16; - uint32_t cumulative_ip_length : 16, - amsdu_parser_error : 1, - cce_match : 1, - flow_idx_invalid : 1, - flow_idx_timeout : 1, - msdu_limit_error : 1, - tcp_udp_chksum_fail_copy : 1, - fisa_timeout : 1, - flow_aggregation_continuation : 1, - aggregation_count : 8; - uint32_t reserved_16a : 24, - key_id_octet : 8; - uint32_t reserved_17b : 8, - __reserved_g_0015 : 1, - wds_keep_alive_event : 1, - wds_roaming_event : 1, - wds_learning_event : 1, - multicast_echo : 1, - dest_chip_id : 2, - intra_bss : 1, - priority_valid : 1, - service_code : 9, - reserved_17a : 6; - uint32_t l4_offset : 8, - ipsec_ah : 1, - l3_offset : 7, - ipsec_esp : 1, - stbc : 1, - msdu_length : 14; - uint32_t ip4_protocol_ip6_next_header : 8, - ldpc : 1, - mesh_control_present : 1, - tcp_udp_header_valid : 1, - ip_extn_header_valid : 1, - ip_fixed_header_valid : 1, - toeplitz_hash_sel : 2, - da_is_bcast_mcast : 1, - tcp_only_ack : 1, - ip_frag : 1, - udp_proto : 1, - tcp_proto : 1, - ipv6_proto : 1, - ipv4_proto : 1, - decap_format : 2, - msdu_number : 8; - uint32_t vlan_stag_ci : 16, - vlan_ctag_ci : 16; - uint32_t peer_meta_data : 32; - uint32_t msdu_done_copy : 1, - mimo_ss_bitmap : 6, - reception_type : 3, - receive_bandwidth : 3, - rate_mcs : 5, - sgi : 2, - pkt_type : 4, - user_rssi : 8; - uint32_t flow_id_toeplitz : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t sa_15_0 : 16, - reserved_28a : 16; - uint32_t sa_47_16 : 32; - uint32_t fcs_err : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - buffer_fragment : 1, - directed : 1, - encrypt_required : 1, - rx_in_tx_decrypt_byp : 1, - amsdu_addr_mismatch : 1, - da_idx_invalid : 1, - sa_idx_invalid : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - msdu_length_err : 1, - overflow_err : 1, - wifi_parser_error : 1, - order : 1, - reserved_30b : 1, - a_msdu_error : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - reserved_30a : 1, - first_mpdu : 1; - uint32_t msdu_done : 1, - reserved_31b : 16, - ifcs_present : 1, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - reserved_31a : 10; -#endif -}; - -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RESERVED_0_LSB 9 -#define RX_MSDU_END_RESERVED_0_MSB 15 -#define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_END_PHY_PPDU_ID_LSB 16 -#define RX_MSDU_END_PHY_PPDU_ID_MSB 31 -#define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000 -#define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32 -#define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47 -#define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000 - -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000 - -#define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RESERVED_1A_LSB 62 -#define RX_MSDU_END_RESERVED_1A_MSB 63 -#define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000 - -#define RX_MSDU_END_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_MSDU_END_RESERVED_2A_LSB 0 -#define RX_MSDU_END_RESERVED_2A_MSB 7 -#define RX_MSDU_END_RESERVED_2A_MASK 0x00000000000000ff - -#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 -#define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 -#define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00 - -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000 - -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000 - -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008 -#define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32 -#define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63 -#define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000 - -#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000010 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff - -#define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010 -#define RX_MSDU_END_DA_OFFSET_LSB 32 -#define RX_MSDU_END_DA_OFFSET_MSB 37 -#define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000 - -#define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010 -#define RX_MSDU_END_SA_OFFSET_LSB 38 -#define RX_MSDU_END_SA_OFFSET_MSB 43 -#define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000 - -#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010 -#define RX_MSDU_END_DA_OFFSET_VALID_LSB 44 -#define RX_MSDU_END_DA_OFFSET_VALID_MSB 44 -#define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000 - -#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010 -#define RX_MSDU_END_SA_OFFSET_VALID_LSB 45 -#define RX_MSDU_END_SA_OFFSET_VALID_MSB 45 -#define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000 - -#define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010 -#define RX_MSDU_END_RESERVED_5A_LSB 46 -#define RX_MSDU_END_RESERVED_5A_MSB 47 -#define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000 - -#define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_END_L3_TYPE_LSB 48 -#define RX_MSDU_END_L3_TYPE_MSB 63 -#define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000 - -#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000018 -#define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 -#define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 -#define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32 -#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63 -#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 - -#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020 -#define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 -#define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 -#define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020 -#define RX_MSDU_END_TCP_FLAG_LSB 32 -#define RX_MSDU_END_TCP_FLAG_MSB 40 -#define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000 - -#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020 -#define RX_MSDU_END_LRO_ELIGIBLE_LSB 41 -#define RX_MSDU_END_LRO_ELIGIBLE_MSB 41 -#define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000 - -#define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020 -#define RX_MSDU_END_RESERVED_9A_LSB 42 -#define RX_MSDU_END_RESERVED_9A_MSB 47 -#define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000 - -#define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020 -#define RX_MSDU_END_WINDOW_SIZE_LSB 48 -#define RX_MSDU_END_WINDOW_SIZE_MSB 63 -#define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000 - -#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 -#define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 -#define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x000000000000ffff - -#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 -#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 -#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000 - -#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 -#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 -#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000 - -#define RX_MSDU_END_TO_DS_OFFSET 0x0000000000000028 -#define RX_MSDU_END_TO_DS_LSB 18 -#define RX_MSDU_END_TO_DS_MSB 18 -#define RX_MSDU_END_TO_DS_MASK 0x0000000000040000 - -#define RX_MSDU_END_TID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_TID_LSB 19 -#define RX_MSDU_END_TID_MSB 22 -#define RX_MSDU_END_TID_MASK 0x0000000000780000 - -#define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IS_VALID_LSB 23 -#define RX_MSDU_END_SA_IS_VALID_MSB 23 -#define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000 - -#define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IS_VALID_LSB 24 -#define RX_MSDU_END_DA_IS_VALID_MSB 24 -#define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000 - -#define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IS_MCBC_LSB 25 -#define RX_MSDU_END_DA_IS_MCBC_MSB 25 -#define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000 - -#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028 -#define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 -#define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 -#define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000 - -#define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028 -#define RX_MSDU_END_FIRST_MSDU_LSB 28 -#define RX_MSDU_END_FIRST_MSDU_MSB 28 -#define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000 - -#define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028 -#define RX_MSDU_END_LAST_MSDU_LSB 29 -#define RX_MSDU_END_LAST_MSDU_MSB 29 -#define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000 - -#define RX_MSDU_END_FR_DS_OFFSET 0x0000000000000028 -#define RX_MSDU_END_FR_DS_LSB 30 -#define RX_MSDU_END_FR_DS_MSB 30 -#define RX_MSDU_END_FR_DS_MASK 0x0000000040000000 - -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000 - -#define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IDX_LSB 32 -#define RX_MSDU_END_SA_IDX_MSB 47 -#define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000 - -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000 - -#define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030 -#define RX_MSDU_END_MSDU_DROP_LSB 0 -#define RX_MSDU_END_MSDU_DROP_MSB 0 -#define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001 - -#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e - -#define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FLOW_IDX_LSB 6 -#define RX_MSDU_END_FLOW_IDX_MSB 25 -#define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0 - -#define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030 -#define RX_MSDU_END_USE_PPE_LSB 26 -#define RX_MSDU_END_USE_PPE_MSB 26 -#define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000 - -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x0000000000000030 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x0000000020000000 - -#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x0000000000000030 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x0000000040000000 - -#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 -#define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 -#define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000080000000 - -#define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FSE_METADATA_LSB 32 -#define RX_MSDU_END_FSE_METADATA_MSB 63 -#define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CCE_METADATA_LSB 0 -#define RX_MSDU_END_CCE_METADATA_MSB 15 -#define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff - -#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000038 -#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 -#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 -#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_AGGREGATION_COUNT_LSB 32 -#define RX_MSDU_END_AGGREGATION_COUNT_MSB 39 -#define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000 - -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000 - -#define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FISA_TIMEOUT_LSB 41 -#define RX_MSDU_END_FISA_TIMEOUT_MSB 41 -#define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000 - -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000038 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 42 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 42 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000040000000000 - -#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000038 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 43 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 43 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000080000000000 - -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 44 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 44 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000100000000000 - -#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_IDX_INVALID_LSB 45 -#define RX_MSDU_END_FLOW_IDX_INVALID_MSB 45 -#define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000200000000000 - -#define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CCE_MATCH_LSB 46 -#define RX_MSDU_END_CCE_MATCH_MSB 46 -#define RX_MSDU_END_CCE_MATCH_MASK 0x0000400000000000 - -#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000038 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 47 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 47 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000800000000000 - -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 48 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 63 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff000000000000 - -#define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000040 -#define RX_MSDU_END_KEY_ID_OCTET_LSB 0 -#define RX_MSDU_END_KEY_ID_OCTET_MSB 7 -#define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff - -#define RX_MSDU_END_RESERVED_16A_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_16A_LSB 8 -#define RX_MSDU_END_RESERVED_16A_MSB 31 -#define RX_MSDU_END_RESERVED_16A_MASK 0x00000000ffffff00 - -#define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_17A_LSB 32 -#define RX_MSDU_END_RESERVED_17A_MSB 37 -#define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000 - -#define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040 -#define RX_MSDU_END_SERVICE_CODE_LSB 38 -#define RX_MSDU_END_SERVICE_CODE_MSB 46 -#define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000 - -#define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040 -#define RX_MSDU_END_PRIORITY_VALID_LSB 47 -#define RX_MSDU_END_PRIORITY_VALID_MSB 47 -#define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000 - -#define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040 -#define RX_MSDU_END_INTRA_BSS_LSB 48 -#define RX_MSDU_END_INTRA_BSS_MSB 48 -#define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000 - -#define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040 -#define RX_MSDU_END_DEST_CHIP_ID_LSB 49 -#define RX_MSDU_END_DEST_CHIP_ID_MSB 50 -#define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000 - -#define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040 -#define RX_MSDU_END_MULTICAST_ECHO_LSB 51 -#define RX_MSDU_END_MULTICAST_ECHO_MSB 51 -#define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000 - -#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52 -#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52 -#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000 - -#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53 -#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53 -#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000 - -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000 - -#define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_17B_LSB 56 -#define RX_MSDU_END_RESERVED_17B_MSB 63 -#define RX_MSDU_END_RESERVED_17B_MASK 0xff00000000000000 - -#define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MSDU_LENGTH_LSB 0 -#define RX_MSDU_END_MSDU_LENGTH_MSB 13 -#define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff - -#define RX_MSDU_END_STBC_OFFSET 0x0000000000000048 -#define RX_MSDU_END_STBC_LSB 14 -#define RX_MSDU_END_STBC_MSB 14 -#define RX_MSDU_END_STBC_MASK 0x0000000000004000 - -#define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPSEC_ESP_LSB 15 -#define RX_MSDU_END_IPSEC_ESP_MSB 15 -#define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000 - -#define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048 -#define RX_MSDU_END_L3_OFFSET_LSB 16 -#define RX_MSDU_END_L3_OFFSET_MSB 22 -#define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000 - -#define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPSEC_AH_LSB 23 -#define RX_MSDU_END_IPSEC_AH_MSB 23 -#define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000 - -#define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048 -#define RX_MSDU_END_L4_OFFSET_LSB 24 -#define RX_MSDU_END_L4_OFFSET_MSB 31 -#define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000 - -#define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MSDU_NUMBER_LSB 32 -#define RX_MSDU_END_MSDU_NUMBER_MSB 39 -#define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000 - -#define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048 -#define RX_MSDU_END_DECAP_FORMAT_LSB 40 -#define RX_MSDU_END_DECAP_FORMAT_MSB 41 -#define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000 - -#define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPV4_PROTO_LSB 42 -#define RX_MSDU_END_IPV4_PROTO_MSB 42 -#define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000 - -#define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPV6_PROTO_LSB 43 -#define RX_MSDU_END_IPV6_PROTO_MSB 43 -#define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000 - -#define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_PROTO_LSB 44 -#define RX_MSDU_END_TCP_PROTO_MSB 44 -#define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000 - -#define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_UDP_PROTO_LSB 45 -#define RX_MSDU_END_UDP_PROTO_MSB 45 -#define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000 - -#define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_FRAG_LSB 46 -#define RX_MSDU_END_IP_FRAG_MSB 46 -#define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000 - -#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_ONLY_ACK_LSB 47 -#define RX_MSDU_END_TCP_ONLY_ACK_MSB 47 -#define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000 - -#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000 - -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000 - -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000 - -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000 - -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000 - -#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000 - -#define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048 -#define RX_MSDU_END_LDPC_LSB 55 -#define RX_MSDU_END_LDPC_MSB 55 -#define RX_MSDU_END_LDPC_MASK 0x0080000000000000 - -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000 - -#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000050 -#define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 -#define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 -#define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff - -#define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000050 -#define RX_MSDU_END_VLAN_STAG_CI_LSB 16 -#define RX_MSDU_END_VLAN_STAG_CI_MSB 31 -#define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_PEER_META_DATA_OFFSET 0x0000000000000050 -#define RX_MSDU_END_PEER_META_DATA_LSB 32 -#define RX_MSDU_END_PEER_META_DATA_MSB 63 -#define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058 -#define RX_MSDU_END_USER_RSSI_LSB 0 -#define RX_MSDU_END_USER_RSSI_MSB 7 -#define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff - -#define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058 -#define RX_MSDU_END_PKT_TYPE_LSB 8 -#define RX_MSDU_END_PKT_TYPE_MSB 11 -#define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00 - -#define RX_MSDU_END_SGI_OFFSET 0x0000000000000058 -#define RX_MSDU_END_SGI_LSB 12 -#define RX_MSDU_END_SGI_MSB 13 -#define RX_MSDU_END_SGI_MASK 0x0000000000003000 - -#define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RATE_MCS_LSB 14 -#define RX_MSDU_END_RATE_MCS_MSB 18 -#define RX_MSDU_END_RATE_MCS_MASK 0x000000000007c000 - -#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 19 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 21 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x0000000000380000 - -#define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RECEPTION_TYPE_LSB 22 -#define RX_MSDU_END_RECEPTION_TYPE_MSB 24 -#define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000001c00000 - -#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058 -#define RX_MSDU_END_MIMO_SS_BITMAP_LSB 25 -#define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 -#define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x000000007e000000 - -#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x0000000000000058 -#define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 -#define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 -#define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x0000000080000000 - -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000058 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000 - -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff - -#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060 -#define RX_MSDU_END_SW_PHY_META_DATA_LSB 32 -#define RX_MSDU_END_SW_PHY_META_DATA_MSB 63 -#define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000068 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000068 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 32 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 63 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 - -#define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070 -#define RX_MSDU_END_RESERVED_28A_LSB 0 -#define RX_MSDU_END_RESERVED_28A_MSB 15 -#define RX_MSDU_END_RESERVED_28A_MASK 0x000000000000ffff - -#define RX_MSDU_END_SA_15_0_OFFSET 0x0000000000000070 -#define RX_MSDU_END_SA_15_0_LSB 16 -#define RX_MSDU_END_SA_15_0_MSB 31 -#define RX_MSDU_END_SA_15_0_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_SA_47_16_OFFSET 0x0000000000000070 -#define RX_MSDU_END_SA_47_16_LSB 32 -#define RX_MSDU_END_SA_47_16_MSB 63 -#define RX_MSDU_END_SA_47_16_MASK 0xffffffff00000000 - -#define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078 -#define RX_MSDU_END_FIRST_MPDU_LSB 0 -#define RX_MSDU_END_FIRST_MPDU_MSB 0 -#define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001 - -#define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_30A_LSB 1 -#define RX_MSDU_END_RESERVED_30A_MSB 1 -#define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002 - -#define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MCAST_BCAST_LSB 2 -#define RX_MSDU_END_MCAST_BCAST_MSB 2 -#define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004 - -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008 - -#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010 - -#define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_POWER_MGMT_LSB 5 -#define RX_MSDU_END_POWER_MGMT_MSB 5 -#define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020 - -#define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078 -#define RX_MSDU_END_NON_QOS_LSB 6 -#define RX_MSDU_END_NON_QOS_MSB 6 -#define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040 - -#define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078 -#define RX_MSDU_END_NULL_DATA_LSB 7 -#define RX_MSDU_END_NULL_DATA_MSB 7 -#define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080 - -#define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MGMT_TYPE_LSB 8 -#define RX_MSDU_END_MGMT_TYPE_MSB 8 -#define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100 - -#define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_CTRL_TYPE_LSB 9 -#define RX_MSDU_END_CTRL_TYPE_MSB 9 -#define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200 - -#define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MORE_DATA_LSB 10 -#define RX_MSDU_END_MORE_DATA_MSB 10 -#define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400 - -#define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078 -#define RX_MSDU_END_EOSP_LSB 11 -#define RX_MSDU_END_EOSP_MSB 11 -#define RX_MSDU_END_EOSP_MASK 0x0000000000000800 - -#define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_A_MSDU_ERROR_LSB 12 -#define RX_MSDU_END_A_MSDU_ERROR_MSB 12 -#define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000 - -#define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_30B_LSB 13 -#define RX_MSDU_END_RESERVED_30B_MSB 13 -#define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000002000 - -#define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078 -#define RX_MSDU_END_ORDER_LSB 14 -#define RX_MSDU_END_ORDER_MSB 14 -#define RX_MSDU_END_ORDER_MASK 0x0000000000004000 - -#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 -#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 -#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000008000 - -#define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_OVERFLOW_ERR_LSB 16 -#define RX_MSDU_END_OVERFLOW_ERR_MSB 16 -#define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000 - -#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 -#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 -#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000 - -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000 - -#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078 -#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 -#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 -#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000 - -#define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078 -#define RX_MSDU_END_SA_IDX_INVALID_LSB 20 -#define RX_MSDU_END_SA_IDX_INVALID_MSB 20 -#define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000 - -#define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DA_IDX_INVALID_LSB 21 -#define RX_MSDU_END_DA_IDX_INVALID_MSB 21 -#define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000 - -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x0000000000400000 - -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000 - -#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 -#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 -#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000 - -#define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DIRECTED_LSB 25 -#define RX_MSDU_END_DIRECTED_MSB 25 -#define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000 - -#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 -#define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 -#define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000 - -#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 -#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 -#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000 - -#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 -#define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 -#define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000 - -#define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DECRYPT_ERR_LSB 29 -#define RX_MSDU_END_DECRYPT_ERR_MSB 29 -#define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000 - -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000 - -#define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_FCS_ERR_LSB 31 -#define RX_MSDU_END_FCS_ERR_MSB 31 -#define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000 - -#define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_31A_LSB 32 -#define RX_MSDU_END_RESERVED_31A_MSB 41 -#define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000 - -#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000 - -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000 - -#define RX_MSDU_END_IFCS_PRESENT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_IFCS_PRESENT_LSB 46 -#define RX_MSDU_END_IFCS_PRESENT_MSB 46 -#define RX_MSDU_END_IFCS_PRESENT_MASK 0x0000400000000000 - -#define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_31B_LSB 47 -#define RX_MSDU_END_RESERVED_31B_MSB 62 -#define RX_MSDU_END_RESERVED_31B_MASK 0x7fff800000000000 - -#define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MSDU_DONE_LSB 63 -#define RX_MSDU_END_MSDU_DONE_MSB 63 -#define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_ext_desc_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_ext_desc_info.h deleted file mode 100644 index 70bda69ddfec..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_ext_desc_info.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_EXT_DESC_INFO_H_ -#define _RX_MSDU_EXT_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1 - -struct rx_msdu_ext_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reo_destination_indication : 5, - service_code : 9, - priority_valid : 1, - data_offset : 12, - src_link_id : 3, - reserved_0a : 2; -#else - uint32_t reserved_0a : 2, - src_link_id : 3, - data_offset : 12, - priority_valid : 1, - service_code : 9, - reo_destination_indication : 5; -#endif -}; - -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_link.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_link.h deleted file mode 100644 index c54357dae2ef..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_link.h +++ /dev/null @@ -1,2051 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_LINK_H_ -#define _RX_MSDU_LINK_H_ - -#include "uniform_descriptor_header.h" -#include "buffer_addr_info.h" -#include "rx_msdu_details.h" -#define NUM_OF_DWORDS_RX_MSDU_LINK 64 - -struct rx_msdu_link { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct uniform_descriptor_header descriptor_header; - struct buffer_addr_info next_msdu_link_desc_addr_info; - uint32_t reserved_3a : 32; - struct rx_msdu_details msdu_0; - struct rx_msdu_details msdu_1; - struct rx_msdu_details msdu_2; - struct rx_msdu_details msdu_3; - struct rx_msdu_details msdu_4; - struct rx_msdu_details msdu_5; - struct rx_msdu_details msdu_6; - struct rx_msdu_details msdu_7; - struct rx_msdu_details msdu_8; - struct rx_msdu_details msdu_9; - struct rx_msdu_details msdu_10; - struct rx_msdu_details msdu_11; - struct rx_msdu_details msdu_12; - struct rx_msdu_details msdu_13; - struct rx_msdu_details msdu_14; -#else - struct uniform_descriptor_header descriptor_header; - struct buffer_addr_info next_msdu_link_desc_addr_info; - uint32_t reserved_3a : 32; - struct rx_msdu_details msdu_0; - struct rx_msdu_details msdu_1; - struct rx_msdu_details msdu_2; - struct rx_msdu_details msdu_3; - struct rx_msdu_details msdu_4; - struct rx_msdu_details msdu_5; - struct rx_msdu_details msdu_6; - struct rx_msdu_details msdu_7; - struct rx_msdu_details msdu_8; - struct rx_msdu_details msdu_9; - struct rx_msdu_details msdu_10; - struct rx_msdu_details msdu_11; - struct rx_msdu_details msdu_12; - struct rx_msdu_details msdu_13; - struct rx_msdu_details msdu_14; -#endif -}; - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB 0 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB 3 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_RESERVED_3A_OFFSET 0x0000000c -#define RX_MSDU_LINK_RESERVED_3A_LSB 0 -#define RX_MSDU_LINK_RESERVED_3A_MSB 31 -#define RX_MSDU_LINK_RESERVED_3A_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000010 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000080 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000090 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000a0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000b0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000c0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000d0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000e0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000f0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_start.h b/drivers/staging/fw-api/hw/fig/v2/rx_msdu_start.h deleted file mode 100644 index e1e99c027c85..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_msdu_start.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_START_H_ -#define _RX_MSDU_START_H_ - -#define NUM_OF_DWORDS_RX_MSDU_START 10 - -#define NUM_OF_QWORDS_RX_MSDU_START 5 - -struct rx_msdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - rate_mcs : 5, - reserved_0 : 2, - phy_ppdu_id : 16; - uint32_t msdu_length : 14, - stbc : 1, - ipsec_esp : 1, - l3_offset : 7, - ipsec_ah : 1, - l4_offset : 8; - uint32_t msdu_number : 8, - decap_format : 2, - ipv4_proto : 1, - ipv6_proto : 1, - tcp_proto : 1, - udp_proto : 1, - ip_frag : 1, - tcp_only_ack : 1, - da_is_bcast_mcast : 1, - toeplitz_hash_sel : 2, - ip_fixed_header_valid : 1, - ip_extn_header_valid : 1, - tcp_udp_header_valid : 1, - mesh_control_present : 1, - ldpc : 1, - ip4_protocol_ip6_next_header : 8; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t flow_id_toeplitz : 32; - uint32_t user_rssi : 8, - pkt_type : 4, - sgi : 2, - reserved_5a : 4, - receive_bandwidth : 3, - reception_type : 3, - mimo_ss_bitmap : 8; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t vlan_ctag_ci : 16, - vlan_stag_ci : 16; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 2, - rate_mcs : 5, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t l4_offset : 8, - ipsec_ah : 1, - l3_offset : 7, - ipsec_esp : 1, - stbc : 1, - msdu_length : 14; - uint32_t ip4_protocol_ip6_next_header : 8, - ldpc : 1, - mesh_control_present : 1, - tcp_udp_header_valid : 1, - ip_extn_header_valid : 1, - ip_fixed_header_valid : 1, - toeplitz_hash_sel : 2, - da_is_bcast_mcast : 1, - tcp_only_ack : 1, - ip_frag : 1, - udp_proto : 1, - tcp_proto : 1, - ipv6_proto : 1, - ipv4_proto : 1, - decap_format : 2, - msdu_number : 8; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t flow_id_toeplitz : 32; - uint32_t mimo_ss_bitmap : 8, - reception_type : 3, - receive_bandwidth : 3, - reserved_5a : 4, - sgi : 2, - pkt_type : 4, - user_rssi : 8; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t vlan_stag_ci : 16, - vlan_ctag_ci : 16; -#endif -}; - -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MSDU_START_RATE_MCS_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RATE_MCS_LSB 9 -#define RX_MSDU_START_RATE_MCS_MSB 13 -#define RX_MSDU_START_RATE_MCS_MASK 0x0000000000003e00 - -#define RX_MSDU_START_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RESERVED_0_LSB 14 -#define RX_MSDU_START_RESERVED_0_MSB 15 -#define RX_MSDU_START_RESERVED_0_MASK 0x000000000000c000 - -#define RX_MSDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_START_PHY_PPDU_ID_LSB 16 -#define RX_MSDU_START_PHY_PPDU_ID_MSB 31 -#define RX_MSDU_START_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MSDU_START_MSDU_LENGTH_OFFSET 0x0000000000000000 -#define RX_MSDU_START_MSDU_LENGTH_LSB 32 -#define RX_MSDU_START_MSDU_LENGTH_MSB 45 -#define RX_MSDU_START_MSDU_LENGTH_MASK 0x00003fff00000000 - -#define RX_MSDU_START_STBC_OFFSET 0x0000000000000000 -#define RX_MSDU_START_STBC_LSB 46 -#define RX_MSDU_START_STBC_MSB 46 -#define RX_MSDU_START_STBC_MASK 0x0000400000000000 - -#define RX_MSDU_START_IPSEC_ESP_OFFSET 0x0000000000000000 -#define RX_MSDU_START_IPSEC_ESP_LSB 47 -#define RX_MSDU_START_IPSEC_ESP_MSB 47 -#define RX_MSDU_START_IPSEC_ESP_MASK 0x0000800000000000 - -#define RX_MSDU_START_L3_OFFSET_OFFSET 0x0000000000000000 -#define RX_MSDU_START_L3_OFFSET_LSB 48 -#define RX_MSDU_START_L3_OFFSET_MSB 54 -#define RX_MSDU_START_L3_OFFSET_MASK 0x007f000000000000 - -#define RX_MSDU_START_IPSEC_AH_OFFSET 0x0000000000000000 -#define RX_MSDU_START_IPSEC_AH_LSB 55 -#define RX_MSDU_START_IPSEC_AH_MSB 55 -#define RX_MSDU_START_IPSEC_AH_MASK 0x0080000000000000 - -#define RX_MSDU_START_L4_OFFSET_OFFSET 0x0000000000000000 -#define RX_MSDU_START_L4_OFFSET_LSB 56 -#define RX_MSDU_START_L4_OFFSET_MSB 63 -#define RX_MSDU_START_L4_OFFSET_MASK 0xff00000000000000 - -#define RX_MSDU_START_MSDU_NUMBER_OFFSET 0x0000000000000008 -#define RX_MSDU_START_MSDU_NUMBER_LSB 0 -#define RX_MSDU_START_MSDU_NUMBER_MSB 7 -#define RX_MSDU_START_MSDU_NUMBER_MASK 0x00000000000000ff - -#define RX_MSDU_START_DECAP_FORMAT_OFFSET 0x0000000000000008 -#define RX_MSDU_START_DECAP_FORMAT_LSB 8 -#define RX_MSDU_START_DECAP_FORMAT_MSB 9 -#define RX_MSDU_START_DECAP_FORMAT_MASK 0x0000000000000300 - -#define RX_MSDU_START_IPV4_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IPV4_PROTO_LSB 10 -#define RX_MSDU_START_IPV4_PROTO_MSB 10 -#define RX_MSDU_START_IPV4_PROTO_MASK 0x0000000000000400 - -#define RX_MSDU_START_IPV6_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IPV6_PROTO_LSB 11 -#define RX_MSDU_START_IPV6_PROTO_MSB 11 -#define RX_MSDU_START_IPV6_PROTO_MASK 0x0000000000000800 - -#define RX_MSDU_START_TCP_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_PROTO_LSB 12 -#define RX_MSDU_START_TCP_PROTO_MSB 12 -#define RX_MSDU_START_TCP_PROTO_MASK 0x0000000000001000 - -#define RX_MSDU_START_UDP_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_UDP_PROTO_LSB 13 -#define RX_MSDU_START_UDP_PROTO_MSB 13 -#define RX_MSDU_START_UDP_PROTO_MASK 0x0000000000002000 - -#define RX_MSDU_START_IP_FRAG_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_FRAG_LSB 14 -#define RX_MSDU_START_IP_FRAG_MSB 14 -#define RX_MSDU_START_IP_FRAG_MASK 0x0000000000004000 - -#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_ONLY_ACK_LSB 15 -#define RX_MSDU_START_TCP_ONLY_ACK_MSB 15 -#define RX_MSDU_START_TCP_ONLY_ACK_MASK 0x0000000000008000 - -#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000008 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB 16 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB 16 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK 0x0000000000010000 - -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB 17 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB 18 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK 0x0000000000060000 - -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB 19 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB 19 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK 0x0000000000080000 - -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB 20 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB 20 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK 0x0000000000100000 - -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB 21 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB 21 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK 0x0000000000200000 - -#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000008 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB 22 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB 22 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK 0x0000000000400000 - -#define RX_MSDU_START_LDPC_OFFSET 0x0000000000000008 -#define RX_MSDU_START_LDPC_LSB 23 -#define RX_MSDU_START_LDPC_MSB 23 -#define RX_MSDU_START_LDPC_MASK 0x0000000000800000 - -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0x00000000ff000000 - -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB 32 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB 63 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 - -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000010 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB 0 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB 31 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK 0x00000000ffffffff - -#define RX_MSDU_START_USER_RSSI_OFFSET 0x0000000000000010 -#define RX_MSDU_START_USER_RSSI_LSB 32 -#define RX_MSDU_START_USER_RSSI_MSB 39 -#define RX_MSDU_START_USER_RSSI_MASK 0x000000ff00000000 - -#define RX_MSDU_START_PKT_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_START_PKT_TYPE_LSB 40 -#define RX_MSDU_START_PKT_TYPE_MSB 43 -#define RX_MSDU_START_PKT_TYPE_MASK 0x00000f0000000000 - -#define RX_MSDU_START_SGI_OFFSET 0x0000000000000010 -#define RX_MSDU_START_SGI_LSB 44 -#define RX_MSDU_START_SGI_MSB 45 -#define RX_MSDU_START_SGI_MASK 0x0000300000000000 - -#define RX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RESERVED_5A_LSB 46 -#define RX_MSDU_START_RESERVED_5A_MSB 49 -#define RX_MSDU_START_RESERVED_5A_MASK 0x0003c00000000000 - -#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB 50 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB 52 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK 0x001c000000000000 - -#define RX_MSDU_START_RECEPTION_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RECEPTION_TYPE_LSB 53 -#define RX_MSDU_START_RECEPTION_TYPE_MSB 55 -#define RX_MSDU_START_RECEPTION_TYPE_MASK 0x00e0000000000000 - -#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET 0x0000000000000010 -#define RX_MSDU_START_MIMO_SS_BITMAP_LSB 56 -#define RX_MSDU_START_MIMO_SS_BITMAP_MSB 63 -#define RX_MSDU_START_MIMO_SS_BITMAP_MASK 0xff00000000000000 - -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000018 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000018 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 - -#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000020 -#define RX_MSDU_START_SW_PHY_META_DATA_LSB 0 -#define RX_MSDU_START_SW_PHY_META_DATA_MSB 31 -#define RX_MSDU_START_SW_PHY_META_DATA_MASK 0x00000000ffffffff - -#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET 0x0000000000000020 -#define RX_MSDU_START_VLAN_CTAG_CI_LSB 32 -#define RX_MSDU_START_VLAN_CTAG_CI_MSB 47 -#define RX_MSDU_START_VLAN_CTAG_CI_MASK 0x0000ffff00000000 - -#define RX_MSDU_START_VLAN_STAG_CI_OFFSET 0x0000000000000020 -#define RX_MSDU_START_VLAN_STAG_CI_LSB 48 -#define RX_MSDU_START_VLAN_STAG_CI_MSB 63 -#define RX_MSDU_START_VLAN_STAG_CI_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_ack_report.h b/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_ack_report.h deleted file mode 100644 index 345b14ea4255..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_ack_report.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_ACK_REPORT_H_ -#define _RX_PPDU_ACK_REPORT_H_ - -#include "ack_report.h" -#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 2 - -#define NUM_OF_QWORDS_RX_PPDU_ACK_REPORT 1 - -struct rx_ppdu_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ack_report ack_report_details; - uint32_t tlv64_padding : 32; -#else - struct ack_report ack_report_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB 0 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB 3 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK 0x000000000000000f - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB 4 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB 7 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000000f0 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB 8 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB 8 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK 0x0000000000000100 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB 9 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB 15 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK 0x000000000000fe00 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 - -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_LSB 32 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MSB 63 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_end_user_stats.h b/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_end_user_stats.h deleted file mode 100644 index 51db8f35a6ab..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_end_user_stats.h +++ /dev/null @@ -1,679 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_END_USER_STATS_H_ -#define _RX_PPDU_END_USER_STATS_H_ - -#include "rx_rxpcu_classification_overview.h" -#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30 - -#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 15 - -struct rx_ppdu_end_user_stats { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t sta_full_aid : 13, - mcs : 5, - nss : 3, - expected_response_ack_or_ba : 1, - reserved_1a : 10; - uint32_t sw_peer_id : 16, - mpdu_cnt_fcs_err : 11, - sw2rxdma0_buf_source_used : 1, - fw2rxdma0_buf_source_used : 1, - sw2rxdma1_buf_source_used : 1, - sw2rxdma2_buf_source_used : 1, - fw2rxdma1_buf_source_used : 1; - uint32_t mpdu_cnt_fcs_ok : 11, - frame_control_info_valid : 1, - qos_control_info_valid : 1, - ht_control_info_valid : 1, - data_sequence_control_info_valid : 1, - ht_control_info_null_valid : 1, - rxdma2fw0_ring_used : 1, - rxdma2fw1_ring_used : 1, - rxdma2fwreo_0_ring_used : 1, - rxdma2fwreo_1_ring_used : 1, - reserved_3a : 1, - ht_control_field_pkt_type : 4, - reserved_3b : 7; - uint32_t ast_index : 16, - frame_control_field : 16; - uint32_t first_data_seq_ctrl : 16, - qos_control_field : 16; - uint32_t ht_control_field : 32; - uint32_t fcs_ok_bitmap_31_0 : 32; - uint32_t fcs_ok_bitmap_63_32 : 32; - uint32_t udp_msdu_count : 16, - tcp_msdu_count : 16; - uint32_t other_msdu_count : 16, - tcp_ack_msdu_count : 16; - uint32_t sw_response_reference_ptr : 32; - uint32_t received_qos_data_tid_bitmap : 16, - received_qos_data_tid_eosp_bitmap : 16; - uint32_t qosctrl_15_8_tid0 : 8, - qosctrl_15_8_tid1 : 8, - qosctrl_15_8_tid2 : 8, - qosctrl_15_8_tid3 : 8; - uint32_t qosctrl_15_8_tid4 : 8, - qosctrl_15_8_tid5 : 8, - qosctrl_15_8_tid6 : 8, - qosctrl_15_8_tid7 : 8; - uint32_t qosctrl_15_8_tid8 : 8, - qosctrl_15_8_tid9 : 8, - qosctrl_15_8_tid10 : 8, - qosctrl_15_8_tid11 : 8; - uint32_t qosctrl_15_8_tid12 : 8, - qosctrl_15_8_tid13 : 8, - qosctrl_15_8_tid14 : 8, - qosctrl_15_8_tid15 : 8; - uint32_t mpdu_ok_byte_count : 25, - ampdu_delim_ok_count_6_0 : 7; - uint32_t ampdu_delim_err_count : 25, - ampdu_delim_ok_count_13_7 : 7; - uint32_t mpdu_err_byte_count : 25, - ampdu_delim_ok_count_20_14 : 7; - uint32_t non_consecutive_delimiter_err : 16, - retried_msdu_count : 16; - uint32_t ht_control_null_field : 32; - uint32_t sw_response_reference_ptr_ext : 32; - uint32_t corrupted_due_to_fifo_delay : 1, - frame_control_info_null_valid : 1, - frame_control_field_null : 16, - retried_mpdu_count : 11, - reserved_23a : 3; - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_24a : 4, - frame_control_info_mgmt_ctrl_valid : 1, - mac_addr_ad2_valid : 1, - mcast_bcast : 1, - frame_control_field_mgmt_ctrl : 16; - uint32_t user_ppdu_len : 24, - reserved_25a : 8; - uint32_t mac_addr_ad2_31_0 : 32; - uint32_t mac_addr_ad2_47_32 : 16, - amsdu_msdu_count : 16; - uint32_t non_amsdu_msdu_count : 16, - ucast_msdu_count : 16; - uint32_t bcast_msdu_count : 16, - mcast_bcast_msdu_count : 16; -#else - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t reserved_1a : 10, - expected_response_ack_or_ba : 1, - nss : 3, - mcs : 5, - sta_full_aid : 13; - uint32_t fw2rxdma1_buf_source_used : 1, - sw2rxdma2_buf_source_used : 1, - sw2rxdma1_buf_source_used : 1, - fw2rxdma0_buf_source_used : 1, - sw2rxdma0_buf_source_used : 1, - mpdu_cnt_fcs_err : 11, - sw_peer_id : 16; - uint32_t reserved_3b : 7, - ht_control_field_pkt_type : 4, - reserved_3a : 1, - rxdma2fwreo_1_ring_used : 1, - rxdma2fwreo_0_ring_used : 1, - rxdma2fw1_ring_used : 1, - rxdma2fw0_ring_used : 1, - ht_control_info_null_valid : 1, - data_sequence_control_info_valid : 1, - ht_control_info_valid : 1, - qos_control_info_valid : 1, - frame_control_info_valid : 1, - mpdu_cnt_fcs_ok : 11; - uint32_t frame_control_field : 16, - ast_index : 16; - uint32_t qos_control_field : 16, - first_data_seq_ctrl : 16; - uint32_t ht_control_field : 32; - uint32_t fcs_ok_bitmap_31_0 : 32; - uint32_t fcs_ok_bitmap_63_32 : 32; - uint32_t tcp_msdu_count : 16, - udp_msdu_count : 16; - uint32_t tcp_ack_msdu_count : 16, - other_msdu_count : 16; - uint32_t sw_response_reference_ptr : 32; - uint32_t received_qos_data_tid_eosp_bitmap : 16, - received_qos_data_tid_bitmap : 16; - uint32_t qosctrl_15_8_tid3 : 8, - qosctrl_15_8_tid2 : 8, - qosctrl_15_8_tid1 : 8, - qosctrl_15_8_tid0 : 8; - uint32_t qosctrl_15_8_tid7 : 8, - qosctrl_15_8_tid6 : 8, - qosctrl_15_8_tid5 : 8, - qosctrl_15_8_tid4 : 8; - uint32_t qosctrl_15_8_tid11 : 8, - qosctrl_15_8_tid10 : 8, - qosctrl_15_8_tid9 : 8, - qosctrl_15_8_tid8 : 8; - uint32_t qosctrl_15_8_tid15 : 8, - qosctrl_15_8_tid14 : 8, - qosctrl_15_8_tid13 : 8, - qosctrl_15_8_tid12 : 8; - uint32_t ampdu_delim_ok_count_6_0 : 7, - mpdu_ok_byte_count : 25; - uint32_t ampdu_delim_ok_count_13_7 : 7, - ampdu_delim_err_count : 25; - uint32_t ampdu_delim_ok_count_20_14 : 7, - mpdu_err_byte_count : 25; - uint32_t retried_msdu_count : 16, - non_consecutive_delimiter_err : 16; - uint32_t ht_control_null_field : 32; - uint32_t sw_response_reference_ptr_ext : 32; - uint32_t reserved_23a : 3, - retried_mpdu_count : 11, - frame_control_field_null : 16, - frame_control_info_null_valid : 1, - corrupted_due_to_fifo_delay : 1; - uint32_t frame_control_field_mgmt_ctrl : 16, - mcast_bcast : 1, - mac_addr_ad2_valid : 1, - frame_control_info_mgmt_ctrl_valid : 1, - reserved_24a : 4, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_25a : 8, - user_ppdu_len : 24; - uint32_t mac_addr_ad2_31_0 : 32; - uint32_t amsdu_msdu_count : 16, - mac_addr_ad2_47_32 : 16; - uint32_t ucast_msdu_count : 16, - non_amsdu_msdu_count : 16; - uint32_t mcast_bcast_msdu_count : 16, - bcast_msdu_count : 16; -#endif -}; - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 32 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 44 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff00000000 - -#define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_MCS_LSB 45 -#define RX_PPDU_END_USER_STATS_MCS_MSB 49 -#define RX_PPDU_END_USER_STATS_MCS_MASK 0x0003e00000000000 - -#define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_NSS_LSB 50 -#define RX_PPDU_END_USER_STATS_NSS_MSB 52 -#define RX_PPDU_END_USER_STATS_NSS_MASK 0x001c000000000000 - -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 53 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 53 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x0020000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 54 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffc0000000000000 - -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x0000000007ff0000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000008000000 - -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_LSB 28 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MSB 28 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000010000000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000020000000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_LSB 30 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MSB 30 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MASK 0x0000000040000000 - -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_LSB 31 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MSB 31 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000080000000 - -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 42 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff00000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 43 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 43 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x0000080000000000 - -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 44 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 44 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x0000100000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 45 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 45 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x0000200000000000 - -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 46 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 46 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x0000400000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 47 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 47 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x0000800000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_LSB 48 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MSB 48 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MASK 0x0001000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_LSB 49 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MSB 49 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MASK 0x0002000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_LSB 50 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MSB 50 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MASK 0x0004000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_LSB 51 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MSB 51 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MASK 0x0008000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_LSB 52 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_MSB 52 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_MASK 0x0010000000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 53 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 56 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e0000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 57 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 -#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 -#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 32 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 47 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 48 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 63 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 32 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 63 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 47 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 32 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 63 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 32 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 39 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff00000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 40 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 47 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff0000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 48 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 55 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 56 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 63 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x00000000000000ff - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x000000000000ff00 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x0000000000ff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0x00000000ff000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 32 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 39 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff00000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 40 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 47 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff0000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 48 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 55 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 56 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 63 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x00000000000000ff - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x000000000000ff00 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x0000000000ff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0x00000000ff000000 - -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 56 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff00000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 57 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 63 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x0000000001ffffff - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0x00000000fe000000 - -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 56 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff00000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 57 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 63 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 32 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 63 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 33 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 33 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x0000000200000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 34 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 49 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc00000000 - -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 50 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 60 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 61 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe000000000000000 - -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB 2 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB 8 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB 9 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB 12 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK 0x0000000000001e00 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB 13 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB 13 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK 0x0000000000002000 - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB 14 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB 14 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK 0x0000000000004000 - -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB 15 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB 15 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK 0x0000000000008000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB 16 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB 31 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB 32 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB 55 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK 0x00ffffff00000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB 56 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB 0 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB 31 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB 32 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB 47 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB 15 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB 47 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_end_user_stats_ext.h b/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_end_user_stats_ext.h deleted file mode 100644 index 0a11202db481..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_end_user_stats_ext.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_END_USER_STATS_EXT_H_ -#define _RX_PPDU_END_USER_STATS_EXT_H_ - -#include "rx_rxpcu_classification_overview.h" -#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8 - -#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS_EXT 4 - -struct rx_ppdu_end_user_stats_ext { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t fcs_ok_bitmap_95_64 : 32; - uint32_t fcs_ok_bitmap_127_96 : 32; - uint32_t fcs_ok_bitmap_159_128 : 32; - uint32_t fcs_ok_bitmap_191_160 : 32; - uint32_t fcs_ok_bitmap_223_192 : 32; - uint32_t fcs_ok_bitmap_255_224 : 32; - uint32_t corrupted_due_to_fifo_delay : 1, - reserved_7a : 31; -#else - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t fcs_ok_bitmap_95_64 : 32; - uint32_t fcs_ok_bitmap_127_96 : 32; - uint32_t fcs_ok_bitmap_159_128 : 32; - uint32_t fcs_ok_bitmap_191_160 : 32; - uint32_t fcs_ok_bitmap_223_192 : 32; - uint32_t fcs_ok_bitmap_255_224 : 32; - uint32_t reserved_7a : 31, - corrupted_due_to_fifo_delay : 1; -#endif -}; - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 - -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB 33 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK 0xfffffffe00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_no_ack_report.h b/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_no_ack_report.h deleted file mode 100644 index d9c54c04df32..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_no_ack_report.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_NO_ACK_REPORT_H_ -#define _RX_PPDU_NO_ACK_REPORT_H_ - -#include "no_ack_report.h" -#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4 - -#define NUM_OF_QWORDS_RX_PPDU_NO_ACK_REPORT 2 - -struct rx_ppdu_no_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct no_ack_report no_ack_report_details; -#else - struct no_ack_report no_ack_report_details; -#endif -}; - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB 0 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB 3 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK 0x000000000000000f - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB 4 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB 7 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000f0 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB 8 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB 15 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000000000ff00 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB 32 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB 55 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK 0x00ffffff00000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB 56 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB 56 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK 0x0100000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 57 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 60 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e00000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB 61 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB 63 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000000fff - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000fff000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB 24 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB 31 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK 0x00000000ff000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 32 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 43 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff00000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB 44 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB 63 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK 0xfffff00000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_start.h b/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_start.h deleted file mode 100644 index 19765eb4409b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_start.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_START_H_ -#define _RX_PPDU_START_H_ - -#define NUM_OF_DWORDS_RX_PPDU_START 6 - -#define NUM_OF_QWORDS_RX_PPDU_START 3 - -struct rx_ppdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - preamble_time_to_rxframe : 8, - reserved_0a : 8; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t rxframe_assert_timestamp : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 8, - preamble_time_to_rxframe : 8, - phy_ppdu_id : 16; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t rxframe_assert_timestamp : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_START_PHY_PPDU_ID_LSB 0 -#define RX_PPDU_START_PHY_PPDU_ID_MSB 15 -#define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000 - -#define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_PPDU_START_RESERVED_0A_LSB 24 -#define RX_PPDU_START_RESERVED_0A_MSB 31 -#define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000 - -#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000 -#define RX_PPDU_START_SW_PHY_META_DATA_LSB 32 -#define RX_PPDU_START_SW_PHY_META_DATA_MSB 63 -#define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000 - -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 - -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff - -#define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010 -#define RX_PPDU_START_TLV64_PADDING_LSB 32 -#define RX_PPDU_START_TLV64_PADDING_MSB 63 -#define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_start_user_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_start_user_info.h deleted file mode 100644 index 16d3bb33edb4..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_ppdu_start_user_info.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_START_USER_INFO_H_ -#define _RX_PPDU_START_USER_INFO_H_ - -#include "receive_user_info.h" -#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8 - -#define NUM_OF_QWORDS_RX_PPDU_START_USER_INFO 4 - -struct rx_ppdu_start_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_user_info receive_user_info_details; -#else - struct receive_user_info receive_user_info_details; -#endif -}; - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 36 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000001f00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 37 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 38 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000006000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 1 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x0000000000000002 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB 2 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB 3 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK 0x000000000000000c - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB 4 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB 5 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK 0x0000000000000030 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB 6 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB 7 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK 0x00000000000000c0 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_LSB 62 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MSB 62 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MASK 0x4000000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0x8000000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_preamble.h b/drivers/staging/fw-api/hw/fig/v2/rx_preamble.h deleted file mode 100644 index 807463753865..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_preamble.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PREAMBLE_H_ -#define _RX_PREAMBLE_H_ - -#define NUM_OF_DWORDS_RX_PREAMBLE 2 - -#define NUM_OF_QWORDS_RX_PREAMBLE 1 - -struct rx_preamble { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t num_users : 6, - pkt_type : 4, - direction : 1, - reserved_0a : 21; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 21, - direction : 1, - pkt_type : 4, - num_users : 6; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PREAMBLE_NUM_USERS_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_NUM_USERS_LSB 0 -#define RX_PREAMBLE_NUM_USERS_MSB 5 -#define RX_PREAMBLE_NUM_USERS_MASK 0x000000000000003f - -#define RX_PREAMBLE_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_PKT_TYPE_LSB 6 -#define RX_PREAMBLE_PKT_TYPE_MSB 9 -#define RX_PREAMBLE_PKT_TYPE_MASK 0x00000000000003c0 - -#define RX_PREAMBLE_DIRECTION_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_DIRECTION_LSB 10 -#define RX_PREAMBLE_DIRECTION_MSB 10 -#define RX_PREAMBLE_DIRECTION_MASK 0x0000000000000400 - -#define RX_PREAMBLE_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_RESERVED_0A_LSB 11 -#define RX_PREAMBLE_RESERVED_0A_MSB 31 -#define RX_PREAMBLE_RESERVED_0A_MASK 0x00000000fffff800 - -#define RX_PREAMBLE_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_TLV64_PADDING_LSB 32 -#define RX_PREAMBLE_TLV64_PADDING_MSB 63 -#define RX_PREAMBLE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_response_required_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_response_required_info.h deleted file mode 100644 index 11da8b5e0bb2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_response_required_info.h +++ /dev/null @@ -1,764 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_RESPONSE_REQUIRED_INFO_H_ -#define _RX_RESPONSE_REQUIRED_INFO_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16 - -#define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8 - -struct rx_response_required_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - su_or_uplink_mu_reception : 1, - trigger_frame_received : 1, - __reserved_g_0012 : 2, - tb___reserved_g_0022_response_required : 2, - mac_security : 1, - filter_pass_monitor_ovrd : 1, - ast_search_incomplete : 1, - r2r_end_status_to_follow : 1, - __reserved_g_0016_listen_cca_check_at_phy_desc : 1, - __reserved_g_0016_listen_indication : 1, - three_or_more_type_subtypes : 1, - wait_sifs_config_valid : 1, - wait_sifs : 2; - uint32_t general_frame_control : 16, - second_frame_control : 16; - uint32_t duration : 16, - pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5, - sgi : 2, - stbc : 1, - ldpc : 1, - ampdu : 1, - rts_ta_grp_bit : 1; - uint32_t ctrl_frame_soliciting_resp : 1, - ast_fail_for_dot11ax_su_ext : 1, - service_dynamic : 1, - m_pkt : 1, - sta_partial_aid : 12, - group_id : 6, - ctrl_resp_pwr_mgmt : 1, - response_indication : 2, - ndp_indication : 1, - ndp_frame_type : 3, - second_frame_control_valid : 1, - ack_ba_resp_more_data : 1, - vht_ack : 1; - uint32_t sta_aid : 11, - interference : 1, - ects_as_tb_ppdu : 1, - ll_traffic_indication : 1, - reserved_4a : 2, - ack_id_ext : 10, - agc_cbw : 3, - service_cbw : 3; - uint32_t response_sta_count : 7, - __reserved_g_0035 : 1, - blackout_details_en : 1, - reserved : 2, - ht_vht_sig_cbw : 3, - cts_cbw : 3, - response_ack_count : 7, - response_assoc_ack_count : 7, - txop_duration_all_ones : 1; - uint32_t response_ba32_count : 7, - response_ba64_count : 7, - response_ba128_count : 7, - response_ba256_count : 7, - multi_tid : 1, - sw_response_tlv_from_crypto : 1, - dot11ax_dl_ul_flag : 1, - emlsr_main_tlv_if : 1; - uint32_t sw_response_frame_length : 16, - response_ba512_count : 7, - response_ba1024_count : 7, - reserved_7a : 2; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t dot11ax_received_format_indication : 1, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_bss_color_id : 6, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_cp_size : 2, - dot11ax_received_ltf_size : 2, - dot11ax_received_coding : 1, - dot11ax_received_dcm : 1, - dot11ax_received_doppler_indication : 1, - dot11ax_received_ext_ru_size : 4, - ftm_fields_valid : 1, - ftm_pe_nss : 3, - ftm_pe_ltf_size : 2, - ftm_pe_content : 1, - ftm_chain_csd_en : 1, - ftm_pe_chain_csd_en : 1; - uint32_t dot11ax_response_rate_source : 8, - dot11ax_ext_response_rate_source : 8, - sw_peer_id : 16; - uint32_t dot11be_puncture_bitmap : 16, - dot11be_response : 1, - punctured_response : 1, - eht_duplicate_mode : 2, - force_extra_symbol : 1, - ctrl_pkt_protect : 1, - mac_hdr_protect : 1, - reserved_13a : 3, - u_sig_puncture_pattern_encoding : 6; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t he_a_control_response_time : 12, - reserved_after_struct16 : 4; - uint32_t dso_primary20_index_select : 4, - dso_freq_subband_channel_bonding_mask : 16, - pad_duration : 5, - q2q_mba : 1, - reserved_15a : 6; -#else - uint32_t wait_sifs : 2, - wait_sifs_config_valid : 1, - three_or_more_type_subtypes : 1, - __reserved_g_0016_listen_indication : 1, - __reserved_g_0016_listen_cca_check_at_phy_desc : 1, - r2r_end_status_to_follow : 1, - ast_search_incomplete : 1, - filter_pass_monitor_ovrd : 1, - mac_security : 1, - tb___reserved_g_0022_response_required : 2, - __reserved_g_0012 : 2, - trigger_frame_received : 1, - su_or_uplink_mu_reception : 1, - phy_ppdu_id : 16; - uint32_t second_frame_control : 16, - general_frame_control : 16; - uint32_t rts_ta_grp_bit : 1, - ampdu : 1, - ldpc : 1, - stbc : 1, - sgi : 2, - rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4, - duration : 16; - uint32_t vht_ack : 1, - ack_ba_resp_more_data : 1, - second_frame_control_valid : 1, - ndp_frame_type : 3, - ndp_indication : 1, - response_indication : 2, - ctrl_resp_pwr_mgmt : 1, - group_id : 6, - sta_partial_aid : 12, - m_pkt : 1, - service_dynamic : 1, - ast_fail_for_dot11ax_su_ext : 1, - ctrl_frame_soliciting_resp : 1; - uint32_t service_cbw : 3, - agc_cbw : 3, - ack_id_ext : 10, - reserved_4a : 2, - ll_traffic_indication : 1, - ects_as_tb_ppdu : 1, - interference : 1, - sta_aid : 11; - uint32_t txop_duration_all_ones : 1, - response_assoc_ack_count : 7, - response_ack_count : 7, - cts_cbw : 3, - ht_vht_sig_cbw : 3, - reserved : 2, - blackout_details_en : 1, - __reserved_g_0035 : 1, - response_sta_count : 7; - uint32_t emlsr_main_tlv_if : 1, - dot11ax_dl_ul_flag : 1, - sw_response_tlv_from_crypto : 1, - multi_tid : 1, - response_ba256_count : 7, - response_ba128_count : 7, - response_ba64_count : 7, - response_ba32_count : 7; - uint32_t reserved_7a : 2, - response_ba1024_count : 7, - response_ba512_count : 7, - sw_response_frame_length : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ftm_pe_chain_csd_en : 1, - ftm_chain_csd_en : 1, - ftm_pe_content : 1, - ftm_pe_ltf_size : 2, - ftm_pe_nss : 3, - ftm_fields_valid : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_received_doppler_indication : 1, - dot11ax_received_dcm : 1, - dot11ax_received_coding : 1, - dot11ax_received_ltf_size : 2, - dot11ax_received_cp_size : 2, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_bss_color_id : 6, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_format_indication : 1; - uint32_t sw_peer_id : 16, - dot11ax_ext_response_rate_source : 8, - dot11ax_response_rate_source : 8; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_13a : 3, - mac_hdr_protect : 1, - ctrl_pkt_protect : 1, - force_extra_symbol : 1, - eht_duplicate_mode : 2, - punctured_response : 1, - dot11be_response : 1, - dot11be_puncture_bitmap : 16; - uint32_t reserved_after_struct16 : 4, - he_a_control_response_time : 12; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint32_t reserved_15a : 6, - q2q_mba : 1, - pad_duration : 5, - dso_freq_subband_channel_bonding_mask : 16, - dso_primary20_index_select : 4; -#endif -}; - -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x0000000000010000 - -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x0000000000020000 - -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x0000000000400000 - -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x0000000000800000 - -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x0000000001000000 - -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000002000000 - -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0x00000000c0000000 - -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x000000000000ffff - -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x00000000000f0000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000100000 - -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x0000000003e00000 - -#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 26 -#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x000000000c000000 - -#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 30 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x0000000040000000 - -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x0000000080000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 32 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x0000000100000000 - -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 33 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 33 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x0000000200000000 - -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 34 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 34 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x0000000400000000 - -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 35 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 35 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x0000000800000000 - -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 36 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff000000000 - -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 53 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 54 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x0040000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 56 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x0180000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 57 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 57 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x0200000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 58 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 60 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 61 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x2000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MASK 0x4000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MSB 10 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MASK 0x00000000000007ff - -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_LSB 11 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MSB 11 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MASK 0x0000000000000800 - -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_LSB 12 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MSB 12 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MASK 0x0000000000001000 - -#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_LSB 13 -#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_MSB 13 -#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_MASK 0x0000000000002000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_LSB 14 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MASK 0x000000000000c000 - -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x0000000003ff0000 - -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x000000001c000000 - -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0x00000000e0000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 38 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f00000000 - -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_LSB 40 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MSB 40 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MASK 0x0000010000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 41 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 42 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x0000060000000000 - -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 43 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 45 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x0000380000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 46 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c00000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 56 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x000000000000007f - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x0000000000003f80 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x00000000001fc000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x000000000fe00000 - -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000040000000 - -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_LSB 31 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MASK 0x0000000080000000 - -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f80000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 49 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 55 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x0080000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 56 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 58 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x0700000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 59 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 60 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x1800000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 61 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x2000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x4000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x00000000000000ff - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x000000000000ff00 - -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0x00000000ffff0000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 49 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 50 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 51 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 52 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 52 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x0010000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_LSB 53 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MSB 53 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MASK 0x0020000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_LSB 54 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MASK 0x0040000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 57 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x0380000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0x00000000f0000000 - -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MSB 35 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MASK 0x0000000f00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 36 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 51 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000ffff000000000 - -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_LSB 52 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MSB 56 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MASK 0x01f0000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_LSB 57 -#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_MSB 57 -#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_MASK 0x0200000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_LSB 58 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MASK 0xfc00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_rxpcu_classification_overview.h b/drivers/staging/fw-api/hw/fig/v2/rx_rxpcu_classification_overview.h deleted file mode 100644 index 92489a5f5b2d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_rxpcu_classification_overview.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ -#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ - -#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 - -struct rx_rxpcu_classification_overview { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t filter_pass_mpdus : 1, - filter_pass_mpdus_fcs_ok : 1, - monitor_direct_mpdus : 1, - monitor_direct_mpdus_fcs_ok : 1, - monitor_other_mpdus : 1, - monitor_other_mpdus_fcs_ok : 1, - phyrx_abort_received : 1, - filter_pass_monitor_ovrd_mpdus : 1, - filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, - reserved_0 : 7, - phy_ppdu_id : 16; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, - filter_pass_monitor_ovrd_mpdus : 1, - phyrx_abort_received : 1, - monitor_other_mpdus_fcs_ok : 1, - monitor_other_mpdus : 1, - monitor_direct_mpdus_fcs_ok : 1, - monitor_direct_mpdus : 1, - filter_pass_mpdus_fcs_ok : 1, - filter_pass_mpdus : 1; -#endif -}; - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB 0 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB 0 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK 0x00000001 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK 0x00000004 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK 0x00000010 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK 0x00000040 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB 9 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB 15 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK 0x0000fe00 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB 16 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB 31 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_start_param.h b/drivers/staging/fw-api/hw/fig/v2/rx_start_param.h deleted file mode 100644 index bb2b87e3cc97..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_start_param.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_START_PARAM_H_ -#define _RX_START_PARAM_H_ - -#define NUM_OF_DWORDS_RX_START_PARAM 2 - -#define NUM_OF_QWORDS_RX_START_PARAM 1 - -struct rx_start_param { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pkt_type : 4, - reserved_0a : 12, - remaining_rx_time : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t remaining_rx_time : 16, - reserved_0a : 12, - pkt_type : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_START_PARAM_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_START_PARAM_PKT_TYPE_LSB 0 -#define RX_START_PARAM_PKT_TYPE_MSB 3 -#define RX_START_PARAM_PKT_TYPE_MASK 0x000000000000000f - -#define RX_START_PARAM_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_START_PARAM_RESERVED_0A_LSB 4 -#define RX_START_PARAM_RESERVED_0A_MSB 15 -#define RX_START_PARAM_RESERVED_0A_MASK 0x000000000000fff0 - -#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET 0x0000000000000000 -#define RX_START_PARAM_REMAINING_RX_TIME_LSB 16 -#define RX_START_PARAM_REMAINING_RX_TIME_MSB 31 -#define RX_START_PARAM_REMAINING_RX_TIME_MASK 0x00000000ffff0000 - -#define RX_START_PARAM_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_START_PARAM_TLV64_PADDING_LSB 32 -#define RX_START_PARAM_TLV64_PADDING_MSB 63 -#define RX_START_PARAM_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_timing_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_timing_info.h deleted file mode 100644 index ea6780e25c55..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_timing_info.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_TIMING_INFO_H_ -#define _RX_TIMING_INFO_H_ - -#define NUM_OF_DWORDS_RX_TIMING_INFO 5 - -struct rx_timing_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_timestamp_1_lower_32 : 32; - uint32_t phy_timestamp_1_upper_32 : 32; - uint32_t phy_timestamp_2_lower_32 : 32; - uint32_t phy_timestamp_2_upper_32 : 32; - uint32_t residual_phase_offset : 12, - sub_usec_ts_rx_end : 10, - reserved : 10; -#else - uint32_t phy_timestamp_1_lower_32 : 32; - uint32_t phy_timestamp_1_upper_32 : 32; - uint32_t phy_timestamp_2_lower_32 : 32; - uint32_t phy_timestamp_2_upper_32 : 32; - uint32_t reserved : 10, - sub_usec_ts_rx_end : 10, - residual_phase_offset : 12; -#endif -}; - -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000000 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000004 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x00000008 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000c -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000010 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_LSB 0 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MSB 11 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff - -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_OFFSET 0x00000010 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_LSB 12 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MSB 21 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MASK 0x003ff000 - -#define RX_TIMING_INFO_RESERVED_OFFSET 0x00000010 -#define RX_TIMING_INFO_RESERVED_LSB 22 -#define RX_TIMING_INFO_RESERVED_MSB 31 -#define RX_TIMING_INFO_RESERVED_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rx_trig_info.h b/drivers/staging/fw-api/hw/fig/v2/rx_trig_info.h deleted file mode 100644 index b6b074118bea..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rx_trig_info.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_TRIG_INFO_H_ -#define _RX_TRIG_INFO_H_ - -#define NUM_OF_DWORDS_RX_TRIG_INFO 2 - -#define NUM_OF_QWORDS_RX_TRIG_INFO 1 - -struct rx_trig_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_trigger_frame_type : 2, - trigger_resp_type : 3, - reserved_0 : 27; - uint32_t ppdu_duration : 16, - unique_destination_id : 16; -#else - uint32_t reserved_0 : 27, - trigger_resp_type : 3, - rx_trigger_frame_type : 2; - uint32_t unique_destination_id : 16, - ppdu_duration : 16; -#endif -}; - -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x0000000000000003 - -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x000000000000001c - -#define RX_TRIG_INFO_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_RESERVED_0_LSB 5 -#define RX_TRIG_INFO_RESERVED_0_MSB 31 -#define RX_TRIG_INFO_RESERVED_0_MASK 0x00000000ffffffe0 - -#define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_PPDU_DURATION_LSB 32 -#define RX_TRIG_INFO_PPDU_DURATION_MSB 47 -#define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff00000000 - -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 48 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 63 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rxpcu_early_rx_indication.h b/drivers/staging/fw-api/hw/fig/v2/rxpcu_early_rx_indication.h deleted file mode 100644 index d2dc464cf1cf..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rxpcu_early_rx_indication.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_EARLY_RX_INDICATION_H_ -#define _RXPCU_EARLY_RX_INDICATION_H_ - -#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 2 - -#define NUM_OF_QWORDS_RXPCU_EARLY_RX_INDICATION 1 - -struct rxpcu_early_rx_indication { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5, - dot11ax_received_ext_ru_size : 4, - reserved_0a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 18, - dot11ax_received_ext_ru_size : 4, - rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB 0 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB 3 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK 0x000000000000000f - -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB 4 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB 4 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK 0x0000000000000010 - -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB 5 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB 9 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK 0x00000000000003e0 - -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 10 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 13 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0000000000003c00 - -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB 14 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB 31 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK 0x00000000ffffc000 - -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_LSB 32 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MSB 63 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rxpcu_ppdu_end_info.h b/drivers/staging/fw-api/hw/fig/v2/rxpcu_ppdu_end_info.h deleted file mode 100644 index c97ad08c26a4..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rxpcu_ppdu_end_info.h +++ /dev/null @@ -1,925 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_PPDU_END_INFO_H_ -#define _RXPCU_PPDU_END_INFO_H_ - -#include "phyrx_abort_request_info.h" -#include "macrx_abort_request_info.h" -#include "rxpcu_ppdu_end_layout_info.h" -#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 32 - -#define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 16 - -struct rxpcu_ppdu_end_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t wb_timestamp_lower_32 : 32; - uint32_t wb_timestamp_upper_32 : 32; - uint32_t rx_antenna : 24, - tx_ht_vht_ack : 1, - unsupported_mu_nc : 1, - otp_txbf_disable : 1, - previous_tlv_corrupted : 1, - phyrx_abort_request_info_valid : 1, - macrx_abort_request_info_valid : 1, - coex_wan_tx_from_start_of_rx_ratid1 : 1, - coex_wan_tx_after_start_of_rx_ratid1 : 1; - uint32_t coex_bt_tx_from_start_of_rx : 1, - coex_bt_tx_after_start_of_rx : 1, - coex_wan_tx_from_start_of_rx : 1, - coex_wan_tx_after_start_of_rx : 1, - coex_wlan_tx_from_start_of_rx : 1, - coex_wlan_tx_after_start_of_rx : 1, - mpdu_delimiter_errors_seen : 1, - __reserved_g_0012 : 2, - dialog_token : 8, - follow_up_dialog_token : 8, - bb_captured_channel : 1, - bb_captured_reason : 3, - bb_captured_timeout : 1, - __reserved_g_0054 : 1, - __reserved_g_0058 : 1; - uint32_t before_mpdu_count_passing_fcs : 10, - before_mpdu_count_failing_fcs : 10, - after_mpdu_count_passing_fcs : 10, - reserved_4 : 2; - uint32_t after_mpdu_count_failing_fcs : 10, - reserved_5 : 22; - uint32_t phy_timestamp_tx_lower_32 : 32; - uint32_t phy_timestamp_tx_upper_32 : 32; - uint32_t bb_length : 16, - bb_data : 1, - reserved_8 : 3, - first_bt_broadcast_status_details : 12; - uint32_t rx_ppdu_duration : 24, - reserved_9 : 8; - uint32_t ast_index : 16, - ast_index_valid : 1, - reserved_10 : 3, - second_bt_broadcast_status_details : 12; - struct phyrx_abort_request_info phyrx_abort_request_info_details; - struct macrx_abort_request_info macrx_abort_request_info_details; - uint16_t pre_bt_broadcast_status_details : 12, - reserved_12a : 4; - uint32_t non_qos_sn_info_valid : 1, - rts_or_trig_protected_ppdu : 1, - rts_or_trig_prot_type : 2, - reserved_13a : 2, - non_qos_sn_highest : 12, - non_qos_sn_highest_retry_setting : 1, - non_qos_sn_lowest : 12, - non_qos_sn_lowest_retry_setting : 1; - uint32_t qos_sn_1_info_valid : 1, - reserved_14a : 1, - qos_sn_1_tid : 4, - qos_sn_1_highest : 12, - qos_sn_1_highest_retry_setting : 1, - qos_sn_1_lowest : 12, - qos_sn_1_lowest_retry_setting : 1; - uint32_t qos_sn_2_info_valid : 1, - reserved_15a : 1, - qos_sn_2_tid : 4, - qos_sn_2_highest : 12, - qos_sn_2_highest_retry_setting : 1, - qos_sn_2_lowest : 12, - qos_sn_2_lowest_retry_setting : 1; - struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; - uint32_t corrupted_due_to_fifo_delay : 1, - qos_sn_1_more_frag_state : 1, - qos_sn_1_frag_num_state : 4, - qos_sn_2_more_frag_state : 1, - qos_sn_2_frag_num_state : 4, - rts_or_trig_prot_non_11a : 1, - rts_or_trig_prot_rate_mcs : 4, - rts_or_trig_prot_peer_addr_15_0 : 16; - uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; - uint32_t rts_or_trig_rx_count : 32; - uint32_t cts_or_null_tx_count : 32; - uint32_t coex_tracker2_tx_from_start_of_rx : 1, - coex_tracker2_tx_after_start_of_rx : 1, - coex_tracker3_tx_from_start_of_rx : 1, - coex_tracker3_tx_after_start_of_rx : 1, - coex_tracker4_tx_from_start_of_rx : 1, - coex_tracker4_tx_after_start_of_rx : 1, - coex_tracker5_tx_from_start_of_rx : 1, - coex_tracker5_tx_after_start_of_rx : 1, - coex_tracker6_tx_from_start_of_rx : 1, - coex_tracker6_tx_after_start_of_rx : 1, - reserved_30a : 22; - uint32_t rx_ppdu_end_marker : 32; -#else - uint32_t wb_timestamp_lower_32 : 32; - uint32_t wb_timestamp_upper_32 : 32; - uint32_t coex_wan_tx_after_start_of_rx_ratid1 : 1, - coex_wan_tx_from_start_of_rx_ratid1 : 1, - macrx_abort_request_info_valid : 1, - phyrx_abort_request_info_valid : 1, - previous_tlv_corrupted : 1, - otp_txbf_disable : 1, - unsupported_mu_nc : 1, - tx_ht_vht_ack : 1, - rx_antenna : 24; - uint32_t __reserved_g_0058 : 1, - __reserved_g_0054 : 1, - bb_captured_timeout : 1, - bb_captured_reason : 3, - bb_captured_channel : 1, - follow_up_dialog_token : 8, - dialog_token : 8, - __reserved_g_0012 : 2, - mpdu_delimiter_errors_seen : 1, - coex_wlan_tx_after_start_of_rx : 1, - coex_wlan_tx_from_start_of_rx : 1, - coex_wan_tx_after_start_of_rx : 1, - coex_wan_tx_from_start_of_rx : 1, - coex_bt_tx_after_start_of_rx : 1, - coex_bt_tx_from_start_of_rx : 1; - uint32_t reserved_4 : 2, - after_mpdu_count_passing_fcs : 10, - before_mpdu_count_failing_fcs : 10, - before_mpdu_count_passing_fcs : 10; - uint32_t reserved_5 : 22, - after_mpdu_count_failing_fcs : 10; - uint32_t phy_timestamp_tx_lower_32 : 32; - uint32_t phy_timestamp_tx_upper_32 : 32; - uint32_t first_bt_broadcast_status_details : 12, - reserved_8 : 3, - bb_data : 1, - bb_length : 16; - uint32_t reserved_9 : 8, - rx_ppdu_duration : 24; - uint32_t second_bt_broadcast_status_details : 12, - reserved_10 : 3, - ast_index_valid : 1, - ast_index : 16; - struct phyrx_abort_request_info phyrx_abort_request_info_details; - uint32_t reserved_12a : 4, - pre_bt_broadcast_status_details : 12; - struct macrx_abort_request_info macrx_abort_request_info_details; - uint32_t non_qos_sn_lowest_retry_setting : 1, - non_qos_sn_lowest : 12, - non_qos_sn_highest_retry_setting : 1, - non_qos_sn_highest : 12, - reserved_13a : 2, - rts_or_trig_prot_type : 2, - rts_or_trig_protected_ppdu : 1, - non_qos_sn_info_valid : 1; - uint32_t qos_sn_1_lowest_retry_setting : 1, - qos_sn_1_lowest : 12, - qos_sn_1_highest_retry_setting : 1, - qos_sn_1_highest : 12, - qos_sn_1_tid : 4, - reserved_14a : 1, - qos_sn_1_info_valid : 1; - uint32_t qos_sn_2_lowest_retry_setting : 1, - qos_sn_2_lowest : 12, - qos_sn_2_highest_retry_setting : 1, - qos_sn_2_highest : 12, - qos_sn_2_tid : 4, - reserved_15a : 1, - qos_sn_2_info_valid : 1; - struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; - uint32_t rts_or_trig_prot_peer_addr_15_0 : 16, - rts_or_trig_prot_rate_mcs : 4, - rts_or_trig_prot_non_11a : 1, - qos_sn_2_frag_num_state : 4, - qos_sn_2_more_frag_state : 1, - qos_sn_1_frag_num_state : 4, - qos_sn_1_more_frag_state : 1, - corrupted_due_to_fifo_delay : 1; - uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; - uint32_t rts_or_trig_rx_count : 32; - uint32_t cts_or_null_tx_count : 32; - uint32_t reserved_30a : 22, - coex_tracker6_tx_after_start_of_rx : 1, - coex_tracker6_tx_from_start_of_rx : 1, - coex_tracker5_tx_after_start_of_rx : 1, - coex_tracker5_tx_from_start_of_rx : 1, - coex_tracker4_tx_after_start_of_rx : 1, - coex_tracker4_tx_from_start_of_rx : 1, - coex_tracker3_tx_after_start_of_rx : 1, - coex_tracker3_tx_from_start_of_rx : 1, - coex_tracker2_tx_after_start_of_rx : 1, - coex_tracker2_tx_from_start_of_rx : 1; - uint32_t rx_ppdu_end_marker : 32; -#endif -}; - -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 32 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 63 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x0000000000ffffff - -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x0000000001000000 - -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x0000000002000000 - -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x0000000004000000 - -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x0000000008000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000010000000 - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000020000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_LSB 30 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MSB 30 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MASK 0x0000000040000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_LSB 31 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MSB 31 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MASK 0x0000000080000000 - -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 32 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 32 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 33 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 33 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 34 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 34 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x0000000400000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 35 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 35 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x0000000800000000 - -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 36 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 36 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x0000001000000000 - -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 37 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 37 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x0000002000000000 - -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 38 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 38 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x0000004000000000 - -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 41 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 48 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe0000000000 - -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 49 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 56 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 57 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 57 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x0200000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 58 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 60 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c00000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 61 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 61 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x2000000000000000 - -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x00000000000003ff - -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x00000000000ffc00 - -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x000000003ff00000 - -#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 -#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0x00000000c0000000 - -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 32 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 41 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 42 -#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 63 -#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc0000000000 - -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x0000000000000018 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000000000000018 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 32 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 63 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x000000000000ffff - -#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 -#define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 -#define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x0000000000010000 - -#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 -#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 -#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x00000000000e0000 - -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 - -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 32 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 55 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 56 -#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 63 -#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff00000000000000 - -#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 -#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 -#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x000000000000ffff - -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x0000000000010000 - -#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 -#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 -#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x00000000000e0000 - -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_LSB 42 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MSB 42 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MASK 0x0000040000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_LSB 43 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MSB 43 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MASK 0x0000080000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_LSB 44 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MSB 44 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MASK 0x0000100000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_LSB 45 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MSB 45 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MASK 0x0000200000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_LSB 46 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MSB 46 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MASK 0x0000400000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 47 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 47 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000800000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 48 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 63 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff000000000000 - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x000000000000ff00 - -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x000000000fff0000 - -#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0x00000000f0000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 32 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 32 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_LSB 33 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MSB 33 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_LSB 34 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MSB 35 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MASK 0x0000000c00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 36 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 37 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x0000003000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 38 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 49 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 50 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 50 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 51 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 62 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff8000000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 63 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 63 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x000000000000003c - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x000000000003ffc0 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x0000000000040000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x000000007ff80000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x0000000080000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 32 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 32 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 33 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 33 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 34 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 37 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c00000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 38 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 49 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 50 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 50 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 51 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 62 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff8000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 63 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 63 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x0000000000000003 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x00000000000000fc - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x0000000000003f00 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x00000000000fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x0000000003f00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 37 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 50 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 62 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0x00000000f0000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 60 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x000000000000007f - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x0000000000003f80 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0x00000000e0000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 57 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x00000000000000ff - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0x00000000ff000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 40 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff0000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x0000000000000060 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x0000000000000060 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x000000000000003c - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x0000000000000040 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x0000000000000780 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_LSB 11 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MSB 11 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MASK 0x0000000000000800 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_LSB 12 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MSB 15 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MASK 0x000000000000f000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_LSB 16 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MSB 31 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MASK 0x00000000ffff0000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_LSB 32 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MSB 63 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_OFFSET 0x0000000000000070 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_LSB 0 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MSB 31 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_OFFSET 0x0000000000000070 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_LSB 32 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MSB 63 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_LSB 0 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MSB 0 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_LSB 1 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MSB 1 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_LSB 2 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MSB 2 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MASK 0x0000000000000004 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_LSB 3 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MSB 3 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MASK 0x0000000000000008 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_LSB 4 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MSB 4 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MASK 0x0000000000000010 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_LSB 5 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MSB 5 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MASK 0x0000000000000020 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_LSB 6 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MSB 6 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MASK 0x0000000000000040 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_LSB 7 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MSB 7 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MASK 0x0000000000000080 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_LSB 8 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MSB 8 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MASK 0x0000000000000100 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_LSB 9 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MSB 9 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MASK 0x0000000000000200 - -#define RXPCU_PPDU_END_INFO_RESERVED_30A_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_LSB 10 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_MASK 0x00000000fffffc00 - -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 32 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 63 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rxpcu_ppdu_end_layout_info.h b/drivers/staging/fw-api/hw/fig/v2/rxpcu_ppdu_end_layout_info.h deleted file mode 100644 index 9d54e91522ec..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rxpcu_ppdu_end_layout_info.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_ -#define _RXPCU_PPDU_END_LAYOUT_INFO_H_ - -#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10 - -struct rxpcu_ppdu_end_layout_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rssi_legacy_offset : 2, - l_sig_a_offset : 6, - l_sig_b_offset : 6, - ht_sig_offset : 6, - vht_sig_a_offset : 6, - repeat_l_sig_a_offset : 6; - uint32_t he_sig_a_su_offset : 6, - he_sig_a_mu_dl_offset : 6, - he_sig_a_mu_ul_offset : 6, - generic_u_sig_offset : 6, - rssi_ht_offset : 7, - reserved_1a : 1; - uint32_t vht_sig_b_su20_offset : 7, - vht_sig_b_su40_offset : 7, - vht_sig_b_su80_offset : 7, - vht_sig_b_su160_offset : 7, - reserved_2a : 4; - uint32_t vht_sig_b_mu20_offset : 7, - vht_sig_b_mu40_offset : 7, - vht_sig_b_mu80_offset : 7, - vht_sig_b_mu160_offset : 7, - reserved_3a : 4; - uint32_t he_sig_b1_mu_offset : 7, - he_sig_b2_mu_offset : 7, - he_sig_b2_ofdma_offset : 7, - first_generic_eht_sig_offset : 7, - multiple_generic_eht_sig_included : 1, - reserved_4a : 3; - uint32_t common_user_info_offset : 7, - first_debug_info_offset : 8, - multiple_debug_info_included : 1, - first_other_receive_info_offset : 8, - multiple_other_receive_info_included : 1, - reserved_5a : 7; - uint32_t data_done_offset : 8, - generated_cbf_details_offset : 8, - pkt_end_part1_offset : 8, - location_offset : 8; - uint32_t __reserved_g_0011 : 8, - pkt_end_offset : 8, - abort_request_ack_offset : 8, - reserved_7a : 8; - uint32_t reserved_8a : 32; - uint32_t reserved_9a : 32; -#else - uint32_t repeat_l_sig_a_offset : 6, - vht_sig_a_offset : 6, - ht_sig_offset : 6, - l_sig_b_offset : 6, - l_sig_a_offset : 6, - rssi_legacy_offset : 2; - uint32_t reserved_1a : 1, - rssi_ht_offset : 7, - generic_u_sig_offset : 6, - he_sig_a_mu_ul_offset : 6, - he_sig_a_mu_dl_offset : 6, - he_sig_a_su_offset : 6; - uint32_t reserved_2a : 4, - vht_sig_b_su160_offset : 7, - vht_sig_b_su80_offset : 7, - vht_sig_b_su40_offset : 7, - vht_sig_b_su20_offset : 7; - uint32_t reserved_3a : 4, - vht_sig_b_mu160_offset : 7, - vht_sig_b_mu80_offset : 7, - vht_sig_b_mu40_offset : 7, - vht_sig_b_mu20_offset : 7; - uint32_t reserved_4a : 3, - multiple_generic_eht_sig_included : 1, - first_generic_eht_sig_offset : 7, - he_sig_b2_ofdma_offset : 7, - he_sig_b2_mu_offset : 7, - he_sig_b1_mu_offset : 7; - uint32_t reserved_5a : 7, - multiple_other_receive_info_included : 1, - first_other_receive_info_offset : 8, - multiple_debug_info_included : 1, - first_debug_info_offset : 8, - common_user_info_offset : 7; - uint32_t location_offset : 8, - pkt_end_part1_offset : 8, - generated_cbf_details_offset : 8, - data_done_offset : 8; - uint32_t reserved_7a : 8, - abort_request_ack_offset : 8, - pkt_end_offset : 8, - __reserved_g_0011 : 8; - uint32_t reserved_8a : 32; - uint32_t reserved_9a : 32; -#endif -}; - -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003 - -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc - -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff - -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/rxpt_classify_info.h b/drivers/staging/fw-api/hw/fig/v2/rxpt_classify_info.h deleted file mode 100644 index 7fc572ae2474..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/rxpt_classify_info.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPT_CLASSIFY_INFO_H_ -#define _RXPT_CLASSIFY_INFO_H_ - -#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 - -struct rxpt_classify_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reo_destination_indication : 5, - lmac_peer_id_msb : 2, - use_flow_id_toeplitz_clfy : 1, - pkt_selection_fp_ucast_data : 1, - pkt_selection_fp_mcast_data : 1, - pkt_selection_fp_1000 : 1, - rxdma0_source_ring_selection : 3, - rxdma0_destination_ring_selection : 3, - mcast_echo_drop_enable : 1, - wds_learning_detect_en : 1, - intrabss_check_en : 1, - use_ppe : 1, - ppe_routing_enable : 1, - cce_source_sel_en : 1, - reserved_0b : 9; -#else - uint32_t reserved_0b : 9, - cce_source_sel_en : 1, - ppe_routing_enable : 1, - use_ppe : 1, - intrabss_check_en : 1, - wds_learning_detect_en : 1, - mcast_echo_drop_enable : 1, - rxdma0_destination_ring_selection : 3, - rxdma0_source_ring_selection : 3, - pkt_selection_fp_1000 : 1, - pkt_selection_fp_mcast_data : 1, - pkt_selection_fp_ucast_data : 1, - use_flow_id_toeplitz_clfy : 1, - lmac_peer_id_msb : 2, - reo_destination_indication : 5; -#endif -}; - -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB 0 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB 4 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB 5 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB 6 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK 0x00000060 - -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB 10 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB 10 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK 0x00000400 - -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 - -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 - -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 - -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB 18 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB 18 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK 0x00040000 - -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB 19 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB 19 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK 0x00080000 - -#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_USE_PPE_LSB 20 -#define RXPT_CLASSIFY_INFO_USE_PPE_MSB 20 -#define RXPT_CLASSIFY_INFO_USE_PPE_MASK 0x00100000 - -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB 21 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB 21 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK 0x00200000 - -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_LSB 22 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MSB 22 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MASK 0x00400000 - -#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB 23 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB 31 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK 0xff800000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/seq_hwio.h b/drivers/staging/fw-api/hw/fig/v2/seq_hwio.h deleted file mode 100644 index 69111d08d535..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/seq_hwio.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef __SEQ_H__ -#define __SEQ_H__ - -#include "HALhwio.h" - -#define SEQ_INH(base, regtype, reg) \ - SEQ_##regtype##_INH(base, reg) - -#define SEQ_INMH(base, regtype, reg, mask) \ - SEQ_##regtype##_INMH(base, reg, mask) - -#define SEQ_INFH(base, regtype, reg, fld) \ - (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) - -#define SEQ_OUTH(base, regtype, reg, val) \ - SEQ_##regtype##_OUTH(base, reg, val) - -#define SEQ_OUTMH(base, regtype, reg, mask, val) \ - SEQ_##regtype##_OUTMH(base, reg, mask, val) - -#define SEQ_OUTFH(base, regtype, reg, fld, val) \ - SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) - -typedef enum { - SEC, - MS, - US, - NS -} SEQ_TimeUnit; - -extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); - -extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); - -#endif - diff --git a/drivers/staging/fw-api/hw/fig/v2/tcl_assist_cmd.h b/drivers/staging/fw-api/hw/fig/v2/tcl_assist_cmd.h deleted file mode 100644 index f7a5bd5287cb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tcl_assist_cmd.h +++ /dev/null @@ -1,411 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TCL_ASSIST_CMD_H_ -#define _TCL_ASSIST_CMD_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_TCL_ASSIST_CMD 16 - -struct tcl_assist_cmd { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_addr_info; - uint32_t buf_or_ext_desc_type : 1, - bank_id : 6, - vdev_id : 8, - data_length : 14, - to_fw_tqm : 2, - reserved_2a : 1; - uint32_t reserved_3a : 25, - metadata_length : 7; - uint32_t txpt_classify_info_index : 8, - txpt_classify_info_sel : 5, - txpt_classify_info_override : 1, - flow_override_enable : 1, - flow_select : 1, - hlos_tid : 4, - hlos_tid_overwrite : 1, - tos_tc_value : 8, - reserved_4a : 3; - uint32_t reserved_5a : 16, - l3_type : 16; - uint32_t l4_protocol : 8, - l4_port : 16, - l4_port_type : 1, - da_is_bcast_mcast : 1, - da_is_bcast : 1, - reserved_6a : 5; - uint32_t ip_address_31_0 : 32; - uint32_t ip_address_63_32 : 32; - uint32_t ip_address_95_64 : 32; - uint32_t ip_address_127_96 : 32; - uint32_t ip_da_or_sa : 1, - encap_length_change : 6, - encap_length_decrease : 1, - encap_length_override : 1, - type_or_length : 1, - snap_oui_zero_or_f8 : 1, - snap_oui_not_zero_and_not_f8 : 1, - msdu_color : 2, - tx_notify_frame : 3, - tqm_no_drop : 1, - reserved_11a : 12, - l3_checksum_enable : 1, - l4_checksum_enable : 1; - uint32_t buffer_timestamp : 19, - buffer_timestamp_valid : 1, - s_vlan_tag_present : 1, - c_vlan_tag_present : 1, - wmac_hdr_len : 7, - reserved_12a : 3; - uint32_t tcl_cmd_number : 32; - uint32_t reserved_14a : 32; - uint32_t reserved_15a : 20, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_addr_info; - uint32_t reserved_2a : 1, - to_fw_tqm : 2, - data_length : 14, - vdev_id : 8, - bank_id : 6, - buf_or_ext_desc_type : 1; - uint32_t metadata_length : 7, - reserved_3a : 25; - uint32_t reserved_4a : 3, - tos_tc_value : 8, - hlos_tid_overwrite : 1, - hlos_tid : 4, - flow_select : 1, - flow_override_enable : 1, - txpt_classify_info_override : 1, - txpt_classify_info_sel : 5, - txpt_classify_info_index : 8; - uint32_t l3_type : 16, - reserved_5a : 16; - uint32_t reserved_6a : 5, - da_is_bcast : 1, - da_is_bcast_mcast : 1, - l4_port_type : 1, - l4_port : 16, - l4_protocol : 8; - uint32_t ip_address_31_0 : 32; - uint32_t ip_address_63_32 : 32; - uint32_t ip_address_95_64 : 32; - uint32_t ip_address_127_96 : 32; - uint32_t l4_checksum_enable : 1, - l3_checksum_enable : 1, - reserved_11a : 12, - tqm_no_drop : 1, - tx_notify_frame : 3, - msdu_color : 2, - snap_oui_not_zero_and_not_f8 : 1, - snap_oui_zero_or_f8 : 1, - type_or_length : 1, - encap_length_override : 1, - encap_length_decrease : 1, - encap_length_change : 6, - ip_da_or_sa : 1; - uint32_t reserved_12a : 3, - wmac_hdr_len : 7, - c_vlan_tag_present : 1, - s_vlan_tag_present : 1, - buffer_timestamp_valid : 1, - buffer_timestamp : 19; - uint32_t tcl_cmd_number : 32; - uint32_t reserved_14a : 32; - uint32_t looping_count : 4, - ring_id : 8, - reserved_15a : 20; -#endif -}; - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_LSB 0 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MSB 0 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000001 - -#define TCL_ASSIST_CMD_BANK_ID_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_BANK_ID_LSB 1 -#define TCL_ASSIST_CMD_BANK_ID_MSB 6 -#define TCL_ASSIST_CMD_BANK_ID_MASK 0x0000007e - -#define TCL_ASSIST_CMD_VDEV_ID_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_VDEV_ID_LSB 7 -#define TCL_ASSIST_CMD_VDEV_ID_MSB 14 -#define TCL_ASSIST_CMD_VDEV_ID_MASK 0x00007f80 - -#define TCL_ASSIST_CMD_DATA_LENGTH_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_DATA_LENGTH_LSB 15 -#define TCL_ASSIST_CMD_DATA_LENGTH_MSB 28 -#define TCL_ASSIST_CMD_DATA_LENGTH_MASK 0x1fff8000 - -#define TCL_ASSIST_CMD_TO_FW_TQM_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_TO_FW_TQM_LSB 29 -#define TCL_ASSIST_CMD_TO_FW_TQM_MSB 30 -#define TCL_ASSIST_CMD_TO_FW_TQM_MASK 0x60000000 - -#define TCL_ASSIST_CMD_RESERVED_2A_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_RESERVED_2A_LSB 31 -#define TCL_ASSIST_CMD_RESERVED_2A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_2A_MASK 0x80000000 - -#define TCL_ASSIST_CMD_RESERVED_3A_OFFSET 0x0000000c -#define TCL_ASSIST_CMD_RESERVED_3A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_3A_MSB 24 -#define TCL_ASSIST_CMD_RESERVED_3A_MASK 0x01ffffff - -#define TCL_ASSIST_CMD_METADATA_LENGTH_OFFSET 0x0000000c -#define TCL_ASSIST_CMD_METADATA_LENGTH_LSB 25 -#define TCL_ASSIST_CMD_METADATA_LENGTH_MSB 31 -#define TCL_ASSIST_CMD_METADATA_LENGTH_MASK 0xfe000000 - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_LSB 0 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MSB 7 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MASK 0x000000ff - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_LSB 8 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MSB 12 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MASK 0x00001f00 - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_LSB 13 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MSB 13 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MASK 0x00002000 - -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_LSB 14 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MSB 14 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00004000 - -#define TCL_ASSIST_CMD_FLOW_SELECT_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_FLOW_SELECT_LSB 15 -#define TCL_ASSIST_CMD_FLOW_SELECT_MSB 15 -#define TCL_ASSIST_CMD_FLOW_SELECT_MASK 0x00008000 - -#define TCL_ASSIST_CMD_HLOS_TID_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_HLOS_TID_LSB 16 -#define TCL_ASSIST_CMD_HLOS_TID_MSB 19 -#define TCL_ASSIST_CMD_HLOS_TID_MASK 0x000f0000 - -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_LSB 20 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MSB 20 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MASK 0x00100000 - -#define TCL_ASSIST_CMD_TOS_TC_VALUE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_LSB 21 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_MSB 28 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_MASK 0x1fe00000 - -#define TCL_ASSIST_CMD_RESERVED_4A_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_RESERVED_4A_LSB 29 -#define TCL_ASSIST_CMD_RESERVED_4A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_4A_MASK 0xe0000000 - -#define TCL_ASSIST_CMD_RESERVED_5A_OFFSET 0x00000014 -#define TCL_ASSIST_CMD_RESERVED_5A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_5A_MSB 15 -#define TCL_ASSIST_CMD_RESERVED_5A_MASK 0x0000ffff - -#define TCL_ASSIST_CMD_L3_TYPE_OFFSET 0x00000014 -#define TCL_ASSIST_CMD_L3_TYPE_LSB 16 -#define TCL_ASSIST_CMD_L3_TYPE_MSB 31 -#define TCL_ASSIST_CMD_L3_TYPE_MASK 0xffff0000 - -#define TCL_ASSIST_CMD_L4_PROTOCOL_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PROTOCOL_LSB 0 -#define TCL_ASSIST_CMD_L4_PROTOCOL_MSB 7 -#define TCL_ASSIST_CMD_L4_PROTOCOL_MASK 0x000000ff - -#define TCL_ASSIST_CMD_L4_PORT_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PORT_LSB 8 -#define TCL_ASSIST_CMD_L4_PORT_MSB 23 -#define TCL_ASSIST_CMD_L4_PORT_MASK 0x00ffff00 - -#define TCL_ASSIST_CMD_L4_PORT_TYPE_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_LSB 24 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_MSB 24 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_MASK 0x01000000 - -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_LSB 25 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MSB 25 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MASK 0x02000000 - -#define TCL_ASSIST_CMD_DA_IS_BCAST_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_DA_IS_BCAST_LSB 26 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MSB 26 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MASK 0x04000000 - -#define TCL_ASSIST_CMD_RESERVED_6A_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_RESERVED_6A_LSB 27 -#define TCL_ASSIST_CMD_RESERVED_6A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_6A_MASK 0xf8000000 - -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_OFFSET 0x0000001c -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_OFFSET 0x00000020 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_OFFSET 0x00000024 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_OFFSET 0x00000028 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_DA_OR_SA_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_IP_DA_OR_SA_LSB 0 -#define TCL_ASSIST_CMD_IP_DA_OR_SA_MSB 0 -#define TCL_ASSIST_CMD_IP_DA_OR_SA_MASK 0x00000001 - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_LSB 1 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MSB 6 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MASK 0x0000007e - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_LSB 7 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MSB 7 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MASK 0x00000080 - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_LSB 8 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MSB 8 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MASK 0x00000100 - -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_LSB 9 -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MSB 9 -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MASK 0x00000200 - -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_LSB 10 -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MSB 10 -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MASK 0x00000400 - -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_LSB 11 -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MSB 11 -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MASK 0x00000800 - -#define TCL_ASSIST_CMD_MSDU_COLOR_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_MSDU_COLOR_LSB 12 -#define TCL_ASSIST_CMD_MSDU_COLOR_MSB 13 -#define TCL_ASSIST_CMD_MSDU_COLOR_MASK 0x00003000 - -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_LSB 14 -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MSB 16 -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MASK 0x0001c000 - -#define TCL_ASSIST_CMD_TQM_NO_DROP_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TQM_NO_DROP_LSB 17 -#define TCL_ASSIST_CMD_TQM_NO_DROP_MSB 17 -#define TCL_ASSIST_CMD_TQM_NO_DROP_MASK 0x00020000 - -#define TCL_ASSIST_CMD_RESERVED_11A_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_RESERVED_11A_LSB 18 -#define TCL_ASSIST_CMD_RESERVED_11A_MSB 29 -#define TCL_ASSIST_CMD_RESERVED_11A_MASK 0x3ffc0000 - -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_LSB 30 -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MSB 30 -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MASK 0x40000000 - -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_LSB 31 -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MSB 31 -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MASK 0x80000000 - -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_LSB 0 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MSB 18 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MASK 0x0007ffff - -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_LSB 19 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MSB 19 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x00080000 - -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_LSB 20 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MSB 20 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MASK 0x00100000 - -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_LSB 21 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MSB 21 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MASK 0x00200000 - -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_LSB 22 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MSB 28 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MASK 0x1fc00000 - -#define TCL_ASSIST_CMD_RESERVED_12A_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_RESERVED_12A_LSB 29 -#define TCL_ASSIST_CMD_RESERVED_12A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_12A_MASK 0xe0000000 - -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_OFFSET 0x00000034 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_LSB 0 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MSB 31 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MASK 0xffffffff - -#define TCL_ASSIST_CMD_RESERVED_14A_OFFSET 0x00000038 -#define TCL_ASSIST_CMD_RESERVED_14A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_14A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_14A_MASK 0xffffffff - -#define TCL_ASSIST_CMD_RESERVED_15A_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_RESERVED_15A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_15A_MSB 19 -#define TCL_ASSIST_CMD_RESERVED_15A_MASK 0x000fffff - -#define TCL_ASSIST_CMD_RING_ID_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_RING_ID_LSB 20 -#define TCL_ASSIST_CMD_RING_ID_MSB 27 -#define TCL_ASSIST_CMD_RING_ID_MASK 0x0ff00000 - -#define TCL_ASSIST_CMD_LOOPING_COUNT_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_LOOPING_COUNT_LSB 28 -#define TCL_ASSIST_CMD_LOOPING_COUNT_MSB 31 -#define TCL_ASSIST_CMD_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tcl_status_ring.h b/drivers/staging/fw-api/hw/fig/v2/tcl_status_ring.h deleted file mode 100644 index 5a24217c95d5..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tcl_status_ring.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TCL_STATUS_RING_H_ -#define _TCL_STATUS_RING_H_ - -#define NUM_OF_DWORDS_TCL_STATUS_RING 8 - -struct tcl_status_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t gse_ctrl : 4, - ase_fse_sel : 1, - cache_op_res : 2, - index_search_en : 1, - msdu_cnt_n : 24; - uint32_t msdu_byte_cnt_n : 32; - uint32_t msdu_timestmp_n : 32; - uint32_t cmd_meta_data_31_0 : 32; - uint32_t cmd_meta_data_63_32 : 32; - uint32_t hash_indx_val : 20, - cache_set_num : 4, - reserved_5a : 8; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 20, - ring_id : 8, - looping_count : 4; -#else - uint32_t msdu_cnt_n : 24, - index_search_en : 1, - cache_op_res : 2, - ase_fse_sel : 1, - gse_ctrl : 4; - uint32_t msdu_byte_cnt_n : 32; - uint32_t msdu_timestmp_n : 32; - uint32_t cmd_meta_data_31_0 : 32; - uint32_t cmd_meta_data_63_32 : 32; - uint32_t reserved_5a : 8, - cache_set_num : 4, - hash_indx_val : 20; - uint32_t reserved_6a : 32; - uint32_t looping_count : 4, - ring_id : 8, - reserved_7a : 20; -#endif -}; - -#define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 -#define TCL_STATUS_RING_GSE_CTRL_LSB 0 -#define TCL_STATUS_RING_GSE_CTRL_MSB 3 -#define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f - -#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 -#define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 -#define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 -#define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 - -#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 -#define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 -#define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 -#define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 - -#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 - -#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 -#define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 -#define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 -#define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 - -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff - -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff - -#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c -#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 -#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 -#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff - -#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff - -#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 -#define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 -#define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 -#define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff - -#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 -#define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 -#define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 -#define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 - -#define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 -#define TCL_STATUS_RING_RESERVED_5A_LSB 24 -#define TCL_STATUS_RING_RESERVED_5A_MSB 31 -#define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 - -#define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 -#define TCL_STATUS_RING_RESERVED_6A_LSB 0 -#define TCL_STATUS_RING_RESERVED_6A_MSB 31 -#define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff - -#define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c -#define TCL_STATUS_RING_RESERVED_7A_LSB 0 -#define TCL_STATUS_RING_RESERVED_7A_MSB 19 -#define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff - -#define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c -#define TCL_STATUS_RING_RING_ID_LSB 20 -#define TCL_STATUS_RING_RING_ID_MSB 27 -#define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 - -#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 -#define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 -#define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tlv_hdr.h b/drivers/staging/fw-api/hw/fig/v2/tlv_hdr.h deleted file mode 100644 index a2defe7be508..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tlv_hdr.h +++ /dev/null @@ -1,634 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TLV_HDR_H_ -#define _TLV_HDR_H_ - -#define _TLV_USERID_WIDTH_ 6 - -#define _TLV_MRV_EN_LEN_WIDTH_ 9 -#define _TLV_MRV_DIS_LEN_WIDTH_ 12 - -#define _TLV_DATA_WIDTH_ 32 -#define _TLV_64_DATA_WIDTH_ 64 -#define _TLV_CDATA_WIDTH_ 32 -#define _TLV_77_DATA_WIDTH_ 77 -#define _TLV_CDATA_77_WIDTH_ 64 - -#define _TLV_TAG_WIDTH_ 10 -#define _TLV_CTAG_WIDTH_ 6 - -struct tlv_mlo_usr_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mlo_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_32_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_32_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : 6; -#else - uint32_t tlv_reserved : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_64_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_64_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_c_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata_lower_52 : 52; - uint64_t tlv_cdata_upper_12 : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - tlv_cdata_upper_12 : 12; - uint64_t tlv_cdata_lower_52 : 52, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_; -#endif -}; - -struct tlv_mlo_usr_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mlo_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_reserved : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mac_usr_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mac_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_reserved : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_usr_c_77_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata_lower_20 : 20; - uint32_t tlv_cdata_middle_32 : 32; - uint32_t tlv_cdata_upper_12 : 12, - tlv_compression : 1, - pad_77to96_bit : 19; - uint32_t pad_96to128_bit : 32; -#else - uint32_t tlv_cdata_lower_20 : 20, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_; - uint32_t tlv_cdata_middle_32 : 32; - uint32_t pad_77to96_bit : 20, - tlv_compression : 1, - tlv_cdata_upper_12 : 12; - uint32_t pad_96to128_bit : 32; -#endif -}; - -struct tlv_usr_32_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_reserved : 32; -#else - uint64_t tlv_reserved : 32, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_32_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : 6, - pad_32to64_bit : 32; -#else - uint64_t pad_32to64_bit : 32, - tlv_reserved : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_77_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint32_t pad_64to75_bit : 12, - tlv_compression : 1, - pad_77to95_bit : 19; -#else - uint32_t pad_77to95_bit : 19, - tlv_compression : 1, - pad_64to75_bit : 12; - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_77_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint32_t pad_64to75_bit : 12, - tlv_compression : 1, - pad_77to96_bit : 19; -#else - uint32_t pad_77to96_bit : 19, - tlv_compression : 1, - pad_64to75_bit : 12; - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_c_44_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata : _TLV_CDATA_WIDTH_, - pad_44to64_bit : 20; -#else - uint64_t tlv_cdata_lower_20 : 20, - pad_44to64_bit : 20, - tlv_cdata_upper_12 : 12; - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_, -#endif -}; - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tlv_tag_def.h b/drivers/staging/fw-api/hw/fig/v2/tlv_tag_def.h deleted file mode 100644 index 27ccee515a00..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tlv_tag_def.h +++ /dev/null @@ -1,1948 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TLV_TAG_DEF_ -#define _TLV_TAG_DEF_ - -typedef enum tlv_tag_def { - WIFIMACTX_CBF_START_E = 0 , - WIFIPHYRX_DATA_E = 1 , - WIFIPHYRX_CBF_DATA_RESP_E = 2 , - WIFIPHYRX_ABORT_REQUEST_E = 3 , - WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 , - WIFIMACTX_DATA_RESP_E = 5 , - WIFIMACTX_CBF_DATA_E = 6 , - WIFIMACTX_CBF_DONE_E = 7 , - WIFIPHYRX_LMR_DATA_RESP_E = 8 , - WIFIRXPCU_TO_UCODE_START_E = 9 , - WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 , - WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 , - WIFIRXPCU_TO_UCODE_FCS_STATUS_E = 12 , - WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 , - WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 , - WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 , - WIFIRXPCU_TO_UCODE_END_E = 16 , - WIFIPHYRX_RSSI_LEGACY_20MHZ_E = 17 , - WIFIPHYRX_NC_ABORT_REQUEST_E = 18 , - WIFIPHYRX_PKT_END_20MHZ_E = 19 , - WIFIPHYRX_NC_DATA_E = 20 , - WIFIMACRX_CBF_READ_REQUEST_E = 64 , - WIFIMACRX_CBF_DATA_REQUEST_E = 65 , - WIFIMACRX_EXPECT_NDP_RECEPTION_E = 66 , - WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 67 , - WIFIMACRX_NDP_TIMEOUT_E = 68 , - WIFIMACRX_ABORT_ACK_E = 69 , - WIFIMACRX_REQ_IMPLICIT_FB_E = 70 , - WIFIMACRX_CHAIN_MASK_E = 71 , - WIFIMACRX_NAP_USER_E = 72 , - WIFIMACRX_ABORT_REQUEST_E = 73 , - WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 74 , - WIFIPHYTX_ABORT_ACK_E = 75 , - WIFIPHYTX_ABORT_REQUEST_E = 76 , - WIFIPHYTX_PKT_END_E = 77 , - WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 78 , - WIFIPHYTX_REQUEST_CTRL_INFO_E = 79 , - WIFIPHYTX_DATA_REQUEST_E = 80 , - WIFIPHYTX_BF_CV_LOADING_DONE_E = 81 , - WIFIPHYTX_NAP_ACK_E = 82 , - WIFIPHYTX_NAP_DONE_E = 83 , - WIFIPHYTX_OFF_ACK_E = 84 , - WIFIPHYTX_ON_ACK_E = 85 , - WIFIPHYTX_SYNTH_OFF_ACK_E = 86 , - WIFIPHYTX_DEBUG16_E = 87 , - WIFIMACTX_ABORT_REQUEST_E = 88 , - WIFIMACTX_ABORT_ACK_E = 89 , - WIFIMACTX_PKT_END_E = 90 , - WIFIMACTX_PRE_PHY_DESC_E = 91 , - WIFIMACTX_BF_PARAMS_COMMON_E = 92 , - WIFIMACTX_BF_PARAMS_PER_USER_E = 93 , - WIFIMACTX_PREFETCH_CV_E = 94 , - WIFIMACTX_USER_DESC_COMMON_E = 95 , - WIFIMACTX_USER_DESC_PER_USER_E = 96 , - WIFIEXAMPLE_USER_TLV_16_E = 97 , - WIFIEXAMPLE_TLV_16_E = 98 , - WIFIMACTX_PHY_OFF_E = 99 , - WIFIMACTX_PHY_ON_E = 100 , - WIFIMACTX_SYNTH_OFF_E = 101 , - WIFIMACTX_EXPECT_CBF_COMMON_E = 102 , - WIFIMACTX_EXPECT_CBF_PER_USER_E = 103 , - WIFIMACTX_PHY_DESC_E = 104 , - WIFIMACTX_L_SIG_A_E = 105 , - WIFIMACTX_L_SIG_B_E = 106 , - WIFIMACTX_HT_SIG_E = 107 , - WIFIMACTX_VHT_SIG_A_E = 108 , - WIFIMACTX_VHT_SIG_B_SU20_E = 109 , - WIFIMACTX_VHT_SIG_B_SU40_E = 110 , - WIFIMACTX_VHT_SIG_B_SU80_E = 111 , - WIFIMACTX_VHT_SIG_B_SU160_E = 112 , - WIFIMACTX_VHT_SIG_B_MU20_E = 113 , - WIFIMACTX_VHT_SIG_B_MU40_E = 114 , - WIFIMACTX_VHT_SIG_B_MU80_E = 115 , - WIFIMACTX_VHT_SIG_B_MU160_E = 116 , - WIFIMACTX_SERVICE_E = 117 , - WIFIMACTX_HE_SIG_A_SU_E = 118 , - WIFIMACTX_HE_SIG_A_MU_DL_E = 119 , - WIFIMACTX_HE_SIG_A_MU_UL_E = 120 , - WIFIMACTX_HE_SIG_B1_MU_E = 121 , - WIFIMACTX_HE_SIG_B2_MU_E = 122 , - WIFIMACTX_HE_SIG_B2_OFDMA_E = 123 , - WIFIMACTX_DELETE_CV_E = 124 , - WIFIMACTX_MU_UPLINK_COMMON_E = 125 , - WIFIMACTX_MU_UPLINK_USER_SETUP_E = 126 , - WIFIMACTX_OTHER_TRANSMIT_INFO_E = 127 , - WIFIMACTX_PHY_NAP_E = 128 , - WIFIMACTX_DEBUG_E = 129 , - WIFIPHYRX_ABORT_ACK_E = 130 , - WIFIPHYRX_GENERATED_CBF_DETAILS_E = 131 , - WIFIPHYRX_RSSI_LEGACY_E = 132 , - WIFIPHYRX_RSSI_HT_E = 133 , - WIFIPHYRX_USER_INFO_E = 134 , - WIFIPHYRX_PKT_END_E = 135 , - WIFIPHYRX_DEBUG_E = 136 , - WIFIPHYRX_CBF_TRANSFER_DONE_E = 137 , - WIFIPHYRX_CBF_TRANSFER_ABORT_E = 138 , - WIFIPHYRX_L_SIG_A_E = 139 , - WIFIPHYRX_L_SIG_B_E = 140 , - WIFIPHYRX_HT_SIG_E = 141 , - WIFIPHYRX_VHT_SIG_A_E = 142 , - WIFIPHYRX_VHT_SIG_B_SU20_E = 143 , - WIFIPHYRX_VHT_SIG_B_SU40_E = 144 , - WIFIPHYRX_VHT_SIG_B_SU80_E = 145 , - WIFIPHYRX_VHT_SIG_B_SU160_E = 146 , - WIFIPHYRX_VHT_SIG_B_MU20_E = 147 , - WIFIPHYRX_VHT_SIG_B_MU40_E = 148 , - WIFIPHYRX_VHT_SIG_B_MU80_E = 149 , - WIFIPHYRX_VHT_SIG_B_MU160_E = 150 , - WIFIPHYRX_HE_SIG_A_SU_E = 151 , - WIFIPHYRX_HE_SIG_A_MU_DL_E = 152 , - WIFIPHYRX_HE_SIG_A_MU_UL_E = 153 , - WIFIPHYRX_HE_SIG_B1_MU_E = 154 , - WIFIPHYRX_HE_SIG_B2_MU_E = 155 , - WIFIPHYRX_HE_SIG_B2_OFDMA_E = 156 , - WIFIPHYRX_OTHER_RECEIVE_INFO_E = 157 , - WIFIPHYRX_COMMON_USER_INFO_E = 158 , - WIFIPHYRX_DATA_DONE_E = 159 , - WIFICOEX_TX_REQ_E = 160 , - WIFIDUMMY_E = 161 , - WIFIEXAMPLE_TLV_32_NAME_E = 162 , - WIFIMPDU_LIMIT_E = 163 , - WIFINA_LENGTH_END_E = 164 , - WIFIOLE_BUF_STATUS_E = 165 , - WIFIPCU_PPDU_SETUP_DONE_E = 166 , - WIFIPCU_PPDU_SETUP_END_E = 167 , - WIFIPCU_PPDU_SETUP_INIT_E = 168 , - WIFIPCU_PPDU_SETUP_START_E = 169 , - WIFIPDG_FES_SETUP_E = 170 , - WIFIPDG_RESPONSE_E = 171 , - WIFIPDG_TX_REQ_E = 172 , - WIFISCH_WAIT_INSTR_E = 173 , - WIFIMACTX_SWITCH_TO_MAIN_E = 174 , - WIFIPHYTX_LINK_STATE_E = 175 , - WIFIAUX_PPDU_END_E = 176 , - WIFITQM_GEN_MPDU_LENGTH_LIST_E = 177 , - WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 178 , - WIFITQM_GEN_MPDUS_E = 179 , - WIFITQM_GEN_MPDUS_STATUS_E = 180 , - WIFITQM_REMOVE_MPDU_E = 181 , - WIFITQM_REMOVE_MPDU_STATUS_E = 182 , - WIFITQM_REMOVE_MSDU_E = 183 , - WIFITQM_REMOVE_MSDU_STATUS_E = 184 , - WIFITQM_UPDATE_TX_MPDU_COUNT_E = 185 , - WIFITQM_WRITE_CMD_E = 186 , - WIFIOFDMA_TRIGGER_DETAILS_E = 187 , - WIFITX_DATA_E = 188 , - WIFITX_FES_SETUP_E = 189 , - WIFIRX_PACKET_E = 190 , - WIFIEXPECTED_RESPONSE_E = 191 , - WIFITX_MPDU_END_E = 192 , - WIFITX_MPDU_START_E = 193 , - WIFITX_MSDU_END_E = 194 , - WIFITX_MSDU_START_E = 195 , - WIFITX_SW_MODE_SETUP_E = 196 , - WIFITXPCU_BUFFER_STATUS_E = 197 , - WIFITXPCU_USER_BUFFER_STATUS_E = 198 , - WIFIDATA_TO_TIME_CONFIG_E = 199 , - WIFIEXAMPLE_USER_TLV_32_E = 200 , - WIFIMPDU_INFO_E = 201 , - WIFIPDG_USER_SETUP_E = 202 , - WIFITX_11AH_SETUP_E = 203 , - WIFITX_PEER_ENTRY_E = 205 , - WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 206 , - WIFIEXAMPLE_USER_TLV_44_E = 207 , - WIFITX_FLUSH_E = 208 , - WIFITX_FLUSH_REQ_E = 209 , - WIFITQM_WRITE_CMD_STATUS_E = 210 , - WIFITQM_GET_MPDU_QUEUE_STATS_E = 211 , - WIFITQM_GET_MSDU_FLOW_STATS_E = 212 , - WIFIEXAMPLE_USER_CTLV_44_E = 213 , - WIFITX_FES_STATUS_START_E = 214 , - WIFITX_FES_STATUS_USER_PPDU_E = 215 , - WIFITX_FES_STATUS_USER_RESPONSE_E = 216 , - WIFITX_FES_STATUS_END_E = 217 , - WIFIRX_TRIG_INFO_E = 218 , - WIFIRXPCU_TX_SETUP_CLEAR_E = 219 , - WIFIRX_FRAME_BITMAP_REQ_E = 220 , - WIFIRX_FRAME_BITMAP_ACK_E = 221 , - WIFICOEX_RX_STATUS_E = 222 , - WIFIRX_START_PARAM_E = 223 , - WIFIRX_PPDU_START_E = 224 , - WIFIRX_PPDU_END_E = 225 , - WIFIRX_MPDU_START_E = 226 , - WIFIRX_MPDU_END_E = 227 , - WIFIRX_MSDU_START_E = 228 , - WIFIRX_MSDU_END_E = 229 , - WIFIRX_ATTENTION_E = 230 , - WIFIRECEIVED_RESPONSE_INFO_E = 231 , - WIFIRX_PHY_SLEEP_E = 232 , - WIFIRX_HEADER_E = 233 , - WIFIRX_PEER_ENTRY_E = 234 , - WIFIRX_FLUSH_E = 235 , - WIFIRX_RESPONSE_REQUIRED_INFO_E = 236 , - WIFIRX_FRAMELESS_BAR_DETAILS_E = 237 , - WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 238 , - WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 239 , - WIFITX_CBF_INFO_E = 240 , - WIFIPCU_PPDU_SETUP_USER_E = 241 , - WIFIRX_MPDU_PCU_START_E = 242 , - WIFIRX_PM_INFO_E = 243 , - WIFIRX_USER_PPDU_END_E = 244 , - WIFIRX_PRE_PPDU_START_E = 245 , - WIFIRX_PREAMBLE_E = 246 , - WIFITX_FES_SETUP_COMPLETE_E = 247 , - WIFITX_LAST_MPDU_FETCHED_E = 248 , - WIFITXDMA_STOP_REQUEST_E = 249 , - WIFIRXPCU_SETUP_E = 250 , - WIFIRXPCU_USER_SETUP_E = 251 , - WIFITX_FES_STATUS_ACK_OR_BA_E = 252 , - WIFITQM_ACKED_MPDU_E = 253 , - WIFICOEX_TX_RESP_E = 254 , - WIFICOEX_TX_STATUS_E = 255 , - WIFIMACTX_COEX_PHY_CTRL_E = 256 , - WIFICOEX_STATUS_BROADCAST_E = 257 , - WIFIRESPONSE_START_STATUS_E = 258 , - WIFIRESPONSE_END_STATUS_E = 259 , - WIFICRYPTO_STATUS_E = 260 , - WIFIRECEIVED_TRIGGER_INFO_E = 261 , - WIFICOEX_TX_STOP_CTRL_E = 262 , - WIFIRX_PPDU_ACK_REPORT_E = 263 , - WIFIRX_PPDU_NO_ACK_REPORT_E = 264 , - WIFISCH_COEX_STATUS_E = 265 , - WIFISCHEDULER_COMMAND_STATUS_E = 266 , - WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 267 , - WIFITX_FES_STATUS_PROT_E = 268 , - WIFITX_FES_STATUS_START_PPDU_E = 269 , - WIFITX_FES_STATUS_START_PROT_E = 270 , - WIFITXPCU_PHYTX_DEBUG32_E = 271 , - WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 272 , - WIFITX_MPDU_COUNT_TRANSFER_END_E = 273 , - WIFIWHO_ANCHOR_OFFSET_E = 274 , - WIFIWHO_ANCHOR_VALUE_E = 275 , - WIFIWHO_CCE_INFO_E = 276 , - WIFIWHO_COMMIT_E = 277 , - WIFIWHO_COMMIT_DONE_E = 278 , - WIFIWHO_FLUSH_E = 279 , - WIFIWHO_L2_LLC_E = 280 , - WIFIWHO_L2_PAYLOAD_E = 281 , - WIFIWHO_L3_CHECKSUM_E = 282 , - WIFIWHO_L3_INFO_E = 283 , - WIFIWHO_L4_CHECKSUM_E = 284 , - WIFIWHO_L4_INFO_E = 285 , - WIFIWHO_MSDU_E = 286 , - WIFIWHO_MSDU_MISC_E = 287 , - WIFIWHO_PACKET_DATA_E = 288 , - WIFIWHO_PACKET_HDR_E = 289 , - WIFIWHO_PPDU_END_E = 290 , - WIFIWHO_PPDU_START_E = 291 , - WIFIWHO_TSO_E = 292 , - WIFIWHO_WMAC_HEADER_PV0_E = 293 , - WIFIWHO_WMAC_HEADER_PV1_E = 294 , - WIFIWHO_WMAC_IV_E = 295 , - WIFIMPDU_INFO_END_E = 296 , - WIFIMPDU_INFO_BITMAP_E = 297 , - WIFITX_QUEUE_EXTENSION_E = 298 , - WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 299 , - WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 300 , - WIFITQM_ACKED_MPDU_STATUS_E = 301 , - WIFITQM_ADD_MSDU_STATUS_E = 302 , - WIFITQM_LIST_GEN_DONE_E = 303 , - WIFIWHO_TERMINATE_E = 304 , - WIFITX_LAST_MPDU_END_E = 305 , - WIFITX_CV_DATA_E = 306 , - WIFIPPDU_TX_END_E = 307 , - WIFIPROT_TX_END_E = 308 , - WIFIMPDU_INFO_GLOBAL_END_E = 309 , - WIFITQM_SCH_INSTR_GLOBAL_END_E = 310 , - WIFIRX_PPDU_END_USER_STATS_E = 311 , - WIFIRX_PPDU_END_USER_STATS_EXT_E = 312 , - WIFITQM_FLUSH_CACHE_E = 321 , - WIFITQM_UNBLOCK_CACHE_E = 322 , - WIFITQM_FLUSH_CACHE_STATUS_E = 323 , - WIFITQM_UNBLOCK_CACHE_STATUS_E = 324 , - WIFIRX_PPDU_END_STATUS_DONE_E = 325 , - WIFIRX_STATUS_BUFFER_DONE_E = 326 , - WIFISCHEDULER_MLO_SW_MSG_STATUS_E = 327 , - WIFISCHEDULER_TXOP_DURATION_TRIGGER_E = 328 , - WIFITX_DATA_SYNC_E = 329 , - WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 330 , - WIFITQM_GET_MPDU_HEAD_INFO_E = 331 , - WIFITQM_SYNC_CMD_E = 332 , - WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 333 , - WIFITQM_SYNC_CMD_STATUS_E = 334 , - WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 335 , - WIFITCC_TQM_WRAPPER_CMD_E = 336 , - WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 340 , - WIFIEXAMPLE_USER_TLV_32_NAME_E = 341 , - WIFIRX_PPDU_START_USER_INFO_E = 342 , - WIFIRX_RING_MASK_E = 343 , - WIFICOEX_MAC_NAP_E = 344 , - WIFIRXPCU_PPDU_END_INFO_E = 345 , - WIFIWHO_MESH_CONTROL_E = 346 , - WIFIPDG_SW_MODE_BW_START_E = 347 , - WIFIPDG_SW_MODE_BW_END_E = 348 , - WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 349 , - WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 350 , - WIFISCHEDULER_END_E = 351 , - WIFIRX_PPDU_START_DROPPED_E = 352 , - WIFIRX_PPDU_END_DROPPED_E = 353 , - WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 354 , - WIFIRX_MPDU_START_DROPPED_E = 355 , - WIFIRX_MSDU_START_DROPPED_E = 356 , - WIFIRX_MSDU_END_DROPPED_E = 357 , - WIFIRX_MPDU_END_DROPPED_E = 358 , - WIFIRX_ATTENTION_DROPPED_E = 359 , - WIFITXPCU_USER_SETUP_E = 360 , - WIFIRXPCU_USER_SETUP_EXT_E = 361 , - WIFICMD_PART_0_END_E = 362 , - WIFIMACTX_SYNTH_ON_E = 363 , - WIFISCH_CRITICAL_TLV_REFERENCE_E = 364 , - WIFITQM_MPDU_GLOBAL_START_E = 365 , - WIFIEXAMPLE_TLV_32_E = 366 , - WIFITQM_UPDATE_TX_MSDU_FLOW_E = 367 , - WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 368 , - WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 369 , - WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 370 , - WIFITQM_2_SCH_MPDU_AVAILABLE_E = 372 , - WIFIPDG_TRIG_RESPONSE_E = 373 , - WIFITRIGGER_RESPONSE_TX_DONE_E = 374 , - WIFIABORT_FROM_PHYRX_DETAILS_E = 375 , - WIFISCH_TQM_CMD_WRAPPER_E = 376 , - WIFIMPDUS_AVAILABLE_E = 377 , - WIFIRECEIVED_RESPONSE_INFO_PART2_E = 378 , - WIFIPHYRX_TX_START_TIMING_E = 379 , - WIFITXPCU_PREAMBLE_DONE_E = 380 , - WIFINDP_PREAMBLE_DONE_E = 381 , - WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 382 , - WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 383 , - WIFIMACTX_CLEAR_PREV_TX_INFO_E = 384 , - WIFITX_PUNCTURE_SETUP_E = 385 , - WIFIR2R_STATUS_END_E = 386 , - WIFIMACTX_PREFETCH_CV_COMMON_E = 387 , - WIFIEND_OF_FLUSH_MARKER_E = 388 , - WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 389 , - WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 390 , - WIFIRECEIVED_RESPONSE_USER_7_0_E = 391 , - WIFIRECEIVED_RESPONSE_USER_15_8_E = 392 , - WIFIRECEIVED_RESPONSE_USER_23_16_E = 393 , - WIFIRECEIVED_RESPONSE_USER_31_24_E = 394 , - WIFIRECEIVED_RESPONSE_USER_36_32_E = 395 , - WIFITX_LOOPBACK_SETUP_E = 396 , - WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 397 , - WIFISCH_WAIT_INSTR_TX_PATH_E = 398 , - WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 399 , - WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 400 , - WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 401 , - WIFITX_WUR_DATA_E = 402 , - WIFIRX_PPDU_END_START_E = 403 , - WIFIRX_PPDU_END_MIDDLE_E = 404 , - WIFIRX_PPDU_END_LAST_E = 405 , - WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 406 , - WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 407 , - WIFISRP_INFO_E = 408 , - WIFIOBSS_SR_INFO_E = 409 , - WIFISCHEDULER_SW_MSG_STATUS_E = 410 , - WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 411 , - WIFIRXPCU_SETUP_COMPLETE_E = 412 , - WIFIMACTX_MCC_SWITCH_E = 413 , - WIFIMACTX_MCC_SWITCH_BACK_E = 414 , - WIFIPHYTX_MCC_SWITCH_ACK_E = 415 , - WIFIPHYTX_MCC_SWITCH_BACK_ACK_E = 416 , - WIFIPHYTX_EMLSR_PRE_SWITCH_ACK_E = 417 , - WIFILMR_TX_END_E = 418 , - WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 419 , - WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 420 , - WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 421 , - WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 422 , - WIFISCH_TLV_WRAPPER_E = 423 , - WIFISCHEDULER_STATUS_WRAPPER_E = 424 , - WIFIMPDU_INFO_6X_E = 425 , - WIFIMACTX___RESERVED_G_0013 = 426 , - WIFIMACTX_U_SIG_EHT_SU_MU_E = 427 , - WIFIMACTX_U_SIG_EHT_TB_E = 428 , - WIFICOEX_TLV_ACC_TLV_TAG0_CFG_E = 429 , - WIFICOEX_TLV_ACC_TLV_TAG1_CFG_E = 430 , - WIFICOEX_TLV_ACC_TLV_TAG2_CFG_E = 431 , - WIFIPHYRX_U_SIG_EHT_SU_MU_E = 432 , - WIFIPHYRX_U_SIG_EHT_TB_E = 433 , - WIFICOEX_TLV_ACC_TLV_TAG3_CFG_E = 434 , - WIFICOEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 435 , - WIFITX_PUNCTURE_6PATTERNS_SETUP_E = 436 , - WIFIMACRX_LMR_READ_REQUEST_E = 437 , - WIFIMACRX_LMR_DATA_REQUEST_E = 438 , - WIFIPHYRX_LMR_TRANSFER_DONE_E = 439 , - WIFIPHYRX_LMR_TRANSFER_ABORT_E = 440 , - WIFIPHYRX_LMR_READ_REQUEST_ACK_E = 441 , - WIFIMACRX_SECURE_LTF_SEQ_PTR_E = 442 , - WIFIPHYRX_USER_INFO_MU_UL_E = 443 , - WIFIMPDU_QUEUE_OVERVIEW_E = 444 , - WIFISCHEDULER_NAV_INFO_E = 445 , - WIFIMACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E = 446 , - WIFILMR_PEER_ENTRY_E = 447 , - WIFILMR_MPDU_START_E = 448 , - WIFILMR_DATA_E = 449 , - WIFILMR_MPDU_END_E = 450 , - WIFIRX_FRAME_1K_BITMAP_ACK_E = 452 , - WIFITX_FES_STATUS_1K_BA_E = 453 , - WIFITQM_ACKED_1K_MPDU_E = 454 , - WIFIMACRX_INBSS_OBSS_IND_E = 455 , - WIFIPHYRX_LOCATION_E = 456 , - WIFIMLO_TX_NOTIFICATION_SU_E = 457 , - WIFIMLO_TX_NOTIFICATION_MU_E = 458 , - WIFIMLO_TX_REQ_SU_E = 459 , - WIFIMLO_TX_REQ_MU_E = 460 , - WIFIMLO_TX_RESP_E = 461 , - WIFIMLO_RX_NOTIFICATION_E = 462 , - WIFIMLO_BKOFF_TRUNC_REQ_E = 463 , - WIFIMLO_TBTT_NOTIFICATION_E = 464 , - WIFIMLO_MESSAGE_E = 465 , - WIFIMLO_TS_SYNC_MSG_E = 466 , - WIFIMLO_FES_SETUP_E = 467 , - WIFIMLO_PDG_FES_SETUP_SU_E = 468 , - WIFIMLO_PDG_FES_SETUP_MU_E = 469 , - WIFIMPDU_INFO_1K_BITMAP_E = 470 , - WIFIMON_BUFFER_ADDR_E = 471 , - WIFITX_FRAG_STATE_E = 472 , - WIFIMACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 473 , - WIFIMACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 474 , - WIFIMACTX_EHT_SIG_USR_OFDMA_E = 475 , - WIFIMACTX_U_SIG_UHR_SU_MU_E = 476 , - WIFIMACTX_U_SIG_UHR_TB_E = 477 , - WIFITX_MPDU_COMPRESSED_DETAILS_TLV_E = 478 , - WIFITX_MSDU_COMPRESSED_DETAILS_TLV_E = 479 , - WIFITX_MSDU_COMPONENT_DETAILS_TLV_E = 480 , - WIFIPHYRX_EHT_SIG_USR_OFDMA_E = 481 , - WIFISCHEDULER_IU_TEMPLATE_ID_E = 482 , - WIFIPHYRX_PKT_END_PART1_E = 483 , - WIFIMACTX_EXPECT_NDP_RECEPTION_E = 484 , - WIFIMACTX_SECURE_LTF_SEQ_PTR_E = 485 , - WIFITX_MPDU_LENGTH_AND_RESTRICTIONS_E = 486 , - WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E = 487 , - WIFIPHYRX___RESERVED_G_0014 = 488 , - WIFIPHYTX_LOCATION_E = 489 , - WIFIPHYTX___RESERVED_G_0014 = 490 , - WIFIMPDU_LENGTH_STRUCTS_START_E = 491 , - WIFIMACTX_EHT_SIG_USR_SU_E = 492 , - WIFIMACTX_EHT_SIG_USR_MU_MIMO_E = 493 , - WIFIPHYRX_EHT_SIG_USR_SU_E = 494 , - WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E = 495 , - WIFIPHYRX_GENERIC_U_SIG_E = 496 , - WIFIPHYRX_GENERIC_EHT_OR_UHR_SIG_E = 497 , - WIFIOVERWRITE_RESP_START_E = 498 , - WIFIOVERWRITE_RESP_PREAMBLE_INFO_E = 499 , - WIFIOVERWRITE_RESP_FRAME_INFO_E = 500 , - WIFIOVERWRITE_RESP_END_E = 501 , - WIFIRXPCU_EARLY_RX_INDICATION_E = 502 , - WIFIMON_DROP_E = 503 , - WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E = 504 , - WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 505 , - WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E = 506 , - WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 507 , - WIFIMACTX_PREFETCH_CV_DMA_E = 508 , - WIFIMACTX_PREFETCH_CV_PER_USER_E = 509 , - WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 510 , - WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E = 511 , - WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E = 512 , - WIFIRANGING_USER_DETAILS_E = 513 , - WIFIPHYTX_CV_CORR_STATUS_E = 514 , - WIFIPHYTX_CV_CORR_COMMON_E = 515 , - WIFIPHYTX_CV_CORR_USER_E = 516 , - WIFIMACTX_CV_CORR_COMMON_E = 517 , - WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E = 518 , - WIFIBW_PUNCTURE_EVAL_WRAPPER_E = 519 , - WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E = 520 , - WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E = 521 , - WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E = 522 , - WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 523 , - WIFIRX_PPDU_END_USER_STATS_EXT2_E = 524 , - WIFIFW2SW_MON_E = 525 , - WIFIWSI_DIRECT_MESSAGE_E = 526 , - WIFIMACTX_EMLSR_PRE_SWITCH_E = 527 , - WIFIMACTX_EMLSR_SWITCH_E = 528 , - WIFIMACTX_EMLSR_SWITCH_BACK_E = 529 , - WIFIPHYTX_EMLSR_SWITCH_ACK_E = 530 , - WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E = 531 , - WIFIEAD_COMMAND_E = 532 , - WIFIEAD_LEGACY_STATUS_CONTROL_E = 533 , - WIFIEAD_LEGACY_INTERRUPT_CONTROL_E = 534 , - WIFITPI_TX_INITIALIZATION_CONFIG_E = 535 , - WIFITPI_ENABLE_RESPONSE_TIMEOUT_E = 536 , - WIFITPI_LEGACY_STATUS_CONTROL_E = 537 , - WIFITPI_LEGACY_INTERRUPT_CONTROL_E = 538 , - WIFITPI_MPDU_START_E = 539 , - WIFITPI_MPDU_CONTINUATION_E = 540 , - WIFITPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E = 541 , - WIFITPI_SEND_TLV_TO_PHYTX_E = 542 , - WIFITPI_TX_START_TIME_ARRIVED_E = 543 , - WIFITPI_STATUS_E = 544 , - WIFITPI_ERROR_STATUS_E = 545 , - WIFITPI_TIMESTAMP_STATUS_E = 546 , - WIFIRPI_SEND_TLV_TO_PHYRX_E = 547 , - WIFIRPI_LEGACY_STATUS_CONTROL_E = 548 , - WIFIRPI_LEGACY_INTERRUPT_CONTROL_E = 549 , - WIFIRPI_STATUS_E = 550 , - WIFIRPI_ERROR_STATUS_E = 551 , - WIFIRPI_TIMESTAMP_STATUS_E = 552 , - WIFIRPI_RX_FRAME_UPDATE_STATUS_E = 553 , - WIFITCC_PUSH_TRANSMIT_COMMAND_E = 554 , - WIFITCC_TLV_FETCH_E = 555 , - WIFITCC_LEGACY_STATUS_CONTROL_E = 556 , - WIFITCC_LEGACY_INTERRUPT_CONTROL_E = 557 , - WIFITCC_STATUS_E = 558 , - WIFITCC_ERROR_STATUS_E = 559 , - WIFITCC_TIMESTAMP_STATUS_E = 560 , - WIFITCC_PRE_BACKOFF_CMD_AVAILABLE_E = 561 , - WIFITCC_SCHEDULER_CMD_E = 562 , - WIFITCC_BURST_CMD_AVAILABLE_E = 563 , - WIFIRPI_NON_DATA_CTLV_44_FROM_PHYRX_E = 564 , - WIFIEAD_RING_AIR_TIME_REFERENCE_E = 565 , - WIFIRPI_FETCH_INFO_FROM_EXT_MEM_E = 566 , - WIFIRPI_WRITE_INFO_TO_EXT_MEM_E = 567 , - WIFIRPI_INIT_CBF_DATA_RESP_ADDR_E = 568 , - WIFIRPI_INIT_LMR_DATA_RESP_ADDR_E = 569 , - WIFITPI_SEND_CBF_DATA_TO_PHYTX_E = 570 , - WIFITPI_SEND_CTLV_44_TO_PHYTX_E = 571 , - WIFITCC_FES_END_MESSAGE_E = 572 , - WIFITPI_TX_FRAME_UPDATE_STATUS_E = 573 , - WIFITPI_DISABLE_RESPONSE_TIMEOUT_E = 574 , - WIFIEAD_MPDU_DATA_FETCH_CONTINUATION_E = 575 , - WIFIEAD_MSDU_STATUS_START_E = 576 , - WIFIEAD_MSDU_STATUS_DETAILS_E = 577 , - WIFIMACTX_UHR_SIG_USR_SU_E = 578 , - WIFIMACTX_UHR_SIG_USR_MU_MIMO_E = 579 , - WIFIMACTX_UHR_SIG_USR_OFDMA_E = 580 , - WIFIMACTX_ELR_SIG_UHR_SU_E = 581 , - WIFICOEX_BLACKOUT_DETAILS_E = 582 , - WIFIPEER_BLACKOUT_DETAILS_E = 583 , - WIFIMACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E = 584 , - WIFIHDR_CTRL_PROT_PEER_ENTRY_E = 585 , - WIFIHDR_CTRL_PROT_MPDU_START_E = 586 , - WIFIHDR_CTRL_PROT_DATA_E = 587 , - WIFIHDR_CTRL_PROT_MPDU_END_E = 588 , - WIFIHDR_CTRL_PROT_MIC_STATUS_E = 589 , - WIFIHDR_CTRL_PROT_PEER_INFO_E = 590 , - WIFIHDR_CTRL_PROT_PEER_ENTRY_DONE_E = 591 , - WIFIMACTX_U_SIG_UHR_ELR_SU_E = 592 , - WIFIMACTX_U_SIG_UHR_COBF_E = 593 , - WIFIMACTX_UHR_SIG_USR_COBF_E = 594 , - WIFIMACTX_U_SIG_UHR_COSR_E = 595 , - WIFIMACTX_UHR_SIG_USR_COSR_E = 596 , - WIFIOVERWRITE_CFP_INFO_E = 597 , - WIFISPARE_REUSE_TAG_0_E = 598 , - WIFISPARE_REUSE_TAG_1_E = 599 , - WIFISPARE_REUSE_TAG_2_E = 600 , - WIFISPARE_REUSE_TAG_3_E = 601 , - WIFISPARE_REUSE_TAG_4_E = 602 , - WIFISPARE_REUSE_TAG_5_E = 603 , - WIFISPARE_REUSE_TAG_6_E = 604 , - WIFISPARE_REUSE_TAG_7_E = 605 , - WIFISPARE_REUSE_TAG_8_E = 606 , - WIFISPARE_REUSE_TAG_9_E = 607 , - WIFISPARE_REUSE_TAG_10_E = 608 , - WIFISPARE_REUSE_TAG_11_E = 609 , - WIFISPARE_REUSE_TAG_12_E = 610 , - WIFISPARE_REUSE_TAG_13_E = 611 , - WIFISPARE_REUSE_TAG_14_E = 612 , - WIFISPARE_REUSE_TAG_15_E = 613 , - WIFISPARE_REUSE_TAG_16_E = 614 , - WIFISPARE_REUSE_TAG_17_E = 615 , - WIFISPARE_REUSE_TAG_18_E = 616 , - WIFISPARE_REUSE_TAG_19_E = 617 , - WIFISPARE_REUSE_TAG_20_E = 618 , - WIFISPARE_REUSE_TAG_21_E = 619 , - WIFISPARE_REUSE_TAG_22_E = 620 , - WIFISPARE_REUSE_TAG_23_E = 621 , - WIFISPARE_REUSE_TAG_24_E = 622 , - WIFISPARE_REUSE_TAG_25_E = 623 , - WIFISPARE_REUSE_TAG_26_E = 624 , - WIFISPARE_REUSE_TAG_27_E = 625 , - WIFISPARE_REUSE_TAG_28_E = 626 , - WIFISPARE_REUSE_TAG_29_E = 627 , - WIFISPARE_REUSE_TAG_30_E = 628 , - WIFISPARE_REUSE_TAG_31_E = 629 , - WIFISPARE_REUSE_TAG_32_E = 630 , - WIFISPARE_REUSE_TAG_33_E = 631 , - WIFISPARE_REUSE_TAG_34_E = 632 , - WIFISPARE_REUSE_TAG_35_E = 633 , - WIFISPARE_REUSE_TAG_36_E = 634 , - WIFISPARE_REUSE_TAG_37_E = 635 , - WIFISPARE_REUSE_TAG_38_E = 636 , - WIFISPARE_REUSE_TAG_39_E = 637 , - WIFISPARE_REUSE_TAG_40_E = 638 , - WIFISPARE_REUSE_TAG_41_E = 639 , - WIFISPARE_REUSE_TAG_42_E = 640 , - WIFISPARE_REUSE_TAG_43_E = 641 , - WIFISPARE_REUSE_TAG_44_E = 642 , - WIFISPARE_REUSE_TAG_45_E = 643 , - WIFISPARE_REUSE_TAG_46_E = 644 , - WIFISPARE_REUSE_TAG_47_E = 645 , - WIFISPARE_REUSE_TAG_48_E = 646 , - WIFISPARE_REUSE_TAG_49_E = 647 , - WIFISPARE_REUSE_TAG_50_E = 648 , - WIFISPARE_REUSE_TAG_51_E = 649 , - WIFISPARE_REUSE_TAG_52_E = 650 , - WIFISPARE_REUSE_TAG_53_E = 651 , - WIFISPARE_REUSE_TAG_54_E = 652 , - WIFISPARE_REUSE_TAG_55_E = 653 , - WIFISPARE_REUSE_TAG_56_E = 654 , - WIFISPARE_REUSE_TAG_57_E = 655 , - WIFISPARE_REUSE_TAG_58_E = 656 , - WIFISPARE_REUSE_TAG_59_E = 657 , - WIFISPARE_REUSE_TAG_60_E = 658 , - WIFISPARE_REUSE_TAG_61_E = 659 , - WIFISPARE_REUSE_TAG_62_E = 660 , - WIFISPARE_REUSE_TAG_63_E = 661 , - WIFISPARE_REUSE_TAG_64_E = 662 , - WIFISPARE_REUSE_TAG_65_E = 663 , - WIFISPARE_REUSE_TAG_66_E = 664 , - WIFISPARE_REUSE_TAG_67_E = 665 , - WIFISPARE_REUSE_TAG_68_E = 666 , - WIFISPARE_REUSE_TAG_69_E = 667 , - WIFISPARE_REUSE_TAG_70_E = 668 , - WIFISPARE_REUSE_TAG_71_E = 669 , - WIFISPARE_REUSE_TAG_72_E = 670 , - WIFISPARE_REUSE_TAG_73_E = 671 , - WIFISPARE_REUSE_TAG_74_E = 672 , - WIFISPARE_REUSE_TAG_75_E = 673 , - WIFISPARE_REUSE_TAG_76_E = 674 , - WIFISPARE_REUSE_TAG_77_E = 675 , - WIFISPARE_REUSE_TAG_78_E = 676 , - WIFISPARE_REUSE_TAG_79_E = 677 , - WIFISPARE_REUSE_TAG_80_E = 678 , - WIFISPARE_REUSE_TAG_81_E = 679 , - WIFISPARE_REUSE_TAG_82_E = 680 , - WIFISPARE_REUSE_TAG_83_E = 681 , - WIFISPARE_REUSE_TAG_84_E = 682 , - WIFISPARE_REUSE_TAG_85_E = 683 , - WIFISPARE_REUSE_TAG_86_E = 684 , - WIFISPARE_REUSE_TAG_87_E = 685 , - WIFISPARE_REUSE_TAG_88_E = 686 , - WIFISPARE_REUSE_TAG_89_E = 687 , - WIFISPARE_REUSE_TAG_90_E = 688 , - WIFISPARE_REUSE_TAG_91_E = 689 , - WIFISPARE_REUSE_TAG_92_E = 690 , - WIFISPARE_REUSE_TAG_93_E = 691 , - WIFISPARE_REUSE_TAG_94_E = 692 , - WIFISPARE_REUSE_TAG_95_E = 693 , - WIFISPARE_REUSE_TAG_96_E = 694 , - WIFISPARE_REUSE_TAG_97_E = 695 , - WIFISPARE_REUSE_TAG_98_E = 696 , - WIFISPARE_REUSE_TAG_99_E = 697 , - WIFISPARE_REUSE_TAG_100_E = 698 , - WIFISPARE_REUSE_TAG_101_E = 699 , - WIFISPARE_REUSE_TAG_102_E = 700 , - WIFISPARE_REUSE_TAG_103_E = 701 , - WIFISPARE_REUSE_TAG_104_E = 702 , - WIFISPARE_REUSE_TAG_105_E = 703 , - WIFISPARE_REUSE_TAG_106_E = 704 , - WIFISPARE_REUSE_TAG_107_E = 705 , - WIFISPARE_REUSE_TAG_108_E = 706 , - WIFISPARE_REUSE_TAG_109_E = 707 , - WIFISPARE_REUSE_TAG_110_E = 708 , - WIFISPARE_REUSE_TAG_111_E = 709 , - WIFISPARE_REUSE_TAG_112_E = 710 , - WIFISPARE_REUSE_TAG_113_E = 711 , - WIFISPARE_REUSE_TAG_114_E = 712 , - WIFISPARE_REUSE_TAG_115_E = 713 , - WIFISPARE_REUSE_TAG_116_E = 714 , - WIFISPARE_REUSE_TAG_117_E = 715 , - WIFISPARE_REUSE_TAG_118_E = 716 , - WIFISPARE_REUSE_TAG_119_E = 717 , - WIFISPARE_REUSE_TAG_120_E = 718 , - WIFISPARE_REUSE_TAG_121_E = 719 , - WIFISPARE_REUSE_TAG_122_E = 720 , - WIFISPARE_REUSE_TAG_123_E = 721 , - WIFISPARE_REUSE_TAG_124_E = 722 , - WIFISPARE_REUSE_TAG_125_E = 723 , - WIFISPARE_REUSE_TAG_126_E = 724 , - WIFISPARE_REUSE_TAG_127_E = 725 , - WIFISPARE_REUSE_TAG_128_E = 726 , - WIFISPARE_REUSE_TAG_129_E = 727 , - WIFISPARE_REUSE_TAG_130_E = 728 , - WIFISPARE_REUSE_TAG_131_E = 729 , - WIFISPARE_REUSE_TAG_132_E = 730 , - WIFISPARE_REUSE_TAG_133_E = 731 , - WIFISPARE_REUSE_TAG_134_E = 732 , - WIFISPARE_REUSE_TAG_135_E = 733 , - WIFISPARE_REUSE_TAG_136_E = 734 , - WIFISPARE_REUSE_TAG_137_E = 735 , - WIFISPARE_REUSE_TAG_138_E = 736 , - WIFISPARE_REUSE_TAG_139_E = 737 , - WIFISPARE_REUSE_TAG_140_E = 738 , - WIFISPARE_REUSE_TAG_141_E = 739 , - WIFISPARE_REUSE_TAG_142_E = 740 , - WIFISPARE_REUSE_TAG_143_E = 741 , - WIFISPARE_REUSE_TAG_144_E = 742 , - WIFISPARE_REUSE_TAG_145_E = 743 , - WIFISPARE_REUSE_TAG_146_E = 744 , - WIFISPARE_REUSE_TAG_147_E = 745 , - WIFISPARE_REUSE_TAG_148_E = 746 , - WIFISPARE_REUSE_TAG_149_E = 747 , - WIFISPARE_REUSE_TAG_150_E = 748 , - WIFISPARE_REUSE_TAG_151_E = 749 , - WIFISPARE_REUSE_TAG_152_E = 750 , - WIFISPARE_REUSE_TAG_153_E = 751 , - WIFISPARE_REUSE_TAG_154_E = 752 , - WIFISPARE_REUSE_TAG_155_E = 753 , - WIFISPARE_REUSE_TAG_156_E = 754 , - WIFISPARE_REUSE_TAG_157_E = 755 , - WIFISPARE_REUSE_TAG_158_E = 756 , - WIFISPARE_REUSE_TAG_159_E = 757 , - WIFISPARE_REUSE_TAG_160_E = 758 , - WIFISPARE_REUSE_TAG_161_E = 759 , - WIFISPARE_REUSE_TAG_162_E = 760 , - WIFISPARE_REUSE_TAG_163_E = 761 , - WIFISPARE_REUSE_TAG_164_E = 762 , - WIFISPARE_REUSE_TAG_165_E = 763 , - WIFISPARE_REUSE_TAG_166_E = 764 , - WIFISPARE_REUSE_TAG_167_E = 765 , - WIFISPARE_REUSE_TAG_168_E = 766 , - WIFISPARE_REUSE_TAG_169_E = 767 , - WIFISPARE_REUSE_TAG_170_E = 768 , - WIFISPARE_REUSE_TAG_171_E = 769 , - WIFISPARE_REUSE_TAG_172_E = 770 , - WIFISPARE_REUSE_TAG_173_E = 771 , - WIFISPARE_REUSE_TAG_174_E = 772 , - WIFISPARE_REUSE_TAG_175_E = 773 , - WIFISPARE_REUSE_TAG_176_E = 774 , - WIFISPARE_REUSE_TAG_177_E = 775 , - WIFISPARE_REUSE_TAG_178_E = 776 , - WIFISPARE_REUSE_TAG_179_E = 777 , - WIFISPARE_REUSE_TAG_180_E = 778 , - WIFISPARE_REUSE_TAG_181_E = 779 , - WIFISPARE_REUSE_TAG_182_E = 780 , - WIFISPARE_REUSE_TAG_183_E = 781 , - WIFISPARE_REUSE_TAG_184_E = 782 , - WIFISPARE_REUSE_TAG_185_E = 783 , - WIFISPARE_REUSE_TAG_186_E = 784 , - WIFISPARE_REUSE_TAG_187_E = 785 , - WIFISPARE_REUSE_TAG_188_E = 786 , - WIFISPARE_REUSE_TAG_189_E = 787 , - WIFISPARE_REUSE_TAG_190_E = 788 , - WIFISPARE_REUSE_TAG_191_E = 789 , - WIFISPARE_REUSE_TAG_192_E = 790 , - WIFISPARE_REUSE_TAG_193_E = 791 , - WIFISPARE_REUSE_TAG_194_E = 792 , - WIFISPARE_REUSE_TAG_195_E = 793 , - WIFISPARE_REUSE_TAG_196_E = 794 , - WIFISPARE_REUSE_TAG_197_E = 795 , - WIFISPARE_REUSE_TAG_198_E = 796 , - WIFISPARE_REUSE_TAG_199_E = 797 , - WIFISPARE_REUSE_TAG_200_E = 798 , - WIFISPARE_REUSE_TAG_201_E = 799 , - WIFISPARE_REUSE_TAG_202_E = 800 , - WIFISPARE_REUSE_TAG_203_E = 801 , - WIFISPARE_REUSE_TAG_204_E = 802 , - WIFISPARE_REUSE_TAG_205_E = 803 , - WIFISPARE_REUSE_TAG_206_E = 804 , - WIFISPARE_REUSE_TAG_207_E = 805 , - WIFISPARE_REUSE_TAG_208_E = 806 , - WIFISPARE_REUSE_TAG_209_E = 807 , - WIFISPARE_REUSE_TAG_210_E = 808 , - WIFISPARE_REUSE_TAG_211_E = 809 , - WIFISPARE_REUSE_TAG_212_E = 810 , - WIFISPARE_REUSE_TAG_213_E = 811 , - WIFISPARE_REUSE_TAG_214_E = 812 , - WIFISPARE_REUSE_TAG_215_E = 813 , - WIFISPARE_REUSE_TAG_216_E = 814 , - WIFISPARE_REUSE_TAG_217_E = 815 , - WIFISPARE_REUSE_TAG_218_E = 816 , - WIFISPARE_REUSE_TAG_219_E = 817 , - WIFISPARE_REUSE_TAG_220_E = 818 , - WIFISPARE_REUSE_TAG_221_E = 819 , - WIFISPARE_REUSE_TAG_222_E = 820 , - WIFISPARE_REUSE_TAG_223_E = 821 , - WIFISPARE_REUSE_TAG_224_E = 822 , - WIFISPARE_REUSE_TAG_225_E = 823 , - WIFISPARE_REUSE_TAG_226_E = 824 , - WIFISPARE_REUSE_TAG_227_E = 825 , - WIFISPARE_REUSE_TAG_228_E = 826 , - WIFISPARE_REUSE_TAG_229_E = 827 , - WIFISPARE_REUSE_TAG_230_E = 828 , - WIFISPARE_REUSE_TAG_231_E = 829 , - WIFISPARE_REUSE_TAG_232_E = 830 , - WIFISPARE_REUSE_TAG_233_E = 831 , - WIFISPARE_REUSE_TAG_234_E = 832 , - WIFISPARE_REUSE_TAG_235_E = 833 , - WIFISPARE_REUSE_TAG_236_E = 834 , - WIFISPARE_REUSE_TAG_237_E = 835 , - WIFISPARE_REUSE_TAG_238_E = 836 , - WIFISPARE_REUSE_TAG_239_E = 837 , - WIFISPARE_REUSE_TAG_240_E = 838 , - WIFISPARE_REUSE_TAG_241_E = 839 , - WIFISPARE_REUSE_TAG_242_E = 840 , - WIFISPARE_REUSE_TAG_243_E = 841 , - WIFISPARE_REUSE_TAG_244_E = 842 , - WIFISPARE_REUSE_TAG_245_E = 843 , - WIFISPARE_REUSE_TAG_246_E = 844 , - WIFISPARE_REUSE_TAG_247_E = 845 , - WIFISPARE_REUSE_TAG_248_E = 846 , - WIFISPARE_REUSE_TAG_249_E = 847 , - WIFISPARE_REUSE_TAG_250_E = 848 , - WIFISPARE_REUSE_TAG_251_E = 849 , - WIFISPARE_REUSE_TAG_252_E = 850 , - WIFISPARE_REUSE_TAG_253_E = 851 , - WIFISPARE_REUSE_TAG_254_E = 852 , - WIFISPARE_REUSE_TAG_255_E = 853 , - WIFISPARE_REUSE_TAG_256_E = 854 , - WIFISPARE_REUSE_TAG_257_E = 855 , - WIFISPARE_REUSE_TAG_258_E = 856 , - WIFISPARE_REUSE_TAG_259_E = 857 , - WIFISPARE_REUSE_TAG_260_E = 858 , - WIFISPARE_REUSE_TAG_261_E = 859 , - WIFISPARE_REUSE_TAG_262_E = 860 , - WIFISPARE_REUSE_TAG_263_E = 861 , - WIFISPARE_REUSE_TAG_264_E = 862 , - WIFISPARE_REUSE_TAG_265_E = 863 , - WIFISPARE_REUSE_TAG_266_E = 864 , - WIFISPARE_REUSE_TAG_267_E = 865 , - WIFISPARE_REUSE_TAG_268_E = 866 , - WIFISPARE_REUSE_TAG_269_E = 867 , - WIFISPARE_REUSE_TAG_270_E = 868 , - WIFISPARE_REUSE_TAG_271_E = 869 , - WIFISPARE_REUSE_TAG_272_E = 870 , - WIFISPARE_REUSE_TAG_273_E = 871 , - WIFISPARE_REUSE_TAG_274_E = 872 , - WIFISPARE_REUSE_TAG_275_E = 873 , - WIFISPARE_REUSE_TAG_276_E = 874 , - WIFISPARE_REUSE_TAG_277_E = 875 , - WIFISPARE_REUSE_TAG_278_E = 876 , - WIFISPARE_REUSE_TAG_279_E = 877 , - WIFISPARE_REUSE_TAG_280_E = 878 , - WIFISPARE_REUSE_TAG_281_E = 879 , - WIFISPARE_REUSE_TAG_282_E = 880 , - WIFISPARE_REUSE_TAG_283_E = 881 , - WIFISPARE_REUSE_TAG_284_E = 882 , - WIFISPARE_REUSE_TAG_285_E = 883 , - WIFISPARE_REUSE_TAG_286_E = 884 , - WIFISPARE_REUSE_TAG_287_E = 885 , - WIFISPARE_REUSE_TAG_288_E = 886 , - WIFISPARE_REUSE_TAG_289_E = 887 , - WIFISPARE_REUSE_TAG_290_E = 888 , - WIFISPARE_REUSE_TAG_291_E = 889 , - WIFISPARE_REUSE_TAG_292_E = 890 , - WIFISPARE_REUSE_TAG_293_E = 891 , - WIFISPARE_REUSE_TAG_294_E = 892 , - WIFISPARE_REUSE_TAG_295_E = 893 , - WIFISPARE_REUSE_TAG_296_E = 894 , - WIFISPARE_REUSE_TAG_297_E = 895 , - WIFISPARE_REUSE_TAG_298_E = 896 , - WIFISPARE_REUSE_TAG_299_E = 897 , - WIFISPARE_REUSE_TAG_300_E = 898 , - WIFISPARE_REUSE_TAG_301_E = 899 , - WIFISPARE_REUSE_TAG_302_E = 900 , - WIFISPARE_REUSE_TAG_303_E = 901 , - WIFISPARE_REUSE_TAG_304_E = 902 , - WIFISPARE_REUSE_TAG_305_E = 903 , - WIFISPARE_REUSE_TAG_306_E = 904 , - WIFISPARE_REUSE_TAG_307_E = 905 , - WIFISPARE_REUSE_TAG_308_E = 906 , - WIFISPARE_REUSE_TAG_309_E = 907 , - WIFISPARE_REUSE_TAG_310_E = 908 , - WIFISPARE_REUSE_TAG_311_E = 909 , - WIFISPARE_REUSE_TAG_312_E = 910 , - WIFISPARE_REUSE_TAG_313_E = 911 , - WIFISPARE_REUSE_TAG_314_E = 912 , - WIFISPARE_REUSE_TAG_315_E = 913 , - WIFISPARE_REUSE_TAG_316_E = 914 , - WIFISPARE_REUSE_TAG_317_E = 915 , - WIFISPARE_REUSE_TAG_318_E = 916 , - WIFISPARE_REUSE_TAG_319_E = 917 , - WIFISPARE_REUSE_TAG_320_E = 918 , - WIFISPARE_REUSE_TAG_321_E = 919 , - WIFISPARE_REUSE_TAG_322_E = 920 , - WIFISPARE_REUSE_TAG_323_E = 921 , - WIFISPARE_REUSE_TAG_324_E = 922 , - WIFISPARE_REUSE_TAG_325_E = 923 , - WIFISPARE_REUSE_TAG_326_E = 924 , - WIFISPARE_REUSE_TAG_327_E = 925 , - WIFISPARE_REUSE_TAG_328_E = 926 , - WIFISPARE_REUSE_TAG_329_E = 927 , - WIFISPARE_REUSE_TAG_330_E = 928 , - WIFISPARE_REUSE_TAG_331_E = 929 , - WIFISPARE_REUSE_TAG_332_E = 930 , - WIFISPARE_REUSE_TAG_333_E = 931 , - WIFISPARE_REUSE_TAG_334_E = 932 , - WIFISPARE_REUSE_TAG_335_E = 933 , - WIFISPARE_REUSE_TAG_336_E = 934 , - WIFISPARE_REUSE_TAG_337_E = 935 , - WIFISPARE_REUSE_TAG_338_E = 936 , - WIFISPARE_REUSE_TAG_339_E = 937 , - WIFISPARE_REUSE_TAG_340_E = 938 , - WIFISPARE_REUSE_TAG_341_E = 939 , - WIFISPARE_REUSE_TAG_342_E = 940 , - WIFISPARE_REUSE_TAG_343_E = 941 , - WIFISPARE_REUSE_TAG_344_E = 942 , - WIFISPARE_REUSE_TAG_345_E = 943 , - WIFISPARE_REUSE_TAG_346_E = 944 , - WIFISPARE_REUSE_TAG_347_E = 945 , - WIFISPARE_REUSE_TAG_348_E = 946 , - WIFISPARE_REUSE_TAG_349_E = 947 , - WIFISPARE_REUSE_TAG_350_E = 948 , - WIFISPARE_REUSE_TAG_351_E = 949 , - WIFISPARE_REUSE_TAG_352_E = 950 , - WIFISPARE_REUSE_TAG_353_E = 951 , - WIFISPARE_REUSE_TAG_354_E = 952 , - WIFISPARE_REUSE_TAG_355_E = 953 , - WIFISPARE_REUSE_TAG_356_E = 954 , - WIFISPARE_REUSE_TAG_357_E = 955 , - WIFISPARE_REUSE_TAG_358_E = 956 , - WIFISPARE_REUSE_TAG_359_E = 957 , - WIFISPARE_REUSE_TAG_360_E = 958 , - WIFISPARE_REUSE_TAG_361_E = 959 , - WIFISPARE_REUSE_TAG_362_E = 960 , - WIFISPARE_REUSE_TAG_363_E = 961 , - WIFISPARE_REUSE_TAG_364_E = 962 , - WIFISPARE_REUSE_TAG_365_E = 963 , - WIFISPARE_REUSE_TAG_366_E = 964 , - WIFISPARE_REUSE_TAG_367_E = 965 , - WIFISPARE_REUSE_TAG_368_E = 966 , - WIFISPARE_REUSE_TAG_369_E = 967 , - WIFISPARE_REUSE_TAG_370_E = 968 , - WIFISPARE_REUSE_TAG_371_E = 969 , - WIFISPARE_REUSE_TAG_372_E = 970 , - WIFISPARE_REUSE_TAG_373_E = 971 , - WIFISPARE_REUSE_TAG_374_E = 972 , - WIFISPARE_REUSE_TAG_375_E = 973 , - WIFISPARE_REUSE_TAG_376_E = 974 , - WIFISPARE_REUSE_TAG_377_E = 975 , - WIFISPARE_REUSE_TAG_378_E = 976 , - WIFISPARE_REUSE_TAG_379_E = 977 , - WIFISPARE_REUSE_TAG_380_E = 978 , - WIFISPARE_REUSE_TAG_381_E = 979 , - WIFISPARE_REUSE_TAG_382_E = 980 , - WIFISPARE_REUSE_TAG_383_E = 981 , - WIFISPARE_REUSE_TAG_384_E = 982 , - WIFISPARE_REUSE_TAG_385_E = 983 , - WIFISPARE_REUSE_TAG_386_E = 984 , - WIFISPARE_REUSE_TAG_387_E = 985 , - WIFISPARE_REUSE_TAG_388_E = 986 , - WIFISPARE_REUSE_TAG_389_E = 987 , - WIFISPARE_REUSE_TAG_390_E = 988 , - WIFISPARE_REUSE_TAG_391_E = 989 , - WIFISPARE_REUSE_TAG_392_E = 990 , - WIFISPARE_REUSE_TAG_393_E = 991 , - WIFISPARE_REUSE_TAG_394_E = 992 , - WIFISPARE_REUSE_TAG_395_E = 993 , - WIFISPARE_REUSE_TAG_396_E = 994 , - WIFISPARE_REUSE_TAG_397_E = 995 , - WIFISPARE_REUSE_TAG_398_E = 996 , - WIFISPARE_REUSE_TAG_399_E = 997 , - WIFISPARE_REUSE_TAG_400_E = 998 , - WIFISPARE_REUSE_TAG_401_E = 999 , - WIFISPARE_REUSE_TAG_402_E = 1000 , - WIFISPARE_REUSE_TAG_403_E = 1001 , - WIFISPARE_REUSE_TAG_404_E = 1002 , - WIFISPARE_REUSE_TAG_405_E = 1003 , - WIFISPARE_REUSE_TAG_406_E = 1004 , - WIFISPARE_REUSE_TAG_407_E = 1005 , - WIFISPARE_REUSE_TAG_408_E = 1006 , - WIFISPARE_REUSE_TAG_409_E = 1007 , - WIFISPARE_REUSE_TAG_410_E = 1008 , - WIFISPARE_REUSE_TAG_411_E = 1009 , - WIFISPARE_REUSE_TAG_412_E = 1010 , - WIFISPARE_REUSE_TAG_413_E = 1011 , - WIFISPARE_REUSE_TAG_414_E = 1012 , - WIFISPARE_REUSE_TAG_415_E = 1013 , - WIFISPARE_REUSE_TAG_416_E = 1014 , - WIFISPARE_REUSE_TAG_417_E = 1015 , - WIFISPARE_REUSE_TAG_418_E = 1016 , - WIFISPARE_REUSE_TAG_419_E = 1017 , - WIFISPARE_REUSE_TAG_420_E = 1018 , - WIFISPARE_REUSE_TAG_421_E = 1019 , - WIFISPARE_REUSE_TAG_422_E = 1020 , - WIFISPARE_REUSE_TAG_423_E = 1021 -} tlv_tag_def__e; - -typedef enum { - WIFI_EXT_PHYRX_DATA_E = 1 , - WIFI_EXT_PHYRX_ABORT_REQUEST_E = 3 , - WIFI_EXT_MACTX_DATA_RESP_E = 5 , - WIFI_EXT_MACTX_CBF_DONE_E = 7 , - WIFI_EXT_RXPCU_TO_UCODE_START_E = 9 , - WIFI_EXT_RXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 , - WIFI_EXT_RXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 , - WIFI_EXT_RXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 , - WIFI_EXT_PHYRX_RSSI_LEGACY_20MHZ_E = 17 , - WIFI_EXT_PHYRX_PKT_END_20MHZ_E = 19 , - WIFI_EXT_MACRX_CBF_DATA_REQUEST_E = 65 , - WIFI_EXT_MACRX_FREEZE_CAPTURE_CHANNEL_E = 67 , - WIFI_EXT_MACRX_ABORT_ACK_E = 69 , - WIFI_EXT_MACRX_CHAIN_MASK_E = 71 , - WIFI_EXT_MACRX_ABORT_REQUEST_E = 73 , - WIFI_EXT_PHYTX_ABORT_ACK_E = 75 , - WIFI_EXT_PHYTX_PKT_END_E = 77 , - WIFI_EXT_PHYTX_REQUEST_CTRL_INFO_E = 79 , - WIFI_EXT_PHYTX_BF_CV_LOADING_DONE_E = 81 , - WIFI_EXT_PHYTX_NAP_DONE_E = 83 , - WIFI_EXT_PHYTX_ON_ACK_E = 85 , - WIFI_EXT_PHYTX_DEBUG16_E = 87 , - WIFI_EXT_MACTX_ABORT_ACK_E = 89 , - WIFI_EXT_MACTX_PRE_PHY_DESC_E = 91 , - WIFI_EXT_MACTX_BF_PARAMS_PER_USER_E = 93 , - WIFI_EXT_MACTX_USER_DESC_COMMON_E = 95 , - WIFI_EXT_EXAMPLE_USER_TLV_16_E = 97 , - WIFI_EXT_MACTX_PHY_OFF_E = 99 , - WIFI_EXT_MACTX_SYNTH_OFF_E = 101 , - WIFI_EXT_MACTX_EXPECT_CBF_PER_USER_E = 103 , - WIFI_EXT_MACTX_L_SIG_A_E = 105 , - WIFI_EXT_MACTX_HT_SIG_E = 107 , - WIFI_EXT_MACTX_VHT_SIG_B_SU20_E = 109 , - WIFI_EXT_MACTX_VHT_SIG_B_SU80_E = 111 , - WIFI_EXT_MACTX_VHT_SIG_B_MU20_E = 113 , - WIFI_EXT_MACTX_VHT_SIG_B_MU80_E = 115 , - WIFI_EXT_MACTX_SERVICE_E = 117 , - WIFI_EXT_MACTX_HE_SIG_A_MU_DL_E = 119 , - WIFI_EXT_MACTX_HE_SIG_B1_MU_E = 121 , - WIFI_EXT_MACTX_HE_SIG_B2_OFDMA_E = 123 , - WIFI_EXT_MACTX_MU_UPLINK_COMMON_E = 125 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_E = 127 , - WIFI_EXT_MACTX_DEBUG_E = 129 , - WIFI_EXT_PHYRX_GENERATED_CBF_DETAILS_E = 131 , - WIFI_EXT_PHYRX_RSSI_HT_E = 133 , - WIFI_EXT_PHYRX_PKT_END_E = 135 , - WIFI_EXT_PHYRX_CBF_TRANSFER_DONE_E = 137 , - WIFI_EXT_PHYRX_L_SIG_A_E = 139 , - WIFI_EXT_PHYRX_HT_SIG_E = 141 , - WIFI_EXT_PHYRX_VHT_SIG_B_SU20_E = 143 , - WIFI_EXT_PHYRX_VHT_SIG_B_SU80_E = 145 , - WIFI_EXT_PHYRX_VHT_SIG_B_MU20_E = 147 , - WIFI_EXT_PHYRX_VHT_SIG_B_MU80_E = 149 , - WIFI_EXT_PHYRX_HE_SIG_A_SU_E = 151 , - WIFI_EXT_PHYRX_HE_SIG_A_MU_UL_E = 153 , - WIFI_EXT_PHYRX_HE_SIG_B2_MU_E = 155 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_E = 157 , - WIFI_EXT_PHYRX_DATA_DONE_E = 159 , - WIFI_EXT_DUMMY_E = 161 , - WIFI_EXT_MPDU_LIMIT_E = 163 , - WIFI_EXT_OLE_BUF_STATUS_E = 165 , - WIFI_EXT_PCU_PPDU_SETUP_END_E = 167 , - WIFI_EXT_PCU_PPDU_SETUP_START_E = 169 , - WIFI_EXT_PDG_RESPONSE_E = 171 , - WIFI_EXT_SCH_WAIT_INSTR_E = 173 , - WIFI_EXT_PHYTX_LINK_STATE_E = 175 , - WIFI_EXT_TQM_GEN_MPDU_LENGTH_LIST_E = 177 , - WIFI_EXT_TQM_GEN_MPDUS_E = 179 , - WIFI_EXT_TQM_REMOVE_MPDU_E = 181 , - WIFI_EXT_TQM_REMOVE_MSDU_E = 183 , - WIFI_EXT_TQM_UPDATE_TX_MPDU_COUNT_E = 185 , - WIFI_EXT_OFDMA_TRIGGER_DETAILS_E = 187 , - WIFI_EXT_TX_FES_SETUP_E = 189 , - WIFI_EXT_EXPECTED_RESPONSE_E = 191 , - WIFI_EXT_TX_MPDU_START_E = 193 , - WIFI_EXT_TX_MSDU_START_E = 195 , - WIFI_EXT_TXPCU_BUFFER_STATUS_E = 197 , - WIFI_EXT_DATA_TO_TIME_CONFIG_E = 199 , - WIFI_EXT_MPDU_INFO_E = 201 , - WIFI_EXT_TX_11AH_SETUP_E = 203 , - WIFI_EXT_TX_PEER_ENTRY_E = 205 , - WIFI_EXT_EXAMPLE_USER_TLV_44_E = 207 , - WIFI_EXT_TX_FLUSH_REQ_E = 209 , - WIFI_EXT_TQM_GET_MPDU_QUEUE_STATS_E = 211 , - WIFI_EXT_EXAMPLE_USER_CTLV_44_E = 213 , - WIFI_EXT_TX_FES_STATUS_USER_PPDU_E = 215 , - WIFI_EXT_TX_FES_STATUS_END_E = 217 , - WIFI_EXT_RXPCU_TX_SETUP_CLEAR_E = 219 , - WIFI_EXT_RX_FRAME_BITMAP_ACK_E = 221 , - WIFI_EXT_RX_START_PARAM_E = 223 , - WIFI_EXT_RX_PPDU_END_E = 225 , - WIFI_EXT_RX_MPDU_END_E = 227 , - WIFI_EXT_RX_MSDU_END_E = 229 , - WIFI_EXT_RECEIVED_RESPONSE_INFO_E = 231 , - WIFI_EXT_RX_HEADER_E = 233 , - WIFI_EXT_RX_FLUSH_E = 235 , - WIFI_EXT_RX_FRAMELESS_BAR_DETAILS_E = 237 , - WIFI_EXT_TQM_GET_MSDU_FLOW_STATS_STATUS_E = 239 , - WIFI_EXT_PCU_PPDU_SETUP_USER_E = 241 , - WIFI_EXT_RX_PM_INFO_E = 243 , - WIFI_EXT_RX_PRE_PPDU_START_E = 245 , - WIFI_EXT_TX_FES_SETUP_COMPLETE_E = 247 , - WIFI_EXT_TXDMA_STOP_REQUEST_E = 249 , - WIFI_EXT_RXPCU_USER_SETUP_E = 251 , - WIFI_EXT_TQM_ACKED_MPDU_E = 253 , - WIFI_EXT_COEX_TX_STATUS_E = 255 , - WIFI_EXT_COEX_STATUS_BROADCAST_E = 257 , - WIFI_EXT_RESPONSE_END_STATUS_E = 259 , - WIFI_EXT_RECEIVED_TRIGGER_INFO_E = 261 , - WIFI_EXT_RX_PPDU_ACK_REPORT_E = 263 , - WIFI_EXT_SCH_COEX_STATUS_E = 265 , - WIFI_EXT_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 267 , - WIFI_EXT_TX_FES_STATUS_START_PPDU_E = 269 , - WIFI_EXT_TXPCU_PHYTX_DEBUG32_E = 271 , - WIFI_EXT_TX_MPDU_COUNT_TRANSFER_END_E = 273 , - WIFI_EXT_WHO_ANCHOR_VALUE_E = 275 , - WIFI_EXT_WHO_COMMIT_E = 277 , - WIFI_EXT_WHO_FLUSH_E = 279 , - WIFI_EXT_WHO_L2_PAYLOAD_E = 281 , - WIFI_EXT_WHO_L3_INFO_E = 283 , - WIFI_EXT_WHO_L4_INFO_E = 285 , - WIFI_EXT_WHO_MSDU_MISC_E = 287 , - WIFI_EXT_WHO_PACKET_HDR_E = 289 , - WIFI_EXT_WHO_PPDU_START_E = 291 , - WIFI_EXT_WHO_WMAC_HEADER_PV0_E = 293 , - WIFI_EXT_WHO_WMAC_IV_E = 295 , - WIFI_EXT_MPDU_INFO_BITMAP_E = 297 , - WIFI_EXT_SCHEDULER_SELFGEN_RESPONSE_STATUS_E = 299 , - WIFI_EXT_TQM_ACKED_MPDU_STATUS_E = 301 , - WIFI_EXT_TQM_LIST_GEN_DONE_E = 303 , - WIFI_EXT_TX_LAST_MPDU_END_E = 305 , - WIFI_EXT_PPDU_TX_END_E = 307 , - WIFI_EXT_MPDU_INFO_GLOBAL_END_E = 309 , - WIFI_EXT_RX_PPDU_END_USER_STATS_E = 311 , - WIFI_EXT_TQM_FLUSH_CACHE_E = 321 , - WIFI_EXT_TQM_FLUSH_CACHE_STATUS_E = 323 , - WIFI_EXT_RX_PPDU_END_STATUS_DONE_E = 325 , - WIFI_EXT_SCHEDULER_MLO_SW_MSG_STATUS_E = 327 , - WIFI_EXT_TX_DATA_SYNC_E = 329 , - WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_E = 331 , - WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_STATUS_E = 333 , - WIFI_EXT_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 335 , - WIFI_EXT_EXAMPLE_USER_TLV_32_NAME_E = 341 , - WIFI_EXT_RX_RING_MASK_E = 343 , - WIFI_EXT_RXPCU_PPDU_END_INFO_E = 345 , - WIFI_EXT_PDG_SW_MODE_BW_START_E = 347 , - WIFI_EXT_PDG_WAIT_FOR_MAC_REQUEST_E = 349 , - WIFI_EXT_SCHEDULER_END_E = 351 , - WIFI_EXT_RX_PPDU_END_DROPPED_E = 353 , - WIFI_EXT_RX_MPDU_START_DROPPED_E = 355 , - WIFI_EXT_RX_MSDU_END_DROPPED_E = 357 , - WIFI_EXT_RX_ATTENTION_DROPPED_E = 359 , - WIFI_EXT_RXPCU_USER_SETUP_EXT_E = 361 , - WIFI_EXT_MACTX_SYNTH_ON_E = 363 , - WIFI_EXT_TQM_MPDU_GLOBAL_START_E = 365 , - WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_E = 367 , - WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 369 , - WIFI_EXT_PDG_TRIG_RESPONSE_E = 373 , - WIFI_EXT_ABORT_FROM_PHYRX_DETAILS_E = 375 , - WIFI_EXT_MPDUS_AVAILABLE_E = 377 , - WIFI_EXT_PHYRX_TX_START_TIMING_E = 379 , - WIFI_EXT_NDP_PREAMBLE_DONE_E = 381 , - WIFI_EXT_SCH_TQM_CMD_WRAPPER_CONT_DROP_E = 383 , - WIFI_EXT_TX_PUNCTURE_SETUP_E = 385 , - WIFI_EXT_MACTX_PREFETCH_CV_COMMON_E = 387 , - WIFI_EXT_MACTX_MU_UPLINK_COMMON_PUNC_E = 389 , - WIFI_EXT_RECEIVED_RESPONSE_USER_7_0_E = 391 , - WIFI_EXT_RECEIVED_RESPONSE_USER_23_16_E = 393 , - WIFI_EXT_RECEIVED_RESPONSE_USER_36_32_E = 395 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 397 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 399 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 401 , - WIFI_EXT_RX_PPDU_END_START_E = 403 , - WIFI_EXT_RX_PPDU_END_LAST_E = 405 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 407 , - WIFI_EXT_OBSS_SR_INFO_E = 409 , - WIFI_EXT_HWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 411 , - WIFI_EXT_MACTX_MCC_SWITCH_E = 413 , - WIFI_EXT_PHYTX_MCC_SWITCH_ACK_E = 415 , - WIFI_EXT_PHYTX_EMLSR_PRE_SWITCH_ACK_E = 417 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 419 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 421 , - WIFI_EXT_SCH_TLV_WRAPPER_E = 423 , - WIFI_EXT_MPDU_INFO_6X_E = 425 , - WIFI_EXT_MACTX_U_SIG_EHT_SU_MU_E = 427 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG0_CFG_E = 429 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG2_CFG_E = 431 , - WIFI_EXT_PHYRX_U_SIG_EHT_TB_E = 433 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 435 , - WIFI_EXT_MACRX_LMR_READ_REQUEST_E = 437 , - WIFI_EXT_PHYRX_LMR_TRANSFER_DONE_E = 439 , - WIFI_EXT_PHYRX_LMR_READ_REQUEST_ACK_E = 441 , - WIFI_EXT_PHYRX_USER_INFO_MU_UL_E = 443 , - WIFI_EXT_SCHEDULER_NAV_INFO_E = 445 , - WIFI_EXT_LMR_PEER_ENTRY_E = 447 , - WIFI_EXT_LMR_DATA_E = 449 , - WIFI_EXT_TX_FES_STATUS_1K_BA_E = 453 , - WIFI_EXT_MACRX_INBSS_OBSS_IND_E = 455 , - WIFI_EXT_MLO_TX_NOTIFICATION_SU_E = 457 , - WIFI_EXT_MLO_TX_REQ_SU_E = 459 , - WIFI_EXT_MLO_TX_RESP_E = 461 , - WIFI_EXT_MLO_BKOFF_TRUNC_REQ_E = 463 , - WIFI_EXT_MLO_MESSAGE_E = 465 , - WIFI_EXT_MLO_FES_SETUP_E = 467 , - WIFI_EXT_MLO_PDG_FES_SETUP_MU_E = 469 , - WIFI_EXT_MON_BUFFER_ADDR_E = 471 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 473 , - WIFI_EXT_MACTX_EHT_SIG_USR_OFDMA_E = 475 , - WIFI_EXT_MACTX_U_SIG_UHR_TB_E = 477 , - WIFI_EXT_TX_MSDU_COMPRESSED_DETAILS_TLV_E = 479 , - WIFI_EXT_PHYRX_EHT_SIG_USR_OFDMA_E = 481 , - WIFI_EXT_PHYRX_PKT_END_PART1_E = 483 , - WIFI_EXT_MACTX_SECURE_LTF_SEQ_PTR_E = 485 , - WIFI_EXT_MLO_PDG_BKOFF_TRUNC_NOTIFY_E = 487 , - WIFI_EXT_PHYTX_LOCATION_E = 489 , - WIFI_EXT_MPDU_LENGTH_STRUCTS_START_E = 491 , - WIFI_EXT_MACTX_EHT_SIG_USR_MU_MIMO_E = 493 , - WIFI_EXT_PHYRX_EHT_SIG_USR_MU_MIMO_E = 495 , - WIFI_EXT_PHYRX_GENERIC_EHT_OR_UHR_SIG_E = 497 , - WIFI_EXT_OVERWRITE_RESP_PREAMBLE_INFO_E = 499 , - WIFI_EXT_OVERWRITE_RESP_END_E = 501 , - WIFI_EXT_MON_DROP_E = 503 , - WIFI_EXT_MACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 505 , - WIFI_EXT_MACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 507 , - WIFI_EXT_MACTX_PREFETCH_CV_PER_USER_E = 509 , - WIFI_EXT_MACTX_BF_PARAMS_UPDATE_COMMON_E = 511 , - WIFI_EXT_RANGING_USER_DETAILS_E = 513 , - WIFI_EXT_PHYTX_CV_CORR_COMMON_E = 515 , - WIFI_EXT_MACTX_CV_CORR_COMMON_E = 517 , - WIFI_EXT_BW_PUNCTURE_EVAL_WRAPPER_E = 519 , - WIFI_EXT_MACTX_TX_NOTIFICATION_FOR_PHY_E = 521 , - WIFI_EXT_MACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 523 , - WIFI_EXT_FW2SW_MON_E = 525 , - WIFI_EXT_MACTX_EMLSR_PRE_SWITCH_E = 527 , - WIFI_EXT_MACTX_EMLSR_SWITCH_BACK_E = 529 , - WIFI_EXT_PHYTX_EMLSR_SWITCH_BACK_ACK_E = 531 , - WIFI_EXT_EAD_LEGACY_STATUS_CONTROL_E = 533 , - WIFI_EXT_TPI_TX_INITIALIZATION_CONFIG_E = 535 , - WIFI_EXT_TPI_LEGACY_STATUS_CONTROL_E = 537 , - WIFI_EXT_TPI_MPDU_START_E = 539 , - WIFI_EXT_TPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E = 541 , - WIFI_EXT_TPI_TX_START_TIME_ARRIVED_E = 543 , - WIFI_EXT_TPI_ERROR_STATUS_E = 545 , - WIFI_EXT_RPI_SEND_TLV_TO_PHYRX_E = 547 , - WIFI_EXT_RPI_LEGACY_INTERRUPT_CONTROL_E = 549 , - WIFI_EXT_RPI_ERROR_STATUS_E = 551 , - WIFI_EXT_RPI_RX_FRAME_UPDATE_STATUS_E = 553 , - WIFI_EXT_TCC_TLV_FETCH_E = 555 , - WIFI_EXT_TCC_LEGACY_INTERRUPT_CONTROL_E = 557 , - WIFI_EXT_TCC_ERROR_STATUS_E = 559 , - WIFI_EXT_TCC_PRE_BACKOFF_CMD_AVAILABLE_E = 561 , - WIFI_EXT_TCC_BURST_CMD_AVAILABLE_E = 563 , - WIFI_EXT_EAD_RING_AIR_TIME_REFERENCE_E = 565 , - WIFI_EXT_RPI_WRITE_INFO_TO_EXT_MEM_E = 567 , - WIFI_EXT_RPI_INIT_LMR_DATA_RESP_ADDR_E = 569 , - WIFI_EXT_TPI_SEND_CTLV_44_TO_PHYTX_E = 571 , - WIFI_EXT_TPI_TX_FRAME_UPDATE_STATUS_E = 573 , - WIFI_EXT_EAD_MPDU_DATA_FETCH_CONTINUATION_E = 575 , - WIFI_EXT_EAD_MSDU_STATUS_DETAILS_E = 577 , - WIFI_EXT_MACTX_UHR_SIG_USR_MU_MIMO_E = 579 , - WIFI_EXT_MACTX_ELR_SIG_UHR_SU_E = 581 , - WIFI_EXT_PEER_BLACKOUT_DETAILS_E = 583 , - WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_E = 585 , - WIFI_EXT_HDR_CTRL_PROT_DATA_E = 587 , - WIFI_EXT_HDR_CTRL_PROT_MIC_STATUS_E = 589 , - WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_DONE_E = 591 , - WIFI_EXT_MACTX_U_SIG_UHR_COBF_E = 593 , - WIFI_EXT_MACTX_U_SIG_UHR_COSR_E = 595 , - WIFI_EXT_OVERWRITE_CFP_INFO_E = 597 , - WIFI_EXT_SPARE_REUSE_TAG_1_E = 599 , - WIFI_EXT_SPARE_REUSE_TAG_3_E = 601 , - WIFI_EXT_SPARE_REUSE_TAG_5_E = 603 , - WIFI_EXT_SPARE_REUSE_TAG_7_E = 605 , - WIFI_EXT_SPARE_REUSE_TAG_9_E = 607 , - WIFI_EXT_SPARE_REUSE_TAG_11_E = 609 , - WIFI_EXT_SPARE_REUSE_TAG_13_E = 611 , - WIFI_EXT_SPARE_REUSE_TAG_15_E = 613 , - WIFI_EXT_SPARE_REUSE_TAG_17_E = 615 , - WIFI_EXT_SPARE_REUSE_TAG_19_E = 617 , - WIFI_EXT_SPARE_REUSE_TAG_21_E = 619 , - WIFI_EXT_SPARE_REUSE_TAG_23_E = 621 , - WIFI_EXT_SPARE_REUSE_TAG_25_E = 623 , - WIFI_EXT_SPARE_REUSE_TAG_27_E = 625 , - WIFI_EXT_SPARE_REUSE_TAG_29_E = 627 , - WIFI_EXT_SPARE_REUSE_TAG_31_E = 629 , - WIFI_EXT_SPARE_REUSE_TAG_33_E = 631 , - WIFI_EXT_SPARE_REUSE_TAG_35_E = 633 , - WIFI_EXT_SPARE_REUSE_TAG_37_E = 635 , - WIFI_EXT_SPARE_REUSE_TAG_39_E = 637 , - WIFI_EXT_SPARE_REUSE_TAG_41_E = 639 , - WIFI_EXT_SPARE_REUSE_TAG_43_E = 641 , - WIFI_EXT_SPARE_REUSE_TAG_45_E = 643 , - WIFI_EXT_SPARE_REUSE_TAG_47_E = 645 , - WIFI_EXT_SPARE_REUSE_TAG_49_E = 647 , - WIFI_EXT_SPARE_REUSE_TAG_51_E = 649 , - WIFI_EXT_SPARE_REUSE_TAG_53_E = 651 , - WIFI_EXT_SPARE_REUSE_TAG_55_E = 653 , - WIFI_EXT_SPARE_REUSE_TAG_57_E = 655 , - WIFI_EXT_SPARE_REUSE_TAG_59_E = 657 , - WIFI_EXT_SPARE_REUSE_TAG_61_E = 659 , - WIFI_EXT_SPARE_REUSE_TAG_63_E = 661 , - WIFI_EXT_SPARE_REUSE_TAG_65_E = 663 , - WIFI_EXT_SPARE_REUSE_TAG_67_E = 665 , - WIFI_EXT_SPARE_REUSE_TAG_69_E = 667 , - WIFI_EXT_SPARE_REUSE_TAG_71_E = 669 , - WIFI_EXT_SPARE_REUSE_TAG_73_E = 671 , - WIFI_EXT_SPARE_REUSE_TAG_75_E = 673 , - WIFI_EXT_SPARE_REUSE_TAG_77_E = 675 , - WIFI_EXT_SPARE_REUSE_TAG_79_E = 677 , - WIFI_EXT_SPARE_REUSE_TAG_81_E = 679 , - WIFI_EXT_SPARE_REUSE_TAG_83_E = 681 , - WIFI_EXT_SPARE_REUSE_TAG_85_E = 683 , - WIFI_EXT_SPARE_REUSE_TAG_87_E = 685 , - WIFI_EXT_SPARE_REUSE_TAG_89_E = 687 , - WIFI_EXT_SPARE_REUSE_TAG_91_E = 689 , - WIFI_EXT_SPARE_REUSE_TAG_93_E = 691 , - WIFI_EXT_SPARE_REUSE_TAG_95_E = 693 , - WIFI_EXT_SPARE_REUSE_TAG_97_E = 695 , - WIFI_EXT_SPARE_REUSE_TAG_99_E = 697 , - WIFI_EXT_SPARE_REUSE_TAG_101_E = 699 , - WIFI_EXT_SPARE_REUSE_TAG_103_E = 701 , - WIFI_EXT_SPARE_REUSE_TAG_105_E = 703 , - WIFI_EXT_SPARE_REUSE_TAG_107_E = 705 , - WIFI_EXT_SPARE_REUSE_TAG_109_E = 707 , - WIFI_EXT_SPARE_REUSE_TAG_111_E = 709 , - WIFI_EXT_SPARE_REUSE_TAG_113_E = 711 , - WIFI_EXT_SPARE_REUSE_TAG_115_E = 713 , - WIFI_EXT_SPARE_REUSE_TAG_117_E = 715 , - WIFI_EXT_SPARE_REUSE_TAG_119_E = 717 , - WIFI_EXT_SPARE_REUSE_TAG_121_E = 719 , - WIFI_EXT_SPARE_REUSE_TAG_123_E = 721 , - WIFI_EXT_SPARE_REUSE_TAG_125_E = 723 , - WIFI_EXT_SPARE_REUSE_TAG_127_E = 725 , - WIFI_EXT_SPARE_REUSE_TAG_129_E = 727 , - WIFI_EXT_SPARE_REUSE_TAG_131_E = 729 , - WIFI_EXT_SPARE_REUSE_TAG_133_E = 731 , - WIFI_EXT_SPARE_REUSE_TAG_135_E = 733 , - WIFI_EXT_SPARE_REUSE_TAG_137_E = 735 , - WIFI_EXT_SPARE_REUSE_TAG_139_E = 737 , - WIFI_EXT_SPARE_REUSE_TAG_141_E = 739 , - WIFI_EXT_SPARE_REUSE_TAG_143_E = 741 , - WIFI_EXT_SPARE_REUSE_TAG_145_E = 743 , - WIFI_EXT_SPARE_REUSE_TAG_147_E = 745 , - WIFI_EXT_SPARE_REUSE_TAG_149_E = 747 , - WIFI_EXT_SPARE_REUSE_TAG_151_E = 749 , - WIFI_EXT_SPARE_REUSE_TAG_153_E = 751 , - WIFI_EXT_SPARE_REUSE_TAG_155_E = 753 , - WIFI_EXT_SPARE_REUSE_TAG_157_E = 755 , - WIFI_EXT_SPARE_REUSE_TAG_159_E = 757 , - WIFI_EXT_SPARE_REUSE_TAG_161_E = 759 , - WIFI_EXT_SPARE_REUSE_TAG_163_E = 761 , - WIFI_EXT_SPARE_REUSE_TAG_165_E = 763 , - WIFI_EXT_SPARE_REUSE_TAG_167_E = 765 , - WIFI_EXT_SPARE_REUSE_TAG_169_E = 767 , - WIFI_EXT_SPARE_REUSE_TAG_171_E = 769 , - WIFI_EXT_SPARE_REUSE_TAG_173_E = 771 , - WIFI_EXT_SPARE_REUSE_TAG_175_E = 773 , - WIFI_EXT_SPARE_REUSE_TAG_177_E = 775 , - WIFI_EXT_SPARE_REUSE_TAG_179_E = 777 , - WIFI_EXT_SPARE_REUSE_TAG_181_E = 779 , - WIFI_EXT_SPARE_REUSE_TAG_183_E = 781 , - WIFI_EXT_SPARE_REUSE_TAG_185_E = 783 , - WIFI_EXT_SPARE_REUSE_TAG_187_E = 785 , - WIFI_EXT_SPARE_REUSE_TAG_189_E = 787 , - WIFI_EXT_SPARE_REUSE_TAG_191_E = 789 , - WIFI_EXT_SPARE_REUSE_TAG_193_E = 791 , - WIFI_EXT_SPARE_REUSE_TAG_195_E = 793 , - WIFI_EXT_SPARE_REUSE_TAG_197_E = 795 , - WIFI_EXT_SPARE_REUSE_TAG_199_E = 797 , - WIFI_EXT_SPARE_REUSE_TAG_201_E = 799 , - WIFI_EXT_SPARE_REUSE_TAG_203_E = 801 , - WIFI_EXT_SPARE_REUSE_TAG_205_E = 803 , - WIFI_EXT_SPARE_REUSE_TAG_207_E = 805 , - WIFI_EXT_SPARE_REUSE_TAG_209_E = 807 , - WIFI_EXT_SPARE_REUSE_TAG_211_E = 809 , - WIFI_EXT_SPARE_REUSE_TAG_213_E = 811 , - WIFI_EXT_SPARE_REUSE_TAG_215_E = 813 , - WIFI_EXT_SPARE_REUSE_TAG_217_E = 815 , - WIFI_EXT_SPARE_REUSE_TAG_219_E = 817 , - WIFI_EXT_SPARE_REUSE_TAG_221_E = 819 , - WIFI_EXT_SPARE_REUSE_TAG_223_E = 821 , - WIFI_EXT_SPARE_REUSE_TAG_225_E = 823 , - WIFI_EXT_SPARE_REUSE_TAG_227_E = 825 , - WIFI_EXT_SPARE_REUSE_TAG_229_E = 827 , - WIFI_EXT_SPARE_REUSE_TAG_231_E = 829 , - WIFI_EXT_SPARE_REUSE_TAG_233_E = 831 , - WIFI_EXT_SPARE_REUSE_TAG_235_E = 833 , - WIFI_EXT_SPARE_REUSE_TAG_237_E = 835 , - WIFI_EXT_SPARE_REUSE_TAG_239_E = 837 , - WIFI_EXT_SPARE_REUSE_TAG_241_E = 839 , - WIFI_EXT_SPARE_REUSE_TAG_243_E = 841 , - WIFI_EXT_SPARE_REUSE_TAG_245_E = 843 , - WIFI_EXT_SPARE_REUSE_TAG_247_E = 845 , - WIFI_EXT_SPARE_REUSE_TAG_249_E = 847 , - WIFI_EXT_SPARE_REUSE_TAG_251_E = 849 , - WIFI_EXT_SPARE_REUSE_TAG_253_E = 851 , - WIFI_EXT_SPARE_REUSE_TAG_255_E = 853 , - WIFI_EXT_SPARE_REUSE_TAG_257_E = 855 , - WIFI_EXT_SPARE_REUSE_TAG_259_E = 857 , - WIFI_EXT_SPARE_REUSE_TAG_261_E = 859 , - WIFI_EXT_SPARE_REUSE_TAG_263_E = 861 , - WIFI_EXT_SPARE_REUSE_TAG_265_E = 863 , - WIFI_EXT_SPARE_REUSE_TAG_267_E = 865 , - WIFI_EXT_SPARE_REUSE_TAG_269_E = 867 , - WIFI_EXT_SPARE_REUSE_TAG_271_E = 869 , - WIFI_EXT_SPARE_REUSE_TAG_273_E = 871 , - WIFI_EXT_SPARE_REUSE_TAG_275_E = 873 , - WIFI_EXT_SPARE_REUSE_TAG_277_E = 875 , - WIFI_EXT_SPARE_REUSE_TAG_279_E = 877 , - WIFI_EXT_SPARE_REUSE_TAG_281_E = 879 , - WIFI_EXT_SPARE_REUSE_TAG_283_E = 881 , - WIFI_EXT_SPARE_REUSE_TAG_285_E = 883 , - WIFI_EXT_SPARE_REUSE_TAG_287_E = 885 , - WIFI_EXT_SPARE_REUSE_TAG_289_E = 887 , - WIFI_EXT_SPARE_REUSE_TAG_291_E = 889 , - WIFI_EXT_SPARE_REUSE_TAG_293_E = 891 , - WIFI_EXT_SPARE_REUSE_TAG_295_E = 893 , - WIFI_EXT_SPARE_REUSE_TAG_297_E = 895 , - WIFI_EXT_SPARE_REUSE_TAG_299_E = 897 , - WIFI_EXT_SPARE_REUSE_TAG_301_E = 899 , - WIFI_EXT_SPARE_REUSE_TAG_303_E = 901 , - WIFI_EXT_SPARE_REUSE_TAG_305_E = 903 , - WIFI_EXT_SPARE_REUSE_TAG_307_E = 905 , - WIFI_EXT_SPARE_REUSE_TAG_309_E = 907 , - WIFI_EXT_SPARE_REUSE_TAG_311_E = 909 , - WIFI_EXT_SPARE_REUSE_TAG_313_E = 911 , - WIFI_EXT_SPARE_REUSE_TAG_315_E = 913 , - WIFI_EXT_SPARE_REUSE_TAG_317_E = 915 , - WIFI_EXT_SPARE_REUSE_TAG_319_E = 917 , - WIFI_EXT_SPARE_REUSE_TAG_321_E = 919 , - WIFI_EXT_SPARE_REUSE_TAG_323_E = 921 , - WIFI_EXT_SPARE_REUSE_TAG_325_E = 923 , - WIFI_EXT_SPARE_REUSE_TAG_327_E = 925 , - WIFI_EXT_SPARE_REUSE_TAG_329_E = 927 , - WIFI_EXT_SPARE_REUSE_TAG_331_E = 929 , - WIFI_EXT_SPARE_REUSE_TAG_333_E = 931 , - WIFI_EXT_SPARE_REUSE_TAG_335_E = 933 , - WIFI_EXT_SPARE_REUSE_TAG_337_E = 935 , - WIFI_EXT_SPARE_REUSE_TAG_339_E = 937 , - WIFI_EXT_SPARE_REUSE_TAG_341_E = 939 , - WIFI_EXT_SPARE_REUSE_TAG_343_E = 941 , - WIFI_EXT_SPARE_REUSE_TAG_345_E = 943 , - WIFI_EXT_SPARE_REUSE_TAG_347_E = 945 , - WIFI_EXT_SPARE_REUSE_TAG_349_E = 947 , - WIFI_EXT_SPARE_REUSE_TAG_351_E = 949 , - WIFI_EXT_SPARE_REUSE_TAG_353_E = 951 , - WIFI_EXT_SPARE_REUSE_TAG_355_E = 953 , - WIFI_EXT_SPARE_REUSE_TAG_357_E = 955 , - WIFI_EXT_SPARE_REUSE_TAG_359_E = 957 , - WIFI_EXT_SPARE_REUSE_TAG_361_E = 959 , - WIFI_EXT_SPARE_REUSE_TAG_363_E = 961 , - WIFI_EXT_SPARE_REUSE_TAG_365_E = 963 , - WIFI_EXT_SPARE_REUSE_TAG_367_E = 965 , - WIFI_EXT_SPARE_REUSE_TAG_369_E = 967 , - WIFI_EXT_SPARE_REUSE_TAG_371_E = 969 , - WIFI_EXT_SPARE_REUSE_TAG_373_E = 971 , - WIFI_EXT_SPARE_REUSE_TAG_375_E = 973 , - WIFI_EXT_SPARE_REUSE_TAG_377_E = 975 , - WIFI_EXT_SPARE_REUSE_TAG_379_E = 977 , - WIFI_EXT_SPARE_REUSE_TAG_381_E = 979 , - WIFI_EXT_SPARE_REUSE_TAG_383_E = 981 , - WIFI_EXT_SPARE_REUSE_TAG_385_E = 983 , - WIFI_EXT_SPARE_REUSE_TAG_387_E = 985 , - WIFI_EXT_SPARE_REUSE_TAG_389_E = 987 , - WIFI_EXT_SPARE_REUSE_TAG_391_E = 989 , - WIFI_EXT_SPARE_REUSE_TAG_393_E = 991 , - WIFI_EXT_SPARE_REUSE_TAG_395_E = 993 , - WIFI_EXT_SPARE_REUSE_TAG_397_E = 995 , - WIFI_EXT_SPARE_REUSE_TAG_399_E = 997 , - WIFI_EXT_SPARE_REUSE_TAG_401_E = 999 , - WIFI_EXT_SPARE_REUSE_TAG_403_E = 1001 , - WIFI_EXT_SPARE_REUSE_TAG_405_E = 1003 , - WIFI_EXT_SPARE_REUSE_TAG_407_E = 1005 , - WIFI_EXT_SPARE_REUSE_TAG_409_E = 1007 , - WIFI_EXT_SPARE_REUSE_TAG_411_E = 1009 , - WIFI_EXT_SPARE_REUSE_TAG_413_E = 1011 , - WIFI_EXT_SPARE_REUSE_TAG_415_E = 1013 , - WIFI_EXT_SPARE_REUSE_TAG_417_E = 1015 , - WIFI_EXT_SPARE_REUSE_TAG_419_E = 1017 , - WIFI_EXT_SPARE_REUSE_TAG_421_E = 1019 , - WIFI_EXT_SPARE_REUSE_TAG_423_E = 1021 -} ext_tlv_tag_def__e; - -typedef enum { - WIFI_N_EXT_MACTX_CBF_START_E = 0 , - WIFI_N_EXT_PHYRX_CBF_DATA_RESP_E = 2 , - WIFI_N_EXT_PHYRX_USER_ABORT_NOTIFICATION_E = 4 , - WIFI_N_EXT_MACTX_CBF_DATA_E = 6 , - WIFI_N_EXT_PHYRX_LMR_DATA_RESP_E = 8 , - WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 , - WIFI_N_EXT_RXPCU_TO_UCODE_FCS_STATUS_E = 12 , - WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 , - WIFI_N_EXT_RXPCU_TO_UCODE_END_E = 16 , - WIFI_N_EXT_PHYRX_NC_ABORT_REQUEST_E = 18 , - WIFI_N_EXT_PHYRX_NC_DATA_E = 20 , - WIFI_N_EXT_MACRX_CBF_READ_REQUEST_E = 64 , - WIFI_N_EXT_MACRX_EXPECT_NDP_RECEPTION_E = 66 , - WIFI_N_EXT_MACRX_NDP_TIMEOUT_E = 68 , - WIFI_N_EXT_MACRX_REQ_IMPLICIT_FB_E = 70 , - WIFI_N_EXT_MACRX_NAP_USER_E = 72 , - WIFI_N_EXT_PHYTX_OTHER_TRANSMIT_INFO16_E = 74 , - WIFI_N_EXT_PHYTX_ABORT_REQUEST_E = 76 , - WIFI_N_EXT_PHYTX_PPDU_HEADER_INFO_REQUEST_E = 78 , - WIFI_N_EXT_PHYTX_DATA_REQUEST_E = 80 , - WIFI_N_EXT_PHYTX_NAP_ACK_E = 82 , - WIFI_N_EXT_PHYTX_OFF_ACK_E = 84 , - WIFI_N_EXT_PHYTX_SYNTH_OFF_ACK_E = 86 , - WIFI_N_EXT_MACTX_ABORT_REQUEST_E = 88 , - WIFI_N_EXT_MACTX_PKT_END_E = 90 , - WIFI_N_EXT_MACTX_BF_PARAMS_COMMON_E = 92 , - WIFI_N_EXT_MACTX_PREFETCH_CV_E = 94 , - WIFI_N_EXT_MACTX_USER_DESC_PER_USER_E = 96 , - WIFI_N_EXT_EXAMPLE_TLV_16_E = 98 , - WIFI_N_EXT_MACTX_PHY_ON_E = 100 , - WIFI_N_EXT_MACTX_EXPECT_CBF_COMMON_E = 102 , - WIFI_N_EXT_MACTX_PHY_DESC_E = 104 , - WIFI_N_EXT_MACTX_L_SIG_B_E = 106 , - WIFI_N_EXT_MACTX_VHT_SIG_A_E = 108 , - WIFI_N_EXT_MACTX_VHT_SIG_B_SU40_E = 110 , - WIFI_N_EXT_MACTX_VHT_SIG_B_SU160_E = 112 , - WIFI_N_EXT_MACTX_VHT_SIG_B_MU40_E = 114 , - WIFI_N_EXT_MACTX_VHT_SIG_B_MU160_E = 116 , - WIFI_N_EXT_MACTX_HE_SIG_A_SU_E = 118 , - WIFI_N_EXT_MACTX_HE_SIG_A_MU_UL_E = 120 , - WIFI_N_EXT_MACTX_HE_SIG_B2_MU_E = 122 , - WIFI_N_EXT_MACTX_DELETE_CV_E = 124 , - WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_E = 126 , - WIFI_N_EXT_MACTX_PHY_NAP_E = 128 , - WIFI_N_EXT_PHYRX_ABORT_ACK_E = 130 , - WIFI_N_EXT_PHYRX_RSSI_LEGACY_E = 132 , - WIFI_N_EXT_PHYRX_USER_INFO_E = 134 , - WIFI_N_EXT_PHYRX_DEBUG_E = 136 , - WIFI_N_EXT_PHYRX_CBF_TRANSFER_ABORT_E = 138 , - WIFI_N_EXT_PHYRX_L_SIG_B_E = 140 , - WIFI_N_EXT_PHYRX_VHT_SIG_A_E = 142 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_SU40_E = 144 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_SU160_E = 146 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_MU40_E = 148 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_MU160_E = 150 , - WIFI_N_EXT_PHYRX_HE_SIG_A_MU_DL_E = 152 , - WIFI_N_EXT_PHYRX_HE_SIG_B1_MU_E = 154 , - WIFI_N_EXT_PHYRX_HE_SIG_B2_OFDMA_E = 156 , - WIFI_N_EXT_PHYRX_COMMON_USER_INFO_E = 158 , - WIFI_N_EXT_COEX_TX_REQ_E = 160 , - WIFI_N_EXT_EXAMPLE_TLV_32_NAME_E = 162 , - WIFI_N_EXT_NA_LENGTH_END_E = 164 , - WIFI_N_EXT_PCU_PPDU_SETUP_DONE_E = 166 , - WIFI_N_EXT_PCU_PPDU_SETUP_INIT_E = 168 , - WIFI_N_EXT_PDG_FES_SETUP_E = 170 , - WIFI_N_EXT_PDG_TX_REQ_E = 172 , - WIFI_N_EXT_MACTX_SWITCH_TO_MAIN_E = 174 , - WIFI_N_EXT_AUX_PPDU_END_E = 176 , - WIFI_N_EXT_TQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 178 , - WIFI_N_EXT_TQM_GEN_MPDUS_STATUS_E = 180 , - WIFI_N_EXT_TQM_REMOVE_MPDU_STATUS_E = 182 , - WIFI_N_EXT_TQM_REMOVE_MSDU_STATUS_E = 184 , - WIFI_N_EXT_TQM_WRITE_CMD_E = 186 , - WIFI_N_EXT_TX_DATA_E = 188 , - WIFI_N_EXT_RX_PACKET_E = 190 , - WIFI_N_EXT_TX_MPDU_END_E = 192 , - WIFI_N_EXT_TX_MSDU_END_E = 194 , - WIFI_N_EXT_TX_SW_MODE_SETUP_E = 196 , - WIFI_N_EXT_TXPCU_USER_BUFFER_STATUS_E = 198 , - WIFI_N_EXT_EXAMPLE_USER_TLV_32_E = 200 , - WIFI_N_EXT_PDG_USER_SETUP_E = 202 , - WIFI_N_EXT_TX_RAW_OR_NATIVE_FRAME_SETUP_E = 206 , - WIFI_N_EXT_TX_FLUSH_E = 208 , - WIFI_N_EXT_TQM_WRITE_CMD_STATUS_E = 210 , - WIFI_N_EXT_TQM_GET_MSDU_FLOW_STATS_E = 212 , - WIFI_N_EXT_TX_FES_STATUS_START_E = 214 , - WIFI_N_EXT_TX_FES_STATUS_USER_RESPONSE_E = 216 , - WIFI_N_EXT_RX_TRIG_INFO_E = 218 , - WIFI_N_EXT_RX_FRAME_BITMAP_REQ_E = 220 , - WIFI_N_EXT_COEX_RX_STATUS_E = 222 , - WIFI_N_EXT_RX_PPDU_START_E = 224 , - WIFI_N_EXT_RX_MPDU_START_E = 226 , - WIFI_N_EXT_RX_MSDU_START_E = 228 , - WIFI_N_EXT_RX_ATTENTION_E = 230 , - WIFI_N_EXT_RX_PHY_SLEEP_E = 232 , - WIFI_N_EXT_RX_PEER_ENTRY_E = 234 , - WIFI_N_EXT_RX_RESPONSE_REQUIRED_INFO_E = 236 , - WIFI_N_EXT_TQM_GET_MPDU_QUEUE_STATS_STATUS_E = 238 , - WIFI_N_EXT_TX_CBF_INFO_E = 240 , - WIFI_N_EXT_RX_MPDU_PCU_START_E = 242 , - WIFI_N_EXT_RX_USER_PPDU_END_E = 244 , - WIFI_N_EXT_RX_PREAMBLE_E = 246 , - WIFI_N_EXT_TX_LAST_MPDU_FETCHED_E = 248 , - WIFI_N_EXT_RXPCU_SETUP_E = 250 , - WIFI_N_EXT_TX_FES_STATUS_ACK_OR_BA_E = 252 , - WIFI_N_EXT_COEX_TX_RESP_E = 254 , - WIFI_N_EXT_MACTX_COEX_PHY_CTRL_E = 256 , - WIFI_N_EXT_RESPONSE_START_STATUS_E = 258 , - WIFI_N_EXT_CRYPTO_STATUS_E = 260 , - WIFI_N_EXT_COEX_TX_STOP_CTRL_E = 262 , - WIFI_N_EXT_RX_PPDU_NO_ACK_REPORT_E = 264 , - WIFI_N_EXT_SCHEDULER_COMMAND_STATUS_E = 266 , - WIFI_N_EXT_TX_FES_STATUS_PROT_E = 268 , - WIFI_N_EXT_TX_FES_STATUS_START_PROT_E = 270 , - WIFI_N_EXT_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 272 , - WIFI_N_EXT_WHO_ANCHOR_OFFSET_E = 274 , - WIFI_N_EXT_WHO_CCE_INFO_E = 276 , - WIFI_N_EXT_WHO_COMMIT_DONE_E = 278 , - WIFI_N_EXT_WHO_L2_LLC_E = 280 , - WIFI_N_EXT_WHO_L3_CHECKSUM_E = 282 , - WIFI_N_EXT_WHO_L4_CHECKSUM_E = 284 , - WIFI_N_EXT_WHO_MSDU_E = 286 , - WIFI_N_EXT_WHO_PACKET_DATA_E = 288 , - WIFI_N_EXT_WHO_PPDU_END_E = 290 , - WIFI_N_EXT_WHO_TSO_E = 292 , - WIFI_N_EXT_WHO_WMAC_HEADER_PV1_E = 294 , - WIFI_N_EXT_MPDU_INFO_END_E = 296 , - WIFI_N_EXT_TX_QUEUE_EXTENSION_E = 298 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 300 , - WIFI_N_EXT_TQM_ADD_MSDU_STATUS_E = 302 , - WIFI_N_EXT_WHO_TERMINATE_E = 304 , - WIFI_N_EXT_TX_CV_DATA_E = 306 , - WIFI_N_EXT_PROT_TX_END_E = 308 , - WIFI_N_EXT_TQM_SCH_INSTR_GLOBAL_END_E = 310 , - WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT_E = 312 , - WIFI_N_EXT_TQM_UNBLOCK_CACHE_E = 322 , - WIFI_N_EXT_TQM_UNBLOCK_CACHE_STATUS_E = 324 , - WIFI_N_EXT_RX_STATUS_BUFFER_DONE_E = 326 , - WIFI_N_EXT_SCHEDULER_TXOP_DURATION_TRIGGER_E = 328 , - WIFI_N_EXT_PHYRX_CBF_READ_REQUEST_ACK_E = 330 , - WIFI_N_EXT_TQM_SYNC_CMD_E = 332 , - WIFI_N_EXT_TQM_SYNC_CMD_STATUS_E = 334 , - WIFI_N_EXT_TCC_TQM_WRAPPER_CMD_E = 336 , - WIFI_N_EXT_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 340 , - WIFI_N_EXT_RX_PPDU_START_USER_INFO_E = 342 , - WIFI_N_EXT_COEX_MAC_NAP_E = 344 , - WIFI_N_EXT_WHO_MESH_CONTROL_E = 346 , - WIFI_N_EXT_PDG_SW_MODE_BW_END_E = 348 , - WIFI_N_EXT_PDG_WAIT_FOR_PHY_REQUEST_E = 350 , - WIFI_N_EXT_RX_PPDU_START_DROPPED_E = 352 , - WIFI_N_EXT_RX_PPDU_END_STATUS_DONE_DROPPED_E = 354 , - WIFI_N_EXT_RX_MSDU_START_DROPPED_E = 356 , - WIFI_N_EXT_RX_MPDU_END_DROPPED_E = 358 , - WIFI_N_EXT_TXPCU_USER_SETUP_E = 360 , - WIFI_N_EXT_CMD_PART_0_END_E = 362 , - WIFI_N_EXT_SCH_CRITICAL_TLV_REFERENCE_E = 364 , - WIFI_N_EXT_EXAMPLE_TLV_32_E = 366 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 368 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 370 , - WIFI_N_EXT_TQM_2_SCH_MPDU_AVAILABLE_E = 372 , - WIFI_N_EXT_TRIGGER_RESPONSE_TX_DONE_E = 374 , - WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_E = 376 , - WIFI_N_EXT_RECEIVED_RESPONSE_INFO_PART2_E = 378 , - WIFI_N_EXT_TXPCU_PREAMBLE_DONE_E = 380 , - WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_RBO_DROP_E = 382 , - WIFI_N_EXT_MACTX_CLEAR_PREV_TX_INFO_E = 384 , - WIFI_N_EXT_R2R_STATUS_END_E = 386 , - WIFI_N_EXT_END_OF_FLUSH_MARKER_E = 388 , - WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_PUNC_E = 390 , - WIFI_N_EXT_RECEIVED_RESPONSE_USER_15_8_E = 392 , - WIFI_N_EXT_RECEIVED_RESPONSE_USER_31_24_E = 394 , - WIFI_N_EXT_TX_LOOPBACK_SETUP_E = 396 , - WIFI_N_EXT_SCH_WAIT_INSTR_TX_PATH_E = 398 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 400 , - WIFI_N_EXT_TX_WUR_DATA_E = 402 , - WIFI_N_EXT_RX_PPDU_END_MIDDLE_E = 404 , - WIFI_N_EXT_MACTX_BACKOFF_BASED_TRANSMISSION_E = 406 , - WIFI_N_EXT_SRP_INFO_E = 408 , - WIFI_N_EXT_SCHEDULER_SW_MSG_STATUS_E = 410 , - WIFI_N_EXT_RXPCU_SETUP_COMPLETE_E = 412 , - WIFI_N_EXT_MACTX_MCC_SWITCH_BACK_E = 414 , - WIFI_N_EXT_PHYTX_MCC_SWITCH_BACK_ACK_E = 416 , - WIFI_N_EXT_LMR_TX_END_E = 418 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 420 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 422 , - WIFI_N_EXT_SCHEDULER_STATUS_WRAPPER_E = 424 , - WIFI_N_EXT_MACTX___RESERVED_G_0013 = 426 , - WIFI_N_EXT_MACTX_U_SIG_EHT_TB_E = 428 , - WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG1_CFG_E = 430 , - WIFI_N_EXT_PHYRX_U_SIG_EHT_SU_MU_E = 432 , - WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG3_CFG_E = 434 , - WIFI_N_EXT_TX_PUNCTURE_6PATTERNS_SETUP_E = 436 , - WIFI_N_EXT_MACRX_LMR_DATA_REQUEST_E = 438 , - WIFI_N_EXT_PHYRX_LMR_TRANSFER_ABORT_E = 440 , - WIFI_N_EXT_MACRX_SECURE_LTF_SEQ_PTR_E = 442 , - WIFI_N_EXT_MPDU_QUEUE_OVERVIEW_E = 444 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E = 446 , - WIFI_N_EXT_LMR_MPDU_START_E = 448 , - WIFI_N_EXT_LMR_MPDU_END_E = 450 , - WIFI_N_EXT_RX_FRAME_1K_BITMAP_ACK_E = 452 , - WIFI_N_EXT_TQM_ACKED_1K_MPDU_E = 454 , - WIFI_N_EXT_PHYRX_LOCATION_E = 456 , - WIFI_N_EXT_MLO_TX_NOTIFICATION_MU_E = 458 , - WIFI_N_EXT_MLO_TX_REQ_MU_E = 460 , - WIFI_N_EXT_MLO_RX_NOTIFICATION_E = 462 , - WIFI_N_EXT_MLO_TBTT_NOTIFICATION_E = 464 , - WIFI_N_EXT_MLO_TS_SYNC_MSG_E = 466 , - WIFI_N_EXT_MLO_PDG_FES_SETUP_SU_E = 468 , - WIFI_N_EXT_MPDU_INFO_1K_BITMAP_E = 470 , - WIFI_N_EXT_TX_FRAG_STATE_E = 472 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 474 , - WIFI_N_EXT_MACTX_U_SIG_UHR_SU_MU_E = 476 , - WIFI_N_EXT_TX_MPDU_COMPRESSED_DETAILS_TLV_E = 478 , - WIFI_N_EXT_TX_MSDU_COMPONENT_DETAILS_TLV_E = 480 , - WIFI_N_EXT_SCHEDULER_IU_TEMPLATE_ID_E = 482 , - WIFI_N_EXT_MACTX_EXPECT_NDP_RECEPTION_E = 484 , - WIFI_N_EXT_TX_MPDU_LENGTH_AND_RESTRICTIONS_E = 486 , - WIFI_N_EXT_PHYRX___RESERVED_G_0014 = 488 , - WIFI_N_EXT_PHYTX___RESERVED_G_0014 = 490 , - WIFI_N_EXT_MACTX_EHT_SIG_USR_SU_E = 492 , - WIFI_N_EXT_PHYRX_EHT_SIG_USR_SU_E = 494 , - WIFI_N_EXT_PHYRX_GENERIC_U_SIG_E = 496 , - WIFI_N_EXT_OVERWRITE_RESP_START_E = 498 , - WIFI_N_EXT_OVERWRITE_RESP_FRAME_INFO_E = 500 , - WIFI_N_EXT_RXPCU_EARLY_RX_INDICATION_E = 502 , - WIFI_N_EXT_MACRX_MU_UPLINK_COMMON_SNIFF_E = 504 , - WIFI_N_EXT_MACRX_MU_UPLINK_USER_SEL_SNIFF_E = 506 , - WIFI_N_EXT_MACTX_PREFETCH_CV_DMA_E = 508 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 510 , - WIFI_N_EXT_MACTX_BF_PARAMS_UPDATE_PER_USER_E = 512 , - WIFI_N_EXT_PHYTX_CV_CORR_STATUS_E = 514 , - WIFI_N_EXT_PHYTX_CV_CORR_USER_E = 516 , - WIFI_N_EXT_MACTX_CV_CORR_MAC_INFO_GROUP_E = 518 , - WIFI_N_EXT_MACTX_RX_NOTIFICATION_FOR_PHY_E = 520 , - WIFI_N_EXT_MACTX_MU_UPLINK_COMMON_PER_BW_E = 522 , - WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT2_E = 524 , - WIFI_N_EXT_WSI_DIRECT_MESSAGE_E = 526 , - WIFI_N_EXT_MACTX_EMLSR_SWITCH_E = 528 , - WIFI_N_EXT_PHYTX_EMLSR_SWITCH_ACK_E = 530 , - WIFI_N_EXT_EAD_COMMAND_E = 532 , - WIFI_N_EXT_EAD_LEGACY_INTERRUPT_CONTROL_E = 534 , - WIFI_N_EXT_TPI_ENABLE_RESPONSE_TIMEOUT_E = 536 , - WIFI_N_EXT_TPI_LEGACY_INTERRUPT_CONTROL_E = 538 , - WIFI_N_EXT_TPI_MPDU_CONTINUATION_E = 540 , - WIFI_N_EXT_TPI_SEND_TLV_TO_PHYTX_E = 542 , - WIFI_N_EXT_TPI_STATUS_E = 544 , - WIFI_N_EXT_TPI_TIMESTAMP_STATUS_E = 546 , - WIFI_N_EXT_RPI_LEGACY_STATUS_CONTROL_E = 548 , - WIFI_N_EXT_RPI_STATUS_E = 550 , - WIFI_N_EXT_RPI_TIMESTAMP_STATUS_E = 552 , - WIFI_N_EXT_TCC_PUSH_TRANSMIT_COMMAND_E = 554 , - WIFI_N_EXT_TCC_LEGACY_STATUS_CONTROL_E = 556 , - WIFI_N_EXT_TCC_STATUS_E = 558 , - WIFI_N_EXT_TCC_TIMESTAMP_STATUS_E = 560 , - WIFI_N_EXT_TCC_SCHEDULER_CMD_E = 562 , - WIFI_N_EXT_RPI_NON_DATA_CTLV_44_FROM_PHYRX_E = 564 , - WIFI_N_EXT_RPI_FETCH_INFO_FROM_EXT_MEM_E = 566 , - WIFI_N_EXT_RPI_INIT_CBF_DATA_RESP_ADDR_E = 568 , - WIFI_N_EXT_TPI_SEND_CBF_DATA_TO_PHYTX_E = 570 , - WIFI_N_EXT_TCC_FES_END_MESSAGE_E = 572 , - WIFI_N_EXT_TPI_DISABLE_RESPONSE_TIMEOUT_E = 574 , - WIFI_N_EXT_EAD_MSDU_STATUS_START_E = 576 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_SU_E = 578 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_OFDMA_E = 580 , - WIFI_N_EXT_COEX_BLACKOUT_DETAILS_E = 582 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E = 584 , - WIFI_N_EXT_HDR_CTRL_PROT_MPDU_START_E = 586 , - WIFI_N_EXT_HDR_CTRL_PROT_MPDU_END_E = 588 , - WIFI_N_EXT_HDR_CTRL_PROT_PEER_INFO_E = 590 , - WIFI_N_EXT_MACTX_U_SIG_UHR_ELR_SU_E = 592 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_COBF_E = 594 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_COSR_E = 596 , - WIFI_N_EXT_SPARE_REUSE_TAG_0_E = 598 , - WIFI_N_EXT_SPARE_REUSE_TAG_2_E = 600 , - WIFI_N_EXT_SPARE_REUSE_TAG_4_E = 602 , - WIFI_N_EXT_SPARE_REUSE_TAG_6_E = 604 , - WIFI_N_EXT_SPARE_REUSE_TAG_8_E = 606 , - WIFI_N_EXT_SPARE_REUSE_TAG_10_E = 608 , - WIFI_N_EXT_SPARE_REUSE_TAG_12_E = 610 , - WIFI_N_EXT_SPARE_REUSE_TAG_14_E = 612 , - WIFI_N_EXT_SPARE_REUSE_TAG_16_E = 614 , - WIFI_N_EXT_SPARE_REUSE_TAG_18_E = 616 , - WIFI_N_EXT_SPARE_REUSE_TAG_20_E = 618 , - WIFI_N_EXT_SPARE_REUSE_TAG_22_E = 620 , - WIFI_N_EXT_SPARE_REUSE_TAG_24_E = 622 , - WIFI_N_EXT_SPARE_REUSE_TAG_26_E = 624 , - WIFI_N_EXT_SPARE_REUSE_TAG_28_E = 626 , - WIFI_N_EXT_SPARE_REUSE_TAG_30_E = 628 , - WIFI_N_EXT_SPARE_REUSE_TAG_32_E = 630 , - WIFI_N_EXT_SPARE_REUSE_TAG_34_E = 632 , - WIFI_N_EXT_SPARE_REUSE_TAG_36_E = 634 , - WIFI_N_EXT_SPARE_REUSE_TAG_38_E = 636 , - WIFI_N_EXT_SPARE_REUSE_TAG_40_E = 638 , - WIFI_N_EXT_SPARE_REUSE_TAG_42_E = 640 , - WIFI_N_EXT_SPARE_REUSE_TAG_44_E = 642 , - WIFI_N_EXT_SPARE_REUSE_TAG_46_E = 644 , - WIFI_N_EXT_SPARE_REUSE_TAG_48_E = 646 , - WIFI_N_EXT_SPARE_REUSE_TAG_50_E = 648 , - WIFI_N_EXT_SPARE_REUSE_TAG_52_E = 650 , - WIFI_N_EXT_SPARE_REUSE_TAG_54_E = 652 , - WIFI_N_EXT_SPARE_REUSE_TAG_56_E = 654 , - WIFI_N_EXT_SPARE_REUSE_TAG_58_E = 656 , - WIFI_N_EXT_SPARE_REUSE_TAG_60_E = 658 , - WIFI_N_EXT_SPARE_REUSE_TAG_62_E = 660 , - WIFI_N_EXT_SPARE_REUSE_TAG_64_E = 662 , - WIFI_N_EXT_SPARE_REUSE_TAG_66_E = 664 , - WIFI_N_EXT_SPARE_REUSE_TAG_68_E = 666 , - WIFI_N_EXT_SPARE_REUSE_TAG_70_E = 668 , - WIFI_N_EXT_SPARE_REUSE_TAG_72_E = 670 , - WIFI_N_EXT_SPARE_REUSE_TAG_74_E = 672 , - WIFI_N_EXT_SPARE_REUSE_TAG_76_E = 674 , - WIFI_N_EXT_SPARE_REUSE_TAG_78_E = 676 , - WIFI_N_EXT_SPARE_REUSE_TAG_80_E = 678 , - WIFI_N_EXT_SPARE_REUSE_TAG_82_E = 680 , - WIFI_N_EXT_SPARE_REUSE_TAG_84_E = 682 , - WIFI_N_EXT_SPARE_REUSE_TAG_86_E = 684 , - WIFI_N_EXT_SPARE_REUSE_TAG_88_E = 686 , - WIFI_N_EXT_SPARE_REUSE_TAG_90_E = 688 , - WIFI_N_EXT_SPARE_REUSE_TAG_92_E = 690 , - WIFI_N_EXT_SPARE_REUSE_TAG_94_E = 692 , - WIFI_N_EXT_SPARE_REUSE_TAG_96_E = 694 , - WIFI_N_EXT_SPARE_REUSE_TAG_98_E = 696 , - WIFI_N_EXT_SPARE_REUSE_TAG_100_E = 698 , - WIFI_N_EXT_SPARE_REUSE_TAG_102_E = 700 , - WIFI_N_EXT_SPARE_REUSE_TAG_104_E = 702 , - WIFI_N_EXT_SPARE_REUSE_TAG_106_E = 704 , - WIFI_N_EXT_SPARE_REUSE_TAG_108_E = 706 , - WIFI_N_EXT_SPARE_REUSE_TAG_110_E = 708 , - WIFI_N_EXT_SPARE_REUSE_TAG_112_E = 710 , - WIFI_N_EXT_SPARE_REUSE_TAG_114_E = 712 , - WIFI_N_EXT_SPARE_REUSE_TAG_116_E = 714 , - WIFI_N_EXT_SPARE_REUSE_TAG_118_E = 716 , - WIFI_N_EXT_SPARE_REUSE_TAG_120_E = 718 , - WIFI_N_EXT_SPARE_REUSE_TAG_122_E = 720 , - WIFI_N_EXT_SPARE_REUSE_TAG_124_E = 722 , - WIFI_N_EXT_SPARE_REUSE_TAG_126_E = 724 , - WIFI_N_EXT_SPARE_REUSE_TAG_128_E = 726 , - WIFI_N_EXT_SPARE_REUSE_TAG_130_E = 728 , - WIFI_N_EXT_SPARE_REUSE_TAG_132_E = 730 , - WIFI_N_EXT_SPARE_REUSE_TAG_134_E = 732 , - WIFI_N_EXT_SPARE_REUSE_TAG_136_E = 734 , - WIFI_N_EXT_SPARE_REUSE_TAG_138_E = 736 , - WIFI_N_EXT_SPARE_REUSE_TAG_140_E = 738 , - WIFI_N_EXT_SPARE_REUSE_TAG_142_E = 740 , - WIFI_N_EXT_SPARE_REUSE_TAG_144_E = 742 , - WIFI_N_EXT_SPARE_REUSE_TAG_146_E = 744 , - WIFI_N_EXT_SPARE_REUSE_TAG_148_E = 746 , - WIFI_N_EXT_SPARE_REUSE_TAG_150_E = 748 , - WIFI_N_EXT_SPARE_REUSE_TAG_152_E = 750 , - WIFI_N_EXT_SPARE_REUSE_TAG_154_E = 752 , - WIFI_N_EXT_SPARE_REUSE_TAG_156_E = 754 , - WIFI_N_EXT_SPARE_REUSE_TAG_158_E = 756 , - WIFI_N_EXT_SPARE_REUSE_TAG_160_E = 758 , - WIFI_N_EXT_SPARE_REUSE_TAG_162_E = 760 , - WIFI_N_EXT_SPARE_REUSE_TAG_164_E = 762 , - WIFI_N_EXT_SPARE_REUSE_TAG_166_E = 764 , - WIFI_N_EXT_SPARE_REUSE_TAG_168_E = 766 , - WIFI_N_EXT_SPARE_REUSE_TAG_170_E = 768 , - WIFI_N_EXT_SPARE_REUSE_TAG_172_E = 770 , - WIFI_N_EXT_SPARE_REUSE_TAG_174_E = 772 , - WIFI_N_EXT_SPARE_REUSE_TAG_176_E = 774 , - WIFI_N_EXT_SPARE_REUSE_TAG_178_E = 776 , - WIFI_N_EXT_SPARE_REUSE_TAG_180_E = 778 , - WIFI_N_EXT_SPARE_REUSE_TAG_182_E = 780 , - WIFI_N_EXT_SPARE_REUSE_TAG_184_E = 782 , - WIFI_N_EXT_SPARE_REUSE_TAG_186_E = 784 , - WIFI_N_EXT_SPARE_REUSE_TAG_188_E = 786 , - WIFI_N_EXT_SPARE_REUSE_TAG_190_E = 788 , - WIFI_N_EXT_SPARE_REUSE_TAG_192_E = 790 , - WIFI_N_EXT_SPARE_REUSE_TAG_194_E = 792 , - WIFI_N_EXT_SPARE_REUSE_TAG_196_E = 794 , - WIFI_N_EXT_SPARE_REUSE_TAG_198_E = 796 , - WIFI_N_EXT_SPARE_REUSE_TAG_200_E = 798 , - WIFI_N_EXT_SPARE_REUSE_TAG_202_E = 800 , - WIFI_N_EXT_SPARE_REUSE_TAG_204_E = 802 , - WIFI_N_EXT_SPARE_REUSE_TAG_206_E = 804 , - WIFI_N_EXT_SPARE_REUSE_TAG_208_E = 806 , - WIFI_N_EXT_SPARE_REUSE_TAG_210_E = 808 , - WIFI_N_EXT_SPARE_REUSE_TAG_212_E = 810 , - WIFI_N_EXT_SPARE_REUSE_TAG_214_E = 812 , - WIFI_N_EXT_SPARE_REUSE_TAG_216_E = 814 , - WIFI_N_EXT_SPARE_REUSE_TAG_218_E = 816 , - WIFI_N_EXT_SPARE_REUSE_TAG_220_E = 818 , - WIFI_N_EXT_SPARE_REUSE_TAG_222_E = 820 , - WIFI_N_EXT_SPARE_REUSE_TAG_224_E = 822 , - WIFI_N_EXT_SPARE_REUSE_TAG_226_E = 824 , - WIFI_N_EXT_SPARE_REUSE_TAG_228_E = 826 , - WIFI_N_EXT_SPARE_REUSE_TAG_230_E = 828 , - WIFI_N_EXT_SPARE_REUSE_TAG_232_E = 830 , - WIFI_N_EXT_SPARE_REUSE_TAG_234_E = 832 , - WIFI_N_EXT_SPARE_REUSE_TAG_236_E = 834 , - WIFI_N_EXT_SPARE_REUSE_TAG_238_E = 836 , - WIFI_N_EXT_SPARE_REUSE_TAG_240_E = 838 , - WIFI_N_EXT_SPARE_REUSE_TAG_242_E = 840 , - WIFI_N_EXT_SPARE_REUSE_TAG_244_E = 842 , - WIFI_N_EXT_SPARE_REUSE_TAG_246_E = 844 , - WIFI_N_EXT_SPARE_REUSE_TAG_248_E = 846 , - WIFI_N_EXT_SPARE_REUSE_TAG_250_E = 848 , - WIFI_N_EXT_SPARE_REUSE_TAG_252_E = 850 , - WIFI_N_EXT_SPARE_REUSE_TAG_254_E = 852 , - WIFI_N_EXT_SPARE_REUSE_TAG_256_E = 854 , - WIFI_N_EXT_SPARE_REUSE_TAG_258_E = 856 , - WIFI_N_EXT_SPARE_REUSE_TAG_260_E = 858 , - WIFI_N_EXT_SPARE_REUSE_TAG_262_E = 860 , - WIFI_N_EXT_SPARE_REUSE_TAG_264_E = 862 , - WIFI_N_EXT_SPARE_REUSE_TAG_266_E = 864 , - WIFI_N_EXT_SPARE_REUSE_TAG_268_E = 866 , - WIFI_N_EXT_SPARE_REUSE_TAG_270_E = 868 , - WIFI_N_EXT_SPARE_REUSE_TAG_272_E = 870 , - WIFI_N_EXT_SPARE_REUSE_TAG_274_E = 872 , - WIFI_N_EXT_SPARE_REUSE_TAG_276_E = 874 , - WIFI_N_EXT_SPARE_REUSE_TAG_278_E = 876 , - WIFI_N_EXT_SPARE_REUSE_TAG_280_E = 878 , - WIFI_N_EXT_SPARE_REUSE_TAG_282_E = 880 , - WIFI_N_EXT_SPARE_REUSE_TAG_284_E = 882 , - WIFI_N_EXT_SPARE_REUSE_TAG_286_E = 884 , - WIFI_N_EXT_SPARE_REUSE_TAG_288_E = 886 , - WIFI_N_EXT_SPARE_REUSE_TAG_290_E = 888 , - WIFI_N_EXT_SPARE_REUSE_TAG_292_E = 890 , - WIFI_N_EXT_SPARE_REUSE_TAG_294_E = 892 , - WIFI_N_EXT_SPARE_REUSE_TAG_296_E = 894 , - WIFI_N_EXT_SPARE_REUSE_TAG_298_E = 896 , - WIFI_N_EXT_SPARE_REUSE_TAG_300_E = 898 , - WIFI_N_EXT_SPARE_REUSE_TAG_302_E = 900 , - WIFI_N_EXT_SPARE_REUSE_TAG_304_E = 902 , - WIFI_N_EXT_SPARE_REUSE_TAG_306_E = 904 , - WIFI_N_EXT_SPARE_REUSE_TAG_308_E = 906 , - WIFI_N_EXT_SPARE_REUSE_TAG_310_E = 908 , - WIFI_N_EXT_SPARE_REUSE_TAG_312_E = 910 , - WIFI_N_EXT_SPARE_REUSE_TAG_314_E = 912 , - WIFI_N_EXT_SPARE_REUSE_TAG_316_E = 914 , - WIFI_N_EXT_SPARE_REUSE_TAG_318_E = 916 , - WIFI_N_EXT_SPARE_REUSE_TAG_320_E = 918 , - WIFI_N_EXT_SPARE_REUSE_TAG_322_E = 920 , - WIFI_N_EXT_SPARE_REUSE_TAG_324_E = 922 , - WIFI_N_EXT_SPARE_REUSE_TAG_326_E = 924 , - WIFI_N_EXT_SPARE_REUSE_TAG_328_E = 926 , - WIFI_N_EXT_SPARE_REUSE_TAG_330_E = 928 , - WIFI_N_EXT_SPARE_REUSE_TAG_332_E = 930 , - WIFI_N_EXT_SPARE_REUSE_TAG_334_E = 932 , - WIFI_N_EXT_SPARE_REUSE_TAG_336_E = 934 , - WIFI_N_EXT_SPARE_REUSE_TAG_338_E = 936 , - WIFI_N_EXT_SPARE_REUSE_TAG_340_E = 938 , - WIFI_N_EXT_SPARE_REUSE_TAG_342_E = 940 , - WIFI_N_EXT_SPARE_REUSE_TAG_344_E = 942 , - WIFI_N_EXT_SPARE_REUSE_TAG_346_E = 944 , - WIFI_N_EXT_SPARE_REUSE_TAG_348_E = 946 , - WIFI_N_EXT_SPARE_REUSE_TAG_350_E = 948 , - WIFI_N_EXT_SPARE_REUSE_TAG_352_E = 950 , - WIFI_N_EXT_SPARE_REUSE_TAG_354_E = 952 , - WIFI_N_EXT_SPARE_REUSE_TAG_356_E = 954 , - WIFI_N_EXT_SPARE_REUSE_TAG_358_E = 956 , - WIFI_N_EXT_SPARE_REUSE_TAG_360_E = 958 , - WIFI_N_EXT_SPARE_REUSE_TAG_362_E = 960 , - WIFI_N_EXT_SPARE_REUSE_TAG_364_E = 962 , - WIFI_N_EXT_SPARE_REUSE_TAG_366_E = 964 , - WIFI_N_EXT_SPARE_REUSE_TAG_368_E = 966 , - WIFI_N_EXT_SPARE_REUSE_TAG_370_E = 968 , - WIFI_N_EXT_SPARE_REUSE_TAG_372_E = 970 , - WIFI_N_EXT_SPARE_REUSE_TAG_374_E = 972 , - WIFI_N_EXT_SPARE_REUSE_TAG_376_E = 974 , - WIFI_N_EXT_SPARE_REUSE_TAG_378_E = 976 , - WIFI_N_EXT_SPARE_REUSE_TAG_380_E = 978 , - WIFI_N_EXT_SPARE_REUSE_TAG_382_E = 980 , - WIFI_N_EXT_SPARE_REUSE_TAG_384_E = 982 , - WIFI_N_EXT_SPARE_REUSE_TAG_386_E = 984 , - WIFI_N_EXT_SPARE_REUSE_TAG_388_E = 986 , - WIFI_N_EXT_SPARE_REUSE_TAG_390_E = 988 , - WIFI_N_EXT_SPARE_REUSE_TAG_392_E = 990 , - WIFI_N_EXT_SPARE_REUSE_TAG_394_E = 992 , - WIFI_N_EXT_SPARE_REUSE_TAG_396_E = 994 , - WIFI_N_EXT_SPARE_REUSE_TAG_398_E = 996 , - WIFI_N_EXT_SPARE_REUSE_TAG_400_E = 998 , - WIFI_N_EXT_SPARE_REUSE_TAG_402_E = 1000 , - WIFI_N_EXT_SPARE_REUSE_TAG_404_E = 1002 , - WIFI_N_EXT_SPARE_REUSE_TAG_406_E = 1004 , - WIFI_N_EXT_SPARE_REUSE_TAG_408_E = 1006 , - WIFI_N_EXT_SPARE_REUSE_TAG_410_E = 1008 , - WIFI_N_EXT_SPARE_REUSE_TAG_412_E = 1010 , - WIFI_N_EXT_SPARE_REUSE_TAG_414_E = 1012 , - WIFI_N_EXT_SPARE_REUSE_TAG_416_E = 1014 , - WIFI_N_EXT_SPARE_REUSE_TAG_418_E = 1016 , - WIFI_N_EXT_SPARE_REUSE_TAG_420_E = 1018 , - WIFI_N_EXT_SPARE_REUSE_TAG_422_E = 1020 -} non_ext_tlv_tag_def__e; - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tqm2sw_completion_ring.h b/drivers/staging/fw-api/hw/fig/v2/tqm2sw_completion_ring.h deleted file mode 100644 index f67deea1f6a1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tqm2sw_completion_ring.h +++ /dev/null @@ -1,262 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TQM2SW_COMPLETION_RING_H_ -#define _TQM2SW_COMPLETION_RING_H_ - -#include "tx_rate_stats_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_TQM2SW_COMPLETION_RING 8 - -struct tqm2sw_completion_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_desc_virt_addr_or_addr_info; - uint32_t release_source_module : 3, - cache_id : 1, - reserved_2a : 2, - buffer_or_desc_type : 3, - return_buffer_manager : 4, - tqm_release_reason : 4, - rbm_override_valid : 1, - sw_buffer_cookie_11_0 : 12, - cookie_conversion_status : 1, - tqm_completion_error : 1; - uint32_t tqm_status_number : 24, - transmit_count : 7, - sw_release_details_valid : 1; - uint32_t ack_frame_rssi : 8, - first_msdu : 1, - last_msdu : 1, - fw_tx_notify_frame : 3, - buffer_timestamp : 19; - struct tx_rate_stats_info tx_rate_stats; - uint32_t sw_peer_id : 16, - tid : 4, - sw_buffer_cookie_19_12 : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_desc_virt_addr_or_addr_info; - uint32_t tqm_completion_error : 1, - cookie_conversion_status : 1, - sw_buffer_cookie_11_0 : 12, - rbm_override_valid : 1, - tqm_release_reason : 4, - return_buffer_manager : 4, - buffer_or_desc_type : 3, - reserved_2a : 2, - cache_id : 1, - release_source_module : 3; - uint32_t sw_release_details_valid : 1, - transmit_count : 7, - tqm_status_number : 24; - uint32_t buffer_timestamp : 19, - fw_tx_notify_frame : 3, - last_msdu : 1, - first_msdu : 1, - ack_frame_rssi : 8; - struct tx_rate_stats_info tx_rate_stats; - uint32_t looping_count : 4, - sw_buffer_cookie_19_12 : 8, - tid : 4, - sw_peer_id : 16; -#endif -}; - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define TQM2SW_COMPLETION_RING_CACHE_ID_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_CACHE_ID_LSB 3 -#define TQM2SW_COMPLETION_RING_CACHE_ID_MSB 3 -#define TQM2SW_COMPLETION_RING_CACHE_ID_MASK 0x00000008 - -#define TQM2SW_COMPLETION_RING_RESERVED_2A_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_LSB 4 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_MSB 5 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_MASK 0x00000030 - -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_LSB 6 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MSB 8 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_LSB 9 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MSB 12 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MASK 0x00001e00 - -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_LSB 13 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MSB 16 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MASK 0x0001e000 - -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_LSB 17 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MSB 17 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MASK 0x00020000 - -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_LSB 18 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MSB 29 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 - -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_LSB 30 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MSB 30 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MASK 0x40000000 - -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_LSB 31 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MSB 31 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MASK 0x80000000 - -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_LSB 0 -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MSB 23 -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MASK 0x00ffffff - -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_LSB 24 -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MSB 30 -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MASK 0x7f000000 - -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_LSB 31 -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MSB 31 -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 - -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_LSB 0 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MSB 7 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MASK 0x000000ff - -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_LSB 8 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MSB 8 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MASK 0x00000100 - -#define TQM2SW_COMPLETION_RING_LAST_MSDU_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_LSB 9 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_MSB 9 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_MASK 0x00000200 - -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_LSB 10 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MSB 12 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 - -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_LSB 13 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MSB 31 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MASK 0xffffe000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_LSB 1 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MSB 3 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MSB 16 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0001f000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_LSB 17 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MSB 19 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MASK 0x000e0000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 20 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 20 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00100000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_LSB 21 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MSB 24 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MASK 0x01e00000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_LSB 25 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MSB 28 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MASK 0x1e000000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff - -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_LSB 0 -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MSB 15 -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MASK 0x0000ffff - -#define TQM2SW_COMPLETION_RING_TID_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_TID_LSB 16 -#define TQM2SW_COMPLETION_RING_TID_MSB 19 -#define TQM2SW_COMPLETION_RING_TID_MASK 0x000f0000 - -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_LSB 20 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MSB 27 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 - -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_LSB 28 -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MSB 31 -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_cbf_info.h b/drivers/staging/fw-api/hw/fig/v2/tx_cbf_info.h deleted file mode 100644 index fed064ce95a8..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_cbf_info.h +++ /dev/null @@ -1,454 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_CBF_INFO_H_ -#define _TX_CBF_INFO_H_ - -#define NUM_OF_DWORDS_TX_CBF_INFO 16 - -#define NUM_OF_QWORDS_TX_CBF_INFO 8 - -struct tx_cbf_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sw_peer_id : 16, - pre_cbf_duration : 16; - uint32_t brpoll_info_valid : 1, - trigger_brpoll_info_valid : 1, - npda_info_11ac_valid : 1, - npda_info_11ax_valid : 1, - dot11ax_su_extended : 1, - bandwidth : 3, - brpoll_info : 8, - cbf_response_table_base_index : 8, - peer_index : 3, - pkt_type : 4, - txop_duration_all_ones : 1; - uint32_t trigger_brpoll_common_info_15_0 : 16, - trigger_brpoll_common_info_31_16 : 16; - uint32_t trigger_brpoll_user_info_15_0 : 16, - trigger_brpoll_user_info_31_16 : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t addr3_47_32 : 16, - sta_partial_aid : 11, - __reserved_g_0035 : 1, - reserved_8a : 3, - cbf_resp_pwr_mgmt : 1; - uint32_t group_id : 6, - rssi_comb : 8, - reserved_9a : 2, - vht_ndpa_sta_info : 16; - uint32_t he_eht_sta_info_15_0 : 16, - he_eht_sta_info_31_16 : 16; - uint32_t dot11ax_received_format_indication : 1, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_bss_color_id : 6, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_cp_size : 2, - dot11ax_received_ltf_size : 2, - dot11ax_received_coding : 1, - dot11ax_received_dcm : 1, - dot11ax_received_doppler_indication : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_dl_ul_flag : 1, - reserved_11a : 8; - uint32_t sw_response_frame_length : 16, - sw_response_tlv_from_crypto : 1, - wait_sifs_config_valid : 1, - wait_sifs : 2, - __reserved_g_0022 : 1, - secure : 1, - tb___reserved_g_0022_response_required : 2, - emlsr_main_tlv_if : 1, - reserved_12a : 1, - u_sig_puncture_pattern_encoding : 6; - uint32_t dot11be_puncture_bitmap : 16, - dot11be_response : 1, - punctured_response : 1, - npda_info_11be_valid : 1, - eht_duplicate_mode : 2, - reserved_13a : 11; - uint32_t eht_sta_info_39_32 : 8, - unassociated___reserved_g_0022_peer : 1, - reserved_14a : 23; - uint32_t tlv64_padding : 32; -#else - uint32_t pre_cbf_duration : 16, - sw_peer_id : 16; - uint32_t txop_duration_all_ones : 1, - pkt_type : 4, - peer_index : 3, - cbf_response_table_base_index : 8, - brpoll_info : 8, - bandwidth : 3, - dot11ax_su_extended : 1, - npda_info_11ax_valid : 1, - npda_info_11ac_valid : 1, - trigger_brpoll_info_valid : 1, - brpoll_info_valid : 1; - uint32_t trigger_brpoll_common_info_31_16 : 16, - trigger_brpoll_common_info_15_0 : 16; - uint32_t trigger_brpoll_user_info_31_16 : 16, - trigger_brpoll_user_info_15_0 : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t cbf_resp_pwr_mgmt : 1, - reserved_8a : 3, - __reserved_g_0035 : 1, - sta_partial_aid : 11, - addr3_47_32 : 16; - uint32_t vht_ndpa_sta_info : 16, - reserved_9a : 2, - rssi_comb : 8, - group_id : 6; - uint32_t he_eht_sta_info_31_16 : 16, - he_eht_sta_info_15_0 : 16; - uint32_t reserved_11a : 8, - dot11ax_dl_ul_flag : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_received_doppler_indication : 1, - dot11ax_received_dcm : 1, - dot11ax_received_coding : 1, - dot11ax_received_ltf_size : 2, - dot11ax_received_cp_size : 2, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_bss_color_id : 6, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_format_indication : 1; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_12a : 1, - emlsr_main_tlv_if : 1, - tb___reserved_g_0022_response_required : 2, - secure : 1, - __reserved_g_0022 : 1, - wait_sifs : 2, - wait_sifs_config_valid : 1, - sw_response_tlv_from_crypto : 1, - sw_response_frame_length : 16; - uint32_t reserved_13a : 11, - eht_duplicate_mode : 2, - npda_info_11be_valid : 1, - punctured_response : 1, - dot11be_response : 1, - dot11be_puncture_bitmap : 16; - uint32_t reserved_14a : 23, - unassociated___reserved_g_0022_peer : 1, - eht_sta_info_39_32 : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_CBF_INFO_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_SW_PEER_ID_LSB 0 -#define TX_CBF_INFO_SW_PEER_ID_MSB 15 -#define TX_CBF_INFO_SW_PEER_ID_MASK 0x000000000000ffff - -#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PRE_CBF_DURATION_LSB 16 -#define TX_CBF_INFO_PRE_CBF_DURATION_MSB 31 -#define TX_CBF_INFO_PRE_CBF_DURATION_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB 32 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB 32 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK 0x0000000100000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB 33 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB 33 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK 0x0000000200000000 - -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB 34 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB 34 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK 0x0000000400000000 - -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB 35 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB 35 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK 0x0000000800000000 - -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB 36 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB 36 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000001000000000 - -#define TX_CBF_INFO_BANDWIDTH_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BANDWIDTH_LSB 37 -#define TX_CBF_INFO_BANDWIDTH_MSB 39 -#define TX_CBF_INFO_BANDWIDTH_MASK 0x000000e000000000 - -#define TX_CBF_INFO_BRPOLL_INFO_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BRPOLL_INFO_LSB 40 -#define TX_CBF_INFO_BRPOLL_INFO_MSB 47 -#define TX_CBF_INFO_BRPOLL_INFO_MASK 0x0000ff0000000000 - -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB 48 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB 55 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK 0x00ff000000000000 - -#define TX_CBF_INFO_PEER_INDEX_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PEER_INDEX_LSB 56 -#define TX_CBF_INFO_PEER_INDEX_MSB 58 -#define TX_CBF_INFO_PEER_INDEX_MASK 0x0700000000000000 - -#define TX_CBF_INFO_PKT_TYPE_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PKT_TYPE_LSB 59 -#define TX_CBF_INFO_PKT_TYPE_MSB 62 -#define TX_CBF_INFO_PKT_TYPE_MASK 0x7800000000000000 - -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB 63 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB 63 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB 0 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB 15 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK 0x000000000000ffff - -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB 16 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB 31 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB 32 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB 47 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB 48 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB 63 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK 0xffff000000000000 - -#define TX_CBF_INFO_ADDR1_31_0_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR1_31_0_LSB 0 -#define TX_CBF_INFO_ADDR1_31_0_MSB 31 -#define TX_CBF_INFO_ADDR1_31_0_MASK 0x00000000ffffffff - -#define TX_CBF_INFO_ADDR1_47_32_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR1_47_32_LSB 32 -#define TX_CBF_INFO_ADDR1_47_32_MSB 47 -#define TX_CBF_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_ADDR2_15_0_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR2_15_0_LSB 48 -#define TX_CBF_INFO_ADDR2_15_0_MSB 63 -#define TX_CBF_INFO_ADDR2_15_0_MASK 0xffff000000000000 - -#define TX_CBF_INFO_ADDR2_47_16_OFFSET 0x0000000000000018 -#define TX_CBF_INFO_ADDR2_47_16_LSB 0 -#define TX_CBF_INFO_ADDR2_47_16_MSB 31 -#define TX_CBF_INFO_ADDR2_47_16_MASK 0x00000000ffffffff - -#define TX_CBF_INFO_ADDR3_31_0_OFFSET 0x0000000000000018 -#define TX_CBF_INFO_ADDR3_31_0_LSB 32 -#define TX_CBF_INFO_ADDR3_31_0_MSB 63 -#define TX_CBF_INFO_ADDR3_31_0_MASK 0xffffffff00000000 - -#define TX_CBF_INFO_ADDR3_47_32_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_ADDR3_47_32_LSB 0 -#define TX_CBF_INFO_ADDR3_47_32_MSB 15 -#define TX_CBF_INFO_ADDR3_47_32_MASK 0x000000000000ffff - -#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_STA_PARTIAL_AID_LSB 16 -#define TX_CBF_INFO_STA_PARTIAL_AID_MSB 26 -#define TX_CBF_INFO_STA_PARTIAL_AID_MASK 0x0000000007ff0000 - -#define TX_CBF_INFO_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RESERVED_8A_LSB 28 -#define TX_CBF_INFO_RESERVED_8A_MSB 30 -#define TX_CBF_INFO_RESERVED_8A_MASK 0x0000000070000000 - -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB 31 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB 31 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK 0x0000000080000000 - -#define TX_CBF_INFO_GROUP_ID_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_GROUP_ID_LSB 32 -#define TX_CBF_INFO_GROUP_ID_MSB 37 -#define TX_CBF_INFO_GROUP_ID_MASK 0x0000003f00000000 - -#define TX_CBF_INFO_RSSI_COMB_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RSSI_COMB_LSB 38 -#define TX_CBF_INFO_RSSI_COMB_MSB 45 -#define TX_CBF_INFO_RSSI_COMB_MASK 0x00003fc000000000 - -#define TX_CBF_INFO_RESERVED_9A_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RESERVED_9A_LSB 46 -#define TX_CBF_INFO_RESERVED_9A_MSB 47 -#define TX_CBF_INFO_RESERVED_9A_MASK 0x0000c00000000000 - -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB 48 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB 63 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK 0xffff000000000000 - -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB 0 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB 15 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK 0x000000000000ffff - -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB 16 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB 31 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB 48 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB 48 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB 49 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB 49 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 - -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB 55 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB 55 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0080000000000000 - -#define TX_CBF_INFO_RESERVED_11A_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_RESERVED_11A_LSB 56 -#define TX_CBF_INFO_RESERVED_11A_MSB 63 -#define TX_CBF_INFO_RESERVED_11A_MASK 0xff00000000000000 - -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x000000000000ffff - -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 16 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 16 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000000010000 - -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB 17 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB 17 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000000020000 - -#define TX_CBF_INFO_WAIT_SIFS_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_WAIT_SIFS_LSB 18 -#define TX_CBF_INFO_WAIT_SIFS_MSB 19 -#define TX_CBF_INFO_WAIT_SIFS_MASK 0x00000000000c0000 - -#define TX_CBF_INFO_SECURE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SECURE_LSB 21 -#define TX_CBF_INFO_SECURE_MSB 21 -#define TX_CBF_INFO_SECURE_MASK 0x0000000000200000 - -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_LSB 24 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MSB 24 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MASK 0x0000000001000000 - -#define TX_CBF_INFO_RESERVED_12A_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_RESERVED_12A_LSB 25 -#define TX_CBF_INFO_RESERVED_12A_MSB 25 -#define TX_CBF_INFO_RESERVED_12A_MASK 0x0000000002000000 - -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB 48 -#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB 48 -#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 - -#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB 49 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB 49 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 - -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB 50 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB 50 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK 0x0004000000000000 - -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB 51 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB 52 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK 0x0018000000000000 - -#define TX_CBF_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_RESERVED_13A_LSB 53 -#define TX_CBF_INFO_RESERVED_13A_MSB 63 -#define TX_CBF_INFO_RESERVED_13A_MASK 0xffe0000000000000 - -#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB 0 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB 7 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK 0x00000000000000ff - -#define TX_CBF_INFO_RESERVED_14A_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_RESERVED_14A_LSB 9 -#define TX_CBF_INFO_RESERVED_14A_MSB 31 -#define TX_CBF_INFO_RESERVED_14A_MASK 0x00000000fffffe00 - -#define TX_CBF_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_TLV64_PADDING_LSB 32 -#define TX_CBF_INFO_TLV64_PADDING_MSB 63 -#define TX_CBF_INFO_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_setup.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_setup.h deleted file mode 100644 index 143ee87f4a5f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_setup.h +++ /dev/null @@ -1,585 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_SETUP_H_ -#define _TX_FES_SETUP_H_ - -#define NUM_OF_DWORDS_TX_FES_SETUP 10 - -#define NUM_OF_QWORDS_TX_FES_SETUP 5 - -struct tx_fes_setup { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t schedule_id : 32; - uint32_t fes_in_11ax_trigger_response_config : 1, - bo_based_tid_aggregation_limit : 4, - __reserved_g_0022 : 1, - expect_i2r_lmr : 1, - transmit_start_reason : 3, - use_alt_power_sr : 1, - static_2_pwr_mode_status : 1, - obss_srg_opport_transmit_status : 1, - srp_based_transmit_status : 1, - obss_pd_based_transmit_status : 1, - puncture_from_all_allowed_modes : 1, - schedule_cmd_ring_id : 5, - fes_control_mode : 2, - number_of_users : 6, - mu_type : 1, - ofdma_triggered_response : 1, - response_to_response_cmd : 1; - uint32_t schedule_try : 4, - reserved_2a : 1, - subband_antenna_selection_en : 1, - txbf : 1, - allow_txop_exceed_in_1st_pkt : 1, - ignore_bw_available : 1, - ignore_tbtt : 1, - static_bandwidth : 3, - set_txop_duration_all_ones : 1, - transmission_contains_mu_rts : 1, - bw_restricted_frames_embedded : 1, - ast_index : 16; - uint32_t cv_id : 8, - trigger_resp_txpdu_ppdu_boundary : 2, - rxpcu_setup_complete_present : 1, - rbo_must_have_data_user_limit : 4, - mu_ndp : 1, - bf_type : 2, - cbf_nc_index_mask : 1, - cbf_nc_index : 3, - cbf_nr_index_mask : 1, - cbf_nr_index : 3, - secure___reserved_g_0022_ista : 1, - ndpa : 1, - wait_sifs : 2, - cbf_feedback_type_mask : 1, - cbf_feedback_type : 1; - uint32_t cbf_sounding_token : 6, - cbf_sounding_token_mask : 1, - cbf_bw_mask : 1, - cbf_bw : 3, - use_static_bw : 1, - coex_nack_count : 5, - sch_tx_burst_ongoing : 1, - gen_tqm_update_mpdu_count_tlv : 1, - rts_tx_over___reserved_g_0016 : 1, - ndp_frame : 3, - optimal_bw_retry_count : 4, - fes_continuation_ratio_threshold : 5; - uint32_t transmit_cca_bitmap : 32; - uint32_t tb___reserved_g_0022 : 1, - __reserved_g_0022_trigger_subtype : 4, - min_cts2self_count : 4, - max_cts2self_count : 4, - wifi_radar_enable : 1, - reserved_6a : 1, - wait_for_chksum_done : 1, - txrx_self_test_enable : 1, - rtt_self_cal_enable : 1, - secure___reserved_g_0022_rsta : 1, - hip_edca_prot_enable : 1, - hip_edca_prot_required : 1, - hip_edca_mini_contention_gap : 8, - last_command_in_burst : 1, - retain_peer_blackout_details : 1, - enable_hw_qos_null : 1; - uint32_t monitor_override_sta_31_0 : 32; - uint32_t monitor_override_sta_36_32 : 5, - enable_qos_null_switch_for_eosp : 1, - __reserved_g_0035 : 1, - secure___reserved_g_0035_smr : 1, - __reserved_g_0035_type : 2, - __reserved_g_0035_trigger_subtype : 4, - cfp_protected_fes : 1, - dot11ax_trigger_frame_embedded : 1, - multiple_triggers_indication : 1, - cmf_uif_length : 4, - npca_switching_cts2self_duration : 8, - reserved_8a : 3; - uint32_t fw2sw_info : 32; -#else - uint32_t schedule_id : 32; - uint32_t response_to_response_cmd : 1, - ofdma_triggered_response : 1, - mu_type : 1, - number_of_users : 6, - fes_control_mode : 2, - schedule_cmd_ring_id : 5, - puncture_from_all_allowed_modes : 1, - obss_pd_based_transmit_status : 1, - srp_based_transmit_status : 1, - obss_srg_opport_transmit_status : 1, - static_2_pwr_mode_status : 1, - use_alt_power_sr : 1, - transmit_start_reason : 3, - expect_i2r_lmr : 1, - __reserved_g_0022 : 1, - bo_based_tid_aggregation_limit : 4, - fes_in_11ax_trigger_response_config : 1; - uint32_t ast_index : 16, - bw_restricted_frames_embedded : 1, - transmission_contains_mu_rts : 1, - set_txop_duration_all_ones : 1, - static_bandwidth : 3, - ignore_tbtt : 1, - ignore_bw_available : 1, - allow_txop_exceed_in_1st_pkt : 1, - txbf : 1, - subband_antenna_selection_en : 1, - reserved_2a : 1, - schedule_try : 4; - uint32_t cbf_feedback_type : 1, - cbf_feedback_type_mask : 1, - wait_sifs : 2, - ndpa : 1, - secure___reserved_g_0022_ista : 1, - cbf_nr_index : 3, - cbf_nr_index_mask : 1, - cbf_nc_index : 3, - cbf_nc_index_mask : 1, - bf_type : 2, - mu_ndp : 1, - rbo_must_have_data_user_limit : 4, - rxpcu_setup_complete_present : 1, - trigger_resp_txpdu_ppdu_boundary : 2, - cv_id : 8; - uint32_t fes_continuation_ratio_threshold : 5, - optimal_bw_retry_count : 4, - ndp_frame : 3, - rts_tx_over___reserved_g_0016 : 1, - gen_tqm_update_mpdu_count_tlv : 1, - sch_tx_burst_ongoing : 1, - coex_nack_count : 5, - use_static_bw : 1, - cbf_bw : 3, - cbf_bw_mask : 1, - cbf_sounding_token_mask : 1, - cbf_sounding_token : 6; - uint32_t transmit_cca_bitmap : 32; - uint32_t enable_hw_qos_null : 1, - retain_peer_blackout_details : 1, - last_command_in_burst : 1, - hip_edca_mini_contention_gap : 8, - hip_edca_prot_required : 1, - hip_edca_prot_enable : 1, - secure___reserved_g_0022_rsta : 1, - rtt_self_cal_enable : 1, - txrx_self_test_enable : 1, - wait_for_chksum_done : 1, - reserved_6a : 1, - wifi_radar_enable : 1, - max_cts2self_count : 4, - min_cts2self_count : 4, - __reserved_g_0022_trigger_subtype : 4, - tb___reserved_g_0022 : 1; - uint32_t monitor_override_sta_31_0 : 32; - uint32_t reserved_8a : 3, - npca_switching_cts2self_duration : 8, - cmf_uif_length : 4, - multiple_triggers_indication : 1, - dot11ax_trigger_frame_embedded : 1, - cfp_protected_fes : 1, - __reserved_g_0035_trigger_subtype : 4, - __reserved_g_0035_type : 2, - secure___reserved_g_0035_smr : 1, - __reserved_g_0035 : 1, - enable_qos_null_switch_for_eosp : 1, - monitor_override_sta_36_32 : 5; - uint32_t fw2sw_info : 32; -#endif -}; - -#define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SCHEDULE_ID_LSB 0 -#define TX_FES_SETUP_SCHEDULE_ID_MSB 31 -#define TX_FES_SETUP_SCHEDULE_ID_MASK 0x00000000ffffffff - -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 32 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 32 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x0000000100000000 - -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 33 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 36 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e00000000 - -#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 38 -#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 38 -#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x0000004000000000 - -#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 39 -#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 41 -#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x0000038000000000 - -#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 42 -#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 42 -#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x0000040000000000 - -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 43 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 43 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x0000080000000000 - -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 44 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 44 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000100000000000 - -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 45 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 45 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000200000000000 - -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 46 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 46 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000400000000000 - -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 47 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 47 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x0000800000000000 - -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 48 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 52 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 - -#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_FES_CONTROL_MODE_LSB 53 -#define TX_FES_SETUP_FES_CONTROL_MODE_MSB 54 -#define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x0060000000000000 - -#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_NUMBER_OF_USERS_LSB 55 -#define TX_FES_SETUP_NUMBER_OF_USERS_MSB 60 -#define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f80000000000000 - -#define TX_FES_SETUP_MU_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_MU_TYPE_LSB 61 -#define TX_FES_SETUP_MU_TYPE_MSB 61 -#define TX_FES_SETUP_MU_TYPE_MASK 0x2000000000000000 - -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 62 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 62 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x4000000000000000 - -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 63 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 63 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x8000000000000000 - -#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 -#define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 -#define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x000000000000000f - -#define TX_FES_SETUP_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RESERVED_2A_LSB 4 -#define TX_FES_SETUP_RESERVED_2A_MSB 4 -#define TX_FES_SETUP_RESERVED_2A_MASK 0x0000000000000010 - -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_LSB 5 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MSB 5 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MASK 0x0000000000000020 - -#define TX_FES_SETUP_TXBF_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TXBF_LSB 6 -#define TX_FES_SETUP_TXBF_MSB 6 -#define TX_FES_SETUP_TXBF_MASK 0x0000000000000040 - -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x0000000000000080 - -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x0000000000000100 - -#define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_IGNORE_TBTT_LSB 9 -#define TX_FES_SETUP_IGNORE_TBTT_MSB 9 -#define TX_FES_SETUP_IGNORE_TBTT_MASK 0x0000000000000200 - -#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 -#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 -#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x0000000000001c00 - -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x0000000000002000 - -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x0000000000004000 - -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x0000000000008000 - -#define TX_FES_SETUP_AST_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_AST_INDEX_LSB 16 -#define TX_FES_SETUP_AST_INDEX_MSB 31 -#define TX_FES_SETUP_AST_INDEX_MASK 0x00000000ffff0000 - -#define TX_FES_SETUP_CV_ID_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CV_ID_LSB 32 -#define TX_FES_SETUP_CV_ID_MSB 39 -#define TX_FES_SETUP_CV_ID_MASK 0x000000ff00000000 - -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 40 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 41 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x0000030000000000 - -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 42 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 42 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x0000040000000000 - -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 43 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 46 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x0000780000000000 - -#define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_MU_NDP_LSB 47 -#define TX_FES_SETUP_MU_NDP_MSB 47 -#define TX_FES_SETUP_MU_NDP_MASK 0x0000800000000000 - -#define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_BF_TYPE_LSB 48 -#define TX_FES_SETUP_BF_TYPE_MSB 49 -#define TX_FES_SETUP_BF_TYPE_MASK 0x0003000000000000 - -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 50 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 50 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x0004000000000000 - -#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NC_INDEX_LSB 51 -#define TX_FES_SETUP_CBF_NC_INDEX_MSB 53 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x0038000000000000 - -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 54 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 54 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x0040000000000000 - -#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NR_INDEX_LSB 55 -#define TX_FES_SETUP_CBF_NR_INDEX_MSB 57 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x0380000000000000 - -#define TX_FES_SETUP_NDPA_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_NDPA_LSB 59 -#define TX_FES_SETUP_NDPA_MSB 59 -#define TX_FES_SETUP_NDPA_MASK 0x0800000000000000 - -#define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_WAIT_SIFS_LSB 60 -#define TX_FES_SETUP_WAIT_SIFS_MSB 61 -#define TX_FES_SETUP_WAIT_SIFS_MASK 0x3000000000000000 - -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 62 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 62 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x4000000000000000 - -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 63 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 63 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x8000000000000000 - -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x000000000000003f - -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x0000000000000040 - -#define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_BW_MASK_LSB 7 -#define TX_FES_SETUP_CBF_BW_MASK_MSB 7 -#define TX_FES_SETUP_CBF_BW_MASK_MASK 0x0000000000000080 - -#define TX_FES_SETUP_CBF_BW_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_BW_LSB 8 -#define TX_FES_SETUP_CBF_BW_MSB 10 -#define TX_FES_SETUP_CBF_BW_MASK 0x0000000000000700 - -#define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_USE_STATIC_BW_LSB 11 -#define TX_FES_SETUP_USE_STATIC_BW_MSB 11 -#define TX_FES_SETUP_USE_STATIC_BW_MASK 0x0000000000000800 - -#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 -#define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 -#define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x000000000001f000 - -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x0000000000020000 - -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x0000000000040000 - -#define TX_FES_SETUP_NDP_FRAME_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_NDP_FRAME_LSB 20 -#define TX_FES_SETUP_NDP_FRAME_MSB 22 -#define TX_FES_SETUP_NDP_FRAME_MASK 0x0000000000700000 - -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x0000000007800000 - -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0x00000000f8000000 - -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 32 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 63 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff00000000 - -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x00000000000001e0 - -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x0000000000001e00 - -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x0000000000002000 - -#define TX_FES_SETUP_RESERVED_6A_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RESERVED_6A_LSB 14 -#define TX_FES_SETUP_RESERVED_6A_MSB 14 -#define TX_FES_SETUP_RESERVED_6A_MASK 0x0000000000004000 - -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_LSB 15 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MSB 15 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MASK 0x0000000000008000 - -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_LSB 16 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MSB 16 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MASK 0x0000000000010000 - -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_LSB 17 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MSB 17 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MASK 0x0000000000020000 - -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_LSB 19 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MSB 19 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MASK 0x0000000000080000 - -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_LSB 20 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MSB 20 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MASK 0x0000000000100000 - -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_LSB 21 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MSB 28 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MASK 0x000000001fe00000 - -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_LSB 29 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MSB 29 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MASK 0x0000000020000000 - -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_LSB 30 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MSB 30 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MASK 0x0000000040000000 - -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_LSB 31 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MSB 31 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MASK 0x0000000080000000 - -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 32 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 63 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff00000000 - -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x000000000000001f - -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_LSB 5 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MSB 5 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MASK 0x0000000000000020 - -#define TX_FES_SETUP_CFP_PROTECTED_FES_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_CFP_PROTECTED_FES_LSB 14 -#define TX_FES_SETUP_CFP_PROTECTED_FES_MSB 14 -#define TX_FES_SETUP_CFP_PROTECTED_FES_MASK 0x0000000000004000 - -#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 15 -#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 15 -#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000000000008000 - -#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_LSB 16 -#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_MSB 16 -#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_MASK 0x0000000000010000 - -#define TX_FES_SETUP_CMF_UIF_LENGTH_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_CMF_UIF_LENGTH_LSB 17 -#define TX_FES_SETUP_CMF_UIF_LENGTH_MSB 20 -#define TX_FES_SETUP_CMF_UIF_LENGTH_MASK 0x00000000001e0000 - -#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_LSB 21 -#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_MSB 28 -#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_MASK 0x000000001fe00000 - -#define TX_FES_SETUP_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_RESERVED_8A_LSB 29 -#define TX_FES_SETUP_RESERVED_8A_MSB 31 -#define TX_FES_SETUP_RESERVED_8A_MASK 0x00000000e0000000 - -#define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_FW2SW_INFO_LSB 32 -#define TX_FES_SETUP_FW2SW_INFO_MSB 63 -#define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_1k_ba.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_1k_ba.h deleted file mode 100644 index 4409dc03ac03..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_1k_ba.h +++ /dev/null @@ -1,313 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_1K_BA_H_ -#define _TX_FES_STATUS_1K_BA_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 - -#define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17 - -struct tx_fes_status_1k_ba { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ack_ba_status_type : 1, - ba_type : 1, - ba_tid : 4, - unexpected_ack_or_ba : 1, - response_timeout : 1, - ack_frame_rssi : 8, - ssn : 12, - reserved_0b : 4; - uint32_t sw_peer_id : 16, - reserved_1a : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; - uint32_t ba_bitmap_287_256 : 32; - uint32_t ba_bitmap_319_288 : 32; - uint32_t ba_bitmap_351_320 : 32; - uint32_t ba_bitmap_383_352 : 32; - uint32_t ba_bitmap_415_384 : 32; - uint32_t ba_bitmap_447_416 : 32; - uint32_t ba_bitmap_479_448 : 32; - uint32_t ba_bitmap_511_480 : 32; - uint32_t ba_bitmap_543_512 : 32; - uint32_t ba_bitmap_575_544 : 32; - uint32_t ba_bitmap_607_576 : 32; - uint32_t ba_bitmap_639_608 : 32; - uint32_t ba_bitmap_671_640 : 32; - uint32_t ba_bitmap_703_672 : 32; - uint32_t ba_bitmap_735_704 : 32; - uint32_t ba_bitmap_767_736 : 32; - uint32_t ba_bitmap_799_768 : 32; - uint32_t ba_bitmap_831_800 : 32; - uint32_t ba_bitmap_863_832 : 32; - uint32_t ba_bitmap_895_864 : 32; - uint32_t ba_bitmap_927_896 : 32; - uint32_t ba_bitmap_959_928 : 32; - uint32_t ba_bitmap_991_960 : 32; - uint32_t ba_bitmap_1023_992 : 32; -#else - uint32_t reserved_0b : 4, - ssn : 12, - ack_frame_rssi : 8, - response_timeout : 1, - unexpected_ack_or_ba : 1, - ba_tid : 4, - ba_type : 1, - ack_ba_status_type : 1; - uint32_t reserved_1a : 16, - sw_peer_id : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; - uint32_t ba_bitmap_287_256 : 32; - uint32_t ba_bitmap_319_288 : 32; - uint32_t ba_bitmap_351_320 : 32; - uint32_t ba_bitmap_383_352 : 32; - uint32_t ba_bitmap_415_384 : 32; - uint32_t ba_bitmap_447_416 : 32; - uint32_t ba_bitmap_479_448 : 32; - uint32_t ba_bitmap_511_480 : 32; - uint32_t ba_bitmap_543_512 : 32; - uint32_t ba_bitmap_575_544 : 32; - uint32_t ba_bitmap_607_576 : 32; - uint32_t ba_bitmap_639_608 : 32; - uint32_t ba_bitmap_671_640 : 32; - uint32_t ba_bitmap_703_672 : 32; - uint32_t ba_bitmap_735_704 : 32; - uint32_t ba_bitmap_767_736 : 32; - uint32_t ba_bitmap_799_768 : 32; - uint32_t ba_bitmap_831_800 : 32; - uint32_t ba_bitmap_863_832 : 32; - uint32_t ba_bitmap_895_864 : 32; - uint32_t ba_bitmap_927_896 : 32; - uint32_t ba_bitmap_959_928 : 32; - uint32_t ba_bitmap_991_960 : 32; - uint32_t ba_bitmap_1023_992 : 32; -#endif -}; - -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 - -#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 -#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 -#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002 - -#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 -#define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 -#define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c - -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 - -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 - -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_SSN_LSB 16 -#define TX_FES_STATUS_1K_BA_SSN_MSB 27 -#define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000 - -#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000 - -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_ack_or_ba.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_ack_or_ba.h deleted file mode 100644 index 678c639141ba..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_ack_or_ba.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_ACK_OR_BA_H_ -#define _TX_FES_STATUS_ACK_OR_BA_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10 - -#define NUM_OF_QWORDS_TX_FES_STATUS_ACK_OR_BA 5 - -struct tx_fes_status_ack_or_ba { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ack_ba_status_type : 1, - ba_type : 1, - ba_tid : 4, - unexpected_ack_or_ba : 1, - response_timeout : 1, - ack_frame_rssi : 8, - ssn : 12, - reserved_0b : 4; - uint32_t sw_peer_id : 16, - reserved_1a : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; -#else - uint32_t reserved_0b : 4, - ssn : 12, - ack_frame_rssi : 8, - response_timeout : 1, - unexpected_ack_or_ba : 1, - ba_tid : 4, - ba_type : 1, - ack_ba_status_type : 1; - uint32_t reserved_1a : 16, - sw_peer_id : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; -#endif -}; - -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB 0 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 - -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB 1 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB 1 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK 0x0000000000000002 - -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB 2 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB 5 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK 0x000000000000003c - -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB 6 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB 6 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 - -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB 7 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB 7 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 - -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB 8 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB 15 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB 16 -#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB 27 -#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK 0x000000000fff0000 - -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB 28 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK 0x00000000f0000000 - -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB 47 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB 48 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK 0xffff000000000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_end.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_end.h deleted file mode 100644 index 450b9227f8b2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_end.h +++ /dev/null @@ -1,602 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_END_H_ -#define _TX_FES_STATUS_END_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_END 12 - -#define NUM_OF_QWORDS_TX_FES_STATUS_END 6 - -struct tx_fes_status_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t __reserved_g_0052 : 1, - __reserved_g_0053 : 1, - __reserved_g_0035 : 1, - __reserved_g_0036 : 1, - __reserved_g_0032 : 1, - __reserved_g_0033 : 1, - __reserved_g_0072 : 1, - __reserved_g_0073 : 1, - __reserved_g_0065 : 1, - __reserved_g_0066 : 1, - __reserved_g_0062 : 1, - __reserved_g_0063 : 1, - global_data_underflow_warning : 1, - global_fes_transmit_result : 4, - cbf_bw_received_valid : 1, - cbf_bw_received : 3, - actual_received_ack_type : 4, - sta_response_count : 6, - more_data_received : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t reserved_after_struct16 : 4, - brp_info_valid : 1, - qos_null_switch_done_for_eosp : 1, - reserved_1a : 5, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - fes_in_11ax_trigger_response_config : 1, - null_delim_inserted_before_mpdus : 1, - only_null_delim_sent : 1; - uint32_t terminate___reserved_g_0022_sequence : 1, - unsolicited_erts_tx : 1, - ects_response_type : 2, - eba_response_type : 2, - response_type : 5, - r2r_end_status_to_follow : 1, - service_cbw : 3, - __reserved_g_0039 : 1, - __reserved_g_0040 : 1, - __reserved_g_0017 : 1, - __reserved_g_0018 : 1, - __reserved_g_0030 : 1, - __reserved_g_0031 : 1, - reserved_2c : 11; - uint32_t beamform_masked_user_bitmap_15_0 : 16, - beamform_masked_user_bitmap_31_16 : 16; - uint32_t cbf_segment_request_mask : 8, - cbf_segment_sent_mask : 8, - highest_achieved_data_null_ratio : 5, - use_alt_power_sr : 1, - static_2_pwr_mode_status : 1, - obss_srg_opport_transmit_status : 1, - srp_based_transmit_status : 1, - obss_pd_based_transmit_status : 1, - beamform_masked_user_bitmap_36_32 : 5, - pdg_mpdu_ready : 1; - uint32_t pdg_mpdu_count : 16, - pdg_est_mpdu_tx_count : 16; - uint32_t pdg_overview_length : 24, - txop_duration : 7, - pdg_dropped_mpdu_warning : 1; - uint32_t packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - packet_extension : 3, - fec_type : 1, - stbc : 1, - num_data_symbols : 16, - ru_size : 4, - reserved_17a : 4; - uint32_t num_ltf_symbols : 3, - ltf_size : 2, - cp_setting : 2, - reserved_18a : 5, - dcm : 1, - ldpc_extra_symbol : 1, - force_extra_symbol : 1, - reserved_18b : 1, - tx_pwr_shared : 8, - tx_pwr_unshared : 8; - uint32_t __reserved_g_0022_active_user_map : 16, - __reserved_g_0022_sent_dummy_tx : 1, - __reserved_g_0022_ftm_frame_sent : 1, - __reserved_g_0067 : 1, - __reserved_g_0068 : 1, - __reserved_g_0037 : 1, - __reserved_g_0038 : 1, - __reserved_g_0069 : 1, - __reserved_g_0070 : 1, - cv_corr_status : 8; - uint32_t current_tx_duration : 16, - reserved_21a : 4, - hw_qos_null_bitmap : 8, - hw_qos_null_setup_missing : 1, - interference : 1, - reserved_21b : 2; - uint32_t reserved_22b : 4, - __reserved_g_0027 : 1, - __reserved_g_0028 : 1, - __reserved_g_0049 : 1, - __reserved_g_0050 : 1, - __reserved_g_0025 : 1, - __reserved_g_0026 : 1, - __reserved_g_0047 : 1, - __reserved_g_0048 : 1, - __reserved_g_0023 : 1, - __reserved_g_0024 : 1, - __reserved_g_0045 : 1, - __reserved_g_0046 : 1, - __reserved_g_0021 : 1, - __reserved_g_0022 : 1, - __reserved_g_0043 : 1, - __reserved_g_0044 : 1, - __reserved_g_0019 : 1, - __reserved_g_0020 : 1, - __reserved_g_0041 : 1, - __reserved_g_0042 : 1, - coex_signaling_status : 8; -#else - uint32_t more_data_received : 1, - sta_response_count : 6, - actual_received_ack_type : 4, - cbf_bw_received : 3, - cbf_bw_received_valid : 1, - global_fes_transmit_result : 4, - global_data_underflow_warning : 1, - __reserved_g_0063 : 1, - __reserved_g_0062 : 1, - __reserved_g_0066 : 1, - __reserved_g_0065 : 1, - __reserved_g_0073 : 1, - __reserved_g_0072 : 1, - __reserved_g_0033 : 1, - __reserved_g_0032 : 1, - __reserved_g_0036 : 1, - __reserved_g_0035 : 1, - __reserved_g_0053 : 1, - __reserved_g_0052 : 1; - uint32_t only_null_delim_sent : 1, - null_delim_inserted_before_mpdus : 1, - fes_in_11ax_trigger_response_config : 1, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - reserved_1a : 5, - qos_null_switch_done_for_eosp : 1, - brp_info_valid : 1, - reserved_after_struct16 : 4; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t reserved_2c : 11, - __reserved_g_0031 : 1, - __reserved_g_0030 : 1, - __reserved_g_0018 : 1, - __reserved_g_0017 : 1, - __reserved_g_0040 : 1, - __reserved_g_0039 : 1, - service_cbw : 3, - r2r_end_status_to_follow : 1, - response_type : 5, - eba_response_type : 2, - ects_response_type : 2, - unsolicited_erts_tx : 1, - terminate___reserved_g_0022_sequence : 1; - uint32_t beamform_masked_user_bitmap_31_16 : 16, - beamform_masked_user_bitmap_15_0 : 16; - uint32_t pdg_mpdu_ready : 1, - beamform_masked_user_bitmap_36_32 : 5, - obss_pd_based_transmit_status : 1, - srp_based_transmit_status : 1, - obss_srg_opport_transmit_status : 1, - static_2_pwr_mode_status : 1, - use_alt_power_sr : 1, - highest_achieved_data_null_ratio : 5, - cbf_segment_sent_mask : 8, - cbf_segment_request_mask : 8; - uint32_t pdg_est_mpdu_tx_count : 16, - pdg_mpdu_count : 16; - uint32_t pdg_dropped_mpdu_warning : 1, - txop_duration : 7, - pdg_overview_length : 24; - uint32_t reserved_17a : 4, - ru_size : 4, - num_data_symbols : 16, - stbc : 1, - fec_type : 1, - packet_extension : 3, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2; - uint32_t tx_pwr_unshared : 8, - tx_pwr_shared : 8, - reserved_18b : 1, - force_extra_symbol : 1, - ldpc_extra_symbol : 1, - dcm : 1, - reserved_18a : 5, - cp_setting : 2, - ltf_size : 2, - num_ltf_symbols : 3; - uint32_t cv_corr_status : 8, - __reserved_g_0070 : 1, - __reserved_g_0069 : 1, - __reserved_g_0038 : 1, - __reserved_g_0037 : 1, - __reserved_g_0068 : 1, - __reserved_g_0067 : 1, - __reserved_g_0022_ftm_frame_sent : 1, - __reserved_g_0022_sent_dummy_tx : 1, - __reserved_g_0022_active_user_map : 16; - uint32_t reserved_21b : 2, - interference : 1, - hw_qos_null_setup_missing : 1, - hw_qos_null_bitmap : 8, - reserved_21a : 4, - current_tx_duration : 16; - uint32_t coex_signaling_status : 8, - __reserved_g_0042 : 1, - __reserved_g_0041 : 1, - __reserved_g_0020 : 1, - __reserved_g_0019 : 1, - __reserved_g_0044 : 1, - __reserved_g_0043 : 1, - __reserved_g_0022 : 1, - __reserved_g_0021 : 1, - __reserved_g_0046 : 1, - __reserved_g_0045 : 1, - __reserved_g_0024 : 1, - __reserved_g_0023 : 1, - __reserved_g_0048 : 1, - __reserved_g_0047 : 1, - __reserved_g_0026 : 1, - __reserved_g_0025 : 1, - __reserved_g_0050 : 1, - __reserved_g_0049 : 1, - __reserved_g_0028 : 1, - __reserved_g_0027 : 1, - reserved_22b : 4; -#endif -}; - -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000001000 - -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x000000000001e000 - -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x0000000000020000 - -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x00000000001c0000 - -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x0000000001e00000 - -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x000000007e000000 - -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_LSB 31 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MSB 31 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 48 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 51 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f000000000000 - -#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 52 -#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 52 -#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x0010000000000000 - -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_LSB 53 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MSB 53 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MASK 0x0020000000000000 - -#define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_RESERVED_1A_LSB 54 -#define TX_FES_STATUS_END_RESERVED_1A_MSB 58 -#define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07c0000000000000 - -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 59 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 59 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x0800000000000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 60 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 60 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x1000000000000000 - -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 61 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 61 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x2000000000000000 - -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 62 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 62 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x4000000000000000 - -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 63 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 63 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x8000000000000000 - -#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_LSB 1 -#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_MSB 1 -#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_MASK 0x0000000000000002 - -#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_LSB 2 -#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_MSB 3 -#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_MASK 0x000000000000000c - -#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_LSB 4 -#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_MSB 5 -#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_MASK 0x0000000000000030 - -#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 6 -#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 10 -#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x00000000000007c0 - -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 11 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 11 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000000000800 - -#define TX_FES_STATUS_END_SERVICE_CBW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_SERVICE_CBW_LSB 12 -#define TX_FES_STATUS_END_SERVICE_CBW_MSB 14 -#define TX_FES_STATUS_END_SERVICE_CBW_MASK 0x0000000000007000 - -#define TX_FES_STATUS_END_RESERVED_2C_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_RESERVED_2C_LSB 21 -#define TX_FES_STATUS_END_RESERVED_2C_MSB 31 -#define TX_FES_STATUS_END_RESERVED_2C_MASK 0x00000000ffe00000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 32 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 47 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 48 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 63 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0xffff000000000000 - -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 0 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 7 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x00000000000000ff - -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 8 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 15 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 16 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 20 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x00000000001f0000 - -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 21 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 21 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x0000000000200000 - -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 22 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 22 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x0000000000400000 - -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 23 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 23 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000000000800000 - -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 24 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 24 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000000001000000 - -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 25 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 25 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000000002000000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 26 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 30 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x000000007c000000 - -#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 31 -#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 31 -#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 32 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 47 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 48 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 63 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0xffff000000000000 - -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 0 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 23 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x0000000000ffffff - -#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_TXOP_DURATION_LSB 24 -#define TX_FES_STATUS_END_TXOP_DURATION_MSB 30 -#define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x000000007f000000 - -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 31 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 31 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 32 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 33 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000300000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 34 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 34 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000400000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 35 -#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 37 -#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x0000003800000000 - -#define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_FEC_TYPE_LSB 38 -#define TX_FES_STATUS_END_FEC_TYPE_MSB 38 -#define TX_FES_STATUS_END_FEC_TYPE_MASK 0x0000004000000000 - -#define TX_FES_STATUS_END_STBC_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_STBC_LSB 39 -#define TX_FES_STATUS_END_STBC_MSB 39 -#define TX_FES_STATUS_END_STBC_MASK 0x0000008000000000 - -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 40 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 55 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x00ffff0000000000 - -#define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_RU_SIZE_LSB 56 -#define TX_FES_STATUS_END_RU_SIZE_MSB 59 -#define TX_FES_STATUS_END_RU_SIZE_MASK 0x0f00000000000000 - -#define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_RESERVED_17A_LSB 60 -#define TX_FES_STATUS_END_RESERVED_17A_MSB 63 -#define TX_FES_STATUS_END_RESERVED_17A_MASK 0xf000000000000000 - -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 0 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 2 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x0000000000000007 - -#define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_LTF_SIZE_LSB 3 -#define TX_FES_STATUS_END_LTF_SIZE_MSB 4 -#define TX_FES_STATUS_END_LTF_SIZE_MASK 0x0000000000000018 - -#define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_CP_SETTING_LSB 5 -#define TX_FES_STATUS_END_CP_SETTING_MSB 6 -#define TX_FES_STATUS_END_CP_SETTING_MASK 0x0000000000000060 - -#define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_RESERVED_18A_LSB 7 -#define TX_FES_STATUS_END_RESERVED_18A_MSB 11 -#define TX_FES_STATUS_END_RESERVED_18A_MASK 0x0000000000000f80 - -#define TX_FES_STATUS_END_DCM_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_DCM_LSB 12 -#define TX_FES_STATUS_END_DCM_MSB 12 -#define TX_FES_STATUS_END_DCM_MASK 0x0000000000001000 - -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 13 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 13 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x0000000000002000 - -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 14 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 14 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x0000000000004000 - -#define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_RESERVED_18B_LSB 15 -#define TX_FES_STATUS_END_RESERVED_18B_MSB 15 -#define TX_FES_STATUS_END_RESERVED_18B_MASK 0x0000000000008000 - -#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 16 -#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 23 -#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x0000000000ff0000 - -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 24 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 31 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0x00000000ff000000 - -#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 56 -#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 63 -#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0xff00000000000000 - -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 0 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 15 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x000000000000ffff - -#define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_21A_LSB 16 -#define TX_FES_STATUS_END_RESERVED_21A_MSB 19 -#define TX_FES_STATUS_END_RESERVED_21A_MASK 0x00000000000f0000 - -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_LSB 20 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MSB 27 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MASK 0x000000000ff00000 - -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_LSB 28 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MSB 28 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MASK 0x0000000010000000 - -#define TX_FES_STATUS_END_INTERFERENCE_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_INTERFERENCE_LSB 29 -#define TX_FES_STATUS_END_INTERFERENCE_MSB 29 -#define TX_FES_STATUS_END_INTERFERENCE_MASK 0x0000000020000000 - -#define TX_FES_STATUS_END_RESERVED_21B_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_21B_LSB 30 -#define TX_FES_STATUS_END_RESERVED_21B_MSB 31 -#define TX_FES_STATUS_END_RESERVED_21B_MASK 0x00000000c0000000 - -#define TX_FES_STATUS_END_RESERVED_22B_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_22B_LSB 32 -#define TX_FES_STATUS_END_RESERVED_22B_MSB 35 -#define TX_FES_STATUS_END_RESERVED_22B_MASK 0x0000000f00000000 - -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_LSB 56 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MSB 63 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_prot.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_prot.h deleted file mode 100644 index 702cc1add940..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_prot.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_PROT_H_ -#define _TX_FES_STATUS_PROT_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 4 - -#define NUM_OF_QWORDS_TX_FES_STATUS_PROT 2 - -struct tx_fes_status_prot { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t success : 1, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - reserved_0 : 19, - pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5; - uint32_t frame_type : 2, - frame_subtype : 4, - rx_pwr_mgmt : 1, - status : 1, - duration_field : 16, - reserved_1a : 2, - agc_cbw : 3, - service_cbw : 3; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t reserved_2a : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4, - reserved_0 : 19, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - success : 1; - uint32_t service_cbw : 3, - agc_cbw : 3, - reserved_1a : 2, - duration_field : 16, - status : 1, - rx_pwr_mgmt : 1, - frame_subtype : 4, - frame_type : 2; - uint32_t reserved_2a : 16; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_SUCCESS_LSB 0 -#define TX_FES_STATUS_PROT_SUCCESS_MSB 0 -#define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001 - -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004 - -#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 -#define TX_FES_STATUS_PROT_RESERVED_0_MSB 21 -#define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000003ffff8 - -#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PKT_TYPE_LSB 22 -#define TX_FES_STATUS_PROT_PKT_TYPE_MSB 25 -#define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000003c00000 - -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 26 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 26 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000004000000 - -#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RATE_MCS_LSB 27 -#define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 -#define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f8000000 - -#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32 -#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33 -#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000 - -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000 - -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000 - -#define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_STATUS_LSB 39 -#define TX_FES_STATUS_PROT_STATUS_MSB 39 -#define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000 - -#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40 -#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55 -#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000 - -#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56 -#define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57 -#define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000 - -#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_AGC_CBW_LSB 58 -#define TX_FES_STATUS_PROT_AGC_CBW_MSB 60 -#define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000 - -#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61 -#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63 -#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00000000000000ff - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x0000000000003f00 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x000000000000c000 - -#define TX_FES_STATUS_PROT_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_RESERVED_2A_LSB 16 -#define TX_FES_STATUS_PROT_RESERVED_2A_MSB 31 -#define TX_FES_STATUS_PROT_RESERVED_2A_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_PROT_TLV64_PADDING_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_PROT_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_PROT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start.h deleted file mode 100644 index bc8e06ec59fb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_H_ -#define _TX_FES_STATUS_START_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START 4 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START 2 - -struct tx_fes_status_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t schedule_id : 32; - uint32_t reserved_1a : 8, - transmit_start_reason : 3, - disabled_user_bitmap_36_32 : 5, - schedule_cmd_ring_id : 5, - fes_control_mode : 2, - schedule_try : 4, - medium_prot_type : 3, - reserved_1b : 2; - uint32_t optimal_bw_try_count : 4, - number_of_users : 7, - coex_nack_count : 5, - cca_ed0 : 16; - uint32_t disabled_user_bitmap_31_0 : 32; -#else - uint32_t schedule_id : 32; - uint32_t reserved_1b : 2, - medium_prot_type : 3, - schedule_try : 4, - fes_control_mode : 2, - schedule_cmd_ring_id : 5, - disabled_user_bitmap_36_32 : 5, - transmit_start_reason : 3, - reserved_1a : 8; - uint32_t cca_ed0 : 16, - coex_nack_count : 5, - number_of_users : 7, - optimal_bw_try_count : 4; - uint32_t disabled_user_bitmap_31_0 : 32; -#endif -}; - -#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_ID_LSB 0 -#define TX_FES_STATUS_START_SCHEDULE_ID_MSB 31 -#define TX_FES_STATUS_START_SCHEDULE_ID_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_RESERVED_1A_LSB 32 -#define TX_FES_STATUS_START_RESERVED_1A_MSB 39 -#define TX_FES_STATUS_START_RESERVED_1A_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB 40 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB 42 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK 0x0000070000000000 - -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB 43 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB 47 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK 0x0000f80000000000 - -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB 48 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB 52 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 - -#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB 53 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB 54 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK 0x0060000000000000 - -#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB 55 -#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB 58 -#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK 0x0780000000000000 - -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB 59 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB 61 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK 0x3800000000000000 - -#define TX_FES_STATUS_START_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_RESERVED_1B_LSB 62 -#define TX_FES_STATUS_START_RESERVED_1B_MSB 63 -#define TX_FES_STATUS_START_RESERVED_1B_MASK 0xc000000000000000 - -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB 0 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB 3 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK 0x000000000000000f - -#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB 4 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB 10 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK 0x00000000000007f0 - -#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB 11 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB 15 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK 0x000000000000f800 - -#define TX_FES_STATUS_START_CCA_ED0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_CCA_ED0_LSB 16 -#define TX_FES_STATUS_START_CCA_ED0_MSB 31 -#define TX_FES_STATUS_START_CCA_ED0_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB 32 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB 63 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start_ppdu.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start_ppdu.h deleted file mode 100644 index a87b3b0a0ccc..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start_ppdu.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_PPDU_H_ -#define _TX_FES_STATUS_START_PPDU_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START_PPDU 3 - -struct tx_fes_status_start_ppdu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ppdu_timestamp_lower_32 : 32; - uint32_t ppdu_timestamp_upper_32 : 32; - uint32_t subband_mask : 16, - ndp_frame : 3, - reserved_2b : 1, - coex_based_tx_bw : 3, - coex_based_ant_mask : 8, - reserved_2c : 1; - uint32_t coex_based_tx_pwr_shared_ant : 8, - coex_based_tx_pwr_ant : 8, - concurrent_bt_tx : 1, - concurrent_wlan_tx : 1, - concurrent_wan_tx : 1, - concurrent_wan_rx : 1, - coex_pwr_reduction_bt : 1, - coex_pwr_reduction_wlan : 1, - coex_pwr_reduction_wan : 1, - coex_result_alt_based : 1, - request_packet_bw : 3, - response_type : 5; - uint32_t concurrent_rx_activity_tracker1 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - coex_pwr_reduction_wan_ratid1 : 1, - reserved_4a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t ppdu_timestamp_lower_32 : 32; - uint32_t ppdu_timestamp_upper_32 : 32; - uint32_t reserved_2c : 1, - coex_based_ant_mask : 8, - coex_based_tx_bw : 3, - reserved_2b : 1, - ndp_frame : 3, - subband_mask : 16; - uint32_t response_type : 5, - request_packet_bw : 3, - coex_result_alt_based : 1, - coex_pwr_reduction_wan : 1, - coex_pwr_reduction_wlan : 1, - coex_pwr_reduction_bt : 1, - concurrent_wan_rx : 1, - concurrent_wan_tx : 1, - concurrent_wlan_tx : 1, - concurrent_bt_tx : 1, - coex_based_tx_pwr_ant : 8, - coex_based_tx_pwr_shared_ant : 8; - uint32_t reserved_4a : 18, - coex_pwr_reduction_wan_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker1 : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB 0 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB 31 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB 32 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB 63 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB 0 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB 15 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK 0x000000000000ffff - -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB 16 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB 18 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK 0x0000000000070000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB 19 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB 19 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK 0x0000000000080000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB 20 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB 22 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK 0x0000000000700000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB 23 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB 30 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK 0x0000000080000000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB 32 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB 39 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB 40 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB 47 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK 0x0000ff0000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB 48 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB 48 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK 0x0001000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB 49 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB 49 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB 50 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB 50 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK 0x0004000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB 51 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB 51 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK 0x0008000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB 52 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB 52 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB 53 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB 53 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB 54 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB 54 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB 55 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB 55 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK 0x0080000000000000 - -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB 56 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB 58 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK 0x0700000000000000 - -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB 59 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB 63 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK 0xf800000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB 0 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB 0 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK 0x0000000000000001 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB 1 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB 1 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK 0x0000000000000002 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB 2 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB 2 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK 0x0000000000000004 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB 3 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB 3 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK 0x0000000000000008 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB 4 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB 4 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK 0x0000000000000010 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB 5 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB 5 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK 0x0000000000000020 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB 6 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB 6 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK 0x0000000000000040 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB 7 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB 7 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK 0x0000000000000080 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB 8 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB 8 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK 0x0000000000000100 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB 9 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB 9 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK 0x0000000000000200 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB 10 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB 10 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK 0x0000000000000400 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_LSB 11 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MSB 11 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MASK 0x0000000000000800 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_LSB 12 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MSB 12 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MASK 0x0000000000001000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_LSB 13 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MSB 13 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MASK 0x0000000000002000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_LSB 14 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MASK 0x00000000ffffc000 - -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start_prot.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start_prot.h deleted file mode 100644 index aca9ac5eb28b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_start_prot.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_PROT_H_ -#define _TX_FES_STATUS_START_PROT_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START_PROT 3 - -struct tx_fes_status_start_prot { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t prot_timestamp_lower_32 : 32; - uint32_t prot_timestamp_upper_32 : 32; - uint32_t subband_mask : 16, - reserved_2b : 4, - prot_coex_based_tx_bw : 3, - prot_coex_based_ant_mask : 8, - prot_coex_result_alt_based : 1; - uint32_t prot_coex_tx_pwr_shared_ant : 8, - prot_coex_tx_pwr_ant : 8, - prot_concurrent_bt_tx : 1, - prot_concurrent_wlan_tx : 1, - prot_concurrent_wan_tx : 1, - prot_concurrent_wan_rx : 1, - prot_coex_pwr_reduction_bt : 1, - prot_coex_pwr_reduction_wlan : 1, - prot_coex_pwr_reduction_wan : 1, - prot_request_packet_bw : 3, - response_type : 5, - reserved_3a : 1; - uint32_t concurrent_rx_activity_tracker1 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - coex_pwr_reduction_wan_ratid1 : 1, - reserved_4a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t prot_timestamp_lower_32 : 32; - uint32_t prot_timestamp_upper_32 : 32; - uint32_t prot_coex_result_alt_based : 1, - prot_coex_based_ant_mask : 8, - prot_coex_based_tx_bw : 3, - reserved_2b : 4, - subband_mask : 16; - uint32_t reserved_3a : 1, - response_type : 5, - prot_request_packet_bw : 3, - prot_coex_pwr_reduction_wan : 1, - prot_coex_pwr_reduction_wlan : 1, - prot_coex_pwr_reduction_bt : 1, - prot_concurrent_wan_rx : 1, - prot_concurrent_wan_tx : 1, - prot_concurrent_wlan_tx : 1, - prot_concurrent_bt_tx : 1, - prot_coex_tx_pwr_ant : 8, - prot_coex_tx_pwr_shared_ant : 8; - uint32_t reserved_4a : 18, - coex_pwr_reduction_wan_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker1 : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB 0 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB 31 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB 32 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB 63 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB 0 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB 15 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK 0x000000000000ffff - -#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB 16 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB 19 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK 0x00000000000f0000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB 20 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB 22 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK 0x0000000000700000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB 23 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB 30 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB 31 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB 31 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK 0x0000000080000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB 32 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB 39 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB 40 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB 47 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK 0x0000ff0000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB 48 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB 48 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK 0x0001000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB 49 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB 49 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB 50 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB 50 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK 0x0004000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB 51 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB 51 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK 0x0008000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB 52 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB 52 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB 53 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB 53 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB 54 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB 54 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB 55 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB 57 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK 0x0380000000000000 - -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB 58 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB 62 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK 0x7c00000000000000 - -#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB 63 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB 63 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK 0x8000000000000000 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB 0 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB 0 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK 0x0000000000000001 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB 1 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB 1 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK 0x0000000000000002 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB 2 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB 2 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK 0x0000000000000004 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB 3 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB 3 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK 0x0000000000000008 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB 4 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB 4 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK 0x0000000000000010 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB 5 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB 5 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK 0x0000000000000020 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB 6 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB 6 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK 0x0000000000000040 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB 7 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB 7 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK 0x0000000000000080 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB 8 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB 8 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK 0x0000000000000100 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB 9 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB 9 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK 0x0000000000000200 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB 10 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB 10 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK 0x0000000000000400 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_LSB 11 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MSB 11 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MASK 0x0000000000000800 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_LSB 12 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MSB 12 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MASK 0x0000000000001000 - -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_LSB 13 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MSB 13 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MASK 0x0000000000002000 - -#define TX_FES_STATUS_START_PROT_RESERVED_4A_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_LSB 14 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_MSB 31 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_MASK 0x00000000ffffc000 - -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_user_ppdu.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_user_ppdu.h deleted file mode 100644 index dad9a040ff46..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_user_ppdu.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_USER_PPDU_H_ -#define _TX_FES_STATUS_USER_PPDU_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3 - -struct tx_fes_status_user_ppdu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t underflow_mpdu_count : 9, - data_underflow_warning : 2, - bw_drop_underflow_warning : 1, - qc_eosp_setting : 1, - mpdu_tx_count : 11, - user_blocked : 1, - pre_trig_response_delim_count : 7; - uint32_t underflow_byte_count : 16, - coex_abort_mpdu_count_valid : 1, - coex_abort_mpdu_count : 9, - transmitted_tid : 4, - txdma_dropped_mpdu_warning : 1, - cv_corr_user_valid_in_phy : 1; - uint32_t duration : 16, - num_eof_delim_added : 16; - uint32_t psdu_octet : 24, - qos_buf_state : 8; - uint32_t num_null_delim_added : 22, - fc_more_data_setting : 1, - fc_pwr_mgt_setting : 1, - nss : 3, - mcs : 5; - uint32_t ht_control : 32; -#else - uint32_t pre_trig_response_delim_count : 7, - user_blocked : 1, - mpdu_tx_count : 11, - qc_eosp_setting : 1, - bw_drop_underflow_warning : 1, - data_underflow_warning : 2, - underflow_mpdu_count : 9; - uint32_t cv_corr_user_valid_in_phy : 1, - txdma_dropped_mpdu_warning : 1, - transmitted_tid : 4, - coex_abort_mpdu_count : 9, - coex_abort_mpdu_count_valid : 1, - underflow_byte_count : 16; - uint32_t num_eof_delim_added : 16, - duration : 16; - uint32_t qos_buf_state : 8, - psdu_octet : 24; - uint32_t mcs : 5, - nss : 3, - fc_pwr_mgt_setting : 1, - fc_more_data_setting : 1, - num_null_delim_added : 22; - uint32_t ht_control : 32; -#endif -}; - -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff - -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 - -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x0000000000000800 - -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x0000000000001000 - -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 13 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x0000000000ffe000 - -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x0000000001000000 - -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0x00000000fe000000 - -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 32 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 47 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 48 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 48 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x0001000000000000 - -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 49 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 57 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe000000000000 - -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 58 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 61 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c00000000000000 - -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 62 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 62 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x4000000000000000 - -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 63 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 63 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x8000000000000000 - -#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 -#define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 -#define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x000000000000ffff - -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 32 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 55 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff00000000 - -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 56 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 63 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff00000000000000 - -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x00000000003fffff - -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 22 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 22 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x0000000000400000 - -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 23 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 23 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x0000000000800000 - -#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_NSS_LSB 24 -#define TX_FES_STATUS_USER_PPDU_NSS_MSB 26 -#define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x0000000007000000 - -#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_MCS_LSB 27 -#define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 -#define TX_FES_STATUS_USER_PPDU_MCS_MASK 0x00000000f8000000 - -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 32 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 63 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_user_response.h b/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_user_response.h deleted file mode 100644 index dea7df35887f..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_fes_status_user_response.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_USER_RESPONSE_H_ -#define _TX_FES_STATUS_USER_RESPONSE_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2 - -#define NUM_OF_QWORDS_TX_FES_STATUS_USER_RESPONSE 1 - -struct tx_fes_status_user_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t fes_transmit_result : 4, - reserved_0 : 23, - overwritten_blackout_window_bitmap : 4, - mic_overwritten : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t pre_padding_fcs_overwritten : 1, - reserved_after_struct16 : 15; -#else - uint32_t mic_overwritten : 1, - overwritten_blackout_window_bitmap : 4, - reserved_0 : 23, - fes_transmit_result : 4; - uint32_t reserved_after_struct16 : 15, - pre_padding_fcs_overwritten : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; -#endif -}; - -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB 0 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB 3 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK 0x000000000000000f - -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB 4 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB 26 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK 0x0000000007fffff0 - -#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_LSB 27 -#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MSB 30 -#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MASK 0x0000000078000000 - -#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_LSB 31 -#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_MSB 31 -#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_MASK 0x0000000080000000 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_LSB 48 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MSB 48 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MASK 0x0001000000000000 - -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB 49 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB 63 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK 0xfffe000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_flush_req.h b/drivers/staging/fw-api/hw/fig/v2/tx_flush_req.h deleted file mode 100644 index af502ec619eb..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_flush_req.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FLUSH_REQ_H_ -#define _TX_FLUSH_REQ_H_ - -#define NUM_OF_DWORDS_TX_FLUSH_REQ 2 - -#define NUM_OF_QWORDS_TX_FLUSH_REQ 1 - -struct tx_flush_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t flush_req_reason : 8, - phytx_abort_reason : 8, - flush_req_user_number_or_link_id : 6, - mlo_abort_reason : 5, - reserved_0a : 5; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 5, - mlo_abort_reason : 5, - flush_req_user_number_or_link_id : 6, - phytx_abort_reason : 8, - flush_req_reason : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x00000000000000ff - -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x000000000000ff00 - -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x00000000003f0000 - -#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x0000000007c00000 - -#define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_RESERVED_0A_LSB 27 -#define TX_FLUSH_REQ_RESERVED_0A_MSB 31 -#define TX_FLUSH_REQ_RESERVED_0A_MASK 0x00000000f8000000 - -#define TX_FLUSH_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_TLV64_PADDING_LSB 32 -#define TX_FLUSH_REQ_TLV64_PADDING_MSB 63 -#define TX_FLUSH_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_mpdu_start.h b/drivers/staging/fw-api/hw/fig/v2/tx_mpdu_start.h deleted file mode 100644 index 1a0c370d2963..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_mpdu_start.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MPDU_START_H_ -#define _TX_MPDU_START_H_ - -#define NUM_OF_DWORDS_TX_MPDU_START 10 - -#define NUM_OF_QWORDS_TX_MPDU_START 5 - -struct tx_mpdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mpdu_length : 14, - frame_not_from_tqm : 1, - vht_control_present : 1, - mpdu_header_length : 8, - retry_count : 7, - wds : 1; - uint32_t pn_31_0 : 32; - uint32_t pn_47_32 : 16, - mpdu_sequence_number : 12, - raw_already_encrypted : 1, - frame_type : 2, - txdma_dropped_mpdu_warning : 1; - uint32_t iv_byte_0 : 8, - iv_byte_1 : 8, - iv_byte_2 : 8, - iv_byte_3 : 8; - uint32_t iv_byte_4 : 8, - iv_byte_5 : 8, - iv_byte_6 : 8, - iv_byte_7 : 8; - uint32_t iv_byte_8 : 8, - iv_byte_9 : 8, - iv_byte_10 : 8, - iv_byte_11 : 8; - uint32_t iv_byte_12 : 8, - iv_byte_13 : 8, - iv_byte_14 : 8, - iv_byte_15 : 8; - uint32_t iv_byte_16 : 8, - iv_byte_17 : 8, - iv_len : 5, - icv_len : 5, - vht_control_offset : 6; - uint32_t mpdu_type : 1, - transmit_bw_restriction : 1, - allowed_transmit_bw : 4, - tx_notify_frame : 3, - frame_subtype : 4, - reserved_8a : 19; - uint32_t tlv64_padding : 32; -#else - uint32_t wds : 1, - retry_count : 7, - mpdu_header_length : 8, - vht_control_present : 1, - frame_not_from_tqm : 1, - mpdu_length : 14; - uint32_t pn_31_0 : 32; - uint32_t txdma_dropped_mpdu_warning : 1, - frame_type : 2, - raw_already_encrypted : 1, - mpdu_sequence_number : 12, - pn_47_32 : 16; - uint32_t iv_byte_3 : 8, - iv_byte_2 : 8, - iv_byte_1 : 8, - iv_byte_0 : 8; - uint32_t iv_byte_7 : 8, - iv_byte_6 : 8, - iv_byte_5 : 8, - iv_byte_4 : 8; - uint32_t iv_byte_11 : 8, - iv_byte_10 : 8, - iv_byte_9 : 8, - iv_byte_8 : 8; - uint32_t iv_byte_15 : 8, - iv_byte_14 : 8, - iv_byte_13 : 8, - iv_byte_12 : 8; - uint32_t vht_control_offset : 6, - icv_len : 5, - iv_len : 5, - iv_byte_17 : 8, - iv_byte_16 : 8; - uint32_t reserved_8a : 19, - frame_subtype : 4, - tx_notify_frame : 3, - allowed_transmit_bw : 4, - transmit_bw_restriction : 1, - mpdu_type : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x0000000000000000 -#define TX_MPDU_START_MPDU_LENGTH_LSB 0 -#define TX_MPDU_START_MPDU_LENGTH_MSB 13 -#define TX_MPDU_START_MPDU_LENGTH_MASK 0x0000000000003fff - -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x0000000000000000 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x0000000000004000 - -#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x0000000000000000 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x0000000000008000 - -#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x0000000000000000 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_RETRY_COUNT_OFFSET 0x0000000000000000 -#define TX_MPDU_START_RETRY_COUNT_LSB 24 -#define TX_MPDU_START_RETRY_COUNT_MSB 30 -#define TX_MPDU_START_RETRY_COUNT_MASK 0x000000007f000000 - -#define TX_MPDU_START_WDS_OFFSET 0x0000000000000000 -#define TX_MPDU_START_WDS_LSB 31 -#define TX_MPDU_START_WDS_MSB 31 -#define TX_MPDU_START_WDS_MASK 0x0000000080000000 - -#define TX_MPDU_START_PN_31_0_OFFSET 0x0000000000000000 -#define TX_MPDU_START_PN_31_0_LSB 32 -#define TX_MPDU_START_PN_31_0_MSB 63 -#define TX_MPDU_START_PN_31_0_MASK 0xffffffff00000000 - -#define TX_MPDU_START_PN_47_32_OFFSET 0x0000000000000008 -#define TX_MPDU_START_PN_47_32_LSB 0 -#define TX_MPDU_START_PN_47_32_MSB 15 -#define TX_MPDU_START_PN_47_32_MASK 0x000000000000ffff - -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000008 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x000000000fff0000 - -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x0000000000000008 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x0000000010000000 - -#define TX_MPDU_START_FRAME_TYPE_OFFSET 0x0000000000000008 -#define TX_MPDU_START_FRAME_TYPE_LSB 29 -#define TX_MPDU_START_FRAME_TYPE_MSB 30 -#define TX_MPDU_START_FRAME_TYPE_MASK 0x0000000060000000 - -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000008 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 - -#define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_0_LSB 32 -#define TX_MPDU_START_IV_BYTE_0_MSB 39 -#define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_1_LSB 40 -#define TX_MPDU_START_IV_BYTE_1_MSB 47 -#define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_2_LSB 48 -#define TX_MPDU_START_IV_BYTE_2_MSB 55 -#define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff000000000000 - -#define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_3_LSB 56 -#define TX_MPDU_START_IV_BYTE_3_MSB 63 -#define TX_MPDU_START_IV_BYTE_3_MASK 0xff00000000000000 - -#define TX_MPDU_START_IV_BYTE_4_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_4_LSB 0 -#define TX_MPDU_START_IV_BYTE_4_MSB 7 -#define TX_MPDU_START_IV_BYTE_4_MASK 0x00000000000000ff - -#define TX_MPDU_START_IV_BYTE_5_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_5_LSB 8 -#define TX_MPDU_START_IV_BYTE_5_MSB 15 -#define TX_MPDU_START_IV_BYTE_5_MASK 0x000000000000ff00 - -#define TX_MPDU_START_IV_BYTE_6_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_6_LSB 16 -#define TX_MPDU_START_IV_BYTE_6_MSB 23 -#define TX_MPDU_START_IV_BYTE_6_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_IV_BYTE_7_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_7_LSB 24 -#define TX_MPDU_START_IV_BYTE_7_MSB 31 -#define TX_MPDU_START_IV_BYTE_7_MASK 0x00000000ff000000 - -#define TX_MPDU_START_IV_BYTE_8_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_8_LSB 32 -#define TX_MPDU_START_IV_BYTE_8_MSB 39 -#define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_9_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_9_LSB 40 -#define TX_MPDU_START_IV_BYTE_9_MSB 47 -#define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_BYTE_10_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_10_LSB 48 -#define TX_MPDU_START_IV_BYTE_10_MSB 55 -#define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff000000000000 - -#define TX_MPDU_START_IV_BYTE_11_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_11_LSB 56 -#define TX_MPDU_START_IV_BYTE_11_MSB 63 -#define TX_MPDU_START_IV_BYTE_11_MASK 0xff00000000000000 - -#define TX_MPDU_START_IV_BYTE_12_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_12_LSB 0 -#define TX_MPDU_START_IV_BYTE_12_MSB 7 -#define TX_MPDU_START_IV_BYTE_12_MASK 0x00000000000000ff - -#define TX_MPDU_START_IV_BYTE_13_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_13_LSB 8 -#define TX_MPDU_START_IV_BYTE_13_MSB 15 -#define TX_MPDU_START_IV_BYTE_13_MASK 0x000000000000ff00 - -#define TX_MPDU_START_IV_BYTE_14_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_14_LSB 16 -#define TX_MPDU_START_IV_BYTE_14_MSB 23 -#define TX_MPDU_START_IV_BYTE_14_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_IV_BYTE_15_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_15_LSB 24 -#define TX_MPDU_START_IV_BYTE_15_MSB 31 -#define TX_MPDU_START_IV_BYTE_15_MASK 0x00000000ff000000 - -#define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_16_LSB 32 -#define TX_MPDU_START_IV_BYTE_16_MSB 39 -#define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_17_LSB 40 -#define TX_MPDU_START_IV_BYTE_17_MSB 47 -#define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_LEN_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_LEN_LSB 48 -#define TX_MPDU_START_IV_LEN_MSB 52 -#define TX_MPDU_START_IV_LEN_MASK 0x001f000000000000 - -#define TX_MPDU_START_ICV_LEN_OFFSET 0x0000000000000018 -#define TX_MPDU_START_ICV_LEN_LSB 53 -#define TX_MPDU_START_ICV_LEN_MSB 57 -#define TX_MPDU_START_ICV_LEN_MASK 0x03e0000000000000 - -#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000000000000018 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 58 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 63 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc00000000000000 - -#define TX_MPDU_START_MPDU_TYPE_OFFSET 0x0000000000000020 -#define TX_MPDU_START_MPDU_TYPE_LSB 0 -#define TX_MPDU_START_MPDU_TYPE_MSB 0 -#define TX_MPDU_START_MPDU_TYPE_MASK 0x0000000000000001 - -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x0000000000000002 - -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x0000000000000020 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x000000000000003c - -#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 -#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 -#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x00000000000001c0 - -#define TX_MPDU_START_FRAME_SUBTYPE_OFFSET 0x0000000000000020 -#define TX_MPDU_START_FRAME_SUBTYPE_LSB 9 -#define TX_MPDU_START_FRAME_SUBTYPE_MSB 12 -#define TX_MPDU_START_FRAME_SUBTYPE_MASK 0x0000000000001e00 - -#define TX_MPDU_START_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_MPDU_START_RESERVED_8A_LSB 13 -#define TX_MPDU_START_RESERVED_8A_MSB 31 -#define TX_MPDU_START_RESERVED_8A_MASK 0x00000000ffffe000 - -#define TX_MPDU_START_TLV64_PADDING_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TLV64_PADDING_LSB 32 -#define TX_MPDU_START_TLV64_PADDING_MSB 63 -#define TX_MPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_msdu_extension.h b/drivers/staging/fw-api/hw/fig/v2/tx_msdu_extension.h deleted file mode 100644 index f8da5593497b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_msdu_extension.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MSDU_EXTENSION_H_ -#define _TX_MSDU_EXTENSION_H_ - -#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 - -struct tx_msdu_extension { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tso_enable : 1, - reserved_0a : 6, - tcp_flag : 9, - tcp_flag_mask : 9, - reserved_0b : 7; - uint32_t l2_length : 16, - ip_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t ip_identification : 16, - udp_length : 16; - uint32_t checksum_offset : 14, - partial_checksum_en : 1, - reserved_4a : 1, - payload_start_offset : 14, - reserved_4b : 2; - uint32_t payload_end_offset : 14, - reserved_5a : 2, - wds : 1, - reserved_5b : 15; - uint32_t buf0_ptr_31_0 : 32; - uint32_t buf0_ptr_39_32 : 8, - reserved_7a : 8, - buf0_len : 16; - uint32_t buf1_ptr_31_0 : 32; - uint32_t buf1_ptr_39_32 : 8, - reserved_9a : 8, - buf1_len : 16; - uint32_t buf2_ptr_31_0 : 32; - uint32_t buf2_ptr_39_32 : 8, - reserved_11a : 8, - buf2_len : 16; - uint32_t buf3_ptr_31_0 : 32; - uint32_t buf3_ptr_39_32 : 8, - reserved_13a : 8, - buf3_len : 16; - uint32_t buf4_ptr_31_0 : 32; - uint32_t buf4_ptr_39_32 : 8, - reserved_15a : 8, - buf4_len : 16; - uint32_t buf5_ptr_31_0 : 32; - uint32_t buf5_ptr_39_32 : 8, - reserved_17a : 8, - buf5_len : 16; -#else - uint32_t reserved_0b : 7, - tcp_flag_mask : 9, - tcp_flag : 9, - reserved_0a : 6, - tso_enable : 1; - uint32_t ip_length : 16, - l2_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t udp_length : 16, - ip_identification : 16; - uint32_t reserved_4b : 2, - payload_start_offset : 14, - reserved_4a : 1, - partial_checksum_en : 1, - checksum_offset : 14; - uint32_t reserved_5b : 15, - wds : 1, - reserved_5a : 2, - payload_end_offset : 14; - uint32_t buf0_ptr_31_0 : 32; - uint32_t buf0_len : 16, - reserved_7a : 8, - buf0_ptr_39_32 : 8; - uint32_t buf1_ptr_31_0 : 32; - uint32_t buf1_len : 16, - reserved_9a : 8, - buf1_ptr_39_32 : 8; - uint32_t buf2_ptr_31_0 : 32; - uint32_t buf2_len : 16, - reserved_11a : 8, - buf2_ptr_39_32 : 8; - uint32_t buf3_ptr_31_0 : 32; - uint32_t buf3_len : 16, - reserved_13a : 8, - buf3_ptr_39_32 : 8; - uint32_t buf4_ptr_31_0 : 32; - uint32_t buf4_len : 16, - reserved_15a : 8, - buf4_ptr_39_32 : 8; - uint32_t buf5_ptr_31_0 : 32; - uint32_t buf5_len : 16, - reserved_17a : 8, - buf5_ptr_39_32 : 8; -#endif -}; - -#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0 -#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB 0 -#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001 - -#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_RESERVED_0A_LSB 1 -#define TX_MSDU_EXTENSION_RESERVED_0A_MSB 6 -#define TX_MSDU_EXTENSION_RESERVED_0A_MASK 0x0000007e - -#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TCP_FLAG_LSB 7 -#define TX_MSDU_EXTENSION_TCP_FLAG_MSB 15 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80 - -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB 24 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000 - -#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_RESERVED_0B_LSB 25 -#define TX_MSDU_EXTENSION_RESERVED_0B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_0B_MASK 0xfe000000 - -#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004 -#define TX_MSDU_EXTENSION_L2_LENGTH_LSB 0 -#define TX_MSDU_EXTENSION_L2_LENGTH_MSB 15 -#define TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff - -#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004 -#define TX_MSDU_EXTENSION_IP_LENGTH_LSB 16 -#define TX_MSDU_EXTENSION_IP_LENGTH_MSB 31 -#define TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB 31 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0 -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB 15 -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff - -#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET 0x0000000c -#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB 16 -#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB 31 -#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB 0 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB 13 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK 0x00003fff - -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB 14 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB 14 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK 0x00004000 - -#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_RESERVED_4A_LSB 15 -#define TX_MSDU_EXTENSION_RESERVED_4A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_4A_MASK 0x00008000 - -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB 16 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB 29 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK 0x3fff0000 - -#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_RESERVED_4B_LSB 30 -#define TX_MSDU_EXTENSION_RESERVED_4B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_4B_MASK 0xc0000000 - -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB 0 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB 13 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK 0x00003fff - -#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_RESERVED_5A_LSB 14 -#define TX_MSDU_EXTENSION_RESERVED_5A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_5A_MASK 0x0000c000 - -#define TX_MSDU_EXTENSION_WDS_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_WDS_LSB 16 -#define TX_MSDU_EXTENSION_WDS_MSB 16 -#define TX_MSDU_EXTENSION_WDS_MASK 0x00010000 - -#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_RESERVED_5B_LSB 17 -#define TX_MSDU_EXTENSION_RESERVED_5B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_5B_MASK 0xfffe0000 - -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_7A_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_RESERVED_7A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_7A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_7A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_BUF0_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF0_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_RESERVED_9A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_9A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_9A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_BUF1_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF1_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_RESERVED_11A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_11A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_11A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_BUF2_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF2_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_RESERVED_13A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_13A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_13A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_BUF3_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF3_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_RESERVED_15A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_15A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_15A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_BUF4_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF4_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_RESERVED_17A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_17A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_17A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_BUF5_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF5_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_msdu_start.h b/drivers/staging/fw-api/hw/fig/v2/tx_msdu_start.h deleted file mode 100644 index e62a76009f3a..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_msdu_start.h +++ /dev/null @@ -1,250 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MSDU_START_H_ -#define _TX_MSDU_START_H_ - -#define NUM_OF_DWORDS_TX_MSDU_START 8 - -#define NUM_OF_QWORDS_TX_MSDU_START 4 - -struct tx_msdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t msdu_len : 14, - first_msdu : 1, - last_msdu : 1, - encap_type : 2, - epd_en : 1, - da_sa_present : 2, - ipv4_checksum_en : 1, - udp_over_ipv4_checksum_en : 1, - udp_over_ipv6_checksum_en : 1, - tcp_over_ipv4_checksum_en : 1, - tcp_over_ipv6_checksum_en : 1, - dummy_msdu_delimitation : 1, - reserved_0a : 5; - uint32_t tso_enable : 1, - reserved_1a : 6, - tcp_flag : 9, - tcp_flag_mask : 9, - mesh_enable : 1, - reserved_1b : 6; - uint32_t l2_length : 16, - ip_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t ip_identification : 16, - checksum_offset : 13, - partial_checksum_en : 1, - reserved_4 : 2; - uint32_t payload_start_offset : 14, - reserved_5a : 2, - payload_end_offset : 14, - reserved_5b : 2; - uint32_t udp_length : 16, - reserved_6 : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 5, - dummy_msdu_delimitation : 1, - tcp_over_ipv6_checksum_en : 1, - tcp_over_ipv4_checksum_en : 1, - udp_over_ipv6_checksum_en : 1, - udp_over_ipv4_checksum_en : 1, - ipv4_checksum_en : 1, - da_sa_present : 2, - epd_en : 1, - encap_type : 2, - last_msdu : 1, - first_msdu : 1, - msdu_len : 14; - uint32_t reserved_1b : 6, - mesh_enable : 1, - tcp_flag_mask : 9, - tcp_flag : 9, - reserved_1a : 6, - tso_enable : 1; - uint32_t ip_length : 16, - l2_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t reserved_4 : 2, - partial_checksum_en : 1, - checksum_offset : 13, - ip_identification : 16; - uint32_t reserved_5b : 2, - payload_end_offset : 14, - reserved_5a : 2, - payload_start_offset : 14; - uint32_t reserved_6 : 16, - udp_length : 16; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_MSDU_START_MSDU_LEN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_MSDU_LEN_LSB 0 -#define TX_MSDU_START_MSDU_LEN_MSB 13 -#define TX_MSDU_START_MSDU_LEN_MASK 0x0000000000003fff - -#define TX_MSDU_START_FIRST_MSDU_OFFSET 0x0000000000000000 -#define TX_MSDU_START_FIRST_MSDU_LSB 14 -#define TX_MSDU_START_FIRST_MSDU_MSB 14 -#define TX_MSDU_START_FIRST_MSDU_MASK 0x0000000000004000 - -#define TX_MSDU_START_LAST_MSDU_OFFSET 0x0000000000000000 -#define TX_MSDU_START_LAST_MSDU_LSB 15 -#define TX_MSDU_START_LAST_MSDU_MSB 15 -#define TX_MSDU_START_LAST_MSDU_MASK 0x0000000000008000 - -#define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_ENCAP_TYPE_LSB 16 -#define TX_MSDU_START_ENCAP_TYPE_MSB 17 -#define TX_MSDU_START_ENCAP_TYPE_MASK 0x0000000000030000 - -#define TX_MSDU_START_EPD_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_EPD_EN_LSB 18 -#define TX_MSDU_START_EPD_EN_MSB 18 -#define TX_MSDU_START_EPD_EN_MASK 0x0000000000040000 - -#define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x0000000000000000 -#define TX_MSDU_START_DA_SA_PRESENT_LSB 19 -#define TX_MSDU_START_DA_SA_PRESENT_MSB 20 -#define TX_MSDU_START_DA_SA_PRESENT_MASK 0x0000000000180000 - -#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x0000000000200000 - -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000000400000 - -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000000800000 - -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000001000000 - -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000002000000 - -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x0000000000000000 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x0000000004000000 - -#define TX_MSDU_START_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_0A_LSB 27 -#define TX_MSDU_START_RESERVED_0A_MSB 31 -#define TX_MSDU_START_RESERVED_0A_MASK 0x00000000f8000000 - -#define TX_MSDU_START_TSO_ENABLE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TSO_ENABLE_LSB 32 -#define TX_MSDU_START_TSO_ENABLE_MSB 32 -#define TX_MSDU_START_TSO_ENABLE_MASK 0x0000000100000000 - -#define TX_MSDU_START_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_1A_LSB 33 -#define TX_MSDU_START_RESERVED_1A_MSB 38 -#define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e00000000 - -#define TX_MSDU_START_TCP_FLAG_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_FLAG_LSB 39 -#define TX_MSDU_START_TCP_FLAG_MSB 47 -#define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff8000000000 - -#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_FLAG_MASK_LSB 48 -#define TX_MSDU_START_TCP_FLAG_MASK_MSB 56 -#define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff000000000000 - -#define TX_MSDU_START_MESH_ENABLE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_MESH_ENABLE_LSB 57 -#define TX_MSDU_START_MESH_ENABLE_MSB 57 -#define TX_MSDU_START_MESH_ENABLE_MASK 0x0200000000000000 - -#define TX_MSDU_START_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_1B_LSB 58 -#define TX_MSDU_START_RESERVED_1B_MSB 63 -#define TX_MSDU_START_RESERVED_1B_MASK 0xfc00000000000000 - -#define TX_MSDU_START_L2_LENGTH_OFFSET 0x0000000000000008 -#define TX_MSDU_START_L2_LENGTH_LSB 0 -#define TX_MSDU_START_L2_LENGTH_MSB 15 -#define TX_MSDU_START_L2_LENGTH_MASK 0x000000000000ffff - -#define TX_MSDU_START_IP_LENGTH_OFFSET 0x0000000000000008 -#define TX_MSDU_START_IP_LENGTH_LSB 16 -#define TX_MSDU_START_IP_LENGTH_MSB 31 -#define TX_MSDU_START_IP_LENGTH_MASK 0x00000000ffff0000 - -#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000000000008 -#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 32 -#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 63 -#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 - -#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x0000000000000010 -#define TX_MSDU_START_IP_IDENTIFICATION_LSB 0 -#define TX_MSDU_START_IP_IDENTIFICATION_MSB 15 -#define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x000000000000ffff - -#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16 -#define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28 -#define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x000000001fff0000 - -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x0000000020000000 - -#define TX_MSDU_START_RESERVED_4_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_4_LSB 30 -#define TX_MSDU_START_RESERVED_4_MSB 31 -#define TX_MSDU_START_RESERVED_4_MASK 0x00000000c0000000 - -#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 32 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 45 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff00000000 - -#define TX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_5A_LSB 46 -#define TX_MSDU_START_RESERVED_5A_MSB 47 -#define TX_MSDU_START_RESERVED_5A_MASK 0x0000c00000000000 - -#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 48 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 61 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff000000000000 - -#define TX_MSDU_START_RESERVED_5B_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_5B_LSB 62 -#define TX_MSDU_START_RESERVED_5B_MSB 63 -#define TX_MSDU_START_RESERVED_5B_MASK 0xc000000000000000 - -#define TX_MSDU_START_UDP_LENGTH_OFFSET 0x0000000000000018 -#define TX_MSDU_START_UDP_LENGTH_LSB 0 -#define TX_MSDU_START_UDP_LENGTH_MSB 15 -#define TX_MSDU_START_UDP_LENGTH_MASK 0x000000000000ffff - -#define TX_MSDU_START_RESERVED_6_OFFSET 0x0000000000000018 -#define TX_MSDU_START_RESERVED_6_LSB 16 -#define TX_MSDU_START_RESERVED_6_MSB 31 -#define TX_MSDU_START_RESERVED_6_MASK 0x00000000ffff0000 - -#define TX_MSDU_START_TLV64_PADDING_OFFSET 0x0000000000000018 -#define TX_MSDU_START_TLV64_PADDING_LSB 32 -#define TX_MSDU_START_TLV64_PADDING_MSB 63 -#define TX_MSDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_peer_entry.h b/drivers/staging/fw-api/hw/fig/v2/tx_peer_entry.h deleted file mode 100644 index c26c7f6a3e05..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_peer_entry.h +++ /dev/null @@ -1,391 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_PEER_ENTRY_H_ -#define _TX_PEER_ENTRY_H_ - -#define NUM_OF_DWORDS_TX_PEER_ENTRY 22 - -#define NUM_OF_QWORDS_TX_PEER_ENTRY 11 - -struct tx_peer_entry { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mac_addr_a_31_0 : 32; - uint32_t mac_addr_a_47_32 : 16, - mac_addr_b_15_0 : 16; - uint32_t mac_addr_b_47_16 : 32; - uint32_t use_ad_b : 1, - strip_insert_vlan_inner : 1, - strip_insert_vlan_outer : 1, - vlan_llc_mode : 1, - key_type : 4, - a_msdu_wds_ad3_ad4 : 3, - ignore_hard_filters : 1, - ignore_soft_filters : 1, - epd_output : 1, - wds : 1, - insert_or_strip : 1, - sw_filter_id : 16; - uint32_t temporal_key_31_0 : 32; - uint32_t temporal_key_63_32 : 32; - uint32_t temporal_key_95_64 : 32; - uint32_t temporal_key_127_96 : 32; - uint32_t temporal_key_159_128 : 32; - uint32_t temporal_key_191_160 : 32; - uint32_t temporal_key_223_192 : 32; - uint32_t temporal_key_255_224 : 32; - uint32_t sta_partial_aid : 11, - transmit_vif : 4, - block_this_user : 1, - mesh_amsdu_mode : 2, - use_qos_alt_mute_mask : 1, - dl_ul_direction : 1, - use_ad_c : 1, - a_msdu_11s_fromtods_10_ad3 : 2, - multi_link_addr_ad3_valid : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_ad1_trans_dis : 1, - data_fromtods_00_ad3 : 2, - mgmt_fromtods_00_ad3 : 2, - reserved_12 : 1; - uint32_t insert_vlan_outer_tci : 16, - insert_vlan_inner_tci : 16; - uint32_t __reserved_g_0007 : 32; - uint32_t __reserved_g_0008 : 16, - __reserved_g_0009 : 16; - uint32_t __reserved_g_0010 : 32; - uint32_t multi_link_addr_crypto_enable : 1, - a_msdu_fromtods_10_ad3 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_11_ad4 : 2, - reserved_17a : 9, - sw_peer_id : 16; - uint32_t mac_addr_c_31_0 : 32; - uint32_t mac_addr_c_47_32 : 16, - multi_link_addr_ad3_47_32 : 16; - uint32_t multi_link_addr_ad3_31_0 : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t mac_addr_a_31_0 : 32; - uint32_t mac_addr_b_15_0 : 16, - mac_addr_a_47_32 : 16; - uint32_t mac_addr_b_47_16 : 32; - uint32_t sw_filter_id : 16, - insert_or_strip : 1, - wds : 1, - epd_output : 1, - ignore_soft_filters : 1, - ignore_hard_filters : 1, - a_msdu_wds_ad3_ad4 : 3, - key_type : 4, - vlan_llc_mode : 1, - strip_insert_vlan_outer : 1, - strip_insert_vlan_inner : 1, - use_ad_b : 1; - uint32_t temporal_key_31_0 : 32; - uint32_t temporal_key_63_32 : 32; - uint32_t temporal_key_95_64 : 32; - uint32_t temporal_key_127_96 : 32; - uint32_t temporal_key_159_128 : 32; - uint32_t temporal_key_191_160 : 32; - uint32_t temporal_key_223_192 : 32; - uint32_t temporal_key_255_224 : 32; - uint32_t reserved_12 : 1, - mgmt_fromtods_00_ad3 : 2, - data_fromtods_00_ad3 : 2, - multi_link_addr_ad1_trans_dis : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_ad3_valid : 1, - a_msdu_11s_fromtods_10_ad3 : 2, - use_ad_c : 1, - dl_ul_direction : 1, - use_qos_alt_mute_mask : 1, - mesh_amsdu_mode : 2, - block_this_user : 1, - transmit_vif : 4, - sta_partial_aid : 11; - uint32_t insert_vlan_inner_tci : 16, - insert_vlan_outer_tci : 16; - uint32_t __reserved_g_0007 : 32; - uint32_t __reserved_g_0009 : 16, - __reserved_g_0008 : 16; - uint32_t __reserved_g_0010 : 32; - uint32_t sw_peer_id : 16, - reserved_17a : 9, - a_msdu_fromtods_11_ad4 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_10_ad3 : 2, - multi_link_addr_crypto_enable : 1; - uint32_t mac_addr_c_31_0 : 32; - uint32_t multi_link_addr_ad3_47_32 : 16, - mac_addr_c_47_32 : 16; - uint32_t multi_link_addr_ad3_31_0 : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 32 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 47 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 48 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 63 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_USE_AD_B_LSB 32 -#define TX_PEER_ENTRY_USE_AD_B_MSB 32 -#define TX_PEER_ENTRY_USE_AD_B_MASK 0x0000000100000000 - -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 33 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 33 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x0000000200000000 - -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 34 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 34 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x0000000400000000 - -#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 35 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 35 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x0000000800000000 - -#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_KEY_TYPE_LSB 36 -#define TX_PEER_ENTRY_KEY_TYPE_MSB 39 -#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f000000000 - -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 40 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 42 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x0000070000000000 - -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 43 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 43 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x0000080000000000 - -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 44 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 44 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x0000100000000000 - -#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 45 -#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 45 -#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x0000200000000000 - -#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_WDS_LSB 46 -#define TX_PEER_ENTRY_WDS_MSB 46 -#define TX_PEER_ENTRY_WDS_MASK 0x0000400000000000 - -#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 47 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 47 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x0000800000000000 - -#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 48 -#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 63 -#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x0000000000000010 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x0000000000000010 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x0000000000000018 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000000000000018 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x0000000000000020 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x0000000000000020 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x0000000000000028 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000000000000028 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x00000000000007ff - -#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 -#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 -#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x0000000000007800 - -#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x0000000000008000 - -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x0000000000030000 - -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x0000000000040000 - -#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x0000000000080000 - -#define TX_PEER_ENTRY_USE_AD_C_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_USE_AD_C_LSB 20 -#define TX_PEER_ENTRY_USE_AD_C_MSB 20 -#define TX_PEER_ENTRY_USE_AD_C_MASK 0x0000000000100000 - -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_LSB 21 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MSB 22 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MASK 0x0000000000600000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_LSB 23 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MSB 23 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MASK 0x0000000000800000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 24 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 24 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x0000000001000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 25 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 25 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x0000000002000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 26 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 26 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x0000000004000000 - -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_LSB 27 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MSB 28 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MASK 0x0000000018000000 - -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_LSB 29 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MSB 30 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MASK 0x0000000060000000 - -#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_RESERVED_12_LSB 31 -#define TX_PEER_ENTRY_RESERVED_12_MSB 31 -#define TX_PEER_ENTRY_RESERVED_12_MASK 0x0000000080000000 - -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 32 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 47 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 48 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 63 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 32 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 32 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x0000000100000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_LSB 33 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MSB 34 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MASK 0x0000000600000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_LSB 35 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MSB 36 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MASK 0x0000001800000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_LSB 37 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MSB 38 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MASK 0x0000006000000000 - -#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_RESERVED_17A_LSB 39 -#define TX_PEER_ENTRY_RESERVED_17A_MSB 47 -#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000ff8000000000 - -#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_SW_PEER_ID_LSB 48 -#define TX_PEER_ENTRY_SW_PEER_ID_MSB 63 -#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_LSB 32 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MSB 47 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_LSB 48 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MSB 63 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_OFFSET 0x0000000000000050 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_LSB 0 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MSB 31 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TLV64_PADDING_OFFSET 0x0000000000000050 -#define TX_PEER_ENTRY_TLV64_PADDING_LSB 32 -#define TX_PEER_ENTRY_TLV64_PADDING_MSB 63 -#define TX_PEER_ENTRY_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_queue_extension.h b/drivers/staging/fw-api/hw/fig/v2/tx_queue_extension.h deleted file mode 100644 index e46bae7cff4c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_queue_extension.h +++ /dev/null @@ -1,432 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_QUEUE_EXTENSION_H_ -#define _TX_QUEUE_EXTENSION_H_ - -#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 18 - -#define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 9 - -struct tx_queue_extension { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t frame_ctl : 16, - qos_ctl : 16; - uint32_t ampdu_flag : 1, - tx_notify_no_htc_override : 1, - reserved_1a : 7, - checksum_tso_disable_for_frag : 1, - key_id : 8, - qos_buf_state_overwrite : 1, - buf_state_sta_id : 1, - buf_state_source : 1, - ht_control_overwrite_enable : 1, - ht_control_overwrite_source : 4, - reserved_1b : 6; - uint32_t ul_headroom_insertion_enable : 1, - ul_headroom_offset : 5, - bqrp_insertion_enable : 1, - bqrp_offset : 5, - ul_headroom_rsvd_7_6 : 2, - bqr_rsvd_9_8 : 2, - base_pn_63_48 : 16; - uint32_t base_pn_95_64 : 32; - uint32_t base_pn_127_96 : 32; - uint32_t ht_control_default_tb_ppdu : 32; - uint32_t ht_control_default_non_tb_ppdu : 32; - uint32_t ht_control_overwrite_tb_ppdu_enable : 1, - ht_control_overwrite_non_tb_ppdu_enable : 1, - reserved_7a : 30; - uint32_t reserved_8a : 32; - uint32_t ht_control_overwrite_mask : 32; - uint32_t cas_control_info : 8, - cas_offset : 5, - cas_insertion_enable : 1, - reserved_10a : 2, - ht_control_overwrite_source_for_srp : 4, - ht_control_overwrite_source_for_bsrp : 4, - pre_padding_fcs_overwrite_enable : 1, - reserved_10b : 5, - mpdu_hdr_len_override_en : 1, - bar_ssn_overwrite_enable : 1; - uint32_t bar_ssn_offset : 12, - mpdu_hdr_len_override_val : 9, - reserved_11a : 11; - uint32_t fw2sw_info : 32; - uint32_t pre_padding_fcs_overwrite_offset : 16, - icf_blackout_info_offset : 16; - uint32_t trigger_common_info_length : 6, - cmf_overwrite_offset : 14, - reserved_15a : 12; - uint32_t hdr_ctrl_prot_key_id_byte_offset : 14, - hdr_ctrl_prot_key_id_bit_offset : 3, - ctrl_pkt_protect : 1, - mac_hdr_protect : 1, - hdr_ctrl_prot_tx_peer_idx : 11, - reserved_16a : 2; - uint32_t pad_byte_offset : 16, - pad_byte_offset_valid : 1, - txop_duration_overwrite_enable : 1, - txop_duration_offset : 14; - uint32_t tlv64_padding : 32; -#else - uint32_t qos_ctl : 16, - frame_ctl : 16; - uint32_t reserved_1b : 6, - ht_control_overwrite_source : 4, - ht_control_overwrite_enable : 1, - buf_state_source : 1, - buf_state_sta_id : 1, - qos_buf_state_overwrite : 1, - key_id : 8, - checksum_tso_disable_for_frag : 1, - reserved_1a : 7, - tx_notify_no_htc_override : 1, - ampdu_flag : 1; - uint32_t base_pn_63_48 : 16, - bqr_rsvd_9_8 : 2, - ul_headroom_rsvd_7_6 : 2, - bqrp_offset : 5, - bqrp_insertion_enable : 1, - ul_headroom_offset : 5, - ul_headroom_insertion_enable : 1; - uint32_t base_pn_95_64 : 32; - uint32_t base_pn_127_96 : 32; - uint32_t ht_control_default_tb_ppdu : 32; - uint32_t ht_control_default_non_tb_ppdu : 32; - uint32_t reserved_7a : 30, - ht_control_overwrite_non_tb_ppdu_enable : 1, - ht_control_overwrite_tb_ppdu_enable : 1; - uint32_t reserved_8a : 32; - uint32_t ht_control_overwrite_mask : 32; - uint32_t bar_ssn_overwrite_enable : 1, - mpdu_hdr_len_override_en : 1, - reserved_10b : 5, - pre_padding_fcs_overwrite_enable : 1, - ht_control_overwrite_source_for_bsrp : 4, - ht_control_overwrite_source_for_srp : 4, - reserved_10a : 2, - cas_insertion_enable : 1, - cas_offset : 5, - cas_control_info : 8; - uint32_t reserved_11a : 11, - mpdu_hdr_len_override_val : 9, - bar_ssn_offset : 12; - uint32_t fw2sw_info : 32; - uint32_t icf_blackout_info_offset : 16, - pre_padding_fcs_overwrite_offset : 16; - uint32_t reserved_15a : 12, - cmf_overwrite_offset : 14, - trigger_common_info_length : 6; - uint32_t reserved_16a : 2, - hdr_ctrl_prot_tx_peer_idx : 11, - mac_hdr_protect : 1, - ctrl_pkt_protect : 1, - hdr_ctrl_prot_key_id_bit_offset : 3, - hdr_ctrl_prot_key_id_byte_offset : 14; - uint32_t txop_duration_offset : 14, - txop_duration_overwrite_enable : 1, - pad_byte_offset_valid : 1, - pad_byte_offset : 16; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 -#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 -#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x000000000000ffff - -#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 -#define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 -#define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0x00000000ffff0000 - -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 32 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 32 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x0000000100000000 - -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 33 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 33 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x0000000200000000 - -#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 34 -#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 40 -#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc00000000 - -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 41 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 41 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x0000020000000000 - -#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_KEY_ID_LSB 42 -#define TX_QUEUE_EXTENSION_KEY_ID_MSB 49 -#define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc0000000000 - -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 50 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 50 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x0004000000000000 - -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 51 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 51 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x0008000000000000 - -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 52 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 52 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x0010000000000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 53 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 53 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x0020000000000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 54 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 57 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c0000000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 58 -#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc00000000000000 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x0000000000000001 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x000000000000003e - -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x0000000000000040 - -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x0000000000000f80 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x0000000000003000 - -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x000000000000c000 - -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0x00000000ffff0000 - -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 32 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 63 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x0000000000000010 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_OFFSET 0x0000000000000010 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_MSB 63 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_LSB 0 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_MSB 31 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_MSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_MASK 0x0000000100000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_LSB 33 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_MSB 33 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_MASK 0x0000000200000000 - -#define TX_QUEUE_EXTENSION_RESERVED_7A_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_RESERVED_7A_LSB 34 -#define TX_QUEUE_EXTENSION_RESERVED_7A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_7A_MASK 0xfffffffc00000000 - -#define TX_QUEUE_EXTENSION_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_QUEUE_EXTENSION_RESERVED_8A_LSB 0 -#define TX_QUEUE_EXTENSION_RESERVED_8A_MSB 31 -#define TX_QUEUE_EXTENSION_RESERVED_8A_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x0000000000000020 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 63 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x00000000000000ff - -#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x0000000000001f00 - -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x0000000000002000 - -#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 -#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 -#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x000000000000c000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x00000000000f0000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x0000000000f00000 - -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_LSB 24 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MSB 24 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MASK 0x0000000001000000 - -#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 25 -#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 -#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x000000003e000000 - -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x0000000040000000 - -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x0000000080000000 - -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 32 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 43 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff00000000 - -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 44 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 52 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff00000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 53 -#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe0000000000000 - -#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x0000000000000030 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 0 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 31 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_OFFSET 0x0000000000000030 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_LSB 32 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MSB 47 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MASK 0x0000ffff00000000 - -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_OFFSET 0x0000000000000030 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_LSB 48 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MSB 63 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MASK 0xffff000000000000 - -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_LSB 0 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MSB 5 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MASK 0x000000000000003f - -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_LSB 6 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MSB 19 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MASK 0x00000000000fffc0 - -#define TX_QUEUE_EXTENSION_RESERVED_15A_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_RESERVED_15A_LSB 20 -#define TX_QUEUE_EXTENSION_RESERVED_15A_MSB 31 -#define TX_QUEUE_EXTENSION_RESERVED_15A_MASK 0x00000000fff00000 - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_LSB 32 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MSB 45 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MASK 0x00003fff00000000 - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_LSB 46 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MSB 48 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MASK 0x0001c00000000000 - -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_LSB 49 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MSB 49 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MASK 0x0002000000000000 - -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_LSB 50 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MSB 50 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MASK 0x0004000000000000 - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_LSB 51 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MSB 61 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MASK 0x3ff8000000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_16A_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_RESERVED_16A_LSB 62 -#define TX_QUEUE_EXTENSION_RESERVED_16A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_16A_MASK 0xc000000000000000 - -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_LSB 0 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MSB 15 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MASK 0x000000000000ffff - -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_LSB 16 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MSB 16 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MASK 0x0000000000010000 - -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_LSB 17 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_MSB 17 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_MASK 0x0000000000020000 - -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_LSB 18 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_MSB 31 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_MASK 0x00000000fffc0000 - -#define TX_QUEUE_EXTENSION_TLV64_PADDING_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_TLV64_PADDING_LSB 32 -#define TX_QUEUE_EXTENSION_TLV64_PADDING_MSB 63 -#define TX_QUEUE_EXTENSION_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_rate_stats_info.h b/drivers/staging/fw-api/hw/fig/v2/tx_rate_stats_info.h deleted file mode 100644 index ce84032dd353..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_rate_stats_info.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_RATE_STATS_INFO_H_ -#define _TX_RATE_STATS_INFO_H_ - -#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 - -struct tx_rate_stats_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_rate_stats_info_valid : 1, - transmit_bw : 3, - transmit_pkt_type : 4, - transmit_stbc : 1, - transmit_ldpc : 1, - transmit_sgi : 2, - transmit_mcs : 5, - unequal_modulation_info : 3, - ofdma_transmission : 1, - reserved_0a : 4, - tones_in_ru : 4, - transmit_nss : 3; - uint32_t ppdu_transmission_tsf : 32; -#else - uint32_t transmit_nss : 3, - tones_in_ru : 4, - reserved_0a : 4, - ofdma_transmission : 1, - unequal_modulation_info : 3, - transmit_mcs : 5, - transmit_sgi : 2, - transmit_ldpc : 1, - transmit_stbc : 1, - transmit_pkt_type : 4, - transmit_bw : 3, - tx_rate_stats_info_valid : 1; - uint32_t ppdu_transmission_tsf : 32; -#endif -}; - -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB 0 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB 0 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 - -#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB 1 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB 3 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK 0x0000000e - -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB 4 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB 7 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK 0x000000f0 - -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB 8 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB 8 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK 0x00000100 - -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB 9 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB 9 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK 0x00000200 - -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB 10 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB 11 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK 0x00000c00 - -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB 12 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB 16 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK 0x0001f000 - -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_LSB 17 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MSB 19 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MASK 0x000e0000 - -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB 20 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB 20 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK 0x00100000 - -#define TX_RATE_STATS_INFO_RESERVED_0A_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_RESERVED_0A_LSB 21 -#define TX_RATE_STATS_INFO_RESERVED_0A_MSB 24 -#define TX_RATE_STATS_INFO_RESERVED_0A_MASK 0x01e00000 - -#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB 25 -#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB 28 -#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK 0x1e000000 - -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_LSB 29 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MSB 31 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MASK 0xe0000000 - -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB 0 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB 31 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/tx_raw_or_native_frame_setup.h b/drivers/staging/fw-api/hw/fig/v2/tx_raw_or_native_frame_setup.h deleted file mode 100644 index 220a82edf96d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/tx_raw_or_native_frame_setup.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ -#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ - -#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 4 - -#define NUM_OF_QWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2 - -struct tx_raw_or_native_frame_setup { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t fc_to_ds_mask : 1, - fc_from_ds_mask : 1, - fc_more_frag_mask : 1, - fc_retry_mask : 1, - fc_pwr_mgt_mask : 1, - fc_more_data_mask : 1, - fc_prot_frame_mask : 1, - fc_order_mask : 1, - duration_field_mask : 1, - sequence_control_mask : 1, - qc_tid_mask : 1, - qc_eosp_mask : 1, - qc_ack_policy_mask : 1, - qc_amsdu_mask : 1, - reserved_0a : 1, - qc_15to8_mask : 1, - iv_mask : 1, - fc_to_ds_setting : 1, - fc_from_ds_setting : 1, - fc_more_frag_setting : 1, - fc_retry_setting : 2, - fc_pwr_mgt_setting : 1, - fc_more_data_setting : 2, - fc_prot_frame_setting : 2, - fc_order_setting : 1, - qc_tid_setting : 4; - uint32_t qc_eosp_setting : 2, - qc_ack_policy_setting : 2, - qc_amsdu_setting : 1, - qc_15to8_setting : 8, - mlo_addr_override : 1, - mlo_ignore_addr3_override : 1, - sequence_control_source : 1, - fragment_number : 4, - sequence_number : 12; - uint32_t mlo_addr_override_for_ctrl : 1, - reserved_2a : 31; - uint32_t tlv64_padding : 32; -#else - uint32_t qc_tid_setting : 4, - fc_order_setting : 1, - fc_prot_frame_setting : 2, - fc_more_data_setting : 2, - fc_pwr_mgt_setting : 1, - fc_retry_setting : 2, - fc_more_frag_setting : 1, - fc_from_ds_setting : 1, - fc_to_ds_setting : 1, - iv_mask : 1, - qc_15to8_mask : 1, - reserved_0a : 1, - qc_amsdu_mask : 1, - qc_ack_policy_mask : 1, - qc_eosp_mask : 1, - qc_tid_mask : 1, - sequence_control_mask : 1, - duration_field_mask : 1, - fc_order_mask : 1, - fc_prot_frame_mask : 1, - fc_more_data_mask : 1, - fc_pwr_mgt_mask : 1, - fc_retry_mask : 1, - fc_more_frag_mask : 1, - fc_from_ds_mask : 1, - fc_to_ds_mask : 1; - uint32_t sequence_number : 12, - fragment_number : 4, - sequence_control_source : 1, - mlo_ignore_addr3_override : 1, - mlo_addr_override : 1, - qc_15to8_setting : 8, - qc_amsdu_setting : 1, - qc_ack_policy_setting : 2, - qc_eosp_setting : 2; - uint32_t reserved_2a : 31, - mlo_addr_override_for_ctrl : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK 0x0000000000000001 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK 0x0000000000000002 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB 2 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB 2 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK 0x0000000000000004 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB 3 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB 3 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK 0x0000000000000008 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB 4 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB 4 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK 0x0000000000000010 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB 5 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB 5 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK 0x0000000000000020 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB 6 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB 6 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK 0x0000000000000040 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB 7 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB 7 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK 0x0000000000000080 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB 8 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB 8 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK 0x0000000000000100 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB 9 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB 9 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK 0x0000000000000200 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB 10 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB 10 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK 0x0000000000000400 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB 11 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB 11 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK 0x0000000000000800 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB 12 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB 12 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK 0x0000000000001000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB 13 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB 13 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK 0x0000000000002000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB 14 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB 14 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK 0x0000000000004000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB 15 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB 15 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK 0x0000000000008000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB 16 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB 16 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK 0x0000000000010000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB 17 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB 17 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK 0x0000000000020000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB 18 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB 18 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK 0x0000000000040000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB 19 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB 19 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK 0x0000000000080000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB 20 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB 21 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK 0x0000000000300000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB 22 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB 22 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK 0x0000000000400000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB 23 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB 24 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK 0x0000000001800000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB 25 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB 26 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK 0x0000000006000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB 27 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB 27 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK 0x0000000008000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB 28 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB 31 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK 0x00000000f0000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB 32 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB 33 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK 0x0000000300000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB 34 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB 35 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK 0x0000000c00000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB 36 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB 36 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK 0x0000001000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB 37 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB 44 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK 0x00001fe000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB 45 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB 45 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK 0x0000200000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB 46 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB 46 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK 0x0000400000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB 47 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB 47 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK 0x0000800000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB 48 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB 51 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK 0x000f000000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB 52 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB 63 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK 0xfff0000000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_LSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MASK 0x0000000000000001 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_LSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MSB 31 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MASK 0x00000000fffffffe - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_LSB 32 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MSB 63 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/txpcu_buffer_basics.h b/drivers/staging/fw-api/hw/fig/v2/txpcu_buffer_basics.h deleted file mode 100644 index 4032a78ad617..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/txpcu_buffer_basics.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_BUFFER_BASICS_H_ -#define _TXPCU_BUFFER_BASICS_H_ - -#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1 - -struct txpcu_buffer_basics { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t available_memory : 8, - partial_tx_data_tlv_count : 8, - tx_data_tlv_count : 16; -#else - uint32_t tx_data_tlv_count : 16, - partial_tx_data_tlv_count : 8, - available_memory : 8; -#endif -}; - -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK 0x000000ff - -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 - -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/txpcu_buffer_status.h b/drivers/staging/fw-api/hw/fig/v2/txpcu_buffer_status.h deleted file mode 100644 index 847ca277267d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/txpcu_buffer_status.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_BUFFER_STATUS_H_ -#define _TXPCU_BUFFER_STATUS_H_ - -#include "txpcu_buffer_basics.h" -#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2 - -#define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1 - -struct txpcu_buffer_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct txpcu_buffer_basics txpcu_basix_buffer_info; - uint32_t reserved : 15, - msdu_end : 1, - tx_data_sync_value : 16; -#else - struct txpcu_buffer_basics txpcu_basix_buffer_info; - uint32_t tx_data_sync_value : 16, - msdu_end : 1, - reserved : 15; -#endif -}; - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 - -#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_RESERVED_LSB 32 -#define TXPCU_BUFFER_STATUS_RESERVED_MSB 46 -#define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff00000000 - -#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_MSDU_END_LSB 47 -#define TXPCU_BUFFER_STATUS_MSDU_END_MSB 47 -#define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 - -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/txpcu_user_buffer_status.h b/drivers/staging/fw-api/hw/fig/v2/txpcu_user_buffer_status.h deleted file mode 100644 index f6ad0fd73721..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/txpcu_user_buffer_status.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_USER_BUFFER_STATUS_H_ -#define _TXPCU_USER_BUFFER_STATUS_H_ - -#include "txpcu_buffer_basics.h" -#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2 - -#define NUM_OF_QWORDS_TXPCU_USER_BUFFER_STATUS 1 - -struct txpcu_user_buffer_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct txpcu_buffer_basics txpcu_basic_buffer_info; - uint32_t stored_word_count_user : 14, - reserved_1a : 1, - msdu_end : 1, - tx_data_sync_value : 16; -#else - struct txpcu_buffer_basics txpcu_basic_buffer_info; - uint32_t tx_data_sync_value : 16, - msdu_end : 1, - reserved_1a : 1, - stored_word_count_user : 14; -#endif -}; - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 - -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB 32 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB 45 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK 0x00003fff00000000 - -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB 46 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB 46 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK 0x0000400000000000 - -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB 47 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB 47 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 - -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/u_sig_eht_su_mu_info.h b/drivers/staging/fw-api/hw/fig/v2/u_sig_eht_su_mu_info.h deleted file mode 100644 index 1a08f3ab39b2..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/u_sig_eht_su_mu_info.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _U_SIG_EHT_SU_MU_INFO_H_ -#define _U_SIG_EHT_SU_MU_INFO_H_ - -#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 - -struct u_sig_eht_su_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_version : 3, - transmit_bw : 3, - dl_ul_flag : 1, - bss_color_id : 6, - txop_duration : 7, - disregard_0a : 5, - validate_0b : 1, - reserved_0c : 6; - uint32_t eht_ppdu_sig_cmn_type : 2, - validate_1a : 1, - punctured_channel_information : 5, - validate_1b : 1, - mcs_of_eht_sig : 2, - num_eht_sig_symbols : 5, - crc : 4, - tail : 6, - dot11ax_su_extended : 1, - reserved_1d : 3, - rx_ndp : 1, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0c : 6, - validate_0b : 1, - disregard_0a : 5, - txop_duration : 7, - bss_color_id : 6, - dl_ul_flag : 1, - transmit_bw : 3, - phy_version : 3; - uint32_t rx_integrity_check_passed : 1, - rx_ndp : 1, - reserved_1d : 3, - dot11ax_su_extended : 1, - tail : 6, - crc : 4, - num_eht_sig_symbols : 5, - mcs_of_eht_sig : 2, - validate_1b : 1, - punctured_channel_information : 5, - validate_1a : 1, - eht_ppdu_sig_cmn_type : 2; -#endif -}; - -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 - -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 - -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 - -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 - -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 - -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 - -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 - -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 - -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 - -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 - -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 - -#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 -#define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 -#define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 - -#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 -#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 -#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 - -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 - -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 - -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 - -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/u_sig_eht_tb_info.h b/drivers/staging/fw-api/hw/fig/v2/u_sig_eht_tb_info.h deleted file mode 100644 index 8e417b38d233..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/u_sig_eht_tb_info.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _U_SIG_EHT_TB_INFO_H_ -#define _U_SIG_EHT_TB_INFO_H_ - -#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2 - -struct u_sig_eht_tb_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_version : 3, - transmit_bw : 3, - dl_ul_flag : 1, - bss_color_id : 6, - txop_duration : 7, - disregard_0a : 6, - reserved_0c : 6; - uint32_t eht_ppdu_sig_cmn_type : 2, - validate_1a : 1, - spatial_reuse : 8, - disregard_1b : 5, - crc : 4, - tail : 6, - reserved_1c : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0c : 6, - disregard_0a : 6, - txop_duration : 7, - bss_color_id : 6, - dl_ul_flag : 1, - transmit_bw : 3, - phy_version : 3; - uint32_t rx_integrity_check_passed : 1, - reserved_1c : 5, - tail : 6, - crc : 4, - disregard_1b : 5, - spatial_reuse : 8, - validate_1a : 1, - eht_ppdu_sig_cmn_type : 2; -#endif -}; - -#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007 - -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038 - -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040 - -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80 - -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000 - -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000 - -#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000 - -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 - -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004 - -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8 - -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800 - -#define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_CRC_LSB 16 -#define U_SIG_EHT_TB_INFO_CRC_MSB 19 -#define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000 - -#define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_TAIL_LSB 20 -#define U_SIG_EHT_TB_INFO_TAIL_MSB 25 -#define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000 - -#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000 - -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/unallocated_ru_160_info.h b/drivers/staging/fw-api/hw/fig/v2/unallocated_ru_160_info.h deleted file mode 100644 index ccd4a7bab9ad..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/unallocated_ru_160_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _UNALLOCATED_RU_160_INFO_H_ -#define _UNALLOCATED_RU_160_INFO_H_ - -#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1 - -struct unallocated_ru_160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t subband80_0_cc0 : 8, - subband80_0_cc1 : 8, - subband80_1_cc0 : 8, - subband80_1_cc1 : 8; -#else - uint32_t subband80_1_cc1 : 8, - subband80_1_cc0 : 8, - subband80_0_cc1 : 8, - subband80_0_cc0 : 8; -#endif -}; - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB 0 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB 7 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK 0x000000ff - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB 8 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB 15 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK 0x0000ff00 - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB 16 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB 23 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK 0x00ff0000 - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB 24 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB 31 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/uniform_descriptor_header.h b/drivers/staging/fw-api/hw/fig/v2/uniform_descriptor_header.h deleted file mode 100644 index 7a2de6ccd8df..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/uniform_descriptor_header.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ -#define _UNIFORM_DESCRIPTOR_HEADER_H_ - -#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 - -struct uniform_descriptor_header { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t owner : 4, - buffer_type : 4, - tx_mpdu_queue_number : 20, - reserved_0a : 4; -#else - uint32_t reserved_0a : 4, - tx_mpdu_queue_number : 20, - buffer_type : 4, - owner : 4; -#endif -}; - -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f - -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 - -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 - -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_a_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_a_info.h deleted file mode 100644 index acd20f43949e..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_a_info.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_A_INFO_H_ -#define _VHT_SIG_A_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2 - -struct vht_sig_a_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t bandwidth : 2, - vhta_reserved_0 : 1, - stbc : 1, - group_id : 6, - n_sts : 12, - txop_ps_not_allowed : 1, - vhta_reserved_0b : 1, - reserved_0 : 8; - uint32_t gi_setting : 2, - su_mu_coding : 1, - ldpc_extra_symbol : 1, - mcs : 4, - beamformed : 1, - vhta_reserved_1 : 1, - crc : 8, - tail : 6, - reserved_1 : 7, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0 : 8, - vhta_reserved_0b : 1, - txop_ps_not_allowed : 1, - n_sts : 12, - group_id : 6, - stbc : 1, - vhta_reserved_0 : 1, - bandwidth : 2; - uint32_t rx_integrity_check_passed : 1, - reserved_1 : 7, - tail : 6, - crc : 8, - vhta_reserved_1 : 1, - beamformed : 1, - mcs : 4, - ldpc_extra_symbol : 1, - su_mu_coding : 1, - gi_setting : 2; -#endif -}; - -#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_BANDWIDTH_LSB 0 -#define VHT_SIG_A_INFO_BANDWIDTH_MSB 1 -#define VHT_SIG_A_INFO_BANDWIDTH_MASK 0x00000003 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB 2 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB 2 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK 0x00000004 - -#define VHT_SIG_A_INFO_STBC_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_STBC_LSB 3 -#define VHT_SIG_A_INFO_STBC_MSB 3 -#define VHT_SIG_A_INFO_STBC_MASK 0x00000008 - -#define VHT_SIG_A_INFO_GROUP_ID_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_GROUP_ID_LSB 4 -#define VHT_SIG_A_INFO_GROUP_ID_MSB 9 -#define VHT_SIG_A_INFO_GROUP_ID_MASK 0x000003f0 - -#define VHT_SIG_A_INFO_N_STS_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_N_STS_LSB 10 -#define VHT_SIG_A_INFO_N_STS_MSB 21 -#define VHT_SIG_A_INFO_N_STS_MASK 0x003ffc00 - -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB 22 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB 22 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB 23 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB 23 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK 0x00800000 - -#define VHT_SIG_A_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_RESERVED_0_LSB 24 -#define VHT_SIG_A_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_A_INFO_RESERVED_0_MASK 0xff000000 - -#define VHT_SIG_A_INFO_GI_SETTING_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_GI_SETTING_LSB 0 -#define VHT_SIG_A_INFO_GI_SETTING_MSB 1 -#define VHT_SIG_A_INFO_GI_SETTING_MASK 0x00000003 - -#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_SU_MU_CODING_LSB 2 -#define VHT_SIG_A_INFO_SU_MU_CODING_MSB 2 -#define VHT_SIG_A_INFO_SU_MU_CODING_MASK 0x00000004 - -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB 3 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB 3 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000008 - -#define VHT_SIG_A_INFO_MCS_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_MCS_LSB 4 -#define VHT_SIG_A_INFO_MCS_MSB 7 -#define VHT_SIG_A_INFO_MCS_MASK 0x000000f0 - -#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_BEAMFORMED_LSB 8 -#define VHT_SIG_A_INFO_BEAMFORMED_MSB 8 -#define VHT_SIG_A_INFO_BEAMFORMED_MASK 0x00000100 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB 9 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB 9 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK 0x00000200 - -#define VHT_SIG_A_INFO_CRC_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_CRC_LSB 10 -#define VHT_SIG_A_INFO_CRC_MSB 17 -#define VHT_SIG_A_INFO_CRC_MASK 0x0003fc00 - -#define VHT_SIG_A_INFO_TAIL_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_TAIL_LSB 18 -#define VHT_SIG_A_INFO_TAIL_MSB 23 -#define VHT_SIG_A_INFO_TAIL_MASK 0x00fc0000 - -#define VHT_SIG_A_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_RESERVED_1_LSB 24 -#define VHT_SIG_A_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_A_INFO_RESERVED_1_MASK 0x7f000000 - -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu160_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu160_info.h deleted file mode 100644 index 13931c5c3556..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu160_info.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU160_INFO_H_ -#define _VHT_SIG_B_MU160_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8 - -struct vht_sig_b_mu160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - mcs : 4, - tail : 6, - reserved_0 : 3; - uint32_t length_copy_a : 19, - mcs_copy_a : 4, - tail_copy_a : 6, - reserved_1 : 3; - uint32_t length_copy_b : 19, - mcs_copy_b : 4, - tail_copy_b : 6, - reserved_2 : 3; - uint32_t length_copy_c : 19, - mcs_copy_c : 4, - tail_copy_c : 6, - reserved_3 : 3; - uint32_t length_copy_d : 19, - mcs_copy_d : 4, - tail_copy_d : 6, - reserved_4 : 3; - uint32_t length_copy_e : 19, - mcs_copy_e : 4, - tail_copy_e : 6, - reserved_5 : 3; - uint32_t length_copy_f : 19, - mcs_copy_f : 4, - tail_copy_f : 6, - mu_user_number : 3; - uint32_t length_copy_g : 19, - mcs_copy_g : 4, - tail_copy_g : 6, - reserved_7 : 3; -#else - uint32_t reserved_0 : 3, - tail : 6, - mcs : 4, - length : 19; - uint32_t reserved_1 : 3, - tail_copy_a : 6, - mcs_copy_a : 4, - length_copy_a : 19; - uint32_t reserved_2 : 3, - tail_copy_b : 6, - mcs_copy_b : 4, - length_copy_b : 19; - uint32_t reserved_3 : 3, - tail_copy_c : 6, - mcs_copy_c : 4, - length_copy_c : 19; - uint32_t reserved_4 : 3, - tail_copy_d : 6, - mcs_copy_d : 4, - length_copy_d : 19; - uint32_t reserved_5 : 3, - tail_copy_e : 6, - mcs_copy_e : 4, - length_copy_e : 19; - uint32_t mu_user_number : 3, - tail_copy_f : 6, - mcs_copy_f : 4, - length_copy_f : 19; - uint32_t reserved_7 : 3, - tail_copy_g : 6, - mcs_copy_g : 4, - length_copy_g : 19; -#endif -}; - -#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_MCS_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_TAIL_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu20_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu20_info.h deleted file mode 100644 index c51ac839a757..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu20_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU20_INFO_H_ -#define _VHT_SIG_B_MU20_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1 - -struct vht_sig_b_mu20_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 16, - mcs : 4, - tail : 6, - mu_user_number : 3, - reserved_0 : 3; -#else - uint32_t reserved_0 : 3, - mu_user_number : 3, - tail : 6, - mcs : 4, - length : 16; -#endif -}; - -#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU20_INFO_LENGTH_MSB 15 -#define VHT_SIG_B_MU20_INFO_LENGTH_MASK 0x0000ffff - -#define VHT_SIG_B_MU20_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_MCS_LSB 16 -#define VHT_SIG_B_MU20_INFO_MCS_MSB 19 -#define VHT_SIG_B_MU20_INFO_MCS_MASK 0x000f0000 - -#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_TAIL_LSB 20 -#define VHT_SIG_B_MU20_INFO_TAIL_MSB 25 -#define VHT_SIG_B_MU20_INFO_TAIL_MASK 0x03f00000 - -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB 26 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB 28 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK 0x1c000000 - -#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu40_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu40_info.h deleted file mode 100644 index 0eb4c164cca1..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu40_info.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU40_INFO_H_ -#define _VHT_SIG_B_MU40_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2 - -struct vht_sig_b_mu40_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 17, - mcs : 4, - tail : 6, - reserved_0 : 2, - mu_user_number : 3; - uint32_t length_copy : 17, - mcs_copy : 4, - tail_copy : 6, - reserved_1 : 5; -#else - uint32_t mu_user_number : 3, - reserved_0 : 2, - tail : 6, - mcs : 4, - length : 17; - uint32_t reserved_1 : 5, - tail_copy : 6, - mcs_copy : 4, - length_copy : 17; -#endif -}; - -#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU40_INFO_LENGTH_MSB 16 -#define VHT_SIG_B_MU40_INFO_LENGTH_MASK 0x0001ffff - -#define VHT_SIG_B_MU40_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_MCS_LSB 17 -#define VHT_SIG_B_MU40_INFO_MCS_MSB 20 -#define VHT_SIG_B_MU40_INFO_MCS_MASK 0x001e0000 - -#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_TAIL_LSB 21 -#define VHT_SIG_B_MU40_INFO_TAIL_MSB 26 -#define VHT_SIG_B_MU40_INFO_TAIL_MASK 0x07e00000 - -#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB 27 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB 28 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK 0x18000000 - -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB 0 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB 16 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK 0x0001ffff - -#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB 17 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB 20 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK 0x001e0000 - -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB 21 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB 26 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK 0x07e00000 - -#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB 27 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK 0xf8000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu80_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu80_info.h deleted file mode 100644 index 33d0f1bc08fc..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_mu80_info.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU80_INFO_H_ -#define _VHT_SIG_B_MU80_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4 - -struct vht_sig_b_mu80_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - mcs : 4, - tail : 6, - reserved_0 : 3; - uint32_t length_copy_a : 19, - mcs_copy_a : 4, - tail_copy_a : 6, - reserved_1 : 3; - uint32_t length_copy_b : 19, - mcs_copy_b : 4, - tail_copy_b : 6, - mu_user_number : 3; - uint32_t length_copy_c : 19, - mcs_copy_c : 4, - tail_copy_c : 6, - reserved_3 : 3; -#else - uint32_t reserved_0 : 3, - tail : 6, - mcs : 4, - length : 19; - uint32_t reserved_1 : 3, - tail_copy_a : 6, - mcs_copy_a : 4, - length_copy_a : 19; - uint32_t mu_user_number : 3, - tail_copy_b : 6, - mcs_copy_b : 4, - length_copy_b : 19; - uint32_t reserved_3 : 3, - tail_copy_c : 6, - mcs_copy_c : 4, - length_copy_c : 19; -#endif -}; - -#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_MCS_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_TAIL_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su160_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su160_info.h deleted file mode 100644 index 7ba503724b56..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su160_info.h +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU160_INFO_H_ -#define _VHT_SIG_B_SU160_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8 - -struct vht_sig_b_su160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 21, - vhtb_reserved : 2, - tail : 6, - reserved_0 : 2, - rx_ndp : 1; - uint32_t length_copy_a : 21, - vhtb_reserved_copy_a : 2, - tail_copy_a : 6, - reserved_1 : 2, - rx_ndp_copy_a : 1; - uint32_t length_copy_b : 21, - vhtb_reserved_copy_b : 2, - tail_copy_b : 6, - reserved_2 : 2, - rx_ndp_copy_b : 1; - uint32_t length_copy_c : 21, - vhtb_reserved_copy_c : 2, - tail_copy_c : 6, - reserved_3 : 2, - rx_ndp_copy_c : 1; - uint32_t length_copy_d : 21, - vhtb_reserved_copy_d : 2, - tail_copy_d : 6, - reserved_4 : 2, - rx_ndp_copy_d : 1; - uint32_t length_copy_e : 21, - vhtb_reserved_copy_e : 2, - tail_copy_e : 6, - reserved_5 : 2, - rx_ndp_copy_e : 1; - uint32_t length_copy_f : 21, - vhtb_reserved_copy_f : 2, - tail_copy_f : 6, - reserved_6 : 2, - rx_ndp_copy_f : 1; - uint32_t length_copy_g : 21, - vhtb_reserved_copy_g : 2, - tail_copy_g : 6, - reserved_7 : 2, - rx_ndp_copy_g : 1; -#else - uint32_t rx_ndp : 1, - reserved_0 : 2, - tail : 6, - vhtb_reserved : 2, - length : 21; - uint32_t rx_ndp_copy_a : 1, - reserved_1 : 2, - tail_copy_a : 6, - vhtb_reserved_copy_a : 2, - length_copy_a : 21; - uint32_t rx_ndp_copy_b : 1, - reserved_2 : 2, - tail_copy_b : 6, - vhtb_reserved_copy_b : 2, - length_copy_b : 21; - uint32_t rx_ndp_copy_c : 1, - reserved_3 : 2, - tail_copy_c : 6, - vhtb_reserved_copy_c : 2, - length_copy_c : 21; - uint32_t rx_ndp_copy_d : 1, - reserved_4 : 2, - tail_copy_d : 6, - vhtb_reserved_copy_d : 2, - length_copy_d : 21; - uint32_t rx_ndp_copy_e : 1, - reserved_5 : 2, - tail_copy_e : 6, - vhtb_reserved_copy_e : 2, - length_copy_e : 21; - uint32_t rx_ndp_copy_f : 1, - reserved_6 : 2, - tail_copy_f : 6, - vhtb_reserved_copy_f : 2, - length_copy_f : 21; - uint32_t rx_ndp_copy_g : 1, - reserved_7 : 2, - tail_copy_g : 6, - vhtb_reserved_copy_g : 2, - length_copy_g : 21; -#endif -}; - -#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_TAIL_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su20_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su20_info.h deleted file mode 100644 index 2c7f11ba3c21..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su20_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU20_INFO_H_ -#define _VHT_SIG_B_SU20_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1 - -struct vht_sig_b_su20_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 17, - vhtb_reserved : 3, - tail : 6, - reserved : 5, - rx_ndp : 1; -#else - uint32_t rx_ndp : 1, - reserved : 5, - tail : 6, - vhtb_reserved : 3, - length : 17; -#endif -}; - -#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU20_INFO_LENGTH_MSB 16 -#define VHT_SIG_B_SU20_INFO_LENGTH_MASK 0x0001ffff - -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB 17 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB 19 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK 0x000e0000 - -#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_TAIL_LSB 20 -#define VHT_SIG_B_SU20_INFO_TAIL_MSB 25 -#define VHT_SIG_B_SU20_INFO_TAIL_MASK 0x03f00000 - -#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_RESERVED_LSB 26 -#define VHT_SIG_B_SU20_INFO_RESERVED_MSB 30 -#define VHT_SIG_B_SU20_INFO_RESERVED_MASK 0x7c000000 - -#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su40_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su40_info.h deleted file mode 100644 index 467259003e8d..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su40_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU40_INFO_H_ -#define _VHT_SIG_B_SU40_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2 - -struct vht_sig_b_su40_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - vhtb_reserved : 2, - tail : 6, - reserved : 4, - rx_ndp : 1; - uint32_t length_copy : 19, - vhtb_reserved_copy : 2, - tail_copy : 6, - reserved_copy : 4, - rx_ndp_copy : 1; -#else - uint32_t rx_ndp : 1, - reserved : 4, - tail : 6, - vhtb_reserved : 2, - length : 19; - uint32_t rx_ndp_copy : 1, - reserved_copy : 4, - tail_copy : 6, - vhtb_reserved_copy : 2, - length_copy : 19; -#endif -}; - -#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU40_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_SU40_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB 19 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB 20 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK 0x00180000 - -#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_TAIL_LSB 21 -#define VHT_SIG_B_SU40_INFO_TAIL_MSB 26 -#define VHT_SIG_B_SU40_INFO_TAIL_MASK 0x07e00000 - -#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_RESERVED_LSB 27 -#define VHT_SIG_B_SU40_INFO_RESERVED_MSB 30 -#define VHT_SIG_B_SU40_INFO_RESERVED_MASK 0x78000000 - -#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB 0 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB 18 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK 0x0007ffff - -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB 19 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB 20 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK 0x00180000 - -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB 21 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB 26 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK 0x07e00000 - -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB 27 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB 30 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK 0x78000000 - -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su80_info.h b/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su80_info.h deleted file mode 100644 index 92ceeab9b476..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/vht_sig_b_su80_info.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU80_INFO_H_ -#define _VHT_SIG_B_SU80_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4 - -struct vht_sig_b_su80_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 21, - vhtb_reserved : 2, - tail : 6, - reserved_0 : 2, - rx_ndp : 1; - uint32_t length_copy_a : 21, - vhtb_reserved_copy_a : 2, - tail_copy_a : 6, - reserved_1 : 2, - rx_ndp_copy_a : 1; - uint32_t length_copy_b : 21, - vhtb_reserved_copy_b : 2, - tail_copy_b : 6, - reserved_2 : 2, - rx_ndp_copy_b : 1; - uint32_t length_copy_c : 21, - vhtb_reserved_copy_c : 2, - tail_copy_c : 6, - reserved_3 : 2, - rx_ndp_copy_c : 1; -#else - uint32_t rx_ndp : 1, - reserved_0 : 2, - tail : 6, - vhtb_reserved : 2, - length : 21; - uint32_t rx_ndp_copy_a : 1, - reserved_1 : 2, - tail_copy_a : 6, - vhtb_reserved_copy_a : 2, - length_copy_a : 21; - uint32_t rx_ndp_copy_b : 1, - reserved_2 : 2, - tail_copy_b : 6, - vhtb_reserved_copy_b : 2, - length_copy_b : 21; - uint32_t rx_ndp_copy_c : 1, - reserved_3 : 2, - tail_copy_c : 6, - vhtb_reserved_copy_c : 2, - length_copy_c : 21; -#endif -}; - -#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_TAIL_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wbm2sw_completion_ring_rx.h b/drivers/staging/fw-api/hw/fig/v2/wbm2sw_completion_ring_rx.h deleted file mode 100644 index e40a7e796a87..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wbm2sw_completion_ring_rx.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM2SW_COMPLETION_RING_RX_H_ -#define _WBM2SW_COMPLETION_RING_RX_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_mpdu_desc_info.h" -#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 - -struct wbm2sw_completion_ring_rx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t release_source_module : 3, - bm_action : 3, - buffer_or_desc_type : 3, - return_buffer_manager : 4, - reserved_2a : 2, - cache_id : 1, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_push_reason : 2, - reo_error_code : 5, - wbm_internal_error : 1; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t buffer_phys_addr_31_0 : 32; - uint32_t buffer_phys_addr_39_32 : 8, - sw_buffer_cookie : 20, - looping_count : 4; -#else - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t wbm_internal_error : 1, - reo_error_code : 5, - reo_push_reason : 2, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - cache_id : 1, - reserved_2a : 2, - return_buffer_manager : 4, - buffer_or_desc_type : 3, - bm_action : 3, - release_source_module : 3; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t buffer_phys_addr_31_0 : 32; - uint32_t looping_count : 4, - sw_buffer_cookie : 20, - buffer_phys_addr_39_32 : 8; -#endif -}; - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 - -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 - -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 - -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 - -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 - -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 - -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 - -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 - -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff - -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 - -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wbm_buffer_ring.h b/drivers/staging/fw-api/hw/fig/v2/wbm_buffer_ring.h deleted file mode 100644 index b1532e15595b..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wbm_buffer_ring.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_BUFFER_RING_H_ -#define _WBM_BUFFER_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 - -struct wbm_buffer_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_addr_info; -#else - struct buffer_addr_info buf_addr_info; -#endif -}; - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wbm_link_descriptor_ring.h b/drivers/staging/fw-api/hw/fig/v2/wbm_link_descriptor_ring.h deleted file mode 100644 index 851807aa4c1c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wbm_link_descriptor_ring.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ -#define _WBM_LINK_DESCRIPTOR_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 - -struct wbm_link_descriptor_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info desc_addr_info; -#else - struct buffer_addr_info desc_addr_info; -#endif -}; - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring.h b/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring.h deleted file mode 100644 index e86d52753912..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_H_ -#define _WBM_RELEASE_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 - -struct wbm_release_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - reserved_2a : 3, - buffer_or_desc_type : 3, - reserved_2b : 22, - wbm_internal_error : 1; - uint32_t reserved_3a : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_5a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 28, - looping_count : 4; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t wbm_internal_error : 1, - reserved_2b : 22, - buffer_or_desc_type : 3, - reserved_2a : 3, - release_source_module : 3; - uint32_t reserved_3a : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_5a : 32; - uint32_t reserved_6a : 32; - uint32_t looping_count : 4, - reserved_7a : 28; -#endif -}; - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RESERVED_2A_LSB 3 -#define WBM_RELEASE_RING_RESERVED_2A_MSB 5 -#define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 - -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RESERVED_2B_LSB 9 -#define WBM_RELEASE_RING_RESERVED_2B_MSB 30 -#define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 - -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 - -#define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c -#define WBM_RELEASE_RING_RESERVED_3A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_3A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 -#define WBM_RELEASE_RING_RESERVED_4A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_4A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 -#define WBM_RELEASE_RING_RESERVED_5A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_5A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 -#define WBM_RELEASE_RING_RESERVED_6A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_6A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c -#define WBM_RELEASE_RING_RESERVED_7A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_7A_MSB 27 -#define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff - -#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 -#define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 -#define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring_rx.h b/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring_rx.h deleted file mode 100644 index a68bc8115a82..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring_rx.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_RX_H_ -#define _WBM_RELEASE_RING_RX_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 4 - -struct wbm_release_ring_rx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - buffer_or_desc_type : 3, - reserved_2a : 14, - mpdu_sequence_number : 12; - uint32_t reserved_3a : 32; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t mpdu_sequence_number : 12, - reserved_2a : 14, - buffer_or_desc_type : 3, - release_source_module : 3; - uint32_t reserved_3a : 32; -#endif -}; - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB 3 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB 5 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x00000038 - -#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB 6 -#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB 19 -#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK 0x000fffc0 - -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_LSB 20 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MSB 31 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 - -#define WBM_RELEASE_RING_RX_RESERVED_3A_OFFSET 0x0000000c -#define WBM_RELEASE_RING_RX_RESERVED_3A_LSB 0 -#define WBM_RELEASE_RING_RX_RESERVED_3A_MSB 31 -#define WBM_RELEASE_RING_RX_RESERVED_3A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring_tx.h b/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring_tx.h deleted file mode 100644 index d1412153c6ae..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wbm_release_ring_tx.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_TX_H_ -#define _WBM_RELEASE_RING_TX_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 4 - -struct wbm_release_ring_tx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - buffer_or_desc_type : 3, - reserved_2a : 26; - uint32_t tqm_status_number : 32; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t reserved_2a : 26, - buffer_or_desc_type : 3, - release_source_module : 3; - uint32_t tqm_status_number : 32; -#endif -}; - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 3 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 5 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x00000038 - -#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 6 -#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 31 -#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0xffffffc0 - -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0 -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 31 -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwiobase.h b/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwiobase.h deleted file mode 100644 index 4e455f399300..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwiobase.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef WCSS_SEQ_HWIOBASE_H -#define WCSS_SEQ_HWIOBASE_H - -#define UMAC_NOC_BASE 0x140000 -#define UMAC_NOC_BASE_SIZE 0x00004480 -#define UMAC_NOC_BASE_PHYS 0x00140000 - -#define PHYA0_BASE 0x300000 -#define PHYA0_BASE_SIZE 0x00300000 -#define PHYA0_BASE_PHYS 0x00300000 - -#define PHYA1_BASE 0x600000 -#define PHYA1_BASE_SIZE 0x00300000 -#define PHYA1_BASE_PHYS 0x00600000 - -#define DMAC_BASE 0x900000 -#define DMAC_BASE_SIZE 0x00080000 -#define DMAC_BASE_PHYS 0x00900000 - -#define UMAC_BASE 0xa00000 -#define UMAC_BASE_SIZE 0x0004d000 -#define UMAC_BASE_PHYS 0x00a00000 - -#define PMAC0_BASE 0xa80000 -#define PMAC0_BASE_SIZE 0x00040000 -#define PMAC0_BASE_PHYS 0x00a80000 - -#define PMAC1_BASE 0xac0000 -#define PMAC1_BASE_SIZE 0x00040000 -#define PMAC1_BASE_PHYS 0x00ac0000 - -#define WFSS_AMCSS_BASE 0xb00000 -#define WFSS_AMCSS_BASE_SIZE 0x00040000 -#define WFSS_AMCSS_BASE_PHYS 0x00b00000 - -#define CXC_BASE 0xb40000 -#define CXC_BASE_SIZE 0x00010000 -#define CXC_BASE_PHYS 0x00b40000 - -#define WFSS_PMM_BASE 0xb50000 -#define WFSS_PMM_BASE_SIZE 0x00002401 -#define WFSS_PMM_BASE_PHYS 0x00b50000 - -#define WFSS_CC_BASE 0xb60000 -#define WFSS_CC_BASE_SIZE 0x00008000 -#define WFSS_CC_BASE_PHYS 0x00b60000 - -#define WCMN_CORE_BASE 0xb68000 -#define WCMN_CORE_BASE_SIZE 0x000008a9 -#define WCMN_CORE_BASE_PHYS 0x00b68000 - -#define WIFI_CFGBUS_APB_TSLV_BASE 0xb6b000 -#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE 0x00001000 -#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS 0x00b6b000 - -#define WFSS_CFGBUS_BASE 0xb6c000 -#define WFSS_CFGBUS_BASE_SIZE 0x000000a0 -#define WFSS_CFGBUS_BASE_PHYS 0x00b6c000 - -#define WIFI_CFGBUS_AHB_TSLV_BASE 0xb6d000 -#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE 0x00001000 -#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS 0x00b6d000 - -#define UMAC_ACMT_BASE 0xb6e000 -#define UMAC_ACMT_BASE_SIZE 0x00001000 -#define UMAC_ACMT_BASE_PHYS 0x00b6e000 - -#define WCSS_CC_BASE 0xb80000 -#define WCSS_CC_BASE_SIZE 0x00010000 -#define WCSS_CC_BASE_PHYS 0x00b80000 - -#define PMM_TOP_BASE 0xb90000 -#define PMM_TOP_BASE_SIZE 0x00010000 -#define PMM_TOP_BASE_PHYS 0x00b90000 - -#define WCSS_TOP_CMN_BASE 0xba0000 -#define WCSS_TOP_CMN_BASE_SIZE 0x00004000 -#define WCSS_TOP_CMN_BASE_PHYS 0x00ba0000 - -#define WCSS_CFGBUS_BASE 0xba4000 -#define WCSS_CFGBUS_BASE_SIZE 0x00008000 -#define WCSS_CFGBUS_BASE_PHYS 0x00ba4000 - -#define MSIP_BASE 0xbb0000 -#define MSIP_BASE_SIZE 0x00010000 -#define MSIP_BASE_PHYS 0x00bb0000 - -#define RFA_BASE 0xbc0000 -#define RFA_BASE_SIZE 0x00040000 -#define RFA_BASE_PHYS 0x00bc0000 - -#define DBG_BASE 0x1000000 -#define DBG_BASE_SIZE 0x00100000 -#define DBG_BASE_PHYS 0x01000000 - -#define Q6SS_WLAN_BASE 0x1100000 -#define Q6SS_WLAN_BASE_SIZE 0x00100000 -#define Q6SS_WLAN_BASE_PHYS 0x01100000 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwioreg_umac.h b/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwioreg_umac.h deleted file mode 100644 index 2f111c881406..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwioreg_umac.h +++ /dev/null @@ -1,2481 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ -#ifndef WCSS_SEQ_HWIOREG_UMAC_H - -#include "seq_hwio.h" -#include "wcss_seq_hwiobase.h" -#ifdef SCALE_INCLUDES -#include "HALhwio.h" -#else -#include "msmhwio.h" -#endif - -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x) ((x) + 0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x) ((x) + 0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS (0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK 0xf8000007 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK 0x7 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x) ((x) + 0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x) ((x) + 0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS (0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK 0x1ffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR 0x00001ffe -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK 0x1ffe000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT 13 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK 0x1ffe -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT 1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK 0x1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT 0 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK 0x1000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT 12 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK 0x800 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT 11 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK 0x400 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT 10 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK 0x200 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT 9 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x) ((x) + 0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x) ((x) + 0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS (0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK 0xff000000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT 24 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK 0xff0000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT 16 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK 0xff00 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT 8 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK 0xff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n) ((base) + 0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_PHYS(base,n) ((base) + 0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_OFFS(n) (0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK 0xfff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_MAXn 31 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_BMSK 0xfff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_SHFT 0 - -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x) ((x) + 0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_PHYS(x) ((x) + 0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OFFS (0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_RMSK 0x3 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x)) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x)) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_BMSK 0x2 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_SHFT 1 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_BMSK 0x1 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_SHFT 0 - -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_OFFS(n) (0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_MAXn 63 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define WBM_REG_REG_BASE (UMAC_BASE + 0x00034000) - -#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) ((x) + 0x40) - -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) ((x) + 0x130) -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x7fc -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 2 -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x2 -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 1 - -#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) ((x) + 0x134) -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 16 -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0xffff -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) ((x) + 0x138) - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) ((x) + 0x13c) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) ((x) + 0x140) - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) ((x) + 0x144) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x1fff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) ((x) + 0x148) - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) ((x) + 0x14c) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x1fff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) ((x) + 0x150) - -#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x24c) - -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0x51c) - -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) ((x) + 0x52c) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_OFFS (0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_RMSK 0x3f -#define HWIO_WBM_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_WBM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_WBM_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_WBM_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_WBM_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_WBM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_WBM_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_BMSK 0x20 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_SHFT 5 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_BMSK 0x10 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_SHFT 4 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x) ((x) + 0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_PHYS(x) ((x) + 0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OFFS (0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RMSK 0xffffffff -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR 0x00000000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ATTR 0x3 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x) \ - in_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x)) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x), m) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUT(x, v) \ - out_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),v) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x)) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_BMSK 0xffe00000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_SHFT 21 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_BMSK 0x1f0000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_SHFT 16 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_BMSK 0xf800 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_SHFT 11 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_BMSK 0x7c0 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_SHFT 6 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_BMSK 0x3e -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_SHFT 1 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_BMSK 0x1 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_SHFT 0 - -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x3ff -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000020 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_BMSK 0x200 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_SHFT 9 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_BMSK 0x100 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_SHFT 8 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_MAXn 255 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3010) - -#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) ((x) + 0x3040) - -#define REO_REG_REG_BASE (UMAC_BASE + 0x00038000) - -#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) ((x) + 0x0) - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x) ((x) + 0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_PHYS(x) ((x) + 0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OFFS (0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR 0x76043210 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x) ((x) + 0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x) ((x) + 0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS (0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR 0x6666ba98 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x) ((x) + 0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_PHYS(x) ((x) + 0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OFFS (0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR 0x66666666 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x) ((x) + 0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_PHYS(x) ((x) + 0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OFFS (0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR 0x66666666 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) ((x) + 0x38) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) ((x) + 0x3c) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x) ((x) + 0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_PHYS(x) ((x) + 0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OFFS (0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR 0x00000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ATTR 0x3 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x), m) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),v) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x) ((x) + 0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_PHYS(x) ((x) + 0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OFFS (0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR 0x00000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ATTR 0x3 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x), m) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),v) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_SHFT 0 - -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x) ((x) + 0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_PHYS(x) ((x) + 0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OFFS (0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_RMSK 0x1ffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR 0x00000000 -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ATTR 0x3 -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x) \ - in_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x)) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x), m) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUT(x, v) \ - out_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),v) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),m,v,HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x)) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_BMSK 0x1ffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_SHFT 0 - -#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x6c) - -#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x70) -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK 0x100000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT 20 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK 0x80000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT 19 -#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 -#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff -#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 - -#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) ((x) + 0x344) - -#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) ((x) + 0x7d0) - -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) ((x) + 0x7d4) -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) ((x) + 0x7d8) - -#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) ((x) + 0x7dc) -#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x7e0) -#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x7e4) - -#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x7e8) - -#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7f4) - -#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x818) - -#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x81c) - -#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x820) - -#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x824) - -#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x828) - -#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x82c) - -#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x830) - -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x844) -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x848) - -#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0xc08) - -#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT 8 - -#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_REO_R0_MISC_CFG_ADDR(x) ((x) + 0x1458) -#define HWIO_REO_R0_MISC_CFG_PHYS(x) ((x) + 0x1458) -#define HWIO_REO_R0_MISC_CFG_OFFS (0x1458) -#define HWIO_REO_R0_MISC_CFG_RMSK 0x1 -#define HWIO_REO_R0_MISC_CFG_POR 0x00000000 -#define HWIO_REO_R0_MISC_CFG_POR_RMSK 0xffffffff -#define HWIO_REO_R0_MISC_CFG_ATTR 0x3 -#define HWIO_REO_R0_MISC_CFG_IN(x) \ - in_dword(HWIO_REO_R0_MISC_CFG_ADDR(x)) -#define HWIO_REO_R0_MISC_CFG_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_MISC_CFG_ADDR(x), m) -#define HWIO_REO_R0_MISC_CFG_OUT(x, v) \ - out_dword(HWIO_REO_R0_MISC_CFG_ADDR(x),v) -#define HWIO_REO_R0_MISC_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_MISC_CFG_ADDR(x),m,v,HWIO_REO_R0_MISC_CFG_IN(x)) -#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_BMSK 0x1 -#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_SHFT 0 - -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x) ((x) + 0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_PHYS(x) ((x) + 0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OFFS (0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_RMSK 0x7ff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR 0x000003ff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR_RMSK 0xffffffff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ATTR 0x3 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x) \ - in_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x)) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x), m) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUT(x, v) \ - out_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),v) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),m,v,HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x)) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_BMSK 0x400 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_SHFT 10 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_BMSK 0x200 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_SHFT 9 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_BMSK 0x100 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_SHFT 8 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_BMSK 0x80 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_SHFT 7 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_BMSK 0x40 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_SHFT 6 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_BMSK 0x20 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_SHFT 5 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_BMSK 0x10 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_SHFT 4 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_BMSK 0x8 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_SHFT 3 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_BMSK 0x4 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_SHFT 2 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_BMSK 0x2 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_SHFT 1 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_BMSK 0x1 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_SHFT 0 - -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x) ((x) + 0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_PHYS(x) ((x) + 0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OFFS (0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_RMSK 0x1ff -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR 0x0000002d -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR_RMSK 0xffffffff -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ATTR 0x3 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x) \ - in_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x)) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x), m) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUT(x, v) \ - out_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),v) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),m,v,HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x)) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_BMSK 0x1fe -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_SHFT 1 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_BMSK 0x1 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_SHFT 0 - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) ((x) + 0x1468) - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) ((x) + 0x146c) - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) ((x) + 0x1470) - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) ((x) + 0x1474) - -#define HWIO_REO_R0_MISC_CTL_ADDR(x) ((x) + 0x14dc) -#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK 0x1e00000 -#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT 21 -#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x1e0000 -#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 17 - -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_REO_R0_CREDIT_ADDR(x) ((x) + 0x16d0) -#define HWIO_REO_R0_CREDIT_PHYS(x) ((x) + 0x16d0) -#define HWIO_REO_R0_CREDIT_OFFS (0x16d0) -#define HWIO_REO_R0_CREDIT_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_POR 0x00000000 -#define HWIO_REO_R0_CREDIT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_ATTR 0x3 -#define HWIO_REO_R0_CREDIT_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_ADDR(x)) -#define HWIO_REO_R0_CREDIT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_OUT(x, v) \ - out_dword(HWIO_REO_R0_CREDIT_ADDR(x),v) -#define HWIO_REO_R0_CREDIT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_CREDIT_ADDR(x),m,v,HWIO_REO_R0_CREDIT_IN(x)) -#define HWIO_REO_R0_CREDIT_VAL_BMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_VAL_SHFT 0 - -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x) ((x) + 0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_PHYS(x) ((x) + 0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OFFS (0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_RMSK 0x7 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR 0x00000002 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ATTR 0x3 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x)) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUT(x, v) \ - out_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),v) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),m,v,HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x)) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_BMSK 0x7 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_SHFT 0 - -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x) ((x) + 0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_PHYS(x) ((x) + 0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_OFFS (0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR 0x00000000 -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ATTR 0x1 -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x)) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_BMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_SHFT 0 - -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_BMSK 0x2000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_SHFT 13 - -#define HWIO_REO_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_OFFS (0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_RMSK 0x7 -#define HWIO_REO_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_REO_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_REO_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_REO_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_REO_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_REO_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_REO_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_REO_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x) ((x) + 0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_PHYS(x) ((x) + 0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OFFS (0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR 0x00060000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ATTR 0x3 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x), m) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),v) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_BMSK 0xf0000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_SHFT 28 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_BMSK 0xf000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_SHFT 24 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_BMSK 0xf00000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_SHFT 20 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_BMSK 0xf0000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_SHFT 16 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_BMSK 0xf000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_SHFT 12 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_BMSK 0xf00 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_SHFT 8 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_BMSK 0xf0 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_SHFT 4 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_BMSK 0xf -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_SHFT 0 - -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x) ((x) + 0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_PHYS(x) ((x) + 0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OFFS (0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR 0x00060000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ATTR 0x3 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x), m) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),v) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_BMSK 0xf0000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_SHFT 28 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_BMSK 0xf000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_SHFT 24 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_BMSK 0xf00000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_SHFT 20 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_BMSK 0xf0000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_SHFT 16 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_BMSK 0xf000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_SHFT 12 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_BMSK 0xf00 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_SHFT 8 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_BMSK 0xf0 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_SHFT 4 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_BMSK 0xf -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_SHFT 0 - -#define HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x) ((x) + 0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_PHYS(x) ((x) + 0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_OFFS (0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_RMSK 0x3f -#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR 0x00000000 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R1_MISC_DEBUG_STATUS_ATTR 0x1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_IN(x) \ - in_dword(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x)) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x), m) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_BMSK 0x20 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_SHFT 5 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_BMSK 0x10 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_SHFT 4 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_BMSK 0x8 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_SHFT 3 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_BMSK 0x4 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_SHFT 2 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_BMSK 0x2 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_SHFT 1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_BMSK 0x1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_SHFT 0 - -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x) ((x) + 0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_PHYS(x) ((x) + 0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OFFS (0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_RMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR 0x00000000 -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR_RMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ATTR 0x3 -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x) \ - in_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x)) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x), m) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUT(x, v) \ - out_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),v) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),m,v,HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x)) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_BMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_SHFT 0 - -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_MAXn 255 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) ((x) + 0x3028) - -#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) ((x) + 0x3070) - -#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) ((x) + 0x3074) - -#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) ((x) + 0x3078) - -#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x) ((x) + 0x30b8) - -#define TQM_REG_REG_BASE (UMAC_BASE + 0x0003c000) -#define TQM_REG_REG_BASE_SIZE 0x4000 - -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_BMSK 0x80 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_SHFT 7 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_BMSK 0x40 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_SHFT 6 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_BMSK 0x20 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_SHFT 5 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_BMSK 0x10 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_SHFT 4 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_BMSK 0x8 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_SHFT 3 - -#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OFFS (0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OFFS (0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_BMSK 0x80000000 -#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_SHFT 31 - -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_BMSK 0x8000 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_SHFT 15 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_BMSK 0x4000 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_SHFT 14 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_BMSK 0x2000 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_SHFT 13 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_BMSK 0x1000 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_SHFT 12 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_BMSK 0x800 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_SHFT 11 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_BMSK 0x400 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_SHFT 10 - -#define HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_OFFS (0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_RMSK 0xf -#define HWIO_TQM_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_TQM_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TQM_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x) ((x) + 0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_PHYS(x) ((x) + 0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OFFS (0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_RMSK 0x1ffff -#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR 0x00000000 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CLKGATE_CTRL_2_ATTR 0x3 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x) \ - in_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x)) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x), m) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUT(x, v) \ - out_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),v) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),m,v,HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x)) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_BMSK 0x2 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_SHFT 1 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_BMSK 0x1 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_SHFT 0 - -#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_BMSK 0x20000000 -#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_SHFT 29 - -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x) ((x) + 0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_PHYS(x) ((x) + 0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OFFS (0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_SHFT 0 - -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x) ((x) + 0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_PHYS(x) ((x) + 0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OFFS (0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_SHFT 0 - -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x) ((x) + 0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_PHYS(x) ((x) + 0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OFFS (0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_SHFT 0 - -#define HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x) ((x) + 0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_PHYS(x) ((x) + 0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OFFS (0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_RMSK 0xfff -#define HWIO_TQM_R0_WATCHDOG_SRNG_POR 0x00000710 -#define HWIO_TQM_R0_WATCHDOG_SRNG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_WATCHDOG_SRNG_ATTR 0x3 -#define HWIO_TQM_R0_WATCHDOG_SRNG_IN(x) \ - in_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x)) -#define HWIO_TQM_R0_WATCHDOG_SRNG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x), m) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),v) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_SRNG_IN(x)) -#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_BMSK 0xfff -#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_SHFT 0 - -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x) ((x) + 0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_PHYS(x) ((x) + 0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OFFS (0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_RMSK 0x1ff -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR 0x000001fe -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_SHFT 8 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_BMSK 0x80 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_SHFT 7 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_BMSK 0x40 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_SHFT 6 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_BMSK 0x20 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_SHFT 5 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_BMSK 0x10 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_SHFT 4 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_BMSK 0x8 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_SHFT 3 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_BMSK 0x4 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_SHFT 2 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_BMSK 0x2 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_SHFT 1 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_BMSK 0x1 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_SHFT 0 - -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x) ((x) + 0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PHYS(x) ((x) + 0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OFFS (0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RMSK 0x3fefff -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR 0x00080170 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ATTR 0x3 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x) \ - in_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x)) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x), m) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),v) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),m,v,HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x)) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_BMSK 0x200000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_SHFT 21 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_BMSK 0x100000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_SHFT 20 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_BMSK 0x80000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_SHFT 19 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_BMSK 0x40000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_SHFT 18 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_BMSK 0x20000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_SHFT 17 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_BMSK 0x10000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_SHFT 16 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_BMSK 0x8000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_SHFT 15 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_BMSK 0x4000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_SHFT 14 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_BMSK 0x2000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_SHFT 13 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_BMSK 0x800 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_SHFT 11 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_BMSK 0x400 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_SHFT 10 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_BMSK 0x200 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_SHFT 9 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_BMSK 0x80 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_SHFT 7 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_BMSK 0x40 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_SHFT 6 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_BMSK 0x20 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_SHFT 5 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_BMSK 0x10 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_SHFT 4 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_BMSK 0x8 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_SHFT 3 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_BMSK 0x4 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_SHFT 2 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_BMSK 0x2 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_SHFT 1 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_BMSK 0x1 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_SHFT 0 - -#define HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_PHYS(x) ((x) + 0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OFFS (0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR 0x00000000 -#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PHYS(x) ((x) + 0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OFFS (0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_RMSK 0x7ffff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR 0x00011100 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x) ((x) + 0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x) ((x) + 0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS (0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x) ((x) + 0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x) ((x) + 0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS (0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x) ((x) + 0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x) ((x) + 0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS (0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR 0x3 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK 0xffff0000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT 16 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK 0xfff0 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT 4 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK 0x8 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT 3 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK 0x4 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT 2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT 1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT 0 - -#define HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x) ((x) + 0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_PHYS(x) ((x) + 0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OFFS (0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x) ((x) + 0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_PHYS(x) ((x) + 0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OFFS (0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x) ((x) + 0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_PHYS(x) ((x) + 0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OFFS (0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x) ((x) + 0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_PHYS(x) ((x) + 0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_OFFS (0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_RMSK 0xf -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR 0x00000000 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ATTR 0x1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x)) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x), m) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_BMSK 0x8 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_SHFT 3 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_BMSK 0x4 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_SHFT 2 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_BMSK 0x2 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_SHFT 1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_BMSK 0x1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_SHFT 0 - -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x) ((x) + 0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_PHYS(x) ((x) + 0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_OFFS (0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR 0x00000000 -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ATTR 0x1 -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_IN(x) \ - in_dword(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x)) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x), m) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_SHFT 0 - -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x) ((x) + 0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_PHYS(x) ((x) + 0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_OFFS (0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR 0x00000000 -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ATTR 0x1 -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_IN(x) \ - in_dword(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x)) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x), m) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_SHFT 0 - -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0xff -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_MAXn 127 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x) ((x) + 0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_PHYS(x) ((x) + 0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OFFS (0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x) ((x) + 0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_PHYS(x) ((x) + 0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OFFS (0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_BMSK 0x80 -#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_SHFT 7 - -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 28 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 27 - -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 - -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 - -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 - -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 - -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 28 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 27 - -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 - -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 - -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 - -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 - -#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_BMSK 0x40 -#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_SHFT 6 - -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x) ((x) + 0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_PHYS(x) ((x) + 0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OFFS (0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_RMSK 0xf -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR 0x0000000a -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ATTR 0x3 -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x) \ - in_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x)) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x), m) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),v) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x)) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_BMSK 0xf -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_SHFT 0 - -#define HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OFFS (0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_RMSK 0x1f -#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_BMSK 0x10 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_SHFT 4 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_BMSK 0x8 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_SHFT 3 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_BMSK 0x4 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_SHFT 2 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_BMSK 0x2 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_SHFT 1 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_UMCMN_R0_LINK_ID_ADDR(x) ((x) + 0x170) -#define HWIO_UMCMN_R0_LINK_ID_PHYS(x) ((x) + 0x170) -#define HWIO_UMCMN_R0_LINK_ID_OFFS (0x170) -#define HWIO_UMCMN_R0_LINK_ID_RMSK 0xffff -#define HWIO_UMCMN_R0_LINK_ID_POR 0x000052c8 -#define HWIO_UMCMN_R0_LINK_ID_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_LINK_ID_ATTR 0x3 -#define HWIO_UMCMN_R0_LINK_ID_IN(x) \ - in_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x)) -#define HWIO_UMCMN_R0_LINK_ID_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_LINK_ID_ADDR(x), m) -#define HWIO_UMCMN_R0_LINK_ID_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x),v) -#define HWIO_UMCMN_R0_LINK_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_LINK_ID_IN(x)) -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_BMSK 0x80 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_SHFT 7 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_BMSK 0x40 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_SHFT 6 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_BMSK 0x38 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_SHFT 3 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_BMSK 0x7 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_SHFT 0 - -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK 0x4000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT 14 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK 0x2000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT 13 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK 0x1000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT 12 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK 0x800 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT 11 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK 0x400 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT 10 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK 0x200 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT 9 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK 0x100 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT 8 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK 0x80 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT 7 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK 0x40 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT 6 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK 0x20 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT 5 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK 0x10 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT 4 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK 0x8 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT 3 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK 0x4 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT 2 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK 0x2 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT 1 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK 0x1 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT 0 - -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x) ((x) + 0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_PHYS(x) ((x) + 0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OFFS (0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_RMSK 0x1 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR 0x00000000 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ATTR 0x3 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x) \ - in_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x)) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x), m) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),v) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x)) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_BMSK 0x1 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_SHFT 0 - -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x) ((x) + 0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_PHYS(x) ((x) + 0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OFFS (0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_RMSK 0x1ffff -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR 0x00000000 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ATTR 0x3 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x) \ - in_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x)) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x), m) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),v) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),m,v,HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x)) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_BMSK 0x1fe00 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_SHFT 9 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_BMSK 0x1fe -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_SHFT 1 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_BMSK 0x1 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_SHFT 0 - -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x1ff -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_BMSK 0x100 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_SHFT 8 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_BMSK 0x80 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_SHFT 7 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_BMSK 0x40 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_SHFT 6 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_BMSK 0x20 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_SHFT 5 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n) ((base) + 0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_PHYS(base,n) ((base) + 0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OFFS(n) (0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_MAXn 7 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR 0x00000000 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ATTR 0x3 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n) \ - in_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n)) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), mask) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTI(base,n,val) \ - out_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),val) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),mask,val,HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n)) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_BMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_SHFT 0 - -#define MAC_TCL_REG_REG_BASE (UMAC_BASE + 0x00044000) - -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) ((x) + 0x20) -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x800000 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 23 - -#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_BMSK 0x200000 -#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_SHFT 21 - -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n) ((base) + 0X74 + (0x4*(n))) -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT 17 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT 14 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT 12 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT 8 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT 7 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT 3 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT 1 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT 0 - -#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n) ((base) + 0X174 + (0x4*(n))) -#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff - -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_BMSK 0x800000 -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_SHFT 23 - -#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_BMSK 0x40 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_SHFT 6 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_BMSK 0x20 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_SHFT 5 - -#define HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x) ((x) + 0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_PHYS(x) ((x) + 0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OFFS (0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_RMSK 0x3 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR 0x00000000 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_CLKGATE_DISABLE2_ATTR 0x3 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x) \ - in_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x)) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x), m) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUT(x, v) \ - out_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),v) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x)) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_BMSK 0x2 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_SHFT 1 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_BMSK 0x1 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_SHFT 0 - -#define HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_OFFS (0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_RMSK 0x7 -#define HWIO_TCL_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_TCL_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_TCL_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_TCL_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_TCL_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_TCL_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TCL_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0x8c8) - -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0x8cc) -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) ((x) + 0x8d0) -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) ((x) + 0x8d8) -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x8e4) - -#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x8e8) - -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x8f8) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x8fc) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x910) - -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x914) -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0x918) - -#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) ((x) + 0x940) - -#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 - -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 - -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x10000 -#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 16 - -#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x10000 -#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 16 - -#define HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_OFFS (0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_RMSK 0x1ff -#define HWIO_TCL_R1_TESTBUS_CTRL_POR 0x00000000 -#define HWIO_TCL_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CTRL_ATTR 0x3 -#define HWIO_TCL_R1_TESTBUS_CTRL_IN(x) \ - in_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x)) -#define HWIO_TCL_R1_TESTBUS_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x), m) -#define HWIO_TCL_R1_TESTBUS_CTRL_OUT(x, v) \ - out_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),v) -#define HWIO_TCL_R1_TESTBUS_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TCL_R1_TESTBUS_CTRL_IN(x)) -#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x100 -#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 8 -#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_BMSK 0xc0 -#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_SHFT 6 -#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_BMSK 0x3f -#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_SHFT 0 - -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_MAXn 511 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) ((x) + 0x2000) - -#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) ((x) + 0x2004) - -#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) ((x) + 0x2008) - -#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwioreg_wifi_top.h b/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwioreg_wifi_top.h deleted file mode 100644 index 072ec2ed4af7..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wcss_seq_hwioreg_wifi_top.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef WCSS_SEQ_HWIOREG_WIFI_TOP_H -#define WCSS_SEQ_HWIOREG_WIFI_TOP_H - -#include "wcss_seq_hwiobase.h" - -#define WFSS_PMM_REG_BASE (WFSS_PMM_BASE + 0x00000000) - -#define HWIO_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_26_ADDR(x) ((x) + 0x164) - -#endif diff --git a/drivers/staging/fw-api/hw/fig/v2/wcss_version.h b/drivers/staging/fw-api/hw/fig/v2/wcss_version.h deleted file mode 100644 index a543f80cca7c..000000000000 --- a/drivers/staging/fw-api/hw/fig/v2/wcss_version.h +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#define WCSS_VERSION 3181 diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/HALcomdef.h b/drivers/staging/fw-api/hw/wcn8750/v1/HALcomdef.h deleted file mode 100644 index 60ee92e6cd2e..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/HALcomdef.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef HAL_COMDEF_H -#define HAL_COMDEF_H - -#ifndef _ARM_ASM_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "com_dtypes.h" - -#ifndef _BOOL32_DEFINED -typedef unsigned long int bool32; -#define _BOOL32_DEFINED -#endif - -#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF - - #define inp(port) (*((volatile byte *) (port))) - #define inpw(port) (*((volatile word *) (port))) - #define inpdw(port) (*((volatile dword *)(port))) - - #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) - #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) - #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) - -#ifdef __cplusplus -} -#endif - -#endif - -#endif - diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/HALhwio.h b/drivers/staging/fw-api/hw/wcn8750/v1/HALhwio.h deleted file mode 100644 index 059d69b1be87..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/HALhwio.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef HAL_HWIO_H -#define HAL_HWIO_H - -#include "HALcomdef.h" - -#define HWIO_BASE_PTR(base) base##_BASE_PTR - -#ifdef __ARMCC_VERSION - #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) -#else - #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) -#endif - -#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) -#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) -#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) -#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) - -#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) -#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) -#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) -#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) -#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) -#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) -#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) - -#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) -#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) -#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) -#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) -#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) -#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) -#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) - -#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) -#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) -#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) -#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) - -#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) -#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) -#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) -#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) - -#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) - -#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) -#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) -#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) -#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) - -#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) -#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) -#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) -#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) - -#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) -#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) - -#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) -#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) -#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) -#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) - -#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) -#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) -#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) -#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) - -#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) - -#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) - -#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) -#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) -#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) -#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) - -#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) -#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) -#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) -#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) -#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) -#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) -#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) - -#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) -#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) -#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) - -#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) -#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) - -#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) -#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) - -#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) -#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) -#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) -#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) -#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) -#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) -#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) -#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) - -#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) -#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) - -#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN -#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) -#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) -#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) -#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) -#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) -#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) -#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) -#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) -#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) -#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) -#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) -#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) -#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) -#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) -#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) -#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR -#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) -#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) -#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) -#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS -#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) -#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) -#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) -#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS -#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) -#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) -#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) -#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK -#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) -#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK -#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT -#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT -#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow -#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) -#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL - -#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) -#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) -#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) -#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) -#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) -#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) -#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) -#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) -#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) -#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) -#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) -#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) -#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) -#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ - static uint32 Readdata, Val_temp, Val; \ - Readdata = HWIO_INX(base, hwiosym); \ - Val_temp = Readdata & ~mask1 & ~mask2; \ - Val = Val_temp | val1 | val2; \ - HWIO_##hwiosym##_OUT(base, Val); \ - } - -#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ - static uint32 Readdata, Val_temp, Val; \ - Readdata = HWIO_INX(base, hwiosym); \ - Val_temp = Readdata & ~mask1 & ~mask2 & ~mask3; \ - Val = Val_temp | val1 | val2 | val3; \ - HWIO_##hwiosym##_OUT(base, Val); \ - } - -#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ - static uint32 Readdata, Val_temp, Val; \ - Readdata = HWIO_INX(base, hwiosym); \ - Val_temp = Readdata & ~mask1 & ~mask2 & ~mask3 & ~mask4; \ - Val = Val_temp | val1 | val2 | val3 | val4; \ - HWIO_##hwiosym##_OUT(base, Val); \ - } - -#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) -#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) -#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) -#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) -#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) -#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) -#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) -#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) -#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) -#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) -#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) - -#define HWIO_INTLOCK() -#define HWIO_INTFREE() - -#define __inp(port) (*((volatile uint8 *) (port))) -#define __inpw(port) (*((volatile uint16 *) (port))) -#define __inpdw(port) (*((volatile uint32 *) (port))) -#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) -#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) -#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) - -#ifdef HAL_HWIO_EXTERNAL - -#undef __inp -#undef __inpw -#undef __inpdw -#undef __outp -#undef __outpw -#undef __outpdw - -#define __inp(port) __inp_extern(port) -#define __inpw(port) __inpw_extern(port) -#define __inpdw(port) __inpdw_extern(port) -#define __outp(port, val) __outp_extern(port, val) -#define __outpw(port, val) __outpw_extern(port, val) -#define __outpdw(port, val) __outpdw_extern(port, val) - -extern uint8 __inp_extern ( uint32 nAddr ); -extern uint16 __inpw_extern ( uint32 nAddr ); -extern uint32 __inpdw_extern ( uint32 nAddr ); -extern void __outp_extern ( uint32 nAddr, uint8 nData ); -extern void __outpw_extern ( uint32 nAddr, uint16 nData ); -extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); - -#endif - -#define in_byte(addr) (__inp(addr)) -#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) -#define out_byte(addr, val) __outp(addr,val) -#define out_byte_masked(io, mask, val, shadow) \ - HWIO_INTLOCK(); \ - out_byte( io, shadow); \ - shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ - HWIO_INTFREE() -#define out_byte_masked_ns(io, mask, val, current_reg_content) \ - out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ - ((uint16)((val) & (mask)))) ) - -#define in_word(addr) (__inpw(addr)) -#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) -#define out_word(addr, val) __outpw(addr,val) -#define out_word_masked(io, mask, val, shadow) \ - HWIO_INTLOCK( ); \ - shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ - out_word( io, shadow); \ - HWIO_INTFREE( ) -#define out_word_masked_ns(io, mask, val, current_reg_content) \ - out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ - ((uint16)((val) & (mask)))) ) - -#define in_dword(addr) (__inpdw(addr)) -#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) -#define out_dword(addr, val) __outpdw(addr,val) -#define out_dword_masked(io, mask, val, shadow) \ - HWIO_INTLOCK(); \ - shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ - out_dword( io, shadow); \ - HWIO_INTFREE() -#define out_dword_masked_ns(io, mask, val, current_reg_content) \ - out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ - ((uint32)((val) & (mask)))) ) - -#endif - diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/ack_report.h b/drivers/staging/fw-api/hw/wcn8750/v1/ack_report.h deleted file mode 100644 index e78921b308fd..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/ack_report.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _ACK_REPORT_H_ -#define _ACK_REPORT_H_ - -#define NUM_OF_DWORDS_ACK_REPORT 1 - -struct ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t selfgen_response_reason : 4, - ax_trigger_type : 4, - sr_ppdu : 1, - reserved : 7, - frame_control : 16; -#else - uint32_t frame_control : 16, - reserved : 7, - sr_ppdu : 1, - ax_trigger_type : 4, - selfgen_response_reason : 4; -#endif -}; - -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3 -#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f - -#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000 -#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4 -#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7 -#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0 - -#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000 -#define ACK_REPORT_SR_PPDU_LSB 8 -#define ACK_REPORT_SR_PPDU_MSB 8 -#define ACK_REPORT_SR_PPDU_MASK 0x00000100 - -#define ACK_REPORT_RESERVED_OFFSET 0x00000000 -#define ACK_REPORT_RESERVED_LSB 9 -#define ACK_REPORT_RESERVED_MSB 15 -#define ACK_REPORT_RESERVED_MASK 0x0000fe00 - -#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 -#define ACK_REPORT_FRAME_CONTROL_LSB 16 -#define ACK_REPORT_FRAME_CONTROL_MSB 31 -#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/boron_top_reg.h b/drivers/staging/fw-api/hw/wcn8750/v1/boron_top_reg.h deleted file mode 100644 index 306398284fe3..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/boron_top_reg.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef BORON_TOP_REG_H -#define BORON_TOP_REG_H - -#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C) -#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050) - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/buffer_addr_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/buffer_addr_info.h deleted file mode 100644 index d65375b54715..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/buffer_addr_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _BUFFER_ADDR_INFO_H_ -#define _BUFFER_ADDR_INFO_H_ - -#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 - -struct buffer_addr_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_addr_31_0 : 32; - uint32_t buffer_addr_39_32 : 8, - return_buffer_manager : 4, - sw_buffer_cookie : 20; -#else - uint32_t buffer_addr_31_0 : 32; - uint32_t sw_buffer_cookie : 20, - return_buffer_manager : 4, - buffer_addr_39_32 : 8; -#endif -}; - -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/ce_src_desc.h b/drivers/staging/fw-api/hw/wcn8750/v1/ce_src_desc.h deleted file mode 100644 index 4ecaedcab2a7..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/ce_src_desc.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _CE_SRC_DESC_H_ -#define _CE_SRC_DESC_H_ - -#define NUM_OF_DWORDS_CE_SRC_DESC 4 - -struct ce_src_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t src_buffer_low : 32; - uint32_t src_buffer_high : 8, - toeplitz_en : 1, - src_swap : 1, - dest_swap : 1, - gather : 1, - ce_res_0 : 1, - barrier_read : 1, - ce_res_1 : 2, - length : 16; - uint32_t fw_metadata : 16, - ce_res_2 : 16; - uint32_t ce_res_3 : 20, - ring_id : 8, - looping_count : 4; -#else - uint32_t src_buffer_low : 32; - uint32_t length : 16, - ce_res_1 : 2, - barrier_read : 1, - ce_res_0 : 1, - gather : 1, - dest_swap : 1, - src_swap : 1, - toeplitz_en : 1, - src_buffer_high : 8; - uint32_t ce_res_2 : 16, - fw_metadata : 16; - uint32_t looping_count : 4, - ring_id : 8, - ce_res_3 : 20; -#endif -}; - -#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000 -#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0 -#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31 -#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff - -#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7 -#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff - -#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004 -#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8 -#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8 -#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100 - -#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004 -#define CE_SRC_DESC_SRC_SWAP_LSB 9 -#define CE_SRC_DESC_SRC_SWAP_MSB 9 -#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200 - -#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004 -#define CE_SRC_DESC_DEST_SWAP_LSB 10 -#define CE_SRC_DESC_DEST_SWAP_MSB 10 -#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400 - -#define CE_SRC_DESC_GATHER_OFFSET 0x00000004 -#define CE_SRC_DESC_GATHER_LSB 11 -#define CE_SRC_DESC_GATHER_MSB 11 -#define CE_SRC_DESC_GATHER_MASK 0x00000800 - -#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004 -#define CE_SRC_DESC_CE_RES_0_LSB 12 -#define CE_SRC_DESC_CE_RES_0_MSB 12 -#define CE_SRC_DESC_CE_RES_0_MASK 0x00001000 - -#define CE_SRC_DESC_BARRIER_READ_OFFSET 0x00000004 -#define CE_SRC_DESC_BARRIER_READ_LSB 13 -#define CE_SRC_DESC_BARRIER_READ_MSB 13 -#define CE_SRC_DESC_BARRIER_READ_MASK 0x00002000 - -#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000004 -#define CE_SRC_DESC_CE_RES_1_LSB 14 -#define CE_SRC_DESC_CE_RES_1_MSB 15 -#define CE_SRC_DESC_CE_RES_1_MASK 0x0000c000 - -#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004 -#define CE_SRC_DESC_LENGTH_LSB 16 -#define CE_SRC_DESC_LENGTH_MSB 31 -#define CE_SRC_DESC_LENGTH_MASK 0xffff0000 - -#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008 -#define CE_SRC_DESC_FW_METADATA_LSB 0 -#define CE_SRC_DESC_FW_METADATA_MSB 15 -#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff - -#define CE_SRC_DESC_CE_RES_2_OFFSET 0x00000008 -#define CE_SRC_DESC_CE_RES_2_LSB 16 -#define CE_SRC_DESC_CE_RES_2_MSB 31 -#define CE_SRC_DESC_CE_RES_2_MASK 0xffff0000 - -#define CE_SRC_DESC_CE_RES_3_OFFSET 0x0000000c -#define CE_SRC_DESC_CE_RES_3_LSB 0 -#define CE_SRC_DESC_CE_RES_3_MSB 19 -#define CE_SRC_DESC_CE_RES_3_MASK 0x000fffff - -#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c -#define CE_SRC_DESC_RING_ID_LSB 20 -#define CE_SRC_DESC_RING_ID_MSB 27 -#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000 - -#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c -#define CE_SRC_DESC_LOOPING_COUNT_LSB 28 -#define CE_SRC_DESC_LOOPING_COUNT_MSB 31 -#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/ce_stat_desc.h b/drivers/staging/fw-api/hw/wcn8750/v1/ce_stat_desc.h deleted file mode 100644 index 0b9f9a221215..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/ce_stat_desc.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _CE_STAT_DESC_H_ -#define _CE_STAT_DESC_H_ - -#define NUM_OF_DWORDS_CE_STAT_DESC 4 - -struct ce_stat_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ce_res_5 : 8, - toeplitz_en : 1, - src_swap : 1, - dest_swap : 1, - gather : 1, - barrier_read : 1, - ce_res_6 : 3, - length : 16; - uint32_t toeplitz_hash_0 : 32; - uint32_t toeplitz_hash_1 : 32; - uint32_t fw_metadata : 16, - ce_res_7 : 4, - ring_id : 8, - looping_count : 4; -#else - uint32_t length : 16, - ce_res_6 : 3, - barrier_read : 1, - gather : 1, - dest_swap : 1, - src_swap : 1, - toeplitz_en : 1, - ce_res_5 : 8; - uint32_t toeplitz_hash_0 : 32; - uint32_t toeplitz_hash_1 : 32; - uint32_t looping_count : 4, - ring_id : 8, - ce_res_7 : 4, - fw_metadata : 16; -#endif -}; - -#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000 -#define CE_STAT_DESC_CE_RES_5_LSB 0 -#define CE_STAT_DESC_CE_RES_5_MSB 7 -#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff - -#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000 -#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8 -#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8 -#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100 - -#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000 -#define CE_STAT_DESC_SRC_SWAP_LSB 9 -#define CE_STAT_DESC_SRC_SWAP_MSB 9 -#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200 - -#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000 -#define CE_STAT_DESC_DEST_SWAP_LSB 10 -#define CE_STAT_DESC_DEST_SWAP_MSB 10 -#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400 - -#define CE_STAT_DESC_GATHER_OFFSET 0x00000000 -#define CE_STAT_DESC_GATHER_LSB 11 -#define CE_STAT_DESC_GATHER_MSB 11 -#define CE_STAT_DESC_GATHER_MASK 0x00000800 - -#define CE_STAT_DESC_BARRIER_READ_OFFSET 0x00000000 -#define CE_STAT_DESC_BARRIER_READ_LSB 12 -#define CE_STAT_DESC_BARRIER_READ_MSB 12 -#define CE_STAT_DESC_BARRIER_READ_MASK 0x00001000 - -#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000 -#define CE_STAT_DESC_CE_RES_6_LSB 13 -#define CE_STAT_DESC_CE_RES_6_MSB 15 -#define CE_STAT_DESC_CE_RES_6_MASK 0x0000e000 - -#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000 -#define CE_STAT_DESC_LENGTH_LSB 16 -#define CE_STAT_DESC_LENGTH_MSB 31 -#define CE_STAT_DESC_LENGTH_MASK 0xffff0000 - -#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31 -#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff - -#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31 -#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff - -#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c -#define CE_STAT_DESC_FW_METADATA_LSB 0 -#define CE_STAT_DESC_FW_METADATA_MSB 15 -#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff - -#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c -#define CE_STAT_DESC_CE_RES_7_LSB 16 -#define CE_STAT_DESC_CE_RES_7_MSB 19 -#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000 - -#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c -#define CE_STAT_DESC_RING_ID_LSB 20 -#define CE_STAT_DESC_RING_ID_MSB 27 -#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000 - -#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c -#define CE_STAT_DESC_LOOPING_COUNT_LSB 28 -#define CE_STAT_DESC_LOOPING_COUNT_MSB 31 -#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/coex_rx_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/coex_rx_status.h deleted file mode 100644 index 7d9c6b4d2057..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/coex_rx_status.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_RX_STATUS_H_ -#define _COEX_RX_STATUS_H_ - -#define NUM_OF_DWORDS_COEX_RX_STATUS 2 - -#define NUM_OF_QWORDS_COEX_RX_STATUS 1 - -struct coex_rx_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_mac_frame_status : 2, - rx_with_tx_response : 1, - rx_rate : 5, - rx_bw : 3, - single_mpdu : 1, - filter_status : 1, - ampdu : 1, - directed : 1, - reserved_0 : 1, - rx_nss : 3, - rx_rssi : 8, - rx_type : 3, - retry_bit_setting : 1, - more_data_bit_setting : 1; - uint32_t remain_rx_packet_time : 16, - rx_remaining_fes_time : 16; -#else - uint32_t more_data_bit_setting : 1, - retry_bit_setting : 1, - rx_type : 3, - rx_rssi : 8, - rx_nss : 3, - reserved_0 : 1, - directed : 1, - ampdu : 1, - filter_status : 1, - single_mpdu : 1, - rx_bw : 3, - rx_rate : 5, - rx_with_tx_response : 1, - rx_mac_frame_status : 2; - uint32_t rx_remaining_fes_time : 16, - remain_rx_packet_time : 16; -#endif -}; - -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 -#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003 - -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 -#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004 - -#define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_RATE_LSB 3 -#define COEX_RX_STATUS_RX_RATE_MSB 7 -#define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8 - -#define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_BW_LSB 8 -#define COEX_RX_STATUS_RX_BW_MSB 10 -#define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700 - -#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 -#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 -#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800 - -#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_FILTER_STATUS_LSB 12 -#define COEX_RX_STATUS_FILTER_STATUS_MSB 12 -#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000 - -#define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_AMPDU_LSB 13 -#define COEX_RX_STATUS_AMPDU_MSB 13 -#define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000 - -#define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_DIRECTED_LSB 14 -#define COEX_RX_STATUS_DIRECTED_MSB 14 -#define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000 - -#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RESERVED_0_LSB 15 -#define COEX_RX_STATUS_RESERVED_0_MSB 15 -#define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000 - -#define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_NSS_LSB 16 -#define COEX_RX_STATUS_RX_NSS_MSB 18 -#define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000 - -#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_RSSI_LSB 19 -#define COEX_RX_STATUS_RX_RSSI_MSB 26 -#define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000 - -#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_TYPE_LSB 27 -#define COEX_RX_STATUS_RX_TYPE_MSB 29 -#define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000 - -#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 -#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000 - -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 -#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000 - -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47 -#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000 - -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63 -#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/coex_tx_req.h b/drivers/staging/fw-api/hw/wcn8750/v1/coex_tx_req.h deleted file mode 100644 index ed5b4c57bfd8..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/coex_tx_req.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_TX_REQ_H_ -#define _COEX_TX_REQ_H_ - -#define NUM_OF_DWORDS_COEX_TX_REQ 6 - -#define NUM_OF_QWORDS_COEX_TX_REQ 3 - -struct coex_tx_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_pwr : 8, - min_tx_pwr : 8, - nss : 3, - tx_chain_mask : 8, - bw : 3, - reserved_0 : 2; - uint32_t alt_tx_pwr : 8, - alt_min_tx_pwr : 8, - alt_nss : 3, - alt_tx_chain_mask : 8, - alt_bw : 3, - reserved_1 : 2; - uint32_t tx_pwr_1 : 8, - alt_tx_pwr_1 : 8, - wlan_request_duration : 16; - uint32_t wlan_pkt_type : 4, - coex_tx_reason : 2, - response_frame_type : 5, - wlan_low_priority_slicing_allowed : 1, - wlan_high_priority_slicing_allowed : 1, - sch_tx_burst_ongoing : 1, - coex_tx_priority : 4, - blackout_details_en : 1, - blackout_peek_duration : 8, - reserved_3a : 5; - uint32_t frequency_channel_bonding_mask : 16, - num_blackout_windows : 8, - reserved_4a : 8; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0 : 2, - bw : 3, - tx_chain_mask : 8, - nss : 3, - min_tx_pwr : 8, - tx_pwr : 8; - uint32_t reserved_1 : 2, - alt_bw : 3, - alt_tx_chain_mask : 8, - alt_nss : 3, - alt_min_tx_pwr : 8, - alt_tx_pwr : 8; - uint32_t wlan_request_duration : 16, - alt_tx_pwr_1 : 8, - tx_pwr_1 : 8; - uint32_t reserved_3a : 5, - blackout_peek_duration : 8, - blackout_details_en : 1, - coex_tx_priority : 4, - sch_tx_burst_ongoing : 1, - wlan_high_priority_slicing_allowed : 1, - wlan_low_priority_slicing_allowed : 1, - response_frame_type : 5, - coex_tx_reason : 2, - wlan_pkt_type : 4; - uint32_t reserved_4a : 8, - num_blackout_windows : 8, - frequency_channel_bonding_mask : 16; - uint32_t tlv64_padding : 32; -#endif -}; - -#define COEX_TX_REQ_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_TX_PWR_LSB 0 -#define COEX_TX_REQ_TX_PWR_MSB 7 -#define COEX_TX_REQ_TX_PWR_MASK 0x00000000000000ff - -#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_MIN_TX_PWR_LSB 8 -#define COEX_TX_REQ_MIN_TX_PWR_MSB 15 -#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define COEX_TX_REQ_NSS_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_NSS_LSB 16 -#define COEX_TX_REQ_NSS_MSB 18 -#define COEX_TX_REQ_NSS_MASK 0x0000000000070000 - -#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19 -#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26 -#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define COEX_TX_REQ_BW_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_BW_LSB 27 -#define COEX_TX_REQ_BW_MSB 29 -#define COEX_TX_REQ_BW_MASK 0x0000000038000000 - -#define COEX_TX_REQ_RESERVED_0_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_RESERVED_0_LSB 30 -#define COEX_TX_REQ_RESERVED_0_MSB 31 -#define COEX_TX_REQ_RESERVED_0_MASK 0x00000000c0000000 - -#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_TX_PWR_LSB 32 -#define COEX_TX_REQ_ALT_TX_PWR_MSB 39 -#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 40 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 47 -#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define COEX_TX_REQ_ALT_NSS_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_NSS_LSB 48 -#define COEX_TX_REQ_ALT_NSS_MSB 50 -#define COEX_TX_REQ_ALT_NSS_MASK 0x0007000000000000 - -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 51 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 58 -#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define COEX_TX_REQ_ALT_BW_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_ALT_BW_LSB 59 -#define COEX_TX_REQ_ALT_BW_MSB 61 -#define COEX_TX_REQ_ALT_BW_MASK 0x3800000000000000 - -#define COEX_TX_REQ_RESERVED_1_OFFSET 0x0000000000000000 -#define COEX_TX_REQ_RESERVED_1_LSB 62 -#define COEX_TX_REQ_RESERVED_1_MSB 63 -#define COEX_TX_REQ_RESERVED_1_MASK 0xc000000000000000 - -#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_TX_PWR_1_LSB 0 -#define COEX_TX_REQ_TX_PWR_1_MSB 7 -#define COEX_TX_REQ_TX_PWR_1_MASK 0x00000000000000ff - -#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8 -#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15 -#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x000000000000ff00 - -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31 -#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0x00000000ffff0000 - -#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 32 -#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 35 -#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f00000000 - -#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_COEX_TX_REASON_LSB 36 -#define COEX_TX_REQ_COEX_TX_REASON_MSB 37 -#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x0000003000000000 - -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 38 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 42 -#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c000000000 - -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 43 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 43 -#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x0000080000000000 - -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 44 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 44 -#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x0000100000000000 - -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 45 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 45 -#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x0000200000000000 - -#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 46 -#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 49 -#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c00000000000 - -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_LSB 50 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MSB 50 -#define COEX_TX_REQ_BLACKOUT_DETAILS_EN_MASK 0x0004000000000000 - -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_LSB 51 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MSB 58 -#define COEX_TX_REQ_BLACKOUT_PEEK_DURATION_MASK 0x07f8000000000000 - -#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000000000008 -#define COEX_TX_REQ_RESERVED_3A_LSB 59 -#define COEX_TX_REQ_RESERVED_3A_MSB 63 -#define COEX_TX_REQ_RESERVED_3A_MASK 0xf800000000000000 - -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_LSB 0 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MSB 15 -#define COEX_TX_REQ_FREQUENCY_CHANNEL_BONDING_MASK_MASK 0x000000000000ffff - -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_LSB 16 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MSB 23 -#define COEX_TX_REQ_NUM_BLACKOUT_WINDOWS_MASK 0x0000000000ff0000 - -#define COEX_TX_REQ_RESERVED_4A_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_RESERVED_4A_LSB 24 -#define COEX_TX_REQ_RESERVED_4A_MSB 31 -#define COEX_TX_REQ_RESERVED_4A_MASK 0x00000000ff000000 - -#define COEX_TX_REQ_TLV64_PADDING_OFFSET 0x0000000000000010 -#define COEX_TX_REQ_TLV64_PADDING_LSB 32 -#define COEX_TX_REQ_TLV64_PADDING_MSB 63 -#define COEX_TX_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/coex_tx_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/coex_tx_status.h deleted file mode 100644 index c47c29c2a5ba..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/coex_tx_status.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _COEX_TX_STATUS_H_ -#define _COEX_TX_STATUS_H_ - -#define NUM_OF_DWORDS_COEX_TX_STATUS 4 - -#define NUM_OF_QWORDS_COEX_TX_STATUS 2 - -struct coex_tx_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 7, - tx_bw : 3, - tx_status_reason : 3, - tx_wait_ack : 1, - fes_tx_is_gen_frame : 1, - sch_tx_burst_ongoing : 1, - current_tx_duration : 16; - uint32_t next_rx_active_time : 16, - remaining_fes_time : 16; - uint32_t tx_antenna_mask : 8, - shared_ant_tx_pwr : 8, - other_ant_tx_pwr : 8, - reserved_2 : 8; - uint32_t tlv64_padding : 32; -#else - uint32_t current_tx_duration : 16, - sch_tx_burst_ongoing : 1, - fes_tx_is_gen_frame : 1, - tx_wait_ack : 1, - tx_status_reason : 3, - tx_bw : 3, - reserved_0a : 7; - uint32_t remaining_fes_time : 16, - next_rx_active_time : 16; - uint32_t reserved_2 : 8, - other_ant_tx_pwr : 8, - shared_ant_tx_pwr : 8, - tx_antenna_mask : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_RESERVED_0A_LSB 0 -#define COEX_TX_STATUS_RESERVED_0A_MSB 6 -#define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f - -#define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_BW_LSB 7 -#define COEX_TX_STATUS_TX_BW_MSB 9 -#define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380 - -#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10 -#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12 -#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00 - -#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13 -#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13 -#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000 - -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14 -#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000 - -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15 -#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000 - -#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31 -#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000 - -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47 -#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000 - -#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000 -#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48 -#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63 -#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000 - -#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7 -#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff - -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15 -#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00 - -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23 -#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000 - -#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_RESERVED_2_LSB 24 -#define COEX_TX_STATUS_RESERVED_2_MSB 31 -#define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000 - -#define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008 -#define COEX_TX_STATUS_TLV64_PADDING_LSB 32 -#define COEX_TX_STATUS_TLV64_PADDING_MSB 63 -#define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/com_dtypes.h b/drivers/staging/fw-api/hw/wcn8750/v1/com_dtypes.h deleted file mode 100644 index aa7bf7a51845..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/com_dtypes.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef COM_DTYPES_H -#define COM_DTYPES_H - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef T_WINNT - #ifndef WIN32 - #define WIN32 - #endif - #include -#endif - -#ifdef TRUE -#undef TRUE -#endif - -#ifdef FALSE -#undef FALSE -#endif - -#define TRUE 1 -#define FALSE 0 - -#define ON 1 -#define OFF 0 - -#ifndef NULL - #define NULL 0 -#endif - -#ifndef _ARM_ASM_ -#ifndef _BOOLEAN_DEFINED - -typedef unsigned char boolean; -#define _BOOLEAN_DEFINED -#endif - -#if defined(DALSTDDEF_H) -#define _BOOLEAN_DEFINED -#define _UINT32_DEFINED -#define _UINT16_DEFINED -#define _UINT8_DEFINED -#define _INT32_DEFINED -#define _INT16_DEFINED -#define _INT8_DEFINED -#define _UINT64_DEFINED -#define _INT64_DEFINED -#define _BYTE_DEFINED -#endif - -#ifndef _UINT32_DEFINED - -typedef unsigned int uint32; -#define _UINT32_DEFINED -#endif - -#ifndef _UINT16_DEFINED - -typedef unsigned short uint16; -#define _UINT16_DEFINED -#endif - -#ifndef _UINT8_DEFINED - -typedef unsigned char uint8; -#define _UINT8_DEFINED -#endif - -#ifndef _INT32_DEFINED - -typedef signed int int32; -#define _INT32_DEFINED -#endif - -#ifndef _INT16_DEFINED - -typedef signed short int16; -#define _INT16_DEFINED -#endif - -#ifndef _INT8_DEFINED - -typedef signed char int8; -#define _INT8_DEFINED -#endif - -#ifndef _BYTE_DEFINED - -typedef unsigned char byte; -#define _BYTE_DEFINED -#endif - -typedef unsigned short word; - -typedef unsigned long dword; - -typedef unsigned char uint1; - -typedef unsigned short uint2; - -typedef unsigned long uint4; - -typedef signed char int1; - -typedef signed short int2; - -typedef long int int4; - -typedef signed long sint31; - -typedef signed short sint15; - -typedef signed char sint7; - -typedef uint16 UWord16 ; -typedef uint32 UWord32 ; -typedef int32 Word32 ; -typedef int16 Word16 ; -typedef uint8 UWord8 ; -typedef int8 Word8 ; -typedef int32 Vect32 ; - -#if (! defined T_WINNT) && (! defined __GNUC__) - - #ifndef _INT64_DEFINED - - typedef long long int64; - #define _INT64_DEFINED - #endif - #ifndef _UINT64_DEFINED - - typedef unsigned long long uint64; - #define _UINT64_DEFINED - #endif -#else - - #if (defined __GNUC__) - #ifndef _INT64_DEFINED - typedef long long int64; - #define _INT64_DEFINED - #endif - #ifndef _UINT64_DEFINED - typedef unsigned long long uint64; - #define _UINT64_DEFINED - #endif - #else - typedef __int64 int64; - #ifndef _UINT64_DEFINED - typedef unsigned __int64 uint64; - #define _UINT64_DEFINED - #endif - #endif -#endif - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_mu_mimo_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_mu_mimo_info.h deleted file mode 100644 index c9e20d75e648..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_mu_mimo_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_ -#define _EHT_SIG_USR_MU_MIMO_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2 - -struct eht_sig_usr_mu_mimo_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - sta_coding : 1, - sta_spatial_config : 6, - reserved_0a : 1, - rx_integrity_check_passed : 1, - subband80_cc_mask : 8; - uint32_t user_order_subband80_0 : 8, - user_order_subband80_1 : 8, - user_order_subband80_2 : 8, - user_order_subband80_3 : 8; -#else - uint32_t subband80_cc_mask : 8, - rx_integrity_check_passed : 1, - reserved_0a : 1, - sta_spatial_config : 6, - sta_coding : 1, - sta_mcs : 4, - sta_id : 11; - uint32_t user_order_subband80_3 : 8, - user_order_subband80_2 : 8, - user_order_subband80_1 : 8, - user_order_subband80_0 : 8; -#endif -}; - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000 - -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21 -#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000 - -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22 -#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000 - -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 - -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31 -#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 - -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31 -#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_ofdma_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_ofdma_info.h deleted file mode 100644 index f2520cccfde9..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_ofdma_info.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_OFDMA_INFO_H_ -#define _EHT_SIG_USR_OFDMA_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2 - -struct eht_sig_usr_ofdma_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - validate_0a : 1, - nss : 4, - txbf : 1, - sta_coding : 1, - reserved_0b : 1, - rx_integrity_check_passed : 1, - subband80_cc_mask : 8; - uint32_t user_order_subband80_0 : 8, - user_order_subband80_1 : 8, - user_order_subband80_2 : 8, - user_order_subband80_3 : 8; -#else - uint32_t subband80_cc_mask : 8, - rx_integrity_check_passed : 1, - reserved_0b : 1, - sta_coding : 1, - txbf : 1, - nss : 4, - validate_0a : 1, - sta_mcs : 4, - sta_id : 11; - uint32_t user_order_subband80_3 : 8, - user_order_subband80_2 : 8, - user_order_subband80_1 : 8, - user_order_subband80_0 : 8; -#endif -}; - -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15 -#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000 - -#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16 -#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19 -#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000 - -#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20 -#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000 - -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21 -#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000 - -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22 -#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000 - -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 - -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31 -#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 - -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31 -#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_su_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_su_info.h deleted file mode 100644 index 208cb4de0539..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/eht_sig_usr_su_info.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EHT_SIG_USR_SU_INFO_H_ -#define _EHT_SIG_USR_SU_INFO_H_ - -#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1 - -struct eht_sig_usr_su_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_mcs : 4, - validate_0a : 1, - nss : 4, - txbf : 1, - sta_coding : 1, - reserved_0b : 9, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0b : 9, - sta_coding : 1, - txbf : 1, - nss : 4, - validate_0a : 1, - sta_mcs : 4, - sta_id : 11; -#endif -}; - -#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0 -#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10 -#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff - -#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11 -#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14 -#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800 - -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15 -#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000 - -#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_NSS_LSB 16 -#define EHT_SIG_USR_SU_INFO_NSS_MSB 19 -#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000 - -#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20 -#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20 -#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000 - -#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21 -#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21 -#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000 - -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30 -#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000 - -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/expected_response.h b/drivers/staging/fw-api/hw/wcn8750/v1/expected_response.h deleted file mode 100644 index 0ef831133865..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/expected_response.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _EXPECTED_RESPONSE_H_ -#define _EXPECTED_RESPONSE_H_ - -#define NUM_OF_DWORDS_EXPECTED_RESPONSE 6 - -#define NUM_OF_QWORDS_EXPECTED_RESPONSE 3 - -struct expected_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_ad2_31_0 : 32; - uint32_t tx_ad2_47_32 : 16, - expected_response_type : 5, - response_to_response : 3, - su_ba_user_number : 1, - response_info_part2_required : 1, - transmitted_bssid_check_en : 1, - eht___reserved_g_0005_ndp_expected : 1, - reserved_1 : 4; - uint32_t ndp_sta_partial_aid_2_8_0 : 11, - reserved_2 : 10, - ndp_sta_partial_aid1_8_0 : 11; - uint32_t ast_index : 16, - capture_ack_ba_sounding : 1, - capture_sounding_1str_20mhz : 1, - capture_sounding_1str_40mhz : 1, - capture_sounding_1str_80mhz : 1, - capture_sounding_1str_160mhz : 1, - capture_sounding_1str_240mhz : 1, - capture_sounding_1str_320mhz : 1, - reserved_3a : 9; - uint32_t fcs : 9, - expect_rx_with_blackout_details : 1, - crc : 4, - scrambler_seed : 7, - reserved_4b : 11; - uint32_t tlv64_padding : 32; -#else - uint32_t tx_ad2_31_0 : 32; - uint32_t reserved_1 : 4, - eht___reserved_g_0005_ndp_expected : 1, - transmitted_bssid_check_en : 1, - response_info_part2_required : 1, - su_ba_user_number : 1, - response_to_response : 3, - expected_response_type : 5, - tx_ad2_47_32 : 16; - uint32_t ndp_sta_partial_aid1_8_0 : 11, - reserved_2 : 10, - ndp_sta_partial_aid_2_8_0 : 11; - uint32_t reserved_3a : 9, - capture_sounding_1str_320mhz : 1, - capture_sounding_1str_240mhz : 1, - capture_sounding_1str_160mhz : 1, - capture_sounding_1str_80mhz : 1, - capture_sounding_1str_40mhz : 1, - capture_sounding_1str_20mhz : 1, - capture_ack_ba_sounding : 1, - ast_index : 16; - uint32_t reserved_4b : 11, - scrambler_seed : 7, - crc : 4, - expect_rx_with_blackout_details : 1, - fcs : 9; - uint32_t tlv64_padding : 32; -#endif -}; - -#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 -#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 -#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff - -#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32 -#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47 -#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000 - -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52 -#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000 - -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55 -#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000 - -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56 -#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000 - -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57 -#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000 - -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58 -#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000 - -#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000 -#define EXPECTED_RESPONSE_RESERVED_1_LSB 60 -#define EXPECTED_RESPONSE_RESERVED_1_MSB 63 -#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf000000000000000 - -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff - -#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_RESERVED_2_LSB 11 -#define EXPECTED_RESPONSE_RESERVED_2_MSB 20 -#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800 - -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 -#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000 - -#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_AST_INDEX_LSB 32 -#define EXPECTED_RESPONSE_AST_INDEX_MSB 47 -#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000 - -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48 -#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000 - -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54 -#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000 - -#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008 -#define EXPECTED_RESPONSE_RESERVED_3A_LSB 55 -#define EXPECTED_RESPONSE_RESERVED_3A_MSB 63 -#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000 - -#define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_FCS_LSB 0 -#define EXPECTED_RESPONSE_FCS_MSB 8 -#define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff - -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB 9 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB 9 -#define EXPECTED_RESPONSE_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK 0x0000000000000200 - -#define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_CRC_LSB 10 -#define EXPECTED_RESPONSE_CRC_MSB 13 -#define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00 - -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 -#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000 - -#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 -#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 -#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000 - -#define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010 -#define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32 -#define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63 -#define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_mu_dl_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_mu_dl_info.h deleted file mode 100644 index 84571eb65d3b..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_mu_dl_info.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_MU_DL_INFO_H_ -#define _HE_SIG_A_MU_DL_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 - -struct he_sig_a_mu_dl_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dl_ul_flag : 1, - mcs_of_sig_b : 3, - dcm_of_sig_b : 1, - bss_color_id : 6, - spatial_reuse : 4, - transmit_bw : 3, - num_sig_b_symbols : 4, - comp_mode_sig_b : 1, - cp_ltf_size : 2, - doppler_indication : 1, - reserved_0a : 6; - uint32_t txop_duration : 7, - reserved_1a : 1, - num_ltf_symbols : 3, - ldpc_extra_symbol : 1, - stbc : 1, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - crc : 4, - tail : 6, - reserved_1b : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0a : 6, - doppler_indication : 1, - cp_ltf_size : 2, - comp_mode_sig_b : 1, - num_sig_b_symbols : 4, - transmit_bw : 3, - spatial_reuse : 4, - bss_color_id : 6, - dcm_of_sig_b : 1, - mcs_of_sig_b : 3, - dl_ul_flag : 1; - uint32_t rx_integrity_check_passed : 1, - reserved_1b : 5, - tail : 6, - crc : 4, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - stbc : 1, - ldpc_extra_symbol : 1, - num_ltf_symbols : 3, - reserved_1a : 1, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0 -#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001 - -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3 -#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e - -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4 -#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010 - -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10 -#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0 - -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14 -#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800 - -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17 -#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000 - -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21 -#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 - -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22 -#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000 - -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24 -#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000 - -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25 -#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000 - -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31 -#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000 - -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080 - -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10 -#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700 - -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11 -#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800 - -#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12 -#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12 -#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000 - -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 - -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 -#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 - -#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16 -#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19 -#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20 -#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25 -#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30 -#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000 - -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_mu_ul_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_mu_ul_info.h deleted file mode 100644 index e2d0ad73a66c..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_mu_ul_info.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_MU_UL_INFO_H_ -#define _HE_SIG_A_MU_UL_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 - -struct he_sig_a_mu_ul_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t format_indication : 1, - bss_color_id : 6, - spatial_reuse : 16, - reserved_0a : 1, - transmit_bw : 2, - reserved_0b : 6; - uint32_t txop_duration : 7, - reserved_1a : 9, - crc : 4, - tail : 6, - reserved_1b : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0b : 6, - transmit_bw : 2, - reserved_0a : 1, - spatial_reuse : 16, - bss_color_id : 6, - format_indication : 1; - uint32_t rx_integrity_check_passed : 1, - reserved_1b : 5, - tail : 6, - crc : 4, - reserved_1a : 9, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0 -#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001 - -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6 -#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e - -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22 -#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000 - -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25 -#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31 -#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000 - -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80 - -#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16 -#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19 -#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20 -#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25 -#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30 -#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000 - -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_su_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_su_info.h deleted file mode 100644 index e4be3671016e..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_a_su_info.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_A_SU_INFO_H_ -#define _HE_SIG_A_SU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2 - -struct he_sig_a_su_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t format_indication : 1, - beam_change : 1, - dl_ul_flag : 1, - transmit_mcs : 4, - dcm : 1, - bss_color_id : 6, - reserved_0a : 1, - spatial_reuse : 4, - transmit_bw : 2, - cp_ltf_size : 2, - nsts : 3, - reserved_0b : 6; - uint32_t txop_duration : 7, - coding : 1, - ldpc_extra_symbol : 1, - stbc : 1, - txbf : 1, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - reserved_1a : 1, - doppler_indication : 1, - crc : 4, - tail : 6, - dot11ax_su_extended : 1, - dot11ax_ext_ru_size : 3, - rx_ndp : 1, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0b : 6, - nsts : 3, - cp_ltf_size : 2, - transmit_bw : 2, - spatial_reuse : 4, - reserved_0a : 1, - bss_color_id : 6, - dcm : 1, - transmit_mcs : 4, - dl_ul_flag : 1, - beam_change : 1, - format_indication : 1; - uint32_t rx_integrity_check_passed : 1, - rx_ndp : 1, - dot11ax_ext_ru_size : 3, - dot11ax_su_extended : 1, - tail : 6, - crc : 4, - doppler_indication : 1, - reserved_1a : 1, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - txbf : 1, - stbc : 1, - ldpc_extra_symbol : 1, - coding : 1, - txop_duration : 7; -#endif -}; - -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0 -#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001 - -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1 -#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002 - -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2 -#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004 - -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6 -#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078 - -#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_DCM_LSB 7 -#define HE_SIG_A_SU_INFO_DCM_MSB 7 -#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080 - -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13 -#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00 - -#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000 - -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18 -#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000 - -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20 -#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000 - -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22 -#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000 - -#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_NSTS_LSB 23 -#define HE_SIG_A_SU_INFO_NSTS_MSB 25 -#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000 - -#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000 -#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26 -#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31 -#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000 - -#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6 -#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f - -#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_CODING_LSB 7 -#define HE_SIG_A_SU_INFO_CODING_MSB 7 -#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080 - -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8 -#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100 - -#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_STBC_LSB 9 -#define HE_SIG_A_SU_INFO_STBC_MSB 9 -#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200 - -#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TXBF_LSB 10 -#define HE_SIG_A_SU_INFO_TXBF_MSB 10 -#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400 - -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 - -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 -#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 - -#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14 -#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000 - -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15 -#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000 - -#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_CRC_LSB 16 -#define HE_SIG_A_SU_INFO_CRC_MSB 19 -#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000 - -#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_TAIL_LSB 20 -#define HE_SIG_A_SU_INFO_TAIL_MSB 25 -#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000 - -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26 -#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 - -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29 -#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 - -#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30 -#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30 -#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000 - -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b1_mu_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b1_mu_info.h deleted file mode 100644 index a248c3dc67b3..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b1_mu_info.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B1_MU_INFO_H_ -#define _HE_SIG_B1_MU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 - -struct he_sig_b1_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_allocation : 8, - reserved_0 : 23, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0 : 23, - ru_allocation : 8; -#endif -}; - -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7 -#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff - -#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8 -#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30 -#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00 - -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b2_mu_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b2_mu_info.h deleted file mode 100644 index 83d6f3bc843f..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b2_mu_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B2_MU_INFO_H_ -#define _HE_SIG_B2_MU_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2 - -struct he_sig_b2_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - sta_spatial_config : 4, - sta_mcs : 4, - reserved_set_to_1 : 1, - sta_coding : 1, - reserved_0a : 7, - nsts : 3, - rx_integrity_check_passed : 1; - uint32_t user_order : 8, - cc_mask : 8, - reserved_1a : 16; -#else - uint32_t rx_integrity_check_passed : 1, - nsts : 3, - reserved_0a : 7, - sta_coding : 1, - reserved_set_to_1 : 1, - sta_mcs : 4, - sta_spatial_config : 4, - sta_id : 11; - uint32_t reserved_1a : 16, - cc_mask : 8, - user_order : 8; -#endif -}; - -#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0 -#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10 -#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff - -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14 -#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800 - -#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15 -#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18 -#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000 - -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19 -#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000 - -#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20 -#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20 -#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000 - -#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27 -#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000 - -#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_NSTS_LSB 28 -#define HE_SIG_B2_MU_INFO_NSTS_MSB 30 -#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000 - -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0 -#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7 -#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff - -#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_CC_MASK_LSB 8 -#define HE_SIG_B2_MU_INFO_CC_MASK_MSB 15 -#define HE_SIG_B2_MU_INFO_CC_MASK_MASK 0x0000ff00 - -#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 16 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31 -#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b2_ofdma_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b2_ofdma_info.h deleted file mode 100644 index 6357d216eb3a..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/he_sig_b2_ofdma_info.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HE_SIG_B2_OFDMA_INFO_H_ -#define _HE_SIG_B2_OFDMA_INFO_H_ - -#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2 - -struct he_sig_b2_ofdma_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sta_id : 11, - nsts : 3, - txbf : 1, - sta_mcs : 4, - sta_dcm : 1, - sta_coding : 1, - reserved_0 : 10, - rx_integrity_check_passed : 1; - uint32_t user_order : 8, - cc_mask : 8, - reserved_1a : 16; -#else - uint32_t rx_integrity_check_passed : 1, - reserved_0 : 10, - sta_coding : 1, - sta_dcm : 1, - sta_mcs : 4, - txbf : 1, - nsts : 3, - sta_id : 11; - uint32_t reserved_1a : 16, - cc_mask : 8, - user_order : 8; -#endif -}; - -#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10 -#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff - -#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11 -#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13 -#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800 - -#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14 -#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14 -#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000 - -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18 -#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000 - -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19 -#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000 - -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20 -#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000 - -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000 - -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7 -#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff - -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15 -#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00 - -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31 -#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/ht_sig_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/ht_sig_info.h deleted file mode 100644 index d6a4a719e6e2..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/ht_sig_info.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _HT_SIG_INFO_H_ -#define _HT_SIG_INFO_H_ - -#define NUM_OF_DWORDS_HT_SIG_INFO 2 - -struct ht_sig_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mcs : 7, - cbw : 1, - length : 16, - reserved_0 : 8; - uint32_t smoothing : 1, - not_sounding : 1, - ht_reserved : 1, - aggregation : 1, - stbc : 2, - fec_coding : 1, - short_gi : 1, - num_ext_sp_str : 2, - crc : 8, - signal_tail : 6, - reserved_1 : 7, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0 : 8, - length : 16, - cbw : 1, - mcs : 7; - uint32_t rx_integrity_check_passed : 1, - reserved_1 : 7, - signal_tail : 6, - crc : 8, - num_ext_sp_str : 2, - short_gi : 1, - fec_coding : 1, - stbc : 2, - aggregation : 1, - ht_reserved : 1, - not_sounding : 1, - smoothing : 1; -#endif -}; - -#define HT_SIG_INFO_MCS_OFFSET 0x00000000 -#define HT_SIG_INFO_MCS_LSB 0 -#define HT_SIG_INFO_MCS_MSB 6 -#define HT_SIG_INFO_MCS_MASK 0x0000007f - -#define HT_SIG_INFO_CBW_OFFSET 0x00000000 -#define HT_SIG_INFO_CBW_LSB 7 -#define HT_SIG_INFO_CBW_MSB 7 -#define HT_SIG_INFO_CBW_MASK 0x00000080 - -#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000 -#define HT_SIG_INFO_LENGTH_LSB 8 -#define HT_SIG_INFO_LENGTH_MSB 23 -#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00 - -#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000 -#define HT_SIG_INFO_RESERVED_0_LSB 24 -#define HT_SIG_INFO_RESERVED_0_MSB 31 -#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000 - -#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004 -#define HT_SIG_INFO_SMOOTHING_LSB 0 -#define HT_SIG_INFO_SMOOTHING_MSB 0 -#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001 - -#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004 -#define HT_SIG_INFO_NOT_SOUNDING_LSB 1 -#define HT_SIG_INFO_NOT_SOUNDING_MSB 1 -#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002 - -#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004 -#define HT_SIG_INFO_HT_RESERVED_LSB 2 -#define HT_SIG_INFO_HT_RESERVED_MSB 2 -#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004 - -#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004 -#define HT_SIG_INFO_AGGREGATION_LSB 3 -#define HT_SIG_INFO_AGGREGATION_MSB 3 -#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008 - -#define HT_SIG_INFO_STBC_OFFSET 0x00000004 -#define HT_SIG_INFO_STBC_LSB 4 -#define HT_SIG_INFO_STBC_MSB 5 -#define HT_SIG_INFO_STBC_MASK 0x00000030 - -#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004 -#define HT_SIG_INFO_FEC_CODING_LSB 6 -#define HT_SIG_INFO_FEC_CODING_MSB 6 -#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040 - -#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004 -#define HT_SIG_INFO_SHORT_GI_LSB 7 -#define HT_SIG_INFO_SHORT_GI_MSB 7 -#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080 - -#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004 -#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8 -#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9 -#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300 - -#define HT_SIG_INFO_CRC_OFFSET 0x00000004 -#define HT_SIG_INFO_CRC_LSB 10 -#define HT_SIG_INFO_CRC_MSB 17 -#define HT_SIG_INFO_CRC_MASK 0x0003fc00 - -#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004 -#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18 -#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23 -#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000 - -#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004 -#define HT_SIG_INFO_RESERVED_1_LSB 24 -#define HT_SIG_INFO_RESERVED_1_MSB 30 -#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000 - -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/l_sig_a_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/l_sig_a_info.h deleted file mode 100644 index 6da0725dfee7..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/l_sig_a_info.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _L_SIG_A_INFO_H_ -#define _L_SIG_A_INFO_H_ - -#define NUM_OF_DWORDS_L_SIG_A_INFO 1 - -struct l_sig_a_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rate : 4, - lsig_reserved : 1, - length : 12, - parity : 1, - tail : 6, - pkt_type : 4, - captured_implicit_sounding : 1, - reserved : 2, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved : 2, - captured_implicit_sounding : 1, - pkt_type : 4, - tail : 6, - parity : 1, - length : 12, - lsig_reserved : 1, - rate : 4; -#endif -}; - -#define L_SIG_A_INFO_RATE_OFFSET 0x00000000 -#define L_SIG_A_INFO_RATE_LSB 0 -#define L_SIG_A_INFO_RATE_MSB 3 -#define L_SIG_A_INFO_RATE_MASK 0x0000000f - -#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000 -#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4 -#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4 -#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010 - -#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000 -#define L_SIG_A_INFO_LENGTH_LSB 5 -#define L_SIG_A_INFO_LENGTH_MSB 16 -#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0 - -#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000 -#define L_SIG_A_INFO_PARITY_LSB 17 -#define L_SIG_A_INFO_PARITY_MSB 17 -#define L_SIG_A_INFO_PARITY_MASK 0x00020000 - -#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000 -#define L_SIG_A_INFO_TAIL_LSB 18 -#define L_SIG_A_INFO_TAIL_MSB 23 -#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000 - -#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000 -#define L_SIG_A_INFO_PKT_TYPE_LSB 24 -#define L_SIG_A_INFO_PKT_TYPE_MSB 27 -#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000 - -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 - -#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000 -#define L_SIG_A_INFO_RESERVED_LSB 29 -#define L_SIG_A_INFO_RESERVED_MSB 30 -#define L_SIG_A_INFO_RESERVED_MASK 0x60000000 - -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/l_sig_b_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/l_sig_b_info.h deleted file mode 100644 index f2052702e2de..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/l_sig_b_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _L_SIG_B_INFO_H_ -#define _L_SIG_B_INFO_H_ - -#define NUM_OF_DWORDS_L_SIG_B_INFO 1 - -struct l_sig_b_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rate : 4, - length : 12, - reserved : 15, - rx_integrity_check_passed : 1; -#else - uint32_t rx_integrity_check_passed : 1, - reserved : 15, - length : 12, - rate : 4; -#endif -}; - -#define L_SIG_B_INFO_RATE_OFFSET 0x00000000 -#define L_SIG_B_INFO_RATE_LSB 0 -#define L_SIG_B_INFO_RATE_MSB 3 -#define L_SIG_B_INFO_RATE_MASK 0x0000000f - -#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000 -#define L_SIG_B_INFO_LENGTH_LSB 4 -#define L_SIG_B_INFO_LENGTH_MSB 15 -#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0 - -#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000 -#define L_SIG_B_INFO_RESERVED_LSB 16 -#define L_SIG_B_INFO_RESERVED_MSB 30 -#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000 - -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/macrx_abort_request_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/macrx_abort_request_info.h deleted file mode 100644 index 038f4038fa59..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/macrx_abort_request_info.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACRX_ABORT_REQUEST_INFO_H_ -#define _MACRX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1 - -struct macrx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t macrx_abort_reason : 8, - reserved_0 : 8; -#else - uint16_t reserved_0 : 8, - macrx_abort_reason : 8; -#endif -}; - -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7 -#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff - -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 -#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_mu_mimo.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_mu_mimo.h deleted file mode 100644 index f29ca356a223..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_mu_mimo.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_ -#define _MACTX_EHT_SIG_USR_MU_MIMO_H_ - -#include "eht_sig_usr_mu_mimo_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1 - -struct mactx_eht_sig_usr_mu_mimo { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; -#else - struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; -#endif -}; - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 - -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 -#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_ofdma.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_ofdma.h deleted file mode 100644 index 24bf6691978d..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_ofdma.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_ -#define _MACTX_EHT_SIG_USR_OFDMA_H_ - -#include "eht_sig_usr_ofdma_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_OFDMA 1 - -struct mactx_eht_sig_usr_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; -#else - struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; -#endif -}; - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x00000000000f0000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000100000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x0000000000400000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 - -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 -#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_su.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_su.h deleted file mode 100644 index 1fb82723c1ff..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_eht_sig_usr_su.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_EHT_SIG_USR_SU_H_ -#define _MACTX_EHT_SIG_USR_SU_H_ - -#include "eht_sig_usr_su_info.h" -#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 2 - -#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_SU 1 - -struct mactx_eht_sig_usr_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; - uint32_t tlv64_padding : 32; -#else - struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x00000000000f0000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x0000000000100000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x000000007fc00000 - -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_LSB 32 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MSB 63 -#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_mu_dl.h deleted file mode 100644 index 438f3af6f9e7..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_mu_dl.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_MU_DL_H_ -#define _MACTX_HE_SIG_A_MU_DL_H_ - -#include "he_sig_a_mu_dl_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_DL 1 - -struct mactx_he_sig_a_mu_dl { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; -#else - struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_mu_ul.h deleted file mode 100644 index 96d2b912665a..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_mu_ul.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_MU_UL_H_ -#define _MACTX_HE_SIG_A_MU_UL_H_ - -#include "he_sig_a_mu_ul_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_UL 1 - -struct mactx_he_sig_a_mu_ul { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; -#else - struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_su.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_su.h deleted file mode 100644 index e51241d26559..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_a_su.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_A_SU_H_ -#define _MACTX_HE_SIG_A_SU_H_ - -#include "he_sig_a_su_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_A_SU 1 - -struct mactx_he_sig_a_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_su_info mactx_he_sig_a_su_info_details; -#else - struct he_sig_a_su_info mactx_he_sig_a_su_info_details; -#endif -}; - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b1_mu.h deleted file mode 100644 index 700528af2048..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b1_mu.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B1_MU_H_ -#define _MACTX_HE_SIG_B1_MU_H_ - -#include "he_sig_b1_mu_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1 - -struct mactx_he_sig_b1_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#else - struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 - -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 -#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b2_mu.h deleted file mode 100644 index ccc1c593fed6..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b2_mu.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B2_MU_H_ -#define _MACTX_HE_SIG_B2_MU_H_ - -#include "he_sig_b2_mu_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_MU 1 - -struct mactx_he_sig_b2_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; -#else - struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; -#endif -}; - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b2_ofdma.h deleted file mode 100644 index afc3c4b22841..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_he_sig_b2_ofdma.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HE_SIG_B2_OFDMA_H_ -#define _MACTX_HE_SIG_B2_OFDMA_H_ - -#include "he_sig_b2_ofdma_info.h" -#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2 - -#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_OFDMA 1 - -struct mactx_he_sig_b2_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; -#else - struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; -#endif -}; - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_ht_sig.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_ht_sig.h deleted file mode 100644 index ec28824c590f..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_ht_sig.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_HT_SIG_H_ -#define _MACTX_HT_SIG_H_ - -#include "ht_sig_info.h" -#define NUM_OF_DWORDS_MACTX_HT_SIG 2 - -#define NUM_OF_QWORDS_MACTX_HT_SIG 1 - -struct mactx_ht_sig { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ht_sig_info mactx_ht_sig_info_details; -#else - struct ht_sig_info mactx_ht_sig_info_details; -#endif -}; - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 36 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 37 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 42 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 49 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_l_sig_a.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_l_sig_a.h deleted file mode 100644 index 061e46e28a2c..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_l_sig_a.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_L_SIG_A_H_ -#define _MACTX_L_SIG_A_H_ - -#include "l_sig_a_info.h" -#define NUM_OF_DWORDS_MACTX_L_SIG_A 2 - -#define NUM_OF_QWORDS_MACTX_L_SIG_A 1 - -struct mactx_l_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_a_info mactx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_a_info mactx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 - -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_A_TLV64_PADDING_LSB 32 -#define MACTX_L_SIG_A_TLV64_PADDING_MSB 63 -#define MACTX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_l_sig_b.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_l_sig_b.h deleted file mode 100644 index 6d533acef675..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_l_sig_b.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_L_SIG_B_H_ -#define _MACTX_L_SIG_B_H_ - -#include "l_sig_b_info.h" -#define NUM_OF_DWORDS_MACTX_L_SIG_B 2 - -#define NUM_OF_QWORDS_MACTX_L_SIG_B 1 - -struct mactx_l_sig_b { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_b_info mactx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_b_info mactx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 - -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define MACTX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_L_SIG_B_TLV64_PADDING_LSB 32 -#define MACTX_L_SIG_B_TLV64_PADDING_MSB 63 -#define MACTX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_phy_desc.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_phy_desc.h deleted file mode 100644 index ee4ccdf65c28..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_phy_desc.h +++ /dev/null @@ -1,348 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_PHY_DESC_H_ -#define _MACTX_PHY_DESC_H_ - -#define NUM_OF_DWORDS_MACTX_PHY_DESC 4 - -#define NUM_OF_QWORDS_MACTX_PHY_DESC 2 - -struct mactx_phy_desc { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 16, - bf_type : 2, - wait_sifs : 2, - dot11b_preamble_type : 1, - pkt_type : 4, - su_or_mu : 2, - mu_type : 1, - bandwidth : 3, - channel_capture : 1; - uint32_t mcs : 5, - global_ofdma_mimo_enable : 1, - stbc : 1, - dot11ax_su_extended : 1, - dot11ax_trigger_frame_embedded : 1, - tx_pwr_shared : 8, - tx_pwr_unshared : 8, - measure_power : 1, - tpc_glut_self_cal : 1, - back_to_back_transmission_expected : 1, - heavy_clip_nss : 3, - txbf_per_packet_no_csd_no_walsh : 1; - uint32_t ndp : 3, - ul_flag : 1, - triggered : 1, - ap_pkt_bw : 3, - ru_position_start : 8, - pcu_ppdu_setup_start_reason : 3, - tlv_source : 1, - reserved_2a : 1, - nss : 3, - stream_offset : 3, - reserved_2b : 2, - clpc_enable : 1, - mu_ndp : 1, - response_expected : 1; - uint32_t rx_chain_mask : 8, - rx_chain_mask_valid : 1, - ant_sel_valid : 1, - ant_sel : 1, - cp_setting : 2, - he_ppdu_subtype : 2, - active_channel : 3, - generate_phyrx_tx_start_timing : 1, - ltf_size : 2, - ru_size_updated_v2 : 4, - reserved_3c : 1, - u_sig_puncture_pattern_encoding : 6; -#else - uint32_t channel_capture : 1, - bandwidth : 3, - mu_type : 1, - su_or_mu : 2, - pkt_type : 4, - dot11b_preamble_type : 1, - wait_sifs : 2, - bf_type : 2, - reserved_0a : 16; - uint32_t txbf_per_packet_no_csd_no_walsh : 1, - heavy_clip_nss : 3, - back_to_back_transmission_expected : 1, - tpc_glut_self_cal : 1, - measure_power : 1, - tx_pwr_unshared : 8, - tx_pwr_shared : 8, - dot11ax_trigger_frame_embedded : 1, - dot11ax_su_extended : 1, - stbc : 1, - global_ofdma_mimo_enable : 1, - mcs : 5; - uint32_t response_expected : 1, - mu_ndp : 1, - clpc_enable : 1, - reserved_2b : 2, - stream_offset : 3, - nss : 3, - reserved_2a : 1, - tlv_source : 1, - pcu_ppdu_setup_start_reason : 3, - ru_position_start : 8, - ap_pkt_bw : 3, - triggered : 1, - ul_flag : 1, - ndp : 3; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_3c : 1, - ru_size_updated_v2 : 4, - ltf_size : 2, - generate_phyrx_tx_start_timing : 1, - active_channel : 3, - he_ppdu_subtype : 2, - cp_setting : 2, - ant_sel : 1, - ant_sel_valid : 1, - rx_chain_mask_valid : 1, - rx_chain_mask : 8; -#endif -}; - -#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_RESERVED_0A_LSB 0 -#define MACTX_PHY_DESC_RESERVED_0A_MSB 15 -#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff - -#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BF_TYPE_LSB 16 -#define MACTX_PHY_DESC_BF_TYPE_MSB 17 -#define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000 - -#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 -#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 -#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000 - -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 -#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000 - -#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_PKT_TYPE_LSB 21 -#define MACTX_PHY_DESC_PKT_TYPE_MSB 24 -#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000 - -#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_SU_OR_MU_LSB 25 -#define MACTX_PHY_DESC_SU_OR_MU_MSB 26 -#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000 - -#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MU_TYPE_LSB 27 -#define MACTX_PHY_DESC_MU_TYPE_MSB 27 -#define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000 - -#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BANDWIDTH_LSB 28 -#define MACTX_PHY_DESC_BANDWIDTH_MSB 30 -#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000 - -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 -#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000 - -#define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MCS_LSB 32 -#define MACTX_PHY_DESC_MCS_MSB 36 -#define MACTX_PHY_DESC_MCS_MASK 0x0000001f00000000 - -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 37 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 37 -#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000002000000000 - -#define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_STBC_LSB 38 -#define MACTX_PHY_DESC_STBC_MSB 38 -#define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000 - -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39 -#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000 - -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40 -#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000 - -#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41 -#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48 -#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000 - -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56 -#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000 - -#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_MEASURE_POWER_LSB 57 -#define MACTX_PHY_DESC_MEASURE_POWER_MSB 57 -#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000 - -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58 -#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000 - -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59 -#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000 - -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62 -#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000 - -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63 -#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000 - -#define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_NDP_LSB 0 -#define MACTX_PHY_DESC_NDP_MSB 2 -#define MACTX_PHY_DESC_NDP_MASK 0x0000000000000007 - -#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_UL_FLAG_LSB 3 -#define MACTX_PHY_DESC_UL_FLAG_MSB 3 -#define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000008 - -#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_TRIGGERED_LSB 4 -#define MACTX_PHY_DESC_TRIGGERED_MSB 4 -#define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000010 - -#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_AP_PKT_BW_LSB 5 -#define MACTX_PHY_DESC_AP_PKT_BW_MSB 7 -#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x00000000000000e0 - -#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RU_POSITION_START_LSB 8 -#define MACTX_PHY_DESC_RU_POSITION_START_MSB 15 -#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x000000000000ff00 - -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 16 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 18 -#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000070000 - -#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_TLV_SOURCE_LSB 19 -#define MACTX_PHY_DESC_TLV_SOURCE_MSB 19 -#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000080000 - -#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_2A_LSB 20 -#define MACTX_PHY_DESC_RESERVED_2A_MSB 20 -#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000100000 - -#define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_NSS_LSB 21 -#define MACTX_PHY_DESC_NSS_MSB 23 -#define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000 - -#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 -#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 -#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000 - -#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_2B_LSB 27 -#define MACTX_PHY_DESC_RESERVED_2B_MSB 28 -#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000 - -#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 -#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 -#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000 - -#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_MU_NDP_LSB 30 -#define MACTX_PHY_DESC_MU_NDP_MSB 30 -#define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000 - -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 -#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000 - -#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000 - -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40 -#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000 - -#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41 -#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41 -#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000 - -#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ANT_SEL_LSB 42 -#define MACTX_PHY_DESC_ANT_SEL_MSB 42 -#define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000 - -#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_CP_SETTING_LSB 43 -#define MACTX_PHY_DESC_CP_SETTING_MSB 44 -#define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000 - -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46 -#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000 - -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49 -#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000 - -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50 -#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000 - -#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_LTF_SIZE_LSB 51 -#define MACTX_PHY_DESC_LTF_SIZE_MSB 52 -#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000 - -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56 -#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000 - -#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_RESERVED_3C_LSB 57 -#define MACTX_PHY_DESC_RESERVED_3C_MSB 57 -#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000 - -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_u_sig_eht_su_mu.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_u_sig_eht_su_mu.h deleted file mode 100644 index f46583e4c7ee..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_u_sig_eht_su_mu.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_U_SIG_EHT_SU_MU_H_ -#define _MACTX_U_SIG_EHT_SU_MU_H_ - -#include "u_sig_eht_su_mu_info.h" -#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2 - -#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_SU_MU 1 - -struct mactx_u_sig_eht_su_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; -#else - struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; -#endif -}; - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB 0 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB 2 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000001f00000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x0000000002000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 34 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 34 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 35 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 39 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f800000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 40 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 40 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x0000010000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 41 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 42 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x0000060000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 43 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 47 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f80000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 48 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 51 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 59 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 61 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x3800000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 62 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 62 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_u_sig_eht_tb.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_u_sig_eht_tb.h deleted file mode 100644 index 5e57312a9da2..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_u_sig_eht_tb.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_U_SIG_EHT_TB_H_ -#define _MACTX_U_SIG_EHT_TB_H_ - -#include "u_sig_eht_tb_info.h" -#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2 - -#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1 - -struct mactx_u_sig_eht_tb { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; -#else - struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; -#endif -}; - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000003f00000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 34 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 34 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 35 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 42 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f800000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 43 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 47 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f80000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 48 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 51 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 52 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 57 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 58 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 62 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c00000000000000 - -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_user_desc_common.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_user_desc_common.h deleted file mode 100644 index 04124271bbc9..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_user_desc_common.h +++ /dev/null @@ -1,482 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_USER_DESC_COMMON_H_ -#define _MACTX_USER_DESC_COMMON_H_ - -#include "unallocated_ru_160_info.h" -#include "ru_allocation_160_info.h" -#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 - -#define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8 - -struct mactx_user_desc_common { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t num_users : 6, - reserved_0b : 5, - ltf_size : 2, - reserved_0c : 3, - he_stf_long : 1, - reserved_0d : 7, - num_users_he_sigb_band0 : 8; - uint32_t num_ltf_symbols : 3, - reserved_1a : 5, - num_users_he_sigb_band1 : 8, - reserved_1b : 16; - uint32_t packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - packet_extension : 3, - reserved : 2, - he_sigb_dcm : 1, - reserved_2b : 7, - he_sigb_compression : 1, - reserved_2c : 15; - uint32_t he_sigb_0_mcs : 3, - reserved_3a : 13, - num_he_sigb_sym : 5, - center_ru_0 : 1, - center_ru_1 : 1, - reserved_3b : 1, - ftm_en : 1, - pe_nss : 3, - pe_ltf_size : 2, - pe_content : 1, - pe_chain_csd_en : 1; - struct ru_allocation_160_info ru_allocation_0123_details; - struct ru_allocation_160_info ru_allocation_4567_details; - struct unallocated_ru_160_info ru_allocation_160_0_details; - struct unallocated_ru_160_info ru_allocation_160_1_details; - uint32_t num_data_symbols : 16, - ndp_ru_tone_set_index : 7, - ndp_feedback_status : 1, - doppler_indication : 1, - reserved_14a : 7; - uint32_t spatial_reuse : 16, - distributed_ru : 1, - dru_spreading_bw : 2, - reserved_15a : 13; -#else - uint32_t num_users_he_sigb_band0 : 8, - reserved_0d : 7, - he_stf_long : 1, - reserved_0c : 3, - ltf_size : 2, - reserved_0b : 5, - num_users : 6; - uint32_t reserved_1b : 16, - num_users_he_sigb_band1 : 8, - reserved_1a : 5, - num_ltf_symbols : 3; - uint32_t reserved_2c : 15, - he_sigb_compression : 1, - reserved_2b : 7, - he_sigb_dcm : 1, - reserved : 2, - packet_extension : 3, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2; - uint32_t pe_chain_csd_en : 1, - pe_content : 1, - pe_ltf_size : 2, - pe_nss : 3, - ftm_en : 1, - reserved_3b : 1, - center_ru_1 : 1, - center_ru_0 : 1, - num_he_sigb_sym : 5, - reserved_3a : 13, - he_sigb_0_mcs : 3; - struct ru_allocation_160_info ru_allocation_0123_details; - struct ru_allocation_160_info ru_allocation_4567_details; - struct unallocated_ru_160_info ru_allocation_160_0_details; - struct unallocated_ru_160_info ru_allocation_160_1_details; - uint32_t reserved_14a : 7, - doppler_indication : 1, - ndp_feedback_status : 1, - ndp_ru_tone_set_index : 7, - num_data_symbols : 16; - uint32_t reserved_15a : 13, - dru_spreading_bw : 2, - distributed_ru : 1, - spatial_reuse : 16; -#endif -}; - -#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 -#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 -#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x000000000000003f - -#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 -#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x00000000000007c0 - -#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 -#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x0000000000001800 - -#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 -#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x000000000000e000 - -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 -#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 -#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x0000000000fe0000 - -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 32 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 34 -#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 35 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 39 -#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f800000000 - -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 40 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 47 -#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff0000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 48 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 63 -#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff000000000000 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 - -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 -#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x0000000000000038 - -#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 -#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 -#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x00000000000000c0 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 -#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x0000000000000100 - -#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 -#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x000000000000fe00 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 -#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 -#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0x00000000fffe0000 - -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 32 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 34 -#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x0000000700000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 35 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 47 -#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff800000000 - -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 48 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 52 -#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f000000000000 - -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 53 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 53 -#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x0020000000000000 - -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 54 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 54 -#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x0040000000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 55 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 55 -#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x0080000000000000 - -#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 56 -#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 56 -#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x0100000000000000 - -#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 57 -#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 59 -#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e00000000000000 - -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 60 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 61 -#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x3000000000000000 - -#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 62 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 62 -#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x4000000000000000 - -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 63 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 63 -#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000000000000018 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x0000000000000020 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000000000000028 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 50 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x00000000000000ff - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x000000000000ff00 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x0000000000ff0000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 32 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 39 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff00000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 40 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 47 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff0000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 48 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 55 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff000000000000 - -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 56 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 63 -#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff00000000000000 - -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 -#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x000000000000ffff - -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 -#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x00000000007f0000 - -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 -#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x0000000000800000 - -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 -#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x0000000001000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 -#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0x00000000fe000000 - -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 32 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 47 -#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_LSB 48 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MSB 48 -#define MACTX_USER_DESC_COMMON_DISTRIBUTED_RU_MASK 0x0001000000000000 - -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_LSB 49 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MSB 50 -#define MACTX_USER_DESC_COMMON_DRU_SPREADING_BW_MASK 0x0006000000000000 - -#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000000000000038 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 51 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 63 -#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xfff8000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_user_desc_per_user.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_user_desc_per_user.h deleted file mode 100644 index a68b50d9d639..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_user_desc_per_user.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_USER_DESC_PER_USER_H_ -#define _MACTX_USER_DESC_PER_USER_H_ - -#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 6 - -#define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 3 - -struct mactx_user_desc_per_user { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t psdu_length : 24, - reserved_0a : 8; - uint32_t ru_start_index : 8, - ru_size : 4, - reserved_1b : 4, - ofdma_mu_mimo_enabled : 1, - nss : 3, - stream_offset : 3, - reserved_1c : 1, - mcs : 5, - dcm : 1, - reserved_1d : 2; - uint32_t fec_type : 1, - reserved_2a : 1, - qam_diff1 : 2, - qam_diff2 : 2, - qam_diff3 : 2, - user_bf_type : 2, - a_factor_ldpc2x : 2, - extra_sym_ldpc2x : 1, - cw_len_2x : 2, - reserved_2b : 1, - drop_user_cbf : 1, - a_factor_ldpc1x : 2, - extra_sym_ldpc1x : 1, - cw_len_1x : 2, - ldpc1x_used : 1, - ldpc2x_used : 1, - ldpc_extra_symbol : 1, - force_extra_symbol : 1, - ldpc_2x_codeword : 1, - reserved_2d : 5; - uint32_t sw_peer_id : 16, - per_user_subband_mask : 16; - uint32_t ldpc_num_avbits : 27, - reserved_4a : 5; - uint32_t num_cw_1x : 16, - num_cw_2x : 16; -#else - uint32_t reserved_0a : 8, - psdu_length : 24; - uint32_t reserved_1d : 2, - dcm : 1, - mcs : 5, - reserved_1c : 1, - stream_offset : 3, - nss : 3, - ofdma_mu_mimo_enabled : 1, - reserved_1b : 4, - ru_size : 4, - ru_start_index : 8; - uint32_t reserved_2d : 5, - ldpc_2x_codeword : 1, - force_extra_symbol : 1, - ldpc_extra_symbol : 1, - ldpc2x_used : 1, - ldpc1x_used : 1, - cw_len_1x : 2, - extra_sym_ldpc1x : 1, - a_factor_ldpc1x : 2, - drop_user_cbf : 1, - reserved_2b : 1, - cw_len_2x : 2, - extra_sym_ldpc2x : 1, - a_factor_ldpc2x : 2, - user_bf_type : 2, - qam_diff3 : 2, - qam_diff2 : 2, - qam_diff1 : 2, - reserved_2a : 1, - fec_type : 1; - uint32_t per_user_subband_mask : 16, - sw_peer_id : 16; - uint32_t reserved_4a : 5, - ldpc_num_avbits : 27; - uint32_t num_cw_2x : 16, - num_cw_1x : 16; -#endif -}; - -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23 -#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x0000000000ffffff - -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0x00000000ff000000 - -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 32 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 39 -#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff00000000 - -#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 40 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 43 -#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f0000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 44 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 47 -#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f00000000000 - -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 48 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 48 -#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x0001000000000000 - -#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_NSS_LSB 49 -#define MACTX_USER_DESC_PER_USER_NSS_MSB 51 -#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e000000000000 - -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 52 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 54 -#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x0070000000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 55 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 55 -#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x0080000000000000 - -#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_MCS_LSB 56 -#define MACTX_USER_DESC_PER_USER_MCS_MSB 60 -#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x1f00000000000000 - -#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_DCM_LSB 61 -#define MACTX_USER_DESC_PER_USER_DCM_MSB 61 -#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x2000000000000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x0000000000000000 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 62 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 63 -#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xc000000000000000 - -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0 -#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x0000000000000001 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 1 -#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x0000000000000002 - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_LSB 2 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MSB 3 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF1_MASK 0x000000000000000c - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_LSB 4 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MSB 5 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF2_MASK 0x0000000000000030 - -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_LSB 6 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MSB 7 -#define MACTX_USER_DESC_PER_USER_QAM_DIFF3_MASK 0x00000000000000c0 - -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9 -#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x0000000000000300 - -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_LSB 10 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MSB 11 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC2X_MASK 0x0000000000000c00 - -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_LSB 12 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MSB 12 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC2X_MASK 0x0000000000001000 - -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_LSB 13 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MSB 14 -#define MACTX_USER_DESC_PER_USER_CW_LEN_2X_MASK 0x0000000000006000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 15 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15 -#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x0000000000008000 - -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16 -#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x0000000000010000 - -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_LSB 17 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MSB 18 -#define MACTX_USER_DESC_PER_USER_A_FACTOR_LDPC1X_MASK 0x0000000000060000 - -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_LSB 19 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MSB 19 -#define MACTX_USER_DESC_PER_USER_EXTRA_SYM_LDPC1X_MASK 0x0000000000080000 - -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_LSB 20 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MSB 21 -#define MACTX_USER_DESC_PER_USER_CW_LEN_1X_MASK 0x0000000000300000 - -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_LSB 22 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MSB 22 -#define MACTX_USER_DESC_PER_USER_LDPC1X_USED_MASK 0x0000000000400000 - -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_LSB 23 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MSB 23 -#define MACTX_USER_DESC_PER_USER_LDPC2X_USED_MASK 0x0000000000800000 - -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24 -#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x0000000001000000 - -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25 -#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x0000000002000000 - -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_LSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_2X_CODEWORD_MASK 0x0000000004000000 - -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 27 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0x00000000f8000000 - -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 32 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 47 -#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 48 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 63 -#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff000000000000 - -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_LSB 0 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MSB 26 -#define MACTX_USER_DESC_PER_USER_LDPC_NUM_AVBITS_MASK 0x0000000007ffffff - -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_LSB 27 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MSB 31 -#define MACTX_USER_DESC_PER_USER_RESERVED_4A_MASK 0x00000000f8000000 - -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_LSB 32 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MSB 47 -#define MACTX_USER_DESC_PER_USER_NUM_CW_1X_MASK 0x0000ffff00000000 - -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_OFFSET 0x0000000000000010 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_LSB 48 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MSB 63 -#define MACTX_USER_DESC_PER_USER_NUM_CW_2X_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_a.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_a.h deleted file mode 100644 index 6dec145785d6..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_a.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_A_H_ -#define _MACTX_VHT_SIG_A_H_ - -#include "vht_sig_a_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_A 1 - -struct mactx_vht_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_a_info mactx_vht_sig_a_info_details; -#else - struct vht_sig_a_info mactx_vht_sig_a_info_details; -#endif -}; - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu160.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu160.h deleted file mode 100644 index b66278da930b..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu160.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU160_H_ -#define _MACTX_VHT_SIG_B_MU160_H_ - -#include "vht_sig_b_mu160_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU160 4 - -struct mactx_vht_sig_b_mu160 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; -#else - struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 50 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 51 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 54 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 61 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 63 -#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu20.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu20.h deleted file mode 100644 index 95feca30eaa3..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu20.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU20_H_ -#define _MACTX_VHT_SIG_B_MU20_H_ - -#include "vht_sig_b_mu20_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU20 1 - -struct mactx_vht_sig_b_mu20 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; - uint32_t tlv64_padding : 32; -#else - struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x000000000000ffff - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x00000000000f0000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x000000001c000000 - -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_LSB 32 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MSB 63 -#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu40.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu40.h deleted file mode 100644 index c770db089203..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu40.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU40_H_ -#define _MACTX_VHT_SIG_B_MU40_H_ - -#include "vht_sig_b_mu40_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU40 1 - -struct mactx_vht_sig_b_mu40 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; -#else - struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x00000000001e0000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x0000000018000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 32 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 48 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff00000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 49 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 52 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e000000000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 53 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 58 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 - -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 59 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf800000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu80.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu80.h deleted file mode 100644 index 9e39d240b618..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_mu80.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_MU80_H_ -#define _MACTX_VHT_SIG_B_MU80_H_ - -#include "vht_sig_b_mu80_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU80 2 - -struct mactx_vht_sig_b_mu80 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; -#else - struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 50 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 51 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 63 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 50 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 51 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 63 -#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su160.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su160.h deleted file mode 100644 index 01bc54e5ab89..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su160.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU160_H_ -#define _MACTX_VHT_SIG_B_SU160_H_ - -#include "vht_sig_b_su160_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU160 4 - -struct mactx_vht_sig_b_su160 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; -#else - struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x0000000000000010 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 52 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 53 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 54 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 61 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 62 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000000000000018 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 63 -#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su20.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su20.h deleted file mode 100644 index c297cc0785e3..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su20.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU20_H_ -#define _MACTX_VHT_SIG_B_SU20_H_ - -#include "vht_sig_b_su20_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1 - -struct mactx_vht_sig_b_su20 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; - uint32_t tlv64_padding : 32; -#else - struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x00000000000e0000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x000000007c000000 - -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB 32 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB 63 -#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su40.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su40.h deleted file mode 100644 index 002d72c430ca..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su40.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU40_H_ -#define _MACTX_VHT_SIG_B_SU40_H_ - -#include "vht_sig_b_su40_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU40 1 - -struct mactx_vht_sig_b_su40 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; -#else - struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000180000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x0000000078000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 32 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 50 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff00000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 51 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 52 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x0018000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 53 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 58 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 59 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 62 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x7800000000000000 - -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 63 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 63 -#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su80.h b/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su80.h deleted file mode 100644 index b15646f03f4a..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mactx_vht_sig_b_su80.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MACTX_VHT_SIG_B_SU80_H_ -#define _MACTX_VHT_SIG_B_SU80_H_ - -#include "vht_sig_b_su80_info.h" -#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4 - -#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU80 2 - -struct mactx_vht_sig_b_su80 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; -#else - struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; -#endif -}; - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 52 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 61 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 62 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 52 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 61 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 62 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 - -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 -#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mlo_sta_id_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/mlo_sta_id_details.h deleted file mode 100644 index 952056890206..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mlo_sta_id_details.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MLO_STA_ID_DETAILS_H_ -#define _MLO_STA_ID_DETAILS_H_ - -#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1 - -struct mlo_sta_id_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t nstr_mlo_sta_id : 10, - block_self_ml_sync : 1, - block_partner_ml_sync : 1, - nstr_mlo_sta_id_valid : 1, - reserved_0a : 3; -#else - uint16_t reserved_0a : 3, - nstr_mlo_sta_id_valid : 1, - block_partner_ml_sync : 1, - block_self_ml_sync : 1, - nstr_mlo_sta_id : 10; -#endif -}; - -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff - -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10 -#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400 - -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 - -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12 -#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 - -#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000 -#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13 -#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15 -#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mon_buffer_addr.h b/drivers/staging/fw-api/hw/wcn8750/v1/mon_buffer_addr.h deleted file mode 100644 index 8cb6f5fd57b9..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mon_buffer_addr.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_BUFFER_ADDR_H_ -#define _MON_BUFFER_ADDR_H_ - -#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4 - -#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2 - -struct mon_buffer_addr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t dma_length : 12, - reserved_2a : 4, - msdu_continuation : 1, - truncated : 1, - reserved_2b : 14; - uint32_t tlv64_padding : 32; -#else - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t reserved_2b : 14, - truncated : 1, - msdu_continuation : 1, - reserved_2a : 4, - dma_length : 12; - uint32_t tlv64_padding : 32; -#endif -}; - -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff - -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63 -#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000 - -#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 -#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 -#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff - -#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 -#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 -#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000 - -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 -#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000 - -#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_TRUNCATED_LSB 17 -#define MON_BUFFER_ADDR_TRUNCATED_MSB 17 -#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000 - -#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 -#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 -#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000 - -#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008 -#define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32 -#define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63 -#define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mon_destination_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/mon_destination_ring.h deleted file mode 100644 index 1f373b585fd5..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mon_destination_ring.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_DESTINATION_RING_H_ -#define _MON_DESTINATION_RING_H_ - -#define NUM_OF_DWORDS_MON_DESTINATION_RING 4 - -struct mon_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t stat_buf_virt_addr_31_0 : 32; - uint32_t stat_buf_virt_addr_63_32 : 32; - uint32_t ppdu_id : 32; - uint32_t end_offset : 12, - reserved_3a : 2, - link_info : 2, - end_reason : 2, - initiator : 1, - empty_descriptor : 1, - pkt_buffer_cnt : 8, - looping_count : 4; -#else - uint32_t stat_buf_virt_addr_31_0 : 32; - uint32_t stat_buf_virt_addr_63_32 : 32; - uint32_t ppdu_id : 32; - uint32_t looping_count : 4, - pkt_buffer_cnt : 8, - empty_descriptor : 1, - initiator : 1, - end_reason : 2, - link_info : 2, - reserved_3a : 2, - end_offset : 12; -#endif -}; - -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff - -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31 -#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff - -#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008 -#define MON_DESTINATION_RING_PPDU_ID_LSB 0 -#define MON_DESTINATION_RING_PPDU_ID_MSB 31 -#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff - -#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c -#define MON_DESTINATION_RING_END_OFFSET_LSB 0 -#define MON_DESTINATION_RING_END_OFFSET_MSB 11 -#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff - -#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c -#define MON_DESTINATION_RING_RESERVED_3A_LSB 12 -#define MON_DESTINATION_RING_RESERVED_3A_MSB 13 -#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x00003000 - -#define MON_DESTINATION_RING_LINK_INFO_OFFSET 0x0000000c -#define MON_DESTINATION_RING_LINK_INFO_LSB 14 -#define MON_DESTINATION_RING_LINK_INFO_MSB 15 -#define MON_DESTINATION_RING_LINK_INFO_MASK 0x0000c000 - -#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c -#define MON_DESTINATION_RING_END_REASON_LSB 16 -#define MON_DESTINATION_RING_END_REASON_MSB 17 -#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000 - -#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c -#define MON_DESTINATION_RING_INITIATOR_LSB 18 -#define MON_DESTINATION_RING_INITIATOR_MSB 18 -#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000 - -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19 -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19 -#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000 - -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_OFFSET 0x0000000c -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_LSB 20 -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MSB 27 -#define MON_DESTINATION_RING_PKT_BUFFER_CNT_MASK 0x0ff00000 - -#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c -#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28 -#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31 -#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mon_drop.h b/drivers/staging/fw-api/hw/wcn8750/v1/mon_drop.h deleted file mode 100644 index d1135ecd0dc2..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mon_drop.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_DROP_H_ -#define _MON_DROP_H_ - -#define NUM_OF_DWORDS_MON_DROP 2 - -#define NUM_OF_QWORDS_MON_DROP 1 - -struct mon_drop { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ppdu_id : 32; - uint32_t ppdu_drop_cnt : 10, - mpdu_drop_cnt : 10, - tlv_drop_cnt : 10, - end_of_ppdu_seen : 1, - reserved_1a : 1; -#else - uint32_t ppdu_id : 32; - uint32_t reserved_1a : 1, - end_of_ppdu_seen : 1, - tlv_drop_cnt : 10, - mpdu_drop_cnt : 10, - ppdu_drop_cnt : 10; -#endif -}; - -#define MON_DROP_PPDU_ID_OFFSET 0x0000000000000000 -#define MON_DROP_PPDU_ID_LSB 0 -#define MON_DROP_PPDU_ID_MSB 31 -#define MON_DROP_PPDU_ID_MASK 0x00000000ffffffff - -#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_PPDU_DROP_CNT_LSB 32 -#define MON_DROP_PPDU_DROP_CNT_MSB 41 -#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff00000000 - -#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_MPDU_DROP_CNT_LSB 42 -#define MON_DROP_MPDU_DROP_CNT_MSB 51 -#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc0000000000 - -#define MON_DROP_TLV_DROP_CNT_OFFSET 0x0000000000000000 -#define MON_DROP_TLV_DROP_CNT_LSB 52 -#define MON_DROP_TLV_DROP_CNT_MSB 61 -#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff0000000000000 - -#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x0000000000000000 -#define MON_DROP_END_OF_PPDU_SEEN_LSB 62 -#define MON_DROP_END_OF_PPDU_SEEN_MSB 62 -#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x4000000000000000 - -#define MON_DROP_RESERVED_1A_OFFSET 0x0000000000000000 -#define MON_DROP_RESERVED_1A_LSB 63 -#define MON_DROP_RESERVED_1A_MSB 63 -#define MON_DROP_RESERVED_1A_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/mon_ingress_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/mon_ingress_ring.h deleted file mode 100644 index 76f4e80417e0..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/mon_ingress_ring.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _MON_INGRESS_RING_H_ -#define _MON_INGRESS_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_MON_INGRESS_RING 4 - -struct mon_ingress_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buffer_addr_info_details; - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; -#else - struct buffer_addr_info buffer_addr_info_details; - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; -#endif -}; - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff - -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 -#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/msmhwiobase.h b/drivers/staging/fw-api/hw/wcn8750/v1/msmhwiobase.h deleted file mode 100644 index 613be3cf2136..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/msmhwiobase.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef MSMHWIOBASE_H -#define MSMHWIOBASE_H - -#define HOST_WCSS_WCSS_BASE 0x0 -#define HOST_WCSS_WCSS_BASE_SIZE 0x00d00000 -#define HOST_WCSS_WCSS_BASE_PHYS 0x00000000 - -#define HOST_HZ_AUXSSAUXSS_SWI_BASE 0x1900000 -#define HOST_HZ_AUXSSAUXSS_SWI_BASE_SIZE 0x00007000 -#define HOST_HZ_AUXSSAUXSS_SWI_BASE_PHYS 0x01900000 - -#define HOST_WLAN_HZ_ZEALIS_AON_BASE 0x1907000 -#define HOST_WLAN_HZ_ZEALIS_AON_BASE_SIZE 0x00019000 -#define HOST_WLAN_HZ_ZEALIS_AON_BASE_PHYS 0x01907000 - -#define HOST_TLMM_BASE 0x1a00000 -#define HOST_TLMM_BASE_SIZE 0x00100000 -#define HOST_TLMM_BASE_PHYS 0x01a00000 - -#define HOST_CORE_TOP_CSR_BASE 0x1b00000 -#define HOST_CORE_TOP_CSR_BASE_SIZE 0x0003f000 -#define HOST_CORE_TOP_CSR_BASE_PHYS 0x01b00000 - -#define QUPV3_QUPV3_ID_3_BASE 0x1b40000 -#define QUPV3_QUPV3_ID_3_BASE_SIZE 0x00040000 -#define QUPV3_QUPV3_ID_3_BASE_PHYS 0x01b40000 - -#define HOST_SOC_WFSS_CE_REG_BASE 0x1b80000 -#define HOST_SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000 -#define HOST_SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000 - -#define HOST_WL_TLMM_BASE 0x1bc0000 -#define HOST_WL_TLMM_BASE_SIZE 0x00020000 -#define HOST_WL_TLMM_BASE_PHYS 0x01bc0000 - -#define HOST_TSENS_SROT_BASE 0x1bf0000 -#define HOST_TSENS_SROT_BASE_SIZE 0x00001000 -#define HOST_TSENS_SROT_BASE_PHYS 0x01bf0000 - -#define HOST_TSENS_TM_BASE 0x1bf1000 -#define HOST_TSENS_TM_BASE_SIZE 0x00001000 -#define HOST_TSENS_TM_BASE_PHYS 0x01bf1000 - -#define HOST_QDSS_LITE_QDSS_LITE_APB_BASE 0x1c00000 -#define HOST_QDSS_LITE_QDSS_LITE_APB_BASE_SIZE 0x00080000 -#define HOST_QDSS_LITE_QDSS_LITE_APB_BASE_PHYS 0x01c00000 - -#define HOST_SOC_DBG_WRAPPER_TOPHOST__BASE 0x1c80000 -#define HOST_SOC_DBG_WRAPPER_TOPHOST__BASE_SIZE 0x0007fffd -#define HOST_SOC_DBG_WRAPPER_TOPHOST__BASE_PHYS 0x01c80000 - -#define HOST_QDSS_APB_WCSS_DBG_DEC_SOC_APB_WCSSDBG_BASE 0x1d00000 -#define HOST_QDSS_APB_WCSS_DBG_DEC_SOC_APB_WCSSDBG_BASE_SIZE 0x00100000 -#define HOST_QDSS_APB_WCSS_DBG_DEC_SOC_APB_WCSSDBG_BASE_PHYS 0x01d00000 - -#define HOST_PCIE_PCIE_TOP_WRAPPER_BASE 0x1e00000 -#define HOST_PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000 -#define HOST_PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000 - -#define HOST_SECURITY_CONTROL_WLAN_BASE 0x1e20000 -#define HOST_SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000 -#define HOST_SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000 - -#define HOST_EDPD_CAL_ACC_BASE 0x1e28000 -#define HOST_EDPD_CAL_ACC_BASE_SIZE 0x00003000 -#define HOST_EDPD_CAL_ACC_BASE_PHYS 0x01e28000 - -#define HOST_CPR_CX_CPR3_BASE 0x1e30000 -#define HOST_CPR_CX_CPR3_BASE_SIZE 0x00004000 -#define HOST_CPR_CX_CPR3_BASE_PHYS 0x01e30000 - -#define HOST_CPR_MX_CPR3_BASE 0x1e34000 -#define HOST_CPR_MX_CPR3_BASE_SIZE 0x00004000 -#define HOST_CPR_MX_CPR3_BASE_PHYS 0x01e34000 - -#define HOST_WCSS_IE_BASE 0x1e38000 -#define HOST_WCSS_IE_BASE_SIZE 0x00001000 -#define HOST_WCSS_IE_BASE_PHYS 0x01e38000 - -#define HOST_GCC_GCC_BASE 0x1e40000 -#define HOST_GCC_GCC_BASE_SIZE 0x0000048c -#define HOST_GCC_GCC_BASE_PHYS 0x01e40000 - -#define HOST_PCNOC_0_BUS_TIMEOUT_BASE 0x1e60000 -#define HOST_PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000 -#define HOST_PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000 - -#define HOST_PCNOC_1_BUS_TIMEOUT_BASE 0x1e61000 -#define HOST_PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000 -#define HOST_PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000 - -#define HOST_PCNOC_2_BUS_TIMEOUT_BASE 0x1e62000 -#define HOST_PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000 -#define HOST_PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000 - -#define HOST_PCNOC_3_BUS_TIMEOUT_BASE 0x1e63000 -#define HOST_PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000 -#define HOST_PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000 - -#define HOST_PCNOC_4_BUS_TIMEOUT_BASE 0x1e64000 -#define HOST_PCNOC_4_BUS_TIMEOUT_BASE_SIZE 0x00001000 -#define HOST_PCNOC_4_BUS_TIMEOUT_BASE_PHYS 0x01e64000 - -#define HOST_PCNOC_5_BUS_TIMEOUT_BASE 0x1e65000 -#define HOST_PCNOC_5_BUS_TIMEOUT_BASE_SIZE 0x00001000 -#define HOST_PCNOC_5_BUS_TIMEOUT_BASE_PHYS 0x01e65000 - -#define HOST_RRI_PREFETCH_REG_BASE 0x1e70000 -#define HOST_RRI_PREFETCH_REG_BASE_SIZE 0x00010000 -#define HOST_RRI_PREFETCH_REG_BASE_PHYS 0x01e70000 - -#define HOST_SYSTEM_NOC_BASE 0x1e80000 -#define HOST_SYSTEM_NOC_BASE_SIZE 0x0000a000 -#define HOST_SYSTEM_NOC_BASE_PHYS 0x01e80000 - -#define HOST_PC_NOC_BASE 0x1f00000 -#define HOST_PC_NOC_BASE_SIZE 0x00003880 -#define HOST_PC_NOC_BASE_PHYS 0x01f00000 - -#define HOST_WLAON_WL_AON_REG_BASE 0x1f80000 -#define HOST_WLAON_WL_AON_REG_BASE_SIZE 0x000007f0 -#define HOST_WLAON_WL_AON_REG_BASE_PHYS 0x01f80000 - -#define HOST_SYSPM_SYSPM_REG_BASE 0x1f82000 -#define HOST_SYSPM_SYSPM_REG_BASE_SIZE 0x00001000 -#define HOST_SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000 - -#define HOST_PMU_WLAN_PMU_TOP_BASE 0x1f88000 -#define HOST_PMU_WLAN_PMU_TOP_BASE_SIZE 0x00000400 -#define HOST_PMU_WLAN_PMU_TOP_BASE_PHYS 0x01f88000 - -#define HOST_PMU_NOC_BASE 0x1f8a000 -#define HOST_PMU_NOC_BASE_SIZE 0x00000180 -#define HOST_PMU_NOC_BASE_PHYS 0x01f8a000 - -#define HOST_BOOT_ROM 0x1200000 -#define HOST_BOOT_ROM_SIZE 0x00004800 -#define HOST_BOOT_ROM_PHYS 0x01200000 - -#define HOST_SYSTEM_IRAM 0x1400000 -#define HOST_SYSTEM_IRAM_SIZE 0x00020000 -#define HOST_SYSTEM_IRAM_PHYS 0x01400000 - -#define HOST_ZEALIS_SRAM 0x28c0000 -#define HOST_ZEALIS_SRAM_SIZE 0x00040000 -#define HOST_ZEALIS_SRAM_PHYS 0x028c0000 - -#define HOST_PCIE_ATU_REGION 0x4000000 -#define HOST_PCIE_ATU_REGION_SIZE 0x40000000 -#define HOST_PCIE_ATU_REGION_PHYS 0x04000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/msmhwioreg.h b/drivers/staging/fw-api/hw/wcn8750/v1/msmhwioreg.h deleted file mode 100644 index 2d9c5ac5a7db..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/msmhwioreg.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef __MSMHWIOREG_H__ -#define __MSMHWIOREG_H__ - -#include "msmhwiobase.h" - -#define HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00001000) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x408) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00000000) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ - in_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x4) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ - in_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00003000) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ - in_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x4) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ - in_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x400) -#define HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00002000) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ - in_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x4) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ - in_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ - in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ - out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ - out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x400) -#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x58) - - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/no_ack_report.h b/drivers/staging/fw-api/hw/wcn8750/v1/no_ack_report.h deleted file mode 100644 index 5f9660801de6..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/no_ack_report.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _NO_ACK_REPORT_H_ -#define _NO_ACK_REPORT_H_ - -#define NUM_OF_DWORDS_NO_ACK_REPORT 4 - -struct no_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t no_ack_transmit_reason : 4, - macrx_abort_reason : 4, - phyrx_abort_reason : 8, - frame_control : 16; - uint32_t rx_ppdu_duration : 24, - sr_ppdu_during_obss : 1, - selfgen_response_reason_to_sr_ppdu : 4, - reserved_1 : 3; - uint32_t pre_bt_broadcast_status_details : 12, - first_bt_broadcast_status_details : 12, - reserved_2 : 8; - uint32_t second_bt_broadcast_status_details : 12, - reserved_3 : 20; -#else - uint32_t frame_control : 16, - phyrx_abort_reason : 8, - macrx_abort_reason : 4, - no_ack_transmit_reason : 4; - uint32_t reserved_1 : 3, - selfgen_response_reason_to_sr_ppdu : 4, - sr_ppdu_during_obss : 1, - rx_ppdu_duration : 24; - uint32_t reserved_2 : 8, - first_bt_broadcast_status_details : 12, - pre_bt_broadcast_status_details : 12; - uint32_t reserved_3 : 20, - second_bt_broadcast_status_details : 12; -#endif -}; - -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3 -#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f - -#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7 -#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0 - -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15 -#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00 - -#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 -#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16 -#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31 -#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 - -#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004 -#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0 -#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23 -#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff - -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24 -#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000 - -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28 -#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000 - -#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004 -#define NO_ACK_REPORT_RESERVED_1_LSB 29 -#define NO_ACK_REPORT_RESERVED_1_MSB 31 -#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000 - -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff - -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 -#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000 - -#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008 -#define NO_ACK_REPORT_RESERVED_2_LSB 24 -#define NO_ACK_REPORT_RESERVED_2_MSB 31 -#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000 - -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff - -#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c -#define NO_ACK_REPORT_RESERVED_3_LSB 12 -#define NO_ACK_REPORT_RESERVED_3_MSB 31 -#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/ofdma_trigger_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/ofdma_trigger_details.h deleted file mode 100644 index 8ad80d76b0ee..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/ofdma_trigger_details.h +++ /dev/null @@ -1,944 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _OFDMA_TRIGGER_DETAILS_H_ -#define _OFDMA_TRIGGER_DETAILS_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 26 - -#define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 13 - -struct ofdma_trigger_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ax_trigger_source : 1, - rx_trigger_frame_user_source : 2, - received_bandwidth : 3, - txop_duration_all_ones : 1, - eht_trigger_response : 1, - pre_rssi_comb : 8, - rssi_comb : 8, - rxpcu_pcie_l0_req_duration : 8; - uint32_t he_trigger_ul_ppdu_length : 5, - he_trigger_ru_allocation : 8, - he_trigger_dl_tx_power : 5, - he_trigger_ul_target_rssi : 5, - he_trigger_ul_mcs : 2, - he_trigger_reserved : 1, - bss_color : 6; - uint32_t trigger_type : 4, - lsig_response_length : 12, - cascade_indication : 1, - carrier_sense : 1, - bandwidth : 2, - cp_ltf_size : 2, - mu_mimo_ltf_mode : 1, - number_of_ltfs : 3, - stbc : 1, - ldpc_extra_symbol : 1, - ap_tx_power_lsb_part : 4; - uint32_t ap_tx_power_msb_part : 2, - packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - spatial_reuse : 16, - doppler : 1, - he_siga_reserved : 9, - reserved_3b : 1; - uint32_t aid12 : 12, - ru_allocation : 9, - mcs : 4, - dcm : 1, - start_spatial_stream : 3, - number_of_spatial_stream : 3; - uint32_t target_rssi : 7, - coding_type : 1, - mpdu_mu_spacing_factor : 2, - tid_aggregation_limit : 3, - reserved_5b : 1, - prefered_ac : 2, - bar_control_ack_policy : 1, - bar_control_multi_tid : 1, - bar_control_compressed_bitmap : 1, - bar_control_reserved : 9, - bar_control_tid_info : 4; - uint32_t nr0_per_tid_info_reserved : 12, - nr0_per_tid_info_tid_value : 4, - nr0_start_seq_ctrl_frag_number : 4, - nr0_start_seq_ctrl_start_seq_number : 12; - uint32_t nr1_per_tid_info_reserved : 12, - nr1_per_tid_info_tid_value : 4, - nr1_start_seq_ctrl_frag_number : 4, - nr1_start_seq_ctrl_start_seq_number : 12; - uint32_t nr2_per_tid_info_reserved : 12, - nr2_per_tid_info_tid_value : 4, - nr2_start_seq_ctrl_frag_number : 4, - nr2_start_seq_ctrl_start_seq_number : 12; - uint32_t nr3_per_tid_info_reserved : 12, - nr3_per_tid_info_tid_value : 4, - nr3_start_seq_ctrl_frag_number : 4, - nr3_start_seq_ctrl_start_seq_number : 12; - uint32_t nr4_per_tid_info_reserved : 12, - nr4_per_tid_info_tid_value : 4, - nr4_start_seq_ctrl_frag_number : 4, - nr4_start_seq_ctrl_start_seq_number : 12; - uint32_t nr5_per_tid_info_reserved : 12, - nr5_per_tid_info_tid_value : 4, - nr5_start_seq_ctrl_frag_number : 4, - nr5_start_seq_ctrl_start_seq_number : 12; - uint32_t nr6_per_tid_info_reserved : 12, - nr6_per_tid_info_tid_value : 4, - nr6_start_seq_ctrl_frag_number : 4, - nr6_start_seq_ctrl_start_seq_number : 12; - uint32_t nr7_per_tid_info_reserved : 12, - nr7_per_tid_info_tid_value : 4, - nr7_start_seq_ctrl_frag_number : 4, - nr7_start_seq_ctrl_start_seq_number : 12; - uint32_t fb_segment_retransmission_bitmap : 8, - reserved_14a : 2, - u_sig_puncture_pattern_encoding : 6, - dot11be_puncture_bitmap : 16; - uint32_t rx_chain_mask : 8, - rx_duration_field : 16, - scrambler_seed : 7, - rx_chain_mask_type : 1; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t normalized_pre_rssi_comb : 8, - normalized_rssi_comb : 8; - uint32_t sw_peer_id : 16, - response_tx_duration : 16; - uint32_t __reserved_g_0005_trigger_subtype : 4, - tbr_trigger_common_info_79_68 : 12, - tbr_trigger_sound_reserved_20_12 : 9, - i2r_rep : 3, - tbr_trigger_sound_reserved_25_24 : 2, - reserved_18a : 1, - qos_null_only_response_tx : 1; - uint32_t tbr_trigger_sound_sac : 16, - reserved_19a : 8, - u_sig_reserved2 : 5, - reserved_19b : 3; - uint32_t eht_special_aid12 : 12, - phy_version : 3, - bandwidth_ext : 2, - eht_spatial_reuse : 8, - u_sig_reserved1 : 7; - uint32_t eht_trigger_special_user_info_71_40 : 32; - uint32_t __reserved_g_0086 : 1, - __reserved_g_0074 : 4, - blackout_details_en : 1, - uhr_trig_response : 1, - mcs_ext : 1, - dso_primary20_index_select : 4, - dso_icf_reception : 1, - dru_spreading_bw : 2, - dru_indication_per_80mhz : 4, - coding_type_ext : 1, - pad_duration : 5, - ects_as_tb_ppdu : 1, - reserved_22a : 6; - uint32_t dso_cca_puncture_pattern : 16, - dso_freq_subband_channel_bonding_mask : 16; - uint32_t __reserved_g_0034 : 1, - enable_steering : 1, - q2q_mba : 1, - reserved_24a : 29; - uint32_t reserved_25a : 32; -#else - uint32_t rxpcu_pcie_l0_req_duration : 8, - rssi_comb : 8, - pre_rssi_comb : 8, - eht_trigger_response : 1, - txop_duration_all_ones : 1, - received_bandwidth : 3, - rx_trigger_frame_user_source : 2, - ax_trigger_source : 1; - uint32_t bss_color : 6, - he_trigger_reserved : 1, - he_trigger_ul_mcs : 2, - he_trigger_ul_target_rssi : 5, - he_trigger_dl_tx_power : 5, - he_trigger_ru_allocation : 8, - he_trigger_ul_ppdu_length : 5; - uint32_t ap_tx_power_lsb_part : 4, - ldpc_extra_symbol : 1, - stbc : 1, - number_of_ltfs : 3, - mu_mimo_ltf_mode : 1, - cp_ltf_size : 2, - bandwidth : 2, - carrier_sense : 1, - cascade_indication : 1, - lsig_response_length : 12, - trigger_type : 4; - uint32_t reserved_3b : 1, - he_siga_reserved : 9, - doppler : 1, - spatial_reuse : 16, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2, - ap_tx_power_msb_part : 2; - uint32_t number_of_spatial_stream : 3, - start_spatial_stream : 3, - dcm : 1, - mcs : 4, - ru_allocation : 9, - aid12 : 12; - uint32_t bar_control_tid_info : 4, - bar_control_reserved : 9, - bar_control_compressed_bitmap : 1, - bar_control_multi_tid : 1, - bar_control_ack_policy : 1, - prefered_ac : 2, - reserved_5b : 1, - tid_aggregation_limit : 3, - mpdu_mu_spacing_factor : 2, - coding_type : 1, - target_rssi : 7; - uint32_t nr0_start_seq_ctrl_start_seq_number : 12, - nr0_start_seq_ctrl_frag_number : 4, - nr0_per_tid_info_tid_value : 4, - nr0_per_tid_info_reserved : 12; - uint32_t nr1_start_seq_ctrl_start_seq_number : 12, - nr1_start_seq_ctrl_frag_number : 4, - nr1_per_tid_info_tid_value : 4, - nr1_per_tid_info_reserved : 12; - uint32_t nr2_start_seq_ctrl_start_seq_number : 12, - nr2_start_seq_ctrl_frag_number : 4, - nr2_per_tid_info_tid_value : 4, - nr2_per_tid_info_reserved : 12; - uint32_t nr3_start_seq_ctrl_start_seq_number : 12, - nr3_start_seq_ctrl_frag_number : 4, - nr3_per_tid_info_tid_value : 4, - nr3_per_tid_info_reserved : 12; - uint32_t nr4_start_seq_ctrl_start_seq_number : 12, - nr4_start_seq_ctrl_frag_number : 4, - nr4_per_tid_info_tid_value : 4, - nr4_per_tid_info_reserved : 12; - uint32_t nr5_start_seq_ctrl_start_seq_number : 12, - nr5_start_seq_ctrl_frag_number : 4, - nr5_per_tid_info_tid_value : 4, - nr5_per_tid_info_reserved : 12; - uint32_t nr6_start_seq_ctrl_start_seq_number : 12, - nr6_start_seq_ctrl_frag_number : 4, - nr6_per_tid_info_tid_value : 4, - nr6_per_tid_info_reserved : 12; - uint32_t nr7_start_seq_ctrl_start_seq_number : 12, - nr7_start_seq_ctrl_frag_number : 4, - nr7_per_tid_info_tid_value : 4, - nr7_per_tid_info_reserved : 12; - uint32_t dot11be_puncture_bitmap : 16, - u_sig_puncture_pattern_encoding : 6, - reserved_14a : 2, - fb_segment_retransmission_bitmap : 8; - uint32_t rx_chain_mask_type : 1, - scrambler_seed : 7, - rx_duration_field : 16, - rx_chain_mask : 8; - uint32_t normalized_rssi_comb : 8, - normalized_pre_rssi_comb : 8; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint32_t response_tx_duration : 16, - sw_peer_id : 16; - uint32_t qos_null_only_response_tx : 1, - reserved_18a : 1, - tbr_trigger_sound_reserved_25_24 : 2, - i2r_rep : 3, - tbr_trigger_sound_reserved_20_12 : 9, - tbr_trigger_common_info_79_68 : 12, - __reserved_g_0005_trigger_subtype : 4; - uint32_t reserved_19b : 3, - u_sig_reserved2 : 5, - reserved_19a : 8, - tbr_trigger_sound_sac : 16; - uint32_t u_sig_reserved1 : 7, - eht_spatial_reuse : 8, - bandwidth_ext : 2, - phy_version : 3, - eht_special_aid12 : 12; - uint32_t eht_trigger_special_user_info_71_40 : 32; - uint32_t reserved_22a : 6, - ects_as_tb_ppdu : 1, - pad_duration : 5, - coding_type_ext : 1, - dru_indication_per_80mhz : 4, - dru_spreading_bw : 2, - dso_icf_reception : 1, - dso_primary20_index_select : 4, - mcs_ext : 1, - uhr_trig_response : 1, - blackout_details_en : 1, - __reserved_g_0074 : 4, - __reserved_g_0086 : 1; - uint32_t dso_freq_subband_channel_bonding_mask : 16, - dso_cca_puncture_pattern : 16; - uint32_t reserved_24a : 29, - q2q_mba : 1, - enable_steering : 1, - __reserved_g_0034 : 1; - uint32_t reserved_25a : 32; -#endif -}; - -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0 -#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000001 - -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2 -#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x0000000000000006 - -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5 -#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x0000000000000038 - -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6 -#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x0000000000000040 - -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x0000000000000080 - -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15 -#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x000000000000ff00 - -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23 -#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x0000000000ff0000 - -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0x00000000ff000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 32 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 36 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f00000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 37 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 44 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 45 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 49 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e00000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 50 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 54 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 55 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 56 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x0180000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 57 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 57 -#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x0200000000000000 - -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x0000000000000000 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 58 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 63 -#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc00000000000000 - -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 -#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f - -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15 -#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x000000000000fff0 - -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16 -#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x0000000000010000 - -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17 -#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x0000000000020000 - -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x00000000000c0000 - -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21 -#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x0000000000300000 - -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22 -#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x0000000000400000 - -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x0000000003800000 - -#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26 -#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26 -#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x0000000004000000 - -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27 -#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000008000000 - -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0x00000000f0000000 - -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 32 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 33 -#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x0000000300000000 - -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 34 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 35 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c00000000 - -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 36 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 36 -#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000001000000000 - -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 37 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 52 -#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe000000000 - -#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 53 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 53 -#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x0020000000000000 - -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 54 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 62 -#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc0000000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x8000000000000000 - -#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0 -#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11 -#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20 -#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x00000000001ff000 - -#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21 -#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24 -#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x0000000001e00000 - -#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25 -#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25 -#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x0000000002000000 - -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28 -#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x000000001c000000 - -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0x00000000e0000000 - -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 32 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 38 -#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f00000000 - -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 39 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 39 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x0000008000000000 - -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 40 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 41 -#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x0000030000000000 - -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 42 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 44 -#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c0000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 45 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 45 -#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x0000200000000000 - -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 46 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 47 -#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c00000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 48 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 48 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x0001000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 49 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 49 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x0002000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 50 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 50 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x0004000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 51 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 59 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff8000000000000 - -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x0000000000000010 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 60 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 63 -#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf000000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15 -#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 - -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 - -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 - -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 32 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 43 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 44 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 47 -#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 - -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 -#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 - -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7 -#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x00000000000000ff - -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9 -#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x0000000000000300 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15 -#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x000000000000fc00 - -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31 -#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0x00000000ffff0000 - -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 32 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 39 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff00000000 - -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 40 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 55 -#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff0000000000 - -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 56 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 62 -#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f00000000000000 - -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000038 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 63 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x8000000000000000 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 - -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31 -#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 - -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 -#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x0000000000000040 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 48 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff000000000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x000000000000fff0 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x0000000001ff0000 - -#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27 -#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x000000000e000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x0000000030000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30 -#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x0000000040000000 - -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31 -#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x0000000080000000 - -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 32 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 47 -#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 48 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 55 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff000000000000 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 56 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 60 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f00000000000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000000000000048 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 61 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe000000000000000 - -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11 -#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x0000000000000fff - -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14 -#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x0000000000007000 - -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16 -#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x0000000000018000 - -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24 -#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x0000000001fe0000 - -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31 -#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0x00000000fe000000 - -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x0000000000000050 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 32 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 63 -#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff00000000 - -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_LSB 5 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MSB 5 -#define OFDMA_TRIGGER_DETAILS_BLACKOUT_DETAILS_EN_MASK 0x0000000000000020 - -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_LSB 6 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MSB 6 -#define OFDMA_TRIGGER_DETAILS_UHR_TRIG_RESPONSE_MASK 0x0000000000000040 - -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_LSB 7 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MSB 7 -#define OFDMA_TRIGGER_DETAILS_MCS_EXT_MASK 0x0000000000000080 - -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_LSB 8 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MSB 11 -#define OFDMA_TRIGGER_DETAILS_DSO_PRIMARY20_INDEX_SELECT_MASK 0x0000000000000f00 - -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_LSB 12 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MSB 12 -#define OFDMA_TRIGGER_DETAILS_DSO_ICF_RECEPTION_MASK 0x0000000000001000 - -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_LSB 13 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MSB 14 -#define OFDMA_TRIGGER_DETAILS_DRU_SPREADING_BW_MASK 0x0000000000006000 - -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_LSB 15 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MSB 18 -#define OFDMA_TRIGGER_DETAILS_DRU_INDICATION_PER_80MHZ_MASK 0x0000000000078000 - -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_LSB 19 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MSB 19 -#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_EXT_MASK 0x0000000000080000 - -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_LSB 20 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MSB 24 -#define OFDMA_TRIGGER_DETAILS_PAD_DURATION_MASK 0x0000000001f00000 - -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB 25 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB 25 -#define OFDMA_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK 0x0000000002000000 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_LSB 26 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RESERVED_22A_MASK 0x00000000fc000000 - -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_LSB 32 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MSB 47 -#define OFDMA_TRIGGER_DETAILS_DSO_CCA_PUNCTURE_PATTERN_MASK 0x0000ffff00000000 - -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000058 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 48 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 63 -#define OFDMA_TRIGGER_DETAILS_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0xffff000000000000 - -#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_LSB 1 -#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_MSB 1 -#define OFDMA_TRIGGER_DETAILS_ENABLE_STEERING_MASK 0x0000000000000002 - -#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_LSB 2 -#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_MSB 2 -#define OFDMA_TRIGGER_DETAILS_Q2Q_MBA_MASK 0x0000000000000004 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_LSB 3 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MSB 31 -#define OFDMA_TRIGGER_DETAILS_RESERVED_24A_MASK 0x00000000fffffff8 - -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_OFFSET 0x0000000000000060 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_LSB 32 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MSB 63 -#define OFDMA_TRIGGER_DETAILS_RESERVED_25A_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/pcu_ppdu_setup_init.h b/drivers/staging/fw-api/hw/wcn8750/v1/pcu_ppdu_setup_init.h deleted file mode 100644 index f623a25ba4d4..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/pcu_ppdu_setup_init.h +++ /dev/null @@ -1,2316 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PCU_PPDU_SETUP_INIT_H_ -#define _PCU_PPDU_SETUP_INIT_H_ - -#include "pdg_response_rate_setting.h" -#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58 - -#define NUM_OF_QWORDS_PCU_PPDU_SETUP_INIT 29 - -struct pcu_ppdu_setup_init { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t medium_prot_type : 3, - response_type : 5, - response_info_part2_required : 1, - response_to_response : 3, - mba_user_order : 2, - expected_mba_size : 11, - required_ul_mu_resp_user_count : 6, - transmitted_bssid_check_en : 1; - uint32_t mprot_required_bw1 : 1, - mprot_required_bw20 : 1, - mprot_required_bw40 : 1, - mprot_required_bw80 : 1, - mprot_required_bw160 : 1, - mprot_required_bw240 : 1, - mprot_required_bw320 : 1, - ppdu_allowed_bw1 : 1, - ppdu_allowed_bw20 : 1, - ppdu_allowed_bw40 : 1, - ppdu_allowed_bw80 : 1, - ppdu_allowed_bw160 : 1, - ppdu_allowed_bw240 : 1, - ppdu_allowed_bw320 : 1, - set_fc_pwr_mgt : 1, - use_cts_duration_for_data_tx : 1, - update_timestamp_64 : 1, - update_timestamp_32_lower : 1, - update_timestamp_32_upper : 1, - reserved_1a : 13; - uint32_t insert_timestamp_offset_0 : 16, - insert_timestamp_offset_1 : 16; - uint32_t max_bw40_try_count : 4, - max_bw80_try_count : 4, - max_bw160_try_count : 4, - max_bw240_try_count : 4, - max_bw320_try_count : 4, - insert_wur_timestamp_offset : 6, - update_wur_timestamp : 1, - wur_embedded_bssid_present : 1, - insert_wur_fcs : 1, - q2q_trigger : 1, - reserved_3b : 2; - struct pdg_response_rate_setting response_to_response_rate_info_bw20; - struct pdg_response_rate_setting response_to_response_rate_info_bw40; - struct pdg_response_rate_setting response_to_response_rate_info_bw80; - struct pdg_response_rate_setting response_to_response_rate_info_bw160; - struct pdg_response_rate_setting response_to_response_rate_info_bw240; - struct pdg_response_rate_setting response_to_response_rate_info_bw320; - uint32_t r2r_hw_response_tx_duration : 16, - r2r_rx_duration_field : 16; - uint32_t r2r_group_id : 6, - r2r_response_frame_type : 4, - r2r_sta_partial_aid : 11, - use_address_fields_for_protection : 1, - r2r_set_required_response_time : 1, - reserved_29a : 3, - r2r_bw20_active_channel : 3, - r2r_bw40_active_channel : 3; - uint32_t r2r_bw80_active_channel : 3, - r2r_bw160_active_channel : 3, - r2r_bw240_active_channel : 3, - r2r_bw320_active_channel : 3, - r2r_bw20 : 3, - r2r_bw40 : 3, - r2r_bw80 : 3, - r2r_bw160 : 3, - r2r_bw240 : 3, - r2r_bw320 : 3, - tx_with_blackout_details : 1, - expect_rx_with_blackout_details : 1; - uint32_t mu_response_expected_bitmap_31_0 : 32; - uint32_t mu_response_expected_bitmap_36_32 : 5, - mu_expected_response_cbf_count : 6, - mu_expected_response_sta_count : 6, - transmit_includes_multidestination : 1, - insert_prev_tx_start_timing_info : 1, - insert_current_tx_start_timing_info : 1, - tx_start_transmit_time_byte_offset : 12; - uint32_t protection_frame_ad1_31_0 : 32; - uint32_t protection_frame_ad1_47_32 : 16, - protection_frame_ad2_15_0 : 16; - uint32_t protection_frame_ad2_47_16 : 32; - uint32_t dynamic_medium_prot_threshold : 24, - dynamic_medium_prot_type : 1, - reserved_54a : 7; - uint32_t protection_frame_ad3_31_0 : 32; - uint32_t protection_frame_ad3_47_32 : 16, - protection_frame_ad4_15_0 : 16; - uint32_t protection_frame_ad4_47_16 : 32; -#else - uint32_t transmitted_bssid_check_en : 1, - required_ul_mu_resp_user_count : 6, - expected_mba_size : 11, - mba_user_order : 2, - response_to_response : 3, - response_info_part2_required : 1, - response_type : 5, - medium_prot_type : 3; - uint32_t reserved_1a : 13, - update_timestamp_32_upper : 1, - update_timestamp_32_lower : 1, - update_timestamp_64 : 1, - use_cts_duration_for_data_tx : 1, - set_fc_pwr_mgt : 1, - ppdu_allowed_bw320 : 1, - ppdu_allowed_bw240 : 1, - ppdu_allowed_bw160 : 1, - ppdu_allowed_bw80 : 1, - ppdu_allowed_bw40 : 1, - ppdu_allowed_bw20 : 1, - ppdu_allowed_bw1 : 1, - mprot_required_bw320 : 1, - mprot_required_bw240 : 1, - mprot_required_bw160 : 1, - mprot_required_bw80 : 1, - mprot_required_bw40 : 1, - mprot_required_bw20 : 1, - mprot_required_bw1 : 1; - uint32_t insert_timestamp_offset_1 : 16, - insert_timestamp_offset_0 : 16; - uint32_t reserved_3b : 2, - q2q_trigger : 1, - insert_wur_fcs : 1, - wur_embedded_bssid_present : 1, - update_wur_timestamp : 1, - insert_wur_timestamp_offset : 6, - max_bw320_try_count : 4, - max_bw240_try_count : 4, - max_bw160_try_count : 4, - max_bw80_try_count : 4, - max_bw40_try_count : 4; - struct pdg_response_rate_setting response_to_response_rate_info_bw20; - struct pdg_response_rate_setting response_to_response_rate_info_bw40; - struct pdg_response_rate_setting response_to_response_rate_info_bw80; - struct pdg_response_rate_setting response_to_response_rate_info_bw160; - struct pdg_response_rate_setting response_to_response_rate_info_bw240; - struct pdg_response_rate_setting response_to_response_rate_info_bw320; - uint32_t r2r_rx_duration_field : 16, - r2r_hw_response_tx_duration : 16; - uint32_t r2r_bw40_active_channel : 3, - r2r_bw20_active_channel : 3, - reserved_29a : 3, - r2r_set_required_response_time : 1, - use_address_fields_for_protection : 1, - r2r_sta_partial_aid : 11, - r2r_response_frame_type : 4, - r2r_group_id : 6; - uint32_t expect_rx_with_blackout_details : 1, - tx_with_blackout_details : 1, - r2r_bw320 : 3, - r2r_bw240 : 3, - r2r_bw160 : 3, - r2r_bw80 : 3, - r2r_bw40 : 3, - r2r_bw20 : 3, - r2r_bw320_active_channel : 3, - r2r_bw240_active_channel : 3, - r2r_bw160_active_channel : 3, - r2r_bw80_active_channel : 3; - uint32_t mu_response_expected_bitmap_31_0 : 32; - uint32_t tx_start_transmit_time_byte_offset : 12, - insert_current_tx_start_timing_info : 1, - insert_prev_tx_start_timing_info : 1, - transmit_includes_multidestination : 1, - mu_expected_response_sta_count : 6, - mu_expected_response_cbf_count : 6, - mu_response_expected_bitmap_36_32 : 5; - uint32_t protection_frame_ad1_31_0 : 32; - uint32_t protection_frame_ad2_15_0 : 16, - protection_frame_ad1_47_32 : 16; - uint32_t protection_frame_ad2_47_16 : 32; - uint32_t reserved_54a : 7, - dynamic_medium_prot_type : 1, - dynamic_medium_prot_threshold : 24; - uint32_t protection_frame_ad3_31_0 : 32; - uint32_t protection_frame_ad4_15_0 : 16, - protection_frame_ad3_47_32 : 16; - uint32_t protection_frame_ad4_47_16 : 32; -#endif -}; - -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB 0 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB 2 -#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK 0x0000000000000007 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK 0x00000000000000f8 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0000000000000100 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK 0x0000000000000e00 - -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB 12 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB 13 -#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK 0x0000000000003000 - -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB 14 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB 24 -#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK 0x0000000001ffc000 - -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB 25 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB 30 -#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK 0x000000007e000000 - -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB 31 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB 31 -#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB 32 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB 32 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB 33 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB 33 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK 0x0000000200000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB 34 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB 34 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK 0x0000000400000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB 35 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB 35 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK 0x0000000800000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB 36 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB 36 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK 0x0000001000000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB 37 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB 37 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK 0x0000002000000000 - -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB 38 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB 38 -#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK 0x0000004000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB 39 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB 39 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB 40 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB 40 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK 0x0000010000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB 41 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB 41 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK 0x0000020000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB 42 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB 42 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB 43 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB 43 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB 44 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB 44 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB 45 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB 45 -#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB 46 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB 46 -#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB 47 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB 47 -#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB 48 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB 48 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK 0x0001000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB 49 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB 49 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK 0x0002000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB 50 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB 50 -#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK 0x0004000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET 0x0000000000000000 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK 0xfff8000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB 0 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB 15 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB 32 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB 35 -#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB 36 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB 39 -#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB 40 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB 43 -#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK 0x00000f0000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB 44 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB 47 -#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK 0x0000f00000000000 - -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB 48 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB 51 -#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK 0x000f000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB 52 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB 57 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB 58 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB 58 -#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB 59 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB 59 -#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK 0x0800000000000000 - -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB 60 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB 60 -#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK 0x1000000000000000 - -#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_LSB 61 -#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_MSB 61 -#define PCU_PPDU_SETUP_INIT_Q2Q_TRIGGER_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET 0x0000000000000008 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK 0xc000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000010 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000000000000018 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000020 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET 0x0000000000000028 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x0000000000000030 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET 0x0000000000000038 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000040 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x0000000000000050 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000058 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET 0x0000000000000060 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000000000000068 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x0000000000000070 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000078 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK 0x000000001e000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK 0x0000000020000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK 0x0007000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK 0x3800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000080 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_2A_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK 0x0000000000000070 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK 0x0000000000000080 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB 37 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK 0x000000e000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK 0x00007c0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000000000000088 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK 0x0000000000000001 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK 0x00000000f8000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK 0x03f0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000090 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK 0x1e00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB 61 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK 0x2000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB 62 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK 0x4000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET 0x0000000000000098 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK 0x8000000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK 0x00000000000000ff - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK 0x0000000000070000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB 27 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB 29 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MSB 35 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_2A_MASK 0x0000000f00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB 36 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK 0x0000007000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK 0x0000008000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB 40 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK 0x0000ff0000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK 0x00ff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff00000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB 5 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK 0x00000000000000e0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK 0x0000000000007c00 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_LSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MSB 15 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_2X_CODEWORD_MASK 0x0000000000008000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB 16 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB 23 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK 0x0000000000ff0000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB 24 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK 0x00000000ff000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK 0x0000000100000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 33 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 38 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 39 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK 0x0000200000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 46 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 50 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 52 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 53 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 54 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 55 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 56 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 58 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x00000000000000a8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK 0xf800000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB 10 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK 0x0000000000000400 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB 11 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB 13 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x0000000000003800 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB 20 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB 25 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK 0x0000000003f00000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 48 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 59 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 - -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000000000000b0 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 -#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB 0 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB 15 -#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB 16 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB 31 -#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB 32 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB 37 -#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK 0x0000003f00000000 - -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB 38 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB 41 -#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK 0x000003c000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB 42 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB 52 -#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK 0x001ffc0000000000 - -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB 53 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB 53 -#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK 0x0020000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB 54 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB 54 -#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK 0x0040000000000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB 55 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB 57 -#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK 0x0380000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB 58 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB 60 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK 0x1c00000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB 61 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB 63 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK 0xe000000000000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB 0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB 2 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK 0x0000000000000007 - -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB 3 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB 5 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK 0x0000000000000038 - -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB 6 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB 8 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK 0x00000000000001c0 - -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB 9 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB 11 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK 0x0000000000000e00 - -#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB 12 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB 14 -#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK 0x0000000000007000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB 15 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB 17 -#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK 0x0000000000038000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB 18 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB 20 -#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK 0x00000000001c0000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB 21 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB 23 -#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK 0x0000000000e00000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB 24 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB 26 -#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK 0x0000000007000000 - -#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB 27 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB 29 -#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK 0x0000000038000000 - -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_LSB 30 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MSB 30 -#define PCU_PPDU_SETUP_INIT_TX_WITH_BLACKOUT_DETAILS_MASK 0x0000000040000000 - -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_LSB 31 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MSB 31 -#define PCU_PPDU_SETUP_INIT_EXPECT_RX_WITH_BLACKOUT_DETAILS_MASK 0x0000000080000000 - -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET 0x00000000000000c0 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB 4 -#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK 0x000000000000001f - -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB 5 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB 10 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK 0x00000000000007e0 - -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB 11 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB 16 -#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK 0x000000000001f800 - -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB 17 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB 17 -#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK 0x0000000000020000 - -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB 18 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB 18 -#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK 0x0000000000040000 - -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB 19 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB 19 -#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK 0x0000000000080000 - -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB 20 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB 31 -#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK 0x00000000fff00000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET 0x00000000000000c8 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB 15 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB 16 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB 31 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET 0x00000000000000d0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB 0 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB 23 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK 0x0000000000ffffff - -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB 24 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB 24 -#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK 0x0000000001000000 - -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB 25 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB 31 -#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK 0x00000000fe000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET 0x00000000000000d8 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK 0xffffffff00000000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB 0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB 15 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK 0x000000000000ffff - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB 16 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB 31 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK 0x00000000ffff0000 - -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET 0x00000000000000e0 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB 32 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB 63 -#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/pdg_response.h b/drivers/staging/fw-api/hw/wcn8750/v1/pdg_response.h deleted file mode 100644 index d94c69ff2645..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/pdg_response.h +++ /dev/null @@ -1,510 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_RESPONSE_H_ -#define _PDG_RESPONSE_H_ - -#include "pdg_response_rate_setting.h" -#define NUM_OF_DWORDS_PDG_RESPONSE 14 - -#define NUM_OF_QWORDS_PDG_RESPONSE 7 - -struct pdg_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct pdg_response_rate_setting hw_response_rate_info; - uint32_t hw_response_tx_duration : 16, - rx_duration_field : 16; - uint32_t punctured_response_transmission : 1, - cca_subband_channel_bonding_mask : 16, - scrambler_seed_override : 2, - response_density_valid : 1, - response_density : 5, - more_data : 1, - duration_indication : 1, - blackout_details_en : 1, - cfp_protected_resp : 1, - bandwidth : 3; - uint32_t ack_id : 16, - block_ack_bitmap : 16; - uint32_t response_frame_type : 4, - ack_id_ext : 10, - ftm_en : 1, - group_id : 6, - sta_partial_aid : 11; - uint32_t ndp_ba_start_seq_ctrl : 12, - active_channel : 3, - txop_duration_all_ones : 1, - frame_length : 16; - uint32_t dso_primary20_index_select : 4, - dso_freq_subband_channel_bonding_mask : 16, - pad_duration : 5, - q2q_mba : 1, - reserved_12a : 6; - uint32_t tlv64_padding : 32; -#else - struct pdg_response_rate_setting hw_response_rate_info; - uint32_t rx_duration_field : 16, - hw_response_tx_duration : 16; - uint32_t bandwidth : 3, - cfp_protected_resp : 1, - blackout_details_en : 1, - duration_indication : 1, - more_data : 1, - response_density : 5, - response_density_valid : 1, - scrambler_seed_override : 2, - cca_subband_channel_bonding_mask : 16, - punctured_response_transmission : 1; - uint32_t block_ack_bitmap : 16, - ack_id : 16; - uint32_t sta_partial_aid : 11, - group_id : 6, - ftm_en : 1, - ack_id_ext : 10, - response_frame_type : 4; - uint32_t frame_length : 16, - txop_duration_all_ones : 1, - active_channel : 3, - ndp_ba_start_seq_ctrl : 12; - uint32_t reserved_12a : 6, - q2q_mba : 1, - pad_duration : 5, - dso_freq_subband_channel_bonding_mask : 16, - dso_primary20_index_select : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x0000000000000001 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x000000001e000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x0000000020000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x0000000040000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x0000000080000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 48 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 50 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x0007000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 58 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 59 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 61 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x3800000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 62 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 62 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MSB 3 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_2A_MASK 0x000000000000000f - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x0000000000000070 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x0000000000000080 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x000000000000ff00 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x0000000000ff0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0x00000000ff000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 36 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x0000001f00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 37 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000e000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 41 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x0000030000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 46 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00007c0000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_LSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_2X_CODEWORD_MASK 0x0000800000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 48 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 55 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000000000008 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 56 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff00000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x0000000000000001 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x0000000000002000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x00000000001c0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0x00000000f8000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 35 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 36 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 39 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 40 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 41 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 42 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x0000040000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 43 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 45 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x0000380000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 46 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 50 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 52 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 57 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f0000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000010 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 - -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 32 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 47 -#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff00000000 - -#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000000000000018 -#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 48 -#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 63 -#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff000000000000 - -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0 -#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x0000000000000001 - -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16 -#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000000000001fffe - -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18 -#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x0000000000060000 - -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19 -#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x0000000000080000 - -#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20 -#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24 -#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x0000000001f00000 - -#define PDG_RESPONSE_MORE_DATA_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_MORE_DATA_LSB 25 -#define PDG_RESPONSE_MORE_DATA_MSB 25 -#define PDG_RESPONSE_MORE_DATA_MASK 0x0000000002000000 - -#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_DURATION_INDICATION_LSB 26 -#define PDG_RESPONSE_DURATION_INDICATION_MSB 26 -#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x0000000004000000 - -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_LSB 27 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MSB 27 -#define PDG_RESPONSE_BLACKOUT_DETAILS_EN_MASK 0x0000000008000000 - -#define PDG_RESPONSE_CFP_PROTECTED_RESP_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_CFP_PROTECTED_RESP_LSB 28 -#define PDG_RESPONSE_CFP_PROTECTED_RESP_MSB 28 -#define PDG_RESPONSE_CFP_PROTECTED_RESP_MASK 0x0000000010000000 - -#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BANDWIDTH_LSB 29 -#define PDG_RESPONSE_BANDWIDTH_MSB 31 -#define PDG_RESPONSE_BANDWIDTH_MASK 0x00000000e0000000 - -#define PDG_RESPONSE_ACK_ID_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_ACK_ID_LSB 32 -#define PDG_RESPONSE_ACK_ID_MSB 47 -#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff00000000 - -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x0000000000000020 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 48 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 63 -#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff000000000000 - -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3 -#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x000000000000000f - -#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_ACK_ID_EXT_LSB 4 -#define PDG_RESPONSE_ACK_ID_EXT_MSB 13 -#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x0000000000003ff0 - -#define PDG_RESPONSE_FTM_EN_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_FTM_EN_LSB 14 -#define PDG_RESPONSE_FTM_EN_MSB 14 -#define PDG_RESPONSE_FTM_EN_MASK 0x0000000000004000 - -#define PDG_RESPONSE_GROUP_ID_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_GROUP_ID_LSB 15 -#define PDG_RESPONSE_GROUP_ID_MSB 20 -#define PDG_RESPONSE_GROUP_ID_MASK 0x00000000001f8000 - -#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21 -#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31 -#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0x00000000ffe00000 - -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 32 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 43 -#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff00000000 - -#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 44 -#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 46 -#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x0000700000000000 - -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 47 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 47 -#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x0000800000000000 - -#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000028 -#define PDG_RESPONSE_FRAME_LENGTH_LSB 48 -#define PDG_RESPONSE_FRAME_LENGTH_MSB 63 -#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff000000000000 - -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_LSB 0 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MSB 3 -#define PDG_RESPONSE_DSO_PRIMARY20_INDEX_SELECT_MASK 0x000000000000000f - -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 4 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 19 -#define PDG_RESPONSE_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x00000000000ffff0 - -#define PDG_RESPONSE_PAD_DURATION_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_PAD_DURATION_LSB 20 -#define PDG_RESPONSE_PAD_DURATION_MSB 24 -#define PDG_RESPONSE_PAD_DURATION_MASK 0x0000000001f00000 - -#define PDG_RESPONSE_Q2Q_MBA_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_Q2Q_MBA_LSB 25 -#define PDG_RESPONSE_Q2Q_MBA_MSB 25 -#define PDG_RESPONSE_Q2Q_MBA_MASK 0x0000000002000000 - -#define PDG_RESPONSE_RESERVED_12A_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_RESERVED_12A_LSB 26 -#define PDG_RESPONSE_RESERVED_12A_MSB 31 -#define PDG_RESPONSE_RESERVED_12A_MASK 0x00000000fc000000 - -#define PDG_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000030 -#define PDG_RESPONSE_TLV64_PADDING_LSB 32 -#define PDG_RESPONSE_TLV64_PADDING_MSB 63 -#define PDG_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/pdg_response_rate_setting.h b/drivers/staging/fw-api/hw/wcn8750/v1/pdg_response_rate_setting.h deleted file mode 100644 index eb123386f2bf..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/pdg_response_rate_setting.h +++ /dev/null @@ -1,409 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_RESPONSE_RATE_SETTING_H_ -#define _PDG_RESPONSE_RATE_SETTING_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7 - -struct pdg_response_rate_setting { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 1, - tx_antenna_sector_ctrl : 24, - pkt_type : 4, - smoothing : 1, - ldpc : 1, - stbc : 1; - uint32_t alt_tx_pwr : 8, - alt_min_tx_pwr : 8, - alt_nss : 3, - alt_tx_chain_mask : 8, - alt_bw : 3, - stf_ltf_3db_boost : 1, - force_extra_symbol : 1; - uint32_t reserved_2a : 4, - nss : 3, - dpd_enable : 1, - tx_pwr : 8, - min_tx_pwr : 8, - tx_chain_mask : 8; - uint32_t alt_rate_mcs : 5, - reserved_3a : 3, - sgi : 2, - rate_mcs : 5, - ldpc_2x_codeword : 1, - tx_pwr_1 : 8, - alt_tx_pwr_1 : 8; - uint32_t aggregation : 1, - dot11ax_bss_color_id : 6, - dot11ax_spatial_reuse : 4, - dot11ax_cp_ltf_size : 2, - dot11ax_dcm : 1, - dot11ax_doppler_indication : 1, - dot11ax_su_extended : 1, - dot11ax_min_packet_extension : 2, - dot11ax_pe_nss : 3, - dot11ax_pe_content : 1, - dot11ax_pe_ltf_size : 2, - dot11ax_chain_csd_en : 1, - dot11ax_pe_chain_csd_en : 1, - dot11ax_dl_ul_flag : 1, - reserved_4a : 5; - uint32_t dot11ax_ext_ru_start_index : 4, - dot11ax_ext_ru_size : 4, - eht_duplicate_mode : 2, - he_sigb_dcm : 1, - he_sigb_0_mcs : 3, - num_he_sigb_sym : 5, - required_response_time_source : 1, - reserved_5a : 6, - u_sig_puncture_pattern_encoding : 6; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t required_response_time : 12, - dot11be_params_placeholder : 4; -#else - uint32_t stbc : 1, - ldpc : 1, - smoothing : 1, - pkt_type : 4, - tx_antenna_sector_ctrl : 24, - reserved_0a : 1; - uint32_t force_extra_symbol : 1, - stf_ltf_3db_boost : 1, - alt_bw : 3, - alt_tx_chain_mask : 8, - alt_nss : 3, - alt_min_tx_pwr : 8, - alt_tx_pwr : 8; - uint32_t tx_chain_mask : 8, - min_tx_pwr : 8, - tx_pwr : 8, - dpd_enable : 1, - nss : 3, - reserved_2a : 4; - uint32_t alt_tx_pwr_1 : 8, - tx_pwr_1 : 8, - ldpc_2x_codeword : 1, - rate_mcs : 5, - sgi : 2, - reserved_3a : 3, - alt_rate_mcs : 5; - uint32_t reserved_4a : 5, - dot11ax_dl_ul_flag : 1, - dot11ax_pe_chain_csd_en : 1, - dot11ax_chain_csd_en : 1, - dot11ax_pe_ltf_size : 2, - dot11ax_pe_content : 1, - dot11ax_pe_nss : 3, - dot11ax_min_packet_extension : 2, - dot11ax_su_extended : 1, - dot11ax_doppler_indication : 1, - dot11ax_dcm : 1, - dot11ax_cp_ltf_size : 2, - dot11ax_spatial_reuse : 4, - dot11ax_bss_color_id : 6, - aggregation : 1; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_5a : 6, - required_response_time_source : 1, - num_he_sigb_sym : 5, - he_sigb_0_mcs : 3, - he_sigb_dcm : 1, - eht_duplicate_mode : 2, - dot11ax_ext_ru_size : 4, - dot11ax_ext_ru_start_index : 4; - uint32_t dot11be_params_placeholder : 4, - required_response_time : 12; - struct mlo_sta_id_details mlo_sta_id_details_rx; -#endif -}; - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001 - -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24 -#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe - -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28 -#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000 - -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29 -#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000 - -#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30 -#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30 -#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000 - -#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000 -#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31 -#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff - -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00 - -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18 -#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29 -#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000 - -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30 -#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000 - -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MSB 3 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_2A_MASK 0x0000000f - -#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4 -#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6 -#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070 - -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080 - -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00 - -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000 - -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 4 -#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000001f - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 5 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000e0 - -#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300 - -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 14 -#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00007c00 - -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_LSB 15 -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_LDPC_2X_CODEWORD_MASK 0x00008000 - -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000 - -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000 - -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0 -#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f - -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7 -#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 - -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300 - -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400 - -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13 -#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800 - -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18 -#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000 - -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 - -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25 -#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000 - -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 - -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 - -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27 -#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 - -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 -#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/pdg_tx_req.h b/drivers/staging/fw-api/hw/wcn8750/v1/pdg_tx_req.h deleted file mode 100644 index 6baf640807da..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/pdg_tx_req.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PDG_TX_REQ_H_ -#define _PDG_TX_REQ_H_ - -#define NUM_OF_DWORDS_PDG_TX_REQ 2 - -#define NUM_OF_QWORDS_PDG_TX_REQ 1 - -struct pdg_tx_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_reason : 2, - use_puncture_pattern : 2, - req_bw : 3, - puncture_pattern_number : 6, - reserved_0b : 1, - req_paprd : 1, - duration_field_boundary_valid : 1, - duration_field_boundary : 16; - uint32_t puncture_subband_mask : 16, - reserved_0c : 16; -#else - uint32_t duration_field_boundary : 16, - duration_field_boundary_valid : 1, - req_paprd : 1, - reserved_0b : 1, - puncture_pattern_number : 6, - req_bw : 3, - use_puncture_pattern : 2, - tx_reason : 2; - uint32_t reserved_0c : 16, - puncture_subband_mask : 16; -#endif -}; - -#define PDG_TX_REQ_TX_REASON_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_TX_REASON_LSB 0 -#define PDG_TX_REQ_TX_REASON_MSB 1 -#define PDG_TX_REQ_TX_REASON_MASK 0x0000000000000003 - -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3 -#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x000000000000000c - -#define PDG_TX_REQ_REQ_BW_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_REQ_BW_LSB 4 -#define PDG_TX_REQ_REQ_BW_MSB 6 -#define PDG_TX_REQ_REQ_BW_MASK 0x0000000000000070 - -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12 -#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x0000000000001f80 - -#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_RESERVED_0B_LSB 13 -#define PDG_TX_REQ_RESERVED_0B_MSB 13 -#define PDG_TX_REQ_RESERVED_0B_MASK 0x0000000000002000 - -#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_REQ_PAPRD_LSB 14 -#define PDG_TX_REQ_REQ_PAPRD_MSB 14 -#define PDG_TX_REQ_REQ_PAPRD_MASK 0x0000000000004000 - -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x0000000000008000 - -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31 -#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0x00000000ffff0000 - -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 32 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 47 -#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff00000000 - -#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x0000000000000000 -#define PDG_TX_REQ_RESERVED_0C_LSB 48 -#define PDG_TX_REQ_RESERVED_0C_MSB 63 -#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_abort_request_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_abort_request_info.h deleted file mode 100644 index 1f3bf4b817b9..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_abort_request_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_ABORT_REQUEST_INFO_H_ -#define _PHYRX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 - -struct phyrx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phyrx_abort_reason : 8, - phy_enters_nap_state : 1, - phy_enters_defer_state : 1, - gain_change_by_main : 1, - gain_change_by_bt : 1, - main_tx_indication : 1, - bt_tx_indication : 1, - concurrent_mode : 1, - reserved_0 : 1, - receive_duration : 16; -#else - uint32_t receive_duration : 16, - reserved_0 : 1, - concurrent_mode : 1, - bt_tx_indication : 1, - main_tx_indication : 1, - gain_change_by_bt : 1, - gain_change_by_main : 1, - phy_enters_defer_state : 1, - phy_enters_nap_state : 1, - phyrx_abort_reason : 8; -#endif -}; - -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7 -#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff - -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100 - -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9 -#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 - -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_LSB 10 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MSB 10 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MASK 0x00000400 - -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_LSB 11 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MSB 11 -#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MASK 0x00000800 - -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_LSB 12 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MSB 12 -#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MASK 0x00001000 - -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_LSB 13 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MSB 13 -#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MASK 0x00002000 - -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_LSB 14 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MSB 14 -#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MASK 0x00004000 - -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 15 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 -#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x00008000 - -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31 -#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_common_user_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_common_user_info.h deleted file mode 100644 index e73d1ab47ee7..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_common_user_info.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_COMMON_USER_INFO_H_ -#define _PHYRX_COMMON_USER_INFO_H_ - -#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4 - -#define NUM_OF_QWORDS_PHYRX_COMMON_USER_INFO 2 - -struct phyrx_common_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t receive_duration : 16, - reserved_0a : 16; - uint32_t u_sig_puncture_pattern_encoding : 6, - eht___reserved_g_0005_ndp : 1, - reserved_1a : 8, - obss_nav_update_enable : 1, - obss_nav_value : 16; - uint32_t eht_or_uhr_ppdu_type : 2, - bss_color_id : 6, - dl_ul_flag : 1, - txop_duration : 7, - cp_setting : 2, - ltf_size : 2, - spatial_reuse : 4, - rx_ndp : 1, - dot11bn_su_elr : 1, - reserved_2a : 6; - uint32_t eht_duplicate : 2, - eht_or_uhr_sig_cmn_field_type : 2, - doppler_indication : 1, - sta_id : 11, - puncture_bitmap : 16; -#else - uint32_t reserved_0a : 16, - receive_duration : 16; - uint32_t obss_nav_value : 16, - obss_nav_update_enable : 1, - reserved_1a : 8, - eht___reserved_g_0005_ndp : 1, - u_sig_puncture_pattern_encoding : 6; - uint32_t reserved_2a : 6, - dot11bn_su_elr : 1, - rx_ndp : 1, - spatial_reuse : 4, - ltf_size : 2, - cp_setting : 2, - txop_duration : 7, - dl_ul_flag : 1, - bss_color_id : 6, - eht_or_uhr_ppdu_type : 2; - uint32_t puncture_bitmap : 16, - sta_id : 11, - doppler_indication : 1, - eht_or_uhr_sig_cmn_field_type : 2, - eht_duplicate : 2; -#endif -}; - -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15 -#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x000000000000ffff - -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31 -#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0x00000000ffff0000 - -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 32 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 37 -#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f00000000 - -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 39 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 46 -#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0x00007f8000000000 - -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_LSB 47 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MSB 47 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MASK 0x0000800000000000 - -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_OFFSET 0x0000000000000000 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_LSB 48 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MSB 63 -#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MASK 0xffff000000000000 - -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_LSB 0 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MSB 1 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_PPDU_TYPE_MASK 0x0000000000000003 - -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7 -#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x00000000000000fc - -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8 -#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x0000000000000100 - -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15 -#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x000000000000fe00 - -#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17 -#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x0000000000030000 - -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19 -#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x00000000000c0000 - -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23 -#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x0000000000f00000 - -#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24 -#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24 -#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x0000000001000000 - -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_LSB 25 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MSB 25 -#define PHYRX_COMMON_USER_INFO_DOT11BN_SU_ELR_MASK 0x0000000002000000 - -#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB 26 -#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB 31 -#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK 0x00000000fc000000 - -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 32 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 33 -#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x0000000300000000 - -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_LSB 34 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MSB 35 -#define PHYRX_COMMON_USER_INFO_EHT_OR_UHR_SIG_CMN_FIELD_TYPE_MASK 0x0000000c00000000 - -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 36 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 36 -#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x0000001000000000 - -#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 37 -#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 47 -#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe000000000 - -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000000000008 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 48 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 63 -#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_mu_dl.h deleted file mode 100644 index da4f1691b9f7..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_mu_dl.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_MU_DL_H_ -#define _PHYRX_HE_SIG_A_MU_DL_H_ - -#include "he_sig_a_mu_dl_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_DL 1 - -struct phyrx_he_sig_a_mu_dl { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; -#else - struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_mu_ul.h deleted file mode 100644 index ff9cf72a7237..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_mu_ul.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_MU_UL_H_ -#define _PHYRX_HE_SIG_A_MU_UL_H_ - -#include "he_sig_a_mu_ul_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_UL 1 - -struct phyrx_he_sig_a_mu_ul { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; -#else - struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 - -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_su.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_su.h deleted file mode 100644 index abca58673a90..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_a_su.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_A_SU_H_ -#define _PHYRX_HE_SIG_A_SU_H_ - -#include "he_sig_a_su_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_SU 1 - -struct phyrx_he_sig_a_su { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; -#else - struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; -#endif -}; - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 - -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b1_mu.h deleted file mode 100644 index ae784469331b..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b1_mu.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B1_MU_H_ -#define _PHYRX_HE_SIG_B1_MU_H_ - -#include "he_sig_b1_mu_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1 - -struct phyrx_he_sig_b1_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#else - struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 - -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 -#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b2_mu.h deleted file mode 100644 index 6035ecffde5d..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b2_mu.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B2_MU_H_ -#define _PHYRX_HE_SIG_B2_MU_H_ - -#include "he_sig_b2_mu_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_MU 1 - -struct phyrx_he_sig_b2_mu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; -#else - struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; -#endif -}; - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 -#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b2_ofdma.h deleted file mode 100644 index 126a9559e155..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_he_sig_b2_ofdma.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_ -#define _PHYRX_HE_SIG_B2_OFDMA_H_ - -#include "he_sig_b2_ofdma_info.h" -#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2 - -#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_OFDMA 1 - -struct phyrx_he_sig_b2_ofdma { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; -#else - struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; -#endif -}; - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 - -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 -#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_ht_sig.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_ht_sig.h deleted file mode 100644 index 4dd90653d431..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_ht_sig.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_HT_SIG_H_ -#define _PHYRX_HT_SIG_H_ - -#include "ht_sig_info.h" -#define NUM_OF_DWORDS_PHYRX_HT_SIG 2 - -#define NUM_OF_QWORDS_PHYRX_HT_SIG 1 - -struct phyrx_ht_sig { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ht_sig_info phyrx_ht_sig_info_details; -#else - struct ht_sig_info phyrx_ht_sig_info_details; -#endif -}; - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 36 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 37 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 42 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 49 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_l_sig_a.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_l_sig_a.h deleted file mode 100644 index 2e70822f5d06..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_l_sig_a.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_L_SIG_A_H_ -#define _PHYRX_L_SIG_A_H_ - -#include "l_sig_a_info.h" -#define NUM_OF_DWORDS_PHYRX_L_SIG_A 2 - -#define NUM_OF_QWORDS_PHYRX_L_SIG_A 1 - -struct phyrx_l_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_a_info phyrx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_a_info phyrx_l_sig_a_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 - -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_A_TLV64_PADDING_LSB 32 -#define PHYRX_L_SIG_A_TLV64_PADDING_MSB 63 -#define PHYRX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_l_sig_b.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_l_sig_b.h deleted file mode 100644 index 461edd24dd4e..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_l_sig_b.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_L_SIG_B_H_ -#define _PHYRX_L_SIG_B_H_ - -#include "l_sig_b_info.h" -#define NUM_OF_DWORDS_PHYRX_L_SIG_B 2 - -#define NUM_OF_QWORDS_PHYRX_L_SIG_B 1 - -struct phyrx_l_sig_b { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct l_sig_b_info phyrx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#else - struct l_sig_b_info phyrx_l_sig_b_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 - -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 - -#define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 -#define PHYRX_L_SIG_B_TLV64_PADDING_LSB 32 -#define PHYRX_L_SIG_B_TLV64_PADDING_MSB 63 -#define PHYRX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_location.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_location.h deleted file mode 100644 index 15a8413e304a..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_location.h +++ /dev/null @@ -1,332 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_LOCATION_H_ -#define _PHYRX_LOCATION_H_ - -#include "rx_location_info.h" -#define NUM_OF_DWORDS_PHYRX_LOCATION 28 - -#define NUM_OF_QWORDS_PHYRX_LOCATION 14 - -struct phyrx_location { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_location_info rx_location_info_details; -#else - struct rx_location_info rx_location_info_details; -#endif -}; - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x0000000000000001 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x0000000000000002 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x00000000000000f0 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x000000000000ff00 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x0000000000ff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0x00000000ff000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 39 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 40 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff0000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 55 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000000000000000 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 56 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff00000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0x00000000ffffffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 39 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 40 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff0000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 51 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 52 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 55 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f0000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000000000008 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 56 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff00000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000000000ff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000000ff000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x0000000000000010 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x0000000000000018 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0x00000000ffffffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000000000000018 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x0000000000000020 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x00000000000000ff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x000000000000ff00 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000000000000028 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x0000000000000030 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000000000000038 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x0000000000000040 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000000000000048 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x0000000000000050 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000000000000058 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 47 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff00000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x0000000000000060 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 48 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff000000000000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x000000000000ffff - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0x00000000ffff0000 - -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 32 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 63 -#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_other_receive_info_ru_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_other_receive_info_ru_details.h deleted file mode 100644 index a6090f721e1d..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_other_receive_info_ru_details.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ -#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ - -#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4 - -#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2 - -struct phyrx_other_receive_info_ru_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_details_channel_0 : 32; - uint32_t ru_details_channel_1 : 32; - uint32_t spare : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t ru_details_channel_0 : 32; - uint32_t ru_details_channel_1 : 32; - uint32_t spare : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0x00000000ffffffff - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff00000000 - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x0000000000000008 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0x00000000ffffffff - -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000008 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_pkt_end.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_pkt_end.h deleted file mode 100644 index 1d1675edc0e1..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_pkt_end.h +++ /dev/null @@ -1,427 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_PKT_END_H_ -#define _PHYRX_PKT_END_H_ - -#include "phyrx_pkt_end_info.h" -#define NUM_OF_DWORDS_PHYRX_PKT_END 24 - -#define NUM_OF_QWORDS_PHYRX_PKT_END 12 - -struct phyrx_pkt_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct phyrx_pkt_end_info rx_pkt_end_details; -#else - struct phyrx_pkt_end_info rx_pkt_end_details; -#endif -}; - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x0000000000000002 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x0000000000000004 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x0000000000000008 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x0000000000000010 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x0000000000000020 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x00000000000000c0 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0x00000000ffff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB 44 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB 53 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK 0x003ff00000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000010 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_LSB 54 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xffc0000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000000000000058 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0x00000000ffffffff - -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000000000000058 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 32 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 63 -#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_pkt_end_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_pkt_end_info.h deleted file mode 100644 index a21edc94d24e..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_pkt_end_info.h +++ /dev/null @@ -1,450 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_PKT_END_INFO_H_ -#define _PHYRX_PKT_END_INFO_H_ - -#include "receive_rssi_info.h" -#include "rx_timing_info.h" -#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24 - -struct phyrx_pkt_end_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t __reserved_g_0001 : 1, - location_info_valid : 1, - timing_info_valid : 1, - rssi_info_valid : 1, - reserved_0a : 1, - frameless_frame_received : 1, - reserved_0b : 2, - rssi_comb : 8, - reserved_0c : 16; - struct rx_timing_info rx_timing_info_details; - struct receive_rssi_info post_rssi_info_details; - uint32_t phy_sw_status_31_0 : 32; - uint32_t phy_sw_status_63_32 : 32; -#else - uint32_t reserved_0c : 16, - rssi_comb : 8, - reserved_0b : 2, - frameless_frame_received : 1, - reserved_0a : 1, - rssi_info_valid : 1, - timing_info_valid : 1, - location_info_valid : 1, - __reserved_g_0001 : 1; - struct rx_timing_info rx_timing_info_details; - struct receive_rssi_info post_rssi_info_details; - uint32_t phy_sw_status_31_0 : 32; - uint32_t phy_sw_status_63_32 : 32; -#endif -}; - -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1 -#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002 - -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2 -#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004 - -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3 -#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008 - -#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4 -#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4 -#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010 - -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5 -#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 - -#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6 -#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7 -#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0 - -#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8 -#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15 -#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000 -#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16 -#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31 -#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000 - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_LSB 12 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MSB 21 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_SUB_USEC_TS_RX_END_MASK 0x003ff000 - -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x00000014 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_LSB 22 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MSB 31 -#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xffc00000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 - -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 -#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 - -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff - -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31 -#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_rssi_legacy.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_rssi_legacy.h deleted file mode 100644 index 820ced6212ca..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_rssi_legacy.h +++ /dev/null @@ -1,806 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_RSSI_LEGACY_H_ -#define _PHYRX_RSSI_LEGACY_H_ - -#include "receive_rssi_info.h" -#include "receive_pkt_start_info.h" -#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42 - -#define NUM_OF_QWORDS_PHYRX_RSSI_LEGACY 21 - -struct phyrx_rssi_legacy { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_pkt_start_info rx_pkt_start_details; - uint32_t sw_phy_meta_data : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 32; - struct receive_rssi_info pre_rssi_info_details; - struct receive_rssi_info preamble_rssi_info_details; - uint32_t pre_rssi_comb : 8, - rssi_comb : 8, - normalized_pre_rssi_comb : 8, - normalized_rssi_comb : 8; - uint32_t rssi_comb_ppdu : 8, - rssi_db_to_dbm_offset : 8, - rssi_for_spatial_reuse : 8, - rssi_for_trigger_resp : 8; -#else - struct receive_pkt_start_info rx_pkt_start_details; - uint32_t sw_phy_meta_data : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 32; - struct receive_rssi_info pre_rssi_info_details; - struct receive_rssi_info preamble_rssi_info_details; - uint32_t normalized_rssi_comb : 8, - normalized_pre_rssi_comb : 8, - rssi_comb : 8, - pre_rssi_comb : 8; - uint32_t rssi_for_trigger_resp : 8, - rssi_for_spatial_reuse : 8, - rssi_db_to_dbm_offset : 8, - rssi_comb_ppdu : 8; -#endif -}; - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_LSB 0 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MSB 3 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MASK 0x000000000000000f - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_LSB 4 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MSB 4 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x0000000000000010 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB 5 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB 7 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK 0x00000000000000e0 - -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB -#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB 8 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB 15 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_LSB 16 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MSB 31 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_LSB 32 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MSB 63 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_LSB 32 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MSB 39 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_LSB 40 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MSB 40 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MASK 0x0000010000000000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_LSB 41 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MSB 63 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MASK 0xfffffe0000000000 - -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x0000000000000010 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 0 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 31 -#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x0000000000000010 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 32 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 63 -#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x0000000000000018 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31 -#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0x00000000ffffffff - -#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000000000000018 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 32 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 63 -#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000020 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000028 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000030 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000038 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000040 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000048 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000050 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000058 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000060 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000068 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000070 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000078 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000080 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000088 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000090 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000098 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 -#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 - -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7 -#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x00000000000000ff - -#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x000000000000ff00 - -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23 -#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 - -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31 -#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 - -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 32 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 39 -#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff00000000 - -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 40 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 47 -#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff0000000000 - -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 48 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 55 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff000000000000 - -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000000000000a0 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 56 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 63 -#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_user_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_user_info.h deleted file mode 100644 index d3dc8b6b2414..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_user_info.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_USER_INFO_H_ -#define _PHYRX_USER_INFO_H_ - -#include "receive_user_info.h" -#define NUM_OF_DWORDS_PHYRX_USER_INFO 8 - -#define NUM_OF_QWORDS_PHYRX_USER_INFO 4 - -struct phyrx_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_user_info receive_user_info_details; -#else - struct receive_user_info receive_user_info_details; -#endif -}; - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 36 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000001f00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 37 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 38 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000006000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 1 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x0000000000000002 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB 2 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB 3 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK 0x000000000000000c - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB 4 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB 5 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK 0x0000000000000030 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB 6 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB 7 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK 0x00000000000000c0 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 62 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc000000000000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000 - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff - -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63 -#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_vht_sig_a.h b/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_vht_sig_a.h deleted file mode 100644 index e47f0e35adeb..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phyrx_vht_sig_a.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYRX_VHT_SIG_A_H_ -#define _PHYRX_VHT_SIG_A_H_ - -#include "vht_sig_a_info.h" -#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2 - -#define NUM_OF_QWORDS_PHYRX_VHT_SIG_A 1 - -struct phyrx_vht_sig_a { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct vht_sig_a_info phyrx_vht_sig_a_info_details; -#else - struct vht_sig_a_info phyrx_vht_sig_a_info_details; -#endif -}; - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 - -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 -#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phytx_abort_request_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/phytx_abort_request_info.h deleted file mode 100644 index e4800f6a2d97..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phytx_abort_request_info.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_ABORT_REQUEST_INFO_H_ -#define _PHYTX_ABORT_REQUEST_INFO_H_ - -#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1 - -struct phytx_abort_request_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t phytx_abort_reason : 8, - user_number : 6, - reserved : 2; -#else - uint16_t reserved : 2, - user_number : 6, - phytx_abort_reason : 8; -#endif -}; - -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7 -#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff - -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13 -#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00 - -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15 -#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phytx_pkt_end.h b/drivers/staging/fw-api/hw/wcn8750/v1/phytx_pkt_end.h deleted file mode 100644 index 55911ea9edb3..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phytx_pkt_end.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_PKT_END_H_ -#define _PHYTX_PKT_END_H_ - -#define NUM_OF_WORDS_PHYTX_PKT_END 28 - -#define NUM_OF_DWORDS_PHYTX_PKT_END 14 - -struct phytx_pkt_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t start_of_frame_timestamp_15_0 : 16; - uint16_t start_of_frame_timestamp_31_16 : 16; - uint16_t end_of_frame_timestamp_15_0 : 16; - uint16_t end_of_frame_timestamp_31_16 : 16; - uint16_t tx_group_delay : 12, - timing_status : 2, - phyrx_entered_nap_state : 1, - dpdtrain_done : 1; - uint16_t transmit_delay : 16; - uint16_t tpc_dbg_info_cmn_15_0 : 16; - uint16_t tpc_dbg_info_cmn_31_16 : 16; - uint16_t tpc_dbg_info_cmn_47_32 : 16; - uint16_t tpc_dbg_info_chn1_15_0 : 16; - uint16_t tpc_dbg_info_chn1_31_16 : 16; - uint16_t tpc_dbg_info_chn1_47_32 : 16; - uint16_t tpc_dbg_info_chn1_63_48 : 16; - uint16_t tpc_dbg_info_chn1_79_64 : 16; - uint16_t tpc_dbg_info_chn2_15_0 : 16; - uint16_t tpc_dbg_info_chn2_31_16 : 16; - uint16_t tpc_dbg_info_chn2_47_32 : 16; - uint16_t tpc_dbg_info_chn2_63_48 : 16; - uint16_t tpc_dbg_info_chn2_79_64 : 16; - uint16_t phytx_tx_end_sw_info_15_0 : 16; - uint16_t phytx_tx_end_sw_info_31_16 : 16; - uint16_t phytx_tx_end_sw_info_47_32 : 16; - uint16_t phytx_tx_end_sw_info_63_48 : 16; - uint16_t beamform_masked_user_bitmap_15_0 : 16; - uint16_t beamform_masked_user_bitmap_31_16 : 16; - uint16_t beamform_masked_user_bitmap_36_32 : 5, - reserved_23 : 11; - uint16_t reserved_26 : 16; - uint16_t reserved_27 : 16; -#else - uint16_t start_of_frame_timestamp_15_0 : 16; - uint16_t start_of_frame_timestamp_31_16 : 16; - uint16_t end_of_frame_timestamp_15_0 : 16; - uint16_t end_of_frame_timestamp_31_16 : 16; - uint16_t dpdtrain_done : 1, - phyrx_entered_nap_state : 1, - timing_status : 2, - tx_group_delay : 12; - uint16_t transmit_delay : 16; - uint16_t tpc_dbg_info_cmn_15_0 : 16; - uint16_t tpc_dbg_info_cmn_31_16 : 16; - uint16_t tpc_dbg_info_cmn_47_32 : 16; - uint16_t tpc_dbg_info_chn1_15_0 : 16; - uint16_t tpc_dbg_info_chn1_31_16 : 16; - uint16_t tpc_dbg_info_chn1_47_32 : 16; - uint16_t tpc_dbg_info_chn1_63_48 : 16; - uint16_t tpc_dbg_info_chn1_79_64 : 16; - uint16_t tpc_dbg_info_chn2_15_0 : 16; - uint16_t tpc_dbg_info_chn2_31_16 : 16; - uint16_t tpc_dbg_info_chn2_47_32 : 16; - uint16_t tpc_dbg_info_chn2_63_48 : 16; - uint16_t tpc_dbg_info_chn2_79_64 : 16; - uint16_t phytx_tx_end_sw_info_15_0 : 16; - uint16_t phytx_tx_end_sw_info_31_16 : 16; - uint16_t phytx_tx_end_sw_info_47_32 : 16; - uint16_t phytx_tx_end_sw_info_63_48 : 16; - uint16_t beamform_masked_user_bitmap_15_0 : 16; - uint16_t beamform_masked_user_bitmap_31_16 : 16; - uint16_t reserved_23 : 11, - beamform_masked_user_bitmap_36_32 : 5; - uint16_t reserved_26 : 16; - uint16_t reserved_27 : 16; -#endif -}; - -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000000 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000002 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 0 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 15 -#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000004 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000006 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 0 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 15 -#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TX_GROUP_DELAY_OFFSET 0x00000008 -#define PHYTX_PKT_END_TX_GROUP_DELAY_LSB 0 -#define PHYTX_PKT_END_TX_GROUP_DELAY_MSB 11 -#define PHYTX_PKT_END_TX_GROUP_DELAY_MASK 0x00000fff - -#define PHYTX_PKT_END_TIMING_STATUS_OFFSET 0x00000008 -#define PHYTX_PKT_END_TIMING_STATUS_LSB 12 -#define PHYTX_PKT_END_TIMING_STATUS_MSB 13 -#define PHYTX_PKT_END_TIMING_STATUS_MASK 0x00003000 - -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_OFFSET 0x00000008 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_LSB 14 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MSB 14 -#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MASK 0x00004000 - -#define PHYTX_PKT_END_DPDTRAIN_DONE_OFFSET 0x00000008 -#define PHYTX_PKT_END_DPDTRAIN_DONE_LSB 15 -#define PHYTX_PKT_END_DPDTRAIN_DONE_MSB 15 -#define PHYTX_PKT_END_DPDTRAIN_DONE_MASK 0x00008000 - -#define PHYTX_PKT_END_TRANSMIT_DELAY_OFFSET 0x0000000a -#define PHYTX_PKT_END_TRANSMIT_DELAY_LSB 0 -#define PHYTX_PKT_END_TRANSMIT_DELAY_MSB 15 -#define PHYTX_PKT_END_TRANSMIT_DELAY_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000c -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000e -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_OFFSET 0x00000010 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x00000012 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x00000014 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x00000016 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x00000018 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000001a -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000001c -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000001e -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x00000020 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x00000022 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x00000024 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_LSB 0 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MSB 15 -#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x00000026 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x00000028 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000002a -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff - -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000002c -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_LSB 0 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MSB 15 -#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000002e -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x00000030 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 15 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x0000ffff - -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x00000032 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 0 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 4 -#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x0000001f - -#define PHYTX_PKT_END_RESERVED_23_OFFSET 0x00000032 -#define PHYTX_PKT_END_RESERVED_23_LSB 5 -#define PHYTX_PKT_END_RESERVED_23_MSB 15 -#define PHYTX_PKT_END_RESERVED_23_MASK 0x0000ffe0 - -#define PHYTX_PKT_END_RESERVED_26_OFFSET 0x00000034 -#define PHYTX_PKT_END_RESERVED_26_LSB 0 -#define PHYTX_PKT_END_RESERVED_26_MSB 15 -#define PHYTX_PKT_END_RESERVED_26_MASK 0x0000ffff - -#define PHYTX_PKT_END_RESERVED_27_OFFSET 0x00000036 -#define PHYTX_PKT_END_RESERVED_27_LSB 0 -#define PHYTX_PKT_END_RESERVED_27_MSB 15 -#define PHYTX_PKT_END_RESERVED_27_MASK 0x0000ffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/phytx_ppdu_header_info_request.h b/drivers/staging/fw-api/hw/wcn8750/v1/phytx_ppdu_header_info_request.h deleted file mode 100644 index 7fbecae41236..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/phytx_ppdu_header_info_request.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ -#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ - -#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2 - -#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1 - -struct phytx_ppdu_header_info_request { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint16_t request_type : 5, - reserved : 11; - uint16_t tlv32_padding : 16; -#else - uint16_t reserved : 11, - request_type : 5; - uint16_t tlv32_padding : 16; -#endif -}; - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0 - -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15 -#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/receive_pkt_start_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/receive_pkt_start_info.h deleted file mode 100644 index 7f7c81449a15..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/receive_pkt_start_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_PKT_START_INFO_H_ -#define _RECEIVE_PKT_START_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_PKT_START_INFO 4 - -struct receive_pkt_start_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reception_type : 4, - rx_chain_mask_type : 1, - receive_bandwidth : 3, - rx_chain_mask : 8, - phy_ppdu_id : 16; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t preamble_time_to_rxframe : 8, - standalone_sniffer_mode : 1, - reserved_3a : 23; -#else - uint32_t phy_ppdu_id : 16, - rx_chain_mask : 8, - receive_bandwidth : 3, - rx_chain_mask_type : 1, - reception_type : 4; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t reserved_3a : 23, - standalone_sniffer_mode : 1, - preamble_time_to_rxframe : 8; -#endif -}; - -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_LSB 0 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MSB 3 -#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MASK 0x0000000f - -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_LSB 4 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MSB 4 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MASK 0x00000010 - -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_LSB 5 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MSB 7 -#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MASK 0x000000e0 - -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_LSB 8 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MSB 15 -#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MASK 0x0000ff00 - -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_OFFSET 0x00000000 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_LSB 16 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MSB 31 -#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MASK 0xffff0000 - -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff - -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff - -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_LSB 0 -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MSB 7 -#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff - -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_LSB 8 -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MSB 8 -#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MASK 0x00000100 - -#define RECEIVE_PKT_START_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVE_PKT_START_INFO_RESERVED_3A_LSB 9 -#define RECEIVE_PKT_START_INFO_RESERVED_3A_MSB 31 -#define RECEIVE_PKT_START_INFO_RESERVED_3A_MASK 0xfffffe00 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/receive_rssi_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/receive_rssi_info.h deleted file mode 100644 index 9aaa98217d99..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/receive_rssi_info.h +++ /dev/null @@ -1,465 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_RSSI_INFO_H_ -#define _RECEIVE_RSSI_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16 - -struct receive_rssi_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rssi_pri20_chain0 : 8, - rssi_ext20_chain0 : 8, - rssi_ext40_low20_chain0 : 8, - rssi_ext40_high20_chain0 : 8; - uint32_t rssi_ext80_low20_chain0 : 8, - rssi_ext80_low_high20_chain0 : 8, - rssi_ext80_high_low20_chain0 : 8, - rssi_ext80_high20_chain0 : 8; - uint32_t rssi_ext160_0_chain0 : 8, - rssi_ext160_1_chain0 : 8, - rssi_ext160_2_chain0 : 8, - rssi_ext160_3_chain0 : 8; - uint32_t rssi_ext160_4_chain0 : 8, - rssi_ext160_5_chain0 : 8, - rssi_ext160_6_chain0 : 8, - rssi_ext160_7_chain0 : 8; - uint32_t rssi_pri20_chain1 : 8, - rssi_ext20_chain1 : 8, - rssi_ext40_low20_chain1 : 8, - rssi_ext40_high20_chain1 : 8; - uint32_t rssi_ext80_low20_chain1 : 8, - rssi_ext80_low_high20_chain1 : 8, - rssi_ext80_high_low20_chain1 : 8, - rssi_ext80_high20_chain1 : 8; - uint32_t rssi_ext160_0_chain1 : 8, - rssi_ext160_1_chain1 : 8, - rssi_ext160_2_chain1 : 8, - rssi_ext160_3_chain1 : 8; - uint32_t rssi_ext160_4_chain1 : 8, - rssi_ext160_5_chain1 : 8, - rssi_ext160_6_chain1 : 8, - rssi_ext160_7_chain1 : 8; - uint32_t rssi_pri20_chain2 : 8, - rssi_ext20_chain2 : 8, - rssi_ext40_low20_chain2 : 8, - rssi_ext40_high20_chain2 : 8; - uint32_t rssi_ext80_low20_chain2 : 8, - rssi_ext80_low_high20_chain2 : 8, - rssi_ext80_high_low20_chain2 : 8, - rssi_ext80_high20_chain2 : 8; - uint32_t rssi_ext160_0_chain2 : 8, - rssi_ext160_1_chain2 : 8, - rssi_ext160_2_chain2 : 8, - rssi_ext160_3_chain2 : 8; - uint32_t rssi_ext160_4_chain2 : 8, - rssi_ext160_5_chain2 : 8, - rssi_ext160_6_chain2 : 8, - rssi_ext160_7_chain2 : 8; - uint32_t rssi_pri20_chain3 : 8, - rssi_ext20_chain3 : 8, - rssi_ext40_low20_chain3 : 8, - rssi_ext40_high20_chain3 : 8; - uint32_t rssi_ext80_low20_chain3 : 8, - rssi_ext80_low_high20_chain3 : 8, - rssi_ext80_high_low20_chain3 : 8, - rssi_ext80_high20_chain3 : 8; - uint32_t rssi_ext160_0_chain3 : 8, - rssi_ext160_1_chain3 : 8, - rssi_ext160_2_chain3 : 8, - rssi_ext160_3_chain3 : 8; - uint32_t rssi_ext160_4_chain3 : 8, - rssi_ext160_5_chain3 : 8, - rssi_ext160_6_chain3 : 8, - rssi_ext160_7_chain3 : 8; -#else - uint32_t rssi_ext40_high20_chain0 : 8, - rssi_ext40_low20_chain0 : 8, - rssi_ext20_chain0 : 8, - rssi_pri20_chain0 : 8; - uint32_t rssi_ext80_high20_chain0 : 8, - rssi_ext80_high_low20_chain0 : 8, - rssi_ext80_low_high20_chain0 : 8, - rssi_ext80_low20_chain0 : 8; - uint32_t rssi_ext160_3_chain0 : 8, - rssi_ext160_2_chain0 : 8, - rssi_ext160_1_chain0 : 8, - rssi_ext160_0_chain0 : 8; - uint32_t rssi_ext160_7_chain0 : 8, - rssi_ext160_6_chain0 : 8, - rssi_ext160_5_chain0 : 8, - rssi_ext160_4_chain0 : 8; - uint32_t rssi_ext40_high20_chain1 : 8, - rssi_ext40_low20_chain1 : 8, - rssi_ext20_chain1 : 8, - rssi_pri20_chain1 : 8; - uint32_t rssi_ext80_high20_chain1 : 8, - rssi_ext80_high_low20_chain1 : 8, - rssi_ext80_low_high20_chain1 : 8, - rssi_ext80_low20_chain1 : 8; - uint32_t rssi_ext160_3_chain1 : 8, - rssi_ext160_2_chain1 : 8, - rssi_ext160_1_chain1 : 8, - rssi_ext160_0_chain1 : 8; - uint32_t rssi_ext160_7_chain1 : 8, - rssi_ext160_6_chain1 : 8, - rssi_ext160_5_chain1 : 8, - rssi_ext160_4_chain1 : 8; - uint32_t rssi_ext40_high20_chain2 : 8, - rssi_ext40_low20_chain2 : 8, - rssi_ext20_chain2 : 8, - rssi_pri20_chain2 : 8; - uint32_t rssi_ext80_high20_chain2 : 8, - rssi_ext80_high_low20_chain2 : 8, - rssi_ext80_low_high20_chain2 : 8, - rssi_ext80_low20_chain2 : 8; - uint32_t rssi_ext160_3_chain2 : 8, - rssi_ext160_2_chain2 : 8, - rssi_ext160_1_chain2 : 8, - rssi_ext160_0_chain2 : 8; - uint32_t rssi_ext160_7_chain2 : 8, - rssi_ext160_6_chain2 : 8, - rssi_ext160_5_chain2 : 8, - rssi_ext160_4_chain2 : 8; - uint32_t rssi_ext40_high20_chain3 : 8, - rssi_ext40_low20_chain3 : 8, - rssi_ext20_chain3 : 8, - rssi_pri20_chain3 : 8; - uint32_t rssi_ext80_high20_chain3 : 8, - rssi_ext80_high_low20_chain3 : 8, - rssi_ext80_low_high20_chain3 : 8, - rssi_ext80_low20_chain3 : 8; - uint32_t rssi_ext160_3_chain3 : 8, - rssi_ext160_2_chain3 : 8, - rssi_ext160_1_chain3 : 8, - rssi_ext160_0_chain3 : 8; - uint32_t rssi_ext160_7_chain3 : 8, - rssi_ext160_6_chain3 : 8, - rssi_ext160_5_chain3 : 8, - rssi_ext160_4_chain3 : 8; -#endif -}; - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 - -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31 -#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/receive_user_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/receive_user_info.h deleted file mode 100644 index 23daabab5dc8..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/receive_user_info.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVE_USER_INFO_H_ -#define _RECEIVE_USER_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8 - -struct receive_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - user_rssi : 8, - pkt_type : 4, - stbc : 1, - reception_type : 3; - uint32_t rate_mcs : 5, - sgi : 2, - __reserved_g_0004 : 1, - mimo_ss_bitmap : 8, - receive_bandwidth : 3, - reserved_1b : 5, - dl_ofdma_user_index : 8; - uint32_t dl_ofdma_content_channel : 1, - reserved_2a : 1, - qam_diff1 : 2, - qam_diff2 : 2, - qam_diff3 : 2, - nss : 3, - stream_offset : 3, - sta_dcm : 1, - ldpc : 1, - ru_type_80_0 : 4, - ru_type_80_1 : 4, - ru_type_80_2 : 4, - ru_type_80_3 : 4; - uint32_t ru_start_index_80_0 : 6, - reserved_3a : 2, - ru_start_index_80_1 : 6, - reserved_3b : 2, - ru_start_index_80_2 : 6, - reserved_3c : 2, - ru_start_index_80_3 : 6, - reserved_3d : 2; - uint32_t user_fd_rssi_seg0 : 32; - uint32_t user_fd_rssi_seg1 : 32; - uint32_t user_fd_rssi_seg2 : 32; - uint32_t user_fd_rssi_seg3 : 32; -#else - uint32_t reception_type : 3, - stbc : 1, - pkt_type : 4, - user_rssi : 8, - phy_ppdu_id : 16; - uint32_t dl_ofdma_user_index : 8, - reserved_1b : 5, - receive_bandwidth : 3, - mimo_ss_bitmap : 8, - __reserved_g_0004 : 1, - sgi : 2, - rate_mcs : 5; - uint32_t ru_type_80_3 : 4, - ru_type_80_2 : 4, - ru_type_80_1 : 4, - ru_type_80_0 : 4, - ldpc : 1, - sta_dcm : 1, - stream_offset : 3, - nss : 3, - qam_diff3 : 2, - qam_diff2 : 2, - qam_diff1 : 2, - reserved_2a : 1, - dl_ofdma_content_channel : 1; - uint32_t reserved_3d : 2, - ru_start_index_80_3 : 6, - reserved_3c : 2, - ru_start_index_80_2 : 6, - reserved_3b : 2, - ru_start_index_80_1 : 6, - reserved_3a : 2, - ru_start_index_80_0 : 6; - uint32_t user_fd_rssi_seg0 : 32; - uint32_t user_fd_rssi_seg1 : 32; - uint32_t user_fd_rssi_seg2 : 32; - uint32_t user_fd_rssi_seg3 : 32; -#endif -}; - -#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15 -#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff - -#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_USER_RSSI_LSB 16 -#define RECEIVE_USER_INFO_USER_RSSI_MSB 23 -#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000 - -#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24 -#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27 -#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000 - -#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_STBC_LSB 28 -#define RECEIVE_USER_INFO_STBC_MSB 28 -#define RECEIVE_USER_INFO_STBC_MASK 0x10000000 - -#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31 -#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000 - -#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RATE_MCS_LSB 0 -#define RECEIVE_USER_INFO_RATE_MCS_MSB 4 -#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000001f - -#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_SGI_LSB 5 -#define RECEIVE_USER_INFO_SGI_MSB 6 -#define RECEIVE_USER_INFO_SGI_MASK 0x00000060 - -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15 -#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00 - -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18 -#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000 - -#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19 -#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23 -#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000 - -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31 -#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000 - -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 - -#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1 -#define RECEIVE_USER_INFO_RESERVED_2A_MSB 1 -#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x00000002 - -#define RECEIVE_USER_INFO_QAM_DIFF1_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF1_LSB 2 -#define RECEIVE_USER_INFO_QAM_DIFF1_MSB 3 -#define RECEIVE_USER_INFO_QAM_DIFF1_MASK 0x0000000c - -#define RECEIVE_USER_INFO_QAM_DIFF2_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF2_LSB 4 -#define RECEIVE_USER_INFO_QAM_DIFF2_MSB 5 -#define RECEIVE_USER_INFO_QAM_DIFF2_MASK 0x00000030 - -#define RECEIVE_USER_INFO_QAM_DIFF3_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_QAM_DIFF3_LSB 6 -#define RECEIVE_USER_INFO_QAM_DIFF3_MSB 7 -#define RECEIVE_USER_INFO_QAM_DIFF3_MASK 0x000000c0 - -#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_NSS_LSB 8 -#define RECEIVE_USER_INFO_NSS_MSB 10 -#define RECEIVE_USER_INFO_NSS_MASK 0x00000700 - -#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11 -#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13 -#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800 - -#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_STA_DCM_LSB 14 -#define RECEIVE_USER_INFO_STA_DCM_MSB 14 -#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000 - -#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_LDPC_LSB 15 -#define RECEIVE_USER_INFO_LDPC_MSB 15 -#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19 -#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23 -#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27 -#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000 - -#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31 -#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f - -#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6 -#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7 -#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00 - -#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14 -#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15 -#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000 - -#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22 -#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23 -#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000 - -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29 -#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000 - -#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c -#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30 -#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31 -#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000 - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff - -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31 -#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_15_8.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_15_8.h deleted file mode 100644 index 6cf8117ff02f..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_15_8.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_15_8_H_ -#define _RECEIVED_RESPONSE_USER_15_8_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_15_8 32 - -struct received_response_user_15_8 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user8; - struct received_response_user_info received_response_details_user9; - struct received_response_user_info received_response_details_user10; - struct received_response_user_info received_response_details_user11; - struct received_response_user_info received_response_details_user12; - struct received_response_user_info received_response_details_user13; - struct received_response_user_info received_response_details_user14; - struct received_response_user_info received_response_details_user15; -#else - struct received_response_user_info received_response_details_user8; - struct received_response_user_info received_response_details_user9; - struct received_response_user_info received_response_details_user10; - struct received_response_user_info received_response_details_user11; - struct received_response_user_info received_response_details_user12; - struct received_response_user_info received_response_details_user13; - struct received_response_user_info received_response_details_user14; - struct received_response_user_info received_response_details_user15; -#endif -}; - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_23_16.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_23_16.h deleted file mode 100644 index ff56f4d96472..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_23_16.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_23_16_H_ -#define _RECEIVED_RESPONSE_USER_23_16_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_23_16 32 - -struct received_response_user_23_16 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user16; - struct received_response_user_info received_response_details_user17; - struct received_response_user_info received_response_details_user18; - struct received_response_user_info received_response_details_user19; - struct received_response_user_info received_response_details_user20; - struct received_response_user_info received_response_details_user21; - struct received_response_user_info received_response_details_user22; - struct received_response_user_info received_response_details_user23; -#else - struct received_response_user_info received_response_details_user16; - struct received_response_user_info received_response_details_user17; - struct received_response_user_info received_response_details_user18; - struct received_response_user_info received_response_details_user19; - struct received_response_user_info received_response_details_user20; - struct received_response_user_info received_response_details_user21; - struct received_response_user_info received_response_details_user22; - struct received_response_user_info received_response_details_user23; -#endif -}; - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_31_24.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_31_24.h deleted file mode 100644 index aaa90838daa9..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_31_24.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_31_24_H_ -#define _RECEIVED_RESPONSE_USER_31_24_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_31_24 32 - -struct received_response_user_31_24 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user24; - struct received_response_user_info received_response_details_user25; - struct received_response_user_info received_response_details_user26; - struct received_response_user_info received_response_details_user27; - struct received_response_user_info received_response_details_user28; - struct received_response_user_info received_response_details_user29; - struct received_response_user_info received_response_details_user30; - struct received_response_user_info received_response_details_user31; -#else - struct received_response_user_info received_response_details_user24; - struct received_response_user_info received_response_details_user25; - struct received_response_user_info received_response_details_user26; - struct received_response_user_info received_response_details_user27; - struct received_response_user_info received_response_details_user28; - struct received_response_user_info received_response_details_user29; - struct received_response_user_info received_response_details_user30; - struct received_response_user_info received_response_details_user31; -#endif -}; - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_36_32.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_36_32.h deleted file mode 100644 index 3f33fdab635e..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_36_32.h +++ /dev/null @@ -1,705 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_36_32_H_ -#define _RECEIVED_RESPONSE_USER_36_32_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_36_32 20 - -struct received_response_user_36_32 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user32; - struct received_response_user_info received_response_details_user33; - struct received_response_user_info received_response_details_user34; - struct received_response_user_info received_response_details_user35; - struct received_response_user_info received_response_details_user36; -#else - struct received_response_user_info received_response_details_user32; - struct received_response_user_info received_response_details_user33; - struct received_response_user_info received_response_details_user34; - struct received_response_user_info received_response_details_user35; - struct received_response_user_info received_response_details_user36; -#endif -}; - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_7_0.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_7_0.h deleted file mode 100644 index f785aca46840..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_7_0.h +++ /dev/null @@ -1,1116 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_7_0_H_ -#define _RECEIVED_RESPONSE_USER_7_0_H_ - -#include "received_response_user_info.h" -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64 - -#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_7_0 32 - -struct received_response_user_7_0 { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_response_user_info received_response_details_user0; - struct received_response_user_info received_response_details_user1; - struct received_response_user_info received_response_details_user2; - struct received_response_user_info received_response_details_user3; - struct received_response_user_info received_response_details_user4; - struct received_response_user_info received_response_details_user5; - struct received_response_user_info received_response_details_user6; - struct received_response_user_info received_response_details_user7; -#else - struct received_response_user_info received_response_details_user0; - struct received_response_user_info received_response_details_user1; - struct received_response_user_info received_response_details_user2; - struct received_response_user_info received_response_details_user3; - struct received_response_user_info received_response_details_user4; - struct received_response_user_info received_response_details_user5; - struct received_response_user_info received_response_details_user6; - struct received_response_user_info received_response_details_user7; -#endif -}; - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET 0x0000000000000008 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET 0x0000000000000028 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x0000000000000040 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET 0x0000000000000048 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x0000000000000060 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET 0x0000000000000068 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x0000000000000080 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET 0x0000000000000088 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET 0x00000000000000a8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET 0x00000000000000c8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x0000000070000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x0000000080000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 53 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB 54 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB 62 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc0000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x8000000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET 0x00000000000000e8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK 0xffff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 32 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 39 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 40 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 47 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 48 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 55 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 - -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 56 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 63 -#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_info.h deleted file mode 100644 index 3c3faf119635..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/received_response_user_info.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_RESPONSE_USER_INFO_H_ -#define _RECEIVED_RESPONSE_USER_INFO_H_ - -#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8 - -struct received_response_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mpdu_fcs_pass_count : 12, - mpdu_fcs_fail_count : 12, - qosnull_frame_count : 4, - reserved_0a : 3, - user_info_valid : 1; - uint32_t null_delimiter_count : 22, - reserved_1a : 9, - ht_control_valid : 1; - uint32_t ht_control : 32; - uint32_t qos_control_valid : 16, - eosp : 16; - uint32_t qos_control_15_8_tid_0 : 8, - qos_control_15_8_tid_1 : 8, - qos_control_15_8_tid_2 : 8, - qos_control_15_8_tid_3 : 8; - uint32_t qos_control_15_8_tid_4 : 8, - qos_control_15_8_tid_5 : 8, - qos_control_15_8_tid_6 : 8, - qos_control_15_8_tid_7 : 8; - uint32_t qos_control_15_8_tid_8 : 8, - qos_control_15_8_tid_9 : 8, - qos_control_15_8_tid_10 : 8, - qos_control_15_8_tid_11 : 8; - uint32_t qos_control_15_8_tid_12 : 8, - qos_control_15_8_tid_13 : 8, - qos_control_15_8_tid_14 : 8, - qos_control_15_8_tid_15 : 8; -#else - uint32_t user_info_valid : 1, - reserved_0a : 3, - qosnull_frame_count : 4, - mpdu_fcs_fail_count : 12, - mpdu_fcs_pass_count : 12; - uint32_t ht_control_valid : 1, - reserved_1a : 9, - null_delimiter_count : 22; - uint32_t ht_control : 32; - uint32_t eosp : 16, - qos_control_valid : 16; - uint32_t qos_control_15_8_tid_3 : 8, - qos_control_15_8_tid_2 : 8, - qos_control_15_8_tid_1 : 8, - qos_control_15_8_tid_0 : 8; - uint32_t qos_control_15_8_tid_7 : 8, - qos_control_15_8_tid_6 : 8, - qos_control_15_8_tid_5 : 8, - qos_control_15_8_tid_4 : 8; - uint32_t qos_control_15_8_tid_11 : 8, - qos_control_15_8_tid_10 : 8, - qos_control_15_8_tid_9 : 8, - qos_control_15_8_tid_8 : 8; - uint32_t qos_control_15_8_tid_15 : 8, - qos_control_15_8_tid_14 : 8, - qos_control_15_8_tid_13 : 8, - qos_control_15_8_tid_12 : 8; -#endif -}; - -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff - -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 - -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27 -#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000 - -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000 - -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000 - -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21 -#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff - -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30 -#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000 - -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000 - -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff - -#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c -#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 - -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31 -#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/received_trigger_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_trigger_info.h deleted file mode 100644 index ff464f4e3bb5..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/received_trigger_info.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_TRIGGER_INFO_H_ -#define _RECEIVED_TRIGGER_INFO_H_ - -#include "received_trigger_info_details.h" -#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 6 - -#define NUM_OF_QWORDS_RECEIVED_TRIGGER_INFO 3 - -struct received_trigger_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct received_trigger_info_details received_trigger_details; -#else - struct received_trigger_info_details received_trigger_details; -#endif -}; - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000010 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000001e0 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x00000000003ffe00 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x0000000000400000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x0000000000800000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x0000000001000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_LSB 29 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MSB 30 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MASK 0x0000000060000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x0000000080000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 47 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 48 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 59 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_LSB 61 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MSB 61 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SCSID_VALID_MASK 0x2000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_LSB 62 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MSB 62 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_ECTS_AS_TB_PPDU_MASK 0x4000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0x8000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x000000000000ffff - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0x00000000ffff0000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 48 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 56 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 62 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xc000000000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0x00000000ffffffff - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB 32 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK 0x0000000100000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_LSB 33 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MSB 36 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_LOWER_4_MASK 0x0000001e00000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_LSB 37 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MSB 39 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_DURATIONID_UPPER_3_MASK 0x000000e000000000 - -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_OFFSET 0x0000000000000010 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_LSB 40 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MSB 63 -#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_5A_MASK 0xffffff0000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/received_trigger_info_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/received_trigger_info_details.h deleted file mode 100644 index ae169bca026b..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/received_trigger_info_details.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_ -#define _RECEIVED_TRIGGER_INFO_DETAILS_H_ - -#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 6 - -struct received_trigger_info_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t trigger_type : 4, - ax_trigger_source : 1, - ax_trigger_type : 4, - trigger_source_sta_full_aid : 13, - frame_control_valid : 1, - qos_control_valid : 1, - he_control_info_valid : 1, - __reserved_g_0005_trigger_subtype : 4, - txop_sharing_mode : 2, - tid_aggregation_limit_is_zero : 1; - uint32_t phy_ppdu_id : 16, - lsig_response_length : 12, - __reserved_g_0086 : 1, - scsid_valid : 1, - ects_as_tb_ppdu : 1, - reserved_1a : 1; - uint32_t frame_control : 16, - qos_control : 16; - uint32_t sw_peer_id : 16, - txop_sharing_allocation_duration : 9, - __reserved_g_0074 : 4, - __reserved_g_0034 : 1, - reserved_3a : 2; - uint32_t he_control : 32; - uint32_t txop_sharing_duration_from_durid : 1, - frame_durationid_lower_4 : 4, - frame_durationid_upper_3 : 3, - reserved_5a : 24; -#else - uint32_t tid_aggregation_limit_is_zero : 1, - txop_sharing_mode : 2, - __reserved_g_0005_trigger_subtype : 4, - he_control_info_valid : 1, - qos_control_valid : 1, - frame_control_valid : 1, - trigger_source_sta_full_aid : 13, - ax_trigger_type : 4, - ax_trigger_source : 1, - trigger_type : 4; - uint32_t reserved_1a : 1, - ects_as_tb_ppdu : 1, - scsid_valid : 1, - __reserved_g_0086 : 1, - lsig_response_length : 12, - phy_ppdu_id : 16; - uint32_t qos_control : 16, - frame_control : 16; - uint32_t reserved_3a : 2, - __reserved_g_0034 : 1, - __reserved_g_0074 : 4, - txop_sharing_allocation_duration : 9, - sw_peer_id : 16; - uint32_t he_control : 32; - uint32_t reserved_5a : 24, - frame_durationid_upper_3 : 3, - frame_durationid_lower_4 : 4, - txop_sharing_duration_from_durid : 1; -#endif -}; - -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f - -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 - -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8 -#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 -#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 -#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_LSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MSB 29 -#define RECEIVED_TRIGGER_INFO_DETAILS_SCSID_VALID_MASK 0x20000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_LSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_ECTS_AS_TB_PPDU_MASK 0x40000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0x80000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15 -#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 30 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xc0000000 - -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff - -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_LSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MSB 0 -#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_DURATION_FROM_DURID_MASK 0x00000001 - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_LSB 1 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MSB 4 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_LOWER_4_MASK 0x0000001e - -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_LSB 5 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MSB 7 -#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_DURATIONID_UPPER_3_MASK 0x000000e0 - -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_OFFSET 0x00000014 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_LSB 8 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MSB 31 -#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_5A_MASK 0xffffff00 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/reo_destination_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/reo_destination_ring.h deleted file mode 100644 index 5147635121c1..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/reo_destination_ring.h +++ /dev/null @@ -1,305 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_DESTINATION_RING_H_ -#define _REO_DESTINATION_RING_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_mpdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_REO_DESTINATION_RING 8 - -struct reo_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t release_source_module : 3, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_delink_error : 1, - sw_buffer_cookie : 20; - uint32_t msdu_link_desc_index : 4, - reserved_6a : 28; - uint32_t reo_dest_buffer_type : 1, - reo_push_reason : 2, - reo_error_code : 5, - captured_msdu_data_size : 4, - sw_exception : 1, - src_link_id : 3, - reo_destination_struct_signature : 4, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t sw_buffer_cookie : 20, - reo_delink_error : 1, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - release_source_module : 3; - uint32_t reserved_6a : 28, - msdu_link_desc_index : 4; - uint32_t looping_count : 4, - ring_id : 8, - reo_destination_struct_signature : 4, - src_link_id : 3, - sw_exception : 1, - captured_msdu_data_size : 4, - reo_error_code : 5, - reo_push_reason : 2, - reo_dest_buffer_type : 1; -#endif -}; - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define REO_DESTINATION_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_OFFSET 0x00000014 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_LSB 3 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MSB 3 -#define REO_DESTINATION_RING_COOKIE_CONVERSION_STATUS_MASK 0x00000008 - -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_LSB 4 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MSB 5 -#define REO_DESTINATION_RING_RXDMA_PUSH_REASON_MASK 0x00000030 - -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_LSB 6 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MSB 10 -#define REO_DESTINATION_RING_RXDMA_ERROR_CODE_MASK 0x000007c0 - -#define REO_DESTINATION_RING_REO_DELINK_ERROR_OFFSET 0x00000014 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_LSB 11 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_MSB 11 -#define REO_DESTINATION_RING_REO_DELINK_ERROR_MASK 0x00000800 - -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_OFFSET 0x00000018 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_LSB 0 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MSB 3 -#define REO_DESTINATION_RING_MSDU_LINK_DESC_INDEX_MASK 0x0000000f - -#define REO_DESTINATION_RING_RESERVED_6A_OFFSET 0x00000018 -#define REO_DESTINATION_RING_RESERVED_6A_LSB 4 -#define REO_DESTINATION_RING_RESERVED_6A_MSB 31 -#define REO_DESTINATION_RING_RESERVED_6A_MASK 0xfffffff0 - -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0 -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0 -#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001 - -#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1 -#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2 -#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006 - -#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3 -#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7 -#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8 - -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8 -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11 -#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 - -#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c -#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12 -#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12 -#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000 - -#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13 -#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15 -#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000 - -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 -#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 - -#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_RING_ID_LSB 20 -#define REO_DESTINATION_RING_RING_ID_MSB 27 -#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000 - -#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28 -#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31 -#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/reo_destination_ring_with_pn.h b/drivers/staging/fw-api/hw/wcn8750/v1/reo_destination_ring_with_pn.h deleted file mode 100644 index b486a8658388..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/reo_destination_ring_with_pn.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_DESTINATION_RING_WITH_PN_H_ -#define _REO_DESTINATION_RING_WITH_PN_H_ - -#include "rx_msdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8 - -struct reo_destination_ring_with_pn { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - uint32_t msdu_count : 8, - prev_pn_23_0 : 24; - uint32_t prev_pn_47_24 : 24, - prev_pn_127_48_info : 2, - reserved_3a : 6; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t release_source_module : 3, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_delink_error : 1, - sw_buffer_cookie : 20; - uint32_t msdu_link_desc_index : 4, - reserved_6a : 28; - uint32_t reo_dest_buffer_type : 1, - reo_push_reason : 2, - reo_error_code : 5, - captured_msdu_data_size : 4, - sw_exception : 1, - src_link_id : 3, - reo_destination_struct_signature : 4, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_link_desc_virt_addr_or_addr_info; - uint32_t prev_pn_23_0 : 24, - msdu_count : 8; - uint32_t reserved_3a : 6, - prev_pn_127_48_info : 2, - prev_pn_47_24 : 24; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t sw_buffer_cookie : 20, - reo_delink_error : 1, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - release_source_module : 3; - uint32_t reserved_6a : 28, - msdu_link_desc_index : 4; - uint32_t looping_count : 4, - ring_id : 8, - reo_destination_struct_signature : 4, - src_link_id : 3, - sw_exception : 1, - captured_msdu_data_size : 4, - reo_error_code : 5, - reo_push_reason : 2, - reo_dest_buffer_type : 1; -#endif -}; - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET 0x00000008 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK 0x000000ff - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET 0x00000008 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK 0xffffff00 - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MSB 23 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_47_24_MASK 0x00ffffff - -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_LSB 24 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MSB 25 -#define REO_DESTINATION_RING_WITH_PN_PREV_PN_127_48_INFO_MASK 0x03000000 - -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_OFFSET 0x0000000c -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_LSB 26 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_3A_MASK 0xfc000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MSB 3 -#define REO_DESTINATION_RING_WITH_PN_COOKIE_CONVERSION_STATUS_MASK 0x00000008 - -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_LSB 4 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MSB 5 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_PUSH_REASON_MASK 0x00000030 - -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_LSB 6 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MSB 10 -#define REO_DESTINATION_RING_WITH_PN_RXDMA_ERROR_CODE_MASK 0x000007c0 - -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_LSB 11 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_REO_DELINK_ERROR_MASK 0x00000800 - -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_OFFSET 0x00000018 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MSB 3 -#define REO_DESTINATION_RING_WITH_PN_MSDU_LINK_DESC_INDEX_MASK 0x0000000f - -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_OFFSET 0x00000018 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_LSB 4 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_RESERVED_6A_MASK 0xfffffff0 - -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB 0 -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB 0 -#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK 0x00000001 - -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB 1 -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB 2 -#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK 0x00000006 - -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB 3 -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB 7 -#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK 0x000000f8 - -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB 8 -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB 11 -#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 - -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB 12 -#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK 0x00001000 - -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB 13 -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB 15 -#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK 0x0000e000 - -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 -#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 - -#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB 20 -#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB 27 -#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK 0x0ff00000 - -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET 0x0000001c -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB 28 -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB 31 -#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/reo_entrance_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/reo_entrance_ring.h deleted file mode 100644 index 17a68d08ce25..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/reo_entrance_ring.h +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _REO_ENTRANCE_RING_H_ -#define _REO_ENTRANCE_RING_H_ - -#include "rx_mpdu_details.h" -#define NUM_OF_DWORDS_REO_ENTRANCE_RING 12 - -struct reo_entrance_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_mpdu_details reo_level_mpdu_frame_info; - uint32_t rx_preamble_timestamp : 32; - uint32_t reserved_7a : 8, - rounded_mpdu_byte_count : 14, - reo_destination_indication : 5, - frameless_bar : 1, - reserved_7b : 4; - uint32_t rxdma_push_reason : 2, - rxdma_error_code : 5, - mpdu_fragment_number : 4, - sw_exception : 1, - sw_exception_mpdu_delink : 1, - sw_exception_destination_ring_valid : 1, - sw_exception_destination_ring : 5, - mpdu_sequence_number : 12, - no_ack : 1; - uint32_t phy_ppdu_id : 16, - src_link_id : 3, - reserved_9a : 5, - rx_reo_queue_desc_addr_39_32 : 8; - uint32_t receive_queue_number : 16, - fw_reorder_push_reason : 2, - fw_reorder_error_code : 5, - reo_bypass : 1, - reserved_10a : 8; - uint32_t phy_lmac_latency : 16, - reserved_15a : 4, - ring_id : 8, - looping_count : 4; -#else - struct rx_mpdu_details reo_level_mpdu_frame_info; - uint32_t rx_preamble_timestamp : 32; - uint32_t reserved_7b : 4, - frameless_bar : 1, - reo_destination_indication : 5, - rounded_mpdu_byte_count : 14, - reserved_7a : 8; - uint32_t no_ack : 1, - mpdu_sequence_number : 12, - sw_exception_destination_ring : 5, - sw_exception_destination_ring_valid : 1, - sw_exception_mpdu_delink : 1, - sw_exception : 1, - mpdu_fragment_number : 4, - rxdma_error_code : 5, - rxdma_push_reason : 2; - uint32_t rx_reo_queue_desc_addr_39_32 : 8, - reserved_9a : 5, - src_link_id : 3, - phy_ppdu_id : 16; - uint32_t reserved_10a : 8, - reo_bypass : 1, - fw_reorder_error_code : 5, - fw_reorder_push_reason : 2, - receive_queue_number : 16; - uint32_t looping_count : 4, - ring_id : 8, - reserved_15a : 4, - phy_lmac_latency : 16; -#endif -}; - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET 0x00000010 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK 0xffffffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB 0 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB 15 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB 16 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB 17 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK 0x00030000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB 18 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB 21 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB 22 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB 31 -#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffc00000 - -#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_OFFSET 0x00000018 -#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_LSB 0 -#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_MSB 31 -#define REO_ENTRANCE_RING_RX_PREAMBLE_TIMESTAMP_MASK 0xffffffff - -#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_RESERVED_7A_LSB 0 -#define REO_ENTRANCE_RING_RESERVED_7A_MSB 7 -#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x000000ff - -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8 -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21 -#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 - -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22 -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26 -#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000 - -#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27 -#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27 -#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000 - -#define REO_ENTRANCE_RING_RESERVED_7B_OFFSET 0x0000001c -#define REO_ENTRANCE_RING_RESERVED_7B_LSB 28 -#define REO_ENTRANCE_RING_RESERVED_7B_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_7B_MASK 0xf0000000 - -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1 -#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003 - -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6 -#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c - -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10 -#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12 -#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 - -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18 -#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 - -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30 -#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000 - -#define REO_ENTRANCE_RING_NO_ACK_OFFSET 0x00000020 -#define REO_ENTRANCE_RING_NO_ACK_LSB 31 -#define REO_ENTRANCE_RING_NO_ACK_MSB 31 -#define REO_ENTRANCE_RING_NO_ACK_MASK 0x80000000 - -#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15 -#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16 -#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18 -#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000 - -#define REO_ENTRANCE_RING_RESERVED_9A_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_RESERVED_9A_LSB 19 -#define REO_ENTRANCE_RING_RESERVED_9A_MSB 23 -#define REO_ENTRANCE_RING_RESERVED_9A_MASK 0x00f80000 - -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000024 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 24 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 31 -#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0xff000000 - -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_LSB 0 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MSB 15 -#define REO_ENTRANCE_RING_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_LSB 16 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MSB 17 -#define REO_ENTRANCE_RING_FW_REORDER_PUSH_REASON_MASK 0x00030000 - -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_LSB 18 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MSB 22 -#define REO_ENTRANCE_RING_FW_REORDER_ERROR_CODE_MASK 0x007c0000 - -#define REO_ENTRANCE_RING_REO_BYPASS_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_REO_BYPASS_LSB 23 -#define REO_ENTRANCE_RING_REO_BYPASS_MSB 23 -#define REO_ENTRANCE_RING_REO_BYPASS_MASK 0x00800000 - -#define REO_ENTRANCE_RING_RESERVED_10A_OFFSET 0x00000028 -#define REO_ENTRANCE_RING_RESERVED_10A_LSB 24 -#define REO_ENTRANCE_RING_RESERVED_10A_MSB 31 -#define REO_ENTRANCE_RING_RESERVED_10A_MASK 0xff000000 - -#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_LSB 0 -#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_MSB 15 -#define REO_ENTRANCE_RING_PHY_LMAC_LATENCY_MASK 0x0000ffff - -#define REO_ENTRANCE_RING_RESERVED_15A_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_RESERVED_15A_LSB 16 -#define REO_ENTRANCE_RING_RESERVED_15A_MSB 19 -#define REO_ENTRANCE_RING_RESERVED_15A_MASK 0x000f0000 - -#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_RING_ID_LSB 20 -#define REO_ENTRANCE_RING_RING_ID_MSB 27 -#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000 - -#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000002c -#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28 -#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31 -#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/response_end_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/response_end_status.h deleted file mode 100644 index 20f72c890ffe..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/response_end_status.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RESPONSE_END_STATUS_H_ -#define _RESPONSE_END_STATUS_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_RESPONSE_END_STATUS 10 - -#define NUM_OF_QWORDS_RESPONSE_END_STATUS 5 - -struct response_end_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t __reserved_g_0072 : 1, - __reserved_g_0065 : 1, - __reserved_g_0062 : 1, - global_data_underflow_warning : 1, - response_transmit_status : 4, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - generated_response : 3, - mba_user_count : 7, - mba_fake_bitmap_count : 7, - coex_based_tx_bw : 3, - trig_response_related : 1, - __reserved_g_0086 : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t cbf_segment_request_mask : 8, - cbf_segment_sent_mask : 8; - uint32_t underflow_mpdu_count : 9, - data_underflow_warning : 2, - reserved_2b : 10, - only_null_delim_sent : 1, - brp_info_valid : 1, - __reserved_g_0067 : 1, - __reserved_g_0069 : 1, - __reserved_g_0051 : 1, - __reserved_g_0049 : 1, - __reserved_g_0047 : 1, - __reserved_g_0045 : 1, - __reserved_g_0043 : 1, - __reserved_g_0041 : 1, - __reserved_g_0030 : 1; - uint32_t mu_response_bitmap_31_0 : 32; - uint32_t mu_response_bitmap_36_32 : 5, - overwritten_blackout_window_bitmap : 4, - mic_overwritten : 1, - trig_resp_cmd_found : 1, - reserved_4a : 21; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t addr3_47_32 : 16, - __reserved_g_0005 : 1, - secure : 1, - __reserved_g_0005_ftm_frame_sent : 1, - reserved_20a : 13; -#else - uint32_t __reserved_g_0086 : 1, - trig_response_related : 1, - coex_based_tx_bw : 3, - mba_fake_bitmap_count : 7, - mba_user_count : 7, - generated_response : 3, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - response_transmit_status : 4, - global_data_underflow_warning : 1, - __reserved_g_0062 : 1, - __reserved_g_0065 : 1, - __reserved_g_0072 : 1; - uint32_t cbf_segment_sent_mask : 8, - cbf_segment_request_mask : 8; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t __reserved_g_0030 : 1, - __reserved_g_0041 : 1, - __reserved_g_0043 : 1, - __reserved_g_0045 : 1, - __reserved_g_0047 : 1, - __reserved_g_0049 : 1, - __reserved_g_0051 : 1, - __reserved_g_0069 : 1, - __reserved_g_0067 : 1, - brp_info_valid : 1, - only_null_delim_sent : 1, - reserved_2b : 10, - data_underflow_warning : 2, - underflow_mpdu_count : 9; - uint32_t mu_response_bitmap_31_0 : 32; - uint32_t reserved_4a : 21, - trig_resp_cmd_found : 1, - mic_overwritten : 1, - overwritten_blackout_window_bitmap : 4, - mu_response_bitmap_36_32 : 5; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t reserved_20a : 13, - __reserved_g_0005_ftm_frame_sent : 1, - secure : 1, - __reserved_g_0005 : 1, - addr3_47_32 : 16; -#endif -}; - -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 -#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008 - -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 -#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0 - -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 -#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200 - -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 -#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00 - -#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 -#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000 - -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 -#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000 - -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 -#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000 - -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 -#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55 -#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000 - -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63 -#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000 - -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 -#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff - -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 -#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 - -#define RESPONSE_END_STATUS_RESERVED_2B_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_RESERVED_2B_LSB 11 -#define RESPONSE_END_STATUS_RESERVED_2B_MSB 20 -#define RESPONSE_END_STATUS_RESERVED_2B_MASK 0x00000000001ff800 - -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 -#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000 - -#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 -#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000 - -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 -#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f - -#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_LSB 5 -#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MSB 8 -#define RESPONSE_END_STATUS_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MASK 0x00000000000001e0 - -#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_LSB 9 -#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_MSB 9 -#define RESPONSE_END_STATUS_MIC_OVERWRITTEN_MASK 0x0000000000000200 - -#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_LSB 10 -#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_MSB 10 -#define RESPONSE_END_STATUS_TRIG_RESP_CMD_FOUND_MASK 0x0000000000000400 - -#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_RESERVED_4A_LSB 11 -#define RESPONSE_END_STATUS_RESERVED_4A_MSB 31 -#define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x00000000fffff800 - -#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000010 -#define RESPONSE_END_STATUS_ADDR1_31_0_LSB 32 -#define RESPONSE_END_STATUS_ADDR1_31_0_MSB 63 -#define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR1_47_32_LSB 0 -#define RESPONSE_END_STATUS_ADDR1_47_32_MSB 15 -#define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x000000000000ffff - -#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR2_15_0_LSB 16 -#define RESPONSE_END_STATUS_ADDR2_15_0_MSB 31 -#define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0x00000000ffff0000 - -#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000018 -#define RESPONSE_END_STATUS_ADDR2_47_16_LSB 32 -#define RESPONSE_END_STATUS_ADDR2_47_16_MSB 63 -#define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0xffffffff00000000 - -#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_ADDR3_31_0_LSB 0 -#define RESPONSE_END_STATUS_ADDR3_31_0_MSB 31 -#define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0x00000000ffffffff - -#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_ADDR3_47_32_LSB 32 -#define RESPONSE_END_STATUS_ADDR3_47_32_MSB 47 -#define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x0000ffff00000000 - -#define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_SECURE_LSB 49 -#define RESPONSE_END_STATUS_SECURE_MSB 49 -#define RESPONSE_END_STATUS_SECURE_MASK 0x0002000000000000 - -#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000020 -#define RESPONSE_END_STATUS_RESERVED_20A_LSB 51 -#define RESPONSE_END_STATUS_RESERVED_20A_MSB 63 -#define RESPONSE_END_STATUS_RESERVED_20A_MASK 0xfff8000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/response_start_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/response_start_status.h deleted file mode 100644 index 0a3090f219fe..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/response_start_status.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RESPONSE_START_STATUS_H_ -#define _RESPONSE_START_STATUS_H_ - -#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 - -#define NUM_OF_QWORDS_RESPONSE_START_STATUS 1 - -struct response_start_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t generated_response : 3, - __reserved_g_0012 : 2, - trig_response_related : 1, - response_sta_count : 7, - mba_for_cfp_ba : 1, - mba_for_cfp_ack : 1, - ects_response_type : 2, - eba_response_type : 2, - cfp_mba : 1, - mba_for_ll_ack : 1, - mba_for_ll_ba : 1, - reserved : 10; - uint32_t phy_ppdu_id : 16, - sw_peer_id : 16; -#else - uint32_t reserved : 10, - mba_for_ll_ba : 1, - mba_for_ll_ack : 1, - cfp_mba : 1, - eba_response_type : 2, - ects_response_type : 2, - mba_for_cfp_ack : 1, - mba_for_cfp_ba : 1, - response_sta_count : 7, - trig_response_related : 1, - __reserved_g_0012 : 2, - generated_response : 3; - uint32_t sw_peer_id : 16, - phy_ppdu_id : 16; -#endif -}; - -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 -#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x0000000000000007 - -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 -#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000000000020 - -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 -#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x0000000000001fc0 - -#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_LSB 13 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_MSB 13 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_BA_MASK 0x0000000000002000 - -#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_LSB 14 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_MSB 14 -#define RESPONSE_START_STATUS_MBA_FOR_CFP_ACK_MASK 0x0000000000004000 - -#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_LSB 15 -#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_MSB 16 -#define RESPONSE_START_STATUS_ECTS_RESPONSE_TYPE_MASK 0x0000000000018000 - -#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_LSB 17 -#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_MSB 18 -#define RESPONSE_START_STATUS_EBA_RESPONSE_TYPE_MASK 0x0000000000060000 - -#define RESPONSE_START_STATUS_CFP_MBA_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_CFP_MBA_LSB 19 -#define RESPONSE_START_STATUS_CFP_MBA_MSB 19 -#define RESPONSE_START_STATUS_CFP_MBA_MASK 0x0000000000080000 - -#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_LSB 20 -#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_MSB 20 -#define RESPONSE_START_STATUS_MBA_FOR_LL_ACK_MASK 0x0000000000100000 - -#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_LSB 21 -#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_MSB 21 -#define RESPONSE_START_STATUS_MBA_FOR_LL_BA_MASK 0x0000000000200000 - -#define RESPONSE_START_STATUS_RESERVED_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_RESERVED_LSB 22 -#define RESPONSE_START_STATUS_RESERVED_MSB 31 -#define RESPONSE_START_STATUS_RESERVED_MASK 0x00000000ffc00000 - -#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 32 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 47 -#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff00000000 - -#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x0000000000000000 -#define RESPONSE_START_STATUS_SW_PEER_ID_LSB 48 -#define RESPONSE_START_STATUS_SW_PEER_ID_MSB 63 -#define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/ru_allocation_160_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/ru_allocation_160_info.h deleted file mode 100644 index 57d51dc44f8a..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/ru_allocation_160_info.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RU_ALLOCATION_160_INFO_H_ -#define _RU_ALLOCATION_160_INFO_H_ - -#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4 - -struct ru_allocation_160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ru_allocation_band0_0 : 9, - ru_allocation_band0_1 : 9, - reserved_0a : 6, - ru_allocations_01_subband80_mask : 4, - ru_allocations_23_subband80_mask : 4; - uint32_t ru_allocation_band0_2 : 9, - ru_allocation_band0_3 : 9, - reserved_1a : 14; - uint32_t ru_allocation_band1_0 : 9, - ru_allocation_band1_1 : 9, - reserved_2a : 14; - uint32_t ru_allocation_band1_2 : 9, - ru_allocation_band1_3 : 9, - reserved_3a : 14; -#else - uint32_t ru_allocations_23_subband80_mask : 4, - ru_allocations_01_subband80_mask : 4, - reserved_0a : 6, - ru_allocation_band0_1 : 9, - ru_allocation_band0_0 : 9; - uint32_t reserved_1a : 14, - ru_allocation_band0_3 : 9, - ru_allocation_band0_2 : 9; - uint32_t reserved_2a : 14, - ru_allocation_band1_1 : 9, - ru_allocation_band1_0 : 9; - uint32_t reserved_3a : 14, - ru_allocation_band1_3 : 9, - ru_allocation_band1_2 : 9; -#endif -}; - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB 23 -#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK 0x00fc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000000 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK 0xfffc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK 0xfffc0000 - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB 0 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB 8 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK 0x000001ff - -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB 9 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB 17 -#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 - -#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB 18 -#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB 31 -#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK 0xfffc0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_attention.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_attention.h deleted file mode 100644 index cac7c2fb52c3..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_attention.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_ATTENTION_H_ -#define _RX_ATTENTION_H_ - -#define NUM_OF_DWORDS_RX_ATTENTION 4 - -#define NUM_OF_QWORDS_RX_ATTENTION 2 - -struct rx_attention { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t first_mpdu : 1, - reserved_1a : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - a_msdu_error : 1, - fragment_flag : 1, - order : 1, - cce_match : 1, - overflow_err : 1, - msdu_length_err : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - sa_idx_invalid : 1, - da_idx_invalid : 1, - reserved_1b : 1, - rx_in_tx_decrypt_byp : 1, - encrypt_required : 1, - directed : 1, - buffer_fragment : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - fcs_err : 1; - uint32_t flow_idx_timeout : 1, - flow_idx_invalid : 1, - wifi_parser_error : 1, - amsdu_parser_error : 1, - sa_idx_timeout : 1, - da_idx_timeout : 1, - msdu_limit_error : 1, - da_is_valid : 1, - da_is_mcbc : 1, - sa_is_valid : 1, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - reserved_2 : 17, - msdu_done : 1; - uint32_t tlv64_padding : 32; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t fcs_err : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - buffer_fragment : 1, - directed : 1, - encrypt_required : 1, - rx_in_tx_decrypt_byp : 1, - reserved_1b : 1, - da_idx_invalid : 1, - sa_idx_invalid : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - msdu_length_err : 1, - overflow_err : 1, - cce_match : 1, - order : 1, - fragment_flag : 1, - a_msdu_error : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - reserved_1a : 1, - first_mpdu : 1; - uint32_t msdu_done : 1, - reserved_2 : 17, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - sa_is_valid : 1, - da_is_mcbc : 1, - da_is_valid : 1, - msdu_limit_error : 1, - da_idx_timeout : 1, - sa_idx_timeout : 1, - amsdu_parser_error : 1, - wifi_parser_error : 1, - flow_idx_invalid : 1, - flow_idx_timeout : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 -#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_0_LSB 9 -#define RX_ATTENTION_RESERVED_0_MSB 15 -#define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_PHY_PPDU_ID_LSB 16 -#define RX_ATTENTION_PHY_PPDU_ID_MSB 31 -#define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FIRST_MPDU_LSB 32 -#define RX_ATTENTION_FIRST_MPDU_MSB 32 -#define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000 - -#define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_1A_LSB 33 -#define RX_ATTENTION_RESERVED_1A_MSB 33 -#define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000 - -#define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MCAST_BCAST_LSB 34 -#define RX_ATTENTION_MCAST_BCAST_MSB 34 -#define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000 - -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35 -#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000 - -#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36 -#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000 - -#define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_POWER_MGMT_LSB 37 -#define RX_ATTENTION_POWER_MGMT_MSB 37 -#define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000 - -#define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000 -#define RX_ATTENTION_NON_QOS_LSB 38 -#define RX_ATTENTION_NON_QOS_MSB 38 -#define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000 - -#define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000 -#define RX_ATTENTION_NULL_DATA_LSB 39 -#define RX_ATTENTION_NULL_DATA_MSB 39 -#define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000 - -#define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MGMT_TYPE_LSB 40 -#define RX_ATTENTION_MGMT_TYPE_MSB 40 -#define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000 - -#define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000 -#define RX_ATTENTION_CTRL_TYPE_LSB 41 -#define RX_ATTENTION_CTRL_TYPE_MSB 41 -#define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000 - -#define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MORE_DATA_LSB 42 -#define RX_ATTENTION_MORE_DATA_MSB 42 -#define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000 - -#define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000 -#define RX_ATTENTION_EOSP_LSB 43 -#define RX_ATTENTION_EOSP_MSB 43 -#define RX_ATTENTION_EOSP_MASK 0x0000080000000000 - -#define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_A_MSDU_ERROR_LSB 44 -#define RX_ATTENTION_A_MSDU_ERROR_MSB 44 -#define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000 - -#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FRAGMENT_FLAG_LSB 45 -#define RX_ATTENTION_FRAGMENT_FLAG_MSB 45 -#define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000 - -#define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000 -#define RX_ATTENTION_ORDER_LSB 46 -#define RX_ATTENTION_ORDER_MSB 46 -#define RX_ATTENTION_ORDER_MASK 0x0000400000000000 - -#define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000 -#define RX_ATTENTION_CCE_MATCH_LSB 47 -#define RX_ATTENTION_CCE_MATCH_MSB 47 -#define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000 - -#define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_OVERFLOW_ERR_LSB 48 -#define RX_ATTENTION_OVERFLOW_ERR_MSB 48 -#define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000 - -#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49 -#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49 -#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000 - -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50 -#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000 - -#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000 -#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51 -#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51 -#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000 - -#define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_SA_IDX_INVALID_LSB 52 -#define RX_ATTENTION_SA_IDX_INVALID_MSB 52 -#define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000 - -#define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DA_IDX_INVALID_LSB 53 -#define RX_ATTENTION_DA_IDX_INVALID_MSB 53 -#define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000 - -#define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RESERVED_1B_LSB 54 -#define RX_ATTENTION_RESERVED_1B_MSB 54 -#define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000 - -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55 -#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000 - -#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000 -#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56 -#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56 -#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000 - -#define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DIRECTED_LSB 57 -#define RX_ATTENTION_DIRECTED_MSB 57 -#define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000 - -#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000 -#define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58 -#define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58 -#define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000 - -#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59 -#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59 -#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000 - -#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_TKIP_MIC_ERR_LSB 60 -#define RX_ATTENTION_TKIP_MIC_ERR_MSB 60 -#define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000 - -#define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_DECRYPT_ERR_LSB 61 -#define RX_ATTENTION_DECRYPT_ERR_MSB 61 -#define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000 - -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62 -#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000 - -#define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000 -#define RX_ATTENTION_FCS_ERR_LSB 63 -#define RX_ATTENTION_FCS_ERR_MSB 63 -#define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000 - -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 -#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001 - -#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 -#define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 -#define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002 - -#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 -#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 -#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004 - -#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 -#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008 - -#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 -#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 -#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010 - -#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 -#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 -#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020 - -#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 -#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040 - -#define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IS_VALID_LSB 7 -#define RX_ATTENTION_DA_IS_VALID_MSB 7 -#define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080 - -#define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DA_IS_MCBC_LSB 8 -#define RX_ATTENTION_DA_IS_MCBC_MSB 8 -#define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100 - -#define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008 -#define RX_ATTENTION_SA_IS_VALID_LSB 9 -#define RX_ATTENTION_SA_IS_VALID_MSB 9 -#define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200 - -#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 -#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00 - -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 -#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000 - -#define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008 -#define RX_ATTENTION_RESERVED_2_LSB 14 -#define RX_ATTENTION_RESERVED_2_MSB 30 -#define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000 - -#define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008 -#define RX_ATTENTION_MSDU_DONE_LSB 31 -#define RX_ATTENTION_MSDU_DONE_MSB 31 -#define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000 - -#define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008 -#define RX_ATTENTION_TLV64_PADDING_LSB 32 -#define RX_ATTENTION_TLV64_PADDING_MSB 63 -#define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_flow_search_entry.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_flow_search_entry.h deleted file mode 100644 index 25f1f81c439f..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_flow_search_entry.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FLOW_SEARCH_ENTRY_H_ -#define _RX_FLOW_SEARCH_ENTRY_H_ - -#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 - -struct rx_flow_search_entry { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t src_ip_127_96 : 32; - uint32_t src_ip_95_64 : 32; - uint32_t src_ip_63_32 : 32; - uint32_t src_ip_31_0 : 32; - uint32_t dest_ip_127_96 : 32; - uint32_t dest_ip_95_64 : 32; - uint32_t dest_ip_63_32 : 32; - uint32_t dest_ip_31_0 : 32; - uint32_t src_port : 16, - dest_port : 16; - uint32_t l4_protocol : 8, - valid : 1, - reserved_9 : 4, - service_code : 9, - priority_valid : 1, - use_ppe : 1, - reo_destination_indication : 5, - msdu_drop : 1, - reo_destination_handler : 2; - uint32_t metadata : 32; - uint32_t aggregation_count : 7, - lro_eligible : 1, - msdu_count : 24; - uint32_t msdu_byte_count : 32; - uint32_t timestamp : 32; - uint32_t cumulative_ip_length_pmac1 : 16, - cumulative_ip_length : 16; - uint32_t tcp_sequence_number : 32; -#else - uint32_t src_ip_127_96 : 32; - uint32_t src_ip_95_64 : 32; - uint32_t src_ip_63_32 : 32; - uint32_t src_ip_31_0 : 32; - uint32_t dest_ip_127_96 : 32; - uint32_t dest_ip_95_64 : 32; - uint32_t dest_ip_63_32 : 32; - uint32_t dest_ip_31_0 : 32; - uint32_t dest_port : 16, - src_port : 16; - uint32_t reo_destination_handler : 2, - msdu_drop : 1, - reo_destination_indication : 5, - use_ppe : 1, - priority_valid : 1, - service_code : 9, - reserved_9 : 4, - valid : 1, - l4_protocol : 8; - uint32_t metadata : 32; - uint32_t msdu_count : 24, - lro_eligible : 1, - aggregation_count : 7; - uint32_t msdu_byte_count : 32; - uint32_t timestamp : 32; - uint32_t cumulative_ip_length : 16, - cumulative_ip_length_pmac1 : 16; - uint32_t tcp_sequence_number : 32; -#endif -}; - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15 -#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff - -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000 - -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7 -#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff - -#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8 -#define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8 -#define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100 - -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 12 -#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x00001e00 - -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB 13 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB 21 -#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK 0x003fe000 - -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB 22 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB 22 -#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK 0x00400000 - -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23 -#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000 - -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29 -#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000 - -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000 - -#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028 -#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6 -#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f - -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7 -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7 -#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8 -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00 - -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff - -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET 0x00000038 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB 15 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK 0x0000ffff - -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 - -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0 -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31 -#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_1k_bitmap_ack.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_1k_bitmap_ack.h deleted file mode 100644 index a43548b14a07..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_1k_bitmap_ack.h +++ /dev/null @@ -1,362 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_1K_BITMAP_ACK_H_ -#define _RX_FRAME_1K_BITMAP_ACK_H_ - -#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38 - -#define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19 - -struct rx_frame_1k_bitmap_ack { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reserved_0a : 5, - ba_bitmap_size : 2, - gen_mlo_notification : 1, - reserved_0b : 2, - ba_tid : 4, - sta_full_aid : 13, - reserved_0c : 5; - uint32_t mlo_sta_id : 10, - ba_size_1024_allowed : 1, - ba_size_512_allowed : 1, - reserved_1a : 20; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_ctrl : 16, - ba_ts_seq : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; - uint32_t ba_ts_bitmap_287_256 : 32; - uint32_t ba_ts_bitmap_319_288 : 32; - uint32_t ba_ts_bitmap_351_320 : 32; - uint32_t ba_ts_bitmap_383_352 : 32; - uint32_t ba_ts_bitmap_415_384 : 32; - uint32_t ba_ts_bitmap_447_416 : 32; - uint32_t ba_ts_bitmap_479_448 : 32; - uint32_t ba_ts_bitmap_511_480 : 32; - uint32_t ba_ts_bitmap_543_512 : 32; - uint32_t ba_ts_bitmap_575_544 : 32; - uint32_t ba_ts_bitmap_607_576 : 32; - uint32_t ba_ts_bitmap_639_608 : 32; - uint32_t ba_ts_bitmap_671_640 : 32; - uint32_t ba_ts_bitmap_703_672 : 32; - uint32_t ba_ts_bitmap_735_704 : 32; - uint32_t ba_ts_bitmap_767_736 : 32; - uint32_t ba_ts_bitmap_799_768 : 32; - uint32_t ba_ts_bitmap_831_800 : 32; - uint32_t ba_ts_bitmap_863_832 : 32; - uint32_t ba_ts_bitmap_895_864 : 32; - uint32_t ba_ts_bitmap_927_896 : 32; - uint32_t ba_ts_bitmap_959_928 : 32; - uint32_t ba_ts_bitmap_991_960 : 32; - uint32_t ba_ts_bitmap_1023_992 : 32; -#else - uint32_t reserved_0c : 5, - sta_full_aid : 13, - ba_tid : 4, - reserved_0b : 2, - gen_mlo_notification : 1, - ba_bitmap_size : 2, - reserved_0a : 5; - uint32_t reserved_1a : 20, - ba_size_512_allowed : 1, - ba_size_1024_allowed : 1, - mlo_sta_id : 10; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_seq : 16, - ba_ts_ctrl : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; - uint32_t ba_ts_bitmap_287_256 : 32; - uint32_t ba_ts_bitmap_319_288 : 32; - uint32_t ba_ts_bitmap_351_320 : 32; - uint32_t ba_ts_bitmap_383_352 : 32; - uint32_t ba_ts_bitmap_415_384 : 32; - uint32_t ba_ts_bitmap_447_416 : 32; - uint32_t ba_ts_bitmap_479_448 : 32; - uint32_t ba_ts_bitmap_511_480 : 32; - uint32_t ba_ts_bitmap_543_512 : 32; - uint32_t ba_ts_bitmap_575_544 : 32; - uint32_t ba_ts_bitmap_607_576 : 32; - uint32_t ba_ts_bitmap_639_608 : 32; - uint32_t ba_ts_bitmap_671_640 : 32; - uint32_t ba_ts_bitmap_703_672 : 32; - uint32_t ba_ts_bitmap_735_704 : 32; - uint32_t ba_ts_bitmap_767_736 : 32; - uint32_t ba_ts_bitmap_799_768 : 32; - uint32_t ba_ts_bitmap_831_800 : 32; - uint32_t ba_ts_bitmap_863_832 : 32; - uint32_t ba_ts_bitmap_895_864 : 32; - uint32_t ba_ts_bitmap_927_896 : 32; - uint32_t ba_ts_bitmap_959_928 : 32; - uint32_t ba_ts_bitmap_991_960 : 32; - uint32_t ba_ts_bitmap_1023_992 : 32; -#endif -}; - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x000000000000001f - -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 -#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 - -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB 7 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB 7 -#define RX_FRAME_1K_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK 0x0000000000000080 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 8 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x0000000000000300 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 -#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 - -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 -#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0x00000000f8000000 - -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MSB 41 -#define RX_FRAME_1K_BITMAP_ACK_MLO_STA_ID_MASK 0x000003ff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB 42 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB 42 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK 0x0000040000000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB 43 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB 43 -#define RX_FRAME_1K_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK 0x0000080000000000 - -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_LSB 44 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_RESERVED_1A_MASK 0xfffff00000000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 47 -#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 48 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 47 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 48 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff000000000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000020 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000028 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000030 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x0000000000000038 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x0000000000000038 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000000000000040 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x0000000000000040 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x0000000000000048 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x0000000000000048 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000000000000050 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x0000000000000050 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x0000000000000058 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x0000000000000058 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000000000000060 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x0000000000000060 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x0000000000000068 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x0000000000000068 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000000000000070 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x0000000000000070 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x0000000000000078 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x0000000000000078 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000000000000080 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x0000000000000080 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x0000000000000088 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x0000000000000088 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0xffffffff00000000 - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000000000000090 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 0 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 31 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0x00000000ffffffff - -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x0000000000000090 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 32 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 63 -#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_bitmap_ack.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_bitmap_ack.h deleted file mode 100644 index 0b68486b038e..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_bitmap_ack.h +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_BITMAP_ACK_H_ -#define _RX_FRAME_BITMAP_ACK_H_ - -#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14 - -#define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7 - -struct rx_frame_bitmap_ack { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t no_bitmap_available : 1, - explicit_ack : 1, - explict_ack_type : 3, - ba_bitmap_size : 2, - gen_mlo_notification : 1, - reserved_0a : 2, - ba_tid : 4, - sta_full_aid : 13, - reserved_0b : 5; - uint32_t mlo_sta_id : 10, - ba_size_1024_allowed : 1, - ba_size_512_allowed : 1, - ba_size_256_allowed : 1, - ba_size_128_allowed : 1, - ba_size_64_allowed : 1, - ba_size_32_allowed : 1, - reserved_1a : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_ctrl : 16, - ba_ts_seq : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; -#else - uint32_t reserved_0b : 5, - sta_full_aid : 13, - ba_tid : 4, - reserved_0a : 2, - gen_mlo_notification : 1, - ba_bitmap_size : 2, - explict_ack_type : 3, - explicit_ack : 1, - no_bitmap_available : 1; - uint32_t reserved_1a : 16, - ba_size_32_allowed : 1, - ba_size_64_allowed : 1, - ba_size_128_allowed : 1, - ba_size_256_allowed : 1, - ba_size_512_allowed : 1, - ba_size_1024_allowed : 1, - mlo_sta_id : 10; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ba_ts_seq : 16, - ba_ts_ctrl : 16; - uint32_t ba_ts_bitmap_31_0 : 32; - uint32_t ba_ts_bitmap_63_32 : 32; - uint32_t ba_ts_bitmap_95_64 : 32; - uint32_t ba_ts_bitmap_127_96 : 32; - uint32_t ba_ts_bitmap_159_128 : 32; - uint32_t ba_ts_bitmap_191_160 : 32; - uint32_t ba_ts_bitmap_223_192 : 32; - uint32_t ba_ts_bitmap_255_224 : 32; -#endif -}; - -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 -#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x0000000000000001 - -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 -#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x0000000000000002 - -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 -#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x000000000000001c - -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 -#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 - -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_LSB 7 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MSB 7 -#define RX_FRAME_BITMAP_ACK_GEN_MLO_NOTIFICATION_MASK 0x0000000000000080 - -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 8 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 -#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x0000000000000300 - -#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 -#define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 -#define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 - -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 -#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 - -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 -#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0x00000000f8000000 - -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_LSB 32 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MSB 41 -#define RX_FRAME_BITMAP_ACK_MLO_STA_ID_MASK 0x000003ff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_LSB 42 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MSB 42 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_1024_ALLOWED_MASK 0x0000040000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_LSB 43 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MSB 43 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_512_ALLOWED_MASK 0x0000080000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_LSB 44 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MSB 44 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_256_ALLOWED_MASK 0x0000100000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_LSB 45 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MSB 45 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_128_ALLOWED_MASK 0x0000200000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_LSB 46 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MSB 46 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_64_ALLOWED_MASK 0x0000400000000000 - -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_LSB 47 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MSB 47 -#define RX_FRAME_BITMAP_ACK_BA_SIZE_32_ALLOWED_MASK 0x0000800000000000 - -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_LSB 48 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MSB 63 -#define RX_FRAME_BITMAP_ACK_RESERVED_1A_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 0 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 31 -#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 32 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 47 -#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 48 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 63 -#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 0 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 31 -#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 47 -#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 48 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff000000000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000020 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000028 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff00000000 - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000030 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0x00000000ffffffff - -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 32 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 63 -#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_bitmap_req.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_bitmap_req.h deleted file mode 100644 index 24f8ddd1c57c..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_frame_bitmap_req.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_FRAME_BITMAP_REQ_H_ -#define _RX_FRAME_BITMAP_REQ_H_ - -#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 2 - -#define NUM_OF_QWORDS_RX_FRAME_BITMAP_REQ 1 - -struct rx_frame_bitmap_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t explicit_user_request : 1, - user_request_type : 1, - user_number : 6, - sw_peer_id : 16, - tid_specific_request : 1, - requested_tid : 4, - reserved_0 : 3; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0 : 3, - requested_tid : 4, - tid_specific_request : 1, - sw_peer_id : 16, - user_number : 6, - user_request_type : 1, - explicit_user_request : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB 0 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB 0 -#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK 0x0000000000000001 - -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB 1 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB 1 -#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK 0x0000000000000002 - -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB 2 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB 7 -#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK 0x00000000000000fc - -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB 8 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB 23 -#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK 0x0000000000ffff00 - -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB 24 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB 24 -#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK 0x0000000001000000 - -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB 25 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB 28 -#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK 0x000000001e000000 - -#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB 29 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB 31 -#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK 0x00000000e0000000 - -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_LSB 32 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MSB 63 -#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_location_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_location_info.h deleted file mode 100644 index cfd6a734f511..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_location_info.h +++ /dev/null @@ -1,453 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_LOCATION_INFO_H_ -#define _RX_LOCATION_INFO_H_ - -#define NUM_OF_DWORDS_RX_LOCATION_INFO 28 - -struct rx_location_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_location_info_valid : 1, - rtt_hw_ifft_mode : 1, - __reserved_g_0083 : 2, - reserved_0 : 4, - rtt_num_fac : 8, - rtt_rx_chain_mask : 8, - rtt_num_streams : 8; - uint32_t rtt_first_selected_chain : 8, - rtt_second_selected_chain : 8, - rtt_cfr_status : 8, - rtt_cir_status : 8; - uint32_t rtt_che_buffer_pointer_low32 : 32; - uint32_t rtt_che_buffer_pointer_high8 : 8, - reserved_3 : 8, - rtt_pkt_bw_vht : 4, - rtt_pkt_bw_leg : 4, - rtt_mcs_rate : 8; - uint32_t rtt_cfo_measurement : 16, - rtt_preamble_type : 8, - rtt_gi_type : 8; - uint32_t rx_start_ts : 32; - uint32_t rx_start_ts_upper : 32; - uint32_t rx_end_ts : 32; - uint32_t gain_chain0 : 16, - gain_chain1 : 16; - uint32_t gain_chain2 : 16, - gain_chain3 : 16; - uint32_t gain_report_status : 8, - rtt_timing_backoff_sel : 8, - rtt_fac_combined : 16; - uint32_t rtt_fac_0 : 16, - rtt_fac_1 : 16; - uint32_t rtt_fac_2 : 16, - rtt_fac_3 : 16; - uint32_t rtt_fac_4 : 16, - rtt_fac_5 : 16; - uint32_t rtt_fac_6 : 16, - rtt_fac_7 : 16; - uint32_t rtt_fac_8 : 16, - rtt_fac_9 : 16; - uint32_t rtt_fac_10 : 16, - rtt_fac_11 : 16; - uint32_t rtt_fac_12 : 16, - rtt_fac_13 : 16; - uint32_t rtt_fac_14 : 16, - rtt_fac_15 : 16; - uint32_t rtt_fac_16 : 16, - rtt_fac_17 : 16; - uint32_t rtt_fac_18 : 16, - rtt_fac_19 : 16; - uint32_t rtt_fac_20 : 16, - rtt_fac_21 : 16; - uint32_t rtt_fac_22 : 16, - rtt_fac_23 : 16; - uint32_t rtt_fac_24 : 16, - rtt_fac_25 : 16; - uint32_t rtt_fac_26 : 16, - rtt_fac_27 : 16; - uint32_t rtt_fac_28 : 16, - rtt_fac_29 : 16; - uint32_t rtt_fac_30 : 16, - rtt_fac_31 : 16; - uint32_t reserved_27a : 32; -#else - uint32_t rtt_num_streams : 8, - rtt_rx_chain_mask : 8, - rtt_num_fac : 8, - reserved_0 : 4, - __reserved_g_0083 : 2, - rtt_hw_ifft_mode : 1, - rx_location_info_valid : 1; - uint32_t rtt_cir_status : 8, - rtt_cfr_status : 8, - rtt_second_selected_chain : 8, - rtt_first_selected_chain : 8; - uint32_t rtt_che_buffer_pointer_low32 : 32; - uint32_t rtt_mcs_rate : 8, - rtt_pkt_bw_leg : 4, - rtt_pkt_bw_vht : 4, - reserved_3 : 8, - rtt_che_buffer_pointer_high8 : 8; - uint32_t rtt_gi_type : 8, - rtt_preamble_type : 8, - rtt_cfo_measurement : 16; - uint32_t rx_start_ts : 32; - uint32_t rx_start_ts_upper : 32; - uint32_t rx_end_ts : 32; - uint32_t gain_chain1 : 16, - gain_chain0 : 16; - uint32_t gain_chain3 : 16, - gain_chain2 : 16; - uint32_t rtt_fac_combined : 16, - rtt_timing_backoff_sel : 8, - gain_report_status : 8; - uint32_t rtt_fac_1 : 16, - rtt_fac_0 : 16; - uint32_t rtt_fac_3 : 16, - rtt_fac_2 : 16; - uint32_t rtt_fac_5 : 16, - rtt_fac_4 : 16; - uint32_t rtt_fac_7 : 16, - rtt_fac_6 : 16; - uint32_t rtt_fac_9 : 16, - rtt_fac_8 : 16; - uint32_t rtt_fac_11 : 16, - rtt_fac_10 : 16; - uint32_t rtt_fac_13 : 16, - rtt_fac_12 : 16; - uint32_t rtt_fac_15 : 16, - rtt_fac_14 : 16; - uint32_t rtt_fac_17 : 16, - rtt_fac_16 : 16; - uint32_t rtt_fac_19 : 16, - rtt_fac_18 : 16; - uint32_t rtt_fac_21 : 16, - rtt_fac_20 : 16; - uint32_t rtt_fac_23 : 16, - rtt_fac_22 : 16; - uint32_t rtt_fac_25 : 16, - rtt_fac_24 : 16; - uint32_t rtt_fac_27 : 16, - rtt_fac_26 : 16; - uint32_t rtt_fac_29 : 16, - rtt_fac_28 : 16; - uint32_t rtt_fac_31 : 16, - rtt_fac_30 : 16; - uint32_t reserved_27a : 32; -#endif -}; - -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB 0 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB 0 -#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK 0x00000001 - -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB 1 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB 1 -#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK 0x00000002 - -#define RX_LOCATION_INFO_RESERVED_0_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RESERVED_0_LSB 4 -#define RX_LOCATION_INFO_RESERVED_0_MSB 7 -#define RX_LOCATION_INFO_RESERVED_0_MASK 0x000000f0 - -#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB 8 -#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB 15 -#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB 16 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB 23 -#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET 0x00000000 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB 24 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB 31 -#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB 0 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB 7 -#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff - -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB 8 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB 15 -#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB 16 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB 23 -#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET 0x00000004 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB 24 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB 31 -#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff - -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7 -#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff - -#define RX_LOCATION_INFO_RESERVED_3_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RESERVED_3_LSB 8 -#define RX_LOCATION_INFO_RESERVED_3_MSB 15 -#define RX_LOCATION_INFO_RESERVED_3_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB 16 -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB 19 -#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK 0x000f0000 - -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB 20 -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB 23 -#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK 0x00f00000 - -#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET 0x0000000c -#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB 24 -#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB 31 -#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK 0xff000000 - -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB 0 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB 15 -#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB 16 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB 23 -#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK 0x00ff0000 - -#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET 0x00000010 -#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB 24 -#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB 31 -#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK 0xff000000 - -#define RX_LOCATION_INFO_RX_START_TS_OFFSET 0x00000014 -#define RX_LOCATION_INFO_RX_START_TS_LSB 0 -#define RX_LOCATION_INFO_RX_START_TS_MSB 31 -#define RX_LOCATION_INFO_RX_START_TS_MASK 0xffffffff - -#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET 0x00000018 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB 0 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB 31 -#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK 0xffffffff - -#define RX_LOCATION_INFO_RX_END_TS_OFFSET 0x0000001c -#define RX_LOCATION_INFO_RX_END_TS_LSB 0 -#define RX_LOCATION_INFO_RX_END_TS_MSB 31 -#define RX_LOCATION_INFO_RX_END_TS_MASK 0xffffffff - -#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET 0x00000020 -#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB 0 -#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB 15 -#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK 0x0000ffff - -#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET 0x00000020 -#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB 16 -#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB 31 -#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK 0xffff0000 - -#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET 0x00000024 -#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB 0 -#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB 15 -#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK 0x0000ffff - -#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET 0x00000024 -#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB 16 -#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB 31 -#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK 0xffff0000 - -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET 0x00000028 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB 0 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB 7 -#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK 0x000000ff - -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB 8 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB 15 -#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00 - -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET 0x00000028 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET 0x0000002c -#define RX_LOCATION_INFO_RTT_FAC_0_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_0_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_0_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET 0x0000002c -#define RX_LOCATION_INFO_RTT_FAC_1_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_1_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_1_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET 0x00000030 -#define RX_LOCATION_INFO_RTT_FAC_2_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_2_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_2_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET 0x00000030 -#define RX_LOCATION_INFO_RTT_FAC_3_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_3_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_3_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET 0x00000034 -#define RX_LOCATION_INFO_RTT_FAC_4_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_4_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_4_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET 0x00000034 -#define RX_LOCATION_INFO_RTT_FAC_5_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_5_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_5_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET 0x00000038 -#define RX_LOCATION_INFO_RTT_FAC_6_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_6_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_6_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET 0x00000038 -#define RX_LOCATION_INFO_RTT_FAC_7_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_7_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_7_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET 0x0000003c -#define RX_LOCATION_INFO_RTT_FAC_8_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_8_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_8_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET 0x0000003c -#define RX_LOCATION_INFO_RTT_FAC_9_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_9_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_9_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET 0x00000040 -#define RX_LOCATION_INFO_RTT_FAC_10_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_10_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_10_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET 0x00000040 -#define RX_LOCATION_INFO_RTT_FAC_11_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_11_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_11_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET 0x00000044 -#define RX_LOCATION_INFO_RTT_FAC_12_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_12_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_12_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET 0x00000044 -#define RX_LOCATION_INFO_RTT_FAC_13_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_13_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_13_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET 0x00000048 -#define RX_LOCATION_INFO_RTT_FAC_14_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_14_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_14_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET 0x00000048 -#define RX_LOCATION_INFO_RTT_FAC_15_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_15_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_15_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET 0x0000004c -#define RX_LOCATION_INFO_RTT_FAC_16_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_16_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_16_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET 0x0000004c -#define RX_LOCATION_INFO_RTT_FAC_17_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_17_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_17_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET 0x00000050 -#define RX_LOCATION_INFO_RTT_FAC_18_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_18_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_18_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET 0x00000050 -#define RX_LOCATION_INFO_RTT_FAC_19_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_19_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_19_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET 0x00000054 -#define RX_LOCATION_INFO_RTT_FAC_20_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_20_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_20_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET 0x00000054 -#define RX_LOCATION_INFO_RTT_FAC_21_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_21_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_21_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET 0x00000058 -#define RX_LOCATION_INFO_RTT_FAC_22_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_22_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_22_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET 0x00000058 -#define RX_LOCATION_INFO_RTT_FAC_23_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_23_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_23_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET 0x0000005c -#define RX_LOCATION_INFO_RTT_FAC_24_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_24_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_24_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET 0x0000005c -#define RX_LOCATION_INFO_RTT_FAC_25_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_25_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_25_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET 0x00000060 -#define RX_LOCATION_INFO_RTT_FAC_26_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_26_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_26_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET 0x00000060 -#define RX_LOCATION_INFO_RTT_FAC_27_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_27_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_27_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET 0x00000064 -#define RX_LOCATION_INFO_RTT_FAC_28_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_28_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_28_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET 0x00000064 -#define RX_LOCATION_INFO_RTT_FAC_29_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_29_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_29_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET 0x00000068 -#define RX_LOCATION_INFO_RTT_FAC_30_LSB 0 -#define RX_LOCATION_INFO_RTT_FAC_30_MSB 15 -#define RX_LOCATION_INFO_RTT_FAC_30_MASK 0x0000ffff - -#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET 0x00000068 -#define RX_LOCATION_INFO_RTT_FAC_31_LSB 16 -#define RX_LOCATION_INFO_RTT_FAC_31_MSB 31 -#define RX_LOCATION_INFO_RTT_FAC_31_MASK 0xffff0000 - -#define RX_LOCATION_INFO_RESERVED_27A_OFFSET 0x0000006c -#define RX_LOCATION_INFO_RESERVED_27A_LSB 0 -#define RX_LOCATION_INFO_RESERVED_27A_MSB 31 -#define RX_LOCATION_INFO_RESERVED_27A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_desc_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_desc_info.h deleted file mode 100644 index 30f538fb1228..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_desc_info.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_DESC_INFO_H_ -#define _RX_MPDU_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 - -struct rx_mpdu_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t msdu_count : 8, - fragment_flag : 1, - mpdu_retry_bit : 1, - ampdu_flag : 1, - bar_frame : 1, - pn_fields_contain_valid_info : 1, - raw_mpdu : 1, - more_fragment_flag : 1, - src_info : 12, - mpdu_qos_control_valid : 1, - tid : 4; - uint32_t peer_meta_data : 32; -#else - uint32_t tid : 4, - mpdu_qos_control_valid : 1, - src_info : 12, - more_fragment_flag : 1, - raw_mpdu : 1, - pn_fields_contain_valid_info : 1, - bar_frame : 1, - ampdu_flag : 1, - mpdu_retry_bit : 1, - fragment_flag : 1, - msdu_count : 8; - uint32_t peer_meta_data : 32; -#endif -}; - -#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB 7 -#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK 0x000000ff - -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB 8 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB 8 -#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK 0x00000100 - -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB 9 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB 9 -#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK 0x00000200 - -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB 10 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB 10 -#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK 0x00000400 - -#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB 11 -#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB 11 -#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK 0x00000800 - -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB 13 -#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB 13 -#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK 0x00002000 - -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_SRC_INFO_LSB 15 -#define RX_MPDU_DESC_INFO_SRC_INFO_MSB 26 -#define RX_MPDU_DESC_INFO_SRC_INFO_MASK 0x07ff8000 - -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB 27 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB 27 -#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define RX_MPDU_DESC_INFO_TID_OFFSET 0x00000000 -#define RX_MPDU_DESC_INFO_TID_LSB 28 -#define RX_MPDU_DESC_INFO_TID_MSB 31 -#define RX_MPDU_DESC_INFO_TID_MASK 0xf0000000 - -#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET 0x00000004 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB 0 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB 31 -#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_details.h deleted file mode 100644 index d2d96a0a9996..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_details.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_DETAILS_H_ -#define _RX_MPDU_DETAILS_H_ - -#include "rx_mpdu_ext_desc_info.h" -#include "rx_mpdu_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MPDU_DETAILS 6 - -struct rx_mpdu_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info msdu_link_desc_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_mpdu_ext_desc_info rx_mpdu_ext_desc_info_details; -#else - struct buffer_addr_info msdu_link_desc_addr_info; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_mpdu_ext_desc_info rx_mpdu_ext_desc_info_details; -#endif -}; - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_OFFSET 0x00000010 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_LSB 0 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MSB 15 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_47_32_MASK 0x0000ffff - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_LSB 16 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MSB 17 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_PN_127_48_INFO_MASK 0x00030000 - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_LSB 18 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MSB 21 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_LSB 22 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MSB 31 -#define RX_MPDU_DETAILS_RX_MPDU_EXT_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_end.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_end.h deleted file mode 100644 index dc54ea129fdd..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_end.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_END_H_ -#define _RX_MPDU_END_H_ - -#define NUM_OF_DWORDS_RX_MPDU_END 4 - -#define NUM_OF_QWORDS_RX_MPDU_END 2 - -struct rx_mpdu_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t reserved_1a : 9, - cfp_mic_err : 1, - cfp_pn_chk_err : 1, - unsup_ktype_short_frame : 1, - rx_in_tx_decrypt_byp : 1, - overflow_err : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - pn_fields_contain_valid_info : 1, - fcs_err : 1, - msdu_length_err : 1, - reserved1c : 6, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - ifcs_present : 1; - uint32_t mpdu_crc_ok_intermediate_fcs : 1, - mpdu_length_intermediate_fcs : 14, - rxpcu_mgmt_sequence_nr_valid : 1, - rxpcu_mgmt_sequence_nr : 16; - uint32_t __reserved_g_0002 : 32; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t ifcs_present : 1, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - reserved1c : 6, - msdu_length_err : 1, - fcs_err : 1, - pn_fields_contain_valid_info : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - overflow_err : 1, - rx_in_tx_decrypt_byp : 1, - unsup_ktype_short_frame : 1, - cfp_pn_chk_err : 1, - cfp_mic_err : 1, - reserved_1a : 9; - uint32_t rxpcu_mgmt_sequence_nr : 16, - rxpcu_mgmt_sequence_nr_valid : 1, - mpdu_length_intermediate_fcs : 14, - mpdu_crc_ok_intermediate_fcs : 1; - uint32_t __reserved_g_0002 : 32; -#endif -}; - -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED_0_LSB 9 -#define RX_MPDU_END_RESERVED_0_MSB 15 -#define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MPDU_END_PHY_PPDU_ID_LSB 16 -#define RX_MPDU_END_PHY_PPDU_ID_MSB 31 -#define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED_1A_LSB 32 -#define RX_MPDU_END_RESERVED_1A_MSB 40 -#define RX_MPDU_END_RESERVED_1A_MASK 0x000001ff00000000 - -#define RX_MPDU_END_CFP_MIC_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_CFP_MIC_ERR_LSB 41 -#define RX_MPDU_END_CFP_MIC_ERR_MSB 41 -#define RX_MPDU_END_CFP_MIC_ERR_MASK 0x0000020000000000 - -#define RX_MPDU_END_CFP_PN_CHK_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_CFP_PN_CHK_ERR_LSB 42 -#define RX_MPDU_END_CFP_PN_CHK_ERR_MSB 42 -#define RX_MPDU_END_CFP_PN_CHK_ERR_MASK 0x0000040000000000 - -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43 -#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000 - -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44 -#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000 - -#define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_OVERFLOW_ERR_LSB 45 -#define RX_MPDU_END_OVERFLOW_ERR_MSB 45 -#define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000 - -#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46 -#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46 -#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000 - -#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_TKIP_MIC_ERR_LSB 47 -#define RX_MPDU_END_TKIP_MIC_ERR_MSB 47 -#define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000 - -#define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_DECRYPT_ERR_LSB 48 -#define RX_MPDU_END_DECRYPT_ERR_MSB 48 -#define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000 - -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49 -#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000 - -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50 -#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000 - -#define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_FCS_ERR_LSB 51 -#define RX_MPDU_END_FCS_ERR_MSB 51 -#define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000 - -#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 -#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52 -#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52 -#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000 - -#define RX_MPDU_END_RESERVED1C_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RESERVED1C_LSB 53 -#define RX_MPDU_END_RESERVED1C_MSB 58 -#define RX_MPDU_END_RESERVED1C_MASK 0x07e0000000000000 - -#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61 -#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000 - -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62 -#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000 - -#define RX_MPDU_END_IFCS_PRESENT_OFFSET 0x0000000000000000 -#define RX_MPDU_END_IFCS_PRESENT_LSB 63 -#define RX_MPDU_END_IFCS_PRESENT_MSB 63 -#define RX_MPDU_END_IFCS_PRESENT_MASK 0x8000000000000000 - -#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_OFFSET 0x0000000000000008 -#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_LSB 0 -#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_MSB 0 -#define RX_MPDU_END_MPDU_CRC_OK_INTERMEDIATE_FCS_MASK 0x0000000000000001 - -#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_OFFSET 0x0000000000000008 -#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_LSB 1 -#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_MSB 14 -#define RX_MPDU_END_MPDU_LENGTH_INTERMEDIATE_FCS_MASK 0x0000000000007ffe - -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000 - -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 -#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_ext_desc_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_ext_desc_info.h deleted file mode 100644 index 83f4df333c88..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_ext_desc_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_EXT_DESC_INFO_H_ -#define _RX_MPDU_EXT_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MPDU_EXT_DESC_INFO 2 - -struct rx_mpdu_ext_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pn_31_0 : 32; - uint32_t pn_47_32 : 16, - pn_127_48_info : 2, - msdu_link_desc_index : 4, - reserved_1a : 10; -#else - uint32_t pn_31_0 : 32; - uint32_t reserved_1a : 10, - msdu_link_desc_index : 4, - pn_127_48_info : 2, - pn_47_32 : 16; -#endif -}; - -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_OFFSET 0x00000000 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_LSB 0 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MSB 31 -#define RX_MPDU_EXT_DESC_INFO_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_LSB 0 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MSB 15 -#define RX_MPDU_EXT_DESC_INFO_PN_47_32_MASK 0x0000ffff - -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_LSB 16 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MSB 17 -#define RX_MPDU_EXT_DESC_INFO_PN_127_48_INFO_MASK 0x00030000 - -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_LSB 18 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MSB 21 -#define RX_MPDU_EXT_DESC_INFO_MSDU_LINK_DESC_INDEX_MASK 0x003c0000 - -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_LSB 22 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MSB 31 -#define RX_MPDU_EXT_DESC_INFO_RESERVED_1A_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_info.h deleted file mode 100644 index d76b47b7a712..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_info.h +++ /dev/null @@ -1,972 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_INFO_H_ -#define _RX_MPDU_INFO_H_ - -#include "rxpt_classify_info.h" -#define NUM_OF_DWORDS_RX_MPDU_INFO 30 - -struct rx_mpdu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rxpt_classify_info rxpt_classify_info_details; - uint32_t epd_en : 1, - all_frames_shall_be_encrypted : 1, - encrypt_type : 4, - wep_key_width_for_variable_key : 2, - __reserved_g_0003 : 2, - bssid_hit : 1, - bssid_number : 4, - tid : 4, - reserved_7a : 13; - uint32_t rx_reo_queue_desc_addr_31_0 : 32; - uint32_t rx_reo_queue_desc_addr_39_32 : 8, - receive_queue_number : 16, - pre_delim_err_warning : 1, - first_delim_err : 1, - reserved_2a : 6; - uint32_t pn_31_0 : 32; - uint32_t pn_63_32 : 32; - uint32_t pn_95_64 : 32; - uint32_t pn_127_96 : 32; - uint32_t mpdu_frame_control_valid : 1, - mpdu_duration_valid : 1, - mac_addr_ad1_valid : 1, - mac_addr_ad2_valid : 1, - mac_addr_ad3_valid : 1, - mac_addr_ad4_valid : 1, - mpdu_sequence_control_valid : 1, - mpdu_qos_control_valid : 1, - mpdu_ht_control_valid : 1, - frame_encryption_info_valid : 1, - mpdu_fragment_number : 4, - more_fragment_flag : 1, - protected_cbf_cqi : 1, - fr_ds : 1, - to_ds : 1, - encrypted : 1, - mpdu_retry : 1, - mpdu_sequence_number : 12; - uint32_t peer_meta_data : 32; - uint32_t ast_index : 16, - sw_peer_id : 16; - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - ndp_frame : 1, - phy_err : 1, - phy_err_during_mpdu_header : 1, - protocol_version_err : 1, - ast_based_lookup_valid : 1, - __reserved_g_0005 : 1, - __reserved_g_0086 : 1, - phy_ppdu_id : 16; - uint32_t key_id_octet : 8, - new_peer_entry : 1, - decrypt_needed : 1, - decap_type : 2, - rx_insert_vlan_c_tag_padding : 1, - rx_insert_vlan_s_tag_padding : 1, - strip_vlan_c_tag_decap : 1, - strip_vlan_s_tag_decap : 1, - pre_delim_count : 12, - ampdu_flag : 1, - bar_frame : 1, - raw_mpdu : 1, - reserved_12 : 1; - uint32_t mpdu_length : 14, - first_mpdu : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - fragment_flag : 1, - order : 1, - u_apsd_trigger : 1, - encrypt_required : 1, - directed : 1, - amsdu_present : 1, - reserved_13 : 1; - uint32_t mpdu_frame_control_field : 16, - mpdu_duration_field : 16; - uint32_t mac_addr_ad1_31_0 : 32; - uint32_t mac_addr_ad1_47_32 : 16, - mac_addr_ad2_15_0 : 16; - uint32_t mac_addr_ad2_47_16 : 32; - uint32_t mac_addr_ad3_31_0 : 32; - uint32_t mac_addr_ad3_47_32 : 16, - mpdu_sequence_control_field : 16; - uint32_t mac_addr_ad4_31_0 : 32; - uint32_t mac_addr_ad4_47_32 : 16, - mpdu_qos_control_field : 16; - uint32_t mpdu_ht_control_field : 32; - uint32_t vdev_id : 8, - service_code : 9, - priority_valid : 1, - src_info : 12, - smr_frame : 1, - __reserved_g_0029 : 1; - uint32_t __reserved_g_0060 : 32; - uint32_t __reserved_g_0057 : 16, - __reserved_g_0059 : 16; - uint32_t __reserved_g_0056 : 32; - uint32_t authorized_to_send_wds : 1, - disallow_mcbc_da_in_unicast_mpdu : 1, - fromtods_00_fnf_check_dis : 1, - fromtods_01_fnf_check_dis : 1, - fromtods_10_fnf_check_dis : 1, - fromtods_11_fnf_check_dis : 1, - rx_misc_config : 3, - a_msdu_fromtods_10_ad3 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_11_ad4 : 2, - multi_link_ds_addr_fromtods_00_raw_en : 1, - multi_link_ds_addr_fromtods_non00_raw_en : 1, - multi_link_ds_addr_ad3_valid : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_ad1_trans_dis : 1, - data_fromtods_00_ad3 : 2, - mgmt_fromtods_00_ad3 : 2, - multi_link_ds_addr_mgmt_en : 1, - multi_link_ds_addr_ctrl_en : 1, - reserved_27a : 5; - uint32_t multi_link_ds_addr_ad3_31_0 : 32; - uint32_t multi_link_ds_addr_ad3_47_32 : 16, - cfp_mic_err : 1, - cfp_pn_chk_err : 1, - reserved_29a : 14; -#else - struct rxpt_classify_info rxpt_classify_info_details; - uint32_t reserved_7a : 13, - tid : 4, - bssid_number : 4, - bssid_hit : 1, - __reserved_g_0003 : 2, - wep_key_width_for_variable_key : 2, - encrypt_type : 4, - all_frames_shall_be_encrypted : 1, - epd_en : 1; - uint32_t rx_reo_queue_desc_addr_31_0 : 32; - uint32_t reserved_2a : 6, - first_delim_err : 1, - pre_delim_err_warning : 1, - receive_queue_number : 16, - rx_reo_queue_desc_addr_39_32 : 8; - uint32_t pn_31_0 : 32; - uint32_t pn_63_32 : 32; - uint32_t pn_95_64 : 32; - uint32_t pn_127_96 : 32; - uint32_t mpdu_sequence_number : 12, - mpdu_retry : 1, - encrypted : 1, - to_ds : 1, - fr_ds : 1, - protected_cbf_cqi : 1, - more_fragment_flag : 1, - mpdu_fragment_number : 4, - frame_encryption_info_valid : 1, - mpdu_ht_control_valid : 1, - mpdu_qos_control_valid : 1, - mpdu_sequence_control_valid : 1, - mac_addr_ad4_valid : 1, - mac_addr_ad3_valid : 1, - mac_addr_ad2_valid : 1, - mac_addr_ad1_valid : 1, - mpdu_duration_valid : 1, - mpdu_frame_control_valid : 1; - uint32_t peer_meta_data : 32; - uint32_t sw_peer_id : 16, - ast_index : 16; - uint32_t phy_ppdu_id : 16, - __reserved_g_0086 : 1, - __reserved_g_0005 : 1, - ast_based_lookup_valid : 1, - protocol_version_err : 1, - phy_err_during_mpdu_header : 1, - phy_err : 1, - ndp_frame : 1, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_12 : 1, - raw_mpdu : 1, - bar_frame : 1, - ampdu_flag : 1, - pre_delim_count : 12, - strip_vlan_s_tag_decap : 1, - strip_vlan_c_tag_decap : 1, - rx_insert_vlan_s_tag_padding : 1, - rx_insert_vlan_c_tag_padding : 1, - decap_type : 2, - decrypt_needed : 1, - new_peer_entry : 1, - key_id_octet : 8; - uint32_t reserved_13 : 1, - amsdu_present : 1, - directed : 1, - encrypt_required : 1, - u_apsd_trigger : 1, - order : 1, - fragment_flag : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - first_mpdu : 1, - mpdu_length : 14; - uint32_t mpdu_duration_field : 16, - mpdu_frame_control_field : 16; - uint32_t mac_addr_ad1_31_0 : 32; - uint32_t mac_addr_ad2_15_0 : 16, - mac_addr_ad1_47_32 : 16; - uint32_t mac_addr_ad2_47_16 : 32; - uint32_t mac_addr_ad3_31_0 : 32; - uint32_t mpdu_sequence_control_field : 16, - mac_addr_ad3_47_32 : 16; - uint32_t mac_addr_ad4_31_0 : 32; - uint32_t mpdu_qos_control_field : 16, - mac_addr_ad4_47_32 : 16; - uint32_t mpdu_ht_control_field : 32; - uint32_t __reserved_g_0029 : 1, - smr_frame : 1, - src_info : 12, - priority_valid : 1, - service_code : 9, - vdev_id : 8; - uint32_t __reserved_g_0060 : 32; - uint32_t __reserved_g_0059 : 16, - __reserved_g_0057 : 16; - uint32_t __reserved_g_0056 : 32; - uint32_t reserved_27a : 5, - multi_link_ds_addr_ctrl_en : 1, - multi_link_ds_addr_mgmt_en : 1, - mgmt_fromtods_00_ad3 : 2, - data_fromtods_00_ad3 : 2, - multi_link_addr_ad1_trans_dis : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_ds_addr_ad3_valid : 1, - multi_link_ds_addr_fromtods_non00_raw_en : 1, - multi_link_ds_addr_fromtods_00_raw_en : 1, - a_msdu_fromtods_11_ad4 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_10_ad3 : 2, - rx_misc_config : 3, - fromtods_11_fnf_check_dis : 1, - fromtods_10_fnf_check_dis : 1, - fromtods_01_fnf_check_dis : 1, - fromtods_00_fnf_check_dis : 1, - disallow_mcbc_da_in_unicast_mpdu : 1, - authorized_to_send_wds : 1; - uint32_t multi_link_ds_addr_ad3_31_0 : 32; - uint32_t reserved_29a : 14, - cfp_pn_chk_err : 1, - cfp_mic_err : 1, - multi_link_ds_addr_ad3_47_32 : 16; -#endif -}; - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x00400000 - -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 -#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xff800000 - -#define RX_MPDU_INFO_EPD_EN_OFFSET 0x00000004 -#define RX_MPDU_INFO_EPD_EN_LSB 0 -#define RX_MPDU_INFO_EPD_EN_MSB 0 -#define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 - -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x00000004 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 -#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 - -#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x00000004 -#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 -#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 -#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c - -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x00000004 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 -#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 - -#define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x00000004 -#define RX_MPDU_INFO_BSSID_HIT_LSB 10 -#define RX_MPDU_INFO_BSSID_HIT_MSB 10 -#define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 - -#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x00000004 -#define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 -#define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 -#define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 - -#define RX_MPDU_INFO_TID_OFFSET 0x00000004 -#define RX_MPDU_INFO_TID_LSB 15 -#define RX_MPDU_INFO_TID_MSB 18 -#define RX_MPDU_INFO_TID_MASK 0x00078000 - -#define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x00000004 -#define RX_MPDU_INFO_RESERVED_7A_LSB 19 -#define RX_MPDU_INFO_RESERVED_7A_MSB 31 -#define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 - -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000008 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000c -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 -#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 -#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 - -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000c -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 -#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 - -#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x0000000c -#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 -#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 -#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 - -#define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x0000000c -#define RX_MPDU_INFO_RESERVED_2A_LSB 26 -#define RX_MPDU_INFO_RESERVED_2A_MSB 31 -#define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 - -#define RX_MPDU_INFO_PN_31_0_OFFSET 0x00000010 -#define RX_MPDU_INFO_PN_31_0_LSB 0 -#define RX_MPDU_INFO_PN_31_0_MSB 31 -#define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000014 -#define RX_MPDU_INFO_PN_63_32_LSB 0 -#define RX_MPDU_INFO_PN_63_32_MSB 31 -#define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000018 -#define RX_MPDU_INFO_PN_95_64_LSB 0 -#define RX_MPDU_INFO_PN_95_64_MSB 31 -#define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff - -#define RX_MPDU_INFO_PN_127_96_OFFSET 0x0000001c -#define RX_MPDU_INFO_PN_127_96_LSB 0 -#define RX_MPDU_INFO_PN_127_96_MSB 31 -#define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff - -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 - -#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 -#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 - -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 -#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 - -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 -#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 - -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 -#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 - -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 -#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 - -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 - -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 - -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 - -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000020 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 -#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 - -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 -#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 - -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000020 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define RX_MPDU_INFO_PROTECTED_CBF_CQI_OFFSET 0x00000020 -#define RX_MPDU_INFO_PROTECTED_CBF_CQI_LSB 15 -#define RX_MPDU_INFO_PROTECTED_CBF_CQI_MSB 15 -#define RX_MPDU_INFO_PROTECTED_CBF_CQI_MASK 0x00008000 - -#define RX_MPDU_INFO_FR_DS_OFFSET 0x00000020 -#define RX_MPDU_INFO_FR_DS_LSB 16 -#define RX_MPDU_INFO_FR_DS_MSB 16 -#define RX_MPDU_INFO_FR_DS_MASK 0x00010000 - -#define RX_MPDU_INFO_TO_DS_OFFSET 0x00000020 -#define RX_MPDU_INFO_TO_DS_LSB 17 -#define RX_MPDU_INFO_TO_DS_MSB 17 -#define RX_MPDU_INFO_TO_DS_MASK 0x00020000 - -#define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x00000020 -#define RX_MPDU_INFO_ENCRYPTED_LSB 18 -#define RX_MPDU_INFO_ENCRYPTED_MSB 18 -#define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 - -#define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_RETRY_LSB 19 -#define RX_MPDU_INFO_MPDU_RETRY_MSB 19 -#define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 - -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 -#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 - -#define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000024 -#define RX_MPDU_INFO_PEER_META_DATA_LSB 0 -#define RX_MPDU_INFO_PEER_META_DATA_MSB 31 -#define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff - -#define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 -#define RX_MPDU_INFO_AST_INDEX_LSB 0 -#define RX_MPDU_INFO_AST_INDEX_MSB 15 -#define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff - -#define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 -#define RX_MPDU_INFO_SW_PEER_ID_LSB 16 -#define RX_MPDU_INFO_SW_PEER_ID_MSB 31 -#define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 - -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000002c -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 - -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x0000002c -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc - -#define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x0000002c -#define RX_MPDU_INFO_NDP_FRAME_LSB 9 -#define RX_MPDU_INFO_NDP_FRAME_MSB 9 -#define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 - -#define RX_MPDU_INFO_PHY_ERR_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_ERR_LSB 10 -#define RX_MPDU_INFO_PHY_ERR_MSB 10 -#define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 - -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 -#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 - -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x0000002c -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 -#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 - -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x0000002c -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 -#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 - -#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x0000002c -#define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 -#define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 -#define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 - -#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 -#define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 -#define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 -#define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff - -#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 -#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 - -#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 -#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 -#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 -#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 - -#define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 -#define RX_MPDU_INFO_DECAP_TYPE_LSB 10 -#define RX_MPDU_INFO_DECAP_TYPE_MSB 11 -#define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 - -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 -#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 - -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 -#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 - -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 -#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 - -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 -#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 - -#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 -#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 - -#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 -#define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 -#define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 -#define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 - -#define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 -#define RX_MPDU_INFO_BAR_FRAME_LSB 29 -#define RX_MPDU_INFO_BAR_FRAME_MSB 29 -#define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 - -#define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 -#define RX_MPDU_INFO_RAW_MPDU_LSB 30 -#define RX_MPDU_INFO_RAW_MPDU_MSB 30 -#define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 - -#define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 -#define RX_MPDU_INFO_RESERVED_12_LSB 31 -#define RX_MPDU_INFO_RESERVED_12_MSB 31 -#define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 - -#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 -#define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 -#define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 -#define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff - -#define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 -#define RX_MPDU_INFO_FIRST_MPDU_LSB 14 -#define RX_MPDU_INFO_FIRST_MPDU_MSB 14 -#define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 - -#define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 -#define RX_MPDU_INFO_MCAST_BCAST_LSB 15 -#define RX_MPDU_INFO_MCAST_BCAST_MSB 15 -#define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 - -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 -#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 - -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 -#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 - -#define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 -#define RX_MPDU_INFO_POWER_MGMT_LSB 18 -#define RX_MPDU_INFO_POWER_MGMT_MSB 18 -#define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 - -#define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 -#define RX_MPDU_INFO_NON_QOS_LSB 19 -#define RX_MPDU_INFO_NON_QOS_MSB 19 -#define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 - -#define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 -#define RX_MPDU_INFO_NULL_DATA_LSB 20 -#define RX_MPDU_INFO_NULL_DATA_MSB 20 -#define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 - -#define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 -#define RX_MPDU_INFO_MGMT_TYPE_LSB 21 -#define RX_MPDU_INFO_MGMT_TYPE_MSB 21 -#define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 - -#define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 -#define RX_MPDU_INFO_CTRL_TYPE_LSB 22 -#define RX_MPDU_INFO_CTRL_TYPE_MSB 22 -#define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 - -#define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 -#define RX_MPDU_INFO_MORE_DATA_LSB 23 -#define RX_MPDU_INFO_MORE_DATA_MSB 23 -#define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 - -#define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 -#define RX_MPDU_INFO_EOSP_LSB 24 -#define RX_MPDU_INFO_EOSP_MSB 24 -#define RX_MPDU_INFO_EOSP_MASK 0x01000000 - -#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 -#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 -#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 -#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 - -#define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 -#define RX_MPDU_INFO_ORDER_LSB 26 -#define RX_MPDU_INFO_ORDER_MSB 26 -#define RX_MPDU_INFO_ORDER_MASK 0x04000000 - -#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 -#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 -#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 -#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 - -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 -#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 - -#define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 -#define RX_MPDU_INFO_DIRECTED_LSB 29 -#define RX_MPDU_INFO_DIRECTED_MSB 29 -#define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 - -#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 -#define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 -#define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 -#define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 - -#define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 -#define RX_MPDU_INFO_RESERVED_13_LSB 31 -#define RX_MPDU_INFO_RESERVED_13_MSB 31 -#define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 - -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 -#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 -#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 -#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 - -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 -#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff - -#define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c -#define RX_MPDU_INFO_VDEV_ID_LSB 0 -#define RX_MPDU_INFO_VDEV_ID_MSB 7 -#define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff - -#define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c -#define RX_MPDU_INFO_SERVICE_CODE_LSB 8 -#define RX_MPDU_INFO_SERVICE_CODE_MSB 16 -#define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 - -#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c -#define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 -#define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 -#define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 - -#define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c -#define RX_MPDU_INFO_SRC_INFO_LSB 18 -#define RX_MPDU_INFO_SRC_INFO_MSB 29 -#define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 - -#define RX_MPDU_INFO_SMR_FRAME_OFFSET 0x0000005c -#define RX_MPDU_INFO_SMR_FRAME_LSB 30 -#define RX_MPDU_INFO_SMR_FRAME_MSB 30 -#define RX_MPDU_INFO_SMR_FRAME_MASK 0x40000000 - -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 -#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 - -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET 0x0000006c -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB 1 -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB 1 -#define RX_MPDU_INFO_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK 0x00000002 - -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_LSB 2 -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MSB 2 -#define RX_MPDU_INFO_FROMTODS_00_FNF_CHECK_DIS_MASK 0x00000004 - -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_LSB 3 -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MSB 3 -#define RX_MPDU_INFO_FROMTODS_01_FNF_CHECK_DIS_MASK 0x00000008 - -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_LSB 4 -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MSB 4 -#define RX_MPDU_INFO_FROMTODS_10_FNF_CHECK_DIS_MASK 0x00000010 - -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_LSB 5 -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MSB 5 -#define RX_MPDU_INFO_FROMTODS_11_FNF_CHECK_DIS_MASK 0x00000020 - -#define RX_MPDU_INFO_RX_MISC_CONFIG_OFFSET 0x0000006c -#define RX_MPDU_INFO_RX_MISC_CONFIG_LSB 6 -#define RX_MPDU_INFO_RX_MISC_CONFIG_MSB 8 -#define RX_MPDU_INFO_RX_MISC_CONFIG_MASK 0x000001c0 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_LSB 9 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MSB 10 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_10_AD3_MASK 0x00000600 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_LSB 11 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MSB 12 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD3_MASK 0x00001800 - -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000006c -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_LSB 13 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MSB 14 -#define RX_MPDU_INFO_A_MSDU_FROMTODS_11_AD4_MASK 0x00006000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_LSB 15 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MSB 15 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MASK 0x00008000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_LSB 16 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MSB 16 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MASK 0x00010000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_LSB 17 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_MSB 17 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_VALID_MASK 0x00020000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 18 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 18 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x00040000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 19 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 19 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x00080000 - -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 20 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 20 -#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x00100000 - -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_LSB 21 -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MSB 22 -#define RX_MPDU_INFO_DATA_FROMTODS_00_AD3_MASK 0x00600000 - -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_OFFSET 0x0000006c -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_LSB 23 -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MSB 24 -#define RX_MPDU_INFO_MGMT_FROMTODS_00_AD3_MASK 0x01800000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_LSB 25 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_MSB 25 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_MGMT_EN_MASK 0x02000000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_OFFSET 0x0000006c -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_LSB 26 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_MSB 26 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_CTRL_EN_MASK 0x04000000 - -#define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c -#define RX_MPDU_INFO_RESERVED_27A_LSB 27 -#define RX_MPDU_INFO_RESERVED_27A_MSB 31 -#define RX_MPDU_INFO_RESERVED_27A_MASK 0xf8000000 - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_OFFSET 0x00000070 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_31_0_MASK 0xffffffff - -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_OFFSET 0x00000074 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_LSB 0 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_MSB 15 -#define RX_MPDU_INFO_MULTI_LINK_DS_ADDR_AD3_47_32_MASK 0x0000ffff - -#define RX_MPDU_INFO_CFP_MIC_ERR_OFFSET 0x00000074 -#define RX_MPDU_INFO_CFP_MIC_ERR_LSB 16 -#define RX_MPDU_INFO_CFP_MIC_ERR_MSB 16 -#define RX_MPDU_INFO_CFP_MIC_ERR_MASK 0x00010000 - -#define RX_MPDU_INFO_CFP_PN_CHK_ERR_OFFSET 0x00000074 -#define RX_MPDU_INFO_CFP_PN_CHK_ERR_LSB 17 -#define RX_MPDU_INFO_CFP_PN_CHK_ERR_MSB 17 -#define RX_MPDU_INFO_CFP_PN_CHK_ERR_MASK 0x00020000 - -#define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 -#define RX_MPDU_INFO_RESERVED_29A_LSB 18 -#define RX_MPDU_INFO_RESERVED_29A_MSB 31 -#define RX_MPDU_INFO_RESERVED_29A_MASK 0xfffc0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_link_ptr.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_link_ptr.h deleted file mode 100644 index e9d7e83a92cc..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_link_ptr.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_LINK_PTR_H_ -#define _RX_MPDU_LINK_PTR_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 - -struct rx_mpdu_link_ptr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info mpdu_link_desc_addr_info; -#else - struct buffer_addr_info mpdu_link_desc_addr_info; -#endif -}; - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_start.h deleted file mode 100644 index fc5029dc2da3..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_mpdu_start.h +++ /dev/null @@ -1,712 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MPDU_START_H_ -#define _RX_MPDU_START_H_ - -#include "rx_mpdu_info.h" -#define NUM_OF_DWORDS_RX_MPDU_START 30 - -#define NUM_OF_QWORDS_RX_MPDU_START 15 - -struct rx_mpdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_mpdu_info rx_mpdu_info_details; -#else - struct rx_mpdu_info rx_mpdu_info_details; -#endif -}; - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x000000000000001f - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x0000000000000060 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x0000000000000080 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x0000000000000400 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x0000000000003800 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x000000000001c000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x0000000000020000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x0000000000040000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x0000000000080000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x0000000000100000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x0000000000200000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x0000000000400000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0x00000000ff800000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x0000000100000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x0000000200000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 38 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x0000040000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x0000780000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK 0x0007800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000000000000000 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff8000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff0000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x0100000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc00000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000000000010 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x0000000000000010 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x0000000000000018 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000000000000018 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x0000000000000001 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB 1 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x0000000000000002 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB 2 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x0000000000000004 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB 3 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x0000000000000008 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB 4 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x0000000000000010 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB 5 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x0000000000000020 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x0000000000000040 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x0000000000000080 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x0000000000003c00 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x0000000000004000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_LSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTECTED_CBF_CQI_MASK 0x0000000000008000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x0000000000010000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB 17 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x0000000000020000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB 18 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x0000000000040000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB 19 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x0000000000080000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x00000000fff00000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000000000020 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000300000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x0000020000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x0000040000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x0000080000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x0000100000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x0000200000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000028 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB 7 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x00000000000000ff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB 8 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x0000000000000100 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB 9 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x0000000000000200 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB 11 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x0000000000000c00 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x0000000000001000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x0000000000002000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB 14 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x0000000000004000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x0000000000008000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB 27 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x000000000fff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB 28 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x0000000010000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB 29 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x0000000020000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB 30 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x0000000040000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x0000000080000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x0000400000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x0000800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x0001000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x0004000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x0008000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x0010000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x0020000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x0040000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x0080000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x0100000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x0400000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x0800000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 60 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB 60 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x1000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x2000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x4000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x0000000000000030 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x8000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000000000000038 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB 15 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x000000000000ffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0x00000000ffff0000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x0000000000000040 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000000000000048 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x0000000000000050 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB 39 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK 0x000000ff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK 0x0001ff0000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB 61 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK 0x3ffc000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_OFFSET 0x0000000000000058 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_LSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_MSB 62 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SMR_FRAME_MASK 0x4000000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK 0x0000000100000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_LSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MSB 33 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DISALLOW_MCBC_DA_IN_UNICAST_MPDU_MASK 0x0000000200000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_LSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MSB 34 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_00_FNF_CHECK_DIS_MASK 0x0000000400000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_LSB 35 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MSB 35 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_01_FNF_CHECK_DIS_MASK 0x0000000800000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_LSB 36 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MSB 36 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_10_FNF_CHECK_DIS_MASK 0x0000001000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_LSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MSB 37 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FROMTODS_11_FNF_CHECK_DIS_MASK 0x0000002000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_LSB 38 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MSB 40 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_MISC_CONFIG_MASK 0x000001c000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_LSB 41 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MSB 42 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_10_AD3_MASK 0x0000060000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_LSB 43 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MSB 44 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD3_MASK 0x0000180000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_LSB 45 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MSB 46 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_A_MSDU_FROMTODS_11_AD4_MASK 0x0000600000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_LSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_00_RAW_EN_MASK 0x0000800000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_FROMTODS_NON00_RAW_EN_MASK 0x0001000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_VALID_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x0004000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 51 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x0008000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 52 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x0010000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_LSB 53 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MSB 54 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DATA_FROMTODS_00_AD3_MASK 0x0060000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_LSB 55 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MSB 56 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_FROMTODS_00_AD3_MASK 0x0180000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_LSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_MSB 57 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_MGMT_EN_MASK 0x0200000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_LSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_MSB 58 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_CTRL_EN_MASK 0x0400000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB 59 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK 0xf800000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_LSB 0 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_MSB 31 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_LSB 32 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_MSB 47 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_DS_ADDR_AD3_47_32_MASK 0x0000ffff00000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_LSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_MSB 48 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_MIC_ERR_MASK 0x0001000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_LSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_MSB 49 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CFP_PN_CHK_ERR_MASK 0x0002000000000000 - -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET 0x0000000000000070 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB 50 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB 63 -#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK 0xfffc000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_desc_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_desc_info.h deleted file mode 100644 index 88569b653b64..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_desc_info.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_DESC_INFO_H_ -#define _RX_MSDU_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 - -struct rx_msdu_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t first_msdu_in_mpdu_flag : 1, - last_msdu_in_mpdu_flag : 1, - msdu_continuation : 1, - msdu_length : 14, - msdu_drop : 1, - sa_is_valid : 1, - da_is_valid : 1, - da_is_mcbc : 1, - l3_header_padding_msb : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - fr_ds : 1, - to_ds : 1, - intra_bss : 1, - dest_chip_id : 2, - decap_format : 2, - __reserved_g_0015 : 1; -#else - uint32_t __reserved_g_0015 : 1, - decap_format : 2, - dest_chip_id : 2, - intra_bss : 1, - to_ds : 1, - fr_ds : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - l3_header_padding_msb : 1, - da_is_mcbc : 1, - da_is_valid : 1, - sa_is_valid : 1, - msdu_drop : 1, - msdu_length : 14, - msdu_continuation : 1, - last_msdu_in_mpdu_flag : 1, - first_msdu_in_mpdu_flag : 1; -#endif -}; - -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 -#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 -#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 -#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 -#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 -#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 -#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_FR_DS_LSB 24 -#define RX_MSDU_DESC_INFO_FR_DS_MSB 24 -#define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 - -#define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_TO_DS_LSB 25 -#define RX_MSDU_DESC_INFO_TO_DS_MSB 25 -#define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 - -#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 -#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 -#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 -#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_details.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_details.h deleted file mode 100644 index 0b763a473ce6..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_details.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_DETAILS_H_ -#define _RX_MSDU_DETAILS_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_msdu_ext_desc_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 - -struct rx_msdu_details { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buffer_addr_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; -#else - struct buffer_addr_info buffer_addr_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; -#endif -}; - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xe0000000 - -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_end.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_end.h deleted file mode 100644 index b05c9896b09a..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_end.h +++ /dev/null @@ -1,1094 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_END_H_ -#define _RX_MSDU_END_H_ - -#define NUM_OF_DWORDS_RX_MSDU_END 32 - -#define NUM_OF_QWORDS_RX_MSDU_END 16 - -struct rx_msdu_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_0 : 7, - phy_ppdu_id : 16; - uint32_t ip_hdr_chksum : 16, - reported_mpdu_length : 14, - reserved_1a : 2; - uint32_t reserved_2a : 8, - cce_super_rule : 6, - cce_classify_not_done_truncate : 1, - cce_classify_not_done_cce_dis : 1, - cumulative_l3_checksum : 16; - uint32_t rule_indication_31_0 : 32; - uint32_t ipv6_options_crc : 32; - uint32_t da_offset : 6, - sa_offset : 6, - da_offset_valid : 1, - sa_offset_valid : 1, - reserved_5a : 2, - l3_type : 16; - uint32_t rule_indication_63_32 : 32; - uint32_t tcp_seq_number : 32; - uint32_t tcp_ack_number : 32; - uint32_t tcp_flag : 9, - lro_eligible : 1, - reserved_9a : 6, - window_size : 16; - uint32_t sa_sw_peer_id : 16, - sa_idx_timeout : 1, - da_idx_timeout : 1, - to_ds : 1, - tid : 4, - sa_is_valid : 1, - da_is_valid : 1, - da_is_mcbc : 1, - l3_header_padding : 2, - first_msdu : 1, - last_msdu : 1, - fr_ds : 1, - ip_chksum_fail_copy : 1; - uint32_t sa_idx : 16, - da_idx_or_sw_peer_id : 16; - uint32_t msdu_drop : 1, - reo_destination_indication : 5, - flow_idx : 20, - use_ppe : 1, - __reserved_g_0003 : 2, - vlan_ctag_stripped : 1, - vlan_stag_stripped : 1, - fragment_flag : 1; - uint32_t fse_metadata : 32; - uint32_t cce_metadata : 16, - tcp_udp_chksum : 16; - uint32_t aggregation_count : 8, - flow_aggregation_continuation : 1, - fisa_timeout : 1, - tcp_udp_chksum_fail_copy : 1, - msdu_limit_error : 1, - flow_idx_timeout : 1, - flow_idx_invalid : 1, - cce_match : 1, - amsdu_parser_error : 1, - cumulative_ip_length : 16; - uint32_t key_id_octet : 8, - reserved_16a : 24; - uint32_t reserved_17a : 6, - service_code : 9, - priority_valid : 1, - intra_bss : 1, - dest_chip_id : 2, - multicast_echo : 1, - wds_learning_event : 1, - wds_roaming_event : 1, - wds_keep_alive_event : 1, - __reserved_g_0015 : 1, - reserved_17b : 8; - uint32_t msdu_length : 14, - stbc : 1, - ipsec_esp : 1, - l3_offset : 7, - ipsec_ah : 1, - l4_offset : 8; - uint32_t msdu_number : 8, - decap_format : 2, - ipv4_proto : 1, - ipv6_proto : 1, - tcp_proto : 1, - udp_proto : 1, - ip_frag : 1, - tcp_only_ack : 1, - da_is_bcast_mcast : 1, - toeplitz_hash_sel : 2, - ip_fixed_header_valid : 1, - ip_extn_header_valid : 1, - tcp_udp_header_valid : 1, - mesh_control_present : 1, - ldpc : 1, - ip4_protocol_ip6_next_header : 8; - uint32_t vlan_ctag_ci : 16, - vlan_stag_ci : 16; - uint32_t peer_meta_data : 32; - uint32_t user_rssi : 8, - pkt_type : 4, - sgi : 2, - rate_mcs : 5, - receive_bandwidth : 3, - reception_type : 3, - mimo_ss_bitmap : 6, - msdu_done_copy : 1; - uint32_t flow_id_toeplitz : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t reserved_28a : 16, - sa_15_0 : 16; - uint32_t sa_47_16 : 32; - uint32_t first_mpdu : 1, - reserved_30a : 1, - mcast_bcast : 1, - ast_index_not_found : 1, - ast_index_timeout : 1, - power_mgmt : 1, - non_qos : 1, - null_data : 1, - mgmt_type : 1, - ctrl_type : 1, - more_data : 1, - eosp : 1, - a_msdu_error : 1, - reserved_30b : 1, - order : 1, - wifi_parser_error : 1, - overflow_err : 1, - msdu_length_err : 1, - tcp_udp_chksum_fail : 1, - ip_chksum_fail : 1, - sa_idx_invalid : 1, - da_idx_invalid : 1, - amsdu_addr_mismatch : 1, - rx_in_tx_decrypt_byp : 1, - encrypt_required : 1, - directed : 1, - buffer_fragment : 1, - mpdu_length_err : 1, - tkip_mic_err : 1, - decrypt_err : 1, - unencrypted_frame_err : 1, - fcs_err : 1; - uint32_t reserved_31a : 10, - decrypt_status_code : 3, - rx_bitmap_not_updated : 1, - ifcs_present : 1, - reserved_31b : 16, - msdu_done : 1; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_1a : 2, - reported_mpdu_length : 14, - ip_hdr_chksum : 16; - uint32_t cumulative_l3_checksum : 16, - cce_classify_not_done_cce_dis : 1, - cce_classify_not_done_truncate : 1, - cce_super_rule : 6, - reserved_2a : 8; - uint32_t rule_indication_31_0 : 32; - uint32_t ipv6_options_crc : 32; - uint32_t l3_type : 16, - reserved_5a : 2, - sa_offset_valid : 1, - da_offset_valid : 1, - sa_offset : 6, - da_offset : 6; - uint32_t rule_indication_63_32 : 32; - uint32_t tcp_seq_number : 32; - uint32_t tcp_ack_number : 32; - uint32_t window_size : 16, - reserved_9a : 6, - lro_eligible : 1, - tcp_flag : 9; - uint32_t ip_chksum_fail_copy : 1, - fr_ds : 1, - last_msdu : 1, - first_msdu : 1, - l3_header_padding : 2, - da_is_mcbc : 1, - da_is_valid : 1, - sa_is_valid : 1, - tid : 4, - to_ds : 1, - da_idx_timeout : 1, - sa_idx_timeout : 1, - sa_sw_peer_id : 16; - uint32_t da_idx_or_sw_peer_id : 16, - sa_idx : 16; - uint32_t fragment_flag : 1, - vlan_stag_stripped : 1, - vlan_ctag_stripped : 1, - __reserved_g_0003 : 2, - use_ppe : 1, - flow_idx : 20, - reo_destination_indication : 5, - msdu_drop : 1; - uint32_t fse_metadata : 32; - uint32_t tcp_udp_chksum : 16, - cce_metadata : 16; - uint32_t cumulative_ip_length : 16, - amsdu_parser_error : 1, - cce_match : 1, - flow_idx_invalid : 1, - flow_idx_timeout : 1, - msdu_limit_error : 1, - tcp_udp_chksum_fail_copy : 1, - fisa_timeout : 1, - flow_aggregation_continuation : 1, - aggregation_count : 8; - uint32_t reserved_16a : 24, - key_id_octet : 8; - uint32_t reserved_17b : 8, - __reserved_g_0015 : 1, - wds_keep_alive_event : 1, - wds_roaming_event : 1, - wds_learning_event : 1, - multicast_echo : 1, - dest_chip_id : 2, - intra_bss : 1, - priority_valid : 1, - service_code : 9, - reserved_17a : 6; - uint32_t l4_offset : 8, - ipsec_ah : 1, - l3_offset : 7, - ipsec_esp : 1, - stbc : 1, - msdu_length : 14; - uint32_t ip4_protocol_ip6_next_header : 8, - ldpc : 1, - mesh_control_present : 1, - tcp_udp_header_valid : 1, - ip_extn_header_valid : 1, - ip_fixed_header_valid : 1, - toeplitz_hash_sel : 2, - da_is_bcast_mcast : 1, - tcp_only_ack : 1, - ip_frag : 1, - udp_proto : 1, - tcp_proto : 1, - ipv6_proto : 1, - ipv4_proto : 1, - decap_format : 2, - msdu_number : 8; - uint32_t vlan_stag_ci : 16, - vlan_ctag_ci : 16; - uint32_t peer_meta_data : 32; - uint32_t msdu_done_copy : 1, - mimo_ss_bitmap : 6, - reception_type : 3, - receive_bandwidth : 3, - rate_mcs : 5, - sgi : 2, - pkt_type : 4, - user_rssi : 8; - uint32_t flow_id_toeplitz : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t sa_15_0 : 16, - reserved_28a : 16; - uint32_t sa_47_16 : 32; - uint32_t fcs_err : 1, - unencrypted_frame_err : 1, - decrypt_err : 1, - tkip_mic_err : 1, - mpdu_length_err : 1, - buffer_fragment : 1, - directed : 1, - encrypt_required : 1, - rx_in_tx_decrypt_byp : 1, - amsdu_addr_mismatch : 1, - da_idx_invalid : 1, - sa_idx_invalid : 1, - ip_chksum_fail : 1, - tcp_udp_chksum_fail : 1, - msdu_length_err : 1, - overflow_err : 1, - wifi_parser_error : 1, - order : 1, - reserved_30b : 1, - a_msdu_error : 1, - eosp : 1, - more_data : 1, - ctrl_type : 1, - mgmt_type : 1, - null_data : 1, - non_qos : 1, - power_mgmt : 1, - ast_index_timeout : 1, - ast_index_not_found : 1, - mcast_bcast : 1, - reserved_30a : 1, - first_mpdu : 1; - uint32_t msdu_done : 1, - reserved_31b : 16, - ifcs_present : 1, - rx_bitmap_not_updated : 1, - decrypt_status_code : 3, - reserved_31a : 10; -#endif -}; - -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RESERVED_0_LSB 9 -#define RX_MSDU_END_RESERVED_0_MSB 15 -#define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_END_PHY_PPDU_ID_LSB 16 -#define RX_MSDU_END_PHY_PPDU_ID_MSB 31 -#define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000 -#define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32 -#define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47 -#define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000 - -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61 -#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000 - -#define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_MSDU_END_RESERVED_1A_LSB 62 -#define RX_MSDU_END_RESERVED_1A_MSB 63 -#define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000 - -#define RX_MSDU_END_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_MSDU_END_RESERVED_2A_LSB 0 -#define RX_MSDU_END_RESERVED_2A_MSB 7 -#define RX_MSDU_END_RESERVED_2A_MASK 0x00000000000000ff - -#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 -#define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 -#define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00 - -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000 - -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 -#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000 - -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 -#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008 -#define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32 -#define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63 -#define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000 - -#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000010 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 -#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff - -#define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010 -#define RX_MSDU_END_DA_OFFSET_LSB 32 -#define RX_MSDU_END_DA_OFFSET_MSB 37 -#define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000 - -#define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010 -#define RX_MSDU_END_SA_OFFSET_LSB 38 -#define RX_MSDU_END_SA_OFFSET_MSB 43 -#define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000 - -#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010 -#define RX_MSDU_END_DA_OFFSET_VALID_LSB 44 -#define RX_MSDU_END_DA_OFFSET_VALID_MSB 44 -#define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000 - -#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010 -#define RX_MSDU_END_SA_OFFSET_VALID_LSB 45 -#define RX_MSDU_END_SA_OFFSET_VALID_MSB 45 -#define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000 - -#define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010 -#define RX_MSDU_END_RESERVED_5A_LSB 46 -#define RX_MSDU_END_RESERVED_5A_MSB 47 -#define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000 - -#define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_END_L3_TYPE_LSB 48 -#define RX_MSDU_END_L3_TYPE_MSB 63 -#define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000 - -#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000018 -#define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 -#define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 -#define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018 -#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32 -#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63 -#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 - -#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020 -#define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 -#define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 -#define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020 -#define RX_MSDU_END_TCP_FLAG_LSB 32 -#define RX_MSDU_END_TCP_FLAG_MSB 40 -#define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000 - -#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020 -#define RX_MSDU_END_LRO_ELIGIBLE_LSB 41 -#define RX_MSDU_END_LRO_ELIGIBLE_MSB 41 -#define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000 - -#define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020 -#define RX_MSDU_END_RESERVED_9A_LSB 42 -#define RX_MSDU_END_RESERVED_9A_MSB 47 -#define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000 - -#define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020 -#define RX_MSDU_END_WINDOW_SIZE_LSB 48 -#define RX_MSDU_END_WINDOW_SIZE_MSB 63 -#define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000 - -#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 -#define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 -#define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x000000000000ffff - -#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 -#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 -#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000 - -#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 -#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 -#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000 - -#define RX_MSDU_END_TO_DS_OFFSET 0x0000000000000028 -#define RX_MSDU_END_TO_DS_LSB 18 -#define RX_MSDU_END_TO_DS_MSB 18 -#define RX_MSDU_END_TO_DS_MASK 0x0000000000040000 - -#define RX_MSDU_END_TID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_TID_LSB 19 -#define RX_MSDU_END_TID_MSB 22 -#define RX_MSDU_END_TID_MASK 0x0000000000780000 - -#define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IS_VALID_LSB 23 -#define RX_MSDU_END_SA_IS_VALID_MSB 23 -#define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000 - -#define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IS_VALID_LSB 24 -#define RX_MSDU_END_DA_IS_VALID_MSB 24 -#define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000 - -#define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IS_MCBC_LSB 25 -#define RX_MSDU_END_DA_IS_MCBC_MSB 25 -#define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000 - -#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028 -#define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 -#define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 -#define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000 - -#define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028 -#define RX_MSDU_END_FIRST_MSDU_LSB 28 -#define RX_MSDU_END_FIRST_MSDU_MSB 28 -#define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000 - -#define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028 -#define RX_MSDU_END_LAST_MSDU_LSB 29 -#define RX_MSDU_END_LAST_MSDU_MSB 29 -#define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000 - -#define RX_MSDU_END_FR_DS_OFFSET 0x0000000000000028 -#define RX_MSDU_END_FR_DS_LSB 30 -#define RX_MSDU_END_FR_DS_MSB 30 -#define RX_MSDU_END_FR_DS_MASK 0x0000000040000000 - -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 -#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000 - -#define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028 -#define RX_MSDU_END_SA_IDX_LSB 32 -#define RX_MSDU_END_SA_IDX_MSB 47 -#define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000 - -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63 -#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000 - -#define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030 -#define RX_MSDU_END_MSDU_DROP_LSB 0 -#define RX_MSDU_END_MSDU_DROP_MSB 0 -#define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001 - -#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 -#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e - -#define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FLOW_IDX_LSB 6 -#define RX_MSDU_END_FLOW_IDX_MSB 25 -#define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0 - -#define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030 -#define RX_MSDU_END_USE_PPE_LSB 26 -#define RX_MSDU_END_USE_PPE_MSB 26 -#define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000 - -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x0000000000000030 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 -#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x0000000020000000 - -#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x0000000000000030 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 -#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x0000000040000000 - -#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 -#define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 -#define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000080000000 - -#define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030 -#define RX_MSDU_END_FSE_METADATA_LSB 32 -#define RX_MSDU_END_FSE_METADATA_MSB 63 -#define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CCE_METADATA_LSB 0 -#define RX_MSDU_END_CCE_METADATA_MSB 15 -#define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff - -#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000038 -#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 -#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 -#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_AGGREGATION_COUNT_LSB 32 -#define RX_MSDU_END_AGGREGATION_COUNT_MSB 39 -#define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000 - -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40 -#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000 - -#define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FISA_TIMEOUT_LSB 41 -#define RX_MSDU_END_FISA_TIMEOUT_MSB 41 -#define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000 - -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000038 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 42 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 42 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000040000000000 - -#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000038 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 43 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 43 -#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000080000000000 - -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 44 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 44 -#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000100000000000 - -#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000038 -#define RX_MSDU_END_FLOW_IDX_INVALID_LSB 45 -#define RX_MSDU_END_FLOW_IDX_INVALID_MSB 45 -#define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000200000000000 - -#define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CCE_MATCH_LSB 46 -#define RX_MSDU_END_CCE_MATCH_MSB 46 -#define RX_MSDU_END_CCE_MATCH_MASK 0x0000400000000000 - -#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000038 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 47 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 47 -#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000800000000000 - -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000038 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 48 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 63 -#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff000000000000 - -#define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000040 -#define RX_MSDU_END_KEY_ID_OCTET_LSB 0 -#define RX_MSDU_END_KEY_ID_OCTET_MSB 7 -#define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff - -#define RX_MSDU_END_RESERVED_16A_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_16A_LSB 8 -#define RX_MSDU_END_RESERVED_16A_MSB 31 -#define RX_MSDU_END_RESERVED_16A_MASK 0x00000000ffffff00 - -#define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_17A_LSB 32 -#define RX_MSDU_END_RESERVED_17A_MSB 37 -#define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000 - -#define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040 -#define RX_MSDU_END_SERVICE_CODE_LSB 38 -#define RX_MSDU_END_SERVICE_CODE_MSB 46 -#define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000 - -#define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040 -#define RX_MSDU_END_PRIORITY_VALID_LSB 47 -#define RX_MSDU_END_PRIORITY_VALID_MSB 47 -#define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000 - -#define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040 -#define RX_MSDU_END_INTRA_BSS_LSB 48 -#define RX_MSDU_END_INTRA_BSS_MSB 48 -#define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000 - -#define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040 -#define RX_MSDU_END_DEST_CHIP_ID_LSB 49 -#define RX_MSDU_END_DEST_CHIP_ID_MSB 50 -#define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000 - -#define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040 -#define RX_MSDU_END_MULTICAST_ECHO_LSB 51 -#define RX_MSDU_END_MULTICAST_ECHO_MSB 51 -#define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000 - -#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52 -#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52 -#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000 - -#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53 -#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53 -#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000 - -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54 -#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000 - -#define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040 -#define RX_MSDU_END_RESERVED_17B_LSB 56 -#define RX_MSDU_END_RESERVED_17B_MSB 63 -#define RX_MSDU_END_RESERVED_17B_MASK 0xff00000000000000 - -#define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MSDU_LENGTH_LSB 0 -#define RX_MSDU_END_MSDU_LENGTH_MSB 13 -#define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff - -#define RX_MSDU_END_STBC_OFFSET 0x0000000000000048 -#define RX_MSDU_END_STBC_LSB 14 -#define RX_MSDU_END_STBC_MSB 14 -#define RX_MSDU_END_STBC_MASK 0x0000000000004000 - -#define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPSEC_ESP_LSB 15 -#define RX_MSDU_END_IPSEC_ESP_MSB 15 -#define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000 - -#define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048 -#define RX_MSDU_END_L3_OFFSET_LSB 16 -#define RX_MSDU_END_L3_OFFSET_MSB 22 -#define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000 - -#define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPSEC_AH_LSB 23 -#define RX_MSDU_END_IPSEC_AH_MSB 23 -#define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000 - -#define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048 -#define RX_MSDU_END_L4_OFFSET_LSB 24 -#define RX_MSDU_END_L4_OFFSET_MSB 31 -#define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000 - -#define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MSDU_NUMBER_LSB 32 -#define RX_MSDU_END_MSDU_NUMBER_MSB 39 -#define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000 - -#define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048 -#define RX_MSDU_END_DECAP_FORMAT_LSB 40 -#define RX_MSDU_END_DECAP_FORMAT_MSB 41 -#define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000 - -#define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPV4_PROTO_LSB 42 -#define RX_MSDU_END_IPV4_PROTO_MSB 42 -#define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000 - -#define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IPV6_PROTO_LSB 43 -#define RX_MSDU_END_IPV6_PROTO_MSB 43 -#define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000 - -#define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_PROTO_LSB 44 -#define RX_MSDU_END_TCP_PROTO_MSB 44 -#define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000 - -#define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048 -#define RX_MSDU_END_UDP_PROTO_LSB 45 -#define RX_MSDU_END_UDP_PROTO_MSB 45 -#define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000 - -#define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_FRAG_LSB 46 -#define RX_MSDU_END_IP_FRAG_MSB 46 -#define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000 - -#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_ONLY_ACK_LSB 47 -#define RX_MSDU_END_TCP_ONLY_ACK_MSB 47 -#define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000 - -#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48 -#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000 - -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50 -#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000 - -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51 -#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000 - -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52 -#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000 - -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53 -#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000 - -#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54 -#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000 - -#define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048 -#define RX_MSDU_END_LDPC_LSB 55 -#define RX_MSDU_END_LDPC_MSB 55 -#define RX_MSDU_END_LDPC_MASK 0x0080000000000000 - -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63 -#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000 - -#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000050 -#define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 -#define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 -#define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff - -#define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000050 -#define RX_MSDU_END_VLAN_STAG_CI_LSB 16 -#define RX_MSDU_END_VLAN_STAG_CI_MSB 31 -#define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_PEER_META_DATA_OFFSET 0x0000000000000050 -#define RX_MSDU_END_PEER_META_DATA_LSB 32 -#define RX_MSDU_END_PEER_META_DATA_MSB 63 -#define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058 -#define RX_MSDU_END_USER_RSSI_LSB 0 -#define RX_MSDU_END_USER_RSSI_MSB 7 -#define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff - -#define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058 -#define RX_MSDU_END_PKT_TYPE_LSB 8 -#define RX_MSDU_END_PKT_TYPE_MSB 11 -#define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00 - -#define RX_MSDU_END_SGI_OFFSET 0x0000000000000058 -#define RX_MSDU_END_SGI_LSB 12 -#define RX_MSDU_END_SGI_MSB 13 -#define RX_MSDU_END_SGI_MASK 0x0000000000003000 - -#define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RATE_MCS_LSB 14 -#define RX_MSDU_END_RATE_MCS_MSB 18 -#define RX_MSDU_END_RATE_MCS_MASK 0x000000000007c000 - -#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 19 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 21 -#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x0000000000380000 - -#define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058 -#define RX_MSDU_END_RECEPTION_TYPE_LSB 22 -#define RX_MSDU_END_RECEPTION_TYPE_MSB 24 -#define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000001c00000 - -#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058 -#define RX_MSDU_END_MIMO_SS_BITMAP_LSB 25 -#define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 -#define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x000000007e000000 - -#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x0000000000000058 -#define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 -#define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 -#define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x0000000080000000 - -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000058 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63 -#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000 - -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff - -#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060 -#define RX_MSDU_END_SW_PHY_META_DATA_LSB 32 -#define RX_MSDU_END_SW_PHY_META_DATA_MSB 63 -#define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000 - -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000068 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000068 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 32 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 63 -#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 - -#define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070 -#define RX_MSDU_END_RESERVED_28A_LSB 0 -#define RX_MSDU_END_RESERVED_28A_MSB 15 -#define RX_MSDU_END_RESERVED_28A_MASK 0x000000000000ffff - -#define RX_MSDU_END_SA_15_0_OFFSET 0x0000000000000070 -#define RX_MSDU_END_SA_15_0_LSB 16 -#define RX_MSDU_END_SA_15_0_MSB 31 -#define RX_MSDU_END_SA_15_0_MASK 0x00000000ffff0000 - -#define RX_MSDU_END_SA_47_16_OFFSET 0x0000000000000070 -#define RX_MSDU_END_SA_47_16_LSB 32 -#define RX_MSDU_END_SA_47_16_MSB 63 -#define RX_MSDU_END_SA_47_16_MASK 0xffffffff00000000 - -#define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078 -#define RX_MSDU_END_FIRST_MPDU_LSB 0 -#define RX_MSDU_END_FIRST_MPDU_MSB 0 -#define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001 - -#define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_30A_LSB 1 -#define RX_MSDU_END_RESERVED_30A_MSB 1 -#define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002 - -#define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MCAST_BCAST_LSB 2 -#define RX_MSDU_END_MCAST_BCAST_MSB 2 -#define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004 - -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 -#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008 - -#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 -#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010 - -#define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_POWER_MGMT_LSB 5 -#define RX_MSDU_END_POWER_MGMT_MSB 5 -#define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020 - -#define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078 -#define RX_MSDU_END_NON_QOS_LSB 6 -#define RX_MSDU_END_NON_QOS_MSB 6 -#define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040 - -#define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078 -#define RX_MSDU_END_NULL_DATA_LSB 7 -#define RX_MSDU_END_NULL_DATA_MSB 7 -#define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080 - -#define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MGMT_TYPE_LSB 8 -#define RX_MSDU_END_MGMT_TYPE_MSB 8 -#define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100 - -#define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_CTRL_TYPE_LSB 9 -#define RX_MSDU_END_CTRL_TYPE_MSB 9 -#define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200 - -#define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MORE_DATA_LSB 10 -#define RX_MSDU_END_MORE_DATA_MSB 10 -#define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400 - -#define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078 -#define RX_MSDU_END_EOSP_LSB 11 -#define RX_MSDU_END_EOSP_MSB 11 -#define RX_MSDU_END_EOSP_MASK 0x0000000000000800 - -#define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_A_MSDU_ERROR_LSB 12 -#define RX_MSDU_END_A_MSDU_ERROR_MSB 12 -#define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000 - -#define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_30B_LSB 13 -#define RX_MSDU_END_RESERVED_30B_MSB 13 -#define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000002000 - -#define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078 -#define RX_MSDU_END_ORDER_LSB 14 -#define RX_MSDU_END_ORDER_MSB 14 -#define RX_MSDU_END_ORDER_MASK 0x0000000000004000 - -#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 -#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 -#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000008000 - -#define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_OVERFLOW_ERR_LSB 16 -#define RX_MSDU_END_OVERFLOW_ERR_MSB 16 -#define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000 - -#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 -#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 -#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000 - -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 -#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000 - -#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078 -#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 -#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 -#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000 - -#define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078 -#define RX_MSDU_END_SA_IDX_INVALID_LSB 20 -#define RX_MSDU_END_SA_IDX_INVALID_MSB 20 -#define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000 - -#define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DA_IDX_INVALID_LSB 21 -#define RX_MSDU_END_DA_IDX_INVALID_MSB 21 -#define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000 - -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x0000000000000078 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 -#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x0000000000400000 - -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 -#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000 - -#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 -#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 -#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000 - -#define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DIRECTED_LSB 25 -#define RX_MSDU_END_DIRECTED_MSB 25 -#define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000 - -#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 -#define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 -#define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000 - -#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 -#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 -#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000 - -#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 -#define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 -#define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000 - -#define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DECRYPT_ERR_LSB 29 -#define RX_MSDU_END_DECRYPT_ERR_MSB 29 -#define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000 - -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 -#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000 - -#define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078 -#define RX_MSDU_END_FCS_ERR_LSB 31 -#define RX_MSDU_END_FCS_ERR_MSB 31 -#define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000 - -#define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_31A_LSB 32 -#define RX_MSDU_END_RESERVED_31A_MSB 41 -#define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000 - -#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44 -#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000 - -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45 -#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000 - -#define RX_MSDU_END_IFCS_PRESENT_OFFSET 0x0000000000000078 -#define RX_MSDU_END_IFCS_PRESENT_LSB 46 -#define RX_MSDU_END_IFCS_PRESENT_MSB 46 -#define RX_MSDU_END_IFCS_PRESENT_MASK 0x0000400000000000 - -#define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078 -#define RX_MSDU_END_RESERVED_31B_LSB 47 -#define RX_MSDU_END_RESERVED_31B_MSB 62 -#define RX_MSDU_END_RESERVED_31B_MASK 0x7fff800000000000 - -#define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078 -#define RX_MSDU_END_MSDU_DONE_LSB 63 -#define RX_MSDU_END_MSDU_DONE_MSB 63 -#define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_ext_desc_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_ext_desc_info.h deleted file mode 100644 index 70bda69ddfec..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_ext_desc_info.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_EXT_DESC_INFO_H_ -#define _RX_MSDU_EXT_DESC_INFO_H_ - -#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1 - -struct rx_msdu_ext_desc_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reo_destination_indication : 5, - service_code : 9, - priority_valid : 1, - data_offset : 12, - src_link_id : 3, - reserved_0a : 2; -#else - uint32_t reserved_0a : 2, - src_link_id : 3, - data_offset : 12, - priority_valid : 1, - service_code : 9, - reo_destination_indication : 5; -#endif -}; - -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13 -#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14 -#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26 -#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29 -#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31 -#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_link.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_link.h deleted file mode 100644 index c54357dae2ef..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_link.h +++ /dev/null @@ -1,2051 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_LINK_H_ -#define _RX_MSDU_LINK_H_ - -#include "uniform_descriptor_header.h" -#include "buffer_addr_info.h" -#include "rx_msdu_details.h" -#define NUM_OF_DWORDS_RX_MSDU_LINK 64 - -struct rx_msdu_link { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct uniform_descriptor_header descriptor_header; - struct buffer_addr_info next_msdu_link_desc_addr_info; - uint32_t reserved_3a : 32; - struct rx_msdu_details msdu_0; - struct rx_msdu_details msdu_1; - struct rx_msdu_details msdu_2; - struct rx_msdu_details msdu_3; - struct rx_msdu_details msdu_4; - struct rx_msdu_details msdu_5; - struct rx_msdu_details msdu_6; - struct rx_msdu_details msdu_7; - struct rx_msdu_details msdu_8; - struct rx_msdu_details msdu_9; - struct rx_msdu_details msdu_10; - struct rx_msdu_details msdu_11; - struct rx_msdu_details msdu_12; - struct rx_msdu_details msdu_13; - struct rx_msdu_details msdu_14; -#else - struct uniform_descriptor_header descriptor_header; - struct buffer_addr_info next_msdu_link_desc_addr_info; - uint32_t reserved_3a : 32; - struct rx_msdu_details msdu_0; - struct rx_msdu_details msdu_1; - struct rx_msdu_details msdu_2; - struct rx_msdu_details msdu_3; - struct rx_msdu_details msdu_4; - struct rx_msdu_details msdu_5; - struct rx_msdu_details msdu_6; - struct rx_msdu_details msdu_7; - struct rx_msdu_details msdu_8; - struct rx_msdu_details msdu_9; - struct rx_msdu_details msdu_10; - struct rx_msdu_details msdu_11; - struct rx_msdu_details msdu_12; - struct rx_msdu_details msdu_13; - struct rx_msdu_details msdu_14; -#endif -}; - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB 0 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB 3 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 - -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_RESERVED_3A_OFFSET 0x0000000c -#define RX_MSDU_LINK_RESERVED_3A_LSB 0 -#define RX_MSDU_LINK_RESERVED_3A_MSB 31 -#define RX_MSDU_LINK_RESERVED_3A_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000010 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000014 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000018 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000001c -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000028 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000002c -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000038 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000003c -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000048 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000004c -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000058 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000005c -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000068 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000006c -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_6_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000078 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000007c -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_6_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000080 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000084 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_7_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000088 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000008c -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_7_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000090 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000094 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_8_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000098 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000009c -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_8_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000a0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000a4 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_9_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000a8 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000ac -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_9_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000b0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000b4 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_10_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000b8 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000bc -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_10_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000c0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000c4 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_11_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000c8 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000cc -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_11_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000d0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000d4 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_12_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000d8 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000dc -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_12_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000e0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000e4 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_13_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000e8 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000ec -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_13_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x000000f0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x000000f4 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 -#define RX_MSDU_LINK_MSDU_14_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x000000f8 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 - -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x000000fc -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 -#define RX_MSDU_LINK_MSDU_14_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_start.h deleted file mode 100644 index e1e99c027c85..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_msdu_start.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_MSDU_START_H_ -#define _RX_MSDU_START_H_ - -#define NUM_OF_DWORDS_RX_MSDU_START 10 - -#define NUM_OF_QWORDS_RX_MSDU_START 5 - -struct rx_msdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - rate_mcs : 5, - reserved_0 : 2, - phy_ppdu_id : 16; - uint32_t msdu_length : 14, - stbc : 1, - ipsec_esp : 1, - l3_offset : 7, - ipsec_ah : 1, - l4_offset : 8; - uint32_t msdu_number : 8, - decap_format : 2, - ipv4_proto : 1, - ipv6_proto : 1, - tcp_proto : 1, - udp_proto : 1, - ip_frag : 1, - tcp_only_ack : 1, - da_is_bcast_mcast : 1, - toeplitz_hash_sel : 2, - ip_fixed_header_valid : 1, - ip_extn_header_valid : 1, - tcp_udp_header_valid : 1, - mesh_control_present : 1, - ldpc : 1, - ip4_protocol_ip6_next_header : 8; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t flow_id_toeplitz : 32; - uint32_t user_rssi : 8, - pkt_type : 4, - sgi : 2, - reserved_5a : 4, - receive_bandwidth : 3, - reception_type : 3, - mimo_ss_bitmap : 8; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t vlan_ctag_ci : 16, - vlan_stag_ci : 16; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 2, - rate_mcs : 5, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t l4_offset : 8, - ipsec_ah : 1, - l3_offset : 7, - ipsec_esp : 1, - stbc : 1, - msdu_length : 14; - uint32_t ip4_protocol_ip6_next_header : 8, - ldpc : 1, - mesh_control_present : 1, - tcp_udp_header_valid : 1, - ip_extn_header_valid : 1, - ip_fixed_header_valid : 1, - toeplitz_hash_sel : 2, - da_is_bcast_mcast : 1, - tcp_only_ack : 1, - ip_frag : 1, - udp_proto : 1, - tcp_proto : 1, - ipv6_proto : 1, - ipv4_proto : 1, - decap_format : 2, - msdu_number : 8; - uint32_t toeplitz_hash_2_or_4 : 32; - uint32_t flow_id_toeplitz : 32; - uint32_t mimo_ss_bitmap : 8, - reception_type : 3, - receive_bandwidth : 3, - reserved_5a : 4, - sgi : 2, - pkt_type : 4, - user_rssi : 8; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t sw_phy_meta_data : 32; - uint32_t vlan_stag_ci : 16, - vlan_ctag_ci : 16; -#endif -}; - -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB 2 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB 8 -#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_MSDU_START_RATE_MCS_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RATE_MCS_LSB 9 -#define RX_MSDU_START_RATE_MCS_MSB 13 -#define RX_MSDU_START_RATE_MCS_MASK 0x0000000000003e00 - -#define RX_MSDU_START_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_MSDU_START_RESERVED_0_LSB 14 -#define RX_MSDU_START_RESERVED_0_MSB 15 -#define RX_MSDU_START_RESERVED_0_MASK 0x000000000000c000 - -#define RX_MSDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_MSDU_START_PHY_PPDU_ID_LSB 16 -#define RX_MSDU_START_PHY_PPDU_ID_MSB 31 -#define RX_MSDU_START_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_MSDU_START_MSDU_LENGTH_OFFSET 0x0000000000000000 -#define RX_MSDU_START_MSDU_LENGTH_LSB 32 -#define RX_MSDU_START_MSDU_LENGTH_MSB 45 -#define RX_MSDU_START_MSDU_LENGTH_MASK 0x00003fff00000000 - -#define RX_MSDU_START_STBC_OFFSET 0x0000000000000000 -#define RX_MSDU_START_STBC_LSB 46 -#define RX_MSDU_START_STBC_MSB 46 -#define RX_MSDU_START_STBC_MASK 0x0000400000000000 - -#define RX_MSDU_START_IPSEC_ESP_OFFSET 0x0000000000000000 -#define RX_MSDU_START_IPSEC_ESP_LSB 47 -#define RX_MSDU_START_IPSEC_ESP_MSB 47 -#define RX_MSDU_START_IPSEC_ESP_MASK 0x0000800000000000 - -#define RX_MSDU_START_L3_OFFSET_OFFSET 0x0000000000000000 -#define RX_MSDU_START_L3_OFFSET_LSB 48 -#define RX_MSDU_START_L3_OFFSET_MSB 54 -#define RX_MSDU_START_L3_OFFSET_MASK 0x007f000000000000 - -#define RX_MSDU_START_IPSEC_AH_OFFSET 0x0000000000000000 -#define RX_MSDU_START_IPSEC_AH_LSB 55 -#define RX_MSDU_START_IPSEC_AH_MSB 55 -#define RX_MSDU_START_IPSEC_AH_MASK 0x0080000000000000 - -#define RX_MSDU_START_L4_OFFSET_OFFSET 0x0000000000000000 -#define RX_MSDU_START_L4_OFFSET_LSB 56 -#define RX_MSDU_START_L4_OFFSET_MSB 63 -#define RX_MSDU_START_L4_OFFSET_MASK 0xff00000000000000 - -#define RX_MSDU_START_MSDU_NUMBER_OFFSET 0x0000000000000008 -#define RX_MSDU_START_MSDU_NUMBER_LSB 0 -#define RX_MSDU_START_MSDU_NUMBER_MSB 7 -#define RX_MSDU_START_MSDU_NUMBER_MASK 0x00000000000000ff - -#define RX_MSDU_START_DECAP_FORMAT_OFFSET 0x0000000000000008 -#define RX_MSDU_START_DECAP_FORMAT_LSB 8 -#define RX_MSDU_START_DECAP_FORMAT_MSB 9 -#define RX_MSDU_START_DECAP_FORMAT_MASK 0x0000000000000300 - -#define RX_MSDU_START_IPV4_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IPV4_PROTO_LSB 10 -#define RX_MSDU_START_IPV4_PROTO_MSB 10 -#define RX_MSDU_START_IPV4_PROTO_MASK 0x0000000000000400 - -#define RX_MSDU_START_IPV6_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IPV6_PROTO_LSB 11 -#define RX_MSDU_START_IPV6_PROTO_MSB 11 -#define RX_MSDU_START_IPV6_PROTO_MASK 0x0000000000000800 - -#define RX_MSDU_START_TCP_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_PROTO_LSB 12 -#define RX_MSDU_START_TCP_PROTO_MSB 12 -#define RX_MSDU_START_TCP_PROTO_MASK 0x0000000000001000 - -#define RX_MSDU_START_UDP_PROTO_OFFSET 0x0000000000000008 -#define RX_MSDU_START_UDP_PROTO_LSB 13 -#define RX_MSDU_START_UDP_PROTO_MSB 13 -#define RX_MSDU_START_UDP_PROTO_MASK 0x0000000000002000 - -#define RX_MSDU_START_IP_FRAG_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_FRAG_LSB 14 -#define RX_MSDU_START_IP_FRAG_MSB 14 -#define RX_MSDU_START_IP_FRAG_MASK 0x0000000000004000 - -#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_ONLY_ACK_LSB 15 -#define RX_MSDU_START_TCP_ONLY_ACK_MSB 15 -#define RX_MSDU_START_TCP_ONLY_ACK_MASK 0x0000000000008000 - -#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000008 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB 16 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB 16 -#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK 0x0000000000010000 - -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB 17 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB 18 -#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK 0x0000000000060000 - -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB 19 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB 19 -#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK 0x0000000000080000 - -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB 20 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB 20 -#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK 0x0000000000100000 - -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB 21 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB 21 -#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK 0x0000000000200000 - -#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000008 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB 22 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB 22 -#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK 0x0000000000400000 - -#define RX_MSDU_START_LDPC_OFFSET 0x0000000000000008 -#define RX_MSDU_START_LDPC_LSB 23 -#define RX_MSDU_START_LDPC_MSB 23 -#define RX_MSDU_START_LDPC_MASK 0x0000000000800000 - -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000008 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 -#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0x00000000ff000000 - -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000008 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB 32 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB 63 -#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 - -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000010 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB 0 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB 31 -#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK 0x00000000ffffffff - -#define RX_MSDU_START_USER_RSSI_OFFSET 0x0000000000000010 -#define RX_MSDU_START_USER_RSSI_LSB 32 -#define RX_MSDU_START_USER_RSSI_MSB 39 -#define RX_MSDU_START_USER_RSSI_MASK 0x000000ff00000000 - -#define RX_MSDU_START_PKT_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_START_PKT_TYPE_LSB 40 -#define RX_MSDU_START_PKT_TYPE_MSB 43 -#define RX_MSDU_START_PKT_TYPE_MASK 0x00000f0000000000 - -#define RX_MSDU_START_SGI_OFFSET 0x0000000000000010 -#define RX_MSDU_START_SGI_LSB 44 -#define RX_MSDU_START_SGI_MSB 45 -#define RX_MSDU_START_SGI_MASK 0x0000300000000000 - -#define RX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RESERVED_5A_LSB 46 -#define RX_MSDU_START_RESERVED_5A_MSB 49 -#define RX_MSDU_START_RESERVED_5A_MASK 0x0003c00000000000 - -#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB 50 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB 52 -#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK 0x001c000000000000 - -#define RX_MSDU_START_RECEPTION_TYPE_OFFSET 0x0000000000000010 -#define RX_MSDU_START_RECEPTION_TYPE_LSB 53 -#define RX_MSDU_START_RECEPTION_TYPE_MSB 55 -#define RX_MSDU_START_RECEPTION_TYPE_MASK 0x00e0000000000000 - -#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET 0x0000000000000010 -#define RX_MSDU_START_MIMO_SS_BITMAP_LSB 56 -#define RX_MSDU_START_MIMO_SS_BITMAP_MSB 63 -#define RX_MSDU_START_MIMO_SS_BITMAP_MASK 0xff00000000000000 - -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000018 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000018 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 -#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 - -#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000020 -#define RX_MSDU_START_SW_PHY_META_DATA_LSB 0 -#define RX_MSDU_START_SW_PHY_META_DATA_MSB 31 -#define RX_MSDU_START_SW_PHY_META_DATA_MASK 0x00000000ffffffff - -#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET 0x0000000000000020 -#define RX_MSDU_START_VLAN_CTAG_CI_LSB 32 -#define RX_MSDU_START_VLAN_CTAG_CI_MSB 47 -#define RX_MSDU_START_VLAN_CTAG_CI_MASK 0x0000ffff00000000 - -#define RX_MSDU_START_VLAN_STAG_CI_OFFSET 0x0000000000000020 -#define RX_MSDU_START_VLAN_STAG_CI_LSB 48 -#define RX_MSDU_START_VLAN_STAG_CI_MSB 63 -#define RX_MSDU_START_VLAN_STAG_CI_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_ack_report.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_ack_report.h deleted file mode 100644 index 345b14ea4255..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_ack_report.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_ACK_REPORT_H_ -#define _RX_PPDU_ACK_REPORT_H_ - -#include "ack_report.h" -#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 2 - -#define NUM_OF_QWORDS_RX_PPDU_ACK_REPORT 1 - -struct rx_ppdu_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct ack_report ack_report_details; - uint32_t tlv64_padding : 32; -#else - struct ack_report ack_report_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB 0 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB 3 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK 0x000000000000000f - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB 4 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB 7 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000000f0 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB 8 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB 8 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK 0x0000000000000100 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB 9 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB 15 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK 0x000000000000fe00 - -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 -#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 - -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_LSB 32 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MSB 63 -#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_end_user_stats.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_end_user_stats.h deleted file mode 100644 index 51db8f35a6ab..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_end_user_stats.h +++ /dev/null @@ -1,679 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_END_USER_STATS_H_ -#define _RX_PPDU_END_USER_STATS_H_ - -#include "rx_rxpcu_classification_overview.h" -#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30 - -#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 15 - -struct rx_ppdu_end_user_stats { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t sta_full_aid : 13, - mcs : 5, - nss : 3, - expected_response_ack_or_ba : 1, - reserved_1a : 10; - uint32_t sw_peer_id : 16, - mpdu_cnt_fcs_err : 11, - sw2rxdma0_buf_source_used : 1, - fw2rxdma0_buf_source_used : 1, - sw2rxdma1_buf_source_used : 1, - sw2rxdma2_buf_source_used : 1, - fw2rxdma1_buf_source_used : 1; - uint32_t mpdu_cnt_fcs_ok : 11, - frame_control_info_valid : 1, - qos_control_info_valid : 1, - ht_control_info_valid : 1, - data_sequence_control_info_valid : 1, - ht_control_info_null_valid : 1, - rxdma2fw0_ring_used : 1, - rxdma2fw1_ring_used : 1, - rxdma2fwreo_0_ring_used : 1, - rxdma2fwreo_1_ring_used : 1, - reserved_3a : 1, - ht_control_field_pkt_type : 4, - reserved_3b : 7; - uint32_t ast_index : 16, - frame_control_field : 16; - uint32_t first_data_seq_ctrl : 16, - qos_control_field : 16; - uint32_t ht_control_field : 32; - uint32_t fcs_ok_bitmap_31_0 : 32; - uint32_t fcs_ok_bitmap_63_32 : 32; - uint32_t udp_msdu_count : 16, - tcp_msdu_count : 16; - uint32_t other_msdu_count : 16, - tcp_ack_msdu_count : 16; - uint32_t sw_response_reference_ptr : 32; - uint32_t received_qos_data_tid_bitmap : 16, - received_qos_data_tid_eosp_bitmap : 16; - uint32_t qosctrl_15_8_tid0 : 8, - qosctrl_15_8_tid1 : 8, - qosctrl_15_8_tid2 : 8, - qosctrl_15_8_tid3 : 8; - uint32_t qosctrl_15_8_tid4 : 8, - qosctrl_15_8_tid5 : 8, - qosctrl_15_8_tid6 : 8, - qosctrl_15_8_tid7 : 8; - uint32_t qosctrl_15_8_tid8 : 8, - qosctrl_15_8_tid9 : 8, - qosctrl_15_8_tid10 : 8, - qosctrl_15_8_tid11 : 8; - uint32_t qosctrl_15_8_tid12 : 8, - qosctrl_15_8_tid13 : 8, - qosctrl_15_8_tid14 : 8, - qosctrl_15_8_tid15 : 8; - uint32_t mpdu_ok_byte_count : 25, - ampdu_delim_ok_count_6_0 : 7; - uint32_t ampdu_delim_err_count : 25, - ampdu_delim_ok_count_13_7 : 7; - uint32_t mpdu_err_byte_count : 25, - ampdu_delim_ok_count_20_14 : 7; - uint32_t non_consecutive_delimiter_err : 16, - retried_msdu_count : 16; - uint32_t ht_control_null_field : 32; - uint32_t sw_response_reference_ptr_ext : 32; - uint32_t corrupted_due_to_fifo_delay : 1, - frame_control_info_null_valid : 1, - frame_control_field_null : 16, - retried_mpdu_count : 11, - reserved_23a : 3; - uint32_t rxpcu_mpdu_filter_in_category : 2, - sw_frame_group_id : 7, - reserved_24a : 4, - frame_control_info_mgmt_ctrl_valid : 1, - mac_addr_ad2_valid : 1, - mcast_bcast : 1, - frame_control_field_mgmt_ctrl : 16; - uint32_t user_ppdu_len : 24, - reserved_25a : 8; - uint32_t mac_addr_ad2_31_0 : 32; - uint32_t mac_addr_ad2_47_32 : 16, - amsdu_msdu_count : 16; - uint32_t non_amsdu_msdu_count : 16, - ucast_msdu_count : 16; - uint32_t bcast_msdu_count : 16, - mcast_bcast_msdu_count : 16; -#else - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t reserved_1a : 10, - expected_response_ack_or_ba : 1, - nss : 3, - mcs : 5, - sta_full_aid : 13; - uint32_t fw2rxdma1_buf_source_used : 1, - sw2rxdma2_buf_source_used : 1, - sw2rxdma1_buf_source_used : 1, - fw2rxdma0_buf_source_used : 1, - sw2rxdma0_buf_source_used : 1, - mpdu_cnt_fcs_err : 11, - sw_peer_id : 16; - uint32_t reserved_3b : 7, - ht_control_field_pkt_type : 4, - reserved_3a : 1, - rxdma2fwreo_1_ring_used : 1, - rxdma2fwreo_0_ring_used : 1, - rxdma2fw1_ring_used : 1, - rxdma2fw0_ring_used : 1, - ht_control_info_null_valid : 1, - data_sequence_control_info_valid : 1, - ht_control_info_valid : 1, - qos_control_info_valid : 1, - frame_control_info_valid : 1, - mpdu_cnt_fcs_ok : 11; - uint32_t frame_control_field : 16, - ast_index : 16; - uint32_t qos_control_field : 16, - first_data_seq_ctrl : 16; - uint32_t ht_control_field : 32; - uint32_t fcs_ok_bitmap_31_0 : 32; - uint32_t fcs_ok_bitmap_63_32 : 32; - uint32_t tcp_msdu_count : 16, - udp_msdu_count : 16; - uint32_t tcp_ack_msdu_count : 16, - other_msdu_count : 16; - uint32_t sw_response_reference_ptr : 32; - uint32_t received_qos_data_tid_eosp_bitmap : 16, - received_qos_data_tid_bitmap : 16; - uint32_t qosctrl_15_8_tid3 : 8, - qosctrl_15_8_tid2 : 8, - qosctrl_15_8_tid1 : 8, - qosctrl_15_8_tid0 : 8; - uint32_t qosctrl_15_8_tid7 : 8, - qosctrl_15_8_tid6 : 8, - qosctrl_15_8_tid5 : 8, - qosctrl_15_8_tid4 : 8; - uint32_t qosctrl_15_8_tid11 : 8, - qosctrl_15_8_tid10 : 8, - qosctrl_15_8_tid9 : 8, - qosctrl_15_8_tid8 : 8; - uint32_t qosctrl_15_8_tid15 : 8, - qosctrl_15_8_tid14 : 8, - qosctrl_15_8_tid13 : 8, - qosctrl_15_8_tid12 : 8; - uint32_t ampdu_delim_ok_count_6_0 : 7, - mpdu_ok_byte_count : 25; - uint32_t ampdu_delim_ok_count_13_7 : 7, - ampdu_delim_err_count : 25; - uint32_t ampdu_delim_ok_count_20_14 : 7, - mpdu_err_byte_count : 25; - uint32_t retried_msdu_count : 16, - non_consecutive_delimiter_err : 16; - uint32_t ht_control_null_field : 32; - uint32_t sw_response_reference_ptr_ext : 32; - uint32_t reserved_23a : 3, - retried_mpdu_count : 11, - frame_control_field_null : 16, - frame_control_info_null_valid : 1, - corrupted_due_to_fifo_delay : 1; - uint32_t frame_control_field_mgmt_ctrl : 16, - mcast_bcast : 1, - mac_addr_ad2_valid : 1, - frame_control_info_mgmt_ctrl_valid : 1, - reserved_24a : 4, - sw_frame_group_id : 7, - rxpcu_mpdu_filter_in_category : 2; - uint32_t reserved_25a : 8, - user_ppdu_len : 24; - uint32_t mac_addr_ad2_31_0 : 32; - uint32_t amsdu_msdu_count : 16, - mac_addr_ad2_47_32 : 16; - uint32_t ucast_msdu_count : 16, - non_amsdu_msdu_count : 16; - uint32_t mcast_bcast_msdu_count : 16, - bcast_msdu_count : 16; -#endif -}; - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 -#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 32 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 44 -#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff00000000 - -#define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_MCS_LSB 45 -#define RX_PPDU_END_USER_STATS_MCS_MSB 49 -#define RX_PPDU_END_USER_STATS_MCS_MASK 0x0003e00000000000 - -#define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_NSS_LSB 50 -#define RX_PPDU_END_USER_STATS_NSS_MSB 52 -#define RX_PPDU_END_USER_STATS_NSS_MASK 0x001c000000000000 - -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 53 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 53 -#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x0020000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 54 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffc0000000000000 - -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 -#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x0000000007ff0000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 -#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000008000000 - -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_LSB 28 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MSB 28 -#define RX_PPDU_END_USER_STATS_FW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000010000000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 -#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000020000000 - -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_LSB 30 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MSB 30 -#define RX_PPDU_END_USER_STATS_SW2RXDMA2_BUF_SOURCE_USED_MASK 0x0000000040000000 - -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_LSB 31 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MSB 31 -#define RX_PPDU_END_USER_STATS_FW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000080000000 - -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 42 -#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff00000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 43 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 43 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x0000080000000000 - -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 44 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 44 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x0000100000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 45 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 45 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x0000200000000000 - -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 46 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 46 -#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x0000400000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 47 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 47 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x0000800000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_LSB 48 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MSB 48 -#define RX_PPDU_END_USER_STATS_RXDMA2FW0_RING_USED_MASK 0x0001000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_LSB 49 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MSB 49 -#define RX_PPDU_END_USER_STATS_RXDMA2FW1_RING_USED_MASK 0x0002000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_LSB 50 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MSB 50 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_0_RING_USED_MASK 0x0004000000000000 - -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_LSB 51 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MSB 51 -#define RX_PPDU_END_USER_STATS_RXDMA2FWREO_1_RING_USED_MASK 0x0008000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_LSB 52 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_MSB 52 -#define RX_PPDU_END_USER_STATS_RESERVED_3A_MASK 0x0010000000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 53 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 56 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e0000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 57 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 -#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 -#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 32 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 47 -#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 48 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 63 -#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 32 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 63 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 -#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 47 -#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x0000000000000020 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 -#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000000000000028 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 32 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 63 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 -#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 32 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 39 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff00000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 40 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 47 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff0000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 48 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 55 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x0000000000000030 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 56 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 63 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x00000000000000ff - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x000000000000ff00 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x0000000000ff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0x00000000ff000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 32 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 39 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff00000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 40 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 47 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff0000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 48 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 55 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000000000000038 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 56 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 63 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x00000000000000ff - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x000000000000ff00 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x0000000000ff0000 - -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 -#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0x00000000ff000000 - -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 56 -#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff00000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x0000000000000040 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 57 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 63 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x0000000001ffffff - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0x00000000fe000000 - -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 56 -#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff00000000 - -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000000000000048 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 57 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 63 -#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe00000000000000 - -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 -#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x0000000000000050 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 32 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 63 -#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 -#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 -#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 33 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 33 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x0000000200000000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 34 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 49 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc00000000 - -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 50 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 60 -#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc000000000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000000000000058 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 61 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe000000000000000 - -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 -#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 - -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB 2 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB 8 -#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc - -#define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB 9 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB 12 -#define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK 0x0000000000001e00 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB 13 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB 13 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK 0x0000000000002000 - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB 14 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB 14 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK 0x0000000000004000 - -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB 15 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB 15 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK 0x0000000000008000 - -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB 16 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB 31 -#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB 32 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB 55 -#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK 0x00ffffff00000000 - -#define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET 0x0000000000000060 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB 56 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB 63 -#define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK 0xff00000000000000 - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB 0 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB 31 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB 32 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB 47 -#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000068 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK 0xffff000000000000 - -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB 0 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB 15 -#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK 0x000000000000ffff - -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB 16 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB 31 -#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB 32 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB 47 -#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK 0x0000ffff00000000 - -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB 48 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB 63 -#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_end_user_stats_ext.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_end_user_stats_ext.h deleted file mode 100644 index 0a11202db481..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_end_user_stats_ext.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_END_USER_STATS_EXT_H_ -#define _RX_PPDU_END_USER_STATS_EXT_H_ - -#include "rx_rxpcu_classification_overview.h" -#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8 - -#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS_EXT 4 - -struct rx_ppdu_end_user_stats_ext { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t fcs_ok_bitmap_95_64 : 32; - uint32_t fcs_ok_bitmap_127_96 : 32; - uint32_t fcs_ok_bitmap_159_128 : 32; - uint32_t fcs_ok_bitmap_191_160 : 32; - uint32_t fcs_ok_bitmap_223_192 : 32; - uint32_t fcs_ok_bitmap_255_224 : 32; - uint32_t corrupted_due_to_fifo_delay : 1, - reserved_7a : 31; -#else - struct rx_rxpcu_classification_overview rxpcu_classification_details; - uint32_t fcs_ok_bitmap_95_64 : 32; - uint32_t fcs_ok_bitmap_127_96 : 32; - uint32_t fcs_ok_bitmap_159_128 : 32; - uint32_t fcs_ok_bitmap_191_160 : 32; - uint32_t fcs_ok_bitmap_223_192 : 32; - uint32_t fcs_ok_bitmap_255_224 : 32; - uint32_t reserved_7a : 31, - corrupted_due_to_fifo_delay : 1; -#endif -}; - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 - -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET 0x0000000000000000 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET 0x0000000000000008 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET 0x0000000000000010 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK 0xffffffff00000000 - -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB 0 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB 31 -#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK 0x00000000ffffffff - -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 -#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 - -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET 0x0000000000000018 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB 33 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB 63 -#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK 0xfffffffe00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_no_ack_report.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_no_ack_report.h deleted file mode 100644 index d9c54c04df32..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_no_ack_report.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_NO_ACK_REPORT_H_ -#define _RX_PPDU_NO_ACK_REPORT_H_ - -#include "no_ack_report.h" -#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4 - -#define NUM_OF_QWORDS_RX_PPDU_NO_ACK_REPORT 2 - -struct rx_ppdu_no_ack_report { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct no_ack_report no_ack_report_details; -#else - struct no_ack_report no_ack_report_details; -#endif -}; - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB 0 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB 3 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK 0x000000000000000f - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB 4 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB 7 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000f0 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB 8 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB 15 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000000000ff00 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB 32 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB 55 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK 0x00ffffff00000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB 56 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB 56 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK 0x0100000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 57 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 60 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e00000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB 61 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB 63 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK 0xe000000000000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000000fff - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000fff000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB 24 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB 31 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK 0x00000000ff000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 32 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 43 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff00000000 - -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB 44 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB 63 -#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK 0xfffff00000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_start.h deleted file mode 100644 index 19765eb4409b..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_start.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_START_H_ -#define _RX_PPDU_START_H_ - -#define NUM_OF_DWORDS_RX_PPDU_START 6 - -#define NUM_OF_QWORDS_RX_PPDU_START 3 - -struct rx_ppdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - preamble_time_to_rxframe : 8, - reserved_0a : 8; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t rxframe_assert_timestamp : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 8, - preamble_time_to_rxframe : 8, - phy_ppdu_id : 16; - uint32_t sw_phy_meta_data : 32; - uint32_t ppdu_start_timestamp_31_0 : 32; - uint32_t ppdu_start_timestamp_63_32 : 32; - uint32_t rxframe_assert_timestamp : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_START_PHY_PPDU_ID_LSB 0 -#define RX_PPDU_START_PHY_PPDU_ID_MSB 15 -#define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 -#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000 - -#define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_PPDU_START_RESERVED_0A_LSB 24 -#define RX_PPDU_START_RESERVED_0A_MSB 31 -#define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000 - -#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000 -#define RX_PPDU_START_SW_PHY_META_DATA_LSB 32 -#define RX_PPDU_START_SW_PHY_META_DATA_MSB 63 -#define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000 - -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff - -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 -#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 - -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 -#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff - -#define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010 -#define RX_PPDU_START_TLV64_PADDING_LSB 32 -#define RX_PPDU_START_TLV64_PADDING_MSB 63 -#define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_start_user_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_start_user_info.h deleted file mode 100644 index 16d3bb33edb4..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_ppdu_start_user_info.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PPDU_START_USER_INFO_H_ -#define _RX_PPDU_START_USER_INFO_H_ - -#include "receive_user_info.h" -#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8 - -#define NUM_OF_QWORDS_RX_PPDU_START_USER_INFO 4 - -struct rx_ppdu_start_user_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct receive_user_info receive_user_info_details; -#else - struct receive_user_info receive_user_info_details; -#endif -}; - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 36 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000001f00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 37 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 38 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000006000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 1 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x0000000000000002 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_LSB 2 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MSB 3 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF1_MASK 0x000000000000000c - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_LSB 4 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MSB 5 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF2_MASK 0x0000000000000030 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_LSB 6 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MSB 7 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_QAM_DIFF3_MASK 0x00000000000000c0 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_LSB 62 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MSB 62 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_2X_CODEWORD_MASK 0x4000000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0x8000000000000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000 - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff - -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63 -#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_preamble.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_preamble.h deleted file mode 100644 index 807463753865..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_preamble.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_PREAMBLE_H_ -#define _RX_PREAMBLE_H_ - -#define NUM_OF_DWORDS_RX_PREAMBLE 2 - -#define NUM_OF_QWORDS_RX_PREAMBLE 1 - -struct rx_preamble { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t num_users : 6, - pkt_type : 4, - direction : 1, - reserved_0a : 21; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 21, - direction : 1, - pkt_type : 4, - num_users : 6; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_PREAMBLE_NUM_USERS_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_NUM_USERS_LSB 0 -#define RX_PREAMBLE_NUM_USERS_MSB 5 -#define RX_PREAMBLE_NUM_USERS_MASK 0x000000000000003f - -#define RX_PREAMBLE_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_PKT_TYPE_LSB 6 -#define RX_PREAMBLE_PKT_TYPE_MSB 9 -#define RX_PREAMBLE_PKT_TYPE_MASK 0x00000000000003c0 - -#define RX_PREAMBLE_DIRECTION_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_DIRECTION_LSB 10 -#define RX_PREAMBLE_DIRECTION_MSB 10 -#define RX_PREAMBLE_DIRECTION_MASK 0x0000000000000400 - -#define RX_PREAMBLE_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_RESERVED_0A_LSB 11 -#define RX_PREAMBLE_RESERVED_0A_MSB 31 -#define RX_PREAMBLE_RESERVED_0A_MASK 0x00000000fffff800 - -#define RX_PREAMBLE_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_PREAMBLE_TLV64_PADDING_LSB 32 -#define RX_PREAMBLE_TLV64_PADDING_MSB 63 -#define RX_PREAMBLE_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_response_required_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_response_required_info.h deleted file mode 100644 index e6ee112bb1ac..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_response_required_info.h +++ /dev/null @@ -1,764 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_RESPONSE_REQUIRED_INFO_H_ -#define _RX_RESPONSE_REQUIRED_INFO_H_ - -#include "mlo_sta_id_details.h" -#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16 - -#define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8 - -struct rx_response_required_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_ppdu_id : 16, - su_or_uplink_mu_reception : 1, - trigger_frame_received : 1, - __reserved_g_0012 : 2, - tb___reserved_g_0005_response_required : 2, - mac_security : 1, - filter_pass_monitor_ovrd : 1, - ast_search_incomplete : 1, - r2r_end_status_to_follow : 1, - __reserved_g_0016_listen_cca_check_at_phy_desc : 1, - __reserved_g_0016_listen_indication : 1, - three_or_more_type_subtypes : 1, - wait_sifs_config_valid : 1, - wait_sifs : 2; - uint32_t general_frame_control : 16, - second_frame_control : 16; - uint32_t duration : 16, - pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5, - sgi : 2, - stbc : 1, - ldpc : 1, - ampdu : 1, - rts_ta_grp_bit : 1; - uint32_t ctrl_frame_soliciting_resp : 1, - ast_fail_for_dot11ax_su_ext : 1, - service_dynamic : 1, - m_pkt : 1, - sta_partial_aid : 12, - group_id : 6, - ctrl_resp_pwr_mgmt : 1, - response_indication : 2, - ndp_indication : 1, - ndp_frame_type : 3, - second_frame_control_valid : 1, - ack_ba_resp_more_data : 1, - vht_ack : 1; - uint32_t sta_aid : 11, - interference : 1, - ects_as_tb_ppdu : 1, - ll_traffic_indication : 1, - reserved_4a : 2, - ack_id_ext : 10, - agc_cbw : 3, - service_cbw : 3; - uint32_t response_sta_count : 7, - __reserved_g_0086 : 1, - blackout_details_en : 1, - reserved : 2, - ht_vht_sig_cbw : 3, - cts_cbw : 3, - response_ack_count : 7, - response_assoc_ack_count : 7, - txop_duration_all_ones : 1; - uint32_t response_ba32_count : 7, - response_ba64_count : 7, - response_ba128_count : 7, - response_ba256_count : 7, - multi_tid : 1, - sw_response_tlv_from_crypto : 1, - dot11ax_dl_ul_flag : 1, - emlsr_main_tlv_if : 1; - uint32_t sw_response_frame_length : 16, - response_ba512_count : 7, - response_ba1024_count : 7, - reserved_7a : 2; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t dot11ax_received_format_indication : 1, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_bss_color_id : 6, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_cp_size : 2, - dot11ax_received_ltf_size : 2, - dot11ax_received_coding : 1, - dot11ax_received_dcm : 1, - dot11ax_received_doppler_indication : 1, - dot11ax_received_ext_ru_size : 4, - ftm_fields_valid : 1, - ftm_pe_nss : 3, - ftm_pe_ltf_size : 2, - ftm_pe_content : 1, - ftm_chain_csd_en : 1, - ftm_pe_chain_csd_en : 1; - uint32_t dot11ax_response_rate_source : 8, - dot11ax_ext_response_rate_source : 8, - sw_peer_id : 16; - uint32_t dot11be_puncture_bitmap : 16, - dot11be_response : 1, - punctured_response : 1, - eht_duplicate_mode : 2, - force_extra_symbol : 1, - ctrl_pkt_protect : 1, - mac_hdr_protect : 1, - reserved_13a : 3, - u_sig_puncture_pattern_encoding : 6; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint16_t he_a_control_response_time : 12, - reserved_after_struct16 : 4; - uint32_t dso_primary20_index_select : 4, - dso_freq_subband_channel_bonding_mask : 16, - pad_duration : 5, - q2q_mba : 1, - reserved_15a : 6; -#else - uint32_t wait_sifs : 2, - wait_sifs_config_valid : 1, - three_or_more_type_subtypes : 1, - __reserved_g_0016_listen_indication : 1, - __reserved_g_0016_listen_cca_check_at_phy_desc : 1, - r2r_end_status_to_follow : 1, - ast_search_incomplete : 1, - filter_pass_monitor_ovrd : 1, - mac_security : 1, - tb___reserved_g_0005_response_required : 2, - __reserved_g_0012 : 2, - trigger_frame_received : 1, - su_or_uplink_mu_reception : 1, - phy_ppdu_id : 16; - uint32_t second_frame_control : 16, - general_frame_control : 16; - uint32_t rts_ta_grp_bit : 1, - ampdu : 1, - ldpc : 1, - stbc : 1, - sgi : 2, - rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4, - duration : 16; - uint32_t vht_ack : 1, - ack_ba_resp_more_data : 1, - second_frame_control_valid : 1, - ndp_frame_type : 3, - ndp_indication : 1, - response_indication : 2, - ctrl_resp_pwr_mgmt : 1, - group_id : 6, - sta_partial_aid : 12, - m_pkt : 1, - service_dynamic : 1, - ast_fail_for_dot11ax_su_ext : 1, - ctrl_frame_soliciting_resp : 1; - uint32_t service_cbw : 3, - agc_cbw : 3, - ack_id_ext : 10, - reserved_4a : 2, - ll_traffic_indication : 1, - ects_as_tb_ppdu : 1, - interference : 1, - sta_aid : 11; - uint32_t txop_duration_all_ones : 1, - response_assoc_ack_count : 7, - response_ack_count : 7, - cts_cbw : 3, - ht_vht_sig_cbw : 3, - reserved : 2, - blackout_details_en : 1, - __reserved_g_0086 : 1, - response_sta_count : 7; - uint32_t emlsr_main_tlv_if : 1, - dot11ax_dl_ul_flag : 1, - sw_response_tlv_from_crypto : 1, - multi_tid : 1, - response_ba256_count : 7, - response_ba128_count : 7, - response_ba64_count : 7, - response_ba32_count : 7; - uint32_t reserved_7a : 2, - response_ba1024_count : 7, - response_ba512_count : 7, - sw_response_frame_length : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t ftm_pe_chain_csd_en : 1, - ftm_chain_csd_en : 1, - ftm_pe_content : 1, - ftm_pe_ltf_size : 2, - ftm_pe_nss : 3, - ftm_fields_valid : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_received_doppler_indication : 1, - dot11ax_received_dcm : 1, - dot11ax_received_coding : 1, - dot11ax_received_ltf_size : 2, - dot11ax_received_cp_size : 2, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_bss_color_id : 6, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_format_indication : 1; - uint32_t sw_peer_id : 16, - dot11ax_ext_response_rate_source : 8, - dot11ax_response_rate_source : 8; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_13a : 3, - mac_hdr_protect : 1, - ctrl_pkt_protect : 1, - force_extra_symbol : 1, - eht_duplicate_mode : 2, - punctured_response : 1, - dot11be_response : 1, - dot11be_puncture_bitmap : 16; - uint32_t reserved_after_struct16 : 4, - he_a_control_response_time : 12; - struct mlo_sta_id_details mlo_sta_id_details_rx; - uint32_t reserved_15a : 6, - q2q_mba : 1, - pad_duration : 5, - dso_freq_subband_channel_bonding_mask : 16, - dso_primary20_index_select : 4; -#endif -}; - -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x000000000000ffff - -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x0000000000010000 - -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17 -#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x0000000000020000 - -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22 -#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x0000000000400000 - -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23 -#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x0000000000800000 - -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24 -#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x0000000001000000 - -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000002000000 - -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0x00000000c0000000 - -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x0000000000000000 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x000000000000ffff - -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19 -#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x00000000000f0000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000100000 - -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x0000000003e00000 - -#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 26 -#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x000000000c000000 - -#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 30 -#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x0000000040000000 - -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x0000000080000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 32 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x0000000100000000 - -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 33 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 33 -#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x0000000200000000 - -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 34 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 34 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x0000000400000000 - -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 35 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 35 -#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x0000000800000000 - -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 36 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff000000000 - -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 53 -#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 54 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x0040000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 56 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x0180000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 57 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 57 -#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x0200000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 58 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 60 -#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 61 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x2000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MASK 0x4000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x0000000000000008 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MSB 10 -#define RX_RESPONSE_REQUIRED_INFO_STA_AID_MASK 0x00000000000007ff - -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_LSB 11 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MSB 11 -#define RX_RESPONSE_REQUIRED_INFO_INTERFERENCE_MASK 0x0000000000000800 - -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_LSB 12 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MSB 12 -#define RX_RESPONSE_REQUIRED_INFO_ECTS_AS_TB_PPDU_MASK 0x0000000000001000 - -#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_LSB 13 -#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_MSB 13 -#define RX_RESPONSE_REQUIRED_INFO_LL_TRAFFIC_INDICATION_MASK 0x0000000000002000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_LSB 14 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_4A_MASK 0x000000000000c000 - -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25 -#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x0000000003ff0000 - -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x000000001c000000 - -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0x00000000e0000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 38 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f00000000 - -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_LSB 40 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MSB 40 -#define RX_RESPONSE_REQUIRED_INFO_BLACKOUT_DETAILS_EN_MASK 0x0000010000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 41 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 42 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x0000060000000000 - -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 43 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 45 -#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x0000380000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 46 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c00000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 56 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000010 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x000000000000007f - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x0000000000003f80 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x00000000001fc000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x000000000fe00000 - -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28 -#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x0000000010000000 - -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000020000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000040000000 - -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_LSB 31 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MASK 0x0000000080000000 - -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f80000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000000000000018 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0x00000000ffffffff - -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x0000000000000020 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0x00000000ffffffff - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 49 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 55 -#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x0080000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 56 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 58 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x0700000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 59 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 60 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x1800000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 61 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 61 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x2000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 62 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 62 -#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x4000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000028 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 63 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x00000000000000ff - -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x000000000000ff00 - -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0x00000000ffff0000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 48 -#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 49 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 49 -#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 50 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 51 -#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 52 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 52 -#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x0010000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_LSB 53 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MSB 53 -#define RX_RESPONSE_REQUIRED_INFO_CTRL_PKT_PROTECT_MASK 0x0020000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_LSB 54 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MSB 54 -#define RX_RESPONSE_REQUIRED_INFO_MAC_HDR_PROTECT_MASK 0x0040000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 55 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 57 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x0380000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 - -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 -#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 - -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27 -#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x000000000fff0000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0x00000000f0000000 - -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_LSB 32 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MSB 35 -#define RX_RESPONSE_REQUIRED_INFO_DSO_PRIMARY20_INDEX_SELECT_MASK 0x0000000f00000000 - -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_LSB 36 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MSB 51 -#define RX_RESPONSE_REQUIRED_INFO_DSO_FREQ_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000ffff000000000 - -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_LSB 52 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MSB 56 -#define RX_RESPONSE_REQUIRED_INFO_PAD_DURATION_MASK 0x01f0000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_LSB 57 -#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_MSB 57 -#define RX_RESPONSE_REQUIRED_INFO_Q2Q_MBA_MASK 0x0200000000000000 - -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_OFFSET 0x0000000000000038 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_LSB 58 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MSB 63 -#define RX_RESPONSE_REQUIRED_INFO_RESERVED_15A_MASK 0xfc00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_rxpcu_classification_overview.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_rxpcu_classification_overview.h deleted file mode 100644 index 92489a5f5b2d..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_rxpcu_classification_overview.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ -#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ - -#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 - -struct rx_rxpcu_classification_overview { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t filter_pass_mpdus : 1, - filter_pass_mpdus_fcs_ok : 1, - monitor_direct_mpdus : 1, - monitor_direct_mpdus_fcs_ok : 1, - monitor_other_mpdus : 1, - monitor_other_mpdus_fcs_ok : 1, - phyrx_abort_received : 1, - filter_pass_monitor_ovrd_mpdus : 1, - filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, - reserved_0 : 7, - phy_ppdu_id : 16; -#else - uint32_t phy_ppdu_id : 16, - reserved_0 : 7, - filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, - filter_pass_monitor_ovrd_mpdus : 1, - phyrx_abort_received : 1, - monitor_other_mpdus_fcs_ok : 1, - monitor_other_mpdus : 1, - monitor_direct_mpdus_fcs_ok : 1, - monitor_direct_mpdus : 1, - filter_pass_mpdus_fcs_ok : 1, - filter_pass_mpdus : 1; -#endif -}; - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB 0 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB 0 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK 0x00000001 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB 1 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB 1 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB 2 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB 2 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK 0x00000004 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB 4 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB 4 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK 0x00000010 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB 6 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB 6 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK 0x00000040 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB 9 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB 15 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK 0x0000fe00 - -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET 0x00000000 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB 16 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB 31 -#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_start_param.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_start_param.h deleted file mode 100644 index bb2b87e3cc97..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_start_param.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_START_PARAM_H_ -#define _RX_START_PARAM_H_ - -#define NUM_OF_DWORDS_RX_START_PARAM 2 - -#define NUM_OF_QWORDS_RX_START_PARAM 1 - -struct rx_start_param { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pkt_type : 4, - reserved_0a : 12, - remaining_rx_time : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t remaining_rx_time : 16, - reserved_0a : 12, - pkt_type : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RX_START_PARAM_PKT_TYPE_OFFSET 0x0000000000000000 -#define RX_START_PARAM_PKT_TYPE_LSB 0 -#define RX_START_PARAM_PKT_TYPE_MSB 3 -#define RX_START_PARAM_PKT_TYPE_MASK 0x000000000000000f - -#define RX_START_PARAM_RESERVED_0A_OFFSET 0x0000000000000000 -#define RX_START_PARAM_RESERVED_0A_LSB 4 -#define RX_START_PARAM_RESERVED_0A_MSB 15 -#define RX_START_PARAM_RESERVED_0A_MASK 0x000000000000fff0 - -#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET 0x0000000000000000 -#define RX_START_PARAM_REMAINING_RX_TIME_LSB 16 -#define RX_START_PARAM_REMAINING_RX_TIME_MSB 31 -#define RX_START_PARAM_REMAINING_RX_TIME_MASK 0x00000000ffff0000 - -#define RX_START_PARAM_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RX_START_PARAM_TLV64_PADDING_LSB 32 -#define RX_START_PARAM_TLV64_PADDING_MSB 63 -#define RX_START_PARAM_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_timing_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_timing_info.h deleted file mode 100644 index ea6780e25c55..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_timing_info.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_TIMING_INFO_H_ -#define _RX_TIMING_INFO_H_ - -#define NUM_OF_DWORDS_RX_TIMING_INFO 5 - -struct rx_timing_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_timestamp_1_lower_32 : 32; - uint32_t phy_timestamp_1_upper_32 : 32; - uint32_t phy_timestamp_2_lower_32 : 32; - uint32_t phy_timestamp_2_upper_32 : 32; - uint32_t residual_phase_offset : 12, - sub_usec_ts_rx_end : 10, - reserved : 10; -#else - uint32_t phy_timestamp_1_lower_32 : 32; - uint32_t phy_timestamp_1_upper_32 : 32; - uint32_t phy_timestamp_2_lower_32 : 32; - uint32_t phy_timestamp_2_upper_32 : 32; - uint32_t reserved : 10, - sub_usec_ts_rx_end : 10, - residual_phase_offset : 12; -#endif -}; - -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000000 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000004 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x00000008 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000c -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31 -#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff - -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000010 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_LSB 0 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MSB 11 -#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff - -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_OFFSET 0x00000010 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_LSB 12 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MSB 21 -#define RX_TIMING_INFO_SUB_USEC_TS_RX_END_MASK 0x003ff000 - -#define RX_TIMING_INFO_RESERVED_OFFSET 0x00000010 -#define RX_TIMING_INFO_RESERVED_LSB 22 -#define RX_TIMING_INFO_RESERVED_MSB 31 -#define RX_TIMING_INFO_RESERVED_MASK 0xffc00000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rx_trig_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rx_trig_info.h deleted file mode 100644 index b6b074118bea..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rx_trig_info.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RX_TRIG_INFO_H_ -#define _RX_TRIG_INFO_H_ - -#define NUM_OF_DWORDS_RX_TRIG_INFO 2 - -#define NUM_OF_QWORDS_RX_TRIG_INFO 1 - -struct rx_trig_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rx_trigger_frame_type : 2, - trigger_resp_type : 3, - reserved_0 : 27; - uint32_t ppdu_duration : 16, - unique_destination_id : 16; -#else - uint32_t reserved_0 : 27, - trigger_resp_type : 3, - rx_trigger_frame_type : 2; - uint32_t unique_destination_id : 16, - ppdu_duration : 16; -#endif -}; - -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1 -#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x0000000000000003 - -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4 -#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x000000000000001c - -#define RX_TRIG_INFO_RESERVED_0_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_RESERVED_0_LSB 5 -#define RX_TRIG_INFO_RESERVED_0_MSB 31 -#define RX_TRIG_INFO_RESERVED_0_MASK 0x00000000ffffffe0 - -#define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_PPDU_DURATION_LSB 32 -#define RX_TRIG_INFO_PPDU_DURATION_MSB 47 -#define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff00000000 - -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x0000000000000000 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 48 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 63 -#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_early_rx_indication.h b/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_early_rx_indication.h deleted file mode 100644 index d2dc464cf1cf..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_early_rx_indication.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_EARLY_RX_INDICATION_H_ -#define _RXPCU_EARLY_RX_INDICATION_H_ - -#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 2 - -#define NUM_OF_QWORDS_RXPCU_EARLY_RX_INDICATION 1 - -struct rxpcu_early_rx_indication { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5, - dot11ax_received_ext_ru_size : 4, - reserved_0a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 18, - dot11ax_received_ext_ru_size : 4, - rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4; - uint32_t tlv64_padding : 32; -#endif -}; - -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB 0 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB 3 -#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK 0x000000000000000f - -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB 4 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB 4 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK 0x0000000000000010 - -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB 5 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB 9 -#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK 0x00000000000003e0 - -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 10 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 13 -#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0000000000003c00 - -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB 14 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB 31 -#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK 0x00000000ffffc000 - -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_OFFSET 0x0000000000000000 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_LSB 32 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MSB 63 -#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_ppdu_end_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_ppdu_end_info.h deleted file mode 100644 index c97ad08c26a4..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_ppdu_end_info.h +++ /dev/null @@ -1,925 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_PPDU_END_INFO_H_ -#define _RXPCU_PPDU_END_INFO_H_ - -#include "phyrx_abort_request_info.h" -#include "macrx_abort_request_info.h" -#include "rxpcu_ppdu_end_layout_info.h" -#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 32 - -#define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 16 - -struct rxpcu_ppdu_end_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t wb_timestamp_lower_32 : 32; - uint32_t wb_timestamp_upper_32 : 32; - uint32_t rx_antenna : 24, - tx_ht_vht_ack : 1, - unsupported_mu_nc : 1, - otp_txbf_disable : 1, - previous_tlv_corrupted : 1, - phyrx_abort_request_info_valid : 1, - macrx_abort_request_info_valid : 1, - coex_wan_tx_from_start_of_rx_ratid1 : 1, - coex_wan_tx_after_start_of_rx_ratid1 : 1; - uint32_t coex_bt_tx_from_start_of_rx : 1, - coex_bt_tx_after_start_of_rx : 1, - coex_wan_tx_from_start_of_rx : 1, - coex_wan_tx_after_start_of_rx : 1, - coex_wlan_tx_from_start_of_rx : 1, - coex_wlan_tx_after_start_of_rx : 1, - mpdu_delimiter_errors_seen : 1, - __reserved_g_0012 : 2, - dialog_token : 8, - follow_up_dialog_token : 8, - bb_captured_channel : 1, - bb_captured_reason : 3, - bb_captured_timeout : 1, - __reserved_g_0054 : 1, - __reserved_g_0058 : 1; - uint32_t before_mpdu_count_passing_fcs : 10, - before_mpdu_count_failing_fcs : 10, - after_mpdu_count_passing_fcs : 10, - reserved_4 : 2; - uint32_t after_mpdu_count_failing_fcs : 10, - reserved_5 : 22; - uint32_t phy_timestamp_tx_lower_32 : 32; - uint32_t phy_timestamp_tx_upper_32 : 32; - uint32_t bb_length : 16, - bb_data : 1, - reserved_8 : 3, - first_bt_broadcast_status_details : 12; - uint32_t rx_ppdu_duration : 24, - reserved_9 : 8; - uint32_t ast_index : 16, - ast_index_valid : 1, - reserved_10 : 3, - second_bt_broadcast_status_details : 12; - struct phyrx_abort_request_info phyrx_abort_request_info_details; - struct macrx_abort_request_info macrx_abort_request_info_details; - uint16_t pre_bt_broadcast_status_details : 12, - reserved_12a : 4; - uint32_t non_qos_sn_info_valid : 1, - rts_or_trig_protected_ppdu : 1, - rts_or_trig_prot_type : 2, - reserved_13a : 2, - non_qos_sn_highest : 12, - non_qos_sn_highest_retry_setting : 1, - non_qos_sn_lowest : 12, - non_qos_sn_lowest_retry_setting : 1; - uint32_t qos_sn_1_info_valid : 1, - reserved_14a : 1, - qos_sn_1_tid : 4, - qos_sn_1_highest : 12, - qos_sn_1_highest_retry_setting : 1, - qos_sn_1_lowest : 12, - qos_sn_1_lowest_retry_setting : 1; - uint32_t qos_sn_2_info_valid : 1, - reserved_15a : 1, - qos_sn_2_tid : 4, - qos_sn_2_highest : 12, - qos_sn_2_highest_retry_setting : 1, - qos_sn_2_lowest : 12, - qos_sn_2_lowest_retry_setting : 1; - struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; - uint32_t corrupted_due_to_fifo_delay : 1, - qos_sn_1_more_frag_state : 1, - qos_sn_1_frag_num_state : 4, - qos_sn_2_more_frag_state : 1, - qos_sn_2_frag_num_state : 4, - rts_or_trig_prot_non_11a : 1, - rts_or_trig_prot_rate_mcs : 4, - rts_or_trig_prot_peer_addr_15_0 : 16; - uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; - uint32_t rts_or_trig_rx_count : 32; - uint32_t cts_or_null_tx_count : 32; - uint32_t coex_tracker2_tx_from_start_of_rx : 1, - coex_tracker2_tx_after_start_of_rx : 1, - coex_tracker3_tx_from_start_of_rx : 1, - coex_tracker3_tx_after_start_of_rx : 1, - coex_tracker4_tx_from_start_of_rx : 1, - coex_tracker4_tx_after_start_of_rx : 1, - coex_tracker5_tx_from_start_of_rx : 1, - coex_tracker5_tx_after_start_of_rx : 1, - coex_tracker6_tx_from_start_of_rx : 1, - coex_tracker6_tx_after_start_of_rx : 1, - reserved_30a : 22; - uint32_t rx_ppdu_end_marker : 32; -#else - uint32_t wb_timestamp_lower_32 : 32; - uint32_t wb_timestamp_upper_32 : 32; - uint32_t coex_wan_tx_after_start_of_rx_ratid1 : 1, - coex_wan_tx_from_start_of_rx_ratid1 : 1, - macrx_abort_request_info_valid : 1, - phyrx_abort_request_info_valid : 1, - previous_tlv_corrupted : 1, - otp_txbf_disable : 1, - unsupported_mu_nc : 1, - tx_ht_vht_ack : 1, - rx_antenna : 24; - uint32_t __reserved_g_0058 : 1, - __reserved_g_0054 : 1, - bb_captured_timeout : 1, - bb_captured_reason : 3, - bb_captured_channel : 1, - follow_up_dialog_token : 8, - dialog_token : 8, - __reserved_g_0012 : 2, - mpdu_delimiter_errors_seen : 1, - coex_wlan_tx_after_start_of_rx : 1, - coex_wlan_tx_from_start_of_rx : 1, - coex_wan_tx_after_start_of_rx : 1, - coex_wan_tx_from_start_of_rx : 1, - coex_bt_tx_after_start_of_rx : 1, - coex_bt_tx_from_start_of_rx : 1; - uint32_t reserved_4 : 2, - after_mpdu_count_passing_fcs : 10, - before_mpdu_count_failing_fcs : 10, - before_mpdu_count_passing_fcs : 10; - uint32_t reserved_5 : 22, - after_mpdu_count_failing_fcs : 10; - uint32_t phy_timestamp_tx_lower_32 : 32; - uint32_t phy_timestamp_tx_upper_32 : 32; - uint32_t first_bt_broadcast_status_details : 12, - reserved_8 : 3, - bb_data : 1, - bb_length : 16; - uint32_t reserved_9 : 8, - rx_ppdu_duration : 24; - uint32_t second_bt_broadcast_status_details : 12, - reserved_10 : 3, - ast_index_valid : 1, - ast_index : 16; - struct phyrx_abort_request_info phyrx_abort_request_info_details; - uint32_t reserved_12a : 4, - pre_bt_broadcast_status_details : 12; - struct macrx_abort_request_info macrx_abort_request_info_details; - uint32_t non_qos_sn_lowest_retry_setting : 1, - non_qos_sn_lowest : 12, - non_qos_sn_highest_retry_setting : 1, - non_qos_sn_highest : 12, - reserved_13a : 2, - rts_or_trig_prot_type : 2, - rts_or_trig_protected_ppdu : 1, - non_qos_sn_info_valid : 1; - uint32_t qos_sn_1_lowest_retry_setting : 1, - qos_sn_1_lowest : 12, - qos_sn_1_highest_retry_setting : 1, - qos_sn_1_highest : 12, - qos_sn_1_tid : 4, - reserved_14a : 1, - qos_sn_1_info_valid : 1; - uint32_t qos_sn_2_lowest_retry_setting : 1, - qos_sn_2_lowest : 12, - qos_sn_2_highest_retry_setting : 1, - qos_sn_2_highest : 12, - qos_sn_2_tid : 4, - reserved_15a : 1, - qos_sn_2_info_valid : 1; - struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; - uint32_t rts_or_trig_prot_peer_addr_15_0 : 16, - rts_or_trig_prot_rate_mcs : 4, - rts_or_trig_prot_non_11a : 1, - qos_sn_2_frag_num_state : 4, - qos_sn_2_more_frag_state : 1, - qos_sn_1_frag_num_state : 4, - qos_sn_1_more_frag_state : 1, - corrupted_due_to_fifo_delay : 1; - uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; - uint32_t rts_or_trig_rx_count : 32; - uint32_t cts_or_null_tx_count : 32; - uint32_t reserved_30a : 22, - coex_tracker6_tx_after_start_of_rx : 1, - coex_tracker6_tx_from_start_of_rx : 1, - coex_tracker5_tx_after_start_of_rx : 1, - coex_tracker5_tx_from_start_of_rx : 1, - coex_tracker4_tx_after_start_of_rx : 1, - coex_tracker4_tx_from_start_of_rx : 1, - coex_tracker3_tx_after_start_of_rx : 1, - coex_tracker3_tx_from_start_of_rx : 1, - coex_tracker2_tx_after_start_of_rx : 1, - coex_tracker2_tx_from_start_of_rx : 1; - uint32_t rx_ppdu_end_marker : 32; -#endif -}; - -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 32 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 63 -#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 -#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x0000000000ffffff - -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 -#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x0000000001000000 - -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 -#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x0000000002000000 - -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 -#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x0000000004000000 - -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 -#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x0000000008000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000010000000 - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000020000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_LSB 30 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MSB 30 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_RATID1_MASK 0x0000000040000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_LSB 31 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MSB 31 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_RATID1_MASK 0x0000000080000000 - -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 32 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 32 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 33 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 33 -#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 34 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 34 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x0000000400000000 - -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 35 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 35 -#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x0000000800000000 - -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 36 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 36 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x0000001000000000 - -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 37 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 37 -#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x0000002000000000 - -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 38 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 38 -#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x0000004000000000 - -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 41 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 48 -#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe0000000000 - -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 49 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 56 -#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 57 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 57 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x0200000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 58 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 60 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c00000000000000 - -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000000000008 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 61 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 61 -#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x2000000000000000 - -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x00000000000003ff - -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 -#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x00000000000ffc00 - -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x000000003ff00000 - -#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 -#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0x00000000c0000000 - -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 32 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 41 -#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x0000000000000010 -#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 42 -#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 63 -#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc0000000000 - -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x0000000000000018 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000000000000018 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 32 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 63 -#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 -#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x000000000000ffff - -#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 -#define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 -#define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x0000000000010000 - -#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 -#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 -#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x00000000000e0000 - -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 -#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 - -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 32 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 55 -#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x0000000000000020 -#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 56 -#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 63 -#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff00000000000000 - -#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 -#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 -#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x000000000000ffff - -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 -#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x0000000000010000 - -#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 -#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 -#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x00000000000e0000 - -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 -#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_LSB 42 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MSB 42 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MASK 0x0000040000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_LSB 43 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MSB 43 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MASK 0x0000080000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_LSB 44 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MSB 44 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MASK 0x0000100000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_LSB 45 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MSB 45 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MASK 0x0000200000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_LSB 46 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MSB 46 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MASK 0x0000400000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 47 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 47 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000800000000000 - -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 48 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 63 -#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff000000000000 - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff - -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 -#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x000000000000ff00 - -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 -#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x000000000fff0000 - -#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0x00000000f0000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 32 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 32 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_LSB 33 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MSB 33 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_LSB 34 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MSB 35 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MASK 0x0000000c00000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 36 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 37 -#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x0000003000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 38 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 49 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 50 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 50 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 51 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 62 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff8000000000000 - -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000030 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 63 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 63 -#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 -#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x000000000000003c - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x000000000003ffc0 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x0000000000040000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x000000007ff80000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x0000000080000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 32 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 32 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x0000000100000000 - -#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 33 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 33 -#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x0000000200000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 34 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 37 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c00000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 38 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 49 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 50 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 50 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 51 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 62 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff8000000000000 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 63 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 63 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x0000000000000003 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x00000000000000fc - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x0000000000003f00 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x00000000000fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x0000000003f00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 37 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 50 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 62 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x0000000000000040 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x8000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0x00000000f0000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000000000000048 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 60 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf000000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x000000000000007f - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x0000000000003f80 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0x00000000e0000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x0000000000000050 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 57 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x00000000000000ff - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0x00000000ff000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 40 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 47 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff0000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000000000000058 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 56 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff00000000000000 - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x0000000000000060 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x0000000000000060 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 32 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 63 -#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 -#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 -#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x000000000000003c - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x0000000000000040 - -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 -#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x0000000000000780 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_LSB 11 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MSB 11 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MASK 0x0000000000000800 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_LSB 12 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MSB 15 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MASK 0x000000000000f000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_LSB 16 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MSB 31 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MASK 0x00000000ffff0000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_OFFSET 0x0000000000000068 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_LSB 32 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MSB 63 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_OFFSET 0x0000000000000070 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_LSB 0 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MSB 31 -#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MASK 0x00000000ffffffff - -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_OFFSET 0x0000000000000070 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_LSB 32 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MSB 63 -#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MASK 0xffffffff00000000 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_LSB 0 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MSB 0 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_FROM_START_OF_RX_MASK 0x0000000000000001 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_LSB 1 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MSB 1 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER2_TX_AFTER_START_OF_RX_MASK 0x0000000000000002 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_LSB 2 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MSB 2 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_FROM_START_OF_RX_MASK 0x0000000000000004 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_LSB 3 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MSB 3 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER3_TX_AFTER_START_OF_RX_MASK 0x0000000000000008 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_LSB 4 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MSB 4 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_FROM_START_OF_RX_MASK 0x0000000000000010 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_LSB 5 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MSB 5 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER4_TX_AFTER_START_OF_RX_MASK 0x0000000000000020 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_LSB 6 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MSB 6 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_FROM_START_OF_RX_MASK 0x0000000000000040 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_LSB 7 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MSB 7 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER5_TX_AFTER_START_OF_RX_MASK 0x0000000000000080 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_LSB 8 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MSB 8 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_FROM_START_OF_RX_MASK 0x0000000000000100 - -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_LSB 9 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MSB 9 -#define RXPCU_PPDU_END_INFO_COEX_TRACKER6_TX_AFTER_START_OF_RX_MASK 0x0000000000000200 - -#define RXPCU_PPDU_END_INFO_RESERVED_30A_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_LSB 10 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_MSB 31 -#define RXPCU_PPDU_END_INFO_RESERVED_30A_MASK 0x00000000fffffc00 - -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x0000000000000078 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 32 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 63 -#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_ppdu_end_layout_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_ppdu_end_layout_info.h deleted file mode 100644 index 9d54e91522ec..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rxpcu_ppdu_end_layout_info.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_ -#define _RXPCU_PPDU_END_LAYOUT_INFO_H_ - -#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10 - -struct rxpcu_ppdu_end_layout_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t rssi_legacy_offset : 2, - l_sig_a_offset : 6, - l_sig_b_offset : 6, - ht_sig_offset : 6, - vht_sig_a_offset : 6, - repeat_l_sig_a_offset : 6; - uint32_t he_sig_a_su_offset : 6, - he_sig_a_mu_dl_offset : 6, - he_sig_a_mu_ul_offset : 6, - generic_u_sig_offset : 6, - rssi_ht_offset : 7, - reserved_1a : 1; - uint32_t vht_sig_b_su20_offset : 7, - vht_sig_b_su40_offset : 7, - vht_sig_b_su80_offset : 7, - vht_sig_b_su160_offset : 7, - reserved_2a : 4; - uint32_t vht_sig_b_mu20_offset : 7, - vht_sig_b_mu40_offset : 7, - vht_sig_b_mu80_offset : 7, - vht_sig_b_mu160_offset : 7, - reserved_3a : 4; - uint32_t he_sig_b1_mu_offset : 7, - he_sig_b2_mu_offset : 7, - he_sig_b2_ofdma_offset : 7, - first_generic_eht_sig_offset : 7, - multiple_generic_eht_sig_included : 1, - reserved_4a : 3; - uint32_t common_user_info_offset : 7, - first_debug_info_offset : 8, - multiple_debug_info_included : 1, - first_other_receive_info_offset : 8, - multiple_other_receive_info_included : 1, - reserved_5a : 7; - uint32_t data_done_offset : 8, - generated_cbf_details_offset : 8, - pkt_end_part1_offset : 8, - location_offset : 8; - uint32_t __reserved_g_0011 : 8, - pkt_end_offset : 8, - abort_request_ack_offset : 8, - reserved_7a : 8; - uint32_t reserved_8a : 32; - uint32_t reserved_9a : 32; -#else - uint32_t repeat_l_sig_a_offset : 6, - vht_sig_a_offset : 6, - ht_sig_offset : 6, - l_sig_b_offset : 6, - l_sig_a_offset : 6, - rssi_legacy_offset : 2; - uint32_t reserved_1a : 1, - rssi_ht_offset : 7, - generic_u_sig_offset : 6, - he_sig_a_mu_ul_offset : 6, - he_sig_a_mu_dl_offset : 6, - he_sig_a_su_offset : 6; - uint32_t reserved_2a : 4, - vht_sig_b_su160_offset : 7, - vht_sig_b_su80_offset : 7, - vht_sig_b_su40_offset : 7, - vht_sig_b_su20_offset : 7; - uint32_t reserved_3a : 4, - vht_sig_b_mu160_offset : 7, - vht_sig_b_mu80_offset : 7, - vht_sig_b_mu40_offset : 7, - vht_sig_b_mu20_offset : 7; - uint32_t reserved_4a : 3, - multiple_generic_eht_sig_included : 1, - first_generic_eht_sig_offset : 7, - he_sig_b2_ofdma_offset : 7, - he_sig_b2_mu_offset : 7, - he_sig_b1_mu_offset : 7; - uint32_t reserved_5a : 7, - multiple_other_receive_info_included : 1, - first_other_receive_info_offset : 8, - multiple_debug_info_included : 1, - first_debug_info_offset : 8, - common_user_info_offset : 7; - uint32_t location_offset : 8, - pkt_end_part1_offset : 8, - generated_cbf_details_offset : 8, - data_done_offset : 8; - uint32_t reserved_7a : 8, - abort_request_ack_offset : 8, - pkt_end_offset : 8, - __reserved_g_0011 : 8; - uint32_t reserved_8a : 32; - uint32_t reserved_9a : 32; -#endif -}; - -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003 - -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc - -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19 -#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30 -#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20 -#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6 -#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7 -#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff - -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15 -#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00 - -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16 -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23 -#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000 - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff - -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31 -#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/rxpt_classify_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/rxpt_classify_info.h deleted file mode 100644 index 7fc572ae2474..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/rxpt_classify_info.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _RXPT_CLASSIFY_INFO_H_ -#define _RXPT_CLASSIFY_INFO_H_ - -#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 - -struct rxpt_classify_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t reo_destination_indication : 5, - lmac_peer_id_msb : 2, - use_flow_id_toeplitz_clfy : 1, - pkt_selection_fp_ucast_data : 1, - pkt_selection_fp_mcast_data : 1, - pkt_selection_fp_1000 : 1, - rxdma0_source_ring_selection : 3, - rxdma0_destination_ring_selection : 3, - mcast_echo_drop_enable : 1, - wds_learning_detect_en : 1, - intrabss_check_en : 1, - use_ppe : 1, - ppe_routing_enable : 1, - cce_source_sel_en : 1, - reserved_0b : 9; -#else - uint32_t reserved_0b : 9, - cce_source_sel_en : 1, - ppe_routing_enable : 1, - use_ppe : 1, - intrabss_check_en : 1, - wds_learning_detect_en : 1, - mcast_echo_drop_enable : 1, - rxdma0_destination_ring_selection : 3, - rxdma0_source_ring_selection : 3, - pkt_selection_fp_1000 : 1, - pkt_selection_fp_mcast_data : 1, - pkt_selection_fp_ucast_data : 1, - use_flow_id_toeplitz_clfy : 1, - lmac_peer_id_msb : 2, - reo_destination_indication : 5; -#endif -}; - -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB 0 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB 4 -#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f - -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB 5 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB 6 -#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK 0x00000060 - -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 -#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB 8 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB 8 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB 9 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB 9 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 - -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB 10 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB 10 -#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK 0x00000400 - -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB 11 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB 13 -#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 - -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 -#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 - -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB 17 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB 17 -#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 - -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB 18 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB 18 -#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK 0x00040000 - -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB 19 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB 19 -#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK 0x00080000 - -#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_USE_PPE_LSB 20 -#define RXPT_CLASSIFY_INFO_USE_PPE_MSB 20 -#define RXPT_CLASSIFY_INFO_USE_PPE_MASK 0x00100000 - -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB 21 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB 21 -#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK 0x00200000 - -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_LSB 22 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MSB 22 -#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MASK 0x00400000 - -#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET 0x00000000 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB 23 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB 31 -#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK 0xff800000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/seq_hwio.h b/drivers/staging/fw-api/hw/wcn8750/v1/seq_hwio.h deleted file mode 100644 index 69111d08d535..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/seq_hwio.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef __SEQ_H__ -#define __SEQ_H__ - -#include "HALhwio.h" - -#define SEQ_INH(base, regtype, reg) \ - SEQ_##regtype##_INH(base, reg) - -#define SEQ_INMH(base, regtype, reg, mask) \ - SEQ_##regtype##_INMH(base, reg, mask) - -#define SEQ_INFH(base, regtype, reg, fld) \ - (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) - -#define SEQ_OUTH(base, regtype, reg, val) \ - SEQ_##regtype##_OUTH(base, reg, val) - -#define SEQ_OUTMH(base, regtype, reg, mask, val) \ - SEQ_##regtype##_OUTMH(base, reg, mask, val) - -#define SEQ_OUTFH(base, regtype, reg, fld, val) \ - SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) - -typedef enum { - SEC, - MS, - US, - NS -} SEQ_TimeUnit; - -extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); - -extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); - -#endif - diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tcl_assist_cmd.h b/drivers/staging/fw-api/hw/wcn8750/v1/tcl_assist_cmd.h deleted file mode 100644 index f7a5bd5287cb..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tcl_assist_cmd.h +++ /dev/null @@ -1,411 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TCL_ASSIST_CMD_H_ -#define _TCL_ASSIST_CMD_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_TCL_ASSIST_CMD 16 - -struct tcl_assist_cmd { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_addr_info; - uint32_t buf_or_ext_desc_type : 1, - bank_id : 6, - vdev_id : 8, - data_length : 14, - to_fw_tqm : 2, - reserved_2a : 1; - uint32_t reserved_3a : 25, - metadata_length : 7; - uint32_t txpt_classify_info_index : 8, - txpt_classify_info_sel : 5, - txpt_classify_info_override : 1, - flow_override_enable : 1, - flow_select : 1, - hlos_tid : 4, - hlos_tid_overwrite : 1, - tos_tc_value : 8, - reserved_4a : 3; - uint32_t reserved_5a : 16, - l3_type : 16; - uint32_t l4_protocol : 8, - l4_port : 16, - l4_port_type : 1, - da_is_bcast_mcast : 1, - da_is_bcast : 1, - reserved_6a : 5; - uint32_t ip_address_31_0 : 32; - uint32_t ip_address_63_32 : 32; - uint32_t ip_address_95_64 : 32; - uint32_t ip_address_127_96 : 32; - uint32_t ip_da_or_sa : 1, - encap_length_change : 6, - encap_length_decrease : 1, - encap_length_override : 1, - type_or_length : 1, - snap_oui_zero_or_f8 : 1, - snap_oui_not_zero_and_not_f8 : 1, - msdu_color : 2, - tx_notify_frame : 3, - tqm_no_drop : 1, - reserved_11a : 12, - l3_checksum_enable : 1, - l4_checksum_enable : 1; - uint32_t buffer_timestamp : 19, - buffer_timestamp_valid : 1, - s_vlan_tag_present : 1, - c_vlan_tag_present : 1, - wmac_hdr_len : 7, - reserved_12a : 3; - uint32_t tcl_cmd_number : 32; - uint32_t reserved_14a : 32; - uint32_t reserved_15a : 20, - ring_id : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_addr_info; - uint32_t reserved_2a : 1, - to_fw_tqm : 2, - data_length : 14, - vdev_id : 8, - bank_id : 6, - buf_or_ext_desc_type : 1; - uint32_t metadata_length : 7, - reserved_3a : 25; - uint32_t reserved_4a : 3, - tos_tc_value : 8, - hlos_tid_overwrite : 1, - hlos_tid : 4, - flow_select : 1, - flow_override_enable : 1, - txpt_classify_info_override : 1, - txpt_classify_info_sel : 5, - txpt_classify_info_index : 8; - uint32_t l3_type : 16, - reserved_5a : 16; - uint32_t reserved_6a : 5, - da_is_bcast : 1, - da_is_bcast_mcast : 1, - l4_port_type : 1, - l4_port : 16, - l4_protocol : 8; - uint32_t ip_address_31_0 : 32; - uint32_t ip_address_63_32 : 32; - uint32_t ip_address_95_64 : 32; - uint32_t ip_address_127_96 : 32; - uint32_t l4_checksum_enable : 1, - l3_checksum_enable : 1, - reserved_11a : 12, - tqm_no_drop : 1, - tx_notify_frame : 3, - msdu_color : 2, - snap_oui_not_zero_and_not_f8 : 1, - snap_oui_zero_or_f8 : 1, - type_or_length : 1, - encap_length_override : 1, - encap_length_decrease : 1, - encap_length_change : 6, - ip_da_or_sa : 1; - uint32_t reserved_12a : 3, - wmac_hdr_len : 7, - c_vlan_tag_present : 1, - s_vlan_tag_present : 1, - buffer_timestamp_valid : 1, - buffer_timestamp : 19; - uint32_t tcl_cmd_number : 32; - uint32_t reserved_14a : 32; - uint32_t looping_count : 4, - ring_id : 8, - reserved_15a : 20; -#endif -}; - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define TCL_ASSIST_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_LSB 0 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MSB 0 -#define TCL_ASSIST_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000001 - -#define TCL_ASSIST_CMD_BANK_ID_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_BANK_ID_LSB 1 -#define TCL_ASSIST_CMD_BANK_ID_MSB 6 -#define TCL_ASSIST_CMD_BANK_ID_MASK 0x0000007e - -#define TCL_ASSIST_CMD_VDEV_ID_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_VDEV_ID_LSB 7 -#define TCL_ASSIST_CMD_VDEV_ID_MSB 14 -#define TCL_ASSIST_CMD_VDEV_ID_MASK 0x00007f80 - -#define TCL_ASSIST_CMD_DATA_LENGTH_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_DATA_LENGTH_LSB 15 -#define TCL_ASSIST_CMD_DATA_LENGTH_MSB 28 -#define TCL_ASSIST_CMD_DATA_LENGTH_MASK 0x1fff8000 - -#define TCL_ASSIST_CMD_TO_FW_TQM_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_TO_FW_TQM_LSB 29 -#define TCL_ASSIST_CMD_TO_FW_TQM_MSB 30 -#define TCL_ASSIST_CMD_TO_FW_TQM_MASK 0x60000000 - -#define TCL_ASSIST_CMD_RESERVED_2A_OFFSET 0x00000008 -#define TCL_ASSIST_CMD_RESERVED_2A_LSB 31 -#define TCL_ASSIST_CMD_RESERVED_2A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_2A_MASK 0x80000000 - -#define TCL_ASSIST_CMD_RESERVED_3A_OFFSET 0x0000000c -#define TCL_ASSIST_CMD_RESERVED_3A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_3A_MSB 24 -#define TCL_ASSIST_CMD_RESERVED_3A_MASK 0x01ffffff - -#define TCL_ASSIST_CMD_METADATA_LENGTH_OFFSET 0x0000000c -#define TCL_ASSIST_CMD_METADATA_LENGTH_LSB 25 -#define TCL_ASSIST_CMD_METADATA_LENGTH_MSB 31 -#define TCL_ASSIST_CMD_METADATA_LENGTH_MASK 0xfe000000 - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_LSB 0 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MSB 7 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_INDEX_MASK 0x000000ff - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_LSB 8 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MSB 12 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_SEL_MASK 0x00001f00 - -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_LSB 13 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MSB 13 -#define TCL_ASSIST_CMD_TXPT_CLASSIFY_INFO_OVERRIDE_MASK 0x00002000 - -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_LSB 14 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MSB 14 -#define TCL_ASSIST_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00004000 - -#define TCL_ASSIST_CMD_FLOW_SELECT_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_FLOW_SELECT_LSB 15 -#define TCL_ASSIST_CMD_FLOW_SELECT_MSB 15 -#define TCL_ASSIST_CMD_FLOW_SELECT_MASK 0x00008000 - -#define TCL_ASSIST_CMD_HLOS_TID_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_HLOS_TID_LSB 16 -#define TCL_ASSIST_CMD_HLOS_TID_MSB 19 -#define TCL_ASSIST_CMD_HLOS_TID_MASK 0x000f0000 - -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_LSB 20 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MSB 20 -#define TCL_ASSIST_CMD_HLOS_TID_OVERWRITE_MASK 0x00100000 - -#define TCL_ASSIST_CMD_TOS_TC_VALUE_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_LSB 21 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_MSB 28 -#define TCL_ASSIST_CMD_TOS_TC_VALUE_MASK 0x1fe00000 - -#define TCL_ASSIST_CMD_RESERVED_4A_OFFSET 0x00000010 -#define TCL_ASSIST_CMD_RESERVED_4A_LSB 29 -#define TCL_ASSIST_CMD_RESERVED_4A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_4A_MASK 0xe0000000 - -#define TCL_ASSIST_CMD_RESERVED_5A_OFFSET 0x00000014 -#define TCL_ASSIST_CMD_RESERVED_5A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_5A_MSB 15 -#define TCL_ASSIST_CMD_RESERVED_5A_MASK 0x0000ffff - -#define TCL_ASSIST_CMD_L3_TYPE_OFFSET 0x00000014 -#define TCL_ASSIST_CMD_L3_TYPE_LSB 16 -#define TCL_ASSIST_CMD_L3_TYPE_MSB 31 -#define TCL_ASSIST_CMD_L3_TYPE_MASK 0xffff0000 - -#define TCL_ASSIST_CMD_L4_PROTOCOL_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PROTOCOL_LSB 0 -#define TCL_ASSIST_CMD_L4_PROTOCOL_MSB 7 -#define TCL_ASSIST_CMD_L4_PROTOCOL_MASK 0x000000ff - -#define TCL_ASSIST_CMD_L4_PORT_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PORT_LSB 8 -#define TCL_ASSIST_CMD_L4_PORT_MSB 23 -#define TCL_ASSIST_CMD_L4_PORT_MASK 0x00ffff00 - -#define TCL_ASSIST_CMD_L4_PORT_TYPE_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_LSB 24 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_MSB 24 -#define TCL_ASSIST_CMD_L4_PORT_TYPE_MASK 0x01000000 - -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_LSB 25 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MSB 25 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MCAST_MASK 0x02000000 - -#define TCL_ASSIST_CMD_DA_IS_BCAST_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_DA_IS_BCAST_LSB 26 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MSB 26 -#define TCL_ASSIST_CMD_DA_IS_BCAST_MASK 0x04000000 - -#define TCL_ASSIST_CMD_RESERVED_6A_OFFSET 0x00000018 -#define TCL_ASSIST_CMD_RESERVED_6A_LSB 27 -#define TCL_ASSIST_CMD_RESERVED_6A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_6A_MASK 0xf8000000 - -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_OFFSET 0x0000001c -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_31_0_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_OFFSET 0x00000020 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_63_32_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_OFFSET 0x00000024 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_95_64_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_OFFSET 0x00000028 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_LSB 0 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MSB 31 -#define TCL_ASSIST_CMD_IP_ADDRESS_127_96_MASK 0xffffffff - -#define TCL_ASSIST_CMD_IP_DA_OR_SA_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_IP_DA_OR_SA_LSB 0 -#define TCL_ASSIST_CMD_IP_DA_OR_SA_MSB 0 -#define TCL_ASSIST_CMD_IP_DA_OR_SA_MASK 0x00000001 - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_LSB 1 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MSB 6 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_CHANGE_MASK 0x0000007e - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_LSB 7 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MSB 7 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_DECREASE_MASK 0x00000080 - -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_LSB 8 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MSB 8 -#define TCL_ASSIST_CMD_ENCAP_LENGTH_OVERRIDE_MASK 0x00000100 - -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_LSB 9 -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MSB 9 -#define TCL_ASSIST_CMD_TYPE_OR_LENGTH_MASK 0x00000200 - -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_LSB 10 -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MSB 10 -#define TCL_ASSIST_CMD_SNAP_OUI_ZERO_OR_F8_MASK 0x00000400 - -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_LSB 11 -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MSB 11 -#define TCL_ASSIST_CMD_SNAP_OUI_NOT_ZERO_AND_NOT_F8_MASK 0x00000800 - -#define TCL_ASSIST_CMD_MSDU_COLOR_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_MSDU_COLOR_LSB 12 -#define TCL_ASSIST_CMD_MSDU_COLOR_MSB 13 -#define TCL_ASSIST_CMD_MSDU_COLOR_MASK 0x00003000 - -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_LSB 14 -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MSB 16 -#define TCL_ASSIST_CMD_TX_NOTIFY_FRAME_MASK 0x0001c000 - -#define TCL_ASSIST_CMD_TQM_NO_DROP_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_TQM_NO_DROP_LSB 17 -#define TCL_ASSIST_CMD_TQM_NO_DROP_MSB 17 -#define TCL_ASSIST_CMD_TQM_NO_DROP_MASK 0x00020000 - -#define TCL_ASSIST_CMD_RESERVED_11A_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_RESERVED_11A_LSB 18 -#define TCL_ASSIST_CMD_RESERVED_11A_MSB 29 -#define TCL_ASSIST_CMD_RESERVED_11A_MASK 0x3ffc0000 - -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_LSB 30 -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MSB 30 -#define TCL_ASSIST_CMD_L3_CHECKSUM_ENABLE_MASK 0x40000000 - -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_OFFSET 0x0000002c -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_LSB 31 -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MSB 31 -#define TCL_ASSIST_CMD_L4_CHECKSUM_ENABLE_MASK 0x80000000 - -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_LSB 0 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MSB 18 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_MASK 0x0007ffff - -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_LSB 19 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MSB 19 -#define TCL_ASSIST_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x00080000 - -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_LSB 20 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MSB 20 -#define TCL_ASSIST_CMD_S_VLAN_TAG_PRESENT_MASK 0x00100000 - -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_LSB 21 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MSB 21 -#define TCL_ASSIST_CMD_C_VLAN_TAG_PRESENT_MASK 0x00200000 - -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_LSB 22 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MSB 28 -#define TCL_ASSIST_CMD_WMAC_HDR_LEN_MASK 0x1fc00000 - -#define TCL_ASSIST_CMD_RESERVED_12A_OFFSET 0x00000030 -#define TCL_ASSIST_CMD_RESERVED_12A_LSB 29 -#define TCL_ASSIST_CMD_RESERVED_12A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_12A_MASK 0xe0000000 - -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_OFFSET 0x00000034 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_LSB 0 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MSB 31 -#define TCL_ASSIST_CMD_TCL_CMD_NUMBER_MASK 0xffffffff - -#define TCL_ASSIST_CMD_RESERVED_14A_OFFSET 0x00000038 -#define TCL_ASSIST_CMD_RESERVED_14A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_14A_MSB 31 -#define TCL_ASSIST_CMD_RESERVED_14A_MASK 0xffffffff - -#define TCL_ASSIST_CMD_RESERVED_15A_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_RESERVED_15A_LSB 0 -#define TCL_ASSIST_CMD_RESERVED_15A_MSB 19 -#define TCL_ASSIST_CMD_RESERVED_15A_MASK 0x000fffff - -#define TCL_ASSIST_CMD_RING_ID_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_RING_ID_LSB 20 -#define TCL_ASSIST_CMD_RING_ID_MSB 27 -#define TCL_ASSIST_CMD_RING_ID_MASK 0x0ff00000 - -#define TCL_ASSIST_CMD_LOOPING_COUNT_OFFSET 0x0000003c -#define TCL_ASSIST_CMD_LOOPING_COUNT_LSB 28 -#define TCL_ASSIST_CMD_LOOPING_COUNT_MSB 31 -#define TCL_ASSIST_CMD_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tcl_status_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/tcl_status_ring.h deleted file mode 100644 index 5a24217c95d5..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tcl_status_ring.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TCL_STATUS_RING_H_ -#define _TCL_STATUS_RING_H_ - -#define NUM_OF_DWORDS_TCL_STATUS_RING 8 - -struct tcl_status_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t gse_ctrl : 4, - ase_fse_sel : 1, - cache_op_res : 2, - index_search_en : 1, - msdu_cnt_n : 24; - uint32_t msdu_byte_cnt_n : 32; - uint32_t msdu_timestmp_n : 32; - uint32_t cmd_meta_data_31_0 : 32; - uint32_t cmd_meta_data_63_32 : 32; - uint32_t hash_indx_val : 20, - cache_set_num : 4, - reserved_5a : 8; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 20, - ring_id : 8, - looping_count : 4; -#else - uint32_t msdu_cnt_n : 24, - index_search_en : 1, - cache_op_res : 2, - ase_fse_sel : 1, - gse_ctrl : 4; - uint32_t msdu_byte_cnt_n : 32; - uint32_t msdu_timestmp_n : 32; - uint32_t cmd_meta_data_31_0 : 32; - uint32_t cmd_meta_data_63_32 : 32; - uint32_t reserved_5a : 8, - cache_set_num : 4, - hash_indx_val : 20; - uint32_t reserved_6a : 32; - uint32_t looping_count : 4, - ring_id : 8, - reserved_7a : 20; -#endif -}; - -#define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 -#define TCL_STATUS_RING_GSE_CTRL_LSB 0 -#define TCL_STATUS_RING_GSE_CTRL_MSB 3 -#define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f - -#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 -#define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 -#define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 -#define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 - -#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 -#define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 -#define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 -#define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 - -#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 -#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 - -#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 -#define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 -#define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 -#define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 - -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 -#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff - -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 -#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff - -#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c -#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 -#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 -#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff - -#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 -#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff - -#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 -#define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 -#define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 -#define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff - -#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 -#define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 -#define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 -#define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 - -#define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 -#define TCL_STATUS_RING_RESERVED_5A_LSB 24 -#define TCL_STATUS_RING_RESERVED_5A_MSB 31 -#define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 - -#define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 -#define TCL_STATUS_RING_RESERVED_6A_LSB 0 -#define TCL_STATUS_RING_RESERVED_6A_MSB 31 -#define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff - -#define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c -#define TCL_STATUS_RING_RESERVED_7A_LSB 0 -#define TCL_STATUS_RING_RESERVED_7A_MSB 19 -#define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff - -#define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c -#define TCL_STATUS_RING_RING_ID_LSB 20 -#define TCL_STATUS_RING_RING_ID_MSB 27 -#define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 - -#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 -#define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 -#define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tlv_hdr.h b/drivers/staging/fw-api/hw/wcn8750/v1/tlv_hdr.h deleted file mode 100644 index a2defe7be508..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tlv_hdr.h +++ /dev/null @@ -1,634 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TLV_HDR_H_ -#define _TLV_HDR_H_ - -#define _TLV_USERID_WIDTH_ 6 - -#define _TLV_MRV_EN_LEN_WIDTH_ 9 -#define _TLV_MRV_DIS_LEN_WIDTH_ 12 - -#define _TLV_DATA_WIDTH_ 32 -#define _TLV_64_DATA_WIDTH_ 64 -#define _TLV_CDATA_WIDTH_ 32 -#define _TLV_77_DATA_WIDTH_ 77 -#define _TLV_CDATA_77_WIDTH_ 64 - -#define _TLV_TAG_WIDTH_ 10 -#define _TLV_CTAG_WIDTH_ 6 - -struct tlv_mlo_usr_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mlo_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_32_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_32_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : 6; -#else - uint32_t tlv_reserved : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_64_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_64_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_usr_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_mac_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved_0a : 6, - dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint64_t pad_65to76_bit : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - pad_65to76_bit : 12; - uint64_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1, - tlv_reserved_0a : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_c_77_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata_lower_52 : 52; - uint64_t tlv_cdata_upper_12 : 12, - tlv_compression : 1, - pad_77to128_bit : 51; -#else - uint64_t pad_77to128_bit : 51, - tlv_compression : 1, - tlv_cdata_upper_12 : 12; - uint64_t tlv_cdata_lower_52 : 52, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_; -#endif -}; - -struct tlv_mlo_usr_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mlo_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_dst_linkid : 3, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_reserved : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_dst_linkid : 3, - tlv_len : _TLV_MRV_EN_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mac_usr_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_mac_64_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : _TLV_USERID_WIDTH_; -#else - uint32_t tlv_reserved : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; -#else - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; -#endif -}; - -struct tlv_usr_c_77_tlw32_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata_lower_20 : 20; - uint32_t tlv_cdata_middle_32 : 32; - uint32_t tlv_cdata_upper_12 : 12, - tlv_compression : 1, - pad_77to96_bit : 19; - uint32_t pad_96to128_bit : 32; -#else - uint32_t tlv_cdata_lower_20 : 20, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_; - uint32_t tlv_cdata_middle_32 : 32; - uint32_t pad_77to96_bit : 20, - tlv_compression : 1, - tlv_cdata_upper_12 : 12; - uint32_t pad_96to128_bit : 32; -#endif -}; - -struct tlv_usr_32_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_reserved : 32; -#else - uint64_t tlv_reserved : 32, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_32_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_reserved : 6, - pad_32to64_bit : 32; -#else - uint64_t pad_32to64_bit : 32, - tlv_reserved : 6, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_77_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint32_t pad_64to75_bit : 12, - tlv_compression : 1, - pad_77to95_bit : 19; -#else - uint32_t pad_77to95_bit : 19, - tlv_compression : 1, - pad_64to75_bit : 12; - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_77_hdr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tlv_tag : _TLV_TAG_WIDTH_, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_src_linkid : 3, - tlv_mrv : 1, - tlv_usrid : _TLV_USERID_WIDTH_; - uint32_t dso_subband0 : 1, - dso_subband1 : 1, - dso_subband2 : 1, - dso_subband3 : 1, - tlv_reserved_1a : 4, - npca_m_prim : 1, - npca_o_prim : 1, - tlv_reserved_1b : 2, - fbw : 1, - tlv_reserved_1c : 19; - uint32_t pad_64to75_bit : 12, - tlv_compression : 1, - pad_77to96_bit : 19; -#else - uint32_t pad_77to96_bit : 19, - tlv_compression : 1, - pad_64to75_bit : 12; - uint32_t tlv_reserved_1c : 19, - fbw : 1, - tlv_reserved_1b : 2, - npca_o_prim : 1, - npca_m_prim : 1, - tlv_reserved_1a : 4, - dso_subband3 : 1, - dso_subband2 : 1, - dso_subband1 : 1, - dso_subband0 : 1; - uint32_t tlv_usrid : _TLV_USERID_WIDTH_, - tlv_mrv : 1, - tlv_src_linkid : 3, - tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, - tlv_tag : _TLV_TAG_WIDTH_; -#endif -}; - -struct tlv_usr_c_44_tlword_t { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint64_t tlv_ctag : _TLV_CTAG_WIDTH_, - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_cdata : _TLV_CDATA_WIDTH_, - pad_44to64_bit : 20; -#else - uint64_t tlv_cdata_lower_20 : 20, - pad_44to64_bit : 20, - tlv_cdata_upper_12 : 12; - tlv_usrid : _TLV_USERID_WIDTH_, - tlv_ctag : _TLV_CTAG_WIDTH_, -#endif -}; - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tlv_tag_def.h b/drivers/staging/fw-api/hw/wcn8750/v1/tlv_tag_def.h deleted file mode 100644 index 8189c6ec5601..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tlv_tag_def.h +++ /dev/null @@ -1,1976 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TLV_TAG_DEF_ -#define _TLV_TAG_DEF_ - -typedef enum tlv_tag_def { - WIFIMACTX_CBF_START_E = 0 , - WIFIPHYRX_DATA_E = 1 , - WIFIPHYRX_CBF_DATA_RESP_E = 2 , - WIFIPHYRX_ABORT_REQUEST_E = 3 , - WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 , - WIFIMACTX_DATA_RESP_E = 5 , - WIFIMACTX_CBF_DATA_E = 6 , - WIFIMACTX_CBF_DONE_E = 7 , - WIFIPHYRX_LMR_DATA_RESP_E = 8 , - WIFIRXPCU_TO_UCODE_START_E = 9 , - WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 , - WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 , - WIFIRXPCU_TO_UCODE_FCS_STATUS_E = 12 , - WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 , - WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 , - WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 , - WIFIRXPCU_TO_UCODE_END_E = 16 , - WIFIPHYRX_RSSI_LEGACY_20MHZ_E = 17 , - WIFIPHYRX_NC_ABORT_REQUEST_E = 18 , - WIFIPHYRX_PKT_END_20MHZ_E = 19 , - WIFIPHYRX_NC_DATA_E = 20 , - WIFIMACRX_CBF_READ_REQUEST_E = 64 , - WIFIMACRX_CBF_DATA_REQUEST_E = 65 , - WIFIMACRX_EXPECT_NDP_RECEPTION_E = 66 , - WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 67 , - WIFIMACRX_NDP_TIMEOUT_E = 68 , - WIFIMACRX_ABORT_ACK_E = 69 , - WIFIMACRX_REQ_IMPLICIT_FB_E = 70 , - WIFIMACRX_CHAIN_MASK_E = 71 , - WIFIMACRX_NAP_USER_E = 72 , - WIFIMACRX_ABORT_REQUEST_E = 73 , - WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 74 , - WIFIPHYTX_ABORT_ACK_E = 75 , - WIFIPHYTX_ABORT_REQUEST_E = 76 , - WIFIPHYTX_PKT_END_E = 77 , - WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 78 , - WIFIPHYTX_REQUEST_CTRL_INFO_E = 79 , - WIFIPHYTX_DATA_REQUEST_E = 80 , - WIFIPHYTX_BF_CV_LOADING_DONE_E = 81 , - WIFIPHYTX_NAP_ACK_E = 82 , - WIFIPHYTX_NAP_DONE_E = 83 , - WIFIPHYTX_OFF_ACK_E = 84 , - WIFIPHYTX_ON_ACK_E = 85 , - WIFIPHYTX_SYNTH_OFF_ACK_E = 86 , - WIFIPHYTX_DEBUG16_E = 87 , - WIFIMACTX_ABORT_REQUEST_E = 88 , - WIFIMACTX_ABORT_ACK_E = 89 , - WIFIMACTX_PKT_END_E = 90 , - WIFIMACTX_PRE_PHY_DESC_E = 91 , - WIFIMACTX_BF_PARAMS_COMMON_E = 92 , - WIFIMACTX_BF_PARAMS_PER_USER_E = 93 , - WIFIMACTX_PREFETCH_CV_E = 94 , - WIFIMACTX_USER_DESC_COMMON_E = 95 , - WIFIMACTX_USER_DESC_PER_USER_E = 96 , - WIFIEXAMPLE_USER_TLV_16_E = 97 , - WIFIEXAMPLE_TLV_16_E = 98 , - WIFIMACTX_PHY_OFF_E = 99 , - WIFIMACTX_PHY_ON_E = 100 , - WIFIMACTX_SYNTH_OFF_E = 101 , - WIFIMACTX_EXPECT_CBF_COMMON_E = 102 , - WIFIMACTX_EXPECT_CBF_PER_USER_E = 103 , - WIFIMACTX_PHY_DESC_E = 104 , - WIFIMACTX_L_SIG_A_E = 105 , - WIFIMACTX_L_SIG_B_E = 106 , - WIFIMACTX_HT_SIG_E = 107 , - WIFIMACTX_VHT_SIG_A_E = 108 , - WIFIMACTX_VHT_SIG_B_SU20_E = 109 , - WIFIMACTX_VHT_SIG_B_SU40_E = 110 , - WIFIMACTX_VHT_SIG_B_SU80_E = 111 , - WIFIMACTX_VHT_SIG_B_SU160_E = 112 , - WIFIMACTX_VHT_SIG_B_MU20_E = 113 , - WIFIMACTX_VHT_SIG_B_MU40_E = 114 , - WIFIMACTX_VHT_SIG_B_MU80_E = 115 , - WIFIMACTX_VHT_SIG_B_MU160_E = 116 , - WIFIMACTX_SERVICE_E = 117 , - WIFIMACTX_HE_SIG_A_SU_E = 118 , - WIFIMACTX_HE_SIG_A_MU_DL_E = 119 , - WIFIMACTX_HE_SIG_A_MU_UL_E = 120 , - WIFIMACTX_HE_SIG_B1_MU_E = 121 , - WIFIMACTX_HE_SIG_B2_MU_E = 122 , - WIFIMACTX_HE_SIG_B2_OFDMA_E = 123 , - WIFIMACTX_DELETE_CV_E = 124 , - WIFIMACTX_MU_UPLINK_COMMON_E = 125 , - WIFIMACTX_MU_UPLINK_USER_SETUP_E = 126 , - WIFIMACTX_OTHER_TRANSMIT_INFO_E = 127 , - WIFIMACTX_PHY_NAP_E = 128 , - WIFIMACTX_DEBUG_E = 129 , - WIFIPHYRX_ABORT_ACK_E = 130 , - WIFIPHYRX_GENERATED_CBF_DETAILS_E = 131 , - WIFIPHYRX_RSSI_LEGACY_E = 132 , - WIFIPHYRX_RSSI_HT_E = 133 , - WIFIPHYRX_USER_INFO_E = 134 , - WIFIPHYRX_PKT_END_E = 135 , - WIFIPHYRX_DEBUG_E = 136 , - WIFIPHYRX_CBF_TRANSFER_DONE_E = 137 , - WIFIPHYRX_CBF_TRANSFER_ABORT_E = 138 , - WIFIPHYRX_L_SIG_A_E = 139 , - WIFIPHYRX_L_SIG_B_E = 140 , - WIFIPHYRX_HT_SIG_E = 141 , - WIFIPHYRX_VHT_SIG_A_E = 142 , - WIFIPHYRX_VHT_SIG_B_SU20_E = 143 , - WIFIPHYRX_VHT_SIG_B_SU40_E = 144 , - WIFIPHYRX_VHT_SIG_B_SU80_E = 145 , - WIFIPHYRX_VHT_SIG_B_SU160_E = 146 , - WIFIPHYRX_VHT_SIG_B_MU20_E = 147 , - WIFIPHYRX_VHT_SIG_B_MU40_E = 148 , - WIFIPHYRX_VHT_SIG_B_MU80_E = 149 , - WIFIPHYRX_VHT_SIG_B_MU160_E = 150 , - WIFIPHYRX_HE_SIG_A_SU_E = 151 , - WIFIPHYRX_HE_SIG_A_MU_DL_E = 152 , - WIFIPHYRX_HE_SIG_A_MU_UL_E = 153 , - WIFIPHYRX_HE_SIG_B1_MU_E = 154 , - WIFIPHYRX_HE_SIG_B2_MU_E = 155 , - WIFIPHYRX_HE_SIG_B2_OFDMA_E = 156 , - WIFIPHYRX_OTHER_RECEIVE_INFO_E = 157 , - WIFIPHYRX_COMMON_USER_INFO_E = 158 , - WIFIPHYRX_DATA_DONE_E = 159 , - WIFICOEX_TX_REQ_E = 160 , - WIFIDUMMY_E = 161 , - WIFIEXAMPLE_TLV_32_NAME_E = 162 , - WIFIMPDU_LIMIT_E = 163 , - WIFINA_LENGTH_END_E = 164 , - WIFIOLE_BUF_STATUS_E = 165 , - WIFIPCU_PPDU_SETUP_DONE_E = 166 , - WIFIPCU_PPDU_SETUP_END_E = 167 , - WIFIPCU_PPDU_SETUP_INIT_E = 168 , - WIFIPCU_PPDU_SETUP_START_E = 169 , - WIFIPDG_FES_SETUP_E = 170 , - WIFIPDG_RESPONSE_E = 171 , - WIFIPDG_TX_REQ_E = 172 , - WIFISCH_WAIT_INSTR_E = 173 , - WIFIMACTX_SWITCH_TO_MAIN_E = 174 , - WIFIPHYTX_LINK_STATE_E = 175 , - WIFIAUX_PPDU_END_E = 176 , - WIFITQM_GEN_MPDU_LENGTH_LIST_E = 177 , - WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 178 , - WIFITQM_GEN_MPDUS_E = 179 , - WIFITQM_GEN_MPDUS_STATUS_E = 180 , - WIFITQM_REMOVE_MPDU_E = 181 , - WIFITQM_REMOVE_MPDU_STATUS_E = 182 , - WIFITQM_REMOVE_MSDU_E = 183 , - WIFITQM_REMOVE_MSDU_STATUS_E = 184 , - WIFITQM_UPDATE_TX_MPDU_COUNT_E = 185 , - WIFITQM_WRITE_CMD_E = 186 , - WIFIOFDMA_TRIGGER_DETAILS_E = 187 , - WIFITX_DATA_E = 188 , - WIFITX_FES_SETUP_E = 189 , - WIFIRX_PACKET_E = 190 , - WIFIEXPECTED_RESPONSE_E = 191 , - WIFITX_MPDU_END_E = 192 , - WIFITX_MPDU_START_E = 193 , - WIFITX_MSDU_END_E = 194 , - WIFITX_MSDU_START_E = 195 , - WIFITX_SW_MODE_SETUP_E = 196 , - WIFITXPCU_BUFFER_STATUS_E = 197 , - WIFITXPCU_USER_BUFFER_STATUS_E = 198 , - WIFIDATA_TO_TIME_CONFIG_E = 199 , - WIFIEXAMPLE_USER_TLV_32_E = 200 , - WIFIMPDU_INFO_E = 201 , - WIFIPDG_USER_SETUP_E = 202 , - WIFITX_11AH_SETUP_E = 203 , - WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 204 , - WIFITX_PEER_ENTRY_E = 205 , - WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 206 , - WIFIEXAMPLE_USER_TLV_44_E = 207 , - WIFITX_FLUSH_E = 208 , - WIFITX_FLUSH_REQ_E = 209 , - WIFITQM_WRITE_CMD_STATUS_E = 210 , - WIFITQM_GET_MPDU_QUEUE_STATS_E = 211 , - WIFITQM_GET_MSDU_FLOW_STATS_E = 212 , - WIFIEXAMPLE_USER_CTLV_44_E = 213 , - WIFITX_FES_STATUS_START_E = 214 , - WIFITX_FES_STATUS_USER_PPDU_E = 215 , - WIFITX_FES_STATUS_USER_RESPONSE_E = 216 , - WIFITX_FES_STATUS_END_E = 217 , - WIFIRX_TRIG_INFO_E = 218 , - WIFIRXPCU_TX_SETUP_CLEAR_E = 219 , - WIFIRX_FRAME_BITMAP_REQ_E = 220 , - WIFIRX_FRAME_BITMAP_ACK_E = 221 , - WIFICOEX_RX_STATUS_E = 222 , - WIFIRX_START_PARAM_E = 223 , - WIFIRX_PPDU_START_E = 224 , - WIFIRX_PPDU_END_E = 225 , - WIFIRX_MPDU_START_E = 226 , - WIFIRX_MPDU_END_E = 227 , - WIFIRX_MSDU_START_E = 228 , - WIFIRX_MSDU_END_E = 229 , - WIFIRX_ATTENTION_E = 230 , - WIFIRECEIVED_RESPONSE_INFO_E = 231 , - WIFIRX_PHY_SLEEP_E = 232 , - WIFIRX_HEADER_E = 233 , - WIFIRX_PEER_ENTRY_E = 234 , - WIFIRX_FLUSH_E = 235 , - WIFIRX_RESPONSE_REQUIRED_INFO_E = 236 , - WIFIRX_FRAMELESS_BAR_DETAILS_E = 237 , - WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 238 , - WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 239 , - WIFITX_CBF_INFO_E = 240 , - WIFIPCU_PPDU_SETUP_USER_E = 241 , - WIFIRX_MPDU_PCU_START_E = 242 , - WIFIRX_PM_INFO_E = 243 , - WIFIRX_USER_PPDU_END_E = 244 , - WIFIRX_PRE_PPDU_START_E = 245 , - WIFIRX_PREAMBLE_E = 246 , - WIFITX_FES_SETUP_COMPLETE_E = 247 , - WIFITX_LAST_MPDU_FETCHED_E = 248 , - WIFITXDMA_STOP_REQUEST_E = 249 , - WIFIRXPCU_SETUP_E = 250 , - WIFIRXPCU_USER_SETUP_E = 251 , - WIFITX_FES_STATUS_ACK_OR_BA_E = 252 , - WIFITQM_ACKED_MPDU_E = 253 , - WIFICOEX_TX_RESP_E = 254 , - WIFICOEX_TX_STATUS_E = 255 , - WIFIMACTX_COEX_PHY_CTRL_E = 256 , - WIFICOEX_STATUS_BROADCAST_E = 257 , - WIFIRESPONSE_START_STATUS_E = 258 , - WIFIRESPONSE_END_STATUS_E = 259 , - WIFICRYPTO_STATUS_E = 260 , - WIFIRECEIVED_TRIGGER_INFO_E = 261 , - WIFICOEX_TX_STOP_CTRL_E = 262 , - WIFIRX_PPDU_ACK_REPORT_E = 263 , - WIFIRX_PPDU_NO_ACK_REPORT_E = 264 , - WIFISCH_COEX_STATUS_E = 265 , - WIFISCHEDULER_COMMAND_STATUS_E = 266 , - WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 267 , - WIFITX_FES_STATUS_PROT_E = 268 , - WIFITX_FES_STATUS_START_PPDU_E = 269 , - WIFITX_FES_STATUS_START_PROT_E = 270 , - WIFITXPCU_PHYTX_DEBUG32_E = 271 , - WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 272 , - WIFITX_MPDU_COUNT_TRANSFER_END_E = 273 , - WIFIWHO_ANCHOR_OFFSET_E = 274 , - WIFIWHO_ANCHOR_VALUE_E = 275 , - WIFIWHO_CCE_INFO_E = 276 , - WIFIWHO_COMMIT_E = 277 , - WIFIWHO_COMMIT_DONE_E = 278 , - WIFIWHO_FLUSH_E = 279 , - WIFIWHO_L2_LLC_E = 280 , - WIFIWHO_L2_PAYLOAD_E = 281 , - WIFIWHO_L3_CHECKSUM_E = 282 , - WIFIWHO_L3_INFO_E = 283 , - WIFIWHO_L4_CHECKSUM_E = 284 , - WIFIWHO_L4_INFO_E = 285 , - WIFIWHO_MSDU_E = 286 , - WIFIWHO_MSDU_MISC_E = 287 , - WIFIWHO_PACKET_DATA_E = 288 , - WIFIWHO_PACKET_HDR_E = 289 , - WIFIWHO_PPDU_END_E = 290 , - WIFIWHO_PPDU_START_E = 291 , - WIFIWHO_TSO_E = 292 , - WIFIWHO_WMAC_HEADER_PV0_E = 293 , - WIFIWHO_WMAC_HEADER_PV1_E = 294 , - WIFIWHO_WMAC_IV_E = 295 , - WIFIMPDU_INFO_END_E = 296 , - WIFIMPDU_INFO_BITMAP_E = 297 , - WIFITX_QUEUE_EXTENSION_E = 298 , - WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 299 , - WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 300 , - WIFITQM_ACKED_MPDU_STATUS_E = 301 , - WIFITQM_ADD_MSDU_STATUS_E = 302 , - WIFITQM_LIST_GEN_DONE_E = 303 , - WIFIWHO_TERMINATE_E = 304 , - WIFITX_LAST_MPDU_END_E = 305 , - WIFITX_CV_DATA_E = 306 , - WIFIPPDU_TX_END_E = 307 , - WIFIPROT_TX_END_E = 308 , - WIFIMPDU_INFO_GLOBAL_END_E = 309 , - WIFITQM_SCH_INSTR_GLOBAL_END_E = 310 , - WIFIRX_PPDU_END_USER_STATS_E = 311 , - WIFIRX_PPDU_END_USER_STATS_EXT_E = 312 , - WIFIREO_GET_QUEUE_STATS_E = 313 , - WIFIREO_FLUSH_QUEUE_E = 314 , - WIFIREO_FLUSH_CACHE_E = 315 , - WIFIREO_UNBLOCK_CACHE_E = 316 , - WIFIREO_GET_QUEUE_STATS_STATUS_E = 317 , - WIFIREO_FLUSH_QUEUE_STATUS_E = 318 , - WIFIREO_FLUSH_CACHE_STATUS_E = 319 , - WIFIREO_UNBLOCK_CACHE_STATUS_E = 320 , - WIFITQM_FLUSH_CACHE_E = 321 , - WIFITQM_UNBLOCK_CACHE_E = 322 , - WIFITQM_FLUSH_CACHE_STATUS_E = 323 , - WIFITQM_UNBLOCK_CACHE_STATUS_E = 324 , - WIFIRX_PPDU_END_STATUS_DONE_E = 325 , - WIFIRX_STATUS_BUFFER_DONE_E = 326 , - WIFISCHEDULER_MLO_SW_MSG_STATUS_E = 327 , - WIFISCHEDULER_TXOP_DURATION_TRIGGER_E = 328 , - WIFITX_DATA_SYNC_E = 329 , - WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 330 , - WIFITQM_GET_MPDU_HEAD_INFO_E = 331 , - WIFITQM_SYNC_CMD_E = 332 , - WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 333 , - WIFITQM_SYNC_CMD_STATUS_E = 334 , - WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 335 , - WIFITCC_TQM_WRAPPER_CMD_E = 336 , - WIFIREO_FLUSH_TIMEOUT_LIST_E = 337 , - WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 338 , - WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 339 , - WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 340 , - WIFIEXAMPLE_USER_TLV_32_NAME_E = 341 , - WIFIRX_PPDU_START_USER_INFO_E = 342 , - WIFIRX_RING_MASK_E = 343 , - WIFICOEX_MAC_NAP_E = 344 , - WIFIRXPCU_PPDU_END_INFO_E = 345 , - WIFIWHO_MESH_CONTROL_E = 346 , - WIFIPDG_SW_MODE_BW_START_E = 347 , - WIFIPDG_SW_MODE_BW_END_E = 348 , - WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 349 , - WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 350 , - WIFISCHEDULER_END_E = 351 , - WIFIRX_PPDU_START_DROPPED_E = 352 , - WIFIRX_PPDU_END_DROPPED_E = 353 , - WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 354 , - WIFIRX_MPDU_START_DROPPED_E = 355 , - WIFIRX_MSDU_START_DROPPED_E = 356 , - WIFIRX_MSDU_END_DROPPED_E = 357 , - WIFIRX_MPDU_END_DROPPED_E = 358 , - WIFIRX_ATTENTION_DROPPED_E = 359 , - WIFITXPCU_USER_SETUP_E = 360 , - WIFIRXPCU_USER_SETUP_EXT_E = 361 , - WIFICMD_PART_0_END_E = 362 , - WIFIMACTX_SYNTH_ON_E = 363 , - WIFISCH_CRITICAL_TLV_REFERENCE_E = 364 , - WIFITQM_MPDU_GLOBAL_START_E = 365 , - WIFIEXAMPLE_TLV_32_E = 366 , - WIFITQM_UPDATE_TX_MSDU_FLOW_E = 367 , - WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 368 , - WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 369 , - WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 370 , - WIFIREO_UPDATE_RX_REO_QUEUE_E = 371 , - WIFITQM_2_SCH_MPDU_AVAILABLE_E = 372 , - WIFIPDG_TRIG_RESPONSE_E = 373 , - WIFITRIGGER_RESPONSE_TX_DONE_E = 374 , - WIFIABORT_FROM_PHYRX_DETAILS_E = 375 , - WIFISCH_TQM_CMD_WRAPPER_E = 376 , - WIFIMPDUS_AVAILABLE_E = 377 , - WIFIRECEIVED_RESPONSE_INFO_PART2_E = 378 , - WIFIPHYRX_TX_START_TIMING_E = 379 , - WIFITXPCU_PREAMBLE_DONE_E = 380 , - WIFINDP_PREAMBLE_DONE_E = 381 , - WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 382 , - WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 383 , - WIFIMACTX_CLEAR_PREV_TX_INFO_E = 384 , - WIFITX_PUNCTURE_SETUP_E = 385 , - WIFIR2R_STATUS_END_E = 386 , - WIFIMACTX_PREFETCH_CV_COMMON_E = 387 , - WIFIEND_OF_FLUSH_MARKER_E = 388 , - WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 389 , - WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 390 , - WIFIRECEIVED_RESPONSE_USER_7_0_E = 391 , - WIFIRECEIVED_RESPONSE_USER_15_8_E = 392 , - WIFIRECEIVED_RESPONSE_USER_23_16_E = 393 , - WIFIRECEIVED_RESPONSE_USER_31_24_E = 394 , - WIFIRECEIVED_RESPONSE_USER_36_32_E = 395 , - WIFITX_LOOPBACK_SETUP_E = 396 , - WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 397 , - WIFISCH_WAIT_INSTR_TX_PATH_E = 398 , - WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 399 , - WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 400 , - WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 401 , - WIFITX_WUR_DATA_E = 402 , - WIFIRX_PPDU_END_START_E = 403 , - WIFIRX_PPDU_END_MIDDLE_E = 404 , - WIFIRX_PPDU_END_LAST_E = 405 , - WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 406 , - WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 407 , - WIFISRP_INFO_E = 408 , - WIFIOBSS_SR_INFO_E = 409 , - WIFISCHEDULER_SW_MSG_STATUS_E = 410 , - WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 411 , - WIFIRXPCU_SETUP_COMPLETE_E = 412 , - WIFIMACTX_MCC_SWITCH_E = 413 , - WIFIMACTX_MCC_SWITCH_BACK_E = 414 , - WIFIPHYTX_MCC_SWITCH_ACK_E = 415 , - WIFIPHYTX_MCC_SWITCH_BACK_ACK_E = 416 , - WIFIPHYTX_EMLSR_PRE_SWITCH_ACK_E = 417 , - WIFILMR_TX_END_E = 418 , - WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 419 , - WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 420 , - WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 421 , - WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 422 , - WIFISCH_TLV_WRAPPER_E = 423 , - WIFISCHEDULER_STATUS_WRAPPER_E = 424 , - WIFIMPDU_INFO_6X_E = 425 , - WIFIMACTX___RESERVED_G_0013 = 426 , - WIFIMACTX_U_SIG_EHT_SU_MU_E = 427 , - WIFIMACTX_U_SIG_EHT_TB_E = 428 , - WIFICOEX_TLV_ACC_TLV_TAG0_CFG_E = 429 , - WIFICOEX_TLV_ACC_TLV_TAG1_CFG_E = 430 , - WIFICOEX_TLV_ACC_TLV_TAG2_CFG_E = 431 , - WIFIPHYRX_U_SIG_EHT_SU_MU_E = 432 , - WIFIPHYRX_U_SIG_EHT_TB_E = 433 , - WIFICOEX_TLV_ACC_TLV_TAG3_CFG_E = 434 , - WIFICOEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 435 , - WIFITX_PUNCTURE_6PATTERNS_SETUP_E = 436 , - WIFIMACRX_LMR_READ_REQUEST_E = 437 , - WIFIMACRX_LMR_DATA_REQUEST_E = 438 , - WIFIPHYRX_LMR_TRANSFER_DONE_E = 439 , - WIFIPHYRX_LMR_TRANSFER_ABORT_E = 440 , - WIFIPHYRX_LMR_READ_REQUEST_ACK_E = 441 , - WIFIMACRX_SECURE_LTF_SEQ_PTR_E = 442 , - WIFIPHYRX_USER_INFO_MU_UL_E = 443 , - WIFIMPDU_QUEUE_OVERVIEW_E = 444 , - WIFISCHEDULER_NAV_INFO_E = 445 , - WIFIMACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E = 446 , - WIFILMR_PEER_ENTRY_E = 447 , - WIFILMR_MPDU_START_E = 448 , - WIFILMR_DATA_E = 449 , - WIFILMR_MPDU_END_E = 450 , - WIFIREO_GET_QUEUE_1K_STATS_STATUS_E = 451 , - WIFIRX_FRAME_1K_BITMAP_ACK_E = 452 , - WIFITX_FES_STATUS_1K_BA_E = 453 , - WIFITQM_ACKED_1K_MPDU_E = 454 , - WIFIMACRX_INBSS_OBSS_IND_E = 455 , - WIFIPHYRX_LOCATION_E = 456 , - WIFIMLO_TX_NOTIFICATION_SU_E = 457 , - WIFIMLO_TX_NOTIFICATION_MU_E = 458 , - WIFIMLO_TX_REQ_SU_E = 459 , - WIFIMLO_TX_REQ_MU_E = 460 , - WIFIMLO_TX_RESP_E = 461 , - WIFIMLO_RX_NOTIFICATION_E = 462 , - WIFIMLO_BKOFF_TRUNC_REQ_E = 463 , - WIFIMLO_TBTT_NOTIFICATION_E = 464 , - WIFIMLO_MESSAGE_E = 465 , - WIFIMLO_TS_SYNC_MSG_E = 466 , - WIFIMLO_FES_SETUP_E = 467 , - WIFIMLO_PDG_FES_SETUP_SU_E = 468 , - WIFIMLO_PDG_FES_SETUP_MU_E = 469 , - WIFIMPDU_INFO_1K_BITMAP_E = 470 , - WIFIMON_BUFFER_ADDR_E = 471 , - WIFITX_FRAG_STATE_E = 472 , - WIFIMACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 473 , - WIFIMACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 474 , - WIFIMACTX_EHT_SIG_USR_OFDMA_E = 475 , - WIFIMACTX_U_SIG_UHR_SU_MU_E = 476 , - WIFIMACTX_U_SIG_UHR_TB_E = 477 , - WIFITX_MPDU_COMPRESSED_DETAILS_TLV_E = 478 , - WIFITX_MSDU_COMPRESSED_DETAILS_TLV_E = 479 , - WIFITX_MSDU_COMPONENT_DETAILS_TLV_E = 480 , - WIFIPHYRX_EHT_SIG_USR_OFDMA_E = 481 , - WIFISCHEDULER_IU_TEMPLATE_ID_E = 482 , - WIFIPHYRX_PKT_END_PART1_E = 483 , - WIFIMACTX_EXPECT_NDP_RECEPTION_E = 484 , - WIFIMACTX_SECURE_LTF_SEQ_PTR_E = 485 , - WIFITX_MPDU_LENGTH_AND_RESTRICTIONS_E = 486 , - WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E = 487 , - WIFIPHYRX___RESERVED_G_0014 = 488 , - WIFIPHYTX_LOCATION_E = 489 , - WIFIPHYTX___RESERVED_G_0014 = 490 , - WIFIMPDU_LENGTH_STRUCTS_START_E = 491 , - WIFIMACTX_EHT_SIG_USR_SU_E = 492 , - WIFIMACTX_EHT_SIG_USR_MU_MIMO_E = 493 , - WIFIPHYRX_EHT_SIG_USR_SU_E = 494 , - WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E = 495 , - WIFIPHYRX_GENERIC_U_SIG_E = 496 , - WIFIPHYRX_GENERIC_EHT_OR_UHR_SIG_E = 497 , - WIFIOVERWRITE_RESP_START_E = 498 , - WIFIOVERWRITE_RESP_PREAMBLE_INFO_E = 499 , - WIFIOVERWRITE_RESP_FRAME_INFO_E = 500 , - WIFIOVERWRITE_RESP_END_E = 501 , - WIFIRXPCU_EARLY_RX_INDICATION_E = 502 , - WIFIMON_DROP_E = 503 , - WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E = 504 , - WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 505 , - WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E = 506 , - WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 507 , - WIFIMACTX_PREFETCH_CV_DMA_E = 508 , - WIFIMACTX_PREFETCH_CV_PER_USER_E = 509 , - WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 510 , - WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E = 511 , - WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E = 512 , - WIFIRANGING_USER_DETAILS_E = 513 , - WIFIPHYTX_CV_CORR_STATUS_E = 514 , - WIFIPHYTX_CV_CORR_COMMON_E = 515 , - WIFIPHYTX_CV_CORR_USER_E = 516 , - WIFIMACTX_CV_CORR_COMMON_E = 517 , - WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E = 518 , - WIFIBW_PUNCTURE_EVAL_WRAPPER_E = 519 , - WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E = 520 , - WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E = 521 , - WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E = 522 , - WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 523 , - WIFIRX_PPDU_END_USER_STATS_EXT2_E = 524 , - WIFIFW2SW_MON_E = 525 , - WIFIWSI_DIRECT_MESSAGE_E = 526 , - WIFIMACTX_EMLSR_PRE_SWITCH_E = 527 , - WIFIMACTX_EMLSR_SWITCH_E = 528 , - WIFIMACTX_EMLSR_SWITCH_BACK_E = 529 , - WIFIPHYTX_EMLSR_SWITCH_ACK_E = 530 , - WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E = 531 , - WIFIEAD_COMMAND_E = 532 , - WIFIEAD_LEGACY_STATUS_CONTROL_E = 533 , - WIFIEAD_LEGACY_INTERRUPT_CONTROL_E = 534 , - WIFITPI_TX_INITIALIZATION_CONFIG_E = 535 , - WIFITPI_ENABLE_RESPONSE_TIMEOUT_E = 536 , - WIFITPI_LEGACY_STATUS_CONTROL_E = 537 , - WIFITPI_LEGACY_INTERRUPT_CONTROL_E = 538 , - WIFITPI_MPDU_START_E = 539 , - WIFITPI_MPDU_CONTINUATION_E = 540 , - WIFITPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E = 541 , - WIFITPI_SEND_TLV_TO_PHYTX_E = 542 , - WIFITPI_TX_START_TIME_ARRIVED_E = 543 , - WIFITPI_STATUS_E = 544 , - WIFITPI_ERROR_STATUS_E = 545 , - WIFITPI_TIMESTAMP_STATUS_E = 546 , - WIFIRPI_SEND_TLV_TO_PHYRX_E = 547 , - WIFIRPI_LEGACY_STATUS_CONTROL_E = 548 , - WIFIRPI_LEGACY_INTERRUPT_CONTROL_E = 549 , - WIFIRPI_STATUS_E = 550 , - WIFIRPI_ERROR_STATUS_E = 551 , - WIFIRPI_TIMESTAMP_STATUS_E = 552 , - WIFIRPI_RX_FRAME_UPDATE_STATUS_E = 553 , - WIFITCC_PUSH_TRANSMIT_COMMAND_E = 554 , - WIFITCC_TLV_FETCH_E = 555 , - WIFITCC_LEGACY_STATUS_CONTROL_E = 556 , - WIFITCC_LEGACY_INTERRUPT_CONTROL_E = 557 , - WIFITCC_STATUS_E = 558 , - WIFITCC_ERROR_STATUS_E = 559 , - WIFITCC_TIMESTAMP_STATUS_E = 560 , - WIFITCC_PRE_BACKOFF_CMD_AVAILABLE_E = 561 , - WIFITCC_SCHEDULER_CMD_E = 562 , - WIFITCC_BURST_CMD_AVAILABLE_E = 563 , - WIFIRPI_NON_DATA_CTLV_44_FROM_PHYRX_E = 564 , - WIFIEAD_RING_AIR_TIME_REFERENCE_E = 565 , - WIFIRPI_FETCH_INFO_FROM_EXT_MEM_E = 566 , - WIFIRPI_WRITE_INFO_TO_EXT_MEM_E = 567 , - WIFIRPI_INIT_CBF_DATA_RESP_ADDR_E = 568 , - WIFIRPI_INIT_LMR_DATA_RESP_ADDR_E = 569 , - WIFITPI_SEND_CBF_DATA_TO_PHYTX_E = 570 , - WIFITPI_SEND_CTLV_44_TO_PHYTX_E = 571 , - WIFITCC_FES_END_MESSAGE_E = 572 , - WIFITPI_TX_FRAME_UPDATE_STATUS_E = 573 , - WIFITPI_DISABLE_RESPONSE_TIMEOUT_E = 574 , - WIFIEAD_MPDU_DATA_FETCH_CONTINUATION_E = 575 , - WIFIEAD_MSDU_STATUS_START_E = 576 , - WIFIEAD_MSDU_STATUS_DETAILS_E = 577 , - WIFIMACTX_UHR_SIG_USR_SU_E = 578 , - WIFIMACTX_UHR_SIG_USR_MU_MIMO_E = 579 , - WIFIMACTX_UHR_SIG_USR_OFDMA_E = 580 , - WIFIMACTX_ELR_SIG_UHR_SU_E = 581 , - WIFICOEX_BLACKOUT_DETAILS_E = 582 , - WIFIPEER_BLACKOUT_DETAILS_E = 583 , - WIFIMACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E = 584 , - WIFIHDR_CTRL_PROT_PEER_ENTRY_E = 585 , - WIFIHDR_CTRL_PROT_MPDU_START_E = 586 , - WIFIHDR_CTRL_PROT_DATA_E = 587 , - WIFIHDR_CTRL_PROT_MPDU_END_E = 588 , - WIFIHDR_CTRL_PROT_MIC_STATUS_E = 589 , - WIFIHDR_CTRL_PROT_PEER_INFO_E = 590 , - WIFIHDR_CTRL_PROT_PEER_ENTRY_DONE_E = 591 , - WIFIMACTX_U_SIG_UHR_ELR_SU_E = 592 , - WIFIMACTX_U_SIG_UHR_COBF_E = 593 , - WIFIMACTX_UHR_SIG_USR_COBF_E = 594 , - WIFISPARE_REUSE_TAG_0_E = 595 , - WIFISPARE_REUSE_TAG_1_E = 596 , - WIFISPARE_REUSE_TAG_2_E = 597 , - WIFISPARE_REUSE_TAG_3_E = 598 , - WIFISPARE_REUSE_TAG_4_E = 599 , - WIFISPARE_REUSE_TAG_5_E = 600 , - WIFISPARE_REUSE_TAG_6_E = 601 , - WIFISPARE_REUSE_TAG_7_E = 602 , - WIFISPARE_REUSE_TAG_8_E = 603 , - WIFISPARE_REUSE_TAG_9_E = 604 , - WIFISPARE_REUSE_TAG_10_E = 605 , - WIFISPARE_REUSE_TAG_11_E = 606 , - WIFISPARE_REUSE_TAG_12_E = 607 , - WIFISPARE_REUSE_TAG_13_E = 608 , - WIFISPARE_REUSE_TAG_14_E = 609 , - WIFISPARE_REUSE_TAG_15_E = 610 , - WIFISPARE_REUSE_TAG_16_E = 611 , - WIFISPARE_REUSE_TAG_17_E = 612 , - WIFISPARE_REUSE_TAG_18_E = 613 , - WIFISPARE_REUSE_TAG_19_E = 614 , - WIFISPARE_REUSE_TAG_20_E = 615 , - WIFISPARE_REUSE_TAG_21_E = 616 , - WIFISPARE_REUSE_TAG_22_E = 617 , - WIFISPARE_REUSE_TAG_23_E = 618 , - WIFISPARE_REUSE_TAG_24_E = 619 , - WIFISPARE_REUSE_TAG_25_E = 620 , - WIFISPARE_REUSE_TAG_26_E = 621 , - WIFISPARE_REUSE_TAG_27_E = 622 , - WIFISPARE_REUSE_TAG_28_E = 623 , - WIFISPARE_REUSE_TAG_29_E = 624 , - WIFISPARE_REUSE_TAG_30_E = 625 , - WIFISPARE_REUSE_TAG_31_E = 626 , - WIFISPARE_REUSE_TAG_32_E = 627 , - WIFISPARE_REUSE_TAG_33_E = 628 , - WIFISPARE_REUSE_TAG_34_E = 629 , - WIFISPARE_REUSE_TAG_35_E = 630 , - WIFISPARE_REUSE_TAG_36_E = 631 , - WIFISPARE_REUSE_TAG_37_E = 632 , - WIFISPARE_REUSE_TAG_38_E = 633 , - WIFISPARE_REUSE_TAG_39_E = 634 , - WIFISPARE_REUSE_TAG_40_E = 635 , - WIFISPARE_REUSE_TAG_41_E = 636 , - WIFISPARE_REUSE_TAG_42_E = 637 , - WIFISPARE_REUSE_TAG_43_E = 638 , - WIFISPARE_REUSE_TAG_44_E = 639 , - WIFISPARE_REUSE_TAG_45_E = 640 , - WIFISPARE_REUSE_TAG_46_E = 641 , - WIFISPARE_REUSE_TAG_47_E = 642 , - WIFISPARE_REUSE_TAG_48_E = 643 , - WIFISPARE_REUSE_TAG_49_E = 644 , - WIFISPARE_REUSE_TAG_50_E = 645 , - WIFISPARE_REUSE_TAG_51_E = 646 , - WIFISPARE_REUSE_TAG_52_E = 647 , - WIFISPARE_REUSE_TAG_53_E = 648 , - WIFISPARE_REUSE_TAG_54_E = 649 , - WIFISPARE_REUSE_TAG_55_E = 650 , - WIFISPARE_REUSE_TAG_56_E = 651 , - WIFISPARE_REUSE_TAG_57_E = 652 , - WIFISPARE_REUSE_TAG_58_E = 653 , - WIFISPARE_REUSE_TAG_59_E = 654 , - WIFISPARE_REUSE_TAG_60_E = 655 , - WIFISPARE_REUSE_TAG_61_E = 656 , - WIFISPARE_REUSE_TAG_62_E = 657 , - WIFISPARE_REUSE_TAG_63_E = 658 , - WIFISPARE_REUSE_TAG_64_E = 659 , - WIFISPARE_REUSE_TAG_65_E = 660 , - WIFISPARE_REUSE_TAG_66_E = 661 , - WIFISPARE_REUSE_TAG_67_E = 662 , - WIFISPARE_REUSE_TAG_68_E = 663 , - WIFISPARE_REUSE_TAG_69_E = 664 , - WIFISPARE_REUSE_TAG_70_E = 665 , - WIFISPARE_REUSE_TAG_71_E = 666 , - WIFISPARE_REUSE_TAG_72_E = 667 , - WIFISPARE_REUSE_TAG_73_E = 668 , - WIFISPARE_REUSE_TAG_74_E = 669 , - WIFISPARE_REUSE_TAG_75_E = 670 , - WIFISPARE_REUSE_TAG_76_E = 671 , - WIFISPARE_REUSE_TAG_77_E = 672 , - WIFISPARE_REUSE_TAG_78_E = 673 , - WIFISPARE_REUSE_TAG_79_E = 674 , - WIFISPARE_REUSE_TAG_80_E = 675 , - WIFISPARE_REUSE_TAG_81_E = 676 , - WIFISPARE_REUSE_TAG_82_E = 677 , - WIFISPARE_REUSE_TAG_83_E = 678 , - WIFISPARE_REUSE_TAG_84_E = 679 , - WIFISPARE_REUSE_TAG_85_E = 680 , - WIFISPARE_REUSE_TAG_86_E = 681 , - WIFISPARE_REUSE_TAG_87_E = 682 , - WIFISPARE_REUSE_TAG_88_E = 683 , - WIFISPARE_REUSE_TAG_89_E = 684 , - WIFISPARE_REUSE_TAG_90_E = 685 , - WIFISPARE_REUSE_TAG_91_E = 686 , - WIFISPARE_REUSE_TAG_92_E = 687 , - WIFISPARE_REUSE_TAG_93_E = 688 , - WIFISPARE_REUSE_TAG_94_E = 689 , - WIFISPARE_REUSE_TAG_95_E = 690 , - WIFISPARE_REUSE_TAG_96_E = 691 , - WIFISPARE_REUSE_TAG_97_E = 692 , - WIFISPARE_REUSE_TAG_98_E = 693 , - WIFISPARE_REUSE_TAG_99_E = 694 , - WIFISPARE_REUSE_TAG_100_E = 695 , - WIFISPARE_REUSE_TAG_101_E = 696 , - WIFISPARE_REUSE_TAG_102_E = 697 , - WIFISPARE_REUSE_TAG_103_E = 698 , - WIFISPARE_REUSE_TAG_104_E = 699 , - WIFISPARE_REUSE_TAG_105_E = 700 , - WIFISPARE_REUSE_TAG_106_E = 701 , - WIFISPARE_REUSE_TAG_107_E = 702 , - WIFISPARE_REUSE_TAG_108_E = 703 , - WIFISPARE_REUSE_TAG_109_E = 704 , - WIFISPARE_REUSE_TAG_110_E = 705 , - WIFISPARE_REUSE_TAG_111_E = 706 , - WIFISPARE_REUSE_TAG_112_E = 707 , - WIFISPARE_REUSE_TAG_113_E = 708 , - WIFISPARE_REUSE_TAG_114_E = 709 , - WIFISPARE_REUSE_TAG_115_E = 710 , - WIFISPARE_REUSE_TAG_116_E = 711 , - WIFISPARE_REUSE_TAG_117_E = 712 , - WIFISPARE_REUSE_TAG_118_E = 713 , - WIFISPARE_REUSE_TAG_119_E = 714 , - WIFISPARE_REUSE_TAG_120_E = 715 , - WIFISPARE_REUSE_TAG_121_E = 716 , - WIFISPARE_REUSE_TAG_122_E = 717 , - WIFISPARE_REUSE_TAG_123_E = 718 , - WIFISPARE_REUSE_TAG_124_E = 719 , - WIFISPARE_REUSE_TAG_125_E = 720 , - WIFISPARE_REUSE_TAG_126_E = 721 , - WIFISPARE_REUSE_TAG_127_E = 722 , - WIFISPARE_REUSE_TAG_128_E = 723 , - WIFISPARE_REUSE_TAG_129_E = 724 , - WIFISPARE_REUSE_TAG_130_E = 725 , - WIFISPARE_REUSE_TAG_131_E = 726 , - WIFISPARE_REUSE_TAG_132_E = 727 , - WIFISPARE_REUSE_TAG_133_E = 728 , - WIFISPARE_REUSE_TAG_134_E = 729 , - WIFISPARE_REUSE_TAG_135_E = 730 , - WIFISPARE_REUSE_TAG_136_E = 731 , - WIFISPARE_REUSE_TAG_137_E = 732 , - WIFISPARE_REUSE_TAG_138_E = 733 , - WIFISPARE_REUSE_TAG_139_E = 734 , - WIFISPARE_REUSE_TAG_140_E = 735 , - WIFISPARE_REUSE_TAG_141_E = 736 , - WIFISPARE_REUSE_TAG_142_E = 737 , - WIFISPARE_REUSE_TAG_143_E = 738 , - WIFISPARE_REUSE_TAG_144_E = 739 , - WIFISPARE_REUSE_TAG_145_E = 740 , - WIFISPARE_REUSE_TAG_146_E = 741 , - WIFISPARE_REUSE_TAG_147_E = 742 , - WIFISPARE_REUSE_TAG_148_E = 743 , - WIFISPARE_REUSE_TAG_149_E = 744 , - WIFISPARE_REUSE_TAG_150_E = 745 , - WIFISPARE_REUSE_TAG_151_E = 746 , - WIFISPARE_REUSE_TAG_152_E = 747 , - WIFISPARE_REUSE_TAG_153_E = 748 , - WIFISPARE_REUSE_TAG_154_E = 749 , - WIFISPARE_REUSE_TAG_155_E = 750 , - WIFISPARE_REUSE_TAG_156_E = 751 , - WIFISPARE_REUSE_TAG_157_E = 752 , - WIFISPARE_REUSE_TAG_158_E = 753 , - WIFISPARE_REUSE_TAG_159_E = 754 , - WIFISPARE_REUSE_TAG_160_E = 755 , - WIFISPARE_REUSE_TAG_161_E = 756 , - WIFISPARE_REUSE_TAG_162_E = 757 , - WIFISPARE_REUSE_TAG_163_E = 758 , - WIFISPARE_REUSE_TAG_164_E = 759 , - WIFISPARE_REUSE_TAG_165_E = 760 , - WIFISPARE_REUSE_TAG_166_E = 761 , - WIFISPARE_REUSE_TAG_167_E = 762 , - WIFISPARE_REUSE_TAG_168_E = 763 , - WIFISPARE_REUSE_TAG_169_E = 764 , - WIFISPARE_REUSE_TAG_170_E = 765 , - WIFISPARE_REUSE_TAG_171_E = 766 , - WIFISPARE_REUSE_TAG_172_E = 767 , - WIFISPARE_REUSE_TAG_173_E = 768 , - WIFISPARE_REUSE_TAG_174_E = 769 , - WIFISPARE_REUSE_TAG_175_E = 770 , - WIFISPARE_REUSE_TAG_176_E = 771 , - WIFISPARE_REUSE_TAG_177_E = 772 , - WIFISPARE_REUSE_TAG_178_E = 773 , - WIFISPARE_REUSE_TAG_179_E = 774 , - WIFISPARE_REUSE_TAG_180_E = 775 , - WIFISPARE_REUSE_TAG_181_E = 776 , - WIFISPARE_REUSE_TAG_182_E = 777 , - WIFISPARE_REUSE_TAG_183_E = 778 , - WIFISPARE_REUSE_TAG_184_E = 779 , - WIFISPARE_REUSE_TAG_185_E = 780 , - WIFISPARE_REUSE_TAG_186_E = 781 , - WIFISPARE_REUSE_TAG_187_E = 782 , - WIFISPARE_REUSE_TAG_188_E = 783 , - WIFISPARE_REUSE_TAG_189_E = 784 , - WIFISPARE_REUSE_TAG_190_E = 785 , - WIFISPARE_REUSE_TAG_191_E = 786 , - WIFISPARE_REUSE_TAG_192_E = 787 , - WIFISPARE_REUSE_TAG_193_E = 788 , - WIFISPARE_REUSE_TAG_194_E = 789 , - WIFISPARE_REUSE_TAG_195_E = 790 , - WIFISPARE_REUSE_TAG_196_E = 791 , - WIFISPARE_REUSE_TAG_197_E = 792 , - WIFISPARE_REUSE_TAG_198_E = 793 , - WIFISPARE_REUSE_TAG_199_E = 794 , - WIFISPARE_REUSE_TAG_200_E = 795 , - WIFISPARE_REUSE_TAG_201_E = 796 , - WIFISPARE_REUSE_TAG_202_E = 797 , - WIFISPARE_REUSE_TAG_203_E = 798 , - WIFISPARE_REUSE_TAG_204_E = 799 , - WIFISPARE_REUSE_TAG_205_E = 800 , - WIFISPARE_REUSE_TAG_206_E = 801 , - WIFISPARE_REUSE_TAG_207_E = 802 , - WIFISPARE_REUSE_TAG_208_E = 803 , - WIFISPARE_REUSE_TAG_209_E = 804 , - WIFISPARE_REUSE_TAG_210_E = 805 , - WIFISPARE_REUSE_TAG_211_E = 806 , - WIFISPARE_REUSE_TAG_212_E = 807 , - WIFISPARE_REUSE_TAG_213_E = 808 , - WIFISPARE_REUSE_TAG_214_E = 809 , - WIFISPARE_REUSE_TAG_215_E = 810 , - WIFISPARE_REUSE_TAG_216_E = 811 , - WIFISPARE_REUSE_TAG_217_E = 812 , - WIFISPARE_REUSE_TAG_218_E = 813 , - WIFISPARE_REUSE_TAG_219_E = 814 , - WIFISPARE_REUSE_TAG_220_E = 815 , - WIFISPARE_REUSE_TAG_221_E = 816 , - WIFISPARE_REUSE_TAG_222_E = 817 , - WIFISPARE_REUSE_TAG_223_E = 818 , - WIFISPARE_REUSE_TAG_224_E = 819 , - WIFISPARE_REUSE_TAG_225_E = 820 , - WIFISPARE_REUSE_TAG_226_E = 821 , - WIFISPARE_REUSE_TAG_227_E = 822 , - WIFISPARE_REUSE_TAG_228_E = 823 , - WIFISPARE_REUSE_TAG_229_E = 824 , - WIFISPARE_REUSE_TAG_230_E = 825 , - WIFISPARE_REUSE_TAG_231_E = 826 , - WIFISPARE_REUSE_TAG_232_E = 827 , - WIFISPARE_REUSE_TAG_233_E = 828 , - WIFISPARE_REUSE_TAG_234_E = 829 , - WIFISPARE_REUSE_TAG_235_E = 830 , - WIFISPARE_REUSE_TAG_236_E = 831 , - WIFISPARE_REUSE_TAG_237_E = 832 , - WIFISPARE_REUSE_TAG_238_E = 833 , - WIFISPARE_REUSE_TAG_239_E = 834 , - WIFISPARE_REUSE_TAG_240_E = 835 , - WIFISPARE_REUSE_TAG_241_E = 836 , - WIFISPARE_REUSE_TAG_242_E = 837 , - WIFISPARE_REUSE_TAG_243_E = 838 , - WIFISPARE_REUSE_TAG_244_E = 839 , - WIFISPARE_REUSE_TAG_245_E = 840 , - WIFISPARE_REUSE_TAG_246_E = 841 , - WIFISPARE_REUSE_TAG_247_E = 842 , - WIFISPARE_REUSE_TAG_248_E = 843 , - WIFISPARE_REUSE_TAG_249_E = 844 , - WIFISPARE_REUSE_TAG_250_E = 845 , - WIFISPARE_REUSE_TAG_251_E = 846 , - WIFISPARE_REUSE_TAG_252_E = 847 , - WIFISPARE_REUSE_TAG_253_E = 848 , - WIFISPARE_REUSE_TAG_254_E = 849 , - WIFISPARE_REUSE_TAG_255_E = 850 , - WIFISPARE_REUSE_TAG_256_E = 851 , - WIFISPARE_REUSE_TAG_257_E = 852 , - WIFISPARE_REUSE_TAG_258_E = 853 , - WIFISPARE_REUSE_TAG_259_E = 854 , - WIFISPARE_REUSE_TAG_260_E = 855 , - WIFISPARE_REUSE_TAG_261_E = 856 , - WIFISPARE_REUSE_TAG_262_E = 857 , - WIFISPARE_REUSE_TAG_263_E = 858 , - WIFISPARE_REUSE_TAG_264_E = 859 , - WIFISPARE_REUSE_TAG_265_E = 860 , - WIFISPARE_REUSE_TAG_266_E = 861 , - WIFISPARE_REUSE_TAG_267_E = 862 , - WIFISPARE_REUSE_TAG_268_E = 863 , - WIFISPARE_REUSE_TAG_269_E = 864 , - WIFISPARE_REUSE_TAG_270_E = 865 , - WIFISPARE_REUSE_TAG_271_E = 866 , - WIFISPARE_REUSE_TAG_272_E = 867 , - WIFISPARE_REUSE_TAG_273_E = 868 , - WIFISPARE_REUSE_TAG_274_E = 869 , - WIFISPARE_REUSE_TAG_275_E = 870 , - WIFISPARE_REUSE_TAG_276_E = 871 , - WIFISPARE_REUSE_TAG_277_E = 872 , - WIFISPARE_REUSE_TAG_278_E = 873 , - WIFISPARE_REUSE_TAG_279_E = 874 , - WIFISPARE_REUSE_TAG_280_E = 875 , - WIFISPARE_REUSE_TAG_281_E = 876 , - WIFISPARE_REUSE_TAG_282_E = 877 , - WIFISPARE_REUSE_TAG_283_E = 878 , - WIFISPARE_REUSE_TAG_284_E = 879 , - WIFISPARE_REUSE_TAG_285_E = 880 , - WIFISPARE_REUSE_TAG_286_E = 881 , - WIFISPARE_REUSE_TAG_287_E = 882 , - WIFISPARE_REUSE_TAG_288_E = 883 , - WIFISPARE_REUSE_TAG_289_E = 884 , - WIFISPARE_REUSE_TAG_290_E = 885 , - WIFISPARE_REUSE_TAG_291_E = 886 , - WIFISPARE_REUSE_TAG_292_E = 887 , - WIFISPARE_REUSE_TAG_293_E = 888 , - WIFISPARE_REUSE_TAG_294_E = 889 , - WIFISPARE_REUSE_TAG_295_E = 890 , - WIFISPARE_REUSE_TAG_296_E = 891 , - WIFISPARE_REUSE_TAG_297_E = 892 , - WIFISPARE_REUSE_TAG_298_E = 893 , - WIFISPARE_REUSE_TAG_299_E = 894 , - WIFISPARE_REUSE_TAG_300_E = 895 , - WIFISPARE_REUSE_TAG_301_E = 896 , - WIFISPARE_REUSE_TAG_302_E = 897 , - WIFISPARE_REUSE_TAG_303_E = 898 , - WIFISPARE_REUSE_TAG_304_E = 899 , - WIFISPARE_REUSE_TAG_305_E = 900 , - WIFISPARE_REUSE_TAG_306_E = 901 , - WIFISPARE_REUSE_TAG_307_E = 902 , - WIFISPARE_REUSE_TAG_308_E = 903 , - WIFISPARE_REUSE_TAG_309_E = 904 , - WIFISPARE_REUSE_TAG_310_E = 905 , - WIFISPARE_REUSE_TAG_311_E = 906 , - WIFISPARE_REUSE_TAG_312_E = 907 , - WIFISPARE_REUSE_TAG_313_E = 908 , - WIFISPARE_REUSE_TAG_314_E = 909 , - WIFISPARE_REUSE_TAG_315_E = 910 , - WIFISPARE_REUSE_TAG_316_E = 911 , - WIFISPARE_REUSE_TAG_317_E = 912 , - WIFISPARE_REUSE_TAG_318_E = 913 , - WIFISPARE_REUSE_TAG_319_E = 914 , - WIFISPARE_REUSE_TAG_320_E = 915 , - WIFISPARE_REUSE_TAG_321_E = 916 , - WIFISPARE_REUSE_TAG_322_E = 917 , - WIFISPARE_REUSE_TAG_323_E = 918 , - WIFISPARE_REUSE_TAG_324_E = 919 , - WIFISPARE_REUSE_TAG_325_E = 920 , - WIFISPARE_REUSE_TAG_326_E = 921 , - WIFISPARE_REUSE_TAG_327_E = 922 , - WIFISPARE_REUSE_TAG_328_E = 923 , - WIFISPARE_REUSE_TAG_329_E = 924 , - WIFISPARE_REUSE_TAG_330_E = 925 , - WIFISPARE_REUSE_TAG_331_E = 926 , - WIFISPARE_REUSE_TAG_332_E = 927 , - WIFISPARE_REUSE_TAG_333_E = 928 , - WIFISPARE_REUSE_TAG_334_E = 929 , - WIFISPARE_REUSE_TAG_335_E = 930 , - WIFISPARE_REUSE_TAG_336_E = 931 , - WIFISPARE_REUSE_TAG_337_E = 932 , - WIFISPARE_REUSE_TAG_338_E = 933 , - WIFISPARE_REUSE_TAG_339_E = 934 , - WIFISPARE_REUSE_TAG_340_E = 935 , - WIFISPARE_REUSE_TAG_341_E = 936 , - WIFISPARE_REUSE_TAG_342_E = 937 , - WIFISPARE_REUSE_TAG_343_E = 938 , - WIFISPARE_REUSE_TAG_344_E = 939 , - WIFISPARE_REUSE_TAG_345_E = 940 , - WIFISPARE_REUSE_TAG_346_E = 941 , - WIFISPARE_REUSE_TAG_347_E = 942 , - WIFISPARE_REUSE_TAG_348_E = 943 , - WIFISPARE_REUSE_TAG_349_E = 944 , - WIFISPARE_REUSE_TAG_350_E = 945 , - WIFISPARE_REUSE_TAG_351_E = 946 , - WIFISPARE_REUSE_TAG_352_E = 947 , - WIFISPARE_REUSE_TAG_353_E = 948 , - WIFISPARE_REUSE_TAG_354_E = 949 , - WIFISPARE_REUSE_TAG_355_E = 950 , - WIFISPARE_REUSE_TAG_356_E = 951 , - WIFISPARE_REUSE_TAG_357_E = 952 , - WIFISPARE_REUSE_TAG_358_E = 953 , - WIFISPARE_REUSE_TAG_359_E = 954 , - WIFISPARE_REUSE_TAG_360_E = 955 , - WIFISPARE_REUSE_TAG_361_E = 956 , - WIFISPARE_REUSE_TAG_362_E = 957 , - WIFISPARE_REUSE_TAG_363_E = 958 , - WIFISPARE_REUSE_TAG_364_E = 959 , - WIFISPARE_REUSE_TAG_365_E = 960 , - WIFISPARE_REUSE_TAG_366_E = 961 , - WIFISPARE_REUSE_TAG_367_E = 962 , - WIFISPARE_REUSE_TAG_368_E = 963 , - WIFISPARE_REUSE_TAG_369_E = 964 , - WIFISPARE_REUSE_TAG_370_E = 965 , - WIFISPARE_REUSE_TAG_371_E = 966 , - WIFISPARE_REUSE_TAG_372_E = 967 , - WIFISPARE_REUSE_TAG_373_E = 968 , - WIFISPARE_REUSE_TAG_374_E = 969 , - WIFISPARE_REUSE_TAG_375_E = 970 , - WIFISPARE_REUSE_TAG_376_E = 971 , - WIFISPARE_REUSE_TAG_377_E = 972 , - WIFISPARE_REUSE_TAG_378_E = 973 , - WIFISPARE_REUSE_TAG_379_E = 974 , - WIFISPARE_REUSE_TAG_380_E = 975 , - WIFISPARE_REUSE_TAG_381_E = 976 , - WIFISPARE_REUSE_TAG_382_E = 977 , - WIFISPARE_REUSE_TAG_383_E = 978 , - WIFISPARE_REUSE_TAG_384_E = 979 , - WIFISPARE_REUSE_TAG_385_E = 980 , - WIFISPARE_REUSE_TAG_386_E = 981 , - WIFISPARE_REUSE_TAG_387_E = 982 , - WIFISPARE_REUSE_TAG_388_E = 983 , - WIFISPARE_REUSE_TAG_389_E = 984 , - WIFISPARE_REUSE_TAG_390_E = 985 , - WIFISPARE_REUSE_TAG_391_E = 986 , - WIFISPARE_REUSE_TAG_392_E = 987 , - WIFISPARE_REUSE_TAG_393_E = 988 , - WIFISPARE_REUSE_TAG_394_E = 989 , - WIFISPARE_REUSE_TAG_395_E = 990 , - WIFISPARE_REUSE_TAG_396_E = 991 , - WIFISPARE_REUSE_TAG_397_E = 992 , - WIFISPARE_REUSE_TAG_398_E = 993 , - WIFISPARE_REUSE_TAG_399_E = 994 , - WIFISPARE_REUSE_TAG_400_E = 995 , - WIFISPARE_REUSE_TAG_401_E = 996 , - WIFISPARE_REUSE_TAG_402_E = 997 , - WIFISPARE_REUSE_TAG_403_E = 998 , - WIFISPARE_REUSE_TAG_404_E = 999 , - WIFISPARE_REUSE_TAG_405_E = 1000 , - WIFISPARE_REUSE_TAG_406_E = 1001 , - WIFISPARE_REUSE_TAG_407_E = 1002 , - WIFISPARE_REUSE_TAG_408_E = 1003 , - WIFISPARE_REUSE_TAG_409_E = 1004 , - WIFISPARE_REUSE_TAG_410_E = 1005 , - WIFISPARE_REUSE_TAG_411_E = 1006 , - WIFISPARE_REUSE_TAG_412_E = 1007 , - WIFISPARE_REUSE_TAG_413_E = 1008 , - WIFISPARE_REUSE_TAG_414_E = 1009 , - WIFISPARE_REUSE_TAG_415_E = 1010 , - WIFISPARE_REUSE_TAG_416_E = 1011 , - WIFISPARE_REUSE_TAG_417_E = 1012 , - WIFISPARE_REUSE_TAG_418_E = 1013 , - WIFISPARE_REUSE_TAG_419_E = 1014 , - WIFISPARE_REUSE_TAG_420_E = 1015 , - WIFISPARE_REUSE_TAG_421_E = 1016 , - WIFISPARE_REUSE_TAG_422_E = 1017 , - WIFISPARE_REUSE_TAG_423_E = 1018 , - WIFISPARE_REUSE_TAG_424_E = 1019 , - WIFISPARE_REUSE_TAG_425_E = 1020 , - WIFISPARE_REUSE_TAG_426_E = 1021 -} tlv_tag_def__e; - -typedef enum { - WIFI_EXT_PHYRX_DATA_E = 1 , - WIFI_EXT_PHYRX_ABORT_REQUEST_E = 3 , - WIFI_EXT_MACTX_DATA_RESP_E = 5 , - WIFI_EXT_MACTX_CBF_DONE_E = 7 , - WIFI_EXT_RXPCU_TO_UCODE_START_E = 9 , - WIFI_EXT_RXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 , - WIFI_EXT_RXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 , - WIFI_EXT_RXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 , - WIFI_EXT_PHYRX_RSSI_LEGACY_20MHZ_E = 17 , - WIFI_EXT_PHYRX_PKT_END_20MHZ_E = 19 , - WIFI_EXT_MACRX_CBF_DATA_REQUEST_E = 65 , - WIFI_EXT_MACRX_FREEZE_CAPTURE_CHANNEL_E = 67 , - WIFI_EXT_MACRX_ABORT_ACK_E = 69 , - WIFI_EXT_MACRX_CHAIN_MASK_E = 71 , - WIFI_EXT_MACRX_ABORT_REQUEST_E = 73 , - WIFI_EXT_PHYTX_ABORT_ACK_E = 75 , - WIFI_EXT_PHYTX_PKT_END_E = 77 , - WIFI_EXT_PHYTX_REQUEST_CTRL_INFO_E = 79 , - WIFI_EXT_PHYTX_BF_CV_LOADING_DONE_E = 81 , - WIFI_EXT_PHYTX_NAP_DONE_E = 83 , - WIFI_EXT_PHYTX_ON_ACK_E = 85 , - WIFI_EXT_PHYTX_DEBUG16_E = 87 , - WIFI_EXT_MACTX_ABORT_ACK_E = 89 , - WIFI_EXT_MACTX_PRE_PHY_DESC_E = 91 , - WIFI_EXT_MACTX_BF_PARAMS_PER_USER_E = 93 , - WIFI_EXT_MACTX_USER_DESC_COMMON_E = 95 , - WIFI_EXT_EXAMPLE_USER_TLV_16_E = 97 , - WIFI_EXT_MACTX_PHY_OFF_E = 99 , - WIFI_EXT_MACTX_SYNTH_OFF_E = 101 , - WIFI_EXT_MACTX_EXPECT_CBF_PER_USER_E = 103 , - WIFI_EXT_MACTX_L_SIG_A_E = 105 , - WIFI_EXT_MACTX_HT_SIG_E = 107 , - WIFI_EXT_MACTX_VHT_SIG_B_SU20_E = 109 , - WIFI_EXT_MACTX_VHT_SIG_B_SU80_E = 111 , - WIFI_EXT_MACTX_VHT_SIG_B_MU20_E = 113 , - WIFI_EXT_MACTX_VHT_SIG_B_MU80_E = 115 , - WIFI_EXT_MACTX_SERVICE_E = 117 , - WIFI_EXT_MACTX_HE_SIG_A_MU_DL_E = 119 , - WIFI_EXT_MACTX_HE_SIG_B1_MU_E = 121 , - WIFI_EXT_MACTX_HE_SIG_B2_OFDMA_E = 123 , - WIFI_EXT_MACTX_MU_UPLINK_COMMON_E = 125 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_E = 127 , - WIFI_EXT_MACTX_DEBUG_E = 129 , - WIFI_EXT_PHYRX_GENERATED_CBF_DETAILS_E = 131 , - WIFI_EXT_PHYRX_RSSI_HT_E = 133 , - WIFI_EXT_PHYRX_PKT_END_E = 135 , - WIFI_EXT_PHYRX_CBF_TRANSFER_DONE_E = 137 , - WIFI_EXT_PHYRX_L_SIG_A_E = 139 , - WIFI_EXT_PHYRX_HT_SIG_E = 141 , - WIFI_EXT_PHYRX_VHT_SIG_B_SU20_E = 143 , - WIFI_EXT_PHYRX_VHT_SIG_B_SU80_E = 145 , - WIFI_EXT_PHYRX_VHT_SIG_B_MU20_E = 147 , - WIFI_EXT_PHYRX_VHT_SIG_B_MU80_E = 149 , - WIFI_EXT_PHYRX_HE_SIG_A_SU_E = 151 , - WIFI_EXT_PHYRX_HE_SIG_A_MU_UL_E = 153 , - WIFI_EXT_PHYRX_HE_SIG_B2_MU_E = 155 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_E = 157 , - WIFI_EXT_PHYRX_DATA_DONE_E = 159 , - WIFI_EXT_DUMMY_E = 161 , - WIFI_EXT_MPDU_LIMIT_E = 163 , - WIFI_EXT_OLE_BUF_STATUS_E = 165 , - WIFI_EXT_PCU_PPDU_SETUP_END_E = 167 , - WIFI_EXT_PCU_PPDU_SETUP_START_E = 169 , - WIFI_EXT_PDG_RESPONSE_E = 171 , - WIFI_EXT_SCH_WAIT_INSTR_E = 173 , - WIFI_EXT_PHYTX_LINK_STATE_E = 175 , - WIFI_EXT_TQM_GEN_MPDU_LENGTH_LIST_E = 177 , - WIFI_EXT_TQM_GEN_MPDUS_E = 179 , - WIFI_EXT_TQM_REMOVE_MPDU_E = 181 , - WIFI_EXT_TQM_REMOVE_MSDU_E = 183 , - WIFI_EXT_TQM_UPDATE_TX_MPDU_COUNT_E = 185 , - WIFI_EXT_OFDMA_TRIGGER_DETAILS_E = 187 , - WIFI_EXT_TX_FES_SETUP_E = 189 , - WIFI_EXT_EXPECTED_RESPONSE_E = 191 , - WIFI_EXT_TX_MPDU_START_E = 193 , - WIFI_EXT_TX_MSDU_START_E = 195 , - WIFI_EXT_TXPCU_BUFFER_STATUS_E = 197 , - WIFI_EXT_DATA_TO_TIME_CONFIG_E = 199 , - WIFI_EXT_MPDU_INFO_E = 201 , - WIFI_EXT_TX_11AH_SETUP_E = 203 , - WIFI_EXT_TX_PEER_ENTRY_E = 205 , - WIFI_EXT_EXAMPLE_USER_TLV_44_E = 207 , - WIFI_EXT_TX_FLUSH_REQ_E = 209 , - WIFI_EXT_TQM_GET_MPDU_QUEUE_STATS_E = 211 , - WIFI_EXT_EXAMPLE_USER_CTLV_44_E = 213 , - WIFI_EXT_TX_FES_STATUS_USER_PPDU_E = 215 , - WIFI_EXT_TX_FES_STATUS_END_E = 217 , - WIFI_EXT_RXPCU_TX_SETUP_CLEAR_E = 219 , - WIFI_EXT_RX_FRAME_BITMAP_ACK_E = 221 , - WIFI_EXT_RX_START_PARAM_E = 223 , - WIFI_EXT_RX_PPDU_END_E = 225 , - WIFI_EXT_RX_MPDU_END_E = 227 , - WIFI_EXT_RX_MSDU_END_E = 229 , - WIFI_EXT_RECEIVED_RESPONSE_INFO_E = 231 , - WIFI_EXT_RX_HEADER_E = 233 , - WIFI_EXT_RX_FLUSH_E = 235 , - WIFI_EXT_RX_FRAMELESS_BAR_DETAILS_E = 237 , - WIFI_EXT_TQM_GET_MSDU_FLOW_STATS_STATUS_E = 239 , - WIFI_EXT_PCU_PPDU_SETUP_USER_E = 241 , - WIFI_EXT_RX_PM_INFO_E = 243 , - WIFI_EXT_RX_PRE_PPDU_START_E = 245 , - WIFI_EXT_TX_FES_SETUP_COMPLETE_E = 247 , - WIFI_EXT_TXDMA_STOP_REQUEST_E = 249 , - WIFI_EXT_RXPCU_USER_SETUP_E = 251 , - WIFI_EXT_TQM_ACKED_MPDU_E = 253 , - WIFI_EXT_COEX_TX_STATUS_E = 255 , - WIFI_EXT_COEX_STATUS_BROADCAST_E = 257 , - WIFI_EXT_RESPONSE_END_STATUS_E = 259 , - WIFI_EXT_RECEIVED_TRIGGER_INFO_E = 261 , - WIFI_EXT_RX_PPDU_ACK_REPORT_E = 263 , - WIFI_EXT_SCH_COEX_STATUS_E = 265 , - WIFI_EXT_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 267 , - WIFI_EXT_TX_FES_STATUS_START_PPDU_E = 269 , - WIFI_EXT_TXPCU_PHYTX_DEBUG32_E = 271 , - WIFI_EXT_TX_MPDU_COUNT_TRANSFER_END_E = 273 , - WIFI_EXT_WHO_ANCHOR_VALUE_E = 275 , - WIFI_EXT_WHO_COMMIT_E = 277 , - WIFI_EXT_WHO_FLUSH_E = 279 , - WIFI_EXT_WHO_L2_PAYLOAD_E = 281 , - WIFI_EXT_WHO_L3_INFO_E = 283 , - WIFI_EXT_WHO_L4_INFO_E = 285 , - WIFI_EXT_WHO_MSDU_MISC_E = 287 , - WIFI_EXT_WHO_PACKET_HDR_E = 289 , - WIFI_EXT_WHO_PPDU_START_E = 291 , - WIFI_EXT_WHO_WMAC_HEADER_PV0_E = 293 , - WIFI_EXT_WHO_WMAC_IV_E = 295 , - WIFI_EXT_MPDU_INFO_BITMAP_E = 297 , - WIFI_EXT_SCHEDULER_SELFGEN_RESPONSE_STATUS_E = 299 , - WIFI_EXT_TQM_ACKED_MPDU_STATUS_E = 301 , - WIFI_EXT_TQM_LIST_GEN_DONE_E = 303 , - WIFI_EXT_TX_LAST_MPDU_END_E = 305 , - WIFI_EXT_PPDU_TX_END_E = 307 , - WIFI_EXT_MPDU_INFO_GLOBAL_END_E = 309 , - WIFI_EXT_RX_PPDU_END_USER_STATS_E = 311 , - WIFI_EXT_REO_GET_QUEUE_STATS_E = 313 , - WIFI_EXT_REO_FLUSH_CACHE_E = 315 , - WIFI_EXT_REO_GET_QUEUE_STATS_STATUS_E = 317 , - WIFI_EXT_REO_FLUSH_CACHE_STATUS_E = 319 , - WIFI_EXT_TQM_FLUSH_CACHE_E = 321 , - WIFI_EXT_TQM_FLUSH_CACHE_STATUS_E = 323 , - WIFI_EXT_RX_PPDU_END_STATUS_DONE_E = 325 , - WIFI_EXT_SCHEDULER_MLO_SW_MSG_STATUS_E = 327 , - WIFI_EXT_TX_DATA_SYNC_E = 329 , - WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_E = 331 , - WIFI_EXT_TQM_GET_MPDU_HEAD_INFO_STATUS_E = 333 , - WIFI_EXT_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 335 , - WIFI_EXT_REO_FLUSH_TIMEOUT_LIST_E = 337 , - WIFI_EXT_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 339 , - WIFI_EXT_EXAMPLE_USER_TLV_32_NAME_E = 341 , - WIFI_EXT_RX_RING_MASK_E = 343 , - WIFI_EXT_RXPCU_PPDU_END_INFO_E = 345 , - WIFI_EXT_PDG_SW_MODE_BW_START_E = 347 , - WIFI_EXT_PDG_WAIT_FOR_MAC_REQUEST_E = 349 , - WIFI_EXT_SCHEDULER_END_E = 351 , - WIFI_EXT_RX_PPDU_END_DROPPED_E = 353 , - WIFI_EXT_RX_MPDU_START_DROPPED_E = 355 , - WIFI_EXT_RX_MSDU_END_DROPPED_E = 357 , - WIFI_EXT_RX_ATTENTION_DROPPED_E = 359 , - WIFI_EXT_RXPCU_USER_SETUP_EXT_E = 361 , - WIFI_EXT_MACTX_SYNTH_ON_E = 363 , - WIFI_EXT_TQM_MPDU_GLOBAL_START_E = 365 , - WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_E = 367 , - WIFI_EXT_TQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 369 , - WIFI_EXT_REO_UPDATE_RX_REO_QUEUE_E = 371 , - WIFI_EXT_PDG_TRIG_RESPONSE_E = 373 , - WIFI_EXT_ABORT_FROM_PHYRX_DETAILS_E = 375 , - WIFI_EXT_MPDUS_AVAILABLE_E = 377 , - WIFI_EXT_PHYRX_TX_START_TIMING_E = 379 , - WIFI_EXT_NDP_PREAMBLE_DONE_E = 381 , - WIFI_EXT_SCH_TQM_CMD_WRAPPER_CONT_DROP_E = 383 , - WIFI_EXT_TX_PUNCTURE_SETUP_E = 385 , - WIFI_EXT_MACTX_PREFETCH_CV_COMMON_E = 387 , - WIFI_EXT_MACTX_MU_UPLINK_COMMON_PUNC_E = 389 , - WIFI_EXT_RECEIVED_RESPONSE_USER_7_0_E = 391 , - WIFI_EXT_RECEIVED_RESPONSE_USER_23_16_E = 393 , - WIFI_EXT_RECEIVED_RESPONSE_USER_36_32_E = 395 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 397 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 399 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 401 , - WIFI_EXT_RX_PPDU_END_START_E = 403 , - WIFI_EXT_RX_PPDU_END_LAST_E = 405 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 407 , - WIFI_EXT_OBSS_SR_INFO_E = 409 , - WIFI_EXT_HWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 411 , - WIFI_EXT_MACTX_MCC_SWITCH_E = 413 , - WIFI_EXT_PHYTX_MCC_SWITCH_ACK_E = 415 , - WIFI_EXT_PHYTX_EMLSR_PRE_SWITCH_ACK_E = 417 , - WIFI_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 419 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 421 , - WIFI_EXT_SCH_TLV_WRAPPER_E = 423 , - WIFI_EXT_MPDU_INFO_6X_E = 425 , - WIFI_EXT_MACTX_U_SIG_EHT_SU_MU_E = 427 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG0_CFG_E = 429 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG2_CFG_E = 431 , - WIFI_EXT_PHYRX_U_SIG_EHT_TB_E = 433 , - WIFI_EXT_COEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 435 , - WIFI_EXT_MACRX_LMR_READ_REQUEST_E = 437 , - WIFI_EXT_PHYRX_LMR_TRANSFER_DONE_E = 439 , - WIFI_EXT_PHYRX_LMR_READ_REQUEST_ACK_E = 441 , - WIFI_EXT_PHYRX_USER_INFO_MU_UL_E = 443 , - WIFI_EXT_SCHEDULER_NAV_INFO_E = 445 , - WIFI_EXT_LMR_PEER_ENTRY_E = 447 , - WIFI_EXT_LMR_DATA_E = 449 , - WIFI_EXT_REO_GET_QUEUE_1K_STATS_STATUS_E = 451 , - WIFI_EXT_TX_FES_STATUS_1K_BA_E = 453 , - WIFI_EXT_MACRX_INBSS_OBSS_IND_E = 455 , - WIFI_EXT_MLO_TX_NOTIFICATION_SU_E = 457 , - WIFI_EXT_MLO_TX_REQ_SU_E = 459 , - WIFI_EXT_MLO_TX_RESP_E = 461 , - WIFI_EXT_MLO_BKOFF_TRUNC_REQ_E = 463 , - WIFI_EXT_MLO_MESSAGE_E = 465 , - WIFI_EXT_MLO_FES_SETUP_E = 467 , - WIFI_EXT_MLO_PDG_FES_SETUP_MU_E = 469 , - WIFI_EXT_MON_BUFFER_ADDR_E = 471 , - WIFI_EXT_MACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 473 , - WIFI_EXT_MACTX_EHT_SIG_USR_OFDMA_E = 475 , - WIFI_EXT_MACTX_U_SIG_UHR_TB_E = 477 , - WIFI_EXT_TX_MSDU_COMPRESSED_DETAILS_TLV_E = 479 , - WIFI_EXT_PHYRX_EHT_SIG_USR_OFDMA_E = 481 , - WIFI_EXT_PHYRX_PKT_END_PART1_E = 483 , - WIFI_EXT_MACTX_SECURE_LTF_SEQ_PTR_E = 485 , - WIFI_EXT_MLO_PDG_BKOFF_TRUNC_NOTIFY_E = 487 , - WIFI_EXT_PHYTX_LOCATION_E = 489 , - WIFI_EXT_MPDU_LENGTH_STRUCTS_START_E = 491 , - WIFI_EXT_MACTX_EHT_SIG_USR_MU_MIMO_E = 493 , - WIFI_EXT_PHYRX_EHT_SIG_USR_MU_MIMO_E = 495 , - WIFI_EXT_PHYRX_GENERIC_EHT_OR_UHR_SIG_E = 497 , - WIFI_EXT_OVERWRITE_RESP_PREAMBLE_INFO_E = 499 , - WIFI_EXT_OVERWRITE_RESP_END_E = 501 , - WIFI_EXT_MON_DROP_E = 503 , - WIFI_EXT_MACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 505 , - WIFI_EXT_MACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 507 , - WIFI_EXT_MACTX_PREFETCH_CV_PER_USER_E = 509 , - WIFI_EXT_MACTX_BF_PARAMS_UPDATE_COMMON_E = 511 , - WIFI_EXT_RANGING_USER_DETAILS_E = 513 , - WIFI_EXT_PHYTX_CV_CORR_COMMON_E = 515 , - WIFI_EXT_MACTX_CV_CORR_COMMON_E = 517 , - WIFI_EXT_BW_PUNCTURE_EVAL_WRAPPER_E = 519 , - WIFI_EXT_MACTX_TX_NOTIFICATION_FOR_PHY_E = 521 , - WIFI_EXT_MACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 523 , - WIFI_EXT_FW2SW_MON_E = 525 , - WIFI_EXT_MACTX_EMLSR_PRE_SWITCH_E = 527 , - WIFI_EXT_MACTX_EMLSR_SWITCH_BACK_E = 529 , - WIFI_EXT_PHYTX_EMLSR_SWITCH_BACK_ACK_E = 531 , - WIFI_EXT_EAD_LEGACY_STATUS_CONTROL_E = 533 , - WIFI_EXT_TPI_TX_INITIALIZATION_CONFIG_E = 535 , - WIFI_EXT_TPI_LEGACY_STATUS_CONTROL_E = 537 , - WIFI_EXT_TPI_MPDU_START_E = 539 , - WIFI_EXT_TPI_WAIT_FOR_PHY_HEADER_INFO_REQUEST_E = 541 , - WIFI_EXT_TPI_TX_START_TIME_ARRIVED_E = 543 , - WIFI_EXT_TPI_ERROR_STATUS_E = 545 , - WIFI_EXT_RPI_SEND_TLV_TO_PHYRX_E = 547 , - WIFI_EXT_RPI_LEGACY_INTERRUPT_CONTROL_E = 549 , - WIFI_EXT_RPI_ERROR_STATUS_E = 551 , - WIFI_EXT_RPI_RX_FRAME_UPDATE_STATUS_E = 553 , - WIFI_EXT_TCC_TLV_FETCH_E = 555 , - WIFI_EXT_TCC_LEGACY_INTERRUPT_CONTROL_E = 557 , - WIFI_EXT_TCC_ERROR_STATUS_E = 559 , - WIFI_EXT_TCC_PRE_BACKOFF_CMD_AVAILABLE_E = 561 , - WIFI_EXT_TCC_BURST_CMD_AVAILABLE_E = 563 , - WIFI_EXT_EAD_RING_AIR_TIME_REFERENCE_E = 565 , - WIFI_EXT_RPI_WRITE_INFO_TO_EXT_MEM_E = 567 , - WIFI_EXT_RPI_INIT_LMR_DATA_RESP_ADDR_E = 569 , - WIFI_EXT_TPI_SEND_CTLV_44_TO_PHYTX_E = 571 , - WIFI_EXT_TPI_TX_FRAME_UPDATE_STATUS_E = 573 , - WIFI_EXT_EAD_MPDU_DATA_FETCH_CONTINUATION_E = 575 , - WIFI_EXT_EAD_MSDU_STATUS_DETAILS_E = 577 , - WIFI_EXT_MACTX_UHR_SIG_USR_MU_MIMO_E = 579 , - WIFI_EXT_MACTX_ELR_SIG_UHR_SU_E = 581 , - WIFI_EXT_PEER_BLACKOUT_DETAILS_E = 583 , - WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_E = 585 , - WIFI_EXT_HDR_CTRL_PROT_DATA_E = 587 , - WIFI_EXT_HDR_CTRL_PROT_MIC_STATUS_E = 589 , - WIFI_EXT_HDR_CTRL_PROT_PEER_ENTRY_DONE_E = 591 , - WIFI_EXT_MACTX_U_SIG_UHR_COBF_E = 593 , - WIFI_EXT_SPARE_REUSE_TAG_0_E = 595 , - WIFI_EXT_SPARE_REUSE_TAG_2_E = 597 , - WIFI_EXT_SPARE_REUSE_TAG_4_E = 599 , - WIFI_EXT_SPARE_REUSE_TAG_6_E = 601 , - WIFI_EXT_SPARE_REUSE_TAG_8_E = 603 , - WIFI_EXT_SPARE_REUSE_TAG_10_E = 605 , - WIFI_EXT_SPARE_REUSE_TAG_12_E = 607 , - WIFI_EXT_SPARE_REUSE_TAG_14_E = 609 , - WIFI_EXT_SPARE_REUSE_TAG_16_E = 611 , - WIFI_EXT_SPARE_REUSE_TAG_18_E = 613 , - WIFI_EXT_SPARE_REUSE_TAG_20_E = 615 , - WIFI_EXT_SPARE_REUSE_TAG_22_E = 617 , - WIFI_EXT_SPARE_REUSE_TAG_24_E = 619 , - WIFI_EXT_SPARE_REUSE_TAG_26_E = 621 , - WIFI_EXT_SPARE_REUSE_TAG_28_E = 623 , - WIFI_EXT_SPARE_REUSE_TAG_30_E = 625 , - WIFI_EXT_SPARE_REUSE_TAG_32_E = 627 , - WIFI_EXT_SPARE_REUSE_TAG_34_E = 629 , - WIFI_EXT_SPARE_REUSE_TAG_36_E = 631 , - WIFI_EXT_SPARE_REUSE_TAG_38_E = 633 , - WIFI_EXT_SPARE_REUSE_TAG_40_E = 635 , - WIFI_EXT_SPARE_REUSE_TAG_42_E = 637 , - WIFI_EXT_SPARE_REUSE_TAG_44_E = 639 , - WIFI_EXT_SPARE_REUSE_TAG_46_E = 641 , - WIFI_EXT_SPARE_REUSE_TAG_48_E = 643 , - WIFI_EXT_SPARE_REUSE_TAG_50_E = 645 , - WIFI_EXT_SPARE_REUSE_TAG_52_E = 647 , - WIFI_EXT_SPARE_REUSE_TAG_54_E = 649 , - WIFI_EXT_SPARE_REUSE_TAG_56_E = 651 , - WIFI_EXT_SPARE_REUSE_TAG_58_E = 653 , - WIFI_EXT_SPARE_REUSE_TAG_60_E = 655 , - WIFI_EXT_SPARE_REUSE_TAG_62_E = 657 , - WIFI_EXT_SPARE_REUSE_TAG_64_E = 659 , - WIFI_EXT_SPARE_REUSE_TAG_66_E = 661 , - WIFI_EXT_SPARE_REUSE_TAG_68_E = 663 , - WIFI_EXT_SPARE_REUSE_TAG_70_E = 665 , - WIFI_EXT_SPARE_REUSE_TAG_72_E = 667 , - WIFI_EXT_SPARE_REUSE_TAG_74_E = 669 , - WIFI_EXT_SPARE_REUSE_TAG_76_E = 671 , - WIFI_EXT_SPARE_REUSE_TAG_78_E = 673 , - WIFI_EXT_SPARE_REUSE_TAG_80_E = 675 , - WIFI_EXT_SPARE_REUSE_TAG_82_E = 677 , - WIFI_EXT_SPARE_REUSE_TAG_84_E = 679 , - WIFI_EXT_SPARE_REUSE_TAG_86_E = 681 , - WIFI_EXT_SPARE_REUSE_TAG_88_E = 683 , - WIFI_EXT_SPARE_REUSE_TAG_90_E = 685 , - WIFI_EXT_SPARE_REUSE_TAG_92_E = 687 , - WIFI_EXT_SPARE_REUSE_TAG_94_E = 689 , - WIFI_EXT_SPARE_REUSE_TAG_96_E = 691 , - WIFI_EXT_SPARE_REUSE_TAG_98_E = 693 , - WIFI_EXT_SPARE_REUSE_TAG_100_E = 695 , - WIFI_EXT_SPARE_REUSE_TAG_102_E = 697 , - WIFI_EXT_SPARE_REUSE_TAG_104_E = 699 , - WIFI_EXT_SPARE_REUSE_TAG_106_E = 701 , - WIFI_EXT_SPARE_REUSE_TAG_108_E = 703 , - WIFI_EXT_SPARE_REUSE_TAG_110_E = 705 , - WIFI_EXT_SPARE_REUSE_TAG_112_E = 707 , - WIFI_EXT_SPARE_REUSE_TAG_114_E = 709 , - WIFI_EXT_SPARE_REUSE_TAG_116_E = 711 , - WIFI_EXT_SPARE_REUSE_TAG_118_E = 713 , - WIFI_EXT_SPARE_REUSE_TAG_120_E = 715 , - WIFI_EXT_SPARE_REUSE_TAG_122_E = 717 , - WIFI_EXT_SPARE_REUSE_TAG_124_E = 719 , - WIFI_EXT_SPARE_REUSE_TAG_126_E = 721 , - WIFI_EXT_SPARE_REUSE_TAG_128_E = 723 , - WIFI_EXT_SPARE_REUSE_TAG_130_E = 725 , - WIFI_EXT_SPARE_REUSE_TAG_132_E = 727 , - WIFI_EXT_SPARE_REUSE_TAG_134_E = 729 , - WIFI_EXT_SPARE_REUSE_TAG_136_E = 731 , - WIFI_EXT_SPARE_REUSE_TAG_138_E = 733 , - WIFI_EXT_SPARE_REUSE_TAG_140_E = 735 , - WIFI_EXT_SPARE_REUSE_TAG_142_E = 737 , - WIFI_EXT_SPARE_REUSE_TAG_144_E = 739 , - WIFI_EXT_SPARE_REUSE_TAG_146_E = 741 , - WIFI_EXT_SPARE_REUSE_TAG_148_E = 743 , - WIFI_EXT_SPARE_REUSE_TAG_150_E = 745 , - WIFI_EXT_SPARE_REUSE_TAG_152_E = 747 , - WIFI_EXT_SPARE_REUSE_TAG_154_E = 749 , - WIFI_EXT_SPARE_REUSE_TAG_156_E = 751 , - WIFI_EXT_SPARE_REUSE_TAG_158_E = 753 , - WIFI_EXT_SPARE_REUSE_TAG_160_E = 755 , - WIFI_EXT_SPARE_REUSE_TAG_162_E = 757 , - WIFI_EXT_SPARE_REUSE_TAG_164_E = 759 , - WIFI_EXT_SPARE_REUSE_TAG_166_E = 761 , - WIFI_EXT_SPARE_REUSE_TAG_168_E = 763 , - WIFI_EXT_SPARE_REUSE_TAG_170_E = 765 , - WIFI_EXT_SPARE_REUSE_TAG_172_E = 767 , - WIFI_EXT_SPARE_REUSE_TAG_174_E = 769 , - WIFI_EXT_SPARE_REUSE_TAG_176_E = 771 , - WIFI_EXT_SPARE_REUSE_TAG_178_E = 773 , - WIFI_EXT_SPARE_REUSE_TAG_180_E = 775 , - WIFI_EXT_SPARE_REUSE_TAG_182_E = 777 , - WIFI_EXT_SPARE_REUSE_TAG_184_E = 779 , - WIFI_EXT_SPARE_REUSE_TAG_186_E = 781 , - WIFI_EXT_SPARE_REUSE_TAG_188_E = 783 , - WIFI_EXT_SPARE_REUSE_TAG_190_E = 785 , - WIFI_EXT_SPARE_REUSE_TAG_192_E = 787 , - WIFI_EXT_SPARE_REUSE_TAG_194_E = 789 , - WIFI_EXT_SPARE_REUSE_TAG_196_E = 791 , - WIFI_EXT_SPARE_REUSE_TAG_198_E = 793 , - WIFI_EXT_SPARE_REUSE_TAG_200_E = 795 , - WIFI_EXT_SPARE_REUSE_TAG_202_E = 797 , - WIFI_EXT_SPARE_REUSE_TAG_204_E = 799 , - WIFI_EXT_SPARE_REUSE_TAG_206_E = 801 , - WIFI_EXT_SPARE_REUSE_TAG_208_E = 803 , - WIFI_EXT_SPARE_REUSE_TAG_210_E = 805 , - WIFI_EXT_SPARE_REUSE_TAG_212_E = 807 , - WIFI_EXT_SPARE_REUSE_TAG_214_E = 809 , - WIFI_EXT_SPARE_REUSE_TAG_216_E = 811 , - WIFI_EXT_SPARE_REUSE_TAG_218_E = 813 , - WIFI_EXT_SPARE_REUSE_TAG_220_E = 815 , - WIFI_EXT_SPARE_REUSE_TAG_222_E = 817 , - WIFI_EXT_SPARE_REUSE_TAG_224_E = 819 , - WIFI_EXT_SPARE_REUSE_TAG_226_E = 821 , - WIFI_EXT_SPARE_REUSE_TAG_228_E = 823 , - WIFI_EXT_SPARE_REUSE_TAG_230_E = 825 , - WIFI_EXT_SPARE_REUSE_TAG_232_E = 827 , - WIFI_EXT_SPARE_REUSE_TAG_234_E = 829 , - WIFI_EXT_SPARE_REUSE_TAG_236_E = 831 , - WIFI_EXT_SPARE_REUSE_TAG_238_E = 833 , - WIFI_EXT_SPARE_REUSE_TAG_240_E = 835 , - WIFI_EXT_SPARE_REUSE_TAG_242_E = 837 , - WIFI_EXT_SPARE_REUSE_TAG_244_E = 839 , - WIFI_EXT_SPARE_REUSE_TAG_246_E = 841 , - WIFI_EXT_SPARE_REUSE_TAG_248_E = 843 , - WIFI_EXT_SPARE_REUSE_TAG_250_E = 845 , - WIFI_EXT_SPARE_REUSE_TAG_252_E = 847 , - WIFI_EXT_SPARE_REUSE_TAG_254_E = 849 , - WIFI_EXT_SPARE_REUSE_TAG_256_E = 851 , - WIFI_EXT_SPARE_REUSE_TAG_258_E = 853 , - WIFI_EXT_SPARE_REUSE_TAG_260_E = 855 , - WIFI_EXT_SPARE_REUSE_TAG_262_E = 857 , - WIFI_EXT_SPARE_REUSE_TAG_264_E = 859 , - WIFI_EXT_SPARE_REUSE_TAG_266_E = 861 , - WIFI_EXT_SPARE_REUSE_TAG_268_E = 863 , - WIFI_EXT_SPARE_REUSE_TAG_270_E = 865 , - WIFI_EXT_SPARE_REUSE_TAG_272_E = 867 , - WIFI_EXT_SPARE_REUSE_TAG_274_E = 869 , - WIFI_EXT_SPARE_REUSE_TAG_276_E = 871 , - WIFI_EXT_SPARE_REUSE_TAG_278_E = 873 , - WIFI_EXT_SPARE_REUSE_TAG_280_E = 875 , - WIFI_EXT_SPARE_REUSE_TAG_282_E = 877 , - WIFI_EXT_SPARE_REUSE_TAG_284_E = 879 , - WIFI_EXT_SPARE_REUSE_TAG_286_E = 881 , - WIFI_EXT_SPARE_REUSE_TAG_288_E = 883 , - WIFI_EXT_SPARE_REUSE_TAG_290_E = 885 , - WIFI_EXT_SPARE_REUSE_TAG_292_E = 887 , - WIFI_EXT_SPARE_REUSE_TAG_294_E = 889 , - WIFI_EXT_SPARE_REUSE_TAG_296_E = 891 , - WIFI_EXT_SPARE_REUSE_TAG_298_E = 893 , - WIFI_EXT_SPARE_REUSE_TAG_300_E = 895 , - WIFI_EXT_SPARE_REUSE_TAG_302_E = 897 , - WIFI_EXT_SPARE_REUSE_TAG_304_E = 899 , - WIFI_EXT_SPARE_REUSE_TAG_306_E = 901 , - WIFI_EXT_SPARE_REUSE_TAG_308_E = 903 , - WIFI_EXT_SPARE_REUSE_TAG_310_E = 905 , - WIFI_EXT_SPARE_REUSE_TAG_312_E = 907 , - WIFI_EXT_SPARE_REUSE_TAG_314_E = 909 , - WIFI_EXT_SPARE_REUSE_TAG_316_E = 911 , - WIFI_EXT_SPARE_REUSE_TAG_318_E = 913 , - WIFI_EXT_SPARE_REUSE_TAG_320_E = 915 , - WIFI_EXT_SPARE_REUSE_TAG_322_E = 917 , - WIFI_EXT_SPARE_REUSE_TAG_324_E = 919 , - WIFI_EXT_SPARE_REUSE_TAG_326_E = 921 , - WIFI_EXT_SPARE_REUSE_TAG_328_E = 923 , - WIFI_EXT_SPARE_REUSE_TAG_330_E = 925 , - WIFI_EXT_SPARE_REUSE_TAG_332_E = 927 , - WIFI_EXT_SPARE_REUSE_TAG_334_E = 929 , - WIFI_EXT_SPARE_REUSE_TAG_336_E = 931 , - WIFI_EXT_SPARE_REUSE_TAG_338_E = 933 , - WIFI_EXT_SPARE_REUSE_TAG_340_E = 935 , - WIFI_EXT_SPARE_REUSE_TAG_342_E = 937 , - WIFI_EXT_SPARE_REUSE_TAG_344_E = 939 , - WIFI_EXT_SPARE_REUSE_TAG_346_E = 941 , - WIFI_EXT_SPARE_REUSE_TAG_348_E = 943 , - WIFI_EXT_SPARE_REUSE_TAG_350_E = 945 , - WIFI_EXT_SPARE_REUSE_TAG_352_E = 947 , - WIFI_EXT_SPARE_REUSE_TAG_354_E = 949 , - WIFI_EXT_SPARE_REUSE_TAG_356_E = 951 , - WIFI_EXT_SPARE_REUSE_TAG_358_E = 953 , - WIFI_EXT_SPARE_REUSE_TAG_360_E = 955 , - WIFI_EXT_SPARE_REUSE_TAG_362_E = 957 , - WIFI_EXT_SPARE_REUSE_TAG_364_E = 959 , - WIFI_EXT_SPARE_REUSE_TAG_366_E = 961 , - WIFI_EXT_SPARE_REUSE_TAG_368_E = 963 , - WIFI_EXT_SPARE_REUSE_TAG_370_E = 965 , - WIFI_EXT_SPARE_REUSE_TAG_372_E = 967 , - WIFI_EXT_SPARE_REUSE_TAG_374_E = 969 , - WIFI_EXT_SPARE_REUSE_TAG_376_E = 971 , - WIFI_EXT_SPARE_REUSE_TAG_378_E = 973 , - WIFI_EXT_SPARE_REUSE_TAG_380_E = 975 , - WIFI_EXT_SPARE_REUSE_TAG_382_E = 977 , - WIFI_EXT_SPARE_REUSE_TAG_384_E = 979 , - WIFI_EXT_SPARE_REUSE_TAG_386_E = 981 , - WIFI_EXT_SPARE_REUSE_TAG_388_E = 983 , - WIFI_EXT_SPARE_REUSE_TAG_390_E = 985 , - WIFI_EXT_SPARE_REUSE_TAG_392_E = 987 , - WIFI_EXT_SPARE_REUSE_TAG_394_E = 989 , - WIFI_EXT_SPARE_REUSE_TAG_396_E = 991 , - WIFI_EXT_SPARE_REUSE_TAG_398_E = 993 , - WIFI_EXT_SPARE_REUSE_TAG_400_E = 995 , - WIFI_EXT_SPARE_REUSE_TAG_402_E = 997 , - WIFI_EXT_SPARE_REUSE_TAG_404_E = 999 , - WIFI_EXT_SPARE_REUSE_TAG_406_E = 1001 , - WIFI_EXT_SPARE_REUSE_TAG_408_E = 1003 , - WIFI_EXT_SPARE_REUSE_TAG_410_E = 1005 , - WIFI_EXT_SPARE_REUSE_TAG_412_E = 1007 , - WIFI_EXT_SPARE_REUSE_TAG_414_E = 1009 , - WIFI_EXT_SPARE_REUSE_TAG_416_E = 1011 , - WIFI_EXT_SPARE_REUSE_TAG_418_E = 1013 , - WIFI_EXT_SPARE_REUSE_TAG_420_E = 1015 , - WIFI_EXT_SPARE_REUSE_TAG_422_E = 1017 , - WIFI_EXT_SPARE_REUSE_TAG_424_E = 1019 , - WIFI_EXT_SPARE_REUSE_TAG_426_E = 1021 -} ext_tlv_tag_def__e; - -typedef enum { - WIFI_N_EXT_MACTX_CBF_START_E = 0 , - WIFI_N_EXT_PHYRX_CBF_DATA_RESP_E = 2 , - WIFI_N_EXT_PHYRX_USER_ABORT_NOTIFICATION_E = 4 , - WIFI_N_EXT_MACTX_CBF_DATA_E = 6 , - WIFI_N_EXT_PHYRX_LMR_DATA_RESP_E = 8 , - WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 , - WIFI_N_EXT_RXPCU_TO_UCODE_FCS_STATUS_E = 12 , - WIFI_N_EXT_RXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 , - WIFI_N_EXT_RXPCU_TO_UCODE_END_E = 16 , - WIFI_N_EXT_PHYRX_NC_ABORT_REQUEST_E = 18 , - WIFI_N_EXT_PHYRX_NC_DATA_E = 20 , - WIFI_N_EXT_MACRX_CBF_READ_REQUEST_E = 64 , - WIFI_N_EXT_MACRX_EXPECT_NDP_RECEPTION_E = 66 , - WIFI_N_EXT_MACRX_NDP_TIMEOUT_E = 68 , - WIFI_N_EXT_MACRX_REQ_IMPLICIT_FB_E = 70 , - WIFI_N_EXT_MACRX_NAP_USER_E = 72 , - WIFI_N_EXT_PHYTX_OTHER_TRANSMIT_INFO16_E = 74 , - WIFI_N_EXT_PHYTX_ABORT_REQUEST_E = 76 , - WIFI_N_EXT_PHYTX_PPDU_HEADER_INFO_REQUEST_E = 78 , - WIFI_N_EXT_PHYTX_DATA_REQUEST_E = 80 , - WIFI_N_EXT_PHYTX_NAP_ACK_E = 82 , - WIFI_N_EXT_PHYTX_OFF_ACK_E = 84 , - WIFI_N_EXT_PHYTX_SYNTH_OFF_ACK_E = 86 , - WIFI_N_EXT_MACTX_ABORT_REQUEST_E = 88 , - WIFI_N_EXT_MACTX_PKT_END_E = 90 , - WIFI_N_EXT_MACTX_BF_PARAMS_COMMON_E = 92 , - WIFI_N_EXT_MACTX_PREFETCH_CV_E = 94 , - WIFI_N_EXT_MACTX_USER_DESC_PER_USER_E = 96 , - WIFI_N_EXT_EXAMPLE_TLV_16_E = 98 , - WIFI_N_EXT_MACTX_PHY_ON_E = 100 , - WIFI_N_EXT_MACTX_EXPECT_CBF_COMMON_E = 102 , - WIFI_N_EXT_MACTX_PHY_DESC_E = 104 , - WIFI_N_EXT_MACTX_L_SIG_B_E = 106 , - WIFI_N_EXT_MACTX_VHT_SIG_A_E = 108 , - WIFI_N_EXT_MACTX_VHT_SIG_B_SU40_E = 110 , - WIFI_N_EXT_MACTX_VHT_SIG_B_SU160_E = 112 , - WIFI_N_EXT_MACTX_VHT_SIG_B_MU40_E = 114 , - WIFI_N_EXT_MACTX_VHT_SIG_B_MU160_E = 116 , - WIFI_N_EXT_MACTX_HE_SIG_A_SU_E = 118 , - WIFI_N_EXT_MACTX_HE_SIG_A_MU_UL_E = 120 , - WIFI_N_EXT_MACTX_HE_SIG_B2_MU_E = 122 , - WIFI_N_EXT_MACTX_DELETE_CV_E = 124 , - WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_E = 126 , - WIFI_N_EXT_MACTX_PHY_NAP_E = 128 , - WIFI_N_EXT_PHYRX_ABORT_ACK_E = 130 , - WIFI_N_EXT_PHYRX_RSSI_LEGACY_E = 132 , - WIFI_N_EXT_PHYRX_USER_INFO_E = 134 , - WIFI_N_EXT_PHYRX_DEBUG_E = 136 , - WIFI_N_EXT_PHYRX_CBF_TRANSFER_ABORT_E = 138 , - WIFI_N_EXT_PHYRX_L_SIG_B_E = 140 , - WIFI_N_EXT_PHYRX_VHT_SIG_A_E = 142 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_SU40_E = 144 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_SU160_E = 146 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_MU40_E = 148 , - WIFI_N_EXT_PHYRX_VHT_SIG_B_MU160_E = 150 , - WIFI_N_EXT_PHYRX_HE_SIG_A_MU_DL_E = 152 , - WIFI_N_EXT_PHYRX_HE_SIG_B1_MU_E = 154 , - WIFI_N_EXT_PHYRX_HE_SIG_B2_OFDMA_E = 156 , - WIFI_N_EXT_PHYRX_COMMON_USER_INFO_E = 158 , - WIFI_N_EXT_COEX_TX_REQ_E = 160 , - WIFI_N_EXT_EXAMPLE_TLV_32_NAME_E = 162 , - WIFI_N_EXT_NA_LENGTH_END_E = 164 , - WIFI_N_EXT_PCU_PPDU_SETUP_DONE_E = 166 , - WIFI_N_EXT_PCU_PPDU_SETUP_INIT_E = 168 , - WIFI_N_EXT_PDG_FES_SETUP_E = 170 , - WIFI_N_EXT_PDG_TX_REQ_E = 172 , - WIFI_N_EXT_MACTX_SWITCH_TO_MAIN_E = 174 , - WIFI_N_EXT_AUX_PPDU_END_E = 176 , - WIFI_N_EXT_TQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 178 , - WIFI_N_EXT_TQM_GEN_MPDUS_STATUS_E = 180 , - WIFI_N_EXT_TQM_REMOVE_MPDU_STATUS_E = 182 , - WIFI_N_EXT_TQM_REMOVE_MSDU_STATUS_E = 184 , - WIFI_N_EXT_TQM_WRITE_CMD_E = 186 , - WIFI_N_EXT_TX_DATA_E = 188 , - WIFI_N_EXT_RX_PACKET_E = 190 , - WIFI_N_EXT_TX_MPDU_END_E = 192 , - WIFI_N_EXT_TX_MSDU_END_E = 194 , - WIFI_N_EXT_TX_SW_MODE_SETUP_E = 196 , - WIFI_N_EXT_TXPCU_USER_BUFFER_STATUS_E = 198 , - WIFI_N_EXT_EXAMPLE_USER_TLV_32_E = 200 , - WIFI_N_EXT_PDG_USER_SETUP_E = 202 , - WIFI_N_EXT_REO_UPDATE_RX_REO_QUEUE_STATUS_E = 204 , - WIFI_N_EXT_TX_RAW_OR_NATIVE_FRAME_SETUP_E = 206 , - WIFI_N_EXT_TX_FLUSH_E = 208 , - WIFI_N_EXT_TQM_WRITE_CMD_STATUS_E = 210 , - WIFI_N_EXT_TQM_GET_MSDU_FLOW_STATS_E = 212 , - WIFI_N_EXT_TX_FES_STATUS_START_E = 214 , - WIFI_N_EXT_TX_FES_STATUS_USER_RESPONSE_E = 216 , - WIFI_N_EXT_RX_TRIG_INFO_E = 218 , - WIFI_N_EXT_RX_FRAME_BITMAP_REQ_E = 220 , - WIFI_N_EXT_COEX_RX_STATUS_E = 222 , - WIFI_N_EXT_RX_PPDU_START_E = 224 , - WIFI_N_EXT_RX_MPDU_START_E = 226 , - WIFI_N_EXT_RX_MSDU_START_E = 228 , - WIFI_N_EXT_RX_ATTENTION_E = 230 , - WIFI_N_EXT_RX_PHY_SLEEP_E = 232 , - WIFI_N_EXT_RX_PEER_ENTRY_E = 234 , - WIFI_N_EXT_RX_RESPONSE_REQUIRED_INFO_E = 236 , - WIFI_N_EXT_TQM_GET_MPDU_QUEUE_STATS_STATUS_E = 238 , - WIFI_N_EXT_TX_CBF_INFO_E = 240 , - WIFI_N_EXT_RX_MPDU_PCU_START_E = 242 , - WIFI_N_EXT_RX_USER_PPDU_END_E = 244 , - WIFI_N_EXT_RX_PREAMBLE_E = 246 , - WIFI_N_EXT_TX_LAST_MPDU_FETCHED_E = 248 , - WIFI_N_EXT_RXPCU_SETUP_E = 250 , - WIFI_N_EXT_TX_FES_STATUS_ACK_OR_BA_E = 252 , - WIFI_N_EXT_COEX_TX_RESP_E = 254 , - WIFI_N_EXT_MACTX_COEX_PHY_CTRL_E = 256 , - WIFI_N_EXT_RESPONSE_START_STATUS_E = 258 , - WIFI_N_EXT_CRYPTO_STATUS_E = 260 , - WIFI_N_EXT_COEX_TX_STOP_CTRL_E = 262 , - WIFI_N_EXT_RX_PPDU_NO_ACK_REPORT_E = 264 , - WIFI_N_EXT_SCHEDULER_COMMAND_STATUS_E = 266 , - WIFI_N_EXT_TX_FES_STATUS_PROT_E = 268 , - WIFI_N_EXT_TX_FES_STATUS_START_PROT_E = 270 , - WIFI_N_EXT_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 272 , - WIFI_N_EXT_WHO_ANCHOR_OFFSET_E = 274 , - WIFI_N_EXT_WHO_CCE_INFO_E = 276 , - WIFI_N_EXT_WHO_COMMIT_DONE_E = 278 , - WIFI_N_EXT_WHO_L2_LLC_E = 280 , - WIFI_N_EXT_WHO_L3_CHECKSUM_E = 282 , - WIFI_N_EXT_WHO_L4_CHECKSUM_E = 284 , - WIFI_N_EXT_WHO_MSDU_E = 286 , - WIFI_N_EXT_WHO_PACKET_DATA_E = 288 , - WIFI_N_EXT_WHO_PPDU_END_E = 290 , - WIFI_N_EXT_WHO_TSO_E = 292 , - WIFI_N_EXT_WHO_WMAC_HEADER_PV1_E = 294 , - WIFI_N_EXT_MPDU_INFO_END_E = 296 , - WIFI_N_EXT_TX_QUEUE_EXTENSION_E = 298 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 300 , - WIFI_N_EXT_TQM_ADD_MSDU_STATUS_E = 302 , - WIFI_N_EXT_WHO_TERMINATE_E = 304 , - WIFI_N_EXT_TX_CV_DATA_E = 306 , - WIFI_N_EXT_PROT_TX_END_E = 308 , - WIFI_N_EXT_TQM_SCH_INSTR_GLOBAL_END_E = 310 , - WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT_E = 312 , - WIFI_N_EXT_REO_FLUSH_QUEUE_E = 314 , - WIFI_N_EXT_REO_UNBLOCK_CACHE_E = 316 , - WIFI_N_EXT_REO_FLUSH_QUEUE_STATUS_E = 318 , - WIFI_N_EXT_REO_UNBLOCK_CACHE_STATUS_E = 320 , - WIFI_N_EXT_TQM_UNBLOCK_CACHE_E = 322 , - WIFI_N_EXT_TQM_UNBLOCK_CACHE_STATUS_E = 324 , - WIFI_N_EXT_RX_STATUS_BUFFER_DONE_E = 326 , - WIFI_N_EXT_SCHEDULER_TXOP_DURATION_TRIGGER_E = 328 , - WIFI_N_EXT_PHYRX_CBF_READ_REQUEST_ACK_E = 330 , - WIFI_N_EXT_TQM_SYNC_CMD_E = 332 , - WIFI_N_EXT_TQM_SYNC_CMD_STATUS_E = 334 , - WIFI_N_EXT_TCC_TQM_WRAPPER_CMD_E = 336 , - WIFI_N_EXT_REO_FLUSH_TIMEOUT_LIST_STATUS_E = 338 , - WIFI_N_EXT_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 340 , - WIFI_N_EXT_RX_PPDU_START_USER_INFO_E = 342 , - WIFI_N_EXT_COEX_MAC_NAP_E = 344 , - WIFI_N_EXT_WHO_MESH_CONTROL_E = 346 , - WIFI_N_EXT_PDG_SW_MODE_BW_END_E = 348 , - WIFI_N_EXT_PDG_WAIT_FOR_PHY_REQUEST_E = 350 , - WIFI_N_EXT_RX_PPDU_START_DROPPED_E = 352 , - WIFI_N_EXT_RX_PPDU_END_STATUS_DONE_DROPPED_E = 354 , - WIFI_N_EXT_RX_MSDU_START_DROPPED_E = 356 , - WIFI_N_EXT_RX_MPDU_END_DROPPED_E = 358 , - WIFI_N_EXT_TXPCU_USER_SETUP_E = 360 , - WIFI_N_EXT_CMD_PART_0_END_E = 362 , - WIFI_N_EXT_SCH_CRITICAL_TLV_REFERENCE_E = 364 , - WIFI_N_EXT_EXAMPLE_TLV_32_E = 366 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 368 , - WIFI_N_EXT_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 370 , - WIFI_N_EXT_TQM_2_SCH_MPDU_AVAILABLE_E = 372 , - WIFI_N_EXT_TRIGGER_RESPONSE_TX_DONE_E = 374 , - WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_E = 376 , - WIFI_N_EXT_RECEIVED_RESPONSE_INFO_PART2_E = 378 , - WIFI_N_EXT_TXPCU_PREAMBLE_DONE_E = 380 , - WIFI_N_EXT_SCH_TQM_CMD_WRAPPER_RBO_DROP_E = 382 , - WIFI_N_EXT_MACTX_CLEAR_PREV_TX_INFO_E = 384 , - WIFI_N_EXT_R2R_STATUS_END_E = 386 , - WIFI_N_EXT_END_OF_FLUSH_MARKER_E = 388 , - WIFI_N_EXT_MACTX_MU_UPLINK_USER_SETUP_PUNC_E = 390 , - WIFI_N_EXT_RECEIVED_RESPONSE_USER_15_8_E = 392 , - WIFI_N_EXT_RECEIVED_RESPONSE_USER_31_24_E = 394 , - WIFI_N_EXT_TX_LOOPBACK_SETUP_E = 396 , - WIFI_N_EXT_SCH_WAIT_INSTR_TX_PATH_E = 398 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 400 , - WIFI_N_EXT_TX_WUR_DATA_E = 402 , - WIFI_N_EXT_RX_PPDU_END_MIDDLE_E = 404 , - WIFI_N_EXT_MACTX_BACKOFF_BASED_TRANSMISSION_E = 406 , - WIFI_N_EXT_SRP_INFO_E = 408 , - WIFI_N_EXT_SCHEDULER_SW_MSG_STATUS_E = 410 , - WIFI_N_EXT_RXPCU_SETUP_COMPLETE_E = 412 , - WIFI_N_EXT_MACTX_MCC_SWITCH_BACK_E = 414 , - WIFI_N_EXT_PHYTX_MCC_SWITCH_BACK_ACK_E = 416 , - WIFI_N_EXT_LMR_TX_END_E = 418 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 420 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 422 , - WIFI_N_EXT_SCHEDULER_STATUS_WRAPPER_E = 424 , - WIFI_N_EXT_MACTX___RESERVED_G_0013 = 426 , - WIFI_N_EXT_MACTX_U_SIG_EHT_TB_E = 428 , - WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG1_CFG_E = 430 , - WIFI_N_EXT_PHYRX_U_SIG_EHT_SU_MU_E = 432 , - WIFI_N_EXT_COEX_TLV_ACC_TLV_TAG3_CFG_E = 434 , - WIFI_N_EXT_TX_PUNCTURE_6PATTERNS_SETUP_E = 436 , - WIFI_N_EXT_MACRX_LMR_DATA_REQUEST_E = 438 , - WIFI_N_EXT_PHYRX_LMR_TRANSFER_ABORT_E = 440 , - WIFI_N_EXT_MACRX_SECURE_LTF_SEQ_PTR_E = 442 , - WIFI_N_EXT_MPDU_QUEUE_OVERVIEW_E = 444 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E = 446 , - WIFI_N_EXT_LMR_MPDU_START_E = 448 , - WIFI_N_EXT_LMR_MPDU_END_E = 450 , - WIFI_N_EXT_RX_FRAME_1K_BITMAP_ACK_E = 452 , - WIFI_N_EXT_TQM_ACKED_1K_MPDU_E = 454 , - WIFI_N_EXT_PHYRX_LOCATION_E = 456 , - WIFI_N_EXT_MLO_TX_NOTIFICATION_MU_E = 458 , - WIFI_N_EXT_MLO_TX_REQ_MU_E = 460 , - WIFI_N_EXT_MLO_RX_NOTIFICATION_E = 462 , - WIFI_N_EXT_MLO_TBTT_NOTIFICATION_E = 464 , - WIFI_N_EXT_MLO_TS_SYNC_MSG_E = 466 , - WIFI_N_EXT_MLO_PDG_FES_SETUP_SU_E = 468 , - WIFI_N_EXT_MPDU_INFO_1K_BITMAP_E = 470 , - WIFI_N_EXT_TX_FRAG_STATE_E = 472 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 474 , - WIFI_N_EXT_MACTX_U_SIG_UHR_SU_MU_E = 476 , - WIFI_N_EXT_TX_MPDU_COMPRESSED_DETAILS_TLV_E = 478 , - WIFI_N_EXT_TX_MSDU_COMPONENT_DETAILS_TLV_E = 480 , - WIFI_N_EXT_SCHEDULER_IU_TEMPLATE_ID_E = 482 , - WIFI_N_EXT_MACTX_EXPECT_NDP_RECEPTION_E = 484 , - WIFI_N_EXT_TX_MPDU_LENGTH_AND_RESTRICTIONS_E = 486 , - WIFI_N_EXT_PHYRX___RESERVED_G_0014 = 488 , - WIFI_N_EXT_PHYTX___RESERVED_G_0014 = 490 , - WIFI_N_EXT_MACTX_EHT_SIG_USR_SU_E = 492 , - WIFI_N_EXT_PHYRX_EHT_SIG_USR_SU_E = 494 , - WIFI_N_EXT_PHYRX_GENERIC_U_SIG_E = 496 , - WIFI_N_EXT_OVERWRITE_RESP_START_E = 498 , - WIFI_N_EXT_OVERWRITE_RESP_FRAME_INFO_E = 500 , - WIFI_N_EXT_RXPCU_EARLY_RX_INDICATION_E = 502 , - WIFI_N_EXT_MACRX_MU_UPLINK_COMMON_SNIFF_E = 504 , - WIFI_N_EXT_MACRX_MU_UPLINK_USER_SEL_SNIFF_E = 506 , - WIFI_N_EXT_MACTX_PREFETCH_CV_DMA_E = 508 , - WIFI_N_EXT_PHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 510 , - WIFI_N_EXT_MACTX_BF_PARAMS_UPDATE_PER_USER_E = 512 , - WIFI_N_EXT_PHYTX_CV_CORR_STATUS_E = 514 , - WIFI_N_EXT_PHYTX_CV_CORR_USER_E = 516 , - WIFI_N_EXT_MACTX_CV_CORR_MAC_INFO_GROUP_E = 518 , - WIFI_N_EXT_MACTX_RX_NOTIFICATION_FOR_PHY_E = 520 , - WIFI_N_EXT_MACTX_MU_UPLINK_COMMON_PER_BW_E = 522 , - WIFI_N_EXT_RX_PPDU_END_USER_STATS_EXT2_E = 524 , - WIFI_N_EXT_WSI_DIRECT_MESSAGE_E = 526 , - WIFI_N_EXT_MACTX_EMLSR_SWITCH_E = 528 , - WIFI_N_EXT_PHYTX_EMLSR_SWITCH_ACK_E = 530 , - WIFI_N_EXT_EAD_COMMAND_E = 532 , - WIFI_N_EXT_EAD_LEGACY_INTERRUPT_CONTROL_E = 534 , - WIFI_N_EXT_TPI_ENABLE_RESPONSE_TIMEOUT_E = 536 , - WIFI_N_EXT_TPI_LEGACY_INTERRUPT_CONTROL_E = 538 , - WIFI_N_EXT_TPI_MPDU_CONTINUATION_E = 540 , - WIFI_N_EXT_TPI_SEND_TLV_TO_PHYTX_E = 542 , - WIFI_N_EXT_TPI_STATUS_E = 544 , - WIFI_N_EXT_TPI_TIMESTAMP_STATUS_E = 546 , - WIFI_N_EXT_RPI_LEGACY_STATUS_CONTROL_E = 548 , - WIFI_N_EXT_RPI_STATUS_E = 550 , - WIFI_N_EXT_RPI_TIMESTAMP_STATUS_E = 552 , - WIFI_N_EXT_TCC_PUSH_TRANSMIT_COMMAND_E = 554 , - WIFI_N_EXT_TCC_LEGACY_STATUS_CONTROL_E = 556 , - WIFI_N_EXT_TCC_STATUS_E = 558 , - WIFI_N_EXT_TCC_TIMESTAMP_STATUS_E = 560 , - WIFI_N_EXT_TCC_SCHEDULER_CMD_E = 562 , - WIFI_N_EXT_RPI_NON_DATA_CTLV_44_FROM_PHYRX_E = 564 , - WIFI_N_EXT_RPI_FETCH_INFO_FROM_EXT_MEM_E = 566 , - WIFI_N_EXT_RPI_INIT_CBF_DATA_RESP_ADDR_E = 568 , - WIFI_N_EXT_TPI_SEND_CBF_DATA_TO_PHYTX_E = 570 , - WIFI_N_EXT_TCC_FES_END_MESSAGE_E = 572 , - WIFI_N_EXT_TPI_DISABLE_RESPONSE_TIMEOUT_E = 574 , - WIFI_N_EXT_EAD_MSDU_STATUS_START_E = 576 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_SU_E = 578 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_OFDMA_E = 580 , - WIFI_N_EXT_COEX_BLACKOUT_DETAILS_E = 582 , - WIFI_N_EXT_MACTX_OTHER_TRANSMIT_INFO_RTT_SELF_CAL_E = 584 , - WIFI_N_EXT_HDR_CTRL_PROT_MPDU_START_E = 586 , - WIFI_N_EXT_HDR_CTRL_PROT_MPDU_END_E = 588 , - WIFI_N_EXT_HDR_CTRL_PROT_PEER_INFO_E = 590 , - WIFI_N_EXT_MACTX_U_SIG_UHR_ELR_SU_E = 592 , - WIFI_N_EXT_MACTX_UHR_SIG_USR_COBF_E = 594 , - WIFI_N_EXT_SPARE_REUSE_TAG_1_E = 596 , - WIFI_N_EXT_SPARE_REUSE_TAG_3_E = 598 , - WIFI_N_EXT_SPARE_REUSE_TAG_5_E = 600 , - WIFI_N_EXT_SPARE_REUSE_TAG_7_E = 602 , - WIFI_N_EXT_SPARE_REUSE_TAG_9_E = 604 , - WIFI_N_EXT_SPARE_REUSE_TAG_11_E = 606 , - WIFI_N_EXT_SPARE_REUSE_TAG_13_E = 608 , - WIFI_N_EXT_SPARE_REUSE_TAG_15_E = 610 , - WIFI_N_EXT_SPARE_REUSE_TAG_17_E = 612 , - WIFI_N_EXT_SPARE_REUSE_TAG_19_E = 614 , - WIFI_N_EXT_SPARE_REUSE_TAG_21_E = 616 , - WIFI_N_EXT_SPARE_REUSE_TAG_23_E = 618 , - WIFI_N_EXT_SPARE_REUSE_TAG_25_E = 620 , - WIFI_N_EXT_SPARE_REUSE_TAG_27_E = 622 , - WIFI_N_EXT_SPARE_REUSE_TAG_29_E = 624 , - WIFI_N_EXT_SPARE_REUSE_TAG_31_E = 626 , - WIFI_N_EXT_SPARE_REUSE_TAG_33_E = 628 , - WIFI_N_EXT_SPARE_REUSE_TAG_35_E = 630 , - WIFI_N_EXT_SPARE_REUSE_TAG_37_E = 632 , - WIFI_N_EXT_SPARE_REUSE_TAG_39_E = 634 , - WIFI_N_EXT_SPARE_REUSE_TAG_41_E = 636 , - WIFI_N_EXT_SPARE_REUSE_TAG_43_E = 638 , - WIFI_N_EXT_SPARE_REUSE_TAG_45_E = 640 , - WIFI_N_EXT_SPARE_REUSE_TAG_47_E = 642 , - WIFI_N_EXT_SPARE_REUSE_TAG_49_E = 644 , - WIFI_N_EXT_SPARE_REUSE_TAG_51_E = 646 , - WIFI_N_EXT_SPARE_REUSE_TAG_53_E = 648 , - WIFI_N_EXT_SPARE_REUSE_TAG_55_E = 650 , - WIFI_N_EXT_SPARE_REUSE_TAG_57_E = 652 , - WIFI_N_EXT_SPARE_REUSE_TAG_59_E = 654 , - WIFI_N_EXT_SPARE_REUSE_TAG_61_E = 656 , - WIFI_N_EXT_SPARE_REUSE_TAG_63_E = 658 , - WIFI_N_EXT_SPARE_REUSE_TAG_65_E = 660 , - WIFI_N_EXT_SPARE_REUSE_TAG_67_E = 662 , - WIFI_N_EXT_SPARE_REUSE_TAG_69_E = 664 , - WIFI_N_EXT_SPARE_REUSE_TAG_71_E = 666 , - WIFI_N_EXT_SPARE_REUSE_TAG_73_E = 668 , - WIFI_N_EXT_SPARE_REUSE_TAG_75_E = 670 , - WIFI_N_EXT_SPARE_REUSE_TAG_77_E = 672 , - WIFI_N_EXT_SPARE_REUSE_TAG_79_E = 674 , - WIFI_N_EXT_SPARE_REUSE_TAG_81_E = 676 , - WIFI_N_EXT_SPARE_REUSE_TAG_83_E = 678 , - WIFI_N_EXT_SPARE_REUSE_TAG_85_E = 680 , - WIFI_N_EXT_SPARE_REUSE_TAG_87_E = 682 , - WIFI_N_EXT_SPARE_REUSE_TAG_89_E = 684 , - WIFI_N_EXT_SPARE_REUSE_TAG_91_E = 686 , - WIFI_N_EXT_SPARE_REUSE_TAG_93_E = 688 , - WIFI_N_EXT_SPARE_REUSE_TAG_95_E = 690 , - WIFI_N_EXT_SPARE_REUSE_TAG_97_E = 692 , - WIFI_N_EXT_SPARE_REUSE_TAG_99_E = 694 , - WIFI_N_EXT_SPARE_REUSE_TAG_101_E = 696 , - WIFI_N_EXT_SPARE_REUSE_TAG_103_E = 698 , - WIFI_N_EXT_SPARE_REUSE_TAG_105_E = 700 , - WIFI_N_EXT_SPARE_REUSE_TAG_107_E = 702 , - WIFI_N_EXT_SPARE_REUSE_TAG_109_E = 704 , - WIFI_N_EXT_SPARE_REUSE_TAG_111_E = 706 , - WIFI_N_EXT_SPARE_REUSE_TAG_113_E = 708 , - WIFI_N_EXT_SPARE_REUSE_TAG_115_E = 710 , - WIFI_N_EXT_SPARE_REUSE_TAG_117_E = 712 , - WIFI_N_EXT_SPARE_REUSE_TAG_119_E = 714 , - WIFI_N_EXT_SPARE_REUSE_TAG_121_E = 716 , - WIFI_N_EXT_SPARE_REUSE_TAG_123_E = 718 , - WIFI_N_EXT_SPARE_REUSE_TAG_125_E = 720 , - WIFI_N_EXT_SPARE_REUSE_TAG_127_E = 722 , - WIFI_N_EXT_SPARE_REUSE_TAG_129_E = 724 , - WIFI_N_EXT_SPARE_REUSE_TAG_131_E = 726 , - WIFI_N_EXT_SPARE_REUSE_TAG_133_E = 728 , - WIFI_N_EXT_SPARE_REUSE_TAG_135_E = 730 , - WIFI_N_EXT_SPARE_REUSE_TAG_137_E = 732 , - WIFI_N_EXT_SPARE_REUSE_TAG_139_E = 734 , - WIFI_N_EXT_SPARE_REUSE_TAG_141_E = 736 , - WIFI_N_EXT_SPARE_REUSE_TAG_143_E = 738 , - WIFI_N_EXT_SPARE_REUSE_TAG_145_E = 740 , - WIFI_N_EXT_SPARE_REUSE_TAG_147_E = 742 , - WIFI_N_EXT_SPARE_REUSE_TAG_149_E = 744 , - WIFI_N_EXT_SPARE_REUSE_TAG_151_E = 746 , - WIFI_N_EXT_SPARE_REUSE_TAG_153_E = 748 , - WIFI_N_EXT_SPARE_REUSE_TAG_155_E = 750 , - WIFI_N_EXT_SPARE_REUSE_TAG_157_E = 752 , - WIFI_N_EXT_SPARE_REUSE_TAG_159_E = 754 , - WIFI_N_EXT_SPARE_REUSE_TAG_161_E = 756 , - WIFI_N_EXT_SPARE_REUSE_TAG_163_E = 758 , - WIFI_N_EXT_SPARE_REUSE_TAG_165_E = 760 , - WIFI_N_EXT_SPARE_REUSE_TAG_167_E = 762 , - WIFI_N_EXT_SPARE_REUSE_TAG_169_E = 764 , - WIFI_N_EXT_SPARE_REUSE_TAG_171_E = 766 , - WIFI_N_EXT_SPARE_REUSE_TAG_173_E = 768 , - WIFI_N_EXT_SPARE_REUSE_TAG_175_E = 770 , - WIFI_N_EXT_SPARE_REUSE_TAG_177_E = 772 , - WIFI_N_EXT_SPARE_REUSE_TAG_179_E = 774 , - WIFI_N_EXT_SPARE_REUSE_TAG_181_E = 776 , - WIFI_N_EXT_SPARE_REUSE_TAG_183_E = 778 , - WIFI_N_EXT_SPARE_REUSE_TAG_185_E = 780 , - WIFI_N_EXT_SPARE_REUSE_TAG_187_E = 782 , - WIFI_N_EXT_SPARE_REUSE_TAG_189_E = 784 , - WIFI_N_EXT_SPARE_REUSE_TAG_191_E = 786 , - WIFI_N_EXT_SPARE_REUSE_TAG_193_E = 788 , - WIFI_N_EXT_SPARE_REUSE_TAG_195_E = 790 , - WIFI_N_EXT_SPARE_REUSE_TAG_197_E = 792 , - WIFI_N_EXT_SPARE_REUSE_TAG_199_E = 794 , - WIFI_N_EXT_SPARE_REUSE_TAG_201_E = 796 , - WIFI_N_EXT_SPARE_REUSE_TAG_203_E = 798 , - WIFI_N_EXT_SPARE_REUSE_TAG_205_E = 800 , - WIFI_N_EXT_SPARE_REUSE_TAG_207_E = 802 , - WIFI_N_EXT_SPARE_REUSE_TAG_209_E = 804 , - WIFI_N_EXT_SPARE_REUSE_TAG_211_E = 806 , - WIFI_N_EXT_SPARE_REUSE_TAG_213_E = 808 , - WIFI_N_EXT_SPARE_REUSE_TAG_215_E = 810 , - WIFI_N_EXT_SPARE_REUSE_TAG_217_E = 812 , - WIFI_N_EXT_SPARE_REUSE_TAG_219_E = 814 , - WIFI_N_EXT_SPARE_REUSE_TAG_221_E = 816 , - WIFI_N_EXT_SPARE_REUSE_TAG_223_E = 818 , - WIFI_N_EXT_SPARE_REUSE_TAG_225_E = 820 , - WIFI_N_EXT_SPARE_REUSE_TAG_227_E = 822 , - WIFI_N_EXT_SPARE_REUSE_TAG_229_E = 824 , - WIFI_N_EXT_SPARE_REUSE_TAG_231_E = 826 , - WIFI_N_EXT_SPARE_REUSE_TAG_233_E = 828 , - WIFI_N_EXT_SPARE_REUSE_TAG_235_E = 830 , - WIFI_N_EXT_SPARE_REUSE_TAG_237_E = 832 , - WIFI_N_EXT_SPARE_REUSE_TAG_239_E = 834 , - WIFI_N_EXT_SPARE_REUSE_TAG_241_E = 836 , - WIFI_N_EXT_SPARE_REUSE_TAG_243_E = 838 , - WIFI_N_EXT_SPARE_REUSE_TAG_245_E = 840 , - WIFI_N_EXT_SPARE_REUSE_TAG_247_E = 842 , - WIFI_N_EXT_SPARE_REUSE_TAG_249_E = 844 , - WIFI_N_EXT_SPARE_REUSE_TAG_251_E = 846 , - WIFI_N_EXT_SPARE_REUSE_TAG_253_E = 848 , - WIFI_N_EXT_SPARE_REUSE_TAG_255_E = 850 , - WIFI_N_EXT_SPARE_REUSE_TAG_257_E = 852 , - WIFI_N_EXT_SPARE_REUSE_TAG_259_E = 854 , - WIFI_N_EXT_SPARE_REUSE_TAG_261_E = 856 , - WIFI_N_EXT_SPARE_REUSE_TAG_263_E = 858 , - WIFI_N_EXT_SPARE_REUSE_TAG_265_E = 860 , - WIFI_N_EXT_SPARE_REUSE_TAG_267_E = 862 , - WIFI_N_EXT_SPARE_REUSE_TAG_269_E = 864 , - WIFI_N_EXT_SPARE_REUSE_TAG_271_E = 866 , - WIFI_N_EXT_SPARE_REUSE_TAG_273_E = 868 , - WIFI_N_EXT_SPARE_REUSE_TAG_275_E = 870 , - WIFI_N_EXT_SPARE_REUSE_TAG_277_E = 872 , - WIFI_N_EXT_SPARE_REUSE_TAG_279_E = 874 , - WIFI_N_EXT_SPARE_REUSE_TAG_281_E = 876 , - WIFI_N_EXT_SPARE_REUSE_TAG_283_E = 878 , - WIFI_N_EXT_SPARE_REUSE_TAG_285_E = 880 , - WIFI_N_EXT_SPARE_REUSE_TAG_287_E = 882 , - WIFI_N_EXT_SPARE_REUSE_TAG_289_E = 884 , - WIFI_N_EXT_SPARE_REUSE_TAG_291_E = 886 , - WIFI_N_EXT_SPARE_REUSE_TAG_293_E = 888 , - WIFI_N_EXT_SPARE_REUSE_TAG_295_E = 890 , - WIFI_N_EXT_SPARE_REUSE_TAG_297_E = 892 , - WIFI_N_EXT_SPARE_REUSE_TAG_299_E = 894 , - WIFI_N_EXT_SPARE_REUSE_TAG_301_E = 896 , - WIFI_N_EXT_SPARE_REUSE_TAG_303_E = 898 , - WIFI_N_EXT_SPARE_REUSE_TAG_305_E = 900 , - WIFI_N_EXT_SPARE_REUSE_TAG_307_E = 902 , - WIFI_N_EXT_SPARE_REUSE_TAG_309_E = 904 , - WIFI_N_EXT_SPARE_REUSE_TAG_311_E = 906 , - WIFI_N_EXT_SPARE_REUSE_TAG_313_E = 908 , - WIFI_N_EXT_SPARE_REUSE_TAG_315_E = 910 , - WIFI_N_EXT_SPARE_REUSE_TAG_317_E = 912 , - WIFI_N_EXT_SPARE_REUSE_TAG_319_E = 914 , - WIFI_N_EXT_SPARE_REUSE_TAG_321_E = 916 , - WIFI_N_EXT_SPARE_REUSE_TAG_323_E = 918 , - WIFI_N_EXT_SPARE_REUSE_TAG_325_E = 920 , - WIFI_N_EXT_SPARE_REUSE_TAG_327_E = 922 , - WIFI_N_EXT_SPARE_REUSE_TAG_329_E = 924 , - WIFI_N_EXT_SPARE_REUSE_TAG_331_E = 926 , - WIFI_N_EXT_SPARE_REUSE_TAG_333_E = 928 , - WIFI_N_EXT_SPARE_REUSE_TAG_335_E = 930 , - WIFI_N_EXT_SPARE_REUSE_TAG_337_E = 932 , - WIFI_N_EXT_SPARE_REUSE_TAG_339_E = 934 , - WIFI_N_EXT_SPARE_REUSE_TAG_341_E = 936 , - WIFI_N_EXT_SPARE_REUSE_TAG_343_E = 938 , - WIFI_N_EXT_SPARE_REUSE_TAG_345_E = 940 , - WIFI_N_EXT_SPARE_REUSE_TAG_347_E = 942 , - WIFI_N_EXT_SPARE_REUSE_TAG_349_E = 944 , - WIFI_N_EXT_SPARE_REUSE_TAG_351_E = 946 , - WIFI_N_EXT_SPARE_REUSE_TAG_353_E = 948 , - WIFI_N_EXT_SPARE_REUSE_TAG_355_E = 950 , - WIFI_N_EXT_SPARE_REUSE_TAG_357_E = 952 , - WIFI_N_EXT_SPARE_REUSE_TAG_359_E = 954 , - WIFI_N_EXT_SPARE_REUSE_TAG_361_E = 956 , - WIFI_N_EXT_SPARE_REUSE_TAG_363_E = 958 , - WIFI_N_EXT_SPARE_REUSE_TAG_365_E = 960 , - WIFI_N_EXT_SPARE_REUSE_TAG_367_E = 962 , - WIFI_N_EXT_SPARE_REUSE_TAG_369_E = 964 , - WIFI_N_EXT_SPARE_REUSE_TAG_371_E = 966 , - WIFI_N_EXT_SPARE_REUSE_TAG_373_E = 968 , - WIFI_N_EXT_SPARE_REUSE_TAG_375_E = 970 , - WIFI_N_EXT_SPARE_REUSE_TAG_377_E = 972 , - WIFI_N_EXT_SPARE_REUSE_TAG_379_E = 974 , - WIFI_N_EXT_SPARE_REUSE_TAG_381_E = 976 , - WIFI_N_EXT_SPARE_REUSE_TAG_383_E = 978 , - WIFI_N_EXT_SPARE_REUSE_TAG_385_E = 980 , - WIFI_N_EXT_SPARE_REUSE_TAG_387_E = 982 , - WIFI_N_EXT_SPARE_REUSE_TAG_389_E = 984 , - WIFI_N_EXT_SPARE_REUSE_TAG_391_E = 986 , - WIFI_N_EXT_SPARE_REUSE_TAG_393_E = 988 , - WIFI_N_EXT_SPARE_REUSE_TAG_395_E = 990 , - WIFI_N_EXT_SPARE_REUSE_TAG_397_E = 992 , - WIFI_N_EXT_SPARE_REUSE_TAG_399_E = 994 , - WIFI_N_EXT_SPARE_REUSE_TAG_401_E = 996 , - WIFI_N_EXT_SPARE_REUSE_TAG_403_E = 998 , - WIFI_N_EXT_SPARE_REUSE_TAG_405_E = 1000 , - WIFI_N_EXT_SPARE_REUSE_TAG_407_E = 1002 , - WIFI_N_EXT_SPARE_REUSE_TAG_409_E = 1004 , - WIFI_N_EXT_SPARE_REUSE_TAG_411_E = 1006 , - WIFI_N_EXT_SPARE_REUSE_TAG_413_E = 1008 , - WIFI_N_EXT_SPARE_REUSE_TAG_415_E = 1010 , - WIFI_N_EXT_SPARE_REUSE_TAG_417_E = 1012 , - WIFI_N_EXT_SPARE_REUSE_TAG_419_E = 1014 , - WIFI_N_EXT_SPARE_REUSE_TAG_421_E = 1016 , - WIFI_N_EXT_SPARE_REUSE_TAG_423_E = 1018 , - WIFI_N_EXT_SPARE_REUSE_TAG_425_E = 1020 -} non_ext_tlv_tag_def__e; - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tqm2sw_completion_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/tqm2sw_completion_ring.h deleted file mode 100644 index f67deea1f6a1..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tqm2sw_completion_ring.h +++ /dev/null @@ -1,262 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TQM2SW_COMPLETION_RING_H_ -#define _TQM2SW_COMPLETION_RING_H_ - -#include "tx_rate_stats_info.h" -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_TQM2SW_COMPLETION_RING 8 - -struct tqm2sw_completion_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_or_desc_virt_addr_or_addr_info; - uint32_t release_source_module : 3, - cache_id : 1, - reserved_2a : 2, - buffer_or_desc_type : 3, - return_buffer_manager : 4, - tqm_release_reason : 4, - rbm_override_valid : 1, - sw_buffer_cookie_11_0 : 12, - cookie_conversion_status : 1, - tqm_completion_error : 1; - uint32_t tqm_status_number : 24, - transmit_count : 7, - sw_release_details_valid : 1; - uint32_t ack_frame_rssi : 8, - first_msdu : 1, - last_msdu : 1, - fw_tx_notify_frame : 3, - buffer_timestamp : 19; - struct tx_rate_stats_info tx_rate_stats; - uint32_t sw_peer_id : 16, - tid : 4, - sw_buffer_cookie_19_12 : 8, - looping_count : 4; -#else - struct buffer_addr_info buf_or_desc_virt_addr_or_addr_info; - uint32_t tqm_completion_error : 1, - cookie_conversion_status : 1, - sw_buffer_cookie_11_0 : 12, - rbm_override_valid : 1, - tqm_release_reason : 4, - return_buffer_manager : 4, - buffer_or_desc_type : 3, - reserved_2a : 2, - cache_id : 1, - release_source_module : 3; - uint32_t sw_release_details_valid : 1, - transmit_count : 7, - tqm_status_number : 24; - uint32_t buffer_timestamp : 19, - fw_tx_notify_frame : 3, - last_msdu : 1, - first_msdu : 1, - ack_frame_rssi : 8; - struct tx_rate_stats_info tx_rate_stats; - uint32_t looping_count : 4, - sw_buffer_cookie_19_12 : 8, - tid : 4, - sw_peer_id : 16; -#endif -}; - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define TQM2SW_COMPLETION_RING_BUF_OR_DESC_VIRT_ADDR_OR_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define TQM2SW_COMPLETION_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define TQM2SW_COMPLETION_RING_CACHE_ID_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_CACHE_ID_LSB 3 -#define TQM2SW_COMPLETION_RING_CACHE_ID_MSB 3 -#define TQM2SW_COMPLETION_RING_CACHE_ID_MASK 0x00000008 - -#define TQM2SW_COMPLETION_RING_RESERVED_2A_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_LSB 4 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_MSB 5 -#define TQM2SW_COMPLETION_RING_RESERVED_2A_MASK 0x00000030 - -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_LSB 6 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MSB 8 -#define TQM2SW_COMPLETION_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_LSB 9 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MSB 12 -#define TQM2SW_COMPLETION_RING_RETURN_BUFFER_MANAGER_MASK 0x00001e00 - -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_LSB 13 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MSB 16 -#define TQM2SW_COMPLETION_RING_TQM_RELEASE_REASON_MASK 0x0001e000 - -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_LSB 17 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MSB 17 -#define TQM2SW_COMPLETION_RING_RBM_OVERRIDE_VALID_MASK 0x00020000 - -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_LSB 18 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MSB 29 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 - -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_LSB 30 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MSB 30 -#define TQM2SW_COMPLETION_RING_COOKIE_CONVERSION_STATUS_MASK 0x40000000 - -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_OFFSET 0x00000008 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_LSB 31 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MSB 31 -#define TQM2SW_COMPLETION_RING_TQM_COMPLETION_ERROR_MASK 0x80000000 - -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_LSB 0 -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MSB 23 -#define TQM2SW_COMPLETION_RING_TQM_STATUS_NUMBER_MASK 0x00ffffff - -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_LSB 24 -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MSB 30 -#define TQM2SW_COMPLETION_RING_TRANSMIT_COUNT_MASK 0x7f000000 - -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_LSB 31 -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MSB 31 -#define TQM2SW_COMPLETION_RING_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 - -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_LSB 0 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MSB 7 -#define TQM2SW_COMPLETION_RING_ACK_FRAME_RSSI_MASK 0x000000ff - -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_LSB 8 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MSB 8 -#define TQM2SW_COMPLETION_RING_FIRST_MSDU_MASK 0x00000100 - -#define TQM2SW_COMPLETION_RING_LAST_MSDU_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_LSB 9 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_MSB 9 -#define TQM2SW_COMPLETION_RING_LAST_MSDU_MASK 0x00000200 - -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_LSB 10 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MSB 12 -#define TQM2SW_COMPLETION_RING_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 - -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_OFFSET 0x00000010 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_LSB 13 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MSB 31 -#define TQM2SW_COMPLETION_RING_BUFFER_TIMESTAMP_MASK 0xffffe000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_LSB 1 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MSB 3 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MSB 16 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0001f000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_LSB 17 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MSB 19 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_UNEQUAL_MODULATION_INFO_MASK 0x000e0000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 20 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 20 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00100000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_LSB 21 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MSB 24 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_RESERVED_0A_MASK 0x01e00000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_LSB 25 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MSB 28 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TONES_IN_RU_MASK 0x1e000000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 - -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 -#define TQM2SW_COMPLETION_RING_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff - -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_LSB 0 -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MSB 15 -#define TQM2SW_COMPLETION_RING_SW_PEER_ID_MASK 0x0000ffff - -#define TQM2SW_COMPLETION_RING_TID_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_TID_LSB 16 -#define TQM2SW_COMPLETION_RING_TID_MSB 19 -#define TQM2SW_COMPLETION_RING_TID_MASK 0x000f0000 - -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_LSB 20 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MSB 27 -#define TQM2SW_COMPLETION_RING_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 - -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_LSB 28 -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MSB 31 -#define TQM2SW_COMPLETION_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_cbf_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_cbf_info.h deleted file mode 100644 index 772b09d7b2a1..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_cbf_info.h +++ /dev/null @@ -1,454 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_CBF_INFO_H_ -#define _TX_CBF_INFO_H_ - -#define NUM_OF_DWORDS_TX_CBF_INFO 16 - -#define NUM_OF_QWORDS_TX_CBF_INFO 8 - -struct tx_cbf_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t sw_peer_id : 16, - pre_cbf_duration : 16; - uint32_t brpoll_info_valid : 1, - trigger_brpoll_info_valid : 1, - npda_info_11ac_valid : 1, - npda_info_11ax_valid : 1, - dot11ax_su_extended : 1, - bandwidth : 3, - brpoll_info : 8, - cbf_response_table_base_index : 8, - peer_index : 3, - pkt_type : 4, - txop_duration_all_ones : 1; - uint32_t trigger_brpoll_common_info_15_0 : 16, - trigger_brpoll_common_info_31_16 : 16; - uint32_t trigger_brpoll_user_info_15_0 : 16, - trigger_brpoll_user_info_31_16 : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr1_47_32 : 16, - addr2_15_0 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t addr3_47_32 : 16, - sta_partial_aid : 11, - __reserved_g_0086 : 1, - reserved_8a : 3, - cbf_resp_pwr_mgmt : 1; - uint32_t group_id : 6, - rssi_comb : 8, - reserved_9a : 2, - vht_ndpa_sta_info : 16; - uint32_t he_eht_sta_info_15_0 : 16, - he_eht_sta_info_31_16 : 16; - uint32_t dot11ax_received_format_indication : 1, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_bss_color_id : 6, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_cp_size : 2, - dot11ax_received_ltf_size : 2, - dot11ax_received_coding : 1, - dot11ax_received_dcm : 1, - dot11ax_received_doppler_indication : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_dl_ul_flag : 1, - reserved_11a : 8; - uint32_t sw_response_frame_length : 16, - sw_response_tlv_from_crypto : 1, - wait_sifs_config_valid : 1, - wait_sifs : 2, - __reserved_g_0005 : 1, - secure : 1, - tb___reserved_g_0005_response_required : 2, - emlsr_main_tlv_if : 1, - reserved_12a : 1, - u_sig_puncture_pattern_encoding : 6; - uint32_t dot11be_puncture_bitmap : 16, - dot11be_response : 1, - punctured_response : 1, - npda_info_11be_valid : 1, - eht_duplicate_mode : 2, - reserved_13a : 11; - uint32_t eht_sta_info_39_32 : 8, - unassociated___reserved_g_0005_peer : 1, - reserved_14a : 23; - uint32_t tlv64_padding : 32; -#else - uint32_t pre_cbf_duration : 16, - sw_peer_id : 16; - uint32_t txop_duration_all_ones : 1, - pkt_type : 4, - peer_index : 3, - cbf_response_table_base_index : 8, - brpoll_info : 8, - bandwidth : 3, - dot11ax_su_extended : 1, - npda_info_11ax_valid : 1, - npda_info_11ac_valid : 1, - trigger_brpoll_info_valid : 1, - brpoll_info_valid : 1; - uint32_t trigger_brpoll_common_info_31_16 : 16, - trigger_brpoll_common_info_15_0 : 16; - uint32_t trigger_brpoll_user_info_31_16 : 16, - trigger_brpoll_user_info_15_0 : 16; - uint32_t addr1_31_0 : 32; - uint32_t addr2_15_0 : 16, - addr1_47_32 : 16; - uint32_t addr2_47_16 : 32; - uint32_t addr3_31_0 : 32; - uint32_t cbf_resp_pwr_mgmt : 1, - reserved_8a : 3, - __reserved_g_0086 : 1, - sta_partial_aid : 11, - addr3_47_32 : 16; - uint32_t vht_ndpa_sta_info : 16, - reserved_9a : 2, - rssi_comb : 8, - group_id : 6; - uint32_t he_eht_sta_info_31_16 : 16, - he_eht_sta_info_15_0 : 16; - uint32_t reserved_11a : 8, - dot11ax_dl_ul_flag : 1, - dot11ax_received_ext_ru_size : 4, - dot11ax_received_doppler_indication : 1, - dot11ax_received_dcm : 1, - dot11ax_received_coding : 1, - dot11ax_received_ltf_size : 2, - dot11ax_received_cp_size : 2, - dot11ax_received_spatial_reuse : 4, - dot11ax_received_bss_color_id : 6, - dot11ax_received_dl_ul_flag : 1, - dot11ax_received_format_indication : 1; - uint32_t u_sig_puncture_pattern_encoding : 6, - reserved_12a : 1, - emlsr_main_tlv_if : 1, - tb___reserved_g_0005_response_required : 2, - secure : 1, - __reserved_g_0005 : 1, - wait_sifs : 2, - wait_sifs_config_valid : 1, - sw_response_tlv_from_crypto : 1, - sw_response_frame_length : 16; - uint32_t reserved_13a : 11, - eht_duplicate_mode : 2, - npda_info_11be_valid : 1, - punctured_response : 1, - dot11be_response : 1, - dot11be_puncture_bitmap : 16; - uint32_t reserved_14a : 23, - unassociated___reserved_g_0005_peer : 1, - eht_sta_info_39_32 : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_CBF_INFO_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_SW_PEER_ID_LSB 0 -#define TX_CBF_INFO_SW_PEER_ID_MSB 15 -#define TX_CBF_INFO_SW_PEER_ID_MASK 0x000000000000ffff - -#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PRE_CBF_DURATION_LSB 16 -#define TX_CBF_INFO_PRE_CBF_DURATION_MSB 31 -#define TX_CBF_INFO_PRE_CBF_DURATION_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB 32 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB 32 -#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK 0x0000000100000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB 33 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB 33 -#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK 0x0000000200000000 - -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB 34 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB 34 -#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK 0x0000000400000000 - -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB 35 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB 35 -#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK 0x0000000800000000 - -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB 36 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB 36 -#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000001000000000 - -#define TX_CBF_INFO_BANDWIDTH_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BANDWIDTH_LSB 37 -#define TX_CBF_INFO_BANDWIDTH_MSB 39 -#define TX_CBF_INFO_BANDWIDTH_MASK 0x000000e000000000 - -#define TX_CBF_INFO_BRPOLL_INFO_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_BRPOLL_INFO_LSB 40 -#define TX_CBF_INFO_BRPOLL_INFO_MSB 47 -#define TX_CBF_INFO_BRPOLL_INFO_MASK 0x0000ff0000000000 - -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB 48 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB 55 -#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK 0x00ff000000000000 - -#define TX_CBF_INFO_PEER_INDEX_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PEER_INDEX_LSB 56 -#define TX_CBF_INFO_PEER_INDEX_MSB 58 -#define TX_CBF_INFO_PEER_INDEX_MASK 0x0700000000000000 - -#define TX_CBF_INFO_PKT_TYPE_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_PKT_TYPE_LSB 59 -#define TX_CBF_INFO_PKT_TYPE_MSB 62 -#define TX_CBF_INFO_PKT_TYPE_MASK 0x7800000000000000 - -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB 63 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB 63 -#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB 0 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB 15 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK 0x000000000000ffff - -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB 16 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB 31 -#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB 32 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB 47 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET 0x0000000000000008 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB 48 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB 63 -#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK 0xffff000000000000 - -#define TX_CBF_INFO_ADDR1_31_0_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR1_31_0_LSB 0 -#define TX_CBF_INFO_ADDR1_31_0_MSB 31 -#define TX_CBF_INFO_ADDR1_31_0_MASK 0x00000000ffffffff - -#define TX_CBF_INFO_ADDR1_47_32_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR1_47_32_LSB 32 -#define TX_CBF_INFO_ADDR1_47_32_MSB 47 -#define TX_CBF_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_ADDR2_15_0_OFFSET 0x0000000000000010 -#define TX_CBF_INFO_ADDR2_15_0_LSB 48 -#define TX_CBF_INFO_ADDR2_15_0_MSB 63 -#define TX_CBF_INFO_ADDR2_15_0_MASK 0xffff000000000000 - -#define TX_CBF_INFO_ADDR2_47_16_OFFSET 0x0000000000000018 -#define TX_CBF_INFO_ADDR2_47_16_LSB 0 -#define TX_CBF_INFO_ADDR2_47_16_MSB 31 -#define TX_CBF_INFO_ADDR2_47_16_MASK 0x00000000ffffffff - -#define TX_CBF_INFO_ADDR3_31_0_OFFSET 0x0000000000000018 -#define TX_CBF_INFO_ADDR3_31_0_LSB 32 -#define TX_CBF_INFO_ADDR3_31_0_MSB 63 -#define TX_CBF_INFO_ADDR3_31_0_MASK 0xffffffff00000000 - -#define TX_CBF_INFO_ADDR3_47_32_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_ADDR3_47_32_LSB 0 -#define TX_CBF_INFO_ADDR3_47_32_MSB 15 -#define TX_CBF_INFO_ADDR3_47_32_MASK 0x000000000000ffff - -#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_STA_PARTIAL_AID_LSB 16 -#define TX_CBF_INFO_STA_PARTIAL_AID_MSB 26 -#define TX_CBF_INFO_STA_PARTIAL_AID_MASK 0x0000000007ff0000 - -#define TX_CBF_INFO_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RESERVED_8A_LSB 28 -#define TX_CBF_INFO_RESERVED_8A_MSB 30 -#define TX_CBF_INFO_RESERVED_8A_MASK 0x0000000070000000 - -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB 31 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB 31 -#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK 0x0000000080000000 - -#define TX_CBF_INFO_GROUP_ID_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_GROUP_ID_LSB 32 -#define TX_CBF_INFO_GROUP_ID_MSB 37 -#define TX_CBF_INFO_GROUP_ID_MASK 0x0000003f00000000 - -#define TX_CBF_INFO_RSSI_COMB_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RSSI_COMB_LSB 38 -#define TX_CBF_INFO_RSSI_COMB_MSB 45 -#define TX_CBF_INFO_RSSI_COMB_MASK 0x00003fc000000000 - -#define TX_CBF_INFO_RESERVED_9A_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_RESERVED_9A_LSB 46 -#define TX_CBF_INFO_RESERVED_9A_MSB 47 -#define TX_CBF_INFO_RESERVED_9A_MASK 0x0000c00000000000 - -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET 0x0000000000000020 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB 48 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB 63 -#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK 0xffff000000000000 - -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB 0 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB 15 -#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK 0x000000000000ffff - -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB 16 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB 31 -#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK 0x00000000ffff0000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 -#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 -#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 -#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 -#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB 48 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB 48 -#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB 49 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB 49 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 -#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 - -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 -#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 - -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB 55 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB 55 -#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0080000000000000 - -#define TX_CBF_INFO_RESERVED_11A_OFFSET 0x0000000000000028 -#define TX_CBF_INFO_RESERVED_11A_LSB 56 -#define TX_CBF_INFO_RESERVED_11A_MSB 63 -#define TX_CBF_INFO_RESERVED_11A_MASK 0xff00000000000000 - -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15 -#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x000000000000ffff - -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 16 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 16 -#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000000010000 - -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB 17 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB 17 -#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000000020000 - -#define TX_CBF_INFO_WAIT_SIFS_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_WAIT_SIFS_LSB 18 -#define TX_CBF_INFO_WAIT_SIFS_MSB 19 -#define TX_CBF_INFO_WAIT_SIFS_MASK 0x00000000000c0000 - -#define TX_CBF_INFO_SECURE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_SECURE_LSB 21 -#define TX_CBF_INFO_SECURE_MSB 21 -#define TX_CBF_INFO_SECURE_MASK 0x0000000000200000 - -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_LSB 24 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MSB 24 -#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MASK 0x0000000001000000 - -#define TX_CBF_INFO_RESERVED_12A_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_RESERVED_12A_LSB 25 -#define TX_CBF_INFO_RESERVED_12A_MSB 25 -#define TX_CBF_INFO_RESERVED_12A_MASK 0x0000000002000000 - -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 -#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 - -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 -#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 - -#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB 48 -#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB 48 -#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 - -#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB 49 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB 49 -#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 - -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB 50 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB 50 -#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK 0x0004000000000000 - -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB 51 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB 52 -#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK 0x0018000000000000 - -#define TX_CBF_INFO_RESERVED_13A_OFFSET 0x0000000000000030 -#define TX_CBF_INFO_RESERVED_13A_LSB 53 -#define TX_CBF_INFO_RESERVED_13A_MSB 63 -#define TX_CBF_INFO_RESERVED_13A_MASK 0xffe0000000000000 - -#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB 0 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB 7 -#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK 0x00000000000000ff - -#define TX_CBF_INFO_RESERVED_14A_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_RESERVED_14A_LSB 9 -#define TX_CBF_INFO_RESERVED_14A_MSB 31 -#define TX_CBF_INFO_RESERVED_14A_MASK 0x00000000fffffe00 - -#define TX_CBF_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 -#define TX_CBF_INFO_TLV64_PADDING_LSB 32 -#define TX_CBF_INFO_TLV64_PADDING_MSB 63 -#define TX_CBF_INFO_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_setup.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_setup.h deleted file mode 100644 index 360e373b8019..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_setup.h +++ /dev/null @@ -1,585 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_SETUP_H_ -#define _TX_FES_SETUP_H_ - -#define NUM_OF_DWORDS_TX_FES_SETUP 10 - -#define NUM_OF_QWORDS_TX_FES_SETUP 5 - -struct tx_fes_setup { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t schedule_id : 32; - uint32_t fes_in_11ax_trigger_response_config : 1, - bo_based_tid_aggregation_limit : 4, - __reserved_g_0005 : 1, - expect_i2r_lmr : 1, - transmit_start_reason : 3, - use_alt_power_sr : 1, - static_2_pwr_mode_status : 1, - obss_srg_opport_transmit_status : 1, - srp_based_transmit_status : 1, - obss_pd_based_transmit_status : 1, - puncture_from_all_allowed_modes : 1, - schedule_cmd_ring_id : 5, - fes_control_mode : 2, - number_of_users : 6, - mu_type : 1, - ofdma_triggered_response : 1, - response_to_response_cmd : 1; - uint32_t schedule_try : 4, - reserved_2a : 1, - subband_antenna_selection_en : 1, - txbf : 1, - allow_txop_exceed_in_1st_pkt : 1, - ignore_bw_available : 1, - ignore_tbtt : 1, - static_bandwidth : 3, - set_txop_duration_all_ones : 1, - transmission_contains_mu_rts : 1, - bw_restricted_frames_embedded : 1, - ast_index : 16; - uint32_t cv_id : 8, - trigger_resp_txpdu_ppdu_boundary : 2, - rxpcu_setup_complete_present : 1, - rbo_must_have_data_user_limit : 4, - mu_ndp : 1, - bf_type : 2, - cbf_nc_index_mask : 1, - cbf_nc_index : 3, - cbf_nr_index_mask : 1, - cbf_nr_index : 3, - secure___reserved_g_0005_ista : 1, - ndpa : 1, - wait_sifs : 2, - cbf_feedback_type_mask : 1, - cbf_feedback_type : 1; - uint32_t cbf_sounding_token : 6, - cbf_sounding_token_mask : 1, - cbf_bw_mask : 1, - cbf_bw : 3, - use_static_bw : 1, - coex_nack_count : 5, - sch_tx_burst_ongoing : 1, - gen_tqm_update_mpdu_count_tlv : 1, - rts_tx_over___reserved_g_0016 : 1, - ndp_frame : 3, - optimal_bw_retry_count : 4, - fes_continuation_ratio_threshold : 5; - uint32_t transmit_cca_bitmap : 32; - uint32_t tb___reserved_g_0005 : 1, - __reserved_g_0005_trigger_subtype : 4, - min_cts2self_count : 4, - max_cts2self_count : 4, - wifi_radar_enable : 1, - reserved_6a : 1, - wait_for_chksum_done : 1, - txrx_self_test_enable : 1, - rtt_self_cal_enable : 1, - secure___reserved_g_0005_rsta : 1, - hip_edca_prot_enable : 1, - hip_edca_prot_required : 1, - hip_edca_mini_contention_gap : 8, - last_command_in_burst : 1, - retain_peer_blackout_details : 1, - enable_hw_qos_null : 1; - uint32_t monitor_override_sta_31_0 : 32; - uint32_t monitor_override_sta_36_32 : 5, - enable_qos_null_switch_for_eosp : 1, - __reserved_g_0086 : 1, - __reserved_g_0081 : 1, - __reserved_g_0084 : 2, - __reserved_g_0074 : 4, - cfp_protected_fes : 1, - dot11ax_trigger_frame_embedded : 1, - multiple_triggers_indication : 1, - cmf_uif_length : 4, - npca_switching_cts2self_duration : 8, - reserved_8a : 3; - uint32_t fw2sw_info : 32; -#else - uint32_t schedule_id : 32; - uint32_t response_to_response_cmd : 1, - ofdma_triggered_response : 1, - mu_type : 1, - number_of_users : 6, - fes_control_mode : 2, - schedule_cmd_ring_id : 5, - puncture_from_all_allowed_modes : 1, - obss_pd_based_transmit_status : 1, - srp_based_transmit_status : 1, - obss_srg_opport_transmit_status : 1, - static_2_pwr_mode_status : 1, - use_alt_power_sr : 1, - transmit_start_reason : 3, - expect_i2r_lmr : 1, - __reserved_g_0005 : 1, - bo_based_tid_aggregation_limit : 4, - fes_in_11ax_trigger_response_config : 1; - uint32_t ast_index : 16, - bw_restricted_frames_embedded : 1, - transmission_contains_mu_rts : 1, - set_txop_duration_all_ones : 1, - static_bandwidth : 3, - ignore_tbtt : 1, - ignore_bw_available : 1, - allow_txop_exceed_in_1st_pkt : 1, - txbf : 1, - subband_antenna_selection_en : 1, - reserved_2a : 1, - schedule_try : 4; - uint32_t cbf_feedback_type : 1, - cbf_feedback_type_mask : 1, - wait_sifs : 2, - ndpa : 1, - secure___reserved_g_0005_ista : 1, - cbf_nr_index : 3, - cbf_nr_index_mask : 1, - cbf_nc_index : 3, - cbf_nc_index_mask : 1, - bf_type : 2, - mu_ndp : 1, - rbo_must_have_data_user_limit : 4, - rxpcu_setup_complete_present : 1, - trigger_resp_txpdu_ppdu_boundary : 2, - cv_id : 8; - uint32_t fes_continuation_ratio_threshold : 5, - optimal_bw_retry_count : 4, - ndp_frame : 3, - rts_tx_over___reserved_g_0016 : 1, - gen_tqm_update_mpdu_count_tlv : 1, - sch_tx_burst_ongoing : 1, - coex_nack_count : 5, - use_static_bw : 1, - cbf_bw : 3, - cbf_bw_mask : 1, - cbf_sounding_token_mask : 1, - cbf_sounding_token : 6; - uint32_t transmit_cca_bitmap : 32; - uint32_t enable_hw_qos_null : 1, - retain_peer_blackout_details : 1, - last_command_in_burst : 1, - hip_edca_mini_contention_gap : 8, - hip_edca_prot_required : 1, - hip_edca_prot_enable : 1, - secure___reserved_g_0005_rsta : 1, - rtt_self_cal_enable : 1, - txrx_self_test_enable : 1, - wait_for_chksum_done : 1, - reserved_6a : 1, - wifi_radar_enable : 1, - max_cts2self_count : 4, - min_cts2self_count : 4, - __reserved_g_0005_trigger_subtype : 4, - tb___reserved_g_0005 : 1; - uint32_t monitor_override_sta_31_0 : 32; - uint32_t reserved_8a : 3, - npca_switching_cts2self_duration : 8, - cmf_uif_length : 4, - multiple_triggers_indication : 1, - dot11ax_trigger_frame_embedded : 1, - cfp_protected_fes : 1, - __reserved_g_0074 : 4, - __reserved_g_0084 : 2, - __reserved_g_0081 : 1, - __reserved_g_0086 : 1, - enable_qos_null_switch_for_eosp : 1, - monitor_override_sta_36_32 : 5; - uint32_t fw2sw_info : 32; -#endif -}; - -#define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SCHEDULE_ID_LSB 0 -#define TX_FES_SETUP_SCHEDULE_ID_MSB 31 -#define TX_FES_SETUP_SCHEDULE_ID_MASK 0x00000000ffffffff - -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 32 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 32 -#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x0000000100000000 - -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 33 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 36 -#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e00000000 - -#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 38 -#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 38 -#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x0000004000000000 - -#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 39 -#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 41 -#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x0000038000000000 - -#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 42 -#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 42 -#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x0000040000000000 - -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 43 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 43 -#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x0000080000000000 - -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 44 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 44 -#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000100000000000 - -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 45 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 45 -#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000200000000000 - -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 46 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 46 -#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000400000000000 - -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 47 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 47 -#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x0000800000000000 - -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 48 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 52 -#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 - -#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_FES_CONTROL_MODE_LSB 53 -#define TX_FES_SETUP_FES_CONTROL_MODE_MSB 54 -#define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x0060000000000000 - -#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_NUMBER_OF_USERS_LSB 55 -#define TX_FES_SETUP_NUMBER_OF_USERS_MSB 60 -#define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f80000000000000 - -#define TX_FES_SETUP_MU_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_MU_TYPE_LSB 61 -#define TX_FES_SETUP_MU_TYPE_MSB 61 -#define TX_FES_SETUP_MU_TYPE_MASK 0x2000000000000000 - -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 62 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 62 -#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x4000000000000000 - -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x0000000000000000 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 63 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 63 -#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x8000000000000000 - -#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 -#define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 -#define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x000000000000000f - -#define TX_FES_SETUP_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RESERVED_2A_LSB 4 -#define TX_FES_SETUP_RESERVED_2A_MSB 4 -#define TX_FES_SETUP_RESERVED_2A_MASK 0x0000000000000010 - -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_LSB 5 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MSB 5 -#define TX_FES_SETUP_SUBBAND_ANTENNA_SELECTION_EN_MASK 0x0000000000000020 - -#define TX_FES_SETUP_TXBF_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TXBF_LSB 6 -#define TX_FES_SETUP_TXBF_MSB 6 -#define TX_FES_SETUP_TXBF_MASK 0x0000000000000040 - -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 -#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x0000000000000080 - -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 -#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x0000000000000100 - -#define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_IGNORE_TBTT_LSB 9 -#define TX_FES_SETUP_IGNORE_TBTT_MSB 9 -#define TX_FES_SETUP_IGNORE_TBTT_MASK 0x0000000000000200 - -#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 -#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 -#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x0000000000001c00 - -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 -#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x0000000000002000 - -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 -#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x0000000000004000 - -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 -#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x0000000000008000 - -#define TX_FES_SETUP_AST_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_AST_INDEX_LSB 16 -#define TX_FES_SETUP_AST_INDEX_MSB 31 -#define TX_FES_SETUP_AST_INDEX_MASK 0x00000000ffff0000 - -#define TX_FES_SETUP_CV_ID_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CV_ID_LSB 32 -#define TX_FES_SETUP_CV_ID_MSB 39 -#define TX_FES_SETUP_CV_ID_MASK 0x000000ff00000000 - -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 40 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 41 -#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x0000030000000000 - -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 42 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 42 -#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x0000040000000000 - -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 43 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 46 -#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x0000780000000000 - -#define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_MU_NDP_LSB 47 -#define TX_FES_SETUP_MU_NDP_MSB 47 -#define TX_FES_SETUP_MU_NDP_MASK 0x0000800000000000 - -#define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_BF_TYPE_LSB 48 -#define TX_FES_SETUP_BF_TYPE_MSB 49 -#define TX_FES_SETUP_BF_TYPE_MASK 0x0003000000000000 - -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 50 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 50 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x0004000000000000 - -#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NC_INDEX_LSB 51 -#define TX_FES_SETUP_CBF_NC_INDEX_MSB 53 -#define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x0038000000000000 - -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 54 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 54 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x0040000000000000 - -#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_NR_INDEX_LSB 55 -#define TX_FES_SETUP_CBF_NR_INDEX_MSB 57 -#define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x0380000000000000 - -#define TX_FES_SETUP_NDPA_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_NDPA_LSB 59 -#define TX_FES_SETUP_NDPA_MSB 59 -#define TX_FES_SETUP_NDPA_MASK 0x0800000000000000 - -#define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_WAIT_SIFS_LSB 60 -#define TX_FES_SETUP_WAIT_SIFS_MSB 61 -#define TX_FES_SETUP_WAIT_SIFS_MASK 0x3000000000000000 - -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 62 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 62 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x4000000000000000 - -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 63 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 63 -#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x8000000000000000 - -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x000000000000003f - -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 -#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x0000000000000040 - -#define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_BW_MASK_LSB 7 -#define TX_FES_SETUP_CBF_BW_MASK_MSB 7 -#define TX_FES_SETUP_CBF_BW_MASK_MASK 0x0000000000000080 - -#define TX_FES_SETUP_CBF_BW_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_CBF_BW_LSB 8 -#define TX_FES_SETUP_CBF_BW_MSB 10 -#define TX_FES_SETUP_CBF_BW_MASK 0x0000000000000700 - -#define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_USE_STATIC_BW_LSB 11 -#define TX_FES_SETUP_USE_STATIC_BW_MSB 11 -#define TX_FES_SETUP_USE_STATIC_BW_MASK 0x0000000000000800 - -#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 -#define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 -#define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x000000000001f000 - -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 -#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x0000000000020000 - -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 -#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x0000000000040000 - -#define TX_FES_SETUP_NDP_FRAME_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_NDP_FRAME_LSB 20 -#define TX_FES_SETUP_NDP_FRAME_MSB 22 -#define TX_FES_SETUP_NDP_FRAME_MASK 0x0000000000700000 - -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 -#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x0000000007800000 - -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 -#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0x00000000f8000000 - -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x0000000000000010 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 32 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 63 -#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff00000000 - -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 -#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x00000000000001e0 - -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 -#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x0000000000001e00 - -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 -#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x0000000000002000 - -#define TX_FES_SETUP_RESERVED_6A_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RESERVED_6A_LSB 14 -#define TX_FES_SETUP_RESERVED_6A_MSB 14 -#define TX_FES_SETUP_RESERVED_6A_MASK 0x0000000000004000 - -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_LSB 15 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MSB 15 -#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MASK 0x0000000000008000 - -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_LSB 16 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MSB 16 -#define TX_FES_SETUP_TXRX_SELF_TEST_ENABLE_MASK 0x0000000000010000 - -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_LSB 17 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MSB 17 -#define TX_FES_SETUP_RTT_SELF_CAL_ENABLE_MASK 0x0000000000020000 - -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_LSB 19 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MSB 19 -#define TX_FES_SETUP_HIP_EDCA_PROT_ENABLE_MASK 0x0000000000080000 - -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_LSB 20 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MSB 20 -#define TX_FES_SETUP_HIP_EDCA_PROT_REQUIRED_MASK 0x0000000000100000 - -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_LSB 21 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MSB 28 -#define TX_FES_SETUP_HIP_EDCA_MINI_CONTENTION_GAP_MASK 0x000000001fe00000 - -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_LSB 29 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MSB 29 -#define TX_FES_SETUP_LAST_COMMAND_IN_BURST_MASK 0x0000000020000000 - -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_LSB 30 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MSB 30 -#define TX_FES_SETUP_RETAIN_PEER_BLACKOUT_DETAILS_MASK 0x0000000040000000 - -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_LSB 31 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MSB 31 -#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MASK 0x0000000080000000 - -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000000000000018 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 32 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 63 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff00000000 - -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 -#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x000000000000001f - -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_LSB 5 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MSB 5 -#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MASK 0x0000000000000020 - -#define TX_FES_SETUP_CFP_PROTECTED_FES_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_CFP_PROTECTED_FES_LSB 14 -#define TX_FES_SETUP_CFP_PROTECTED_FES_MSB 14 -#define TX_FES_SETUP_CFP_PROTECTED_FES_MASK 0x0000000000004000 - -#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 15 -#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 15 -#define TX_FES_SETUP_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000000000008000 - -#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_LSB 16 -#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_MSB 16 -#define TX_FES_SETUP_MULTIPLE_TRIGGERS_INDICATION_MASK 0x0000000000010000 - -#define TX_FES_SETUP_CMF_UIF_LENGTH_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_CMF_UIF_LENGTH_LSB 17 -#define TX_FES_SETUP_CMF_UIF_LENGTH_MSB 20 -#define TX_FES_SETUP_CMF_UIF_LENGTH_MASK 0x00000000001e0000 - -#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_LSB 21 -#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_MSB 28 -#define TX_FES_SETUP_NPCA_SWITCHING_CTS2SELF_DURATION_MASK 0x000000001fe00000 - -#define TX_FES_SETUP_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_RESERVED_8A_LSB 29 -#define TX_FES_SETUP_RESERVED_8A_MSB 31 -#define TX_FES_SETUP_RESERVED_8A_MASK 0x00000000e0000000 - -#define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x0000000000000020 -#define TX_FES_SETUP_FW2SW_INFO_LSB 32 -#define TX_FES_SETUP_FW2SW_INFO_MSB 63 -#define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_1k_ba.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_1k_ba.h deleted file mode 100644 index 4409dc03ac03..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_1k_ba.h +++ /dev/null @@ -1,313 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_1K_BA_H_ -#define _TX_FES_STATUS_1K_BA_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 - -#define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17 - -struct tx_fes_status_1k_ba { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ack_ba_status_type : 1, - ba_type : 1, - ba_tid : 4, - unexpected_ack_or_ba : 1, - response_timeout : 1, - ack_frame_rssi : 8, - ssn : 12, - reserved_0b : 4; - uint32_t sw_peer_id : 16, - reserved_1a : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; - uint32_t ba_bitmap_287_256 : 32; - uint32_t ba_bitmap_319_288 : 32; - uint32_t ba_bitmap_351_320 : 32; - uint32_t ba_bitmap_383_352 : 32; - uint32_t ba_bitmap_415_384 : 32; - uint32_t ba_bitmap_447_416 : 32; - uint32_t ba_bitmap_479_448 : 32; - uint32_t ba_bitmap_511_480 : 32; - uint32_t ba_bitmap_543_512 : 32; - uint32_t ba_bitmap_575_544 : 32; - uint32_t ba_bitmap_607_576 : 32; - uint32_t ba_bitmap_639_608 : 32; - uint32_t ba_bitmap_671_640 : 32; - uint32_t ba_bitmap_703_672 : 32; - uint32_t ba_bitmap_735_704 : 32; - uint32_t ba_bitmap_767_736 : 32; - uint32_t ba_bitmap_799_768 : 32; - uint32_t ba_bitmap_831_800 : 32; - uint32_t ba_bitmap_863_832 : 32; - uint32_t ba_bitmap_895_864 : 32; - uint32_t ba_bitmap_927_896 : 32; - uint32_t ba_bitmap_959_928 : 32; - uint32_t ba_bitmap_991_960 : 32; - uint32_t ba_bitmap_1023_992 : 32; -#else - uint32_t reserved_0b : 4, - ssn : 12, - ack_frame_rssi : 8, - response_timeout : 1, - unexpected_ack_or_ba : 1, - ba_tid : 4, - ba_type : 1, - ack_ba_status_type : 1; - uint32_t reserved_1a : 16, - sw_peer_id : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; - uint32_t ba_bitmap_287_256 : 32; - uint32_t ba_bitmap_319_288 : 32; - uint32_t ba_bitmap_351_320 : 32; - uint32_t ba_bitmap_383_352 : 32; - uint32_t ba_bitmap_415_384 : 32; - uint32_t ba_bitmap_447_416 : 32; - uint32_t ba_bitmap_479_448 : 32; - uint32_t ba_bitmap_511_480 : 32; - uint32_t ba_bitmap_543_512 : 32; - uint32_t ba_bitmap_575_544 : 32; - uint32_t ba_bitmap_607_576 : 32; - uint32_t ba_bitmap_639_608 : 32; - uint32_t ba_bitmap_671_640 : 32; - uint32_t ba_bitmap_703_672 : 32; - uint32_t ba_bitmap_735_704 : 32; - uint32_t ba_bitmap_767_736 : 32; - uint32_t ba_bitmap_799_768 : 32; - uint32_t ba_bitmap_831_800 : 32; - uint32_t ba_bitmap_863_832 : 32; - uint32_t ba_bitmap_895_864 : 32; - uint32_t ba_bitmap_927_896 : 32; - uint32_t ba_bitmap_959_928 : 32; - uint32_t ba_bitmap_991_960 : 32; - uint32_t ba_bitmap_1023_992 : 32; -#endif -}; - -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 -#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 - -#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 -#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 -#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002 - -#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 -#define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 -#define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c - -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 -#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 - -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 -#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 - -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 -#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_SSN_LSB 16 -#define TX_FES_STATUS_1K_BA_SSN_MSB 27 -#define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000 - -#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 -#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000 - -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47 -#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63 -#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63 -#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_ack_or_ba.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_ack_or_ba.h deleted file mode 100644 index 678c639141ba..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_ack_or_ba.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_ACK_OR_BA_H_ -#define _TX_FES_STATUS_ACK_OR_BA_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10 - -#define NUM_OF_QWORDS_TX_FES_STATUS_ACK_OR_BA 5 - -struct tx_fes_status_ack_or_ba { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ack_ba_status_type : 1, - ba_type : 1, - ba_tid : 4, - unexpected_ack_or_ba : 1, - response_timeout : 1, - ack_frame_rssi : 8, - ssn : 12, - reserved_0b : 4; - uint32_t sw_peer_id : 16, - reserved_1a : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; -#else - uint32_t reserved_0b : 4, - ssn : 12, - ack_frame_rssi : 8, - response_timeout : 1, - unexpected_ack_or_ba : 1, - ba_tid : 4, - ba_type : 1, - ack_ba_status_type : 1; - uint32_t reserved_1a : 16, - sw_peer_id : 16; - uint32_t ba_bitmap_31_0 : 32; - uint32_t ba_bitmap_63_32 : 32; - uint32_t ba_bitmap_95_64 : 32; - uint32_t ba_bitmap_127_96 : 32; - uint32_t ba_bitmap_159_128 : 32; - uint32_t ba_bitmap_191_160 : 32; - uint32_t ba_bitmap_223_192 : 32; - uint32_t ba_bitmap_255_224 : 32; -#endif -}; - -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB 0 -#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 - -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB 1 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB 1 -#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK 0x0000000000000002 - -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB 2 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB 5 -#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK 0x000000000000003c - -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB 6 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB 6 -#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 - -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB 7 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB 7 -#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 - -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB 8 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB 15 -#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB 16 -#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB 27 -#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK 0x000000000fff0000 - -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB 28 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK 0x00000000f0000000 - -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB 47 -#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB 48 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK 0xffff000000000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB 0 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB 31 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB 32 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB 63 -#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_end.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_end.h deleted file mode 100644 index f1ac77424029..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_end.h +++ /dev/null @@ -1,602 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_END_H_ -#define _TX_FES_STATUS_END_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_END 12 - -#define NUM_OF_QWORDS_TX_FES_STATUS_END 6 - -struct tx_fes_status_end { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t __reserved_g_0052 : 1, - __reserved_g_0053 : 1, - __reserved_g_0035 : 1, - __reserved_g_0036 : 1, - __reserved_g_0032 : 1, - __reserved_g_0033 : 1, - __reserved_g_0072 : 1, - __reserved_g_0073 : 1, - __reserved_g_0065 : 1, - __reserved_g_0066 : 1, - __reserved_g_0062 : 1, - __reserved_g_0063 : 1, - global_data_underflow_warning : 1, - global_fes_transmit_result : 4, - cbf_bw_received_valid : 1, - cbf_bw_received : 3, - actual_received_ack_type : 4, - sta_response_count : 6, - more_data_received : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t reserved_after_struct16 : 4, - brp_info_valid : 1, - qos_null_switch_done_for_eosp : 1, - reserved_1a : 5, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - fes_in_11ax_trigger_response_config : 1, - null_delim_inserted_before_mpdus : 1, - only_null_delim_sent : 1; - uint32_t terminate___reserved_g_0005_sequence : 1, - unsolicited_erts_tx : 1, - ects_response_type : 2, - eba_response_type : 2, - response_type : 5, - r2r_end_status_to_follow : 1, - service_cbw : 3, - __reserved_g_0039 : 1, - __reserved_g_0040 : 1, - __reserved_g_0017 : 1, - __reserved_g_0018 : 1, - __reserved_g_0030 : 1, - __reserved_g_0031 : 1, - reserved_2c : 11; - uint32_t beamform_masked_user_bitmap_15_0 : 16, - beamform_masked_user_bitmap_31_16 : 16; - uint32_t cbf_segment_request_mask : 8, - cbf_segment_sent_mask : 8, - highest_achieved_data_null_ratio : 5, - use_alt_power_sr : 1, - static_2_pwr_mode_status : 1, - obss_srg_opport_transmit_status : 1, - srp_based_transmit_status : 1, - obss_pd_based_transmit_status : 1, - beamform_masked_user_bitmap_36_32 : 5, - pdg_mpdu_ready : 1; - uint32_t pdg_mpdu_count : 16, - pdg_est_mpdu_tx_count : 16; - uint32_t pdg_overview_length : 24, - txop_duration : 7, - pdg_dropped_mpdu_warning : 1; - uint32_t packet_extension_a_factor : 2, - packet_extension_pe_disambiguity : 1, - packet_extension : 3, - fec_type : 1, - stbc : 1, - num_data_symbols : 16, - ru_size : 4, - reserved_17a : 4; - uint32_t num_ltf_symbols : 3, - ltf_size : 2, - cp_setting : 2, - reserved_18a : 5, - dcm : 1, - ldpc_extra_symbol : 1, - force_extra_symbol : 1, - reserved_18b : 1, - tx_pwr_shared : 8, - tx_pwr_unshared : 8; - uint32_t __reserved_g_0005_active_user_map : 16, - __reserved_g_0005_sent_dummy_tx : 1, - __reserved_g_0005_ftm_frame_sent : 1, - __reserved_g_0067 : 1, - __reserved_g_0068 : 1, - __reserved_g_0037 : 1, - __reserved_g_0038 : 1, - __reserved_g_0069 : 1, - __reserved_g_0070 : 1, - cv_corr_status : 8; - uint32_t current_tx_duration : 16, - reserved_21a : 4, - hw_qos_null_bitmap : 8, - hw_qos_null_setup_missing : 1, - interference : 1, - reserved_21b : 2; - uint32_t reserved_22b : 4, - __reserved_g_0027 : 1, - __reserved_g_0028 : 1, - __reserved_g_0049 : 1, - __reserved_g_0050 : 1, - __reserved_g_0025 : 1, - __reserved_g_0026 : 1, - __reserved_g_0047 : 1, - __reserved_g_0048 : 1, - __reserved_g_0023 : 1, - __reserved_g_0024 : 1, - __reserved_g_0045 : 1, - __reserved_g_0046 : 1, - __reserved_g_0021 : 1, - __reserved_g_0022 : 1, - __reserved_g_0043 : 1, - __reserved_g_0044 : 1, - __reserved_g_0019 : 1, - __reserved_g_0020 : 1, - __reserved_g_0041 : 1, - __reserved_g_0042 : 1, - coex_signaling_status : 8; -#else - uint32_t more_data_received : 1, - sta_response_count : 6, - actual_received_ack_type : 4, - cbf_bw_received : 3, - cbf_bw_received_valid : 1, - global_fes_transmit_result : 4, - global_data_underflow_warning : 1, - __reserved_g_0063 : 1, - __reserved_g_0062 : 1, - __reserved_g_0066 : 1, - __reserved_g_0065 : 1, - __reserved_g_0073 : 1, - __reserved_g_0072 : 1, - __reserved_g_0033 : 1, - __reserved_g_0032 : 1, - __reserved_g_0036 : 1, - __reserved_g_0035 : 1, - __reserved_g_0053 : 1, - __reserved_g_0052 : 1; - uint32_t only_null_delim_sent : 1, - null_delim_inserted_before_mpdus : 1, - fes_in_11ax_trigger_response_config : 1, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - reserved_1a : 5, - qos_null_switch_done_for_eosp : 1, - brp_info_valid : 1, - reserved_after_struct16 : 4; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t reserved_2c : 11, - __reserved_g_0031 : 1, - __reserved_g_0030 : 1, - __reserved_g_0018 : 1, - __reserved_g_0017 : 1, - __reserved_g_0040 : 1, - __reserved_g_0039 : 1, - service_cbw : 3, - r2r_end_status_to_follow : 1, - response_type : 5, - eba_response_type : 2, - ects_response_type : 2, - unsolicited_erts_tx : 1, - terminate___reserved_g_0005_sequence : 1; - uint32_t beamform_masked_user_bitmap_31_16 : 16, - beamform_masked_user_bitmap_15_0 : 16; - uint32_t pdg_mpdu_ready : 1, - beamform_masked_user_bitmap_36_32 : 5, - obss_pd_based_transmit_status : 1, - srp_based_transmit_status : 1, - obss_srg_opport_transmit_status : 1, - static_2_pwr_mode_status : 1, - use_alt_power_sr : 1, - highest_achieved_data_null_ratio : 5, - cbf_segment_sent_mask : 8, - cbf_segment_request_mask : 8; - uint32_t pdg_est_mpdu_tx_count : 16, - pdg_mpdu_count : 16; - uint32_t pdg_dropped_mpdu_warning : 1, - txop_duration : 7, - pdg_overview_length : 24; - uint32_t reserved_17a : 4, - ru_size : 4, - num_data_symbols : 16, - stbc : 1, - fec_type : 1, - packet_extension : 3, - packet_extension_pe_disambiguity : 1, - packet_extension_a_factor : 2; - uint32_t tx_pwr_unshared : 8, - tx_pwr_shared : 8, - reserved_18b : 1, - force_extra_symbol : 1, - ldpc_extra_symbol : 1, - dcm : 1, - reserved_18a : 5, - cp_setting : 2, - ltf_size : 2, - num_ltf_symbols : 3; - uint32_t cv_corr_status : 8, - __reserved_g_0070 : 1, - __reserved_g_0069 : 1, - __reserved_g_0038 : 1, - __reserved_g_0037 : 1, - __reserved_g_0068 : 1, - __reserved_g_0067 : 1, - __reserved_g_0005_ftm_frame_sent : 1, - __reserved_g_0005_sent_dummy_tx : 1, - __reserved_g_0005_active_user_map : 16; - uint32_t reserved_21b : 2, - interference : 1, - hw_qos_null_setup_missing : 1, - hw_qos_null_bitmap : 8, - reserved_21a : 4, - current_tx_duration : 16; - uint32_t coex_signaling_status : 8, - __reserved_g_0042 : 1, - __reserved_g_0041 : 1, - __reserved_g_0020 : 1, - __reserved_g_0019 : 1, - __reserved_g_0044 : 1, - __reserved_g_0043 : 1, - __reserved_g_0022 : 1, - __reserved_g_0021 : 1, - __reserved_g_0046 : 1, - __reserved_g_0045 : 1, - __reserved_g_0024 : 1, - __reserved_g_0023 : 1, - __reserved_g_0048 : 1, - __reserved_g_0047 : 1, - __reserved_g_0026 : 1, - __reserved_g_0025 : 1, - __reserved_g_0050 : 1, - __reserved_g_0049 : 1, - __reserved_g_0028 : 1, - __reserved_g_0027 : 1, - reserved_22b : 4; -#endif -}; - -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 -#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000001000 - -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 -#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x000000000001e000 - -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x0000000000020000 - -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 -#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x00000000001c0000 - -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 -#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x0000000001e00000 - -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 -#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x000000007e000000 - -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_LSB 31 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MSB 31 -#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 48 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 51 -#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f000000000000 - -#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 52 -#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 52 -#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x0010000000000000 - -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_LSB 53 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MSB 53 -#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MASK 0x0020000000000000 - -#define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_RESERVED_1A_LSB 54 -#define TX_FES_STATUS_END_RESERVED_1A_MSB 58 -#define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07c0000000000000 - -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 59 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 59 -#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x0800000000000000 - -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 60 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 60 -#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x1000000000000000 - -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 61 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 61 -#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x2000000000000000 - -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 62 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 62 -#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x4000000000000000 - -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 63 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 63 -#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x8000000000000000 - -#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_LSB 1 -#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_MSB 1 -#define TX_FES_STATUS_END_UNSOLICITED_ERTS_TX_MASK 0x0000000000000002 - -#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_LSB 2 -#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_MSB 3 -#define TX_FES_STATUS_END_ECTS_RESPONSE_TYPE_MASK 0x000000000000000c - -#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_LSB 4 -#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_MSB 5 -#define TX_FES_STATUS_END_EBA_RESPONSE_TYPE_MASK 0x0000000000000030 - -#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 6 -#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 10 -#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x00000000000007c0 - -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 11 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 11 -#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000000000800 - -#define TX_FES_STATUS_END_SERVICE_CBW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_SERVICE_CBW_LSB 12 -#define TX_FES_STATUS_END_SERVICE_CBW_MSB 14 -#define TX_FES_STATUS_END_SERVICE_CBW_MASK 0x0000000000007000 - -#define TX_FES_STATUS_END_RESERVED_2C_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_RESERVED_2C_LSB 21 -#define TX_FES_STATUS_END_RESERVED_2C_MSB 31 -#define TX_FES_STATUS_END_RESERVED_2C_MASK 0x00000000ffe00000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 32 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 47 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 48 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 63 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0xffff000000000000 - -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 0 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 7 -#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x00000000000000ff - -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 8 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 15 -#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x000000000000ff00 - -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 16 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 20 -#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x00000000001f0000 - -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 21 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 21 -#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x0000000000200000 - -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 22 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 22 -#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x0000000000400000 - -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 23 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 23 -#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000000000800000 - -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 24 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 24 -#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000000001000000 - -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 25 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 25 -#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000000002000000 - -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 26 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 30 -#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x000000007c000000 - -#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 31 -#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 31 -#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 32 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 47 -#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 48 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 63 -#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0xffff000000000000 - -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 0 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 23 -#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x0000000000ffffff - -#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_TXOP_DURATION_LSB 24 -#define TX_FES_STATUS_END_TXOP_DURATION_MSB 30 -#define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x000000007f000000 - -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 31 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 31 -#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 32 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 33 -#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000300000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 34 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 34 -#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000400000000 - -#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 35 -#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 37 -#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x0000003800000000 - -#define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_FEC_TYPE_LSB 38 -#define TX_FES_STATUS_END_FEC_TYPE_MSB 38 -#define TX_FES_STATUS_END_FEC_TYPE_MASK 0x0000004000000000 - -#define TX_FES_STATUS_END_STBC_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_STBC_LSB 39 -#define TX_FES_STATUS_END_STBC_MSB 39 -#define TX_FES_STATUS_END_STBC_MASK 0x0000008000000000 - -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 40 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 55 -#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x00ffff0000000000 - -#define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_RU_SIZE_LSB 56 -#define TX_FES_STATUS_END_RU_SIZE_MSB 59 -#define TX_FES_STATUS_END_RU_SIZE_MASK 0x0f00000000000000 - -#define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000000000000018 -#define TX_FES_STATUS_END_RESERVED_17A_LSB 60 -#define TX_FES_STATUS_END_RESERVED_17A_MSB 63 -#define TX_FES_STATUS_END_RESERVED_17A_MASK 0xf000000000000000 - -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 0 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 2 -#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x0000000000000007 - -#define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_LTF_SIZE_LSB 3 -#define TX_FES_STATUS_END_LTF_SIZE_MSB 4 -#define TX_FES_STATUS_END_LTF_SIZE_MASK 0x0000000000000018 - -#define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_CP_SETTING_LSB 5 -#define TX_FES_STATUS_END_CP_SETTING_MSB 6 -#define TX_FES_STATUS_END_CP_SETTING_MASK 0x0000000000000060 - -#define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_RESERVED_18A_LSB 7 -#define TX_FES_STATUS_END_RESERVED_18A_MSB 11 -#define TX_FES_STATUS_END_RESERVED_18A_MASK 0x0000000000000f80 - -#define TX_FES_STATUS_END_DCM_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_DCM_LSB 12 -#define TX_FES_STATUS_END_DCM_MSB 12 -#define TX_FES_STATUS_END_DCM_MASK 0x0000000000001000 - -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 13 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 13 -#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x0000000000002000 - -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 14 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 14 -#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x0000000000004000 - -#define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_RESERVED_18B_LSB 15 -#define TX_FES_STATUS_END_RESERVED_18B_MSB 15 -#define TX_FES_STATUS_END_RESERVED_18B_MASK 0x0000000000008000 - -#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 16 -#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 23 -#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x0000000000ff0000 - -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 24 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 31 -#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0x00000000ff000000 - -#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x0000000000000020 -#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 56 -#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 63 -#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0xff00000000000000 - -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 0 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 15 -#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x000000000000ffff - -#define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_21A_LSB 16 -#define TX_FES_STATUS_END_RESERVED_21A_MSB 19 -#define TX_FES_STATUS_END_RESERVED_21A_MASK 0x00000000000f0000 - -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_LSB 20 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MSB 27 -#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MASK 0x000000000ff00000 - -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_LSB 28 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MSB 28 -#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MASK 0x0000000010000000 - -#define TX_FES_STATUS_END_INTERFERENCE_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_INTERFERENCE_LSB 29 -#define TX_FES_STATUS_END_INTERFERENCE_MSB 29 -#define TX_FES_STATUS_END_INTERFERENCE_MASK 0x0000000020000000 - -#define TX_FES_STATUS_END_RESERVED_21B_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_21B_LSB 30 -#define TX_FES_STATUS_END_RESERVED_21B_MSB 31 -#define TX_FES_STATUS_END_RESERVED_21B_MASK 0x00000000c0000000 - -#define TX_FES_STATUS_END_RESERVED_22B_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_RESERVED_22B_LSB 32 -#define TX_FES_STATUS_END_RESERVED_22B_MSB 35 -#define TX_FES_STATUS_END_RESERVED_22B_MASK 0x0000000f00000000 - -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_OFFSET 0x0000000000000028 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_LSB 56 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MSB 63 -#define TX_FES_STATUS_END_COEX_SIGNALING_STATUS_MASK 0xff00000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_prot.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_prot.h deleted file mode 100644 index 702cc1add940..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_prot.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_PROT_H_ -#define _TX_FES_STATUS_PROT_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 4 - -#define NUM_OF_QWORDS_TX_FES_STATUS_PROT 2 - -struct tx_fes_status_prot { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t success : 1, - phytx_pkt_end_info_valid : 1, - phytx_abort_request_info_valid : 1, - reserved_0 : 19, - pkt_type : 4, - dot11ax_su_extended : 1, - rate_mcs : 5; - uint32_t frame_type : 2, - frame_subtype : 4, - rx_pwr_mgmt : 1, - status : 1, - duration_field : 16, - reserved_1a : 2, - agc_cbw : 3, - service_cbw : 3; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t reserved_2a : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t rate_mcs : 5, - dot11ax_su_extended : 1, - pkt_type : 4, - reserved_0 : 19, - phytx_abort_request_info_valid : 1, - phytx_pkt_end_info_valid : 1, - success : 1; - uint32_t service_cbw : 3, - agc_cbw : 3, - reserved_1a : 2, - duration_field : 16, - status : 1, - rx_pwr_mgmt : 1, - frame_subtype : 4, - frame_type : 2; - uint32_t reserved_2a : 16; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_SUCCESS_LSB 0 -#define TX_FES_STATUS_PROT_SUCCESS_MSB 0 -#define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001 - -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 -#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004 - -#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 -#define TX_FES_STATUS_PROT_RESERVED_0_MSB 21 -#define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000003ffff8 - -#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_PKT_TYPE_LSB 22 -#define TX_FES_STATUS_PROT_PKT_TYPE_MSB 25 -#define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000003c00000 - -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 26 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 26 -#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000004000000 - -#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RATE_MCS_LSB 27 -#define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 -#define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f8000000 - -#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32 -#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33 -#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000 - -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37 -#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000 - -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38 -#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000 - -#define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_STATUS_LSB 39 -#define TX_FES_STATUS_PROT_STATUS_MSB 39 -#define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000 - -#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40 -#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55 -#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000 - -#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56 -#define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57 -#define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000 - -#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_AGC_CBW_LSB 58 -#define TX_FES_STATUS_PROT_AGC_CBW_MSB 60 -#define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000 - -#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61 -#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63 -#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00000000000000ff - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x0000000000003f00 - -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 -#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x000000000000c000 - -#define TX_FES_STATUS_PROT_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_RESERVED_2A_LSB 16 -#define TX_FES_STATUS_PROT_RESERVED_2A_MSB 31 -#define TX_FES_STATUS_PROT_RESERVED_2A_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_PROT_TLV64_PADDING_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_PROT_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_PROT_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_PROT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start.h deleted file mode 100644 index bc8e06ec59fb..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_H_ -#define _TX_FES_STATUS_START_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START 4 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START 2 - -struct tx_fes_status_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t schedule_id : 32; - uint32_t reserved_1a : 8, - transmit_start_reason : 3, - disabled_user_bitmap_36_32 : 5, - schedule_cmd_ring_id : 5, - fes_control_mode : 2, - schedule_try : 4, - medium_prot_type : 3, - reserved_1b : 2; - uint32_t optimal_bw_try_count : 4, - number_of_users : 7, - coex_nack_count : 5, - cca_ed0 : 16; - uint32_t disabled_user_bitmap_31_0 : 32; -#else - uint32_t schedule_id : 32; - uint32_t reserved_1b : 2, - medium_prot_type : 3, - schedule_try : 4, - fes_control_mode : 2, - schedule_cmd_ring_id : 5, - disabled_user_bitmap_36_32 : 5, - transmit_start_reason : 3, - reserved_1a : 8; - uint32_t cca_ed0 : 16, - coex_nack_count : 5, - number_of_users : 7, - optimal_bw_try_count : 4; - uint32_t disabled_user_bitmap_31_0 : 32; -#endif -}; - -#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_ID_LSB 0 -#define TX_FES_STATUS_START_SCHEDULE_ID_MSB 31 -#define TX_FES_STATUS_START_SCHEDULE_ID_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_RESERVED_1A_LSB 32 -#define TX_FES_STATUS_START_RESERVED_1A_MSB 39 -#define TX_FES_STATUS_START_RESERVED_1A_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB 40 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB 42 -#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK 0x0000070000000000 - -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB 43 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB 47 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK 0x0000f80000000000 - -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB 48 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB 52 -#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 - -#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB 53 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB 54 -#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK 0x0060000000000000 - -#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB 55 -#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB 58 -#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK 0x0780000000000000 - -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB 59 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB 61 -#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK 0x3800000000000000 - -#define TX_FES_STATUS_START_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_RESERVED_1B_LSB 62 -#define TX_FES_STATUS_START_RESERVED_1B_MSB 63 -#define TX_FES_STATUS_START_RESERVED_1B_MASK 0xc000000000000000 - -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB 0 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB 3 -#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK 0x000000000000000f - -#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB 4 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB 10 -#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK 0x00000000000007f0 - -#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB 11 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB 15 -#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK 0x000000000000f800 - -#define TX_FES_STATUS_START_CCA_ED0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_CCA_ED0_LSB 16 -#define TX_FES_STATUS_START_CCA_ED0_MSB 31 -#define TX_FES_STATUS_START_CCA_ED0_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB 32 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB 63 -#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start_ppdu.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start_ppdu.h deleted file mode 100644 index a87b3b0a0ccc..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start_ppdu.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_PPDU_H_ -#define _TX_FES_STATUS_START_PPDU_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START_PPDU 3 - -struct tx_fes_status_start_ppdu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t ppdu_timestamp_lower_32 : 32; - uint32_t ppdu_timestamp_upper_32 : 32; - uint32_t subband_mask : 16, - ndp_frame : 3, - reserved_2b : 1, - coex_based_tx_bw : 3, - coex_based_ant_mask : 8, - reserved_2c : 1; - uint32_t coex_based_tx_pwr_shared_ant : 8, - coex_based_tx_pwr_ant : 8, - concurrent_bt_tx : 1, - concurrent_wlan_tx : 1, - concurrent_wan_tx : 1, - concurrent_wan_rx : 1, - coex_pwr_reduction_bt : 1, - coex_pwr_reduction_wlan : 1, - coex_pwr_reduction_wan : 1, - coex_result_alt_based : 1, - request_packet_bw : 3, - response_type : 5; - uint32_t concurrent_rx_activity_tracker1 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - coex_pwr_reduction_wan_ratid1 : 1, - reserved_4a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t ppdu_timestamp_lower_32 : 32; - uint32_t ppdu_timestamp_upper_32 : 32; - uint32_t reserved_2c : 1, - coex_based_ant_mask : 8, - coex_based_tx_bw : 3, - reserved_2b : 1, - ndp_frame : 3, - subband_mask : 16; - uint32_t response_type : 5, - request_packet_bw : 3, - coex_result_alt_based : 1, - coex_pwr_reduction_wan : 1, - coex_pwr_reduction_wlan : 1, - coex_pwr_reduction_bt : 1, - concurrent_wan_rx : 1, - concurrent_wan_tx : 1, - concurrent_wlan_tx : 1, - concurrent_bt_tx : 1, - coex_based_tx_pwr_ant : 8, - coex_based_tx_pwr_shared_ant : 8; - uint32_t reserved_4a : 18, - coex_pwr_reduction_wan_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker1 : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB 0 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB 31 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB 32 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB 63 -#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB 0 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB 15 -#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK 0x000000000000ffff - -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB 16 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB 18 -#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK 0x0000000000070000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB 19 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB 19 -#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK 0x0000000000080000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB 20 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB 22 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK 0x0000000000700000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB 23 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB 30 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK 0x0000000080000000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB 32 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB 39 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB 40 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB 47 -#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK 0x0000ff0000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB 48 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB 48 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK 0x0001000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB 49 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB 49 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB 50 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB 50 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK 0x0004000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB 51 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB 51 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK 0x0008000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB 52 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB 52 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB 53 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB 53 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB 54 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB 54 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 - -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB 55 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB 55 -#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK 0x0080000000000000 - -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB 56 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB 58 -#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK 0x0700000000000000 - -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB 59 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB 63 -#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK 0xf800000000000000 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB 0 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB 0 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK 0x0000000000000001 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB 1 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB 1 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK 0x0000000000000002 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB 2 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB 2 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK 0x0000000000000004 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB 3 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB 3 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK 0x0000000000000008 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB 4 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB 4 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK 0x0000000000000010 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB 5 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB 5 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK 0x0000000000000020 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB 6 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB 6 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK 0x0000000000000040 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB 7 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB 7 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK 0x0000000000000080 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB 8 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB 8 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK 0x0000000000000100 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB 9 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB 9 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK 0x0000000000000200 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB 10 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB 10 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK 0x0000000000000400 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_LSB 11 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MSB 11 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_RATID1_MASK 0x0000000000000800 - -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_LSB 12 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MSB 12 -#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_RATID1_MASK 0x0000000000001000 - -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_LSB 13 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MSB 13 -#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_RATID1_MASK 0x0000000000002000 - -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_LSB 14 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MSB 31 -#define TX_FES_STATUS_START_PPDU_RESERVED_4A_MASK 0x00000000ffffc000 - -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_START_PPDU_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start_prot.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start_prot.h deleted file mode 100644 index aca9ac5eb28b..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_start_prot.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_START_PROT_H_ -#define _TX_FES_STATUS_START_PROT_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_START_PROT 3 - -struct tx_fes_status_start_prot { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t prot_timestamp_lower_32 : 32; - uint32_t prot_timestamp_upper_32 : 32; - uint32_t subband_mask : 16, - reserved_2b : 4, - prot_coex_based_tx_bw : 3, - prot_coex_based_ant_mask : 8, - prot_coex_result_alt_based : 1; - uint32_t prot_coex_tx_pwr_shared_ant : 8, - prot_coex_tx_pwr_ant : 8, - prot_concurrent_bt_tx : 1, - prot_concurrent_wlan_tx : 1, - prot_concurrent_wan_tx : 1, - prot_concurrent_wan_rx : 1, - prot_coex_pwr_reduction_bt : 1, - prot_coex_pwr_reduction_wlan : 1, - prot_coex_pwr_reduction_wan : 1, - prot_request_packet_bw : 3, - response_type : 5, - reserved_3a : 1; - uint32_t concurrent_rx_activity_tracker1 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - coex_pwr_reduction_wan_ratid1 : 1, - reserved_4a : 18; - uint32_t tlv64_padding : 32; -#else - uint32_t prot_timestamp_lower_32 : 32; - uint32_t prot_timestamp_upper_32 : 32; - uint32_t prot_coex_result_alt_based : 1, - prot_coex_based_ant_mask : 8, - prot_coex_based_tx_bw : 3, - reserved_2b : 4, - subband_mask : 16; - uint32_t reserved_3a : 1, - response_type : 5, - prot_request_packet_bw : 3, - prot_coex_pwr_reduction_wan : 1, - prot_coex_pwr_reduction_wlan : 1, - prot_coex_pwr_reduction_bt : 1, - prot_concurrent_wan_rx : 1, - prot_concurrent_wan_tx : 1, - prot_concurrent_wlan_tx : 1, - prot_concurrent_bt_tx : 1, - prot_coex_tx_pwr_ant : 8, - prot_coex_tx_pwr_shared_ant : 8; - uint32_t reserved_4a : 18, - coex_pwr_reduction_wan_ratid1 : 1, - concurrent_wan_rx_ratid1 : 1, - concurrent_wan_tx_ratid1 : 1, - concurrent_rx_activity_tracker6 : 1, - concurrent_tx_activity_tracker6 : 1, - concurrent_rx_activity_tracker5 : 1, - concurrent_tx_activity_tracker5 : 1, - concurrent_rx_activity_tracker4 : 1, - concurrent_tx_activity_tracker4 : 1, - concurrent_rx_activity_tracker3 : 1, - concurrent_tx_activity_tracker3 : 1, - concurrent_rx_activity_tracker2 : 1, - concurrent_tx_activity_tracker2 : 1, - concurrent_rx_activity_tracker1 : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB 0 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB 31 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff - -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB 32 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB 63 -#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 - -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB 0 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB 15 -#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK 0x000000000000ffff - -#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB 16 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB 19 -#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK 0x00000000000f0000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB 20 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB 22 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK 0x0000000000700000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB 23 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB 30 -#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB 31 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB 31 -#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK 0x0000000080000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB 32 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB 39 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB 40 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB 47 -#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK 0x0000ff0000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB 48 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB 48 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK 0x0001000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB 49 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB 49 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB 50 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB 50 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK 0x0004000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB 51 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB 51 -#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK 0x0008000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB 52 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB 52 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB 53 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB 53 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB 54 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB 54 -#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 - -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB 55 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB 57 -#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK 0x0380000000000000 - -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB 58 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB 62 -#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK 0x7c00000000000000 - -#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB 63 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB 63 -#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK 0x8000000000000000 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_LSB 0 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MSB 0 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER1_MASK 0x0000000000000001 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_LSB 1 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MSB 1 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER2_MASK 0x0000000000000002 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_LSB 2 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MSB 2 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER2_MASK 0x0000000000000004 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_LSB 3 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MSB 3 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER3_MASK 0x0000000000000008 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_LSB 4 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MSB 4 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER3_MASK 0x0000000000000010 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_LSB 5 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MSB 5 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER4_MASK 0x0000000000000020 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_LSB 6 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MSB 6 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER4_MASK 0x0000000000000040 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_LSB 7 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MSB 7 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER5_MASK 0x0000000000000080 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_LSB 8 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MSB 8 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER5_MASK 0x0000000000000100 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_LSB 9 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MSB 9 -#define TX_FES_STATUS_START_PROT_CONCURRENT_TX_ACTIVITY_TRACKER6_MASK 0x0000000000000200 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_LSB 10 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MSB 10 -#define TX_FES_STATUS_START_PROT_CONCURRENT_RX_ACTIVITY_TRACKER6_MASK 0x0000000000000400 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_LSB 11 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MSB 11 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_TX_RATID1_MASK 0x0000000000000800 - -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_LSB 12 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MSB 12 -#define TX_FES_STATUS_START_PROT_CONCURRENT_WAN_RX_RATID1_MASK 0x0000000000001000 - -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_LSB 13 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MSB 13 -#define TX_FES_STATUS_START_PROT_COEX_PWR_REDUCTION_WAN_RATID1_MASK 0x0000000000002000 - -#define TX_FES_STATUS_START_PROT_RESERVED_4A_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_LSB 14 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_MSB 31 -#define TX_FES_STATUS_START_PROT_RESERVED_4A_MASK 0x00000000ffffc000 - -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_LSB 32 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MSB 63 -#define TX_FES_STATUS_START_PROT_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_user_ppdu.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_user_ppdu.h deleted file mode 100644 index dad9a040ff46..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_user_ppdu.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_USER_PPDU_H_ -#define _TX_FES_STATUS_USER_PPDU_H_ - -#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 - -#define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3 - -struct tx_fes_status_user_ppdu { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t underflow_mpdu_count : 9, - data_underflow_warning : 2, - bw_drop_underflow_warning : 1, - qc_eosp_setting : 1, - mpdu_tx_count : 11, - user_blocked : 1, - pre_trig_response_delim_count : 7; - uint32_t underflow_byte_count : 16, - coex_abort_mpdu_count_valid : 1, - coex_abort_mpdu_count : 9, - transmitted_tid : 4, - txdma_dropped_mpdu_warning : 1, - cv_corr_user_valid_in_phy : 1; - uint32_t duration : 16, - num_eof_delim_added : 16; - uint32_t psdu_octet : 24, - qos_buf_state : 8; - uint32_t num_null_delim_added : 22, - fc_more_data_setting : 1, - fc_pwr_mgt_setting : 1, - nss : 3, - mcs : 5; - uint32_t ht_control : 32; -#else - uint32_t pre_trig_response_delim_count : 7, - user_blocked : 1, - mpdu_tx_count : 11, - qc_eosp_setting : 1, - bw_drop_underflow_warning : 1, - data_underflow_warning : 2, - underflow_mpdu_count : 9; - uint32_t cv_corr_user_valid_in_phy : 1, - txdma_dropped_mpdu_warning : 1, - transmitted_tid : 4, - coex_abort_mpdu_count : 9, - coex_abort_mpdu_count_valid : 1, - underflow_byte_count : 16; - uint32_t num_eof_delim_added : 16, - duration : 16; - uint32_t qos_buf_state : 8, - psdu_octet : 24; - uint32_t mcs : 5, - nss : 3, - fc_pwr_mgt_setting : 1, - fc_more_data_setting : 1, - num_null_delim_added : 22; - uint32_t ht_control : 32; -#endif -}; - -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff - -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 -#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 - -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 -#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x0000000000000800 - -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 -#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x0000000000001000 - -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 13 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 -#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x0000000000ffe000 - -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 -#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x0000000001000000 - -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 -#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0x00000000fe000000 - -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 32 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 47 -#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff00000000 - -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 48 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 48 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x0001000000000000 - -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 49 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 57 -#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe000000000000 - -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 58 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 61 -#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c00000000000000 - -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 62 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 62 -#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x4000000000000000 - -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 63 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 63 -#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x8000000000000000 - -#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 -#define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 -#define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x000000000000ffff - -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 -#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0x00000000ffff0000 - -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 32 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 55 -#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff00000000 - -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000000000008 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 56 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 63 -#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff00000000000000 - -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 -#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x00000000003fffff - -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 22 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 22 -#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x0000000000400000 - -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 23 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 23 -#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x0000000000800000 - -#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_NSS_LSB 24 -#define TX_FES_STATUS_USER_PPDU_NSS_MSB 26 -#define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x0000000007000000 - -#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_MCS_LSB 27 -#define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 -#define TX_FES_STATUS_USER_PPDU_MCS_MASK 0x00000000f8000000 - -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x0000000000000010 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 32 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 63 -#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_user_response.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_user_response.h deleted file mode 100644 index dea7df35887f..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_fes_status_user_response.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FES_STATUS_USER_RESPONSE_H_ -#define _TX_FES_STATUS_USER_RESPONSE_H_ - -#include "phytx_abort_request_info.h" -#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2 - -#define NUM_OF_QWORDS_TX_FES_STATUS_USER_RESPONSE 1 - -struct tx_fes_status_user_response { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t fes_transmit_result : 4, - reserved_0 : 23, - overwritten_blackout_window_bitmap : 4, - mic_overwritten : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; - uint16_t pre_padding_fcs_overwritten : 1, - reserved_after_struct16 : 15; -#else - uint32_t mic_overwritten : 1, - overwritten_blackout_window_bitmap : 4, - reserved_0 : 23, - fes_transmit_result : 4; - uint32_t reserved_after_struct16 : 15, - pre_padding_fcs_overwritten : 1; - struct phytx_abort_request_info phytx_abort_request_info_details; -#endif -}; - -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB 0 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB 3 -#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK 0x000000000000000f - -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB 4 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB 26 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK 0x0000000007fffff0 - -#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_LSB 27 -#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MSB 30 -#define TX_FES_STATUS_USER_RESPONSE_OVERWRITTEN_BLACKOUT_WINDOW_BITMAP_MASK 0x0000000078000000 - -#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_LSB 31 -#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_MSB 31 -#define TX_FES_STATUS_USER_RESPONSE_MIC_OVERWRITTEN_MASK 0x0000000080000000 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 - -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 -#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 - -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_LSB 48 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MSB 48 -#define TX_FES_STATUS_USER_RESPONSE_PRE_PADDING_FCS_OVERWRITTEN_MASK 0x0001000000000000 - -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB 49 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB 63 -#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK 0xfffe000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_flush_req.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_flush_req.h deleted file mode 100644 index af502ec619eb..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_flush_req.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_FLUSH_REQ_H_ -#define _TX_FLUSH_REQ_H_ - -#define NUM_OF_DWORDS_TX_FLUSH_REQ 2 - -#define NUM_OF_QWORDS_TX_FLUSH_REQ 1 - -struct tx_flush_req { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t flush_req_reason : 8, - phytx_abort_reason : 8, - flush_req_user_number_or_link_id : 6, - mlo_abort_reason : 5, - reserved_0a : 5; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 5, - mlo_abort_reason : 5, - flush_req_user_number_or_link_id : 6, - phytx_abort_reason : 8, - flush_req_reason : 8; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7 -#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x00000000000000ff - -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15 -#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x000000000000ff00 - -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21 -#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x00000000003f0000 - -#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26 -#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x0000000007c00000 - -#define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_RESERVED_0A_LSB 27 -#define TX_FLUSH_REQ_RESERVED_0A_MSB 31 -#define TX_FLUSH_REQ_RESERVED_0A_MASK 0x00000000f8000000 - -#define TX_FLUSH_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 -#define TX_FLUSH_REQ_TLV64_PADDING_LSB 32 -#define TX_FLUSH_REQ_TLV64_PADDING_MSB 63 -#define TX_FLUSH_REQ_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_mpdu_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_mpdu_start.h deleted file mode 100644 index 1a0c370d2963..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_mpdu_start.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MPDU_START_H_ -#define _TX_MPDU_START_H_ - -#define NUM_OF_DWORDS_TX_MPDU_START 10 - -#define NUM_OF_QWORDS_TX_MPDU_START 5 - -struct tx_mpdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mpdu_length : 14, - frame_not_from_tqm : 1, - vht_control_present : 1, - mpdu_header_length : 8, - retry_count : 7, - wds : 1; - uint32_t pn_31_0 : 32; - uint32_t pn_47_32 : 16, - mpdu_sequence_number : 12, - raw_already_encrypted : 1, - frame_type : 2, - txdma_dropped_mpdu_warning : 1; - uint32_t iv_byte_0 : 8, - iv_byte_1 : 8, - iv_byte_2 : 8, - iv_byte_3 : 8; - uint32_t iv_byte_4 : 8, - iv_byte_5 : 8, - iv_byte_6 : 8, - iv_byte_7 : 8; - uint32_t iv_byte_8 : 8, - iv_byte_9 : 8, - iv_byte_10 : 8, - iv_byte_11 : 8; - uint32_t iv_byte_12 : 8, - iv_byte_13 : 8, - iv_byte_14 : 8, - iv_byte_15 : 8; - uint32_t iv_byte_16 : 8, - iv_byte_17 : 8, - iv_len : 5, - icv_len : 5, - vht_control_offset : 6; - uint32_t mpdu_type : 1, - transmit_bw_restriction : 1, - allowed_transmit_bw : 4, - tx_notify_frame : 3, - frame_subtype : 4, - reserved_8a : 19; - uint32_t tlv64_padding : 32; -#else - uint32_t wds : 1, - retry_count : 7, - mpdu_header_length : 8, - vht_control_present : 1, - frame_not_from_tqm : 1, - mpdu_length : 14; - uint32_t pn_31_0 : 32; - uint32_t txdma_dropped_mpdu_warning : 1, - frame_type : 2, - raw_already_encrypted : 1, - mpdu_sequence_number : 12, - pn_47_32 : 16; - uint32_t iv_byte_3 : 8, - iv_byte_2 : 8, - iv_byte_1 : 8, - iv_byte_0 : 8; - uint32_t iv_byte_7 : 8, - iv_byte_6 : 8, - iv_byte_5 : 8, - iv_byte_4 : 8; - uint32_t iv_byte_11 : 8, - iv_byte_10 : 8, - iv_byte_9 : 8, - iv_byte_8 : 8; - uint32_t iv_byte_15 : 8, - iv_byte_14 : 8, - iv_byte_13 : 8, - iv_byte_12 : 8; - uint32_t vht_control_offset : 6, - icv_len : 5, - iv_len : 5, - iv_byte_17 : 8, - iv_byte_16 : 8; - uint32_t reserved_8a : 19, - frame_subtype : 4, - tx_notify_frame : 3, - allowed_transmit_bw : 4, - transmit_bw_restriction : 1, - mpdu_type : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x0000000000000000 -#define TX_MPDU_START_MPDU_LENGTH_LSB 0 -#define TX_MPDU_START_MPDU_LENGTH_MSB 13 -#define TX_MPDU_START_MPDU_LENGTH_MASK 0x0000000000003fff - -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x0000000000000000 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 -#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x0000000000004000 - -#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x0000000000000000 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 -#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x0000000000008000 - -#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x0000000000000000 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 -#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_RETRY_COUNT_OFFSET 0x0000000000000000 -#define TX_MPDU_START_RETRY_COUNT_LSB 24 -#define TX_MPDU_START_RETRY_COUNT_MSB 30 -#define TX_MPDU_START_RETRY_COUNT_MASK 0x000000007f000000 - -#define TX_MPDU_START_WDS_OFFSET 0x0000000000000000 -#define TX_MPDU_START_WDS_LSB 31 -#define TX_MPDU_START_WDS_MSB 31 -#define TX_MPDU_START_WDS_MASK 0x0000000080000000 - -#define TX_MPDU_START_PN_31_0_OFFSET 0x0000000000000000 -#define TX_MPDU_START_PN_31_0_LSB 32 -#define TX_MPDU_START_PN_31_0_MSB 63 -#define TX_MPDU_START_PN_31_0_MASK 0xffffffff00000000 - -#define TX_MPDU_START_PN_47_32_OFFSET 0x0000000000000008 -#define TX_MPDU_START_PN_47_32_LSB 0 -#define TX_MPDU_START_PN_47_32_MSB 15 -#define TX_MPDU_START_PN_47_32_MASK 0x000000000000ffff - -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000008 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 -#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x000000000fff0000 - -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x0000000000000008 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 -#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x0000000010000000 - -#define TX_MPDU_START_FRAME_TYPE_OFFSET 0x0000000000000008 -#define TX_MPDU_START_FRAME_TYPE_LSB 29 -#define TX_MPDU_START_FRAME_TYPE_MSB 30 -#define TX_MPDU_START_FRAME_TYPE_MASK 0x0000000060000000 - -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000008 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 -#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 - -#define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_0_LSB 32 -#define TX_MPDU_START_IV_BYTE_0_MSB 39 -#define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_1_LSB 40 -#define TX_MPDU_START_IV_BYTE_1_MSB 47 -#define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_2_LSB 48 -#define TX_MPDU_START_IV_BYTE_2_MSB 55 -#define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff000000000000 - -#define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000000000008 -#define TX_MPDU_START_IV_BYTE_3_LSB 56 -#define TX_MPDU_START_IV_BYTE_3_MSB 63 -#define TX_MPDU_START_IV_BYTE_3_MASK 0xff00000000000000 - -#define TX_MPDU_START_IV_BYTE_4_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_4_LSB 0 -#define TX_MPDU_START_IV_BYTE_4_MSB 7 -#define TX_MPDU_START_IV_BYTE_4_MASK 0x00000000000000ff - -#define TX_MPDU_START_IV_BYTE_5_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_5_LSB 8 -#define TX_MPDU_START_IV_BYTE_5_MSB 15 -#define TX_MPDU_START_IV_BYTE_5_MASK 0x000000000000ff00 - -#define TX_MPDU_START_IV_BYTE_6_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_6_LSB 16 -#define TX_MPDU_START_IV_BYTE_6_MSB 23 -#define TX_MPDU_START_IV_BYTE_6_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_IV_BYTE_7_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_7_LSB 24 -#define TX_MPDU_START_IV_BYTE_7_MSB 31 -#define TX_MPDU_START_IV_BYTE_7_MASK 0x00000000ff000000 - -#define TX_MPDU_START_IV_BYTE_8_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_8_LSB 32 -#define TX_MPDU_START_IV_BYTE_8_MSB 39 -#define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_9_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_9_LSB 40 -#define TX_MPDU_START_IV_BYTE_9_MSB 47 -#define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_BYTE_10_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_10_LSB 48 -#define TX_MPDU_START_IV_BYTE_10_MSB 55 -#define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff000000000000 - -#define TX_MPDU_START_IV_BYTE_11_OFFSET 0x0000000000000010 -#define TX_MPDU_START_IV_BYTE_11_LSB 56 -#define TX_MPDU_START_IV_BYTE_11_MSB 63 -#define TX_MPDU_START_IV_BYTE_11_MASK 0xff00000000000000 - -#define TX_MPDU_START_IV_BYTE_12_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_12_LSB 0 -#define TX_MPDU_START_IV_BYTE_12_MSB 7 -#define TX_MPDU_START_IV_BYTE_12_MASK 0x00000000000000ff - -#define TX_MPDU_START_IV_BYTE_13_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_13_LSB 8 -#define TX_MPDU_START_IV_BYTE_13_MSB 15 -#define TX_MPDU_START_IV_BYTE_13_MASK 0x000000000000ff00 - -#define TX_MPDU_START_IV_BYTE_14_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_14_LSB 16 -#define TX_MPDU_START_IV_BYTE_14_MSB 23 -#define TX_MPDU_START_IV_BYTE_14_MASK 0x0000000000ff0000 - -#define TX_MPDU_START_IV_BYTE_15_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_15_LSB 24 -#define TX_MPDU_START_IV_BYTE_15_MSB 31 -#define TX_MPDU_START_IV_BYTE_15_MASK 0x00000000ff000000 - -#define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_16_LSB 32 -#define TX_MPDU_START_IV_BYTE_16_MSB 39 -#define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff00000000 - -#define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_BYTE_17_LSB 40 -#define TX_MPDU_START_IV_BYTE_17_MSB 47 -#define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff0000000000 - -#define TX_MPDU_START_IV_LEN_OFFSET 0x0000000000000018 -#define TX_MPDU_START_IV_LEN_LSB 48 -#define TX_MPDU_START_IV_LEN_MSB 52 -#define TX_MPDU_START_IV_LEN_MASK 0x001f000000000000 - -#define TX_MPDU_START_ICV_LEN_OFFSET 0x0000000000000018 -#define TX_MPDU_START_ICV_LEN_LSB 53 -#define TX_MPDU_START_ICV_LEN_MSB 57 -#define TX_MPDU_START_ICV_LEN_MASK 0x03e0000000000000 - -#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000000000000018 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 58 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 63 -#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc00000000000000 - -#define TX_MPDU_START_MPDU_TYPE_OFFSET 0x0000000000000020 -#define TX_MPDU_START_MPDU_TYPE_LSB 0 -#define TX_MPDU_START_MPDU_TYPE_MSB 0 -#define TX_MPDU_START_MPDU_TYPE_MASK 0x0000000000000001 - -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 -#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x0000000000000002 - -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x0000000000000020 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 -#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x000000000000003c - -#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 -#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 -#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x00000000000001c0 - -#define TX_MPDU_START_FRAME_SUBTYPE_OFFSET 0x0000000000000020 -#define TX_MPDU_START_FRAME_SUBTYPE_LSB 9 -#define TX_MPDU_START_FRAME_SUBTYPE_MSB 12 -#define TX_MPDU_START_FRAME_SUBTYPE_MASK 0x0000000000001e00 - -#define TX_MPDU_START_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_MPDU_START_RESERVED_8A_LSB 13 -#define TX_MPDU_START_RESERVED_8A_MSB 31 -#define TX_MPDU_START_RESERVED_8A_MASK 0x00000000ffffe000 - -#define TX_MPDU_START_TLV64_PADDING_OFFSET 0x0000000000000020 -#define TX_MPDU_START_TLV64_PADDING_LSB 32 -#define TX_MPDU_START_TLV64_PADDING_MSB 63 -#define TX_MPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_msdu_extension.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_msdu_extension.h deleted file mode 100644 index f8da5593497b..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_msdu_extension.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MSDU_EXTENSION_H_ -#define _TX_MSDU_EXTENSION_H_ - -#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 - -struct tx_msdu_extension { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tso_enable : 1, - reserved_0a : 6, - tcp_flag : 9, - tcp_flag_mask : 9, - reserved_0b : 7; - uint32_t l2_length : 16, - ip_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t ip_identification : 16, - udp_length : 16; - uint32_t checksum_offset : 14, - partial_checksum_en : 1, - reserved_4a : 1, - payload_start_offset : 14, - reserved_4b : 2; - uint32_t payload_end_offset : 14, - reserved_5a : 2, - wds : 1, - reserved_5b : 15; - uint32_t buf0_ptr_31_0 : 32; - uint32_t buf0_ptr_39_32 : 8, - reserved_7a : 8, - buf0_len : 16; - uint32_t buf1_ptr_31_0 : 32; - uint32_t buf1_ptr_39_32 : 8, - reserved_9a : 8, - buf1_len : 16; - uint32_t buf2_ptr_31_0 : 32; - uint32_t buf2_ptr_39_32 : 8, - reserved_11a : 8, - buf2_len : 16; - uint32_t buf3_ptr_31_0 : 32; - uint32_t buf3_ptr_39_32 : 8, - reserved_13a : 8, - buf3_len : 16; - uint32_t buf4_ptr_31_0 : 32; - uint32_t buf4_ptr_39_32 : 8, - reserved_15a : 8, - buf4_len : 16; - uint32_t buf5_ptr_31_0 : 32; - uint32_t buf5_ptr_39_32 : 8, - reserved_17a : 8, - buf5_len : 16; -#else - uint32_t reserved_0b : 7, - tcp_flag_mask : 9, - tcp_flag : 9, - reserved_0a : 6, - tso_enable : 1; - uint32_t ip_length : 16, - l2_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t udp_length : 16, - ip_identification : 16; - uint32_t reserved_4b : 2, - payload_start_offset : 14, - reserved_4a : 1, - partial_checksum_en : 1, - checksum_offset : 14; - uint32_t reserved_5b : 15, - wds : 1, - reserved_5a : 2, - payload_end_offset : 14; - uint32_t buf0_ptr_31_0 : 32; - uint32_t buf0_len : 16, - reserved_7a : 8, - buf0_ptr_39_32 : 8; - uint32_t buf1_ptr_31_0 : 32; - uint32_t buf1_len : 16, - reserved_9a : 8, - buf1_ptr_39_32 : 8; - uint32_t buf2_ptr_31_0 : 32; - uint32_t buf2_len : 16, - reserved_11a : 8, - buf2_ptr_39_32 : 8; - uint32_t buf3_ptr_31_0 : 32; - uint32_t buf3_len : 16, - reserved_13a : 8, - buf3_ptr_39_32 : 8; - uint32_t buf4_ptr_31_0 : 32; - uint32_t buf4_len : 16, - reserved_15a : 8, - buf4_ptr_39_32 : 8; - uint32_t buf5_ptr_31_0 : 32; - uint32_t buf5_len : 16, - reserved_17a : 8, - buf5_ptr_39_32 : 8; -#endif -}; - -#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0 -#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB 0 -#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001 - -#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_RESERVED_0A_LSB 1 -#define TX_MSDU_EXTENSION_RESERVED_0A_MSB 6 -#define TX_MSDU_EXTENSION_RESERVED_0A_MASK 0x0000007e - -#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TCP_FLAG_LSB 7 -#define TX_MSDU_EXTENSION_TCP_FLAG_MSB 15 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80 - -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB 24 -#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000 - -#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET 0x00000000 -#define TX_MSDU_EXTENSION_RESERVED_0B_LSB 25 -#define TX_MSDU_EXTENSION_RESERVED_0B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_0B_MASK 0xfe000000 - -#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004 -#define TX_MSDU_EXTENSION_L2_LENGTH_LSB 0 -#define TX_MSDU_EXTENSION_L2_LENGTH_MSB 15 -#define TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff - -#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004 -#define TX_MSDU_EXTENSION_IP_LENGTH_LSB 16 -#define TX_MSDU_EXTENSION_IP_LENGTH_MSB 31 -#define TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB 31 -#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0 -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB 15 -#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff - -#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET 0x0000000c -#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB 16 -#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB 31 -#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB 0 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB 13 -#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK 0x00003fff - -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB 14 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB 14 -#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK 0x00004000 - -#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_RESERVED_4A_LSB 15 -#define TX_MSDU_EXTENSION_RESERVED_4A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_4A_MASK 0x00008000 - -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB 16 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB 29 -#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK 0x3fff0000 - -#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET 0x00000010 -#define TX_MSDU_EXTENSION_RESERVED_4B_LSB 30 -#define TX_MSDU_EXTENSION_RESERVED_4B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_4B_MASK 0xc0000000 - -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB 0 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB 13 -#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK 0x00003fff - -#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_RESERVED_5A_LSB 14 -#define TX_MSDU_EXTENSION_RESERVED_5A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_5A_MASK 0x0000c000 - -#define TX_MSDU_EXTENSION_WDS_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_WDS_LSB 16 -#define TX_MSDU_EXTENSION_WDS_MSB 16 -#define TX_MSDU_EXTENSION_WDS_MASK 0x00010000 - -#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET 0x00000014 -#define TX_MSDU_EXTENSION_RESERVED_5B_LSB 17 -#define TX_MSDU_EXTENSION_RESERVED_5B_MSB 31 -#define TX_MSDU_EXTENSION_RESERVED_5B_MASK 0xfffe0000 - -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_7A_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_RESERVED_7A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_7A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_7A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c -#define TX_MSDU_EXTENSION_BUF0_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF0_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_RESERVED_9A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_9A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_9A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024 -#define TX_MSDU_EXTENSION_BUF1_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF1_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_RESERVED_11A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_11A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_11A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c -#define TX_MSDU_EXTENSION_BUF2_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF2_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_RESERVED_13A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_13A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_13A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034 -#define TX_MSDU_EXTENSION_BUF3_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF3_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_RESERVED_15A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_15A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_15A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c -#define TX_MSDU_EXTENSION_BUF4_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF4_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000 - -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB 31 -#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff - -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB 7 -#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff - -#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_RESERVED_17A_LSB 8 -#define TX_MSDU_EXTENSION_RESERVED_17A_MSB 15 -#define TX_MSDU_EXTENSION_RESERVED_17A_MASK 0x0000ff00 - -#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044 -#define TX_MSDU_EXTENSION_BUF5_LEN_LSB 16 -#define TX_MSDU_EXTENSION_BUF5_LEN_MSB 31 -#define TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_msdu_start.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_msdu_start.h deleted file mode 100644 index e62a76009f3a..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_msdu_start.h +++ /dev/null @@ -1,250 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_MSDU_START_H_ -#define _TX_MSDU_START_H_ - -#define NUM_OF_DWORDS_TX_MSDU_START 8 - -#define NUM_OF_QWORDS_TX_MSDU_START 4 - -struct tx_msdu_start { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t msdu_len : 14, - first_msdu : 1, - last_msdu : 1, - encap_type : 2, - epd_en : 1, - da_sa_present : 2, - ipv4_checksum_en : 1, - udp_over_ipv4_checksum_en : 1, - udp_over_ipv6_checksum_en : 1, - tcp_over_ipv4_checksum_en : 1, - tcp_over_ipv6_checksum_en : 1, - dummy_msdu_delimitation : 1, - reserved_0a : 5; - uint32_t tso_enable : 1, - reserved_1a : 6, - tcp_flag : 9, - tcp_flag_mask : 9, - mesh_enable : 1, - reserved_1b : 6; - uint32_t l2_length : 16, - ip_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t ip_identification : 16, - checksum_offset : 13, - partial_checksum_en : 1, - reserved_4 : 2; - uint32_t payload_start_offset : 14, - reserved_5a : 2, - payload_end_offset : 14, - reserved_5b : 2; - uint32_t udp_length : 16, - reserved_6 : 16; - uint32_t tlv64_padding : 32; -#else - uint32_t reserved_0a : 5, - dummy_msdu_delimitation : 1, - tcp_over_ipv6_checksum_en : 1, - tcp_over_ipv4_checksum_en : 1, - udp_over_ipv6_checksum_en : 1, - udp_over_ipv4_checksum_en : 1, - ipv4_checksum_en : 1, - da_sa_present : 2, - epd_en : 1, - encap_type : 2, - last_msdu : 1, - first_msdu : 1, - msdu_len : 14; - uint32_t reserved_1b : 6, - mesh_enable : 1, - tcp_flag_mask : 9, - tcp_flag : 9, - reserved_1a : 6, - tso_enable : 1; - uint32_t ip_length : 16, - l2_length : 16; - uint32_t tcp_seq_number : 32; - uint32_t reserved_4 : 2, - partial_checksum_en : 1, - checksum_offset : 13, - ip_identification : 16; - uint32_t reserved_5b : 2, - payload_end_offset : 14, - reserved_5a : 2, - payload_start_offset : 14; - uint32_t reserved_6 : 16, - udp_length : 16; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_MSDU_START_MSDU_LEN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_MSDU_LEN_LSB 0 -#define TX_MSDU_START_MSDU_LEN_MSB 13 -#define TX_MSDU_START_MSDU_LEN_MASK 0x0000000000003fff - -#define TX_MSDU_START_FIRST_MSDU_OFFSET 0x0000000000000000 -#define TX_MSDU_START_FIRST_MSDU_LSB 14 -#define TX_MSDU_START_FIRST_MSDU_MSB 14 -#define TX_MSDU_START_FIRST_MSDU_MASK 0x0000000000004000 - -#define TX_MSDU_START_LAST_MSDU_OFFSET 0x0000000000000000 -#define TX_MSDU_START_LAST_MSDU_LSB 15 -#define TX_MSDU_START_LAST_MSDU_MSB 15 -#define TX_MSDU_START_LAST_MSDU_MASK 0x0000000000008000 - -#define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_ENCAP_TYPE_LSB 16 -#define TX_MSDU_START_ENCAP_TYPE_MSB 17 -#define TX_MSDU_START_ENCAP_TYPE_MASK 0x0000000000030000 - -#define TX_MSDU_START_EPD_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_EPD_EN_LSB 18 -#define TX_MSDU_START_EPD_EN_MSB 18 -#define TX_MSDU_START_EPD_EN_MASK 0x0000000000040000 - -#define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x0000000000000000 -#define TX_MSDU_START_DA_SA_PRESENT_LSB 19 -#define TX_MSDU_START_DA_SA_PRESENT_MSB 20 -#define TX_MSDU_START_DA_SA_PRESENT_MASK 0x0000000000180000 - -#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21 -#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x0000000000200000 - -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22 -#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000000400000 - -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23 -#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000000800000 - -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24 -#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000001000000 - -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25 -#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000002000000 - -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x0000000000000000 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26 -#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x0000000004000000 - -#define TX_MSDU_START_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_0A_LSB 27 -#define TX_MSDU_START_RESERVED_0A_MSB 31 -#define TX_MSDU_START_RESERVED_0A_MASK 0x00000000f8000000 - -#define TX_MSDU_START_TSO_ENABLE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TSO_ENABLE_LSB 32 -#define TX_MSDU_START_TSO_ENABLE_MSB 32 -#define TX_MSDU_START_TSO_ENABLE_MASK 0x0000000100000000 - -#define TX_MSDU_START_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_1A_LSB 33 -#define TX_MSDU_START_RESERVED_1A_MSB 38 -#define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e00000000 - -#define TX_MSDU_START_TCP_FLAG_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_FLAG_LSB 39 -#define TX_MSDU_START_TCP_FLAG_MSB 47 -#define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff8000000000 - -#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x0000000000000000 -#define TX_MSDU_START_TCP_FLAG_MASK_LSB 48 -#define TX_MSDU_START_TCP_FLAG_MASK_MSB 56 -#define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff000000000000 - -#define TX_MSDU_START_MESH_ENABLE_OFFSET 0x0000000000000000 -#define TX_MSDU_START_MESH_ENABLE_LSB 57 -#define TX_MSDU_START_MESH_ENABLE_MSB 57 -#define TX_MSDU_START_MESH_ENABLE_MASK 0x0200000000000000 - -#define TX_MSDU_START_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_MSDU_START_RESERVED_1B_LSB 58 -#define TX_MSDU_START_RESERVED_1B_MSB 63 -#define TX_MSDU_START_RESERVED_1B_MASK 0xfc00000000000000 - -#define TX_MSDU_START_L2_LENGTH_OFFSET 0x0000000000000008 -#define TX_MSDU_START_L2_LENGTH_LSB 0 -#define TX_MSDU_START_L2_LENGTH_MSB 15 -#define TX_MSDU_START_L2_LENGTH_MASK 0x000000000000ffff - -#define TX_MSDU_START_IP_LENGTH_OFFSET 0x0000000000000008 -#define TX_MSDU_START_IP_LENGTH_LSB 16 -#define TX_MSDU_START_IP_LENGTH_MSB 31 -#define TX_MSDU_START_IP_LENGTH_MASK 0x00000000ffff0000 - -#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000000000008 -#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 32 -#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 63 -#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 - -#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x0000000000000010 -#define TX_MSDU_START_IP_IDENTIFICATION_LSB 0 -#define TX_MSDU_START_IP_IDENTIFICATION_MSB 15 -#define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x000000000000ffff - -#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16 -#define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28 -#define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x000000001fff0000 - -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29 -#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x0000000020000000 - -#define TX_MSDU_START_RESERVED_4_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_4_LSB 30 -#define TX_MSDU_START_RESERVED_4_MSB 31 -#define TX_MSDU_START_RESERVED_4_MASK 0x00000000c0000000 - -#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 32 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 45 -#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff00000000 - -#define TX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_5A_LSB 46 -#define TX_MSDU_START_RESERVED_5A_MSB 47 -#define TX_MSDU_START_RESERVED_5A_MASK 0x0000c00000000000 - -#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x0000000000000010 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 48 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 61 -#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff000000000000 - -#define TX_MSDU_START_RESERVED_5B_OFFSET 0x0000000000000010 -#define TX_MSDU_START_RESERVED_5B_LSB 62 -#define TX_MSDU_START_RESERVED_5B_MSB 63 -#define TX_MSDU_START_RESERVED_5B_MASK 0xc000000000000000 - -#define TX_MSDU_START_UDP_LENGTH_OFFSET 0x0000000000000018 -#define TX_MSDU_START_UDP_LENGTH_LSB 0 -#define TX_MSDU_START_UDP_LENGTH_MSB 15 -#define TX_MSDU_START_UDP_LENGTH_MASK 0x000000000000ffff - -#define TX_MSDU_START_RESERVED_6_OFFSET 0x0000000000000018 -#define TX_MSDU_START_RESERVED_6_LSB 16 -#define TX_MSDU_START_RESERVED_6_MSB 31 -#define TX_MSDU_START_RESERVED_6_MASK 0x00000000ffff0000 - -#define TX_MSDU_START_TLV64_PADDING_OFFSET 0x0000000000000018 -#define TX_MSDU_START_TLV64_PADDING_LSB 32 -#define TX_MSDU_START_TLV64_PADDING_MSB 63 -#define TX_MSDU_START_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_peer_entry.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_peer_entry.h deleted file mode 100644 index c26c7f6a3e05..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_peer_entry.h +++ /dev/null @@ -1,391 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_PEER_ENTRY_H_ -#define _TX_PEER_ENTRY_H_ - -#define NUM_OF_DWORDS_TX_PEER_ENTRY 22 - -#define NUM_OF_QWORDS_TX_PEER_ENTRY 11 - -struct tx_peer_entry { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t mac_addr_a_31_0 : 32; - uint32_t mac_addr_a_47_32 : 16, - mac_addr_b_15_0 : 16; - uint32_t mac_addr_b_47_16 : 32; - uint32_t use_ad_b : 1, - strip_insert_vlan_inner : 1, - strip_insert_vlan_outer : 1, - vlan_llc_mode : 1, - key_type : 4, - a_msdu_wds_ad3_ad4 : 3, - ignore_hard_filters : 1, - ignore_soft_filters : 1, - epd_output : 1, - wds : 1, - insert_or_strip : 1, - sw_filter_id : 16; - uint32_t temporal_key_31_0 : 32; - uint32_t temporal_key_63_32 : 32; - uint32_t temporal_key_95_64 : 32; - uint32_t temporal_key_127_96 : 32; - uint32_t temporal_key_159_128 : 32; - uint32_t temporal_key_191_160 : 32; - uint32_t temporal_key_223_192 : 32; - uint32_t temporal_key_255_224 : 32; - uint32_t sta_partial_aid : 11, - transmit_vif : 4, - block_this_user : 1, - mesh_amsdu_mode : 2, - use_qos_alt_mute_mask : 1, - dl_ul_direction : 1, - use_ad_c : 1, - a_msdu_11s_fromtods_10_ad3 : 2, - multi_link_addr_ad3_valid : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_ad1_trans_dis : 1, - data_fromtods_00_ad3 : 2, - mgmt_fromtods_00_ad3 : 2, - reserved_12 : 1; - uint32_t insert_vlan_outer_tci : 16, - insert_vlan_inner_tci : 16; - uint32_t __reserved_g_0007 : 32; - uint32_t __reserved_g_0008 : 16, - __reserved_g_0009 : 16; - uint32_t __reserved_g_0010 : 32; - uint32_t multi_link_addr_crypto_enable : 1, - a_msdu_fromtods_10_ad3 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_11_ad4 : 2, - reserved_17a : 9, - sw_peer_id : 16; - uint32_t mac_addr_c_31_0 : 32; - uint32_t mac_addr_c_47_32 : 16, - multi_link_addr_ad3_47_32 : 16; - uint32_t multi_link_addr_ad3_31_0 : 32; - uint32_t tlv64_padding : 32; -#else - uint32_t mac_addr_a_31_0 : 32; - uint32_t mac_addr_b_15_0 : 16, - mac_addr_a_47_32 : 16; - uint32_t mac_addr_b_47_16 : 32; - uint32_t sw_filter_id : 16, - insert_or_strip : 1, - wds : 1, - epd_output : 1, - ignore_soft_filters : 1, - ignore_hard_filters : 1, - a_msdu_wds_ad3_ad4 : 3, - key_type : 4, - vlan_llc_mode : 1, - strip_insert_vlan_outer : 1, - strip_insert_vlan_inner : 1, - use_ad_b : 1; - uint32_t temporal_key_31_0 : 32; - uint32_t temporal_key_63_32 : 32; - uint32_t temporal_key_95_64 : 32; - uint32_t temporal_key_127_96 : 32; - uint32_t temporal_key_159_128 : 32; - uint32_t temporal_key_191_160 : 32; - uint32_t temporal_key_223_192 : 32; - uint32_t temporal_key_255_224 : 32; - uint32_t reserved_12 : 1, - mgmt_fromtods_00_ad3 : 2, - data_fromtods_00_ad3 : 2, - multi_link_addr_ad1_trans_dis : 1, - multi_link_addr_mgmt_crypto_en : 1, - multi_link_addr_fromtods_00_crypto_en : 1, - multi_link_addr_ad3_valid : 1, - a_msdu_11s_fromtods_10_ad3 : 2, - use_ad_c : 1, - dl_ul_direction : 1, - use_qos_alt_mute_mask : 1, - mesh_amsdu_mode : 2, - block_this_user : 1, - transmit_vif : 4, - sta_partial_aid : 11; - uint32_t insert_vlan_inner_tci : 16, - insert_vlan_outer_tci : 16; - uint32_t __reserved_g_0007 : 32; - uint32_t __reserved_g_0009 : 16, - __reserved_g_0008 : 16; - uint32_t __reserved_g_0010 : 32; - uint32_t sw_peer_id : 16, - reserved_17a : 9, - a_msdu_fromtods_11_ad4 : 2, - a_msdu_fromtods_11_ad3 : 2, - a_msdu_fromtods_10_ad3 : 2, - multi_link_addr_crypto_enable : 1; - uint32_t mac_addr_c_31_0 : 32; - uint32_t multi_link_addr_ad3_47_32 : 16, - mac_addr_c_47_32 : 16; - uint32_t multi_link_addr_ad3_31_0 : 32; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 32 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 47 -#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x0000000000000000 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 48 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 63 -#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_USE_AD_B_LSB 32 -#define TX_PEER_ENTRY_USE_AD_B_MSB 32 -#define TX_PEER_ENTRY_USE_AD_B_MASK 0x0000000100000000 - -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 33 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 33 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x0000000200000000 - -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 34 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 34 -#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x0000000400000000 - -#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 35 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 35 -#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x0000000800000000 - -#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_KEY_TYPE_LSB 36 -#define TX_PEER_ENTRY_KEY_TYPE_MSB 39 -#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f000000000 - -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 40 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 42 -#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x0000070000000000 - -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 43 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 43 -#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x0000080000000000 - -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 44 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 44 -#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x0000100000000000 - -#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 45 -#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 45 -#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x0000200000000000 - -#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_WDS_LSB 46 -#define TX_PEER_ENTRY_WDS_MSB 46 -#define TX_PEER_ENTRY_WDS_MASK 0x0000400000000000 - -#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 47 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 47 -#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x0000800000000000 - -#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000000000008 -#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 48 -#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 63 -#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x0000000000000010 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x0000000000000010 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x0000000000000018 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000000000000018 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x0000000000000020 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x0000000000000020 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x0000000000000028 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 -#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000000000000028 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 32 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 63 -#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff00000000 - -#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 -#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x00000000000007ff - -#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 -#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 -#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x0000000000007800 - -#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 -#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x0000000000008000 - -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 -#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x0000000000030000 - -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 -#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x0000000000040000 - -#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 -#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x0000000000080000 - -#define TX_PEER_ENTRY_USE_AD_C_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_USE_AD_C_LSB 20 -#define TX_PEER_ENTRY_USE_AD_C_MSB 20 -#define TX_PEER_ENTRY_USE_AD_C_MASK 0x0000000000100000 - -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_LSB 21 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MSB 22 -#define TX_PEER_ENTRY_A_MSDU_11S_FROMTODS_10_AD3_MASK 0x0000000000600000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_LSB 23 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MSB 23 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_VALID_MASK 0x0000000000800000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_LSB 24 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MSB 24 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_FROMTODS_00_CRYPTO_EN_MASK 0x0000000001000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_LSB 25 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MSB 25 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_MGMT_CRYPTO_EN_MASK 0x0000000002000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_LSB 26 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MSB 26 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_TRANS_DIS_MASK 0x0000000004000000 - -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_LSB 27 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MSB 28 -#define TX_PEER_ENTRY_DATA_FROMTODS_00_AD3_MASK 0x0000000018000000 - -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_LSB 29 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MSB 30 -#define TX_PEER_ENTRY_MGMT_FROMTODS_00_AD3_MASK 0x0000000060000000 - -#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_RESERVED_12_LSB 31 -#define TX_PEER_ENTRY_RESERVED_12_MSB 31 -#define TX_PEER_ENTRY_RESERVED_12_MASK 0x0000000080000000 - -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 32 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 47 -#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x0000000000000030 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 48 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 63 -#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 32 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 32 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x0000000100000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_LSB 33 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MSB 34 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_10_AD3_MASK 0x0000000600000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_LSB 35 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MSB 36 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD3_MASK 0x0000001800000000 - -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_LSB 37 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MSB 38 -#define TX_PEER_ENTRY_A_MSDU_FROMTODS_11_AD4_MASK 0x0000006000000000 - -#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_RESERVED_17A_LSB 39 -#define TX_PEER_ENTRY_RESERVED_17A_MSB 47 -#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000ff8000000000 - -#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x0000000000000040 -#define TX_PEER_ENTRY_SW_PEER_ID_LSB 48 -#define TX_PEER_ENTRY_SW_PEER_ID_MSB 63 -#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_LSB 0 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MSB 31 -#define TX_PEER_ENTRY_MAC_ADDR_C_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_LSB 32 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MSB 47 -#define TX_PEER_ENTRY_MAC_ADDR_C_47_32_MASK 0x0000ffff00000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_OFFSET 0x0000000000000048 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_LSB 48 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MSB 63 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_47_32_MASK 0xffff000000000000 - -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_OFFSET 0x0000000000000050 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_LSB 0 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MSB 31 -#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD3_31_0_MASK 0x00000000ffffffff - -#define TX_PEER_ENTRY_TLV64_PADDING_OFFSET 0x0000000000000050 -#define TX_PEER_ENTRY_TLV64_PADDING_LSB 32 -#define TX_PEER_ENTRY_TLV64_PADDING_MSB 63 -#define TX_PEER_ENTRY_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_queue_extension.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_queue_extension.h deleted file mode 100644 index e46bae7cff4c..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_queue_extension.h +++ /dev/null @@ -1,432 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_QUEUE_EXTENSION_H_ -#define _TX_QUEUE_EXTENSION_H_ - -#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 18 - -#define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 9 - -struct tx_queue_extension { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t frame_ctl : 16, - qos_ctl : 16; - uint32_t ampdu_flag : 1, - tx_notify_no_htc_override : 1, - reserved_1a : 7, - checksum_tso_disable_for_frag : 1, - key_id : 8, - qos_buf_state_overwrite : 1, - buf_state_sta_id : 1, - buf_state_source : 1, - ht_control_overwrite_enable : 1, - ht_control_overwrite_source : 4, - reserved_1b : 6; - uint32_t ul_headroom_insertion_enable : 1, - ul_headroom_offset : 5, - bqrp_insertion_enable : 1, - bqrp_offset : 5, - ul_headroom_rsvd_7_6 : 2, - bqr_rsvd_9_8 : 2, - base_pn_63_48 : 16; - uint32_t base_pn_95_64 : 32; - uint32_t base_pn_127_96 : 32; - uint32_t ht_control_default_tb_ppdu : 32; - uint32_t ht_control_default_non_tb_ppdu : 32; - uint32_t ht_control_overwrite_tb_ppdu_enable : 1, - ht_control_overwrite_non_tb_ppdu_enable : 1, - reserved_7a : 30; - uint32_t reserved_8a : 32; - uint32_t ht_control_overwrite_mask : 32; - uint32_t cas_control_info : 8, - cas_offset : 5, - cas_insertion_enable : 1, - reserved_10a : 2, - ht_control_overwrite_source_for_srp : 4, - ht_control_overwrite_source_for_bsrp : 4, - pre_padding_fcs_overwrite_enable : 1, - reserved_10b : 5, - mpdu_hdr_len_override_en : 1, - bar_ssn_overwrite_enable : 1; - uint32_t bar_ssn_offset : 12, - mpdu_hdr_len_override_val : 9, - reserved_11a : 11; - uint32_t fw2sw_info : 32; - uint32_t pre_padding_fcs_overwrite_offset : 16, - icf_blackout_info_offset : 16; - uint32_t trigger_common_info_length : 6, - cmf_overwrite_offset : 14, - reserved_15a : 12; - uint32_t hdr_ctrl_prot_key_id_byte_offset : 14, - hdr_ctrl_prot_key_id_bit_offset : 3, - ctrl_pkt_protect : 1, - mac_hdr_protect : 1, - hdr_ctrl_prot_tx_peer_idx : 11, - reserved_16a : 2; - uint32_t pad_byte_offset : 16, - pad_byte_offset_valid : 1, - txop_duration_overwrite_enable : 1, - txop_duration_offset : 14; - uint32_t tlv64_padding : 32; -#else - uint32_t qos_ctl : 16, - frame_ctl : 16; - uint32_t reserved_1b : 6, - ht_control_overwrite_source : 4, - ht_control_overwrite_enable : 1, - buf_state_source : 1, - buf_state_sta_id : 1, - qos_buf_state_overwrite : 1, - key_id : 8, - checksum_tso_disable_for_frag : 1, - reserved_1a : 7, - tx_notify_no_htc_override : 1, - ampdu_flag : 1; - uint32_t base_pn_63_48 : 16, - bqr_rsvd_9_8 : 2, - ul_headroom_rsvd_7_6 : 2, - bqrp_offset : 5, - bqrp_insertion_enable : 1, - ul_headroom_offset : 5, - ul_headroom_insertion_enable : 1; - uint32_t base_pn_95_64 : 32; - uint32_t base_pn_127_96 : 32; - uint32_t ht_control_default_tb_ppdu : 32; - uint32_t ht_control_default_non_tb_ppdu : 32; - uint32_t reserved_7a : 30, - ht_control_overwrite_non_tb_ppdu_enable : 1, - ht_control_overwrite_tb_ppdu_enable : 1; - uint32_t reserved_8a : 32; - uint32_t ht_control_overwrite_mask : 32; - uint32_t bar_ssn_overwrite_enable : 1, - mpdu_hdr_len_override_en : 1, - reserved_10b : 5, - pre_padding_fcs_overwrite_enable : 1, - ht_control_overwrite_source_for_bsrp : 4, - ht_control_overwrite_source_for_srp : 4, - reserved_10a : 2, - cas_insertion_enable : 1, - cas_offset : 5, - cas_control_info : 8; - uint32_t reserved_11a : 11, - mpdu_hdr_len_override_val : 9, - bar_ssn_offset : 12; - uint32_t fw2sw_info : 32; - uint32_t icf_blackout_info_offset : 16, - pre_padding_fcs_overwrite_offset : 16; - uint32_t reserved_15a : 12, - cmf_overwrite_offset : 14, - trigger_common_info_length : 6; - uint32_t reserved_16a : 2, - hdr_ctrl_prot_tx_peer_idx : 11, - mac_hdr_protect : 1, - ctrl_pkt_protect : 1, - hdr_ctrl_prot_key_id_bit_offset : 3, - hdr_ctrl_prot_key_id_byte_offset : 14; - uint32_t txop_duration_offset : 14, - txop_duration_overwrite_enable : 1, - pad_byte_offset_valid : 1, - pad_byte_offset : 16; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 -#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 -#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x000000000000ffff - -#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 -#define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 -#define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0x00000000ffff0000 - -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 32 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 32 -#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x0000000100000000 - -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 33 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 33 -#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x0000000200000000 - -#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 34 -#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 40 -#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc00000000 - -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 41 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 41 -#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x0000020000000000 - -#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_KEY_ID_LSB 42 -#define TX_QUEUE_EXTENSION_KEY_ID_MSB 49 -#define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc0000000000 - -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 50 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 50 -#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x0004000000000000 - -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 51 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 51 -#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x0008000000000000 - -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 52 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 52 -#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x0010000000000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 53 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 53 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x0020000000000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 54 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 57 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c0000000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x0000000000000000 -#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 58 -#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc00000000000000 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x0000000000000001 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x000000000000003e - -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 -#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x0000000000000040 - -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 -#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x0000000000000f80 - -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 -#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x0000000000003000 - -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 -#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x000000000000c000 - -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 -#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0x00000000ffff0000 - -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000000000008 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 32 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 63 -#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x0000000000000010 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 -#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_OFFSET 0x0000000000000010 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_MSB 63 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_TB_PPDU_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_LSB 0 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_MSB 31 -#define TX_QUEUE_EXTENSION_HT_CONTROL_DEFAULT_NON_TB_PPDU_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_MSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_TB_PPDU_ENABLE_MASK 0x0000000100000000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_LSB 33 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_MSB 33 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_NON_TB_PPDU_ENABLE_MASK 0x0000000200000000 - -#define TX_QUEUE_EXTENSION_RESERVED_7A_OFFSET 0x0000000000000018 -#define TX_QUEUE_EXTENSION_RESERVED_7A_LSB 34 -#define TX_QUEUE_EXTENSION_RESERVED_7A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_7A_MASK 0xfffffffc00000000 - -#define TX_QUEUE_EXTENSION_RESERVED_8A_OFFSET 0x0000000000000020 -#define TX_QUEUE_EXTENSION_RESERVED_8A_LSB 0 -#define TX_QUEUE_EXTENSION_RESERVED_8A_MSB 31 -#define TX_QUEUE_EXTENSION_RESERVED_8A_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x0000000000000020 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 32 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 63 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff00000000 - -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 -#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x00000000000000ff - -#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 -#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x0000000000001f00 - -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 -#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x0000000000002000 - -#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 -#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 -#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x000000000000c000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x00000000000f0000 - -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 -#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x0000000000f00000 - -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_LSB 24 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MSB 24 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_ENABLE_MASK 0x0000000001000000 - -#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 25 -#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 -#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x000000003e000000 - -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x0000000040000000 - -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 -#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x0000000080000000 - -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 32 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 43 -#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff00000000 - -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 44 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 52 -#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff00000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000000000000028 -#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 53 -#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe0000000000000 - -#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x0000000000000030 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 0 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 31 -#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0x00000000ffffffff - -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_OFFSET 0x0000000000000030 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_LSB 32 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MSB 47 -#define TX_QUEUE_EXTENSION_PRE_PADDING_FCS_OVERWRITE_OFFSET_MASK 0x0000ffff00000000 - -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_OFFSET 0x0000000000000030 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_LSB 48 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MSB 63 -#define TX_QUEUE_EXTENSION_ICF_BLACKOUT_INFO_OFFSET_MASK 0xffff000000000000 - -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_LSB 0 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MSB 5 -#define TX_QUEUE_EXTENSION_TRIGGER_COMMON_INFO_LENGTH_MASK 0x000000000000003f - -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_LSB 6 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MSB 19 -#define TX_QUEUE_EXTENSION_CMF_OVERWRITE_OFFSET_MASK 0x00000000000fffc0 - -#define TX_QUEUE_EXTENSION_RESERVED_15A_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_RESERVED_15A_LSB 20 -#define TX_QUEUE_EXTENSION_RESERVED_15A_MSB 31 -#define TX_QUEUE_EXTENSION_RESERVED_15A_MASK 0x00000000fff00000 - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_LSB 32 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MSB 45 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BYTE_OFFSET_MASK 0x00003fff00000000 - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_LSB 46 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MSB 48 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_KEY_ID_BIT_OFFSET_MASK 0x0001c00000000000 - -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_LSB 49 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MSB 49 -#define TX_QUEUE_EXTENSION_CTRL_PKT_PROTECT_MASK 0x0002000000000000 - -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_LSB 50 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MSB 50 -#define TX_QUEUE_EXTENSION_MAC_HDR_PROTECT_MASK 0x0004000000000000 - -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_LSB 51 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MSB 61 -#define TX_QUEUE_EXTENSION_HDR_CTRL_PROT_TX_PEER_IDX_MASK 0x3ff8000000000000 - -#define TX_QUEUE_EXTENSION_RESERVED_16A_OFFSET 0x0000000000000038 -#define TX_QUEUE_EXTENSION_RESERVED_16A_LSB 62 -#define TX_QUEUE_EXTENSION_RESERVED_16A_MSB 63 -#define TX_QUEUE_EXTENSION_RESERVED_16A_MASK 0xc000000000000000 - -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_LSB 0 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MSB 15 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_MASK 0x000000000000ffff - -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_LSB 16 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MSB 16 -#define TX_QUEUE_EXTENSION_PAD_BYTE_OFFSET_VALID_MASK 0x0000000000010000 - -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_LSB 17 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_MSB 17 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OVERWRITE_ENABLE_MASK 0x0000000000020000 - -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_LSB 18 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_MSB 31 -#define TX_QUEUE_EXTENSION_TXOP_DURATION_OFFSET_MASK 0x00000000fffc0000 - -#define TX_QUEUE_EXTENSION_TLV64_PADDING_OFFSET 0x0000000000000040 -#define TX_QUEUE_EXTENSION_TLV64_PADDING_LSB 32 -#define TX_QUEUE_EXTENSION_TLV64_PADDING_MSB 63 -#define TX_QUEUE_EXTENSION_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_rate_stats_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_rate_stats_info.h deleted file mode 100644 index ce84032dd353..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_rate_stats_info.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_RATE_STATS_INFO_H_ -#define _TX_RATE_STATS_INFO_H_ - -#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 - -struct tx_rate_stats_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t tx_rate_stats_info_valid : 1, - transmit_bw : 3, - transmit_pkt_type : 4, - transmit_stbc : 1, - transmit_ldpc : 1, - transmit_sgi : 2, - transmit_mcs : 5, - unequal_modulation_info : 3, - ofdma_transmission : 1, - reserved_0a : 4, - tones_in_ru : 4, - transmit_nss : 3; - uint32_t ppdu_transmission_tsf : 32; -#else - uint32_t transmit_nss : 3, - tones_in_ru : 4, - reserved_0a : 4, - ofdma_transmission : 1, - unequal_modulation_info : 3, - transmit_mcs : 5, - transmit_sgi : 2, - transmit_ldpc : 1, - transmit_stbc : 1, - transmit_pkt_type : 4, - transmit_bw : 3, - tx_rate_stats_info_valid : 1; - uint32_t ppdu_transmission_tsf : 32; -#endif -}; - -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB 0 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB 0 -#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 - -#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB 1 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB 3 -#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK 0x0000000e - -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB 4 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB 7 -#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK 0x000000f0 - -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB 8 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB 8 -#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK 0x00000100 - -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB 9 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB 9 -#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK 0x00000200 - -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB 10 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB 11 -#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK 0x00000c00 - -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB 12 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB 16 -#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK 0x0001f000 - -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_LSB 17 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MSB 19 -#define TX_RATE_STATS_INFO_UNEQUAL_MODULATION_INFO_MASK 0x000e0000 - -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB 20 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB 20 -#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK 0x00100000 - -#define TX_RATE_STATS_INFO_RESERVED_0A_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_RESERVED_0A_LSB 21 -#define TX_RATE_STATS_INFO_RESERVED_0A_MSB 24 -#define TX_RATE_STATS_INFO_RESERVED_0A_MASK 0x01e00000 - -#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB 25 -#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB 28 -#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK 0x1e000000 - -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_OFFSET 0x00000000 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_LSB 29 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MSB 31 -#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MASK 0xe0000000 - -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB 0 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB 31 -#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/tx_raw_or_native_frame_setup.h b/drivers/staging/fw-api/hw/wcn8750/v1/tx_raw_or_native_frame_setup.h deleted file mode 100644 index 220a82edf96d..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/tx_raw_or_native_frame_setup.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ -#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ - -#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 4 - -#define NUM_OF_QWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2 - -struct tx_raw_or_native_frame_setup { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t fc_to_ds_mask : 1, - fc_from_ds_mask : 1, - fc_more_frag_mask : 1, - fc_retry_mask : 1, - fc_pwr_mgt_mask : 1, - fc_more_data_mask : 1, - fc_prot_frame_mask : 1, - fc_order_mask : 1, - duration_field_mask : 1, - sequence_control_mask : 1, - qc_tid_mask : 1, - qc_eosp_mask : 1, - qc_ack_policy_mask : 1, - qc_amsdu_mask : 1, - reserved_0a : 1, - qc_15to8_mask : 1, - iv_mask : 1, - fc_to_ds_setting : 1, - fc_from_ds_setting : 1, - fc_more_frag_setting : 1, - fc_retry_setting : 2, - fc_pwr_mgt_setting : 1, - fc_more_data_setting : 2, - fc_prot_frame_setting : 2, - fc_order_setting : 1, - qc_tid_setting : 4; - uint32_t qc_eosp_setting : 2, - qc_ack_policy_setting : 2, - qc_amsdu_setting : 1, - qc_15to8_setting : 8, - mlo_addr_override : 1, - mlo_ignore_addr3_override : 1, - sequence_control_source : 1, - fragment_number : 4, - sequence_number : 12; - uint32_t mlo_addr_override_for_ctrl : 1, - reserved_2a : 31; - uint32_t tlv64_padding : 32; -#else - uint32_t qc_tid_setting : 4, - fc_order_setting : 1, - fc_prot_frame_setting : 2, - fc_more_data_setting : 2, - fc_pwr_mgt_setting : 1, - fc_retry_setting : 2, - fc_more_frag_setting : 1, - fc_from_ds_setting : 1, - fc_to_ds_setting : 1, - iv_mask : 1, - qc_15to8_mask : 1, - reserved_0a : 1, - qc_amsdu_mask : 1, - qc_ack_policy_mask : 1, - qc_eosp_mask : 1, - qc_tid_mask : 1, - sequence_control_mask : 1, - duration_field_mask : 1, - fc_order_mask : 1, - fc_prot_frame_mask : 1, - fc_more_data_mask : 1, - fc_pwr_mgt_mask : 1, - fc_retry_mask : 1, - fc_more_frag_mask : 1, - fc_from_ds_mask : 1, - fc_to_ds_mask : 1; - uint32_t sequence_number : 12, - fragment_number : 4, - sequence_control_source : 1, - mlo_ignore_addr3_override : 1, - mlo_addr_override : 1, - qc_15to8_setting : 8, - qc_amsdu_setting : 1, - qc_ack_policy_setting : 2, - qc_eosp_setting : 2; - uint32_t reserved_2a : 31, - mlo_addr_override_for_ctrl : 1; - uint32_t tlv64_padding : 32; -#endif -}; - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK 0x0000000000000001 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK 0x0000000000000002 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB 2 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB 2 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK 0x0000000000000004 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB 3 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB 3 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK 0x0000000000000008 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB 4 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB 4 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK 0x0000000000000010 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB 5 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB 5 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK 0x0000000000000020 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB 6 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB 6 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK 0x0000000000000040 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB 7 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB 7 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK 0x0000000000000080 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB 8 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB 8 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK 0x0000000000000100 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB 9 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB 9 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK 0x0000000000000200 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB 10 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB 10 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK 0x0000000000000400 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB 11 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB 11 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK 0x0000000000000800 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB 12 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB 12 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK 0x0000000000001000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB 13 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB 13 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK 0x0000000000002000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB 14 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB 14 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK 0x0000000000004000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB 15 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB 15 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK 0x0000000000008000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB 16 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB 16 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK 0x0000000000010000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB 17 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB 17 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK 0x0000000000020000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB 18 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB 18 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK 0x0000000000040000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB 19 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB 19 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK 0x0000000000080000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB 20 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB 21 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK 0x0000000000300000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB 22 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB 22 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK 0x0000000000400000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB 23 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB 24 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK 0x0000000001800000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB 25 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB 26 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK 0x0000000006000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB 27 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB 27 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK 0x0000000008000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB 28 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB 31 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK 0x00000000f0000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB 32 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB 33 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK 0x0000000300000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB 34 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB 35 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK 0x0000000c00000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB 36 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB 36 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK 0x0000001000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB 37 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB 44 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK 0x00001fe000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB 45 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB 45 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK 0x0000200000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB 46 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB 46 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK 0x0000400000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB 47 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB 47 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK 0x0000800000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB 48 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB 51 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK 0x000f000000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET 0x0000000000000000 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB 52 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB 63 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK 0xfff0000000000000 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_LSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MSB 0 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_FOR_CTRL_MASK 0x0000000000000001 - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_LSB 1 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MSB 31 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_2A_MASK 0x00000000fffffffe - -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_OFFSET 0x0000000000000008 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_LSB 32 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MSB 63 -#define TX_RAW_OR_NATIVE_FRAME_SETUP_TLV64_PADDING_MASK 0xffffffff00000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_buffer_basics.h b/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_buffer_basics.h deleted file mode 100644 index 4032a78ad617..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_buffer_basics.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_BUFFER_BASICS_H_ -#define _TXPCU_BUFFER_BASICS_H_ - -#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1 - -struct txpcu_buffer_basics { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t available_memory : 8, - partial_tx_data_tlv_count : 8, - tx_data_tlv_count : 16; -#else - uint32_t tx_data_tlv_count : 16, - partial_tx_data_tlv_count : 8, - available_memory : 8; -#endif -}; - -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK 0x000000ff - -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 - -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET 0x00000000 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK 0xffff0000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_buffer_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_buffer_status.h deleted file mode 100644 index 847ca277267d..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_buffer_status.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_BUFFER_STATUS_H_ -#define _TXPCU_BUFFER_STATUS_H_ - -#include "txpcu_buffer_basics.h" -#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2 - -#define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1 - -struct txpcu_buffer_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct txpcu_buffer_basics txpcu_basix_buffer_info; - uint32_t reserved : 15, - msdu_end : 1, - tx_data_sync_value : 16; -#else - struct txpcu_buffer_basics txpcu_basix_buffer_info; - uint32_t tx_data_sync_value : 16, - msdu_end : 1, - reserved : 15; -#endif -}; - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 - -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 - -#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_RESERVED_LSB 32 -#define TXPCU_BUFFER_STATUS_RESERVED_MSB 46 -#define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff00000000 - -#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_MSDU_END_LSB 47 -#define TXPCU_BUFFER_STATUS_MSDU_END_MSB 47 -#define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 - -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 -#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_user_buffer_status.h b/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_user_buffer_status.h deleted file mode 100644 index f6ad0fd73721..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/txpcu_user_buffer_status.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _TXPCU_USER_BUFFER_STATUS_H_ -#define _TXPCU_USER_BUFFER_STATUS_H_ - -#include "txpcu_buffer_basics.h" -#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2 - -#define NUM_OF_QWORDS_TXPCU_USER_BUFFER_STATUS 1 - -struct txpcu_user_buffer_status { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct txpcu_buffer_basics txpcu_basic_buffer_info; - uint32_t stored_word_count_user : 14, - reserved_1a : 1, - msdu_end : 1, - tx_data_sync_value : 16; -#else - struct txpcu_buffer_basics txpcu_basic_buffer_info; - uint32_t tx_data_sync_value : 16, - msdu_end : 1, - reserved_1a : 1, - stored_word_count_user : 14; -#endif -}; - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 - -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 -#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 - -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB 32 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB 45 -#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK 0x00003fff00000000 - -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB 46 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB 46 -#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK 0x0000400000000000 - -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB 47 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB 47 -#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 - -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 -#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/u_sig_eht_su_mu_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/u_sig_eht_su_mu_info.h deleted file mode 100644 index 1a08f3ab39b2..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/u_sig_eht_su_mu_info.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _U_SIG_EHT_SU_MU_INFO_H_ -#define _U_SIG_EHT_SU_MU_INFO_H_ - -#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 - -struct u_sig_eht_su_mu_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_version : 3, - transmit_bw : 3, - dl_ul_flag : 1, - bss_color_id : 6, - txop_duration : 7, - disregard_0a : 5, - validate_0b : 1, - reserved_0c : 6; - uint32_t eht_ppdu_sig_cmn_type : 2, - validate_1a : 1, - punctured_channel_information : 5, - validate_1b : 1, - mcs_of_eht_sig : 2, - num_eht_sig_symbols : 5, - crc : 4, - tail : 6, - dot11ax_su_extended : 1, - reserved_1d : 3, - rx_ndp : 1, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0c : 6, - validate_0b : 1, - disregard_0a : 5, - txop_duration : 7, - bss_color_id : 6, - dl_ul_flag : 1, - transmit_bw : 3, - phy_version : 3; - uint32_t rx_integrity_check_passed : 1, - rx_ndp : 1, - reserved_1d : 3, - dot11ax_su_extended : 1, - tail : 6, - crc : 4, - num_eht_sig_symbols : 5, - mcs_of_eht_sig : 2, - validate_1b : 1, - punctured_channel_information : 5, - validate_1a : 1, - eht_ppdu_sig_cmn_type : 2; -#endif -}; - -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 -#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 - -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 -#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 - -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 -#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 - -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 -#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 - -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 -#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 - -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 -#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 - -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 - -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 -#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 - -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 -#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 - -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 -#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 - -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 -#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 - -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 -#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 - -#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 -#define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 -#define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 - -#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 -#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 -#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 - -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 -#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 - -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 -#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 - -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 -#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 - -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/u_sig_eht_tb_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/u_sig_eht_tb_info.h deleted file mode 100644 index 8e417b38d233..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/u_sig_eht_tb_info.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _U_SIG_EHT_TB_INFO_H_ -#define _U_SIG_EHT_TB_INFO_H_ - -#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2 - -struct u_sig_eht_tb_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t phy_version : 3, - transmit_bw : 3, - dl_ul_flag : 1, - bss_color_id : 6, - txop_duration : 7, - disregard_0a : 6, - reserved_0c : 6; - uint32_t eht_ppdu_sig_cmn_type : 2, - validate_1a : 1, - spatial_reuse : 8, - disregard_1b : 5, - crc : 4, - tail : 6, - reserved_1c : 5, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0c : 6, - disregard_0a : 6, - txop_duration : 7, - bss_color_id : 6, - dl_ul_flag : 1, - transmit_bw : 3, - phy_version : 3; - uint32_t rx_integrity_check_passed : 1, - reserved_1c : 5, - tail : 6, - crc : 4, - disregard_1b : 5, - spatial_reuse : 8, - validate_1a : 1, - eht_ppdu_sig_cmn_type : 2; -#endif -}; - -#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2 -#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007 - -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5 -#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038 - -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6 -#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040 - -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12 -#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80 - -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19 -#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000 - -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25 -#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000 - -#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31 -#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000 - -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 -#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 - -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2 -#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004 - -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10 -#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8 - -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15 -#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800 - -#define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_CRC_LSB 16 -#define U_SIG_EHT_TB_INFO_CRC_MSB 19 -#define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000 - -#define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_TAIL_LSB 20 -#define U_SIG_EHT_TB_INFO_TAIL_MSB 25 -#define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000 - -#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30 -#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000 - -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/unallocated_ru_160_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/unallocated_ru_160_info.h deleted file mode 100644 index ccd4a7bab9ad..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/unallocated_ru_160_info.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _UNALLOCATED_RU_160_INFO_H_ -#define _UNALLOCATED_RU_160_INFO_H_ - -#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1 - -struct unallocated_ru_160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t subband80_0_cc0 : 8, - subband80_0_cc1 : 8, - subband80_1_cc0 : 8, - subband80_1_cc1 : 8; -#else - uint32_t subband80_1_cc1 : 8, - subband80_1_cc0 : 8, - subband80_0_cc1 : 8, - subband80_0_cc0 : 8; -#endif -}; - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB 0 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB 7 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK 0x000000ff - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB 8 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB 15 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK 0x0000ff00 - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB 16 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB 23 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK 0x00ff0000 - -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET 0x00000000 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB 24 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB 31 -#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK 0xff000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/uniform_descriptor_header.h b/drivers/staging/fw-api/hw/wcn8750/v1/uniform_descriptor_header.h deleted file mode 100644 index 7a2de6ccd8df..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/uniform_descriptor_header.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ -#define _UNIFORM_DESCRIPTOR_HEADER_H_ - -#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 - -struct uniform_descriptor_header { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t owner : 4, - buffer_type : 4, - tx_mpdu_queue_number : 20, - reserved_0a : 4; -#else - uint32_t reserved_0a : 4, - tx_mpdu_queue_number : 20, - buffer_type : 4, - owner : 4; -#endif -}; - -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3 -#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f - -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 -#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 - -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 -#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 - -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_a_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_a_info.h deleted file mode 100644 index acd20f43949e..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_a_info.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_A_INFO_H_ -#define _VHT_SIG_A_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2 - -struct vht_sig_a_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t bandwidth : 2, - vhta_reserved_0 : 1, - stbc : 1, - group_id : 6, - n_sts : 12, - txop_ps_not_allowed : 1, - vhta_reserved_0b : 1, - reserved_0 : 8; - uint32_t gi_setting : 2, - su_mu_coding : 1, - ldpc_extra_symbol : 1, - mcs : 4, - beamformed : 1, - vhta_reserved_1 : 1, - crc : 8, - tail : 6, - reserved_1 : 7, - rx_integrity_check_passed : 1; -#else - uint32_t reserved_0 : 8, - vhta_reserved_0b : 1, - txop_ps_not_allowed : 1, - n_sts : 12, - group_id : 6, - stbc : 1, - vhta_reserved_0 : 1, - bandwidth : 2; - uint32_t rx_integrity_check_passed : 1, - reserved_1 : 7, - tail : 6, - crc : 8, - vhta_reserved_1 : 1, - beamformed : 1, - mcs : 4, - ldpc_extra_symbol : 1, - su_mu_coding : 1, - gi_setting : 2; -#endif -}; - -#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_BANDWIDTH_LSB 0 -#define VHT_SIG_A_INFO_BANDWIDTH_MSB 1 -#define VHT_SIG_A_INFO_BANDWIDTH_MASK 0x00000003 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB 2 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB 2 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK 0x00000004 - -#define VHT_SIG_A_INFO_STBC_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_STBC_LSB 3 -#define VHT_SIG_A_INFO_STBC_MSB 3 -#define VHT_SIG_A_INFO_STBC_MASK 0x00000008 - -#define VHT_SIG_A_INFO_GROUP_ID_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_GROUP_ID_LSB 4 -#define VHT_SIG_A_INFO_GROUP_ID_MSB 9 -#define VHT_SIG_A_INFO_GROUP_ID_MASK 0x000003f0 - -#define VHT_SIG_A_INFO_N_STS_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_N_STS_LSB 10 -#define VHT_SIG_A_INFO_N_STS_MSB 21 -#define VHT_SIG_A_INFO_N_STS_MASK 0x003ffc00 - -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB 22 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB 22 -#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB 23 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB 23 -#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK 0x00800000 - -#define VHT_SIG_A_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_A_INFO_RESERVED_0_LSB 24 -#define VHT_SIG_A_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_A_INFO_RESERVED_0_MASK 0xff000000 - -#define VHT_SIG_A_INFO_GI_SETTING_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_GI_SETTING_LSB 0 -#define VHT_SIG_A_INFO_GI_SETTING_MSB 1 -#define VHT_SIG_A_INFO_GI_SETTING_MASK 0x00000003 - -#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_SU_MU_CODING_LSB 2 -#define VHT_SIG_A_INFO_SU_MU_CODING_MSB 2 -#define VHT_SIG_A_INFO_SU_MU_CODING_MASK 0x00000004 - -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB 3 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB 3 -#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000008 - -#define VHT_SIG_A_INFO_MCS_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_MCS_LSB 4 -#define VHT_SIG_A_INFO_MCS_MSB 7 -#define VHT_SIG_A_INFO_MCS_MASK 0x000000f0 - -#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_BEAMFORMED_LSB 8 -#define VHT_SIG_A_INFO_BEAMFORMED_MSB 8 -#define VHT_SIG_A_INFO_BEAMFORMED_MASK 0x00000100 - -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB 9 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB 9 -#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK 0x00000200 - -#define VHT_SIG_A_INFO_CRC_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_CRC_LSB 10 -#define VHT_SIG_A_INFO_CRC_MSB 17 -#define VHT_SIG_A_INFO_CRC_MASK 0x0003fc00 - -#define VHT_SIG_A_INFO_TAIL_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_TAIL_LSB 18 -#define VHT_SIG_A_INFO_TAIL_MSB 23 -#define VHT_SIG_A_INFO_TAIL_MASK 0x00fc0000 - -#define VHT_SIG_A_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_RESERVED_1_LSB 24 -#define VHT_SIG_A_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_A_INFO_RESERVED_1_MASK 0x7f000000 - -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 -#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu160_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu160_info.h deleted file mode 100644 index 13931c5c3556..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu160_info.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU160_INFO_H_ -#define _VHT_SIG_B_MU160_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8 - -struct vht_sig_b_mu160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - mcs : 4, - tail : 6, - reserved_0 : 3; - uint32_t length_copy_a : 19, - mcs_copy_a : 4, - tail_copy_a : 6, - reserved_1 : 3; - uint32_t length_copy_b : 19, - mcs_copy_b : 4, - tail_copy_b : 6, - reserved_2 : 3; - uint32_t length_copy_c : 19, - mcs_copy_c : 4, - tail_copy_c : 6, - reserved_3 : 3; - uint32_t length_copy_d : 19, - mcs_copy_d : 4, - tail_copy_d : 6, - reserved_4 : 3; - uint32_t length_copy_e : 19, - mcs_copy_e : 4, - tail_copy_e : 6, - reserved_5 : 3; - uint32_t length_copy_f : 19, - mcs_copy_f : 4, - tail_copy_f : 6, - mu_user_number : 3; - uint32_t length_copy_g : 19, - mcs_copy_g : 4, - tail_copy_g : 6, - reserved_7 : 3; -#else - uint32_t reserved_0 : 3, - tail : 6, - mcs : 4, - length : 19; - uint32_t reserved_1 : 3, - tail_copy_a : 6, - mcs_copy_a : 4, - length_copy_a : 19; - uint32_t reserved_2 : 3, - tail_copy_b : 6, - mcs_copy_b : 4, - length_copy_b : 19; - uint32_t reserved_3 : 3, - tail_copy_c : 6, - mcs_copy_c : 4, - length_copy_c : 19; - uint32_t reserved_4 : 3, - tail_copy_d : 6, - mcs_copy_d : 4, - length_copy_d : 19; - uint32_t reserved_5 : 3, - tail_copy_e : 6, - mcs_copy_e : 4, - length_copy_e : 19; - uint32_t mu_user_number : 3, - tail_copy_f : 6, - mcs_copy_f : 4, - length_copy_f : 19; - uint32_t reserved_7 : 3, - tail_copy_g : 6, - mcs_copy_g : 4, - length_copy_g : 19; -#endif -}; - -#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_MCS_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_TAIL_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET 0x00000010 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET 0x00000014 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET 0x00000018 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB 0 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB 18 -#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK 0x0007ffff - -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB 19 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB 22 -#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK 0x00780000 - -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB 23 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB 28 -#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK 0x1f800000 - -#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET 0x0000001c -#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB 29 -#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB 31 -#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu20_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu20_info.h deleted file mode 100644 index c51ac839a757..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu20_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU20_INFO_H_ -#define _VHT_SIG_B_MU20_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1 - -struct vht_sig_b_mu20_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 16, - mcs : 4, - tail : 6, - mu_user_number : 3, - reserved_0 : 3; -#else - uint32_t reserved_0 : 3, - mu_user_number : 3, - tail : 6, - mcs : 4, - length : 16; -#endif -}; - -#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU20_INFO_LENGTH_MSB 15 -#define VHT_SIG_B_MU20_INFO_LENGTH_MASK 0x0000ffff - -#define VHT_SIG_B_MU20_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_MCS_LSB 16 -#define VHT_SIG_B_MU20_INFO_MCS_MSB 19 -#define VHT_SIG_B_MU20_INFO_MCS_MASK 0x000f0000 - -#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_TAIL_LSB 20 -#define VHT_SIG_B_MU20_INFO_TAIL_MSB 25 -#define VHT_SIG_B_MU20_INFO_TAIL_MASK 0x03f00000 - -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB 26 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB 28 -#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK 0x1c000000 - -#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu40_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu40_info.h deleted file mode 100644 index 0eb4c164cca1..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu40_info.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU40_INFO_H_ -#define _VHT_SIG_B_MU40_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2 - -struct vht_sig_b_mu40_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 17, - mcs : 4, - tail : 6, - reserved_0 : 2, - mu_user_number : 3; - uint32_t length_copy : 17, - mcs_copy : 4, - tail_copy : 6, - reserved_1 : 5; -#else - uint32_t mu_user_number : 3, - reserved_0 : 2, - tail : 6, - mcs : 4, - length : 17; - uint32_t reserved_1 : 5, - tail_copy : 6, - mcs_copy : 4, - length_copy : 17; -#endif -}; - -#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU40_INFO_LENGTH_MSB 16 -#define VHT_SIG_B_MU40_INFO_LENGTH_MASK 0x0001ffff - -#define VHT_SIG_B_MU40_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_MCS_LSB 17 -#define VHT_SIG_B_MU40_INFO_MCS_MSB 20 -#define VHT_SIG_B_MU40_INFO_MCS_MASK 0x001e0000 - -#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_TAIL_LSB 21 -#define VHT_SIG_B_MU40_INFO_TAIL_MSB 26 -#define VHT_SIG_B_MU40_INFO_TAIL_MASK 0x07e00000 - -#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB 27 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB 28 -#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK 0x18000000 - -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET 0x00000000 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB 0 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB 16 -#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK 0x0001ffff - -#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB 17 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB 20 -#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK 0x001e0000 - -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB 21 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB 26 -#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK 0x07e00000 - -#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB 27 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK 0xf8000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu80_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu80_info.h deleted file mode 100644 index 33d0f1bc08fc..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_mu80_info.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_MU80_INFO_H_ -#define _VHT_SIG_B_MU80_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4 - -struct vht_sig_b_mu80_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - mcs : 4, - tail : 6, - reserved_0 : 3; - uint32_t length_copy_a : 19, - mcs_copy_a : 4, - tail_copy_a : 6, - reserved_1 : 3; - uint32_t length_copy_b : 19, - mcs_copy_b : 4, - tail_copy_b : 6, - mu_user_number : 3; - uint32_t length_copy_c : 19, - mcs_copy_c : 4, - tail_copy_c : 6, - reserved_3 : 3; -#else - uint32_t reserved_0 : 3, - tail : 6, - mcs : 4, - length : 19; - uint32_t reserved_1 : 3, - tail_copy_a : 6, - mcs_copy_a : 4, - length_copy_a : 19; - uint32_t mu_user_number : 3, - tail_copy_b : 6, - mcs_copy_b : 4, - length_copy_b : 19; - uint32_t reserved_3 : 3, - tail_copy_c : 6, - mcs_copy_c : 4, - length_copy_c : 19; -#endif -}; - -#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_MCS_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_TAIL_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET 0x00000008 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB 29 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB 31 -#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK 0xe0000000 - -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB 18 -#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK 0x0007ffff - -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB 19 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB 22 -#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK 0x00780000 - -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB 31 -#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK 0xe0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su160_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su160_info.h deleted file mode 100644 index 7ba503724b56..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su160_info.h +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU160_INFO_H_ -#define _VHT_SIG_B_SU160_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8 - -struct vht_sig_b_su160_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 21, - vhtb_reserved : 2, - tail : 6, - reserved_0 : 2, - rx_ndp : 1; - uint32_t length_copy_a : 21, - vhtb_reserved_copy_a : 2, - tail_copy_a : 6, - reserved_1 : 2, - rx_ndp_copy_a : 1; - uint32_t length_copy_b : 21, - vhtb_reserved_copy_b : 2, - tail_copy_b : 6, - reserved_2 : 2, - rx_ndp_copy_b : 1; - uint32_t length_copy_c : 21, - vhtb_reserved_copy_c : 2, - tail_copy_c : 6, - reserved_3 : 2, - rx_ndp_copy_c : 1; - uint32_t length_copy_d : 21, - vhtb_reserved_copy_d : 2, - tail_copy_d : 6, - reserved_4 : 2, - rx_ndp_copy_d : 1; - uint32_t length_copy_e : 21, - vhtb_reserved_copy_e : 2, - tail_copy_e : 6, - reserved_5 : 2, - rx_ndp_copy_e : 1; - uint32_t length_copy_f : 21, - vhtb_reserved_copy_f : 2, - tail_copy_f : 6, - reserved_6 : 2, - rx_ndp_copy_f : 1; - uint32_t length_copy_g : 21, - vhtb_reserved_copy_g : 2, - tail_copy_g : 6, - reserved_7 : 2, - rx_ndp_copy_g : 1; -#else - uint32_t rx_ndp : 1, - reserved_0 : 2, - tail : 6, - vhtb_reserved : 2, - length : 21; - uint32_t rx_ndp_copy_a : 1, - reserved_1 : 2, - tail_copy_a : 6, - vhtb_reserved_copy_a : 2, - length_copy_a : 21; - uint32_t rx_ndp_copy_b : 1, - reserved_2 : 2, - tail_copy_b : 6, - vhtb_reserved_copy_b : 2, - length_copy_b : 21; - uint32_t rx_ndp_copy_c : 1, - reserved_3 : 2, - tail_copy_c : 6, - vhtb_reserved_copy_c : 2, - length_copy_c : 21; - uint32_t rx_ndp_copy_d : 1, - reserved_4 : 2, - tail_copy_d : 6, - vhtb_reserved_copy_d : 2, - length_copy_d : 21; - uint32_t rx_ndp_copy_e : 1, - reserved_5 : 2, - tail_copy_e : 6, - vhtb_reserved_copy_e : 2, - length_copy_e : 21; - uint32_t rx_ndp_copy_f : 1, - reserved_6 : 2, - tail_copy_f : 6, - vhtb_reserved_copy_f : 2, - length_copy_f : 21; - uint32_t rx_ndp_copy_g : 1, - reserved_7 : 2, - tail_copy_g : 6, - vhtb_reserved_copy_g : 2, - length_copy_g : 21; -#endif -}; - -#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_TAIL_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET 0x00000010 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET 0x00000014 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET 0x00000018 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK 0x80000000 - -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB 0 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB 20 -#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK 0x001fffff - -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB 21 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB 22 -#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK 0x00600000 - -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB 23 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB 28 -#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK 0x1f800000 - -#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB 29 -#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB 30 -#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK 0x60000000 - -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET 0x0000001c -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB 31 -#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su20_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su20_info.h deleted file mode 100644 index 2c7f11ba3c21..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su20_info.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU20_INFO_H_ -#define _VHT_SIG_B_SU20_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1 - -struct vht_sig_b_su20_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 17, - vhtb_reserved : 3, - tail : 6, - reserved : 5, - rx_ndp : 1; -#else - uint32_t rx_ndp : 1, - reserved : 5, - tail : 6, - vhtb_reserved : 3, - length : 17; -#endif -}; - -#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU20_INFO_LENGTH_MSB 16 -#define VHT_SIG_B_SU20_INFO_LENGTH_MASK 0x0001ffff - -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB 17 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB 19 -#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK 0x000e0000 - -#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_TAIL_LSB 20 -#define VHT_SIG_B_SU20_INFO_TAIL_MSB 25 -#define VHT_SIG_B_SU20_INFO_TAIL_MASK 0x03f00000 - -#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_RESERVED_LSB 26 -#define VHT_SIG_B_SU20_INFO_RESERVED_MSB 30 -#define VHT_SIG_B_SU20_INFO_RESERVED_MASK 0x7c000000 - -#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su40_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su40_info.h deleted file mode 100644 index 467259003e8d..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su40_info.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU40_INFO_H_ -#define _VHT_SIG_B_SU40_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2 - -struct vht_sig_b_su40_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 19, - vhtb_reserved : 2, - tail : 6, - reserved : 4, - rx_ndp : 1; - uint32_t length_copy : 19, - vhtb_reserved_copy : 2, - tail_copy : 6, - reserved_copy : 4, - rx_ndp_copy : 1; -#else - uint32_t rx_ndp : 1, - reserved : 4, - tail : 6, - vhtb_reserved : 2, - length : 19; - uint32_t rx_ndp_copy : 1, - reserved_copy : 4, - tail_copy : 6, - vhtb_reserved_copy : 2, - length_copy : 19; -#endif -}; - -#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU40_INFO_LENGTH_MSB 18 -#define VHT_SIG_B_SU40_INFO_LENGTH_MASK 0x0007ffff - -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB 19 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB 20 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK 0x00180000 - -#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_TAIL_LSB 21 -#define VHT_SIG_B_SU40_INFO_TAIL_MSB 26 -#define VHT_SIG_B_SU40_INFO_TAIL_MASK 0x07e00000 - -#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_RESERVED_LSB 27 -#define VHT_SIG_B_SU40_INFO_RESERVED_MSB 30 -#define VHT_SIG_B_SU40_INFO_RESERVED_MASK 0x78000000 - -#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB 0 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB 18 -#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK 0x0007ffff - -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB 19 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB 20 -#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK 0x00180000 - -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB 21 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB 26 -#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK 0x07e00000 - -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB 27 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB 30 -#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK 0x78000000 - -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET 0x00000004 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB 31 -#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su80_info.h b/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su80_info.h deleted file mode 100644 index 92ceeab9b476..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/vht_sig_b_su80_info.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _VHT_SIG_B_SU80_INFO_H_ -#define _VHT_SIG_B_SU80_INFO_H_ - -#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4 - -struct vht_sig_b_su80_info { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t length : 21, - vhtb_reserved : 2, - tail : 6, - reserved_0 : 2, - rx_ndp : 1; - uint32_t length_copy_a : 21, - vhtb_reserved_copy_a : 2, - tail_copy_a : 6, - reserved_1 : 2, - rx_ndp_copy_a : 1; - uint32_t length_copy_b : 21, - vhtb_reserved_copy_b : 2, - tail_copy_b : 6, - reserved_2 : 2, - rx_ndp_copy_b : 1; - uint32_t length_copy_c : 21, - vhtb_reserved_copy_c : 2, - tail_copy_c : 6, - reserved_3 : 2, - rx_ndp_copy_c : 1; -#else - uint32_t rx_ndp : 1, - reserved_0 : 2, - tail : 6, - vhtb_reserved : 2, - length : 21; - uint32_t rx_ndp_copy_a : 1, - reserved_1 : 2, - tail_copy_a : 6, - vhtb_reserved_copy_a : 2, - length_copy_a : 21; - uint32_t rx_ndp_copy_b : 1, - reserved_2 : 2, - tail_copy_b : 6, - vhtb_reserved_copy_b : 2, - length_copy_b : 21; - uint32_t rx_ndp_copy_c : 1, - reserved_3 : 2, - tail_copy_c : 6, - vhtb_reserved_copy_c : 2, - length_copy_c : 21; -#endif -}; - -#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_LENGTH_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_TAIL_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET 0x00000000 -#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK 0x80000000 - -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB 0 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB 20 -#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK 0x001fffff - -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB 21 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB 22 -#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 - -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB 23 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB 28 -#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK 0x1f800000 - -#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB 29 -#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB 30 -#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK 0x60000000 - -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB 31 -#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK 0x80000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wbm2sw_completion_ring_rx.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm2sw_completion_ring_rx.h deleted file mode 100644 index e40a7e796a87..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wbm2sw_completion_ring_rx.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM2SW_COMPLETION_RING_RX_H_ -#define _WBM2SW_COMPLETION_RING_RX_H_ - -#include "rx_msdu_desc_info.h" -#include "rx_mpdu_desc_info.h" -#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 - -struct wbm2sw_completion_ring_rx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t release_source_module : 3, - bm_action : 3, - buffer_or_desc_type : 3, - return_buffer_manager : 4, - reserved_2a : 2, - cache_id : 1, - cookie_conversion_status : 1, - rxdma_push_reason : 2, - rxdma_error_code : 5, - reo_push_reason : 2, - reo_error_code : 5, - wbm_internal_error : 1; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t buffer_phys_addr_31_0 : 32; - uint32_t buffer_phys_addr_39_32 : 8, - sw_buffer_cookie : 20, - looping_count : 4; -#else - uint32_t buffer_virt_addr_31_0 : 32; - uint32_t buffer_virt_addr_63_32 : 32; - uint32_t wbm_internal_error : 1, - reo_error_code : 5, - reo_push_reason : 2, - rxdma_error_code : 5, - rxdma_push_reason : 2, - cookie_conversion_status : 1, - cache_id : 1, - reserved_2a : 2, - return_buffer_manager : 4, - buffer_or_desc_type : 3, - bm_action : 3, - release_source_module : 3; - struct rx_mpdu_desc_info rx_mpdu_desc_info_details; - struct rx_msdu_desc_info rx_msdu_desc_info_details; - uint32_t buffer_phys_addr_31_0 : 32; - uint32_t looping_count : 4, - sw_buffer_cookie : 20, - buffer_phys_addr_39_32 : 8; -#endif -}; - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 -#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 -#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 - -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 -#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 - -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 -#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 - -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 -#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 - -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 - -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 -#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 - -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 -#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 - -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 -#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 - -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 - -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 -#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff - -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 -#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff - -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 -#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 - -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 -#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_buffer_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm_buffer_ring.h deleted file mode 100644 index b1532e15595b..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_buffer_ring.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_BUFFER_RING_H_ -#define _WBM_BUFFER_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 - -struct wbm_buffer_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info buf_addr_info; -#else - struct buffer_addr_info buf_addr_info; -#endif -}; - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_link_descriptor_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm_link_descriptor_ring.h deleted file mode 100644 index 851807aa4c1c..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_link_descriptor_ring.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ -#define _WBM_LINK_DESCRIPTOR_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 - -struct wbm_link_descriptor_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info desc_addr_info; -#else - struct buffer_addr_info desc_addr_info; -#endif -}; - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring.h deleted file mode 100644 index e86d52753912..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_H_ -#define _WBM_RELEASE_RING_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 - -struct wbm_release_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - reserved_2a : 3, - buffer_or_desc_type : 3, - reserved_2b : 22, - wbm_internal_error : 1; - uint32_t reserved_3a : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_5a : 32; - uint32_t reserved_6a : 32; - uint32_t reserved_7a : 28, - looping_count : 4; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t wbm_internal_error : 1, - reserved_2b : 22, - buffer_or_desc_type : 3, - reserved_2a : 3, - release_source_module : 3; - uint32_t reserved_3a : 32; - uint32_t reserved_4a : 32; - uint32_t reserved_5a : 32; - uint32_t reserved_6a : 32; - uint32_t looping_count : 4, - reserved_7a : 28; -#endif -}; - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RESERVED_2A_LSB 3 -#define WBM_RELEASE_RING_RESERVED_2A_MSB 5 -#define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 - -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 -#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 - -#define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RESERVED_2B_LSB 9 -#define WBM_RELEASE_RING_RESERVED_2B_MSB 30 -#define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 - -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 -#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 - -#define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c -#define WBM_RELEASE_RING_RESERVED_3A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_3A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 -#define WBM_RELEASE_RING_RESERVED_4A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_4A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 -#define WBM_RELEASE_RING_RESERVED_5A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_5A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 -#define WBM_RELEASE_RING_RESERVED_6A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_6A_MSB 31 -#define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff - -#define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c -#define WBM_RELEASE_RING_RESERVED_7A_LSB 0 -#define WBM_RELEASE_RING_RESERVED_7A_MSB 27 -#define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff - -#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c -#define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 -#define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 -#define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring_rx.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring_rx.h deleted file mode 100644 index a68bc8115a82..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring_rx.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_RX_H_ -#define _WBM_RELEASE_RING_RX_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 4 - -struct wbm_release_ring_rx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - buffer_or_desc_type : 3, - reserved_2a : 14, - mpdu_sequence_number : 12; - uint32_t reserved_3a : 32; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t mpdu_sequence_number : 12, - reserved_2a : 14, - buffer_or_desc_type : 3, - release_source_module : 3; - uint32_t reserved_3a : 32; -#endif -}; - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB 3 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB 5 -#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x00000038 - -#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB 6 -#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB 19 -#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK 0x000fffc0 - -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_LSB 20 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MSB 31 -#define WBM_RELEASE_RING_RX_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 - -#define WBM_RELEASE_RING_RX_RESERVED_3A_OFFSET 0x0000000c -#define WBM_RELEASE_RING_RX_RESERVED_3A_LSB 0 -#define WBM_RELEASE_RING_RX_RESERVED_3A_MSB 31 -#define WBM_RELEASE_RING_RX_RESERVED_3A_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring_tx.h b/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring_tx.h deleted file mode 100644 index d1412153c6ae..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wbm_release_ring_tx.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef _WBM_RELEASE_RING_TX_H_ -#define _WBM_RELEASE_RING_TX_H_ - -#include "buffer_addr_info.h" -#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 4 - -struct wbm_release_ring_tx { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t release_source_module : 3, - buffer_or_desc_type : 3, - reserved_2a : 26; - uint32_t tqm_status_number : 32; -#else - struct buffer_addr_info released_buff_or_desc_addr_info; - uint32_t reserved_2a : 26, - buffer_or_desc_type : 3, - release_source_module : 3; - uint32_t tqm_status_number : 32; -#endif -}; - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 - -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 -#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 - -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 -#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 - -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 3 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 5 -#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x00000038 - -#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008 -#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 6 -#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 31 -#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0xffffffc0 - -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0 -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 31 -#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0xffffffff - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwiobase.h b/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwiobase.h deleted file mode 100644 index 4e455f399300..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwiobase.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef WCSS_SEQ_HWIOBASE_H -#define WCSS_SEQ_HWIOBASE_H - -#define UMAC_NOC_BASE 0x140000 -#define UMAC_NOC_BASE_SIZE 0x00004480 -#define UMAC_NOC_BASE_PHYS 0x00140000 - -#define PHYA0_BASE 0x300000 -#define PHYA0_BASE_SIZE 0x00300000 -#define PHYA0_BASE_PHYS 0x00300000 - -#define PHYA1_BASE 0x600000 -#define PHYA1_BASE_SIZE 0x00300000 -#define PHYA1_BASE_PHYS 0x00600000 - -#define DMAC_BASE 0x900000 -#define DMAC_BASE_SIZE 0x00080000 -#define DMAC_BASE_PHYS 0x00900000 - -#define UMAC_BASE 0xa00000 -#define UMAC_BASE_SIZE 0x0004d000 -#define UMAC_BASE_PHYS 0x00a00000 - -#define PMAC0_BASE 0xa80000 -#define PMAC0_BASE_SIZE 0x00040000 -#define PMAC0_BASE_PHYS 0x00a80000 - -#define PMAC1_BASE 0xac0000 -#define PMAC1_BASE_SIZE 0x00040000 -#define PMAC1_BASE_PHYS 0x00ac0000 - -#define WFSS_AMCSS_BASE 0xb00000 -#define WFSS_AMCSS_BASE_SIZE 0x00040000 -#define WFSS_AMCSS_BASE_PHYS 0x00b00000 - -#define CXC_BASE 0xb40000 -#define CXC_BASE_SIZE 0x00010000 -#define CXC_BASE_PHYS 0x00b40000 - -#define WFSS_PMM_BASE 0xb50000 -#define WFSS_PMM_BASE_SIZE 0x00002401 -#define WFSS_PMM_BASE_PHYS 0x00b50000 - -#define WFSS_CC_BASE 0xb60000 -#define WFSS_CC_BASE_SIZE 0x00008000 -#define WFSS_CC_BASE_PHYS 0x00b60000 - -#define WCMN_CORE_BASE 0xb68000 -#define WCMN_CORE_BASE_SIZE 0x000008a9 -#define WCMN_CORE_BASE_PHYS 0x00b68000 - -#define WIFI_CFGBUS_APB_TSLV_BASE 0xb6b000 -#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE 0x00001000 -#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS 0x00b6b000 - -#define WFSS_CFGBUS_BASE 0xb6c000 -#define WFSS_CFGBUS_BASE_SIZE 0x000000a0 -#define WFSS_CFGBUS_BASE_PHYS 0x00b6c000 - -#define WIFI_CFGBUS_AHB_TSLV_BASE 0xb6d000 -#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE 0x00001000 -#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS 0x00b6d000 - -#define UMAC_ACMT_BASE 0xb6e000 -#define UMAC_ACMT_BASE_SIZE 0x00001000 -#define UMAC_ACMT_BASE_PHYS 0x00b6e000 - -#define WCSS_CC_BASE 0xb80000 -#define WCSS_CC_BASE_SIZE 0x00010000 -#define WCSS_CC_BASE_PHYS 0x00b80000 - -#define PMM_TOP_BASE 0xb90000 -#define PMM_TOP_BASE_SIZE 0x00010000 -#define PMM_TOP_BASE_PHYS 0x00b90000 - -#define WCSS_TOP_CMN_BASE 0xba0000 -#define WCSS_TOP_CMN_BASE_SIZE 0x00004000 -#define WCSS_TOP_CMN_BASE_PHYS 0x00ba0000 - -#define WCSS_CFGBUS_BASE 0xba4000 -#define WCSS_CFGBUS_BASE_SIZE 0x00008000 -#define WCSS_CFGBUS_BASE_PHYS 0x00ba4000 - -#define MSIP_BASE 0xbb0000 -#define MSIP_BASE_SIZE 0x00010000 -#define MSIP_BASE_PHYS 0x00bb0000 - -#define RFA_BASE 0xbc0000 -#define RFA_BASE_SIZE 0x00040000 -#define RFA_BASE_PHYS 0x00bc0000 - -#define DBG_BASE 0x1000000 -#define DBG_BASE_SIZE 0x00100000 -#define DBG_BASE_PHYS 0x01000000 - -#define Q6SS_WLAN_BASE 0x1100000 -#define Q6SS_WLAN_BASE_SIZE 0x00100000 -#define Q6SS_WLAN_BASE_PHYS 0x01100000 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwioreg_umac.h b/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwioreg_umac.h deleted file mode 100644 index 60d2a0b5099f..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwioreg_umac.h +++ /dev/null @@ -1,13579 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef WCSS_SEQ_HWIOREG_UMAC_H -#define WCSS_SEQ_HWIOREG_UMAC_H - -#include "seq_hwio.h" -#include "wcss_seq_hwiobase.h" -#ifdef SCALE_INCLUDES -#include "HALhwio.h" -#else -#include "msmhwio.h" -#endif - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDR(x) ((x) + 0x1c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_PHYS(x) ((x) + 0x1c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_OFFS (0x1c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDRESS_RANGE_LIMIT_BMSK 0xc0000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ADDRESS_RANGE_LIMIT_SHFT 30 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_WINDOW_SIZE_BMSK 0x38000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_WINDOW_SIZE_SHFT 27 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_RESET_CNT_BMSK 0x4000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_RESET_CNT_SHFT 26 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_CNTR_EN_BMSK 0x2000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_CNTR_EN_SHFT 25 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ID_BITMAP_BMSK 0x1ffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_0_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n) ((base) + 0X20 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_PHYS(base,n) ((base) + 0X20 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_OFFS(n) (0X20 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ID_BITMAP_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_0_IX_n_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_ADDR(x) ((x) + 0x30) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_PHYS(x) ((x) + 0x30) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_OFFS (0x30) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_0_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_ADDR(x) ((x) + 0x34) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_PHYS(x) ((x) + 0x34) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_OFFS (0x34) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_0_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDR(x) ((x) + 0x38) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_PHYS(x) ((x) + 0x38) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_OFFS (0x38) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDRESS_RANGE_LIMIT_BMSK 0xc0000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ADDRESS_RANGE_LIMIT_SHFT 30 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_WINDOW_SIZE_BMSK 0x38000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_WINDOW_SIZE_SHFT 27 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_RESET_CNT_BMSK 0x4000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_RESET_CNT_SHFT 26 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_CNTR_EN_BMSK 0x2000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_CNTR_EN_SHFT 25 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ID_BITMAP_BMSK 0x1ffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_1_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n) ((base) + 0X3C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_PHYS(base,n) ((base) + 0X3C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_OFFS(n) (0X3C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ID_BITMAP_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_1_IX_n_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_ADDR(x) ((x) + 0x4c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_PHYS(x) ((x) + 0x4c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_OFFS (0x4c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_1_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_ADDR(x) ((x) + 0x50) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_PHYS(x) ((x) + 0x50) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_OFFS (0x50) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_1_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDR(x) ((x) + 0x54) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_PHYS(x) ((x) + 0x54) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_OFFS (0x54) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDRESS_RANGE_LIMIT_BMSK 0xc0000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ADDRESS_RANGE_LIMIT_SHFT 30 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_WINDOW_SIZE_BMSK 0x38000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_WINDOW_SIZE_SHFT 27 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_RESET_CNT_BMSK 0x4000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_RESET_CNT_SHFT 26 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_CNTR_EN_BMSK 0x2000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_CNTR_EN_SHFT 25 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ID_BITMAP_BMSK 0x1ffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_2_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ADDR(base,n) ((base) + 0X58 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_PHYS(base,n) ((base) + 0X58 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_OFFS(n) (0X58 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ID_BITMAP_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_2_IX_n_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_ADDR(x) ((x) + 0x68) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_PHYS(x) ((x) + 0x68) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_OFFS (0x68) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_2_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_ADDR(x) ((x) + 0x6c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_PHYS(x) ((x) + 0x6c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_OFFS (0x6c) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_2_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDR(x) ((x) + 0x70) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_PHYS(x) ((x) + 0x70) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_OFFS (0x70) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDRESS_RANGE_LIMIT_BMSK 0xc0000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ADDRESS_RANGE_LIMIT_SHFT 30 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_WINDOW_SIZE_BMSK 0x38000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_WINDOW_SIZE_SHFT 27 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_RESET_CNT_BMSK 0x4000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_RESET_CNT_SHFT 26 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_CNTR_EN_BMSK 0x2000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_CNTR_EN_SHFT 25 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ID_BITMAP_BMSK 0x1ffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_CFG_3_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ADDR(base,n) ((base) + 0X74 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_PHYS(base,n) ((base) + 0X74 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_OFFS(n) (0X74 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ID_BITMAP_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_ID_CFG_3_IX_n_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_ADDR(x) ((x) + 0x84) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_PHYS(x) ((x) + 0x84) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_OFFS (0x84) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_CNTR_VAL_3_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_ADDR(x) ((x) + 0x88) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_PHYS(x) ((x) + 0x88) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_OFFS (0x88) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_PERF_TXN_CTR_3_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n) ((base) + 0X94 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_PHYS(base,n) ((base) + 0X94 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_OFFS(n) (0X94 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ID_BITMAP_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_n_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n) ((base) + 0XB0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_PHYS(base,n) ((base) + 0XB0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_OFFS(n) (0XB0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ID_BITMAP_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_n_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x) ((x) + 0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x) ((x) + 0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS (0xc8) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK 0x7 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK 0x7 -#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x) ((x) + 0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x) ((x) + 0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS (0xcc) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK 0x1ffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR 0x00001ffe -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK 0x1ffe000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT 13 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK 0x1ffe -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT 1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK 0x1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT 0 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_DATA_FIFORAM_BMSK 0x2000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_DATA_FIFORAM_SHFT 13 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK 0x1000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT 12 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK 0x800 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT 11 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK 0x400 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT 10 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK 0x200 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT 9 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x) ((x) + 0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x) ((x) + 0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS (0x100) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK 0xff000000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT 24 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK 0xff0000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT 16 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK 0xff00 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT 8 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK 0xff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT 0 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_SNAPSHOT_ENABLE_BMSK 0x2 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_SNAPSHOT_ENABLE_SHFT 1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ADDR(base,n) ((base) + 0X138 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_PHYS(base,n) ((base) + 0X138 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_OFFS(n) (0X138 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_n_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ADDR(base,n) ((base) + 0X14C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_PHYS(base,n) ((base) + 0X14C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_OFFS(n) (0X14C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_n_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_FREEZE_EN_BMSK 0x40000000 -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_FREEZE_EN_SHFT 30 -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ADDR(base,n) ((base) + 0X1B8 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_PHYS(base,n) ((base) + 0X1B8 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_OFFS(n) (0X1B8 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ID_BITMAP_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_n_ID_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n) ((base) + 0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_PHYS(base,n) ((base) + 0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_OFFS(n) (0X2D0 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK 0xfff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_MAXn 31 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_BMSK 0xfff -#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_SHFT 0 - -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x) ((x) + 0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_PHYS(x) ((x) + 0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OFFS (0x360) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_RMSK 0x3 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x)) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x)) -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_BMSK 0x2 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_SHFT 1 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_BMSK 0x1 -#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ADDR(base,n) ((base) + 0X364 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_PHYS(base,n) ((base) + 0X364 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_OFFS(n) (0X364 + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_POR 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WRITE_EVENTS_BITMAP_IX_n_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ADDR(base,n) ((base) + 0X36C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_PHYS(base,n) ((base) + 0X36C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_OFFS(n) (0X36C + (0x4*(n))) -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_MAXn 1 -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_POR 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_OUTI(base,n,val) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ADDR(base,n),val) -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_ADDR(base,n),mask,val,HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_INI(base,n)) -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_VALUE_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_READ_EVENTS_BITMAP_IX_n_VALUE_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_ADDR(x) ((x) + 0x374) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_PHYS(x) ((x) + 0x374) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_OFFS (0x374) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_RMSK 0xffffff7f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_POR 0x7ffff07f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWVALID_BMSK 0x80000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWVALID_SHFT 31 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWADDR_22_4_BMSK 0x7ffff000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWADDR_22_4_SHFT 12 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWREADY_BMSK 0x800 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_AWREADY_SHFT 11 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WVALID_BMSK 0x400 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WVALID_SHFT 10 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WREADY_BMSK 0x200 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WREADY_SHFT 9 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WLAST_BMSK 0x100 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_WLAST_SHFT 8 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_BID_BMSK 0x7f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_0_AXI_WR_IF_BID_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_ADDR(x) ((x) + 0x378) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_PHYS(x) ((x) + 0x378) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_OFFS (0x378) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_REM_ADDR_WCOUNT_BMSK 0xfff80000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_REM_ADDR_WCOUNT_SHFT 19 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_REM_DATA_WCOUNT_BMSK 0x7ffc0 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_REM_DATA_WCOUNT_SHFT 6 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_AXI_PENDING_CNT_BMSK 0x3f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_1_WR_AXI_PENDING_CNT_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_ADDR(x) ((x) + 0x37c) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_PHYS(x) ((x) + 0x37c) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_OFFS (0x37c) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_RMSK 0x7fffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_POR 0x00000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_PREFIL_CNT_BMSK 0x70000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_PREFIL_CNT_SHFT 28 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_WR_BMSK 0x8000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_WR_SHFT 27 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_WR_ADDR_BMSK 0x7e00000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_WR_ADDR_SHFT 21 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_RD_BMSK 0x100000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_RD_SHFT 20 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_RD_ADDR_BMSK 0xfc000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_CMD_FIFO_RD_ADDR_SHFT 14 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_WR_BMSK 0x2000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_WR_SHFT 13 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_WR_ADDR_BMSK 0x1f80 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_WR_ADDR_SHFT 7 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_RD_BMSK 0x40 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_RD_SHFT 6 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_RD_ADDR_BMSK 0x3f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_2_WR_DATA_FIFO_RD_ADDR_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_ADDR(x) ((x) + 0x380) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_PHYS(x) ((x) + 0x380) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_OFFS (0x380) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_RMSK 0x1ffff7f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_POR 0x00044f7f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_STATE_BMSK 0x1fc0000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_STATE_SHFT 18 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_ADDR_STATE_BMSK 0x3c000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_ADDR_STATE_SHFT 14 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_FLUSH_DONE_BMSK 0x2000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_FLUSH_DONE_SHFT 13 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_FLUSH_BMSK 0x1000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_FLUSH_SHFT 12 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_PHASE_SUBID_BMSK 0xf00 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_PHASE_SUBID_SHFT 8 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_PHASE_ID_BMSK 0x7f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_3_WR_DATA_PHASE_ID_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_ADDR(x) ((x) + 0x384) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_PHYS(x) ((x) + 0x384) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_OFFS (0x384) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_POR 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_WR_DATA_PHASE_ADDR_31_0_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_4_WR_DATA_PHASE_ADDR_31_0_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_ADDR(x) ((x) + 0x388) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_PHYS(x) ((x) + 0x388) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_OFFS (0x388) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_RMSK 0x1fffff7f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_POR 0x00e04f7f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_AXI_WR_IF_BRESP_BMSK 0x18000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_AXI_WR_IF_BRESP_SHFT 27 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_AXI_WR_IF_BVALID_BMSK 0x4000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_AXI_WR_IF_BVALID_SHFT 26 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_MAX_OT_REACHED_BMSK 0x2000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_MAX_OT_REACHED_SHFT 25 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_GXI_BACKPRESSURE_BMSK 0x1000000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_GXI_BACKPRESSURE_SHFT 24 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_GXI_IDLE_BMSK 0x800000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_GXI_IDLE_SHFT 23 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_DATA_IDLE_BMSK 0x400000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_DATA_IDLE_SHFT 22 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_IDLE_BMSK 0x200000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_IDLE_SHFT 21 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_AXI_PENDING_CNT_DATA_BMSK 0x1f8000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_AXI_PENDING_CNT_DATA_SHFT 15 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_CMD_FIFO_EMPTY_BMSK 0x4000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_CMD_FIFO_EMPTY_SHFT 14 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_CMD_FIFO_FULL_BMSK 0x2000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_CMD_FIFO_FULL_SHFT 13 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_DATA_FIFO_FULL_BMSK 0x1000 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_DATA_FIFO_FULL_SHFT 12 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_PHASE_SUBID_BMSK 0xf00 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_PHASE_SUBID_SHFT 8 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_PHASE_ID_BMSK 0x7f -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_5_WR_ADDR_PHASE_ID_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_ADDR(x) ((x) + 0x38c) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_PHYS(x) ((x) + 0x38c) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_OFFS (0x38c) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_POR 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_WR_ADDR_PHASE_ADDR_31_0_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_WR_WDOG_SNAPSHOT_IX_6_WR_ADDR_PHASE_ADDR_31_0_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_ADDR(x) ((x) + 0x390) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_PHYS(x) ((x) + 0x390) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_OFFS (0x390) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_RMSK 0xffffff7f -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_POR 0x7ffff07f -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARVALID_BMSK 0x80000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARVALID_SHFT 31 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARADDR_22_4_BMSK 0x7ffff000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARADDR_22_4_SHFT 12 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARREADY_BMSK 0x800 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_ARREADY_SHFT 11 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RVALID_BMSK 0x400 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RVALID_SHFT 10 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RREADY_BMSK 0x200 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RREADY_SHFT 9 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RLAST_BMSK 0x100 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RLAST_SHFT 8 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RID_BMSK 0x7f -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_0_AXI_RD_IF_RID_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_ADDR(x) ((x) + 0x394) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_PHYS(x) ((x) + 0x394) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_OFFS (0x394) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RMSK 0xfffff7ff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_POR 0x800007ff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_DATA_FIFO_EMPTY_BMSK 0x80000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_DATA_FIFO_EMPTY_SHFT 31 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_DATA_FIFO_FULL_BMSK 0x40000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_DATA_FIFO_FULL_SHFT 30 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_REM_ADDR_WCOUNT_BMSK 0x3ffc0000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_REM_ADDR_WCOUNT_SHFT 18 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_AXI_PENDING_CNT_BMSK 0x3f000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_AXI_PENDING_CNT_SHFT 12 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_CMD_FIFO_RDATA_ID_BMSK 0x7f0 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_CMD_FIFO_RDATA_ID_SHFT 4 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_CMD_FIFO_RDATA_SUB_ID_BMSK 0xf -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_1_RD_CMD_FIFO_RDATA_SUB_ID_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_ADDR(x) ((x) + 0x398) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_PHYS(x) ((x) + 0x398) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_OFFS (0x398) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_POR 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_RD_CMD_FIFO_RDATA_ADDR_31_0_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_2_RD_CMD_FIFO_RDATA_ADDR_31_0_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_ADDR(x) ((x) + 0x39c) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_PHYS(x) ((x) + 0x39c) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_OFFS (0x39c) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_POR 0x3fe04002 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_ATTR 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_STATE_BMSK 0xe0000000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_STATE_SHFT 29 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_RDATA_ADDR_39_32_BMSK 0x1fe00000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_RDATA_ADDR_39_32_SHFT 21 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_AXI_RD_IF_INT_RREADY_BMSK 0x100000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_AXI_RD_IF_INT_RREADY_SHFT 20 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_MAX_OUTSTANDING_REACHED_BMSK 0x80000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_MAX_OUTSTANDING_REACHED_SHFT 19 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_AXI_RD_IF_RRESP_BMSK 0x60000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_AXI_RD_IF_RRESP_SHFT 17 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_DATA_FLUSH_BMSK 0x10000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_DATA_FLUSH_SHFT 16 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_DATA_FLUSH_DONE_BMSK 0x8000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_DATA_FLUSH_DONE_SHFT 15 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_IDLE_BMSK 0x4000 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_IDLE_SHFT 14 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_WR_ADDR_BMSK 0x3f00 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_WR_ADDR_SHFT 8 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_RD_ADDR_BMSK 0xfc -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_RD_ADDR_SHFT 2 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_EMPTY_BMSK 0x2 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_EMPTY_SHFT 1 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_FULL_BMSK 0x1 -#define HWIO_UMAC_MXI_R0_MXI_RD_WDOG_SNAPSHOT_IX_3_RD_CMD_FIFO_FULL_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ADDR(x) ((x) + 0x3a0) -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_PHYS(x) ((x) + 0x3a0) -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_OFFS (0x3a0) -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_RMSK 0x3ff -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_POR 0x0000014a -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_WR_LATENCY_VAL_BMSK 0x3e0 -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_WR_LATENCY_VAL_SHFT 5 -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_RD_LATENCY_VAL_BMSK 0x1f -#define HWIO_UMAC_MXI_R0_MXI_LONG_LATENCY_CONFIG_REG_RD_LATENCY_VAL_SHFT 0 - -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ADDR(x) ((x) + 0x3a4) -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_PHYS(x) ((x) + 0x3a4) -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_OFFS (0x3a4) -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_RMSK 0xf -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_POR 0x00000001 -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ATTR 0x3 -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_IN(x) \ - in_dword(HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ADDR(x)) -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_INM(x, m) \ - in_dword_masked(HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ADDR(x), m) -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_OUT(x, v) \ - out_dword(HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ADDR(x),v) -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_IN(x)) -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_RD_DATA_WORD_SEL_BITMAP_BMSK 0xf -#define HWIO_UMAC_MXI_R0_MXI_READ_DATA_WORD_SEL_BITMAP_RD_DATA_WORD_SEL_BITMAP_SHFT 0 - -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_OFFS(n) (0X508 + (0x4*(n))) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_MAXn 63 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define WBM_REG_REG_BASE (UMAC_BASE + 0x00034000) -#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) ((x) + 0x40) -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) ((x) + 0x130) -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x7fc -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 2 -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x2 -#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 1 -#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) ((x) + 0x134) -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 16 -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0xffff -#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) ((x) + 0x138) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) ((x) + 0x13c) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) ((x) + 0x140) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) ((x) + 0x144) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x1fff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) ((x) + 0x148) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) ((x) + 0x14c) -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x1fff00 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 8 -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 - -#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) ((x) + 0x150) -#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x24c) -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0x51c) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) ((x) + 0x52c) -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x5e8) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x5ec) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x5f0) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x5f4) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_OFFS (0x1f7c) -#define HWIO_WBM_R0_LPM_FW_CTRL_RMSK 0x3f -#define HWIO_WBM_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_WBM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_WBM_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_WBM_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_WBM_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_WBM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_WBM_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_BMSK 0x20 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_SHFT 5 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_BMSK 0x10 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_SHFT 4 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x) ((x) + 0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_PHYS(x) ((x) + 0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OFFS (0x1f80) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RMSK 0xffffffff -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR 0x00000000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR_RMSK 0xffffffff -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ATTR 0x3 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x) \ - in_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x)) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_INM(x, m) \ - in_dword_masked(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x), m) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUT(x, v) \ - out_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),v) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x)) -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_BMSK 0xffe00000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_SHFT 21 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_BMSK 0x1f0000 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_SHFT 16 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_BMSK 0xf800 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_SHFT 11 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_BMSK 0x7c0 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_SHFT 6 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_BMSK 0x3e -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_SHFT 1 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_BMSK 0x1 -#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_SHFT 0 - -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2030) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x3ff -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000020 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_BMSK 0x200 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_SHFT 9 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_BMSK 0x100 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_SHFT 8 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2034 + (0x4*(n))) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_MAXn 255 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3010) -#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) ((x) + 0x3040) -#define REO_REG_REG_BASE (UMAC_BASE + 0x00038000) -#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) ((x) + 0x0) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x) ((x) + 0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_PHYS(x) ((x) + 0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OFFS (0x14) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR 0x76043210 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x) ((x) + 0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x) ((x) + 0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS (0x18) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR 0x6666ba98 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x) ((x) + 0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_PHYS(x) ((x) + 0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OFFS (0x1c) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR 0x66666666 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_SHFT 0 - -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x) ((x) + 0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_PHYS(x) ((x) + 0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OFFS (0x20) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR 0x66666666 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR_RMSK 0xffffffff -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ATTR 0x3 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x) \ - in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x), m) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUT(x, v) \ - out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),v) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x)) -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_BMSK 0xf0000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_SHFT 28 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_BMSK 0xf000000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_SHFT 24 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_BMSK 0xf00000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_SHFT 20 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_BMSK 0xf0000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_SHFT 16 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_BMSK 0xf000 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_SHFT 12 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_BMSK 0xf00 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_SHFT 8 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_BMSK 0xf0 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_SHFT 4 -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_BMSK 0xf -#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) ((x) + 0x38) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) ((x) + 0x3c) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x) ((x) + 0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_PHYS(x) ((x) + 0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OFFS (0x40) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR 0x00000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ATTR 0x3 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x), m) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),v) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_SHFT 0 - -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x) ((x) + 0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_PHYS(x) ((x) + 0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OFFS (0x44) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR 0x00000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ATTR 0x3 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x), m) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),v) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x)) -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_BMSK 0xf0000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_SHFT 28 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_BMSK 0xf000000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_SHFT 24 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_BMSK 0xf00000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_SHFT 20 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_BMSK 0xf0000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_SHFT 16 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_BMSK 0xf000 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_SHFT 12 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_BMSK 0xf00 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_SHFT 8 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_BMSK 0xf0 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_SHFT 4 -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_BMSK 0xf -#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_SHFT 0 - -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x) ((x) + 0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_PHYS(x) ((x) + 0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OFFS (0x48) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_RMSK 0x1ffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR 0x00000000 -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ATTR 0x3 -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x) \ - in_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x)) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x), m) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUT(x, v) \ - out_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),v) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),m,v,HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x)) -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_BMSK 0x1ffff -#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_SHFT 0 - -#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x6c) -#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x70) -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK 0x100000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT 20 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK 0x80000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT 19 -#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 -#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 -#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff -#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 - -#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) ((x) + 0x344) -#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_ADDR(x) ((x) + 0x524) -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_PHYS(x) ((x) + 0x524) -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_OFFS (0x524) -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_BASE_LSB_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_ADDR(x) ((x) + 0x528) -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_PHYS(x) ((x) + 0x528) -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_OFFS (0x528) -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_BASE_MSB_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_FW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_ID_ADDR(x) ((x) + 0x52c) -#define HWIO_REO_R0_FW2REO_RING_ID_PHYS(x) ((x) + 0x52c) -#define HWIO_REO_R0_FW2REO_RING_ID_OFFS (0x52c) -#define HWIO_REO_R0_FW2REO_RING_ID_RMSK 0xff -#define HWIO_REO_R0_FW2REO_RING_ID_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_ID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_ID_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_ID_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_ID_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_ID_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_ID_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_ID_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_ID_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_ID_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_REO_R0_FW2REO_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_STATUS_ADDR(x) ((x) + 0x530) -#define HWIO_REO_R0_FW2REO_RING_STATUS_PHYS(x) ((x) + 0x530) -#define HWIO_REO_R0_FW2REO_RING_STATUS_OFFS (0x530) -#define HWIO_REO_R0_FW2REO_RING_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_STATUS_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_STATUS_ATTR 0x1 -#define HWIO_REO_R0_FW2REO_RING_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_STATUS_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_STATUS_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_FW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_FW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_FW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_MISC_ADDR(x) ((x) + 0x534) -#define HWIO_REO_R0_FW2REO_RING_MISC_PHYS(x) ((x) + 0x534) -#define HWIO_REO_R0_FW2REO_RING_MISC_OFFS (0x534) -#define HWIO_REO_R0_FW2REO_RING_MISC_RMSK 0x7fffff -#define HWIO_REO_R0_FW2REO_RING_MISC_POR 0x00000080 -#define HWIO_REO_R0_FW2REO_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MISC_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_MISC_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_MISC_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_MISC_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_MISC_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_MISC_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_MISC_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_REO_R0_FW2REO_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_REO_R0_FW2REO_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_REO_R0_FW2REO_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_REO_R0_FW2REO_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_REO_R0_FW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_REO_R0_FW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_REO_R0_FW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_REO_R0_FW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_REO_R0_FW2REO_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_REO_R0_FW2REO_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_REO_R0_FW2REO_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_REO_R0_FW2REO_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_REO_R0_FW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_REO_R0_FW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_REO_R0_FW2REO_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_REO_R0_FW2REO_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x540) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x540) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_OFFS (0x540) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x544) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x544) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_OFFS (0x544) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_RMSK 0xff -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_FW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x554) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x554) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x554) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x558) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x558) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x558) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x55c) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x55c) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_OFFS (0x55c) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_ATTR 0x1 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x560) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x560) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x560) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x564) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x564) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x564) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x568) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x568) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x568) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R0_FW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x56c) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x56c) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_OFFS (0x56c) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x570) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x570) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_OFFS (0x570) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_FW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ADDR(x) ((x) + 0x574) -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_PHYS(x) ((x) + 0x574) -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_OFFS (0x574) -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_MSI1_DATA_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x594) -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x594) -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_OFFS (0x594) -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_REO_R0_FW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_REO_R0_FW2REO_RING_MISC_1_ADDR(x) ((x) + 0x598) -#define HWIO_REO_R0_FW2REO_RING_MISC_1_PHYS(x) ((x) + 0x598) -#define HWIO_REO_R0_FW2REO_RING_MISC_1_OFFS (0x598) -#define HWIO_REO_R0_FW2REO_RING_MISC_1_RMSK 0xffff003f -#define HWIO_REO_R0_FW2REO_RING_MISC_1_POR 0x00000000 -#define HWIO_REO_R0_FW2REO_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO_RING_MISC_1_ATTR 0x3 -#define HWIO_REO_R0_FW2REO_RING_MISC_1_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO_RING_MISC_1_ADDR(x)) -#define HWIO_REO_R0_FW2REO_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO_RING_MISC_1_ADDR(x), m) -#define HWIO_REO_R0_FW2REO_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO_RING_MISC_1_ADDR(x),v) -#define HWIO_REO_R0_FW2REO_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_FW2REO_RING_MISC_1_IN(x)) -#define HWIO_REO_R0_FW2REO_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_FW2REO_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_FW2REO_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_FW2REO_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ADDR(x) ((x) + 0x59c) -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_PHYS(x) ((x) + 0x59c) -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_OFFS (0x59c) -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_BASE_LSB_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ADDR(x) ((x) + 0x5a0) -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_PHYS(x) ((x) + 0x5a0) -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_OFFS (0x5a0) -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_BASE_MSB_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_FW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_ID_ADDR(x) ((x) + 0x5a4) -#define HWIO_REO_R0_FW2REO1_RING_ID_PHYS(x) ((x) + 0x5a4) -#define HWIO_REO_R0_FW2REO1_RING_ID_OFFS (0x5a4) -#define HWIO_REO_R0_FW2REO1_RING_ID_RMSK 0xff -#define HWIO_REO_R0_FW2REO1_RING_ID_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_ID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_ID_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_ID_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_ID_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_ID_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_ID_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_ID_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_ID_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_ID_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_REO_R0_FW2REO1_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_STATUS_ADDR(x) ((x) + 0x5a8) -#define HWIO_REO_R0_FW2REO1_RING_STATUS_PHYS(x) ((x) + 0x5a8) -#define HWIO_REO_R0_FW2REO1_RING_STATUS_OFFS (0x5a8) -#define HWIO_REO_R0_FW2REO1_RING_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_STATUS_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_STATUS_ATTR 0x1 -#define HWIO_REO_R0_FW2REO1_RING_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_STATUS_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_STATUS_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_FW2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_FW2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_FW2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_MISC_ADDR(x) ((x) + 0x5ac) -#define HWIO_REO_R0_FW2REO1_RING_MISC_PHYS(x) ((x) + 0x5ac) -#define HWIO_REO_R0_FW2REO1_RING_MISC_OFFS (0x5ac) -#define HWIO_REO_R0_FW2REO1_RING_MISC_RMSK 0x7fffff -#define HWIO_REO_R0_FW2REO1_RING_MISC_POR 0x00000080 -#define HWIO_REO_R0_FW2REO1_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MISC_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_MISC_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_MISC_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_MISC_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_MISC_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_MISC_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_MISC_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_REO_R0_FW2REO1_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_REO_R0_FW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_REO_R0_FW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_REO_R0_FW2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_REO_R0_FW2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_REO_R0_FW2REO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_REO_R0_FW2REO1_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_REO_R0_FW2REO1_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_REO_R0_FW2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_REO_R0_FW2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_REO_R0_FW2REO1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_REO_R0_FW2REO1_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x5b8) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x5b8) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_OFFS (0x5b8) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x5bc) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x5bc) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_OFFS (0x5bc) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_RMSK 0xff -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_FW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x5cc) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x5cc) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x5cc) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x5d0) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x5d0) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x5d0) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x5d4) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x5d4) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_OFFS (0x5d4) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_ATTR 0x1 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x5d8) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x5d8) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x5d8) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x5dc) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x5dc) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x5dc) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x5e0) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x5e0) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x5e0) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R0_FW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x5e4) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x5e4) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_OFFS (0x5e4) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x5e8) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x5e8) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_OFFS (0x5e8) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ADDR(x) ((x) + 0x5ec) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_PHYS(x) ((x) + 0x5ec) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_OFFS (0x5ec) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x60c) -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x60c) -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_OFFS (0x60c) -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_REO_R0_FW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_ADDR(x) ((x) + 0x610) -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_PHYS(x) ((x) + 0x610) -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_OFFS (0x610) -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_RMSK 0xffff003f -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_POR 0x00000000 -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_ATTR 0x3 -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_IN(x) \ - in_dword(HWIO_REO_R0_FW2REO1_RING_MISC_1_ADDR(x)) -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_FW2REO1_RING_MISC_1_ADDR(x), m) -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_FW2REO1_RING_MISC_1_ADDR(x),v) -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_FW2REO1_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_FW2REO1_RING_MISC_1_IN(x)) -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_FW2REO1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) ((x) + 0x7d0) -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) ((x) + 0x7d4) -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) ((x) + 0x7d8) -#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x7e0) -#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x7e4) -#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x7e8) -#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7f4) -#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x818) -#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x81c) -#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x820) -#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x824) -#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x828) -#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x82c) -#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x830) -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x844) -#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x848) -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 -#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW5_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW5_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW6_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW6_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW7_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW7_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW8_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW8_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ADDR(x) ((x) + 0xb90) -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_PHYS(x) ((x) + 0xb90) -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_OFFS (0xb90) -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_BASE_LSB_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ADDR(x) ((x) + 0xb94) -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_PHYS(x) ((x) + 0xb94) -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_OFFS (0xb94) -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_RMSK 0xfffffff -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_BASE_MSB_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_REO2SW9_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_ID_ADDR(x) ((x) + 0xb98) -#define HWIO_REO_R0_REO2SW9_RING_ID_PHYS(x) ((x) + 0xb98) -#define HWIO_REO_R0_REO2SW9_RING_ID_OFFS (0xb98) -#define HWIO_REO_R0_REO2SW9_RING_ID_RMSK 0xffff -#define HWIO_REO_R0_REO2SW9_RING_ID_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_ID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_ID_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_ID_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_ID_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_ID_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_ID_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_ID_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_ID_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_REO_R0_REO2SW9_RING_ID_RING_ID_SHFT 8 -#define HWIO_REO_R0_REO2SW9_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_REO_R0_REO2SW9_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_STATUS_ADDR(x) ((x) + 0xb9c) -#define HWIO_REO_R0_REO2SW9_RING_STATUS_PHYS(x) ((x) + 0xb9c) -#define HWIO_REO_R0_REO2SW9_RING_STATUS_OFFS (0xb9c) -#define HWIO_REO_R0_REO2SW9_RING_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_STATUS_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_STATUS_ATTR 0x1 -#define HWIO_REO_R0_REO2SW9_RING_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_STATUS_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_STATUS_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW9_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_REO2SW9_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_REO2SW9_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_MISC_ADDR(x) ((x) + 0xba0) -#define HWIO_REO_R0_REO2SW9_RING_MISC_PHYS(x) ((x) + 0xba0) -#define HWIO_REO_R0_REO2SW9_RING_MISC_OFFS (0xba0) -#define HWIO_REO_R0_REO2SW9_RING_MISC_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MISC_POR 0x00000080 -#define HWIO_REO_R0_REO2SW9_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MISC_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_MISC_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_MISC_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MISC_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_MISC_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_MISC_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MISC_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW9_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW9_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2SW9_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_REO_R0_REO2SW9_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_REO_R0_REO2SW9_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_REO_R0_REO2SW9_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_REO_R0_REO2SW9_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_REO_R0_REO2SW9_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_REO_R0_REO2SW9_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_REO_R0_REO2SW9_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_REO_R0_REO2SW9_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_REO_R0_REO2SW9_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_REO_R0_REO2SW9_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_REO_R0_REO2SW9_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_REO_R0_REO2SW9_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_REO_R0_REO2SW9_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_REO_R0_REO2SW9_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xba4) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xba4) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_OFFS (0xba4) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xba8) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xba8) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_OFFS (0xba8) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_REO2SW9_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xbb4) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xbb4) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_OFFS (0xbb4) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xbb8) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xbb8) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_OFFS (0xbb8) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xbbc) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xbbc) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_OFFS (0xbbc) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xbd8) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xbd8) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_OFFS (0xbd8) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xbdc) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xbdc) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_OFFS (0xbdc) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ADDR(x) ((x) + 0xbe0) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_PHYS(x) ((x) + 0xbe0) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_OFFS (0xbe0) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xbe4) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xbe4) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_OFFS (0xbe4) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff -#define HWIO_REO_R0_REO2SW9_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xbe8) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xbe8) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_OFFS (0xbe8) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xbec) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xbec) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_OFFS (0xbec) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ADDR(x) ((x) + 0xbf0) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_PHYS(x) ((x) + 0xbf0) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_OFFS (0xbf0) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xc00) -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xc00) -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_OFFS (0xc00) -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_REO_R0_REO2SW9_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_ADDR(x) ((x) + 0xc04) -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_PHYS(x) ((x) + 0xc04) -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_OFFS (0xc04) -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_RMSK 0xffff003f -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_RING_MISC_1_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_RING_MISC_1_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_RING_MISC_1_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_RING_MISC_1_IN(x)) -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_REO2SW9_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0xc08) -#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_REO2SW0_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2SW0_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ADDR(x) ((x) + 0x126c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_PHYS(x) ((x) + 0x126c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_OFFS (0x126c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ADDR(x) ((x) + 0x1270) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_PHYS(x) ((x) + 0x1270) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_OFFS (0x1270) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ADDR(x) ((x) + 0x1274) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_PHYS(x) ((x) + 0x1274) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_OFFS (0x1274) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_RMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_ID_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_ADDR(x) ((x) + 0x1278) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_PHYS(x) ((x) + 0x1278) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_OFFS (0x1278) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ADDR(x) ((x) + 0x127c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_PHYS(x) ((x) + 0x127c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_OFFS (0x127c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_RMSK 0x7fffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_POR 0x00000080 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1288) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1288) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_OFFS (0x1288) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x128c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x128c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_OFFS (0x128c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_RMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x129c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x129c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x129c) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x12a0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x12a0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x12a0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x12a4) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x12a4) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_OFFS (0x12a4) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x12a8) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x12a8) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x12a8) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x12ac) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x12ac) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x12ac) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x12b0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x12b0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x12b0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x12b4) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x12b4) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_OFFS (0x12b4) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x12b8) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x12b8) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_OFFS (0x12b8) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ADDR(x) ((x) + 0x12bc) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_PHYS(x) ((x) + 0x12bc) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_OFFS (0x12bc) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x12dc) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x12dc) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_OFFS (0x12dc) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ADDR(x) ((x) + 0x12e0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_PHYS(x) ((x) + 0x12e0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_OFFS (0x12e0) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_RMSK 0xffff003f -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_SW2FW_REO0_C_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ADDR(x) ((x) + 0x12e4) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_PHYS(x) ((x) + 0x12e4) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_OFFS (0x12e4) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ADDR(x) ((x) + 0x12e8) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_PHYS(x) ((x) + 0x12e8) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_OFFS (0x12e8) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ADDR(x) ((x) + 0x12ec) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_PHYS(x) ((x) + 0x12ec) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_OFFS (0x12ec) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_RMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_ID_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_ADDR(x) ((x) + 0x12f0) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_PHYS(x) ((x) + 0x12f0) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_OFFS (0x12f0) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ADDR(x) ((x) + 0x12f4) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_PHYS(x) ((x) + 0x12f4) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_OFFS (0x12f4) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_RMSK 0x7fffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_POR 0x00000080 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1300) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1300) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_OFFS (0x1300) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x1304) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x1304) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_OFFS (0x1304) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_RMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x1314) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x1314) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x1314) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x1318) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x1318) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x1318) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x131c) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x131c) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_OFFS (0x131c) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x1320) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x1320) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x1320) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x1324) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x1324) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x1324) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x1328) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x1328) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x1328) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x132c) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x132c) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_OFFS (0x132c) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x1330) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x1330) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_OFFS (0x1330) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ADDR(x) ((x) + 0x1334) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_PHYS(x) ((x) + 0x1334) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_OFFS (0x1334) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x1354) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x1354) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_OFFS (0x1354) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ADDR(x) ((x) + 0x1358) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_PHYS(x) ((x) + 0x1358) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_OFFS (0x1358) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_RMSK 0xffff003f -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_SW2FW_REO1_C_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ADDR(x) ((x) + 0x135c) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_PHYS(x) ((x) + 0x135c) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_OFFS (0x135c) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ADDR(x) ((x) + 0x1360) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_PHYS(x) ((x) + 0x1360) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_OFFS (0x1360) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ADDR(x) ((x) + 0x1364) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_PHYS(x) ((x) + 0x1364) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_OFFS (0x1364) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_RMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_ID_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_RING_ID_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_ADDR(x) ((x) + 0x1368) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_PHYS(x) ((x) + 0x1368) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_OFFS (0x1368) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADDR(x) ((x) + 0x136c) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_PHYS(x) ((x) + 0x136c) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_OFFS (0x136c) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_POR 0x00000080 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x1370) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x1370) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_OFFS (0x1370) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x1374) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x1374) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_OFFS (0x1374) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x1380) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x1380) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_OFFS (0x1380) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x1384) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x1384) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_OFFS (0x1384) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x1388) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x1388) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_OFFS (0x1388) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x13a4) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x13a4) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_OFFS (0x13a4) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x13a8) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x13a8) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_OFFS (0x13a8) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ADDR(x) ((x) + 0x13ac) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_PHYS(x) ((x) + 0x13ac) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_OFFS (0x13ac) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x13b0) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x13b0) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_OFFS (0x13b0) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x13b4) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x13b4) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_OFFS (0x13b4) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x13b8) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x13b8) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_OFFS (0x13b8) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ADDR(x) ((x) + 0x13bc) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_PHYS(x) ((x) + 0x13bc) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_OFFS (0x13bc) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x13cc) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x13cc) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_OFFS (0x13cc) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ADDR(x) ((x) + 0x13d0) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_PHYS(x) ((x) + 0x13d0) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_OFFS (0x13d0) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_RMSK 0xffff003f -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_IN(x)) -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_SW2FW_REO0_P_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ADDR(x) ((x) + 0x13d4) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_PHYS(x) ((x) + 0x13d4) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_OFFS (0x13d4) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ADDR(x) ((x) + 0x13d8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_PHYS(x) ((x) + 0x13d8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_OFFS (0x13d8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ADDR(x) ((x) + 0x13dc) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_PHYS(x) ((x) + 0x13dc) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_OFFS (0x13dc) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_RMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_ID_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_RING_ID_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_ADDR(x) ((x) + 0x13e0) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_PHYS(x) ((x) + 0x13e0) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_OFFS (0x13e0) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADDR(x) ((x) + 0x13e4) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_PHYS(x) ((x) + 0x13e4) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_OFFS (0x13e4) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_POR 0x00000080 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x13e8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x13e8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_OFFS (0x13e8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x13ec) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x13ec) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_OFFS (0x13ec) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x13f8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x13f8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_OFFS (0x13f8) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x13fc) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x13fc) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_OFFS (0x13fc) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x1400) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x1400) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_OFFS (0x1400) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x141c) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x141c) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_OFFS (0x141c) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x1420) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x1420) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_OFFS (0x1420) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ADDR(x) ((x) + 0x1424) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_PHYS(x) ((x) + 0x1424) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_OFFS (0x1424) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x1428) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x1428) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_OFFS (0x1428) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x142c) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x142c) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_OFFS (0x142c) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x1430) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x1430) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_OFFS (0x1430) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ADDR(x) ((x) + 0x1434) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_PHYS(x) ((x) + 0x1434) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_OFFS (0x1434) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x1444) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x1444) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_OFFS (0x1444) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ADDR(x) ((x) + 0x1448) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_PHYS(x) ((x) + 0x1448) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_OFFS (0x1448) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_RMSK 0xffff003f -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_POR 0x00000000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ATTR 0x3 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_IN(x) \ - in_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ADDR(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ADDR(x), m) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ADDR(x),v) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_IN(x)) -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_REO_R0_SW2FW_REO1_P_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_SW2FW_REO1_P_RING_BACK_PRESSURE_BMSK 0x10000 -#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_SW2FW_REO1_P_RING_BACK_PRESSURE_SHFT 16 -#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_SW2FW_REO0_P_RING_BACK_PRESSURE_BMSK 0x8000 -#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_SW2FW_REO0_P_RING_BACK_PRESSURE_SHFT 15 -#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW9_RING_BACK_PRESSURE_BMSK 0x4000 -#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW9_RING_BACK_PRESSURE_SHFT 14 -#define HWIO_REO_R0_MISC_CFG_ADDR(x) ((x) + 0x1458) -#define HWIO_REO_R0_MISC_CFG_PHYS(x) ((x) + 0x1458) -#define HWIO_REO_R0_MISC_CFG_OFFS (0x1458) -#define HWIO_REO_R0_MISC_CFG_RMSK 0x1 -#define HWIO_REO_R0_MISC_CFG_POR 0x00000000 -#define HWIO_REO_R0_MISC_CFG_POR_RMSK 0xffffffff -#define HWIO_REO_R0_MISC_CFG_ATTR 0x3 -#define HWIO_REO_R0_MISC_CFG_IN(x) \ - in_dword(HWIO_REO_R0_MISC_CFG_ADDR(x)) -#define HWIO_REO_R0_MISC_CFG_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_MISC_CFG_ADDR(x), m) -#define HWIO_REO_R0_MISC_CFG_OUT(x, v) \ - out_dword(HWIO_REO_R0_MISC_CFG_ADDR(x),v) -#define HWIO_REO_R0_MISC_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_MISC_CFG_ADDR(x),m,v,HWIO_REO_R0_MISC_CFG_IN(x)) -#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_BMSK 0x1 -#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_SHFT 0 - -#define HWIO_REO_R0_MISC_CFG_BN_1_ADDR(x) ((x) + 0x145c) -#define HWIO_REO_R0_MISC_CFG_BN_1_PHYS(x) ((x) + 0x145c) -#define HWIO_REO_R0_MISC_CFG_BN_1_OFFS (0x145c) -#define HWIO_REO_R0_MISC_CFG_BN_1_RMSK 0x3cfff -#define HWIO_REO_R0_MISC_CFG_BN_1_POR 0x00000801 -#define HWIO_REO_R0_MISC_CFG_BN_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_MISC_CFG_BN_1_ATTR 0x3 -#define HWIO_REO_R0_MISC_CFG_BN_1_IN(x) \ - in_dword(HWIO_REO_R0_MISC_CFG_BN_1_ADDR(x)) -#define HWIO_REO_R0_MISC_CFG_BN_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_MISC_CFG_BN_1_ADDR(x), m) -#define HWIO_REO_R0_MISC_CFG_BN_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_MISC_CFG_BN_1_ADDR(x),v) -#define HWIO_REO_R0_MISC_CFG_BN_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_MISC_CFG_BN_1_ADDR(x),m,v,HWIO_REO_R0_MISC_CFG_BN_1_IN(x)) -#define HWIO_REO_R0_MISC_CFG_BN_1_NULL_BUFFER_ERROR_DEST_RING_BMSK 0x3c000 -#define HWIO_REO_R0_MISC_CFG_BN_1_NULL_BUFFER_ERROR_DEST_RING_SHFT 14 -#define HWIO_REO_R0_MISC_CFG_BN_1_STOP_DELINKING_DURING_CORRUPTION_BMSK 0x800 -#define HWIO_REO_R0_MISC_CFG_BN_1_STOP_DELINKING_DURING_CORRUPTION_SHFT 11 -#define HWIO_REO_R0_MISC_CFG_BN_1_MSDU_LINK_SHARING_BW_MPDU_FEATURE_ENABLE_BMSK 0x400 -#define HWIO_REO_R0_MISC_CFG_BN_1_MSDU_LINK_SHARING_BW_MPDU_FEATURE_ENABLE_SHFT 10 -#define HWIO_REO_R0_MISC_CFG_BN_1_ADDITIONAL_BMSK 0x3c0 -#define HWIO_REO_R0_MISC_CFG_BN_1_ADDITIONAL_SHFT 6 -#define HWIO_REO_R0_MISC_CFG_BN_1_ACCUM_RESOLUTION_BMSK 0x20 -#define HWIO_REO_R0_MISC_CFG_BN_1_ACCUM_RESOLUTION_SHFT 5 -#define HWIO_REO_R0_MISC_CFG_BN_1_RX_RXDMA_ERROR_COMPLETION_EN_BMSK 0x10 -#define HWIO_REO_R0_MISC_CFG_BN_1_RX_RXDMA_ERROR_COMPLETION_EN_SHFT 4 -#define HWIO_REO_R0_MISC_CFG_BN_1_RX_REO_ERROR_COMPLETION_EN_BMSK 0x8 -#define HWIO_REO_R0_MISC_CFG_BN_1_RX_REO_ERROR_COMPLETION_EN_SHFT 3 -#define HWIO_REO_R0_MISC_CFG_BN_1_NULL_OUT_MSDU_LINK_BEFORE_RELEASE_TO_WBM_BMSK 0x4 -#define HWIO_REO_R0_MISC_CFG_BN_1_NULL_OUT_MSDU_LINK_BEFORE_RELEASE_TO_WBM_SHFT 2 -#define HWIO_REO_R0_MISC_CFG_BN_1_MSDU_FETCH_GXI_OPTIMISATION_BMSK 0x2 -#define HWIO_REO_R0_MISC_CFG_BN_1_MSDU_FETCH_GXI_OPTIMISATION_SHFT 1 -#define HWIO_REO_R0_MISC_CFG_BN_1_REO_LITE_EN_BMSK 0x1 -#define HWIO_REO_R0_MISC_CFG_BN_1_REO_LITE_EN_SHFT 0 - -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x) ((x) + 0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_PHYS(x) ((x) + 0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OFFS (0x1460) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_RMSK 0x7ff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR 0x000003ff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_POR_RMSK 0xffffffff -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_ATTR 0x3 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x) \ - in_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x)) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x), m) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUT(x, v) \ - out_dword(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),v) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_COOKIE_CONV_EN_RING_ADDR(x),m,v,HWIO_REO_R0_COOKIE_CONV_EN_RING_IN(x)) -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_BMSK 0x400 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2FW_SHFT 10 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_BMSK 0x200 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW9_SHFT 9 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_BMSK 0x100 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW8_SHFT 8 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_BMSK 0x80 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW7_SHFT 7 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_BMSK 0x40 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW6_SHFT 6 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_BMSK 0x20 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW5_SHFT 5 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_BMSK 0x10 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW4_SHFT 4 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_BMSK 0x8 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW3_SHFT 3 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_BMSK 0x4 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW2_SHFT 2 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_BMSK 0x2 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW1_SHFT 1 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_BMSK 0x1 -#define HWIO_REO_R0_COOKIE_CONV_EN_RING_REO2SW0_SHFT 0 - -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x) ((x) + 0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_PHYS(x) ((x) + 0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OFFS (0x1464) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_RMSK 0x1ff -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR 0x0000002d -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR_RMSK 0xffffffff -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ATTR 0x3 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x) \ - in_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x)) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x), m) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUT(x, v) \ - out_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),v) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),m,v,HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x)) -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_BMSK 0x1fe -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_SHFT 1 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_BMSK 0x1 -#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_SHFT 0 - -#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) ((x) + 0x1468) -#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) ((x) + 0x146c) -#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) ((x) + 0x1470) -#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) ((x) + 0x1474) -#define HWIO_REO_R0_MISC_CTL_ADDR(x) ((x) + 0x14dc) -#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK 0x1e00000 -#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT 21 -#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x1e0000 -#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 17 -#define HWIO_REO_R0_MISC_CTL_2_REO2SW9_RING_PRIORITY_BMSK 0x30000000 -#define HWIO_REO_R0_MISC_CTL_2_REO2SW9_RING_PRIORITY_SHFT 28 -#define HWIO_REO_R0_MISC_CTL_5_ADDR(x) ((x) + 0x14ec) -#define HWIO_REO_R0_MISC_CTL_5_PHYS(x) ((x) + 0x14ec) -#define HWIO_REO_R0_MISC_CTL_5_OFFS (0x14ec) -#define HWIO_REO_R0_MISC_CTL_5_RMSK 0x3f -#define HWIO_REO_R0_MISC_CTL_5_POR 0x00000000 -#define HWIO_REO_R0_MISC_CTL_5_POR_RMSK 0xffffffff -#define HWIO_REO_R0_MISC_CTL_5_ATTR 0x3 -#define HWIO_REO_R0_MISC_CTL_5_IN(x) \ - in_dword(HWIO_REO_R0_MISC_CTL_5_ADDR(x)) -#define HWIO_REO_R0_MISC_CTL_5_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_MISC_CTL_5_ADDR(x), m) -#define HWIO_REO_R0_MISC_CTL_5_OUT(x, v) \ - out_dword(HWIO_REO_R0_MISC_CTL_5_ADDR(x),v) -#define HWIO_REO_R0_MISC_CTL_5_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_5_ADDR(x),m,v,HWIO_REO_R0_MISC_CTL_5_IN(x)) -#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO1_C_VC_ID_BMSK 0x20 -#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO1_C_VC_ID_SHFT 5 -#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO0_C_VC_ID_BMSK 0x10 -#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO0_C_VC_ID_SHFT 4 -#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO1_P_RING_PRIORITY_BMSK 0xc -#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO1_P_RING_PRIORITY_SHFT 2 -#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO0_P_RING_PRIORITY_BMSK 0x3 -#define HWIO_REO_R0_MISC_CTL_5_SW2FW_REO0_P_RING_PRIORITY_SHFT 0 - -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) ((x) + 0x16b4) -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) ((x) + 0x16b4) -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_OFFS (0x16b4) -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_POR 0x00000000 -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ATTR 0x3 -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ - in_dword(HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x)) -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), m) -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x),v) -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x),m,v,HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_IN(x)) -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 16 -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0xf -#define HWIO_REO_R0_REO2SW9_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x16c0) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x16c4) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x16c8) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x16cc) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_REO_R0_CREDIT_ADDR(x) ((x) + 0x16d0) -#define HWIO_REO_R0_CREDIT_PHYS(x) ((x) + 0x16d0) -#define HWIO_REO_R0_CREDIT_OFFS (0x16d0) -#define HWIO_REO_R0_CREDIT_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_POR 0x00000000 -#define HWIO_REO_R0_CREDIT_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_ATTR 0x3 -#define HWIO_REO_R0_CREDIT_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_ADDR(x)) -#define HWIO_REO_R0_CREDIT_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_OUT(x, v) \ - out_dword(HWIO_REO_R0_CREDIT_ADDR(x),v) -#define HWIO_REO_R0_CREDIT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_CREDIT_ADDR(x),m,v,HWIO_REO_R0_CREDIT_IN(x)) -#define HWIO_REO_R0_CREDIT_VAL_BMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_VAL_SHFT 0 - -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x) ((x) + 0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_PHYS(x) ((x) + 0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OFFS (0x16d4) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_RMSK 0x7 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR 0x00000002 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ATTR 0x3 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x)) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUT(x, v) \ - out_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),v) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),m,v,HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x)) -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_BMSK 0x7 -#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_SHFT 0 - -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x) ((x) + 0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_PHYS(x) ((x) + 0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_OFFS (0x16d8) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR 0x00000000 -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ATTR 0x1 -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_IN(x) \ - in_dword(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x)) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x), m) -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_BMSK 0xffffffff -#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_SHFT 0 - -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_CMD_FIFO_MEM_BMSK 0x2000000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_CMD_FIFO_MEM_SHFT 25 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM3_BMSK 0x1000000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM3_SHFT 24 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM222_BMSK 0x800000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM222_SHFT 23 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM1_BMSK 0x400000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM1_SHFT 22 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM0_BMSK 0x200000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SEQ_MEM0_SHFT 21 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW2FW_REO1_MEM_BMSK 0x100000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW2FW_REO1_MEM_SHFT 20 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW2FW_REO0_MEM_BMSK 0x80000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW2FW_REO0_MEM_SHFT 19 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_REO_RELEASE_RING_MEM_BMSK 0x40000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_REO_RELEASE_RING_MEM_SHFT 18 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW_PROD_MEM_MEM_BMSK 0x20000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SW_PROD_MEM_MEM_SHFT 17 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_RING_PREFETCH_MEM_BMSK 0x10000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_RING_PREFETCH_MEM_SHFT 16 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_BMSK 0x2000 -#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_SHFT 13 -#define HWIO_REO_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_OFFS (0x1704) -#define HWIO_REO_R0_LPM_FW_CTRL_RMSK 0x7 -#define HWIO_REO_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_REO_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_REO_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_REO_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_REO_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_REO_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_REO_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_REO_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_ADDR(x) ((x) + 0x1708) -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_PHYS(x) ((x) + 0x1708) -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_OFFS (0x1708) -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_RMSK 0xffff -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_POR 0x00000000 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_POR_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_ATTR 0x3 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_IN(x) \ - in_dword(HWIO_REO_R0_ERROR_CODE_REO_DELINK_ADDR(x)) -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_ERROR_CODE_REO_DELINK_ADDR(x), m) -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_OUT(x, v) \ - out_dword(HWIO_REO_R0_ERROR_CODE_REO_DELINK_ADDR(x),v) -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_ERROR_CODE_REO_DELINK_ADDR(x),m,v,HWIO_REO_R0_ERROR_CODE_REO_DELINK_IN(x)) -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_OTHER_BMSK 0x8000 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_OTHER_SHFT 15 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_14_BMSK 0x4000 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_14_SHFT 14 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_13_BMSK 0x2000 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_13_SHFT 13 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_12_BMSK 0x1000 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_12_SHFT 12 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_11_BMSK 0x800 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_11_SHFT 11 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_10_BMSK 0x400 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_10_SHFT 10 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_9_BMSK 0x200 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_9_SHFT 9 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_8_BMSK 0x100 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_8_SHFT 8 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_7_BMSK 0x80 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_7_SHFT 7 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_6_BMSK 0x40 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_6_SHFT 6 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_5_BMSK 0x20 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_5_SHFT 5 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_4_BMSK 0x10 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_4_SHFT 4 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_3_BMSK 0x8 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_3_SHFT 3 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_2_BMSK 0x4 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_2_SHFT 2 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_1_BMSK 0x2 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_1_SHFT 1 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_0_BMSK 0x1 -#define HWIO_REO_R0_ERROR_CODE_REO_DELINK_REO_ERROR_CODE_0_SHFT 0 - -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ADDR(x) ((x) + 0x170c) -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_PHYS(x) ((x) + 0x170c) -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_OFFS (0x170c) -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_RMSK 0xffff -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_POR 0x00000000 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_POR_RMSK 0xffffffff -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ATTR 0x3 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_IN(x) \ - in_dword(HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ADDR(x)) -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ADDR(x), m) -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_OUT(x, v) \ - out_dword(HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ADDR(x),v) -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_ADDR(x),m,v,HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_IN(x)) -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_OTHER_BMSK 0x8000 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_OTHER_SHFT 15 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_14_BMSK 0x4000 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_14_SHFT 14 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_13_BMSK 0x2000 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_13_SHFT 13 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_12_BMSK 0x1000 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_12_SHFT 12 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_11_BMSK 0x800 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_11_SHFT 11 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_10_BMSK 0x400 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_10_SHFT 10 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_9_BMSK 0x200 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_9_SHFT 9 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_8_BMSK 0x100 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_8_SHFT 8 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_7_BMSK 0x80 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_7_SHFT 7 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_6_BMSK 0x40 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_6_SHFT 6 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_5_BMSK 0x20 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_5_SHFT 5 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_4_BMSK 0x10 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_4_SHFT 4 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_3_BMSK 0x8 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_3_SHFT 3 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_2_BMSK 0x4 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_2_SHFT 2 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_1_BMSK 0x2 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_1_SHFT 1 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_0_BMSK 0x1 -#define HWIO_REO_R0_ERROR_CODE_RBM_OVERRIDE_REO_ERROR_CODE_0_SHFT 0 - -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x) ((x) + 0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_PHYS(x) ((x) + 0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OFFS (0x1710) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR 0x00060000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ATTR 0x3 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x) \ - in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x), m) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUT(x, v) \ - out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),v) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_IN(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_BMSK 0xf0000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_7_SHFT 28 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_BMSK 0xf000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_6_SHFT 24 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_BMSK 0xf00000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_5_SHFT 20 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_BMSK 0xf0000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_4_SHFT 16 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_BMSK 0xf000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_3_SHFT 12 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_BMSK 0xf00 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_2_SHFT 8 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_BMSK 0xf0 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_1_SHFT 4 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_BMSK 0xf -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_0_RBM_RING_MAPPING_0_SHFT 0 - -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x) ((x) + 0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_PHYS(x) ((x) + 0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OFFS (0x1714) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR 0x00060000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_POR_RMSK 0xffffffff -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ATTR 0x3 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x) \ - in_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_INM(x, m) \ - in_dword_masked(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x), m) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUT(x, v) \ - out_dword(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),v) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_ADDR(x),m,v,HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_IN(x)) -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_BMSK 0xf0000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_15_SHFT 28 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_BMSK 0xf000000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_14_SHFT 24 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_BMSK 0xf00000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_13_SHFT 20 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_BMSK 0xf0000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_12_SHFT 16 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_BMSK 0xf000 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_11_SHFT 12 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_BMSK 0xf00 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_10_SHFT 8 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_BMSK 0xf0 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_9_SHFT 4 -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_BMSK 0xf -#define HWIO_REO_R0_RBM_DESTINATION_RING_CTRL_IX_1_RBM_RING_MAPPING_8_SHFT 0 - -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ADDR(x) ((x) + 0x2008) -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_PHYS(x) ((x) + 0x2008) -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_OFFS (0x2008) -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_RMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_POR 0x00000000 -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_POR_RMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ATTR 0x1 -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_IN(x) \ - in_dword(HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ADDR(x)) -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ADDR(x), m) -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ADDR_39_8_BMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_DELINK_ERROR_MSDU_LINK_ADDR_39_8_SHFT 0 - -#define HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x) ((x) + 0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_PHYS(x) ((x) + 0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_OFFS (0x20c4) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_RMSK 0x3f -#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR 0x00000000 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R1_MISC_DEBUG_STATUS_ATTR 0x1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_IN(x) \ - in_dword(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x)) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x), m) -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_BMSK 0x20 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_SHFT 5 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_BMSK 0x10 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_SHFT 4 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_BMSK 0x8 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_SHFT 3 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_BMSK 0x4 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_SHFT 2 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_BMSK 0x2 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_SHFT 1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_BMSK 0x1 -#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_SHFT 0 - -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x) ((x) + 0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_PHYS(x) ((x) + 0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OFFS (0x20c8) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_RMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR 0x00000000 -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR_RMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ATTR 0x3 -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x) \ - in_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x)) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x), m) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUT(x, v) \ - out_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),v) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),m,v,HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x)) -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_BMSK 0xffffffff -#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_SHFT 0 - -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x20d0) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X20D4 + (0x4*(n))) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_MAXn 255 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) ((x) + 0x3028) -#define HWIO_REO_R2_FW2REO_RING_HP_ADDR(x) ((x) + 0x3048) -#define HWIO_REO_R2_FW2REO_RING_HP_PHYS(x) ((x) + 0x3048) -#define HWIO_REO_R2_FW2REO_RING_HP_OFFS (0x3048) -#define HWIO_REO_R2_FW2REO_RING_HP_RMSK 0xffff -#define HWIO_REO_R2_FW2REO_RING_HP_POR 0x00000000 -#define HWIO_REO_R2_FW2REO_RING_HP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_FW2REO_RING_HP_ATTR 0x3 -#define HWIO_REO_R2_FW2REO_RING_HP_IN(x) \ - in_dword(HWIO_REO_R2_FW2REO_RING_HP_ADDR(x)) -#define HWIO_REO_R2_FW2REO_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_FW2REO_RING_HP_ADDR(x), m) -#define HWIO_REO_R2_FW2REO_RING_HP_OUT(x, v) \ - out_dword(HWIO_REO_R2_FW2REO_RING_HP_ADDR(x),v) -#define HWIO_REO_R2_FW2REO_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_FW2REO_RING_HP_ADDR(x),m,v,HWIO_REO_R2_FW2REO_RING_HP_IN(x)) -#define HWIO_REO_R2_FW2REO_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_REO_R2_FW2REO_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_REO_R2_FW2REO_RING_TP_ADDR(x) ((x) + 0x304c) -#define HWIO_REO_R2_FW2REO_RING_TP_PHYS(x) ((x) + 0x304c) -#define HWIO_REO_R2_FW2REO_RING_TP_OFFS (0x304c) -#define HWIO_REO_R2_FW2REO_RING_TP_RMSK 0xffff -#define HWIO_REO_R2_FW2REO_RING_TP_POR 0x00000000 -#define HWIO_REO_R2_FW2REO_RING_TP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_FW2REO_RING_TP_ATTR 0x3 -#define HWIO_REO_R2_FW2REO_RING_TP_IN(x) \ - in_dword(HWIO_REO_R2_FW2REO_RING_TP_ADDR(x)) -#define HWIO_REO_R2_FW2REO_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_FW2REO_RING_TP_ADDR(x), m) -#define HWIO_REO_R2_FW2REO_RING_TP_OUT(x, v) \ - out_dword(HWIO_REO_R2_FW2REO_RING_TP_ADDR(x),v) -#define HWIO_REO_R2_FW2REO_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_FW2REO_RING_TP_ADDR(x),m,v,HWIO_REO_R2_FW2REO_RING_TP_IN(x)) -#define HWIO_REO_R2_FW2REO_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R2_FW2REO_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R2_FW2REO1_RING_HP_ADDR(x) ((x) + 0x3050) -#define HWIO_REO_R2_FW2REO1_RING_HP_PHYS(x) ((x) + 0x3050) -#define HWIO_REO_R2_FW2REO1_RING_HP_OFFS (0x3050) -#define HWIO_REO_R2_FW2REO1_RING_HP_RMSK 0xffff -#define HWIO_REO_R2_FW2REO1_RING_HP_POR 0x00000000 -#define HWIO_REO_R2_FW2REO1_RING_HP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_FW2REO1_RING_HP_ATTR 0x3 -#define HWIO_REO_R2_FW2REO1_RING_HP_IN(x) \ - in_dword(HWIO_REO_R2_FW2REO1_RING_HP_ADDR(x)) -#define HWIO_REO_R2_FW2REO1_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_FW2REO1_RING_HP_ADDR(x), m) -#define HWIO_REO_R2_FW2REO1_RING_HP_OUT(x, v) \ - out_dword(HWIO_REO_R2_FW2REO1_RING_HP_ADDR(x),v) -#define HWIO_REO_R2_FW2REO1_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_FW2REO1_RING_HP_ADDR(x),m,v,HWIO_REO_R2_FW2REO1_RING_HP_IN(x)) -#define HWIO_REO_R2_FW2REO1_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_REO_R2_FW2REO1_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_REO_R2_FW2REO1_RING_TP_ADDR(x) ((x) + 0x3054) -#define HWIO_REO_R2_FW2REO1_RING_TP_PHYS(x) ((x) + 0x3054) -#define HWIO_REO_R2_FW2REO1_RING_TP_OFFS (0x3054) -#define HWIO_REO_R2_FW2REO1_RING_TP_RMSK 0xffff -#define HWIO_REO_R2_FW2REO1_RING_TP_POR 0x00000000 -#define HWIO_REO_R2_FW2REO1_RING_TP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_FW2REO1_RING_TP_ATTR 0x3 -#define HWIO_REO_R2_FW2REO1_RING_TP_IN(x) \ - in_dword(HWIO_REO_R2_FW2REO1_RING_TP_ADDR(x)) -#define HWIO_REO_R2_FW2REO1_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_FW2REO1_RING_TP_ADDR(x), m) -#define HWIO_REO_R2_FW2REO1_RING_TP_OUT(x, v) \ - out_dword(HWIO_REO_R2_FW2REO1_RING_TP_ADDR(x),v) -#define HWIO_REO_R2_FW2REO1_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_FW2REO1_RING_TP_ADDR(x),m,v,HWIO_REO_R2_FW2REO1_RING_TP_IN(x)) -#define HWIO_REO_R2_FW2REO1_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R2_FW2REO1_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) ((x) + 0x3070) -#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) ((x) + 0x3074) -#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) ((x) + 0x3078) -#define HWIO_REO_R2_REO2SW9_RING_HP_ADDR(x) ((x) + 0x30b0) -#define HWIO_REO_R2_REO2SW9_RING_HP_PHYS(x) ((x) + 0x30b0) -#define HWIO_REO_R2_REO2SW9_RING_HP_OFFS (0x30b0) -#define HWIO_REO_R2_REO2SW9_RING_HP_RMSK 0xfffff -#define HWIO_REO_R2_REO2SW9_RING_HP_POR 0x00000000 -#define HWIO_REO_R2_REO2SW9_RING_HP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_REO2SW9_RING_HP_ATTR 0x3 -#define HWIO_REO_R2_REO2SW9_RING_HP_IN(x) \ - in_dword(HWIO_REO_R2_REO2SW9_RING_HP_ADDR(x)) -#define HWIO_REO_R2_REO2SW9_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_REO2SW9_RING_HP_ADDR(x), m) -#define HWIO_REO_R2_REO2SW9_RING_HP_OUT(x, v) \ - out_dword(HWIO_REO_R2_REO2SW9_RING_HP_ADDR(x),v) -#define HWIO_REO_R2_REO2SW9_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_REO2SW9_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW9_RING_HP_IN(x)) -#define HWIO_REO_R2_REO2SW9_RING_HP_HEAD_PTR_BMSK 0xfffff -#define HWIO_REO_R2_REO2SW9_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_REO_R2_REO2SW9_RING_TP_ADDR(x) ((x) + 0x30b4) -#define HWIO_REO_R2_REO2SW9_RING_TP_PHYS(x) ((x) + 0x30b4) -#define HWIO_REO_R2_REO2SW9_RING_TP_OFFS (0x30b4) -#define HWIO_REO_R2_REO2SW9_RING_TP_RMSK 0xfffff -#define HWIO_REO_R2_REO2SW9_RING_TP_POR 0x00000000 -#define HWIO_REO_R2_REO2SW9_RING_TP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_REO2SW9_RING_TP_ATTR 0x3 -#define HWIO_REO_R2_REO2SW9_RING_TP_IN(x) \ - in_dword(HWIO_REO_R2_REO2SW9_RING_TP_ADDR(x)) -#define HWIO_REO_R2_REO2SW9_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_REO2SW9_RING_TP_ADDR(x), m) -#define HWIO_REO_R2_REO2SW9_RING_TP_OUT(x, v) \ - out_dword(HWIO_REO_R2_REO2SW9_RING_TP_ADDR(x),v) -#define HWIO_REO_R2_REO2SW9_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_REO2SW9_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW9_RING_TP_IN(x)) -#define HWIO_REO_R2_REO2SW9_RING_TP_TAIL_PTR_BMSK 0xfffff -#define HWIO_REO_R2_REO2SW9_RING_TP_TAIL_PTR_SHFT 0 -#define TQM_REG_REG_BASE (UMAC_BASE + 0x0003c000) -#define TQM_REG_REG_BASE_SIZE 0x4000 - -#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x) ((x) + 0x30b8) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ADDR(x) ((x) + 0x3118) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_PHYS(x) ((x) + 0x3118) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_OFFS (0x3118) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_RMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_POR 0x00000000 -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ATTR 0x3 -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_IN(x) \ - in_dword(HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ADDR(x)) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ADDR(x), m) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_OUT(x, v) \ - out_dword(HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ADDR(x),v) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO0_C_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO0_C_RING_HP_IN(x)) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO0_C_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ADDR(x) ((x) + 0x311c) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_PHYS(x) ((x) + 0x311c) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_OFFS (0x311c) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_RMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_POR 0x00000000 -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ATTR 0x3 -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_IN(x) \ - in_dword(HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ADDR(x)) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ADDR(x), m) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_OUT(x, v) \ - out_dword(HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ADDR(x),v) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO0_C_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO0_C_RING_TP_IN(x)) -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO0_C_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ADDR(x) ((x) + 0x3120) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_PHYS(x) ((x) + 0x3120) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_OFFS (0x3120) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_RMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_POR 0x00000000 -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ATTR 0x3 -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_IN(x) \ - in_dword(HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ADDR(x)) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ADDR(x), m) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_OUT(x, v) \ - out_dword(HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ADDR(x),v) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO1_C_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO1_C_RING_HP_IN(x)) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO1_C_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ADDR(x) ((x) + 0x3124) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_PHYS(x) ((x) + 0x3124) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_OFFS (0x3124) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_RMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_POR 0x00000000 -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ATTR 0x3 -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_IN(x) \ - in_dword(HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ADDR(x)) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ADDR(x), m) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_OUT(x, v) \ - out_dword(HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ADDR(x),v) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO1_C_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO1_C_RING_TP_IN(x)) -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO1_C_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ADDR(x) ((x) + 0x3128) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_PHYS(x) ((x) + 0x3128) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_OFFS (0x3128) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_RMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_POR 0x00000000 -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ATTR 0x3 -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_IN(x) \ - in_dword(HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ADDR(x)) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ADDR(x), m) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_OUT(x, v) \ - out_dword(HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ADDR(x),v) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO0_P_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO0_P_RING_HP_IN(x)) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO0_P_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ADDR(x) ((x) + 0x312c) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_PHYS(x) ((x) + 0x312c) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_OFFS (0x312c) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_RMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_POR 0x00000000 -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ATTR 0x3 -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_IN(x) \ - in_dword(HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ADDR(x)) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ADDR(x), m) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_OUT(x, v) \ - out_dword(HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ADDR(x),v) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO0_P_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO0_P_RING_TP_IN(x)) -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO0_P_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ADDR(x) ((x) + 0x3130) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_PHYS(x) ((x) + 0x3130) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_OFFS (0x3130) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_RMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_POR 0x00000000 -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ATTR 0x3 -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_IN(x) \ - in_dword(HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ADDR(x)) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ADDR(x), m) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_OUT(x, v) \ - out_dword(HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ADDR(x),v) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO1_P_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO1_P_RING_HP_IN(x)) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO1_P_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ADDR(x) ((x) + 0x3134) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_PHYS(x) ((x) + 0x3134) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_OFFS (0x3134) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_RMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_POR 0x00000000 -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_POR_RMSK 0xffffffff -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ATTR 0x3 -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_IN(x) \ - in_dword(HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ADDR(x)) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ADDR(x), m) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_OUT(x, v) \ - out_dword(HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ADDR(x),v) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_REO_R2_SW2FW_REO1_P_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2FW_REO1_P_RING_TP_IN(x)) -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_REO_R2_SW2FW_REO1_P_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_BMSK 0x80 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_SHFT 7 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_BMSK 0x40 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_SHFT 6 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_BMSK 0x20 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_SHFT 5 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_BMSK 0x10 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_SHFT 4 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_BMSK 0x8 -#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_SHFT 3 -#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x64c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x64c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_OFFS (0x64c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x650) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x650) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_OFFS (0x650) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ADDR(x) ((x) + 0x654) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_PHYS(x) ((x) + 0x654) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_OFFS (0x654) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x658) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x658) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_OFFS (0x658) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADDR(x) ((x) + 0x65c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_PHYS(x) ((x) + 0x65c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_OFFS (0x65c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x660) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x660) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_OFFS (0x660) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x664) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x664) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_OFFS (0x664) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x670) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x670) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x670) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x674) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x674) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x674) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x678) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x678) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x678) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x694) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x694) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x694) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x698) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x698) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x698) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x69c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x69c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_OFFS (0x69c) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x6a0) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x6a0) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x6a0) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x6a4) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x6a4) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x6a4) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x6a8) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x6a8) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x6a8) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x6ac) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x6ac) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_OFFS (0x6ac) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x6bc) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x6bc) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x6bc) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x6c0) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x6c0) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_OFFS (0x6c0) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM2FW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x6c4) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x6c4) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_OFFS (0x6c4) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x6c8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x6c8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_OFFS (0x6c8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ADDR(x) ((x) + 0x6cc) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_PHYS(x) ((x) + 0x6cc) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_OFFS (0x6cc) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x6d0) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x6d0) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_OFFS (0x6d0) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADDR(x) ((x) + 0x6d4) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_PHYS(x) ((x) + 0x6d4) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_OFFS (0x6d4) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6d8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6d8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_OFFS (0x6d8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x6dc) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x6dc) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_OFFS (0x6dc) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x6e8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x6e8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x6e8) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x6ec) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x6ec) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x6ec) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x6f0) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x6f0) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x6f0) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x70c) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x70c) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x70c) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x710) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x710) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x710) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x714) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x714) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_OFFS (0x714) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x718) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x718) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x718) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x71c) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x71c) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x71c) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x720) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x720) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x720) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x724) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x724) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_OFFS (0x724) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x734) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x734) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x734) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x738) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x738) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_OFFS (0x738) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM_ERROR_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OFFS (0x73c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x740) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x740) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_OFFS (0x740) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ADDR(x) ((x) + 0x744) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_PHYS(x) ((x) + 0x744) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_OFFS (0x744) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x748) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x748) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_OFFS (0x748) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADDR(x) ((x) + 0x74c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_PHYS(x) ((x) + 0x74c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_OFFS (0x74c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x750) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x750) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_OFFS (0x750) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x754) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x754) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_OFFS (0x754) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x760) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x760) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x760) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x764) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x764) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x764) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x768) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x768) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x768) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x784) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x784) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x784) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x788) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x788) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x788) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x78c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x78c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_OFFS (0x78c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x790) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x790) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x790) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x794) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x794) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x794) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x798) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x798) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x798) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x79c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x79c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_OFFS (0x79c) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x7ac) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x7ac) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x7ac) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x7b0) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x7b0) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_OFFS (0x7b0) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM2SW0_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OFFS (0x7b4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x7b8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x7b8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_OFFS (0x7b8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ADDR(x) ((x) + 0x7bc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_PHYS(x) ((x) + 0x7bc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_OFFS (0x7bc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x7c0) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x7c0) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_OFFS (0x7c0) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADDR(x) ((x) + 0x7c4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_PHYS(x) ((x) + 0x7c4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_OFFS (0x7c4) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x7c8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x7c8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_OFFS (0x7c8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x7cc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x7cc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_OFFS (0x7cc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7d8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7d8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x7d8) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x7dc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x7dc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x7dc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x7e0) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x7e0) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x7e0) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x7fc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x7fc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x7fc) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x800) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x800) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x800) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x804) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x804) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_OFFS (0x804) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x808) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x808) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x808) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x80c) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x80c) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x80c) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x810) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x810) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x810) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x814) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x814) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_OFFS (0x814) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x824) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x824) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x824) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x828) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x828) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_OFFS (0x828) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM2SW1_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x82c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x82c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_OFFS (0x82c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x830) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x830) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_OFFS (0x830) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ADDR(x) ((x) + 0x834) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_PHYS(x) ((x) + 0x834) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_OFFS (0x834) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x838) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x838) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_OFFS (0x838) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADDR(x) ((x) + 0x83c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_PHYS(x) ((x) + 0x83c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_OFFS (0x83c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x840) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x840) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_OFFS (0x840) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x844) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x844) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_OFFS (0x844) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x850) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x850) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x850) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x854) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x854) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x854) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x858) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x858) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x858) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x874) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x874) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x874) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x878) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x878) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x878) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x87c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x87c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_OFFS (0x87c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x880) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x880) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x880) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x884) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x884) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x884) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x888) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x888) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x888) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x88c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x88c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_OFFS (0x88c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x89c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x89c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x89c) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x8a0) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x8a0) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_OFFS (0x8a0) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM2SW2_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x8a4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x8a4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_OFFS (0x8a4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x8a8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x8a8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_OFFS (0x8a8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ADDR(x) ((x) + 0x8ac) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_PHYS(x) ((x) + 0x8ac) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_OFFS (0x8ac) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x8b0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x8b0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_OFFS (0x8b0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADDR(x) ((x) + 0x8b4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_PHYS(x) ((x) + 0x8b4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_OFFS (0x8b4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x8b8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x8b8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_OFFS (0x8b8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x8bc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x8bc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_OFFS (0x8bc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x8c8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x8c8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x8c8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x8cc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x8cc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x8cc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x8d0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x8d0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x8d0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x8ec) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x8ec) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x8ec) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x8f0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x8f0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x8f0) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x8f4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x8f4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_OFFS (0x8f4) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x8f8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x8f8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x8f8) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x8fc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x8fc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x8fc) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x900) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x900) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x900) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x904) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x904) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_OFFS (0x904) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x914) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x914) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x914) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x918) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x918) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_OFFS (0x918) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM2SW3_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x91c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x91c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_OFFS (0x91c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x920) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x920) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_OFFS (0x920) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ADDR(x) ((x) + 0x924) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_PHYS(x) ((x) + 0x924) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_OFFS (0x924) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x928) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x928) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_OFFS (0x928) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADDR(x) ((x) + 0x92c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_PHYS(x) ((x) + 0x92c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_OFFS (0x92c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x930) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x930) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_OFFS (0x930) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x934) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x934) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_OFFS (0x934) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x940) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x940) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x940) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x944) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x944) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x944) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x948) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x948) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x948) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x964) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x964) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x964) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x968) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x968) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x968) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x96c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x96c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_OFFS (0x96c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x970) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x970) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x970) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x974) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x974) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x974) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x978) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x978) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x978) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x97c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x97c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_OFFS (0x97c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x98c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x98c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x98c) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x990) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x990) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_OFFS (0x990) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM2SW4_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x994) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x994) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_OFFS (0x994) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x998) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x998) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_OFFS (0x998) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ADDR(x) ((x) + 0x99c) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_PHYS(x) ((x) + 0x99c) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_OFFS (0x99c) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x9a0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x9a0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_OFFS (0x9a0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADDR(x) ((x) + 0x9a4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_PHYS(x) ((x) + 0x9a4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_OFFS (0x9a4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x9a8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x9a8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_OFFS (0x9a8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x9ac) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x9ac) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_OFFS (0x9ac) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x9b8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x9b8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x9b8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x9bc) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x9bc) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x9bc) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x9c0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x9c0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x9c0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x9dc) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x9dc) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x9dc) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x9e0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x9e0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x9e0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x9e4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x9e4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_OFFS (0x9e4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x9e8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x9e8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x9e8) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x9ec) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x9ec) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x9ec) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x9f0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x9f0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x9f0) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x9f4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x9f4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_OFFS (0x9f4) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xa04) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xa04) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xa04) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xa08) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xa08) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_OFFS (0xa08) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM2SW5_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xa0c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xa0c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_OFFS (0xa0c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xa10) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xa10) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_OFFS (0xa10) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ADDR(x) ((x) + 0xa14) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_PHYS(x) ((x) + 0xa14) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_OFFS (0xa14) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_RING_ID_BMSK 0xff00 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_RING_ID_SHFT 8 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xa18) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xa18) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_OFFS (0xa18) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADDR(x) ((x) + 0xa1c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_PHYS(x) ((x) + 0xa1c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_OFFS (0xa1c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xa20) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xa20) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_OFFS (0xa20) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xa24) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xa24) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_OFFS (0xa24) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xa30) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xa30) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xa30) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xa34) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xa34) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xa34) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xa38) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xa38) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xa38) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa54) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa54) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xa54) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa58) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa58) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xa58) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xa5c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xa5c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_OFFS (0xa5c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xa60) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xa60) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xa60) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xa64) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xa64) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_OFFS (0xa64) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xa68) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xa68) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_OFFS (0xa68) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0xa6c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0xa6c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_OFFS (0xa6c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xa7c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xa7c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xa7c) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xa80) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xa80) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_OFFS (0xa80) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_TQM2SW6_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xdcc) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xdd0) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xdd4) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xdd8) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xddc) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xddc) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_OFFS (0xddc) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xde0) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xde0) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_OFFS (0xde0) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_RMSK 0xffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ADDR(x) ((x) + 0xde4) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_PHYS(x) ((x) + 0xde4) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_OFFS (0xde4) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_RMSK 0xff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xde8) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xde8) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_OFFS (0xde8) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ADDR(x) ((x) + 0xdec) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_PHYS(x) ((x) + 0xdec) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_OFFS (0xdec) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_RMSK 0x7fffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_POR 0x00000080 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xdf8) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xdf8) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_OFFS (0xdf8) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xdfc) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xdfc) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_OFFS (0xdfc) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_RMSK 0xff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xe0c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xe0c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xe0c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xe10) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xe10) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xe10) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xe14) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xe14) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_OFFS (0xe14) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xe18) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xe18) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xe18) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xe1c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xe1c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xe1c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xe20) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xe20) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xe20) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xe24) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xe24) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xe24) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xe28) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xe28) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xe28) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xe2c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xe2c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_OFFS (0xe2c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xe4c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xe4c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xe4c) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xe50) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xe50) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_OFFS (0xe50) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_POR 0x00000000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ATTR 0x3 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_IN(x) \ - in_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ADDR(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ADDR(x), m) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ADDR(x),v) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_IN(x)) -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TQM_R0_FW2TQM_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TQM_R0_EVENTMASK_IX_4_ADDR(x) ((x) + 0xeac) -#define HWIO_TQM_R0_EVENTMASK_IX_4_PHYS(x) ((x) + 0xeac) -#define HWIO_TQM_R0_EVENTMASK_IX_4_OFFS (0xeac) -#define HWIO_TQM_R0_EVENTMASK_IX_4_RMSK 0xffffffff -#define HWIO_TQM_R0_EVENTMASK_IX_4_POR 0x00000000 -#define HWIO_TQM_R0_EVENTMASK_IX_4_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_EVENTMASK_IX_4_ATTR 0x3 -#define HWIO_TQM_R0_EVENTMASK_IX_4_IN(x) \ - in_dword(HWIO_TQM_R0_EVENTMASK_IX_4_ADDR(x)) -#define HWIO_TQM_R0_EVENTMASK_IX_4_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_EVENTMASK_IX_4_ADDR(x), m) -#define HWIO_TQM_R0_EVENTMASK_IX_4_OUT(x, v) \ - out_dword(HWIO_TQM_R0_EVENTMASK_IX_4_ADDR(x),v) -#define HWIO_TQM_R0_EVENTMASK_IX_4_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_EVENTMASK_IX_4_ADDR(x),m,v,HWIO_TQM_R0_EVENTMASK_IX_4_IN(x)) -#define HWIO_TQM_R0_EVENTMASK_IX_4_MASK_BMSK 0xffffffff -#define HWIO_TQM_R0_EVENTMASK_IX_4_MASK_SHFT 0 - -#define HWIO_TQM_R0_EVENTMASK_IX_5_ADDR(x) ((x) + 0xeb0) -#define HWIO_TQM_R0_EVENTMASK_IX_5_PHYS(x) ((x) + 0xeb0) -#define HWIO_TQM_R0_EVENTMASK_IX_5_OFFS (0xeb0) -#define HWIO_TQM_R0_EVENTMASK_IX_5_RMSK 0xffffffff -#define HWIO_TQM_R0_EVENTMASK_IX_5_POR 0x00000000 -#define HWIO_TQM_R0_EVENTMASK_IX_5_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_EVENTMASK_IX_5_ATTR 0x3 -#define HWIO_TQM_R0_EVENTMASK_IX_5_IN(x) \ - in_dword(HWIO_TQM_R0_EVENTMASK_IX_5_ADDR(x)) -#define HWIO_TQM_R0_EVENTMASK_IX_5_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_EVENTMASK_IX_5_ADDR(x), m) -#define HWIO_TQM_R0_EVENTMASK_IX_5_OUT(x, v) \ - out_dword(HWIO_TQM_R0_EVENTMASK_IX_5_ADDR(x),v) -#define HWIO_TQM_R0_EVENTMASK_IX_5_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_EVENTMASK_IX_5_ADDR(x),m,v,HWIO_TQM_R0_EVENTMASK_IX_5_IN(x)) -#define HWIO_TQM_R0_EVENTMASK_IX_5_MASK_BMSK 0xffffffff -#define HWIO_TQM_R0_EVENTMASK_IX_5_MASK_SHFT 0 - -#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_BMSK 0x80000000 -#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_SHFT 31 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_EMPTY_INDICATION_UPDATE_BMSK 0x10000 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_EMPTY_INDICATION_UPDATE_SHFT 16 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_BMSK 0x8000 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_SHFT 15 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_BMSK 0x4000 -#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_SHFT 14 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_BMSK 0x2000 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_SHFT 13 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_BMSK 0x1000 -#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_SHFT 12 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_BMSK 0x800 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_SHFT 11 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_BMSK 0x400 -#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_SHFT 10 -#define HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_OFFS (0xed8) -#define HWIO_TQM_R0_LPM_FW_CTRL_RMSK 0xf -#define HWIO_TQM_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_TQM_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TQM_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x) ((x) + 0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_PHYS(x) ((x) + 0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OFFS (0xee0) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_RMSK 0x1ffff -#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR 0x00000000 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CLKGATE_CTRL_2_ATTR 0x3 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x) \ - in_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x)) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x), m) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUT(x, v) \ - out_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),v) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),m,v,HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x)) -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TQM_STATUS_MEM_BMSK 0x10000 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TQM_STATUS_MEM_SHFT 16 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TQM_PREFETCH_MEM_BMSK 0x8000 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TQM_PREFETCH_MEM_SHFT 15 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LINK_ZERO_OUT_BMSK 0x4000 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LINK_ZERO_OUT_SHFT 14 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_MSDU_DELINK_BMSK 0x2000 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_MSDU_DELINK_SHFT 13 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_RLS_REQ_PARSER_BMSK 0x1000 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_RLS_REQ_PARSER_SHFT 12 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW6_PROD_RELEASE_BMSK 0x800 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW6_PROD_RELEASE_SHFT 11 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW5_PROD_RELEASE_BMSK 0x400 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW5_PROD_RELEASE_SHFT 10 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW4_PROD_RELEASE_BMSK 0x200 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW4_PROD_RELEASE_SHFT 9 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW3_PROD_RELEASE_BMSK 0x100 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW3_PROD_RELEASE_SHFT 8 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW2_PROD_RELEASE_BMSK 0x80 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW2_PROD_RELEASE_SHFT 7 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW1_PROD_RELEASE_BMSK 0x40 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW1_PROD_RELEASE_SHFT 6 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW0_PROD_RELEASE_BMSK 0x20 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_SW0_PROD_RELEASE_SHFT 5 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_FW2TQM_RELEASE_RING_SM_BMSK 0x10 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_FW2TQM_RELEASE_RING_SM_SHFT 4 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_ERROR_RELEASE_BMSK 0x8 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_ERROR_RELEASE_SHFT 3 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_FW_PROD_RELEASE_BMSK 0x4 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_FW_PROD_RELEASE_SHFT 2 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_BMSK 0x2 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_SHFT 1 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_BMSK 0x1 -#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_SHFT 0 - -#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_BMSK 0x20000000 -#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_SHFT 29 -#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_FW2TQM_RELEASE_RING_BMSK 0xc00000 -#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_FW2TQM_RELEASE_RING_SHFT 22 -#define HWIO_TQM_R0_VC_ID_FW2TQM_RELEASE_C_SRNG_BMSK 0x40 -#define HWIO_TQM_R0_VC_ID_FW2TQM_RELEASE_C_SRNG_SHFT 6 -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x) ((x) + 0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_PHYS(x) ((x) + 0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OFFS (0xf70) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_SHFT 0 - -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x) ((x) + 0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_PHYS(x) ((x) + 0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OFFS (0xf74) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_SHFT 0 - -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x) ((x) + 0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_PHYS(x) ((x) + 0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OFFS (0xf78) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR 0x00000000 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ATTR 0x3 -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x) \ - in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x), m) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),v) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x)) -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_SHFT 0 - -#define HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x) ((x) + 0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_PHYS(x) ((x) + 0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OFFS (0xf84) -#define HWIO_TQM_R0_WATCHDOG_SRNG_RMSK 0xfff -#define HWIO_TQM_R0_WATCHDOG_SRNG_POR 0x00000710 -#define HWIO_TQM_R0_WATCHDOG_SRNG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_WATCHDOG_SRNG_ATTR 0x3 -#define HWIO_TQM_R0_WATCHDOG_SRNG_IN(x) \ - in_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x)) -#define HWIO_TQM_R0_WATCHDOG_SRNG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x), m) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),v) -#define HWIO_TQM_R0_WATCHDOG_SRNG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_SRNG_IN(x)) -#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_BMSK 0xfff -#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_SHFT 0 - -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x) ((x) + 0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_PHYS(x) ((x) + 0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OFFS (0x1204) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_RMSK 0x1ff -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR 0x000001fe -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM_COOKIE_CONV_GLOBAL_ENABLE_SHFT 8 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_BMSK 0x80 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW6_COOKIE_CONVERSION_EN_SHFT 7 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_BMSK 0x40 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW5_COOKIE_CONVERSION_EN_SHFT 6 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_BMSK 0x20 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW4_COOKIE_CONVERSION_EN_SHFT 5 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_BMSK 0x10 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW3_COOKIE_CONVERSION_EN_SHFT 4 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_BMSK 0x8 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW2_COOKIE_CONVERSION_EN_SHFT 3 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_BMSK 0x4 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW1_COOKIE_CONVERSION_EN_SHFT 2 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_BMSK 0x2 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2SW0_COOKIE_CONVERSION_EN_SHFT 1 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_BMSK 0x1 -#define HWIO_TQM_R0_SW_COOKIE_CONVERT_CFG_TQM2FW_COOKIE_CONVERSION_EN_SHFT 0 - -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_ADDR(x) ((x) + 0x120c) -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_PHYS(x) ((x) + 0x120c) -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_OFFS (0x120c) -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_RMSK 0xfffff -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_POR 0x00000000 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_ATTR 0x3 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_IN(x) \ - in_dword(HWIO_TQM_R0_RING_PRIORITY_CFG1_ADDR(x)) -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_RING_PRIORITY_CFG1_ADDR(x), m) -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_RING_PRIORITY_CFG1_ADDR(x),v) -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_RING_PRIORITY_CFG1_ADDR(x),m,v,HWIO_TQM_R0_RING_PRIORITY_CFG1_IN(x)) -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_SW_COOKIE_CONV_GXI_PRIORITY_BMSK 0xc0000 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_SW_COOKIE_CONV_GXI_PRIORITY_SHFT 18 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW6_RELEASE_RING_PRIORITY_BMSK 0x30000 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW6_RELEASE_RING_PRIORITY_SHFT 16 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW5_RELEASE_RING_PRIORITY_BMSK 0xc000 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW5_RELEASE_RING_PRIORITY_SHFT 14 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM_ERROR_RELEASE_RING_PRIORITY_BMSK 0x3000 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM_ERROR_RELEASE_RING_PRIORITY_SHFT 12 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW4_RELEASE_RING_PRIORITY_BMSK 0xc00 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW4_RELEASE_RING_PRIORITY_SHFT 10 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW3_RELEASE_RING_PRIORITY_BMSK 0x300 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW3_RELEASE_RING_PRIORITY_SHFT 8 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW2_RELEASE_RING_PRIORITY_BMSK 0xc0 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW2_RELEASE_RING_PRIORITY_SHFT 6 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW1_RELEASE_RING_PRIORITY_BMSK 0x30 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW1_RELEASE_RING_PRIORITY_SHFT 4 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW0_RELEASE_RING_PRIORITY_BMSK 0xc -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2SW0_RELEASE_RING_PRIORITY_SHFT 2 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2FW_RELEASE_RING_PRIORITY_BMSK 0x3 -#define HWIO_TQM_R0_RING_PRIORITY_CFG1_TQM2FW_RELEASE_RING_PRIORITY_SHFT 0 - -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1214) -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1214) -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_OFFS (0x1214) -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_RMSK 0x3fff -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x3f80 -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_SW0_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1218) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1218) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_OFFS (0x1218) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_RMSK 0xff -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0xfe -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x121c) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x121c) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_OFFS (0x121c) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1220) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1220) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_OFFS (0x1220) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW0_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1224) -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1224) -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_OFFS (0x1224) -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_RMSK 0x3fff -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x3f80 -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_SW1_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1228) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1228) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_OFFS (0x1228) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_RMSK 0xff -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0xfe -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x122c) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x122c) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_OFFS (0x122c) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1230) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1230) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_OFFS (0x1230) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW1_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1234) -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1234) -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_OFFS (0x1234) -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_RMSK 0x3fff -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x3f80 -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_SW2_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1238) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1238) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_OFFS (0x1238) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_RMSK 0xff -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0xfe -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x123c) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x123c) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_OFFS (0x123c) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1240) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1240) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_OFFS (0x1240) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW2_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1244) -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1244) -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_OFFS (0x1244) -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_RMSK 0x3fff -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x3f80 -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_SW3_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1248) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1248) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_OFFS (0x1248) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_RMSK 0xff -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0xfe -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x124c) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x124c) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_OFFS (0x124c) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1250) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1250) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_OFFS (0x1250) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW3_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1254) -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1254) -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_OFFS (0x1254) -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_RMSK 0x3fff -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x3f80 -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_SW4_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1258) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1258) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_OFFS (0x1258) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_RMSK 0xff -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0xfe -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x125c) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x125c) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_OFFS (0x125c) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1260) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1260) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_OFFS (0x1260) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW4_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1264) -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1264) -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_OFFS (0x1264) -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_RMSK 0x3fff -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x3f80 -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_SW5_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1268) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1268) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_OFFS (0x1268) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_RMSK 0xff -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0xfe -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x126c) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x126c) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_OFFS (0x126c) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1270) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1270) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_OFFS (0x1270) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW5_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1274) -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1274) -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_OFFS (0x1274) -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_RMSK 0x1fff -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x1f80 -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_SW6_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1278) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1278) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_OFFS (0x1278) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_RMSK 0x7f -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x7e -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x127c) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x127c) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_OFFS (0x127c) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1280) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1280) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_OFFS (0x1280) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_SW6_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x12d4) -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x12d4) -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_OFFS (0x12d4) -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_RMSK 0x1fff -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x1f80 -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_FW_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x12d8) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x12d8) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_OFFS (0x12d8) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_RMSK 0x7f -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x7e -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x12dc) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x12dc) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_OFFS (0x12dc) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x12e0) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x12e0) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_OFFS (0x12e0) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_FW_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x12e4) -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x12e4) -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_OFFS (0x12e4) -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_RMSK 0x1fff -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x1f80 -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_ERR_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x12e8) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x12e8) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_OFFS (0x12e8) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_RMSK 0x7f -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x7e -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x12ec) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x12ec) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_OFFS (0x12ec) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x12f0) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x12f0) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_OFFS (0x12f0) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_ERR_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x) ((x) + 0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PHYS(x) ((x) + 0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OFFS (0x12f4) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RMSK 0x3fefff -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR 0x00080170 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ATTR 0x3 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x) \ - in_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x)) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x), m) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT(x, v) \ - out_dword(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),v) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ADDR(x),m,v,HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_IN(x)) -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_BMSK 0x200000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ZERO_OUT_LOGIC_GXI_SWAP_SHFT 21 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_BMSK 0x100000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_PROD_FIFO_BUNCHING_DISABLE_SHFT 20 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_BMSK 0x80000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LINK_DESC_CONTENT_CLEAR_ENABLE_SHFT 19 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_BMSK 0x40000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_FUNCTION_ENABLE_SHFT 18 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_BMSK 0x20000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_CACHE1_GXI_VC_ID_SHFT 17 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_BMSK 0x10000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_VC_ID_SHFT 16 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_BMSK 0x8000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_LPM_CACHE_SELF_FLUSH_ENABLE_SHFT 15 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_BMSK 0x4000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_READ_STRUCT_SWAP_SHFT 14 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_BMSK 0x2000 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_GXI_WRITE_STRUCT_SWAP_SHFT 13 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_BMSK 0x800 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TQM_VC_ID_DISABLE_SHFT 11 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_BMSK 0x400 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_VA_GXI_READ_SWAP_SHFT 10 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_BMSK 0x200 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERR_LOG_ON_EGRESS_FULL_SHFT 9 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_BMSK 0x100 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_FW_REINJECTION_FIX_ENABLE_SHFT 8 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_BMSK 0x80 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_REQ_FSM_STUCK_EN_SHFT 7 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_BMSK 0x40 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_DEBUG_SEL_SHFT 6 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_BMSK 0x20 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_UPDATE_SHFT 5 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_BMSK 0x10 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_TRANS_BUNCHING_256B_EN_SHFT 4 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_BMSK 0x8 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_COOKIE_CONV_INDICATION_EN_SHFT 3 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_BMSK 0x4 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_OUT_OF_ORDER_RELEASE_EN_SHFT 2 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_BMSK 0x2 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_ERROR_PATH_COOKIE_CONV_EN_SHFT 1 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_BMSK 0x1 -#define HWIO_TQM_R0_TX_COMPLETION_MISC_CFG_RELEASE_PATH_COOKIE_CONV_EN_SHFT 0 - -#define HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_PHYS(x) ((x) + 0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OFFS (0x12f8) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR 0x00000000 -#define HWIO_TQM_R0_SW_COOKIE_CFG0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG0_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG0_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PHYS(x) ((x) + 0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OFFS (0x12fc) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_RMSK 0x7ffff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR 0x00011100 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_ATTR 0x3 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x) \ - in_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x), m) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUT(x, v) \ - out_dword(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),v) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_SW_COOKIE_CFG1_ADDR(x),m,v,HWIO_TQM_R0_SW_COOKIE_CFG1_IN(x)) -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 -#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 - -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1300) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1300) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_OFFS (0x1300) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_RMSK 0x7f -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_PTR_BMSK 0x7e -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_ADDR(x) ((x) + 0x1304) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_PHYS(x) ((x) + 0x1304) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_OFFS (0x1304) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_RMSK 0x1fff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x1f80 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_UD_CNT_BMSK 0x7f -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1308) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1308) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_OFFS (0x1308) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x130c) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x130c) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_OFFS (0x130c) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_ADDR(x) ((x) + 0x1310) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_PHYS(x) ((x) + 0x1310) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_OFFS (0x1310) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_RMSK 0x1f -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x18 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_INTERNAL_PTR_SHFT 3 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_UD_CNT_BMSK 0x7 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1314) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1314) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_OFFS (0x1314) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RMSK 0x7 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_PTR_BMSK 0x6 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1318) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1318) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_OFFS (0x1318) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_ADDR(x) ((x) + 0x131c) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_PHYS(x) ((x) + 0x131c) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_OFFS (0x131c) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_RMSK 0x1f -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x18 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_INTERNAL_PTR_SHFT 3 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_UD_CNT_BMSK 0x7 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1320) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1320) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_OFFS (0x1320) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_RMSK 0x7 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_RD_PTR_BMSK 0x6 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1324) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1324) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_OFFS (0x1324) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL1_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ADDR(x) ((x) + 0x1328) -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_PHYS(x) ((x) + 0x1328) -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_OFFS (0x1328) -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_RMSK 0xfffffff -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_POR 0x00000000 -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ATTR 0x1 -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_IN(x) \ - in_dword(HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ADDR(x)) -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ADDR(x), m) -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_VALUE_BMSK 0xfffffff -#define HWIO_TQM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_VALUE_SHFT 0 - -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x) ((x) + 0x132c) -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_PHYS(x) ((x) + 0x132c) -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_OFFS (0x132c) -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_RMSK 0x3fff -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_POR 0x00000000 -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ATTR 0x3 -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_IN(x) \ - in_dword(HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x)) -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x), m) -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_OUT(x, v) \ - out_dword(HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x),v) -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_IN(x)) -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_RESOLUTION_UNITS_BMSK 0x3000 -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_RESOLUTION_UNITS_SHFT 12 -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_VALUE_BMSK 0xfff -#define HWIO_TQM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_VALUE_SHFT 0 - -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ADDR(x) ((x) + 0x1330) -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_PHYS(x) ((x) + 0x1330) -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_OFFS (0x1330) -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_RMSK 0xfffffff -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_POR 0x00000000 -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ATTR 0x1 -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_IN(x) \ - in_dword(HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ADDR(x)) -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ADDR(x), m) -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_VALUE_BMSK 0xfffffff -#define HWIO_TQM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_VALUE_SHFT 0 - -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_ADDR(x) ((x) + 0x1334) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_PHYS(x) ((x) + 0x1334) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_OFFS (0x1334) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_RMSK 0x7ff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_POR 0x00000000 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_ATTR 0x1 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_IN(x) \ - in_dword(HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_ADDR(x)) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_ADDR(x), m) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x7c0 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_INTERNAL_PTR_SHFT 6 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_UD_CNT_BMSK 0x3f -#define HWIO_TQM_R0_RLS_PARSER_FIFO_DETAILS_UD_CNT_SHFT 0 - -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1338) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1338) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_OFFS (0x1338) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_RMSK 0x3f -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_POR 0x00000000 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ATTR 0x3 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_IN(x) \ - in_dword(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x)) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x), m) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x),v) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_IN(x)) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_PTR_SHFT 1 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_VALID_SHFT 0 - -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x133c) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x133c) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_OFFS (0x133c) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_RMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_POR 0x00000000 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_ATTR 0x1 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_IN(x) \ - in_dword(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_ADDR(x)) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_ADDR(x), m) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_0_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1340) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1340) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_OFFS (0x1340) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_RMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_POR 0x00000000 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_ATTR 0x1 -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_IN(x) \ - in_dword(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_ADDR(x)) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_ADDR(x), m) -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_FIFO_RD_DATA_1_RD_DATA_SHFT 0 - -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_ADDR(x) ((x) + 0x1344) -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_PHYS(x) ((x) + 0x1344) -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_OFFS (0x1344) -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_RMSK 0x1fffff -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_POR 0x00000000 -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_ATTR 0x1 -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_IN(x) \ - in_dword(HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_ADDR(x)) -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_ADDR(x), m) -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_ERR_BMSK 0x1e0000 -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_ERR_SHFT 17 -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_BMSK 0x1fff0 -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_SHFT 4 -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_P_STATE_ENC_BMSK 0xf -#define HWIO_TQM_R0_RLS_PARSER_SM_STUCK_INFO_P_STATE_ENC_SHFT 0 - -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_ADDR(x) ((x) + 0x1348) -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_PHYS(x) ((x) + 0x1348) -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_OFFS (0x1348) -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_RMSK 0x7 -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_POR 0x00000000 -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_ATTR 0x3 -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_IN(x) \ - in_dword(HWIO_TQM_R0_MSDU_PARSER_CONTROL_ADDR(x)) -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_CONTROL_ADDR(x), m) -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_OUT(x, v) \ - out_dword(HWIO_TQM_R0_MSDU_PARSER_CONTROL_ADDR(x),v) -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_MSDU_PARSER_CONTROL_ADDR(x),m,v,HWIO_TQM_R0_MSDU_PARSER_CONTROL_IN(x)) -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_BMSK 0x4 -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_SHFT 2 -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_BMSK 0x2 -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_SHFT 1 -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_BMSK 0x1 -#define HWIO_TQM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_SHFT 0 - -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_ADDR(x) ((x) + 0x134c) -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_PHYS(x) ((x) + 0x134c) -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_OFFS (0x134c) -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_RMSK 0x3ffff -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_POR 0x00001441 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_ATTR 0x1 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_IN(x) \ - in_dword(HWIO_TQM_R0_MSDU_PARSER_STATUS_ADDR(x)) -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_MSDU_PARSER_STATUS_ADDR(x), m) -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_2_DONE_BMSK 0x20000 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_2_DONE_SHFT 17 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_CACHE_2_STATE_BMSK 0x1f000 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_CACHE_2_STATE_SHFT 12 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_1_DONE_BMSK 0x800 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_1_DONE_SHFT 11 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_BMSK 0x400 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_SHFT 10 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_BMSK 0x3c0 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_SHFT 6 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_BMSK 0x20 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_SHFT 5 -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_BMSK 0x1f -#define HWIO_TQM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_SHFT 0 - -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ADDR(x) ((x) + 0x1350) -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_PHYS(x) ((x) + 0x1350) -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_OFFS (0x1350) -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_RMSK 0xffffffff -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_POR 0x00000000 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ATTR 0x1 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_IN(x) \ - in_dword(HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ADDR(x)) -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ADDR(x), m) -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_OCCURRENCE_BMSK 0x80000000 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_OCCURRENCE_SHFT 31 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_SOURCE_BMSK 0x40000000 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_SOURCE_SHFT 30 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_TYPE_BMSK 0x30000000 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_ERROR_TYPE_SHFT 28 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_SW_BUFFER_COOKIE_BMSK 0xffffe00 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_SW_BUFFER_COOKIE_SHFT 9 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_BM_ACTION_BMSK 0x180 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_BM_ACTION_SHFT 7 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_BUFFER_DESC_TYPE_BMSK 0x70 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_BUFFER_DESC_TYPE_SHFT 4 -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_RETURN_BUFFER_MANAGER_BMSK 0xf -#define HWIO_TQM_R0_TX_COMPLETION_INTERRUPT_DATA_CAPTURE_RETURN_BUFFER_MANAGER_SHFT 0 - -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_ADDR(x) ((x) + 0x1354) -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_PHYS(x) ((x) + 0x1354) -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_OFFS (0x1354) -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_RMSK 0x13fff -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_POR 0x00000020 -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_ATTR 0x3 -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_IN(x) \ - in_dword(HWIO_TQM_R0_RELEASE_RING_FLUSH_ADDR(x)) -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_RELEASE_RING_FLUSH_ADDR(x), m) -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_OUT(x, v) \ - out_dword(HWIO_TQM_R0_RELEASE_RING_FLUSH_ADDR(x),v) -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R0_RELEASE_RING_FLUSH_ADDR(x),m,v,HWIO_TQM_R0_RELEASE_RING_FLUSH_IN(x)) -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_BMSK 0x10000 -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_SHFT 16 -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_BMSK 0x2000 -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_SHFT 13 -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_BMSK 0x1000 -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_SHFT 12 -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_BMSK 0xfff -#define HWIO_TQM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_SHFT 0 - -#define HWIO_TQM_R0_SM_STATES_IX4_ADDR(x) ((x) + 0x15f0) -#define HWIO_TQM_R0_SM_STATES_IX4_PHYS(x) ((x) + 0x15f0) -#define HWIO_TQM_R0_SM_STATES_IX4_OFFS (0x15f0) -#define HWIO_TQM_R0_SM_STATES_IX4_RMSK 0xffffffff -#define HWIO_TQM_R0_SM_STATES_IX4_POR 0x00000000 -#define HWIO_TQM_R0_SM_STATES_IX4_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SM_STATES_IX4_ATTR 0x1 -#define HWIO_TQM_R0_SM_STATES_IX4_IN(x) \ - in_dword(HWIO_TQM_R0_SM_STATES_IX4_ADDR(x)) -#define HWIO_TQM_R0_SM_STATES_IX4_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SM_STATES_IX4_ADDR(x), m) -#define HWIO_TQM_R0_SM_STATES_IX4_SW6_RELEASE_PROD_SM_STATE_BMSK 0xc0000000 -#define HWIO_TQM_R0_SM_STATES_IX4_SW6_RELEASE_PROD_SM_STATE_SHFT 30 -#define HWIO_TQM_R0_SM_STATES_IX4_SW5_RELEASE_PROD_SM_STATE_BMSK 0x30000000 -#define HWIO_TQM_R0_SM_STATES_IX4_SW5_RELEASE_PROD_SM_STATE_SHFT 28 -#define HWIO_TQM_R0_SM_STATES_IX4_SW4_RELEASE_PROD_SM_STATE_BMSK 0xc000000 -#define HWIO_TQM_R0_SM_STATES_IX4_SW4_RELEASE_PROD_SM_STATE_SHFT 26 -#define HWIO_TQM_R0_SM_STATES_IX4_SW3_RELEASE_PROD_SM_STATE_BMSK 0x3000000 -#define HWIO_TQM_R0_SM_STATES_IX4_SW3_RELEASE_PROD_SM_STATE_SHFT 24 -#define HWIO_TQM_R0_SM_STATES_IX4_SW2_RELEASE_PROD_SM_STATE_BMSK 0xc00000 -#define HWIO_TQM_R0_SM_STATES_IX4_SW2_RELEASE_PROD_SM_STATE_SHFT 22 -#define HWIO_TQM_R0_SM_STATES_IX4_SW1_RELEASE_PROD_SM_STATE_BMSK 0x300000 -#define HWIO_TQM_R0_SM_STATES_IX4_SW1_RELEASE_PROD_SM_STATE_SHFT 20 -#define HWIO_TQM_R0_SM_STATES_IX4_SW0_RELEASE_PROD_SM_STATE_BMSK 0xc0000 -#define HWIO_TQM_R0_SM_STATES_IX4_SW0_RELEASE_PROD_SM_STATE_SHFT 18 -#define HWIO_TQM_R0_SM_STATES_IX4_ERROR_RELEASE_PROD_SM_STATE_BMSK 0x30000 -#define HWIO_TQM_R0_SM_STATES_IX4_ERROR_RELEASE_PROD_SM_STATE_SHFT 16 -#define HWIO_TQM_R0_SM_STATES_IX4_FW_RELEASE_PROD_SM_STATE_BMSK 0xc000 -#define HWIO_TQM_R0_SM_STATES_IX4_FW_RELEASE_PROD_SM_STATE_SHFT 14 -#define HWIO_TQM_R0_SM_STATES_IX4_LINK_ZERO_OUT_STATE_BMSK 0x3000 -#define HWIO_TQM_R0_SM_STATES_IX4_LINK_ZERO_OUT_STATE_SHFT 12 -#define HWIO_TQM_R0_SM_STATES_IX4_MSDU_DELINK_PARSER_STATE_BMSK 0xf00 -#define HWIO_TQM_R0_SM_STATES_IX4_MSDU_DELINK_PARSER_STATE_SHFT 8 -#define HWIO_TQM_R0_SM_STATES_IX4_DELINK_CACHE_STATE_BMSK 0xf8 -#define HWIO_TQM_R0_SM_STATES_IX4_DELINK_CACHE_STATE_SHFT 3 -#define HWIO_TQM_R0_SM_STATES_IX4_RLS_REQ_STATE_SM_BMSK 0x7 -#define HWIO_TQM_R0_SM_STATES_IX4_RLS_REQ_STATE_SM_SHFT 0 - -#define HWIO_TQM_R0_SM_STATES_IX5_ADDR(x) ((x) + 0x15f4) -#define HWIO_TQM_R0_SM_STATES_IX5_PHYS(x) ((x) + 0x15f4) -#define HWIO_TQM_R0_SM_STATES_IX5_OFFS (0x15f4) -#define HWIO_TQM_R0_SM_STATES_IX5_RMSK 0xf -#define HWIO_TQM_R0_SM_STATES_IX5_POR 0x00000000 -#define HWIO_TQM_R0_SM_STATES_IX5_POR_RMSK 0xffffffff -#define HWIO_TQM_R0_SM_STATES_IX5_ATTR 0x1 -#define HWIO_TQM_R0_SM_STATES_IX5_IN(x) \ - in_dword(HWIO_TQM_R0_SM_STATES_IX5_ADDR(x)) -#define HWIO_TQM_R0_SM_STATES_IX5_INM(x, m) \ - in_dword_masked(HWIO_TQM_R0_SM_STATES_IX5_ADDR(x), m) -#define HWIO_TQM_R0_SM_STATES_IX5_FW2TQM_RELEASE_READ_REQ_STATE_BMSK 0xc -#define HWIO_TQM_R0_SM_STATES_IX5_FW2TQM_RELEASE_READ_REQ_STATE_SHFT 2 -#define HWIO_TQM_R0_SM_STATES_IX5_FW2TQM_RELEASE_PREFETCH_STATE_BMSK 0x3 -#define HWIO_TQM_R0_SM_STATES_IX5_FW2TQM_RELEASE_PREFETCH_STATE_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x204c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2050) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x) ((x) + 0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x) ((x) + 0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS (0x2054) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK 0xff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x) ((x) + 0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x) ((x) + 0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS (0x2058) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT 0 - -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x) ((x) + 0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x) ((x) + 0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS (0x205c) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR 0x00000000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR 0x3 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x) \ - in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v) \ - out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x)) -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK 0xffff0000 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT 16 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK 0xfff0 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT 4 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK 0x8 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT 3 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK 0x4 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT 2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK 0x2 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT 1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK 0x1 -#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT 0 - -#define HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x) ((x) + 0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_PHYS(x) ((x) + 0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OFFS (0x2060) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x) ((x) + 0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_PHYS(x) ((x) + 0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OFFS (0x2064) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x) ((x) + 0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_PHYS(x) ((x) + 0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OFFS (0x2068) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_RMSK 0x1ffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR 0x00000000 -#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_ATTR 0x3 -#define HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x) \ - in_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x)) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x), m) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUT(x, v) \ - out_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),v) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x)) -#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff -#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 - -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x) ((x) + 0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_PHYS(x) ((x) + 0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_OFFS (0x206c) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_RMSK 0xf -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR 0x00000000 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ATTR 0x1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_IN(x) \ - in_dword(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x)) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x), m) -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_BMSK 0x8 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_SHFT 3 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_BMSK 0x4 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_SHFT 2 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_BMSK 0x2 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_SHFT 1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_BMSK 0x1 -#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_SHFT 0 - -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x) ((x) + 0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_PHYS(x) ((x) + 0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_OFFS (0x2070) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR 0x00000000 -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ATTR 0x1 -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_IN(x) \ - in_dword(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x)) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x), m) -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_SHFT 0 - -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x) ((x) + 0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_PHYS(x) ((x) + 0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_OFFS (0x2074) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR 0x00000000 -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ATTR 0x1 -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_IN(x) \ - in_dword(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x)) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x), m) -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_BMSK 0xffffffff -#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_SHFT 0 - -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2078) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0xff -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_ADDR(x) ((x) + 0x211c) -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_PHYS(x) ((x) + 0x211c) -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_OFFS (0x211c) -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_RMSK 0xffffffff -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_POR 0x00000000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_ATTR 0x1 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_IN(x) \ - in_dword(HWIO_TQM_R1_BANK_SM_STATES_IX4_ADDR(x)) -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_BANK_SM_STATES_IX4_ADDR(x), m) -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW6_RELEASE_PROD_SM_STATE_BMSK 0xc0000000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW6_RELEASE_PROD_SM_STATE_SHFT 30 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW5_RELEASE_PROD_SM_STATE_BMSK 0x30000000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW5_RELEASE_PROD_SM_STATE_SHFT 28 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW4_RELEASE_PROD_SM_STATE_BMSK 0xc000000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW4_RELEASE_PROD_SM_STATE_SHFT 26 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW3_RELEASE_PROD_SM_STATE_BMSK 0x3000000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW3_RELEASE_PROD_SM_STATE_SHFT 24 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW2_RELEASE_PROD_SM_STATE_BMSK 0xc00000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW2_RELEASE_PROD_SM_STATE_SHFT 22 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW1_RELEASE_PROD_SM_STATE_BMSK 0x300000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW1_RELEASE_PROD_SM_STATE_SHFT 20 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW0_RELEASE_PROD_SM_STATE_BMSK 0xc0000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_SW0_RELEASE_PROD_SM_STATE_SHFT 18 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_ERROR_RELEASE_PROD_SM_STATE_BMSK 0x30000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_ERROR_RELEASE_PROD_SM_STATE_SHFT 16 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_FW_RELEASE_PROD_SM_STATE_BMSK 0xc000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_FW_RELEASE_PROD_SM_STATE_SHFT 14 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_LINK_ZERO_OUT_STATE_BMSK 0x3000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_LINK_ZERO_OUT_STATE_SHFT 12 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_MSDU_DELINK_PARSER_STATE_BMSK 0xf00 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_MSDU_DELINK_PARSER_STATE_SHFT 8 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_DELINK_CACHE_STATE_BMSK 0xf8 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_DELINK_CACHE_STATE_SHFT 3 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_RLS_REQ_STATE_SM_BMSK 0x7 -#define HWIO_TQM_R1_BANK_SM_STATES_IX4_RLS_REQ_STATE_SM_SHFT 0 - -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_ADDR(x) ((x) + 0x2120) -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_PHYS(x) ((x) + 0x2120) -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_OFFS (0x2120) -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_RMSK 0xf -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_POR 0x00000000 -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_ATTR 0x1 -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_IN(x) \ - in_dword(HWIO_TQM_R1_BANK_SM_STATES_IX5_ADDR(x)) -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_INM(x, m) \ - in_dword_masked(HWIO_TQM_R1_BANK_SM_STATES_IX5_ADDR(x), m) -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_FW2TQM_RELEASE_READ_REQ_STATE_BMSK 0xc -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_FW2TQM_RELEASE_READ_REQ_STATE_SHFT 2 -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_FW2TQM_RELEASE_PREFETCH_STATE_BMSK 0x3 -#define HWIO_TQM_R1_BANK_SM_STATES_IX5_FW2TQM_RELEASE_PREFETCH_STATE_SHFT 0 - -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2124 + (0x4*(n))) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_MAXn 127 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3068) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_PHYS(x) ((x) + 0x3068) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_OFFS (0x3068) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ADDR(x) ((x) + 0x306c) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_PHYS(x) ((x) + 0x306c) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_OFFS (0x306c) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2FW_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ADDR(x) ((x) + 0x3070) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_PHYS(x) ((x) + 0x3070) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_OFFS (0x3070) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ADDR(x) ((x) + 0x3074) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_PHYS(x) ((x) + 0x3074) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_OFFS (0x3074) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM_ERROR_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x) ((x) + 0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_PHYS(x) ((x) + 0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OFFS (0x3078) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ADDR(x) ((x) + 0x307c) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_PHYS(x) ((x) + 0x307c) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_OFFS (0x307c) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW0_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x) ((x) + 0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_PHYS(x) ((x) + 0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OFFS (0x3080) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ADDR(x) ((x) + 0x3084) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_PHYS(x) ((x) + 0x3084) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_OFFS (0x3084) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW1_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ADDR(x) ((x) + 0x3088) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_PHYS(x) ((x) + 0x3088) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_OFFS (0x3088) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ADDR(x) ((x) + 0x308c) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_PHYS(x) ((x) + 0x308c) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_OFFS (0x308c) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW2_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ADDR(x) ((x) + 0x3090) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_PHYS(x) ((x) + 0x3090) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_OFFS (0x3090) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ADDR(x) ((x) + 0x3094) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_PHYS(x) ((x) + 0x3094) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_OFFS (0x3094) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW3_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ADDR(x) ((x) + 0x3098) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_PHYS(x) ((x) + 0x3098) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_OFFS (0x3098) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ADDR(x) ((x) + 0x309c) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_PHYS(x) ((x) + 0x309c) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_OFFS (0x309c) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW4_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ADDR(x) ((x) + 0x30a0) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_PHYS(x) ((x) + 0x30a0) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_OFFS (0x30a0) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ADDR(x) ((x) + 0x30a4) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_PHYS(x) ((x) + 0x30a4) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_OFFS (0x30a4) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW5_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ADDR(x) ((x) + 0x30a8) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_PHYS(x) ((x) + 0x30a8) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_OFFS (0x30a8) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ADDR(x) ((x) + 0x30ac) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_PHYS(x) ((x) + 0x30ac) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_OFFS (0x30ac) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_TQM2SW6_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ADDR(x) ((x) + 0x30e8) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_PHYS(x) ((x) + 0x30e8) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_OFFS (0x30e8) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_RMSK 0xffff -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_POR 0x00000000 -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ATTR 0x3 -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_IN(x) \ - in_dword(HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ADDR(x)) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ADDR(x), m) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ADDR(x),v) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_IN(x)) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ADDR(x) ((x) + 0x30ec) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_PHYS(x) ((x) + 0x30ec) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_OFFS (0x30ec) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_RMSK 0xffff -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_POR 0x00000000 -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ATTR 0x3 -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_IN(x) \ - in_dword(HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ADDR(x)) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ADDR(x), m) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_OUT(x, v) \ - out_dword(HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ADDR(x),v) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_IN(x)) -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff -#define HWIO_TQM_R2_FW2TQM_RELEASE_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_BMSK 0x80 -#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_SHFT 7 -#define HWIO_UMCMN_R0_ISR_P_TQM3_BMSK 0x40000 -#define HWIO_UMCMN_R0_ISR_P_TQM3_SHFT 18 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 28 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 27 -#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO1_P_RING_WDG_BMSK 0x4000000 -#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO1_P_RING_WDG_SHFT 26 -#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO0_P_RING_WDG_BMSK 0x2000000 -#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO0_P_RING_WDG_SHFT 25 -#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO1_C_RING_WDG_BMSK 0x1000000 -#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO1_C_RING_WDG_SHFT 24 -#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO0_C_RING_WDG_BMSK 0x800000 -#define HWIO_UMCMN_R0_ISR_S6_SW2FW_REO0_C_RING_WDG_SHFT 23 -#define HWIO_UMCMN_R0_ISR_S6_REO2SW9_RING_WDG_BMSK 0x400000 -#define HWIO_UMCMN_R0_ISR_S6_REO2SW9_RING_WDG_SHFT 22 -#define HWIO_UMCMN_R0_ISR_S6_FW2REO1_RING_WDG_BMSK 0x80 -#define HWIO_UMCMN_R0_ISR_S6_FW2REO1_RING_WDG_SHFT 7 -#define HWIO_UMCMN_R0_ISR_S6_FW2REO_RING_WDG_BMSK 0x1 -#define HWIO_UMCMN_R0_ISR_S6_FW2REO_RING_WDG_SHFT 0 - -#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO1_P_WDG_ERR_BMSK 0x800000 -#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO1_P_WDG_ERR_SHFT 23 -#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO0_P_WDG_ERR_BMSK 0x400000 -#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO0_P_WDG_ERR_SHFT 22 -#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO1_C_WDG_ERR_BMSK 0x200000 -#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO1_C_WDG_ERR_SHFT 21 -#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO0_C_WDG_ERR_BMSK 0x100000 -#define HWIO_UMCMN_R0_ISR_S9_SW2FW_REO0_C_WDG_ERR_SHFT 20 -#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO1_P_RING_REQ_ERR_BMSK 0x400000 -#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO1_P_RING_REQ_ERR_SHFT 22 -#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO0_P_RING_REQ_ERR_BMSK 0x200000 -#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO0_P_RING_REQ_ERR_SHFT 21 -#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO1_C_RING_REQ_ERR_BMSK 0x100000 -#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO1_C_RING_REQ_ERR_SHFT 20 -#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO0_C_RING_REQ_ERR_BMSK 0x80000 -#define HWIO_UMCMN_R0_ISR_S10_SW2FW_REO0_C_RING_REQ_ERR_SHFT 19 -#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG12_REQ_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG12_REQ_ERR_SHFT 18 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 -#define HWIO_UMCMN_R0_ISR_S12_TCL_EXTN_SEG1_LEN_ZERO_ERR_BMSK 0x80000000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_EXTN_SEG1_LEN_ZERO_ERR_SHFT 31 -#define HWIO_UMCMN_R0_ISR_S12_TCL_EXTN_SEG1_ADDR_ZERO_ERR_BMSK 0x40000000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_EXTN_SEG1_ADDR_ZERO_ERR_SHFT 30 -#define HWIO_UMCMN_R0_ISR_S12_TCL_BUFFER_LEN_ZERO_ERR_BMSK 0x20000000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_BUFFER_LEN_ZERO_ERR_SHFT 29 -#define HWIO_UMCMN_R0_ISR_S12_TCL_BUFFER_ADDR_ZERO_ERR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_BUFFER_ADDR_ZERO_ERR_SHFT 28 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_ZERO_LEN_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_ZERO_LEN_ERR_SHFT 27 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_RING_WDG_ERR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_RING_WDG_ERR_SHFT 26 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_RING_REQ_ERR_BMSK 0x2000000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL7_RING_REQ_ERR_SHFT 25 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_ZERO_LEN_ERR_BMSK 0x1000000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_ZERO_LEN_ERR_SHFT 24 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_RING_WDG_ERR_BMSK 0x800000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_RING_WDG_ERR_SHFT 23 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_RING_REQ_ERR_BMSK 0x400000 -#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL6_RING_REQ_ERR_SHFT 22 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 -#define HWIO_UMCMN_R0_ISR_S15_TQM_RELEASE_PARSER_WDG_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_ISR_S15_TQM_RELEASE_PARSER_WDG_ERR_SHFT 18 -#define HWIO_UMCMN_R0_ISR_S15_TQM_MSDU_PARSER_ERROR_INT_BMSK 0x20000 -#define HWIO_UMCMN_R0_ISR_S15_TQM_MSDU_PARSER_ERROR_INT_SHFT 17 -#define HWIO_UMCMN_R0_ISR_S15_TQM_FW2TQM_RELEASE_RING_REQ_ERR_BMSK 0x10000 -#define HWIO_UMCMN_R0_ISR_S15_TQM_FW2TQM_RELEASE_RING_REQ_ERR_SHFT 16 -#define HWIO_UMCMN_R0_ISR_S15_TQM_FW2TQM_RELEASE_RING_WDG_ERR_BMSK 0x8000 -#define HWIO_UMCMN_R0_ISR_S15_TQM_FW2TQM_RELEASE_RING_WDG_ERR_SHFT 15 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 -#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 -#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 -#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 -#define HWIO_UMCMN_R0_IMR_P_TQM3_BMSK 0x40000 -#define HWIO_UMCMN_R0_IMR_P_TQM3_SHFT 18 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 28 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 27 -#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO1_P_RING_WDG_BMSK 0x4000000 -#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO1_P_RING_WDG_SHFT 26 -#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO0_P_RING_WDG_BMSK 0x2000000 -#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO0_P_RING_WDG_SHFT 25 -#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO1_C_RING_WDG_BMSK 0x1000000 -#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO1_C_RING_WDG_SHFT 24 -#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO0_C_RING_WDG_BMSK 0x800000 -#define HWIO_UMCMN_R0_IMR_S6_SW2FW_REO0_C_RING_WDG_SHFT 23 -#define HWIO_UMCMN_R0_IMR_S6_REO2SW9_RING_WDG_BMSK 0x400000 -#define HWIO_UMCMN_R0_IMR_S6_REO2SW9_RING_WDG_SHFT 22 -#define HWIO_UMCMN_R0_IMR_S6_FW2REO1_RING_WDG_BMSK 0x80 -#define HWIO_UMCMN_R0_IMR_S6_FW2REO1_RING_WDG_SHFT 7 -#define HWIO_UMCMN_R0_IMR_S6_FW2REO_RING_WDG_BMSK 0x1 -#define HWIO_UMCMN_R0_IMR_S6_FW2REO_RING_WDG_SHFT 0 - -#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO1_P_WDG_ERR_BMSK 0x800000 -#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO1_P_WDG_ERR_SHFT 23 -#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO0_P_WDG_ERR_BMSK 0x400000 -#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO0_P_WDG_ERR_SHFT 22 -#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO1_C_WDG_ERR_BMSK 0x200000 -#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO1_C_WDG_ERR_SHFT 21 -#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO0_C_WDG_ERR_BMSK 0x100000 -#define HWIO_UMCMN_R0_IMR_S9_SW2FW_REO0_C_WDG_ERR_SHFT 20 -#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO1_P_RING_REQ_ERR_BMSK 0x400000 -#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO1_P_RING_REQ_ERR_SHFT 22 -#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO0_P_RING_REQ_ERR_BMSK 0x200000 -#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO0_P_RING_REQ_ERR_SHFT 21 -#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO1_C_RING_REQ_ERR_BMSK 0x100000 -#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO1_C_RING_REQ_ERR_SHFT 20 -#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO0_C_RING_REQ_ERR_BMSK 0x80000 -#define HWIO_UMCMN_R0_IMR_S10_SW2FW_REO0_C_RING_REQ_ERR_SHFT 19 -#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG12_REQ_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG12_REQ_ERR_SHFT 18 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 -#define HWIO_UMCMN_R0_IMR_S12_TCL_EXTN_SEG1_LEN_ZERO_ERR_BMSK 0x80000000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_EXTN_SEG1_LEN_ZERO_ERR_SHFT 31 -#define HWIO_UMCMN_R0_IMR_S12_TCL_EXTN_SEG1_ADDR_ZERO_ERR_BMSK 0x40000000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_EXTN_SEG1_ADDR_ZERO_ERR_SHFT 30 -#define HWIO_UMCMN_R0_IMR_S12_TCL_BUFFER_LEN_ZERO_ERR_BMSK 0x20000000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_BUFFER_LEN_ZERO_ERR_SHFT 29 -#define HWIO_UMCMN_R0_IMR_S12_TCL_BUFFER_ADDR_ZERO_ERR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_BUFFER_ADDR_ZERO_ERR_SHFT 28 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_ZERO_LEN_ERR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_ZERO_LEN_ERR_SHFT 27 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_RING_WDG_ERR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_RING_WDG_ERR_SHFT 26 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_RING_REQ_ERR_BMSK 0x2000000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL7_RING_REQ_ERR_SHFT 25 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_ZERO_LEN_ERR_BMSK 0x1000000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_ZERO_LEN_ERR_SHFT 24 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_RING_WDG_ERR_BMSK 0x800000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_RING_WDG_ERR_SHFT 23 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_RING_REQ_ERR_BMSK 0x400000 -#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL6_RING_REQ_ERR_SHFT 22 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 -#define HWIO_UMCMN_R0_IMR_S15_TQM_RELEASE_PARSER_WDG_ERR_BMSK 0x40000 -#define HWIO_UMCMN_R0_IMR_S15_TQM_RELEASE_PARSER_WDG_ERR_SHFT 18 -#define HWIO_UMCMN_R0_IMR_S15_TQM_MSDU_PARSER_ERROR_INT_BMSK 0x20000 -#define HWIO_UMCMN_R0_IMR_S15_TQM_MSDU_PARSER_ERROR_INT_SHFT 17 -#define HWIO_UMCMN_R0_IMR_S15_TQM_FW2TQM_RELEASE_RING_REQ_ERR_BMSK 0x10000 -#define HWIO_UMCMN_R0_IMR_S15_TQM_FW2TQM_RELEASE_RING_REQ_ERR_SHFT 16 -#define HWIO_UMCMN_R0_IMR_S15_TQM_FW2TQM_RELEASE_RING_WDG_ERR_BMSK 0x8000 -#define HWIO_UMCMN_R0_IMR_S15_TQM_FW2TQM_RELEASE_RING_WDG_ERR_SHFT 15 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 -#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 -#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 -#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 -#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_BMSK 0x40 -#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_SHFT 6 -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x) ((x) + 0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_PHYS(x) ((x) + 0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OFFS (0x168) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_RMSK 0xf -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR 0x0000000a -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ATTR 0x3 -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x) \ - in_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x)) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x), m) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),v) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x)) -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_BMSK 0xf -#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_SHFT 0 - -#define HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OFFS (0x16c) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_RMSK 0x1f -#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_BMSK 0x10 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_SHFT 4 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_BMSK 0x8 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_SHFT 3 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_BMSK 0x4 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_SHFT 2 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_BMSK 0x2 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_SHFT 1 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_UMCMN_R0_LINK_ID_ADDR(x) ((x) + 0x170) -#define HWIO_UMCMN_R0_LINK_ID_PHYS(x) ((x) + 0x170) -#define HWIO_UMCMN_R0_LINK_ID_OFFS (0x170) -#define HWIO_UMCMN_R0_LINK_ID_RMSK 0xffff -#define HWIO_UMCMN_R0_LINK_ID_POR 0x000052c8 -#define HWIO_UMCMN_R0_LINK_ID_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_LINK_ID_ATTR 0x3 -#define HWIO_UMCMN_R0_LINK_ID_IN(x) \ - in_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x)) -#define HWIO_UMCMN_R0_LINK_ID_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_LINK_ID_ADDR(x), m) -#define HWIO_UMCMN_R0_LINK_ID_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x),v) -#define HWIO_UMCMN_R0_LINK_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_LINK_ID_IN(x)) -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_BMSK 0x80 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_SHFT 7 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_BMSK 0x40 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_SHFT 6 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_BMSK 0x38 -#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_SHFT 3 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_BMSK 0x7 -#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_SHFT 0 - -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK 0x4000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT 14 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK 0x2000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT 13 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK 0x1000 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT 12 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK 0x800 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT 11 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK 0x400 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT 10 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK 0x200 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT 9 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK 0x100 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT 8 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK 0x80 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT 7 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK 0x40 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT 6 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK 0x20 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT 5 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK 0x10 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT 4 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK 0x8 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT 3 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK 0x4 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT 2 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK 0x2 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT 1 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK 0x1 -#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT 0 - -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x) ((x) + 0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_PHYS(x) ((x) + 0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OFFS (0x184) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_RMSK 0x1 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR 0x00000000 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ATTR 0x3 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x) \ - in_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x)) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x), m) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),v) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x)) -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_BMSK 0x1 -#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_SHFT 0 - -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x) ((x) + 0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_PHYS(x) ((x) + 0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OFFS (0x188) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_RMSK 0x1ffff -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR 0x00000000 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ATTR 0x3 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x) \ - in_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x)) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x), m) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),v) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),m,v,HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x)) -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_BMSK 0x1fe00 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_SHFT 9 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_BMSK 0x1fe -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_SHFT 1 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_BMSK 0x1 -#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_SHFT 0 - -#define HWIO_UMCMN_R0_ISR_S18_ADDR(x) ((x) + 0x194) -#define HWIO_UMCMN_R0_ISR_S18_PHYS(x) ((x) + 0x194) -#define HWIO_UMCMN_R0_ISR_S18_OFFS (0x194) -#define HWIO_UMCMN_R0_ISR_S18_RMSK 0x7fffffff -#define HWIO_UMCMN_R0_ISR_S18_POR 0x00000000 -#define HWIO_UMCMN_R0_ISR_S18_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_ISR_S18_ATTR 0x0 -#define HWIO_UMCMN_R0_ISR_S18_IN(x) \ - in_dword(HWIO_UMCMN_R0_ISR_S18_ADDR(x)) -#define HWIO_UMCMN_R0_ISR_S18_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_ISR_S18_ADDR(x), m) -#define HWIO_UMCMN_R0_ISR_S18_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_ISR_S18_ADDR(x),v) -#define HWIO_UMCMN_R0_ISR_S18_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S18_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S18_IN(x)) -#define HWIO_UMCMN_R0_ISR_S18_TQM_VA_CONV_ERR_INTR_BMSK 0x40000000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_VA_CONV_ERR_INTR_SHFT 30 -#define HWIO_UMCMN_R0_ISR_S18_TQM_MSDU_DELINK_PARSE_ERR_INTR_BMSK 0x20000000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_MSDU_DELINK_PARSE_ERR_INTR_SHFT 29 -#define HWIO_UMCMN_R0_ISR_S18_TQM_MSDU_DELINK_WATCHDOG_INTR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_MSDU_DELINK_WATCHDOG_INTR_SHFT 28 -#define HWIO_UMCMN_R0_ISR_S18_TQM_FW_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_FW_BUFFER_PROD_WATCHDOG_INTR_SHFT 27 -#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_PROD_WATCHDOG_INTR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_PROD_WATCHDOG_INTR_SHFT 26 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW0_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x2000000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW0_BUFFER_PROD_WATCHDOG_INTR_SHFT 25 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW1_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x1000000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW1_BUFFER_PROD_WATCHDOG_INTR_SHFT 24 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW2_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x800000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW2_BUFFER_PROD_WATCHDOG_INTR_SHFT 23 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW3_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x400000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW3_BUFFER_PROD_WATCHDOG_INTR_SHFT 22 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW4_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x200000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW4_BUFFER_PROD_WATCHDOG_INTR_SHFT 21 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW5_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x100000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW5_BUFFER_PROD_WATCHDOG_INTR_SHFT 20 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW6_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x80000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW6_BUFFER_PROD_WATCHDOG_INTR_SHFT 19 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW_COOKIE_IDLE_TIMEOUT_BMSK 0x40000 -#define HWIO_UMCMN_R0_ISR_S18_TQM_SW_COOKIE_IDLE_TIMEOUT_SHFT 18 -#define HWIO_UMCMN_R0_ISR_S18_TQM2FW_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x20000 -#define HWIO_UMCMN_R0_ISR_S18_TQM2FW_RELEASE_RING_REQ_ERROR_INTR_SHFT 17 -#define HWIO_UMCMN_R0_ISR_S18_TQM2FW_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x10000 -#define HWIO_UMCMN_R0_ISR_S18_TQM2FW_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 16 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW0_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x8000 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW0_RELEASE_RING_REQ_ERROR_INTR_SHFT 15 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW0_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x4000 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW0_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 14 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW1_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x2000 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW1_RELEASE_RING_REQ_ERROR_INTR_SHFT 13 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW1_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x1000 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW1_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 12 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW2_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x800 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW2_RELEASE_RING_REQ_ERROR_INTR_SHFT 11 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW2_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x400 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW2_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 10 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW3_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x200 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW3_RELEASE_RING_REQ_ERROR_INTR_SHFT 9 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW3_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x100 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW3_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 8 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW4_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x80 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW4_RELEASE_RING_REQ_ERROR_INTR_SHFT 7 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW4_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x40 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW4_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 6 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW5_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x20 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW5_RELEASE_RING_REQ_ERROR_INTR_SHFT 5 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW5_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x10 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW5_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 4 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW6_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x8 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW6_RELEASE_RING_REQ_ERROR_INTR_SHFT 3 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW6_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x4 -#define HWIO_UMCMN_R0_ISR_S18_TQM2SW6_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 2 -#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x2 -#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_RING_REQ_ERROR_INTR_SHFT 1 -#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x1 -#define HWIO_UMCMN_R0_ISR_S18_TQM_ERROR_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 0 - -#define HWIO_UMCMN_R0_IMR_S18_ADDR(x) ((x) + 0x198) -#define HWIO_UMCMN_R0_IMR_S18_PHYS(x) ((x) + 0x198) -#define HWIO_UMCMN_R0_IMR_S18_OFFS (0x198) -#define HWIO_UMCMN_R0_IMR_S18_RMSK 0x7fffffff -#define HWIO_UMCMN_R0_IMR_S18_POR 0x00000000 -#define HWIO_UMCMN_R0_IMR_S18_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R0_IMR_S18_ATTR 0x3 -#define HWIO_UMCMN_R0_IMR_S18_IN(x) \ - in_dword(HWIO_UMCMN_R0_IMR_S18_ADDR(x)) -#define HWIO_UMCMN_R0_IMR_S18_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R0_IMR_S18_ADDR(x), m) -#define HWIO_UMCMN_R0_IMR_S18_OUT(x, v) \ - out_dword(HWIO_UMCMN_R0_IMR_S18_ADDR(x),v) -#define HWIO_UMCMN_R0_IMR_S18_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S18_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S18_IN(x)) -#define HWIO_UMCMN_R0_IMR_S18_TQM_VA_CONV_ERR_INTR_BMSK 0x40000000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_VA_CONV_ERR_INTR_SHFT 30 -#define HWIO_UMCMN_R0_IMR_S18_TQM_MSDU_DELINK_PARSE_ERR_INTR_BMSK 0x20000000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_MSDU_DELINK_PARSE_ERR_INTR_SHFT 29 -#define HWIO_UMCMN_R0_IMR_S18_TQM_MSDU_DELINK_WATCHDOG_INTR_BMSK 0x10000000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_MSDU_DELINK_WATCHDOG_INTR_SHFT 28 -#define HWIO_UMCMN_R0_IMR_S18_TQM_FW_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x8000000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_FW_BUFFER_PROD_WATCHDOG_INTR_SHFT 27 -#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_PROD_WATCHDOG_INTR_BMSK 0x4000000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_PROD_WATCHDOG_INTR_SHFT 26 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW0_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x2000000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW0_BUFFER_PROD_WATCHDOG_INTR_SHFT 25 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW1_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x1000000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW1_BUFFER_PROD_WATCHDOG_INTR_SHFT 24 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW2_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x800000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW2_BUFFER_PROD_WATCHDOG_INTR_SHFT 23 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW3_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x400000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW3_BUFFER_PROD_WATCHDOG_INTR_SHFT 22 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW4_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x200000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW4_BUFFER_PROD_WATCHDOG_INTR_SHFT 21 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW5_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x100000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW5_BUFFER_PROD_WATCHDOG_INTR_SHFT 20 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW6_BUFFER_PROD_WATCHDOG_INTR_BMSK 0x80000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW6_BUFFER_PROD_WATCHDOG_INTR_SHFT 19 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW_COOKIE_IDLE_TIMEOUT_BMSK 0x40000 -#define HWIO_UMCMN_R0_IMR_S18_TQM_SW_COOKIE_IDLE_TIMEOUT_SHFT 18 -#define HWIO_UMCMN_R0_IMR_S18_TQM2FW_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x20000 -#define HWIO_UMCMN_R0_IMR_S18_TQM2FW_RELEASE_RING_REQ_ERROR_INTR_SHFT 17 -#define HWIO_UMCMN_R0_IMR_S18_TQM2FW_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x10000 -#define HWIO_UMCMN_R0_IMR_S18_TQM2FW_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 16 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW0_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x8000 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW0_RELEASE_RING_REQ_ERROR_INTR_SHFT 15 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW0_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x4000 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW0_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 14 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW1_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x2000 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW1_RELEASE_RING_REQ_ERROR_INTR_SHFT 13 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW1_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x1000 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW1_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 12 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW2_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x800 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW2_RELEASE_RING_REQ_ERROR_INTR_SHFT 11 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW2_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x400 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW2_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 10 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW3_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x200 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW3_RELEASE_RING_REQ_ERROR_INTR_SHFT 9 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW3_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x100 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW3_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 8 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW4_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x80 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW4_RELEASE_RING_REQ_ERROR_INTR_SHFT 7 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW4_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x40 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW4_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 6 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW5_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x20 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW5_RELEASE_RING_REQ_ERROR_INTR_SHFT 5 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW5_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x10 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW5_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 4 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW6_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x8 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW6_RELEASE_RING_REQ_ERROR_INTR_SHFT 3 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW6_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x4 -#define HWIO_UMCMN_R0_IMR_S18_TQM2SW6_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 2 -#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x2 -#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_RING_REQ_ERROR_INTR_SHFT 1 -#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x1 -#define HWIO_UMCMN_R0_IMR_S18_TQM_ERROR_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 0 - -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2010) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x1ff -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_BMSK 0x100 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_SHFT 8 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_BMSK 0x80 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_SHFT 7 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_BMSK 0x40 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_SHFT 6 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_BMSK 0x20 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_SHFT 5 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n) ((base) + 0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_PHYS(base,n) ((base) + 0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OFFS(n) (0X2014 + (0x4*(n))) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_MAXn 7 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR 0x00000000 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR_RMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ATTR 0x3 -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n) \ - in_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n)) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), mask) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTI(base,n,val) \ - out_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),val) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTMI(base,n,mask,val) \ - out_dword_masked_ns(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),mask,val,HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n)) -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_BMSK 0xffffffff -#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_SHFT 0 - -#define MAC_TCL_REG_REG_BASE (UMAC_BASE + 0x00044000) -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_ADDR(x) ((x) + 0x14) -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_PHYS(x) ((x) + 0x14) -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_OFFS (0x14) -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_RMSK 0x3ffe0 -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_CTRL_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CTRL_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_CTRL_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_CTRL_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_TIMEOUT_VAL_SHFT 6 -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_RNG_PRTY_BMSK 0x20 -#define HWIO_TCL_R0_SW2TCL6_RING_CTRL_RNG_PRTY_SHFT 5 - -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_ADDR(x) ((x) + 0x18) -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_PHYS(x) ((x) + 0x18) -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_OFFS (0x18) -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_RMSK 0x3ffe0 -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_CTRL_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CTRL_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_CTRL_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_CTRL_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_TIMEOUT_VAL_SHFT 6 -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_RNG_PRTY_BMSK 0x20 -#define HWIO_TCL_R0_SW2TCL7_RING_CTRL_RNG_PRTY_SHFT 5 - -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) ((x) + 0x20) -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x800000 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 23 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL7_RNG_HALT_STAT_BMSK 0x20000 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL7_RNG_HALT_STAT_SHFT 17 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL6_RNG_HALT_STAT_BMSK 0x10000 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL6_RNG_HALT_STAT_SHFT 16 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL7_RNG_HALT_BMSK 0x200 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL7_RNG_HALT_SHFT 9 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL6_RNG_HALT_BMSK 0x100 -#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL6_RNG_HALT_SHFT 8 -#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_BMSK 0x200000 -#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_SHFT 21 -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ADDR(x) ((x) + 0x34) -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_PHYS(x) ((x) + 0x34) -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_OFFS (0x34) -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_RMSK 0xffffffff -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_POR 0x005a0060 -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ATTR 0x3 -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_IN(x) \ - in_dword(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ADDR(x)) -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ADDR(x), m) -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_OUT(x, v) \ - out_dword(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ADDR(x),v) -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_ADDR(x),m,v,HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_IN(x)) -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_NATIVE_WIFI_BMSK 0xffff0000 -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_NATIVE_WIFI_SHFT 16 -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_RAW_WIFI_BMSK 0xffff -#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_RAW_WIFI_SHFT 0 - -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ADDR(x) ((x) + 0x38) -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_PHYS(x) ((x) + 0x38) -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_OFFS (0x38) -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_RMSK 0xffffffff -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_POR 0x004a004a -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ATTR 0x3 -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_IN(x) \ - in_dword(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ADDR(x)) -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ADDR(x), m) -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_OUT(x, v) \ - out_dword(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ADDR(x),v) -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ADDR(x),m,v,HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_IN(x)) -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_IEEE_802_BMSK 0xffff0000 -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_IEEE_802_SHFT 16 -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ETHERNET_II_BMSK 0xffff -#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_ETHERNET_II_SHFT 0 - -#define HWIO_TCL_R0_UMXI_PRIORITY0_FW2TCL1_RING_BMSK 0xc000 -#define HWIO_TCL_R0_UMXI_PRIORITY0_FW2TCL1_RING_SHFT 14 -#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL7_RING_BMSK 0x3000 -#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL7_RING_SHFT 12 -#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL6_RING_BMSK 0xc00 -#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL6_RING_SHFT 10 -#define HWIO_TCL_R0_UMXI_PRIORITY1_METADATA_FETCH_GXI_RD_BMSK 0xc0 -#define HWIO_TCL_R0_UMXI_PRIORITY1_METADATA_FETCH_GXI_RD_SHFT 6 -#define HWIO_TCL_R0_UMXI_PRIORITY1_PEER_TABLE_FETCH_GXI_RD_BMSK 0x30 -#define HWIO_TCL_R0_UMXI_PRIORITY1_PEER_TABLE_FETCH_GXI_RD_SHFT 4 - -#define HWIO_TCL_R0_VC_ID_MAP_FW2TCL1_RING_BMSK 0x80 -#define HWIO_TCL_R0_VC_ID_MAP_FW2TCL1_RING_SHFT 7 -#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL7_RING_BMSK 0x40 -#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL7_RING_SHFT 6 -#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL6_RING_BMSK 0x20 -#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL6_RING_SHFT 5 -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_ADDR(x) ((x) + 0x64) -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_PHYS(x) ((x) + 0x64) -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_OFFS (0x64) -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_RMSK 0x1fff -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_POR 0x00000004 -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_DESC_RD_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_DESC_RD_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_DESC_RD_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_DESC_RD_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_TIMEOUT_LIMIT_SHFT 5 -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_BUNCH_COUNT_BMSK 0x1f -#define HWIO_TCL_R0_SW2TCL6_DESC_RD_BUNCH_COUNT_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_ADDR(x) ((x) + 0x68) -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_PHYS(x) ((x) + 0x68) -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_OFFS (0x68) -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_RMSK 0x1fff -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_POR 0x00000004 -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_DESC_RD_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_DESC_RD_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_DESC_RD_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_DESC_RD_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_TIMEOUT_LIMIT_SHFT 5 -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_BUNCH_COUNT_BMSK 0x1f -#define HWIO_TCL_R0_SW2TCL7_DESC_RD_BUNCH_COUNT_SHFT 0 - -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_ADDR(x) ((x) + 0x6c) -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_PHYS(x) ((x) + 0x6c) -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_OFFS (0x6c) -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_RMSK 0x1fff -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_POR 0x00000004 -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_ATTR 0x3 -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_IN(x) \ - in_dword(HWIO_TCL_R0_FW2TCL1_DESC_RD_ADDR(x)) -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_FW2TCL1_DESC_RD_ADDR(x), m) -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_OUT(x, v) \ - out_dword(HWIO_TCL_R0_FW2TCL1_DESC_RD_ADDR(x),v) -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_DESC_RD_IN(x)) -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_TIMEOUT_LIMIT_SHFT 5 -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_BUNCH_COUNT_BMSK 0x1f -#define HWIO_TCL_R0_FW2TCL1_DESC_RD_BUNCH_COUNT_SHFT 0 - -#define HWIO_TCL_R0_RBM_MAPPING0_FW2TCL1_RING_BMSK 0xf0000000 -#define HWIO_TCL_R0_RBM_MAPPING0_FW2TCL1_RING_SHFT 28 -#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL7_RING_BMSK 0xf000000 -#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL7_RING_SHFT 24 -#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL6_RING_BMSK 0xf00000 -#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL6_RING_SHFT 20 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n) ((base) + 0X74 + (0x4*(n))) -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT 17 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT 14 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT 12 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT 8 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT 7 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT 3 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT 1 -#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT 0 - -#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n) ((base) + 0X174 + (0x4*(n))) -#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_3_TUPLE_IP_ADDR_INDEX_BMSK 0x6000000 -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_3_TUPLE_IP_ADDR_INDEX_SHFT 25 -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_3_TUPLE_BMSK 0x1000000 -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_3_TUPLE_SHFT 24 -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_BMSK 0x800000 -#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_SHFT 23 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ADDR(x) ((x) + 0x818) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_PHYS(x) ((x) + 0x818) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_OFFS (0x818) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_RMSK 0xff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IPV6_BMSK 0xf0 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IPV6_SHFT 4 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IPV4_BMSK 0xf -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_SELECT_IPV4_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ADDR(x) ((x) + 0x81c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_PHYS(x) ((x) + 0x81c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_OFFS (0x81c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_31_TO_0_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ADDR(x) ((x) + 0x820) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_PHYS(x) ((x) + 0x820) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_OFFS (0x820) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_63_TO_32_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ADDR(x) ((x) + 0x824) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_PHYS(x) ((x) + 0x824) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_OFFS (0x824) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_95_TO_64_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ADDR(x) ((x) + 0x828) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_PHYS(x) ((x) + 0x828) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_OFFS (0x828) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR0_127_TO_96_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ADDR(x) ((x) + 0x82c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_PHYS(x) ((x) + 0x82c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_OFFS (0x82c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_31_TO_0_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ADDR(x) ((x) + 0x830) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_PHYS(x) ((x) + 0x830) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_OFFS (0x830) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_63_TO_32_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ADDR(x) ((x) + 0x834) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_PHYS(x) ((x) + 0x834) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_OFFS (0x834) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_95_TO_64_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ADDR(x) ((x) + 0x838) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_PHYS(x) ((x) + 0x838) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_OFFS (0x838) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR1_127_TO_96_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ADDR(x) ((x) + 0x83c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_PHYS(x) ((x) + 0x83c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_OFFS (0x83c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_31_TO_0_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ADDR(x) ((x) + 0x840) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_PHYS(x) ((x) + 0x840) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_OFFS (0x840) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_63_TO_32_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ADDR(x) ((x) + 0x844) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_PHYS(x) ((x) + 0x844) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_OFFS (0x844) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_95_TO_64_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ADDR(x) ((x) + 0x848) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_PHYS(x) ((x) + 0x848) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_OFFS (0x848) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR2_127_TO_96_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ADDR(x) ((x) + 0x84c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_PHYS(x) ((x) + 0x84c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_OFFS (0x84c) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_31_TO_0_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ADDR(x) ((x) + 0x850) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_PHYS(x) ((x) + 0x850) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_OFFS (0x850) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_63_TO_32_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ADDR(x) ((x) + 0x854) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_PHYS(x) ((x) + 0x854) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_OFFS (0x854) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_95_TO_64_VAL_SHFT 0 - -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ADDR(x) ((x) + 0x858) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_PHYS(x) ((x) + 0x858) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_OFFS (0x858) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_POR 0x00000000 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ATTR 0x3 -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_IN(x) \ - in_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ADDR(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ADDR(x), m) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ADDR(x),v) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_ADDR(x),m,v,HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_IN(x)) -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_VAL_BMSK 0xffffffff -#define HWIO_TCL_R0_LCE_MATCH_3_TUPLE_IP_ADDR3_127_TO_96_VAL_SHFT 0 - -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ADDR(x) ((x) + 0x85c) -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_PHYS(x) ((x) + 0x85c) -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_OFFS (0x85c) -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_RMSK 0x3f -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_POR 0x00000000 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ATTR 0x3 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_IN(x) \ - in_dword(HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ADDR(x)) -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ADDR(x), m) -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ADDR(x),v) -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_ADDR(x),m,v,HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_IN(x)) -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_HDR_FETCH_BMSK 0x20 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_HDR_FETCH_SHFT 5 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_FLOW_LOOKUP_LCE_RES_BMSK 0x10 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_FLOW_LOOKUP_LCE_RES_SHFT 4 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_LCE_INPUT_FIFO_BMSK 0x8 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_LCE_INPUT_FIFO_SHFT 3 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_FLOW_LOOKUP_INPUT_FIFO_BMSK 0x4 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_FLOW_LOOKUP_INPUT_FIFO_SHFT 2 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_DSCP_TID_MAP_MEM_CTRL_BMSK 0x2 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_DSCP_TID_MAP_MEM_CTRL_SHFT 1 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_LITE_CMD_MAPPER_BMSK 0x1 -#define HWIO_TCL_R0_LITE_CLKGATE_DISABLE0_LITE_CMD_MAPPER_SHFT 0 - -#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_8_BMSK 0x1000 -#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_8_SHFT 12 -#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_7_BMSK 0x800 -#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_7_SHFT 11 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_DSCP_TID_MAP_MEM_BMSK 0x1000 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_DSCP_TID_MAP_MEM_SHFT 12 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_FLOW_LOOKUP_RES_MEM_BMSK 0x800 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_FLOW_LOOKUP_RES_MEM_SHFT 11 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_HDR_DATA_MEM_BMSK 0x400 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_HDR_DATA_MEM_SHFT 10 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_DESC_DATA_MEM_BMSK 0x200 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_DESC_DATA_MEM_SHFT 9 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_BMSK 0x40 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_SHFT 6 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_BMSK 0x20 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_SHFT 5 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_TQM_SRNG_BUNCH_BMSK 0x2 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_TQM_SRNG_BUNCH_SHFT 1 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_APB_CLK_BMSK 0x1 -#define HWIO_TCL_R0_CLKGATE_DISABLE1_APB_CLK_SHFT 0 - -#define HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x) ((x) + 0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_PHYS(x) ((x) + 0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OFFS (0x868) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_RMSK 0x3 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR 0x00000000 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_CLKGATE_DISABLE2_ATTR 0x3 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x) \ - in_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x)) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x), m) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUT(x, v) \ - out_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),v) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x)) -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_BMSK 0x2 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_SHFT 1 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_BMSK 0x1 -#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_SHFT 0 - -#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING7_BMSK 0x80 -#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING7_SHFT 7 -#define HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_OFFS (0x8bc) -#define HWIO_TCL_R0_LPM_FW_CTRL_RMSK 0x7 -#define HWIO_TCL_R0_LPM_FW_CTRL_POR 0x00000000 -#define HWIO_TCL_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_LPM_FW_CTRL_ATTR 0x3 -#define HWIO_TCL_R0_LPM_FW_CTRL_IN(x) \ - in_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x)) -#define HWIO_TCL_R0_LPM_FW_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x), m) -#define HWIO_TCL_R0_LPM_FW_CTRL_OUT(x, v) \ - out_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),v) -#define HWIO_TCL_R0_LPM_FW_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TCL_R0_LPM_FW_CTRL_IN(x)) -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 -#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 - -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ADDR(x) ((x) + 0x8c0) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_PHYS(x) ((x) + 0x8c0) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_OFFS (0x8c0) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_RMSK 0xffffffff -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_POR 0x00000000 -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ATTR 0x3 -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_IN(x) \ - in_dword(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ADDR(x)) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ADDR(x), m) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ADDR(x),v) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_ADDR(x),m,v,HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_IN(x)) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_BASE_ADDR_BMSK 0xffffffff -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_LSB_BASE_ADDR_SHFT 0 - -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ADDR(x) ((x) + 0x8c4) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_PHYS(x) ((x) + 0x8c4) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_OFFS (0x8c4) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_RMSK 0xff -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_POR 0x00000000 -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ATTR 0x3 -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_IN(x) \ - in_dword(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ADDR(x)) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ADDR(x), m) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ADDR(x),v) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_ADDR(x),m,v,HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_IN(x)) -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_BASE_ADDR_BMSK 0xff -#define HWIO_TCL_R0_FLOW_LOOKUP_TABLE_MSB_BASE_ADDR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0x8c8) -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0x8cc) -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) ((x) + 0x8d0) -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) ((x) + 0x8d8) -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x8e4) -#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x8e8) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x8f8) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x8fc) -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x910) -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x914) -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0x918) -#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) ((x) + 0x940) -#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ADDR(x) ((x) + 0xb20) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_PHYS(x) ((x) + 0xb20) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_OFFS (0xb20) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ADDR(x) ((x) + 0xb24) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_PHYS(x) ((x) + 0xb24) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_OFFS (0xb24) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_RMSK 0xfffffff -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL6_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_ID_ADDR(x) ((x) + 0xb28) -#define HWIO_TCL_R0_SW2TCL6_RING_ID_PHYS(x) ((x) + 0xb28) -#define HWIO_TCL_R0_SW2TCL6_RING_ID_OFFS (0xb28) -#define HWIO_TCL_R0_SW2TCL6_RING_ID_RMSK 0xff -#define HWIO_TCL_R0_SW2TCL6_RING_ID_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_ID_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_ID_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_ID_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_ID_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_ID_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_ID_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_ID_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL6_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_ADDR(x) ((x) + 0xb2c) -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_PHYS(x) ((x) + 0xb2c) -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_OFFS (0xb2c) -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_ATTR 0x1 -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_STATUS_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_STATUS_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL6_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_ADDR(x) ((x) + 0xb30) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_PHYS(x) ((x) + 0xb30) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_OFFS (0xb30) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_RMSK 0x7fffff -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_POR 0x00000080 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_MISC_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_MISC_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_MISC_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_MISC_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xb3c) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xb3c) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_OFFS (0xb3c) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xb40) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xb40) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_OFFS (0xb40) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_RMSK 0xff -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL6_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xb50) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xb50) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xb50) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xb54) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xb54) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xb54) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xb58) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xb58) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_OFFS (0xb58) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_ATTR 0x1 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xb5c) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xb5c) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xb5c) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xb60) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xb60) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xb60) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xb64) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xb64) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xb64) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff -#define HWIO_TCL_R0_SW2TCL6_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xb68) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xb68) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_OFFS (0xb68) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xb6c) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xb6c) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_OFFS (0xb6c) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ADDR(x) ((x) + 0xb70) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_PHYS(x) ((x) + 0xb70) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_OFFS (0xb70) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xb90) -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xb90) -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_OFFS (0xb90) -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL6_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ADDR(x) ((x) + 0xb94) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_PHYS(x) ((x) + 0xb94) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_OFFS (0xb94) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL6_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL6_RING_MISC_1_IN(x)) -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TCL_R0_SW2TCL6_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ADDR(x) ((x) + 0xb98) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_PHYS(x) ((x) + 0xb98) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_OFFS (0xb98) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ADDR(x) ((x) + 0xb9c) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_PHYS(x) ((x) + 0xb9c) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_OFFS (0xb9c) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_RMSK 0xfffffff -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_RING_SIZE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL7_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_ID_ADDR(x) ((x) + 0xba0) -#define HWIO_TCL_R0_SW2TCL7_RING_ID_PHYS(x) ((x) + 0xba0) -#define HWIO_TCL_R0_SW2TCL7_RING_ID_OFFS (0xba0) -#define HWIO_TCL_R0_SW2TCL7_RING_ID_RMSK 0xff -#define HWIO_TCL_R0_SW2TCL7_RING_ID_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_ID_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_ID_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_ID_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_ID_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_ID_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_ID_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_ID_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_ID_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_ID_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_ID_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_ID_ENTRY_SIZE_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL7_RING_ID_ENTRY_SIZE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_ADDR(x) ((x) + 0xba4) -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_PHYS(x) ((x) + 0xba4) -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_OFFS (0xba4) -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_ATTR 0x1 -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_STATUS_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_STATUS_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL7_RING_STATUS_NUM_VALID_WORDS_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_ADDR(x) ((x) + 0xba8) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_PHYS(x) ((x) + 0xba8) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_OFFS (0xba8) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_RMSK 0x7fffff -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_POR 0x00000080 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_MISC_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_MISC_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_MISC_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_MISC_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SPARE_CONTROL_SHFT 14 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_SM_STATE2_SHFT 12 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_SM_STATE1_SHFT 8 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_IS_IDLE_SHFT 7 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_ENABLE_BMSK 0x40 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SRNG_ENABLE_SHFT 6 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_MSI_SWAP_BIT_SHFT 3 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SECURITY_BIT_BMSK 0x4 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_SECURITY_BIT_SHFT 2 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_LOOPCNT_DISABLE_SHFT 1 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_RING_ID_DISABLE_BMSK 0x1 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_RING_ID_DISABLE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xbb4) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xbb4) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_OFFS (0xbb4) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xbb8) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xbb8) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_OFFS (0xbb8) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_RMSK 0xff -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL7_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xbc8) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xbc8) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xbc8) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xbcc) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xbcc) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xbcc) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xbd0) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xbd0) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_OFFS (0xbd0) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_ATTR 0x1 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xbd4) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xbd4) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xbd4) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xbd8) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xbd8) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xbd8) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xbdc) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xbdc) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xbdc) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff -#define HWIO_TCL_R0_SW2TCL7_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xbe0) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xbe0) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_OFFS (0xbe0) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_LSB_ADDR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xbe4) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xbe4) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_OFFS (0xbe4) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_RMSK 0x1ff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_BASE_MSB_ADDR_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ADDR(x) ((x) + 0xbe8) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_PHYS(x) ((x) + 0xbe8) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_OFFS (0xbe8) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_VALUE_BMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MSI1_DATA_VALUE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xc08) -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xc08) -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_OFFS (0xc08) -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_RMSK 0xffff -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff -#define HWIO_TCL_R0_SW2TCL7_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 - -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ADDR(x) ((x) + 0xc0c) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_PHYS(x) ((x) + 0xc0c) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_OFFS (0xc0c) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_RMSK 0xffff003f -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_POR 0x00000000 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ATTR 0x3 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_IN(x) \ - in_dword(HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ADDR(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ADDR(x), m) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_OUT(x, v) \ - out_dword(HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ADDR(x),v) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_SW2TCL7_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL7_RING_MISC_1_IN(x)) -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f -#define HWIO_TCL_R0_SW2TCL7_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 - -#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 -#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL2_BMSK 0xf0000000 -#define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL2_SHFT 28 -#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 -#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xd78) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xd7c) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xd80) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 - -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xd84) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ - in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ - in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ - out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff -#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 - -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x1000) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ - in_dword(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ - in_dword_masked(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 -#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 - -#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL7_RING_BMSK 0x1c0000 -#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL7_RING_SHFT 18 -#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL6_RING_BMSK 0x38000 -#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL6_RING_SHFT 15 -#define HWIO_TCL_R1_SM_STATES_IX_2_EXTN_DESC_FETCH_BMSK 0x1c00 -#define HWIO_TCL_R1_SM_STATES_IX_2_EXTN_DESC_FETCH_SHFT 10 - -#define HWIO_TCL_R1_STATUS_TIMESTMP_FIFO_EMPTY_BMSK 0x4000000 -#define HWIO_TCL_R1_STATUS_TIMESTMP_FIFO_EMPTY_SHFT 26 -#define HWIO_TCL_R1_STATUS_FLOW_LOOKUP_INPUT_FIFO_EMPTY_BMSK 0x2000000 -#define HWIO_TCL_R1_STATUS_FLOW_LOOKUP_INPUT_FIFO_EMPTY_SHFT 25 -#define HWIO_TCL_R1_STATUS_LCE_INPUT_FIFO_EMPTY_BMSK 0x1000000 -#define HWIO_TCL_R1_STATUS_LCE_INPUT_FIFO_EMPTY_SHFT 24 -#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x10000 -#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 16 -#define HWIO_TCL_R1_STATUS_SW2TCL7_CONS_IDLE_BMSK 0x1000 -#define HWIO_TCL_R1_STATUS_SW2TCL7_CONS_IDLE_SHFT 12 -#define HWIO_TCL_R1_STATUS_SW2TCL6_CONS_IDLE_BMSK 0x800 -#define HWIO_TCL_R1_STATUS_SW2TCL6_CONS_IDLE_SHFT 11 -#define HWIO_TCL_R1_STATUS_HDR_FETCH_IDLE_BMSK 0x4 -#define HWIO_TCL_R1_STATUS_HDR_FETCH_IDLE_SHFT 2 -#define HWIO_TCL_R1_STATUS_CMD_MAPPER_IDLE_BMSK 0x2 -#define HWIO_TCL_R1_STATUS_CMD_MAPPER_IDLE_SHFT 1 -#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL7_RING_BMSK 0x1c0000 -#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL7_RING_SHFT 18 -#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL6_RING_BMSK 0x38000 -#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL6_RING_SHFT 15 -#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_EXTN_DESC_FETCH_BMSK 0x1c00 -#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_EXTN_DESC_FETCH_SHFT 10 - -#define HWIO_TCL_R1_WDOG_STATUS_TIMESTMP_FIFO_EMPTY_BMSK 0x4000000 -#define HWIO_TCL_R1_WDOG_STATUS_TIMESTMP_FIFO_EMPTY_SHFT 26 -#define HWIO_TCL_R1_WDOG_STATUS_FLOW_LOOKUP_INPUT_FIFO_EMPTY_BMSK 0x2000000 -#define HWIO_TCL_R1_WDOG_STATUS_FLOW_LOOKUP_INPUT_FIFO_EMPTY_SHFT 25 -#define HWIO_TCL_R1_WDOG_STATUS_LCE_INPUT_FIFO_EMPTY_BMSK 0x1000000 -#define HWIO_TCL_R1_WDOG_STATUS_LCE_INPUT_FIFO_EMPTY_SHFT 24 -#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x10000 -#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 16 -#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL7_CONS_IDLE_BMSK 0x1000 -#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL7_CONS_IDLE_SHFT 12 -#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL6_CONS_IDLE_BMSK 0x800 -#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL6_CONS_IDLE_SHFT 11 -#define HWIO_TCL_R1_WDOG_STATUS_HDR_FETCH_IDLE_BMSK 0x4 -#define HWIO_TCL_R1_WDOG_STATUS_HDR_FETCH_IDLE_SHFT 2 -#define HWIO_TCL_R1_WDOG_STATUS_CMD_MAPPER_IDLE_BMSK 0x2 -#define HWIO_TCL_R1_WDOG_STATUS_CMD_MAPPER_IDLE_SHFT 1 -#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL7_BMSK 0x40 -#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL7_SHFT 6 -#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL6_BMSK 0x20 -#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL6_SHFT 5 -#define HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_OFFS (0x1030) -#define HWIO_TCL_R1_TESTBUS_CTRL_RMSK 0x1ff -#define HWIO_TCL_R1_TESTBUS_CTRL_POR 0x00000000 -#define HWIO_TCL_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CTRL_ATTR 0x3 -#define HWIO_TCL_R1_TESTBUS_CTRL_IN(x) \ - in_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x)) -#define HWIO_TCL_R1_TESTBUS_CTRL_INM(x, m) \ - in_dword_masked(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x), m) -#define HWIO_TCL_R1_TESTBUS_CTRL_OUT(x, v) \ - out_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),v) -#define HWIO_TCL_R1_TESTBUS_CTRL_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TCL_R1_TESTBUS_CTRL_IN(x)) -#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x100 -#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 8 -#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_BMSK 0xc0 -#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_SHFT 6 -#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_BMSK 0x3f -#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_SHFT 0 - -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X1034 + (0x4*(n))) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_MAXn 511 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR 0x00000000 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ATTR 0x1 -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INI(base,n) \ - in_dword(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n)) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ - in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff -#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 - -#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) ((x) + 0x2000) -#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) ((x) + 0x2004) -#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) ((x) + 0x2008) -#define HWIO_TCL_R2_SW2TCL6_RING_HP_ADDR(x) ((x) + 0x2028) -#define HWIO_TCL_R2_SW2TCL6_RING_HP_PHYS(x) ((x) + 0x2028) -#define HWIO_TCL_R2_SW2TCL6_RING_HP_OFFS (0x2028) -#define HWIO_TCL_R2_SW2TCL6_RING_HP_RMSK 0xfffff -#define HWIO_TCL_R2_SW2TCL6_RING_HP_POR 0x00000000 -#define HWIO_TCL_R2_SW2TCL6_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TCL_R2_SW2TCL6_RING_HP_ATTR 0x3 -#define HWIO_TCL_R2_SW2TCL6_RING_HP_IN(x) \ - in_dword(HWIO_TCL_R2_SW2TCL6_RING_HP_ADDR(x)) -#define HWIO_TCL_R2_SW2TCL6_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TCL_R2_SW2TCL6_RING_HP_ADDR(x), m) -#define HWIO_TCL_R2_SW2TCL6_RING_HP_OUT(x, v) \ - out_dword(HWIO_TCL_R2_SW2TCL6_RING_HP_ADDR(x),v) -#define HWIO_TCL_R2_SW2TCL6_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R2_SW2TCL6_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL6_RING_HP_IN(x)) -#define HWIO_TCL_R2_SW2TCL6_RING_HP_HEAD_PTR_BMSK 0xfffff -#define HWIO_TCL_R2_SW2TCL6_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TCL_R2_SW2TCL6_RING_TP_ADDR(x) ((x) + 0x202c) -#define HWIO_TCL_R2_SW2TCL6_RING_TP_PHYS(x) ((x) + 0x202c) -#define HWIO_TCL_R2_SW2TCL6_RING_TP_OFFS (0x202c) -#define HWIO_TCL_R2_SW2TCL6_RING_TP_RMSK 0xfffff -#define HWIO_TCL_R2_SW2TCL6_RING_TP_POR 0x00000000 -#define HWIO_TCL_R2_SW2TCL6_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TCL_R2_SW2TCL6_RING_TP_ATTR 0x3 -#define HWIO_TCL_R2_SW2TCL6_RING_TP_IN(x) \ - in_dword(HWIO_TCL_R2_SW2TCL6_RING_TP_ADDR(x)) -#define HWIO_TCL_R2_SW2TCL6_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TCL_R2_SW2TCL6_RING_TP_ADDR(x), m) -#define HWIO_TCL_R2_SW2TCL6_RING_TP_OUT(x, v) \ - out_dword(HWIO_TCL_R2_SW2TCL6_RING_TP_ADDR(x),v) -#define HWIO_TCL_R2_SW2TCL6_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R2_SW2TCL6_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL6_RING_TP_IN(x)) -#define HWIO_TCL_R2_SW2TCL6_RING_TP_TAIL_PTR_BMSK 0xfffff -#define HWIO_TCL_R2_SW2TCL6_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_TCL_R2_SW2TCL7_RING_HP_ADDR(x) ((x) + 0x2030) -#define HWIO_TCL_R2_SW2TCL7_RING_HP_PHYS(x) ((x) + 0x2030) -#define HWIO_TCL_R2_SW2TCL7_RING_HP_OFFS (0x2030) -#define HWIO_TCL_R2_SW2TCL7_RING_HP_RMSK 0xfffff -#define HWIO_TCL_R2_SW2TCL7_RING_HP_POR 0x00000000 -#define HWIO_TCL_R2_SW2TCL7_RING_HP_POR_RMSK 0xffffffff -#define HWIO_TCL_R2_SW2TCL7_RING_HP_ATTR 0x3 -#define HWIO_TCL_R2_SW2TCL7_RING_HP_IN(x) \ - in_dword(HWIO_TCL_R2_SW2TCL7_RING_HP_ADDR(x)) -#define HWIO_TCL_R2_SW2TCL7_RING_HP_INM(x, m) \ - in_dword_masked(HWIO_TCL_R2_SW2TCL7_RING_HP_ADDR(x), m) -#define HWIO_TCL_R2_SW2TCL7_RING_HP_OUT(x, v) \ - out_dword(HWIO_TCL_R2_SW2TCL7_RING_HP_ADDR(x),v) -#define HWIO_TCL_R2_SW2TCL7_RING_HP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R2_SW2TCL7_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL7_RING_HP_IN(x)) -#define HWIO_TCL_R2_SW2TCL7_RING_HP_HEAD_PTR_BMSK 0xfffff -#define HWIO_TCL_R2_SW2TCL7_RING_HP_HEAD_PTR_SHFT 0 - -#define HWIO_TCL_R2_SW2TCL7_RING_TP_ADDR(x) ((x) + 0x2034) -#define HWIO_TCL_R2_SW2TCL7_RING_TP_PHYS(x) ((x) + 0x2034) -#define HWIO_TCL_R2_SW2TCL7_RING_TP_OFFS (0x2034) -#define HWIO_TCL_R2_SW2TCL7_RING_TP_RMSK 0xfffff -#define HWIO_TCL_R2_SW2TCL7_RING_TP_POR 0x00000000 -#define HWIO_TCL_R2_SW2TCL7_RING_TP_POR_RMSK 0xffffffff -#define HWIO_TCL_R2_SW2TCL7_RING_TP_ATTR 0x3 -#define HWIO_TCL_R2_SW2TCL7_RING_TP_IN(x) \ - in_dword(HWIO_TCL_R2_SW2TCL7_RING_TP_ADDR(x)) -#define HWIO_TCL_R2_SW2TCL7_RING_TP_INM(x, m) \ - in_dword_masked(HWIO_TCL_R2_SW2TCL7_RING_TP_ADDR(x), m) -#define HWIO_TCL_R2_SW2TCL7_RING_TP_OUT(x, v) \ - out_dword(HWIO_TCL_R2_SW2TCL7_RING_TP_ADDR(x),v) -#define HWIO_TCL_R2_SW2TCL7_RING_TP_OUTM(x,m,v) \ - out_dword_masked_ns(HWIO_TCL_R2_SW2TCL7_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL7_RING_TP_IN(x)) -#define HWIO_TCL_R2_SW2TCL7_RING_TP_TAIL_PTR_BMSK 0xfffff -#define HWIO_TCL_R2_SW2TCL7_RING_TP_TAIL_PTR_SHFT 0 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT16_BMSK 0x10000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT16_SHFT 16 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT15_BMSK 0x8000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT15_SHFT 15 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT12_BMSK 0x1000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT12_SHFT 12 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT7_BMSK 0x80 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT7_SHFT 7 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT3_BMSK 0x8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT3_SHFT 3 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT1_SHFT 1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT0_BMSK 0x1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT0_SHFT 0 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT16_BMSK 0x10000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT16_SHFT 16 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT15_BMSK 0x8000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT15_SHFT 15 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT12_BMSK 0x1000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT12_SHFT 12 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT7_BMSK 0x80 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT7_SHFT 7 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT3_BMSK 0x8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT3_SHFT 3 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT1_SHFT 1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT0_BMSK 0x1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT0_SHFT 0 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT3_BMSK 0x8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT3_SHFT 3 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT1_SHFT 1 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT3_BMSK 0x8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT3_SHFT 3 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT1_SHFT 1 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT3_BMSK 0x8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT3_SHFT 3 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT1_SHFT 1 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT3_BMSK 0x8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT3_SHFT 3 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT1_SHFT 1 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT3_BMSK 0x8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT3_SHFT 3 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT1_SHFT 1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT0_BMSK 0x1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT0_SHFT 0 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT3_BMSK 0x8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT3_SHFT 3 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT1_SHFT 1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT0_BMSK 0x1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT0_SHFT 0 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT23_BMSK 0x800000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT23_SHFT 23 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT22_BMSK 0x400000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT22_SHFT 22 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT21_BMSK 0x200000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT21_SHFT 21 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT20_BMSK 0x100000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT20_SHFT 20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT19_BMSK 0x80000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT19_SHFT 19 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT18_BMSK 0x40000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT18_SHFT 18 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT17_BMSK 0x20000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT17_SHFT 17 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT16_BMSK 0x10000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT16_SHFT 16 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT15_BMSK 0x8000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT15_SHFT 15 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT12_BMSK 0x1000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT12_SHFT 12 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT7_BMSK 0x80 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT7_SHFT 7 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT1_SHFT 1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT0_BMSK 0x1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT0_SHFT 0 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT23_BMSK 0x800000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT23_SHFT 23 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT22_BMSK 0x400000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT22_SHFT 22 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT21_BMSK 0x200000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT21_SHFT 21 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT20_BMSK 0x100000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT20_SHFT 20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT19_BMSK 0x80000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT19_SHFT 19 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT18_BMSK 0x40000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT18_SHFT 18 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT17_BMSK 0x20000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT17_SHFT 17 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT16_BMSK 0x10000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT16_SHFT 16 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT15_BMSK 0x8000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT15_SHFT 15 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT12_BMSK 0x1000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT12_SHFT 12 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT7_BMSK 0x80 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT7_SHFT 7 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT1_SHFT 1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT0_BMSK 0x1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT0_SHFT 0 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT23_BMSK 0x800000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT23_SHFT 23 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT22_BMSK 0x400000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT22_SHFT 22 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT21_BMSK 0x200000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT21_SHFT 21 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT20_BMSK 0x100000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT20_SHFT 20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT19_BMSK 0x80000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT19_SHFT 19 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT18_BMSK 0x40000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT18_SHFT 18 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT17_BMSK 0x20000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT17_SHFT 17 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT16_BMSK 0x10000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT16_SHFT 16 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT15_BMSK 0x8000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT15_SHFT 15 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT14_BMSK 0x4000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT14_SHFT 14 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT13_BMSK 0x2000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT13_SHFT 13 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT12_BMSK 0x1000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT12_SHFT 12 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT11_BMSK 0x800 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT11_SHFT 11 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT10_BMSK 0x400 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT10_SHFT 10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT9_BMSK 0x200 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT9_SHFT 9 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT8_BMSK 0x100 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT8_SHFT 8 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT7_BMSK 0x80 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT7_SHFT 7 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT6_BMSK 0x40 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT6_SHFT 6 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT5_BMSK 0x20 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT5_SHFT 5 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT4_BMSK 0x10 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT4_SHFT 4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT2_BMSK 0x4 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT2_SHFT 2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT1_BMSK 0x2 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT1_SHFT 1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT0_BMSK 0x1 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT0_SHFT 0 - -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT19_BMSK 0x80000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT19_SHFT 19 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT18_BMSK 0x40000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT18_SHFT 18 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT17_BMSK 0x20000 -#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT17_SHFT 17 - -#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 -#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 -#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 -#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 -#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 -#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_ADDR(x) ((x) + 0x4400) -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_PHYS(x) ((x) + 0x4400) -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_OFFS (0x4400) -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_RMSK 0xffffff -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_POR 0x0020e93b -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_POR_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_ATTR 0x1 -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_IN(x) \ - in_dword(HWIO_UMAC_NOC_DEBUG_SWID_LOW_ADDR(x)) -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_INM(x, m) \ - in_dword_masked(HWIO_UMAC_NOC_DEBUG_SWID_LOW_ADDR(x), m) -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_UNITTYPEID_BMSK 0xff0000 -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_UNITTYPEID_SHFT 16 -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_UNITCONFID_BMSK 0xffff -#define HWIO_UMAC_NOC_DEBUG_SWID_LOW_UNITCONFID_SHFT 0 - -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_ADDR(x) ((x) + 0x4404) -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_PHYS(x) ((x) + 0x4404) -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_OFFS (0x4404) -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_POR 0xb51bbb75 -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_POR_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_ATTR 0x1 -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_IN(x) \ - in_dword(HWIO_UMAC_NOC_DEBUG_SWID_HIGH_ADDR(x)) -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_INM(x, m) \ - in_dword_masked(HWIO_UMAC_NOC_DEBUG_SWID_HIGH_ADDR(x), m) -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_QNOCID_BMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_SWID_HIGH_QNOCID_SHFT 0 - -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_ADDR(x) ((x) + 0x4408) -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_PHYS(x) ((x) + 0x4408) -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_OFFS (0x4408) -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_RMSK 0x1 -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_POR 0x00000000 -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_POR_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_ATTR 0x1 -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_IN(x) \ - in_dword(HWIO_UMAC_NOC_DEBUG_LOAD_LOW_ADDR(x)) -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_INM(x, m) \ - in_dword_masked(HWIO_UMAC_NOC_DEBUG_LOAD_LOW_ADDR(x), m) -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_LOAD_BMSK 0x1 -#define HWIO_UMAC_NOC_DEBUG_LOAD_LOW_LOAD_SHFT 0 - -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_ADDR(x) ((x) + 0x4410) -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_PHYS(x) ((x) + 0x4410) -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_OFFS (0x4410) -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_POR 0xdeadbeef -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_POR_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_ATTR 0x1 -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_IN(x) \ - in_dword(HWIO_UMAC_NOC_DEBUG_DUMP_LOW_ADDR(x)) -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_INM(x, m) \ - in_dword_masked(HWIO_UMAC_NOC_DEBUG_DUMP_LOW_ADDR(x), m) -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_DUMP_LSB_BMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_DUMP_LOW_DUMP_LSB_SHFT 0 - -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_ADDR(x) ((x) + 0x4414) -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_PHYS(x) ((x) + 0x4414) -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_OFFS (0x4414) -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_POR 0xdeadbeef -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_POR_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_ATTR 0x1 -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_IN(x) \ - in_dword(HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_ADDR(x)) -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_INM(x, m) \ - in_dword_masked(HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_ADDR(x), m) -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_DUMP_MSB_BMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_DUMP_HIGH_DUMP_MSB_SHFT 0 - -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_ADDR(x) ((x) + 0x4418) -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_PHYS(x) ((x) + 0x4418) -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_OFFS (0x4418) -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_RMSK 0xffff -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_POR 0x000000dd -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_POR_RMSK 0xffffffff -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_ATTR 0x1 -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_IN(x) \ - in_dword(HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_ADDR(x)) -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_INM(x, m) \ - in_dword_masked(HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_ADDR(x), m) -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_SHIFTREGLEN_BMSK 0xffff -#define HWIO_UMAC_NOC_DEBUG_SHIFTREGLEN_LOW_SHIFTREGLEN_SHFT 0 - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwioreg_wifi_top.h b/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwioreg_wifi_top.h deleted file mode 100644 index 072ec2ed4af7..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wcss_seq_hwioreg_wifi_top.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#ifndef WCSS_SEQ_HWIOREG_WIFI_TOP_H -#define WCSS_SEQ_HWIOREG_WIFI_TOP_H - -#include "wcss_seq_hwiobase.h" - -#define WFSS_PMM_REG_BASE (WFSS_PMM_BASE + 0x00000000) - -#define HWIO_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_26_ADDR(x) ((x) + 0x164) - -#endif diff --git a/drivers/staging/fw-api/hw/wcn8750/v1/wcss_version.h b/drivers/staging/fw-api/hw/wcn8750/v1/wcss_version.h deleted file mode 100644 index cbfded86e5a4..000000000000 --- a/drivers/staging/fw-api/hw/wcn8750/v1/wcss_version.h +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - * SPDX-License-Identifier: ISC - */ - -#define WCSS_VERSION 3150 diff --git a/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_internal.h b/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_internal.h index 61c290aea844..77b1337baca5 100644 --- a/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_internal.h +++ b/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_internal.h @@ -2363,14 +2363,6 @@ void dp_is_hw_dbs_enable(struct dp_soc *soc, #if defined(WLAN_SUPPORT_RX_FISA) void dp_rx_dump_fisa_table(struct dp_soc *soc); -/** - * dp_print_fisa_stats() - Print FISA stats - * @soc: DP soc handle - * - * Return: None - */ -void dp_print_fisa_stats(struct dp_soc *soc); - /* * dp_rx_fst_update_cmem_params() - Update CMEM FST params * @soc: DP SoC context @@ -2396,10 +2388,6 @@ static inline void dp_rx_fst_update_pm_suspend_status(struct dp_soc *soc, bool suspended) { } - -static inline void dp_print_fisa_stats(struct dp_soc *soc) -{ -} #endif /* WLAN_SUPPORT_RX_FISA */ #ifdef MAX_ALLOC_PAGE_SIZE diff --git a/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_main.c b/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_main.c index c0806f998969..7016cfacc9e6 100644 --- a/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_main.c +++ b/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_main.c @@ -10101,7 +10101,6 @@ static QDF_STATUS dp_txrx_dump_stats(struct cdp_soc_t *psoc, uint16_t value, dp_txrx_path_stats(soc); dp_print_soc_interrupt_stats(soc); hal_dump_reg_write_stats(soc->hal_soc); - dp_print_fisa_stats(soc); break; case CDP_RX_RING_STATS: diff --git a/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_types.h b/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_types.h index 65057170c078..25ba47531cd1 100644 --- a/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_types.h +++ b/drivers/staging/qca-wifi-host-cmn/dp/wifi3.0/dp_types.h @@ -3134,23 +3134,10 @@ struct dp_rx_fst { #define DP_RX_GET_SW_FT_ENTRY_SIZE sizeof(struct dp_rx_fse) #elif WLAN_SUPPORT_RX_FISA -/** - * struct dp_fisa_reo_mismatch_stats - reo mismatch sub-case stats for FISA - * @allow_cce_match: packet allowed due to cce mismatch - * @allow_fse_metdata_mismatch: packet allowed since it belongs to same flow, - * only fse_metadata is not same. - * @allow_non_aggr: packet allowed due to any other reason. - */ -struct dp_fisa_reo_mismatch_stats { - uint32_t allow_cce_match; - uint32_t allow_fse_metdata_mismatch; - uint32_t allow_non_aggr; -}; - struct dp_fisa_stats { /* flow index invalid from RX HW TLV */ uint32_t invalid_flow_index; - struct dp_fisa_reo_mismatch_stats reo_mismatch; + uint32_t reo_mismatch; uint32_t incorrect_rdi; }; diff --git a/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_main.c b/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_main.c index 895c1bd94f46..14f4f978fef5 100644 --- a/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_main.c +++ b/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_main.c @@ -2227,7 +2227,7 @@ hif_send_head(struct hif_opaque_softc *hif_ctx, if (qdf_unlikely(!ce_hdl)) { hif_err("CE handle is null"); - return QDF_STATUS_E_FAILURE; + return A_ERROR; } QDF_NBUF_UPDATE_TX_PKT_COUNT(nbuf, QDF_NBUF_TX_PKT_HIF); diff --git a/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_trace.c b/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_trace.c index 30815cb19d89..0b3e2dbd150d 100644 --- a/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_trace.c +++ b/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_trace.c @@ -411,19 +411,10 @@ void qdf_mtrace_log(QDF_MODULE_ID src_module, QDF_MODULE_ID dst_module, uint16_t message_id, uint8_t vdev_id) { uint32_t trace_log, payload; - static __qdf_atomic_t counter; - static bool initialized = false; - - // Initialize counter only once - if (!initialized) { - qdf_atomic_init(&counter); - initialized = true; - } + static uint16_t counter; trace_log = (src_module << 23) | (dst_module << 15) | message_id; - - qdf_atomic_add(1, &counter); - payload = ((uint32_t)vdev_id << 16) | (qdf_atomic_read(&counter) & 0xFFFF); + payload = (vdev_id << 16) | counter++; QDF_TRACE(src_module, QDF_TRACE_LEVEL_TRACE, "%x %x", trace_log, payload); diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_build_chan_list.c b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_build_chan_list.c index b5d40a746a81..6059b406d57b 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_build_chan_list.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_build_chan_list.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1079,7 +1079,7 @@ reg_append_mas_chan_list_for_6g_lpi(struct wlan_regulatory_pdev_priv_obj struct regulatory_channel *master_chan_list_6g_client_lpi; uint8_t i, j; - if (!pdev_priv_obj->reg_rules.num_of_6g_client_reg_rules[REG_INDOOR_AP]) { + if (!pdev_priv_obj->reg_rules.num_of_6g_ap_reg_rules[REG_INDOOR_AP]) { reg_debug("No LPI reg rules"); return; } @@ -1117,7 +1117,7 @@ reg_append_mas_chan_list_for_6g_vlp(struct wlan_regulatory_pdev_priv_obj struct regulatory_channel *master_chan_list_6g_client_vlp; uint8_t i, j; - if (!pdev_priv_obj->reg_rules.num_of_6g_client_reg_rules[REG_VERY_LOW_POWER_AP]) { + if (!pdev_priv_obj->reg_rules.num_of_6g_ap_reg_rules[REG_VERY_LOW_POWER_AP]) { reg_debug("No VLP reg rules"); return; } @@ -1758,8 +1758,9 @@ static void reg_store_regulatory_ext_info_to_socpriv( soc_reg->domain_code_6g_ap[i] = regulat_info->domain_code_6g_ap[i]; - soc_reg->mas_chan_params[phy_id]. - is_6g_channel_list_populated = true; + if (soc_reg->domain_code_6g_ap[i]) + soc_reg->mas_chan_params[phy_id]. + is_6g_channel_list_populated = true; qdf_mem_copy(soc_reg->domain_code_6g_client[i], regulat_info->domain_code_6g_client[i], @@ -2088,11 +2089,6 @@ QDF_STATUS reg_process_master_chan_list_ext( reg_store_regulatory_ext_info_to_socpriv(soc_reg, regulat_info, phy_id); - if (this_mchan_params->client_type >= REG_MAX_CLIENT_TYPE) { - reg_err("6 GHz reg client type invalid"); - return QDF_STATUS_E_FAILURE; - } - status = reg_fill_master_channels(regulat_info, &this_mchan_params->reg_rules, this_mchan_params->client_type, diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services_common.c b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services_common.c index 328a4898dcd1..7732e35b5ee4 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services_common.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services_common.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022,2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -5113,7 +5113,7 @@ QDF_STATUS reg_get_6g_chan_ap_power(struct wlan_objmgr_pdev *pdev, QDF_STATUS reg_get_client_power_for_connecting_ap(struct wlan_objmgr_pdev *pdev, enum reg_6g_ap_type ap_type, qdf_freq_t chan_freq, - bool is_psd, + bool *is_psd, uint16_t *tx_power, uint16_t *eirp_psd_power) { @@ -5136,7 +5136,8 @@ QDF_STATUS reg_get_client_power_for_connecting_ap(struct wlan_objmgr_pdev *pdev, reg_find_txpower_from_6g_list(chan_freq, master_chan_list, tx_power); - if (is_psd) + *is_psd = reg_is_6g_psd_power(pdev); + if (*is_psd) status = reg_get_6g_chan_psd_eirp_power(chan_freq, master_chan_list, eirp_psd_power); diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services_common.h b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services_common.h index 3a94a215298a..c0d478ea1887 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services_common.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services_common.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. * * * Permission to use, copy, modify, and/or distribute this software for @@ -1484,7 +1484,7 @@ QDF_STATUS reg_get_6g_chan_ap_power(struct wlan_objmgr_pdev *pdev, * * This function is meant to be called to find the channel frequency power * information for a client when the device is operating as a client. It will - * fill in the parameters tx_power and eirp_psd_power. eirp_psd_power + * fill in the parameter is_psd, tx_power, and eirp_psd_power. eirp_psd_power * will only be filled if the channel is PSD. * * Return: QDF_STATUS @@ -1492,7 +1492,7 @@ QDF_STATUS reg_get_6g_chan_ap_power(struct wlan_objmgr_pdev *pdev, QDF_STATUS reg_get_client_power_for_connecting_ap(struct wlan_objmgr_pdev *pdev, enum reg_6g_ap_type ap_type, qdf_freq_t chan_freq, - bool is_psd, + bool *is_psd, uint16_t *tx_power, uint16_t *eirp_psd_power); @@ -1582,10 +1582,11 @@ static inline QDF_STATUS reg_get_client_power_for_connecting_ap(struct wlan_objmgr_pdev *pdev, enum reg_6g_ap_type ap_type, qdf_freq_t chan_freq, - bool is_psd, + bool *is_psd, uint16_t *tx_power, uint16_t *eirp_psd_power) { + *is_psd = false; *tx_power = 0; *eirp_psd_power = 0; return QDF_STATUS_E_NOSUPPORT; diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/inc/wlan_reg_services_api.h b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/inc/wlan_reg_services_api.h index c380a077abe5..d8c7ad95a133 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/inc/wlan_reg_services_api.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/inc/wlan_reg_services_api.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1869,8 +1869,8 @@ QDF_STATUS wlan_reg_get_6g_chan_ap_power(struct wlan_objmgr_pdev *pdev, * * This function is meant to be called to find the channel frequency power * information for a client when the device is operating as a client. It will - * fill in the parameters tx_power and eirp_psd_power. eirp_psd_power will - * only be filled if the channel is PSD. + * fill in the parameter is_psd, tx_power, and eirp_psd_power. eirp_psd_power + * will only be filled if the channel is PSD. * * Return: QDF_STATUS */ @@ -1878,7 +1878,7 @@ QDF_STATUS wlan_reg_get_client_power_for_connecting_ap(struct wlan_objmgr_pdev *pdev, enum reg_6g_ap_type ap_type, qdf_freq_t chan_freq, - bool is_psd, uint16_t *tx_power, + bool *is_psd, uint16_t *tx_power, uint16_t *eirp_psd_power); /** @@ -1985,9 +1985,10 @@ static inline QDF_STATUS wlan_reg_get_client_power_for_connecting_ap(struct wlan_objmgr_pdev *pdev, enum reg_6g_ap_type ap_type, qdf_freq_t chan_freq, - bool is_psd, uint16_t *tx_power, + bool *is_psd, uint16_t *tx_power, uint16_t *eirp_psd_power) { + *is_psd = false; *tx_power = 0; *eirp_psd_power = 0; return QDF_STATUS_E_NOSUPPORT; diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/src/wlan_reg_services_api.c b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/src/wlan_reg_services_api.c index 7d458f0421fc..2b720dee6ca6 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/src/wlan_reg_services_api.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/src/wlan_reg_services_api.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * * Permission to use, copy, modify, and/or distribute this software for @@ -1443,7 +1443,7 @@ QDF_STATUS wlan_reg_get_client_power_for_connecting_ap(struct wlan_objmgr_pdev *pdev, enum reg_6g_ap_type ap_type, qdf_freq_t chan_freq, - bool is_psd, uint16_t *tx_power, + bool *is_psd, uint16_t *tx_power, uint16_t *eirp_psd_power) { return reg_get_client_power_for_connecting_ap(pdev, ap_type, chan_freq, diff --git a/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c b/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c index b9359e099ce6..cd998b35ca7e 100644 --- a/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c +++ b/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c @@ -14208,14 +14208,9 @@ extract_roam_scan_ap_stats_tlv(wmi_unified_t wmi_handle, void *evt_buf, return QDF_STATUS_E_FAILURE; } - /* - * Check to validate that the requested number of APs do not exceed the - * remaining APs in param_buf after ap_idx to prevent out of bounds - * access. - */ - if ((ap_idx + num_cand) > param_buf->num_roam_ap_info) { - wmi_err("Invalid roam scan AP tlv ap_idx:%d, num_cand:%d, total_ap:%d", - ap_idx, num_cand, param_buf->num_roam_ap_info); + if (ap_idx >= param_buf->num_roam_ap_info) { + wmi_err("Invalid roam scan AP tlv ap_idx:%d total_ap:%d", + ap_idx, param_buf->num_roam_ap_info); return QDF_STATUS_E_FAILURE; } @@ -14729,12 +14724,6 @@ static QDF_STATUS extract_pdev_csa_switch_count_status_tlv( wmi_handle, csa_status->pdev_id); param->current_switch_count = csa_status->current_switch_count; - - if (param_buf->num_vdev_ids != csa_status->num_vdevs) { - wmi_err("Invalid number of vdevs: received = %d, expected = %d", - csa_status->num_vdevs, param_buf->num_vdev_ids); - return QDF_STATUS_E_INVAL; - } param->num_vdevs = csa_status->num_vdevs; param->vdev_ids = param_buf->vdev_ids; diff --git a/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h b/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h index 141ce08f47a2..d902f7ee4327 100644 --- a/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h +++ b/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h @@ -210,24 +210,6 @@ QDF_STATUS policy_mgr_get_sta_sap_scc_on_dfs_chnl(struct wlan_objmgr_psoc *psoc, uint8_t *sta_sap_scc_on_dfs_chnl); -/** - * policy_mgr_is_bonded_chan_dfs() - check whether the given bonded - * channel configuration falls under DFS - * @psoc: pointer to psoc - * @ch_width: channel width of the operating channel - * @mhz_freq_seg1: center frequency of segment 1; used for 80+80 MHz - * @chan_freq: primary/operating channel frequency in MHz - * - * This API checks whether the given channel or bonded channel span - * includes DFS, based on the channel width and frequency segments. - * - * Return: true if the given bonded channel is DFS, else false. - */ -bool -policy_mgr_is_bonded_chan_dfs(struct wlan_objmgr_psoc *psoc, - enum phy_ch_width ch_width, - qdf_freq_t mhz_freq_seg1, - uint32_t chan_freq); /** * policy_mgr_get_dfs_master_dynamic_enabled() - support dfs master or not * on AP interafce when STA+SAP(GO) concurrency diff --git a/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c b/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c index 0bffbe5e612e..5661c5a03491 100644 --- a/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c +++ b/drivers/staging/qcacld-3.0/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c @@ -181,45 +181,6 @@ policy_mgr_get_sta_sap_scc_on_dfs_chnl(struct wlan_objmgr_psoc *psoc, return QDF_STATUS_SUCCESS; } -bool -policy_mgr_is_bonded_chan_dfs(struct wlan_objmgr_psoc *psoc, - enum phy_ch_width ch_width, - qdf_freq_t mhz_freq_seg1, - uint32_t chan_freq) -{ - bool is_ch_dfs = false; - struct policy_mgr_psoc_priv_obj *pm_ctx; - - pm_ctx = policy_mgr_get_context(psoc); - if (!pm_ctx) { - policy_mgr_err("pm_ctx is NULL"); - return false; - } - - if (ch_width == CH_WIDTH_160MHZ) { - if (wlan_reg_get_5g_bonded_channel_state_for_freq(pm_ctx->pdev, - chan_freq, - ch_width) - == CHANNEL_STATE_DFS) - is_ch_dfs = true; - } else if (ch_width == CH_WIDTH_80P80MHZ) { - if (wlan_reg_get_channel_state_for_freq( - pm_ctx->pdev, - chan_freq) == - CHANNEL_STATE_DFS || - wlan_reg_get_channel_state_for_freq( - pm_ctx->pdev, - mhz_freq_seg1) == - CHANNEL_STATE_DFS) - is_ch_dfs = true; - } else { - if (wlan_reg_is_dfs_for_freq(pm_ctx->pdev, chan_freq)) - is_ch_dfs = true; - } - - return is_ch_dfs; -} - static bool policy_mgr_update_dfs_master_dynamic_enabled( struct wlan_objmgr_psoc *psoc, uint8_t vdev_id) diff --git a/drivers/staging/qcacld-3.0/components/mlme/core/src/wlan_mlme_main.c b/drivers/staging/qcacld-3.0/components/mlme/core/src/wlan_mlme_main.c index 131518cc5cd9..66f4ef140432 100644 --- a/drivers/staging/qcacld-3.0/components/mlme/core/src/wlan_mlme_main.c +++ b/drivers/staging/qcacld-3.0/components/mlme/core/src/wlan_mlme_main.c @@ -1,7 +1,6 @@ /* * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1847,8 +1846,6 @@ static void mlme_init_lfr_cfg(struct wlan_objmgr_psoc *psoc, cfg_get(psoc, CFG_LFR3_ROAM_PREAUTH_RETRY_COUNT); lfr->roam_rssi_diff = cfg_get(psoc, CFG_LFR_ROAM_RSSI_DIFF); lfr->roam_rssi_diff_6ghz = cfg_get(psoc, CFG_LFR_ROAM_RSSI_DIFF_6GHZ); - lfr->roam_rssi_delta_6ghz_to_non_6ghz = - cfg_get(psoc, CFG_LFR_ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ); lfr->bg_rssi_threshold = cfg_get(psoc, CFG_LFR_ROAM_BG_RSSI_TH); lfr->roam_scan_offload_enabled = cfg_get(psoc, CFG_LFR_ROAM_SCAN_OFFLOAD_ENABLED); diff --git a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/cfg_mlme_lfr.h b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/cfg_mlme_lfr.h index 135eb7597a3c..6ad5d7011e58 100644 --- a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/cfg_mlme_lfr.h +++ b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/cfg_mlme_lfr.h @@ -1,7 +1,6 @@ /* * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1281,38 +1280,6 @@ CFG_VALUE_OR_DEFAULT, \ "Enable 6 GHz roam based on rssi") -/* - * - * roam_rssi_delta_from_6ghz_to_non_6ghz - Enable roam to Non 6 GHz AP based - * on rssi - * @Min: 0 - * @Max: 100 - * @Default: 0 - * - * This INI is used to decide whether to roam to Non 6 GHz AP or not based on - * RSSI. AP1 is the currently associated AP(6 GHz) and AP2(2.4 GHz / 5 GHz) is - * chosen for roaming. The Roaming will happen only if AP2 has better Signal - * Quality and it has a RSSI better than AP1. - * roam_rssi_delta_from_6ghz_to_non_6ghz is the number of dB units AP2 is - * better than AP1. - * - * - * Related: None - * - * Supported Feature: Roaming - * - * Usage: External - * - * - */ -#define CFG_LFR_ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ CFG_INI_UINT( \ - "roam_rssi_delta_from_6ghz_to_non_6ghz", \ - 0, \ - 100, \ - 0, \ - CFG_VALUE_OR_DEFAULT, \ - "Enable 6 GHz to non 6 GHz roam based on rssi") - /* * * bg_rssi_threshold - To set RSSI Threshold for BG scan roaming @@ -2963,7 +2930,6 @@ CFG(CFG_LFR_FAST_TRANSITION_ENABLED) \ CFG(CFG_LFR_ROAM_RSSI_DIFF) \ CFG(CFG_LFR_ROAM_RSSI_DIFF_6GHZ) \ - CFG(CFG_LFR_ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ) \ CFG(CFG_LFR_ROAM_BG_RSSI_TH) \ CFG(CFG_LFR_ENABLE_WES_MODE) \ CFG(CFG_LFR_ROAM_SCAN_OFFLOAD_ENABLED) \ diff --git a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_api.h b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_api.h index 3b757579f129..401bd9c549e5 100644 --- a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_api.h +++ b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_api.h @@ -2444,30 +2444,11 @@ wlan_mlme_get_ignore_fw_reg_offload_ind(struct wlan_objmgr_psoc *psoc, char *mlme_get_roam_trigger_str(uint32_t roam_scan_trigger); /** - * enum roam_stats_scan_type - Roam scan type defines - * @ROAM_STATS_SCAN_TYPE_PARTIAL: Partial scan - * @ROAM_STATS_SCAN_TYPE_FULL: Full scan - * @ROAM_STATS_SCAN_TYPE_NO_SCAN: No roam scan was triggered. This is generally - * used in BTM events to indicate BTM frame exchange logs. - * @ROAM_STATS_SCAN_TYPE_HIGHER_BAND_5GHZ_6GHZ: Higher band roam scan from 2 GHz - * to 5 GHz or 6 GHz - * @ROAM_STATS_SCAN_TYPE_HIGHER_BAND_6GHZ: Higher band roam scan from 5 GHz to - * 6 GHz - */ -enum roam_stats_scan_type { - ROAM_STATS_SCAN_TYPE_PARTIAL = 0, - ROAM_STATS_SCAN_TYPE_FULL = 1, - ROAM_STATS_SCAN_TYPE_NO_SCAN = 2, - ROAM_STATS_SCAN_TYPE_HIGHER_BAND_5GHZ_6GHZ = 3, - ROAM_STATS_SCAN_TYPE_HIGHER_BAND_6GHZ = 4, -}; - -/** - * mlme_get_roam_scan_type_str() - Get the string for roam scan type + * mlme_get_roam_scan_type_str() - Get the string for roam sacn type * @roam_scan_type: roam scan type coming from fw via * wmi_roam_scan_info tlv * - * Return: Meaningful string for roam scan type + * Return: Meaningful string for roam sacn type */ char *mlme_get_roam_scan_type_str(uint32_t roam_scan_type); diff --git a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_public_struct.h b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_public_struct.h index 9ca94e78d468..ad48cd35c0cd 100644 --- a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_public_struct.h +++ b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_public_struct.h @@ -1,7 +1,6 @@ /* * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1681,10 +1680,8 @@ struct fw_scan_channels { * @roam_preauth_no_ack_timeout: Configure the no ack timeout period * @roam_rssi_diff: Enable roam based on rssi * @roam_rssi_diff_6ghz: RSSI diff value to be used for roaming to 6 GHz AP. - * @roam_rssi_delta_6ghz_to_non_6ghz: RSSI diff value to be used for - * roaming from 6 GHz to Non 6GHz AP. - * @roam_scan_offload_enabled: Enable Roam Scan Offload - * @neighbor_scan_timer_period: Neighbor scan timer period + * @roam_scan_offload_enabled: Enable Roam Scan Offload + * @neighbor_scan_timer_period: Neighbor scan timer period * @neighbor_scan_min_timer_period: Min neighbor scan timer period * @neighbor_lookup_rssi_threshold: Neighbor lookup rssi threshold * @opportunistic_scan_threshold_diff: Set oppurtunistic threshold diff @@ -1807,7 +1804,6 @@ struct wlan_mlme_lfr_cfg { uint32_t roam_preauth_no_ack_timeout; uint8_t roam_rssi_diff; uint8_t roam_rssi_diff_6ghz; - uint8_t roam_rssi_delta_6ghz_to_non_6ghz; uint8_t bg_rssi_threshold; bool roam_scan_offload_enabled; uint32_t neighbor_scan_timer_period; diff --git a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/src/wlan_mlme_api.c b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/src/wlan_mlme_api.c index 633b36067c91..dd930d969742 100644 --- a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/src/wlan_mlme_api.c +++ b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/src/wlan_mlme_api.c @@ -3793,16 +3793,14 @@ char *mlme_get_roam_status_str(uint32_t roam_status) char *mlme_get_roam_scan_type_str(uint32_t roam_scan_type) { switch (roam_scan_type) { - case ROAM_STATS_SCAN_TYPE_PARTIAL: + case 0: return "PARTIAL"; - case ROAM_STATS_SCAN_TYPE_FULL: + case 1: return "FULL"; - case ROAM_STATS_SCAN_TYPE_NO_SCAN: + case 2: return "NO SCAN"; - case ROAM_STATS_SCAN_TYPE_HIGHER_BAND_5GHZ_6GHZ: - return "Higher Band: 5 GHz + 6 GHz"; - case ROAM_STATS_SCAN_TYPE_HIGHER_BAND_6GHZ: - return "Higher Band : 6 GHz"; + case 3: + return "Higher Band"; default: return "UNKNOWN"; } diff --git a/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_off_chan_tx.c b/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_off_chan_tx.c index 857e619900a8..1478df85dce7 100644 --- a/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_off_chan_tx.c +++ b/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_off_chan_tx.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -211,7 +211,7 @@ static QDF_STATUS p2p_check_and_update_channel(struct tx_action_context *tx_ctx) struct p2p_soc_priv_obj *p2p_soc_obj; struct p2p_roc_context *curr_roc_ctx; - if (!tx_ctx || tx_ctx->chan_freq) { + if (!tx_ctx || tx_ctx->chan) { p2p_err("NULL tx ctx or channel valid"); return QDF_STATUS_E_INVAL; } @@ -232,7 +232,7 @@ static QDF_STATUS p2p_check_and_update_channel(struct tx_action_context *tx_ctx) (mode == QDF_P2P_DEVICE_MODE || mode == QDF_P2P_CLIENT_MODE || mode == QDF_P2P_GO_MODE)) - tx_ctx->chan_freq = curr_roc_ctx->chan_freq; + tx_ctx->chan = curr_roc_ctx->chan; wlan_objmgr_vdev_release_ref(vdev, WLAN_P2P_ID); @@ -1068,13 +1068,16 @@ static QDF_STATUS p2p_mgmt_tx(struct tx_action_context *tx_ctx, void *mac_addr; uint8_t pdev_id; struct wlan_objmgr_vdev *vdev; + uint16_t chanfreq = 0; psoc = tx_ctx->p2p_soc_obj->soc; mgmt_param.tx_frame = packet; mgmt_param.frm_len = buf_len; mgmt_param.vdev_id = tx_ctx->vdev_id; mgmt_param.pdata = frame; - mgmt_param.chanfreq = tx_ctx->chan_freq; + if (tx_ctx->chan) + chanfreq = (uint16_t)wlan_chan_to_freq(tx_ctx->chan); + mgmt_param.chanfreq = chanfreq; mgmt_param.qdf_ctx = wlan_psoc_get_qdf_dev(psoc); if (!(mgmt_param.qdf_ctx)) { @@ -1158,7 +1161,7 @@ static QDF_STATUS p2p_roc_req_for_tx_action( p2p_soc_obj = tx_ctx->p2p_soc_obj; roc_ctx->p2p_soc_obj = p2p_soc_obj; roc_ctx->vdev_id = tx_ctx->vdev_id; - roc_ctx->chan_freq = tx_ctx->chan_freq; + roc_ctx->chan = tx_ctx->chan; roc_ctx->duration = tx_ctx->duration; roc_ctx->roc_state = ROC_STATE_IDLE; roc_ctx->roc_type = OFF_CHANNEL_TX; @@ -1801,15 +1804,13 @@ void p2p_dump_tx_queue(struct p2p_soc_priv_obj *p2p_soc_obj) while (QDF_IS_STATUS_SUCCESS(status)) { tx_ctx = qdf_container_of(p_node, struct tx_action_context, node); - p2p_debug("p2p soc object:%pK, tx ctx:%pK, vdev_id:%d, " - "scan_id:%d, roc_cookie:%llx, freq:%d, buf:%pK, " - "len:%d, off_chan:%d, cck:%d, ack:%d, duration:%d", - p2p_soc_obj, tx_ctx, - tx_ctx->vdev_id, tx_ctx->scan_id, - tx_ctx->roc_cookie, tx_ctx->chan_freq, - tx_ctx->buf, tx_ctx->buf_len, - tx_ctx->off_chan, tx_ctx->no_cck, - tx_ctx->no_ack, tx_ctx->duration); + p2p_debug("p2p soc object:%pK, tx ctx:%pK, vdev_id:%d, scan_id:%d, roc_cookie:%llx, chan:%d, buf:%pK, len:%d, off_chan:%d, cck:%d, ack:%d, duration:%d", + p2p_soc_obj, tx_ctx, + tx_ctx->vdev_id, tx_ctx->scan_id, + tx_ctx->roc_cookie, tx_ctx->chan, + tx_ctx->buf, tx_ctx->buf_len, + tx_ctx->off_chan, tx_ctx->no_cck, + tx_ctx->no_ack, tx_ctx->duration); status = qdf_list_peek_next(&p2p_soc_obj->tx_q_roc, p_node, &p_node); @@ -1821,15 +1822,13 @@ void p2p_dump_tx_queue(struct p2p_soc_priv_obj *p2p_soc_obj) while (QDF_IS_STATUS_SUCCESS(status)) { tx_ctx = qdf_container_of(p_node, struct tx_action_context, node); - p2p_debug("p2p soc object:%pK, tx_ctx:%pK, vdev_id:%d, " - "scan_id:%d, roc_cookie:%llx, freq:%d, buf:%pK, " - "len:%d, off_chan:%d, cck:%d, ack:%d, duration:%d", - p2p_soc_obj, tx_ctx, - tx_ctx->vdev_id, tx_ctx->scan_id, - tx_ctx->roc_cookie, tx_ctx->chan_freq, - tx_ctx->buf, tx_ctx->buf_len, - tx_ctx->off_chan, tx_ctx->no_cck, - tx_ctx->no_ack, tx_ctx->duration); + p2p_debug("p2p soc object:%pK, tx_ctx:%pK, vdev_id:%d, scan_id:%d, roc_cookie:%llx, chan:%d, buf:%pK, len:%d, off_chan:%d, cck:%d, ack:%d, duration:%d", + p2p_soc_obj, tx_ctx, + tx_ctx->vdev_id, tx_ctx->scan_id, + tx_ctx->roc_cookie, tx_ctx->chan, + tx_ctx->buf, tx_ctx->buf_len, + tx_ctx->off_chan, tx_ctx->no_cck, + tx_ctx->no_ack, tx_ctx->duration); status = qdf_list_peek_next(&p2p_soc_obj->tx_q_ack, p_node, &p_node); @@ -2919,17 +2918,17 @@ void p2p_rand_mac_tx(struct tx_action_context *tx_action) return; soc = tx_action->p2p_soc_obj->soc; - if (!tx_action->no_ack && tx_action->chan_freq && + if (!tx_action->no_ack && tx_action->chan && tx_action->buf_len > MIN_MAC_HEADER_LEN && p2p_is_vdev_support_rand_mac_by_id(soc, tx_action->vdev_id) && p2p_is_random_mac(soc, tx_action->vdev_id, &tx_action->buf[SRC_MAC_ADDR_OFFSET])) { status = p2p_request_random_mac( - soc, tx_action->vdev_id, - &tx_action->buf[SRC_MAC_ADDR_OFFSET], - tx_action->chan_freq, - tx_action->id, - tx_action->duration); + soc, tx_action->vdev_id, + &tx_action->buf[SRC_MAC_ADDR_OFFSET], + wlan_chan_to_freq(tx_action->chan), + tx_action->id, + tx_action->duration); if (status == QDF_STATUS_SUCCESS) tx_action->rand_mac_tx = true; else @@ -2999,13 +2998,11 @@ QDF_STATUS p2p_process_mgmt_tx(struct tx_action_context *tx_ctx) p2p_soc_obj = tx_ctx->p2p_soc_obj; - p2p_debug("soc:%pK, tx_ctx:%pK, vdev_id:%d, scan_id:%d, " - "roc_cookie:%llx, freq:%d, buf:%pK, len:%d, " - "off_chan:%d, cck:%d, ack:%d, duration:%d", - p2p_soc_obj->soc, tx_ctx, tx_ctx->vdev_id, - tx_ctx->scan_id, tx_ctx->roc_cookie, tx_ctx->chan_freq, - tx_ctx->buf, tx_ctx->buf_len, tx_ctx->off_chan, - tx_ctx->no_cck, tx_ctx->no_ack, tx_ctx->duration); + p2p_debug("soc:%pK, tx_ctx:%pK, vdev_id:%d, scan_id:%d, roc_cookie:%llx, chan:%d, buf:%pK, len:%d, off_chan:%d, cck:%d, ack:%d, duration:%d", + p2p_soc_obj->soc, tx_ctx, tx_ctx->vdev_id, + tx_ctx->scan_id, tx_ctx->roc_cookie, tx_ctx->chan, + tx_ctx->buf, tx_ctx->buf_len, tx_ctx->off_chan, + tx_ctx->no_cck, tx_ctx->no_ack, tx_ctx->duration); status = p2p_get_frame_info(tx_ctx->buf, tx_ctx->buf_len, &(tx_ctx->frame_info)); @@ -3034,8 +3031,8 @@ QDF_STATUS p2p_process_mgmt_tx(struct tx_action_context *tx_ctx) tx_ctx->no_ack = 1; } - if (!tx_ctx->off_chan || !tx_ctx->chan_freq) { - if (!tx_ctx->chan_freq) + if (!tx_ctx->off_chan || !tx_ctx->chan) { + if (!tx_ctx->chan) p2p_check_and_update_channel(tx_ctx); status = p2p_execute_tx_action_frame(tx_ctx); if (status != QDF_STATUS_SUCCESS) { @@ -3047,7 +3044,7 @@ QDF_STATUS p2p_process_mgmt_tx(struct tx_action_context *tx_ctx) /* For off channel tx case */ curr_roc_ctx = p2p_find_current_roc_ctx(p2p_soc_obj); - if (curr_roc_ctx && (curr_roc_ctx->chan_freq == tx_ctx->chan_freq)) { + if (curr_roc_ctx && (curr_roc_ctx->chan == tx_ctx->chan)) { if ((curr_roc_ctx->roc_state == ROC_STATE_REQUESTED) || (curr_roc_ctx->roc_state == ROC_STATE_STARTED)) { tx_ctx->roc_cookie = (uintptr_t)curr_roc_ctx; @@ -3078,8 +3075,7 @@ QDF_STATUS p2p_process_mgmt_tx(struct tx_action_context *tx_ctx) } } - curr_roc_ctx = p2p_find_roc_by_chan_freq(p2p_soc_obj, - tx_ctx->chan_freq); + curr_roc_ctx = p2p_find_roc_by_chan(p2p_soc_obj, tx_ctx->chan); if (curr_roc_ctx && (curr_roc_ctx->roc_state == ROC_STATE_IDLE)) { tx_ctx->roc_cookie = (uintptr_t)curr_roc_ctx; status = qdf_list_insert_back( diff --git a/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_off_chan_tx.h b/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_off_chan_tx.h index 5b98ccbc7066..46e80fca5a33 100644 --- a/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_off_chan_tx.h +++ b/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_off_chan_tx.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. - * Copyright (c) 2022, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -157,7 +157,7 @@ struct p2p_frame_info { * @scan_id: Scan id given by scan component for this roc req * @roc_cookie: Cookie for remain on channel request * @id: Identifier of this tx context - * @chan_freq: Chan frequency for which this tx has been requested + * @chan: Chan for which this tx has been requested * @buf: tx buffer * @buf_len: Length of tx buffer * @off_chan: Is this off channel tx @@ -174,7 +174,7 @@ struct tx_action_context { int scan_id; uint64_t roc_cookie; int32_t id; - qdf_freq_t chan_freq; + uint8_t chan; uint8_t *buf; int buf_len; bool off_chan; diff --git a/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_roc.c b/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_roc.c index 643d54a1a428..7146367eae62 100644 --- a/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_roc.c +++ b/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_roc.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -114,7 +114,7 @@ static QDF_STATUS p2p_scan_start(struct p2p_roc_context *roc_ctx) req->scan_req.scan_type = SCAN_TYPE_P2P_LISTEN; req->scan_req.scan_req_id = p2p_soc_obj->scan_req_id; req->scan_req.chan_list.num_chan = 1; - req->scan_req.chan_list.chan[0].freq = roc_ctx->chan_freq; + req->scan_req.chan_list.chan[0].freq = wlan_chan_to_freq(roc_ctx->chan); req->scan_req.dwell_time_passive = roc_ctx->duration; req->scan_req.dwell_time_active = 0; req->scan_req.scan_priority = SCAN_PRIORITY_HIGH; @@ -278,7 +278,7 @@ static QDF_STATUS p2p_send_roc_event( p2p_evt.vdev_id = roc_ctx->vdev_id; p2p_evt.roc_event = evt; p2p_evt.cookie = (uint64_t)roc_ctx->id; - p2p_evt.chan_freq = roc_ctx->chan_freq; + p2p_evt.chan = roc_ctx->chan; p2p_evt.duration = roc_ctx->duration; p2p_debug("roc_event: %d, cookie:%llx", p2p_evt.roc_event, @@ -305,10 +305,9 @@ static QDF_STATUS p2p_destroy_roc_ctx(struct p2p_roc_context *roc_ctx, QDF_STATUS status = QDF_STATUS_SUCCESS; struct p2p_soc_priv_obj *p2p_soc_obj = roc_ctx->p2p_soc_obj; - p2p_debug("p2p_soc_obj:%pK, roc_ctx:%pK, up_layer_event:%d," - " in_roc_queue:%d vdev_id:%d freq:%d duration:%d", - p2p_soc_obj, roc_ctx, up_layer_event, in_roc_queue, - roc_ctx->vdev_id, roc_ctx->chan_freq, roc_ctx->duration); + p2p_debug("p2p_soc_obj:%pK, roc_ctx:%pK, up_layer_event:%d, in_roc_queue:%d vdev_id:%d chan:%d duration:%d", + p2p_soc_obj, roc_ctx, up_layer_event, in_roc_queue, + roc_ctx->vdev_id, roc_ctx->chan, roc_ctx->duration); if (up_layer_event) { if (roc_ctx->roc_state < ROC_STATE_ON_CHAN) @@ -392,13 +391,11 @@ static void p2p_roc_timeout(void *pdata) return; } - p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d," - " tx ctx:%pK, freq:%d, phy_mode:%d, duration:%d," - " roc_type:%d, roc_state:%d", - roc_ctx->p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, - roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan_freq, - roc_ctx->phy_mode, roc_ctx->duration, - roc_ctx->roc_type, roc_ctx->roc_state); + p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d, tx ctx:%pK, chan:%d, phy_mode:%d, duration:%d, roc_type:%d, roc_state:%d", + roc_ctx->p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, + roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan, + roc_ctx->phy_mode, roc_ctx->duration, + roc_ctx->roc_type, roc_ctx->roc_state); if (roc_ctx->roc_state == ROC_STATE_CANCEL_IN_PROG) { p2p_err("Cancellation already in progress"); @@ -421,13 +418,11 @@ static QDF_STATUS p2p_execute_roc_req(struct p2p_roc_context *roc_ctx) QDF_STATUS status; struct p2p_soc_priv_obj *p2p_soc_obj = roc_ctx->p2p_soc_obj; - p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d," - " tx ctx:%pK, freq:%d, phy_mode:%d, duration:%d," - " roc_type:%d, roc_state:%d", - p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, - roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan_freq, - roc_ctx->phy_mode, roc_ctx->duration, - roc_ctx->roc_type, roc_ctx->roc_state); + p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d, tx ctx:%pK, chan:%d, phy_mode:%d, duration:%d, roc_type:%d, roc_state:%d", + p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, + roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan, + roc_ctx->phy_mode, roc_ctx->duration, + roc_ctx->roc_type, roc_ctx->roc_state); /* prevent runtime suspend */ qdf_runtime_pm_prevent_suspend(&p2p_soc_obj->roc_runtime_lock); @@ -650,14 +645,14 @@ struct p2p_roc_context *p2p_find_current_roc_ctx( struct p2p_roc_context, node); if (roc_ctx->roc_state != ROC_STATE_IDLE) { p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id" - ":%d, scan_id:%d, tx ctx:%pK, freq:" - "%d, phy_mode:%d, duration:%d, " - "roc_type:%d, roc_state:%d", - roc_ctx->p2p_soc_obj, roc_ctx, - roc_ctx->vdev_id, roc_ctx->scan_id, - roc_ctx->tx_ctx, roc_ctx->chan_freq, - roc_ctx->phy_mode, roc_ctx->duration, - roc_ctx->roc_type, roc_ctx->roc_state); + ":%d, scan_id:%d, tx ctx:%pK, chan:" + "%d, phy_mode:%d, duration:%d, " + "roc_type:%d, roc_state:%d", + roc_ctx->p2p_soc_obj, roc_ctx, + roc_ctx->vdev_id, roc_ctx->scan_id, + roc_ctx->tx_ctx, roc_ctx->chan, + roc_ctx->phy_mode, roc_ctx->duration, + roc_ctx->roc_type, roc_ctx->roc_state); return roc_ctx; } @@ -690,8 +685,8 @@ struct p2p_roc_context *p2p_find_roc_by_tx_ctx( return NULL; } -struct p2p_roc_context *p2p_find_roc_by_chan_freq( - struct p2p_soc_priv_obj *p2p_soc_obj, qdf_freq_t chan_freq) +struct p2p_roc_context *p2p_find_roc_by_chan( + struct p2p_soc_priv_obj *p2p_soc_obj, uint8_t chan) { struct p2p_roc_context *roc_ctx; qdf_list_node_t *p_node; @@ -702,14 +697,11 @@ struct p2p_roc_context *p2p_find_roc_by_chan_freq( roc_ctx = qdf_container_of(p_node, struct p2p_roc_context, node); - if (roc_ctx->chan_freq == chan_freq) { - p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d," - " scan_id:%d, tx ctx:%pK, freq:%d," - " phy_mode:%d, duration:%d," - " roc_type:%d, roc_state:%d", + if (roc_ctx->chan == chan) { + p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d, tx ctx:%pK, chan:%d, phy_mode:%d, duration:%d, roc_type:%d, roc_state:%d", roc_ctx->p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, roc_ctx->scan_id, - roc_ctx->tx_ctx, roc_ctx->chan_freq, + roc_ctx->tx_ctx, roc_ctx->chan, roc_ctx->phy_mode, roc_ctx->duration, roc_ctx->roc_type, roc_ctx->roc_state); @@ -816,12 +808,10 @@ QDF_STATUS p2p_process_cleanup_roc_queue( roc_ctx = qdf_container_of(p_node, struct p2p_roc_context, node); - p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, " - "scan_id:%d, tx ctx:%pK, freq:%d, phy_mode:%d, " - "duration:%d, roc_type:%d, roc_state:%d", + p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d, tx ctx:%pK, chan:%d, phy_mode:%d, duration:%d, roc_type:%d, roc_state:%d", roc_ctx->p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, roc_ctx->scan_id, - roc_ctx->tx_ctx, roc_ctx->chan_freq, + roc_ctx->tx_ctx, roc_ctx->chan, roc_ctx->phy_mode, roc_ctx->duration, roc_ctx->roc_type, roc_ctx->roc_state); status = qdf_list_peek_next(&p2p_soc_obj->roc_q, @@ -846,11 +836,9 @@ QDF_STATUS p2p_process_cleanup_roc_queue( roc_ctx = qdf_container_of(p_node, struct p2p_roc_context, node); - p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, " - "scan_id:%d, tx ctx:%pK, freq:%d, phy_mode:%d, " - "duration:%d, roc_type:%d, roc_state:%d", + p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d, tx ctx:%pK, chan:%d, phy_mode:%d, duration:%d, roc_type:%d, roc_state:%d", roc_ctx->p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, - roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan_freq, + roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan, roc_ctx->phy_mode, roc_ctx->duration, roc_ctx->roc_type, roc_ctx->roc_state); @@ -883,13 +871,11 @@ QDF_STATUS p2p_process_roc_req(struct p2p_roc_context *roc_ctx) p2p_soc_obj = roc_ctx->p2p_soc_obj; - p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d, " - "tx_ctx:%pK, freq:%d, phy_mode:%d, duration:%d, " - "roc_type:%d, roc_state:%d", - p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, - roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan_freq, - roc_ctx->phy_mode, roc_ctx->duration, - roc_ctx->roc_type, roc_ctx->roc_state); + p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d, tx_ctx:%pK, chan:%d, phy_mode:%d, duration:%d, roc_type:%d, roc_state:%d", + p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, + roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan, + roc_ctx->phy_mode, roc_ctx->duration, + roc_ctx->roc_type, roc_ctx->roc_state); status = qdf_list_insert_back(&p2p_soc_obj->roc_q, &roc_ctx->node); diff --git a/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_roc.h b/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_roc.h index b800b20174b4..143e01726a8f 100644 --- a/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_roc.h +++ b/drivers/staging/qcacld-3.0/components/p2p/core/src/wlan_p2p_roc.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. - * Copyright (c) 2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -81,7 +81,7 @@ enum roc_state { * @vdev_id: Vdev id on which this request has come * @scan_id: Scan id given by scan component for this roc req * @tx_ctx: TX context if this ROC is for tx MGMT - * @chan_freq: Chan frequency for which this RoC has been requested + * @chan: Chan for which this RoC has been requested * @phy_mode: PHY mode * @duration: Duration for the RoC * @roc_type: RoC type User requested or internal @@ -95,7 +95,7 @@ struct p2p_roc_context { uint32_t vdev_id; uint32_t scan_id; void *tx_ctx; - qdf_freq_t chan_freq; + uint8_t chan; uint8_t phy_mode; uint32_t duration; enum roc_type roc_type; @@ -165,9 +165,9 @@ struct p2p_roc_context *p2p_find_roc_by_tx_ctx( struct p2p_soc_priv_obj *p2p_soc_obj, uint64_t cookie); /** - * p2p_find_roc_by_chan_freq() - Find out roc context by channel + * p2p_find_roc_by_chan() - Find out roc context by channel * @p2p_soc_obj: p2p psoc private object - * @chan_freq: channel frequency of the ROC + * @chan: channel of the ROC * * This function finds out roc context by channel from p2p psoc * private object @@ -175,8 +175,8 @@ struct p2p_roc_context *p2p_find_roc_by_tx_ctx( * Return: Pointer to roc context - success * NULL - failure */ -struct p2p_roc_context *p2p_find_roc_by_chan_freq( - struct p2p_soc_priv_obj *p2p_soc_obj, qdf_freq_t chan_freq); +struct p2p_roc_context *p2p_find_roc_by_chan( + struct p2p_soc_priv_obj *p2p_soc_obj, uint8_t chan); /** * p2p_restart_roc_timer() - Restarts roc timer diff --git a/drivers/staging/qcacld-3.0/components/p2p/dispatcher/inc/wlan_p2p_public_struct.h b/drivers/staging/qcacld-3.0/components/p2p/dispatcher/inc/wlan_p2p_public_struct.h index 060f0df3ba8b..33fd71c70b40 100644 --- a/drivers/staging/qcacld-3.0/components/p2p/dispatcher/inc/wlan_p2p_public_struct.h +++ b/drivers/staging/qcacld-3.0/components/p2p/dispatcher/inc/wlan_p2p_public_struct.h @@ -1,6 +1,5 @@ /* * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. - * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -62,13 +61,13 @@ struct p2p_ps_params { /** * struct p2p_roc_req - P2P roc request * @vdev_id: Vdev id on which this request has come - * @chan_freq: Chan frequency for which this RoC has been requested + * @chan: Chan for which this RoC has been requested * @phy_mode: PHY mode * @duration: Duration for the RoC */ struct p2p_roc_req { uint32_t vdev_id; - qdf_freq_t chan_freq; + uint32_t chan; uint32_t phy_mode; uint32_t duration; }; @@ -90,14 +89,14 @@ enum p2p_roc_event { * @vdev_id: Vdev id * @roc_event: RoC event * @cookie: Cookie which is given to supplicant for this roc req - * @chan_freq: Chan frequency for which this RoC has been requested + * @chan: Chan for which this RoC has been requested * @duration: Duration for the RoC */ struct p2p_event { uint32_t vdev_id; enum p2p_roc_event roc_event; uint64_t cookie; - qdf_freq_t chan_freq; + uint32_t chan; uint32_t duration; }; @@ -138,7 +137,7 @@ struct p2p_tx_cnf { /** * struct p2p_mgmt_tx - p2p mgmt tx structure * @vdev_id: Vdev id - * @chan_freq: Chan frequency for which this RoC has been requested + * @chan: Chan for which this RoC has been requested * @wait: Duration for the RoC * @len: Length of tx buffer * @no_cck: Required cck or not @@ -148,7 +147,7 @@ struct p2p_tx_cnf { */ struct p2p_mgmt_tx { uint32_t vdev_id; - qdf_freq_t chan_freq; + uint32_t chan; uint32_t wait; uint32_t len; uint32_t no_cck; diff --git a/drivers/staging/qcacld-3.0/components/p2p/dispatcher/src/wlan_p2p_ucfg_api.c b/drivers/staging/qcacld-3.0/components/p2p/dispatcher/src/wlan_p2p_ucfg_api.c index 3b862f62d3de..50444dc6d8e4 100644 --- a/drivers/staging/qcacld-3.0/components/p2p/dispatcher/src/wlan_p2p_ucfg_api.c +++ b/drivers/staging/qcacld-3.0/components/p2p/dispatcher/src/wlan_p2p_ucfg_api.c @@ -1,6 +1,5 @@ /* * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -119,9 +118,9 @@ QDF_STATUS ucfg_p2p_roc_req(struct wlan_objmgr_psoc *soc, QDF_STATUS status; int32_t id; - p2p_debug("soc:%pK, vdev_id:%d, chanfreq:%d, phy_mode:%d, duration:%d", - soc, roc_req->vdev_id, roc_req->chan_freq, - roc_req->phy_mode, roc_req->duration); + p2p_debug("soc:%pK, vdev_id:%d, chan:%d, phy_mode:%d, duration:%d", + soc, roc_req->vdev_id, roc_req->chan, + roc_req->phy_mode, roc_req->duration); if (!soc) { p2p_err("psoc context passed is NULL"); @@ -149,7 +148,7 @@ QDF_STATUS ucfg_p2p_roc_req(struct wlan_objmgr_psoc *soc, *cookie = (uint64_t)id; roc_ctx->p2p_soc_obj = p2p_soc_obj; roc_ctx->vdev_id = roc_req->vdev_id; - roc_ctx->chan_freq = roc_req->chan_freq; + roc_ctx->chan = roc_req->chan; roc_ctx->phy_mode = roc_req->phy_mode; roc_ctx->duration = roc_req->duration; roc_ctx->roc_state = ROC_STATE_IDLE; @@ -325,11 +324,10 @@ QDF_STATUS ucfg_p2p_mgmt_tx(struct wlan_objmgr_psoc *soc, QDF_STATUS status; int32_t id; - p2p_debug("soc:%pK, vdev_id:%d, freq:%d, wait:%d, buf_len:%d," - " cck:%d, no ack:%d, off chan:%d", - soc, mgmt_frm->vdev_id, mgmt_frm->chan_freq, - mgmt_frm->wait, mgmt_frm->len, mgmt_frm->no_cck, - mgmt_frm->dont_wait_for_ack, mgmt_frm->off_chan); + p2p_debug("soc:%pK, vdev_id:%d, chan:%d, wait:%d, buf_len:%d, cck:%d, no ack:%d, off chan:%d", + soc, mgmt_frm->vdev_id, mgmt_frm->chan, + mgmt_frm->wait, mgmt_frm->len, mgmt_frm->no_cck, + mgmt_frm->dont_wait_for_ack, mgmt_frm->off_chan); if (!soc) { p2p_err("psoc context passed is NULL"); @@ -363,7 +361,7 @@ QDF_STATUS ucfg_p2p_mgmt_tx(struct wlan_objmgr_psoc *soc, *cookie = (uint64_t)id; tx_action->p2p_soc_obj = p2p_soc_obj; tx_action->vdev_id = mgmt_frm->vdev_id; - tx_action->chan_freq = mgmt_frm->chan_freq; + tx_action->chan = mgmt_frm->chan; tx_action->duration = mgmt_frm->wait; tx_action->buf_len = mgmt_frm->len; tx_action->no_cck = mgmt_frm->no_cck; diff --git a/drivers/staging/qcacld-3.0/components/target_if/connection_mgr/src/target_if_cm_roam_offload.c b/drivers/staging/qcacld-3.0/components/target_if/connection_mgr/src/target_if_cm_roam_offload.c index 970d0429f1b7..46e1cab26484 100644 --- a/drivers/staging/qcacld-3.0/components/target_if/connection_mgr/src/target_if_cm_roam_offload.c +++ b/drivers/staging/qcacld-3.0/components/target_if/connection_mgr/src/target_if_cm_roam_offload.c @@ -1,7 +1,6 @@ /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -265,41 +264,6 @@ target_if_cm_roam_rssi_diff_6ghz(struct wlan_objmgr_vdev *vdev, return status; } -/** - * target_if_cm_roam_rssi_delta_6ghz_to_non_6ghz() - Sends the roam RSSI - * diff value to the FW. This value is used to determine how much better - * the RSSI of the new/roamable non-6 GHz AP must be for roaming. - * - * @vdev: vdev object - * @roam_rssi_delta_6ghz_to_non_6ghz: RSSI diff value to be used for roaming to - * Non 6 GHz AP - * - * Return: QDF_STATUS - */ -static QDF_STATUS -target_if_cm_roam_rssi_delta_6ghz_to_non_6ghz(struct wlan_objmgr_vdev *vdev, - uint8_t roam_rssi_delta_6ghz_to_non_6ghz) -{ - QDF_STATUS status = QDF_STATUS_E_FAILURE; - uint8_t vdev_id; - wmi_unified_t wmi_handle; - - wmi_handle = target_if_cm_roam_get_wmi_handle_from_vdev(vdev); - if (!wmi_handle) - return status; - - vdev_id = wlan_vdev_get_id(vdev); - status = target_if_roam_set_param( - wmi_handle, vdev_id, - WMI_ROAM_PARAM_ROAM_RSSI_PENALTY_FOR_NON_6GHZ_CAND_AP, - roam_rssi_delta_6ghz_to_non_6ghz); - - if (QDF_IS_STATUS_ERROR(status)) - target_if_err("Failed to set WMI_ROAM_PARAM_ROAM_RSSI_PENALTY_FOR_NON_6GHZ_CAND_AP"); - - return status; -} - static QDF_STATUS target_if_cm_roam_scan_offload_rssi_thresh( wmi_unified_t wmi_handle, @@ -403,13 +367,6 @@ target_if_cm_roam_rssi_diff_6ghz(struct wlan_objmgr_vdev *vdev, return QDF_STATUS_E_NOSUPPORT; } -static QDF_STATUS -target_if_cm_roam_rssi_delta_6ghz_to_non_6ghz(struct wlan_objmgr_vdev *vdev, - uint8_t roam_rssi_diff_6ghz) -{ - return QDF_STATUS_E_NOSUPPORT; -} - static inline void target_if_check_hi_rssi_5ghz_support( wmi_unified_t wmi_handle, @@ -1319,9 +1276,6 @@ target_if_cm_roam_send_start(struct wlan_objmgr_vdev *vdev, if (req->wlan_roam_rssi_diff_6ghz) target_if_cm_roam_rssi_diff_6ghz(vdev, req->wlan_roam_rssi_diff_6ghz); - if (req->wlan_roam_rssi_delta_6ghz_to_non_6ghz) - target_if_cm_roam_rssi_delta_6ghz_to_non_6ghz( - vdev, req->wlan_roam_rssi_delta_6ghz_to_non_6ghz); /* add other wmi commands */ end: @@ -1562,10 +1516,6 @@ target_if_cm_roam_send_update_config(struct wlan_objmgr_vdev *vdev, if (req->wlan_roam_rssi_diff_6ghz) target_if_cm_roam_rssi_diff_6ghz( vdev, req->wlan_roam_rssi_diff_6ghz); - - if (req->wlan_roam_rssi_delta_6ghz_to_non_6ghz) - target_if_cm_roam_rssi_delta_6ghz_to_non_6ghz( - vdev, req->wlan_roam_rssi_delta_6ghz_to_non_6ghz); } end: return status; diff --git a/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/core/src/wlan_cm_roam_offload.c b/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/core/src/wlan_cm_roam_offload.c index 8f5e5272d77c..647f5e0229b2 100644 --- a/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/core/src/wlan_cm_roam_offload.c +++ b/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/core/src/wlan_cm_roam_offload.c @@ -629,10 +629,6 @@ cm_roam_start_req(struct wlan_objmgr_psoc *psoc, uint8_t vdev_id, wlan_cm_roam_cfg_get_value(psoc, vdev_id, ROAM_RSSI_DIFF_6GHZ, &temp); start_req->wlan_roam_rssi_diff_6ghz = temp.uint_value; - wlan_cm_roam_cfg_get_value(psoc, vdev_id, - ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ, &temp); - start_req->wlan_roam_rssi_delta_6ghz_to_non_6ghz = temp.uint_value; - status = wlan_cm_tgt_send_roam_start_req(psoc, vdev_id, start_req); if (QDF_IS_STATUS_ERROR(status)) mlme_debug("fail to send roam start"); @@ -695,10 +691,6 @@ cm_roam_update_config_req(struct wlan_objmgr_psoc *psoc, uint8_t vdev_id, wlan_cm_roam_cfg_get_value(psoc, vdev_id, ROAM_RSSI_DIFF_6GHZ, &temp); update_req->wlan_roam_rssi_diff_6ghz = temp.uint_value; - wlan_cm_roam_cfg_get_value(psoc, vdev_id, - ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ, &temp); - update_req->wlan_roam_rssi_delta_6ghz_to_non_6ghz = temp.uint_value; - status = wlan_cm_tgt_send_roam_update_req(psoc, vdev_id, update_req); if (QDF_IS_STATUS_ERROR(status)) mlme_debug("fail to send update config"); diff --git a/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/dispatcher/inc/wlan_cm_roam_public_struct.h b/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/dispatcher/inc/wlan_cm_roam_public_struct.h index b4d17e9c04fe..9a027bc6a11f 100644 --- a/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/dispatcher/inc/wlan_cm_roam_public_struct.h +++ b/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/dispatcher/inc/wlan_cm_roam_public_struct.h @@ -1,7 +1,6 @@ /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -121,14 +120,12 @@ * @BEACON_RSSI_WEIGHT: Beacon Rssi weight parameter * @HI_RSSI_DELAY_BTW_SCANS: High Rssi delay between scans * @ROAM_RSSI_DIFF_6GHZ: roam rssi diff for 6 GHz AP - * @ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ: roam rssi diff for Non 6 GHz AP */ enum roam_cfg_param { RSSI_CHANGE_THRESHOLD, BEACON_RSSI_WEIGHT, HI_RSSI_DELAY_BTW_SCANS, ROAM_RSSI_DIFF_6GHZ, - ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ, }; /** @@ -1209,8 +1206,6 @@ enum roam_rt_stats_params { * scan only on prior discovery of any 6 GHz support in the environment. * @wlan_roam_rssi_diff_6ghz: This value is used as to how better the RSSI of * the new/roamable 6GHz AP should be for roaming. - * @wlan_roam_rssi_delta_6ghz_to_non_6ghz: This value is used as to how better - * the RSSI of the new/roamable non 6GHz AP should be for roaming. */ struct wlan_roam_start_config { struct wlan_roam_offload_scan_rssi_params rssi_params; @@ -1234,7 +1229,6 @@ struct wlan_roam_start_config { uint8_t wlan_exclude_rm_partial_scan_freq; uint8_t wlan_roam_full_scan_6ghz_on_disc; uint8_t wlan_roam_rssi_diff_6ghz; - uint8_t wlan_roam_rssi_delta_6ghz_to_non_6ghz; /* other wmi cmd structures */ }; @@ -1287,8 +1281,6 @@ struct wlan_roam_stop_config { * scan only on prior discovery of any 6 GHz support in the environment. * @wlan_roam_rssi_diff_6ghz: This value is used as to how better the RSSI of * the new/roamable 6GHz AP should be for roaming. - * @wlan_roam_rssi_delta_6ghz_to_non_6ghz: This value is used as to how better - * the RSSI of the new/roamable non 6GHz AP should be for roaming. */ struct wlan_roam_update_config { struct wlan_roam_beacon_miss_cnt beacon_miss_cnt; @@ -1307,7 +1299,6 @@ struct wlan_roam_update_config { uint8_t wlan_exclude_rm_partial_scan_freq; uint8_t wlan_roam_full_scan_6ghz_on_disc; uint8_t wlan_roam_rssi_diff_6ghz; - uint8_t wlan_roam_rssi_delta_6ghz_to_non_6ghz; }; #if defined(WLAN_FEATURE_HOST_ROAM) || defined(WLAN_FEATURE_ROAM_OFFLOAD) @@ -1531,8 +1522,6 @@ enum roam_fail_params { * @roam_invoke_fail_reason: One of reason id from enum * wmi_roam_invoke_status_error in case of forced roam * @roam_rssi_diff_6ghz: roam rssi diff for 6 GHz AP - * @roam_rssi_delta_6ghz_to_non_6ghz: RSSI Delta value to be used for roaming - * from 6 GHz to Non 6GHz AP. */ struct wlan_cm_rso_configs { uint8_t rescan_rssi_delta; @@ -1543,7 +1532,6 @@ struct wlan_cm_rso_configs { uint32_t roam_trigger_reason; uint32_t roam_invoke_fail_reason; uint8_t roam_rssi_diff_6ghz; - uint8_t roam_rssi_delta_6ghz_to_non_6ghz; }; /** diff --git a/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/dispatcher/src/wlan_cm_roam_api.c b/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/dispatcher/src/wlan_cm_roam_api.c index 8ad4cef25e38..53fce94e29c3 100644 --- a/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/dispatcher/src/wlan_cm_roam_api.c +++ b/drivers/staging/qcacld-3.0/components/umac/mlme/connection_mgr/dispatcher/src/wlan_cm_roam_api.c @@ -1,7 +1,6 @@ /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -520,10 +519,6 @@ QDF_STATUS wlan_cm_roam_cfg_get_value(struct wlan_objmgr_psoc *psoc, case ROAM_RSSI_DIFF_6GHZ: dst_config->uint_value = src_config->roam_rssi_diff_6ghz; break; - case ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ: - dst_config->uint_value = - src_config->roam_rssi_delta_6ghz_to_non_6ghz; - break; default: mlme_err("Invalid roam config requested:%d", roam_cfg_type); status = QDF_STATUS_E_FAILURE; @@ -573,10 +568,6 @@ wlan_cm_roam_cfg_set_value(struct wlan_objmgr_psoc *psoc, uint8_t vdev_id, case ROAM_RSSI_DIFF_6GHZ: dst_config->roam_rssi_diff_6ghz = src_config->uint_value; break; - case ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ: - dst_config->roam_rssi_delta_6ghz_to_non_6ghz = - src_config->uint_value; - break; default: mlme_err("Invalid roam config requested:%d", roam_cfg_type); status = QDF_STATUS_E_FAILURE; diff --git a/drivers/staging/qcacld-3.0/core/dp/htt/htt_h2t.c b/drivers/staging/qcacld-3.0/core/dp/htt/htt_h2t.c index 3038b831a3e5..e1bed656e5ec 100644 --- a/drivers/staging/qcacld-3.0/core/dp/htt/htt_h2t.c +++ b/drivers/staging/qcacld-3.0/core/dp/htt/htt_h2t.c @@ -629,7 +629,7 @@ htt_h2t_rx_ring_cfg_msg_hl(struct htt_pdev_t *pdev) pkt = htt_htc_pkt_alloc(pdev); if (!pkt) - return QDF_STATUS_E_FAILURE; /* failure */ + return A_ERROR; /* failure */ /* * show that this is not a tx frame download @@ -645,7 +645,7 @@ htt_h2t_rx_ring_cfg_msg_hl(struct htt_pdev_t *pdev) HTC_HEADER_LEN + HTC_HDR_ALIGNMENT_PADDING, 4, true); if (!msg) { htt_htc_pkt_free(pdev, pkt); - return QDF_STATUS_E_FAILURE; /* failure */ + return A_ERROR; /* failure */ } /* * Set the length of the message. diff --git a/drivers/staging/qcacld-3.0/core/dp/txrx3.0/dp_fisa_rx.c b/drivers/staging/qcacld-3.0/core/dp/txrx3.0/dp_fisa_rx.c index 835f795e7736..d0d84e40a9ce 100644 --- a/drivers/staging/qcacld-3.0/core/dp/txrx3.0/dp_fisa_rx.c +++ b/drivers/staging/qcacld-3.0/core/dp/txrx3.0/dp_fisa_rx.c @@ -1677,33 +1677,15 @@ static int dp_add_nbuf_to_fisa_flow(struct dp_rx_fst *fisa_hdl, fse_metadata = hal_rx_msdu_fse_metadata_get(hal_soc_hdl, rx_tlv_hdr); cce_match = hal_rx_msdu_cce_match_get(rx_tlv_hdr); - /* - * For two cases the fse_metadata will not match the metadata - * from the fisa_flow_table entry - * 1) Flow has been evicted (lru deletion), and this packet is - * one of the few packets pending in the rx ring from the prev - * flow - * 2) HW flow table match fails for some packets in the - * currently active flow. - */ - if (cce_match) { + if (cce_match || (fisa_hdl->del_flow_count && + fse_metadata != fisa_flow->metadata)) { dp_rx_fisa_release_ft_lock(fisa_hdl, napi_id); - DP_STATS_INC(fisa_hdl, reo_mismatch.allow_cce_match, - 1); - return FISA_AGGR_NOT_ELIGIBLE; - } - - if (fse_metadata != fisa_flow->metadata) { - dp_rx_fisa_release_ft_lock(fisa_hdl, napi_id); - DP_STATS_INC(fisa_hdl, - reo_mismatch.allow_fse_metdata_mismatch, - 1); return FISA_AGGR_NOT_ELIGIBLE; } dp_err("REO id mismatch flow: %pK napi_id: %u nbuf: %pK reo_id: %u", fisa_flow, fisa_flow->napi_id, nbuf, napi_id); - DP_STATS_INC(fisa_hdl, reo_mismatch.allow_non_aggr, 1); + DP_STATS_INC(fisa_hdl, reo_mismatch, 1); QDF_BUG(0); dp_rx_fisa_release_ft_lock(fisa_hdl, napi_id); return FISA_AGGR_NOT_ELIGIBLE; diff --git a/drivers/staging/qcacld-3.0/core/dp/txrx3.0/dp_rx_fst.c b/drivers/staging/qcacld-3.0/core/dp/txrx3.0/dp_rx_fst.c index 4d88045dedf1..023729a53bf1 100644 --- a/drivers/staging/qcacld-3.0/core/dp/txrx3.0/dp_rx_fst.c +++ b/drivers/staging/qcacld-3.0/core/dp/txrx3.0/dp_rx_fst.c @@ -63,24 +63,6 @@ void dp_rx_dump_fisa_table(struct dp_soc *soc) } } -void dp_print_fisa_stats(struct dp_soc *soc) -{ - struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx; - struct dp_rx_fst *fst = soc->rx_fst; - - /* Check if it is enabled in the INI */ - if (!wlan_cfg_is_rx_fisa_enabled(cfg)) - return; - - dp_info("invalid flow index: %u", fst->stats.invalid_flow_index); - dp_info("reo_mismatch: cce_match: %u", - fst->stats.reo_mismatch.allow_cce_match); - dp_info("reo_mismatch: allow_fse_metdata_mismatch: %u", - fst->stats.reo_mismatch.allow_fse_metdata_mismatch); - dp_info("reo_mismatch: allow_non_aggr: %u", - fst->stats.reo_mismatch.allow_non_aggr); -} - /** * dp_rx_flow_send_htt_operation_cmd() - Invalidate FSE cache on FT change * @pdev: handle to DP pdev diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c index 8166bd994710..5ffa66dabe3d 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c @@ -1718,7 +1718,7 @@ static const struct nl80211_vendor_cmd_info wlan_hdd_cfg80211_vendor_events[] = }; /** - * __is_driver_dfs_capable() - get driver DFS offload capability + * __is_driver_dfs_capable() - get driver DFS capability * @wiphy: pointer to wireless wiphy structure. * @wdev: pointer to wireless_dev structure. * @data: Pointer to the data to be passed via vendor interface @@ -17744,7 +17744,7 @@ void wlan_hdd_update_wiphy(struct hdd_context *hdd_ctx) { int value; bool fils_enabled, mac_spoofing_enabled; - bool is_oce_sta_enabled = false; + bool dfs_master_capable = true, is_oce_sta_enabled = false; QDF_STATUS status; struct wiphy *wiphy = hdd_ctx->wiphy; uint8_t allow_mcc_go_diff_bi = 0, enable_mcc = 0; @@ -17769,7 +17769,11 @@ void wlan_hdd_update_wiphy(struct hdd_context *hdd_ctx) if (fils_enabled) wlan_hdd_cfg80211_set_wiphy_fils_feature(wiphy); - wlan_hdd_cfg80211_set_dfs_offload_feature(wiphy); + status = ucfg_mlme_get_dfs_master_capability(hdd_ctx->psoc, + &dfs_master_capable); + if (QDF_IS_STATUS_SUCCESS(status) && dfs_master_capable) + wlan_hdd_cfg80211_set_dfs_offload_feature(wiphy); + status = ucfg_mlme_get_bigtk_support(hdd_ctx->psoc, &is_bigtk_supported); diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_hostapd.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_hostapd.c index 76a1a5228125..80659541d94a 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_hostapd.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_hostapd.c @@ -5244,7 +5244,6 @@ int wlan_hdd_cfg80211_start_bss(struct hdd_adapter *adapter, bool deliver_start_evt = true; struct s_ext_cap *p_ext_cap; enum reg_phymode reg_phy_mode, updated_phy_mode; - bool dfs_master_capable; hdd_enter(); @@ -5788,24 +5787,6 @@ int wlan_hdd_cfg80211_start_bss(struct hdd_adapter *adapter, config->ch_width_orig = CH_WIDTH_20MHZ; } - status = ucfg_mlme_get_dfs_master_capability(hdd_ctx->psoc, - &dfs_master_capable); - if (QDF_IS_STATUS_ERROR(status)) { - hdd_err("Failed to get dfs master capable"); - ret = -EINVAL; - goto error; - } - - if (!dfs_master_capable && - policy_mgr_is_bonded_chan_dfs(hdd_ctx->psoc, - config->ch_width_orig, - config->ch_params.mhz_freq_seg1, - config->chan_freq)) { - hdd_err("Failed to bringup SAP; Atleast one bonded channel is DFS"); - ret = -EINVAL; - goto error; - } - if (wlan_hdd_setup_driver_overrides(adapter)) { ret = -EINVAL; goto error; diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_p2p.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_p2p.c index d8aee3c9ee21..4743ce81ba2a 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_p2p.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_p2p.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -286,16 +286,15 @@ wlan_hdd_validate_and_override_offchan(struct hdd_adapter *adapter, struct ieee80211_channel *chan, bool *offchan) { - qdf_freq_t home_ch_freq; + uint8_t home_ch; if (!offchan || !chan || !(*offchan)) return; - home_ch_freq = hdd_get_adapter_home_channel(adapter); + home_ch = hdd_get_adapter_home_channel(adapter); - if (chan->center_freq == home_ch_freq) { - hdd_debug("override offchan to 0 at home channel %d", - home_ch_freq); + if (ieee80211_frequency_to_channel(chan->center_freq) == home_ch) { + hdd_debug("override offchan to 0 at home channel %d", home_ch); *offchan = false; } } diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_stats.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_stats.c index 67f104883d23..82e357d2e799 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_stats.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_stats.c @@ -3917,8 +3917,7 @@ hdd_get_roam_rt_stats_event_len(struct mlme_roam_debug_info *roam_stats) len += nla_total_size(sizeof(uint8_t)); if (roam_stats->scan.present) { - if (roam_stats->scan.num_chan && - roam_stats->scan.type == ROAM_STATS_SCAN_TYPE_PARTIAL) + if (roam_stats->scan.num_chan && !roam_stats->scan.type) for (i = 0; i < roam_stats->scan.num_chan;) i++; @@ -3991,8 +3990,7 @@ roam_rt_stats_fill_scan_freq(struct sk_buff *vendor_event, kfree_skb(vendor_event); return; } - if (roam_stats->scan.num_chan && - roam_stats->scan.type == ROAM_STATS_SCAN_TYPE_PARTIAL) { + if (roam_stats->scan.num_chan && !roam_stats->scan.type) { for (i = 0; i < roam_stats->scan.num_chan; i++) { if (nla_put_u32(vendor_event, i, roam_stats->scan.chan_freq[i])) { diff --git a/drivers/staging/qcacld-3.0/core/mac/inc/qwlan_version.h b/drivers/staging/qcacld-3.0/core/mac/inc/qwlan_version.h index 500f1f71f75c..c8f76c9a8572 100644 --- a/drivers/staging/qcacld-3.0/core/mac/inc/qwlan_version.h +++ b/drivers/staging/qcacld-3.0/core/mac/inc/qwlan_version.h @@ -32,9 +32,9 @@ #define QWLAN_VERSION_MAJOR 2 #define QWLAN_VERSION_MINOR 0 #define QWLAN_VERSION_PATCH 8 -#define QWLAN_VERSION_EXTRA "G" -#define QWLAN_VERSION_BUILD 35 +#define QWLAN_VERSION_EXTRA "Z" +#define QWLAN_VERSION_BUILD 34 -#define QWLAN_VERSIONSTR "2.0.8.35G" +#define QWLAN_VERSIONSTR "2.0.8.34Z" #endif /* QWLAN_VERSION_H */ diff --git a/drivers/staging/qcacld-3.0/core/mac/inc/sir_api.h b/drivers/staging/qcacld-3.0/core/mac/inc/sir_api.h index d520ba3f3525..3bdcdf7f390a 100644 --- a/drivers/staging/qcacld-3.0/core/mac/inc/sir_api.h +++ b/drivers/staging/qcacld-3.0/core/mac/inc/sir_api.h @@ -786,7 +786,6 @@ struct bss_description { #if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) uint32_t is_single_pmk; #endif - uint16_t neg_rsn_caps; /* Please keep the structure 4 bytes aligned above the ieFields */ uint32_t ieFields[1]; }; diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_session.h b/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_session.h index 25f2f90143c5..5488a180a145 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_session.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_session.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -140,7 +140,6 @@ struct obss_detection_cfg { * @prev_auth_seq_num: Sequence number of previously received auth frame to * detect duplicate frames. * @prev_auth_mac_addr: mac_addr of the sta correspond to @prev_auth_seq_num - * @cal_tpc_post_csa: Recalculate tx power power csa */ struct pe_session { /* To check session table is in use or free */ @@ -581,7 +580,6 @@ struct pe_session { uint32_t dfs_regdomain; uint8_t ap_defined_power_type_6g; uint8_t best_6g_power_type; - bool cal_tpc_post_csa; }; /*------------------------------------------------------------------------- diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_api.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_api.c index 2e0f0511dc89..80ee8867c140 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_api.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_api.c @@ -2631,10 +2631,6 @@ pe_roam_synch_callback(struct mac_context *mac_ctx, lim_fill_ft_session(mac_ctx, bss_desc, ft_session_ptr, session_ptr, roam_sync_ind_ptr->phy_mode); pe_update_crypto_params(mac_ctx, ft_session_ptr, roam_sync_ind_ptr); - - /* Reset the SPMK global cache */ - wlan_mlme_set_sae_single_pmk_bss_cap(mac_ctx->psoc, - ft_session_ptr->vdev_id, false); /* Next routine may update nss based on dot11Mode */ lim_ft_prepare_add_bss_req(mac_ctx, ft_session_ptr, bss_desc); if (session_ptr->is11Rconnection) diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_sme_req_messages.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_sme_req_messages.c index f9eb195526dd..49113c9529e4 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_sme_req_messages.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_sme_req_messages.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1604,14 +1604,6 @@ __lim_process_sme_join_req(struct mac_context *mac_ctx, void *msg_buf) session->connected_akm = sme_join_req->akm; session->is_adaptive_11r_connection = sme_join_req->is_adaptive_11r_connection; - /* Reset the SPMK global cache for non-SAE connection */ - if (session->connected_akm != ANI_AKM_TYPE_SAE) { - wlan_mlme_set_sae_single_pmk_bss_cap(mac_ctx->psoc, - session->vdev_id, - false); - wlan_mlme_clear_sae_single_pmk_info(session->vdev, - NULL); - } #ifdef FEATURE_WLAN_ESE session->isESEconnection = sme_join_req->isESEconnection; #endif @@ -1840,7 +1832,7 @@ __lim_process_sme_join_req(struct mac_context *mac_ctx, void *msg_buf) session->spectrumMgtEnabled = true; session->isOSENConnection = sme_join_req->isOSENConnection; - pe_debug("Freq %d width %d freq0 %d freq1 %d, Smps %d: mode %d action %d, nss 1x1 %d vdev_nss %d nss %d cbMode %d dot11mode %d subfer %d subfee %d csn %d is_cisco %d akm %d", + pe_debug("Freq %d width %d freq0 %d freq1 %d, Smps %d: mode %d action %d, nss 1x1 %d vdev_nss %d nss %d cbMode %d dot11mode %d subfer %d subfee %d csn %d is_cisco %d", session->curr_op_freq, session->ch_width, session->ch_center_freq_seg0, session->ch_center_freq_seg1, @@ -1851,7 +1843,7 @@ __lim_process_sme_join_req(struct mac_context *mac_ctx, void *msg_buf) session->vht_config.su_beam_former, session->vht_config.su_beam_formee, session->vht_config.csnof_beamformer_antSup, - session->isCiscoVendorAP, session->connected_akm); + session->isCiscoVendorAP); /* Issue LIM_MLM_JOIN_REQ to MLM */ status = lim_send_join_req(session, mlm_join_req); @@ -1911,8 +1903,6 @@ void lim_parse_tpe_ie(struct mac_context *mac, struct pe_session *session, uint16_t bw_val, ch_width; qdf_freq_t curr_op_freq, curr_freq; enum reg_6g_client_type client_mobility_type; - enum reg_6g_ap_type ap_power_type_6g; - uint16_t reg_max = 0, psd_power = 0; struct ch_params ch_params = {0}; tDot11fIEtransmit_power_env single_tpe; /* @@ -1989,25 +1979,6 @@ void lim_parse_tpe_ie(struct mac_context *mac, struct pe_session *session, curr_op_freq = session->curr_op_freq; bw_val = wlan_reg_get_bw_value(session->ch_width); - if (psd_set) { - if (wlan_reg_is_6ghz_chan_freq(curr_op_freq)) { - ap_power_type_6g = session->best_6g_power_type; - - wlan_reg_get_client_power_for_connecting_ap( - mac->pdev, ap_power_type_6g, - curr_op_freq, true, ®_max, &psd_power); - - /* If reg rules don't support psd power, ignore PSD - * TPE IE - */ - if (!psd_power) { - pe_debug_rl("reg rule doesn't support psd for %d ap type %d", - curr_op_freq, ap_power_type_6g); - psd_set = false; - } - } - } - if (non_psd_set && !psd_set) { single_tpe = tpe_ies[non_psd_index]; vdev_mlme->reg_tpc_obj.is_psd_power = false; @@ -2088,9 +2059,6 @@ void lim_parse_tpe_ie(struct mac_context *mac, struct pe_session *session, single_tpe = tpe_ies[non_psd_index]; vdev_mlme->reg_tpc_obj.eirp_power = single_tpe.tx_power[single_tpe.max_tx_pwr_count]; - pe_debug("eirp_power %d", vdev_mlme->reg_tpc_obj.eirp_power); - if (!psd_set) - vdev_mlme->reg_tpc_obj.is_psd_power = false; } } @@ -2234,6 +2202,7 @@ void lim_calculate_tpc(struct mac_context *mac, skip_tpe = wlan_mlme_skip_tpe(mac->psoc); } else { is_6ghz_freq = true; + is_psd_power = wlan_reg_is_6g_psd_power(mac->pdev); if (LIM_IS_STA_ROLE(session)) ap_power_type_6g = session->best_6g_power_type; } @@ -2241,7 +2210,6 @@ void lim_calculate_tpc(struct mac_context *mac, if (mlme_obj->reg_tpc_obj.num_pwr_levels) { is_tpe_present = true; num_pwr_levels = mlme_obj->reg_tpc_obj.num_pwr_levels; - is_psd_power = mlme_obj->reg_tpc_obj.is_psd_power; } else { num_pwr_levels = lim_get_num_pwr_levels(is_psd_power, session->ch_width); @@ -2255,21 +2223,13 @@ void lim_calculate_tpc(struct mac_context *mac, ch_params.ch_width = CH_WIDTH_20MHZ; - for (i = 0; - i < num_pwr_levels && (ch_params.ch_width != CH_WIDTH_INVALID); - i++) { + for (i = 0; i < num_pwr_levels; i++) { if (is_tpe_present) { if (is_6ghz_freq) { - if (is_psd_power) { - wlan_reg_get_client_power_for_connecting_ap( - mac->pdev, ap_power_type_6g, - mlme_obj->reg_tpc_obj.frequency[i], - is_psd_power, ®_max, &psd_power); - } else { - wlan_reg_get_client_power_for_connecting_ap( - mac->pdev, ap_power_type_6g, oper_freq, - is_psd_power, ®_max, &psd_power); - } + wlan_reg_get_client_power_for_connecting_ap( + mac->pdev, ap_power_type_6g, + mlme_obj->reg_tpc_obj.frequency[i], + &is_psd_power, ®_max, &psd_power); } } else { /* center frequency calculation */ @@ -2281,18 +2241,18 @@ void lim_calculate_tpc(struct mac_context *mac, mac->pdev, oper_freq, 0, &ch_params); mlme_obj->reg_tpc_obj.frequency[i] = ch_params.mhz_freq_seg0; - if (ch_params.ch_width != CH_WIDTH_INVALID) - ch_params.ch_width = - get_next_higher_bw[ch_params.ch_width]; + ch_params.ch_width = + get_next_higher_bw[ch_params.ch_width]; } if (is_6ghz_freq) { if (LIM_IS_STA_ROLE(session)) { wlan_reg_get_client_power_for_connecting_ap (mac->pdev, ap_power_type_6g, mlme_obj->reg_tpc_obj.frequency[i], - is_psd_power, ®_max, &psd_power); + &is_psd_power, ®_max, &psd_power); } else { - wlan_reg_get_cur_6g_ap_pwr_type( + ap_power_type_6g = + wlan_reg_get_cur_6g_ap_pwr_type( mac->pdev, &ap_power_type_6g); wlan_reg_get_6g_chan_ap_power( @@ -2358,6 +2318,7 @@ void lim_calculate_tpc(struct mac_context *mac, } mlme_obj->reg_tpc_obj.num_pwr_levels = num_pwr_levels; + mlme_obj->reg_tpc_obj.is_psd_power = is_psd_power; mlme_obj->reg_tpc_obj.eirp_power = reg_max; mlme_obj->reg_tpc_obj.power_type_6g = ap_power_type_6g; @@ -6528,9 +6489,6 @@ static void lim_process_set_ie_req(struct mac_context *mac_ctx, uint32_t *msg_bu if (p_ext_cap->interworking_service) p_ext_cap->qos_map = 1; - if (wma_is_mbssid_enabled()) - p_ext_cap->multi_bssid = 1; - extra_ext_cap.num_bytes = lim_compute_ext_cap_ie_length(&extra_ext_cap); send_ie: diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_sme_rsp_messages.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_sme_rsp_messages.c index 639fac0c3c4f..8b6a073ea59e 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_sme_rsp_messages.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_sme_rsp_messages.c @@ -1,6 +1,5 @@ /* * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1885,7 +1884,6 @@ void lim_handle_csa_offload_msg(struct mac_context *mac_ctx, err: qdf_mem_free(csa_params); - session_entry->cal_tpc_post_csa = true; } /*-------------------------------------------------------------------------- diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_beacon_process.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_beacon_process.c index 8ffa424d5962..3c0914e6c71a 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_beacon_process.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_beacon_process.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -704,9 +704,8 @@ static void __sch_beacon_process_for_session(struct mac_context *mac_ctx, } if ((ap_constraint_change && local_constraint) || - (tpe_change && !skip_tpe) || session->cal_tpc_post_csa) { + (tpe_change && !skip_tpe)) { lim_calculate_tpc(mac_ctx, session); - session->cal_tpc_post_csa = false; if (tx_ops->set_tpc_power) tx_ops->set_tpc_power(mac_ctx->psoc, diff --git a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_roam.c b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_roam.c index cf719e8501a6..262b4f292c30 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_roam.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_roam.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -17422,8 +17422,6 @@ static void csr_cm_update_driver_assoc_ies( MIN_TX_PWR_CAP, MAX_TX_PWR_CAP}; uint8_t max_tx_pwr_cap = 0; uint8_t supp_chan_ie[DOT11F_IE_SUPPCHANNELS_MAX_LEN], supp_chan_ie_len; - struct s_ext_cap *extcap; - uint8_t *ext_cap_ie; static const uint8_t qcn_ie[] = {0x8C, 0xFD, 0xF0, 0x1, QCN_IE_VERSION_SUBATTR_ID, QCN_IE_VERSION_SUBATTR_DATA_LEN, @@ -17435,14 +17433,6 @@ static void csr_cm_update_driver_assoc_ies( qdf_mem_copy(rso_mode_cfg->assoc_ie, session->pAddIEAssoc, rso_mode_cfg->assoc_ie_length); - ext_cap_ie = (uint8_t *)wlan_get_ie_ptr_from_eid(WLAN_ELEMID_XCAPS, - rso_mode_cfg->assoc_ie, - rso_mode_cfg->assoc_ie_length); - if (ext_cap_ie && wma_is_mbssid_enabled()) { - extcap = (struct s_ext_cap *)&ext_cap_ie[2]; - extcap->multi_bssid = 1; - } - if (session->pConnectBssDesc) max_tx_pwr_cap = csr_get_cfg_max_tx_power( mac_ctx, @@ -21461,15 +21451,12 @@ csr_process_roam_sync_callback(struct mac_context *mac_ctx, mac_ctx->psoc); mac_ctx->sme.set_connection_info_cb(false); - if (roam_synch_data->pmk_len) { - mlme_debug("Received pmk in roam sync. Length: %d", - roam_synch_data->pmk_len); + if (roam_synch_data->pmk_len) csr_check_and_set_sae_single_pmk_cap( mac_ctx, session, session_id, roam_synch_data->pmk, roam_synch_data->pmk_len); - } if (ucfg_pkt_capture_get_pktcap_mode(mac_ctx->psoc)) ucfg_pkt_capture_record_channel(vdev); @@ -21599,12 +21586,11 @@ csr_process_roam_sync_callback(struct mac_context *mac_ctx, * eapol. So the session->psk_pmk will be stale in PMKSA cached * SAE/OWE roaming case. */ - akm_type = session->connectedProfile.AuthType; - if (roam_synch_data->authStatus == CSR_ROAM_AUTH_STATUS_AUTHENTICATED || - akm_type == eCSR_AUTH_TYPE_SAE || - akm_type == eCSR_AUTH_TYPE_FT_SAE || - akm_type == eCSR_AUTH_TYPE_OWE) { + session->pCurRoamProfile->negotiatedAuthType == + eCSR_AUTH_TYPE_SAE || + session->pCurRoamProfile->negotiatedAuthType == + eCSR_AUTH_TYPE_OWE) { csr_roam_substate_change(mac_ctx, eCSR_ROAM_SUBSTATE_NONE, session_id); /* @@ -21629,7 +21615,8 @@ csr_process_roam_sync_callback(struct mac_context *mac_ctx, &session->connectedProfile.bssid); sme_debug("Trying to find PMKID for " QDF_MAC_ADDR_FMT " AKM Type:%d", QDF_MAC_ADDR_REF(pmkid_cache->BSSID.bytes), - akm_type); + session->pCurRoamProfile->negotiatedAuthType); + akm_type = session->connectedProfile.AuthType; mdie_present = session->connectedProfile.mdid.mdie_present; if (csr_lookup_pmkid_using_bssid(mac_ctx, session, @@ -21709,8 +21696,6 @@ csr_process_roam_sync_callback(struct mac_context *mac_ctx, qdf_mem_zero(pmksa, sizeof(*pmksa)); qdf_mem_free(pmksa); } - } else { - sme_debug("PMK not received from fw"); } sme_debug("pmkid found for " QDF_MAC_ADDR_FMT " len %d", QDF_MAC_ADDR_REF(pmkid_cache->BSSID.bytes), diff --git a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_scan.c b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_scan.c index 5ce7d5345138..8ba4ef61b6a1 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_scan.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_scan.c @@ -2256,7 +2256,6 @@ static QDF_STATUS csr_fill_bss_from_scan_entry(struct mac_context *mac_ctx, bss_desc->beaconInterval = scan_entry->bcn_int; bss_desc->capabilityInfo = scan_entry->cap_info.value; - bss_desc->neg_rsn_caps = scan_entry->neg_sec_info.rsn_caps; if (WLAN_REG_IS_5GHZ_CH_FREQ(scan_entry->channel.chan_freq) || WLAN_REG_IS_6GHZ_CHAN_FREQ(scan_entry->channel.chan_freq)) diff --git a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_neighbor_roam.c b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_neighbor_roam.c index ccfa013b89c3..e40a9efd179c 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_neighbor_roam.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_neighbor_roam.c @@ -848,9 +848,6 @@ static void csr_neighbor_roam_info_ctx_init(struct mac_context *mac, wlan_cm_roam_cfg_set_value(mac->psoc, session_id, ROAM_RSSI_DIFF_6GHZ, &src_cfg); - src_cfg.uint_value = mac->mlme_cfg->lfr.roam_rssi_delta_6ghz_to_non_6ghz; - wlan_cm_roam_cfg_set_value(mac->psoc, session_id, - ROAM_RSSI_DELTA_6GHZ_TO_NON_6GHZ, &src_cfg); /* * Now we can clear the preauthDone that * was saved as we are connected afresh diff --git a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_util.c b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_util.c index c2e0f97e1e1f..f8c2f48b711c 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_util.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_util.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -2451,27 +2451,18 @@ static void csr_update_key_mgmt_crypto_param(struct wlan_objmgr_vdev *vdev, { int32_t key_mgmt = 0; int32_t neg_akm; - int32_t ap_akm = 0; uint8_t i; - neg_akm = wlan_crypto_get_param(vdev, WLAN_CRYPTO_PARAM_ORIG_KEY_MGMT); + neg_akm = wlan_crypto_get_param(vdev, WLAN_CRYPTO_PARAM_KEY_MGMT); if (neg_akm < 0) { sme_err("Invalid AKM suite"); return; } for (i = 0; i < ap_rsn.akm_suite_cnt; i++) - SET_PARAM(ap_akm, + SET_PARAM(neg_akm, wlan_crypto_rsn_suite_to_keymgmt(ap_rsn.akm_suite[i])); - /* Intersect crypto AKM and candidate AP's AKM */ - neg_akm &= ap_akm; - if (neg_akm <= 0) { - sme_err("Invalid AKM suite"); - return; - } - sme_debug("Intersected AKM with AP's AKM 0x%x", neg_akm); - /* * As there can be multiple AKM present select the most secured AKM * present @@ -2540,7 +2531,6 @@ static void csr_update_ucast_cipher_crypto_param(struct wlan_objmgr_vdev *vdev, { int32_t ucastcipherset = 0; int32_t neg_ucastcipher; - int32_t ap_ucastcipher = 0; uint8_t i; neg_ucastcipher = wlan_crypto_get_param(vdev, @@ -2551,16 +2541,9 @@ static void csr_update_ucast_cipher_crypto_param(struct wlan_objmgr_vdev *vdev, } for (i = 0; i < ap_rsn.pwise_cipher_suite_count; i++) - SET_PARAM(ap_ucastcipher, + SET_PARAM(neg_ucastcipher, wlan_crypto_rsn_suite_to_cipher(ap_rsn.pwise_cipher_suites[i])); - /* Intersect crypto cipherset and candidate AP's cipherset */ - neg_ucastcipher &= ap_ucastcipher; - if (neg_ucastcipher <= 0) { - sme_err("Invalid unicast cipherset"); - return; - } - /* * As there can be multiple ucastcipher present select the most secured * ucastcipher present. @@ -2604,6 +2587,8 @@ uint8_t csr_construct_rsn_ie(struct mac_context *mac, uint32_t sessionId, (mac, pSirBssDesc, &local_ap_ie)))) return ie_len; + /* get AP RSN cap */ + qdf_mem_copy(&rsn_cap, local_ap_ie->RSN.RSN_Cap, sizeof(rsn_cap)); if (!ap_ie && local_ap_ie) /* locally allocated */ qdf_mem_free(local_ap_ie); @@ -2623,8 +2608,6 @@ uint8_t csr_construct_rsn_ie(struct mac_context *mac, uint32_t sessionId, } self_rsn_cap = (uint16_t)rsn_val; - /* get AP RSN cap */ - rsn_cap = pSirBssDesc->neg_rsn_caps; /* If AP is capable then use self capability else set PMF as 0 */ if (rsn_cap & WLAN_CRYPTO_RSN_CAP_MFP_ENABLED && pProfile->MFPCapable) { diff --git a/drivers/staging/qcacld-3.0/core/wma/inc/wma.h b/drivers/staging/qcacld-3.0/core/wma/inc/wma.h index 99b2164e618a..5474fe767d0f 100644 --- a/drivers/staging/qcacld-3.0/core/wma/inc/wma.h +++ b/drivers/staging/qcacld-3.0/core/wma/inc/wma.h @@ -909,12 +909,11 @@ struct wma_wlm_stats_data { * @dynamic_nss_chains_update: per vdev nss, chains update * @ito_repeat_count: Indicates ito repeated count * @wma_fw_time_sync_timer: timer used for firmware time sync - * @fw_therm_throt_support: FW Supports thermal throttling? - * @roam_sync_runtime_lock: roam sync runtime lock - * @is_roam_lock_acquired: Is roam_sync_runtime_lock acquired + * * @fw_therm_throt_support: FW Supports thermal throttling? * * This structure is the global wma context. It contains global wma * module parameters and handles of other modules. + */ typedef struct { void *wmi_handle; @@ -1046,8 +1045,6 @@ typedef struct { qdf_mc_timer_t wma_fw_time_sync_timer; bool fw_therm_throt_support; bool enable_tx_compl_tsf64; - qdf_runtime_lock_t roam_sync_runtime_lock; - bool is_roam_lock_acquired; } t_wma_handle, *tp_wma_handle; /** diff --git a/drivers/staging/qcacld-3.0/core/wma/inc/wma_internal.h b/drivers/staging/qcacld-3.0/core/wma/inc/wma_internal.h index 45e2e678442b..1d7f88d5392c 100644 --- a/drivers/staging/qcacld-3.0/core/wma/inc/wma_internal.h +++ b/drivers/staging/qcacld-3.0/core/wma/inc/wma_internal.h @@ -1587,23 +1587,6 @@ void wma_acquire_wakelock(qdf_wake_lock_t *wl, uint32_t msec); */ void wma_release_wakelock(qdf_wake_lock_t *wl); -/** - * wma_prevent_pm_during_roam_sync() - prevent runtime PM during roam sync - * @wma: a reference to the global WMA handle - * - * Return: None - */ -void wma_prevent_pm_during_roam_sync(t_wma_handle *wma); - -/** - * wma_allow_pm_after_roam_sync() - allow runtime PM after roam - * sync complete - * @wma: a reference to the global WMA handle - * - * Return: None - */ -void wma_allow_pm_after_roam_sync(t_wma_handle *wma); - /** * wma_send_vdev_stop_to_fw() - send the vdev stop command to firmware * @wma: a reference to the global WMA handle diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_dev_if.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_dev_if.c index 4d045b27df28..15f3c657a065 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_dev_if.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_dev_if.c @@ -943,14 +943,14 @@ static void wma_peer_send_phymode(struct wlan_objmgr_vdev *vdev, fw_phymode = wma_host_to_fw_phymode(new_phymode); vdev_id = wlan_vdev_get_id(vdev); + wma_set_peer_param(wma, peer_mac_addr, WMI_PEER_PHYMODE, + fw_phymode, vdev_id); + max_ch_width_supported = wmi_get_ch_width_from_phy_mode(wma->wmi_handle, fw_phymode); wma_set_peer_param(wma, peer_mac_addr, WMI_PEER_CHWIDTH, max_ch_width_supported, vdev_id); - wma_set_peer_param(wma, peer_mac_addr, WMI_PEER_PHYMODE, - fw_phymode, vdev_id); - wma_debug("FW phymode %d old phymode %d new phymode %d bw %d macaddr "QDF_MAC_ADDR_FMT, fw_phymode, old_peer_phymode, new_phymode, max_ch_width_supported, QDF_MAC_ADDR_REF(peer_mac_addr)); diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_features.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_features.c index 2d22d4726167..dcd409da821b 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_features.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_features.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -2907,9 +2907,6 @@ int wma_wow_wakeup_host_event(void *handle, uint8_t *event, uint32_t len) WMI_WOW_WAKEUP_HOST_EVENTID_param_tlvs *event_param; WOW_EVENT_INFO_fixed_param *wake_info; - if (!wma || !wma->psoc) - return -EINVAL; - event_param = (WMI_WOW_WAKEUP_HOST_EVENTID_param_tlvs *)event; if (!event_param) { wma_err("Wake event data is null"); diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_main.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_main.c index 7021b8720fc3..b48b2729e9ae 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_main.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_main.c @@ -3428,8 +3428,6 @@ QDF_STATUS wma_open(struct wlan_objmgr_psoc *psoc, "wlan_fw_rsp_wakelock"); qdf_runtime_lock_init(&wma_handle->wmi_cmd_rsp_runtime_lock); qdf_runtime_lock_init(&wma_handle->sap_prevent_runtime_pm_lock); - qdf_runtime_lock_init(&wma_handle->roam_sync_runtime_lock); - wma_handle->is_roam_lock_acquired = false; /* Register peer assoc conf event handler */ wmi_unified_register_event_handler(wma_handle->wmi_handle, @@ -3540,7 +3538,6 @@ err_dbglog_init: qdf_runtime_lock_deinit(&wma_handle->sap_prevent_runtime_pm_lock); qdf_runtime_lock_deinit(&wma_handle->wmi_cmd_rsp_runtime_lock); qdf_spinlock_destroy(&wma_handle->wma_hold_req_q_lock); - qdf_runtime_lock_deinit(&wma_handle->roam_sync_runtime_lock); err_event_init: wmi_unified_unregister_event_handler(wma_handle->wmi_handle, wmi_debug_print_event_id); @@ -4595,7 +4592,6 @@ QDF_STATUS wma_close(void) qdf_wake_lock_destroy(&wma_handle->wmi_cmd_rsp_wake_lock); qdf_runtime_lock_deinit(&wma_handle->sap_prevent_runtime_pm_lock); qdf_runtime_lock_deinit(&wma_handle->wmi_cmd_rsp_runtime_lock); - qdf_runtime_lock_deinit(&wma_handle->roam_sync_runtime_lock); qdf_spinlock_destroy(&wma_handle->wma_hold_req_q_lock); if (wma_handle->pGetRssiReq) { diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_mgmt.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_mgmt.c index ec3e079e5096..3c7e6c9105e0 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_mgmt.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_mgmt.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2013-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022, 2026 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -2732,10 +2732,6 @@ void wma_process_update_opmode(tp_wma_handle wma_handle, wma_set_peer_param(wma_handle, update_vht_opmode->peer_mac, WMI_PEER_CHWIDTH, update_vht_opmode->opMode, update_vht_opmode->smesessionId); - - wma_set_peer_param(wma_handle, update_vht_opmode->peer_mac, - WMI_PEER_PHYMODE, - fw_phymode, update_vht_opmode->smesessionId); } /** diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_power.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_power.c index 66ca5d8947a4..4fdc73e85179 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_power.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_power.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1171,28 +1171,20 @@ static void wma_update_beacon_noa_ie(struct beacon_info *bcn, /* TODO: Assuming p2p noa ie is last ie in the beacon */ qdf_mem_zero(bcn->noa_ie, (bcn->noa_sub_ie_len + sizeof(struct p2p_ie))); - if (bcn->len < (bcn->noa_sub_ie_len + - sizeof(struct p2p_ie))) - bcn->len = 0; - else - bcn->len -= (bcn->noa_sub_ie_len + - sizeof(struct p2p_ie)); + bcn->len -= (bcn->noa_sub_ie_len + + sizeof(struct p2p_ie)); bcn->noa_ie = NULL; bcn->noa_sub_ie_len = 0; } + wma_debug("No need to update NoA"); return; } if (bcn->noa_sub_ie_len && bcn->noa_ie) { - if (bcn->len < (bcn->noa_sub_ie_len + sizeof(struct p2p_ie))) - bcn->len = 0; - else - bcn->len -= (bcn->noa_sub_ie_len + - sizeof(struct p2p_ie)); - /* NoA present in previous beacon, update it */ wma_debug("NoA present in previous beacon, update the NoA IE, bcn->len %u bcn->noa_sub_ie_len %u", - bcn->len, bcn->noa_sub_ie_len); + bcn->len, bcn->noa_sub_ie_len); + bcn->len -= (bcn->noa_sub_ie_len + sizeof(struct p2p_ie)); qdf_mem_zero(bcn->noa_ie, (bcn->noa_sub_ie_len + sizeof(struct p2p_ie))); } else { /* NoA is not present in previous beacon */ diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c index 915e196f4d81..702063ef6170 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c @@ -1617,23 +1617,21 @@ int wma_roam_synch_event_handler(void *handle, uint8_t *event, return status; } - wma_prevent_pm_during_roam_sync(wma); - param_buf = (WMI_ROAM_SYNCH_EVENTID_param_tlvs *)event; if (!param_buf) { wma_err_rl("received null buf from target"); - goto fail; + return status; } synch_event = param_buf->fixed_param; if (!synch_event) { wma_err_rl("received null event data from target"); - goto fail; + return status; } if (synch_event->vdev_id >= wma->max_bssid) { wma_err_rl("received invalid vdev_id %d", synch_event->vdev_id); - goto fail; + return status; } iface = &wma->interfaces[synch_event->vdev_id]; @@ -1649,14 +1647,10 @@ int wma_roam_synch_event_handler(void *handle, uint8_t *event, if (QDF_IS_STATUS_ERROR(qdf_status)) { wma_err("Failed to send the EV_ROAM"); wma_post_roam_sync_failure(wma, synch_event->vdev_id); - goto fail; + return status; } wma_debug("Posted EV_ROAM to VDEV SM"); return 0; - -fail: - wma_allow_pm_after_roam_sync(wma); - return status; } int wma_roam_auth_offload_event_handler(WMA_HANDLE handle, uint8_t *event, @@ -2070,7 +2064,7 @@ wma_rso_print_scan_info(struct wmi_roam_scan_data *scan, uint8_t vdev_id, tmp = buf; /* For partial scans, print the channel info */ - if (scan->type == ROAM_STATS_SCAN_TYPE_PARTIAL) { + if (!scan->type) { buf_cons = qdf_snprint(tmp, buf_left, "{"); buf_left -= buf_cons; tmp += buf_cons; @@ -2839,7 +2833,6 @@ void wma_process_roam_synch_complete(WMA_HANDLE handle, uint8_t vdev_id) wma_info("LFR3: vdev[%d] Sent ROAM_SYNCH_COMPLETE", vdev_id); wlan_roam_debug_log(vdev_id, DEBUG_ROAM_SYNCH_CNF, DEBUG_INVALID_PEER_ID, NULL, NULL, 0, 0); - wma_allow_pm_after_roam_sync(wma_handle); } #endif /* WLAN_FEATURE_ROAM_OFFLOAD */ @@ -4558,12 +4551,10 @@ static void wma_invalid_roam_reason_handler(tp_wma_handle wma_handle, if (notif == WMI_ROAM_NOTIF_ROAM_START) { wma_handle->interfaces[vdev_id].roaming_in_progress = true; op_code = SIR_ROAMING_START; - wma_prevent_pm_during_roam_sync(wma_handle); } else if (notif == WMI_ROAM_NOTIF_ROAM_ABORT) { wma_handle->interfaces[vdev_id].roaming_in_progress = false; op_code = SIR_ROAMING_ABORT; lim_sae_auth_cleanup_retry(wma_handle->mac_context, vdev_id); - wma_allow_pm_after_roam_sync(wma_handle); } else { wma_debug("Invalid notif %d", notif); return; @@ -4739,7 +4730,6 @@ int wma_roam_event_callback(WMA_HANDLE handle, uint8_t *event_buf, = false; lim_sae_auth_cleanup_retry(wma_handle->mac_context, wmi_event->vdev_id); - wma_allow_pm_after_roam_sync(wma_handle); break; #endif case WMI_ROAM_REASON_INVALID: diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_utils.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_utils.c index 23d2e9a87be8..57d3d09ea1da 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_utils.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_utils.c @@ -1361,15 +1361,6 @@ wma_fill_rx_stats(struct sir_wifi_ll_ext_stats *ll_stats, wmi_peer_rx, wmi_rx, peer_stats); return QDF_STATUS_E_FAILURE; } - - /* Check if num_rx_stats is sufficient to avoid buffer overflow */ - if (param_buf->num_rx_stats < - fix_param->num_peer_ac_rx_stats * WLAN_MAX_AC) { - wma_err("Insufficient rx_stats buffer: available %d, required %d", - param_buf->num_rx_stats, - fix_param->num_peer_ac_rx_stats * WLAN_MAX_AC); - return QDF_STATUS_E_FAILURE; - } for (i = 0; i < fix_param->num_peer_ac_rx_stats; i++) { uint32_t peer_id = wmi_peer_rx[i].peer_id; struct sir_wifi_rx *ac; @@ -3824,30 +3815,6 @@ void wma_release_wakelock(qdf_wake_lock_t *wl) qdf_runtime_pm_allow_suspend(&wma->wmi_cmd_rsp_runtime_lock); } -void wma_prevent_pm_during_roam_sync(t_wma_handle *wma) -{ - if (!wma) - return; - - if (wma->is_roam_lock_acquired) - return; - - qdf_runtime_pm_prevent_suspend(&wma->roam_sync_runtime_lock); - wma->is_roam_lock_acquired = true; -} - -void wma_allow_pm_after_roam_sync(t_wma_handle *wma) -{ - if (!wma) - return; - - if (!wma->is_roam_lock_acquired) - return; - - qdf_runtime_pm_allow_suspend(&wma->roam_sync_runtime_lock); - wma->is_roam_lock_acquired = false; -} - QDF_STATUS wma_send_vdev_stop_to_fw(t_wma_handle *wma, uint8_t vdev_id) { QDF_STATUS status = QDF_STATUS_E_FAILURE; diff --git a/drivers/staging/qcacld-3.0/os_if/p2p/src/wlan_cfg80211_p2p.c b/drivers/staging/qcacld-3.0/os_if/p2p/src/wlan_cfg80211_p2p.c index 8363fbe52a80..ddeba7bf0d51 100644 --- a/drivers/staging/qcacld-3.0/os_if/p2p/src/wlan_cfg80211_p2p.c +++ b/drivers/staging/qcacld-3.0/os_if/p2p/src/wlan_cfg80211_p2p.c @@ -1,6 +1,5 @@ /* * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -282,7 +281,8 @@ static void wlan_p2p_event_callback(void *user_data, goto fail; } - chan = ieee80211_get_channel(wdev->wiphy, p2p_event->chan_freq); + chan = ieee80211_get_channel(wdev->wiphy, + wlan_chan_to_freq(p2p_event->chan)); if (!chan) { osif_err("channel conversion failed"); goto fail; @@ -360,7 +360,7 @@ int wlan_cfg80211_roc(struct wlan_objmgr_vdev *vdev, return -EINVAL; } - roc_req.chan_freq = chan->center_freq; + roc_req.chan = (uint32_t)wlan_freq_to_chan(chan->center_freq); roc_req.duration = duration; roc_req.vdev_id = (uint32_t)vdev_id; @@ -372,7 +372,7 @@ int wlan_cfg80211_roc(struct wlan_objmgr_vdev *vdev, } if (!ok) { - osif_err("channel%d not OK for DNBS", roc_req.chan_freq); + osif_err("channel%d not OK for DNBS", roc_req.chan); return -EINVAL; } @@ -409,7 +409,7 @@ int wlan_cfg80211_mgmt_tx(struct wlan_objmgr_vdev *vdev, struct p2p_mgmt_tx mgmt_tx = {0}; struct wlan_objmgr_psoc *psoc; uint8_t vdev_id; - qdf_freq_t chan_freq = 0; + uint32_t channel = 0; if (!vdev) { osif_err("invalid vdev object"); @@ -417,7 +417,7 @@ int wlan_cfg80211_mgmt_tx(struct wlan_objmgr_vdev *vdev, } if (chan) - chan_freq = chan->center_freq; + channel = (uint32_t)wlan_freq_to_chan(chan->center_freq); else osif_debug("NULL chan, set channel to 0"); @@ -436,7 +436,8 @@ int wlan_cfg80211_mgmt_tx(struct wlan_objmgr_vdev *vdev, int ret; bool ok; - ret = policy_mgr_is_chan_ok_for_dnbs(psoc, chan_freq, &ok); + ret = policy_mgr_is_chan_ok_for_dnbs( + psoc, wlan_chan_to_freq(channel), &ok); if (QDF_IS_STATUS_ERROR(ret)) { osif_err("policy_mgr_is_chan_ok_for_dnbs():ret:%d", ret); @@ -444,13 +445,13 @@ int wlan_cfg80211_mgmt_tx(struct wlan_objmgr_vdev *vdev, } if (!ok) { osif_err("Rejecting mgmt_tx for channel:%d as DNSC is set", - chan_freq); + channel); return -EINVAL; } } mgmt_tx.vdev_id = (uint32_t)vdev_id; - mgmt_tx.chan_freq = chan_freq; + mgmt_tx.chan = channel; mgmt_tx.wait = wait; mgmt_tx.len = len; mgmt_tx.no_cck = (uint32_t)no_cck; diff --git a/drivers/staging/qcacld-3.0/uapi/linux/a_types.h b/drivers/staging/qcacld-3.0/uapi/linux/a_types.h index 5537fae67697..190d40df6afd 100644 --- a/drivers/staging/qcacld-3.0/uapi/linux/a_types.h +++ b/drivers/staging/qcacld-3.0/uapi/linux/a_types.h @@ -1,6 +1,5 @@ /* * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -30,21 +29,15 @@ #define _A_TYPES_H_ #include -typedef unsigned long long A_UINT64; -typedef long long A_INT64; - typedef unsigned int A_UINT32; -typedef int A_INT32; - +typedef unsigned long long A_UINT64; typedef unsigned short A_UINT16; -typedef short A_INT16; - typedef unsigned char A_UINT8; -typedef char A_INT8; - +typedef int A_INT32; +typedef short A_INT16; +typedef char A_INT8; typedef unsigned char A_UCHAR; -typedef char A_CHAR; - +typedef char A_CHAR; typedef _Bool A_BOOL; #endif /* _ATHTYPES_H_ */ diff --git a/drivers/staging/vme/devices/vme_user.c b/drivers/staging/vme/devices/vme_user.c index fd0ea4dbcb91..6a33aaa1a49f 100644 --- a/drivers/staging/vme/devices/vme_user.c +++ b/drivers/staging/vme/devices/vme_user.c @@ -494,7 +494,7 @@ static const struct file_operations vme_user_fops = { .write = vme_user_write, .llseek = vme_user_llseek, .unlocked_ioctl = vme_user_unlocked_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = vme_user_unlocked_ioctl, .mmap = vme_user_mmap, }; diff --git a/drivers/target/loopback/tcm_loop.c b/drivers/target/loopback/tcm_loop.c index 9360148e1f4e..5ae5d94c5b93 100644 --- a/drivers/target/loopback/tcm_loop.c +++ b/drivers/target/loopback/tcm_loop.c @@ -933,9 +933,6 @@ static ssize_t tcm_loop_tpg_address_show(struct config_item *item, struct tcm_loop_tpg, tl_se_tpg); struct tcm_loop_hba *tl_hba = tl_tpg->tl_hba; - if (!tl_hba->sh) - return -ENODEV; - return snprintf(page, PAGE_SIZE, "%d:0:%d\n", tl_hba->sh->host_no, tl_tpg->tl_tpgt); } diff --git a/drivers/target/target_core_configfs.c b/drivers/target/target_core_configfs.c index ce7fda75b9cc..4edabab65b87 100644 --- a/drivers/target/target_core_configfs.c +++ b/drivers/target/target_core_configfs.c @@ -2563,7 +2563,7 @@ static ssize_t target_lu_gp_members_show(struct config_item *item, char *page) config_item_name(&dev->dev_group.cg_item)); cur_len++; /* Extra byte for NULL terminator */ - if ((cur_len + len) > PAGE_SIZE || cur_len > LU_GROUP_NAME_BUF) { + if ((cur_len + len) > PAGE_SIZE) { pr_warn("Ran out of lu_gp_show_attr" "_members buffer\n"); break; diff --git a/drivers/tee/tee_core.c b/drivers/tee/tee_core.c index faa6ac8719cc..357944bc73b1 100644 --- a/drivers/tee/tee_core.c +++ b/drivers/tee/tee_core.c @@ -683,7 +683,7 @@ static const struct file_operations tee_fops = { .open = tee_open, .release = tee_release, .unlocked_ioctl = tee_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = tee_ioctl, }; static void tee_release_device(struct device *dev) @@ -722,7 +722,7 @@ struct tee_device *tee_device_alloc(const struct tee_desc *teedesc, if (!teedesc || !teedesc->name || !teedesc->ops || !teedesc->ops->get_version || !teedesc->ops->open || - !teedesc->ops->release) + !teedesc->ops->release || !pool) return ERR_PTR(-EINVAL); teedev = kzalloc(sizeof(*teedev), GFP_KERNEL); diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index 1521a743cc90..2d5a039229ac 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -283,6 +283,9 @@ static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, long rate; int ret; + if (IS_ERR(d->clk)) + goto out; + clk_disable_unprepare(d->clk); rate = clk_round_rate(d->clk, baud * 16); if (rate < 0) @@ -293,10 +296,8 @@ static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, ret = clk_set_rate(d->clk, rate); clk_prepare_enable(d->clk); - if (ret) - goto out; - - p->uartclk = rate; + if (!ret) + p->uartclk = rate; out: p->status &= ~UPSTAT_AUTOCTS; @@ -384,16 +385,6 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) } } -static void dw8250_clk_disable_unprepare(void *data) -{ - clk_disable_unprepare(data); -} - -static void dw8250_reset_control_assert(void *data) -{ - reset_control_assert(data); -} - static int dw8250_probe(struct platform_device *pdev) { struct uart_8250_port uart = {}, *up = &uart; @@ -482,54 +473,46 @@ static int dw8250_probe(struct platform_device *pdev) device_property_read_u32(dev, "clock-frequency", &p->uartclk); /* If there is separate baudclk, get the rate from it. */ - data->clk = devm_clk_get_optional(dev, "baudclk"); - if (data->clk == NULL) - data->clk = devm_clk_get_optional(dev, NULL); - if (IS_ERR(data->clk)) - return PTR_ERR(data->clk); - - err = clk_prepare_enable(data->clk); - if (err) - dev_warn(dev, "could not enable optional baudclk: %d\n", err); - - err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->clk); - if (err) - return err; - - if (data->clk) - p->uartclk = clk_get_rate(data->clk); + data->clk = devm_clk_get(dev, "baudclk"); + if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER) + data->clk = devm_clk_get(dev, NULL); + if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) + return -EPROBE_DEFER; + if (!IS_ERR_OR_NULL(data->clk)) { + err = clk_prepare_enable(data->clk); + if (err) + dev_warn(dev, "could not enable optional baudclk: %d\n", + err); + else + p->uartclk = clk_get_rate(data->clk); + } /* If no clock rate is defined, fail. */ if (!p->uartclk) { dev_err(dev, "clock rate not defined\n"); - return -EINVAL; + err = -EINVAL; + goto err_clk; } - data->pclk = devm_clk_get_optional(dev, "apb_pclk"); - if (IS_ERR(data->pclk)) - return PTR_ERR(data->pclk); - - err = clk_prepare_enable(data->pclk); - if (err) { - dev_err(dev, "could not enable apb_pclk\n"); - return err; + data->pclk = devm_clk_get(dev, "apb_pclk"); + if (IS_ERR(data->pclk) && PTR_ERR(data->pclk) == -EPROBE_DEFER) { + err = -EPROBE_DEFER; + goto err_clk; + } + if (!IS_ERR(data->pclk)) { + err = clk_prepare_enable(data->pclk); + if (err) { + dev_err(dev, "could not enable apb_pclk\n"); + goto err_clk; + } } - - err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->pclk); - if (err) - return err; data->rst = devm_reset_control_get_optional_exclusive(dev, NULL); - if (IS_ERR(data->rst)) - return PTR_ERR(data->rst); - - err = reset_control_deassert(data->rst); - if (err) - return dev_err_probe(dev, err, "failed to deassert resets\n"); - - err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst); - if (err) - return err; + if (IS_ERR(data->rst)) { + err = PTR_ERR(data->rst); + goto err_pclk; + } + reset_control_deassert(data->rst); dw8250_quirks(p, data); @@ -548,8 +531,10 @@ static int dw8250_probe(struct platform_device *pdev) } data->data.line = serial8250_register_8250_port(up); - if (data->data.line < 0) - return data->data.line; + if (data->data.line < 0) { + err = data->data.line; + goto err_reset; + } platform_set_drvdata(pdev, data); @@ -557,6 +542,19 @@ static int dw8250_probe(struct platform_device *pdev) pm_runtime_enable(dev); return 0; + +err_reset: + reset_control_assert(data->rst); + +err_pclk: + if (!IS_ERR(data->pclk)) + clk_disable_unprepare(data->pclk); + +err_clk: + if (!IS_ERR(data->clk)) + clk_disable_unprepare(data->clk); + + return err; } static int dw8250_remove(struct platform_device *pdev) @@ -568,6 +566,14 @@ static int dw8250_remove(struct platform_device *pdev) serial8250_unregister_port(data->data.line); + reset_control_assert(data->rst); + + if (!IS_ERR(data->pclk)) + clk_disable_unprepare(data->pclk); + + if (!IS_ERR(data->clk)) + clk_disable_unprepare(data->clk); + pm_runtime_disable(dev); pm_runtime_put_noidle(dev); @@ -599,9 +605,11 @@ static int dw8250_runtime_suspend(struct device *dev) { struct dw8250_data *data = dev_get_drvdata(dev); - clk_disable_unprepare(data->clk); + if (!IS_ERR(data->clk)) + clk_disable_unprepare(data->clk); - clk_disable_unprepare(data->pclk); + if (!IS_ERR(data->pclk)) + clk_disable_unprepare(data->pclk); return 0; } @@ -610,9 +618,11 @@ static int dw8250_runtime_resume(struct device *dev) { struct dw8250_data *data = dev_get_drvdata(dev); - clk_prepare_enable(data->pclk); + if (!IS_ERR(data->pclk)) + clk_prepare_enable(data->pclk); - clk_prepare_enable(data->clk); + if (!IS_ERR(data->clk)) + clk_prepare_enable(data->clk); return 0; } diff --git a/drivers/tty/serial/max310x.c b/drivers/tty/serial/max310x.c index c621a5ecf200..26bdb32e3ce3 100644 --- a/drivers/tty/serial/max310x.c +++ b/drivers/tty/serial/max310x.c @@ -1647,8 +1647,6 @@ static int max310x_i2c_probe(struct i2c_client *client) port_client = devm_i2c_new_dummy_device(&client->dev, client->adapter, port_addr); - if (IS_ERR(port_client)) - return PTR_ERR(port_client); regmaps[i] = devm_regmap_init_i2c(port_client, ®cfg_i2c); } diff --git a/drivers/tty/serial/msm_serial_hs.c b/drivers/tty/serial/msm_serial_hs.c index 47c50bb1eef3..cfee5b5799b6 100644 --- a/drivers/tty/serial/msm_serial_hs.c +++ b/drivers/tty/serial/msm_serial_hs.c @@ -2684,7 +2684,7 @@ static int msm_hs_startup(struct uart_port *uport) tx->dma_in_flight = false; MSM_HS_DBG("%s():desc usage flag 0x%lx\n", __func__, rx->queued_flag); timer_setup(&(tx->tx_timeout_timer), - tx_timeout_handler, TIMER_IRQSAFE); + tx_timeout_handler, 0); /* Enable reading the current CTS, no harm even if CTS is ignored */ msm_uport->imr_reg |= UARTDM_ISR_CURRENT_CTS_BMSK; diff --git a/drivers/tty/tty_ioctl.c b/drivers/tty/tty_ioctl.c index 2fbd991f5e34..5d833f0b412d 100644 --- a/drivers/tty/tty_ioctl.c +++ b/drivers/tty/tty_ioctl.c @@ -807,7 +807,7 @@ int tty_mode_ioctl(struct tty_struct *tty, struct file *file, ret = -EFAULT; return ret; case TIOCSLCKTRMIOS: - if (!checkpoint_restore_ns_capable(&init_user_ns)) + if (!capable(CAP_SYS_ADMIN)) return -EPERM; copy_termios_locked(real_tty, &kterm); if (user_termios_to_kernel_termios(&kterm, @@ -824,7 +824,7 @@ int tty_mode_ioctl(struct tty_struct *tty, struct file *file, ret = -EFAULT; return ret; case TIOCSLCKTRMIOS: - if (!checkpoint_restore_ns_capable(&init_user_ns)) + if (!capable(CAP_SYS_ADMIN)) return -EPERM; copy_termios_locked(real_tty, &kterm); if (user_termios_to_kernel_termios_1(&kterm, diff --git a/drivers/uio/uio_hv_generic.c b/drivers/uio/uio_hv_generic.c index 0d7ebf7b35e1..c707c3627cc2 100644 --- a/drivers/uio/uio_hv_generic.c +++ b/drivers/uio/uio_hv_generic.c @@ -80,15 +80,9 @@ hv_uio_irqcontrol(struct uio_info *info, s32 irq_state) { struct hv_uio_private_data *pdata = info->priv; struct hv_device *dev = pdata->device; - struct vmbus_channel *primary, *sc; - primary = dev->channel; - primary->inbound.ring_buffer->interrupt_mask = !irq_state; - - mutex_lock(&vmbus_connection.channel_mutex); - list_for_each_entry(sc, &primary->sc_list, sc_list) - sc->inbound.ring_buffer->interrupt_mask = !irq_state; - mutex_unlock(&vmbus_connection.channel_mutex); + dev->channel->inbound.ring_buffer->interrupt_mask = !irq_state; + virt_mb(); return 0; } @@ -99,18 +93,12 @@ hv_uio_irqcontrol(struct uio_info *info, s32 irq_state) static void hv_uio_channel_cb(void *context) { struct vmbus_channel *chan = context; - struct hv_device *hv_dev; - struct hv_uio_private_data *pdata; + struct hv_device *hv_dev = chan->device_obj; + struct hv_uio_private_data *pdata = hv_get_drvdata(hv_dev); + chan->inbound.ring_buffer->interrupt_mask = 1; virt_mb(); - /* - * The callback may come from a subchannel, in which case look - * for the hv device in the primary channel - */ - hv_dev = chan->primary_channel ? - chan->primary_channel->device_obj : chan->device_obj; - pdata = hv_get_drvdata(hv_dev); uio_event_notify(&pdata->info); } @@ -185,6 +173,8 @@ hv_uio_new_channel(struct vmbus_channel *new_sc) return; } + /* Disable interrupts on sub channel */ + new_sc->inbound.ring_buffer->interrupt_mask = 1; set_channel_read_mode(new_sc, HV_CALL_ISR); ret = sysfs_create_bin_file(&new_sc->kobj, &ring_buffer_bin_attr); @@ -228,7 +218,9 @@ hv_uio_open(struct uio_info *info, struct inode *inode) ret = vmbus_connect_ring(dev->channel, hv_uio_channel_cb, dev->channel); - if (ret) + if (ret == 0) + dev->channel->inbound.ring_buffer->interrupt_mask = 1; + else atomic_dec(&pdata->refcnt); return ret; diff --git a/drivers/usb/class/cdc-wdm.c b/drivers/usb/class/cdc-wdm.c index d2bbc9a43e7b..6afb941dd267 100644 --- a/drivers/usb/class/cdc-wdm.c +++ b/drivers/usb/class/cdc-wdm.c @@ -790,7 +790,7 @@ static const struct file_operations wdm_fops = { .release = wdm_release, .poll = wdm_poll, .unlocked_ioctl = wdm_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = wdm_ioctl, .llseek = noop_llseek, }; diff --git a/drivers/usb/class/usbtmc.c b/drivers/usb/class/usbtmc.c index 7ad47637f2a7..d8ed205e6b43 100644 --- a/drivers/usb/class/usbtmc.c +++ b/drivers/usb/class/usbtmc.c @@ -2241,7 +2241,9 @@ static const struct file_operations fops = { .release = usbtmc_release, .flush = usbtmc_flush, .unlocked_ioctl = usbtmc_ioctl, - .compat_ioctl = compat_ptr_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = usbtmc_ioctl, +#endif .fasync = usbtmc_fasync, .poll = usbtmc_poll, .llseek = default_llseek, diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c index de52ed067d24..d0726f02ae63 100644 --- a/drivers/usb/core/quirks.c +++ b/drivers/usb/core/quirks.c @@ -463,8 +463,6 @@ static const struct usb_device_id usb_quirk_list[] = { /* Huawei 4G LTE module */ { USB_DEVICE(0x12d1, 0x15bb), .driver_info = USB_QUIRK_DISCONNECT_SUSPEND }, - { USB_DEVICE(0x12d1, 0x15c1), .driver_info = - USB_QUIRK_DISCONNECT_SUSPEND }, { USB_DEVICE(0x12d1, 0x15c3), .driver_info = USB_QUIRK_DISCONNECT_SUSPEND }, diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 2b9a638bbd60..a12c5c9ed397 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -491,10 +491,6 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, dwc3_gadget_ep_get_transfer_index(dep); } - if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER && - !(cmd & DWC3_DEPCMD_CMDIOC)) - mdelay(1); - if (saved_config) { reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); reg |= saved_config; @@ -3754,6 +3750,9 @@ int dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt) else dep->flags |= DWC3_EP_END_TRANSFER_PENDING; + if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) + udelay(100); + return ret; } EXPORT_SYMBOL(dwc3_stop_active_transfer); diff --git a/drivers/usb/gadget/configfs.c b/drivers/usb/gadget/configfs.c index 56dc905d73b7..b0000980f5f1 100644 --- a/drivers/usb/gadget/configfs.c +++ b/drivers/usb/gadget/configfs.c @@ -1454,9 +1454,8 @@ static int configfs_composite_bind(struct usb_gadget *gadget, cdev->use_os_string = true; cdev->b_vendor_code = gi->b_vendor_code; memcpy(cdev->qw_sign, gi->qw_sign, OS_STRING_QW_SIGN_LEN); - } else { + } else cdev->use_os_string = false; - } if (gadget_is_otg(gadget) && !otg_desc[0]) { struct usb_descriptor_header *usb_desc; diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c index 3c8853cb0d01..ec2dea6fe270 100644 --- a/drivers/usb/gadget/function/f_fs.c +++ b/drivers/usb/gadget/function/f_fs.c @@ -2258,12 +2258,7 @@ static int ffs_func_eps_enable(struct ffs_function *func) ep = func->eps; epfile = ffs->epfiles; count = ffs->eps_count; - if (!epfile) { - ret = -ENOMEM; - goto done; - } - - while (count--) { + while(count--) { ep->ep->driver_data = ep; ret = config_ep_by_speed(func->gadget, &func->function, ep->ep); @@ -2289,7 +2284,6 @@ static int ffs_func_eps_enable(struct ffs_function *func) } wake_up_interruptible(&ffs->wait); -done: spin_unlock_irqrestore(&func->ffs->eps_lock, flags); return ret; diff --git a/drivers/usb/gadget/function/f_hid.c b/drivers/usb/gadget/function/f_hid.c index cea9157ea2b4..77354626252c 100644 --- a/drivers/usb/gadget/function/f_hid.c +++ b/drivers/usb/gadget/function/f_hid.c @@ -496,7 +496,7 @@ try_again: } req->status = 0; - req->zero = 1; + req->zero = 0; req->length = count; req->complete = f_hidg_req_complete; req->context = hidg; @@ -767,7 +767,7 @@ stall: return -EOPNOTSUPP; respond: - req->zero = 1; + req->zero = 0; req->length = length; status = usb_ep_queue(cdev->gadget->ep0, req, GFP_ATOMIC); if (status < 0) diff --git a/drivers/usb/gadget/function/f_ncm.c b/drivers/usb/gadget/function/f_ncm.c index b1e569337382..ca50257b9538 100644 --- a/drivers/usb/gadget/function/f_ncm.c +++ b/drivers/usb/gadget/function/f_ncm.c @@ -1472,8 +1472,6 @@ static int ncm_bind(struct usb_configuration *c, struct usb_function *f) ncm_opts->bound = true; - ncm_string_defs[1].s = ncm->ethaddr; - us = usb_gstrings_attach(cdev, ncm_strings, ARRAY_SIZE(ncm_string_defs)); if (IS_ERR(us)) { @@ -1737,6 +1735,7 @@ static struct usb_function *ncm_alloc(struct usb_function_instance *fi) mutex_unlock(&opts->lock); return ERR_PTR(-EINVAL); } + ncm_string_defs[STRING_MAC_IDX].s = ncm->ethaddr; spin_lock_init(&ncm->lock); ncm_reset_values(ncm); diff --git a/drivers/usb/gadget/function/f_uvc.c b/drivers/usb/gadget/function/f_uvc.c index b4c08b4ed602..094a88ff9a67 100644 --- a/drivers/usb/gadget/function/f_uvc.c +++ b/drivers/usb/gadget/function/f_uvc.c @@ -808,9 +808,9 @@ static struct usb_function_instance *uvc_alloc_inst(void) cd->wObjectiveFocalLengthMax = cpu_to_le16(0); cd->wOcularFocalLength = cpu_to_le16(0); cd->bControlSize = 3; - cd->bmControls[0] = 62; - cd->bmControls[1] = 126; - cd->bmControls[2] = 10; + cd->bmControls[0] = 2; + cd->bmControls[1] = 0; + cd->bmControls[2] = 0; pd = &opts->uvc_processing; pd->bLength = UVC_DT_PROCESSING_UNIT_SIZE(2); @@ -820,8 +820,8 @@ static struct usb_function_instance *uvc_alloc_inst(void) pd->bSourceID = 1; pd->wMaxMultiplier = cpu_to_le16(16*1024); pd->bControlSize = 2; - pd->bmControls[0] = 91; - pd->bmControls[1] = 23; + pd->bmControls[0] = 1; + pd->bmControls[1] = 0; pd->iProcessing = 0; pd->bmVideoStandards = 0; diff --git a/drivers/usb/gadget/function/uvc.h b/drivers/usb/gadget/function/uvc.h index 9961d7d04546..1473d25ff17a 100644 --- a/drivers/usb/gadget/function/uvc.h +++ b/drivers/usb/gadget/function/uvc.h @@ -65,7 +65,7 @@ extern unsigned int uvc_gadget_trace_param; * Driver specific constants */ -#define UVC_NUM_REQUESTS 64 +#define UVC_NUM_REQUESTS 4 #define UVC_MAX_REQUEST_SIZE 64 #define UVC_MAX_EVENTS 4 diff --git a/drivers/usb/gadget/function/uvc_configfs.c b/drivers/usb/gadget/function/uvc_configfs.c index 5480a2988fe4..00fb58e50a15 100644 --- a/drivers/usb/gadget/function/uvc_configfs.c +++ b/drivers/usb/gadget/function/uvc_configfs.c @@ -762,19 +762,16 @@ static const struct uvcg_config_group_type uvcg_control_grp_type = { /* ----------------------------------------------------------------------------- * streaming/uncompressed * streaming/mjpeg - * streaming/framebased */ static const char * const uvcg_format_names[] = { "uncompressed", "mjpeg", - "framebased" }; enum uvcg_format_type { UVCG_UNCOMPRESSED = 0, UVCG_MJPEG, - UVCG_FRAMEBASED, }; struct uvcg_format { @@ -1083,7 +1080,6 @@ struct uvcg_frame { u32 dw_max_video_frame_buffer_size; u32 dw_default_frame_interval; u8 b_frame_interval_type; - u32 dw_bytes_perline; } __attribute__((packed)) frame; u32 *dw_frame_interval; }; @@ -1194,7 +1190,6 @@ UVCG_FRAME_ATTR(dw_min_bit_rate, dwMinBitRate, 32); UVCG_FRAME_ATTR(dw_max_bit_rate, dwMaxBitRate, 32); UVCG_FRAME_ATTR(dw_max_video_frame_buffer_size, dwMaxVideoFrameBufferSize, 32); UVCG_FRAME_ATTR(dw_default_frame_interval, dwDefaultFrameInterval, 32); -UVCG_FRAME_ATTR(dw_bytes_perline, dwBytesPerLine, 32); #undef UVCG_FRAME_ATTR @@ -1329,7 +1324,7 @@ end: UVC_ATTR(uvcg_frame_, dw_frame_interval, dwFrameInterval); -static struct configfs_attribute *uvcg_frame_attrs1[] = { +static struct configfs_attribute *uvcg_frame_attrs[] = { &uvcg_frame_attr_b_frame_index, &uvcg_frame_attr_bm_capabilities, &uvcg_frame_attr_w_width, @@ -1342,32 +1337,12 @@ static struct configfs_attribute *uvcg_frame_attrs1[] = { NULL, }; -static struct configfs_attribute *uvcg_frame_attrs2[] = { - &uvcg_frame_attr_b_frame_index, - &uvcg_frame_attr_bm_capabilities, - &uvcg_frame_attr_w_width, - &uvcg_frame_attr_w_height, - &uvcg_frame_attr_dw_min_bit_rate, - &uvcg_frame_attr_dw_max_bit_rate, - &uvcg_frame_attr_dw_max_video_frame_buffer_size, - &uvcg_frame_attr_dw_default_frame_interval, - &uvcg_frame_attr_dw_frame_interval, - &uvcg_frame_attr_dw_bytes_perline, - NULL, -}; - -static const struct config_item_type uvcg_frame_type1 = { +static const struct config_item_type uvcg_frame_type = { .ct_item_ops = &uvcg_config_item_ops, - .ct_attrs = uvcg_frame_attrs1, + .ct_attrs = uvcg_frame_attrs, .ct_owner = THIS_MODULE, }; -static const struct config_item_type uvcg_frame_type2 = { - .ct_item_ops = &uvcg_config_item_ops, - .ct_attrs = uvcg_frame_attrs2, - .ct_owner = THIS_MODULE, -}; - static struct config_item *uvcg_frame_make(struct config_group *group, const char *name) { @@ -1388,7 +1363,6 @@ static struct config_item *uvcg_frame_make(struct config_group *group, h->frame.dw_max_bit_rate = 55296000; h->frame.dw_max_video_frame_buffer_size = 460800; h->frame.dw_default_frame_interval = 666666; - h->frame.dw_bytes_perline = 0; opts_item = group->cg_item.ci_parent->ci_parent->ci_parent; opts = to_f_uvc_opts(opts_item); @@ -1401,9 +1375,6 @@ static struct config_item *uvcg_frame_make(struct config_group *group, } else if (fmt->type == UVCG_MJPEG) { h->frame.b_descriptor_subtype = UVC_VS_FRAME_MJPEG; h->fmt_type = UVCG_MJPEG; - } else if (fmt->type == UVCG_FRAMEBASED) { - h->frame.b_descriptor_subtype = UVC_VS_FRAME_FRAME_BASED; - h->fmt_type = UVCG_FRAMEBASED; } else { mutex_unlock(&opts->lock); kfree(h); @@ -1412,10 +1383,7 @@ static struct config_item *uvcg_frame_make(struct config_group *group, ++fmt->num_frames; mutex_unlock(&opts->lock); - if (fmt->type == UVCG_FRAMEBASED) - config_item_init_type_name(&h->item, name, &uvcg_frame_type2); - else - config_item_init_type_name(&h->item, name, &uvcg_frame_type1); + config_item_init_type_name(&h->item, name, &uvcg_frame_type); return &h->item; } @@ -1445,6 +1413,9 @@ static void uvcg_format_set_indices(struct config_group *fmt) list_for_each_entry(ci, &fmt->cg_children, ci_entry) { struct uvcg_frame *frm; + if (ci->ci_type != &uvcg_frame_type) + continue; + frm = to_uvcg_frame(ci); frm->frame.b_frame_index = i++; } @@ -1885,260 +1856,6 @@ static const struct uvcg_config_group_type uvcg_mjpeg_grp_type = { .name = "mjpeg", }; -/* ----------------------------------------------------------------------------- - * streaming/framebased/ - */ - -struct uvcg_framebased { - struct uvcg_format fmt; - struct uvc_format_framebased desc; -}; - -static inline struct uvcg_framebased *to_uvcg_framebased(struct config_item *item) -{ - return container_of(to_uvcg_format(item), struct uvcg_framebased, fmt); -} - -static struct configfs_group_operations uvcg_framebased_group_ops = { - .make_item = uvcg_frame_make, - .drop_item = uvcg_frame_drop, -}; - -#define UVCG_FRAMEBASED_ATTR_RO(cname, aname, bits) \ - static ssize_t uvcg_framebased_##cname##_show(struct config_item *item, \ - char *page) \ -{ \ - struct uvcg_framebased *u = to_uvcg_framebased(item); \ - struct f_uvc_opts *opts; \ - struct config_item *opts_item; \ - struct mutex *su_mutex = &u->fmt.group.cg_subsys->su_mutex; \ - int result; \ - \ - mutex_lock(su_mutex); /* for navigating configfs hierarchy */ \ - \ - opts_item = u->fmt.group.cg_item.ci_parent->ci_parent->ci_parent; \ - opts = to_f_uvc_opts(opts_item); \ - \ - mutex_lock(&opts->lock); \ - result = scnprintf(page, PAGE_SIZE, "%u\n", le##bits##_to_cpu(u->desc.aname));\ - mutex_unlock(&opts->lock); \ - \ - mutex_unlock(su_mutex); \ - return result; \ -} \ - \ -UVC_ATTR_RO(uvcg_framebased_, cname, aname) - -#define UVCG_FRAMEBASED_ATTR(cname, aname, bits) \ - static ssize_t uvcg_framebased_##cname##_show(struct config_item *item, \ - char *page) \ -{ \ - struct uvcg_framebased *u = to_uvcg_framebased(item); \ - struct f_uvc_opts *opts; \ - struct config_item *opts_item; \ - struct mutex *su_mutex = &u->fmt.group.cg_subsys->su_mutex; \ - int result; \ - \ - mutex_lock(su_mutex); /* for navigating configfs hierarchy */ \ - \ - opts_item = u->fmt.group.cg_item.ci_parent->ci_parent->ci_parent;\ - opts = to_f_uvc_opts(opts_item); \ - \ - mutex_lock(&opts->lock); \ - result = scnprintf(page, PAGE_SIZE, "%u\n", le##bits##_to_cpu(u->desc.aname));\ - mutex_unlock(&opts->lock); \ - \ - mutex_unlock(su_mutex); \ - return result; \ -} \ - \ -static ssize_t \ -uvcg_framebased_##cname##_store(struct config_item *item, \ - const char *page, size_t len) \ -{ \ - struct uvcg_framebased *u = to_uvcg_framebased(item); \ - struct f_uvc_opts *opts; \ - struct config_item *opts_item; \ - struct mutex *su_mutex = &u->fmt.group.cg_subsys->su_mutex; \ - int ret; \ - u8 num; \ - \ - mutex_lock(su_mutex); /* for navigating configfs hierarchy */ \ - \ - opts_item = u->fmt.group.cg_item.ci_parent->ci_parent->ci_parent;\ - opts = to_f_uvc_opts(opts_item); \ - \ - mutex_lock(&opts->lock); \ - if (u->fmt.linked || opts->refcnt) { \ - ret = -EBUSY; \ - goto end; \ - } \ - \ - ret = kstrtou8(page, 0, &num); \ - if (ret) \ - goto end; \ - \ - if (num > 255) { \ - ret = -EINVAL; \ - goto end; \ - } \ - u->desc.aname = num; \ - ret = len; \ -end: \ - mutex_unlock(&opts->lock); \ - mutex_unlock(su_mutex); \ - return ret; \ -} \ - \ -UVC_ATTR(uvcg_framebased_, cname, aname) - -UVCG_FRAMEBASED_ATTR_RO(b_format_index, bFormatIndex, 8); -UVCG_FRAMEBASED_ATTR_RO(b_bits_per_pixel, bBitsPerPixel, 8); -UVCG_FRAMEBASED_ATTR(b_default_frame_index, bDefaultFrameIndex, 8); -UVCG_FRAMEBASED_ATTR_RO(b_aspect_ratio_x, bAspectRatioX, 8); -UVCG_FRAMEBASED_ATTR_RO(b_aspect_ratio_y, bAspectRatioY, 8); -UVCG_FRAMEBASED_ATTR_RO(bm_interface_flags, bmInterfaceFlags, 8); - -#undef UVCG_FRAMEBASED_ATTR -#undef UVCG_FRAMEBASED_ATTR_RO - -static ssize_t uvcg_framebased_guid_format_show(struct config_item *item, - char *page) -{ - struct uvcg_framebased *ch = to_uvcg_framebased(item); - struct f_uvc_opts *opts; - struct config_item *opts_item; - struct mutex *su_mutex = &ch->fmt.group.cg_subsys->su_mutex; - - mutex_lock(su_mutex); /* for navigating configfs hierarchy */ - - opts_item = ch->fmt.group.cg_item.ci_parent->ci_parent->ci_parent; - opts = to_f_uvc_opts(opts_item); - - mutex_lock(&opts->lock); - memcpy(page, ch->desc.guidFormat, sizeof(ch->desc.guidFormat)); - mutex_unlock(&opts->lock); - - mutex_unlock(su_mutex); - - return sizeof(ch->desc.guidFormat); -} - -static ssize_t uvcg_framebased_guid_format_store(struct config_item *item, - const char *page, size_t len) -{ - struct uvcg_framebased *ch = to_uvcg_framebased(item); - struct f_uvc_opts *opts; - struct config_item *opts_item; - struct mutex *su_mutex = &ch->fmt.group.cg_subsys->su_mutex; - int ret; - - mutex_lock(su_mutex); /* for navigating configfs hierarchy */ - - opts_item = ch->fmt.group.cg_item.ci_parent->ci_parent->ci_parent; - opts = to_f_uvc_opts(opts_item); - - mutex_lock(&opts->lock); - if (ch->fmt.linked || opts->refcnt) { - ret = -EBUSY; - goto end; - } - - memcpy(ch->desc.guidFormat, page, - min(sizeof(ch->desc.guidFormat), len)); - ret = sizeof(ch->desc.guidFormat); - -end: - mutex_unlock(&opts->lock); - mutex_unlock(su_mutex); - return ret; -} - -UVC_ATTR(uvcg_framebased_, guid_format, guidFormat); - - static inline ssize_t -uvcg_framebased_bma_controls_show(struct config_item *item, char *page) -{ - struct uvcg_framebased *u = to_uvcg_framebased(item); - - return uvcg_format_bma_controls_show(&u->fmt, page); -} - - static inline ssize_t -uvcg_framebased_bma_controls_store(struct config_item *item, - const char *page, size_t len) -{ - struct uvcg_framebased *u = to_uvcg_framebased(item); - - return uvcg_format_bma_controls_store(&u->fmt, page, len); -} - -UVC_ATTR(uvcg_framebased_, bma_controls, bmaControls); - -static struct configfs_attribute *uvcg_framebased_attrs[] = { - &uvcg_framebased_attr_b_format_index, - &uvcg_framebased_attr_b_default_frame_index, - &uvcg_framebased_attr_b_bits_per_pixel, - &uvcg_framebased_attr_b_aspect_ratio_x, - &uvcg_framebased_attr_b_aspect_ratio_y, - &uvcg_framebased_attr_bm_interface_flags, - &uvcg_framebased_attr_bma_controls, - &uvcg_framebased_attr_guid_format, - NULL, -}; - -static const struct config_item_type uvcg_framebased_type = { - .ct_item_ops = &uvcg_config_item_ops, - .ct_group_ops = &uvcg_framebased_group_ops, - .ct_attrs = uvcg_framebased_attrs, - .ct_owner = THIS_MODULE, -}; - -static struct config_group *uvcg_framebased_make(struct config_group *group, - const char *name) -{ - static char guid[] = { /*Declear frame based as H264 format*/ - 'H', '2', '6', '4', 0x00, 0x00, 0x10, 0x00, - 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71 - }; - struct uvcg_framebased *h; - - h = kzalloc(sizeof(*h), GFP_KERNEL); - if (!h) - return ERR_PTR(-ENOMEM); - - h->desc.bLength = UVC_DT_FORMAT_FRAMEBASED_SIZE; - h->desc.bDescriptorType = USB_DT_CS_INTERFACE; - h->desc.bDescriptorSubType = UVC_VS_FORMAT_FRAME_BASED; - memcpy(h->desc.guidFormat, guid, sizeof(guid)); - h->desc.bBitsPerPixel = 0; - h->desc.bDefaultFrameIndex = 1; - h->desc.bAspectRatioX = 0; - h->desc.bAspectRatioY = 0; - h->desc.bmInterfaceFlags = 0; - h->desc.bCopyProtect = 0; - h->desc.bVariableSize = 1; - - h->fmt.type = UVCG_FRAMEBASED; - config_group_init_type_name(&h->fmt.group, name, - &uvcg_framebased_type); - - return &h->fmt.group; -} - -static struct configfs_group_operations uvcg_framebased_grp_ops = { - .make_group = uvcg_framebased_make, -}; - -static const struct uvcg_config_group_type uvcg_framebased_grp_type = { - .type = { - .ct_item_ops = &uvcg_config_item_ops, - .ct_group_ops = &uvcg_framebased_grp_ops, - .ct_owner = THIS_MODULE, - }, - .name = "framebased", -}; - /* ----------------------------------------------------------------------------- * streaming/color_matching/default */ @@ -2284,7 +2001,6 @@ static int __uvcg_iter_strm_cls(struct uvcg_streaming_header *h, if (ret) return ret; grp = &f->fmt->group; - j = 0; list_for_each_entry(item, &grp->cg_children, ci_entry) { frm = to_uvcg_frame(item); ret = fun(frm, priv2, priv3, j++, UVCG_FRAME); @@ -2333,11 +2049,6 @@ static int __uvcg_cnt_strm(void *priv1, void *priv2, void *priv3, int n, container_of(fmt, struct uvcg_mjpeg, fmt); *size += sizeof(m->desc); - } else if (fmt->type == UVCG_FRAMEBASED) { - struct uvcg_framebased *f = - container_of(fmt, struct uvcg_framebased, fmt); - - *size += sizeof(f->desc); } else { return -EINVAL; } @@ -2348,11 +2059,6 @@ static int __uvcg_cnt_strm(void *priv1, void *priv2, void *priv3, int n, int sz = sizeof(frm->dw_frame_interval); *size += sizeof(frm->frame); - /* - * framebased has duplicate member with uncompressed and - * mjpeg, so minus it - */ - *size -= sizeof(u32); *size += frm->frame.b_frame_interval_type * sz; } break; @@ -2363,27 +2069,6 @@ static int __uvcg_cnt_strm(void *priv1, void *priv2, void *priv3, int n, return 0; } -static int __uvcg_copy_framebased_desc(void *dest, struct uvcg_frame *frm, - int sz) -{ - struct uvc_frame_framebased *desc = dest; - - desc->bLength = frm->frame.b_length; - desc->bDescriptorType = frm->frame.b_descriptor_type; - desc->bDescriptorSubType = frm->frame.b_descriptor_subtype; - desc->bFrameIndex = frm->frame.b_frame_index; - desc->bmCapabilities = frm->frame.bm_capabilities; - desc->wWidth = frm->frame.w_width; - desc->wHeight = frm->frame.w_height; - desc->dwMinBitRate = frm->frame.dw_min_bit_rate; - desc->dwMaxBitRate = frm->frame.dw_max_bit_rate; - desc->dwDefaultFrameInterval = frm->frame.dw_default_frame_interval; - desc->bFrameIntervalType = frm->frame.b_frame_interval_type; - desc->dwBytesPerLine = frm->frame.dw_bytes_perline; - - return 0; -} - /* * Fill an array of streaming descriptors. * @@ -2438,15 +2123,6 @@ static int __uvcg_fill_strm(void *priv1, void *priv2, void *priv3, int n, m->desc.bNumFrameDescriptors = fmt->num_frames; memcpy(*dest, &m->desc, sizeof(m->desc)); *dest += sizeof(m->desc); - } else if (fmt->type == UVCG_FRAMEBASED) { - struct uvcg_framebased *f = - container_of(fmt, struct uvcg_framebased, - fmt); - - f->desc.bFormatIndex = n + 1; - f->desc.bNumFrameDescriptors = fmt->num_frames; - memcpy(*dest, &f->desc, sizeof(f->desc)); - *dest += sizeof(f->desc); } else { return -EINVAL; } @@ -2456,11 +2132,8 @@ static int __uvcg_fill_strm(void *priv1, void *priv2, void *priv3, int n, struct uvcg_frame *frm = priv1; struct uvc_descriptor_header *h = *dest; - sz = sizeof(frm->frame) - 4; - if (frm->fmt_type != UVCG_FRAMEBASED) - memcpy(*dest, &frm->frame, sz); - else - __uvcg_copy_framebased_desc(*dest, frm, sz); + sz = sizeof(frm->frame); + memcpy(*dest, &frm->frame, sz); *dest += sz; sz = frm->frame.b_frame_interval_type * sizeof(*frm->dw_frame_interval); @@ -2472,9 +2145,6 @@ static int __uvcg_fill_strm(void *priv1, void *priv2, void *priv3, int n, else if (frm->fmt_type == UVCG_MJPEG) h->bLength = UVC_DT_FRAME_MJPEG_SIZE( frm->frame.b_frame_interval_type); - else if (frm->fmt_type == UVCG_FRAMEBASED) - h->bLength = UVC_DT_FRAME_FRAMEBASED_SIZE( - frm->frame.b_frame_interval_type); } break; } @@ -2687,7 +2357,6 @@ static const struct uvcg_config_group_type uvcg_streaming_grp_type = { &uvcg_streaming_header_grp_type, &uvcg_uncompressed_grp_type, &uvcg_mjpeg_grp_type, - &uvcg_framebased_grp_type, &uvcg_color_matching_grp_type, &uvcg_streaming_class_grp_type, NULL, diff --git a/drivers/usb/gadget/function/uvc_v4l2.c b/drivers/usb/gadget/function/uvc_v4l2.c index 49f1f2ad134e..495f0ec663ea 100644 --- a/drivers/usb/gadget/function/uvc_v4l2.c +++ b/drivers/usb/gadget/function/uvc_v4l2.c @@ -58,9 +58,6 @@ struct uvc_format { static struct uvc_format uvc_formats[] = { { 16, V4L2_PIX_FMT_YUYV }, { 0, V4L2_PIX_FMT_MJPEG }, - { 0, V4L2_PIX_FMT_H264 }, - { 12, V4L2_PIX_FMT_YUV420 }, - { 8, V4L2_PIX_FMT_GREY }, }; static int diff --git a/drivers/usb/host/max3421-hcd.c b/drivers/usb/host/max3421-hcd.c index cfdbe90f867e..5a21777197e9 100644 --- a/drivers/usb/host/max3421-hcd.c +++ b/drivers/usb/host/max3421-hcd.c @@ -1925,7 +1925,7 @@ error: if (hcd) { kfree(max3421_hcd->tx); kfree(max3421_hcd->rx); - if (!IS_ERR_OR_NULL(max3421_hcd->spi_thread)) + if (max3421_hcd->spi_thread) kthread_stop(max3421_hcd->spi_thread); usb_put_hcd(hcd); } diff --git a/drivers/usb/host/xhci-dbgcap.c b/drivers/usb/host/xhci-dbgcap.c index 4e65ebbaa09b..93e2cca5262d 100644 --- a/drivers/usb/host/xhci-dbgcap.c +++ b/drivers/usb/host/xhci-dbgcap.c @@ -975,15 +975,8 @@ int xhci_dbc_suspend(struct xhci_hcd *xhci) if (!dbc) return 0; - switch (dbc->state) { - case DS_ENABLED: - case DS_CONNECTED: - case DS_CONFIGURED: + if (dbc->state == DS_CONFIGURED) dbc->resume_required = 1; - break; - default: - break; - } xhci_dbc_stop(xhci); diff --git a/drivers/usb/mon/mon_bin.c b/drivers/usb/mon/mon_bin.c index 93998d328d9a..35483217b1f6 100644 --- a/drivers/usb/mon/mon_bin.c +++ b/drivers/usb/mon/mon_bin.c @@ -68,20 +68,18 @@ * The magic limit was calculated so that it allows the monitoring * application to pick data once in two ticks. This way, another application, * which presumably drives the bus, gets to hog CPU, yet we collect our data. - * - * Originally, for a 480 Mbit/s bus this required a buffer of about 1 MB. For - * modern 20 Gbps buses, this value increases to over 50 MB. The maximum - * buffer size is set to 64 MiB to accommodate this. + * If HZ is 100, a 480 mbit/s bus drives 614 KB every jiffy. USB has an + * enormous overhead built into the bus protocol, so we need about 1000 KB. * * This is still too much for most cases, where we just snoop a few * descriptor fetches for enumeration. So, the default is a "reasonable" - * amount for typical, low-throughput use cases. + * amount for systems with HZ=250 and incomplete bus saturation. * * XXX What about multi-megabyte URBs which take minutes to transfer? */ -#define BUFF_MAX CHUNK_ALIGN(64*1024*1024) -#define BUFF_DFL CHUNK_ALIGN(300*1024) -#define BUFF_MIN CHUNK_ALIGN(8*1024) +#define BUFF_MAX CHUNK_ALIGN(1200*1024) +#define BUFF_DFL CHUNK_ALIGN(300*1024) +#define BUFF_MIN CHUNK_ALIGN(8*1024) /* * The per-event API header (2 per URB). diff --git a/drivers/usb/phy/phy-twl6030-usb.c b/drivers/usb/phy/phy-twl6030-usb.c index 607c3f18356a..9337c30f0743 100644 --- a/drivers/usb/phy/phy-twl6030-usb.c +++ b/drivers/usb/phy/phy-twl6030-usb.c @@ -328,8 +328,9 @@ static int twl6030_set_vbus(struct phy_companion *comparator, bool enabled) static int twl6030_usb_probe(struct platform_device *pdev) { + u32 ret; struct twl6030_usb *twl; - int status, err, ret; + int status, err; struct device_node *np = pdev->dev.of_node; struct device *dev = &pdev->dev; diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index 4a93bfbe4c6c..a417d32bfc96 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -273,7 +273,6 @@ static void option_instat_callback(struct urb *urb); #define QUECTEL_PRODUCT_EM05CN 0x0312 #define QUECTEL_PRODUCT_EM05G_GR 0x0313 #define QUECTEL_PRODUCT_EM05G_RS 0x0314 -#define QUECTEL_PRODUCT_RG255C 0x0316 #define QUECTEL_PRODUCT_EM12 0x0512 #define QUECTEL_PRODUCT_RM500Q 0x0800 #define QUECTEL_PRODUCT_RM520N 0x0801 @@ -618,7 +617,6 @@ static void option_instat_callback(struct urb *urb); #define UNISOC_VENDOR_ID 0x1782 /* TOZED LT70-C based on UNISOC SL8563 uses UNISOC's vendor ID */ #define TOZED_PRODUCT_LT70C 0x4055 -#define UNISOC_PRODUCT_UIS7720 0x4064 /* Luat Air72*U series based on UNISOC UIS8910 uses UNISOC's vendor ID */ #define LUAT_PRODUCT_AIR720U 0x4e00 @@ -1272,9 +1270,6 @@ static const struct usb_device_id option_ids[] = { { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM500K, 0xff, 0x00, 0x00) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RG650V, 0xff, 0xff, 0x30) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RG650V, 0xff, 0, 0) }, - { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RG255C, 0xff, 0xff, 0x30) }, - { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RG255C, 0xff, 0, 0) }, - { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RG255C, 0xff, 0xff, 0x40) }, { USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_6001) }, { USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_CMU_300) }, @@ -1403,14 +1398,10 @@ static const struct usb_device_id option_ids[] = { .driver_info = RSVD(0) | NCTRL(3) }, { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x10a2, 0xff), /* Telit FN920C04 (MBIM) */ .driver_info = NCTRL(4) }, - { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x10a3, 0xff), /* Telit FN920C04 (ECM) */ - .driver_info = NCTRL(4) }, { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x10a4, 0xff), /* Telit FN20C04 (rmnet) */ .driver_info = RSVD(0) | NCTRL(3) }, { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x10a7, 0xff), /* Telit FN920C04 (MBIM) */ .driver_info = NCTRL(4) }, - { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x10a8, 0xff), /* Telit FN920C04 (ECM) */ - .driver_info = NCTRL(4) }, { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x10a9, 0xff), /* Telit FN20C04 (rmnet) */ .driver_info = RSVD(0) | NCTRL(2) | RSVD(3) | RSVD(4) }, { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x10aa, 0xff), /* Telit FN920C04 (MBIM) */ @@ -2123,12 +2114,6 @@ static const struct usb_device_id option_ids[] = { { USB_DEVICE_INTERFACE_CLASS(0x1e0e, 0x9003, 0xff) }, /* Simcom SIM7500/SIM7600 MBIM mode */ { USB_DEVICE_INTERFACE_CLASS(0x1e0e, 0x9011, 0xff), /* Simcom SIM7500/SIM7600 RNDIS mode */ .driver_info = RSVD(7) }, - { USB_DEVICE(0x1e0e, 0x9071), /* Simcom SIM8230 RMNET mode */ - .driver_info = RSVD(3) | RSVD(4) }, - { USB_DEVICE_INTERFACE_CLASS(0x1e0e, 0x9078, 0xff), /* Simcom SIM8230 ECM mode */ - .driver_info = RSVD(5) }, - { USB_DEVICE_INTERFACE_CLASS(0x1e0e, 0x907b, 0xff), /* Simcom SIM8230 RNDIS mode */ - .driver_info = RSVD(5) }, { USB_DEVICE_INTERFACE_CLASS(0x1e0e, 0x9205, 0xff) }, /* Simcom SIM7070/SIM7080/SIM7090 AT+ECM mode */ { USB_DEVICE_INTERFACE_CLASS(0x1e0e, 0x9206, 0xff) }, /* Simcom SIM7070/SIM7080/SIM7090 AT-only mode */ { USB_DEVICE(ALCATEL_VENDOR_ID, ALCATEL_PRODUCT_X060S_X200), @@ -2475,7 +2460,6 @@ static const struct usb_device_id option_ids[] = { { USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9291, 0xff, 0xff, 0x30) }, { USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9291, 0xff, 0xff, 0x40) }, { USB_DEVICE_AND_INTERFACE_INFO(UNISOC_VENDOR_ID, TOZED_PRODUCT_LT70C, 0xff, 0, 0) }, - { USB_DEVICE_AND_INTERFACE_INFO(UNISOC_VENDOR_ID, UNISOC_PRODUCT_UIS7720, 0xff, 0, 0) }, { USB_DEVICE_AND_INTERFACE_INFO(UNISOC_VENDOR_ID, LUAT_PRODUCT_AIR720U, 0xff, 0, 0) }, { USB_DEVICE_INTERFACE_CLASS(0x1bbb, 0x0530, 0xff), /* TCL IK512 MBIM */ .driver_info = NCTRL(1) }, diff --git a/drivers/usb/usbip/vhci_hcd.c b/drivers/usb/usbip/vhci_hcd.c index d31b7e5895ce..ee8fa558e3ed 100644 --- a/drivers/usb/usbip/vhci_hcd.c +++ b/drivers/usb/usbip/vhci_hcd.c @@ -765,17 +765,6 @@ static int vhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flag ctrlreq->wValue, vdev->rhport); vdev->udev = usb_get_dev(urb->dev); - /* - * NOTE: A similar operation has been done via - * USB_REQ_GET_DESCRIPTOR handler below, which is - * supposed to always precede USB_REQ_SET_ADDRESS. - * - * It's not entirely clear if operating on a different - * usb_device instance here is a real possibility, - * otherwise this call and vdev->udev assignment above - * should be dropped. - */ - dev_pm_syscore_device(&vdev->udev->dev, true); usb_put_dev(old); spin_lock(&vdev->ud.lock); @@ -796,17 +785,6 @@ static int vhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flag "Not yet?:Get_Descriptor to device 0 (get max pipe size)\n"); vdev->udev = usb_get_dev(urb->dev); - /* - * Set syscore PM flag for the virtually attached - * devices to ensure they will not enter suspend on - * the client side. - * - * Note this doesn't have any impact on the physical - * devices attached to the host system on the server - * side, hence there is no need to undo the operation - * on disconnect. - */ - dev_pm_syscore_device(&vdev->udev->dev, true); usb_put_dev(old); goto out; diff --git a/drivers/video/backlight/lp855x_bl.c b/drivers/video/backlight/lp855x_bl.c index 80a4b12563c6..e94932c69f54 100644 --- a/drivers/video/backlight/lp855x_bl.c +++ b/drivers/video/backlight/lp855x_bl.c @@ -21,7 +21,7 @@ #define LP855X_DEVICE_CTRL 0x01 #define LP855X_EEPROM_START 0xA0 #define LP855X_EEPROM_END 0xA7 -#define LP8556_EPROM_START 0x98 +#define LP8556_EPROM_START 0xA0 #define LP8556_EPROM_END 0xAF /* LP8555/7 Registers */ diff --git a/drivers/video/fbdev/aty/atyfb_base.c b/drivers/video/fbdev/aty/atyfb_base.c index 87b7702330b1..bb9ecf12e763 100644 --- a/drivers/video/fbdev/aty/atyfb_base.c +++ b/drivers/video/fbdev/aty/atyfb_base.c @@ -2576,12 +2576,8 @@ static int aty_init(struct fb_info *info) pr_cont("\n"); } #endif - if (par->pll_ops->init_pll) { - ret = par->pll_ops->init_pll(info, &par->pll); - if (ret) - return ret; - } - + if (par->pll_ops->init_pll) + par->pll_ops->init_pll(info, &par->pll); if (par->pll_ops->resume_pll) par->pll_ops->resume_pll(info, &par->pll); diff --git a/drivers/video/fbdev/core/bitblit.c b/drivers/video/fbdev/core/bitblit.c index 75c20f8e58e3..5bb2b07cbe1a 100644 --- a/drivers/video/fbdev/core/bitblit.c +++ b/drivers/video/fbdev/core/bitblit.c @@ -80,16 +80,12 @@ static inline void bit_putcs_aligned(struct vc_data *vc, struct fb_info *info, struct fb_image *image, u8 *buf, u8 *dst) { u16 charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff; - unsigned int charcnt = vc->vc_font.charcount; u32 idx = vc->vc_font.width >> 3; u8 *src; while (cnt--) { - u16 ch = scr_readw(s++) & charmask; - - if (ch >= charcnt) - ch = 0; - src = vc->vc_font.data + (unsigned int)ch * cellsize; + src = vc->vc_font.data + (scr_readw(s++)& + charmask)*cellsize; if (attr) { update_attr(buf, src, attr, vc); @@ -117,18 +113,14 @@ static inline void bit_putcs_unaligned(struct vc_data *vc, u8 *dst) { u16 charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff; - unsigned int charcnt = vc->vc_font.charcount; u32 shift_low = 0, mod = vc->vc_font.width % 8; u32 shift_high = 8; u32 idx = vc->vc_font.width >> 3; u8 *src; while (cnt--) { - u16 ch = scr_readw(s++) & charmask; - - if (ch >= charcnt) - ch = 0; - src = vc->vc_font.data + (unsigned int)ch * cellsize; + src = vc->vc_font.data + (scr_readw(s++)& + charmask)*cellsize; if (attr) { update_attr(buf, src, attr, vc); @@ -169,11 +161,6 @@ static void bit_putcs(struct vc_data *vc, struct fb_info *info, image.height = vc->vc_font.height; image.depth = 1; - if (image.dy >= info->var.yres) - return; - - image.height = min(image.height, info->var.yres - image.dy); - if (attribute) { buf = kmalloc(cellsize, GFP_ATOMIC); if (!buf) @@ -187,18 +174,6 @@ static void bit_putcs(struct vc_data *vc, struct fb_info *info, cnt = count; image.width = vc->vc_font.width * cnt; - - if (image.dx >= info->var.xres) - break; - - if (image.dx + image.width > info->var.xres) { - image.width = info->var.xres - image.dx; - cnt = image.width / vc->vc_font.width; - if (cnt == 0) - break; - image.width = cnt * vc->vc_font.width; - } - pitch = DIV_ROUND_UP(image.width, 8) + scan_align; pitch &= ~scan_align; size = pitch * image.height + buf_align; diff --git a/drivers/video/fbdev/hpfb.c b/drivers/video/fbdev/hpfb.c index 8992e9d5b4e5..40e51a2fc34d 100644 --- a/drivers/video/fbdev/hpfb.c +++ b/drivers/video/fbdev/hpfb.c @@ -403,7 +403,7 @@ int __init hpfb_init(void) if (err) return err; - err = copy_from_kernel_nofault(&i, (unsigned char *)INTFBVADDR + DIO_IDOFF, 1); + err = probe_kernel_read(&i, (unsigned char *)INTFBVADDR + DIO_IDOFF, 1); if (!err && (i == DIO_ID_FBUFFER) && topcat_sid_ok(sid = DIO_SECID(INTFBVADDR))) { if (!request_mem_region(INTFBPADDR, DIO_DEVSIZE, "Internal Topcat")) diff --git a/drivers/video/fbdev/pvr2fb.c b/drivers/video/fbdev/pvr2fb.c index efdb325461a2..c916e9161443 100644 --- a/drivers/video/fbdev/pvr2fb.c +++ b/drivers/video/fbdev/pvr2fb.c @@ -191,7 +191,7 @@ static unsigned long pvr2fb_map; #ifdef CONFIG_PVR2_DMA static unsigned int shdma = PVR2_CASCADE_CHAN; -static unsigned int pvr2dma = CONFIG_NR_ONCHIP_DMA_CHANNELS; +static unsigned int pvr2dma = ONCHIP_NR_DMA_CHANNELS; #endif static struct fb_videomode pvr2_modedb[] = { diff --git a/drivers/video/fbdev/valkyriefb.c b/drivers/video/fbdev/valkyriefb.c index 152b6db0c8f9..e04fde9c1fcd 100644 --- a/drivers/video/fbdev/valkyriefb.c +++ b/drivers/video/fbdev/valkyriefb.c @@ -336,13 +336,11 @@ int __init valkyriefb_init(void) if (of_address_to_resource(dp, 0, &r)) { printk(KERN_ERR "can't find address for valkyrie\n"); - of_node_put(dp); return 0; } frame_buffer_phys = r.start; cmap_regs_phys = r.start + 0x304000; - of_node_put(dp); } #endif /* ppc (!CONFIG_MAC) */ diff --git a/drivers/virt/fsl_hypervisor.c b/drivers/virt/fsl_hypervisor.c index 46ee0a0998b6..fb292f9cf29d 100644 --- a/drivers/virt/fsl_hypervisor.c +++ b/drivers/virt/fsl_hypervisor.c @@ -705,7 +705,7 @@ static const struct file_operations fsl_hv_fops = { .poll = fsl_hv_poll, .read = fsl_hv_read, .unlocked_ioctl = fsl_hv_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = fsl_hv_ioctl, }; static struct miscdevice fsl_hv_misc_dev = { diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c index 18349ec0c101..3fc457bc16db 100644 --- a/drivers/watchdog/mpc8xxx_wdt.c +++ b/drivers/watchdog/mpc8xxx_wdt.c @@ -100,8 +100,6 @@ static int mpc8xxx_wdt_start(struct watchdog_device *w) ddata->swtc = tmp >> 16; set_bit(WDOG_HW_RUNNING, &ddata->wdd.status); - mpc8xxx_wdt_keepalive(ddata); - return 0; } diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c index 5baa185c323c..f8554d9a9f28 100644 --- a/drivers/xen/events/events_base.c +++ b/drivers/xen/events/events_base.c @@ -1210,12 +1210,10 @@ EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irq_lateeoi); static int find_virq(unsigned int virq, unsigned int cpu) { struct evtchn_status status; - int port; + int port, rc = -ENOENT; memset(&status, 0, sizeof(status)); for (port = 0; port < xen_evtchn_max_channels(); port++) { - int rc; - status.dom = DOMID_SELF; status.port = port; rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status); @@ -1223,10 +1221,12 @@ static int find_virq(unsigned int virq, unsigned int cpu) continue; if (status.status != EVTCHNSTAT_virq) continue; - if (status.u.virq == virq && status.vcpu == xen_vcpu_nr(cpu)) - return port; + if (status.u.virq == virq && status.vcpu == xen_vcpu_nr(cpu)) { + rc = port; + break; + } } - return -ENOENT; + return rc; } /** @@ -1717,20 +1717,9 @@ static int xen_rebind_evtchn_to_cpu(struct irq_info *info, unsigned int tcpu) * virq or IPI channel, which don't actually need to be rebound. Ignore * it, but don't do the xenlinux-level rebind in that case. */ - if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) { - int old_cpu = info->cpu; - + if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) bind_evtchn_to_cpu(evtchn, tcpu); - if (info->type == IRQT_VIRQ) { - int virq = info->u.virq; - int irq = per_cpu(virq_to_irq, old_cpu)[virq]; - - per_cpu(virq_to_irq, old_cpu)[virq] = -1; - per_cpu(virq_to_irq, tcpu)[virq] = irq; - } - } - do_unmask(info, EVT_MASK_REASON_TEMPORARY); return 0; diff --git a/drivers/xen/manage.c b/drivers/xen/manage.c index 86341bd5f6e4..cd046684e0d1 100644 --- a/drivers/xen/manage.c +++ b/drivers/xen/manage.c @@ -116,7 +116,7 @@ static void do_suspend(void) err = dpm_suspend_start(PMSG_FREEZE); if (err) { pr_err("%s: dpm_suspend_start %d\n", __func__, err); - goto out_resume_end; + goto out_thaw; } printk(KERN_DEBUG "suspending xenstore...\n"); @@ -156,7 +156,6 @@ out_resume: else xs_suspend_cancel(); -out_resume_end: dpm_resume_end(si.cancelled ? PMSG_THAW : PMSG_RESTORE); out_thaw: diff --git a/fs/9p/v9fs.c b/fs/9p/v9fs.c index 1dd8a735bf7f..39def020a074 100644 --- a/fs/9p/v9fs.c +++ b/fs/9p/v9fs.c @@ -558,7 +558,7 @@ static ssize_t caches_show(struct kobject *kobj, spin_lock(&v9fs_sessionlist_lock); list_for_each_entry(v9ses, &v9fs_sessionlist, slist) { if (v9ses->cachetag) { - n = snprintf(buf + count, limit, "%s\n", v9ses->cachetag); + n = snprintf(buf, limit, "%s\n", v9ses->cachetag); if (n < 0) { count = n; break; @@ -594,16 +594,13 @@ static struct attribute_group v9fs_attr_group = { static int __init v9fs_sysfs_init(void) { - int ret; - v9fs_kobj = kobject_create_and_add("9p", fs_kobj); if (!v9fs_kobj) return -ENOMEM; - ret = sysfs_create_group(v9fs_kobj, &v9fs_attr_group); - if (ret) { + if (sysfs_create_group(v9fs_kobj, &v9fs_attr_group)) { kobject_put(v9fs_kobj); - return ret; + return -ENOMEM; } return 0; diff --git a/fs/9p/vfs_inode.c b/fs/9p/vfs_inode.c index 4446e83aea7a..ffce168296bd 100644 --- a/fs/9p/vfs_inode.c +++ b/fs/9p/vfs_inode.c @@ -455,7 +455,7 @@ static int v9fs_test_inode(struct inode *inode, void *data) umode = p9mode2unixmode(v9ses, st, &rdev); /* don't match inode of different type */ - if (inode_wrong_type(inode, umode)) + if ((inode->i_mode & S_IFMT) != (umode & S_IFMT)) return 0; /* compare qid details */ @@ -1412,7 +1412,7 @@ int v9fs_refresh_inode(struct p9_fid *fid, struct inode *inode) * Don't update inode if the file type is different */ umode = p9mode2unixmode(v9ses, st, &rdev); - if (inode_wrong_type(inode, umode)) + if ((inode->i_mode & S_IFMT) != (umode & S_IFMT)) goto out; /* diff --git a/fs/9p/vfs_inode_dotl.c b/fs/9p/vfs_inode_dotl.c index 614f23a9d2bc..9795fe0f1ba2 100644 --- a/fs/9p/vfs_inode_dotl.c +++ b/fs/9p/vfs_inode_dotl.c @@ -59,7 +59,7 @@ static int v9fs_test_inode_dotl(struct inode *inode, void *data) struct p9_stat_dotl *st = (struct p9_stat_dotl *)data; /* don't match inode of different type */ - if (inode_wrong_type(inode, st->st_mode)) + if ((inode->i_mode & S_IFMT) != (st->st_mode & S_IFMT)) return 0; if (inode->i_generation != st->st_gen) @@ -924,7 +924,7 @@ int v9fs_refresh_inode_dotl(struct p9_fid *fid, struct inode *inode) /* * Don't update inode if the file type is different */ - if (inode_wrong_type(inode, st->st_mode)) + if ((inode->i_mode & S_IFMT) != (st->st_mode & S_IFMT)) goto out; /* diff --git a/fs/9p/vfs_super.c b/fs/9p/vfs_super.c index c226d876383d..46e58fdf9ba5 100644 --- a/fs/9p/vfs_super.c +++ b/fs/9p/vfs_super.c @@ -80,10 +80,8 @@ v9fs_fill_super(struct super_block *sb, struct v9fs_session_info *v9ses, if (ret) return ret; - if (!v9ses->cache) { - sb->s_bdi->ra_pages = 0; - sb->s_bdi->io_pages = 0; - } + if (v9ses->cache) + sb->s_bdi->ra_pages = VM_READAHEAD_PAGES; sb->s_flags |= SB_ACTIVE | SB_DIRSYNC; if (!v9ses->cache) diff --git a/fs/afs/super.c b/fs/afs/super.c index f432713872e3..554119068ea4 100644 --- a/fs/afs/super.c +++ b/fs/afs/super.c @@ -449,6 +449,7 @@ static int afs_fill_super(struct super_block *sb, struct afs_fs_context *ctx) ret = super_setup_bdi(sb); if (ret) return ret; + sb->s_bdi->ra_pages = VM_READAHEAD_PAGES; /* allocate the root inode and dentry */ if (as->dyn_root) { diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index 176ba981f055..660544fc0781 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -3008,6 +3008,7 @@ int open_ctree(struct super_block *sb, sb->s_bdi->congested_fn = btrfs_congested_fn; sb->s_bdi->congested_data = fs_info; sb->s_bdi->capabilities |= BDI_CAP_CGROUP_WRITEBACK; + sb->s_bdi->ra_pages = VM_READAHEAD_PAGES; sb->s_bdi->ra_pages *= btrfs_super_num_devices(disk_super); sb->s_bdi->ra_pages = max(sb->s_bdi->ra_pages, SZ_4M / PAGE_SIZE); diff --git a/fs/btrfs/export.c b/fs/btrfs/export.c index c244b4cc8ba1..08d1d456e2f0 100644 --- a/fs/btrfs/export.c +++ b/fs/btrfs/export.c @@ -22,11 +22,7 @@ static int btrfs_encode_fh(struct inode *inode, u32 *fh, int *max_len, int type; if (parent && (len < BTRFS_FID_SIZE_CONNECTABLE)) { - if (BTRFS_I(inode)->root->root_key.objectid != - BTRFS_I(parent)->root->root_key.objectid) - *max_len = BTRFS_FID_SIZE_CONNECTABLE_ROOT; - else - *max_len = BTRFS_FID_SIZE_CONNECTABLE; + *max_len = BTRFS_FID_SIZE_CONNECTABLE; return FILEID_INVALID; } else if (len < BTRFS_FID_SIZE_NON_CONNECTABLE) { *max_len = BTRFS_FID_SIZE_NON_CONNECTABLE; @@ -48,8 +44,6 @@ static int btrfs_encode_fh(struct inode *inode, u32 *fh, int *max_len, parent_root_id = BTRFS_I(parent)->root->root_key.objectid; if (parent_root_id != fid->root_objectid) { - if (*max_len < BTRFS_FID_SIZE_CONNECTABLE_ROOT) - return FILEID_INVALID; fid->parent_root_objectid = parent_root_id; len = BTRFS_FID_SIZE_CONNECTABLE_ROOT; type = FILEID_BTRFS_WITH_PARENT_ROOT; diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c index daa0c0467991..e271f1f8c601 100644 --- a/fs/btrfs/super.c +++ b/fs/btrfs/super.c @@ -2322,7 +2322,7 @@ static const struct super_operations btrfs_super_ops = { static const struct file_operations btrfs_ctl_fops = { .open = btrfs_control_open, .unlocked_ioctl = btrfs_control_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = btrfs_control_ioctl, .owner = THIS_MODULE, .llseek = noop_llseek, }; diff --git a/fs/btrfs/transaction.c b/fs/btrfs/transaction.c index 6618b42defed..094b024bbf0c 100644 --- a/fs/btrfs/transaction.c +++ b/fs/btrfs/transaction.c @@ -1546,7 +1546,7 @@ static noinline int create_pending_snapshot(struct btrfs_trans_handle *trans, } /* see comments in should_cow_block() */ set_bit(BTRFS_ROOT_FORCE_COW, &root->state); - smp_mb__after_atomic(); + smp_wmb(); btrfs_set_root_node(new_root_item, tmp); /* record when the snapshot was created in key.offset */ diff --git a/fs/ceph/locks.c b/fs/ceph/locks.c index d93515c2fa56..544e9e85b120 100644 --- a/fs/ceph/locks.c +++ b/fs/ceph/locks.c @@ -206,10 +206,7 @@ static int ceph_lock_wait_for_completion(struct ceph_mds_client *mdsc, if (err && err != -ERESTARTSYS) return err; - err = wait_for_completion_killable(&req->r_safe_completion); - if (err) - return err; - + wait_for_completion_killable(&req->r_safe_completion); return 0; } diff --git a/fs/cifs/inode.c b/fs/cifs/inode.c index 932aa65182b3..af0980c720c7 100644 --- a/fs/cifs/inode.c +++ b/fs/cifs/inode.c @@ -420,7 +420,8 @@ int cifs_get_inode_info_unix(struct inode **pinode, } /* if filetype is different, return error */ - if (unlikely(inode_wrong_type(*pinode, fattr.cf_mode))) { + if (unlikely(((*pinode)->i_mode & S_IFMT) != + (fattr.cf_mode & S_IFMT))) { CIFS_I(*pinode)->time = 0; /* force reval */ rc = -ESTALE; goto cgiiu_exit; @@ -979,7 +980,7 @@ cifs_find_inode(struct inode *inode, void *opaque) return 0; /* don't match inode of different type */ - if (inode_wrong_type(inode, fattr->cf_mode)) + if ((inode->i_mode & S_IFMT) != (fattr->cf_mode & S_IFMT)) return 0; /* if it's not a directory or has no dentries, then flag it */ diff --git a/fs/cramfs/inode.c b/fs/cramfs/inode.c index 82c45ca45321..2f04024c3588 100644 --- a/fs/cramfs/inode.c +++ b/fs/cramfs/inode.c @@ -117,18 +117,9 @@ static struct inode *get_cramfs_inode(struct super_block *sb, inode_nohighmem(inode); inode->i_data.a_ops = &cramfs_aops; break; - case S_IFCHR: - case S_IFBLK: - case S_IFIFO: - case S_IFSOCK: + default: init_special_inode(inode, cramfs_inode->mode, old_decode_dev(cramfs_inode->size)); - break; - default: - printk(KERN_DEBUG "CRAMFS: Invalid file type 0%04o for inode %lu.\n", - inode->i_mode, inode->i_ino); - iget_failed(inode); - return ERR_PTR(-EIO); } inode->i_mode = cramfs_inode->mode; diff --git a/fs/dcache.c b/fs/dcache.c index f1e1b14c3cb1..78081bdc4931 100644 --- a/fs/dcache.c +++ b/fs/dcache.c @@ -165,7 +165,7 @@ static long get_nr_dentry_negative(void) return sum < 0 ? 0 : sum; } -int proc_nr_dentry(struct ctl_table *table, int write, void *buffer, +int proc_nr_dentry(struct ctl_table *table, int write, void __user *buffer, size_t *lenp, loff_t *ppos) { dentry_stat.nr_dentry = get_nr_dentry(); @@ -1782,8 +1782,6 @@ struct dentry *d_alloc(struct dentry * parent, const struct qstr *name) __dget_dlock(parent); dentry->d_parent = parent; list_add(&dentry->d_child, &parent->d_subdirs); - if (parent->d_flags & DCACHE_DISCONNECTED) - dentry->d_flags |= DCACHE_DISCONNECTED; spin_unlock(&parent->d_lock); return dentry; diff --git a/fs/dlm/lockspace.c b/fs/dlm/lockspace.c index 9030e0e5927c..c689359ca532 100644 --- a/fs/dlm/lockspace.c +++ b/fs/dlm/lockspace.c @@ -793,7 +793,7 @@ static int release_lockspace(struct dlm_ls *ls, int force) dlm_device_deregister(ls); - if (force != 3 && dlm_user_daemon_available()) + if (force < 3 && dlm_user_daemon_available()) do_uevent(ls, 0); dlm_recoverd_stop(ls); diff --git a/fs/drop_caches.c b/fs/drop_caches.c index f00fcc4a4f72..dc1a1d5d825b 100644 --- a/fs/drop_caches.c +++ b/fs/drop_caches.c @@ -47,7 +47,7 @@ static void drop_pagecache_sb(struct super_block *sb, void *unused) } int drop_caches_sysctl_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos) + void __user *buffer, size_t *length, loff_t *ppos) { int ret; diff --git a/fs/eventpoll.c b/fs/eventpoll.c index b78134c4c5bf..21f290bac813 100644 --- a/fs/eventpoll.c +++ b/fs/eventpoll.c @@ -1803,25 +1803,15 @@ static int ep_send_events(struct eventpoll *ep, return esed.res; } -static struct timespec64 *ep_timeout_to_timespec(struct timespec64 *to, long ms) +static inline struct timespec64 ep_set_mstimeout(long ms) { - struct timespec64 now; - - if (ms < 0) - return NULL; - - if (!ms) { - to->tv_sec = 0; - to->tv_nsec = 0; - return to; - } - - to->tv_sec = ms / MSEC_PER_SEC; - to->tv_nsec = NSEC_PER_MSEC * (ms % MSEC_PER_SEC); + struct timespec64 now, ts = { + .tv_sec = ms / MSEC_PER_SEC, + .tv_nsec = NSEC_PER_MSEC * (ms % MSEC_PER_SEC), + }; ktime_get_ts64(&now); - *to = timespec64_add_safe(now, *to); - return to; + return timespec64_add_safe(now, ts); } /* @@ -1852,8 +1842,8 @@ static int ep_autoremove_wake_function(struct wait_queue_entry *wq_entry, * stored. * @maxevents: Size (in terms of number of events) of the caller event buffer. * @timeout: Maximum timeout for the ready events fetch operation, in - * timespec. If the timeout is zero, the function will not block, - * while if the @timeout ptr is NULL, the function will block + * milliseconds. If the @timeout is zero, the function will not block, + * while if the @timeout is less than zero, the function will block * until at least one event has been retrieved (or an error * occurred). * @@ -1861,7 +1851,7 @@ static int ep_autoremove_wake_function(struct wait_queue_entry *wq_entry, * error code, in case of error. */ static int ep_poll(struct eventpoll *ep, struct epoll_event __user *events, - int maxevents, struct timespec64 *timeout) + int maxevents, long timeout) { int res = 0, eavail, timed_out = 0; u64 slack = 0; @@ -1870,11 +1860,13 @@ static int ep_poll(struct eventpoll *ep, struct epoll_event __user *events, lockdep_assert_irqs_enabled(); - if (timeout && (timeout->tv_sec | timeout->tv_nsec)) { - slack = select_estimate_accuracy(timeout); + if (timeout > 0) { + struct timespec64 end_time = ep_set_mstimeout(timeout); + + slack = select_estimate_accuracy(&end_time); to = &expires; - *to = timespec64_to_ktime(*timeout); - } else if (timeout) { + *to = timespec64_to_ktime(end_time); + } else if (timeout == 0) { /* * Avoid the unnecessary trip to the wait queue loop, if the * caller specified a non blocking operation. We still need @@ -2313,7 +2305,7 @@ error_return: * part of the user space epoll_wait(2). */ static int do_epoll_wait(int epfd, struct epoll_event __user *events, - int maxevents, struct timespec64 *to) + int maxevents, int timeout) { int error; struct fd f; @@ -2347,7 +2339,7 @@ static int do_epoll_wait(int epfd, struct epoll_event __user *events, ep = f.file->private_data; /* Time to fish for events ... */ - error = ep_poll(ep, events, maxevents, to); + error = ep_poll(ep, events, maxevents, timeout); error_fput: fdput(f); @@ -2357,19 +2349,16 @@ error_fput: SYSCALL_DEFINE4(epoll_wait, int, epfd, struct epoll_event __user *, events, int, maxevents, int, timeout) { - struct timespec64 to; - - return do_epoll_wait(epfd, events, maxevents, - ep_timeout_to_timespec(&to, timeout)); + return do_epoll_wait(epfd, events, maxevents, timeout); } /* * Implement the event wait interface for the eventpoll file. It is the kernel * part of the user space epoll_pwait(2). */ -static int do_epoll_pwait(int epfd, struct epoll_event __user *events, - int maxevents, struct timespec64 *to, - const sigset_t __user *sigmask, size_t sigsetsize) +SYSCALL_DEFINE6(epoll_pwait, int, epfd, struct epoll_event __user *, events, + int, maxevents, int, timeout, const sigset_t __user *, sigmask, + size_t, sigsetsize) { int error; @@ -2381,47 +2370,18 @@ static int do_epoll_pwait(int epfd, struct epoll_event __user *events, if (error) return error; - error = do_epoll_wait(epfd, events, maxevents, to); - + error = do_epoll_wait(epfd, events, maxevents, timeout); restore_saved_sigmask_unless(error == -EINTR); return error; } -SYSCALL_DEFINE6(epoll_pwait, int, epfd, struct epoll_event __user *, events, - int, maxevents, int, timeout, const sigset_t __user *, sigmask, - size_t, sigsetsize) -{ - struct timespec64 to; - - return do_epoll_pwait(epfd, events, maxevents, - ep_timeout_to_timespec(&to, timeout), - sigmask, sigsetsize); -} - -SYSCALL_DEFINE6(epoll_pwait2, int, epfd, struct epoll_event __user *, events, - int, maxevents, const struct __kernel_timespec __user *, timeout, - const sigset_t __user *, sigmask, size_t, sigsetsize) -{ - struct timespec64 ts, *to = NULL; - - if (timeout) { - if (get_timespec64(&ts, timeout)) - return -EFAULT; - to = &ts; - if (poll_select_set_timeout(to, ts.tv_sec, ts.tv_nsec)) - return -EINVAL; - } - - return do_epoll_pwait(epfd, events, maxevents, to, - sigmask, sigsetsize); -} - #ifdef CONFIG_COMPAT -static int do_compat_epoll_pwait(int epfd, struct epoll_event __user *events, - int maxevents, struct timespec64 *timeout, - const compat_sigset_t __user *sigmask, - compat_size_t sigsetsize) +COMPAT_SYSCALL_DEFINE6(epoll_pwait, int, epfd, + struct epoll_event __user *, events, + int, maxevents, int, timeout, + const compat_sigset_t __user *, sigmask, + compat_size_t, sigsetsize) { long err; @@ -2434,46 +2394,10 @@ static int do_compat_epoll_pwait(int epfd, struct epoll_event __user *events, return err; err = do_epoll_wait(epfd, events, maxevents, timeout); - restore_saved_sigmask_unless(err == -EINTR); return err; } - -COMPAT_SYSCALL_DEFINE6(epoll_pwait, int, epfd, - struct epoll_event __user *, events, - int, maxevents, int, timeout, - const compat_sigset_t __user *, sigmask, - compat_size_t, sigsetsize) -{ - struct timespec64 to; - - return do_compat_epoll_pwait(epfd, events, maxevents, - ep_timeout_to_timespec(&to, timeout), - sigmask, sigsetsize); -} - -COMPAT_SYSCALL_DEFINE6(epoll_pwait2, int, epfd, - struct epoll_event __user *, events, - int, maxevents, - const struct __kernel_timespec __user *, timeout, - const compat_sigset_t __user *, sigmask, - compat_size_t, sigsetsize) -{ - struct timespec64 ts, *to = NULL; - - if (timeout) { - if (get_timespec64(&ts, timeout)) - return -EFAULT; - to = &ts; - if (poll_select_set_timeout(to, ts.tv_sec, ts.tv_nsec)) - return -EINVAL; - } - - return do_compat_epoll_pwait(epfd, events, maxevents, to, - sigmask, sigsetsize); -} - #endif static int __init eventpoll_init(void) diff --git a/fs/exec.c b/fs/exec.c index 910b407d267e..d50d65857823 100644 --- a/fs/exec.c +++ b/fs/exec.c @@ -701,7 +701,7 @@ int setup_arg_pages(struct linux_binprm *bprm, unsigned long stack_top, int executable_stack) { - int ret; + unsigned long ret; unsigned long stack_shift; struct mm_struct *mm = current->mm; struct vm_area_struct *vma = bprm->vma; diff --git a/fs/ext4/fsmap.c b/fs/ext4/fsmap.c index 00b929ab0b68..bdc194b8f4de 100644 --- a/fs/ext4/fsmap.c +++ b/fs/ext4/fsmap.c @@ -74,8 +74,7 @@ static int ext4_getfsmap_dev_compare(const void *p1, const void *p2) static bool ext4_getfsmap_rec_before_low_key(struct ext4_getfsmap_info *info, struct ext4_fsmap *rec) { - return rec->fmr_physical + rec->fmr_length <= - info->gfi_low.fmr_physical; + return rec->fmr_physical < info->gfi_low.fmr_physical; } /* @@ -201,18 +200,15 @@ static int ext4_getfsmap_meta_helper(struct super_block *sb, ext4_group_first_block_no(sb, agno)); fs_end = fs_start + EXT4_C2B(sbi, len); - /* - * Return relevant extents from the meta_list. We emit all extents that - * partially/fully overlap with the query range - */ + /* Return relevant extents from the meta_list */ list_for_each_entry_safe(p, tmp, &info->gfi_meta_list, fmr_list) { - if (p->fmr_physical + p->fmr_length <= info->gfi_next_fsblk) { + if (p->fmr_physical < info->gfi_next_fsblk) { list_del(&p->fmr_list); kfree(p); continue; } - if (p->fmr_physical <= fs_end && - p->fmr_physical + p->fmr_length > fs_start) { + if (p->fmr_physical <= fs_start || + p->fmr_physical + p->fmr_length <= fs_end) { /* Emit the retained free extent record if present */ if (info->gfi_lastfree.fmr_owner) { error = ext4_getfsmap_helper(sb, info, diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c index 5373799ac224..1514eddaa1ca 100644 --- a/fs/ext4/inode.c +++ b/fs/ext4/inode.c @@ -4301,11 +4301,7 @@ int ext4_can_truncate(struct inode *inode) * We have to make sure i_disksize gets properly updated before we truncate * page cache due to hole punching or zero range. Otherwise i_disksize update * can get lost as it may have been postponed to submission of writeback but - * that will never happen if we remove the folio containing i_size from the - * page cache. Also if we punch hole within i_size but above i_disksize, - * following ext4_page_mkwrite() may mistakenly allocate written blocks over - * the hole and thus introduce allocated blocks beyond i_disksize which is - * not allowed (e2fsck would complain in case of crash). + * that will never happen after we truncate page cache. */ int ext4_update_disksize_before_punch(struct inode *inode, loff_t offset, loff_t len) @@ -4314,11 +4310,9 @@ int ext4_update_disksize_before_punch(struct inode *inode, loff_t offset, loff_t size = i_size_read(inode); WARN_ON(!inode_is_locked(inode)); - if (offset > size) + if (offset > size || offset + len < size) return 0; - if (offset + len < size) - size = offset + len; if (EXT4_I(inode)->i_disksize >= size) return 0; @@ -5131,14 +5125,6 @@ struct inode *__ext4_iget(struct super_block *sb, unsigned long ino, } ei->i_flags = le32_to_cpu(raw_inode->i_flags); ext4_set_inode_flags(inode); - /* Detect invalid flag combination - can't have both inline data and extents */ - if (ext4_test_inode_flag(inode, EXT4_INODE_INLINE_DATA) && - ext4_test_inode_flag(inode, EXT4_INODE_EXTENTS)) { - ext4_error_inode(inode, function, line, 0, - "inode has both inline data and extents flags"); - ret = -EFSCORRUPTED; - goto bad_inode; - } inode->i_blocks = ext4_inode_blocks(raw_inode, ei); ei->i_file_acl = le32_to_cpu(raw_inode->i_file_acl_lo); if (ext4_has_feature_64bit(sb)) diff --git a/fs/ext4/super.c b/fs/ext4/super.c index 933f855276b4..6fb8dcebc01a 100644 --- a/fs/ext4/super.c +++ b/fs/ext4/super.c @@ -210,7 +210,7 @@ void *ext4_kvmalloc(size_t size, gfp_t flags) ret = kmalloc(size, flags | __GFP_NOWARN); if (!ret) - ret = __vmalloc(size, flags); + ret = __vmalloc(size, flags, PAGE_KERNEL); return ret; } @@ -220,7 +220,7 @@ void *ext4_kvzalloc(size_t size, gfp_t flags) ret = kzalloc(size, flags | __GFP_NOWARN); if (!ret) - ret = __vmalloc(size, flags | __GFP_ZERO); + ret = __vmalloc(size, flags | __GFP_ZERO, PAGE_KERNEL); return ret; } @@ -3948,16 +3948,18 @@ static int ext4_fill_super(struct super_block *sb, void *data, int silent) } if (sbi->s_es->s_mount_opts[0]) { - char s_mount_opts[65]; - - strscpy_pad(s_mount_opts, sbi->s_es->s_mount_opts, - sizeof(s_mount_opts)); + char *s_mount_opts = kstrndup(sbi->s_es->s_mount_opts, + sizeof(sbi->s_es->s_mount_opts), + GFP_KERNEL); + if (!s_mount_opts) + goto failed_mount; if (!parse_options(s_mount_opts, sb, &journal_devnum, &journal_ioprio, 0)) { ext4_msg(sb, KERN_WARNING, "failed to parse options in superblock: %s", s_mount_opts); } + kfree(s_mount_opts); } sbi->s_def_mount_opt = sbi->s_mount_opt; if (!parse_options((char *) data, sb, &journal_devnum, diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c index e08ba064cb82..f32e720e9e20 100644 --- a/fs/ext4/xattr.c +++ b/fs/ext4/xattr.c @@ -1030,7 +1030,7 @@ static int ext4_xattr_inode_update_ref(handle_t *handle, struct inode *ea_inode, int ref_change) { struct ext4_iloc iloc; - u64 ref_count; + s64 ref_count; int ret; inode_lock_nested(ea_inode, I_MUTEX_XATTR); @@ -1040,17 +1040,13 @@ static int ext4_xattr_inode_update_ref(handle_t *handle, struct inode *ea_inode, goto out; ref_count = ext4_xattr_inode_get_ref(ea_inode); - if ((ref_count == 0 && ref_change < 0) || (ref_count == U64_MAX && ref_change > 0)) { - ext4_error_inode(ea_inode, __func__, __LINE__, 0, - "EA inode %lu ref wraparound: ref_count=%lld ref_change=%d", - ea_inode->i_ino, ref_count, ref_change); - ret = -EFSCORRUPTED; - goto out; - } ref_count += ref_change; ext4_xattr_inode_set_ref(ea_inode, ref_count); if (ref_change > 0) { + WARN_ONCE(ref_count <= 0, "EA inode %lu ref_count=%lld", + ea_inode->i_ino, ref_count); + if (ref_count == 1) { WARN_ONCE(ea_inode->i_nlink, "EA inode %lu i_nlink=%u", ea_inode->i_ino, ea_inode->i_nlink); @@ -1059,6 +1055,9 @@ static int ext4_xattr_inode_update_ref(handle_t *handle, struct inode *ea_inode, ext4_orphan_del(handle, ea_inode); } } else { + WARN_ONCE(ref_count < 0, "EA inode %lu ref_count=%lld", + ea_inode->i_ino, ref_count); + if (ref_count == 0) { WARN_ONCE(ea_inode->i_nlink != 1, "EA inode %lu i_nlink=%u", diff --git a/fs/file.c b/fs/file.c index aa4ab548e917..95f6af59df80 100644 --- a/fs/file.c +++ b/fs/file.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -19,7 +18,6 @@ #include #include #include -#include unsigned int sysctl_nr_open __read_mostly = 1024*1024; unsigned int sysctl_nr_open_min = BITS_PER_LONG; @@ -86,14 +84,6 @@ static void copy_fdtable(struct fdtable *nfdt, struct fdtable *ofdt) * 'unsigned long' in some places, but simply because that is how the Linux * kernel bitmaps are defined to work: they are not "bits in an array of bytes", * they are very much "bits in an array of unsigned long". - * - * The ALIGN(nr, BITS_PER_LONG) here is for clarity: since we just multiplied - * by that "1024/sizeof(ptr)" before, we already know there are sufficient - * clear low bits. Clang seems to realize that, gcc ends up being confused. - * - * On a 128-bit machine, the ALIGN() would actually matter. In the meantime, - * let's consider it documentation (and maybe a test-case for gcc to improve - * its code generation ;) */ static struct fdtable *alloc_fdtable(unsigned int slots_wanted) { @@ -282,45 +272,36 @@ static inline void __clear_open_fd(unsigned int fd, struct fdtable *fdt) __clear_bit(fd / BITS_PER_LONG, fdt->full_fds_bits); } -/* - * Note that a sane fdtable size always has to be a multiple of - * BITS_PER_LONG, since we have bitmaps that are sized by this. - * - * punch_hole is optional - when close_range() is asked to unshare - * and close, we don't need to copy descriptors in that range, so - * a smaller cloned descriptor table might suffice if the last - * currently opened descriptor falls into that range. - */ -static unsigned int sane_fdtable_size(struct fdtable *fdt, struct fd_range *punch_hole) +static unsigned int count_open_files(struct fdtable *fdt) { - unsigned int last = find_last_bit(fdt->open_fds, fdt->max_fds); + unsigned int size = fdt->max_fds; + unsigned int i; - if (last == fdt->max_fds) - return NR_OPEN_DEFAULT; - if (punch_hole && punch_hole->to >= last && punch_hole->from <= last) { - last = find_last_bit(fdt->open_fds, punch_hole->from); - if (last == punch_hole->from) - return NR_OPEN_DEFAULT; + /* Find the last open fd */ + for (i = size / BITS_PER_LONG; i > 0; ) { + if (fdt->open_fds[--i]) + break; } - return ALIGN(last + 1, BITS_PER_LONG); + i = (i + 1) * BITS_PER_LONG; + return i; } /* - * Allocate a new descriptor table and copy contents from the passed in - * instance. Returns a pointer to cloned table on success, ERR_PTR() - * on failure. For 'punch_hole' see sane_fdtable_size(). + * Allocate a new files structure and copy contents from the + * passed in files structure. + * errorp will be valid only when the returned files_struct is NULL. */ -struct files_struct *dup_fd(struct files_struct *oldf, struct fd_range *punch_hole) +struct files_struct *dup_fd(struct files_struct *oldf, int *errorp) { struct files_struct *newf; struct file **old_fds, **new_fds; unsigned int open_files, i; struct fdtable *old_fdt, *new_fdt; - int error; + *errorp = -ENOMEM; newf = kmem_cache_alloc(files_cachep, GFP_KERNEL); if (!newf) - return ERR_PTR(-ENOMEM); + goto out; atomic_set(&newf->count, 1); @@ -337,7 +318,7 @@ struct files_struct *dup_fd(struct files_struct *oldf, struct fd_range *punch_ho spin_lock(&oldf->file_lock); old_fdt = files_fdtable(oldf); - open_files = sane_fdtable_size(old_fdt, punch_hole); + open_files = count_open_files(old_fdt); /* * Check whether we need to allocate a larger fd array and fd set. @@ -350,7 +331,7 @@ struct files_struct *dup_fd(struct files_struct *oldf, struct fd_range *punch_ho new_fdt = alloc_fdtable(open_files); if (IS_ERR(new_fdt)) { - error = PTR_ERR(new_fdt); + *errorp = PTR_ERR(new_fdt); goto out_release; } @@ -361,7 +342,7 @@ struct files_struct *dup_fd(struct files_struct *oldf, struct fd_range *punch_ho */ spin_lock(&oldf->file_lock); old_fdt = files_fdtable(oldf); - open_files = sane_fdtable_size(old_fdt, punch_hole); + open_files = count_open_files(old_fdt); } copy_fd_bitmaps(new_fdt, old_fdt, open_files / BITS_PER_LONG); @@ -395,7 +376,8 @@ struct files_struct *dup_fd(struct files_struct *oldf, struct fd_range *punch_ho out_release: kmem_cache_free(files_cachep, newf); - return ERR_PTR(error); +out: + return NULL; } static struct fdtable *close_files(struct files_struct * files) @@ -648,162 +630,31 @@ void fd_install(unsigned int fd, struct file *file) EXPORT_SYMBOL(fd_install); -/** - * pick_file - return file associatd with fd - * @files: file struct to retrieve file from - * @fd: file descriptor to retrieve file for - * - * If this functions returns an EINVAL error pointer the fd was beyond the - * current maximum number of file descriptors for that fdtable. - * - * Returns: The file associated with @fd, on error returns an error pointer. - */ -static struct file *pick_file(struct files_struct *files, unsigned fd) -{ - struct file *file; - struct fdtable *fdt; - - spin_lock(&files->file_lock); - fdt = files_fdtable(files); - if (fd >= fdt->max_fds) { - file = ERR_PTR(-EINVAL); - goto out_unlock; - } - fd = array_index_nospec(fd, fdt->max_fds); - file = fdt->fd[fd]; - if (!file) { - file = ERR_PTR(-EBADF); - goto out_unlock; - } - rcu_assign_pointer(fdt->fd[fd], NULL); - __put_unused_fd(files, fd); - -out_unlock: - spin_unlock(&files->file_lock); - return file; -} - /* * The same warnings as for __alloc_fd()/__fd_install() apply here... */ int __close_fd(struct files_struct *files, unsigned fd) { struct file *file; - - file = pick_file(files, fd); - if (IS_ERR(file)) - return -EBADF; - - return filp_close(file, files); -} -EXPORT_SYMBOL(__close_fd); /* for ksys_close() */ - -/** - * last_fd - return last valid index into fd table - * @cur_fds: files struct - * - * Context: Either rcu read lock or files_lock must be held. - * - * Returns: Last valid index into fdtable. - */ -static inline unsigned last_fd(struct fdtable *fdt) -{ - return fdt->max_fds - 1; -} - -static inline void __range_cloexec(struct files_struct *cur_fds, - unsigned int fd, unsigned int max_fd) -{ struct fdtable *fdt; - /* make sure we're using the correct maximum value */ - spin_lock(&cur_fds->file_lock); - fdt = files_fdtable(cur_fds); - max_fd = min(last_fd(fdt), max_fd); - if (fd <= max_fd) - bitmap_set(fdt->close_on_exec, fd, max_fd - fd + 1); - spin_unlock(&cur_fds->file_lock); -} - -static inline void __range_close(struct files_struct *cur_fds, unsigned int fd, - unsigned int max_fd) -{ - while (fd <= max_fd) { - struct file *file; - - file = pick_file(cur_fds, fd++); - if (!IS_ERR(file)) { - /* found a valid file to close */ - filp_close(file, cur_fds); - cond_resched(); - continue; - } - - /* beyond the last fd in that table */ - if (PTR_ERR(file) == -EINVAL) - return; - } -} - -/** - * __close_range() - Close all file descriptors in a given range. - * - * @fd: starting file descriptor to close - * @max_fd: last file descriptor to close - * - * This closes a range of file descriptors. All file descriptors - * from @fd up to and including @max_fd are closed. - */ -int __close_range(unsigned fd, unsigned max_fd, unsigned int flags) -{ - struct task_struct *me = current; - struct files_struct *cur_fds = me->files, *fds = NULL; - - if (flags & ~(CLOSE_RANGE_UNSHARE | CLOSE_RANGE_CLOEXEC)) - return -EINVAL; - - if (fd > max_fd) - return -EINVAL; - - if ((flags & CLOSE_RANGE_UNSHARE) && atomic_read(&cur_fds->count) > 1) { - struct fd_range range = {fd, max_fd}, *punch_hole = ⦥ - - /* - * If the caller requested all fds to be made cloexec we always - * copy all of the file descriptors since they still want to - * use them. - */ - if (flags & CLOSE_RANGE_CLOEXEC) - punch_hole = NULL; - - fds = dup_fd(cur_fds, punch_hole); - if (IS_ERR(fds)) - return PTR_ERR(fds); - /* - * We used to share our file descriptor table, and have now - * created a private one, make sure we're using it below. - */ - swap(cur_fds, fds); - } - - if (flags & CLOSE_RANGE_CLOEXEC) - __range_cloexec(cur_fds, fd, max_fd); - else - __range_close(cur_fds, fd, max_fd); - - if (fds) { - /* - * We're done closing the files we were supposed to. Time to install - * the new file descriptor table and drop the old one. - */ - task_lock(me); - me->files = cur_fds; - task_unlock(me); - put_files_struct(fds); - } - - return 0; + spin_lock(&files->file_lock); + fdt = files_fdtable(files); + if (fd >= fdt->max_fds) + goto out_unlock; + file = fdt->fd[fd]; + if (!file) + goto out_unlock; + rcu_assign_pointer(fdt->fd[fd], NULL); + __put_unused_fd(files, fd); + spin_unlock(&files->file_lock); + return filp_close(file, files); + +out_unlock: + spin_unlock(&files->file_lock); + return -EBADF; } +EXPORT_SYMBOL(__close_fd); /* for ksys_close() */ /* * variant of __close_fd that gets a ref on the file for later fput diff --git a/fs/file_table.c b/fs/file_table.c index e220e31952b2..70e8fb68a171 100644 --- a/fs/file_table.c +++ b/fs/file_table.c @@ -80,14 +80,14 @@ EXPORT_SYMBOL_GPL(get_max_files); */ #if defined(CONFIG_SYSCTL) && defined(CONFIG_PROC_FS) int proc_nr_files(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { files_stat.nr_files = get_nr_files(); return proc_doulongvec_minmax(table, write, buffer, lenp, ppos); } #else int proc_nr_files(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return -ENOSYS; } diff --git a/fs/fs-writeback.c b/fs/fs-writeback.c index 963a3ac0e08d..3ec2c16abece 100644 --- a/fs/fs-writeback.c +++ b/fs/fs-writeback.c @@ -2195,7 +2195,7 @@ static int __init start_dirtytime_writeback(void) __initcall(start_dirtytime_writeback); int dirtytime_interval_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int ret; diff --git a/fs/fscache/main.c b/fs/fscache/main.c index 4207f98e405f..3aa3756c7176 100644 --- a/fs/fscache/main.c +++ b/fs/fscache/main.c @@ -51,7 +51,8 @@ static unsigned fscache_op_max_active = 2; static struct ctl_table_header *fscache_sysctl_header; static int fscache_max_active_sysctl(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { struct workqueue_struct **wqp = table->extra1; unsigned int *datap = table->data; diff --git a/fs/fuse/Kconfig b/fs/fuse/Kconfig index ab3428492b61..0635cba19971 100644 --- a/fs/fuse/Kconfig +++ b/fs/fuse/Kconfig @@ -8,7 +8,7 @@ config FUSE_FS There's also a companion library: libfuse2. This library is available from the FUSE homepage: - + although chances are your distribution already has that library installed if you've installed the "fuse" package itself. @@ -34,29 +34,7 @@ config VIRTIO_FS select VIRTIO help The Virtio Filesystem allows guests to mount file systems from the - host. + host. If you want to share files between guests or with the host, answer Y - or M. - -config FUSE_DAX - bool "Virtio Filesystem Direct Host Memory Access support" - default y - select INTERVAL_TREE - depends on VIRTIO_FS - depends on FS_DAX - depends on DAX_DRIVER - help - This allows bypassing guest page cache and allows mapping host page - cache directly in guest address space. - - If you want to allow mounting a Virtio Filesystem with the "dax" - option, answer Y. - -config FUSE_BPF - bool "Adds BPF to fuse" - depends on FUSE_FS - depends on BPF - help - Extends FUSE by adding BPF to prefilter calls and potentially pass to a - backing file system + or M. diff --git a/fs/fuse/Makefile b/fs/fuse/Makefile index 7bd922ff8604..6971454a2bdf 100644 --- a/fs/fuse/Makefile +++ b/fs/fuse/Makefile @@ -7,8 +7,6 @@ obj-$(CONFIG_FUSE_FS) += fuse.o obj-$(CONFIG_CUSE) += cuse.o obj-$(CONFIG_VIRTIO_FS) += virtiofs.o -fuse-y := dev.o dir.o file.o inode.o control.o xattr.o acl.o readdir.o passthrough.o -fuse-$(CONFIG_FUSE_DAX) += dax.o -fuse-$(CONFIG_FUSE_BPF) += backing.o - -virtiofs-y := virtio_fs.o +fuse-objs := dev.o dir.o file.o inode.o control.o xattr.o acl.o readdir.o +fuse-objs += passthrough.o +virtiofs-y += virtio_fs.o diff --git a/fs/fuse/backing.c b/fs/fuse/backing.c deleted file mode 100644 index 013a03259f0c..000000000000 --- a/fs/fuse/backing.c +++ /dev/null @@ -1,2546 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * FUSE-BPF: Filesystem in Userspace with BPF - * Copyright (c) 2021 Google LLC - */ - -#include "fuse_i.h" - -#include -#include -#include -#include - -#include "../internal.h" - -#define FUSE_BPF_IOCB_MASK (IOCB_APPEND | IOCB_DSYNC | IOCB_HIPRI | IOCB_NOWAIT | IOCB_SYNC) - -struct fuse_bpf_aio_req { - struct kiocb iocb; - refcount_t ref; - struct kiocb *iocb_orig; -}; - -static struct kmem_cache *fuse_bpf_aio_request_cachep; - -static void fuse_stat_to_attr(struct fuse_conn *fc, struct inode *inode, - struct kstat *stat, struct fuse_attr *attr); - -static void fuse_file_accessed(struct file *dst_file, struct file *src_file) -{ - struct inode *dst_inode; - struct inode *src_inode; - - if (dst_file->f_flags & O_NOATIME) - return; - - dst_inode = file_inode(dst_file); - src_inode = file_inode(src_file); - - if ((!timespec64_equal(&dst_inode->i_mtime, &src_inode->i_mtime) || - !timespec64_equal(&dst_inode->i_ctime, &src_inode->i_ctime))) { - dst_inode->i_mtime = src_inode->i_mtime; - dst_inode->i_ctime = src_inode->i_ctime; - } - - touch_atime(&dst_file->f_path); -} - -struct bpf_prog *fuse_get_bpf_prog(struct file *file) -{ - struct bpf_prog *bpf_prog = ERR_PTR(-EINVAL); - - if (!file || IS_ERR(file)) - return bpf_prog; - /** - * Two ways of getting a bpf prog from another task's fd, since - * bpf_prog_get_type_dev only works with an fd - * - * 1) Duplicate a little of the needed code. Requires access to - * bpf_prog_fops for validation, which is not exported for modules - * 2) Insert the bpf_file object into a fd from the current task - * Stupidly complex, but I think OK, as security checks are not run - * during the existence of the handle - * - * Best would be to upstream 1) into kernel/bpf/syscall.c and export it - * for use here. Failing that, we have to use 2, since fuse must be - * compilable as a module. - */ -#if 0 - if (file->f_op != &bpf_prog_fops) - goto out; - - bpf_prog = file->private_data; - if (bpf_prog->type == BPF_PROG_TYPE_FUSE) - bpf_prog_inc(bpf_prog); - else - bpf_prog = ERR_PTR(-EINVAL); - -#else - { - int task_fd = get_unused_fd_flags(file->f_flags); - - if (task_fd < 0) - goto out; - - fd_install(task_fd, file); - - bpf_prog = bpf_prog_get_type_dev(task_fd, BPF_PROG_TYPE_FUSE, - false); - - /* Close the fd, which also closes the file */ - __close_fd(current->files, task_fd); - file = NULL; - } -#endif - -out: - if (file) - fput(file); - return bpf_prog; -} - -int fuse_open_initialize(struct fuse_bpf_args *fa, struct fuse_open_io *foio, - struct inode *inode, struct file *file, bool isdir) -{ - foio->foi = (struct fuse_open_in) { - .flags = file->f_flags & ~(O_CREAT | O_EXCL | O_NOCTTY), - }; - - foio->foo = (struct fuse_open_out) {0}; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_fuse_inode(inode)->nodeid, - .opcode = isdir ? FUSE_OPENDIR : FUSE_OPEN, - .in_numargs = 1, - .out_numargs = 1, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(foio->foi), - .value = &foio->foi, - }, - .out_args[0] = (struct fuse_bpf_arg) { - .size = sizeof(foio->foo), - .value = &foio->foo, - }, - }; - - return 0; -} - -int fuse_open_backing(struct fuse_bpf_args *fa, - struct inode *inode, struct file *file, bool isdir) -{ - struct fuse_mount *fm = get_fuse_mount(inode); - const struct fuse_open_in *foi = fa->in_args[0].value; - struct fuse_file *ff; - int retval; - int mask; - struct fuse_dentry *fd = get_fuse_dentry(file->f_path.dentry); - struct file *backing_file; - - ff = fuse_file_alloc(fm); - if (!ff) - return -ENOMEM; - file->private_data = ff; - - switch (foi->flags & O_ACCMODE) { - case O_RDONLY: - mask = MAY_READ; - break; - - case O_WRONLY: - mask = MAY_WRITE; - break; - - case O_RDWR: - mask = MAY_READ | MAY_WRITE; - break; - - default: - return -EINVAL; - } - - retval = inode_permission(get_fuse_inode(inode)->backing_inode, mask); - if (retval) - return retval; - - backing_file = dentry_open(&fd->backing_path, - foi->flags, - current_cred()); - - if (IS_ERR(backing_file)) { - fuse_file_free(ff); - file->private_data = NULL; - return PTR_ERR(backing_file); - } - ff->backing_file = backing_file; - - return 0; -} - -void *fuse_open_finalize(struct fuse_bpf_args *fa, - struct inode *inode, struct file *file, bool isdir) -{ - struct fuse_file *ff = file->private_data; - struct fuse_open_out *foo = fa->out_args[0].value; - - if (ff) { - ff->fh = foo->fh; - ff->nodeid = get_fuse_inode(inode)->nodeid; - } - return 0; -} - -int fuse_create_open_initialize( - struct fuse_bpf_args *fa, struct fuse_create_open_io *fcoio, - struct inode *dir, struct dentry *entry, - struct file *file, unsigned int flags, umode_t mode) -{ - fcoio->fci = (struct fuse_create_in) { - .flags = file->f_flags & ~(O_CREAT | O_EXCL | O_NOCTTY), - .mode = mode, - }; - - fcoio->feo = (struct fuse_entry_out) {0}; - fcoio->foo = (struct fuse_open_out) {0}; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(dir), - .opcode = FUSE_CREATE, - .in_numargs = 2, - .out_numargs = 2, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(fcoio->fci), - .value = &fcoio->fci, - }, - .in_args[1] = (struct fuse_bpf_in_arg) { - .size = entry->d_name.len + 1, - .value = entry->d_name.name, - }, - .out_args[0] = (struct fuse_bpf_arg) { - .size = sizeof(fcoio->feo), - .value = &fcoio->feo, - }, - .out_args[1] = (struct fuse_bpf_arg) { - .size = sizeof(fcoio->foo), - .value = &fcoio->foo, - }, - }; - - return 0; -} - -static int fuse_open_file_backing(struct inode *inode, struct file *file) -{ - struct fuse_mount *fm = get_fuse_mount(inode); - struct dentry *entry = file->f_path.dentry; - struct fuse_dentry *fuse_dentry = get_fuse_dentry(entry); - struct fuse_file *fuse_file; - struct file *backing_file; - - fuse_file = fuse_file_alloc(fm); - if (!fuse_file) - return -ENOMEM; - file->private_data = fuse_file; - - backing_file = dentry_open(&fuse_dentry->backing_path, file->f_flags, - current_cred()); - if (IS_ERR(backing_file)) { - fuse_file_free(fuse_file); - file->private_data = NULL; - return PTR_ERR(backing_file); - } - fuse_file->backing_file = backing_file; - - return 0; -} - -int fuse_create_open_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, - struct file *file, unsigned int flags, umode_t mode) -{ - struct fuse_inode *dir_fuse_inode = get_fuse_inode(dir); - struct fuse_dentry *fuse_entry = get_fuse_dentry(entry); - struct fuse_dentry *dir_fuse_dentry = get_fuse_dentry(entry->d_parent); - struct dentry *backing_dentry = NULL; - struct inode *inode = NULL; - struct dentry *newent; - int err = 0; - const struct fuse_create_in *fci = fa->in_args[0].value; - struct inode *d_inode = entry->d_inode; - u64 target_nodeid = 0; - - if (!dir_fuse_inode || !dir_fuse_dentry) - return -EIO; - - inode_lock_nested(dir_fuse_inode->backing_inode, I_MUTEX_PARENT); - backing_dentry = lookup_one_len(fa->in_args[1].value, - dir_fuse_dentry->backing_path.dentry, - strlen(fa->in_args[1].value)); - inode_unlock(dir_fuse_inode->backing_inode); - - if (IS_ERR(backing_dentry)) - return PTR_ERR(backing_dentry); - - if (d_really_is_positive(backing_dentry)) { - err = -EIO; - goto out; - } - - err = vfs_create(dir_fuse_inode->backing_inode, backing_dentry, - fci->mode, true); - if (err) - goto out; - - if (fuse_entry->backing_path.dentry) - path_put(&fuse_entry->backing_path); - fuse_entry->backing_path = (struct path) { - .mnt = dir_fuse_dentry->backing_path.mnt, - .dentry = backing_dentry, - }; - path_get(&fuse_entry->backing_path); - - if (d_inode) - target_nodeid = get_fuse_inode(d_inode)->nodeid; - - inode = fuse_iget_backing(dir->i_sb, target_nodeid, - fuse_entry->backing_path.dentry->d_inode); - if (!inode) { - err = -EIO; - goto out; - } - - if (get_fuse_inode(inode)->bpf) - bpf_prog_put(get_fuse_inode(inode)->bpf); - get_fuse_inode(inode)->bpf = fuse_entry->bpf; - fuse_entry->bpf = NULL; - - newent = d_splice_alias(inode, entry); - if (IS_ERR(newent)) { - err = PTR_ERR(newent); - goto out; - } - - inode = NULL; - entry = newent ? newent : entry; - err = finish_open(file, entry, fuse_open_file_backing); - -out: - iput(inode); - dput(backing_dentry); - return err; -} - -void *fuse_create_open_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, - struct file *file, unsigned int flags, umode_t mode) -{ - struct fuse_file *ff = file->private_data; - struct fuse_inode *fi = get_fuse_inode(file->f_inode); - struct fuse_entry_out *feo = fa->out_args[0].value; - struct fuse_open_out *foo = fa->out_args[1].value; - - if (fi) - fi->nodeid = feo->nodeid; - if (ff) - ff->fh = foo->fh; - return 0; -} - -int fuse_release_initialize(struct fuse_bpf_args *fa, struct fuse_release_in *fri, - struct inode *inode, struct fuse_file *ff) -{ - /* Always put backing file whatever bpf/userspace says */ - if (ff->backing_file) { - fput(ff->backing_file); - } - - *fri = (struct fuse_release_in) { - .fh = ff->fh, - }; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_fuse_inode(inode)->nodeid, - .opcode = S_ISDIR(inode->i_mode) ? FUSE_RELEASEDIR - : FUSE_RELEASE, - .in_numargs = 1, - .in_args[0].size = sizeof(*fri), - .in_args[0].value = fri, - }; - - return 0; -} - -int fuse_release_backing(struct fuse_bpf_args *fa, - struct inode *inode, struct fuse_file *ff) -{ - return 0; -} - -void *fuse_release_finalize(struct fuse_bpf_args *fa, - struct inode *inode, struct fuse_file *ff) -{ - return NULL; -} - -int fuse_flush_initialize(struct fuse_bpf_args *fa, struct fuse_flush_in *ffi, - struct file *file, fl_owner_t id) -{ - struct fuse_file *fuse_file = file->private_data; - - *ffi = (struct fuse_flush_in) { - .fh = fuse_file->fh, - }; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(file->f_inode), - .opcode = FUSE_FLUSH, - .in_numargs = 1, - .in_args[0].size = sizeof(*ffi), - .in_args[0].value = ffi, - .flags = FUSE_BPF_FORCE, - }; - - return 0; -} - -int fuse_flush_backing(struct fuse_bpf_args *fa, struct file *file, fl_owner_t id) -{ - struct fuse_file *fuse_file = file->private_data; - struct file *backing_file = fuse_file->backing_file; - - if (backing_file->f_op->flush) - return backing_file->f_op->flush(backing_file, id); - return 0; -} - -void *fuse_flush_finalize(struct fuse_bpf_args *fa, struct file *file, fl_owner_t id) -{ - return NULL; -} - -int fuse_lseek_initialize(struct fuse_bpf_args *fa, struct fuse_lseek_io *flio, - struct file *file, loff_t offset, int whence) -{ - struct fuse_file *fuse_file = file->private_data; - - flio->fli = (struct fuse_lseek_in) { - .fh = fuse_file->fh, - .offset = offset, - .whence = whence, - }; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(file->f_inode), - .opcode = FUSE_LSEEK, - .in_numargs = 1, - .in_args[0].size = sizeof(flio->fli), - .in_args[0].value = &flio->fli, - .out_numargs = 1, - .out_args[0].size = sizeof(flio->flo), - .out_args[0].value = &flio->flo, - }; - - return 0; -} - -int fuse_lseek_backing(struct fuse_bpf_args *fa, struct file *file, loff_t offset, int whence) -{ - const struct fuse_lseek_in *fli = fa->in_args[0].value; - struct fuse_lseek_out *flo = fa->out_args[0].value; - struct fuse_file *fuse_file = file->private_data; - struct file *backing_file = fuse_file->backing_file; - loff_t ret; - - if (offset == 0) { - if (whence == SEEK_CUR) { - flo->offset = file->f_pos; - return 0; - } - - if (whence == SEEK_SET) { - flo->offset = vfs_setpos(file, 0, 0); - return 0; - } - } - - inode_lock(file->f_inode); - backing_file->f_pos = file->f_pos; - ret = vfs_llseek(backing_file, fli->offset, fli->whence); - - if (!IS_ERR(ERR_PTR(ret))) { - flo->offset = ret; - ret = 0; - } - inode_unlock(file->f_inode); - return ret; -} - -void *fuse_lseek_finalize(struct fuse_bpf_args *fa, struct file *file, loff_t offset, int whence) -{ - struct fuse_lseek_out *flo = fa->out_args[0].value; - - if (!fa->error_in) - file->f_pos = flo->offset; - return ERR_PTR(flo->offset); -} - -int fuse_copy_file_range_initialize(struct fuse_bpf_args *fa, struct fuse_copy_file_range_io *fcf, - struct file *file_in, loff_t pos_in, struct file *file_out, - loff_t pos_out, size_t len, unsigned int flags) -{ - struct fuse_file *fuse_file_in = file_in->private_data; - struct fuse_file *fuse_file_out = file_out->private_data; - - - fcf->fci = (struct fuse_copy_file_range_in) { - .fh_in = fuse_file_in->fh, - .off_in = pos_in, - .nodeid_out = fuse_file_out->nodeid, - .fh_out = fuse_file_out->fh, - .off_out = pos_out, - .len = len, - .flags = flags, - }; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(file_in->f_inode), - .opcode = FUSE_COPY_FILE_RANGE, - .in_numargs = 1, - .in_args[0].size = sizeof(fcf->fci), - .in_args[0].value = &fcf->fci, - .out_numargs = 1, - .out_args[0].size = sizeof(fcf->fwo), - .out_args[0].value = &fcf->fwo, - }; - - return 0; -} - -int fuse_copy_file_range_backing(struct fuse_bpf_args *fa, struct file *file_in, loff_t pos_in, - struct file *file_out, loff_t pos_out, size_t len, - unsigned int flags) -{ - const struct fuse_copy_file_range_in *fci = fa->in_args[0].value; - struct fuse_file *fuse_file_in = file_in->private_data; - struct file *backing_file_in = fuse_file_in->backing_file; - struct fuse_file *fuse_file_out = file_out->private_data; - struct file *backing_file_out = fuse_file_out->backing_file; - - /* TODO: Handle changing of in/out files */ - if (backing_file_out) - return vfs_copy_file_range(backing_file_in, fci->off_in, backing_file_out, - fci->off_out, fci->len, fci->flags); - else - return generic_copy_file_range(file_in, pos_in, file_out, pos_out, len, - flags); -} - -void *fuse_copy_file_range_finalize(struct fuse_bpf_args *fa, struct file *file_in, loff_t pos_in, - struct file *file_out, loff_t pos_out, size_t len, - unsigned int flags) -{ - return NULL; -} - -int fuse_fsync_initialize(struct fuse_bpf_args *fa, struct fuse_fsync_in *ffi, - struct file *file, loff_t start, loff_t end, int datasync) -{ - struct fuse_file *fuse_file = file->private_data; - - *ffi = (struct fuse_fsync_in) { - .fh = fuse_file->fh, - .fsync_flags = datasync ? FUSE_FSYNC_FDATASYNC : 0, - }; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_fuse_inode(file->f_inode)->nodeid, - .opcode = FUSE_FSYNC, - .in_numargs = 1, - .in_args[0].size = sizeof(*ffi), - .in_args[0].value = ffi, - .flags = FUSE_BPF_FORCE, - }; - - return 0; -} - -int fuse_fsync_backing(struct fuse_bpf_args *fa, - struct file *file, loff_t start, loff_t end, int datasync) -{ - struct fuse_file *fuse_file = file->private_data; - struct file *backing_file = fuse_file->backing_file; - const struct fuse_fsync_in *ffi = fa->in_args[0].value; - int new_datasync = (ffi->fsync_flags & FUSE_FSYNC_FDATASYNC) ? 1 : 0; - - return vfs_fsync(backing_file, new_datasync); -} - -void *fuse_fsync_finalize(struct fuse_bpf_args *fa, - struct file *file, loff_t start, loff_t end, int datasync) -{ - return NULL; -} - -int fuse_dir_fsync_initialize(struct fuse_bpf_args *fa, struct fuse_fsync_in *ffi, - struct file *file, loff_t start, loff_t end, int datasync) -{ - struct fuse_file *fuse_file = file->private_data; - - *ffi = (struct fuse_fsync_in) { - .fh = fuse_file->fh, - .fsync_flags = datasync ? FUSE_FSYNC_FDATASYNC : 0, - }; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_fuse_inode(file->f_inode)->nodeid, - .opcode = FUSE_FSYNCDIR, - .in_numargs = 1, - .in_args[0].size = sizeof(*ffi), - .in_args[0].value = ffi, - .flags = FUSE_BPF_FORCE, - }; - - return 0; -} - -int fuse_getxattr_initialize(struct fuse_bpf_args *fa, - struct fuse_getxattr_io *fgio, - struct dentry *dentry, const char *name, void *value, - size_t size) -{ - *fgio = (struct fuse_getxattr_io) { - .fgi.size = size, - }; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_fuse_inode(dentry->d_inode)->nodeid, - .opcode = FUSE_GETXATTR, - .in_numargs = 2, - .out_numargs = 1, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(fgio->fgi), - .value = &fgio->fgi, - }, - .in_args[1] = (struct fuse_bpf_in_arg) { - .size = strlen(name) + 1, - .value = name, - }, - .flags = size ? FUSE_BPF_OUT_ARGVAR : 0, - .out_args[0].size = size ? size : sizeof(fgio->fgo), - .out_args[0].value = size ? value : &fgio->fgo, - }; - return 0; -} - -int fuse_getxattr_backing(struct fuse_bpf_args *fa, - struct dentry *dentry, const char *name, void *value, - size_t size) -{ - ssize_t ret = vfs_getxattr(get_fuse_dentry(dentry)->backing_path.dentry, - fa->in_args[1].value, value, size); - - if (fa->flags & FUSE_BPF_OUT_ARGVAR) - fa->out_args[0].size = ret; - else - ((struct fuse_getxattr_out *)fa->out_args[0].value)->size = ret; - - return 0; -} - -void *fuse_getxattr_finalize(struct fuse_bpf_args *fa, - struct dentry *dentry, const char *name, void *value, - size_t size) -{ - struct fuse_getxattr_out *fgo; - - if (fa->flags & FUSE_BPF_OUT_ARGVAR) - return ERR_PTR(fa->out_args[0].size); - - fgo = fa->out_args[0].value; - - return ERR_PTR(fgo->size); - -} - -int fuse_listxattr_initialize(struct fuse_bpf_args *fa, - struct fuse_getxattr_io *fgio, - struct dentry *dentry, char *list, size_t size) -{ - *fgio = (struct fuse_getxattr_io){ - .fgi.size = size, - }; - - *fa = (struct fuse_bpf_args){ - .nodeid = get_fuse_inode(dentry->d_inode)->nodeid, - .opcode = FUSE_LISTXATTR, - .in_numargs = 1, - .out_numargs = 1, - .in_args[0] = - (struct fuse_bpf_in_arg){ - .size = sizeof(fgio->fgi), - .value = &fgio->fgi, - }, - .flags = size ? FUSE_BPF_OUT_ARGVAR : 0, - .out_args[0].size = size ? size : sizeof(fgio->fgo), - .out_args[0].value = size ? (void *)list : &fgio->fgo, - }; - - return 0; -} - -int fuse_listxattr_backing(struct fuse_bpf_args *fa, struct dentry *dentry, - char *list, size_t size) -{ - ssize_t ret = - vfs_listxattr(get_fuse_dentry(dentry)->backing_path.dentry, - list, size); - - if (ret < 0) - return ret; - - if (fa->flags & FUSE_BPF_OUT_ARGVAR) - fa->out_args[0].size = ret; - else - ((struct fuse_getxattr_out *)fa->out_args[0].value)->size = ret; - - return ret; -} - -void *fuse_listxattr_finalize(struct fuse_bpf_args *fa, struct dentry *dentry, - char *list, size_t size) -{ - struct fuse_getxattr_out *fgo; - - if (fa->error_in) - return NULL; - - if (fa->flags & FUSE_BPF_OUT_ARGVAR) - return ERR_PTR(fa->out_args[0].size); - - fgo = fa->out_args[0].value; - return ERR_PTR(fgo->size); -} - -int fuse_setxattr_initialize(struct fuse_bpf_args *fa, - struct fuse_setxattr_in *fsxi, - struct dentry *dentry, const char *name, - const void *value, size_t size, int flags) -{ - *fsxi = (struct fuse_setxattr_in) { - .size = size, - .flags = flags, - }; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_fuse_inode(dentry->d_inode)->nodeid, - .opcode = FUSE_SETXATTR, - .in_numargs = 3, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(*fsxi), - .value = fsxi, - }, - .in_args[1] = (struct fuse_bpf_in_arg) { - .size = strlen(name) + 1, - .value = name, - }, - .in_args[2] = (struct fuse_bpf_in_arg) { - .size = size, - .value = value, - }, - }; - - return 0; -} - -int fuse_setxattr_backing(struct fuse_bpf_args *fa, struct dentry *dentry, - const char *name, const void *value, size_t size, - int flags) -{ - return vfs_setxattr(get_fuse_dentry(dentry)->backing_path.dentry, name, - value, size, flags); -} - -void *fuse_setxattr_finalize(struct fuse_bpf_args *fa, struct dentry *dentry, - const char *name, const void *value, size_t size, - int flags) -{ - return NULL; -} - -int fuse_removexattr_initialize(struct fuse_bpf_args *fa, - struct fuse_dummy_io *unused, - struct dentry *dentry, const char *name) -{ - *fa = (struct fuse_bpf_args) { - .nodeid = get_fuse_inode(dentry->d_inode)->nodeid, - .opcode = FUSE_REMOVEXATTR, - .in_numargs = 1, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = strlen(name) + 1, - .value = name, - }, - }; - - return 0; -} - -int fuse_removexattr_backing(struct fuse_bpf_args *fa, - struct dentry *dentry, const char *name) -{ - struct path *backing_path = - &get_fuse_dentry(dentry)->backing_path; - - /* TODO account for changes of the name by prefilter */ - return vfs_removexattr(backing_path->dentry, name); -} - -void *fuse_removexattr_finalize(struct fuse_bpf_args *fa, - struct dentry *dentry, const char *name) -{ - return NULL; -} - -static inline void fuse_bpf_aio_put(struct fuse_bpf_aio_req *aio_req) -{ - if (refcount_dec_and_test(&aio_req->ref)) - kmem_cache_free(fuse_bpf_aio_request_cachep, aio_req); -} - -static void fuse_bpf_aio_cleanup_handler(struct fuse_bpf_aio_req *aio_req) -{ - struct kiocb *iocb = &aio_req->iocb; - struct kiocb *iocb_orig = aio_req->iocb_orig; - - if (iocb->ki_flags & IOCB_WRITE) { - __sb_writers_acquired(file_inode(iocb->ki_filp)->i_sb, - SB_FREEZE_WRITE); - file_end_write(iocb->ki_filp); - fuse_copyattr(iocb_orig->ki_filp, iocb->ki_filp); - } - iocb_orig->ki_pos = iocb->ki_pos; - fuse_bpf_aio_put(aio_req); -} - -static void fuse_bpf_aio_rw_complete(struct kiocb *iocb, long res, long res2) -{ - struct fuse_bpf_aio_req *aio_req = - container_of(iocb, struct fuse_bpf_aio_req, iocb); - struct kiocb *iocb_orig = aio_req->iocb_orig; - - fuse_bpf_aio_cleanup_handler(aio_req); - iocb_orig->ki_complete(iocb_orig, res, res2); -} - - -int fuse_file_read_iter_initialize( - struct fuse_bpf_args *fa, struct fuse_file_read_iter_io *fri, - struct kiocb *iocb, struct iov_iter *to) -{ - struct file *file = iocb->ki_filp; - struct fuse_file *ff = file->private_data; - - fri->fri = (struct fuse_read_in) { - .fh = ff->fh, - .offset = iocb->ki_pos, - .size = to->count, - }; - - fri->frio = (struct fuse_read_iter_out) { - .ret = fri->fri.size, - }; - - /* TODO we can't assume 'to' is a kvec */ - /* TODO we also can't assume the vector has only one component */ - *fa = (struct fuse_bpf_args) { - .opcode = FUSE_READ, - .nodeid = ff->nodeid, - .in_numargs = 1, - .in_args[0].size = sizeof(fri->fri), - .in_args[0].value = &fri->fri, - .out_numargs = 1, - .out_args[0].size = sizeof(fri->frio), - .out_args[0].value = &fri->frio, - /* - * TODO Design this properly. - * Possible approach: do not pass buf to bpf - * If going to userland, do a deep copy - * For extra credit, do that to/from the vector, rather than - * making an extra copy in the kernel - */ - }; - - return 0; -} - -int fuse_file_read_iter_backing(struct fuse_bpf_args *fa, - struct kiocb *iocb, struct iov_iter *to) -{ - struct fuse_read_iter_out *frio = fa->out_args[0].value; - struct file *file = iocb->ki_filp; - struct fuse_file *ff = file->private_data; - ssize_t ret; - - if (!iov_iter_count(to)) - return 0; - - if ((iocb->ki_flags & IOCB_DIRECT) && - (!ff->backing_file->f_mapping->a_ops || - !ff->backing_file->f_mapping->a_ops->direct_IO)) - return -EINVAL; - - /* TODO This just plain ignores any change to fuse_read_in */ - if (is_sync_kiocb(iocb)) { - ret = vfs_iter_read(ff->backing_file, to, &iocb->ki_pos, - iocb_to_rw_flags(iocb->ki_flags, FUSE_BPF_IOCB_MASK)); - } else { - struct fuse_bpf_aio_req *aio_req; - - ret = -ENOMEM; - aio_req = kmem_cache_zalloc(fuse_bpf_aio_request_cachep, GFP_KERNEL); - if (!aio_req) - goto out; - - aio_req->iocb_orig = iocb; - kiocb_clone(&aio_req->iocb, iocb, ff->backing_file); - aio_req->iocb.ki_complete = fuse_bpf_aio_rw_complete; - refcount_set(&aio_req->ref, 2); - ret = vfs_iocb_iter_read(ff->backing_file, &aio_req->iocb, to); - fuse_bpf_aio_put(aio_req); - if (ret != -EIOCBQUEUED) - fuse_bpf_aio_cleanup_handler(aio_req); - } - - frio->ret = ret; - - /* TODO Need to point value at the buffer for post-modification */ - -out: - fuse_file_accessed(file, ff->backing_file); - - return ret; -} - -void *fuse_file_read_iter_finalize(struct fuse_bpf_args *fa, - struct kiocb *iocb, struct iov_iter *to) -{ - struct fuse_read_iter_out *frio = fa->out_args[0].value; - - return ERR_PTR(frio->ret); -} - -int fuse_file_write_iter_initialize( - struct fuse_bpf_args *fa, struct fuse_file_write_iter_io *fwio, - struct kiocb *iocb, struct iov_iter *from) -{ - struct file *file = iocb->ki_filp; - struct fuse_file *ff = file->private_data; - - *fwio = (struct fuse_file_write_iter_io) { - .fwi.fh = ff->fh, - .fwi.offset = iocb->ki_pos, - .fwi.size = from->count, - }; - - /* TODO we can't assume 'from' is a kvec */ - *fa = (struct fuse_bpf_args) { - .opcode = FUSE_WRITE, - .nodeid = ff->nodeid, - .in_numargs = 2, - .in_args[0].size = sizeof(fwio->fwi), - .in_args[0].value = &fwio->fwi, - .in_args[1].size = fwio->fwi.size, - .in_args[1].value = from->kvec->iov_base, - .out_numargs = 1, - .out_args[0].size = sizeof(fwio->fwio), - .out_args[0].value = &fwio->fwio, - }; - - return 0; -} - -int fuse_file_write_iter_backing(struct fuse_bpf_args *fa, - struct kiocb *iocb, struct iov_iter *from) -{ - struct file *file = iocb->ki_filp; - struct fuse_file *ff = file->private_data; - struct fuse_write_iter_out *fwio = fa->out_args[0].value; - ssize_t ret; - - if (!iov_iter_count(from)) - return 0; - - /* TODO This just plain ignores any change to fuse_write_in */ - /* TODO uint32_t seems smaller than ssize_t.... right? */ - inode_lock(file_inode(file)); - - fuse_copyattr(file, ff->backing_file); - - if (is_sync_kiocb(iocb)) { - file_start_write(ff->backing_file); - ret = vfs_iter_write(ff->backing_file, from, &iocb->ki_pos, - iocb_to_rw_flags(iocb->ki_flags, FUSE_BPF_IOCB_MASK)); - file_end_write(ff->backing_file); - - /* Must reflect change in size of backing file to upper file */ - if (ret > 0) - fuse_copyattr(file, ff->backing_file); - } else { - struct fuse_bpf_aio_req *aio_req; - - ret = -ENOMEM; - aio_req = kmem_cache_zalloc(fuse_bpf_aio_request_cachep, GFP_KERNEL); - if (!aio_req) - goto out; - - file_start_write(ff->backing_file); - __sb_writers_release(file_inode(ff->backing_file)->i_sb, SB_FREEZE_WRITE); - aio_req->iocb_orig = iocb; - kiocb_clone(&aio_req->iocb, iocb, ff->backing_file); - aio_req->iocb.ki_complete = fuse_bpf_aio_rw_complete; - refcount_set(&aio_req->ref, 2); - ret = vfs_iocb_iter_write(ff->backing_file, &aio_req->iocb, from); - fuse_bpf_aio_put(aio_req); - if (ret != -EIOCBQUEUED) - fuse_bpf_aio_cleanup_handler(aio_req); - } - -out: - inode_unlock(file_inode(file)); - fwio->ret = ret; - if (ret < 0) - return ret; - return 0; -} - -void *fuse_file_write_iter_finalize(struct fuse_bpf_args *fa, - struct kiocb *iocb, struct iov_iter *from) -{ - struct fuse_write_iter_out *fwio = fa->out_args[0].value; - - return ERR_PTR(fwio->ret); -} - -long fuse_backing_ioctl(struct file *file, unsigned int command, unsigned long arg, int flags) -{ - struct fuse_file *ff = file->private_data; - long ret; - - if (flags & FUSE_IOCTL_COMPAT) - ret = -ENOTTY; - else - ret = vfs_ioctl(ff->backing_file, command, arg); - - return ret; -} - -int fuse_file_flock_backing(struct file *file, int cmd, struct file_lock *fl) -{ - struct fuse_file *ff = file->private_data; - struct file *backing_file = ff->backing_file; - int error; - - fl->fl_file = backing_file; - if (backing_file->f_op->flock) - error = backing_file->f_op->flock(backing_file, cmd, fl); - else - error = locks_lock_file_wait(backing_file, fl); - return error; -} - -ssize_t fuse_backing_mmap(struct file *file, struct vm_area_struct *vma) -{ - int ret; - struct fuse_file *ff = file->private_data; - struct inode *fuse_inode = file_inode(file); - struct file *backing_file = ff->backing_file; - struct inode *backing_inode = file_inode(backing_file); - - if (!backing_file->f_op->mmap) - return -ENODEV; - - if (WARN_ON(file != vma->vm_file)) - return -EIO; - - get_file(backing_file); - swap(vma->vm_file, backing_file); - fput(backing_file); - ret = call_mmap(vma->vm_file, vma); - if (ret) - return ret; - - if (file->f_flags & O_NOATIME) - return ret; - - if ((!timespec64_equal(&fuse_inode->i_mtime, - &backing_inode->i_mtime) || - !timespec64_equal(&fuse_inode->i_ctime, - &backing_inode->i_ctime))) { - fuse_inode->i_mtime = backing_inode->i_mtime; - fuse_inode->i_ctime = backing_inode->i_ctime; - } - touch_atime(&file->f_path); - - return ret; -} - -int fuse_file_fallocate_initialize(struct fuse_bpf_args *fa, - struct fuse_fallocate_in *ffi, - struct file *file, int mode, loff_t offset, loff_t length) -{ - struct fuse_file *ff = file->private_data; - - *ffi = (struct fuse_fallocate_in) { - .fh = ff->fh, - .offset = offset, - .length = length, - .mode = mode - }; - - *fa = (struct fuse_bpf_args) { - .opcode = FUSE_FALLOCATE, - .nodeid = ff->nodeid, - .in_numargs = 1, - .in_args[0].size = sizeof(*ffi), - .in_args[0].value = ffi, - }; - - return 0; -} - -int fuse_file_fallocate_backing(struct fuse_bpf_args *fa, - struct file *file, int mode, loff_t offset, loff_t length) -{ - const struct fuse_fallocate_in *ffi = fa->in_args[0].value; - struct fuse_file *ff = file->private_data; - - return vfs_fallocate(ff->backing_file, ffi->mode, ffi->offset, - ffi->length); -} - -void *fuse_file_fallocate_finalize(struct fuse_bpf_args *fa, - struct file *file, int mode, loff_t offset, loff_t length) -{ - return NULL; -} - -/******************************************************************************* - * Directory operations after here * - ******************************************************************************/ - -int fuse_lookup_initialize(struct fuse_bpf_args *fa, struct fuse_lookup_io *fli, - struct inode *dir, struct dentry *entry, unsigned int flags) -{ - *fa = (struct fuse_bpf_args) { - .nodeid = get_fuse_inode(dir)->nodeid, - .opcode = FUSE_LOOKUP, - .in_numargs = 1, - .out_numargs = 2, - .flags = FUSE_BPF_OUT_ARGVAR, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = entry->d_name.len + 1, - .value = entry->d_name.name, - }, - .out_args[0] = (struct fuse_bpf_arg) { - .size = sizeof(fli->feo), - .value = &fli->feo, - }, - .out_args[1] = (struct fuse_bpf_arg) { - .size = sizeof(fli->feb.out), - .value = &fli->feb.out, - }, - }; - - return 0; -} - -int fuse_lookup_backing(struct fuse_bpf_args *fa, struct inode *dir, - struct dentry *entry, unsigned int flags) -{ - struct fuse_dentry *fuse_entry = get_fuse_dentry(entry); - struct fuse_dentry *dir_fuse_entry = get_fuse_dentry(entry->d_parent); - struct dentry *dir_backing_entry = dir_fuse_entry->backing_path.dentry; - struct inode *dir_backing_inode = dir_backing_entry->d_inode; - struct dentry *backing_entry; - struct fuse_entry_out *feo = (void *)fa->out_args[0].value; - struct kstat stat; - int err; - - inode_lock_nested(dir_backing_inode, I_MUTEX_PARENT); - backing_entry = lookup_one_len(entry->d_name.name, dir_backing_entry, - strlen(entry->d_name.name)); - inode_unlock(dir_backing_inode); - - if (IS_ERR(backing_entry)) - return PTR_ERR(backing_entry); - - fuse_entry->backing_path = (struct path) { - .dentry = backing_entry, - .mnt = mntget(dir_fuse_entry->backing_path.mnt), - }; - - if (d_is_negative(backing_entry)) { - fa->error_in = -ENOENT; - return 0; - } - - err = follow_down(&fuse_entry->backing_path); - if (err) - goto err_out; - - err = vfs_getattr(&fuse_entry->backing_path, &stat, - STATX_BASIC_STATS, 0); - if (err) - goto err_out; - - fuse_stat_to_attr(get_fuse_conn(dir), - backing_entry->d_inode, &stat, &feo->attr); - return 0; - -err_out: - path_put_init(&fuse_entry->backing_path); - return err; -} - -int fuse_handle_backing(struct fuse_entry_bpf *feb, struct inode **backing_inode, - struct path *backing_path) { - switch (feb->out.backing_action) { - case FUSE_ACTION_KEEP: - /* backing inode/path are added in fuse_lookup_backing */ - break; - - case FUSE_ACTION_REMOVE: - iput(*backing_inode); - *backing_inode = NULL; - path_put_init(backing_path); - break; - - case FUSE_ACTION_REPLACE: { - struct file *backing_file = feb->backing_file; - - if (!backing_file) - return -EINVAL; - if (IS_ERR(backing_file)) - return PTR_ERR(backing_file); - - if (backing_inode) - iput(*backing_inode); - *backing_inode = backing_file->f_inode; - ihold(*backing_inode); - - path_put(backing_path); - *backing_path = backing_file->f_path; - path_get(backing_path); - break; - } - - default: - return -EINVAL; - } - - return 0; -} - -int fuse_handle_bpf_prog(struct fuse_entry_bpf *feb, struct inode *parent, - struct bpf_prog **bpf) -{ - struct bpf_prog *new_bpf = NULL; - - switch (feb->out.bpf_action) { - case FUSE_ACTION_KEEP: { - /* Parent isn't presented, but we want to keep - * Don't touch bpf program at all in this case - */ - if (!parent) - return 0; - - new_bpf = get_fuse_inode(parent)->bpf; - if (new_bpf) - bpf_prog_inc(new_bpf); - break; - } - - case FUSE_ACTION_REMOVE: - break; - - case FUSE_ACTION_REPLACE: { - struct file *bpf_file = feb->bpf_file; - - if (!bpf_file) - return -EINVAL; - if (IS_ERR(bpf_file)) - return PTR_ERR(bpf_file); - - new_bpf = fuse_get_bpf_prog(bpf_file); - if (IS_ERR(new_bpf)) - return PTR_ERR(new_bpf); - break; - } - - default: - return -EINVAL; - } - - /* Cannot change existing program */ - if (*bpf) { - if (new_bpf) - bpf_prog_put(new_bpf); - return new_bpf == *bpf ? 0 : -EINVAL; - } - - *bpf = new_bpf; - return 0; -} - -struct dentry *fuse_lookup_finalize(struct fuse_bpf_args *fa, struct inode *dir, - struct dentry *entry, unsigned int flags) -{ - struct fuse_dentry *fuse_entry; - struct dentry *backing_entry; - struct inode *inode = NULL, *backing_inode; - struct inode *entry_inode = entry->d_inode; - struct fuse_entry_out *feo = fa->out_args[0].value; - struct fuse_entry_bpf_out *febo = fa->out_args[1].value; - struct fuse_entry_bpf *feb = container_of(febo, struct fuse_entry_bpf, - out); - int error = -1; - u64 target_nodeid = 0; - struct dentry *ret = NULL; - - fuse_entry = get_fuse_dentry(entry); - if (!fuse_entry) { - ret = ERR_PTR(-EIO); - goto out; - } - - backing_entry = fuse_entry->backing_path.dentry; - if (!backing_entry) { - ret = ERR_PTR(-ENOENT); - goto out; - } - - if (entry_inode) - target_nodeid = get_fuse_inode(entry_inode)->nodeid; - - backing_inode = backing_entry->d_inode; - if (backing_inode) - inode = fuse_iget_backing(dir->i_sb, target_nodeid, - backing_inode); - - error = inode ? - fuse_handle_bpf_prog(feb, dir, &get_fuse_inode(inode)->bpf) : - fuse_handle_bpf_prog(feb, dir, &fuse_entry->bpf); - if (error) { - ret = ERR_PTR(error); - goto out; - } - - if (inode) { - error = fuse_handle_backing(feb, - &get_fuse_inode(inode)->backing_inode, - &fuse_entry->backing_path); - if (error) { - ret = ERR_PTR(error); - goto out; - } - - get_fuse_inode(inode)->nodeid = feo->nodeid; - ret = d_splice_alias(inode, entry); - if (!IS_ERR(ret)) - inode = NULL; - } -out: - iput(inode); - if (feb->backing_file) - fput(feb->backing_file); - return ret; -} - -int fuse_revalidate_backing(struct dentry *entry, unsigned int flags) -{ - struct fuse_dentry *fuse_dentry = get_fuse_dentry(entry); - struct dentry *backing_entry = fuse_dentry->backing_path.dentry; - - spin_lock(&backing_entry->d_lock); - if (d_unhashed(backing_entry)) { - spin_unlock(&backing_entry->d_lock); - return 0; - } - spin_unlock(&backing_entry->d_lock); - - if (unlikely(backing_entry->d_flags & DCACHE_OP_REVALIDATE)) - return backing_entry->d_op->d_revalidate(backing_entry, flags); - return 1; -} - -int fuse_canonical_path_initialize(struct fuse_bpf_args *fa, - struct fuse_dummy_io *fdi, - const struct path *path, - struct path *canonical_path) -{ - fa->opcode = FUSE_CANONICAL_PATH; - return 0; -} - -int fuse_canonical_path_backing(struct fuse_bpf_args *fa, const struct path *path, - struct path *canonical_path) -{ - get_fuse_backing_path(path->dentry, canonical_path); - return 0; -} - -void *fuse_canonical_path_finalize(struct fuse_bpf_args *fa, - const struct path *path, - struct path *canonical_path) -{ - return NULL; -} - -int fuse_mknod_initialize( - struct fuse_bpf_args *fa, struct fuse_mknod_in *fmi, - struct inode *dir, struct dentry *entry, umode_t mode, dev_t rdev) -{ - *fmi = (struct fuse_mknod_in) { - .mode = mode, - .rdev = new_encode_dev(rdev), - .umask = current_umask(), - }; - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(dir), - .opcode = FUSE_MKNOD, - .in_numargs = 2, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(*fmi), - .value = fmi, - }, - .in_args[1] = (struct fuse_bpf_in_arg) { - .size = entry->d_name.len + 1, - .value = entry->d_name.name, - }, - }; - - return 0; -} - -int fuse_mknod_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, umode_t mode, dev_t rdev) -{ - int err = 0; - const struct fuse_mknod_in *fmi = fa->in_args[0].value; - struct fuse_inode *fuse_inode = get_fuse_inode(dir); - struct inode *backing_inode = fuse_inode->backing_inode; - struct path backing_path = {}; - struct inode *inode = NULL; - - //TODO Actually deal with changing the backing entry in mknod - get_fuse_backing_path(entry, &backing_path); - if (!backing_path.dentry) - return -EBADF; - - inode_lock_nested(backing_inode, I_MUTEX_PARENT); - mode = fmi->mode; - if (!IS_POSIXACL(backing_inode)) - mode &= ~fmi->umask; - err = vfs_mknod(backing_inode, backing_path.dentry, - mode, new_decode_dev(fmi->rdev)); - inode_unlock(backing_inode); - if (err) - goto out; - if (d_really_is_negative(backing_path.dentry) || - unlikely(d_unhashed(backing_path.dentry))) { - err = -EINVAL; - /** - * TODO: overlayfs responds to this situation with a - * lookupOneLen. Should we do that too? - */ - goto out; - } - inode = fuse_iget_backing(dir->i_sb, fuse_inode->nodeid, backing_inode); - if (IS_ERR(inode)) { - err = PTR_ERR(inode); - goto out; - } - d_instantiate(entry, inode); -out: - path_put(&backing_path); - return err; -} - -void *fuse_mknod_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, umode_t mode, dev_t rdev) -{ - return NULL; -} - -int fuse_mkdir_initialize( - struct fuse_bpf_args *fa, struct fuse_mkdir_in *fmi, - struct inode *dir, struct dentry *entry, umode_t mode) -{ - *fmi = (struct fuse_mkdir_in) { - .mode = mode, - .umask = current_umask(), - }; - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(dir), - .opcode = FUSE_MKDIR, - .in_numargs = 2, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(*fmi), - .value = fmi, - }, - .in_args[1] = (struct fuse_bpf_in_arg) { - .size = entry->d_name.len + 1, - .value = entry->d_name.name, - }, - }; - - return 0; -} - -int fuse_mkdir_backing( - struct fuse_bpf_args *fa, - struct inode *dir_inode, struct dentry *entry, umode_t mode) -{ - int err = 0; - const struct fuse_mkdir_in *fmi = fa->in_args[0].value; - struct fuse_inode *dir_fuse_inode = get_fuse_inode(dir_inode); - struct inode *dir_backing_inode = dir_fuse_inode->backing_inode; - struct path backing_path = {}; - struct inode *inode = NULL; - - //TODO Actually deal with changing the backing entry in mkdir - get_fuse_backing_path(entry, &backing_path); - if (!backing_path.dentry) - return -EBADF; - - inode_lock_nested(dir_backing_inode, I_MUTEX_PARENT); - mode = fmi->mode; - if (!IS_POSIXACL(dir_backing_inode)) - mode &= ~fmi->umask; - err = vfs_mkdir(dir_backing_inode, backing_path.dentry, mode); - if (err) - goto out; - if (d_really_is_negative(backing_path.dentry) || - unlikely(d_unhashed(backing_path.dentry))) { - struct dentry *d = lookup_one_len(entry->d_name.name, - backing_path.dentry->d_parent, - entry->d_name.len); - - if (IS_ERR(d)) { - err = PTR_ERR(d); - goto out; - } - dput(backing_path.dentry); - backing_path.dentry = d; - } - inode = fuse_iget_backing(dir_inode->i_sb, 0, - backing_path.dentry->d_inode); - if (IS_ERR(inode)) { - err = PTR_ERR(inode); - goto out; - } - d_instantiate(entry, inode); - if (get_fuse_inode(inode)->bpf) - bpf_prog_put(get_fuse_inode(inode)->bpf); - get_fuse_inode(inode)->bpf = get_fuse_dentry(entry)->bpf; - get_fuse_dentry(entry)->bpf = NULL; -out: - inode_unlock(dir_backing_inode); - path_put(&backing_path); - return err; -} - -void *fuse_mkdir_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, umode_t mode) -{ - return NULL; -} - -int fuse_rmdir_initialize( - struct fuse_bpf_args *fa, struct fuse_dummy_io *dummy, - struct inode *dir, struct dentry *entry) -{ - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(dir), - .opcode = FUSE_RMDIR, - .in_numargs = 1, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = entry->d_name.len + 1, - .value = entry->d_name.name, - }, - }; - - return 0; -} - -int fuse_rmdir_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry) -{ - int err = 0; - struct path backing_path = {}; - struct dentry *backing_parent_dentry; - struct inode *backing_inode; - - /* TODO Actually deal with changing the backing entry in rmdir */ - get_fuse_backing_path(entry, &backing_path); - if (!backing_path.dentry) - return -EBADF; - - /* TODO Not sure if we should reverify like overlayfs, or get inode from d_parent */ - backing_parent_dentry = dget_parent(backing_path.dentry); - backing_inode = d_inode(backing_parent_dentry); - - inode_lock_nested(backing_inode, I_MUTEX_PARENT); - err = vfs_rmdir(backing_inode, backing_path.dentry); - inode_unlock(backing_inode); - - dput(backing_parent_dentry); - if (!err) - d_drop(entry); - path_put(&backing_path); - return err; -} - -void *fuse_rmdir_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry) -{ - return NULL; -} - -static int fuse_rename_backing_common( - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent, - unsigned int flags) -{ - int err = 0; - struct path old_backing_path; - struct path new_backing_path; - struct dentry *old_backing_dir_dentry; - struct dentry *old_backing_dentry; - struct dentry *new_backing_dir_dentry; - struct dentry *new_backing_dentry; - struct dentry *trap = NULL; - struct inode *target_inode; - - //TODO Actually deal with changing anything that isn't a flag - get_fuse_backing_path(oldent, &old_backing_path); - if (!old_backing_path.dentry) - return -EBADF; - get_fuse_backing_path(newent, &new_backing_path); - if (!new_backing_path.dentry) { - /* - * TODO A file being moved from a backing path to another - * backing path which is not yet instrumented with FUSE-BPF. - * This may be slow and should be substituted with something - * more clever. - */ - err = -EXDEV; - goto put_old_path; - } - if (new_backing_path.mnt != old_backing_path.mnt) { - err = -EXDEV; - goto put_new_path; - } - old_backing_dentry = old_backing_path.dentry; - new_backing_dentry = new_backing_path.dentry; - old_backing_dir_dentry = dget_parent(old_backing_dentry); - new_backing_dir_dentry = dget_parent(new_backing_dentry); - target_inode = d_inode(newent); - - trap = lock_rename(old_backing_dir_dentry, new_backing_dir_dentry); - if (trap == old_backing_dentry) { - err = -EINVAL; - goto put_parents; - } - if (trap == new_backing_dentry) { - err = -ENOTEMPTY; - goto put_parents; - } - err = vfs_rename(d_inode(old_backing_dir_dentry), old_backing_dentry, - d_inode(new_backing_dir_dentry), new_backing_dentry, - NULL, flags); - if (err) - goto unlock; - if (target_inode) - fsstack_copy_attr_all(target_inode, - get_fuse_inode(target_inode)->backing_inode); - fsstack_copy_attr_all(d_inode(oldent), d_inode(old_backing_dentry)); -unlock: - unlock_rename(old_backing_dir_dentry, new_backing_dir_dentry); -put_parents: - dput(new_backing_dir_dentry); - dput(old_backing_dir_dentry); -put_new_path: - path_put(&new_backing_path); -put_old_path: - path_put(&old_backing_path); - return err; -} - -int fuse_rename2_initialize(struct fuse_bpf_args *fa, struct fuse_rename2_in *fri, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent, - unsigned int flags) -{ - *fri = (struct fuse_rename2_in) { - .newdir = get_node_id(newdir), - .flags = flags, - }; - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(olddir), - .opcode = FUSE_RENAME2, - .in_numargs = 3, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(*fri), - .value = fri, - }, - .in_args[1] = (struct fuse_bpf_in_arg) { - .size = oldent->d_name.len + 1, - .value = oldent->d_name.name, - }, - .in_args[2] = (struct fuse_bpf_in_arg) { - .size = newent->d_name.len + 1, - .value = newent->d_name.name, - }, - }; - - return 0; -} - -int fuse_rename2_backing(struct fuse_bpf_args *fa, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent, - unsigned int flags) -{ - const struct fuse_rename2_in *fri = fa->in_args[0].value; - - /* TODO: deal with changing dirs/ents */ - return fuse_rename_backing_common(olddir, oldent, newdir, newent, fri->flags); -} - -void *fuse_rename2_finalize(struct fuse_bpf_args *fa, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent, - unsigned int flags) -{ - return NULL; -} - -int fuse_rename_initialize(struct fuse_bpf_args *fa, struct fuse_rename_in *fri, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent) -{ - *fri = (struct fuse_rename_in) { - .newdir = get_node_id(newdir), - }; - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(olddir), - .opcode = FUSE_RENAME, - .in_numargs = 3, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(*fri), - .value = fri, - }, - .in_args[1] = (struct fuse_bpf_in_arg) { - .size = oldent->d_name.len + 1, - .value = oldent->d_name.name, - }, - .in_args[2] = (struct fuse_bpf_in_arg) { - .size = newent->d_name.len + 1, - .value = newent->d_name.name, - }, - }; - - return 0; -} - -int fuse_rename_backing(struct fuse_bpf_args *fa, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent) -{ - /* TODO: deal with changing dirs/ents */ - return fuse_rename_backing_common(olddir, oldent, newdir, newent, 0); -} - -void *fuse_rename_finalize(struct fuse_bpf_args *fa, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent) -{ - return NULL; -} - -int fuse_unlink_initialize( - struct fuse_bpf_args *fa, struct fuse_dummy_io *dummy, - struct inode *dir, struct dentry *entry) -{ - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(dir), - .opcode = FUSE_UNLINK, - .in_numargs = 1, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = entry->d_name.len + 1, - .value = entry->d_name.name, - }, - }; - - return 0; -} - -int fuse_unlink_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry) -{ - int err = 0; - struct path backing_path = {}; - struct dentry *backing_parent_dentry; - struct inode *backing_inode; - - /* TODO Actually deal with changing the backing entry in unlink */ - get_fuse_backing_path(entry, &backing_path); - if (!backing_path.dentry) - return -EBADF; - - /* TODO Not sure if we should reverify like overlayfs, or get inode from d_parent */ - backing_parent_dentry = dget_parent(backing_path.dentry); - backing_inode = d_inode(backing_parent_dentry); - - inode_lock_nested(backing_inode, I_MUTEX_PARENT); - err = vfs_unlink(backing_inode, backing_path.dentry, NULL); - inode_unlock(backing_inode); - - dput(backing_parent_dentry); - if (!err) - d_drop(entry); - path_put(&backing_path); - return err; -} - -void *fuse_unlink_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry) -{ - return NULL; -} - -int fuse_link_initialize(struct fuse_bpf_args *fa, struct fuse_link_in *fli, - struct dentry *entry, struct inode *dir, - struct dentry *newent) -{ - struct inode *src_inode = entry->d_inode; - - *fli = (struct fuse_link_in){ - .oldnodeid = get_node_id(src_inode), - }; - - fa->opcode = FUSE_LINK; - fa->in_numargs = 2; - fa->in_args[0].size = sizeof(*fli); - fa->in_args[0].value = fli; - fa->in_args[1].size = newent->d_name.len + 1; - fa->in_args[1].value = newent->d_name.name; - - return 0; -} - -int fuse_link_backing(struct fuse_bpf_args *fa, struct dentry *entry, - struct inode *dir, struct dentry *newent) -{ - int err = 0; - struct path backing_old_path = {}; - struct path backing_new_path = {}; - struct dentry *backing_dir_dentry; - struct inode *fuse_new_inode = NULL; - struct fuse_inode *fuse_dir_inode = get_fuse_inode(dir); - struct inode *backing_dir_inode = fuse_dir_inode->backing_inode; - - get_fuse_backing_path(entry, &backing_old_path); - if (!backing_old_path.dentry) - return -EBADF; - - get_fuse_backing_path(newent, &backing_new_path); - if (!backing_new_path.dentry) { - err = -EBADF; - goto err_dst_path; - } - - backing_dir_dentry = dget_parent(backing_new_path.dentry); - backing_dir_inode = d_inode(backing_dir_dentry); - - inode_lock_nested(backing_dir_inode, I_MUTEX_PARENT); - err = vfs_link(backing_old_path.dentry, backing_dir_inode, backing_new_path.dentry, NULL); - inode_unlock(backing_dir_inode); - if (err) - goto out; - - if (d_really_is_negative(backing_new_path.dentry) || - unlikely(d_unhashed(backing_new_path.dentry))) { - err = -EINVAL; - /** - * TODO: overlayfs responds to this situation with a - * lookupOneLen. Should we do that too? - */ - goto out; - } - - fuse_new_inode = fuse_iget_backing(dir->i_sb, fuse_dir_inode->nodeid, backing_dir_inode); - if (IS_ERR(fuse_new_inode)) { - err = PTR_ERR(fuse_new_inode); - goto out; - } - d_instantiate(newent, fuse_new_inode); - -out: - dput(backing_dir_dentry); - path_put(&backing_new_path); -err_dst_path: - path_put(&backing_old_path); - return err; -} - -void *fuse_link_finalize(struct fuse_bpf_args *fa, struct dentry *entry, - struct inode *dir, struct dentry *newent) -{ - return NULL; -} - -int fuse_getattr_initialize(struct fuse_bpf_args *fa, struct fuse_getattr_io *fgio, - const struct dentry *entry, struct kstat *stat, - u32 request_mask, unsigned int flags) -{ - fgio->fgi = (struct fuse_getattr_in) { - .getattr_flags = flags, - .fh = -1, /* TODO is this OK? */ - }; - - fgio->fao = (struct fuse_attr_out) {0}; - - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(entry->d_inode), - .opcode = FUSE_GETATTR, - .in_numargs = 1, - .out_numargs = 1, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(fgio->fgi), - .value = &fgio->fgi, - }, - .out_args[0] = (struct fuse_bpf_arg) { - .size = sizeof(fgio->fao), - .value = &fgio->fao, - }, - }; - - return 0; -} - -static void fuse_stat_to_attr(struct fuse_conn *fc, struct inode *inode, - struct kstat *stat, struct fuse_attr *attr) -{ - unsigned int blkbits; - - /* see the comment in fuse_change_attributes() */ - if (fc->writeback_cache && S_ISREG(inode->i_mode)) { - stat->size = i_size_read(inode); - stat->mtime.tv_sec = inode->i_mtime.tv_sec; - stat->mtime.tv_nsec = inode->i_mtime.tv_nsec; - stat->ctime.tv_sec = inode->i_ctime.tv_sec; - stat->ctime.tv_nsec = inode->i_ctime.tv_nsec; - } - - attr->ino = stat->ino; - attr->mode = (inode->i_mode & S_IFMT) | (stat->mode & 07777); - attr->nlink = stat->nlink; - attr->uid = from_kuid(fc->user_ns, stat->uid); - attr->gid = from_kgid(fc->user_ns, stat->gid); - attr->atime = stat->atime.tv_sec; - attr->atimensec = stat->atime.tv_nsec; - attr->mtime = stat->mtime.tv_sec; - attr->mtimensec = stat->mtime.tv_nsec; - attr->ctime = stat->ctime.tv_sec; - attr->ctimensec = stat->ctime.tv_nsec; - attr->size = stat->size; - attr->blocks = stat->blocks; - - if (stat->blksize != 0) - blkbits = ilog2(stat->blksize); - else - blkbits = inode->i_sb->s_blocksize_bits; - - attr->blksize = 1 << blkbits; -} - -int fuse_getattr_backing(struct fuse_bpf_args *fa, - const struct dentry *entry, struct kstat *stat, - u32 request_mask, unsigned int flags) -{ - struct path *backing_path = - &get_fuse_dentry(entry)->backing_path; - struct inode *backing_inode = backing_path->dentry->d_inode; - struct fuse_attr_out *fao = fa->out_args[0].value; - struct kstat tmp; - int err; - - if (!stat) - stat = &tmp; - - err = vfs_getattr(backing_path, stat, request_mask, flags); - - if (!err) - fuse_stat_to_attr(get_fuse_conn(entry->d_inode), - backing_inode, stat, &fao->attr); - - return err; -} - -void *fuse_getattr_finalize(struct fuse_bpf_args *fa, - const struct dentry *entry, struct kstat *stat, - u32 request_mask, unsigned int flags) -{ - struct fuse_attr_out *outarg = fa->out_args[0].value; - struct inode *inode = entry->d_inode; - u64 attr_version = fuse_get_attr_version(get_fuse_mount(inode)->fc); - int err = 0; - - /* TODO: Ensure this doesn't happen if we had an error getting attrs in - * backing. - */ - err = finalize_attr(inode, outarg, attr_version, stat); - return ERR_PTR(err); -} - -static void fattr_to_iattr(struct fuse_conn *fc, - const struct fuse_setattr_in *arg, - struct iattr *iattr) -{ - unsigned int fvalid = arg->valid; - - if (fvalid & FATTR_MODE) - iattr->ia_valid |= ATTR_MODE, iattr->ia_mode = arg->mode; - if (fvalid & FATTR_UID) { - iattr->ia_valid |= ATTR_UID; - iattr->ia_uid = make_kuid(fc->user_ns, arg->uid); - } - if (fvalid & FATTR_GID) { - iattr->ia_valid |= ATTR_GID; - iattr->ia_gid = make_kgid(fc->user_ns, arg->gid); - } - if (fvalid & FATTR_SIZE) - iattr->ia_valid |= ATTR_SIZE, iattr->ia_size = arg->size; - if (fvalid & FATTR_ATIME) { - iattr->ia_valid |= ATTR_ATIME; - iattr->ia_atime.tv_sec = arg->atime; - iattr->ia_atime.tv_nsec = arg->atimensec; - if (!(fvalid & FATTR_ATIME_NOW)) - iattr->ia_valid |= ATTR_ATIME_SET; - } - if (fvalid & FATTR_MTIME) { - iattr->ia_valid |= ATTR_MTIME; - iattr->ia_mtime.tv_sec = arg->mtime; - iattr->ia_mtime.tv_nsec = arg->mtimensec; - if (!(fvalid & FATTR_MTIME_NOW)) - iattr->ia_valid |= ATTR_MTIME_SET; - } - if (fvalid & FATTR_CTIME) { - iattr->ia_valid |= ATTR_CTIME; - iattr->ia_ctime.tv_sec = arg->ctime; - iattr->ia_ctime.tv_nsec = arg->ctimensec; - } -} - -int fuse_setattr_initialize(struct fuse_bpf_args *fa, struct fuse_setattr_io *fsio, - struct dentry *dentry, struct iattr *attr, struct file *file) -{ - struct fuse_conn *fc = get_fuse_conn(dentry->d_inode); - - *fsio = (struct fuse_setattr_io) {0}; - iattr_to_fattr(fc, attr, &fsio->fsi, true); - - *fa = (struct fuse_bpf_args) { - .opcode = FUSE_SETATTR, - .nodeid = get_node_id(dentry->d_inode), - .in_numargs = 1, - .in_args[0].size = sizeof(fsio->fsi), - .in_args[0].value = &fsio->fsi, - .out_numargs = 1, - .out_args[0].size = sizeof(fsio->fao), - .out_args[0].value = &fsio->fao, - }; - - return 0; -} - -int fuse_setattr_backing(struct fuse_bpf_args *fa, - struct dentry *dentry, struct iattr *attr, struct file *file) -{ - struct fuse_conn *fc = get_fuse_conn(dentry->d_inode); - const struct fuse_setattr_in *fsi = fa->in_args[0].value; - struct iattr new_attr = {0}; - struct path *backing_path = &get_fuse_dentry(dentry)->backing_path; - int res; - - fattr_to_iattr(fc, fsi, &new_attr); - /* TODO: Some info doesn't get saved by the attr->fattr->attr transition - * When we actually allow the bpf to change these, we may have to consider - * the extra flags more, or pass more info into the bpf. Until then we can - * keep everything except for ATTR_FILE, since we'd need a file on the - * lower fs. For what it's worth, neither f2fs nor ext4 make use of that - * even if it is present. - */ - new_attr.ia_valid = attr->ia_valid & ~ATTR_FILE; - inode_lock(d_inode(backing_path->dentry)); - res = notify_change(backing_path->dentry, &new_attr, NULL); - inode_unlock(d_inode(backing_path->dentry)); - - if (res == 0 && (new_attr.ia_valid & ATTR_SIZE)) - i_size_write(dentry->d_inode, new_attr.ia_size); - return res; -} - -void *fuse_setattr_finalize(struct fuse_bpf_args *fa, - struct dentry *dentry, struct iattr *attr, struct file *file) -{ - return NULL; -} - -int fuse_statfs_initialize( - struct fuse_bpf_args *fa, struct fuse_statfs_out *fso, - struct dentry *dentry, struct kstatfs *buf) -{ - *fso = (struct fuse_statfs_out) {0}; - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(d_inode(dentry)), - .opcode = FUSE_STATFS, - .out_numargs = 1, - .out_numargs = 1, - .out_args[0].size = sizeof(fso), - .out_args[0].value = fso, - }; - - return 0; -} - -int fuse_statfs_backing( - struct fuse_bpf_args *fa, - struct dentry *dentry, struct kstatfs *buf) -{ - int err = 0; - struct path backing_path; - struct fuse_statfs_out *fso = fa->out_args[0].value; - - get_fuse_backing_path(dentry, &backing_path); - if (!backing_path.dentry) - return -EBADF; - err = vfs_statfs(&backing_path, buf); - path_put(&backing_path); - buf->f_type = FUSE_SUPER_MAGIC; - - //TODO Provide postfilter opportunity to modify - if (!err) - convert_statfs_to_fuse(&fso->st, buf); - - return err; -} - -void *fuse_statfs_finalize( - struct fuse_bpf_args *fa, - struct dentry *dentry, struct kstatfs *buf) -{ - struct fuse_statfs_out *fso = fa->out_args[0].value; - - if (!fa->error_in) - convert_fuse_statfs(buf, &fso->st); - return NULL; -} - -int fuse_get_link_initialize(struct fuse_bpf_args *fa, struct fuse_dummy_io *unused, - struct inode *inode, struct dentry *dentry, - struct delayed_call *callback, const char **out) -{ - /* - * TODO - * If we want to handle changing these things, we'll need to copy - * the lower fs's data into our own buffer, and provide our own callback - * to free that buffer. - * - * Pre could change the name we're looking at - * postfilter can change the name we return - * - * We ought to only make that buffer if it's been requested, so leaving - * this unimplemented for the moment - */ - *fa = (struct fuse_bpf_args) { - .opcode = FUSE_READLINK, - .nodeid = get_node_id(inode), - .in_numargs = 1, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = dentry->d_name.len + 1, - .value = dentry->d_name.name, - }, - /* - * .out_argvar = 1, - * .out_numargs = 1, - * .out_args[0].size = , - * .out_args[0].value = , - */ - }; - - return 0; -} - -int fuse_get_link_backing(struct fuse_bpf_args *fa, - struct inode *inode, struct dentry *dentry, - struct delayed_call *callback, const char **out) -{ - struct path backing_path; - - if (!dentry) { - *out = ERR_PTR(-ECHILD); - return PTR_ERR(*out); - } - - get_fuse_backing_path(dentry, &backing_path); - if (!backing_path.dentry) { - *out = ERR_PTR(-ECHILD); - return PTR_ERR(*out); - } - - /* - * TODO: If we want to do our own thing, copy the data and then call the - * callback - */ - *out = vfs_get_link(backing_path.dentry, callback); - - path_put(&backing_path); - return 0; -} - -void *fuse_get_link_finalize(struct fuse_bpf_args *fa, - struct inode *inode, struct dentry *dentry, - struct delayed_call *callback, const char **out) -{ - return NULL; -} - -int fuse_symlink_initialize( - struct fuse_bpf_args *fa, struct fuse_dummy_io *unused, - struct inode *dir, struct dentry *entry, const char *link, int len) -{ - *fa = (struct fuse_bpf_args) { - .nodeid = get_node_id(dir), - .opcode = FUSE_SYMLINK, - .in_numargs = 2, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = entry->d_name.len + 1, - .value = entry->d_name.name, - }, - .in_args[1] = (struct fuse_bpf_in_arg) { - .size = len, - .value = link, - }, - }; - - return 0; -} - -int fuse_symlink_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, const char *link, int len) -{ - int err = 0; - struct fuse_inode *fuse_inode = get_fuse_inode(dir); - struct inode *backing_inode = fuse_inode->backing_inode; - struct path backing_path = {}; - struct inode *inode = NULL; - - //TODO Actually deal with changing the backing entry in symlink - get_fuse_backing_path(entry, &backing_path); - if (!backing_path.dentry) - return -EBADF; - - inode_lock_nested(backing_inode, I_MUTEX_PARENT); - err = vfs_symlink(backing_inode, backing_path.dentry, link); - inode_unlock(backing_inode); - if (err) - goto out; - if (d_really_is_negative(backing_path.dentry) || - unlikely(d_unhashed(backing_path.dentry))) { - err = -EINVAL; - /** - * TODO: overlayfs responds to this situation with a - * lookupOneLen. Should we do that too? - */ - goto out; - } - inode = fuse_iget_backing(dir->i_sb, fuse_inode->nodeid, backing_inode); - if (IS_ERR(inode)) { - err = PTR_ERR(inode); - goto out; - } - d_instantiate(entry, inode); -out: - path_put(&backing_path); - return err; -} - -void *fuse_symlink_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, const char *link, int len) -{ - return NULL; -} - -int fuse_readdir_initialize(struct fuse_bpf_args *fa, struct fuse_read_io *frio, - struct file *file, struct dir_context *ctx, - bool *force_again, bool *allow_force, bool is_continued) -{ - struct fuse_file *ff = file->private_data; - u8 *page = (u8 *)__get_free_page(GFP_KERNEL); - - if (!page) - return -ENOMEM; - - *fa = (struct fuse_bpf_args) { - .nodeid = ff->nodeid, - .opcode = FUSE_READDIR, - .in_numargs = 1, - .flags = FUSE_BPF_OUT_ARGVAR, - .out_numargs = 2, - .in_args[0] = (struct fuse_bpf_in_arg) { - .size = sizeof(frio->fri), - .value = &frio->fri, - }, - .out_args[0] = (struct fuse_bpf_arg) { - .size = sizeof(frio->fro), - .value = &frio->fro, - }, - .out_args[1] = (struct fuse_bpf_arg) { - .size = PAGE_SIZE, - .value = page, - }, - }; - - frio->fri = (struct fuse_read_in) { - .fh = ff->fh, - .offset = ctx->pos, - .size = PAGE_SIZE, - }; - frio->fro = (struct fuse_read_out) { - .again = 0, - .offset = 0, - }; - *force_again = false; - *allow_force = true; - return 0; -} - -struct extfuse_ctx { - struct dir_context ctx; - u8 *addr; - size_t offset; -}; - -static int filldir(struct dir_context *ctx, const char *name, int namelen, - loff_t offset, u64 ino, unsigned int d_type) -{ - struct extfuse_ctx *ec = container_of(ctx, struct extfuse_ctx, ctx); - struct fuse_dirent *fd = (struct fuse_dirent *) (ec->addr + ec->offset); - - if (ec->offset + sizeof(struct fuse_dirent) + namelen > PAGE_SIZE) - return -ENOMEM; - - *fd = (struct fuse_dirent) { - .ino = ino, - .off = offset, - .namelen = namelen, - .type = d_type, - }; - - memcpy(fd->name, name, namelen); - ec->offset += FUSE_DIRENT_SIZE(fd); - - return 0; -} - -static int parse_dirfile(char *buf, size_t nbytes, struct dir_context *ctx) -{ - while (nbytes >= FUSE_NAME_OFFSET) { - struct fuse_dirent *dirent = (struct fuse_dirent *) buf; - size_t reclen = FUSE_DIRENT_SIZE(dirent); - - if (!dirent->namelen || dirent->namelen > FUSE_NAME_MAX) - return -EIO; - if (reclen > nbytes) - break; - if (memchr(dirent->name, '/', dirent->namelen) != NULL) - return -EIO; - - ctx->pos = dirent->off; - if (!dir_emit(ctx, dirent->name, dirent->namelen, dirent->ino, - dirent->type)) - break; - - buf += reclen; - nbytes -= reclen; - } - - return 0; -} - - -int fuse_readdir_backing(struct fuse_bpf_args *fa, - struct file *file, struct dir_context *ctx, - bool *force_again, bool *allow_force, bool is_continued) -{ - struct fuse_file *ff = file->private_data; - struct file *backing_dir = ff->backing_file; - struct fuse_read_out *fro = fa->out_args[0].value; - struct extfuse_ctx ec; - int err; - - ec = (struct extfuse_ctx) { - .ctx.actor = filldir, - .ctx.pos = ctx->pos, - .addr = fa->out_args[1].value, - }; - - if (!ec.addr) - return -ENOMEM; - - if (!is_continued) - backing_dir->f_pos = file->f_pos; - - err = iterate_dir(backing_dir, &ec.ctx); - if (ec.offset == 0) - *allow_force = false; - fa->out_args[1].size = ec.offset; - - fro->offset = ec.ctx.pos; - fro->again = false; - return err; -} - -void *fuse_readdir_finalize(struct fuse_bpf_args *fa, - struct file *file, struct dir_context *ctx, - bool *force_again, bool *allow_force, bool is_continued) -{ - struct fuse_read_out *fro = fa->out_args[0].value; - struct fuse_file *ff = file->private_data; - struct file *backing_dir = ff->backing_file; - int err = 0; - - err = parse_dirfile(fa->out_args[1].value, fa->out_args[1].size, ctx); - *force_again = !!fro->again; - if (*force_again && !*allow_force) - err = -EINVAL; - - ctx->pos = fro->offset; - backing_dir->f_pos = fro->offset; - - free_page((unsigned long) fa->out_args[1].value); - return ERR_PTR(err); -} - -int fuse_access_initialize(struct fuse_bpf_args *fa, struct fuse_access_in *fai, - struct inode *inode, int mask) -{ - *fai = (struct fuse_access_in) { - .mask = mask, - }; - - *fa = (struct fuse_bpf_args) { - .opcode = FUSE_ACCESS, - .nodeid = get_node_id(inode), - .in_numargs = 1, - .in_args[0].size = sizeof(*fai), - .in_args[0].value = fai, - }; - - return 0; -} - -int fuse_access_backing(struct fuse_bpf_args *fa, struct inode *inode, int mask) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - const struct fuse_access_in *fai = fa->in_args[0].value; - - return inode_permission(/* For mainline: init_user_ns,*/ - fi->backing_inode, fai->mask); -} - -void *fuse_access_finalize(struct fuse_bpf_args *fa, struct inode *inode, int mask) -{ - return NULL; -} - -int __init fuse_bpf_init(void) -{ - fuse_bpf_aio_request_cachep = kmem_cache_create("fuse_bpf_aio_req", - sizeof(struct fuse_bpf_aio_req), - 0, SLAB_HWCACHE_ALIGN, NULL); - if (!fuse_bpf_aio_request_cachep) - return -ENOMEM; - - return 0; -} - -void __exit fuse_bpf_cleanup(void) -{ - kmem_cache_destroy(fuse_bpf_aio_request_cachep); -} - -ssize_t fuse_bpf_simple_request(struct fuse_mount *fm, struct fuse_bpf_args *bpf_args) -{ - int i; - ssize_t res; - struct fuse_args args = { - .nodeid = bpf_args->nodeid, - .opcode = bpf_args->opcode, - .error_in = bpf_args->error_in, - .in_numargs = bpf_args->in_numargs, - .out_numargs = bpf_args->out_numargs, - .force = !!(bpf_args->flags & FUSE_BPF_FORCE), - .out_argvar = !!(bpf_args->flags & FUSE_BPF_OUT_ARGVAR), - }; - - for (i = 0; i < args.in_numargs; ++i) - args.in_args[i] = (struct fuse_in_arg) { - .size = bpf_args->in_args[i].size, - .value = bpf_args->in_args[i].value, - }; - for (i = 0; i < args.out_numargs; ++i) - args.out_args[i] = (struct fuse_arg) { - .size = bpf_args->out_args[i].size, - .value = bpf_args->out_args[i].value, - }; - - res = fuse_simple_request(fm, &args); - - *bpf_args = (struct fuse_bpf_args) { - .nodeid = args.nodeid, - .opcode = args.opcode, - .error_in = args.error_in, - .in_numargs = args.in_numargs, - .out_numargs = args.out_numargs, - }; - if (args.force) - bpf_args->flags |= FUSE_BPF_FORCE; - if (args.out_argvar) - bpf_args->flags |= FUSE_BPF_OUT_ARGVAR; - for (i = 0; i < args.in_numargs; ++i) - bpf_args->in_args[i] = (struct fuse_bpf_in_arg) { - .size = args.in_args[i].size, - .value = args.in_args[i].value, - }; - for (i = 0; i < args.out_numargs; ++i) - bpf_args->out_args[i] = (struct fuse_bpf_arg) { - .size = args.out_args[i].size, - .value = args.out_args[i].value, - }; - return res; -} diff --git a/fs/fuse/control.c b/fs/fuse/control.c index 4aae0e606ba4..7092958c43ed 100644 --- a/fs/fuse/control.c +++ b/fs/fuse/control.c @@ -164,7 +164,6 @@ static ssize_t fuse_conn_congestion_threshold_write(struct file *file, { unsigned val; struct fuse_conn *fc; - struct fuse_mount *fm; ssize_t ret; ret = fuse_conn_limit_write(file, buf, count, ppos, &val, @@ -175,27 +174,18 @@ static ssize_t fuse_conn_congestion_threshold_write(struct file *file, if (!fc) goto out; - down_read(&fc->killsb); spin_lock(&fc->bg_lock); fc->congestion_threshold = val; - - /* - * Get any fuse_mount belonging to this fuse_conn; s_bdi is - * shared between all of them - */ - - if (!list_empty(&fc->mounts)) { - fm = list_first_entry(&fc->mounts, struct fuse_mount, fc_entry); + if (fc->sb) { if (fc->num_background < fc->congestion_threshold) { - clear_bdi_congested(fm->sb->s_bdi, BLK_RW_SYNC); - clear_bdi_congested(fm->sb->s_bdi, BLK_RW_ASYNC); + clear_bdi_congested(fc->sb->s_bdi, BLK_RW_SYNC); + clear_bdi_congested(fc->sb->s_bdi, BLK_RW_ASYNC); } else { - set_bdi_congested(fm->sb->s_bdi, BLK_RW_SYNC); - set_bdi_congested(fm->sb->s_bdi, BLK_RW_ASYNC); + set_bdi_congested(fc->sb->s_bdi, BLK_RW_SYNC); + set_bdi_congested(fc->sb->s_bdi, BLK_RW_ASYNC); } } spin_unlock(&fc->bg_lock); - up_read(&fc->killsb); fuse_conn_put(fc); out: return ret; @@ -328,7 +318,7 @@ void fuse_ctl_remove_conn(struct fuse_conn *fc) drop_nlink(d_inode(fuse_control_sb->s_root)); } -static int fuse_ctl_fill_super(struct super_block *sb, struct fs_context *fsc) +static int fuse_ctl_fill_super(struct super_block *sb, struct fs_context *fctx) { static const struct tree_descr empty_descr = {""}; struct fuse_conn *fc; @@ -354,18 +344,18 @@ static int fuse_ctl_fill_super(struct super_block *sb, struct fs_context *fsc) return 0; } -static int fuse_ctl_get_tree(struct fs_context *fsc) +static int fuse_ctl_get_tree(struct fs_context *fc) { - return get_tree_single(fsc, fuse_ctl_fill_super); + return get_tree_single(fc, fuse_ctl_fill_super); } static const struct fs_context_operations fuse_ctl_context_ops = { .get_tree = fuse_ctl_get_tree, }; -static int fuse_ctl_init_fs_context(struct fs_context *fsc) +static int fuse_ctl_init_fs_context(struct fs_context *fc) { - fsc->ops = &fuse_ctl_context_ops; + fc->ops = &fuse_ctl_context_ops; return 0; } @@ -395,7 +385,7 @@ int __init fuse_ctl_init(void) return register_filesystem(&fuse_ctl_fs_type); } -void fuse_ctl_cleanup(void) +void __exit fuse_ctl_cleanup(void) { unregister_filesystem(&fuse_ctl_fs_type); } diff --git a/fs/fuse/cuse.c b/fs/fuse/cuse.c index a37528b51798..072b68fbf8f4 100644 --- a/fs/fuse/cuse.c +++ b/fs/fuse/cuse.c @@ -57,7 +57,6 @@ struct cuse_conn { struct list_head list; /* linked on cuse_conntbl */ - struct fuse_mount fm; /* Dummy mount referencing fc */ struct fuse_conn fc; /* fuse connection */ struct cdev *cdev; /* associated character device */ struct device *dev; /* device representing @cdev */ @@ -135,7 +134,7 @@ static int cuse_open(struct inode *inode, struct file *file) * Generic permission check is already done against the chrdev * file, proceed to open. */ - rc = fuse_do_open(&cc->fm, 0, file, 0); + rc = fuse_do_open(&cc->fc, 0, file, 0); if (rc) fuse_conn_put(&cc->fc); return rc; @@ -144,10 +143,10 @@ static int cuse_open(struct inode *inode, struct file *file) static int cuse_release(struct inode *inode, struct file *file) { struct fuse_file *ff = file->private_data; - struct fuse_mount *fm = ff->fm; + struct fuse_conn *fc = ff->fc; fuse_sync_release(NULL, ff, file->f_flags); - fuse_conn_put(fm->fc); + fuse_conn_put(fc); return 0; } @@ -156,7 +155,7 @@ static long cuse_file_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { struct fuse_file *ff = file->private_data; - struct cuse_conn *cc = fc_to_cc(ff->fm->fc); + struct cuse_conn *cc = fc_to_cc(ff->fc); unsigned int flags = 0; if (cc->unrestricted_ioctl) @@ -169,7 +168,7 @@ static long cuse_file_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { struct fuse_file *ff = file->private_data; - struct cuse_conn *cc = fc_to_cc(ff->fm->fc); + struct cuse_conn *cc = fc_to_cc(ff->fc); unsigned int flags = FUSE_IOCTL_COMPAT; if (cc->unrestricted_ioctl) @@ -314,10 +313,9 @@ struct cuse_init_args { * required data structures for it. Please read the comment at the * top of this file for high level overview. */ -static void cuse_process_init_reply(struct fuse_mount *fm, +static void cuse_process_init_reply(struct fuse_conn *fc, struct fuse_args *args, int error) { - struct fuse_conn *fc = fm->fc; struct cuse_init_args *ia = container_of(args, typeof(*ia), ap.args); struct fuse_args_pages *ap = &ia->ap; struct cuse_conn *cc = fc_to_cc(fc), *pos; @@ -426,7 +424,7 @@ static int cuse_send_init(struct cuse_conn *cc) { int rc; struct page *page; - struct fuse_mount *fm = &cc->fm; + struct fuse_conn *fc = &cc->fc; struct cuse_init_args *ia; struct fuse_args_pages *ap; @@ -453,8 +451,8 @@ static int cuse_send_init(struct cuse_conn *cc) ap->args.out_args[0].size = sizeof(ia->out); ap->args.out_args[0].value = &ia->out; ap->args.out_args[1].size = CUSE_INIT_INFO_MAX; - ap->args.out_argvar = true; - ap->args.out_pages = true; + ap->args.out_argvar = 1; + ap->args.out_pages = 1; ap->num_pages = 1; ap->pages = &ia->page; ap->descs = &ia->desc; @@ -462,7 +460,7 @@ static int cuse_send_init(struct cuse_conn *cc) ia->desc.length = ap->args.out_args[1].size; ap->args.end = cuse_process_init_reply; - rc = fuse_simple_background(fm, &ap->args, GFP_KERNEL); + rc = fuse_simple_background(fc, &ap->args, GFP_KERNEL); if (rc) { kfree(ia); err_free_page: @@ -508,8 +506,7 @@ static int cuse_channel_open(struct inode *inode, struct file *file) * Limit the cuse channel to requests that can * be represented in file->f_cred->user_ns. */ - fuse_conn_init(&cc->fc, &cc->fm, file->f_cred->user_ns, - &fuse_dev_fiq_ops, NULL); + fuse_conn_init(&cc->fc, file->f_cred->user_ns, &fuse_dev_fiq_ops, NULL); fud = fuse_dev_alloc_install(&cc->fc); if (!fud) { diff --git a/fs/fuse/dax.c b/fs/fuse/dax.c deleted file mode 100644 index 2739e218df64..000000000000 --- a/fs/fuse/dax.c +++ /dev/null @@ -1,1366 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * dax: direct host memory access - * Copyright (C) 2020 Red Hat, Inc. - */ - -#include "fuse_i.h" - -#include -#include -#include -#include -#include -#include - -/* - * Default memory range size. A power of 2 so it agrees with common FUSE_INIT - * map_alignment values 4KB and 64KB. - */ -#define FUSE_DAX_SHIFT 21 -#define FUSE_DAX_SZ (1 << FUSE_DAX_SHIFT) -#define FUSE_DAX_PAGES (FUSE_DAX_SZ / PAGE_SIZE) - -/* Number of ranges reclaimer will try to free in one invocation */ -#define FUSE_DAX_RECLAIM_CHUNK (10) - -/* - * Dax memory reclaim threshold in percetage of total ranges. When free - * number of free ranges drops below this threshold, reclaim can trigger - * Default is 20% - */ -#define FUSE_DAX_RECLAIM_THRESHOLD (20) - -/** Translation information for file offsets to DAX window offsets */ -struct fuse_dax_mapping { - /* Pointer to inode where this memory range is mapped */ - struct inode *inode; - - /* Will connect in fcd->free_ranges to keep track of free memory */ - struct list_head list; - - /* For interval tree in file/inode */ - struct interval_tree_node itn; - - /* Will connect in fc->busy_ranges to keep track busy memory */ - struct list_head busy_list; - - /** Position in DAX window */ - u64 window_offset; - - /** Length of mapping, in bytes */ - loff_t length; - - /* Is this mapping read-only or read-write */ - bool writable; - - /* reference count when the mapping is used by dax iomap. */ - refcount_t refcnt; -}; - -/* Per-inode dax map */ -struct fuse_inode_dax { - /* Semaphore to protect modifications to the dmap tree */ - struct rw_semaphore sem; - - /* Sorted rb tree of struct fuse_dax_mapping elements */ - struct rb_root_cached tree; - unsigned long nr; -}; - -struct fuse_conn_dax { - /* DAX device */ - struct dax_device *dev; - - /* Lock protecting accessess to members of this structure */ - spinlock_t lock; - - /* List of memory ranges which are busy */ - unsigned long nr_busy_ranges; - struct list_head busy_ranges; - - /* Worker to free up memory ranges */ - struct delayed_work free_work; - - /* Wait queue for a dax range to become free */ - wait_queue_head_t range_waitq; - - /* DAX Window Free Ranges */ - long nr_free_ranges; - struct list_head free_ranges; - - unsigned long nr_ranges; -}; - -static inline struct fuse_dax_mapping * -node_to_dmap(struct interval_tree_node *node) -{ - if (!node) - return NULL; - - return container_of(node, struct fuse_dax_mapping, itn); -} - -static struct fuse_dax_mapping * -alloc_dax_mapping_reclaim(struct fuse_conn_dax *fcd, struct inode *inode); - -static void -__kick_dmap_free_worker(struct fuse_conn_dax *fcd, unsigned long delay_ms) -{ - unsigned long free_threshold; - - /* If number of free ranges are below threshold, start reclaim */ - free_threshold = max_t(unsigned long, fcd->nr_ranges * FUSE_DAX_RECLAIM_THRESHOLD / 100, - 1); - if (fcd->nr_free_ranges < free_threshold) - queue_delayed_work(system_long_wq, &fcd->free_work, - msecs_to_jiffies(delay_ms)); -} - -static void kick_dmap_free_worker(struct fuse_conn_dax *fcd, - unsigned long delay_ms) -{ - spin_lock(&fcd->lock); - __kick_dmap_free_worker(fcd, delay_ms); - spin_unlock(&fcd->lock); -} - -static struct fuse_dax_mapping *alloc_dax_mapping(struct fuse_conn_dax *fcd) -{ - struct fuse_dax_mapping *dmap; - - spin_lock(&fcd->lock); - dmap = list_first_entry_or_null(&fcd->free_ranges, - struct fuse_dax_mapping, list); - if (dmap) { - list_del_init(&dmap->list); - WARN_ON(fcd->nr_free_ranges <= 0); - fcd->nr_free_ranges--; - } - spin_unlock(&fcd->lock); - - kick_dmap_free_worker(fcd, 0); - return dmap; -} - -/* This assumes fcd->lock is held */ -static void __dmap_remove_busy_list(struct fuse_conn_dax *fcd, - struct fuse_dax_mapping *dmap) -{ - list_del_init(&dmap->busy_list); - WARN_ON(fcd->nr_busy_ranges == 0); - fcd->nr_busy_ranges--; -} - -static void dmap_remove_busy_list(struct fuse_conn_dax *fcd, - struct fuse_dax_mapping *dmap) -{ - spin_lock(&fcd->lock); - __dmap_remove_busy_list(fcd, dmap); - spin_unlock(&fcd->lock); -} - -/* This assumes fcd->lock is held */ -static void __dmap_add_to_free_pool(struct fuse_conn_dax *fcd, - struct fuse_dax_mapping *dmap) -{ - list_add_tail(&dmap->list, &fcd->free_ranges); - fcd->nr_free_ranges++; - wake_up(&fcd->range_waitq); -} - -static void dmap_add_to_free_pool(struct fuse_conn_dax *fcd, - struct fuse_dax_mapping *dmap) -{ - /* Return fuse_dax_mapping to free list */ - spin_lock(&fcd->lock); - __dmap_add_to_free_pool(fcd, dmap); - spin_unlock(&fcd->lock); -} - -static int fuse_setup_one_mapping(struct inode *inode, unsigned long start_idx, - struct fuse_dax_mapping *dmap, bool writable, - bool upgrade) -{ - struct fuse_mount *fm = get_fuse_mount(inode); - struct fuse_conn_dax *fcd = fm->fc->dax; - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_setupmapping_in inarg; - loff_t offset = start_idx << FUSE_DAX_SHIFT; - FUSE_ARGS(args); - ssize_t err; - - WARN_ON(fcd->nr_free_ranges < 0); - - /* Ask fuse daemon to setup mapping */ - memset(&inarg, 0, sizeof(inarg)); - inarg.foffset = offset; - inarg.fh = -1; - inarg.moffset = dmap->window_offset; - inarg.len = FUSE_DAX_SZ; - inarg.flags |= FUSE_SETUPMAPPING_FLAG_READ; - if (writable) - inarg.flags |= FUSE_SETUPMAPPING_FLAG_WRITE; - args.opcode = FUSE_SETUPMAPPING; - args.nodeid = fi->nodeid; - args.in_numargs = 1; - args.in_args[0].size = sizeof(inarg); - args.in_args[0].value = &inarg; - err = fuse_simple_request(fm, &args); - if (err < 0) - return err; - dmap->writable = writable; - if (!upgrade) { - /* - * We don't take a refernce on inode. inode is valid right now - * and when inode is going away, cleanup logic should first - * cleanup dmap entries. - */ - dmap->inode = inode; - dmap->itn.start = dmap->itn.last = start_idx; - /* Protected by fi->dax->sem */ - interval_tree_insert(&dmap->itn, &fi->dax->tree); - fi->dax->nr++; - spin_lock(&fcd->lock); - list_add_tail(&dmap->busy_list, &fcd->busy_ranges); - fcd->nr_busy_ranges++; - spin_unlock(&fcd->lock); - } - return 0; -} - -static int fuse_send_removemapping(struct inode *inode, - struct fuse_removemapping_in *inargp, - struct fuse_removemapping_one *remove_one) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_mount *fm = get_fuse_mount(inode); - FUSE_ARGS(args); - - args.opcode = FUSE_REMOVEMAPPING; - args.nodeid = fi->nodeid; - args.in_numargs = 2; - args.in_args[0].size = sizeof(*inargp); - args.in_args[0].value = inargp; - args.in_args[1].size = inargp->count * sizeof(*remove_one); - args.in_args[1].value = remove_one; - return fuse_simple_request(fm, &args); -} - -static int dmap_removemapping_list(struct inode *inode, unsigned int num, - struct list_head *to_remove) -{ - struct fuse_removemapping_one *remove_one, *ptr; - struct fuse_removemapping_in inarg; - struct fuse_dax_mapping *dmap; - int ret, i = 0, nr_alloc; - - nr_alloc = min_t(unsigned int, num, FUSE_REMOVEMAPPING_MAX_ENTRY); - remove_one = kmalloc_array(nr_alloc, sizeof(*remove_one), GFP_NOFS); - if (!remove_one) - return -ENOMEM; - - ptr = remove_one; - list_for_each_entry(dmap, to_remove, list) { - ptr->moffset = dmap->window_offset; - ptr->len = dmap->length; - ptr++; - i++; - num--; - if (i >= nr_alloc || num == 0) { - memset(&inarg, 0, sizeof(inarg)); - inarg.count = i; - ret = fuse_send_removemapping(inode, &inarg, - remove_one); - if (ret) - goto out; - ptr = remove_one; - i = 0; - } - } -out: - kfree(remove_one); - return ret; -} - -/* - * Cleanup dmap entry and add back to free list. This should be called with - * fcd->lock held. - */ -static void dmap_reinit_add_to_free_pool(struct fuse_conn_dax *fcd, - struct fuse_dax_mapping *dmap) -{ - pr_debug("fuse: freeing memory range start_idx=0x%lx end_idx=0x%lx window_offset=0x%llx length=0x%llx\n", - dmap->itn.start, dmap->itn.last, dmap->window_offset, - dmap->length); - __dmap_remove_busy_list(fcd, dmap); - dmap->inode = NULL; - dmap->itn.start = dmap->itn.last = 0; - __dmap_add_to_free_pool(fcd, dmap); -} - -/* - * Free inode dmap entries whose range falls inside [start, end]. - * Does not take any locks. At this point of time it should only be - * called from evict_inode() path where we know all dmap entries can be - * reclaimed. - */ -static void inode_reclaim_dmap_range(struct fuse_conn_dax *fcd, - struct inode *inode, - loff_t start, loff_t end) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_dax_mapping *dmap, *n; - int err, num = 0; - LIST_HEAD(to_remove); - unsigned long start_idx = start >> FUSE_DAX_SHIFT; - unsigned long end_idx = end >> FUSE_DAX_SHIFT; - struct interval_tree_node *node; - - while (1) { - node = interval_tree_iter_first(&fi->dax->tree, start_idx, - end_idx); - if (!node) - break; - dmap = node_to_dmap(node); - /* inode is going away. There should not be any users of dmap */ - WARN_ON(refcount_read(&dmap->refcnt) > 1); - interval_tree_remove(&dmap->itn, &fi->dax->tree); - num++; - list_add(&dmap->list, &to_remove); - } - - /* Nothing to remove */ - if (list_empty(&to_remove)) - return; - - WARN_ON(fi->dax->nr < num); - fi->dax->nr -= num; - err = dmap_removemapping_list(inode, num, &to_remove); - if (err && err != -ENOTCONN) { - pr_warn("Failed to removemappings. start=0x%llx end=0x%llx\n", - start, end); - } - spin_lock(&fcd->lock); - list_for_each_entry_safe(dmap, n, &to_remove, list) { - list_del_init(&dmap->list); - dmap_reinit_add_to_free_pool(fcd, dmap); - } - spin_unlock(&fcd->lock); -} - -static int dmap_removemapping_one(struct inode *inode, - struct fuse_dax_mapping *dmap) -{ - struct fuse_removemapping_one forget_one; - struct fuse_removemapping_in inarg; - - memset(&inarg, 0, sizeof(inarg)); - inarg.count = 1; - memset(&forget_one, 0, sizeof(forget_one)); - forget_one.moffset = dmap->window_offset; - forget_one.len = dmap->length; - - return fuse_send_removemapping(inode, &inarg, &forget_one); -} - -/* - * It is called from evict_inode() and by that time inode is going away. So - * this function does not take any locks like fi->dax->sem for traversing - * that fuse inode interval tree. If that lock is taken then lock validator - * complains of deadlock situation w.r.t fs_reclaim lock. - */ -void fuse_dax_inode_cleanup(struct inode *inode) -{ - struct fuse_conn *fc = get_fuse_conn(inode); - struct fuse_inode *fi = get_fuse_inode(inode); - - /* - * fuse_evict_inode() has already called truncate_inode_pages_final() - * before we arrive here. So we should not have to worry about any - * pages/exception entries still associated with inode. - */ - inode_reclaim_dmap_range(fc->dax, inode, 0, -1); - WARN_ON(fi->dax->nr); -} - -static void fuse_fill_iomap_hole(struct iomap *iomap, loff_t length) -{ - iomap->addr = IOMAP_NULL_ADDR; - iomap->length = length; - iomap->type = IOMAP_HOLE; -} - -static void fuse_fill_iomap(struct inode *inode, loff_t pos, loff_t length, - struct iomap *iomap, struct fuse_dax_mapping *dmap, - unsigned int flags) -{ - loff_t offset, len; - loff_t i_size = i_size_read(inode); - - offset = pos - (dmap->itn.start << FUSE_DAX_SHIFT); - len = min(length, dmap->length - offset); - - /* If length is beyond end of file, truncate further */ - if (pos + len > i_size) - len = i_size - pos; - - if (len > 0) { - iomap->addr = dmap->window_offset + offset; - iomap->length = len; - if (flags & IOMAP_FAULT) - iomap->length = ALIGN(len, PAGE_SIZE); - iomap->type = IOMAP_MAPPED; - /* - * increace refcnt so that reclaim code knows this dmap is in - * use. This assumes fi->dax->sem mutex is held either - * shared/exclusive. - */ - refcount_inc(&dmap->refcnt); - - /* iomap->private should be NULL */ - WARN_ON_ONCE(iomap->private); - iomap->private = dmap; - } else { - /* Mapping beyond end of file is hole */ - fuse_fill_iomap_hole(iomap, length); - } -} - -static int fuse_setup_new_dax_mapping(struct inode *inode, loff_t pos, - loff_t length, unsigned int flags, - struct iomap *iomap) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_conn *fc = get_fuse_conn(inode); - struct fuse_conn_dax *fcd = fc->dax; - struct fuse_dax_mapping *dmap, *alloc_dmap = NULL; - int ret; - bool writable = flags & IOMAP_WRITE; - unsigned long start_idx = pos >> FUSE_DAX_SHIFT; - struct interval_tree_node *node; - - /* - * Can't do inline reclaim in fault path. We call - * dax_layout_busy_page() before we free a range. And - * fuse_wait_dax_page() drops fi->i_mmap_sem lock and requires it. - * In fault path we enter with fi->i_mmap_sem held and can't drop - * it. Also in fault path we hold fi->i_mmap_sem shared and not - * exclusive, so that creates further issues with fuse_wait_dax_page(). - * Hence return -EAGAIN and fuse_dax_fault() will wait for a memory - * range to become free and retry. - */ - if (flags & IOMAP_FAULT) { - alloc_dmap = alloc_dax_mapping(fcd); - if (!alloc_dmap) - return -EAGAIN; - } else { - alloc_dmap = alloc_dax_mapping_reclaim(fcd, inode); - if (IS_ERR(alloc_dmap)) - return PTR_ERR(alloc_dmap); - } - - /* If we are here, we should have memory allocated */ - if (WARN_ON(!alloc_dmap)) - return -EIO; - - /* - * Take write lock so that only one caller can try to setup mapping - * and other waits. - */ - down_write(&fi->dax->sem); - /* - * We dropped lock. Check again if somebody else setup - * mapping already. - */ - node = interval_tree_iter_first(&fi->dax->tree, start_idx, start_idx); - if (node) { - dmap = node_to_dmap(node); - fuse_fill_iomap(inode, pos, length, iomap, dmap, flags); - dmap_add_to_free_pool(fcd, alloc_dmap); - up_write(&fi->dax->sem); - return 0; - } - - /* Setup one mapping */ - ret = fuse_setup_one_mapping(inode, pos >> FUSE_DAX_SHIFT, alloc_dmap, - writable, false); - if (ret < 0) { - dmap_add_to_free_pool(fcd, alloc_dmap); - up_write(&fi->dax->sem); - return ret; - } - fuse_fill_iomap(inode, pos, length, iomap, alloc_dmap, flags); - up_write(&fi->dax->sem); - return 0; -} - -static int fuse_upgrade_dax_mapping(struct inode *inode, loff_t pos, - loff_t length, unsigned int flags, - struct iomap *iomap) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_dax_mapping *dmap; - int ret; - unsigned long idx = pos >> FUSE_DAX_SHIFT; - struct interval_tree_node *node; - - /* - * Take exclusive lock so that only one caller can try to setup - * mapping and others wait. - */ - down_write(&fi->dax->sem); - node = interval_tree_iter_first(&fi->dax->tree, idx, idx); - - /* We are holding either inode lock or i_mmap_sem, and that should - * ensure that dmap can't be truncated. We are holding a reference - * on dmap and that should make sure it can't be reclaimed. So dmap - * should still be there in tree despite the fact we dropped and - * re-acquired the fi->dax->sem lock. - */ - ret = -EIO; - if (WARN_ON(!node)) - goto out_err; - - dmap = node_to_dmap(node); - - /* We took an extra reference on dmap to make sure its not reclaimd. - * Now we hold fi->dax->sem lock and that reference is not needed - * anymore. Drop it. - */ - if (refcount_dec_and_test(&dmap->refcnt)) { - /* refcount should not hit 0. This object only goes - * away when fuse connection goes away - */ - WARN_ON_ONCE(1); - } - - /* Maybe another thread already upgraded mapping while we were not - * holding lock. - */ - if (dmap->writable) { - ret = 0; - goto out_fill_iomap; - } - - ret = fuse_setup_one_mapping(inode, pos >> FUSE_DAX_SHIFT, dmap, true, - true); - if (ret < 0) - goto out_err; -out_fill_iomap: - fuse_fill_iomap(inode, pos, length, iomap, dmap, flags); -out_err: - up_write(&fi->dax->sem); - return ret; -} - -/* This is just for DAX and the mapping is ephemeral, do not use it for other - * purposes since there is no block device with a permanent mapping. - */ -static int fuse_iomap_begin(struct inode *inode, loff_t pos, loff_t length, - unsigned int flags, struct iomap *iomap, - struct iomap *srcmap) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_conn *fc = get_fuse_conn(inode); - struct fuse_dax_mapping *dmap; - bool writable = flags & IOMAP_WRITE; - unsigned long start_idx = pos >> FUSE_DAX_SHIFT; - struct interval_tree_node *node; - - /* We don't support FIEMAP */ - if (WARN_ON(flags & IOMAP_REPORT)) - return -EIO; - - iomap->offset = pos; - iomap->flags = 0; - iomap->bdev = NULL; - iomap->dax_dev = fc->dax->dev; - - /* - * Both read/write and mmap path can race here. So we need something - * to make sure if we are setting up mapping, then other path waits - * - * For now, use a semaphore for this. It probably needs to be - * optimized later. - */ - down_read(&fi->dax->sem); - node = interval_tree_iter_first(&fi->dax->tree, start_idx, start_idx); - if (node) { - dmap = node_to_dmap(node); - if (writable && !dmap->writable) { - /* Upgrade read-only mapping to read-write. This will - * require exclusive fi->dax->sem lock as we don't want - * two threads to be trying to this simultaneously - * for same dmap. So drop shared lock and acquire - * exclusive lock. - * - * Before dropping fi->dax->sem lock, take reference - * on dmap so that its not freed by range reclaim. - */ - refcount_inc(&dmap->refcnt); - up_read(&fi->dax->sem); - pr_debug("%s: Upgrading mapping at offset 0x%llx length 0x%llx\n", - __func__, pos, length); - return fuse_upgrade_dax_mapping(inode, pos, length, - flags, iomap); - } else { - fuse_fill_iomap(inode, pos, length, iomap, dmap, flags); - up_read(&fi->dax->sem); - return 0; - } - } else { - up_read(&fi->dax->sem); - pr_debug("%s: no mapping at offset 0x%llx length 0x%llx\n", - __func__, pos, length); - if (pos >= i_size_read(inode)) - goto iomap_hole; - - return fuse_setup_new_dax_mapping(inode, pos, length, flags, - iomap); - } - - /* - * If read beyond end of file happnes, fs code seems to return - * it as hole - */ -iomap_hole: - fuse_fill_iomap_hole(iomap, length); - pr_debug("%s returning hole mapping. pos=0x%llx length_asked=0x%llx length_returned=0x%llx\n", - __func__, pos, length, iomap->length); - return 0; -} - -static int fuse_iomap_end(struct inode *inode, loff_t pos, loff_t length, - ssize_t written, unsigned int flags, - struct iomap *iomap) -{ - struct fuse_dax_mapping *dmap = iomap->private; - - if (dmap) { - if (refcount_dec_and_test(&dmap->refcnt)) { - /* refcount should not hit 0. This object only goes - * away when fuse connection goes away - */ - WARN_ON_ONCE(1); - } - } - - /* DAX writes beyond end-of-file aren't handled using iomap, so the - * file size is unchanged and there is nothing to do here. - */ - return 0; -} - -static const struct iomap_ops fuse_iomap_ops = { - .iomap_begin = fuse_iomap_begin, - .iomap_end = fuse_iomap_end, -}; - -static void fuse_wait_dax_page(struct inode *inode) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - - up_write(&fi->i_mmap_sem); - schedule(); - down_write(&fi->i_mmap_sem); -} - -/* Should be called with fi->i_mmap_sem lock held exclusively */ -static int __fuse_dax_break_layouts(struct inode *inode, bool *retry, - loff_t start, loff_t end) -{ - struct page *page; - - page = dax_layout_busy_page_range(inode->i_mapping, start, end); - if (!page) - return 0; - - *retry = true; - return ___wait_var_event(&page->_refcount, - atomic_read(&page->_refcount) == 1, TASK_INTERRUPTIBLE, - 0, 0, fuse_wait_dax_page(inode)); -} - -/* dmap_end == 0 leads to unmapping of whole file */ -int fuse_dax_break_layouts(struct inode *inode, u64 dmap_start, - u64 dmap_end) -{ - bool retry; - int ret; - - do { - retry = false; - ret = __fuse_dax_break_layouts(inode, &retry, dmap_start, - dmap_end); - } while (ret == 0 && retry); - - return ret; -} - -ssize_t fuse_dax_read_iter(struct kiocb *iocb, struct iov_iter *to) -{ - struct inode *inode = file_inode(iocb->ki_filp); - ssize_t ret; - - if (iocb->ki_flags & IOCB_NOWAIT) { - if (!inode_trylock_shared(inode)) - return -EAGAIN; - } else { - inode_lock_shared(inode); - } - - ret = dax_iomap_rw(iocb, to, &fuse_iomap_ops); - inode_unlock_shared(inode); - - /* TODO file_accessed(iocb->f_filp) */ - return ret; -} - -static bool file_extending_write(struct kiocb *iocb, struct iov_iter *from) -{ - struct inode *inode = file_inode(iocb->ki_filp); - - return (iov_iter_rw(from) == WRITE && - ((iocb->ki_pos) >= i_size_read(inode) || - (iocb->ki_pos + iov_iter_count(from) > i_size_read(inode)))); -} - -static ssize_t fuse_dax_direct_write(struct kiocb *iocb, struct iov_iter *from) -{ - struct inode *inode = file_inode(iocb->ki_filp); - struct fuse_io_priv io = FUSE_IO_PRIV_SYNC(iocb); - ssize_t ret; - - ret = fuse_direct_io(&io, from, &iocb->ki_pos, FUSE_DIO_WRITE); - if (ret < 0) - return ret; - - fuse_invalidate_attr(inode); - fuse_write_update_size(inode, iocb->ki_pos); - return ret; -} - -ssize_t fuse_dax_write_iter(struct kiocb *iocb, struct iov_iter *from) -{ - struct inode *inode = file_inode(iocb->ki_filp); - ssize_t ret; - - if (iocb->ki_flags & IOCB_NOWAIT) { - if (!inode_trylock(inode)) - return -EAGAIN; - } else { - inode_lock(inode); - } - - ret = generic_write_checks(iocb, from); - if (ret <= 0) - goto out; - - ret = file_remove_privs(iocb->ki_filp); - if (ret) - goto out; - /* TODO file_update_time() but we don't want metadata I/O */ - - /* Do not use dax for file extending writes as write and on - * disk i_size increase are not atomic otherwise. - */ - if (file_extending_write(iocb, from)) - ret = fuse_dax_direct_write(iocb, from); - else - ret = dax_iomap_rw(iocb, from, &fuse_iomap_ops); - -out: - inode_unlock(inode); - - if (ret > 0) - ret = generic_write_sync(iocb, ret); - return ret; -} - -static int fuse_dax_writepages(struct address_space *mapping, - struct writeback_control *wbc) -{ - - struct inode *inode = mapping->host; - struct fuse_conn *fc = get_fuse_conn(inode); - - return dax_writeback_mapping_range(mapping, fc->dax->dev, wbc); -} - -static vm_fault_t __fuse_dax_fault(struct vm_fault *vmf, - enum page_entry_size pe_size, bool write) -{ - vm_fault_t ret; - struct inode *inode = file_inode(vmf->vma->vm_file); - struct super_block *sb = inode->i_sb; - pfn_t pfn; - int error = 0; - struct fuse_conn *fc = get_fuse_conn(inode); - struct fuse_conn_dax *fcd = fc->dax; - bool retry = false; - - if (write) - sb_start_pagefault(sb); -retry: - if (retry && !(fcd->nr_free_ranges > 0)) - wait_event(fcd->range_waitq, (fcd->nr_free_ranges > 0)); - - /* - * We need to serialize against not only truncate but also against - * fuse dax memory range reclaim. While a range is being reclaimed, - * we do not want any read/write/mmap to make progress and try - * to populate page cache or access memory we are trying to free. - */ - down_read(&get_fuse_inode(inode)->i_mmap_sem); - ret = dax_iomap_fault(vmf, pe_size, &pfn, &error, &fuse_iomap_ops); - if ((ret & VM_FAULT_ERROR) && error == -EAGAIN) { - error = 0; - retry = true; - up_read(&get_fuse_inode(inode)->i_mmap_sem); - goto retry; - } - - if (ret & VM_FAULT_NEEDDSYNC) - ret = dax_finish_sync_fault(vmf, pe_size, pfn); - up_read(&get_fuse_inode(inode)->i_mmap_sem); - - if (write) - sb_end_pagefault(sb); - - return ret; -} - -static vm_fault_t fuse_dax_fault(struct vm_fault *vmf) -{ - return __fuse_dax_fault(vmf, PE_SIZE_PTE, - vmf->flags & FAULT_FLAG_WRITE); -} - -static vm_fault_t fuse_dax_huge_fault(struct vm_fault *vmf, - enum page_entry_size pe_size) -{ - return __fuse_dax_fault(vmf, pe_size, vmf->flags & FAULT_FLAG_WRITE); -} - -static vm_fault_t fuse_dax_page_mkwrite(struct vm_fault *vmf) -{ - return __fuse_dax_fault(vmf, PE_SIZE_PTE, true); -} - -static vm_fault_t fuse_dax_pfn_mkwrite(struct vm_fault *vmf) -{ - return __fuse_dax_fault(vmf, PE_SIZE_PTE, true); -} - -static const struct vm_operations_struct fuse_dax_vm_ops = { - .fault = fuse_dax_fault, - .huge_fault = fuse_dax_huge_fault, - .page_mkwrite = fuse_dax_page_mkwrite, - .pfn_mkwrite = fuse_dax_pfn_mkwrite, -}; - -int fuse_dax_mmap(struct file *file, struct vm_area_struct *vma) -{ - file_accessed(file); - vma->vm_ops = &fuse_dax_vm_ops; - vma->vm_flags |= VM_MIXEDMAP | VM_HUGEPAGE; - return 0; -} - -static int dmap_writeback_invalidate(struct inode *inode, - struct fuse_dax_mapping *dmap) -{ - int ret; - loff_t start_pos = dmap->itn.start << FUSE_DAX_SHIFT; - loff_t end_pos = (start_pos + FUSE_DAX_SZ - 1); - - ret = filemap_fdatawrite_range(inode->i_mapping, start_pos, end_pos); - if (ret) { - pr_debug("fuse: filemap_fdatawrite_range() failed. err=%d start_pos=0x%llx, end_pos=0x%llx\n", - ret, start_pos, end_pos); - return ret; - } - - ret = invalidate_inode_pages2_range(inode->i_mapping, - start_pos >> PAGE_SHIFT, - end_pos >> PAGE_SHIFT); - if (ret) - pr_debug("fuse: invalidate_inode_pages2_range() failed err=%d\n", - ret); - - return ret; -} - -static int reclaim_one_dmap_locked(struct inode *inode, - struct fuse_dax_mapping *dmap) -{ - int ret; - struct fuse_inode *fi = get_fuse_inode(inode); - - /* - * igrab() was done to make sure inode won't go under us, and this - * further avoids the race with evict(). - */ - ret = dmap_writeback_invalidate(inode, dmap); - if (ret) - return ret; - - /* Remove dax mapping from inode interval tree now */ - interval_tree_remove(&dmap->itn, &fi->dax->tree); - fi->dax->nr--; - - /* It is possible that umount/shutdown has killed the fuse connection - * and worker thread is trying to reclaim memory in parallel. Don't - * warn in that case. - */ - ret = dmap_removemapping_one(inode, dmap); - if (ret && ret != -ENOTCONN) { - pr_warn("Failed to remove mapping. offset=0x%llx len=0x%llx ret=%d\n", - dmap->window_offset, dmap->length, ret); - } - return 0; -} - -/* Find first mapped dmap for an inode and return file offset. Caller needs - * to hold fi->dax->sem lock either shared or exclusive. - */ -static struct fuse_dax_mapping *inode_lookup_first_dmap(struct inode *inode) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_dax_mapping *dmap; - struct interval_tree_node *node; - - for (node = interval_tree_iter_first(&fi->dax->tree, 0, -1); node; - node = interval_tree_iter_next(node, 0, -1)) { - dmap = node_to_dmap(node); - /* still in use. */ - if (refcount_read(&dmap->refcnt) > 1) - continue; - - return dmap; - } - - return NULL; -} - -/* - * Find first mapping in the tree and free it and return it. Do not add - * it back to free pool. - */ -static struct fuse_dax_mapping * -inode_inline_reclaim_one_dmap(struct fuse_conn_dax *fcd, struct inode *inode, - bool *retry) -{ - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_dax_mapping *dmap; - u64 dmap_start, dmap_end; - unsigned long start_idx; - int ret; - struct interval_tree_node *node; - - down_write(&fi->i_mmap_sem); - - /* Lookup a dmap and corresponding file offset to reclaim. */ - down_read(&fi->dax->sem); - dmap = inode_lookup_first_dmap(inode); - if (dmap) { - start_idx = dmap->itn.start; - dmap_start = start_idx << FUSE_DAX_SHIFT; - dmap_end = dmap_start + FUSE_DAX_SZ - 1; - } - up_read(&fi->dax->sem); - - if (!dmap) - goto out_mmap_sem; - /* - * Make sure there are no references to inode pages using - * get_user_pages() - */ - ret = fuse_dax_break_layouts(inode, dmap_start, dmap_end); - if (ret) { - pr_debug("fuse: fuse_dax_break_layouts() failed. err=%d\n", - ret); - dmap = ERR_PTR(ret); - goto out_mmap_sem; - } - - down_write(&fi->dax->sem); - node = interval_tree_iter_first(&fi->dax->tree, start_idx, start_idx); - /* Range already got reclaimed by somebody else */ - if (!node) { - if (retry) - *retry = true; - goto out_write_dmap_sem; - } - - dmap = node_to_dmap(node); - /* still in use. */ - if (refcount_read(&dmap->refcnt) > 1) { - dmap = NULL; - if (retry) - *retry = true; - goto out_write_dmap_sem; - } - - ret = reclaim_one_dmap_locked(inode, dmap); - if (ret < 0) { - dmap = ERR_PTR(ret); - goto out_write_dmap_sem; - } - - /* Clean up dmap. Do not add back to free list */ - dmap_remove_busy_list(fcd, dmap); - dmap->inode = NULL; - dmap->itn.start = dmap->itn.last = 0; - - pr_debug("fuse: %s: inline reclaimed memory range. inode=%p, window_offset=0x%llx, length=0x%llx\n", - __func__, inode, dmap->window_offset, dmap->length); - -out_write_dmap_sem: - up_write(&fi->dax->sem); -out_mmap_sem: - up_write(&fi->i_mmap_sem); - return dmap; -} - -static struct fuse_dax_mapping * -alloc_dax_mapping_reclaim(struct fuse_conn_dax *fcd, struct inode *inode) -{ - struct fuse_dax_mapping *dmap; - struct fuse_inode *fi = get_fuse_inode(inode); - - while (1) { - bool retry = false; - - dmap = alloc_dax_mapping(fcd); - if (dmap) - return dmap; - - dmap = inode_inline_reclaim_one_dmap(fcd, inode, &retry); - /* - * Either we got a mapping or it is an error, return in both - * the cases. - */ - if (dmap) - return dmap; - - /* If we could not reclaim a mapping because it - * had a reference or some other temporary failure, - * Try again. We want to give up inline reclaim only - * if there is no range assigned to this node. Otherwise - * if a deadlock is possible if we sleep with fi->i_mmap_sem - * held and worker to free memory can't make progress due - * to unavailability of fi->i_mmap_sem lock. So sleep - * only if fi->dax->nr=0 - */ - if (retry) - continue; - /* - * There are no mappings which can be reclaimed. Wait for one. - * We are not holding fi->dax->sem. So it is possible - * that range gets added now. But as we are not holding - * fi->i_mmap_sem, worker should still be able to free up - * a range and wake us up. - */ - if (!fi->dax->nr && !(fcd->nr_free_ranges > 0)) { - if (wait_event_killable_exclusive(fcd->range_waitq, - (fcd->nr_free_ranges > 0))) { - return ERR_PTR(-EINTR); - } - } - } -} - -static int lookup_and_reclaim_dmap_locked(struct fuse_conn_dax *fcd, - struct inode *inode, - unsigned long start_idx) -{ - int ret; - struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_dax_mapping *dmap; - struct interval_tree_node *node; - - /* Find fuse dax mapping at file offset inode. */ - node = interval_tree_iter_first(&fi->dax->tree, start_idx, start_idx); - - /* Range already got cleaned up by somebody else */ - if (!node) - return 0; - dmap = node_to_dmap(node); - - /* still in use. */ - if (refcount_read(&dmap->refcnt) > 1) - return 0; - - ret = reclaim_one_dmap_locked(inode, dmap); - if (ret < 0) - return ret; - - /* Cleanup dmap entry and add back to free list */ - spin_lock(&fcd->lock); - dmap_reinit_add_to_free_pool(fcd, dmap); - spin_unlock(&fcd->lock); - return ret; -} - -/* - * Free a range of memory. - * Locking: - * 1. Take fi->i_mmap_sem to block dax faults. - * 2. Take fi->dax->sem to protect interval tree and also to make sure - * read/write can not reuse a dmap which we might be freeing. - */ -static int lookup_and_reclaim_dmap(struct fuse_conn_dax *fcd, - struct inode *inode, - unsigned long start_idx, - unsigned long end_idx) -{ - int ret; - struct fuse_inode *fi = get_fuse_inode(inode); - loff_t dmap_start = start_idx << FUSE_DAX_SHIFT; - loff_t dmap_end = (dmap_start + FUSE_DAX_SZ) - 1; - - down_write(&fi->i_mmap_sem); - ret = fuse_dax_break_layouts(inode, dmap_start, dmap_end); - if (ret) { - pr_debug("virtio_fs: fuse_dax_break_layouts() failed. err=%d\n", - ret); - goto out_mmap_sem; - } - - down_write(&fi->dax->sem); - ret = lookup_and_reclaim_dmap_locked(fcd, inode, start_idx); - up_write(&fi->dax->sem); -out_mmap_sem: - up_write(&fi->i_mmap_sem); - return ret; -} - -static int try_to_free_dmap_chunks(struct fuse_conn_dax *fcd, - unsigned long nr_to_free) -{ - struct fuse_dax_mapping *dmap, *pos, *temp; - int ret, nr_freed = 0; - unsigned long start_idx = 0, end_idx = 0; - struct inode *inode = NULL; - - /* Pick first busy range and free it for now*/ - while (1) { - if (nr_freed >= nr_to_free) - break; - - dmap = NULL; - spin_lock(&fcd->lock); - - if (!fcd->nr_busy_ranges) { - spin_unlock(&fcd->lock); - return 0; - } - - list_for_each_entry_safe(pos, temp, &fcd->busy_ranges, - busy_list) { - /* skip this range if it's in use. */ - if (refcount_read(&pos->refcnt) > 1) - continue; - - inode = igrab(pos->inode); - /* - * This inode is going away. That will free - * up all the ranges anyway, continue to - * next range. - */ - if (!inode) - continue; - /* - * Take this element off list and add it tail. If - * this element can't be freed, it will help with - * selecting new element in next iteration of loop. - */ - dmap = pos; - list_move_tail(&dmap->busy_list, &fcd->busy_ranges); - start_idx = end_idx = dmap->itn.start; - break; - } - spin_unlock(&fcd->lock); - if (!dmap) - return 0; - - ret = lookup_and_reclaim_dmap(fcd, inode, start_idx, end_idx); - iput(inode); - if (ret) - return ret; - nr_freed++; - } - return 0; -} - -static void fuse_dax_free_mem_worker(struct work_struct *work) -{ - int ret; - struct fuse_conn_dax *fcd = container_of(work, struct fuse_conn_dax, - free_work.work); - ret = try_to_free_dmap_chunks(fcd, FUSE_DAX_RECLAIM_CHUNK); - if (ret) { - pr_debug("fuse: try_to_free_dmap_chunks() failed with err=%d\n", - ret); - } - - /* If number of free ranges are still below threhold, requeue */ - kick_dmap_free_worker(fcd, 1); -} - -static void fuse_free_dax_mem_ranges(struct list_head *mem_list) -{ - struct fuse_dax_mapping *range, *temp; - - /* Free All allocated elements */ - list_for_each_entry_safe(range, temp, mem_list, list) { - list_del(&range->list); - if (!list_empty(&range->busy_list)) - list_del(&range->busy_list); - kfree(range); - } -} - -void fuse_dax_conn_free(struct fuse_conn *fc) -{ - if (fc->dax) { - fuse_free_dax_mem_ranges(&fc->dax->free_ranges); - kfree(fc->dax); - fc->dax = NULL; - } -} - -static int fuse_dax_mem_range_init(struct fuse_conn_dax *fcd) -{ - long nr_pages, nr_ranges; - void *kaddr; - pfn_t pfn; - struct fuse_dax_mapping *range; - int ret, id; - size_t dax_size = -1; - unsigned long i; - - init_waitqueue_head(&fcd->range_waitq); - INIT_LIST_HEAD(&fcd->free_ranges); - INIT_LIST_HEAD(&fcd->busy_ranges); - INIT_DELAYED_WORK(&fcd->free_work, fuse_dax_free_mem_worker); - - id = dax_read_lock(); - nr_pages = dax_direct_access(fcd->dev, 0, PHYS_PFN(dax_size), &kaddr, - &pfn); - dax_read_unlock(id); - if (nr_pages < 0) { - pr_debug("dax_direct_access() returned %ld\n", nr_pages); - return nr_pages; - } - - nr_ranges = nr_pages/FUSE_DAX_PAGES; - pr_debug("%s: dax mapped %ld pages. nr_ranges=%ld\n", - __func__, nr_pages, nr_ranges); - - for (i = 0; i < nr_ranges; i++) { - range = kzalloc(sizeof(struct fuse_dax_mapping), GFP_KERNEL); - ret = -ENOMEM; - if (!range) - goto out_err; - - /* TODO: This offset only works if virtio-fs driver is not - * having some memory hidden at the beginning. This needs - * better handling - */ - range->window_offset = i * FUSE_DAX_SZ; - range->length = FUSE_DAX_SZ; - INIT_LIST_HEAD(&range->busy_list); - refcount_set(&range->refcnt, 1); - list_add_tail(&range->list, &fcd->free_ranges); - } - - fcd->nr_free_ranges = nr_ranges; - fcd->nr_ranges = nr_ranges; - return 0; -out_err: - /* Free All allocated elements */ - fuse_free_dax_mem_ranges(&fcd->free_ranges); - return ret; -} - -int fuse_dax_conn_alloc(struct fuse_conn *fc, struct dax_device *dax_dev) -{ - struct fuse_conn_dax *fcd; - int err; - - if (!dax_dev) - return 0; - - fcd = kzalloc(sizeof(*fcd), GFP_KERNEL); - if (!fcd) - return -ENOMEM; - - spin_lock_init(&fcd->lock); - fcd->dev = dax_dev; - err = fuse_dax_mem_range_init(fcd); - if (err) { - kfree(fcd); - return err; - } - - fc->dax = fcd; - return 0; -} - -bool fuse_dax_inode_alloc(struct super_block *sb, struct fuse_inode *fi) -{ - struct fuse_conn *fc = get_fuse_conn_super(sb); - - fi->dax = NULL; - if (fc->dax) { - fi->dax = kzalloc(sizeof(*fi->dax), GFP_KERNEL_ACCOUNT); - if (!fi->dax) - return false; - - init_rwsem(&fi->dax->sem); - fi->dax->tree = RB_ROOT_CACHED; - } - - return true; -} - -static const struct address_space_operations fuse_dax_file_aops = { - .writepages = fuse_dax_writepages, - .direct_IO = noop_direct_IO, - .set_page_dirty = noop_set_page_dirty, - .invalidatepage = noop_invalidatepage, -}; - -void fuse_dax_inode_init(struct inode *inode) -{ - struct fuse_conn *fc = get_fuse_conn(inode); - - if (!fc->dax) - return; - - inode->i_flags |= S_DAX; - inode->i_data.a_ops = &fuse_dax_file_aops; -} - -bool fuse_dax_check_alignment(struct fuse_conn *fc, unsigned int map_alignment) -{ - if (fc->dax && (map_alignment > FUSE_DAX_SHIFT)) { - pr_warn("FUSE: map_alignment %u incompatible with dax mem range size %u\n", - map_alignment, FUSE_DAX_SZ); - return false; - } - return true; -} - -void fuse_dax_cancel_work(struct fuse_conn *fc) -{ - struct fuse_conn_dax *fcd = fc->dax; - - if (fcd) - cancel_delayed_work_sync(&fcd->free_work); - -} -EXPORT_SYMBOL_GPL(fuse_dax_cancel_work); diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c index c908eb46cbd0..90afaa7eeeeb 100644 --- a/fs/fuse/dev.c +++ b/fs/fuse/dev.c @@ -42,21 +42,20 @@ static struct fuse_dev *fuse_get_dev(struct file *file) return READ_ONCE(file->private_data); } -static void fuse_request_init(struct fuse_mount *fm, struct fuse_req *req) +static void fuse_request_init(struct fuse_req *req) { INIT_LIST_HEAD(&req->list); INIT_LIST_HEAD(&req->intr_entry); init_waitqueue_head(&req->waitq); refcount_set(&req->count, 1); __set_bit(FR_PENDING, &req->flags); - req->fm = fm; } -static struct fuse_req *fuse_request_alloc(struct fuse_mount *fm, gfp_t flags) +static struct fuse_req *fuse_request_alloc(gfp_t flags) { struct fuse_req *req = kmem_cache_zalloc(fuse_req_cachep, flags); if (req) - fuse_request_init(fm, req); + fuse_request_init(req); return req; } @@ -103,11 +102,10 @@ static void fuse_drop_waiting(struct fuse_conn *fc) } } -static void fuse_put_request(struct fuse_req *req); +static void fuse_put_request(struct fuse_conn *fc, struct fuse_req *req); -static struct fuse_req *fuse_get_req(struct fuse_mount *fm, bool for_background) +static struct fuse_req *fuse_get_req(struct fuse_conn *fc, bool for_background) { - struct fuse_conn *fc = fm->fc; struct fuse_req *req; int err; atomic_inc(&fc->num_waiting); @@ -129,7 +127,7 @@ static struct fuse_req *fuse_get_req(struct fuse_mount *fm, bool for_background) if (fc->conn_error) goto out; - req = fuse_request_alloc(fm, GFP_KERNEL); + req = fuse_request_alloc(GFP_KERNEL); err = -ENOMEM; if (!req) { if (for_background) @@ -147,7 +145,7 @@ static struct fuse_req *fuse_get_req(struct fuse_mount *fm, bool for_background) if (unlikely(req->in.h.uid == ((uid_t)-1) || req->in.h.gid == ((gid_t)-1))) { - fuse_put_request(req); + fuse_put_request(fc, req); return ERR_PTR(-EOVERFLOW); } return req; @@ -157,10 +155,8 @@ static struct fuse_req *fuse_get_req(struct fuse_mount *fm, bool for_background) return ERR_PTR(err); } -static void fuse_put_request(struct fuse_req *req) +static void fuse_put_request(struct fuse_conn *fc, struct fuse_req *req) { - struct fuse_conn *fc = req->fm->fc; - if (refcount_dec_and_test(&req->count)) { if (test_bit(FR_BACKGROUND, &req->flags)) { /* @@ -243,11 +239,6 @@ void fuse_queue_forget(struct fuse_conn *fc, struct fuse_forget_link *forget, { struct fuse_iqueue *fiq = &fc->iq; - if (nodeid == 0) { - kfree(forget); - return; - } - forget->forget_one.nodeid = nodeid; forget->forget_one.nlookup = nlookup; @@ -287,10 +278,8 @@ static void flush_bg_queue(struct fuse_conn *fc) * the 'end' callback is called if given, else the reference to the * request is released */ -void fuse_request_end(struct fuse_req *req) +void fuse_request_end(struct fuse_conn *fc, struct fuse_req *req) { - struct fuse_mount *fm = req->fm; - struct fuse_conn *fc = fm->fc; struct fuse_iqueue *fiq = &fc->iq; if (test_and_set_bit(FR_FINISHED, &req->flags)) @@ -325,9 +314,9 @@ void fuse_request_end(struct fuse_req *req) wake_up(&fc->blocked_waitq); } - if (fc->num_background == fc->congestion_threshold && fm->sb) { - clear_bdi_congested(fm->sb->s_bdi, BLK_RW_SYNC); - clear_bdi_congested(fm->sb->s_bdi, BLK_RW_ASYNC); + if (fc->num_background == fc->congestion_threshold && fc->sb) { + clear_bdi_congested(fc->sb->s_bdi, BLK_RW_SYNC); + clear_bdi_congested(fc->sb->s_bdi, BLK_RW_ASYNC); } fc->num_background--; fc->active_background--; @@ -339,16 +328,14 @@ void fuse_request_end(struct fuse_req *req) } if (test_bit(FR_ASYNC, &req->flags)) - req->args->end(fm, req->args, req->out.h.error); + req->args->end(fc, req->args, req->out.h.error); put_request: - fuse_put_request(req); + fuse_put_request(fc, req); } EXPORT_SYMBOL_GPL(fuse_request_end); -static int queue_interrupt(struct fuse_req *req) +static int queue_interrupt(struct fuse_iqueue *fiq, struct fuse_req *req) { - struct fuse_iqueue *fiq = &req->fm->fc->iq; - spin_lock(&fiq->lock); /* Check for we've sent request to interrupt this req */ if (unlikely(!test_bit(FR_INTERRUPTED, &req->flags))) { @@ -360,7 +347,7 @@ static int queue_interrupt(struct fuse_req *req) list_add_tail(&req->intr_entry, &fiq->interrupts); /* * Pairs with smp_mb() implied by test_and_set_bit() - * from fuse_request_end(). + * from request_end(). */ smp_mb(); if (test_bit(FR_FINISHED, &req->flags)) { @@ -375,9 +362,8 @@ static int queue_interrupt(struct fuse_req *req) return 0; } -static void request_wait_answer(struct fuse_req *req) +static void request_wait_answer(struct fuse_conn *fc, struct fuse_req *req) { - struct fuse_conn *fc = req->fm->fc; struct fuse_iqueue *fiq = &fc->iq; int err; @@ -392,7 +378,7 @@ static void request_wait_answer(struct fuse_req *req) /* matches barrier in fuse_dev_do_read() */ smp_mb__after_atomic(); if (test_bit(FR_SENT, &req->flags)) - queue_interrupt(req); + queue_interrupt(fiq, req); } if (!test_bit(FR_FORCE, &req->flags)) { @@ -423,9 +409,9 @@ static void request_wait_answer(struct fuse_req *req) test_bit(FR_FINISHED, &req->flags)); } -static void __fuse_request_send(struct fuse_req *req) +static void __fuse_request_send(struct fuse_conn *fc, struct fuse_req *req) { - struct fuse_iqueue *fiq = &req->fm->fc->iq; + struct fuse_iqueue *fiq = &fc->iq; BUG_ON(test_bit(FR_BACKGROUND, &req->flags)); spin_lock(&fiq->lock); @@ -439,7 +425,7 @@ static void __fuse_request_send(struct fuse_req *req) __fuse_get_request(req); queue_request_and_unlock(fiq, req, 1); - request_wait_answer(req); + request_wait_answer(fc, req); /* Pairs with smp_wmb() in fuse_request_end() */ smp_rmb(); } @@ -478,10 +464,8 @@ static void fuse_adjust_compat(struct fuse_conn *fc, struct fuse_args *args) } } -static void fuse_force_creds(struct fuse_req *req) +static void fuse_force_creds(struct fuse_conn *fc, struct fuse_req *req) { - struct fuse_conn *fc = req->fm->fc; - req->in.h.uid = from_kuid_munged(fc->user_ns, current_fsuid()); req->in.h.gid = from_kgid_munged(fc->user_ns, current_fsgid()); req->in.h.pid = pid_nr_ns(task_pid(current), fc->pid_ns); @@ -491,30 +475,28 @@ static void fuse_args_to_req(struct fuse_req *req, struct fuse_args *args) { req->in.h.opcode = args->opcode; req->in.h.nodeid = args->nodeid; - req->in.h.error_in = args->error_in; req->args = args; if (args->end) __set_bit(FR_ASYNC, &req->flags); } -ssize_t fuse_simple_request(struct fuse_mount *fm, struct fuse_args *args) +ssize_t fuse_simple_request(struct fuse_conn *fc, struct fuse_args *args) { - struct fuse_conn *fc = fm->fc; struct fuse_req *req; ssize_t ret; if (args->force) { atomic_inc(&fc->num_waiting); - req = fuse_request_alloc(fm, GFP_KERNEL | __GFP_NOFAIL); + req = fuse_request_alloc(GFP_KERNEL | __GFP_NOFAIL); if (!args->nocreds) - fuse_force_creds(req); + fuse_force_creds(fc, req); __set_bit(FR_WAITING, &req->flags); __set_bit(FR_FORCE, &req->flags); } else { WARN_ON(args->nocreds); - req = fuse_get_req(fm, false); + req = fuse_get_req(fc, false); if (IS_ERR(req)) return PTR_ERR(req); } @@ -525,21 +507,20 @@ ssize_t fuse_simple_request(struct fuse_mount *fm, struct fuse_args *args) if (!args->noreply) __set_bit(FR_ISREPLY, &req->flags); - __fuse_request_send(req); + __fuse_request_send(fc, req); ret = req->out.h.error; if (!ret && args->out_argvar) { BUG_ON(args->out_numargs == 0); ret = args->out_args[args->out_numargs - 1].size; } - fuse_put_request(req); + fuse_put_request(fc, req); return ret; } -static bool fuse_request_queue_background(struct fuse_req *req) +static bool fuse_request_queue_background(struct fuse_conn *fc, + struct fuse_req *req) { - struct fuse_mount *fm = req->fm; - struct fuse_conn *fc = fm->fc; bool queued = false; WARN_ON(!test_bit(FR_BACKGROUND, &req->flags)); @@ -553,9 +534,9 @@ static bool fuse_request_queue_background(struct fuse_req *req) fc->num_background++; if (fc->num_background == fc->max_background) fc->blocked = 1; - if (fc->num_background == fc->congestion_threshold && fm->sb) { - set_bdi_congested(fm->sb->s_bdi, BLK_RW_SYNC); - set_bdi_congested(fm->sb->s_bdi, BLK_RW_ASYNC); + if (fc->num_background == fc->congestion_threshold && fc->sb) { + set_bdi_congested(fc->sb->s_bdi, BLK_RW_SYNC); + set_bdi_congested(fc->sb->s_bdi, BLK_RW_ASYNC); } list_add_tail(&req->list, &fc->bg_queue); flush_bg_queue(fc); @@ -566,28 +547,28 @@ static bool fuse_request_queue_background(struct fuse_req *req) return queued; } -int fuse_simple_background(struct fuse_mount *fm, struct fuse_args *args, +int fuse_simple_background(struct fuse_conn *fc, struct fuse_args *args, gfp_t gfp_flags) { struct fuse_req *req; if (args->force) { WARN_ON(!args->nocreds); - req = fuse_request_alloc(fm, gfp_flags); + req = fuse_request_alloc(gfp_flags); if (!req) return -ENOMEM; __set_bit(FR_BACKGROUND, &req->flags); } else { WARN_ON(args->nocreds); - req = fuse_get_req(fm, true); + req = fuse_get_req(fc, true); if (IS_ERR(req)) return PTR_ERR(req); } fuse_args_to_req(req, args); - if (!fuse_request_queue_background(req)) { - fuse_put_request(req); + if (!fuse_request_queue_background(fc, req)) { + fuse_put_request(fc, req); return -ENOTCONN; } @@ -595,14 +576,14 @@ int fuse_simple_background(struct fuse_mount *fm, struct fuse_args *args, } EXPORT_SYMBOL_GPL(fuse_simple_background); -static int fuse_simple_notify_reply(struct fuse_mount *fm, +static int fuse_simple_notify_reply(struct fuse_conn *fc, struct fuse_args *args, u64 unique) { struct fuse_req *req; - struct fuse_iqueue *fiq = &fm->fc->iq; + struct fuse_iqueue *fiq = &fc->iq; int err = 0; - req = fuse_get_req(fm, false); + req = fuse_get_req(fc, false); if (IS_ERR(req)) return PTR_ERR(req); @@ -617,7 +598,7 @@ static int fuse_simple_notify_reply(struct fuse_mount *fm, } else { err = -ENODEV; spin_unlock(&fiq->lock); - fuse_put_request(req); + fuse_put_request(fc, req); } return err; @@ -696,10 +677,6 @@ static void fuse_copy_finish(struct fuse_copy_state *cs) flush_dcache_page(cs->pg); set_page_dirty_lock(cs->pg); } - /* - * The page could be GUP page(see iov_iter_get_pages in - * fuse_copy_fill) so use put_page to release it. - */ put_page(cs->pg); } cs->pg = NULL; @@ -803,7 +780,8 @@ static int fuse_check_page(struct page *page) 1 << PG_workingset | 1 << PG_reclaim | 1 << PG_waiters))) { - dump_page(page, "fuse: trying to steal weird page"); + pr_warn("trying to steal weird page\n"); + pr_warn(" page=%p index=%li flags=%08lx, count=%i, mapcount=%i, mapping=%p\n", page, page->index, page->flags, page_count(page), page_mapcount(page), page->mapping); return 1; } return 0; @@ -1305,7 +1283,7 @@ static ssize_t fuse_dev_do_read(struct fuse_dev *fud, struct file *file, /* SETXATTR is special, since it may contain too large data */ if (args->opcode == FUSE_SETXATTR) req->out.h.error = -E2BIG; - fuse_request_end(req); + fuse_request_end(fc, req); goto restart; } spin_lock(&fpq->lock); @@ -1348,8 +1326,8 @@ static ssize_t fuse_dev_do_read(struct fuse_dev *fud, struct file *file, /* matches barrier in request_wait_answer() */ smp_mb__after_atomic(); if (test_bit(FR_INTERRUPTED, &req->flags)) - queue_interrupt(req); - fuse_put_request(req); + queue_interrupt(fiq, req); + fuse_put_request(fc, req); return reqsize; @@ -1357,7 +1335,7 @@ out_end: if (!test_bit(FR_PRIVATE, &req->flags)) list_del_init(&req->list); spin_unlock(&fpq->lock); - fuse_request_end(req); + fuse_request_end(fc, req); return err; err_unlock: @@ -1480,8 +1458,11 @@ static int fuse_notify_inval_inode(struct fuse_conn *fc, unsigned int size, fuse_copy_finish(cs); down_read(&fc->killsb); - err = fuse_reverse_inval_inode(fc, outarg.ino, - outarg.off, outarg.len); + err = -ENOENT; + if (fc->sb) { + err = fuse_reverse_inval_inode(fc->sb, outarg.ino, + outarg.off, outarg.len); + } up_read(&fc->killsb); return err; @@ -1527,7 +1508,9 @@ static int fuse_notify_inval_entry(struct fuse_conn *fc, unsigned int size, buf[outarg.namelen] = 0; down_read(&fc->killsb); - err = fuse_reverse_inval_entry(fc, outarg.parent, 0, &name); + err = -ENOENT; + if (fc->sb) + err = fuse_reverse_inval_entry(fc->sb, outarg.parent, 0, &name); up_read(&fc->killsb); kfree(buf); return err; @@ -1575,7 +1558,10 @@ static int fuse_notify_delete(struct fuse_conn *fc, unsigned int size, buf[outarg.namelen] = 0; down_read(&fc->killsb); - err = fuse_reverse_inval_entry(fc, outarg.parent, outarg.child, &name); + err = -ENOENT; + if (fc->sb) + err = fuse_reverse_inval_entry(fc->sb, outarg.parent, + outarg.child, &name); up_read(&fc->killsb); kfree(buf); return err; @@ -1617,7 +1603,10 @@ static int fuse_notify_store(struct fuse_conn *fc, unsigned int size, down_read(&fc->killsb); err = -ENOENT; - inode = fuse_ilookup(fc, nodeid, NULL); + if (!fc->sb) + goto out_up_killsb; + + inode = ilookup5(fc->sb, nodeid, fuse_inode_eq, &nodeid); if (!inode) goto out_up_killsb; @@ -1676,7 +1665,7 @@ struct fuse_retrieve_args { struct fuse_notify_retrieve_in inarg; }; -static void fuse_retrieve_end(struct fuse_mount *fm, struct fuse_args *args, +static void fuse_retrieve_end(struct fuse_conn *fc, struct fuse_args *args, int error) { struct fuse_retrieve_args *ra = @@ -1686,7 +1675,7 @@ static void fuse_retrieve_end(struct fuse_mount *fm, struct fuse_args *args, kfree(ra); } -static int fuse_retrieve(struct fuse_mount *fm, struct inode *inode, +static int fuse_retrieve(struct fuse_conn *fc, struct inode *inode, struct fuse_notify_retrieve_out *outarg) { int err; @@ -1697,7 +1686,6 @@ static int fuse_retrieve(struct fuse_mount *fm, struct inode *inode, unsigned int offset; size_t total_len = 0; unsigned int num_pages; - struct fuse_conn *fc = fm->fc; struct fuse_retrieve_args *ra; size_t args_size = sizeof(*ra); struct fuse_args_pages *ap; @@ -1759,9 +1747,9 @@ static int fuse_retrieve(struct fuse_mount *fm, struct inode *inode, args->in_args[0].value = &ra->inarg; args->in_args[1].size = total_len; - err = fuse_simple_notify_reply(fm, args, outarg->notify_unique); + err = fuse_simple_notify_reply(fc, args, outarg->notify_unique); if (err) - fuse_retrieve_end(fm, args, err); + fuse_retrieve_end(fc, args, err); return err; } @@ -1770,9 +1758,7 @@ static int fuse_notify_retrieve(struct fuse_conn *fc, unsigned int size, struct fuse_copy_state *cs) { struct fuse_notify_retrieve_out outarg; - struct fuse_mount *fm; struct inode *inode; - u64 nodeid; int err; err = -EINVAL; @@ -1787,12 +1773,14 @@ static int fuse_notify_retrieve(struct fuse_conn *fc, unsigned int size, down_read(&fc->killsb); err = -ENOENT; - nodeid = outarg.nodeid; + if (fc->sb) { + u64 nodeid = outarg.nodeid; - inode = fuse_ilookup(fc, nodeid, &fm); - if (inode) { - err = fuse_retrieve(fm, inode, &outarg); - iput(inode); + inode = ilookup5(fc->sb, nodeid, fuse_inode_eq, &nodeid); + if (inode) { + err = fuse_retrieve(fc, inode, &outarg); + iput(inode); + } } up_read(&fc->killsb); @@ -1931,9 +1919,9 @@ static ssize_t fuse_dev_do_write(struct fuse_dev *fud, else if (oh.error == -ENOSYS) fc->no_interrupt = 1; else if (oh.error == -EAGAIN) - err = queue_interrupt(req); + err = queue_interrupt(&fc->iq, req); - fuse_put_request(req); + fuse_put_request(fc, req); goto copy_finish; } @@ -1959,19 +1947,6 @@ static ssize_t fuse_dev_do_write(struct fuse_dev *fud, req->out.h.error = kern_path(path, 0, req->args->canonical_path); } - if (!err && (req->in.h.opcode == FUSE_LOOKUP || - req->in.h.opcode == (FUSE_LOOKUP | FUSE_POSTFILTER)) && - req->args->out_args[1].size == sizeof(struct fuse_entry_bpf_out)) { - struct fuse_entry_bpf_out *febo = (struct fuse_entry_bpf_out *) - req->args->out_args[1].value; - struct fuse_entry_bpf *feb = container_of(febo, struct fuse_entry_bpf, out); - - if (febo->backing_action == FUSE_ACTION_REPLACE) - feb->backing_file = fget(febo->backing_fd); - if (febo->bpf_action == FUSE_ACTION_REPLACE) - feb->bpf_file = fget(febo->bpf_fd); - } - spin_lock(&fpq->lock); clear_bit(FR_LOCKED, &req->flags); if (!fpq->connected) @@ -1982,7 +1957,7 @@ static ssize_t fuse_dev_do_write(struct fuse_dev *fud, list_del_init(&req->list); spin_unlock(&fpq->lock); - fuse_request_end(req); + fuse_request_end(fc, req); out: return err ? err : nbytes; @@ -2118,7 +2093,7 @@ static __poll_t fuse_dev_poll(struct file *file, poll_table *wait) } /* Abort all requests on the given list (pending or processing) */ -static void end_requests(struct list_head *head) +static void end_requests(struct fuse_conn *fc, struct list_head *head) { while (!list_empty(head)) { struct fuse_req *req; @@ -2126,7 +2101,7 @@ static void end_requests(struct list_head *head) req->out.h.error = -ECONNABORTED; clear_bit(FR_SENT, &req->flags); list_del_init(&req->list); - fuse_request_end(req); + fuse_request_end(fc, req); } } @@ -2221,7 +2196,7 @@ void fuse_abort_conn(struct fuse_conn *fc) wake_up_all(&fc->blocked_waitq); spin_unlock(&fc->lock); - end_requests(&to_end); + end_requests(fc, &to_end); } else { spin_unlock(&fc->lock); } @@ -2251,7 +2226,7 @@ int fuse_dev_release(struct inode *inode, struct file *file) list_splice_init(&fpq->processing[i], &to_end); spin_unlock(&fpq->lock); - end_requests(&to_end); + end_requests(fc, &to_end); /* Are we the last open device? */ if (atomic_dec_and_test(&fc->dev_count)) { @@ -2353,7 +2328,7 @@ const struct file_operations fuse_dev_operations = { .release = fuse_dev_release, .fasync = fuse_dev_fasync, .unlocked_ioctl = fuse_dev_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = fuse_dev_ioctl, }; EXPORT_SYMBOL_GPL(fuse_dev_operations); diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c index a55375ae2797..7cf55a7635fa 100644 --- a/fs/fuse/dir.c +++ b/fs/fuse/dir.c @@ -8,11 +8,8 @@ #include "fuse_i.h" -#include #include #include -#include -#include #include #include #include @@ -20,8 +17,6 @@ #include #include -#include "../internal.h" - static void fuse_advise_use_readdirplus(struct inode *dir) { struct fuse_inode *fi = get_fuse_inode(dir); @@ -29,7 +24,7 @@ static void fuse_advise_use_readdirplus(struct inode *dir) set_bit(FUSE_I_ADVISE_RDPLUS, &fi->state); } -#if BITS_PER_LONG >= 64 && !defined(CONFIG_FUSE_BPF) +#if BITS_PER_LONG >= 64 static inline void __fuse_dentry_settime(struct dentry *entry, u64 time) { entry->d_fsdata = (void *) time; @@ -41,15 +36,19 @@ static inline u64 fuse_dentry_time(const struct dentry *entry) } #else +union fuse_dentry { + u64 time; + struct rcu_head rcu; +}; static inline void __fuse_dentry_settime(struct dentry *dentry, u64 time) { - ((struct fuse_dentry *) dentry->d_fsdata)->time = time; + ((union fuse_dentry *) dentry->d_fsdata)->time = time; } static inline u64 fuse_dentry_time(const struct dentry *entry) { - return ((struct fuse_dentry *) entry->d_fsdata)->time; + return ((union fuse_dentry *) entry->d_fsdata)->time; } #endif @@ -74,16 +73,26 @@ static void fuse_dentry_settime(struct dentry *dentry, u64 time) __fuse_dentry_settime(dentry, time); } -void fuse_init_dentry_root(struct dentry *root, struct file *backing_dir) -{ -#ifdef CONFIG_FUSE_BPF - struct fuse_dentry *fuse_dentry = root->d_fsdata; +/* + * FUSE caches dentries and attributes with separate timeout. The + * time in jiffies until the dentry/attributes are valid is stored in + * dentry->d_fsdata and fuse_inode->i_time respectively. + */ - if (backing_dir) { - fuse_dentry->backing_path = backing_dir->f_path; - path_get(&fuse_dentry->backing_path); - } -#endif +/* + * Calculate the time in jiffies until a dentry/attributes are valid + */ +static u64 time_to_jiffies(u64 sec, u32 nsec) +{ + if (sec || nsec) { + struct timespec64 ts = { + sec, + min_t(u32, nsec, NSEC_PER_SEC - 1) + }; + + return get_jiffies_64() + timespec64_to_jiffies(&ts); + } else + return 0; } /* @@ -96,6 +105,11 @@ void fuse_change_entry_timeout(struct dentry *entry, struct fuse_entry_out *o) time_to_jiffies(o->entry_valid, o->entry_valid_nsec)); } +static u64 attr_timeout(struct fuse_attr_out *o) +{ + return time_to_jiffies(o->attr_valid, o->attr_valid_nsec); +} + u64 entry_attr_timeout(struct fuse_entry_out *o) { return time_to_jiffies(o->attr_valid, o->attr_valid_nsec); @@ -156,8 +170,7 @@ static void fuse_invalidate_entry(struct dentry *entry) static void fuse_lookup_init(struct fuse_conn *fc, struct fuse_args *args, u64 nodeid, const struct qstr *name, - struct fuse_entry_out *outarg, - struct fuse_entry_bpf_out *bpf_outarg) + struct fuse_entry_out *outarg) { memset(outarg, 0, sizeof(struct fuse_entry_out)); args->opcode = FUSE_LOOKUP; @@ -165,57 +178,11 @@ static void fuse_lookup_init(struct fuse_conn *fc, struct fuse_args *args, args->in_numargs = 1; args->in_args[0].size = name->len + 1; args->in_args[0].value = name->name; - args->out_argvar = true; - args->out_numargs = 2; + args->out_numargs = 1; args->out_args[0].size = sizeof(struct fuse_entry_out); args->out_args[0].value = outarg; - args->out_args[1].size = sizeof(struct fuse_entry_bpf_out); - args->out_args[1].value = bpf_outarg; } -#ifdef CONFIG_FUSE_BPF -static bool backing_data_changed(struct fuse_inode *fi, struct dentry *entry, - struct fuse_entry_bpf *bpf_arg) -{ - struct path new_backing_path; - struct inode *new_backing_inode; - struct bpf_prog *bpf = NULL; - int err; - bool ret = true; - - if (!entry || !fi->backing_inode) { - ret = false; - goto put_backing_file; - } - - get_fuse_backing_path(entry, &new_backing_path); - new_backing_inode = fi->backing_inode; - ihold(new_backing_inode); - - err = fuse_handle_backing(bpf_arg, &new_backing_inode, &new_backing_path); - - if (err) - goto put_inode; - - err = fuse_handle_bpf_prog(bpf_arg, entry->d_parent->d_inode, &bpf); - if (err) - goto put_bpf; - - ret = (bpf != fi->bpf || fi->backing_inode != new_backing_inode || - !path_equal(&get_fuse_dentry(entry)->backing_path, &new_backing_path)); -put_bpf: - if (bpf) - bpf_prog_put(bpf); -put_inode: - iput(new_backing_inode); - path_put(&new_backing_path); -put_backing_file: - if (bpf_arg->backing_file) - fput(bpf_arg->backing_file); - return ret; -} -#endif - /* * Check whether the dentry is still valid * @@ -229,29 +196,16 @@ static int fuse_dentry_revalidate(struct dentry *entry, unsigned int flags) { struct inode *inode; struct dentry *parent; - struct fuse_mount *fm; + struct fuse_conn *fc; struct fuse_inode *fi; int ret; inode = d_inode_rcu(entry); if (inode && fuse_is_bad(inode)) goto invalid; -#ifdef CONFIG_FUSE_BPF - /* TODO: Do we need bpf support for revalidate? - * If the lower filesystem says the entry is invalid, FUSE probably shouldn't - * try to fix that without going through the normal lookup path... - */ - if (get_fuse_dentry(entry)->backing_path.dentry) { - ret = fuse_revalidate_backing(entry, flags); - if (ret <= 0) { - goto out; - } - } -#endif - if (time_before64(fuse_dentry_time(entry), get_jiffies_64()) || - (flags & (LOOKUP_EXCL | LOOKUP_REVAL | LOOKUP_RENAME_TARGET))) { + else if (time_before64(fuse_dentry_time(entry), get_jiffies_64()) || + (flags & LOOKUP_REVAL)) { struct fuse_entry_out outarg; - struct fuse_entry_bpf bpf_arg; FUSE_ARGS(args); struct fuse_forget_link *forget; u64 attr_version; @@ -263,47 +217,28 @@ static int fuse_dentry_revalidate(struct dentry *entry, unsigned int flags) ret = -ECHILD; if (flags & LOOKUP_RCU) goto out; - fm = get_fuse_mount(inode); - parent = dget_parent(entry); + fc = get_fuse_conn(inode); -#ifdef CONFIG_FUSE_BPF - /* TODO: Once we're handling timeouts for backing inodes, do a - * bpf based lookup_revalidate here. - */ - if (get_fuse_inode(parent->d_inode)->backing_inode) { - dput(parent); - ret = 1; - goto out; - } -#endif forget = fuse_alloc_forget(); ret = -ENOMEM; - if (!forget) { - dput(parent); + if (!forget) goto out; - } - attr_version = fuse_get_attr_version(fm->fc); + attr_version = fuse_get_attr_version(fc); - fuse_lookup_init(fm->fc, &args, get_node_id(d_inode(parent)), - &entry->d_name, &outarg, &bpf_arg.out); - ret = fuse_simple_request(fm, &args); + parent = dget_parent(entry); + fuse_lookup_init(fc, &args, get_node_id(d_inode(parent)), + &entry->d_name, &outarg); + ret = fuse_simple_request(fc, &args); dput(parent); - /* Zero nodeid is same as -ENOENT */ if (!ret && !outarg.nodeid) ret = -ENOENT; - if (!ret || ret == sizeof(bpf_arg.out)) { + if (!ret) { fi = get_fuse_inode(inode); - if (outarg.nodeid != get_node_id(inode) || -#ifdef CONFIG_FUSE_BPF - (ret == sizeof(bpf_arg.out) && - backing_data_changed(fi, entry, &bpf_arg)) || -#endif - (bool) IS_AUTOMOUNT(inode) != (bool) (outarg.attr.flags & FUSE_ATTR_SUBMOUNT)) { - fuse_queue_forget(fm->fc, forget, - outarg.nodeid, 1); + if (outarg.nodeid != get_node_id(inode)) { + fuse_queue_forget(fc, forget, outarg.nodeid, 1); goto invalid; } spin_lock(&fi->lock); @@ -314,7 +249,7 @@ static int fuse_dentry_revalidate(struct dentry *entry, unsigned int flags) if (ret == -ENOMEM || ret == -EINTR) goto out; if (ret || fuse_invalid_attr(&outarg.attr) || - fuse_stale_inode(inode, outarg.generation, &outarg.attr)) + (outarg.attr.mode ^ inode->i_mode) & S_IFMT) goto invalid; forget_all_cached_acls(inode); @@ -342,25 +277,17 @@ invalid: goto out; } -#if BITS_PER_LONG < 64 || defined(CONFIG_FUSE_BPF) +#if BITS_PER_LONG < 64 static int fuse_dentry_init(struct dentry *dentry) { - dentry->d_fsdata = kzalloc(sizeof(struct fuse_dentry), + dentry->d_fsdata = kzalloc(sizeof(union fuse_dentry), GFP_KERNEL_ACCOUNT | __GFP_RECLAIMABLE); return dentry->d_fsdata ? 0 : -ENOMEM; } static void fuse_dentry_release(struct dentry *dentry) { - struct fuse_dentry *fd = dentry->d_fsdata; - -#ifdef CONFIG_FUSE_BPF - if (fd && fd->backing_path.dentry) - path_put(&fd->backing_path); - - if (fd && fd->bpf) - bpf_prog_put(fd->bpf); -#endif + union fuse_dentry *fd = dentry->d_fsdata; kfree_rcu(fd, rcu); } @@ -379,25 +306,11 @@ static int fuse_dentry_delete(const struct dentry *dentry) */ static void fuse_dentry_canonical_path(const struct path *path, struct path *canonical_path) { struct inode *inode = d_inode(path->dentry); - //struct fuse_conn *fc = get_fuse_conn(inode); - struct fuse_mount *fm = get_fuse_mount_super(path->mnt->mnt_sb); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); char *path_name; int err; - -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_dummy_io, - fuse_canonical_path_initialize, - fuse_canonical_path_backing, - fuse_canonical_path_finalize, path, - canonical_path); - if (fer.ret) - return; -#endif - path_name = (char *)get_zeroed_page(GFP_KERNEL); if (!path_name) goto default_path; @@ -411,7 +324,7 @@ static void fuse_dentry_canonical_path(const struct path *path, struct path *can args.canonical_path = canonical_path; args.out_argvar = 1; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); free_page((unsigned long)path_name); if (err > 0) return; @@ -421,107 +334,18 @@ default_path: path_get(canonical_path); } -/* - * Create a fuse_mount object with a new superblock (with path->dentry - * as the root), and return that mount so it can be auto-mounted on - * @path. - */ -static struct vfsmount *fuse_dentry_automount(struct path *path) -{ - struct fs_context *fsc; - struct fuse_mount *parent_fm = get_fuse_mount_super(path->mnt->mnt_sb); - struct fuse_conn *fc = parent_fm->fc; - struct fuse_mount *fm; - struct vfsmount *mnt; - struct fuse_inode *mp_fi = get_fuse_inode(d_inode(path->dentry)); - struct super_block *sb; - int err; - - fsc = fs_context_for_submount(path->mnt->mnt_sb->s_type, path->dentry); - if (IS_ERR(fsc)) { - err = PTR_ERR(fsc); - goto out; - } - - err = -ENOMEM; - fm = kzalloc(sizeof(struct fuse_mount), GFP_KERNEL); - if (!fm) - goto out_put_fsc; - - refcount_set(&fm->count, 1); - fsc->s_fs_info = fm; - sb = sget_fc(fsc, NULL, set_anon_super_fc); - if (IS_ERR(sb)) { - err = PTR_ERR(sb); - fuse_mount_put(fm); - goto out_put_fsc; - } - fm->fc = fuse_conn_get(fc); - - /* Initialize superblock, making @mp_fi its root */ - err = fuse_fill_super_submount(sb, mp_fi); - if (err) { - fuse_conn_put(fc); - kfree(fm); - sb->s_fs_info = NULL; - goto out_put_sb; - } - - down_write(&fc->killsb); - list_add_tail(&fm->fc_entry, &fc->mounts); - up_write(&fc->killsb); - - sb->s_flags |= SB_ACTIVE; - fsc->root = dget(sb->s_root); - - /* - * FIXME: setting SB_BORN requires a write barrier for - * super_cache_count(). We should actually come - * up with a proper ->get_tree() implementation - * for submounts and call vfs_get_tree() to take - * care of the write barrier. - */ - smp_wmb(); - sb->s_flags |= SB_BORN; - - /* We are done configuring the superblock, so unlock it */ - up_write(&sb->s_umount); - - /* Create the submount */ - mnt = vfs_create_mount(fsc); - if (IS_ERR(mnt)) { - err = PTR_ERR(mnt); - goto out_put_fsc; - } - mntget(mnt); - put_fs_context(fsc); - return mnt; - -out_put_sb: - /* - * Only jump here when fsc->root is NULL and sb is still locked - * (otherwise put_fs_context() will put the superblock) - */ - deactivate_locked_super(sb); -out_put_fsc: - put_fs_context(fsc); -out: - return ERR_PTR(err); -} - const struct dentry_operations fuse_dentry_operations = { .d_revalidate = fuse_dentry_revalidate, .d_delete = fuse_dentry_delete, -#if BITS_PER_LONG < 64 || defined(CONFIG_FUSE_BPF) +#if BITS_PER_LONG < 64 .d_init = fuse_dentry_init, .d_release = fuse_dentry_release, #endif - .d_automount = fuse_dentry_automount, .d_canonical_path = fuse_dentry_canonical_path, }; const struct dentry_operations fuse_root_dentry_operations = { -#if BITS_PER_LONG < 64 || defined(CONFIG_FUSE_BPF) +#if BITS_PER_LONG < 64 .d_init = fuse_dentry_init, .d_release = fuse_dentry_release, #endif @@ -540,13 +364,10 @@ bool fuse_invalid_attr(struct fuse_attr *attr) } int fuse_lookup_name(struct super_block *sb, u64 nodeid, const struct qstr *name, - struct fuse_entry_out *outarg, - struct dentry *entry, - struct inode **inode) + struct fuse_entry_out *outarg, struct inode **inode) { - struct fuse_mount *fm = get_fuse_mount_super(sb); + struct fuse_conn *fc = get_fuse_conn_super(sb); FUSE_ARGS(args); - struct fuse_entry_bpf bpf_arg = {0}; struct fuse_forget_link *forget; u64 attr_version; int err; @@ -556,77 +377,32 @@ int fuse_lookup_name(struct super_block *sb, u64 nodeid, const struct qstr *name if (name->len > FUSE_NAME_MAX) goto out; + forget = fuse_alloc_forget(); err = -ENOMEM; if (!forget) goto out; - attr_version = fuse_get_attr_version(fm->fc); + attr_version = fuse_get_attr_version(fc); - fuse_lookup_init(fm->fc, &args, nodeid, name, outarg, &bpf_arg.out); - err = fuse_simple_request(fm, &args); + fuse_lookup_init(fc, &args, nodeid, name, outarg); + err = fuse_simple_request(fc, &args); + /* Zero nodeid is same as -ENOENT, but with valid timeout */ + if (err || !outarg->nodeid) + goto out_put_forget; -#ifdef CONFIG_FUSE_BPF - if (err == sizeof(bpf_arg.out)) { - /* TODO Make sure this handles invalid handles */ - struct file *backing_file; - struct inode *backing_inode; - - err = -ENOENT; - if (!entry) - goto out_put_forget; - - err = -EINVAL; - backing_file = bpf_arg.backing_file; - if (!backing_file) - goto out_put_forget; - - if (IS_ERR(backing_file)) { - err = PTR_ERR(backing_file); - goto out_put_forget; - } - - backing_inode = backing_file->f_inode; - *inode = fuse_iget_backing(sb, outarg->nodeid, backing_inode); - if (!*inode) - goto out_put_forget; - - err = fuse_handle_backing(&bpf_arg, - &get_fuse_inode(*inode)->backing_inode, - &get_fuse_dentry(entry)->backing_path); - if (!err) - err = fuse_handle_bpf_prog(&bpf_arg, NULL, - &get_fuse_inode(*inode)->bpf); - if (err) { - iput(*inode); - *inode = NULL; - goto out_put_forget; - } - } else -#endif - { - /* Zero nodeid is same as -ENOENT, but with valid timeout */ - if (err || !outarg->nodeid) - goto out_put_forget; - - err = -EIO; - if (!outarg->nodeid) - goto out_put_forget; - if (fuse_invalid_attr(&outarg->attr)) - goto out_put_forget; - if (outarg->nodeid == FUSE_ROOT_ID && outarg->generation != 0) { - pr_warn_once("root generation should be zero\n"); - outarg->generation = 0; - } - - *inode = fuse_iget(sb, outarg->nodeid, outarg->generation, - &outarg->attr, entry_attr_timeout(outarg), - attr_version); - } + err = -EIO; + if (!outarg->nodeid) + goto out_put_forget; + if (fuse_invalid_attr(&outarg->attr)) + goto out_put_forget; + *inode = fuse_iget(sb, outarg->nodeid, outarg->generation, + &outarg->attr, entry_attr_timeout(outarg), + attr_version); err = -ENOMEM; - if (!*inode && outarg->nodeid) { - fuse_queue_forget(fm->fc, forget, outarg->nodeid, 1); + if (!*inode) { + fuse_queue_forget(fc, forget, outarg->nodeid, 1); goto out; } err = 0; @@ -634,8 +410,6 @@ int fuse_lookup_name(struct super_block *sb, u64 nodeid, const struct qstr *name out_put_forget: kfree(forget); out: - if (bpf_arg.backing_file) - fput(bpf_arg.backing_file); return err; } @@ -649,23 +423,12 @@ static struct dentry *fuse_lookup(struct inode *dir, struct dentry *entry, bool outarg_valid = true; bool locked; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(dir, struct fuse_lookup_io, - fuse_lookup_initialize, fuse_lookup_backing, - fuse_lookup_finalize, - dir, entry, flags); - if (fer.ret) - return fer.result; -#endif - if (fuse_is_bad(dir)) return ERR_PTR(-EIO); locked = fuse_lock_inode(dir); err = fuse_lookup_name(dir->i_sb, get_node_id(dir), &entry->d_name, - &outarg, entry, &inode); + &outarg, &inode); fuse_unlock_inode(dir, locked); if (err == -ENOENT) { outarg_valid = false; @@ -712,7 +475,6 @@ static int fuse_create_open(struct inode *dir, struct dentry *entry, int err; struct inode *inode; struct fuse_conn *fc = get_fuse_conn(dir); - struct fuse_mount *fm = get_fuse_mount(dir); FUSE_ARGS(args); struct fuse_forget_link *forget; struct fuse_create_in inarg; @@ -720,36 +482,21 @@ static int fuse_create_open(struct inode *dir, struct dentry *entry, struct fuse_entry_out outentry; struct fuse_inode *fi; struct fuse_file *ff; - bool trunc = flags & O_TRUNC; /* Userspace expects S_IFREG in create mode */ BUG_ON((mode & S_IFMT) != S_IFREG); -#ifdef CONFIG_FUSE_BPF - { - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(dir, struct fuse_create_open_io, - fuse_create_open_initialize, - fuse_create_open_backing, - fuse_create_open_finalize, - dir, entry, file, flags, mode); - if (fer.ret) - return PTR_ERR(fer.result); - } -#endif - forget = fuse_alloc_forget(); err = -ENOMEM; if (!forget) goto out_err; err = -ENOMEM; - ff = fuse_file_alloc(fm); + ff = fuse_file_alloc(fc); if (!ff) goto out_put_forget_req; - if (!fm->fc->dont_mask) + if (!fc->dont_mask) mode &= ~current_umask(); flags &= ~O_NOCTTY; @@ -770,7 +517,7 @@ static int fuse_create_open(struct inode *dir, struct dentry *entry, args.out_args[0].value = &outentry; args.out_args[1].size = sizeof(outopen); args.out_args[1].value = &outopen; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err) goto out_free_ff; @@ -788,7 +535,7 @@ static int fuse_create_open(struct inode *dir, struct dentry *entry, if (!inode) { flags &= ~(O_CREAT | O_EXCL | O_TRUNC); fuse_sync_release(NULL, ff, flags); - fuse_queue_forget(fm->fc, forget, outentry.nodeid, 1); + fuse_queue_forget(fc, forget, outentry.nodeid, 1); err = -ENOMEM; goto out_err; } @@ -803,10 +550,6 @@ static int fuse_create_open(struct inode *dir, struct dentry *entry, } else { file->private_data = ff; fuse_finish_open(inode, file); - if (fm->fc->atomic_o_trunc && trunc) - truncate_pagecache(inode, 0); - else if (!(ff->open_flags & FOPEN_KEEP_CACHE)) - invalidate_inode_pages2(inode->i_mapping); } return err; @@ -868,7 +611,7 @@ no_open: /* * Code shared between mknod, mkdir, symlink and link */ -static int create_new_entry(struct fuse_mount *fm, struct fuse_args *args, +static int create_new_entry(struct fuse_conn *fc, struct fuse_args *args, struct inode *dir, struct dentry *entry, umode_t mode) { @@ -890,7 +633,7 @@ static int create_new_entry(struct fuse_mount *fm, struct fuse_args *args, args->out_numargs = 1; args->out_args[0].size = sizeof(outarg); args->out_args[0].value = &outarg; - err = fuse_simple_request(fm, args); + err = fuse_simple_request(fc, args); if (err) goto out_put_forget_req; @@ -904,7 +647,7 @@ static int create_new_entry(struct fuse_mount *fm, struct fuse_args *args, inode = fuse_iget(dir->i_sb, outarg.nodeid, outarg.generation, &outarg.attr, entry_attr_timeout(&outarg), 0); if (!inode) { - fuse_queue_forget(fm->fc, forget, outarg.nodeid, 1); + fuse_queue_forget(fc, forget, outarg.nodeid, 1); return -ENOMEM; } kfree(forget); @@ -932,21 +675,10 @@ static int fuse_mknod(struct inode *dir, struct dentry *entry, umode_t mode, dev_t rdev) { struct fuse_mknod_in inarg; - struct fuse_mount *fm = get_fuse_mount(dir); + struct fuse_conn *fc = get_fuse_conn(dir); FUSE_ARGS(args); -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(dir, struct fuse_mknod_in, - fuse_mknod_initialize, fuse_mknod_backing, - fuse_mknod_finalize, - dir, entry, mode, rdev); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - - if (!fm->fc->dont_mask) + if (!fc->dont_mask) mode &= ~current_umask(); memset(&inarg, 0, sizeof(inarg)); @@ -959,7 +691,7 @@ static int fuse_mknod(struct inode *dir, struct dentry *entry, umode_t mode, args.in_args[0].value = &inarg; args.in_args[1].size = entry->d_name.len + 1; args.in_args[1].value = entry->d_name.name; - return create_new_entry(fm, &args, dir, entry, mode); + return create_new_entry(fc, &args, dir, entry, mode); } static int fuse_create(struct inode *dir, struct dentry *entry, umode_t mode, @@ -971,21 +703,10 @@ static int fuse_create(struct inode *dir, struct dentry *entry, umode_t mode, static int fuse_mkdir(struct inode *dir, struct dentry *entry, umode_t mode) { struct fuse_mkdir_in inarg; - struct fuse_mount *fm = get_fuse_mount(dir); + struct fuse_conn *fc = get_fuse_conn(dir); FUSE_ARGS(args); -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(dir, struct fuse_mkdir_in, - fuse_mkdir_initialize, fuse_mkdir_backing, - fuse_mkdir_finalize, - dir, entry, mode); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - - if (!fm->fc->dont_mask) + if (!fc->dont_mask) mode &= ~current_umask(); memset(&inarg, 0, sizeof(inarg)); @@ -997,41 +718,23 @@ static int fuse_mkdir(struct inode *dir, struct dentry *entry, umode_t mode) args.in_args[0].value = &inarg; args.in_args[1].size = entry->d_name.len + 1; args.in_args[1].value = entry->d_name.name; - return create_new_entry(fm, &args, dir, entry, S_IFDIR); + return create_new_entry(fc, &args, dir, entry, S_IFDIR); } static int fuse_symlink(struct inode *dir, struct dentry *entry, const char *link) { - struct fuse_mount *fm = get_fuse_mount(dir); + struct fuse_conn *fc = get_fuse_conn(dir); unsigned len = strlen(link) + 1; FUSE_ARGS(args); -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(dir, struct fuse_dummy_io, - fuse_symlink_initialize, fuse_symlink_backing, - fuse_symlink_finalize, - dir, entry, link, len); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - args.opcode = FUSE_SYMLINK; args.in_numargs = 2; args.in_args[0].size = entry->d_name.len + 1; args.in_args[0].value = entry->d_name.name; args.in_args[1].size = len; args.in_args[1].value = link; - return create_new_entry(fm, &args, dir, entry, S_IFLNK); -} - -void fuse_flush_time_update(struct inode *inode) -{ - int err = sync_inode_metadata(inode, 1); - - mapping_set_error(inode->i_mapping, err); + return create_new_entry(fc, &args, dir, entry, S_IFLNK); } void fuse_update_ctime(struct inode *inode) @@ -1039,45 +742,30 @@ void fuse_update_ctime(struct inode *inode) if (!IS_NOCMTIME(inode)) { inode->i_ctime = current_time(inode); mark_inode_dirty_sync(inode); - fuse_flush_time_update(inode); } } static int fuse_unlink(struct inode *dir, struct dentry *entry) { int err; - struct fuse_mount *fm = get_fuse_mount(dir); + struct fuse_conn *fc = get_fuse_conn(dir); FUSE_ARGS(args); if (fuse_is_bad(dir)) return -EIO; -#ifdef CONFIG_FUSE_BPF - { - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(dir, struct fuse_dummy_io, - fuse_unlink_initialize, - fuse_unlink_backing, - fuse_unlink_finalize, - dir, entry); - if (fer.ret) - return PTR_ERR(fer.result); - } -#endif - args.opcode = FUSE_UNLINK; args.nodeid = get_node_id(dir); args.in_numargs = 1; args.in_args[0].size = entry->d_name.len + 1; args.in_args[0].value = entry->d_name.name; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (!err) { struct inode *inode = d_inode(entry); struct fuse_inode *fi = get_fuse_inode(inode); spin_lock(&fi->lock); - fi->attr_version = atomic64_inc_return(&fm->fc->attr_version); + fi->attr_version = atomic64_inc_return(&fc->attr_version); /* * If i_nlink == 0 then unlink doesn't make sense, yet this can * happen if userspace filesystem is careless. It would be @@ -1099,32 +787,18 @@ static int fuse_unlink(struct inode *dir, struct dentry *entry) static int fuse_rmdir(struct inode *dir, struct dentry *entry) { int err; - struct fuse_mount *fm = get_fuse_mount(dir); + struct fuse_conn *fc = get_fuse_conn(dir); FUSE_ARGS(args); if (fuse_is_bad(dir)) return -EIO; -#ifdef CONFIG_FUSE_BPF - { - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(dir, struct fuse_dummy_io, - fuse_rmdir_initialize, - fuse_rmdir_backing, - fuse_rmdir_finalize, - dir, entry); - if (fer.ret) - return PTR_ERR(fer.result); - } -#endif - args.opcode = FUSE_RMDIR; args.nodeid = get_node_id(dir); args.in_numargs = 1; args.in_args[0].size = entry->d_name.len + 1; args.in_args[0].value = entry->d_name.name; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (!err) { clear_nlink(d_inode(entry)); fuse_dir_changed(dir); @@ -1140,7 +814,7 @@ static int fuse_rename_common(struct inode *olddir, struct dentry *oldent, { int err; struct fuse_rename2_in inarg; - struct fuse_mount *fm = get_fuse_mount(olddir); + struct fuse_conn *fc = get_fuse_conn(olddir); FUSE_ARGS(args); memset(&inarg, 0, argsize); @@ -1155,7 +829,7 @@ static int fuse_rename_common(struct inode *olddir, struct dentry *oldent, args.in_args[1].value = oldent->d_name.name; args.in_args[2].size = newent->d_name.len + 1; args.in_args[2].value = newent->d_name.name; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (!err) { /* ctime changes */ fuse_invalidate_attr(d_inode(oldent)); @@ -1200,22 +874,10 @@ static int fuse_rename2(struct inode *olddir, struct dentry *oldent, if (fuse_is_bad(olddir)) return -EIO; - if (flags & ~(RENAME_NOREPLACE | RENAME_EXCHANGE | RENAME_WHITEOUT)) + if (flags & ~(RENAME_NOREPLACE | RENAME_EXCHANGE)) return -EINVAL; if (flags) { -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(olddir, struct fuse_rename2_in, - fuse_rename2_initialize, fuse_rename2_backing, - fuse_rename2_finalize, - olddir, oldent, newdir, newent, flags); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - - /* TODO: how should this go with bpfs involved? */ if (fc->no_rename2 || fc->minor < 23) return -EINVAL; @@ -1227,17 +889,6 @@ static int fuse_rename2(struct inode *olddir, struct dentry *oldent, err = -EINVAL; } } else { -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(olddir, struct fuse_rename_in, - fuse_rename_initialize, fuse_rename_backing, - fuse_rename_finalize, - olddir, oldent, newdir, newent); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - err = fuse_rename_common(olddir, oldent, newdir, newent, 0, FUSE_RENAME, sizeof(struct fuse_rename_in)); @@ -1252,19 +903,9 @@ static int fuse_link(struct dentry *entry, struct inode *newdir, int err; struct fuse_link_in inarg; struct inode *inode = d_inode(entry); - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_link_in, fuse_link_initialize, - fuse_link_backing, fuse_link_finalize, entry, - newdir, newent); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - memset(&inarg, 0, sizeof(inarg)); inarg.oldnodeid = get_node_id(inode); args.opcode = FUSE_LINK; @@ -1273,7 +914,7 @@ static int fuse_link(struct dentry *entry, struct inode *newdir, args.in_args[0].value = &inarg; args.in_args[1].size = newent->d_name.len + 1; args.in_args[1].value = newent->d_name.name; - err = create_new_entry(fm, &args, newdir, newent, inode->i_mode); + err = create_new_entry(fc, &args, newdir, newent, inode->i_mode); /* Contrary to "normal" filesystems it can happen that link makes two "logical" inodes point to the same "physical" inode. We invalidate the attributes of the old one, so it @@ -1284,7 +925,7 @@ static int fuse_link(struct dentry *entry, struct inode *newdir, struct fuse_inode *fi = get_fuse_inode(inode); spin_lock(&fi->lock); - fi->attr_version = atomic64_inc_return(&fm->fc->attr_version); + fi->attr_version = atomic64_inc_return(&fc->attr_version); if (likely(inode->i_nlink < UINT_MAX)) inc_nlink(inode); spin_unlock(&fi->lock); @@ -1296,7 +937,7 @@ static int fuse_link(struct dentry *entry, struct inode *newdir, return err; } -void fuse_fillattr(struct inode *inode, struct fuse_attr *attr, +static void fuse_fillattr(struct inode *inode, struct fuse_attr *attr, struct kstat *stat) { unsigned int blkbits; @@ -1341,11 +982,11 @@ static int fuse_do_getattr(struct inode *inode, struct kstat *stat, int err; struct fuse_getattr_in inarg; struct fuse_attr_out outarg; - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); u64 attr_version; - attr_version = fuse_get_attr_version(fm->fc); + attr_version = fuse_get_attr_version(fc); memset(&inarg, 0, sizeof(inarg)); memset(&outarg, 0, sizeof(outarg)); @@ -1364,14 +1005,24 @@ static int fuse_do_getattr(struct inode *inode, struct kstat *stat, args.out_numargs = 1; args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; - err = fuse_simple_request(fm, &args); - if (!err) - err = finalize_attr(inode, &outarg, attr_version, stat); + err = fuse_simple_request(fc, &args); + if (!err) { + if (fuse_invalid_attr(&outarg.attr) || + (inode->i_mode ^ outarg.attr.mode) & S_IFMT) { + fuse_make_bad(inode); + err = -EIO; + } else { + fuse_change_attributes(inode, &outarg.attr, + attr_timeout(&outarg), + attr_version); + if (stat) + fuse_fillattr(inode, &outarg.attr, stat); + } + } return err; } static int fuse_update_get_attr(struct inode *inode, struct file *file, - const struct path *path, struct kstat *stat, u32 request_mask, unsigned int flags) { @@ -1379,17 +1030,6 @@ static int fuse_update_get_attr(struct inode *inode, struct file *file, int err = 0; bool sync; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_getattr_io, - fuse_getattr_initialize, fuse_getattr_backing, - fuse_getattr_finalize, - path->dentry, stat, request_mask, flags); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (flags & AT_STATX_FORCE_SYNC) sync = true; else if (flags & AT_STATX_DONT_SYNC) @@ -1414,11 +1054,11 @@ static int fuse_update_get_attr(struct inode *inode, struct file *file, int fuse_update_attributes(struct inode *inode, struct file *file) { /* Do *not* need to get atime for internal purposes */ - return fuse_update_get_attr(inode, file, &file->f_path, NULL, + return fuse_update_get_attr(inode, file, NULL, STATX_BASIC_STATS & ~STATX_ATIME, 0); } -int fuse_reverse_inval_entry(struct fuse_conn *fc, u64 parent_nodeid, +int fuse_reverse_inval_entry(struct super_block *sb, u64 parent_nodeid, u64 child_nodeid, struct qstr *name) { int err = -ENOTDIR; @@ -1426,7 +1066,7 @@ int fuse_reverse_inval_entry(struct fuse_conn *fc, u64 parent_nodeid, struct dentry *dir; struct dentry *entry; - parent = fuse_ilookup(fc, parent_nodeid, NULL); + parent = ilookup5(sb, parent_nodeid, fuse_inode_eq, &parent_nodeid); if (!parent) return -ENOENT; @@ -1518,24 +1158,14 @@ int fuse_allow_current_process(struct fuse_conn *fc) static int fuse_access(struct inode *inode, int mask) { - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); struct fuse_access_in inarg; int err; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_access_in, - fuse_access_initialize, fuse_access_backing, - fuse_access_finalize, inode, mask); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - BUG_ON(mask & MAY_NOT_BLOCK); - if (fm->fc->no_access) + if (fc->no_access) return 0; memset(&inarg, 0, sizeof(inarg)); @@ -1545,9 +1175,9 @@ static int fuse_access(struct inode *inode, int mask) args.in_numargs = 1; args.in_args[0].size = sizeof(inarg); args.in_args[0].value = &inarg; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err == -ENOSYS) { - fm->fc->no_access = 1; + fc->no_access = 1; err = 0; } return err; @@ -1580,10 +1210,6 @@ static int fuse_permission(struct inode *inode, int mask) struct fuse_conn *fc = get_fuse_conn(inode); bool refreshed = false; int err = 0; - struct fuse_inode *fi = get_fuse_inode(inode); -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; -#endif if (fuse_is_bad(inode)) return -EIO; @@ -1591,19 +1217,12 @@ static int fuse_permission(struct inode *inode, int mask) if (!fuse_allow_current_process(fc)) return -EACCES; -#ifdef CONFIG_FUSE_BPF - fer = fuse_bpf_backing(inode, struct fuse_access_in, - fuse_access_initialize, fuse_access_backing, - fuse_access_finalize, inode, mask); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - /* * If attributes are needed, refresh them before proceeding */ if (fc->default_permissions || ((mask & MAY_EXEC) && S_ISREG(inode->i_mode))) { + struct fuse_inode *fi = get_fuse_inode(inode); u32 perm_mask = STATX_MODE | STATX_UID | STATX_GID; if (perm_mask & READ_ONCE(fi->inval_mask) || @@ -1649,7 +1268,7 @@ static int fuse_permission(struct inode *inode, int mask) static int fuse_readlink_page(struct inode *inode, struct page *page) { - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_page_desc desc = { .length = PAGE_SIZE - 1 }; struct fuse_args_pages ap = { .num_pages = 1, @@ -1666,7 +1285,7 @@ static int fuse_readlink_page(struct inode *inode, struct page *page) ap.args.page_zeroing = true; ap.args.out_numargs = 1; ap.args.out_args[0].size = desc.length; - res = fuse_simple_request(fm, &ap.args); + res = fuse_simple_request(fc, &ap.args); fuse_invalidate_atime(inode); @@ -1693,21 +1312,6 @@ static const char *fuse_get_link(struct dentry *dentry, struct inode *inode, if (fuse_is_bad(inode)) goto out_err; -#ifdef CONFIG_FUSE_BPF - { - struct fuse_err_ret fer; - const char *out = NULL; - - fer = fuse_bpf_backing(inode, struct fuse_dummy_io, - fuse_get_link_initialize, - fuse_get_link_backing, - fuse_get_link_finalize, - inode, dentry, callback, &out); - if (fer.ret) - return fer.result ?: out; - } -#endif - if (fc->cache_symlinks) return page_get_link_raw(dentry, inode, callback); @@ -1742,6 +1346,7 @@ static int fuse_dir_open(struct inode *inode, struct file *file) static int fuse_dir_release(struct inode *inode, struct file *file) { fuse_release_common(file, true); + return 0; } @@ -1755,19 +1360,6 @@ static int fuse_dir_fsync(struct file *file, loff_t start, loff_t end, if (fuse_is_bad(inode)) return -EIO; -#ifdef CONFIG_FUSE_BPF - { - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_fsync_in, - fuse_dir_fsync_initialize, fuse_fsync_backing, - fuse_fsync_finalize, - file, start, end, datasync); - if (fer.ret) - return PTR_ERR(fer.result); - } -#endif - if (fc->no_fsyncdir) return 0; @@ -1806,6 +1398,58 @@ static long fuse_dir_compat_ioctl(struct file *file, unsigned int cmd, FUSE_IOCTL_COMPAT | FUSE_IOCTL_DIR); } +static bool update_mtime(unsigned ivalid, bool trust_local_mtime) +{ + /* Always update if mtime is explicitly set */ + if (ivalid & ATTR_MTIME_SET) + return true; + + /* Or if kernel i_mtime is the official one */ + if (trust_local_mtime) + return true; + + /* If it's an open(O_TRUNC) or an ftruncate(), don't update */ + if ((ivalid & ATTR_SIZE) && (ivalid & (ATTR_OPEN | ATTR_FILE))) + return false; + + /* In all other cases update */ + return true; +} + +static void iattr_to_fattr(struct fuse_conn *fc, struct iattr *iattr, + struct fuse_setattr_in *arg, bool trust_local_cmtime) +{ + unsigned ivalid = iattr->ia_valid; + + if (ivalid & ATTR_MODE) + arg->valid |= FATTR_MODE, arg->mode = iattr->ia_mode; + if (ivalid & ATTR_UID) + arg->valid |= FATTR_UID, arg->uid = from_kuid(fc->user_ns, iattr->ia_uid); + if (ivalid & ATTR_GID) + arg->valid |= FATTR_GID, arg->gid = from_kgid(fc->user_ns, iattr->ia_gid); + if (ivalid & ATTR_SIZE) + arg->valid |= FATTR_SIZE, arg->size = iattr->ia_size; + if (ivalid & ATTR_ATIME) { + arg->valid |= FATTR_ATIME; + arg->atime = iattr->ia_atime.tv_sec; + arg->atimensec = iattr->ia_atime.tv_nsec; + if (!(ivalid & ATTR_ATIME_SET)) + arg->valid |= FATTR_ATIME_NOW; + } + if ((ivalid & ATTR_MTIME) && update_mtime(ivalid, trust_local_cmtime)) { + arg->valid |= FATTR_MTIME; + arg->mtime = iattr->ia_mtime.tv_sec; + arg->mtimensec = iattr->ia_mtime.tv_nsec; + if (!(ivalid & ATTR_MTIME_SET) && !trust_local_cmtime) + arg->valid |= FATTR_MTIME_NOW; + } + if ((ivalid & ATTR_CTIME) && trust_local_cmtime) { + arg->valid |= FATTR_CTIME; + arg->ctime = iattr->ia_ctime.tv_sec; + arg->ctimensec = iattr->ia_ctime.tv_nsec; + } +} + /* * Prevent concurrent writepages on inode * @@ -1869,7 +1513,7 @@ static void fuse_setattr_fill(struct fuse_conn *fc, struct fuse_args *args, */ int fuse_flush_times(struct inode *inode, struct fuse_file *ff) { - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); struct fuse_setattr_in inarg; struct fuse_attr_out outarg; @@ -1880,7 +1524,7 @@ int fuse_flush_times(struct inode *inode, struct fuse_file *ff) inarg.valid = FATTR_MTIME; inarg.mtime = inode->i_mtime.tv_sec; inarg.mtimensec = inode->i_mtime.tv_nsec; - if (fm->fc->minor >= 23) { + if (fc->minor >= 23) { inarg.valid |= FATTR_CTIME; inarg.ctime = inode->i_ctime.tv_sec; inarg.ctimensec = inode->i_ctime.tv_nsec; @@ -1889,9 +1533,9 @@ int fuse_flush_times(struct inode *inode, struct fuse_file *ff) inarg.valid |= FATTR_FH; inarg.fh = ff->fh; } - fuse_setattr_fill(fm->fc, &args, inode, &inarg, &outarg); + fuse_setattr_fill(fc, &args, inode, &inarg, &outarg); - return fuse_simple_request(fm, &args); + return fuse_simple_request(fc, &args); } /* @@ -1906,8 +1550,7 @@ int fuse_do_setattr(struct dentry *dentry, struct iattr *attr, struct file *file) { struct inode *inode = d_inode(dentry); - struct fuse_mount *fm = get_fuse_mount(inode); - struct fuse_conn *fc = fm->fc; + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_inode *fi = get_fuse_inode(inode); FUSE_ARGS(args); struct fuse_setattr_in inarg; @@ -1917,17 +1560,6 @@ int fuse_do_setattr(struct dentry *dentry, struct iattr *attr, loff_t oldsize; int err; bool trust_local_cmtime = is_wb && S_ISREG(inode->i_mode); - bool fault_blocked = false; - -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_setattr_io, - fuse_setattr_initialize, fuse_setattr_backing, - fuse_setattr_finalize, dentry, attr, file); - if (fer.ret) - return PTR_ERR(fer.result); -#endif if (!fc->default_permissions) attr->ia_valid |= ATTR_FORCE; @@ -1936,22 +1568,6 @@ int fuse_do_setattr(struct dentry *dentry, struct iattr *attr, if (err) return err; - if (attr->ia_valid & ATTR_SIZE) { - if (WARN_ON(!S_ISREG(inode->i_mode))) - return -EIO; - is_truncate = true; - } - - if (FUSE_IS_DAX(inode) && is_truncate) { - down_write(&fi->i_mmap_sem); - fault_blocked = true; - err = fuse_dax_break_layouts(inode, 0, 0); - if (err) { - up_write(&fi->i_mmap_sem); - return err; - } - } - if (attr->ia_valid & ATTR_OPEN) { /* This is coming from open(..., ... | O_TRUNC); */ WARN_ON(!(attr->ia_valid & ATTR_SIZE)); @@ -1964,11 +1580,17 @@ int fuse_do_setattr(struct dentry *dentry, struct iattr *attr, */ i_size_write(inode, 0); truncate_pagecache(inode, 0); - goto out; + return 0; } file = NULL; } + if (attr->ia_valid & ATTR_SIZE) { + if (WARN_ON(!S_ISREG(inode->i_mode))) + return -EIO; + is_truncate = true; + } + /* Flush dirty data/metadata before non-truncate SETATTR */ if (is_wb && S_ISREG(inode->i_mode) && attr->ia_valid & @@ -2003,7 +1625,7 @@ int fuse_do_setattr(struct dentry *dentry, struct iattr *attr, inarg.lock_owner = fuse_lock_owner_id(fc, current->files); } fuse_setattr_fill(fc, &args, inode, &inarg, &outarg); - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err) { if (err == -EINTR) fuse_invalidate_attr(inode); @@ -2011,7 +1633,7 @@ int fuse_do_setattr(struct dentry *dentry, struct iattr *attr, } if (fuse_invalid_attr(&outarg.attr) || - inode_wrong_type(inode, outarg.attr.mode)) { + (inode->i_mode ^ outarg.attr.mode) & S_IFMT) { fuse_make_bad(inode); err = -EIO; goto error; @@ -2051,10 +1673,6 @@ int fuse_do_setattr(struct dentry *dentry, struct iattr *attr, } clear_bit(FUSE_I_SIZE_UNSTABLE, &fi->state); -out: - if (fault_blocked) - up_write(&fi->i_mmap_sem); - return 0; error: @@ -2062,9 +1680,6 @@ error: fuse_release_nowrite(inode); clear_bit(FUSE_I_SIZE_UNSTABLE, &fi->state); - - if (fault_blocked) - up_write(&fi->i_mmap_sem); return err; } @@ -2092,22 +1707,11 @@ static int fuse_setattr(struct dentry *entry, struct iattr *attr) * This should be done on write(), truncate() and chown(). */ if (!fc->handle_killpriv) { -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - /* * ia_mode calculation may have used stale i_mode. * Refresh and recalculate. */ - fer = fuse_bpf_backing(inode, struct fuse_getattr_io, - fuse_getattr_initialize, fuse_getattr_backing, - fuse_getattr_finalize, - entry, NULL, 0, 0); - if (fer.ret) - ret = PTR_ERR(fer.result); - else -#endif - ret = fuse_do_getattr(inode, NULL, file); + ret = fuse_do_getattr(inode, NULL, file); if (ret) return ret; @@ -2150,21 +1754,10 @@ static int fuse_getattr(const struct path *path, struct kstat *stat, if (fuse_is_bad(inode)) return -EIO; - if (!fuse_allow_current_process(fc)) { - if (!request_mask) { - /* - * If user explicitly requested *nothing* then don't - * error out, but return st_dev only. - */ - stat->result_mask = 0; - stat->dev = inode->i_sb->s_dev; - return 0; - } + if (!fuse_allow_current_process(fc)) return -EACCES; - } - return fuse_update_get_attr(inode, NULL, path, stat, request_mask, - flags); + return fuse_update_get_attr(inode, NULL, stat, request_mask, flags); } static const struct inode_operations fuse_dir_inode_operations = { diff --git a/fs/fuse/file.c b/fs/fuse/file.c index cb34aa80c4f8..8a715e80c486 100644 --- a/fs/fuse/file.c +++ b/fs/fuse/file.c @@ -8,7 +8,6 @@ #include "fuse_i.h" -#include #include #include #include @@ -33,7 +32,7 @@ static struct page **fuse_pages_alloc(unsigned int npages, gfp_t flags, return pages; } -static int fuse_send_open(struct fuse_mount *fm, u64 nodeid, struct file *file, +static int fuse_send_open(struct fuse_conn *fc, u64 nodeid, struct file *file, int opcode, struct fuse_open_out *outargp) { struct fuse_open_in inarg; @@ -41,7 +40,7 @@ static int fuse_send_open(struct fuse_mount *fm, u64 nodeid, struct file *file, memset(&inarg, 0, sizeof(inarg)); inarg.flags = file->f_flags & ~(O_CREAT | O_EXCL | O_NOCTTY); - if (!fm->fc->atomic_o_trunc) + if (!fc->atomic_o_trunc) inarg.flags &= ~O_TRUNC; args.opcode = opcode; args.nodeid = nodeid; @@ -52,7 +51,7 @@ static int fuse_send_open(struct fuse_mount *fm, u64 nodeid, struct file *file, args.out_args[0].size = sizeof(*outargp); args.out_args[0].value = outargp; - return fuse_simple_request(fm, &args); + return fuse_simple_request(fc, &args); } struct fuse_release_args { @@ -61,7 +60,7 @@ struct fuse_release_args { struct inode *inode; }; -struct fuse_file *fuse_file_alloc(struct fuse_mount *fm) +struct fuse_file *fuse_file_alloc(struct fuse_conn *fc) { struct fuse_file *ff; @@ -69,7 +68,7 @@ struct fuse_file *fuse_file_alloc(struct fuse_mount *fm) if (unlikely(!ff)) return NULL; - ff->fm = fm; + ff->fc = fc; ff->release_args = kzalloc(sizeof(*ff->release_args), GFP_KERNEL_ACCOUNT); if (!ff->release_args) { @@ -83,7 +82,7 @@ struct fuse_file *fuse_file_alloc(struct fuse_mount *fm) RB_CLEAR_NODE(&ff->polled_node); init_waitqueue_head(&ff->poll_wait); - ff->kh = atomic64_inc_return(&fm->fc->khctr); + ff->kh = atomic64_inc_return(&fc->khctr); return ff; } @@ -101,7 +100,7 @@ static struct fuse_file *fuse_file_get(struct fuse_file *ff) return ff; } -static void fuse_release_end(struct fuse_mount *fm, struct fuse_args *args, +static void fuse_release_end(struct fuse_conn *fc, struct fuse_args *args, int error) { struct fuse_release_args *ra = container_of(args, typeof(*ra), args); @@ -110,53 +109,34 @@ static void fuse_release_end(struct fuse_mount *fm, struct fuse_args *args, kfree(ra); } -static void fuse_file_put(struct inode *inode, struct fuse_file *ff, - bool sync, bool isdir) +static void fuse_file_put(struct fuse_file *ff, bool sync, bool isdir) { - struct fuse_args *args = &ff->release_args->args; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; -#endif + if (refcount_dec_and_test(&ff->count)) { + struct fuse_args *args = &ff->release_args->args; - if (!refcount_dec_and_test(&ff->count)) - return; - -#ifdef CONFIG_FUSE_BPF - fer = fuse_bpf_backing(inode, struct fuse_release_in, - fuse_release_initialize, fuse_release_backing, - fuse_release_finalize, - inode, ff); - if (fer.ret) { - fuse_release_end(ff->fm, args, 0); - } else -#endif - if (isdir ? ff->fm->fc->no_opendir : ff->fm->fc->no_open) { - /* Do nothing when client does not implement 'open' */ - fuse_release_end(ff->fm, args, 0); - } else if (sync) { - fuse_simple_request(ff->fm, args); - fuse_release_end(ff->fm, args, 0); - } else { - args->end = fuse_release_end; - if (fuse_simple_background(ff->fm, args, - GFP_KERNEL | __GFP_NOFAIL)) - fuse_release_end(ff->fm, args, -ENOTCONN); + if (isdir ? ff->fc->no_opendir : ff->fc->no_open) { + /* Do nothing when client does not implement 'open' */ + fuse_release_end(ff->fc, args, 0); + } else if (sync) { + fuse_simple_request(ff->fc, args); + fuse_release_end(ff->fc, args, 0); + } else { + args->end = fuse_release_end; + if (fuse_simple_background(ff->fc, args, + GFP_KERNEL | __GFP_NOFAIL)) + fuse_release_end(ff->fc, args, -ENOTCONN); + } + kfree(ff); } - kfree(ff); } -int fuse_do_open(struct fuse_mount *fm, u64 nodeid, struct file *file, +int fuse_do_open(struct fuse_conn *fc, u64 nodeid, struct file *file, bool isdir) { - struct fuse_conn *fc = fm->fc; struct fuse_file *ff; int opcode = isdir ? FUSE_OPENDIR : FUSE_OPEN; - if (file->private_data) { - ff = file->private_data; - file->private_data = NULL; - } else - ff = fuse_file_alloc(fm); + ff = fuse_file_alloc(fc); if (!ff) return -ENOMEM; @@ -167,7 +147,7 @@ int fuse_do_open(struct fuse_mount *fm, u64 nodeid, struct file *file, struct fuse_open_out outarg; int err; - err = fuse_send_open(fm, nodeid, file, opcode, &outarg); + err = fuse_send_open(fc, nodeid, file, opcode, &outarg); if (!err) { ff->fh = outarg.fh; ff->open_flags = outarg.open_flags; @@ -225,24 +205,25 @@ void fuse_finish_open(struct inode *inode, struct file *file) fi->attr_version = atomic64_inc_return(&fc->attr_version); i_size_write(inode, 0); spin_unlock(&fi->lock); + truncate_pagecache(inode, 0); fuse_invalidate_attr(inode); if (fc->writeback_cache) file_update_time(file); + } else if (!(ff->open_flags & FOPEN_KEEP_CACHE)) { + invalidate_inode_pages2(inode->i_mapping); } + if ((file->f_mode & FMODE_WRITE) && fc->writeback_cache) fuse_link_write_file(file); } int fuse_open_common(struct inode *inode, struct file *file, bool isdir) { - struct fuse_mount *fm = get_fuse_mount(inode); - struct fuse_conn *fc = fm->fc; + struct fuse_conn *fc = get_fuse_conn(inode); int err; bool is_wb_truncate = (file->f_flags & O_TRUNC) && fc->atomic_o_trunc && fc->writeback_cache; - bool dax_truncate = (file->f_flags & O_TRUNC) && - fc->atomic_o_trunc && FUSE_IS_DAX(inode); if (fuse_is_bad(inode)) return -EIO; @@ -251,53 +232,20 @@ int fuse_open_common(struct inode *inode, struct file *file, bool isdir) if (err) return err; -#ifdef CONFIG_FUSE_BPF - { - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_open_io, - fuse_open_initialize, - fuse_open_backing, - fuse_open_finalize, - inode, file, isdir); - if (fer.ret) - return PTR_ERR(fer.result); - } -#endif - - if (is_wb_truncate || dax_truncate) + if (is_wb_truncate) { inode_lock(inode); - - if (dax_truncate) { - down_write(&get_fuse_inode(inode)->i_mmap_sem); - err = fuse_dax_break_layouts(inode, 0, 0); - if (err) - goto out_inode_unlock; + fuse_set_nowrite(inode); } - if (is_wb_truncate || dax_truncate) - fuse_set_nowrite(inode); + err = fuse_do_open(fc, get_node_id(inode), file, isdir); - err = fuse_do_open(fm, get_node_id(inode), file, isdir); if (!err) fuse_finish_open(inode, file); - if (is_wb_truncate || dax_truncate) + if (is_wb_truncate) { fuse_release_nowrite(inode); - if (!err) { - struct fuse_file *ff = file->private_data; - - if (fc->atomic_o_trunc && (file->f_flags & O_TRUNC)) - truncate_pagecache(inode, 0); - else if (!(ff->open_flags & FOPEN_KEEP_CACHE)) - invalidate_inode_pages2(inode->i_mapping); - } - if (dax_truncate) - up_write(&get_fuse_inode(inode)->i_mmap_sem); - -out_inode_unlock: - if (is_wb_truncate || dax_truncate) inode_unlock(inode); + } return err; } @@ -305,7 +253,7 @@ out_inode_unlock: static void fuse_prepare_release(struct fuse_inode *fi, struct fuse_file *ff, int flags, int opcode) { - struct fuse_conn *fc = ff->fm->fc; + struct fuse_conn *fc = ff->fc; struct fuse_release_args *ra = ff->release_args; /* Inode is NULL on error path of fuse_create_open() */ @@ -345,7 +293,7 @@ void fuse_release_common(struct file *file, bool isdir) if (ff->flock) { ra->inarg.release_flags |= FUSE_RELEASE_FLOCK_UNLOCK; - ra->inarg.lock_owner = fuse_lock_owner_id(ff->fm->fc, + ra->inarg.lock_owner = fuse_lock_owner_id(ff->fc, (fl_owner_t) file); } /* Hold inode until release is finished */ @@ -359,14 +307,8 @@ void fuse_release_common(struct file *file, bool isdir) * Make the release synchronous if this is a fuseblk mount, * synchronous RELEASE is allowed (and desirable) in this case * because the server can be trusted not to screw up. - * - * Always use the asynchronous file put because the current thread - * might be the fuse server. This can happen if a process starts some - * aio and closes the fd before the aio completes. Since aio takes its - * own ref to the file, the IO completion has to drop the ref, which is - * how the fuse server can end up closing its clients' files. */ - fuse_file_put(ra->inode, ff, false, isdir); + fuse_file_put(ff, ff->fc->destroy, isdir); } static int fuse_open(struct inode *inode, struct file *file) @@ -396,7 +338,7 @@ void fuse_sync_release(struct fuse_inode *fi, struct fuse_file *ff, int flags) * iput(NULL) is a no-op and since the refcount is 1 and everything's * synchronous, we are fine with not doing igrab() here" */ - fuse_file_put(&fi->inode, ff, true, false); + fuse_file_put(ff, true, false); } EXPORT_SYMBOL_GPL(fuse_sync_release); @@ -424,7 +366,7 @@ u64 fuse_lock_owner_id(struct fuse_conn *fc, fl_owner_t id) struct fuse_writepage_args { struct fuse_io_args ia; - struct rb_node writepages_entry; + struct list_head writepages_entry; struct list_head queue_entry; struct fuse_writepage_args *next; struct inode *inode; @@ -433,23 +375,17 @@ struct fuse_writepage_args { static struct fuse_writepage_args *fuse_find_writeback(struct fuse_inode *fi, pgoff_t idx_from, pgoff_t idx_to) { - struct rb_node *n; + struct fuse_writepage_args *wpa; - n = fi->writepages.rb_node; - - while (n) { - struct fuse_writepage_args *wpa; + list_for_each_entry(wpa, &fi->writepages, writepages_entry) { pgoff_t curr_index; - wpa = rb_entry(n, struct fuse_writepage_args, writepages_entry); WARN_ON(get_fuse_inode(wpa->inode) != fi); curr_index = wpa->ia.write.in.offset >> PAGE_SHIFT; - if (idx_from >= curr_index + wpa->ia.ap.num_pages) - n = n->rb_right; - else if (idx_to < curr_index) - n = n->rb_left; - else + if (idx_from < curr_index + wpa->ia.ap.num_pages && + curr_index <= idx_to) { return wpa; + } } return NULL; } @@ -509,26 +445,18 @@ static void fuse_sync_writes(struct inode *inode) static int fuse_flush(struct file *file, fl_owner_t id) { struct inode *inode = file_inode(file); - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_file *ff = file->private_data; struct fuse_flush_in inarg; FUSE_ARGS(args); int err; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(file->f_inode, struct fuse_flush_in, - fuse_flush_initialize, fuse_flush_backing, - fuse_flush_finalize, - file, id); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (fuse_is_bad(inode)) return -EIO; + if (fc->no_flush) + return 0; + err = write_inode_now(inode, 1); if (err) return err; @@ -541,13 +469,9 @@ static int fuse_flush(struct file *file, fl_owner_t id) if (err) return err; - err = 0; - if (fm->fc->no_flush) - goto inval_attr_out; - memset(&inarg, 0, sizeof(inarg)); inarg.fh = ff->fh; - inarg.lock_owner = fuse_lock_owner_id(fm->fc, id); + inarg.lock_owner = fuse_lock_owner_id(fc, id); args.opcode = FUSE_FLUSH; args.nodeid = get_node_id(inode); args.in_numargs = 1; @@ -555,19 +479,11 @@ static int fuse_flush(struct file *file, fl_owner_t id) args.in_args[0].value = &inarg; args.force = true; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err == -ENOSYS) { - fm->fc->no_flush = 1; + fc->no_flush = 1; err = 0; } - -inval_attr_out: - /* - * In memory i_blocks is not maintained by fuse, if writeback cache is - * enabled, i_blocks from cached attr may not be accurate. - */ - if (!err && fm->fc->writeback_cache) - fuse_invalidate_attr(inode); return err; } @@ -575,7 +491,7 @@ int fuse_fsync_common(struct file *file, loff_t start, loff_t end, int datasync, int opcode) { struct inode *inode = file->f_mapping->host; - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_file *ff = file->private_data; FUSE_ARGS(args); struct fuse_fsync_in inarg; @@ -588,7 +504,7 @@ int fuse_fsync_common(struct file *file, loff_t start, loff_t end, args.in_numargs = 1; args.in_args[0].size = sizeof(inarg); args.in_args[0].value = &inarg; - return fuse_simple_request(fm, &args); + return fuse_simple_request(fc, &args); } static int fuse_fsync(struct file *file, loff_t start, loff_t end, @@ -598,17 +514,6 @@ static int fuse_fsync(struct file *file, loff_t start, loff_t end, struct fuse_conn *fc = get_fuse_conn(inode); int err; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_fsync_in, - fuse_fsync_initialize, fuse_fsync_backing, - fuse_fsync_finalize, - file, start, end, datasync); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (fuse_is_bad(inode)) return -EIO; @@ -774,7 +679,7 @@ static void fuse_io_free(struct fuse_io_args *ia) kfree(ia); } -static void fuse_aio_complete_req(struct fuse_mount *fm, struct fuse_args *args, +static void fuse_aio_complete_req(struct fuse_conn *fc, struct fuse_args *args, int err) { struct fuse_io_args *ia = container_of(args, typeof(*ia), ap.args); @@ -803,7 +708,7 @@ static void fuse_aio_complete_req(struct fuse_mount *fm, struct fuse_args *args, fuse_io_free(ia); } -static ssize_t fuse_async_req_send(struct fuse_mount *fm, +static ssize_t fuse_async_req_send(struct fuse_conn *fc, struct fuse_io_args *ia, size_t num_bytes) { ssize_t err; @@ -817,9 +722,9 @@ static ssize_t fuse_async_req_send(struct fuse_mount *fm, ia->ap.args.end = fuse_aio_complete_req; ia->ap.args.may_block = io->should_dirty; - err = fuse_simple_background(fm, &ia->ap.args, GFP_KERNEL); + err = fuse_simple_background(fc, &ia->ap.args, GFP_KERNEL); if (err) - fuse_aio_complete_req(fm, &ia->ap.args, err); + fuse_aio_complete_req(fc, &ia->ap.args, err); return num_bytes; } @@ -829,18 +734,18 @@ static ssize_t fuse_send_read(struct fuse_io_args *ia, loff_t pos, size_t count, { struct file *file = ia->io->iocb->ki_filp; struct fuse_file *ff = file->private_data; - struct fuse_mount *fm = ff->fm; + struct fuse_conn *fc = ff->fc; fuse_read_args_fill(ia, file, pos, count, FUSE_READ); if (owner != NULL) { ia->read.in.read_flags |= FUSE_READ_LOCKOWNER; - ia->read.in.lock_owner = fuse_lock_owner_id(fm->fc, owner); + ia->read.in.lock_owner = fuse_lock_owner_id(fc, owner); } if (ia->io->async) - return fuse_async_req_send(fm, ia, count); + return fuse_async_req_send(fc, ia, count); - return fuse_simple_request(fm, &ia->ap.args); + return fuse_simple_request(fc, &ia->ap.args); } static void fuse_read_update_size(struct inode *inode, loff_t size, @@ -850,7 +755,7 @@ static void fuse_read_update_size(struct inode *inode, loff_t size, struct fuse_inode *fi = get_fuse_inode(inode); spin_lock(&fi->lock); - if (attr_ver >= fi->attr_version && size < inode->i_size && + if (attr_ver == fi->attr_version && size < inode->i_size && !test_bit(FUSE_I_SIZE_UNSTABLE, &fi->state)) { fi->attr_version = atomic64_inc_return(&fc->attr_version); i_size_write(inode, size); @@ -886,7 +791,7 @@ static void fuse_short_read(struct inode *inode, u64 attr_ver, size_t num_read, static int fuse_do_readpage(struct file *file, struct page *page) { struct inode *inode = page->mapping->host; - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); loff_t pos = page_offset(page); struct fuse_page_desc desc = { .length = PAGE_SIZE }; struct fuse_io_args ia = { @@ -906,14 +811,14 @@ static int fuse_do_readpage(struct file *file, struct page *page) */ fuse_wait_on_page_writeback(inode, page->index); - attr_ver = fuse_get_attr_version(fm->fc); + attr_ver = fuse_get_attr_version(fc); /* Don't overflow end offset */ if (pos + (desc.length - 1) == LLONG_MAX) desc.length--; fuse_read_args_fill(&ia, file, pos, desc.length, FUSE_READ); - res = fuse_simple_request(fm, &ia.ap.args); + res = fuse_simple_request(fc, &ia.ap.args); if (res < 0) return res; /* @@ -943,7 +848,7 @@ static int fuse_readpage(struct file *file, struct page *page) return err; } -static void fuse_readpages_end(struct fuse_mount *fm, struct fuse_args *args, +static void fuse_readpages_end(struct fuse_conn *fc, struct fuse_args *args, int err) { int i; @@ -978,11 +883,8 @@ static void fuse_readpages_end(struct fuse_mount *fm, struct fuse_args *args, unlock_page(page); put_page(page); } - if (ia->ff) { - WARN_ON(!mapping); - fuse_file_put(mapping ? mapping->host : NULL, ia->ff, - false, false); - } + if (ia->ff) + fuse_file_put(ia->ff, false, false); fuse_io_free(ia); } @@ -990,7 +892,7 @@ static void fuse_readpages_end(struct fuse_mount *fm, struct fuse_args *args, static void fuse_send_readpages(struct fuse_io_args *ia, struct file *file) { struct fuse_file *ff = file->private_data; - struct fuse_mount *fm = ff->fm; + struct fuse_conn *fc = ff->fc; struct fuse_args_pages *ap = &ia->ap; loff_t pos = page_offset(ap->pages[0]); size_t count = ap->num_pages << PAGE_SHIFT; @@ -1009,18 +911,18 @@ static void fuse_send_readpages(struct fuse_io_args *ia, struct file *file) WARN_ON((loff_t) (pos + count) < 0); fuse_read_args_fill(ia, file, pos, count, FUSE_READ); - ia->read.attr_ver = fuse_get_attr_version(fm->fc); - if (fm->fc->async_read) { + ia->read.attr_ver = fuse_get_attr_version(fc); + if (fc->async_read) { ia->ff = fuse_file_get(ff); ap->args.end = fuse_readpages_end; - err = fuse_simple_background(fm, &ap->args, GFP_KERNEL); + err = fuse_simple_background(fc, &ap->args, GFP_KERNEL); if (!err) return; } else { - res = fuse_simple_request(fm, &ap->args); + res = fuse_simple_request(fc, &ap->args); err = res < 0 ? res : 0; } - fuse_readpages_end(fm, &ap->args, err); + fuse_readpages_end(fc, &ap->args, err); } struct fuse_fill_data { @@ -1039,19 +941,6 @@ static int fuse_readpages_fill(void *_data, struct page *page) struct inode *inode = data->inode; struct fuse_conn *fc = get_fuse_conn(inode); -#ifdef CONFIG_FUSE_BPF - /* - * Currently no meaningful readahead is possible with fuse-bpf within - * the kernel, so unless the daemon is aware of this file, ignore this - * call. - */ - if (!get_fuse_inode(inode)->nodeid) - return -EIO; -#endif - - if (fuse_is_bad(inode)) - return -EIO; - fuse_wait_on_page_writeback(inode, page->index); if (ap->num_pages && @@ -1148,7 +1037,7 @@ static void fuse_write_args_fill(struct fuse_io_args *ia, struct fuse_file *ff, args->opcode = FUSE_WRITE; args->nodeid = ff->nodeid; args->in_numargs = 2; - if (ff->fm->fc->minor < 9) + if (ff->fc->minor < 9) args->in_args[0].size = FUSE_COMPAT_WRITE_IN_SIZE; else args->in_args[0].size = sizeof(ia->write.in); @@ -1177,7 +1066,7 @@ static ssize_t fuse_send_write(struct fuse_io_args *ia, loff_t pos, struct kiocb *iocb = ia->io->iocb; struct file *file = iocb->ki_filp; struct fuse_file *ff = file->private_data; - struct fuse_mount *fm = ff->fm; + struct fuse_conn *fc = ff->fc; struct fuse_write_in *inarg = &ia->write.in; ssize_t err; @@ -1185,13 +1074,13 @@ static ssize_t fuse_send_write(struct fuse_io_args *ia, loff_t pos, inarg->flags = fuse_write_flags(iocb); if (owner != NULL) { inarg->write_flags |= FUSE_WRITE_LOCKOWNER; - inarg->lock_owner = fuse_lock_owner_id(fm->fc, owner); + inarg->lock_owner = fuse_lock_owner_id(fc, owner); } if (ia->io->async) - return fuse_async_req_send(fm, ia, count); + return fuse_async_req_send(fc, ia, count); - err = fuse_simple_request(fm, &ia->ap.args); + err = fuse_simple_request(fc, &ia->ap.args); if (!err && ia->write.out.size > count) err = -EIO; @@ -1222,7 +1111,7 @@ static ssize_t fuse_send_write_pages(struct fuse_io_args *ia, struct fuse_args_pages *ap = &ia->ap; struct file *file = iocb->ki_filp; struct fuse_file *ff = file->private_data; - struct fuse_mount *fm = ff->fm; + struct fuse_conn *fc = ff->fc; unsigned int offset, i; bool short_write; int err; @@ -1233,7 +1122,7 @@ static ssize_t fuse_send_write_pages(struct fuse_io_args *ia, fuse_write_args_fill(ia, ff, pos, count); ia->write.in.flags = fuse_write_flags(iocb); - err = fuse_simple_request(fm, &ap->args); + err = fuse_simple_request(fc, &ap->args); if (!err && ia->write.out.size > count) err = -EIO; @@ -1548,9 +1437,9 @@ static int fuse_get_user_pages(struct fuse_args_pages *ap, struct iov_iter *ii, ap->args.user_pages = true; if (write) - ap->args.in_pages = true; + ap->args.in_pages = 1; else - ap->args.out_pages = true; + ap->args.out_pages = 1; *nbytesp = nbytes; @@ -1565,7 +1454,7 @@ ssize_t fuse_direct_io(struct fuse_io_priv *io, struct iov_iter *iter, struct file *file = io->iocb->ki_filp; struct inode *inode = file->f_mapping->host; struct fuse_file *ff = file->private_data; - struct fuse_conn *fc = ff->fm->fc; + struct fuse_conn *fc = ff->fc; size_t nmax = write ? fc->max_write : fc->max_read; loff_t pos = *ppos; size_t count = iov_iter_count(iter); @@ -1705,28 +1594,10 @@ static ssize_t fuse_file_read_iter(struct kiocb *iocb, struct iov_iter *to) { struct file *file = iocb->ki_filp; struct fuse_file *ff = file->private_data; - struct inode *inode = file_inode(file); - if (fuse_is_bad(inode)) + if (fuse_is_bad(file_inode(file))) return -EIO; - if (FUSE_IS_DAX(inode)) - return fuse_dax_read_iter(iocb, to); - -#ifdef CONFIG_FUSE_BPF - { - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_file_read_iter_io, - fuse_file_read_iter_initialize, - fuse_file_read_iter_backing, - fuse_file_read_iter_finalize, - iocb, to); - if (fer.ret) - return PTR_ERR(fer.result); - } -#endif - if (ff->passthrough.filp) return fuse_passthrough_read_iter(iocb, to); else if (!(ff->open_flags & FOPEN_DIRECT_IO)) @@ -1739,28 +1610,10 @@ static ssize_t fuse_file_write_iter(struct kiocb *iocb, struct iov_iter *from) { struct file *file = iocb->ki_filp; struct fuse_file *ff = file->private_data; - struct inode *inode = file_inode(file); - if (fuse_is_bad(inode)) + if (fuse_is_bad(file_inode(file))) return -EIO; - if (FUSE_IS_DAX(inode)) - return fuse_dax_write_iter(iocb, from); - -#ifdef CONFIG_FUSE_BPF - { - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_file_write_iter_io, - fuse_file_write_iter_initialize, - fuse_file_write_iter_backing, - fuse_file_write_iter_finalize, - iocb, from); - if (fer.ret) - return PTR_ERR(fer.result); - } -#endif - if (ff->passthrough.filp) return fuse_passthrough_write_iter(iocb, from); else if (!(ff->open_flags & FOPEN_DIRECT_IO)) @@ -1778,13 +1631,13 @@ static void fuse_writepage_free(struct fuse_writepage_args *wpa) __free_page(ap->pages[i]); if (wpa->ia.ff) - fuse_file_put(wpa->inode, wpa->ia.ff, false, false); + fuse_file_put(wpa->ia.ff, false, false); kfree(ap->pages); kfree(wpa); } -static void fuse_writepage_finish(struct fuse_mount *fm, +static void fuse_writepage_finish(struct fuse_conn *fc, struct fuse_writepage_args *wpa) { struct fuse_args_pages *ap = &wpa->ia.ap; @@ -1793,6 +1646,7 @@ static void fuse_writepage_finish(struct fuse_mount *fm, struct backing_dev_info *bdi = inode_to_bdi(inode); int i; + list_del(&wpa->writepages_entry); for (i = 0; i < ap->num_pages; i++) { dec_wb_stat(&bdi->wb, WB_WRITEBACK); dec_node_page_state(ap->pages[i], NR_WRITEBACK_TEMP); @@ -1802,7 +1656,7 @@ static void fuse_writepage_finish(struct fuse_mount *fm, } /* Called under fi->lock, may release and reacquire it */ -static void fuse_send_writepage(struct fuse_mount *fm, +static void fuse_send_writepage(struct fuse_conn *fc, struct fuse_writepage_args *wpa, loff_t size) __releases(fi->lock) __acquires(fi->lock) @@ -1828,10 +1682,10 @@ __acquires(fi->lock) args->force = true; args->nocreds = true; - err = fuse_simple_background(fm, args, GFP_ATOMIC); + err = fuse_simple_background(fc, args, GFP_ATOMIC); if (err == -ENOMEM) { spin_unlock(&fi->lock); - err = fuse_simple_background(fm, args, GFP_NOFS | __GFP_NOFAIL); + err = fuse_simple_background(fc, args, GFP_NOFS | __GFP_NOFAIL); spin_lock(&fi->lock); } @@ -1843,8 +1697,7 @@ __acquires(fi->lock) out_free: fi->writectr--; - rb_erase(&wpa->writepages_entry, &fi->writepages); - fuse_writepage_finish(fm, wpa); + fuse_writepage_finish(fc, wpa); spin_unlock(&fi->lock); /* After rb_erase() aux request list is private */ @@ -1874,7 +1727,7 @@ void fuse_flush_writepages(struct inode *inode) __releases(fi->lock) __acquires(fi->lock) { - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_inode *fi = get_fuse_inode(inode); loff_t crop = i_size_read(inode); struct fuse_writepage_args *wpa; @@ -1883,76 +1736,29 @@ __acquires(fi->lock) wpa = list_entry(fi->queued_writes.next, struct fuse_writepage_args, queue_entry); list_del_init(&wpa->queue_entry); - fuse_send_writepage(fm, wpa, crop); + fuse_send_writepage(fc, wpa, crop); } } -static struct fuse_writepage_args *fuse_insert_writeback(struct rb_root *root, - struct fuse_writepage_args *wpa) -{ - pgoff_t idx_from = wpa->ia.write.in.offset >> PAGE_SHIFT; - pgoff_t idx_to = idx_from + wpa->ia.ap.num_pages - 1; - struct rb_node **p = &root->rb_node; - struct rb_node *parent = NULL; - - WARN_ON(!wpa->ia.ap.num_pages); - while (*p) { - struct fuse_writepage_args *curr; - pgoff_t curr_index; - - parent = *p; - curr = rb_entry(parent, struct fuse_writepage_args, - writepages_entry); - WARN_ON(curr->inode != wpa->inode); - curr_index = curr->ia.write.in.offset >> PAGE_SHIFT; - - if (idx_from >= curr_index + curr->ia.ap.num_pages) - p = &(*p)->rb_right; - else if (idx_to < curr_index) - p = &(*p)->rb_left; - else - return curr; - } - - rb_link_node(&wpa->writepages_entry, parent, p); - rb_insert_color(&wpa->writepages_entry, root); - return NULL; -} - -static void tree_insert(struct rb_root *root, struct fuse_writepage_args *wpa) -{ - WARN_ON(fuse_insert_writeback(root, wpa)); -} - -static void fuse_writepage_end(struct fuse_mount *fm, struct fuse_args *args, +static void fuse_writepage_end(struct fuse_conn *fc, struct fuse_args *args, int error) { struct fuse_writepage_args *wpa = container_of(args, typeof(*wpa), ia.ap.args); struct inode *inode = wpa->inode; struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_conn *fc = get_fuse_conn(inode); mapping_set_error(inode->i_mapping, error); - /* - * A writeback finished and this might have updated mtime/ctime on - * server making local mtime/ctime stale. Hence invalidate attrs. - * Do this only if writeback_cache is not enabled. If writeback_cache - * is enabled, we trust local ctime/mtime. - */ - if (!fc->writeback_cache) - fuse_invalidate_attr(inode); spin_lock(&fi->lock); - rb_erase(&wpa->writepages_entry, &fi->writepages); while (wpa->next) { - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_write_in *inarg = &wpa->ia.write.in; struct fuse_writepage_args *next = wpa->next; wpa->next = next->next; next->next = NULL; next->ia.ff = fuse_file_get(wpa->ia.ff); - tree_insert(&fi->writepages, next); + list_add(&next->writepages_entry, &fi->writepages); /* * Skip fuse_flush_writepages() to make it easy to crop requests @@ -1977,10 +1783,10 @@ static void fuse_writepage_end(struct fuse_mount *fm, struct fuse_args *args, * no invocations of fuse_writepage_end() while we're in * fuse_set_nowrite..fuse_release_nowrite section. */ - fuse_send_writepage(fm, next, inarg->offset + inarg->size); + fuse_send_writepage(fc, next, inarg->offset + inarg->size); } fi->writectr--; - fuse_writepage_finish(fm, wpa); + fuse_writepage_finish(fc, wpa); spin_unlock(&fi->lock); fuse_writepage_free(wpa); } @@ -2016,33 +1822,10 @@ int fuse_write_inode(struct inode *inode, struct writeback_control *wbc) struct fuse_file *ff; int err; - /** - * TODO - fully understand why this is necessary - * - * With fuse-bpf, fsstress fails if rename is enabled without this - * - * We are getting writes here on directory inodes, which do not have an - * initialized file list so crash. - * - * The question is why we are getting those writes - */ - if (!S_ISREG(inode->i_mode)) - return 0; - /* - * Inode is always written before the last reference is dropped and - * hence this should not be reached from reclaim. - * - * Writing back the inode from reclaim can deadlock if the request - * processing itself needs an allocation. Allocations triggering - * reclaim while serving a request can't be prevented, because it can - * involve any number of unrelated userspace processes. - */ - WARN_ON(wbc->for_reclaim); - ff = __fuse_write_file_get(fc, fi); err = fuse_flush_times(inode, ff); if (ff) - fuse_file_put(inode, ff, false, false); + fuse_file_put(ff, false, false); return err; } @@ -2110,7 +1893,7 @@ static int fuse_writepage_locked(struct page *page) inc_node_page_state(tmp_page, NR_WRITEBACK_TEMP); spin_lock(&fi->lock); - tree_insert(&fi->writepages, wpa); + list_add(&wpa->writepages_entry, &fi->writepages); list_add_tail(&wpa->queue_entry, &fi->queued_writes); fuse_flush_writepages(inode); spin_unlock(&fi->lock); @@ -2205,14 +1988,14 @@ static void fuse_writepages_send(struct fuse_fill_wb_data *data) } /* - * Check under fi->lock if the page is under writeback, and insert it onto the - * rb_tree if not. Otherwise iterate auxiliary write requests, to see if there's + * First recheck under fi->lock if the offending offset is still under + * writeback. If yes, then iterate auxiliary write requests, to see if there's * one already added for a page at this offset. If there's none, then insert * this new request onto the auxiliary list, otherwise reuse the existing one by - * swapping the new temp page with the old one. + * copying the new page contents over to the old temporary page. */ -static bool fuse_writepage_add(struct fuse_writepage_args *new_wpa, - struct page *page) +static bool fuse_writepage_in_flight(struct fuse_writepage_args *new_wpa, + struct page *page) { struct fuse_inode *fi = get_fuse_inode(new_wpa->inode); struct fuse_writepage_args *tmp; @@ -2220,15 +2003,17 @@ static bool fuse_writepage_add(struct fuse_writepage_args *new_wpa, struct fuse_args_pages *new_ap = &new_wpa->ia.ap; WARN_ON(new_ap->num_pages != 0); - new_ap->num_pages = 1; spin_lock(&fi->lock); - old_wpa = fuse_insert_writeback(&fi->writepages, new_wpa); + list_del(&new_wpa->writepages_entry); + old_wpa = fuse_find_writeback(fi, page->index, page->index); if (!old_wpa) { + list_add(&new_wpa->writepages_entry, &fi->writepages); spin_unlock(&fi->lock); - return true; + return false; } + new_ap->num_pages = 1; for (tmp = old_wpa->next; tmp; tmp = tmp->next) { pgoff_t curr_index; @@ -2257,41 +2042,7 @@ static bool fuse_writepage_add(struct fuse_writepage_args *new_wpa, fuse_writepage_free(new_wpa); } - return false; -} - -static bool fuse_writepage_need_send(struct fuse_conn *fc, struct page *page, - struct fuse_args_pages *ap, - struct fuse_fill_wb_data *data) -{ - WARN_ON(!ap->num_pages); - - /* - * Being under writeback is unlikely but possible. For example direct - * read to an mmaped fuse file will set the page dirty twice; once when - * the pages are faulted with get_user_pages(), and then after the read - * completed. - */ - if (fuse_page_is_writeback(data->inode, page->index)) - return true; - - /* Reached max pages */ - if (ap->num_pages == fc->max_pages) - return true; - - /* Reached max write bytes */ - if ((ap->num_pages + 1) * PAGE_SIZE > fc->max_write) - return true; - - /* Discontinuity */ - if (data->orig_pages[ap->num_pages - 1]->index + 1 != page->index) - return true; - - /* Need to grow the pages array? If so, did the expansion fail? */ - if (ap->num_pages == data->max_pages && !fuse_pages_realloc(data)) - return true; - - return false; + return true; } static int fuse_writepages_fill(struct page *page, @@ -2304,6 +2055,7 @@ static int fuse_writepages_fill(struct page *page, struct fuse_inode *fi = get_fuse_inode(inode); struct fuse_conn *fc = get_fuse_conn(inode); struct page *tmp_page; + bool is_writeback; int err; if (!data->ff) { @@ -2313,9 +2065,25 @@ static int fuse_writepages_fill(struct page *page, goto out_unlock; } - if (wpa && fuse_writepage_need_send(fc, page, ap, data)) { + /* + * Being under writeback is unlikely but possible. For example direct + * read to an mmaped fuse file will set the page dirty twice; once when + * the pages are faulted with get_user_pages(), and then after the read + * completed. + */ + is_writeback = fuse_page_is_writeback(inode, page->index); + + if (wpa && ap->num_pages && + (is_writeback || ap->num_pages == fc->max_pages || + (ap->num_pages + 1) * PAGE_SIZE > fc->max_write || + data->orig_pages[ap->num_pages - 1]->index + 1 != page->index)) { fuse_writepages_send(data); data->wpa = NULL; + } else if (wpa && ap->num_pages == data->max_pages) { + if (!fuse_pages_realloc(data)) { + fuse_writepages_send(data); + data->wpa = NULL; + } } err = -ENOMEM; @@ -2353,6 +2121,12 @@ static int fuse_writepages_fill(struct page *page, ap->args.end = fuse_writepage_end; ap->num_pages = 0; wpa->inode = inode; + + spin_lock(&fi->lock); + list_add(&wpa->writepages_entry, &fi->writepages); + spin_unlock(&fi->lock); + + data->wpa = wpa; } set_page_writeback(page); @@ -2360,25 +2134,26 @@ static int fuse_writepages_fill(struct page *page, ap->pages[ap->num_pages] = tmp_page; ap->descs[ap->num_pages].offset = 0; ap->descs[ap->num_pages].length = PAGE_SIZE; - data->orig_pages[ap->num_pages] = page; inc_wb_stat(&inode_to_bdi(inode)->wb, WB_WRITEBACK); inc_node_page_state(tmp_page, NR_WRITEBACK_TEMP); err = 0; - if (data->wpa) { - /* - * Protected by fi->lock against concurrent access by - * fuse_page_is_writeback(). - */ - spin_lock(&fi->lock); - ap->num_pages++; - spin_unlock(&fi->lock); - } else if (fuse_writepage_add(wpa, page)) { - data->wpa = wpa; - } else { + if (is_writeback && fuse_writepage_in_flight(wpa, page)) { end_page_writeback(page); + data->wpa = NULL; + goto out_unlock; } + data->orig_pages[ap->num_pages] = page; + + /* + * Protected by fi->lock against concurrent access by + * fuse_page_is_writeback(). + */ + spin_lock(&fi->lock); + ap->num_pages++; + spin_unlock(&fi->lock); + out_unlock: unlock_page(page); @@ -2414,7 +2189,7 @@ static int fuse_writepages(struct address_space *mapping, fuse_writepages_send(&data); } if (data.ff) - fuse_file_put(inode, data.ff, false, false); + fuse_file_put(data.ff, false, false); kfree(data.orig_pages); out: @@ -2561,16 +2336,6 @@ static int fuse_file_mmap(struct file *file, struct vm_area_struct *vma) { struct fuse_file *ff = file->private_data; - /* DAX mmap is superior to direct_io mmap */ - if (FUSE_IS_DAX(file_inode(file))) - return fuse_dax_mmap(file, vma); - -#ifdef CONFIG_FUSE_BPF - /* TODO - this is simply passthrough, not a proper BPF filter */ - if (ff->backing_file) - return fuse_backing_mmap(file, vma); -#endif - if (ff->passthrough.filp) return fuse_passthrough_mmap(file, vma); @@ -2652,7 +2417,7 @@ static void fuse_lk_fill(struct fuse_args *args, struct file *file, static int fuse_getlk(struct file *file, struct file_lock *fl) { struct inode *inode = file_inode(file); - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); struct fuse_lk_in inarg; struct fuse_lk_out outarg; @@ -2662,9 +2427,9 @@ static int fuse_getlk(struct file *file, struct file_lock *fl) args.out_numargs = 1; args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (!err) - err = convert_fuse_file_lock(fm->fc, &outarg.lk, fl); + err = convert_fuse_file_lock(fc, &outarg.lk, fl); return err; } @@ -2672,12 +2437,12 @@ static int fuse_getlk(struct file *file, struct file_lock *fl) static int fuse_setlk(struct file *file, struct file_lock *fl, int flock) { struct inode *inode = file_inode(file); - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); struct fuse_lk_in inarg; int opcode = (fl->fl_flags & FL_SLEEP) ? FUSE_SETLKW : FUSE_SETLK; struct pid *pid = fl->fl_type != F_UNLCK ? task_tgid(current) : NULL; - pid_t pid_nr = pid_nr_ns(pid, fm->fc->pid_ns); + pid_t pid_nr = pid_nr_ns(pid, fc->pid_ns); int err; if (fl->fl_lmops && fl->fl_lmops->lm_grant) { @@ -2690,7 +2455,7 @@ static int fuse_setlk(struct file *file, struct file_lock *fl, int flock) return 0; fuse_lk_fill(&args, file, fl, opcode, pid_nr, flock, &inarg); - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); /* locking is restartable */ if (err == -EINTR) @@ -2726,18 +2491,12 @@ static int fuse_file_flock(struct file *file, int cmd, struct file_lock *fl) { struct inode *inode = file_inode(file); struct fuse_conn *fc = get_fuse_conn(inode); - struct fuse_file *ff = file->private_data; int err; -#ifdef CONFIG_FUSE_BPF - /* TODO - this is simply passthrough, not a proper BPF filter */ - if (ff->backing_file) - return fuse_file_flock_backing(file, cmd, fl); -#endif - if (fc->no_flock) { err = locks_lock_file_wait(file, fl); } else { + struct fuse_file *ff = file->private_data; /* emulate flock with POSIX locks */ ff->flock = true; @@ -2750,13 +2509,13 @@ static int fuse_file_flock(struct file *file, int cmd, struct file_lock *fl) static sector_t fuse_bmap(struct address_space *mapping, sector_t block) { struct inode *inode = mapping->host; - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); struct fuse_bmap_in inarg; struct fuse_bmap_out outarg; int err; - if (!inode->i_sb->s_bdev || fm->fc->no_bmap) + if (!inode->i_sb->s_bdev || fc->no_bmap) return 0; memset(&inarg, 0, sizeof(inarg)); @@ -2770,9 +2529,9 @@ static sector_t fuse_bmap(struct address_space *mapping, sector_t block) args.out_numargs = 1; args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err == -ENOSYS) - fm->fc->no_bmap = 1; + fc->no_bmap = 1; return err ? 0 : outarg.block; } @@ -2780,7 +2539,7 @@ static sector_t fuse_bmap(struct address_space *mapping, sector_t block) static loff_t fuse_lseek(struct file *file, loff_t offset, int whence) { struct inode *inode = file->f_mapping->host; - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_file *ff = file->private_data; FUSE_ARGS(args); struct fuse_lseek_in inarg = { @@ -2791,7 +2550,7 @@ static loff_t fuse_lseek(struct file *file, loff_t offset, int whence) struct fuse_lseek_out outarg; int err; - if (fm->fc->no_lseek) + if (fc->no_lseek) goto fallback; args.opcode = FUSE_LSEEK; @@ -2802,10 +2561,10 @@ static loff_t fuse_lseek(struct file *file, loff_t offset, int whence) args.out_numargs = 1; args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err) { if (err == -ENOSYS) { - fm->fc->no_lseek = 1; + fc->no_lseek = 1; goto fallback; } return err; @@ -2825,17 +2584,6 @@ static loff_t fuse_file_llseek(struct file *file, loff_t offset, int whence) { loff_t retval; struct inode *inode = file_inode(file); -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_lseek_io, - fuse_lseek_initialize, - fuse_lseek_backing, - fuse_lseek_finalize, - file, offset, whence); - if (fer.ret) - return PTR_ERR(fer.result); -#endif switch (whence) { case SEEK_SET: @@ -3002,7 +2750,7 @@ long fuse_do_ioctl(struct file *file, unsigned int cmd, unsigned long arg, unsigned int flags) { struct fuse_file *ff = file->private_data; - struct fuse_mount *fm = ff->fm; + struct fuse_conn *fc = ff->fc; struct fuse_ioctl_in inarg = { .fh = ff->fh, .cmd = cmd, @@ -3035,12 +2783,12 @@ long fuse_do_ioctl(struct file *file, unsigned int cmd, unsigned long arg, BUILD_BUG_ON(sizeof(struct fuse_ioctl_iovec) * FUSE_IOCTL_MAX_IOV > PAGE_SIZE); err = -ENOMEM; - ap.pages = fuse_pages_alloc(fm->fc->max_pages, GFP_KERNEL, &ap.descs); + ap.pages = fuse_pages_alloc(fc->max_pages, GFP_KERNEL, &ap.descs); iov_page = (struct iovec *) __get_free_page(GFP_KERNEL); if (!ap.pages || !iov_page) goto out; - fuse_page_descs_length_init(ap.descs, 0, fm->fc->max_pages); + fuse_page_descs_length_init(ap.descs, 0, fc->max_pages); /* * If restricted, initialize IO parameters as encoded in @cmd. @@ -3085,7 +2833,7 @@ long fuse_do_ioctl(struct file *file, unsigned int cmd, unsigned long arg, /* make sure there are enough buffer pages and init request with them */ err = -ENOMEM; - if (max_pages > fm->fc->max_pages) + if (max_pages > fc->max_pages) goto out; while (ap.num_pages < max_pages) { ap.pages[ap.num_pages] = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); @@ -3122,7 +2870,7 @@ long fuse_do_ioctl(struct file *file, unsigned int cmd, unsigned long arg, ap.args.out_pages = true; ap.args.out_argvar = true; - transferred = fuse_simple_request(fm, &ap.args); + transferred = fuse_simple_request(fc, &ap.args); err = transferred; if (transferred < 0) goto out; @@ -3150,7 +2898,7 @@ long fuse_do_ioctl(struct file *file, unsigned int cmd, unsigned long arg, goto out; vaddr = kmap_atomic(ap.pages[0]); - err = fuse_copy_ioctl_iovec(fm->fc, iov_page, vaddr, + err = fuse_copy_ioctl_iovec(fc, iov_page, vaddr, transferred, in_iovs + out_iovs, (flags & FUSE_IOCTL_COMPAT) != 0); kunmap_atomic(vaddr); @@ -3160,11 +2908,11 @@ long fuse_do_ioctl(struct file *file, unsigned int cmd, unsigned long arg, in_iov = iov_page; out_iov = in_iov + in_iovs; - err = fuse_verify_ioctl_iov(fm->fc, in_iov, in_iovs); + err = fuse_verify_ioctl_iov(fc, in_iov, in_iovs); if (err) goto out; - err = fuse_verify_ioctl_iov(fm->fc, out_iov, out_iovs); + err = fuse_verify_ioctl_iov(fc, out_iov, out_iovs); if (err) goto out; @@ -3205,15 +2953,6 @@ long fuse_ioctl_common(struct file *file, unsigned int cmd, if (fuse_is_bad(inode)) return -EIO; -#ifdef CONFIG_FUSE_BPF - { - struct fuse_file *ff = file->private_data; - - /* TODO - this is simply passthrough, not a proper BPF filter */ - if (ff->backing_file) - return fuse_backing_ioctl(file, cmd, arg, flags); - } -#endif return fuse_do_ioctl(file, cmd, arg, flags); } @@ -3283,13 +3022,13 @@ static void fuse_register_polled_file(struct fuse_conn *fc, __poll_t fuse_file_poll(struct file *file, poll_table *wait) { struct fuse_file *ff = file->private_data; - struct fuse_mount *fm = ff->fm; + struct fuse_conn *fc = ff->fc; struct fuse_poll_in inarg = { .fh = ff->fh, .kh = ff->kh }; struct fuse_poll_out outarg; FUSE_ARGS(args); int err; - if (fm->fc->no_poll) + if (fc->no_poll) return DEFAULT_POLLMASK; poll_wait(file, &ff->poll_wait, wait); @@ -3301,7 +3040,7 @@ __poll_t fuse_file_poll(struct file *file, poll_table *wait) */ if (waitqueue_active(&ff->poll_wait)) { inarg.flags |= FUSE_POLL_SCHEDULE_NOTIFY; - fuse_register_polled_file(fm->fc, ff); + fuse_register_polled_file(fc, ff); } args.opcode = FUSE_POLL; @@ -3312,12 +3051,12 @@ __poll_t fuse_file_poll(struct file *file, poll_table *wait) args.out_numargs = 1; args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (!err) return demangle_poll(outarg.revents); if (err == -ENOSYS) { - fm->fc->no_poll = 1; + fc->no_poll = 1; return DEFAULT_POLLMASK; } return EPOLLERR; @@ -3403,13 +3142,13 @@ fuse_direct_IO(struct kiocb *iocb, struct iov_iter *iter) * By default, we want to optimize all I/Os with async request * submission to the client filesystem if supported. */ - io->async = ff->fm->fc->async_dio; + io->async = ff->fc->async_dio; io->iocb = iocb; io->blocking = is_sync_kiocb(iocb); /* optimization for short read */ if (io->async && !io->write && offset + count > i_size) { - iov_iter_truncate(iter, fuse_round_up(ff->fm->fc, i_size - offset)); + iov_iter_truncate(iter, fuse_round_up(ff->fc, i_size - offset)); shortened = count - iov_iter_count(iter); count -= shortened; } @@ -3479,7 +3218,7 @@ static long fuse_file_fallocate(struct file *file, int mode, loff_t offset, struct fuse_file *ff = file->private_data; struct inode *inode = file_inode(file); struct fuse_inode *fi = get_fuse_inode(inode); - struct fuse_mount *fm = ff->fm; + struct fuse_conn *fc = ff->fc; FUSE_ARGS(args); struct fuse_fallocate_in inarg = { .fh = ff->fh, @@ -3488,36 +3227,13 @@ static long fuse_file_fallocate(struct file *file, int mode, loff_t offset, .mode = mode }; int err; - bool block_faults = FUSE_IS_DAX(inode) && - (!(mode & FALLOC_FL_KEEP_SIZE) || - (mode & FALLOC_FL_PUNCH_HOLE)); - -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_fallocate_in, - fuse_file_fallocate_initialize, - fuse_file_fallocate_backing, - fuse_file_fallocate_finalize, - file, mode, offset, length); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (mode & ~(FALLOC_FL_KEEP_SIZE | FALLOC_FL_PUNCH_HOLE)) return -EOPNOTSUPP; - if (fm->fc->no_fallocate) + if (fc->no_fallocate) return -EOPNOTSUPP; inode_lock(inode); - if (block_faults) { - down_write(&fi->i_mmap_sem); - err = fuse_dax_break_layouts(inode, 0, 0); - if (err) - goto out; - } - if (mode & FALLOC_FL_PUNCH_HOLE) { loff_t endbyte = offset + length - 1; @@ -3545,9 +3261,9 @@ static long fuse_file_fallocate(struct file *file, int mode, loff_t offset, args.in_numargs = 1; args.in_args[0].size = sizeof(inarg); args.in_args[0].value = &inarg; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err == -ENOSYS) { - fm->fc->no_fallocate = 1; + fc->no_fallocate = 1; err = -EOPNOTSUPP; } if (err) @@ -3557,7 +3273,7 @@ static long fuse_file_fallocate(struct file *file, int mode, loff_t offset, if (!(mode & FALLOC_FL_KEEP_SIZE)) { bool changed = fuse_write_update_size(inode, offset + length); - if (changed && fm->fc->writeback_cache) + if (changed && fc->writeback_cache) file_update_time(file); } @@ -3570,13 +3286,8 @@ out: if (!(mode & FALLOC_FL_KEEP_SIZE)) clear_bit(FUSE_I_SIZE_UNSTABLE, &fi->state); - if (block_faults) - up_write(&fi->i_mmap_sem); - inode_unlock(inode); - fuse_flush_time_update(inode); - return err; } @@ -3589,8 +3300,7 @@ static ssize_t __fuse_copy_file_range(struct file *file_in, loff_t pos_in, struct inode *inode_in = file_inode(file_in); struct inode *inode_out = file_inode(file_out); struct fuse_inode *fi_out = get_fuse_inode(inode_out); - struct fuse_mount *fm = ff_in->fm; - struct fuse_conn *fc = fm->fc; + struct fuse_conn *fc = ff_in->fc; FUSE_ARGS(args); struct fuse_copy_file_range_in inarg = { .fh_in = ff_in->fh, @@ -3608,18 +3318,6 @@ static ssize_t __fuse_copy_file_range(struct file *file_in, loff_t pos_in, bool is_unstable = (!fc->writeback_cache) && ((pos_out + len) > inode_out->i_size); -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(file_in->f_inode, struct fuse_copy_file_range_io, - fuse_copy_file_range_initialize, - fuse_copy_file_range_backing, - fuse_copy_file_range_finalize, - file_in, pos_in, file_out, pos_out, len, flags); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (fc->no_copy_file_range) return -EOPNOTSUPP; @@ -3671,7 +3369,7 @@ static ssize_t __fuse_copy_file_range(struct file *file_in, loff_t pos_in, args.out_numargs = 1; args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err == -ENOSYS) { fc->no_copy_file_range = 1; err = -EOPNOTSUPP; @@ -3729,7 +3427,6 @@ static const struct file_operations fuse_file_operations = { .release = fuse_release, .fsync = fuse_fsync, .lock = fuse_file_lock, - .get_unmapped_area = thp_get_unmapped_area, .flock = fuse_file_flock, .splice_read = generic_file_splice_read, .splice_write = iter_file_splice_write, @@ -3764,8 +3461,5 @@ void fuse_init_file_inode(struct inode *inode) INIT_LIST_HEAD(&fi->queued_writes); fi->writectr = 0; init_waitqueue_head(&fi->page_waitq); - fi->writepages = RB_ROOT; - - if (IS_ENABLED(CONFIG_FUSE_DAX)) - fuse_dax_inode_init(inode); + INIT_LIST_HEAD(&fi->writepages); } diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h index 97b44bbf5274..2eec57bb3707 100644 --- a/fs/fuse/fuse_i.h +++ b/fs/fuse/fuse_i.h @@ -13,8 +13,6 @@ # define pr_fmt(fmt) "fuse: " fmt #endif -#include -#include #include #include #include @@ -33,9 +31,6 @@ #include #include #include -#include - -#define FUSE_SUPER_MAGIC 0x65735546 /** Default max number of pages that can be used in a single read request */ #define FUSE_DEFAULT_MAX_PAGES_PER_REQ 32 @@ -68,63 +63,11 @@ struct fuse_forget_link { struct fuse_forget_link *next; }; -/** FUSE specific dentry data */ -#if BITS_PER_LONG < 64 || defined(CONFIG_FUSE_BPF) -struct fuse_dentry { - union { - u64 time; - struct rcu_head rcu; - }; - -#ifdef CONFIG_FUSE_BPF - struct path backing_path; - - /* bpf program *only* set for negative dentries */ - struct bpf_prog *bpf; -#endif -}; - -static inline struct fuse_dentry *get_fuse_dentry(const struct dentry *entry) -{ - return entry->d_fsdata; -} -#endif - -#ifdef CONFIG_FUSE_BPF -static inline void get_fuse_backing_path(const struct dentry *d, - struct path *path) -{ - struct fuse_dentry *di = get_fuse_dentry(d); - - if (!di) { - *path = (struct path) {}; - return; - } - - *path = di->backing_path; - path_get(path); -} -#endif - /** FUSE inode */ struct fuse_inode { /** Inode data */ struct inode inode; -#ifdef CONFIG_FUSE_BPF - /** - * Backing inode, if this inode is from a backing file system. - * If this is set, nodeid is 0. - */ - struct inode *backing_inode; - - /** - * bpf_prog, run on all operations to determine whether to pass through - * or handle in place - */ - struct bpf_prog *bpf; -#endif - /** Unique ID, which identifies the inode between userspace * and kernel */ u64 nodeid; @@ -168,7 +111,7 @@ struct fuse_inode { wait_queue_head_t page_waitq; /* List of writepage requestst (pending or sent) */ - struct rb_root writepages; + struct list_head writepages; }; /* readdir cache (directory only) */ @@ -205,20 +148,6 @@ struct fuse_inode { /** Lock to protect write related fields */ spinlock_t lock; - - /** - * Can't take inode lock in fault path (leads to circular dependency). - * Introduce another semaphore which can be taken in fault path and - * then other filesystem paths can take this to block faults. - */ - struct rw_semaphore i_mmap_sem; - -#ifdef CONFIG_FUSE_DAX - /* - * Dax specific inode data - */ - struct fuse_inode_dax *dax; -#endif }; /** FUSE inode state bits */ @@ -234,7 +163,6 @@ enum { }; struct fuse_conn; -struct fuse_mount; struct fuse_release_args; /** @@ -251,7 +179,7 @@ struct fuse_passthrough { /** FUSE specific file data */ struct fuse_file { /** Fuse connection for this file */ - struct fuse_mount *fm; + struct fuse_conn *fc; /* Argument space reserved for release */ struct fuse_release_args *release_args; @@ -296,14 +224,6 @@ struct fuse_file { /** Container for data related to the passthrough functionality */ struct fuse_passthrough passthrough; -#ifdef CONFIG_FUSE_BPF - /** - * TODO: Reconcile with passthrough file - * backing file when in bpf mode - */ - struct file *backing_file; -#endif - /** RB node to be linked on fuse_conn->polled_files */ struct rb_node polled_node; @@ -335,7 +255,6 @@ struct fuse_page_desc { struct fuse_args { uint64_t nodeid; uint32_t opcode; - uint32_t error_in; unsigned short in_numargs; unsigned short out_numargs; bool force:1; @@ -348,9 +267,9 @@ struct fuse_args { bool page_zeroing:1; bool page_replace:1; bool may_block:1; - struct fuse_in_arg in_args[FUSE_MAX_IN_ARGS]; - struct fuse_arg out_args[FUSE_MAX_OUT_ARGS]; - void (*end)(struct fuse_mount *fm, struct fuse_args *args, int error); + struct fuse_in_arg in_args[3]; + struct fuse_arg out_args[2]; + void (*end)(struct fuse_conn *fc, struct fuse_args *args, int error); /* Path used for completing d_canonical_path */ struct path *canonical_path; @@ -457,11 +376,10 @@ struct fuse_req { /** Used to wake up the task waiting for completion of request*/ wait_queue_head_t waitq; +#if IS_ENABLED(CONFIG_VIRTIO_FS) /** virtio-fs's physically contiguous buffer for in and out args */ void *argbuf; - - /** fuse_mount this request belongs to */ - struct fuse_mount *fm; +#endif }; struct fuse_iqueue; @@ -584,17 +502,10 @@ struct fuse_fs_context { bool destroy:1; bool no_control:1; bool no_force_umount:1; - bool legacy_opts_show:1; - bool dax:1; - bool no_daemon:1; + bool no_mount_options:1; unsigned int max_read; unsigned int blksize; const char *subtype; - struct bpf_prog *root_bpf; - struct file *root_dir; - - /* DAX device, may be NULL */ - struct dax_device *dax_dev; /* fuse_dev pointer to fill in, should contain NULL on entry */ void **fudptr; @@ -603,9 +514,9 @@ struct fuse_fs_context { /** * A Fuse connection. * - * This structure is created, when the root filesystem is mounted, and - * is destroyed, when the client device is closed and the last - * fuse_mount is destroyed. + * This structure is created, when the filesystem is mounted, and is + * destroyed, when the client device is closed and the filesystem is + * unmounted. */ struct fuse_conn { /** Lock protecting accessess to members of this structure */ @@ -640,9 +551,6 @@ struct fuse_conn { /** Maxmum number of pages that can be used in a single request */ unsigned int max_pages; - /** Constrain ->max_pages to this value during feature negotiation */ - unsigned int max_pages_limit; - /** Input queue */ struct fuse_iqueue iq; @@ -722,9 +630,6 @@ struct fuse_conn { /** cache READLINK responses in page cache */ unsigned cache_symlinks:1; - /* show legacy mount options */ - unsigned int legacy_opts_show:1; - /* * The following bitfields are only for optimization purposes * and hence races in setting them will not cause malfunction @@ -832,25 +737,22 @@ struct fuse_conn { /** Do not allow MNT_FORCE umount */ unsigned int no_force_umount:1; - /* Auto-mount submounts announced by the server */ - unsigned int auto_submounts:1; + /* Do not show mount options */ + unsigned int no_mount_options:1; /** Passthrough mode for read/write IO */ unsigned int passthrough:1; - /** BPF Only, no Daemon running */ - unsigned int no_daemon:1; - /** The number of requests waiting for completion */ atomic_t num_waiting; /** Negotiated minor version */ unsigned minor; - /** Entry on the fuse_mount_list */ + /** Entry on the fuse_conn_list */ struct list_head entry; - /** Device ID from the root super block */ + /** Device ID from super block */ dev_t dev; /** Dentries in the control filesystem */ @@ -868,23 +770,15 @@ struct fuse_conn { /** Called on final put */ void (*release)(struct fuse_conn *); - /** - * Read/write semaphore to hold when accessing the sb of any - * fuse_mount belonging to this connection - */ + /** Super block for this connection. */ + struct super_block *sb; + + /** Read/write semaphore to hold when accessing sb. */ struct rw_semaphore killsb; /** List of device instances belonging to this connection */ struct list_head devices; -#ifdef CONFIG_FUSE_DAX - /* Dax specific conn data, non-NULL if DAX is enabled */ - struct fuse_conn_dax *dax; -#endif - - /** List of filesystems using this connection */ - struct list_head mounts; - /** IDR for passthrough requests */ struct idr passthrough_req; @@ -892,52 +786,14 @@ struct fuse_conn { spinlock_t passthrough_req_lock; }; -/* - * Represents a mounted filesystem, potentially a submount. - * - * This object allows sharing a fuse_conn between separate mounts to - * allow submounts with dedicated superblocks and thus separate device - * IDs. - */ -struct fuse_mount { - /* Underlying (potentially shared) connection to the FUSE server */ - struct fuse_conn *fc; - - /* Refcount */ - refcount_t count; - - /* - * Super block for this connection (fc->killsb must be held when - * accessing this). - */ - struct super_block *sb; - - /* Entry on fc->mounts */ - struct list_head fc_entry; -}; - -static inline struct fuse_mount *get_fuse_mount_super(struct super_block *sb) +static inline struct fuse_conn *get_fuse_conn_super(struct super_block *sb) { return sb->s_fs_info; } -static inline struct fuse_conn *get_fuse_conn_super(struct super_block *sb) -{ - struct fuse_mount *fm = get_fuse_mount_super(sb); - - return fm ? fm->fc : NULL; -} - -static inline struct fuse_mount *get_fuse_mount(struct inode *inode) -{ - return get_fuse_mount_super(inode->i_sb); -} - static inline struct fuse_conn *get_fuse_conn(struct inode *inode) { - struct fuse_mount *fm = get_fuse_mount(inode); - - return fm ? fm->fc : NULL; + return get_fuse_conn_super(inode->i_sb); } static inline struct fuse_inode *get_fuse_inode(struct inode *inode) @@ -960,13 +816,6 @@ static inline u64 fuse_get_attr_version(struct fuse_conn *fc) return atomic64_read(&fc->attr_version); } -static inline bool fuse_stale_inode(const struct inode *inode, int generation, - struct fuse_attr *attr) -{ - return inode->i_generation != generation || - inode_wrong_type(inode, attr->mode); -} - static inline void fuse_make_bad(struct inode *inode) { set_bit(FUSE_I_BAD, &get_fuse_inode(inode)->state); @@ -984,18 +833,19 @@ extern const struct dentry_operations fuse_dentry_operations; extern const struct dentry_operations fuse_root_dentry_operations; /** - * Get a filled-in inode + * Inode to nodeid comparison. + */ +int fuse_inode_eq(struct inode *inode, void *_nodeidp); + +/** + * Get a filled in inode */ -struct inode *fuse_iget_backing(struct super_block *sb, - u64 nodeid, - struct inode *backing_inode); struct inode *fuse_iget(struct super_block *sb, u64 nodeid, int generation, struct fuse_attr *attr, u64 attr_valid, u64 attr_version); int fuse_lookup_name(struct super_block *sb, u64 nodeid, const struct qstr *name, - struct fuse_entry_out *outarg, - struct dentry *entry, struct inode **inode); + struct fuse_entry_out *outarg, struct inode **inode); /** * Send FORGET command @@ -1032,12 +882,13 @@ struct fuse_io_args { void fuse_read_args_fill(struct fuse_io_args *ia, struct file *file, loff_t pos, size_t count, int opcode); + /** * Send OPEN or OPENDIR request */ int fuse_open_common(struct inode *inode, struct file *file, bool isdir); -struct fuse_file *fuse_file_alloc(struct fuse_mount *fm); +struct fuse_file *fuse_file_alloc(struct fuse_conn *fc); void fuse_file_free(struct fuse_file *ff); void fuse_finish_open(struct inode *inode, struct file *file); @@ -1100,19 +951,19 @@ int fuse_dev_init(void); void fuse_dev_cleanup(void); int fuse_ctl_init(void); -void fuse_ctl_cleanup(void); +void __exit fuse_ctl_cleanup(void); /** * Simple request sending that does request allocation and freeing */ -ssize_t fuse_simple_request(struct fuse_mount *fm, struct fuse_args *args); -int fuse_simple_background(struct fuse_mount *fm, struct fuse_args *args, +ssize_t fuse_simple_request(struct fuse_conn *fc, struct fuse_args *args); +int fuse_simple_background(struct fuse_conn *fc, struct fuse_args *args, gfp_t gfp_flags); /** * End a finished request */ -void fuse_request_end(struct fuse_req *req); +void fuse_request_end(struct fuse_conn *fc, struct fuse_req *req); /* Abort all requests */ void fuse_abort_conn(struct fuse_conn *fc); @@ -1128,7 +979,6 @@ void fuse_invalidate_entry_cache(struct dentry *entry); void fuse_invalidate_atime(struct inode *inode); u64 entry_attr_timeout(struct fuse_entry_out *o); -void fuse_init_dentry_root(struct dentry *root, struct file *backing_dir); void fuse_change_entry_timeout(struct dentry *entry, struct fuse_entry_out *o); /** @@ -1139,8 +989,7 @@ struct fuse_conn *fuse_conn_get(struct fuse_conn *fc); /** * Initialize fuse_conn */ -void fuse_conn_init(struct fuse_conn *fc, struct fuse_mount *fm, - struct user_namespace *user_ns, +void fuse_conn_init(struct fuse_conn *fc, struct user_namespace *user_ns, const struct fuse_iqueue_ops *fiq_ops, void *fiq_priv); /** @@ -1148,21 +997,11 @@ void fuse_conn_init(struct fuse_conn *fc, struct fuse_mount *fm, */ void fuse_conn_put(struct fuse_conn *fc); -/** - * Acquire reference to fuse_mount - */ -struct fuse_mount *fuse_mount_get(struct fuse_mount *fm); - -/** - * Release reference to fuse_mount - */ -void fuse_mount_put(struct fuse_mount *fm); - struct fuse_dev *fuse_dev_alloc_install(struct fuse_conn *fc); struct fuse_dev *fuse_dev_alloc(void); void fuse_dev_install(struct fuse_dev *fud, struct fuse_conn *fc); void fuse_dev_free(struct fuse_dev *fud); -void fuse_send_init(struct fuse_mount *fm); +void fuse_send_init(struct fuse_conn *fc); /** * Fill in superblock and initialize fuse connection @@ -1171,26 +1010,12 @@ void fuse_send_init(struct fuse_mount *fm); */ int fuse_fill_super_common(struct super_block *sb, struct fuse_fs_context *ctx); -/* - * Fill in superblock for submounts - * @sb: partially-initialized superblock to fill in - * @parent_fi: The fuse_inode of the parent filesystem where this submount is - * mounted - */ -int fuse_fill_super_submount(struct super_block *sb, - struct fuse_inode *parent_fi); - -/* - * Remove the mount from the connection +/** + * Disassociate fuse connection from superblock and kill the superblock * - * Returns whether this was the last mount + * Calls kill_anon_super(), do not use with bdev mounts. */ -bool fuse_mount_remove(struct fuse_mount *fm); - -/* - * Shut down the connection (possibly sending DESTROY request). - */ -void fuse_conn_destroy(struct fuse_mount *fm); +void fuse_kill_sb_anon(struct super_block *sb); /** * Add connection to control filesystem @@ -1216,7 +1041,6 @@ int fuse_allow_current_process(struct fuse_conn *fc); u64 fuse_lock_owner_id(struct fuse_conn *fc, fl_owner_t id); -void fuse_flush_time_update(struct inode *inode); void fuse_update_ctime(struct inode *inode); int fuse_update_attributes(struct inode *inode, struct file *file); @@ -1226,20 +1050,10 @@ void fuse_flush_writepages(struct inode *inode); void fuse_set_nowrite(struct inode *inode); void fuse_release_nowrite(struct inode *inode); -/** - * Scan all fuse_mounts belonging to fc to find the first where - * ilookup5() returns a result. Return that result and the - * respective fuse_mount in *fm (unless fm is NULL). - * - * The caller must hold fc->killsb. - */ -struct inode *fuse_ilookup(struct fuse_conn *fc, u64 nodeid, - struct fuse_mount **fm); - /** * File-system tells the kernel to invalidate cache for the given node id. */ -int fuse_reverse_inval_inode(struct fuse_conn *fc, u64 nodeid, +int fuse_reverse_inval_inode(struct super_block *sb, u64 nodeid, loff_t offset, loff_t len); /** @@ -1252,10 +1066,10 @@ int fuse_reverse_inval_inode(struct fuse_conn *fc, u64 nodeid, * - is a file or oan empty directory * then the dentry is unhashed (d_delete()). */ -int fuse_reverse_inval_entry(struct fuse_conn *fc, u64 parent_nodeid, +int fuse_reverse_inval_entry(struct super_block *sb, u64 parent_nodeid, u64 child_nodeid, struct qstr *name); -int fuse_do_open(struct fuse_mount *fm, u64 nodeid, struct file *file, +int fuse_do_open(struct fuse_conn *fc, u64 nodeid, struct file *file, bool isdir); /** @@ -1319,24 +1133,7 @@ unsigned int fuse_len_args(unsigned int numargs, struct fuse_arg *args); u64 fuse_get_unique(struct fuse_iqueue *fiq); void fuse_free_conn(struct fuse_conn *fc); -/* dax.c */ - -#define FUSE_IS_DAX(inode) (IS_ENABLED(CONFIG_FUSE_DAX) && IS_DAX(inode)) - -ssize_t fuse_dax_read_iter(struct kiocb *iocb, struct iov_iter *to); -ssize_t fuse_dax_write_iter(struct kiocb *iocb, struct iov_iter *from); -int fuse_dax_mmap(struct file *file, struct vm_area_struct *vma); -int fuse_dax_break_layouts(struct inode *inode, u64 dmap_start, u64 dmap_end); -int fuse_dax_conn_alloc(struct fuse_conn *fc, struct dax_device *dax_dev); -void fuse_dax_conn_free(struct fuse_conn *fc); -bool fuse_dax_inode_alloc(struct super_block *sb, struct fuse_inode *fi); -void fuse_dax_inode_init(struct inode *inode); -void fuse_dax_inode_cleanup(struct inode *inode); -bool fuse_dax_check_alignment(struct fuse_conn *fc, unsigned int map_alignment); -void fuse_dax_cancel_work(struct fuse_conn *fc); - /* passthrough.c */ -void fuse_copyattr(struct file *dst_file, struct file *src_file); int fuse_passthrough_open(struct fuse_dev *fud, u32 lower_fd); int fuse_passthrough_setup(struct fuse_conn *fc, struct fuse_file *ff, struct fuse_open_out *openarg); @@ -1345,648 +1142,4 @@ ssize_t fuse_passthrough_read_iter(struct kiocb *iocb, struct iov_iter *to); ssize_t fuse_passthrough_write_iter(struct kiocb *iocb, struct iov_iter *from); ssize_t fuse_passthrough_mmap(struct file *file, struct vm_area_struct *vma); -/* backing.c */ - -struct bpf_prog *fuse_get_bpf_prog(struct file *file); - -/* - * Dummy io passed to fuse_bpf_backing when io operation needs no scratch space - */ -struct fuse_dummy_io { - int unused; -}; - -struct fuse_open_io { - struct fuse_open_in foi; - struct fuse_open_out foo; -}; - -int fuse_open_initialize(struct fuse_bpf_args *fa, struct fuse_open_io *foi, - struct inode *inode, struct file *file, bool isdir); -int fuse_open_backing(struct fuse_bpf_args *fa, - struct inode *inode, struct file *file, bool isdir); -void *fuse_open_finalize(struct fuse_bpf_args *fa, - struct inode *inode, struct file *file, bool isdir); - -struct fuse_create_open_io { - struct fuse_create_in fci; - struct fuse_entry_out feo; - struct fuse_open_out foo; -}; - -int fuse_create_open_initialize( - struct fuse_bpf_args *fa, struct fuse_create_open_io *fcoi, - struct inode *dir, struct dentry *entry, - struct file *file, unsigned int flags, umode_t mode); -int fuse_create_open_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, - struct file *file, unsigned int flags, umode_t mode); -void *fuse_create_open_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, - struct file *file, unsigned int flags, umode_t mode); - -int fuse_mknod_initialize( - struct fuse_bpf_args *fa, struct fuse_mknod_in *fmi, - struct inode *dir, struct dentry *entry, umode_t mode, dev_t rdev); -int fuse_mknod_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, umode_t mode, dev_t rdev); -void *fuse_mknod_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, umode_t mode, dev_t rdev); - -int fuse_mkdir_initialize( - struct fuse_bpf_args *fa, struct fuse_mkdir_in *fmi, - struct inode *dir, struct dentry *entry, umode_t mode); -int fuse_mkdir_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, umode_t mode); -void *fuse_mkdir_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, umode_t mode); - -int fuse_rmdir_initialize( - struct fuse_bpf_args *fa, struct fuse_dummy_io *fmi, - struct inode *dir, struct dentry *entry); -int fuse_rmdir_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry); -void *fuse_rmdir_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry); - -int fuse_rename2_initialize(struct fuse_bpf_args *fa, struct fuse_rename2_in *fri, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent, - unsigned int flags); -int fuse_rename2_backing(struct fuse_bpf_args *fa, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent, - unsigned int flags); -void *fuse_rename2_finalize(struct fuse_bpf_args *fa, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent, - unsigned int flags); - -int fuse_rename_initialize(struct fuse_bpf_args *fa, struct fuse_rename_in *fri, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent); -int fuse_rename_backing(struct fuse_bpf_args *fa, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent); -void *fuse_rename_finalize(struct fuse_bpf_args *fa, - struct inode *olddir, struct dentry *oldent, - struct inode *newdir, struct dentry *newent); - -int fuse_unlink_initialize( - struct fuse_bpf_args *fa, struct fuse_dummy_io *fmi, - struct inode *dir, struct dentry *entry); -int fuse_unlink_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry); -void *fuse_unlink_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry); - -int fuse_link_initialize(struct fuse_bpf_args *fa, struct fuse_link_in *fli, - struct dentry *entry, struct inode *dir, - struct dentry *newent); -int fuse_link_backing(struct fuse_bpf_args *fa, struct dentry *entry, - struct inode *dir, struct dentry *newent); -void *fuse_link_finalize(struct fuse_bpf_args *fa, struct dentry *entry, - struct inode *dir, struct dentry *newent); - -int fuse_release_initialize(struct fuse_bpf_args *fa, struct fuse_release_in *fri, - struct inode *inode, struct fuse_file *ff); -int fuse_release_backing(struct fuse_bpf_args *fa, - struct inode *inode, struct fuse_file *ff); -void *fuse_release_finalize(struct fuse_bpf_args *fa, - struct inode *inode, struct fuse_file *ff); - -int fuse_flush_initialize(struct fuse_bpf_args *fa, struct fuse_flush_in *ffi, - struct file *file, fl_owner_t id); -int fuse_flush_backing(struct fuse_bpf_args *fa, struct file *file, fl_owner_t id); -void *fuse_flush_finalize(struct fuse_bpf_args *fa, - struct file *file, fl_owner_t id); - -struct fuse_lseek_io { - struct fuse_lseek_in fli; - struct fuse_lseek_out flo; -}; - -int fuse_lseek_initialize(struct fuse_bpf_args *fa, struct fuse_lseek_io *fli, - struct file *file, loff_t offset, int whence); -int fuse_lseek_backing(struct fuse_bpf_args *fa, struct file *file, loff_t offset, int whence); -void *fuse_lseek_finalize(struct fuse_bpf_args *fa, struct file *file, loff_t offset, int whence); - -struct fuse_copy_file_range_io { - struct fuse_copy_file_range_in fci; - struct fuse_write_out fwo; -}; - -int fuse_copy_file_range_initialize(struct fuse_bpf_args *fa, - struct fuse_copy_file_range_io *fcf, - struct file *file_in, loff_t pos_in, - struct file *file_out, loff_t pos_out, - size_t len, unsigned int flags); -int fuse_copy_file_range_backing(struct fuse_bpf_args *fa, - struct file *file_in, loff_t pos_in, - struct file *file_out, loff_t pos_out, - size_t len, unsigned int flags); -void *fuse_copy_file_range_finalize(struct fuse_bpf_args *fa, - struct file *file_in, loff_t pos_in, - struct file *file_out, loff_t pos_out, - size_t len, unsigned int flags); - -int fuse_fsync_initialize(struct fuse_bpf_args *fa, struct fuse_fsync_in *ffi, - struct file *file, loff_t start, loff_t end, int datasync); -int fuse_fsync_backing(struct fuse_bpf_args *fa, - struct file *file, loff_t start, loff_t end, int datasync); -void *fuse_fsync_finalize(struct fuse_bpf_args *fa, - struct file *file, loff_t start, loff_t end, int datasync); -int fuse_dir_fsync_initialize(struct fuse_bpf_args *fa, struct fuse_fsync_in *ffi, - struct file *file, loff_t start, loff_t end, int datasync); - -struct fuse_getxattr_io { - struct fuse_getxattr_in fgi; - struct fuse_getxattr_out fgo; -}; - -int fuse_getxattr_initialize( - struct fuse_bpf_args *fa, struct fuse_getxattr_io *fgio, - struct dentry *dentry, const char *name, void *value, - size_t size); -int fuse_getxattr_backing( - struct fuse_bpf_args *fa, - struct dentry *dentry, const char *name, void *value, - size_t size); -void *fuse_getxattr_finalize( - struct fuse_bpf_args *fa, - struct dentry *dentry, const char *name, void *value, - size_t size); - -int fuse_listxattr_initialize(struct fuse_bpf_args *fa, - struct fuse_getxattr_io *fgio, - struct dentry *dentry, char *list, size_t size); -int fuse_listxattr_backing(struct fuse_bpf_args *fa, struct dentry *dentry, - char *list, size_t size); -void *fuse_listxattr_finalize(struct fuse_bpf_args *fa, struct dentry *dentry, - char *list, size_t size); - -int fuse_setxattr_initialize(struct fuse_bpf_args *fa, - struct fuse_setxattr_in *fsxi, - struct dentry *dentry, const char *name, - const void *value, size_t size, int flags); -int fuse_setxattr_backing(struct fuse_bpf_args *fa, struct dentry *dentry, - const char *name, const void *value, size_t size, - int flags); -void *fuse_setxattr_finalize(struct fuse_bpf_args *fa, struct dentry *dentry, - const char *name, const void *value, size_t size, - int flags); - -int fuse_removexattr_initialize(struct fuse_bpf_args *fa, - struct fuse_dummy_io *unused, - struct dentry *dentry, const char *name); -int fuse_removexattr_backing(struct fuse_bpf_args *fa, - struct dentry *dentry, const char *name); -void *fuse_removexattr_finalize(struct fuse_bpf_args *fa, - struct dentry *dentry, const char *name); - -struct fuse_read_iter_out { - uint64_t ret; -}; -struct fuse_file_read_iter_io { - struct fuse_read_in fri; - struct fuse_read_iter_out frio; -}; - -int fuse_file_read_iter_initialize( - struct fuse_bpf_args *fa, struct fuse_file_read_iter_io *fri, - struct kiocb *iocb, struct iov_iter *to); -int fuse_file_read_iter_backing(struct fuse_bpf_args *fa, - struct kiocb *iocb, struct iov_iter *to); -void *fuse_file_read_iter_finalize(struct fuse_bpf_args *fa, - struct kiocb *iocb, struct iov_iter *to); - -struct fuse_write_iter_out { - uint64_t ret; -}; -struct fuse_file_write_iter_io { - struct fuse_write_in fwi; - struct fuse_write_out fwo; - struct fuse_write_iter_out fwio; -}; - -int fuse_file_write_iter_initialize( - struct fuse_bpf_args *fa, struct fuse_file_write_iter_io *fwio, - struct kiocb *iocb, struct iov_iter *from); -int fuse_file_write_iter_backing(struct fuse_bpf_args *fa, - struct kiocb *iocb, struct iov_iter *from); -void *fuse_file_write_iter_finalize(struct fuse_bpf_args *fa, - struct kiocb *iocb, struct iov_iter *from); - -long fuse_backing_ioctl(struct file *file, unsigned int command, unsigned long arg, int flags); - -int fuse_file_flock_backing(struct file *file, int cmd, struct file_lock *fl); -ssize_t fuse_backing_mmap(struct file *file, struct vm_area_struct *vma); - -int fuse_file_fallocate_initialize(struct fuse_bpf_args *fa, - struct fuse_fallocate_in *ffi, - struct file *file, int mode, loff_t offset, loff_t length); -int fuse_file_fallocate_backing(struct fuse_bpf_args *fa, - struct file *file, int mode, loff_t offset, loff_t length); -void *fuse_file_fallocate_finalize(struct fuse_bpf_args *fa, - struct file *file, int mode, loff_t offset, loff_t length); - -struct fuse_lookup_io { - struct fuse_entry_out feo; - struct fuse_entry_bpf feb; -}; - -int fuse_handle_backing(struct fuse_entry_bpf *feb, struct inode **backing_inode, - struct path *backing_path); -int fuse_handle_bpf_prog(struct fuse_entry_bpf *feb, struct inode *parent, - struct bpf_prog **bpf); - -int fuse_lookup_initialize(struct fuse_bpf_args *fa, struct fuse_lookup_io *feo, - struct inode *dir, struct dentry *entry, unsigned int flags); -int fuse_lookup_backing(struct fuse_bpf_args *fa, struct inode *dir, - struct dentry *entry, unsigned int flags); -struct dentry *fuse_lookup_finalize(struct fuse_bpf_args *fa, struct inode *dir, - struct dentry *entry, unsigned int flags); -int fuse_revalidate_backing(struct dentry *entry, unsigned int flags); - -int fuse_canonical_path_initialize(struct fuse_bpf_args *fa, - struct fuse_dummy_io *fdi, - const struct path *path, - struct path *canonical_path); -int fuse_canonical_path_backing(struct fuse_bpf_args *fa, const struct path *path, - struct path *canonical_path); -void *fuse_canonical_path_finalize(struct fuse_bpf_args *fa, - const struct path *path, - struct path *canonical_path); - -struct fuse_getattr_io { - struct fuse_getattr_in fgi; - struct fuse_attr_out fao; -}; -int fuse_getattr_initialize(struct fuse_bpf_args *fa, struct fuse_getattr_io *fgio, - const struct dentry *entry, struct kstat *stat, - u32 request_mask, unsigned int flags); -int fuse_getattr_backing(struct fuse_bpf_args *fa, - const struct dentry *entry, struct kstat *stat, - u32 request_mask, unsigned int flags); -void *fuse_getattr_finalize(struct fuse_bpf_args *fa, - const struct dentry *entry, struct kstat *stat, - u32 request_mask, unsigned int flags); - -struct fuse_setattr_io { - struct fuse_setattr_in fsi; - struct fuse_attr_out fao; -}; - -int fuse_setattr_initialize(struct fuse_bpf_args *fa, struct fuse_setattr_io *fsi, - struct dentry *dentry, struct iattr *attr, struct file *file); -int fuse_setattr_backing(struct fuse_bpf_args *fa, - struct dentry *dentry, struct iattr *attr, struct file *file); -void *fuse_setattr_finalize(struct fuse_bpf_args *fa, - struct dentry *dentry, struct iattr *attr, struct file *file); - -int fuse_statfs_initialize(struct fuse_bpf_args *fa, struct fuse_statfs_out *fso, - struct dentry *dentry, struct kstatfs *buf); -int fuse_statfs_backing(struct fuse_bpf_args *fa, - struct dentry *dentry, struct kstatfs *buf); -void *fuse_statfs_finalize(struct fuse_bpf_args *fa, - struct dentry *dentry, struct kstatfs *buf); - -int fuse_get_link_initialize(struct fuse_bpf_args *fa, struct fuse_dummy_io *dummy, - struct inode *inode, struct dentry *dentry, - struct delayed_call *callback, const char **out); -int fuse_get_link_backing(struct fuse_bpf_args *fa, - struct inode *inode, struct dentry *dentry, - struct delayed_call *callback, const char **out); -void *fuse_get_link_finalize(struct fuse_bpf_args *fa, - struct inode *inode, struct dentry *dentry, - struct delayed_call *callback, const char **out); - -int fuse_symlink_initialize( - struct fuse_bpf_args *fa, struct fuse_dummy_io *unused, - struct inode *dir, struct dentry *entry, const char *link, int len); -int fuse_symlink_backing( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, const char *link, int len); -void *fuse_symlink_finalize( - struct fuse_bpf_args *fa, - struct inode *dir, struct dentry *entry, const char *link, int len); - -struct fuse_read_io { - struct fuse_read_in fri; - struct fuse_read_out fro; -}; - -int fuse_readdir_initialize(struct fuse_bpf_args *fa, struct fuse_read_io *frio, - struct file *file, struct dir_context *ctx, - bool *force_again, bool *allow_force, bool is_continued); -int fuse_readdir_backing(struct fuse_bpf_args *fa, - struct file *file, struct dir_context *ctx, - bool *force_again, bool *allow_force, bool is_continued); -void *fuse_readdir_finalize(struct fuse_bpf_args *fa, - struct file *file, struct dir_context *ctx, - bool *force_again, bool *allow_force, bool is_continued); - -int fuse_access_initialize(struct fuse_bpf_args *fa, struct fuse_access_in *fai, - struct inode *inode, int mask); -int fuse_access_backing(struct fuse_bpf_args *fa, struct inode *inode, int mask); -void *fuse_access_finalize(struct fuse_bpf_args *fa, struct inode *inode, int mask); - -/* - * FUSE caches dentries and attributes with separate timeout. The - * time in jiffies until the dentry/attributes are valid is stored in - * dentry->d_fsdata and fuse_inode->i_time respectively. - */ - -/* - * Calculate the time in jiffies until a dentry/attributes are valid - */ -static inline u64 time_to_jiffies(u64 sec, u32 nsec) -{ - if (sec || nsec) { - struct timespec64 ts = { - sec, - min_t(u32, nsec, NSEC_PER_SEC - 1) - }; - - return get_jiffies_64() + timespec64_to_jiffies(&ts); - } else - return 0; -} - -static inline u64 attr_timeout(struct fuse_attr_out *o) -{ - return time_to_jiffies(o->attr_valid, o->attr_valid_nsec); -} - -static inline bool update_mtime(unsigned ivalid, bool trust_local_mtime) -{ - /* Always update if mtime is explicitly set */ - if (ivalid & ATTR_MTIME_SET) - return true; - - /* Or if kernel i_mtime is the official one */ - if (trust_local_mtime) - return true; - - /* If it's an open(O_TRUNC) or an ftruncate(), don't update */ - if ((ivalid & ATTR_SIZE) && (ivalid & (ATTR_OPEN | ATTR_FILE))) - return false; - - /* In all other cases update */ - return true; -} - -void fuse_fillattr(struct inode *inode, struct fuse_attr *attr, - struct kstat *stat); - -static inline void iattr_to_fattr(struct fuse_conn *fc, struct iattr *iattr, - struct fuse_setattr_in *arg, bool trust_local_cmtime) -{ - unsigned ivalid = iattr->ia_valid; - - if (ivalid & ATTR_MODE) - arg->valid |= FATTR_MODE, arg->mode = iattr->ia_mode; - if (ivalid & ATTR_UID) - arg->valid |= FATTR_UID, arg->uid = from_kuid(fc->user_ns, iattr->ia_uid); - if (ivalid & ATTR_GID) - arg->valid |= FATTR_GID, arg->gid = from_kgid(fc->user_ns, iattr->ia_gid); - if (ivalid & ATTR_SIZE) - arg->valid |= FATTR_SIZE, arg->size = iattr->ia_size; - if (ivalid & ATTR_ATIME) { - arg->valid |= FATTR_ATIME; - arg->atime = iattr->ia_atime.tv_sec; - arg->atimensec = iattr->ia_atime.tv_nsec; - if (!(ivalid & ATTR_ATIME_SET)) - arg->valid |= FATTR_ATIME_NOW; - } - if ((ivalid & ATTR_MTIME) && update_mtime(ivalid, trust_local_cmtime)) { - arg->valid |= FATTR_MTIME; - arg->mtime = iattr->ia_mtime.tv_sec; - arg->mtimensec = iattr->ia_mtime.tv_nsec; - if (!(ivalid & ATTR_MTIME_SET) && !trust_local_cmtime) - arg->valid |= FATTR_MTIME_NOW; - } - if ((ivalid & ATTR_CTIME) && trust_local_cmtime) { - arg->valid |= FATTR_CTIME; - arg->ctime = iattr->ia_ctime.tv_sec; - arg->ctimensec = iattr->ia_ctime.tv_nsec; - } -} - -static inline int finalize_attr(struct inode *inode, struct fuse_attr_out *outarg, - u64 attr_version, struct kstat *stat) -{ - int err = 0; - - if (fuse_invalid_attr(&outarg->attr) || - ((inode->i_mode ^ outarg->attr.mode) & S_IFMT)) { - fuse_make_bad(inode); - err = -EIO; - } else { - fuse_change_attributes(inode, &outarg->attr, - attr_timeout(outarg), - attr_version); - if (stat) - fuse_fillattr(inode, &outarg->attr, stat); - } - return err; -} - -static inline void convert_statfs_to_fuse(struct fuse_kstatfs *attr, struct kstatfs *stbuf) -{ - attr->bsize = stbuf->f_bsize; - attr->frsize = stbuf->f_frsize; - attr->blocks = stbuf->f_blocks; - attr->bfree = stbuf->f_bfree; - attr->bavail = stbuf->f_bavail; - attr->files = stbuf->f_files; - attr->ffree = stbuf->f_ffree; - attr->namelen = stbuf->f_namelen; - /* fsid is left zero */ -} - -static inline void convert_fuse_statfs(struct kstatfs *stbuf, struct fuse_kstatfs *attr) -{ - stbuf->f_type = FUSE_SUPER_MAGIC; - stbuf->f_bsize = attr->bsize; - stbuf->f_frsize = attr->frsize; - stbuf->f_blocks = attr->blocks; - stbuf->f_bfree = attr->bfree; - stbuf->f_bavail = attr->bavail; - stbuf->f_files = attr->files; - stbuf->f_ffree = attr->ffree; - stbuf->f_namelen = attr->namelen; - /* fsid is left zero */ -} - -#ifdef CONFIG_FUSE_BPF -struct fuse_err_ret { - void *result; - bool ret; -}; - -int __init fuse_bpf_init(void); -void __exit fuse_bpf_cleanup(void); - -ssize_t fuse_bpf_simple_request(struct fuse_mount *fm, struct fuse_bpf_args *args); - -static inline int fuse_bpf_run(struct bpf_prog *prog, struct fuse_bpf_args *fba) -{ - int ret; - - migrate_disable(); - ret = BPF_PROG_RUN(prog, fba); - migrate_enable(); - return ret; -} - -/* - * expression statement to wrap the backing filter logic - * struct inode *inode: inode with bpf and backing inode - * typedef io: (typically complex) type whose components fuse_args can point to. - * An instance of this type is created locally and passed to initialize - * void initialize(struct fuse_bpf_args *fa, io *in_out, args...): function that sets - * up fa and io based on args - * int backing(struct fuse_bpf_args *fa, args...): function that actually performs - * the backing io operation - * void *finalize(struct fuse_bpf_args *, args...): function that performs any final - * work needed to commit the backing io - */ -#define fuse_bpf_backing(inode, io, initialize, backing, finalize, \ - args...) \ -({ \ - struct fuse_err_ret fer = {0}; \ - int ext_flags; \ - struct fuse_inode *fuse_inode = get_fuse_inode(inode); \ - struct fuse_mount *fm = get_fuse_mount(inode); \ - io feo = {0}; \ - struct fuse_bpf_args fa = {0}, fa_backup = {0}; \ - bool locked; \ - ssize_t res; \ - void *err; \ - int i; \ - bool initialized = false; \ - \ - do { \ - if (!fuse_inode || !fuse_inode->backing_inode) \ - break; \ - \ - err = ERR_PTR(initialize(&fa, &feo, args)); \ - if (err) { \ - fer = (struct fuse_err_ret) { \ - err, \ - true, \ - }; \ - break; \ - } \ - initialized = true; \ - \ - fa_backup = fa; \ - fa.opcode |= FUSE_PREFILTER; \ - for (i = 0; i < fa.in_numargs; ++i) \ - fa.out_args[i] = (struct fuse_bpf_arg) { \ - .size = fa.in_args[i].size, \ - .value = (void *)fa.in_args[i].value, \ - }; \ - fa.out_numargs = fa.in_numargs; \ - \ - ext_flags = fuse_inode->bpf ? \ - fuse_bpf_run(fuse_inode->bpf, &fa) : \ - FUSE_BPF_BACKING; \ - if (ext_flags < 0) { \ - fer = (struct fuse_err_ret) { \ - ERR_PTR(ext_flags), \ - true, \ - }; \ - break; \ - } \ - \ - if (ext_flags & FUSE_BPF_USER_FILTER) { \ - locked = fuse_lock_inode(inode); \ - res = fuse_bpf_simple_request(fm, &fa); \ - fuse_unlock_inode(inode, locked); \ - if (res < 0) { \ - fer = (struct fuse_err_ret) { \ - ERR_PTR(res), \ - true, \ - }; \ - break; \ - } \ - } \ - \ - if (!(ext_flags & FUSE_BPF_BACKING)) \ - break; \ - \ - fa.opcode &= ~FUSE_PREFILTER; \ - for (i = 0; i < fa.in_numargs; ++i) \ - fa.in_args[i] = (struct fuse_bpf_in_arg) { \ - .size = fa.out_args[i].size, \ - .value = fa.out_args[i].value, \ - }; \ - for (i = 0; i < fa_backup.out_numargs; ++i) \ - fa.out_args[i] = (struct fuse_bpf_arg) { \ - .size = fa_backup.out_args[i].size, \ - .value = fa_backup.out_args[i].value, \ - }; \ - fa.out_numargs = fa_backup.out_numargs; \ - \ - fer = (struct fuse_err_ret) { \ - ERR_PTR(backing(&fa, args)), \ - true, \ - }; \ - if (IS_ERR(fer.result)) \ - fa.error_in = PTR_ERR(fer.result); \ - if (!(ext_flags & FUSE_BPF_POST_FILTER)) \ - break; \ - \ - fa.opcode |= FUSE_POSTFILTER; \ - for (i = 0; i < fa.out_numargs; ++i) \ - fa.in_args[fa.in_numargs++] = \ - (struct fuse_bpf_in_arg) { \ - .size = fa.out_args[i].size, \ - .value = fa.out_args[i].value, \ - }; \ - ext_flags = fuse_bpf_run(fuse_inode->bpf, &fa); \ - if (ext_flags < 0) { \ - fer = (struct fuse_err_ret) { \ - ERR_PTR(ext_flags), \ - true, \ - }; \ - break; \ - } \ - if (!(ext_flags & FUSE_BPF_USER_FILTER)) \ - break; \ - \ - fa.out_args[0].size = fa_backup.out_args[0].size; \ - fa.out_args[1].size = fa_backup.out_args[1].size; \ - fa.out_numargs = fa_backup.out_numargs; \ - locked = fuse_lock_inode(inode); \ - res = fuse_bpf_simple_request(fm, &fa); \ - fuse_unlock_inode(inode, locked); \ - if (res < 0) { \ - fer.result = ERR_PTR(res); \ - break; \ - } \ - } while (false); \ - \ - if (initialized && fer.ret) { \ - err = finalize(&fa, args); \ - if (err) \ - fer.result = err; \ - } \ - \ - fer; \ -}) -#endif /* CONFIG_FUSE_BPF */ - #endif /* _FS_FUSE_I_H */ diff --git a/fs/fuse/inode.c b/fs/fuse/inode.c index e37fba257c8b..b32c5c84004c 100644 --- a/fs/fuse/inode.c +++ b/fs/fuse/inode.c @@ -50,6 +50,8 @@ MODULE_PARM_DESC(max_user_congthresh, "Global limit for the maximum congestion threshold an " "unprivileged user can set"); +#define FUSE_SUPER_MAGIC 0x65735546 + #define FUSE_DEFAULT_BLKSIZE 512 /** Maximum number of outstanding background requests */ @@ -77,32 +79,20 @@ static struct inode *fuse_alloc_inode(struct super_block *sb) fi->i_time = 0; fi->inval_mask = 0; -#ifdef CONFIG_FUSE_BPF - fi->backing_inode = NULL; - fi->bpf = NULL; -#endif fi->nodeid = 0; fi->nlookup = 0; fi->attr_version = 0; fi->orig_ino = 0; fi->state = 0; mutex_init(&fi->mutex); - init_rwsem(&fi->i_mmap_sem); spin_lock_init(&fi->lock); fi->forget = fuse_alloc_forget(); - if (!fi->forget) - goto out_free; - - if (IS_ENABLED(CONFIG_FUSE_DAX) && !fuse_dax_inode_alloc(sb, fi)) - goto out_free_forget; + if (!fi->forget) { + kmem_cache_free(fuse_inode_cachep, fi); + return NULL; + } return &fi->inode; - -out_free_forget: - kfree(fi->forget); -out_free: - kmem_cache_free(fuse_inode_cachep, fi); - return NULL; } static void fuse_free_inode(struct inode *inode) @@ -111,13 +101,6 @@ static void fuse_free_inode(struct inode *inode) mutex_destroy(&fi->mutex); kfree(fi->forget); -#ifdef CONFIG_FUSE_DAX - kfree(fi->dax); -#endif -#ifdef CONFIG_FUSE_BPF - if (fi->bpf) - bpf_prog_put(fi->bpf); -#endif kmem_cache_free(fuse_inode_cachep, fi); } @@ -125,21 +108,12 @@ static void fuse_evict_inode(struct inode *inode) { struct fuse_inode *fi = get_fuse_inode(inode); - /* Will write inode on close/munmap and in all other dirtiers */ - WARN_ON(inode->i_state & I_DIRTY_INODE); - truncate_inode_pages_final(&inode->i_data); clear_inode(inode); if (inode->i_sb->s_flags & SB_ACTIVE) { struct fuse_conn *fc = get_fuse_conn(inode); - - if (FUSE_IS_DAX(inode)) - fuse_dax_inode_cleanup(inode); - if (fi->nlookup) { - fuse_queue_forget(fc, fi->forget, fi->nodeid, - fi->nlookup); - fi->forget = NULL; - } + fuse_queue_forget(fc, fi->forget, fi->nodeid, fi->nlookup); + fi->forget = NULL; } if (S_ISREG(inode->i_mode) && !fuse_is_bad(inode)) { WARN_ON(!list_empty(&fi->write_files)); @@ -147,21 +121,12 @@ static void fuse_evict_inode(struct inode *inode) } } -#ifdef CONFIG_FUSE_BPF -static void fuse_destroy_inode(struct inode *inode) +static int fuse_reconfigure(struct fs_context *fc) { - struct fuse_inode *fi = get_fuse_inode(inode); - - iput(fi->backing_inode); -} -#endif - -static int fuse_reconfigure(struct fs_context *fsc) -{ - struct super_block *sb = fsc->root->d_sb; + struct super_block *sb = fc->root->d_sb; sync_filesystem(sb); - if (fsc->sb_flags & SB_MANDLOCK) + if (fc->sb_flags & SB_MANDLOCK) return -EINVAL; return 0; @@ -179,28 +144,6 @@ static ino_t fuse_squash_ino(u64 ino64) return ino; } -static void fuse_fill_attr_from_inode(struct fuse_attr *attr, - const struct inode *inode) -{ - *attr = (struct fuse_attr){ - .ino = inode->i_ino, - .size = inode->i_size, - .blocks = inode->i_blocks, - .atime = inode->i_atime.tv_sec, - .mtime = inode->i_mtime.tv_sec, - .ctime = inode->i_ctime.tv_sec, - .atimensec = inode->i_atime.tv_nsec, - .mtimensec = inode->i_mtime.tv_nsec, - .ctimensec = inode->i_ctime.tv_nsec, - .mode = inode->i_mode, - .nlink = inode->i_nlink, - .uid = inode->i_uid.val, - .gid = inode->i_gid.val, - .rdev = inode->i_rdev, - .blksize = 1u << inode->i_blkbits, - }; -} - void fuse_change_attributes_common(struct inode *inode, struct fuse_attr *attr, u64 attr_valid) { @@ -325,104 +268,28 @@ static void fuse_init_inode(struct inode *inode, struct fuse_attr *attr) else if (S_ISCHR(inode->i_mode) || S_ISBLK(inode->i_mode) || S_ISFIFO(inode->i_mode) || S_ISSOCK(inode->i_mode)) { fuse_init_common(inode); - init_special_inode(inode, inode->i_mode, attr->rdev); + init_special_inode(inode, inode->i_mode, + new_decode_dev(attr->rdev)); } else BUG(); } -struct fuse_inode_identifier { - u64 nodeid; - struct inode *backing_inode; -}; - -static int fuse_inode_eq(struct inode *inode, void *_nodeidp) +int fuse_inode_eq(struct inode *inode, void *_nodeidp) { - struct fuse_inode_identifier *fii = - (struct fuse_inode_identifier *) _nodeidp; - struct fuse_inode *fi = get_fuse_inode(inode); - - return fii->nodeid == fi->nodeid; -} - -static int fuse_inode_backing_eq(struct inode *inode, void *_nodeidp) -{ - struct fuse_inode_identifier *fii = - (struct fuse_inode_identifier *) _nodeidp; - struct fuse_inode *fi = get_fuse_inode(inode); - - return fii->nodeid == fi->nodeid -#ifdef CONFIG_FUSE_BPF - && fii->backing_inode == fi->backing_inode -#endif - ; + u64 nodeid = *(u64 *) _nodeidp; + if (get_node_id(inode) == nodeid) + return 1; + else + return 0; } static int fuse_inode_set(struct inode *inode, void *_nodeidp) { - struct fuse_inode_identifier *fii = - (struct fuse_inode_identifier *) _nodeidp; - struct fuse_inode *fi = get_fuse_inode(inode); - - fi->nodeid = fii->nodeid; - + u64 nodeid = *(u64 *) _nodeidp; + get_fuse_inode(inode)->nodeid = nodeid; return 0; } -static int fuse_inode_backing_set(struct inode *inode, void *_nodeidp) -{ - struct fuse_inode_identifier *fii = - (struct fuse_inode_identifier *) _nodeidp; - struct fuse_inode *fi = get_fuse_inode(inode); - - fi->nodeid = fii->nodeid; -#ifdef CONFIG_FUSE_BPF - fi->backing_inode = fii->backing_inode; - if (fi->backing_inode) - ihold(fi->backing_inode); -#endif - - return 0; -} - -struct inode *fuse_iget_backing(struct super_block *sb, u64 nodeid, - struct inode *backing_inode) -{ - struct inode *inode; - struct fuse_inode *fi; - struct fuse_conn *fc = get_fuse_conn_super(sb); - struct fuse_inode_identifier fii = { - .nodeid = nodeid, - .backing_inode = backing_inode, - }; - struct fuse_attr attr; - unsigned long hash = (unsigned long) backing_inode; - - if (nodeid) - hash = nodeid; - - fuse_fill_attr_from_inode(&attr, backing_inode); - inode = iget5_locked(sb, hash, fuse_inode_backing_eq, - fuse_inode_backing_set, &fii); - if (!inode) - return NULL; - - if ((inode->i_state & I_NEW)) { - inode->i_flags |= S_NOATIME; - if (!fc->writeback_cache) - inode->i_flags |= S_NOCMTIME; - fuse_init_common(inode); - unlock_new_inode(inode); - } - - fi = get_fuse_inode(inode); - fuse_init_inode(inode, &attr); - spin_lock(&fi->lock); - fi->nlookup++; - spin_unlock(&fi->lock); - - return inode; -} - struct inode *fuse_iget(struct super_block *sb, u64 nodeid, int generation, struct fuse_attr *attr, u64 attr_valid, u64 attr_version) @@ -430,31 +297,9 @@ struct inode *fuse_iget(struct super_block *sb, u64 nodeid, struct inode *inode; struct fuse_inode *fi; struct fuse_conn *fc = get_fuse_conn_super(sb); - struct fuse_inode_identifier fii = { - .nodeid = nodeid, - }; - /* - * Auto mount points get their node id from the submount root, which is - * not a unique identifier within this filesystem. - * - * To avoid conflicts, do not place submount points into the inode hash - * table. - */ - if (fc->auto_submounts && (attr->flags & FUSE_ATTR_SUBMOUNT) && - S_ISDIR(attr->mode)) { - inode = new_inode(sb); - if (!inode) - return NULL; - - fuse_init_inode(inode, attr); - get_fuse_inode(inode)->nodeid = nodeid; - inode->i_flags |= S_AUTOMOUNT; - goto done; - } - -retry: - inode = iget5_locked(sb, nodeid, fuse_inode_eq, fuse_inode_set, &fii); + retry: + inode = iget5_locked(sb, nodeid, fuse_inode_eq, fuse_inode_set, &nodeid); if (!inode) return NULL; @@ -465,8 +310,8 @@ retry: inode->i_generation = generation; fuse_init_inode(inode, attr); unlock_new_inode(inode); - } else if (fuse_stale_inode(inode, generation, attr)) { - /* nodeid was reused, any I/O on the old inode should fail */ + } else if ((inode->i_mode ^ attr->mode) & S_IFMT) { + /* Inode has changed type, any I/O on the old should fail */ fuse_make_bad(inode); if (inode != d_inode(sb->s_root)) { remove_inode_hash(inode); @@ -474,7 +319,7 @@ retry: goto retry; } } -done: + fi = get_fuse_inode(inode); spin_lock(&fi->lock); fi->nlookup++; @@ -484,40 +329,16 @@ done: return inode; } -struct inode *fuse_ilookup(struct fuse_conn *fc, u64 nodeid, - struct fuse_mount **fm) -{ - struct fuse_mount *fm_iter; - struct inode *inode; - struct fuse_inode_identifier fii = { - .nodeid = nodeid, - }; - - WARN_ON(!rwsem_is_locked(&fc->killsb)); - list_for_each_entry(fm_iter, &fc->mounts, fc_entry) { - if (!fm_iter->sb) - continue; - - inode = ilookup5(fm_iter->sb, nodeid, fuse_inode_eq, &fii); - if (inode) { - if (fm) - *fm = fm_iter; - return inode; - } - } - - return NULL; -} - -int fuse_reverse_inval_inode(struct fuse_conn *fc, u64 nodeid, +int fuse_reverse_inval_inode(struct super_block *sb, u64 nodeid, loff_t offset, loff_t len) { + struct fuse_conn *fc = get_fuse_conn_super(sb); struct fuse_inode *fi; struct inode *inode; pgoff_t pg_start; pgoff_t pg_end; - inode = fuse_ilookup(fc, nodeid, NULL); + inode = ilookup5(sb, nodeid, fuse_inode_eq, &nodeid); if (!inode) return -ENOENT; @@ -567,50 +388,57 @@ static void fuse_umount_begin(struct super_block *sb) fuse_abort_conn(fc); } -static void fuse_send_destroy(struct fuse_mount *fm) +static void fuse_send_destroy(struct fuse_conn *fc) { - if (fm->fc->conn_init) { + if (fc->conn_init) { FUSE_ARGS(args); args.opcode = FUSE_DESTROY; args.force = true; args.nocreds = true; - fuse_simple_request(fm, &args); + fuse_simple_request(fc, &args); } } static void fuse_put_super(struct super_block *sb) { - struct fuse_mount *fm = get_fuse_mount_super(sb); + struct fuse_conn *fc = get_fuse_conn_super(sb); - fuse_mount_put(fm); + mutex_lock(&fuse_mutex); + list_del(&fc->entry); + fuse_ctl_remove_conn(fc); + mutex_unlock(&fuse_mutex); + + fuse_conn_put(fc); +} + +static void convert_fuse_statfs(struct kstatfs *stbuf, struct fuse_kstatfs *attr) +{ + stbuf->f_type = FUSE_SUPER_MAGIC; + stbuf->f_bsize = attr->bsize; + stbuf->f_frsize = attr->frsize; + stbuf->f_blocks = attr->blocks; + stbuf->f_bfree = attr->bfree; + stbuf->f_bavail = attr->bavail; + stbuf->f_files = attr->files; + stbuf->f_ffree = attr->ffree; + stbuf->f_namelen = attr->namelen; + /* fsid is left zero */ } static int fuse_statfs(struct dentry *dentry, struct kstatfs *buf) { struct super_block *sb = dentry->d_sb; - struct fuse_mount *fm = get_fuse_mount_super(sb); + struct fuse_conn *fc = get_fuse_conn_super(sb); FUSE_ARGS(args); struct fuse_statfs_out outarg; int err; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; -#endif - if (!fuse_allow_current_process(fm->fc)) { + if (!fuse_allow_current_process(fc)) { buf->f_type = FUSE_SUPER_MAGIC; return 0; } -#ifdef CONFIG_FUSE_BPF - fer = fuse_bpf_backing(dentry->d_inode, struct fuse_statfs_out, - fuse_statfs_initialize, fuse_statfs_backing, - fuse_statfs_finalize, - dentry, buf); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - memset(&outarg, 0, sizeof(outarg)); args.in_numargs = 0; args.opcode = FUSE_STATFS; @@ -618,7 +446,7 @@ static int fuse_statfs(struct dentry *dentry, struct kstatfs *buf) args.out_numargs = 1; args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (!err) convert_fuse_statfs(buf, &outarg.st); return err; @@ -635,9 +463,6 @@ enum { OPT_ALLOW_OTHER, OPT_MAX_READ, OPT_BLKSIZE, - OPT_ROOT_BPF, - OPT_ROOT_DIR, - OPT_NO_DAEMON, OPT_ERR }; @@ -652,9 +477,6 @@ static const struct fs_parameter_spec fuse_param_specs[] = { fsparam_u32 ("max_read", OPT_MAX_READ), fsparam_u32 ("blksize", OPT_BLKSIZE), fsparam_string ("subtype", OPT_SUBTYPE), - fsparam_u32 ("root_bpf", OPT_ROOT_BPF), - fsparam_u32 ("root_dir", OPT_ROOT_DIR), - fsparam_flag ("no_daemon", OPT_NO_DAEMON), {} }; @@ -663,90 +485,70 @@ static const struct fs_parameter_description fuse_fs_parameters = { .specs = fuse_param_specs, }; -static int fuse_parse_param(struct fs_context *fsc, struct fs_parameter *param) +static int fuse_parse_param(struct fs_context *fc, struct fs_parameter *param) { struct fs_parse_result result; - struct fuse_fs_context *ctx = fsc->fs_private; + struct fuse_fs_context *ctx = fc->fs_private; int opt; - kuid_t kuid; - kgid_t kgid; - if (fsc->purpose == FS_CONTEXT_FOR_RECONFIGURE) { - /* - * Ignore options coming from mount(MS_REMOUNT) for backward - * compatibility. - */ - if (fsc->oldapi) - return 0; + /* + * Ignore options coming from mount(MS_REMOUNT) for backward + * compatibility. + */ + if (fc->purpose == FS_CONTEXT_FOR_RECONFIGURE) + return 0; - return invalf(fsc, "No changes allowed in reconfigure"); - } - - opt = fs_parse(fsc, &fuse_fs_parameters, param, &result); + opt = fs_parse(fc, &fuse_fs_parameters, param, &result); if (opt < 0) return opt; switch (opt) { case OPT_SOURCE: - if (fsc->source) - return invalf(fsc, "Multiple sources specified"); - fsc->source = param->string; + if (fc->source) + return invalf(fc, "fuse: Multiple sources specified"); + fc->source = param->string; param->string = NULL; break; case OPT_SUBTYPE: if (ctx->subtype) - return invalf(fsc, "Multiple subtypes specified"); + return invalf(fc, "fuse: Multiple subtypes specified"); ctx->subtype = param->string; param->string = NULL; return 0; case OPT_FD: ctx->fd = result.uint_32; - ctx->fd_present = true; + ctx->fd_present = 1; break; case OPT_ROOTMODE: if (!fuse_valid_type(result.uint_32)) - return invalf(fsc, "Invalid rootmode"); + return invalf(fc, "fuse: Invalid rootmode"); ctx->rootmode = result.uint_32; - ctx->rootmode_present = true; + ctx->rootmode_present = 1; break; case OPT_USER_ID: - kuid = make_kuid(fsc->user_ns, result.uint_32); - if (!uid_valid(kuid)) - return invalf(fsc, "Invalid user_id"); - /* - * The requested uid must be representable in the - * filesystem's idmapping. - */ - if (!kuid_has_mapping(fsc->user_ns, kuid)) - return invalf(fsc, "Invalid user_id"); - ctx->user_id = kuid; - ctx->user_id_present = true; + ctx->user_id = make_kuid(fc->user_ns, result.uint_32); + if (!uid_valid(ctx->user_id)) + return invalf(fc, "fuse: Invalid user_id"); + ctx->user_id_present = 1; break; case OPT_GROUP_ID: - kgid = make_kgid(fsc->user_ns, result.uint_32);; - if (!gid_valid(kgid)) - return invalf(fsc, "Invalid group_id"); - /* - * The requested gid must be representable in the - * filesystem's idmapping. - */ - if (!kgid_has_mapping(fsc->user_ns, kgid)) - return invalf(fsc, "Invalid group_id"); - ctx->group_id = kgid; - ctx->group_id_present = true; + ctx->group_id = make_kgid(fc->user_ns, result.uint_32); + if (!gid_valid(ctx->group_id)) + return invalf(fc, "fuse: Invalid group_id"); + ctx->group_id_present = 1; break; case OPT_DEFAULT_PERMISSIONS: - ctx->default_permissions = true; + ctx->default_permissions = 1; break; case OPT_ALLOW_OTHER: - ctx->allow_other = true; + ctx->allow_other = 1; break; case OPT_MAX_READ: @@ -755,30 +557,10 @@ static int fuse_parse_param(struct fs_context *fsc, struct fs_parameter *param) case OPT_BLKSIZE: if (!ctx->is_bdev) - return invalf(fsc, "blksize only supported for fuseblk"); + return invalf(fc, "fuse: blksize only supported for fuseblk"); ctx->blksize = result.uint_32; break; - case OPT_ROOT_BPF: - ctx->root_bpf = bpf_prog_get_type_dev(result.uint_32, - BPF_PROG_TYPE_FUSE, false); - if (IS_ERR(ctx->root_bpf)) { - ctx->root_bpf = NULL; - return invalf(fsc, "Unable to open bpf program"); - } - break; - - case OPT_ROOT_DIR: - ctx->root_dir = fget(result.uint_32); - if (!ctx->root_dir) - return invalf(fsc, "Unable to open root directory"); - break; - - case OPT_NO_DAEMON: - ctx->no_daemon = true; - ctx->fd_present = true; - break; - default: return -EINVAL; } @@ -786,15 +568,11 @@ static int fuse_parse_param(struct fs_context *fsc, struct fs_parameter *param) return 0; } -static void fuse_free_fsc(struct fs_context *fsc) +static void fuse_free_fc(struct fs_context *fc) { - struct fuse_fs_context *ctx = fsc->fs_private; + struct fuse_fs_context *ctx = fc->fs_private; if (ctx) { - if (ctx->root_dir) - fput(ctx->root_dir); - if (ctx->root_bpf) - bpf_prog_put(ctx->root_bpf); kfree(ctx->subtype); kfree(ctx); } @@ -805,25 +583,19 @@ static int fuse_show_options(struct seq_file *m, struct dentry *root) struct super_block *sb = root->d_sb; struct fuse_conn *fc = get_fuse_conn_super(sb); - if (fc->legacy_opts_show) { - seq_printf(m, ",user_id=%u", - from_kuid_munged(fc->user_ns, fc->user_id)); - seq_printf(m, ",group_id=%u", - from_kgid_munged(fc->user_ns, fc->group_id)); - if (fc->default_permissions) - seq_puts(m, ",default_permissions"); - if (fc->allow_other) - seq_puts(m, ",allow_other"); - if (fc->max_read != ~0) - seq_printf(m, ",max_read=%u", fc->max_read); - if (sb->s_bdev && sb->s_blocksize != FUSE_DEFAULT_BLKSIZE) - seq_printf(m, ",blksize=%lu", sb->s_blocksize); - } -#ifdef CONFIG_FUSE_DAX - if (fc->dax) - seq_puts(m, ",dax"); -#endif + if (fc->no_mount_options) + return 0; + seq_printf(m, ",user_id=%u", from_kuid_munged(fc->user_ns, fc->user_id)); + seq_printf(m, ",group_id=%u", from_kgid_munged(fc->user_ns, fc->group_id)); + if (fc->default_permissions) + seq_puts(m, ",default_permissions"); + if (fc->allow_other) + seq_puts(m, ",allow_other"); + if (fc->max_read != ~0) + seq_printf(m, ",max_read=%u", fc->max_read); + if (sb->s_bdev && sb->s_blocksize != FUSE_DEFAULT_BLKSIZE) + seq_printf(m, ",blksize=%lu", sb->s_blocksize); return 0; } @@ -853,8 +625,7 @@ static void fuse_pqueue_init(struct fuse_pqueue *fpq) fpq->connected = 1; } -void fuse_conn_init(struct fuse_conn *fc, struct fuse_mount *fm, - struct user_namespace *user_ns, +void fuse_conn_init(struct fuse_conn *fc, struct user_namespace *user_ns, const struct fuse_iqueue_ops *fiq_ops, void *fiq_priv) { memset(fc, 0, sizeof(*fc)); @@ -883,12 +654,6 @@ void fuse_conn_init(struct fuse_conn *fc, struct fuse_mount *fm, fc->pid_ns = get_pid_ns(task_active_pid_ns(current)); fc->user_ns = get_user_ns(user_ns); fc->max_pages = FUSE_DEFAULT_MAX_PAGES_PER_REQ; - fc->max_pages_limit = FUSE_MAX_MAX_PAGES; - - INIT_LIST_HEAD(&fc->mounts); - list_add(&fm->fc_entry, &fc->mounts); - fm->fc = fc; - refcount_set(&fm->count, 1); } EXPORT_SYMBOL_GPL(fuse_conn_init); @@ -897,8 +662,6 @@ void fuse_conn_put(struct fuse_conn *fc) if (refcount_dec_and_test(&fc->count)) { struct fuse_iqueue *fiq = &fc->iq; - if (IS_ENABLED(CONFIG_FUSE_DAX)) - fuse_dax_conn_free(fc); if (fiq->ops->release) fiq->ops->release(fiq); put_pid_ns(fc->pid_ns); @@ -915,51 +678,15 @@ struct fuse_conn *fuse_conn_get(struct fuse_conn *fc) } EXPORT_SYMBOL_GPL(fuse_conn_get); -void fuse_mount_put(struct fuse_mount *fm) -{ - if (refcount_dec_and_test(&fm->count)) { - if (fm->fc) - fuse_conn_put(fm->fc); - kfree(fm); - } -} -EXPORT_SYMBOL_GPL(fuse_mount_put); - -struct fuse_mount *fuse_mount_get(struct fuse_mount *fm) -{ - refcount_inc(&fm->count); - return fm; -} -EXPORT_SYMBOL_GPL(fuse_mount_get); - -static struct inode *fuse_get_root_inode(struct super_block *sb, - unsigned int mode, - struct bpf_prog *root_bpf, - struct file *backing_fd) +static struct inode *fuse_get_root_inode(struct super_block *sb, unsigned mode) { struct fuse_attr attr; - struct inode *inode; - memset(&attr, 0, sizeof(attr)); + attr.mode = mode; attr.ino = FUSE_ROOT_ID; attr.nlink = 1; - inode = fuse_iget(sb, 1, 0, &attr, 0, 0); - if (!inode) - return NULL; - -#ifdef CONFIG_FUSE_BPF - get_fuse_inode(inode)->bpf = root_bpf; - if (root_bpf) - bpf_prog_inc(root_bpf); - - if (backing_fd) { - get_fuse_inode(inode)->backing_inode = backing_fd->f_inode; - ihold(backing_fd->f_inode); - } -#endif - - return inode; + return fuse_iget(sb, 1, 0, &attr, 0, 0); } struct fuse_inode_handle { @@ -974,14 +701,11 @@ static struct dentry *fuse_get_dentry(struct super_block *sb, struct inode *inode; struct dentry *entry; int err = -ESTALE; - struct fuse_inode_identifier fii = { - .nodeid = handle->nodeid, - }; if (handle->nodeid == 0) goto out_err; - inode = ilookup5(sb, handle->nodeid, fuse_inode_eq, &fii); + inode = ilookup5(sb, handle->nodeid, fuse_inode_eq, &handle->nodeid); if (!inode) { struct fuse_entry_out outarg; const struct qstr name = QSTR_INIT(".", 1); @@ -990,7 +714,7 @@ static struct dentry *fuse_get_dentry(struct super_block *sb, goto out_err; err = fuse_lookup_name(sb, handle->nodeid, &name, &outarg, - NULL, &inode); + &inode); if (err && err != -ENOENT) goto out_err; if (err || !inode) { @@ -1091,7 +815,7 @@ static struct dentry *fuse_get_parent(struct dentry *child) return ERR_PTR(-ESTALE); err = fuse_lookup_name(child_inode->i_sb, get_node_id(child_inode), - &name, &outarg, NULL, &inode); + &name, &outarg, &inode); if (err) { if (err == -ENOENT) return ERR_PTR(-ESTALE); @@ -1114,9 +838,6 @@ static const struct export_operations fuse_export_operations = { static const struct super_operations fuse_super_operations = { .alloc_inode = fuse_alloc_inode, -#ifdef CONFIG_FUSE_BPF - .destroy_inode = fuse_destroy_inode, -#endif .free_inode = fuse_free_inode, .evict_inode = fuse_evict_inode, .write_inode = fuse_write_inode, @@ -1186,16 +907,14 @@ struct fuse_init_args { struct fuse_init_out out; }; -static void process_init_reply(struct fuse_mount *fm, struct fuse_args *args, +static void process_init_reply(struct fuse_conn *fc, struct fuse_args *args, int error) { - struct fuse_conn *fc = fm->fc; struct fuse_init_args *ia = container_of(args, typeof(*ia), args); struct fuse_init_out *arg = &ia->out; - bool ok = true; if (error || arg->major != FUSE_KERNEL_VERSION) - ok = false; + fc->conn_error = 1; else { unsigned long ra_pages; @@ -1243,11 +962,11 @@ static void process_init_reply(struct fuse_mount *fm, struct fuse_args *args, if (arg->flags & FUSE_HANDLE_KILLPRIV) fc->handle_killpriv = 1; if (arg->time_gran && arg->time_gran <= 1000000000) - fm->sb->s_time_gran = arg->time_gran; + fc->sb->s_time_gran = arg->time_gran; if ((arg->flags & FUSE_POSIX_ACL)) { fc->default_permissions = 1; fc->posix_acl = 1; - fm->sb->s_xattr = fuse_acl_xattr_handlers; + fc->sb->s_xattr = fuse_acl_xattr_handlers; } if (arg->flags & FUSE_CACHE_SYMLINKS) fc->cache_symlinks = 1; @@ -1255,18 +974,13 @@ static void process_init_reply(struct fuse_mount *fm, struct fuse_args *args, fc->abort_err = 1; if (arg->flags & FUSE_MAX_PAGES) { fc->max_pages = - min_t(unsigned int, fc->max_pages_limit, + min_t(unsigned int, FUSE_MAX_MAX_PAGES, max_t(unsigned int, arg->max_pages, 1)); } - if (IS_ENABLED(CONFIG_FUSE_DAX) && - arg->flags & FUSE_MAP_ALIGNMENT && - !fuse_dax_check_alignment(fc, arg->map_alignment)) { - ok = false; - } if (arg->flags & FUSE_PASSTHROUGH) { fc->passthrough = 1; /* Prevent further stacking */ - fm->sb->s_stack_depth = + fc->sb->s_stack_depth = FILESYSTEM_MAX_STACK_DEPTH; } } else { @@ -1275,8 +989,8 @@ static void process_init_reply(struct fuse_mount *fm, struct fuse_args *args, fc->no_flock = 1; } - fm->sb->s_bdi->ra_pages = - min(fm->sb->s_bdi->ra_pages, ra_pages); + fc->sb->s_bdi->ra_pages = + min(fc->sb->s_bdi->ra_pages, ra_pages); fc->minor = arg->minor; fc->max_write = arg->minor < 5 ? 4096 : arg->max_write; fc->max_write = max_t(unsigned, 4096, fc->max_write); @@ -1284,16 +998,11 @@ static void process_init_reply(struct fuse_mount *fm, struct fuse_args *args, } kfree(ia); - if (!ok) { - fc->conn_init = 0; - fc->conn_error = 1; - } - fuse_set_initialized(fc); wake_up_all(&fc->blocked_waitq); } -void fuse_send_init(struct fuse_mount *fm) +void fuse_send_init(struct fuse_conn *fc) { struct fuse_init_args *ia; @@ -1301,7 +1010,7 @@ void fuse_send_init(struct fuse_mount *fm) ia->in.major = FUSE_KERNEL_VERSION; ia->in.minor = FUSE_KERNEL_MINOR_VERSION; - ia->in.max_readahead = fm->sb->s_bdi->ra_pages * PAGE_SIZE; + ia->in.max_readahead = fc->sb->s_bdi->ra_pages * PAGE_SIZE; ia->in.flags |= FUSE_ASYNC_READ | FUSE_POSIX_LOCKS | FUSE_ATOMIC_O_TRUNC | FUSE_EXPORT_SUPPORT | FUSE_BIG_WRITES | FUSE_DONT_MASK | @@ -1313,13 +1022,6 @@ void fuse_send_init(struct fuse_mount *fm) FUSE_ABORT_ERROR | FUSE_MAX_PAGES | FUSE_CACHE_SYMLINKS | FUSE_NO_OPENDIR_SUPPORT | FUSE_EXPLICIT_INVAL_DATA | FUSE_PASSTHROUGH; -#ifdef CONFIG_FUSE_DAX - if (fm->fc->dax) - ia->in.flags |= FUSE_MAP_ALIGNMENT; -#endif - if (fm->fc->auto_submounts) - ia->in.flags |= FUSE_SUBMOUNTS; - ia->args.opcode = FUSE_INIT; ia->args.in_numargs = 1; ia->args.in_args[0].size = sizeof(ia->in); @@ -1328,15 +1030,15 @@ void fuse_send_init(struct fuse_mount *fm) /* Variable length argument used for backward compatibility with interface version < 7.5. Rest of init_out is zeroed by do_get_request(), so a short reply is not a problem */ - ia->args.out_argvar = true; + ia->args.out_argvar = 1; ia->args.out_args[0].size = sizeof(ia->out); ia->args.out_args[0].value = &ia->out; ia->args.force = true; ia->args.nocreds = true; ia->args.end = process_init_reply; - if (unlikely(fm->fc->no_daemon) || fuse_simple_background(fm, &ia->args, GFP_KERNEL) != 0) - process_init_reply(fm, &ia->args, -ENOTCONN); + if (fuse_simple_background(fc, &ia->args, GFP_KERNEL) != 0) + process_init_reply(fc, &ia->args, -ENOTCONN); } EXPORT_SYMBOL_GPL(fuse_send_init); @@ -1378,6 +1080,7 @@ static int fuse_bdi_init(struct fuse_conn *fc, struct super_block *sb) if (err) return err; + sb->s_bdi->ra_pages = VM_READAHEAD_PAGES; /* fuse does it's own writeback accounting */ sb->s_bdi->capabilities = BDI_CAP_NO_ACCT_WB | BDI_CAP_STRICTLIMIT; @@ -1458,70 +1161,10 @@ void fuse_dev_free(struct fuse_dev *fud) } EXPORT_SYMBOL_GPL(fuse_dev_free); -static void fuse_sb_defaults(struct super_block *sb) -{ - sb->s_magic = FUSE_SUPER_MAGIC; - sb->s_op = &fuse_super_operations; - sb->s_xattr = fuse_xattr_handlers; - sb->s_maxbytes = MAX_LFS_FILESIZE; - sb->s_time_gran = 1; - sb->s_export_op = &fuse_export_operations; - sb->s_iflags |= SB_I_IMA_UNVERIFIABLE_SIGNATURE; - if (sb->s_user_ns != &init_user_ns) - sb->s_iflags |= SB_I_UNTRUSTED_MOUNTER; - sb->s_flags &= ~(SB_NOSEC | SB_I_VERSION); - - /* - * If we are not in the initial user namespace posix - * acls must be translated. - */ - if (sb->s_user_ns != &init_user_ns) - sb->s_xattr = fuse_no_acl_xattr_handlers; -} - -int fuse_fill_super_submount(struct super_block *sb, - struct fuse_inode *parent_fi) -{ - struct fuse_mount *fm = get_fuse_mount_super(sb); - struct super_block *parent_sb = parent_fi->inode.i_sb; - struct fuse_attr root_attr; - struct inode *root; - - fuse_sb_defaults(sb); - fm->sb = sb; - - WARN_ON(sb->s_bdi != &noop_backing_dev_info); - sb->s_bdi = bdi_get(parent_sb->s_bdi); - - sb->s_xattr = parent_sb->s_xattr; - sb->s_time_gran = parent_sb->s_time_gran; - sb->s_blocksize = parent_sb->s_blocksize; - sb->s_blocksize_bits = parent_sb->s_blocksize_bits; - sb->s_subtype = kstrdup(parent_sb->s_subtype, GFP_KERNEL); - if (parent_sb->s_subtype && !sb->s_subtype) - return -ENOMEM; - - fuse_fill_attr_from_inode(&root_attr, &parent_fi->inode); - root = fuse_iget(sb, parent_fi->nodeid, 0, &root_attr, 0, 0); - /* - * This inode is just a duplicate, so it is not looked up and - * its nlookup should not be incremented. fuse_iget() does - * that, though, so undo it here. - */ - get_fuse_inode(root)->nlookup--; - sb->s_d_op = &fuse_dentry_operations; - sb->s_root = d_make_root(root); - if (!sb->s_root) - return -ENOMEM; - - return 0; -} - int fuse_fill_super_common(struct super_block *sb, struct fuse_fs_context *ctx) { - struct fuse_dev *fud = NULL; - struct fuse_mount *fm = get_fuse_mount_super(sb); - struct fuse_conn *fc = fm->fc; + struct fuse_dev *fud; + struct fuse_conn *fc = get_fuse_conn_super(sb); struct inode *root; struct dentry *root_dentry; int err; @@ -1530,7 +1173,7 @@ int fuse_fill_super_common(struct super_block *sb, struct fuse_fs_context *ctx) if (sb->s_flags & SB_MANDLOCK) goto err; - fuse_sb_defaults(sb); + sb->s_flags &= ~(SB_NOSEC | SB_I_VERSION); if (ctx->is_bdev) { #ifdef CONFIG_BLOCK @@ -1545,21 +1188,29 @@ int fuse_fill_super_common(struct super_block *sb, struct fuse_fs_context *ctx) sb->s_subtype = ctx->subtype; ctx->subtype = NULL; - if (IS_ENABLED(CONFIG_FUSE_DAX)) { - err = fuse_dax_conn_alloc(fc, ctx->dax_dev); - if (err) - goto err; - } + sb->s_magic = FUSE_SUPER_MAGIC; + sb->s_op = &fuse_super_operations; + sb->s_xattr = fuse_xattr_handlers; + sb->s_maxbytes = MAX_LFS_FILESIZE; + sb->s_time_gran = 1; + sb->s_export_op = &fuse_export_operations; + sb->s_iflags |= SB_I_IMA_UNVERIFIABLE_SIGNATURE; + if (sb->s_user_ns != &init_user_ns) + sb->s_iflags |= SB_I_UNTRUSTED_MOUNTER; - if (ctx->fudptr) { - err = -ENOMEM; - fud = fuse_dev_alloc_install(fc); - if (!fud) - goto err_free_dax; - } + /* + * If we are not in the initial user namespace posix + * acls must be translated. + */ + if (sb->s_user_ns != &init_user_ns) + sb->s_xattr = fuse_no_acl_xattr_handlers; + + fud = fuse_dev_alloc_install(fc); + if (!fud) + goto err; fc->dev = sb->s_dev; - fm->sb = sb; + fc->sb = sb; err = fuse_bdi_init(fc, sb); if (err) goto err_dev_free; @@ -1573,27 +1224,24 @@ int fuse_fill_super_common(struct super_block *sb, struct fuse_fs_context *ctx) fc->allow_other = ctx->allow_other; fc->user_id = ctx->user_id; fc->group_id = ctx->group_id; - fc->legacy_opts_show = ctx->legacy_opts_show; - fc->max_read = max_t(unsigned int, 4096, ctx->max_read); + fc->max_read = max_t(unsigned, 4096, ctx->max_read); fc->destroy = ctx->destroy; fc->no_control = ctx->no_control; fc->no_force_umount = ctx->no_force_umount; - fc->no_daemon = ctx->no_daemon; + fc->no_mount_options = ctx->no_mount_options; err = -ENOMEM; - root = fuse_get_root_inode(sb, ctx->rootmode, ctx->root_bpf, - ctx->root_dir); + root = fuse_get_root_inode(sb, ctx->rootmode); sb->s_d_op = &fuse_root_dentry_operations; root_dentry = d_make_root(root); if (!root_dentry) goto err_dev_free; - fuse_init_dentry_root(root_dentry, ctx->root_dir); /* Root dentry doesn't have .d_revalidate */ sb->s_d_op = &fuse_dentry_operations; mutex_lock(&fuse_mutex); err = -EINVAL; - if (ctx->fudptr && *ctx->fudptr) + if (*ctx->fudptr) goto err_unlock; err = fuse_ctl_add_conn(fc); @@ -1602,8 +1250,7 @@ int fuse_fill_super_common(struct super_block *sb, struct fuse_fs_context *ctx) list_add_tail(&fc->entry, &fuse_conn_list); sb->s_root = root_dentry; - if (ctx->fudptr) - *ctx->fudptr = fud; + *ctx->fudptr = fud; mutex_unlock(&fuse_mutex); return 0; @@ -1611,11 +1258,7 @@ int fuse_fill_super_common(struct super_block *sb, struct fuse_fs_context *ctx) mutex_unlock(&fuse_mutex); dput(root_dentry); err_dev_free: - if (fud) - fuse_dev_free(fud); - err_free_dax: - if (IS_ENABLED(CONFIG_FUSE_DAX)) - fuse_dax_conn_free(fc); + fuse_dev_free(fud); err: return err; } @@ -1627,39 +1270,29 @@ static int fuse_fill_super(struct super_block *sb, struct fs_context *fsc) struct file *file; int err; struct fuse_conn *fc; - struct fuse_mount *fm; err = -EINVAL; - if (!ctx->no_daemon) { - file = fget(ctx->fd); - if (!file) - goto err; + file = fget(ctx->fd); + if (!file) + goto err; - /* - * Require mount to happen from the same user namespace which - * opened /dev/fuse to prevent potential attacks. - */ - if ((file->f_op != &fuse_dev_operations) || - (file->f_cred->user_ns != sb->s_user_ns)) - goto err_fput; - ctx->fudptr = &file->private_data; - } + /* + * Require mount to happen from the same user namespace which + * opened /dev/fuse to prevent potential attacks. + */ + if ((file->f_op != &fuse_dev_operations) || + (file->f_cred->user_ns != sb->s_user_ns)) + goto err_fput; + ctx->fudptr = &file->private_data; fc = kmalloc(sizeof(*fc), GFP_KERNEL); err = -ENOMEM; if (!fc) goto err_fput; - fm = kzalloc(sizeof(*fm), GFP_KERNEL); - if (!fm) { - kfree(fc); - goto err_fput; - } - - fuse_conn_init(fc, fm, sb->s_user_ns, &fuse_dev_fiq_ops, NULL); + fuse_conn_init(fc, sb->s_user_ns, &fuse_dev_fiq_ops, NULL); fc->release = fuse_free_conn; - - sb->s_fs_info = fm; + sb->s_fs_info = fc; err = fuse_fill_super_common(sb, ctx); if (err) @@ -1669,24 +1302,22 @@ static int fuse_fill_super(struct super_block *sb, struct fs_context *fsc) * memory barrier for file->private_data to be visible on all * CPUs after this */ - if (!ctx->no_daemon) - fput(file); - fuse_send_init(get_fuse_mount_super(sb)); + fput(file); + fuse_send_init(get_fuse_conn_super(sb)); return 0; err_put_conn: - fuse_mount_put(fm); + fuse_conn_put(fc); sb->s_fs_info = NULL; err_fput: - if (!ctx->no_daemon) - fput(file); + fput(file); err: return err; } -static int fuse_get_tree(struct fs_context *fsc) +static int fuse_get_tree(struct fs_context *fc) { - struct fuse_fs_context *ctx = fsc->fs_private; + struct fuse_fs_context *ctx = fc->fs_private; if (!ctx->fd_present || !ctx->rootmode_present || !ctx->user_id_present || !ctx->group_id_present) @@ -1694,14 +1325,14 @@ static int fuse_get_tree(struct fs_context *fsc) #ifdef CONFIG_BLOCK if (ctx->is_bdev) - return get_tree_bdev(fsc, fuse_fill_super); + return get_tree_bdev(fc, fuse_fill_super); #endif - return get_tree_nodev(fsc, fuse_fill_super); + return get_tree_nodev(fc, fuse_fill_super); } static const struct fs_context_operations fuse_context_ops = { - .free = fuse_free_fsc, + .free = fuse_free_fc, .parse_param = fuse_parse_param, .reconfigure = fuse_reconfigure, .get_tree = fuse_get_tree, @@ -1710,7 +1341,7 @@ static const struct fs_context_operations fuse_context_ops = { /* * Set up the filesystem mount context. */ -static int fuse_init_fs_context(struct fs_context *fsc) +static int fuse_init_fs_context(struct fs_context *fc) { struct fuse_fs_context *ctx; @@ -1720,66 +1351,42 @@ static int fuse_init_fs_context(struct fs_context *fsc) ctx->max_read = ~0; ctx->blksize = FUSE_DEFAULT_BLKSIZE; - ctx->legacy_opts_show = true; #ifdef CONFIG_BLOCK - if (fsc->fs_type == &fuseblk_fs_type) { + if (fc->fs_type == &fuseblk_fs_type) { ctx->is_bdev = true; ctx->destroy = true; } #endif - fsc->fs_private = ctx; - fsc->ops = &fuse_context_ops; + fc->fs_private = ctx; + fc->ops = &fuse_context_ops; return 0; } -bool fuse_mount_remove(struct fuse_mount *fm) +static void fuse_sb_destroy(struct super_block *sb) { - struct fuse_conn *fc = fm->fc; - bool last = false; + struct fuse_conn *fc = get_fuse_conn_super(sb); - down_write(&fc->killsb); - list_del_init(&fm->fc_entry); - if (list_empty(&fc->mounts)) - last = true; - up_write(&fc->killsb); + if (fc) { + if (fc->destroy) + fuse_send_destroy(fc); - return last; -} -EXPORT_SYMBOL_GPL(fuse_mount_remove); + fuse_abort_conn(fc); + fuse_wait_aborted(fc); -void fuse_conn_destroy(struct fuse_mount *fm) -{ - struct fuse_conn *fc = fm->fc; - - if (fc->destroy) - fuse_send_destroy(fm); - - fuse_abort_conn(fc); - fuse_wait_aborted(fc); - - if (!list_empty(&fc->entry)) { - mutex_lock(&fuse_mutex); - list_del(&fc->entry); - fuse_ctl_remove_conn(fc); - mutex_unlock(&fuse_mutex); + down_write(&fc->killsb); + fc->sb = NULL; + up_write(&fc->killsb); } } -EXPORT_SYMBOL_GPL(fuse_conn_destroy); -static void fuse_kill_sb_anon(struct super_block *sb) +void fuse_kill_sb_anon(struct super_block *sb) { - struct fuse_mount *fm = get_fuse_mount_super(sb); - bool last; - - if (fm) { - last = fuse_mount_remove(fm); - if (last) - fuse_conn_destroy(fm); - } + fuse_sb_destroy(sb); kill_anon_super(sb); } +EXPORT_SYMBOL_GPL(fuse_kill_sb_anon); static struct file_system_type fuse_fs_type = { .owner = THIS_MODULE, @@ -1794,14 +1401,7 @@ MODULE_ALIAS_FS("fuse"); #ifdef CONFIG_BLOCK static void fuse_kill_sb_blk(struct super_block *sb) { - struct fuse_mount *fm = get_fuse_mount_super(sb); - bool last; - - if (sb->s_root) { - last = fuse_mount_remove(fm); - if (last) - fuse_conn_destroy(fm); - } + fuse_sb_destroy(sb); kill_block_super(sb); } @@ -1887,61 +1487,6 @@ static void fuse_fs_cleanup(void) static struct kobject *fuse_kobj; -#ifdef CONFIG_FUSE_BPF -static ssize_t fuse_bpf_show(struct kobject *kobj, - struct kobj_attribute *attr, char *buff) -{ - return sysfs_emit(buff, "supported\n"); -} - -static struct kobj_attribute fuse_bpf_attr = - __ATTR_RO(fuse_bpf); -#endif - -static struct attribute *bpf_features[] = { -#ifdef CONFIG_FUSE_BPF - &fuse_bpf_attr.attr, -#endif - NULL, -}; - -static const struct attribute_group bpf_features_group = { - .name = "features", - .attrs = bpf_features, -}; - -/* - * TODO Remove this once fuse-bpf is upstreamed - * - * bpf_prog_type_fuse exports the bpf_prog_type_fuse 'constant', which cannot be - * constant until the code is upstreamed - */ -static ssize_t bpf_prog_type_fuse_show(struct kobject *kobj, - struct kobj_attribute *attr, char *buff) -{ - return sysfs_emit(buff, "%d\n", BPF_PROG_TYPE_FUSE); -} - -static struct kobj_attribute bpf_prog_type_fuse_attr = - __ATTR_RO(bpf_prog_type_fuse); - -static struct attribute *bpf_attributes[] = { - &bpf_prog_type_fuse_attr.attr, - NULL, -}; - -static const struct attribute_group bpf_attr_group = { - .attrs = bpf_attributes, -}; - -static const struct attribute_group *attribute_groups[] = { - &bpf_features_group, - &bpf_attr_group, - NULL -}; - -/* TODO remove to here */ - static int fuse_sysfs_init(void) { int err; @@ -1956,15 +1501,8 @@ static int fuse_sysfs_init(void) if (err) goto out_fuse_unregister; - /* TODO Remove when BPF_PROG_TYPE_FUSE is upstreamed */ - err = sysfs_create_groups(fuse_kobj, attribute_groups); - if (err) - goto out_fuse_remove_mount_point; - return 0; - out_fuse_remove_mount_point: - sysfs_remove_mount_point(fuse_kobj, "connections"); out_fuse_unregister: kobject_put(fuse_kobj); out_err: @@ -1973,7 +1511,6 @@ static int fuse_sysfs_init(void) static void fuse_sysfs_cleanup(void) { - sysfs_remove_groups(fuse_kobj, attribute_groups); sysfs_remove_mount_point(fuse_kobj, "connections"); kobject_put(fuse_kobj); } @@ -2002,21 +1539,11 @@ static int __init fuse_init(void) if (res) goto err_sysfs_cleanup; -#ifdef CONFIG_FUSE_BPF - res = fuse_bpf_init(); - if (res) - goto err_ctl_cleanup; -#endif - sanitize_global_limit(&max_user_bgreq); sanitize_global_limit(&max_user_congthresh); return 0; -#ifdef CONFIG_FUSE_BPF - err_ctl_cleanup: - fuse_ctl_cleanup(); -#endif err_sysfs_cleanup: fuse_sysfs_cleanup(); err_dev_cleanup: @@ -2034,9 +1561,6 @@ static void __exit fuse_exit(void) fuse_ctl_cleanup(); fuse_sysfs_cleanup(); fuse_fs_cleanup(); -#ifdef CONFIG_FUSE_BPF - fuse_bpf_cleanup(); -#endif fuse_dev_cleanup(); } diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c index 1845e05db2da..95368ddfb53a 100644 --- a/fs/fuse/passthrough.c +++ b/fs/fuse/passthrough.c @@ -14,6 +14,18 @@ struct fuse_aio_req { struct kiocb *iocb_fuse; }; +static inline void kiocb_clone(struct kiocb *kiocb, struct kiocb *kiocb_src, + struct file *filp) +{ + *kiocb = (struct kiocb){ + .ki_filp = filp, + .ki_flags = kiocb_src->ki_flags, + .ki_hint = kiocb_src->ki_hint, + .ki_ioprio = kiocb_src->ki_ioprio, + .ki_pos = kiocb_src->ki_pos, + }; +} + static void fuse_file_accessed(struct file *dst_file, struct file *src_file) { struct inode *dst_inode; @@ -34,7 +46,7 @@ static void fuse_file_accessed(struct file *dst_file, struct file *src_file) touch_atime(&dst_file->f_path); } -void fuse_copyattr(struct file *dst_file, struct file *src_file) +static void fuse_copyattr(struct file *dst_file, struct file *src_file) { struct inode *dst = file_inode(dst_file); struct inode *src = file_inode(src_file); @@ -213,8 +225,7 @@ int fuse_passthrough_open(struct fuse_dev *fud, u32 lower_fd) } if (!passthrough_filp->f_op->read_iter || - !((passthrough_filp->f_path.mnt->mnt_flags | MNT_READONLY) || - passthrough_filp->f_op->write_iter)) { + !passthrough_filp->f_op->write_iter) { pr_err("FUSE: passthrough file misses file operations.\n"); res = -EBADF; goto err_free_file; diff --git a/fs/fuse/readdir.c b/fs/fuse/readdir.c index f9d0be56d34a..512609da8590 100644 --- a/fs/fuse/readdir.c +++ b/fs/fuse/readdir.c @@ -20,8 +20,6 @@ static bool fuse_use_readdirplus(struct inode *dir, struct dir_context *ctx) if (!fc->do_readdirplus) return false; - if (fi->nodeid == 0) - return false; if (!fc->readdirplus_auto) return true; if (test_and_clear_bit(FUSE_I_ADVISE_RDPLUS, &fi->state)) @@ -79,10 +77,8 @@ static void fuse_add_dirent_to_cache(struct file *file, goto unlock; addr = kmap_atomic(page); - if (!offset) { + if (!offset) clear_page(addr); - SetPageUptodate(page); - } memcpy(addr + offset, dirent, reclen); kunmap_atomic(addr); fi->rdc.size = (index << PAGE_SHIFT) + offset + reclen; @@ -204,12 +200,9 @@ retry: if (!d_in_lookup(dentry)) { struct fuse_inode *fi; inode = d_inode(dentry); - if (inode && get_node_id(inode) != o->nodeid) - inode = NULL; if (!inode || - fuse_stale_inode(inode, o->generation, &o->attr)) { - if (inode) - fuse_make_bad(inode); + get_node_id(inode) != o->nodeid || + ((o->attr.mode ^ inode->i_mode) & S_IFMT)) { d_invalidate(dentry); dput(dentry); goto retry; @@ -267,7 +260,7 @@ retry: static void fuse_force_forget(struct file *file, u64 nodeid) { struct inode *inode = file_inode(file); - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_forget_in inarg; FUSE_ARGS(args); @@ -281,7 +274,7 @@ static void fuse_force_forget(struct file *file, u64 nodeid) args.force = true; args.noreply = true; - fuse_simple_request(fm, &args); + fuse_simple_request(fc, &args); /* ignore errors */ } @@ -335,7 +328,7 @@ static int fuse_readdir_uncached(struct file *file, struct dir_context *ctx) ssize_t res; struct page *page; struct inode *inode = file_inode(file); - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); struct fuse_io_args ia = {}; struct fuse_args_pages *ap = &ia.ap; struct fuse_page_desc desc = { .length = PAGE_SIZE }; @@ -347,12 +340,12 @@ static int fuse_readdir_uncached(struct file *file, struct dir_context *ctx) return -ENOMEM; plus = fuse_use_readdirplus(inode, ctx); - ap->args.out_pages = true; + ap->args.out_pages = 1; ap->num_pages = 1; ap->pages = &page; ap->descs = &desc; if (plus) { - attr_version = fuse_get_attr_version(fm->fc); + attr_version = fuse_get_attr_version(fc); fuse_read_args_fill(&ia, file, ctx->pos, PAGE_SIZE, FUSE_READDIRPLUS); } else { @@ -360,7 +353,7 @@ static int fuse_readdir_uncached(struct file *file, struct dir_context *ctx) FUSE_READDIR); } locked = fuse_lock_inode(inode); - res = fuse_simple_request(fm, &ap->args); + res = fuse_simple_request(fc, &ap->args); fuse_unlock_inode(inode, locked); if (res >= 0) { if (!res) { @@ -528,12 +521,6 @@ retry_locked: page = find_get_page_flags(file->f_mapping, index, FGP_ACCESSED | FGP_LOCK); - /* Page gone missing, then re-added to cache, but not initialized? */ - if (page && !PageUptodate(page)) { - unlock_page(page); - put_page(page); - page = NULL; - } spin_lock(&fi->rdc.lock); if (!page) { /* @@ -589,26 +576,6 @@ int fuse_readdir(struct file *file, struct dir_context *ctx) struct inode *inode = file_inode(file); int err; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - bool allow_force; - bool force_again = false; - bool is_continued = false; - -again: - fer = fuse_bpf_backing(inode, struct fuse_read_io, - fuse_readdir_initialize, fuse_readdir_backing, - fuse_readdir_finalize, - file, ctx, &force_again, &allow_force, is_continued); - if (force_again && !IS_ERR(fer.result)) { - is_continued = true; - goto again; - } - - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (fuse_is_bad(inode)) return -EIO; diff --git a/fs/fuse/virtio_fs.c b/fs/fuse/virtio_fs.c index c23a94d179fd..97259c6afac8 100644 --- a/fs/fuse/virtio_fs.c +++ b/fs/fuse/virtio_fs.c @@ -5,25 +5,14 @@ */ #include -#include -#include -#include #include #include #include #include #include -#include #include -#include #include "fuse_i.h" -/* Used to help calculate the FUSE connection's max_pages limit for a request's - * size. Parts of the struct fuse_req are sliced into scattergather lists in - * addition to the pages used, so this can help account for that overhead. - */ -#define FUSE_HEADER_OVERHEAD 4 - /* List of virtio-fs device instances and a lock for the list. Also provides * mutual exclusion in device removal and mounting path */ @@ -35,8 +24,6 @@ enum { VQ_REQUEST }; -#define VQ_NAME_LEN 24 - /* Per-virtqueue state */ struct virtio_fs_vq { spinlock_t lock; @@ -48,8 +35,7 @@ struct virtio_fs_vq { struct fuse_dev *fud; bool connected; long in_flight; - struct completion in_flight_zero; /* No inflight requests */ - char name[VQ_NAME_LEN]; + char name[24]; } ____cacheline_aligned_in_smp; /* A virtio-fs device instance */ @@ -60,23 +46,13 @@ struct virtio_fs { struct virtio_fs_vq *vqs; unsigned int nvqs; /* number of virtqueues */ unsigned int num_request_queues; /* number of request queues */ - struct dax_device *dax_dev; - - /* DAX memory window where file contents are mapped */ - void *window_kaddr; - phys_addr_t window_phys_addr; - size_t window_len; -}; - -struct virtio_fs_forget_req { - struct fuse_in_header ih; - struct fuse_forget_in arg; }; struct virtio_fs_forget { + struct fuse_in_header ih; + struct fuse_forget_in arg; /* This request can be temporarily queued on virt queue */ struct list_head list; - struct virtio_fs_forget_req req; }; struct virtio_fs_req_work { @@ -88,48 +64,6 @@ struct virtio_fs_req_work { static int virtio_fs_enqueue_req(struct virtio_fs_vq *fsvq, struct fuse_req *req, bool in_flight); -enum { - OPT_DAX, -}; - -static const struct fs_parameter_spec virtio_param_specs[] = { - fsparam_flag("dax", OPT_DAX), - {} -}; - -static const struct fs_parameter_description virtio_fs_parameters = { - .specs = virtio_param_specs, -}; - -static int virtio_fs_parse_param(struct fs_context *fsc, - struct fs_parameter *param) -{ - struct fs_parse_result result; - struct fuse_fs_context *ctx = fsc->fs_private; - int opt; - - opt = fs_parse(fsc, &virtio_fs_parameters, param, &result); - if (opt < 0) - return opt; - - switch (opt) { - case OPT_DAX: - ctx->dax = 1; - break; - default: - return -EINVAL; - } - - return 0; -} - -static void virtio_fs_free_fsc(struct fs_context *fsc) -{ - struct fuse_fs_context *ctx = fsc->fs_private; - - kfree(ctx); -} - static inline struct virtio_fs_vq *vq_to_fsvq(struct virtqueue *vq) { struct virtio_fs *fs = vq->vdev->priv; @@ -153,8 +87,6 @@ static inline void dec_in_flight_req(struct virtio_fs_vq *fsvq) { WARN_ON(fsvq->in_flight <= 0); fsvq->in_flight--; - if (!fsvq->in_flight) - complete(&fsvq->in_flight_zero); } static void release_virtio_fs_obj(struct kref *ref) @@ -185,23 +117,22 @@ static void virtio_fs_drain_queue(struct virtio_fs_vq *fsvq) WARN_ON(fsvq->in_flight < 0); /* Wait for in flight requests to finish.*/ - spin_lock(&fsvq->lock); - if (fsvq->in_flight) { - /* We are holding virtio_fs_mutex. There should not be any - * waiters waiting for completion. - */ - reinit_completion(&fsvq->in_flight_zero); - spin_unlock(&fsvq->lock); - wait_for_completion(&fsvq->in_flight_zero); - } else { + while (1) { + spin_lock(&fsvq->lock); + if (!fsvq->in_flight) { + spin_unlock(&fsvq->lock); + break; + } spin_unlock(&fsvq->lock); + /* TODO use completion instead of timeout */ + usleep_range(1000, 2000); } flush_work(&fsvq->done_work); flush_delayed_work(&fsvq->dispatch_work); } -static void virtio_fs_drain_all_queues_locked(struct virtio_fs *fs) +static void virtio_fs_drain_all_queues(struct virtio_fs *fs) { struct virtio_fs_vq *fsvq; int i; @@ -212,19 +143,6 @@ static void virtio_fs_drain_all_queues_locked(struct virtio_fs *fs) } } -static void virtio_fs_drain_all_queues(struct virtio_fs *fs) -{ - /* Provides mutual exclusion between ->remove and ->kill_sb - * paths. We don't want both of these draining queue at the - * same time. Current completion logic reinits completion - * and that means there should not be any other thread - * doing reinit or waiting for completion already. - */ - mutex_lock(&virtio_fs_mutex); - virtio_fs_drain_all_queues_locked(fs); - mutex_unlock(&virtio_fs_mutex); -} - static void virtio_fs_start_all_queues(struct virtio_fs *fs) { struct virtio_fs_vq *fsvq; @@ -360,6 +278,7 @@ static void virtio_fs_request_dispatch_work(struct work_struct *work) struct fuse_req *req; struct virtio_fs_vq *fsvq = container_of(work, struct virtio_fs_vq, dispatch_work.work); + struct fuse_conn *fc = fsvq->fud->fc; int ret; pr_debug("virtio-fs: worker %s called.\n", __func__); @@ -374,7 +293,7 @@ static void virtio_fs_request_dispatch_work(struct work_struct *work) list_del_init(&req->list); spin_unlock(&fsvq->lock); - fuse_request_end(req); + fuse_request_end(fc, req); } /* Dispatch pending requests */ @@ -405,77 +324,22 @@ static void virtio_fs_request_dispatch_work(struct work_struct *work) spin_unlock(&fsvq->lock); pr_err("virtio-fs: virtio_fs_enqueue_req() failed %d\n", ret); - fuse_request_end(req); + fuse_request_end(fc, req); } } } -/* - * Returns 1 if queue is full and sender should wait a bit before sending - * next request, 0 otherwise. - */ -static int send_forget_request(struct virtio_fs_vq *fsvq, - struct virtio_fs_forget *forget, - bool in_flight) -{ - struct scatterlist sg; - struct virtqueue *vq; - int ret = 0; - bool notify; - struct virtio_fs_forget_req *req = &forget->req; - - spin_lock(&fsvq->lock); - if (!fsvq->connected) { - if (in_flight) - dec_in_flight_req(fsvq); - kfree(forget); - goto out; - } - - sg_init_one(&sg, req, sizeof(*req)); - vq = fsvq->vq; - dev_dbg(&vq->vdev->dev, "%s\n", __func__); - - ret = virtqueue_add_outbuf(vq, &sg, 1, forget, GFP_ATOMIC); - if (ret < 0) { - if (ret == -ENOMEM || ret == -ENOSPC) { - pr_debug("virtio-fs: Could not queue FORGET: err=%d. Will try later\n", - ret); - list_add_tail(&forget->list, &fsvq->queued_reqs); - schedule_delayed_work(&fsvq->dispatch_work, - msecs_to_jiffies(1)); - if (!in_flight) - inc_in_flight_req(fsvq); - /* Queue is full */ - ret = 1; - } else { - pr_debug("virtio-fs: Could not queue FORGET: err=%d. Dropping it.\n", - ret); - kfree(forget); - if (in_flight) - dec_in_flight_req(fsvq); - } - goto out; - } - - if (!in_flight) - inc_in_flight_req(fsvq); - notify = virtqueue_kick_prepare(vq); - spin_unlock(&fsvq->lock); - - if (notify) - virtqueue_notify(vq); - return ret; -out: - spin_unlock(&fsvq->lock); - return ret; -} - static void virtio_fs_hiprio_dispatch_work(struct work_struct *work) { struct virtio_fs_forget *forget; struct virtio_fs_vq *fsvq = container_of(work, struct virtio_fs_vq, dispatch_work.work); + struct virtqueue *vq = fsvq->vq; + struct scatterlist sg; + struct scatterlist *sgs[] = {&sg}; + bool notify; + int ret; + pr_debug("virtio-fs: worker %s called.\n", __func__); while (1) { spin_lock(&fsvq->lock); @@ -487,9 +351,43 @@ static void virtio_fs_hiprio_dispatch_work(struct work_struct *work) } list_del(&forget->list); - spin_unlock(&fsvq->lock); - if (send_forget_request(fsvq, forget, true)) + if (!fsvq->connected) { + dec_in_flight_req(fsvq); + spin_unlock(&fsvq->lock); + kfree(forget); + continue; + } + + sg_init_one(&sg, forget, sizeof(*forget)); + + /* Enqueue the request */ + dev_dbg(&vq->vdev->dev, "%s\n", __func__); + ret = virtqueue_add_sgs(vq, sgs, 1, 0, forget, GFP_ATOMIC); + if (ret < 0) { + if (ret == -ENOMEM || ret == -ENOSPC) { + pr_debug("virtio-fs: Could not queue FORGET: err=%d. Will try later\n", + ret); + list_add_tail(&forget->list, + &fsvq->queued_reqs); + schedule_delayed_work(&fsvq->dispatch_work, + msecs_to_jiffies(1)); + } else { + pr_debug("virtio-fs: Could not queue FORGET: err=%d. Dropping it.\n", + ret); + dec_in_flight_req(fsvq); + kfree(forget); + } + spin_unlock(&fsvq->lock); return; + } + + notify = virtqueue_kick_prepare(vq); + spin_unlock(&fsvq->lock); + + if (notify) + virtqueue_notify(vq); + pr_debug("virtio-fs: worker %s dispatched one forget request.\n", + __func__); } } @@ -565,6 +463,7 @@ static void virtio_fs_request_complete(struct fuse_req *req, struct virtio_fs_vq *fsvq) { struct fuse_pqueue *fpq = &fsvq->fud->pq; + struct fuse_conn *fc = fsvq->fud->fc; struct fuse_args *args; struct fuse_args_pages *ap; unsigned int len, i, thislen; @@ -597,7 +496,7 @@ static void virtio_fs_request_complete(struct fuse_req *req, clear_bit(FR_SENT, &req->flags); spin_unlock(&fpq->lock); - fuse_request_end(req); + fuse_request_end(fc, req); spin_lock(&fsvq->lock); dec_in_flight_req(fsvq); spin_unlock(&fsvq->lock); @@ -665,26 +564,6 @@ static void virtio_fs_vq_done(struct virtqueue *vq) schedule_work(&fsvq->done_work); } -static void virtio_fs_init_vq(struct virtio_fs_vq *fsvq, char *name, - int vq_type) -{ - strncpy(fsvq->name, name, VQ_NAME_LEN); - spin_lock_init(&fsvq->lock); - INIT_LIST_HEAD(&fsvq->queued_reqs); - INIT_LIST_HEAD(&fsvq->end_reqs); - init_completion(&fsvq->in_flight_zero); - - if (vq_type == VQ_REQUEST) { - INIT_WORK(&fsvq->done_work, virtio_fs_requests_done_work); - INIT_DELAYED_WORK(&fsvq->dispatch_work, - virtio_fs_request_dispatch_work); - } else { - INIT_WORK(&fsvq->done_work, virtio_fs_hiprio_done_work); - INIT_DELAYED_WORK(&fsvq->dispatch_work, - virtio_fs_hiprio_dispatch_work); - } -} - /* Initialize virtqueues */ static int virtio_fs_setup_vqs(struct virtio_device *vdev, struct virtio_fs *fs) @@ -695,12 +574,12 @@ static int virtio_fs_setup_vqs(struct virtio_device *vdev, unsigned int i; int ret = 0; - virtio_cread_le(vdev, struct virtio_fs_config, num_request_queues, - &fs->num_request_queues); + virtio_cread(vdev, struct virtio_fs_config, num_request_queues, + &fs->num_request_queues); if (fs->num_request_queues == 0) return -EINVAL; - fs->nvqs = VQ_REQUEST + fs->num_request_queues; + fs->nvqs = 1 + fs->num_request_queues; fs->vqs = kcalloc(fs->nvqs, sizeof(fs->vqs[VQ_HIPRIO]), GFP_KERNEL); if (!fs->vqs) return -ENOMEM; @@ -714,17 +593,27 @@ static int virtio_fs_setup_vqs(struct virtio_device *vdev, goto out; } - /* Initialize the hiprio/forget request virtqueue */ callbacks[VQ_HIPRIO] = virtio_fs_vq_done; - virtio_fs_init_vq(&fs->vqs[VQ_HIPRIO], "hiprio", VQ_HIPRIO); + snprintf(fs->vqs[VQ_HIPRIO].name, sizeof(fs->vqs[VQ_HIPRIO].name), + "hiprio"); names[VQ_HIPRIO] = fs->vqs[VQ_HIPRIO].name; + INIT_WORK(&fs->vqs[VQ_HIPRIO].done_work, virtio_fs_hiprio_done_work); + INIT_LIST_HEAD(&fs->vqs[VQ_HIPRIO].queued_reqs); + INIT_LIST_HEAD(&fs->vqs[VQ_HIPRIO].end_reqs); + INIT_DELAYED_WORK(&fs->vqs[VQ_HIPRIO].dispatch_work, + virtio_fs_hiprio_dispatch_work); + spin_lock_init(&fs->vqs[VQ_HIPRIO].lock); /* Initialize the requests virtqueues */ for (i = VQ_REQUEST; i < fs->nvqs; i++) { - char vq_name[VQ_NAME_LEN]; - - snprintf(vq_name, VQ_NAME_LEN, "requests.%u", i - VQ_REQUEST); - virtio_fs_init_vq(&fs->vqs[i], vq_name, VQ_REQUEST); + spin_lock_init(&fs->vqs[i].lock); + INIT_WORK(&fs->vqs[i].done_work, virtio_fs_requests_done_work); + INIT_DELAYED_WORK(&fs->vqs[i].dispatch_work, + virtio_fs_request_dispatch_work); + INIT_LIST_HEAD(&fs->vqs[i].queued_reqs); + INIT_LIST_HEAD(&fs->vqs[i].end_reqs); + snprintf(fs->vqs[i].name, sizeof(fs->vqs[i].name), + "requests.%u", i - VQ_REQUEST); callbacks[i] = virtio_fs_vq_done; names[i] = fs->vqs[i].name; } @@ -753,130 +642,6 @@ static void virtio_fs_cleanup_vqs(struct virtio_device *vdev, vdev->config->del_vqs(vdev); } -/* Map a window offset to a page frame number. The window offset will have - * been produced by .iomap_begin(), which maps a file offset to a window - * offset. - */ -static long virtio_fs_direct_access(struct dax_device *dax_dev, pgoff_t pgoff, - long nr_pages, void **kaddr, pfn_t *pfn) -{ - struct virtio_fs *fs = dax_get_private(dax_dev); - phys_addr_t offset = PFN_PHYS(pgoff); - size_t max_nr_pages = fs->window_len/PAGE_SIZE - pgoff; - - if (kaddr) - *kaddr = fs->window_kaddr + offset; - if (pfn) - *pfn = phys_to_pfn_t(fs->window_phys_addr + offset, - PFN_DEV | PFN_MAP); - return nr_pages > max_nr_pages ? max_nr_pages : nr_pages; -} - -static size_t virtio_fs_copy_from_iter(struct dax_device *dax_dev, - pgoff_t pgoff, void *addr, - size_t bytes, struct iov_iter *i) -{ - return copy_from_iter(addr, bytes, i); -} - -static size_t virtio_fs_copy_to_iter(struct dax_device *dax_dev, - pgoff_t pgoff, void *addr, - size_t bytes, struct iov_iter *i) -{ - return copy_to_iter(addr, bytes, i); -} - -static int virtio_fs_zero_page_range(struct dax_device *dax_dev, - pgoff_t pgoff, size_t nr_pages) -{ - long rc; - void *kaddr; - - rc = dax_direct_access(dax_dev, pgoff, nr_pages, &kaddr, NULL); - if (rc < 0) - return rc; - memset(kaddr, 0, nr_pages << PAGE_SHIFT); - dax_flush(dax_dev, kaddr, nr_pages << PAGE_SHIFT); - return 0; -} - -static const struct dax_operations virtio_fs_dax_ops = { - .direct_access = virtio_fs_direct_access, - .copy_from_iter = virtio_fs_copy_from_iter, - .copy_to_iter = virtio_fs_copy_to_iter, - .zero_page_range = virtio_fs_zero_page_range, -}; - -static void virtio_fs_cleanup_dax(void *data) -{ - struct dax_device *dax_dev = data; - - kill_dax(dax_dev); - put_dax(dax_dev); -} - -static int virtio_fs_setup_dax(struct virtio_device *vdev, struct virtio_fs *fs) -{ - struct virtio_shm_region cache_reg; - struct dev_pagemap *pgmap; - bool have_cache; - - if (!IS_ENABLED(CONFIG_FUSE_DAX)) - return 0; - - /* Get cache region */ - have_cache = virtio_get_shm_region(vdev, &cache_reg, - (u8)VIRTIO_FS_SHMCAP_ID_CACHE); - if (!have_cache) { - dev_notice(&vdev->dev, "%s: No cache capability\n", __func__); - return 0; - } - - if (!devm_request_mem_region(&vdev->dev, cache_reg.addr, cache_reg.len, - dev_name(&vdev->dev))) { - dev_warn(&vdev->dev, "could not reserve region addr=0x%llx len=0x%llx\n", - cache_reg.addr, cache_reg.len); - return -EBUSY; - } - - dev_notice(&vdev->dev, "Cache len: 0x%llx @ 0x%llx\n", cache_reg.len, - cache_reg.addr); - - pgmap = devm_kzalloc(&vdev->dev, sizeof(*pgmap), GFP_KERNEL); - if (!pgmap) - return -ENOMEM; - - pgmap->type = MEMORY_DEVICE_FS_DAX; - - /* Ideally we would directly use the PCI BAR resource but - * devm_memremap_pages() wants its own copy in pgmap. So - * initialize a struct resource from scratch (only the start - * and end fields will be used). - */ - pgmap->res = (struct resource){ - .name = "virtio-fs dax window", - .start = (phys_addr_t) cache_reg.addr, - .end = (phys_addr_t) cache_reg.addr + cache_reg.len - 1, - }; - - fs->window_kaddr = devm_memremap_pages(&vdev->dev, pgmap); - if (IS_ERR(fs->window_kaddr)) - return PTR_ERR(fs->window_kaddr); - - fs->window_phys_addr = (phys_addr_t) cache_reg.addr; - fs->window_len = (phys_addr_t) cache_reg.len; - - dev_dbg(&vdev->dev, "%s: window kaddr 0x%px phys_addr 0x%llx len 0x%llx\n", - __func__, fs->window_kaddr, cache_reg.addr, cache_reg.len); - - fs->dax_dev = alloc_dax(fs, NULL, &virtio_fs_dax_ops, 0); - if (IS_ERR(fs->dax_dev)) - return PTR_ERR(fs->dax_dev); - - return devm_add_action_or_reset(&vdev->dev, virtio_fs_cleanup_dax, - fs->dax_dev); -} - static int virtio_fs_probe(struct virtio_device *vdev) { struct virtio_fs *fs; @@ -898,10 +663,6 @@ static int virtio_fs_probe(struct virtio_device *vdev) /* TODO vq affinity */ - ret = virtio_fs_setup_dax(vdev, fs); - if (ret < 0) - goto out_vqs; - /* Bring the device online in case the filesystem is mounted and * requests need to be sent before we return. */ @@ -945,7 +706,7 @@ static void virtio_fs_remove(struct virtio_device *vdev) /* This device is going away. No one should get new reference */ list_del_init(&fs->list); virtio_fs_stop_all_queues(fs); - virtio_fs_drain_all_queues_locked(fs); + virtio_fs_drain_all_queues(fs); vdev->config->reset(vdev); virtio_fs_cleanup_vqs(vdev, fs); @@ -970,12 +731,12 @@ static int virtio_fs_restore(struct virtio_device *vdev) } #endif /* CONFIG_PM_SLEEP */ -static const struct virtio_device_id id_table[] = { +const static struct virtio_device_id id_table[] = { { VIRTIO_ID_FS, VIRTIO_DEV_ANY_ID }, {}, }; -static const unsigned int feature_table[] = {}; +const static unsigned int feature_table[] = {}; static struct virtio_driver virtio_fs_driver = { .driver.name = KBUILD_MODNAME, @@ -996,10 +757,14 @@ __releases(fiq->lock) { struct fuse_forget_link *link; struct virtio_fs_forget *forget; - struct virtio_fs_forget_req *req; + struct scatterlist sg; + struct scatterlist *sgs[] = {&sg}; struct virtio_fs *fs; + struct virtqueue *vq; struct virtio_fs_vq *fsvq; + bool notify; u64 unique; + int ret; link = fuse_dequeue_forget(fiq, 1, NULL); unique = fuse_get_unique(fiq); @@ -1010,19 +775,57 @@ __releases(fiq->lock) /* Allocate a buffer for the request */ forget = kmalloc(sizeof(*forget), GFP_NOFS | __GFP_NOFAIL); - req = &forget->req; - req->ih = (struct fuse_in_header){ + forget->ih = (struct fuse_in_header){ .opcode = FUSE_FORGET, .nodeid = link->forget_one.nodeid, .unique = unique, - .len = sizeof(*req), + .len = sizeof(*forget), }; - req->arg = (struct fuse_forget_in){ + forget->arg = (struct fuse_forget_in){ .nlookup = link->forget_one.nlookup, }; - send_forget_request(fsvq, forget, false); + sg_init_one(&sg, forget, sizeof(*forget)); + + /* Enqueue the request */ + spin_lock(&fsvq->lock); + + if (!fsvq->connected) { + kfree(forget); + spin_unlock(&fsvq->lock); + goto out; + } + + vq = fsvq->vq; + dev_dbg(&vq->vdev->dev, "%s\n", __func__); + + ret = virtqueue_add_sgs(vq, sgs, 1, 0, forget, GFP_ATOMIC); + if (ret < 0) { + if (ret == -ENOMEM || ret == -ENOSPC) { + pr_debug("virtio-fs: Could not queue FORGET: err=%d. Will try later.\n", + ret); + list_add_tail(&forget->list, &fsvq->queued_reqs); + schedule_delayed_work(&fsvq->dispatch_work, + msecs_to_jiffies(1)); + inc_in_flight_req(fsvq); + } else { + pr_debug("virtio-fs: Could not queue FORGET: err=%d. Dropping it.\n", + ret); + kfree(forget); + } + spin_unlock(&fsvq->lock); + goto out; + } + + inc_in_flight_req(fsvq); + notify = virtqueue_kick_prepare(vq); + + spin_unlock(&fsvq->lock); + + if (notify) + virtqueue_notify(vq); +out: kfree(link); } @@ -1039,37 +842,18 @@ __releases(fiq->lock) spin_unlock(&fiq->lock); } -/* Count number of scatter-gather elements required */ -static unsigned int sg_count_fuse_pages(struct fuse_page_desc *page_descs, - unsigned int num_pages, - unsigned int total_len) -{ - unsigned int i; - unsigned int this_len; - - for (i = 0; i < num_pages && total_len; i++) { - this_len = min(page_descs[i].length, total_len); - total_len -= this_len; - } - - return i; -} - /* Return the number of scatter-gather list elements required */ static unsigned int sg_count_fuse_req(struct fuse_req *req) { struct fuse_args *args = req->args; struct fuse_args_pages *ap = container_of(args, typeof(*ap), args); - unsigned int size, total_sgs = 1 /* fuse_in_header */; + unsigned int total_sgs = 1 /* fuse_in_header */; if (args->in_numargs - args->in_pages) total_sgs += 1; - if (args->in_pages) { - size = args->in_args[args->in_numargs - 1].size; - total_sgs += sg_count_fuse_pages(ap->descs, ap->num_pages, - size); - } + if (args->in_pages) + total_sgs += ap->num_pages; if (!test_bit(FR_ISREPLY, &req->flags)) return total_sgs; @@ -1079,11 +863,8 @@ static unsigned int sg_count_fuse_req(struct fuse_req *req) if (args->out_numargs - args->out_pages) total_sgs += 1; - if (args->out_pages) { - size = args->out_args[args->out_numargs - 1].size; - total_sgs += sg_count_fuse_pages(ap->descs, ap->num_pages, - size); - } + if (args->out_pages) + total_sgs += ap->num_pages; return total_sgs; } @@ -1292,35 +1073,31 @@ __releases(fiq->lock) } } -static const struct fuse_iqueue_ops virtio_fs_fiq_ops = { +const static struct fuse_iqueue_ops virtio_fs_fiq_ops = { .wake_forget_and_unlock = virtio_fs_wake_forget_and_unlock, .wake_interrupt_and_unlock = virtio_fs_wake_interrupt_and_unlock, .wake_pending_and_unlock = virtio_fs_wake_pending_and_unlock, .release = virtio_fs_fiq_release, }; -static inline void virtio_fs_ctx_set_defaults(struct fuse_fs_context *ctx) +static int virtio_fs_fill_super(struct super_block *sb) { - ctx->rootmode = S_IFDIR; - ctx->default_permissions = 1; - ctx->allow_other = 1; - ctx->max_read = UINT_MAX; - ctx->blksize = 512; - ctx->destroy = true; - ctx->no_control = true; - ctx->no_force_umount = true; -} - -static int virtio_fs_fill_super(struct super_block *sb, struct fs_context *fsc) -{ - struct fuse_mount *fm = get_fuse_mount_super(sb); - struct fuse_conn *fc = fm->fc; + struct fuse_conn *fc = get_fuse_conn_super(sb); struct virtio_fs *fs = fc->iq.priv; - struct fuse_fs_context *ctx = fsc->fs_private; unsigned int i; int err; + struct fuse_fs_context ctx = { + .rootmode = S_IFDIR, + .default_permissions = 1, + .allow_other = 1, + .max_read = UINT_MAX, + .blksize = 512, + .destroy = true, + .no_control = true, + .no_force_umount = true, + .no_mount_options = true, + }; - virtio_fs_ctx_set_defaults(ctx); mutex_lock(&virtio_fs_mutex); /* After holding mutex, make sure virtiofs device is still there. @@ -1335,7 +1112,7 @@ static int virtio_fs_fill_super(struct super_block *sb, struct fs_context *fsc) err = -ENOMEM; /* Allocate fuse_dev for hiprio and notification queues */ - for (i = 0; i < fs->nvqs; i++) { + for (i = 0; i < VQ_REQUEST; i++) { struct virtio_fs_vq *fsvq = &fs->vqs[i]; fsvq->fud = fuse_dev_alloc(); @@ -1343,30 +1120,24 @@ static int virtio_fs_fill_super(struct super_block *sb, struct fs_context *fsc) goto err_free_fuse_devs; } - /* virtiofs allocates and installs its own fuse devices */ - ctx->fudptr = NULL; - if (ctx->dax) { - if (!fs->dax_dev) { - err = -EINVAL; - pr_err("virtio-fs: dax can't be enabled as filesystem" - " device does not support it.\n"); - goto err_free_fuse_devs; - } - ctx->dax_dev = fs->dax_dev; - } - err = fuse_fill_super_common(sb, ctx); + ctx.fudptr = (void **)&fs->vqs[VQ_REQUEST].fud; + err = fuse_fill_super_common(sb, &ctx); if (err < 0) goto err_free_fuse_devs; + fc = fs->vqs[VQ_REQUEST].fud->fc; + for (i = 0; i < fs->nvqs; i++) { struct virtio_fs_vq *fsvq = &fs->vqs[i]; + if (i == VQ_REQUEST) + continue; /* already initialized */ fuse_dev_install(fsvq->fud, fc); } /* Previous unmount will stop all queues. Start these again */ virtio_fs_start_all_queues(fs); - fuse_send_init(fm); + fuse_send_init(fc); mutex_unlock(&virtio_fs_mutex); return 0; @@ -1377,17 +1148,18 @@ err: return err; } -static void virtio_fs_conn_destroy(struct fuse_mount *fm) +static void virtio_kill_sb(struct super_block *sb) { - struct fuse_conn *fc = fm->fc; - struct virtio_fs *vfs = fc->iq.priv; - struct virtio_fs_vq *fsvq = &vfs->vqs[VQ_HIPRIO]; + struct fuse_conn *fc = get_fuse_conn_super(sb); + struct virtio_fs *vfs; + struct virtio_fs_vq *fsvq; - /* Stop dax worker. Soon evict_inodes() will be called which - * will free all memory ranges belonging to all inodes. - */ - if (IS_ENABLED(CONFIG_FUSE_DAX)) - fuse_dax_cancel_work(fc); + /* If mount failed, we can still be called without any fc */ + if (!fc) + return fuse_kill_sb_anon(sb); + + vfs = fc->iq.priv; + fsvq = &vfs->vqs[VQ_HIPRIO]; /* Stop forget queue. Soon destroy will be sent */ spin_lock(&fsvq->lock); @@ -1395,9 +1167,9 @@ static void virtio_fs_conn_destroy(struct fuse_mount *fm) spin_unlock(&fsvq->lock); virtio_fs_drain_all_queues(vfs); - fuse_conn_destroy(fm); + fuse_kill_sb_anon(sb); - /* fuse_conn_destroy() must have sent destroy. Stop all queues + /* fuse_kill_sb_anon() must have sent destroy. Stop all queues * and drain one more time and free fuse devices. Freeing fuse * devices will drop their reference on fuse_conn and that in * turn will drop its reference on virtio_fs object. @@ -1407,27 +1179,12 @@ static void virtio_fs_conn_destroy(struct fuse_mount *fm) virtio_fs_free_devs(vfs); } -static void virtio_kill_sb(struct super_block *sb) -{ - struct fuse_mount *fm = get_fuse_mount_super(sb); - bool last; - - /* If mount failed, we can still be called without any fc */ - if (sb->s_root) { - last = fuse_mount_remove(fm); - if (last) - virtio_fs_conn_destroy(fm); - } - kill_anon_super(sb); -} - static int virtio_fs_test_super(struct super_block *sb, struct fs_context *fsc) { - struct fuse_mount *fsc_fm = fsc->s_fs_info; - struct fuse_mount *sb_fm = get_fuse_mount_super(sb); + struct fuse_conn *fc = fsc->s_fs_info; - return fsc_fm->fc->iq.priv == sb_fm->fc->iq.priv; + return fc->iq.priv == get_fuse_conn_super(sb)->iq.priv; } static int virtio_fs_set_super(struct super_block *sb, @@ -1437,7 +1194,7 @@ static int virtio_fs_set_super(struct super_block *sb, err = get_anon_bdev(&sb->s_dev); if (!err) - fuse_mount_get(fsc->s_fs_info); + fuse_conn_get(fsc->s_fs_info); return err; } @@ -1446,10 +1203,8 @@ static int virtio_fs_get_tree(struct fs_context *fsc) { struct virtio_fs *fs; struct super_block *sb; - struct fuse_conn *fc = NULL; - struct fuse_mount *fm; - unsigned int virtqueue_size; - int err = -EIO; + struct fuse_conn *fc; + int err; if (!fsc->source) return invalf(fsc, "No source specified"); @@ -1464,39 +1219,28 @@ static int virtio_fs_get_tree(struct fs_context *fsc) return -EINVAL; } - virtqueue_size = virtqueue_get_vring_size(fs->vqs[VQ_REQUEST].vq); - if (WARN_ON(virtqueue_size <= FUSE_HEADER_OVERHEAD)) - goto out_err; - - err = -ENOMEM; fc = kzalloc(sizeof(struct fuse_conn), GFP_KERNEL); - if (!fc) - goto out_err; + if (!fc) { + mutex_lock(&virtio_fs_mutex); + virtio_fs_put(fs); + mutex_unlock(&virtio_fs_mutex); + return -ENOMEM; + } - fm = kzalloc(sizeof(struct fuse_mount), GFP_KERNEL); - if (!fm) - goto out_err; - - fuse_conn_init(fc, fm, fsc->user_ns, &virtio_fs_fiq_ops, fs); + fuse_conn_init(fc, get_user_ns(current_user_ns()), &virtio_fs_fiq_ops, + fs); fc->release = fuse_free_conn; fc->delete_stale = true; - fc->auto_submounts = true; - /* Tell FUSE to split requests that exceed the virtqueue's size */ - fc->max_pages_limit = min_t(unsigned int, fc->max_pages_limit, - virtqueue_size - FUSE_HEADER_OVERHEAD); - - fsc->s_fs_info = fm; + fsc->s_fs_info = fc; sb = sget_fc(fsc, virtio_fs_test_super, virtio_fs_set_super); - fuse_mount_put(fm); + fuse_conn_put(fc); if (IS_ERR(sb)) return PTR_ERR(sb); if (!sb->s_root) { - err = virtio_fs_fill_super(sb, fsc); + err = virtio_fs_fill_super(sb); if (err) { - fuse_mount_put(fm); - sb->s_fs_info = NULL; deactivate_locked_super(sb); return err; } @@ -1507,29 +1251,14 @@ static int virtio_fs_get_tree(struct fs_context *fsc) WARN_ON(fsc->root); fsc->root = dget(sb->s_root); return 0; - -out_err: - kfree(fc); - mutex_lock(&virtio_fs_mutex); - virtio_fs_put(fs); - mutex_unlock(&virtio_fs_mutex); - return err; } static const struct fs_context_operations virtio_fs_context_ops = { - .free = virtio_fs_free_fsc, - .parse_param = virtio_fs_parse_param, .get_tree = virtio_fs_get_tree, }; static int virtio_fs_init_fs_context(struct fs_context *fsc) { - struct fuse_fs_context *ctx; - - ctx = kzalloc(sizeof(struct fuse_fs_context), GFP_KERNEL); - if (!ctx) - return -ENOMEM; - fsc->fs_private = ctx; fsc->ops = &virtio_fs_context_ops; return 0; } diff --git a/fs/fuse/xattr.c b/fs/fuse/xattr.c index 3abdf0e2be89..9d3f28b1f6f8 100644 --- a/fs/fuse/xattr.c +++ b/fs/fuse/xattr.c @@ -14,12 +14,12 @@ int fuse_setxattr(struct inode *inode, const char *name, const void *value, size_t size, int flags) { - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); struct fuse_setxattr_in inarg; int err; - if (fm->fc->no_setxattr) + if (fc->no_setxattr) return -EOPNOTSUPP; memset(&inarg, 0, sizeof(inarg)); @@ -34,9 +34,9 @@ int fuse_setxattr(struct inode *inode, const char *name, const void *value, args.in_args[1].value = name; args.in_args[2].size = size; args.in_args[2].value = value; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err == -ENOSYS) { - fm->fc->no_setxattr = 1; + fc->no_setxattr = 1; err = -EOPNOTSUPP; } if (!err) { @@ -49,13 +49,13 @@ int fuse_setxattr(struct inode *inode, const char *name, const void *value, ssize_t fuse_getxattr(struct inode *inode, const char *name, void *value, size_t size) { - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); struct fuse_getxattr_in inarg; struct fuse_getxattr_out outarg; ssize_t ret; - if (fm->fc->no_getxattr) + if (fc->no_getxattr) return -EOPNOTSUPP; memset(&inarg, 0, sizeof(inarg)); @@ -77,11 +77,11 @@ ssize_t fuse_getxattr(struct inode *inode, const char *name, void *value, args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; } - ret = fuse_simple_request(fm, &args); + ret = fuse_simple_request(fc, &args); if (!ret && !size) ret = min_t(size_t, outarg.size, XATTR_SIZE_MAX); if (ret == -ENOSYS) { - fm->fc->no_getxattr = 1; + fc->no_getxattr = 1; ret = -EOPNOTSUPP; } return ret; @@ -107,30 +107,19 @@ static int fuse_verify_xattr_list(char *list, size_t size) ssize_t fuse_listxattr(struct dentry *entry, char *list, size_t size) { struct inode *inode = d_inode(entry); - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); struct fuse_getxattr_in inarg; struct fuse_getxattr_out outarg; ssize_t ret; -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_getxattr_io, - fuse_listxattr_initialize, - fuse_listxattr_backing, fuse_listxattr_finalize, - entry, list, size); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (fuse_is_bad(inode)) return -EIO; - if (!fuse_allow_current_process(fm->fc)) + if (!fuse_allow_current_process(fc)) return -EACCES; - if (fm->fc->no_listxattr) + if (fc->no_listxattr) return -EOPNOTSUPP; memset(&inarg, 0, sizeof(inarg)); @@ -150,13 +139,13 @@ ssize_t fuse_listxattr(struct dentry *entry, char *list, size_t size) args.out_args[0].size = sizeof(outarg); args.out_args[0].value = &outarg; } - ret = fuse_simple_request(fm, &args); + ret = fuse_simple_request(fc, &args); if (!ret && !size) ret = min_t(size_t, outarg.size, XATTR_LIST_MAX); if (ret > 0 && size) ret = fuse_verify_xattr_list(list, ret); if (ret == -ENOSYS) { - fm->fc->no_listxattr = 1; + fc->no_listxattr = 1; ret = -EOPNOTSUPP; } return ret; @@ -164,11 +153,11 @@ ssize_t fuse_listxattr(struct dentry *entry, char *list, size_t size) int fuse_removexattr(struct inode *inode, const char *name) { - struct fuse_mount *fm = get_fuse_mount(inode); + struct fuse_conn *fc = get_fuse_conn(inode); FUSE_ARGS(args); int err; - if (fm->fc->no_removexattr) + if (fc->no_removexattr) return -EOPNOTSUPP; args.opcode = FUSE_REMOVEXATTR; @@ -176,9 +165,9 @@ int fuse_removexattr(struct inode *inode, const char *name) args.in_numargs = 1; args.in_args[0].size = strlen(name) + 1; args.in_args[0].value = name; - err = fuse_simple_request(fm, &args); + err = fuse_simple_request(fc, &args); if (err == -ENOSYS) { - fm->fc->no_removexattr = 1; + fc->no_removexattr = 1; err = -EOPNOTSUPP; } if (!err) { @@ -192,17 +181,6 @@ static int fuse_xattr_get(const struct xattr_handler *handler, struct dentry *dentry, struct inode *inode, const char *name, void *value, size_t size, int flags) { -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - fer = fuse_bpf_backing(inode, struct fuse_getxattr_io, - fuse_getxattr_initialize, fuse_getxattr_backing, - fuse_getxattr_finalize, - dentry, name, value, size); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (fuse_is_bad(inode)) return -EIO; @@ -214,24 +192,6 @@ static int fuse_xattr_set(const struct xattr_handler *handler, const char *name, const void *value, size_t size, int flags) { -#ifdef CONFIG_FUSE_BPF - struct fuse_err_ret fer; - - if (value) - fer = fuse_bpf_backing(inode, struct fuse_setxattr_in, - fuse_setxattr_initialize, fuse_setxattr_backing, - fuse_setxattr_finalize, dentry, name, value, - size, flags); - else - fer = fuse_bpf_backing(inode, struct fuse_dummy_io, - fuse_removexattr_initialize, - fuse_removexattr_backing, - fuse_removexattr_finalize, - dentry, name); - if (fer.ret) - return PTR_ERR(fer.result); -#endif - if (fuse_is_bad(inode)) return -EIO; diff --git a/fs/gfs2/dir.c b/fs/gfs2/dir.c index e609ec4b8fdf..eb9c0578978f 100644 --- a/fs/gfs2/dir.c +++ b/fs/gfs2/dir.c @@ -357,7 +357,7 @@ static __be64 *gfs2_dir_get_hash_table(struct gfs2_inode *ip) hc = kmalloc(hsize, GFP_NOFS | __GFP_NOWARN); if (hc == NULL) - hc = __vmalloc(hsize, GFP_NOFS); + hc = __vmalloc(hsize, GFP_NOFS, PAGE_KERNEL); if (hc == NULL) return ERR_PTR(-ENOMEM); @@ -1169,7 +1169,7 @@ static int dir_double_exhash(struct gfs2_inode *dip) hc2 = kmalloc_array(hsize_bytes, 2, GFP_NOFS | __GFP_NOWARN); if (hc2 == NULL) - hc2 = __vmalloc(hsize_bytes * 2, GFP_NOFS); + hc2 = __vmalloc(hsize_bytes * 2, GFP_NOFS, PAGE_KERNEL); if (!hc2) return -ENOMEM; @@ -1330,7 +1330,7 @@ static void *gfs2_alloc_sort_buffer(unsigned size) if (size < KMALLOC_MAX_SIZE) ptr = kmalloc(size, GFP_NOFS | __GFP_NOWARN); if (!ptr) - ptr = __vmalloc(size, GFP_NOFS); + ptr = __vmalloc(size, GFP_NOFS, PAGE_KERNEL); return ptr; } @@ -1990,7 +1990,8 @@ static int leaf_dealloc(struct gfs2_inode *dip, u32 index, u32 len, ht = kzalloc(size, GFP_NOFS | __GFP_NOWARN); if (ht == NULL) - ht = __vmalloc(size, GFP_NOFS | __GFP_NOWARN | __GFP_ZERO); + ht = __vmalloc(size, GFP_NOFS | __GFP_NOWARN | __GFP_ZERO, + PAGE_KERNEL); if (!ht) return -ENOMEM; diff --git a/fs/gfs2/quota.c b/fs/gfs2/quota.c index 7a2dd960ce05..ce3d65787e01 100644 --- a/fs/gfs2/quota.c +++ b/fs/gfs2/quota.c @@ -1366,7 +1366,7 @@ int gfs2_quota_init(struct gfs2_sbd *sdp) sdp->sd_quota_bitmap = kzalloc(bm_size, GFP_NOFS | __GFP_NOWARN); if (sdp->sd_quota_bitmap == NULL) sdp->sd_quota_bitmap = __vmalloc(bm_size, GFP_NOFS | - __GFP_ZERO); + __GFP_ZERO, PAGE_KERNEL); if (!sdp->sd_quota_bitmap) return error; diff --git a/fs/hfs/bfind.c b/fs/hfs/bfind.c index 6d37b4c75903..ef9498a6e88a 100644 --- a/fs/hfs/bfind.c +++ b/fs/hfs/bfind.c @@ -18,7 +18,7 @@ int hfs_find_init(struct hfs_btree *tree, struct hfs_find_data *fd) fd->tree = tree; fd->bnode = NULL; - ptr = kzalloc(tree->max_key_len * 2 + 4, GFP_KERNEL); + ptr = kmalloc(tree->max_key_len * 2 + 4, GFP_KERNEL); if (!ptr) return -ENOMEM; fd->search_key = ptr; @@ -112,12 +112,6 @@ int hfs_brec_find(struct hfs_find_data *fd) __be32 data; int height, res; - fd->record = -1; - fd->keyoffset = -1; - fd->keylength = -1; - fd->entryoffset = -1; - fd->entrylength = -1; - tree = fd->tree; if (fd->bnode) hfs_bnode_put(fd->bnode); diff --git a/fs/hfs/brec.c b/fs/hfs/brec.c index b01db1fae147..896396554bcc 100644 --- a/fs/hfs/brec.c +++ b/fs/hfs/brec.c @@ -179,7 +179,6 @@ int hfs_brec_remove(struct hfs_find_data *fd) struct hfs_btree *tree; struct hfs_bnode *node, *parent; int end_off, rec_off, data_off, size; - int src, dst, len; tree = fd->tree; node = fd->bnode; @@ -209,13 +208,9 @@ again: } hfs_bnode_write_u16(node, offsetof(struct hfs_bnode_desc, num_recs), node->num_recs); - size = fd->keylength + fd->entrylength; - - if (rec_off == end_off) { - src = fd->keyoffset; - hfs_bnode_clear(node, src, size); + if (rec_off == end_off) goto skip; - } + size = fd->keylength + fd->entrylength; do { data_off = hfs_bnode_read_u16(node, rec_off); @@ -224,23 +219,9 @@ again: } while (rec_off >= end_off); /* fill hole */ - dst = fd->keyoffset; - src = fd->keyoffset + size; - len = data_off - src; - - hfs_bnode_move(node, dst, src, len); - - src = dst + len; - len = data_off - src; - - hfs_bnode_clear(node, src, len); - + hfs_bnode_move(node, fd->keyoffset, fd->keyoffset + size, + data_off - fd->keyoffset - size); skip: - /* - * Remove the obsolete offset to free space. - */ - hfs_bnode_write_u16(node, end_off, 0); - hfs_bnode_dump(node); if (!fd->record) hfs_brec_update_parent(fd); diff --git a/fs/hfs/mdb.c b/fs/hfs/mdb.c index 8036445672c5..460281b1299e 100644 --- a/fs/hfs/mdb.c +++ b/fs/hfs/mdb.c @@ -166,7 +166,7 @@ int hfs_mdb_get(struct super_block *sb) pr_warn("continuing without an alternate MDB\n"); } - HFS_SB(sb)->bitmap = kzalloc(8192, GFP_KERNEL); + HFS_SB(sb)->bitmap = kmalloc(8192, GFP_KERNEL); if (!HFS_SB(sb)->bitmap) goto out; diff --git a/fs/hfsplus/bfind.c b/fs/hfsplus/bfind.c index 26ebac4c6042..901e83d65d20 100644 --- a/fs/hfsplus/bfind.c +++ b/fs/hfsplus/bfind.c @@ -18,7 +18,7 @@ int hfs_find_init(struct hfs_btree *tree, struct hfs_find_data *fd) fd->tree = tree; fd->bnode = NULL; - ptr = kzalloc(tree->max_key_len * 2 + 4, GFP_KERNEL); + ptr = kmalloc(tree->max_key_len * 2 + 4, GFP_KERNEL); if (!ptr) return -ENOMEM; fd->search_key = ptr; @@ -158,12 +158,6 @@ int hfs_brec_find(struct hfs_find_data *fd, search_strategy_t do_key_compare) __be32 data; int height, res; - fd->record = -1; - fd->keyoffset = -1; - fd->keylength = -1; - fd->entryoffset = -1; - fd->entrylength = -1; - tree = fd->tree; if (fd->bnode) hfs_bnode_put(fd->bnode); diff --git a/fs/hfsplus/bnode.c b/fs/hfsplus/bnode.c index e566cea23827..c9c38fddf505 100644 --- a/fs/hfsplus/bnode.c +++ b/fs/hfsplus/bnode.c @@ -18,6 +18,47 @@ #include "hfsplus_fs.h" #include "hfsplus_raw.h" +static inline +bool is_bnode_offset_valid(struct hfs_bnode *node, int off) +{ + bool is_valid = off < node->tree->node_size; + + if (!is_valid) { + pr_err("requested invalid offset: " + "NODE: id %u, type %#x, height %u, " + "node_size %u, offset %d\n", + node->this, node->type, node->height, + node->tree->node_size, off); + } + + return is_valid; +} + +static inline +int check_and_correct_requested_length(struct hfs_bnode *node, int off, int len) +{ + unsigned int node_size; + + if (!is_bnode_offset_valid(node, off)) + return 0; + + node_size = node->tree->node_size; + + if ((off + len) > node_size) { + int new_len = (int)node_size - off; + + pr_err("requested length has been corrected: " + "NODE: id %u, type %#x, height %u, " + "node_size %u, offset %d, " + "requested_len %d, corrected_len %d\n", + node->this, node->type, node->height, + node->tree->node_size, off, len, new_len); + + return new_len; + } + + return len; +} /* Copy a specified range of bytes from the raw data of a node */ void hfs_bnode_read(struct hfs_bnode *node, void *buf, int off, int len) diff --git a/fs/hfsplus/btree.c b/fs/hfsplus/btree.c index 2211907537fe..66774f4cb4fd 100644 --- a/fs/hfsplus/btree.c +++ b/fs/hfsplus/btree.c @@ -392,12 +392,6 @@ struct hfs_bnode *hfs_bmap_alloc(struct hfs_btree *tree) len = hfs_brec_lenoff(node, 2, &off16); off = off16; - if (!is_bnode_offset_valid(node, off)) { - hfs_bnode_put(node); - return ERR_PTR(-EIO); - } - len = check_and_correct_requested_length(node, off, len); - off += node->page_offset; pagep = node->page + (off >> PAGE_SHIFT); data = kmap(*pagep); diff --git a/fs/hfsplus/hfsplus_fs.h b/fs/hfsplus/hfsplus_fs.h index 5355d1ff7a9b..86cfc147bf3d 100644 --- a/fs/hfsplus/hfsplus_fs.h +++ b/fs/hfsplus/hfsplus_fs.h @@ -561,48 +561,6 @@ hfsplus_btree_lock_class(struct hfs_btree *tree) return class; } -static inline -bool is_bnode_offset_valid(struct hfs_bnode *node, int off) -{ - bool is_valid = off < node->tree->node_size; - - if (!is_valid) { - pr_err("requested invalid offset: " - "NODE: id %u, type %#x, height %u, " - "node_size %u, offset %d\n", - node->this, node->type, node->height, - node->tree->node_size, off); - } - - return is_valid; -} - -static inline -int check_and_correct_requested_length(struct hfs_bnode *node, int off, int len) -{ - unsigned int node_size; - - if (!is_bnode_offset_valid(node, off)) - return 0; - - node_size = node->tree->node_size; - - if ((off + len) > node_size) { - int new_len = (int)node_size - off; - - pr_err("requested length has been corrected: " - "NODE: id %u, type %#x, height %u, " - "node_size %u, offset %d, " - "requested_len %d, corrected_len %d\n", - node->this, node->type, node->height, - node->tree->node_size, off, len, new_len); - - return new_len; - } - - return len; -} - /* compatibility */ #define hfsp_mt2ut(t) (struct timespec){ .tv_sec = __hfsp_mt2ut(t) } #define hfsp_ut2mt(t) __hfsp_ut2mt((t).tv_sec) diff --git a/fs/hfsplus/super.c b/fs/hfsplus/super.c index db68ed59b4b2..29a39afe2653 100644 --- a/fs/hfsplus/super.c +++ b/fs/hfsplus/super.c @@ -67,26 +67,13 @@ struct inode *hfsplus_iget(struct super_block *sb, unsigned long ino) if (!(inode->i_state & I_NEW)) return inode; - atomic_set(&HFSPLUS_I(inode)->opencnt, 0); - HFSPLUS_I(inode)->first_blocks = 0; - HFSPLUS_I(inode)->clump_blocks = 0; - HFSPLUS_I(inode)->alloc_blocks = 0; - HFSPLUS_I(inode)->cached_start = U32_MAX; - HFSPLUS_I(inode)->cached_blocks = 0; - memset(HFSPLUS_I(inode)->first_extents, 0, sizeof(hfsplus_extent_rec)); - memset(HFSPLUS_I(inode)->cached_extents, 0, sizeof(hfsplus_extent_rec)); - HFSPLUS_I(inode)->extent_state = 0; - mutex_init(&HFSPLUS_I(inode)->extents_lock); - HFSPLUS_I(inode)->rsrc_inode = NULL; - HFSPLUS_I(inode)->create_date = 0; - HFSPLUS_I(inode)->linkid = 0; - HFSPLUS_I(inode)->flags = 0; - HFSPLUS_I(inode)->fs_blocks = 0; - HFSPLUS_I(inode)->userflags = 0; - HFSPLUS_I(inode)->subfolders = 0; INIT_LIST_HEAD(&HFSPLUS_I(inode)->open_dir_list); spin_lock_init(&HFSPLUS_I(inode)->open_dir_lock); - HFSPLUS_I(inode)->phys_size = 0; + mutex_init(&HFSPLUS_I(inode)->extents_lock); + HFSPLUS_I(inode)->flags = 0; + HFSPLUS_I(inode)->extent_state = 0; + HFSPLUS_I(inode)->rsrc_inode = NULL; + atomic_set(&HFSPLUS_I(inode)->opencnt, 0); if (inode->i_ino >= HFSPLUS_FIRSTUSER_CNID || inode->i_ino == HFSPLUS_ROOT_CNID) { @@ -539,7 +526,7 @@ static int hfsplus_fill_super(struct super_block *sb, void *data, int silent) if (!hfs_brec_read(&fd, &entry, sizeof(entry))) { hfs_find_exit(&fd); if (entry.type != cpu_to_be16(HFSPLUS_FOLDER)) { - err = -EIO; + err = -EINVAL; goto out_put_root; } inode = hfsplus_iget(sb, be32_to_cpu(entry.folder.id)); diff --git a/fs/hfsplus/unicode.c b/fs/hfsplus/unicode.c index ebd326799f35..36b6cf2a3abb 100644 --- a/fs/hfsplus/unicode.c +++ b/fs/hfsplus/unicode.c @@ -40,18 +40,6 @@ int hfsplus_strcasecmp(const struct hfsplus_unistr *s1, p1 = s1->unicode; p2 = s2->unicode; - if (len1 > HFSPLUS_MAX_STRLEN) { - len1 = HFSPLUS_MAX_STRLEN; - pr_err("invalid length %u has been corrected to %d\n", - be16_to_cpu(s1->length), len1); - } - - if (len2 > HFSPLUS_MAX_STRLEN) { - len2 = HFSPLUS_MAX_STRLEN; - pr_err("invalid length %u has been corrected to %d\n", - be16_to_cpu(s2->length), len2); - } - while (1) { c1 = c2 = 0; @@ -86,18 +74,6 @@ int hfsplus_strcmp(const struct hfsplus_unistr *s1, p1 = s1->unicode; p2 = s2->unicode; - if (len1 > HFSPLUS_MAX_STRLEN) { - len1 = HFSPLUS_MAX_STRLEN; - pr_err("invalid length %u has been corrected to %d\n", - be16_to_cpu(s1->length), len1); - } - - if (len2 > HFSPLUS_MAX_STRLEN) { - len2 = HFSPLUS_MAX_STRLEN; - pr_err("invalid length %u has been corrected to %d\n", - be16_to_cpu(s2->length), len2); - } - for (len = min(len1, len2); len > 0; len--) { c1 = be16_to_cpu(*p1); c2 = be16_to_cpu(*p2); diff --git a/fs/hpfs/namei.c b/fs/hpfs/namei.c index bc1309ef4cfa..1aee39160ac5 100644 --- a/fs/hpfs/namei.c +++ b/fs/hpfs/namei.c @@ -52,10 +52,8 @@ static int hpfs_mkdir(struct inode *dir, struct dentry *dentry, umode_t mode) dee.fnode = cpu_to_le32(fno); dee.creation_date = dee.write_date = dee.read_date = cpu_to_le32(local_get_seconds(dir->i_sb)); result = new_inode(dir->i_sb); - if (!result) { - err = -ENOMEM; + if (!result) goto bail2; - } hpfs_init_inode(result); result->i_ino = fno; hpfs_i(result)->i_parent_dir = dir->i_ino; @@ -156,10 +154,9 @@ static int hpfs_create(struct inode *dir, struct dentry *dentry, umode_t mode, b dee.creation_date = dee.write_date = dee.read_date = cpu_to_le32(local_get_seconds(dir->i_sb)); result = new_inode(dir->i_sb); - if (!result) { - err = -ENOMEM; + if (!result) goto bail1; - } + hpfs_init_inode(result); result->i_ino = fno; result->i_mode |= S_IFREG; @@ -244,10 +241,9 @@ static int hpfs_mknod(struct inode *dir, struct dentry *dentry, umode_t mode, de dee.creation_date = dee.write_date = dee.read_date = cpu_to_le32(local_get_seconds(dir->i_sb)); result = new_inode(dir->i_sb); - if (!result) { - err = -ENOMEM; + if (!result) goto bail1; - } + hpfs_init_inode(result); result->i_ino = fno; hpfs_i(result)->i_parent_dir = dir->i_ino; @@ -321,10 +317,8 @@ static int hpfs_symlink(struct inode *dir, struct dentry *dentry, const char *sy dee.creation_date = dee.write_date = dee.read_date = cpu_to_le32(local_get_seconds(dir->i_sb)); result = new_inode(dir->i_sb); - if (!result) { - err = -ENOMEM; + if (!result) goto bail1; - } result->i_ino = fno; hpfs_init_inode(result); hpfs_i(result)->i_parent_dir = dir->i_ino; diff --git a/fs/inode.c b/fs/inode.c index 1d9e44bef709..e31e18a5e647 100644 --- a/fs/inode.c +++ b/fs/inode.c @@ -108,7 +108,7 @@ long get_nr_dirty_inodes(void) */ #ifdef CONFIG_SYSCTL int proc_nr_inodes(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { inodes_stat.nr_inodes = get_nr_inodes(); inodes_stat.nr_unused = get_nr_inodes_unused(); diff --git a/fs/jbd2/transaction.c b/fs/jbd2/transaction.c index 97ff68f90d57..72e9297d6adc 100644 --- a/fs/jbd2/transaction.c +++ b/fs/jbd2/transaction.c @@ -1550,7 +1550,6 @@ int jbd2_journal_forget (handle_t *handle, struct buffer_head *bh) int drop_reserve = 0; int err = 0; int was_modified = 0; - int wait_for_writeback = 0; if (is_handle_aborted(handle)) return -EROFS; @@ -1676,22 +1675,18 @@ int jbd2_journal_forget (handle_t *handle, struct buffer_head *bh) } /* - * The buffer has not yet been written to disk. We should - * either clear the buffer or ensure that the ongoing I/O - * is completed, and attach this buffer to current - * transaction so that the buffer can be checkpointed only - * after the current transaction commits. + * The buffer is still not written to disk, we should + * attach this buffer to current transaction so that the + * buffer can be checkpointed only after the current + * transaction commits. */ clear_buffer_dirty(bh); - wait_for_writeback = 1; __jbd2_journal_file_buffer(jh, transaction, BJ_Forget); spin_unlock(&journal->j_list_lock); } jbd_unlock_bh_state(bh); __brelse(bh); - if (wait_for_writeback) - wait_on_buffer(bh); drop: if (drop_reserve) { /* no need to reserve log space for this block -bzzz */ diff --git a/fs/jfs/inode.c b/fs/jfs/inode.c index 0fb502ed7273..6d353fbe67c0 100644 --- a/fs/jfs/inode.c +++ b/fs/jfs/inode.c @@ -59,15 +59,9 @@ struct inode *jfs_iget(struct super_block *sb, unsigned long ino) */ inode->i_link[inode->i_size] = '\0'; } - } else if (S_ISCHR(inode->i_mode) || S_ISBLK(inode->i_mode) || - S_ISFIFO(inode->i_mode) || S_ISSOCK(inode->i_mode)) { + } else { inode->i_op = &jfs_file_inode_operations; init_special_inode(inode, inode->i_mode, inode->i_rdev); - } else { - printk(KERN_DEBUG "JFS: Invalid file type 0%04o for inode %lu.\n", - inode->i_mode, inode->i_ino); - iget_failed(inode); - return ERR_PTR(-EIO); } unlock_new_inode(inode); return inode; diff --git a/fs/jfs/jfs_txnmgr.c b/fs/jfs/jfs_txnmgr.c index 97a2eb0f0b75..6f6a5b9203d3 100644 --- a/fs/jfs/jfs_txnmgr.c +++ b/fs/jfs/jfs_txnmgr.c @@ -272,15 +272,14 @@ int txInit(void) if (TxBlock == NULL) return -ENOMEM; - for (k = 0; k < nTxBlock; k++) { + for (k = 1; k < nTxBlock - 1; k++) { + TxBlock[k].next = k + 1; init_waitqueue_head(&TxBlock[k].gcwait); init_waitqueue_head(&TxBlock[k].waitor); } - - for (k = 1; k < nTxBlock - 1; k++) { - TxBlock[k].next = k + 1; - } TxBlock[k].next = 0; + init_waitqueue_head(&TxBlock[k].gcwait); + init_waitqueue_head(&TxBlock[k].waitor); TxAnchor.freetid = 1; init_waitqueue_head(&TxAnchor.freewait); diff --git a/fs/kernfs/dir.c b/fs/kernfs/dir.c index 4e31444679d7..d3a602ea795b 100644 --- a/fs/kernfs/dir.c +++ b/fs/kernfs/dir.c @@ -544,7 +544,7 @@ void kernfs_put(struct kernfs_node *kn) kmem_cache_free(kernfs_iattrs_cache, kn->iattr); } spin_lock(&kernfs_idr_lock); - idr_remove(&root->ino_idr, kernfs_ino(kn)); + idr_remove(&root->ino_idr, kn->id.ino); spin_unlock(&kernfs_idr_lock); kmem_cache_free(kernfs_node_cache, kn); @@ -651,8 +651,8 @@ static struct kernfs_node *__kernfs_new_node(struct kernfs_root *root, idr_preload_end(); if (ret < 0) goto err_out2; - - kn->id = (u64)gen << 32 | ret; + kn->id.ino = ret; + kn->id.generation = gen; /* * set ino first. This RELEASE is paired with atomic_inc_not_zero in @@ -687,7 +687,7 @@ static struct kernfs_node *__kernfs_new_node(struct kernfs_root *root, return kn; err_out3: - idr_remove(&root->ino_idr, kernfs_ino(kn)); + idr_remove(&root->ino_idr, kn->id.ino); err_out2: kmem_cache_free(kernfs_node_cache, kn); err_out1: @@ -760,7 +760,7 @@ struct kernfs_node *kernfs_find_and_get_node_by_ino(struct kernfs_root *root, * before 'count'. So if 'count' is uptodate, 'ino' should be uptodate, * hence we can use 'ino' to filter stale node. */ - if ((u32)kn->id != ino) + if (kn->id.ino != ino) goto out; rcu_read_unlock(); @@ -1699,7 +1699,7 @@ static int kernfs_fop_readdir(struct file *file, struct dir_context *ctx) const char *name = pos->name; unsigned int type = dt_type(pos); int len = strlen(name); - ino_t ino = kernfs_ino(pos); + ino_t ino = pos->id.ino; ctx->pos = pos->hash; file->private_data = pos; diff --git a/fs/kernfs/file.c b/fs/kernfs/file.c index 2a1879a6e795..c35bbaa19486 100644 --- a/fs/kernfs/file.c +++ b/fs/kernfs/file.c @@ -892,7 +892,7 @@ repeat: * have the matching @file available. Look up the inodes * and generate the events manually. */ - inode = ilookup(info->sb, kernfs_ino(kn)); + inode = ilookup(info->sb, kn->id.ino); if (!inode) continue; @@ -901,7 +901,7 @@ repeat: if (parent) { struct inode *p_inode; - p_inode = ilookup(info->sb, kernfs_ino(parent)); + p_inode = ilookup(info->sb, parent->id.ino); if (p_inode) { fsnotify(p_inode, FS_MODIFY | FS_EVENT_ON_CHILD, inode, FSNOTIFY_EVENT_INODE, &name, 0); diff --git a/fs/kernfs/inode.c b/fs/kernfs/inode.c index e160a5c3b049..22357c69a82b 100644 --- a/fs/kernfs/inode.c +++ b/fs/kernfs/inode.c @@ -53,8 +53,6 @@ static struct kernfs_iattrs *__kernfs_iattrs(struct kernfs_node *kn, int alloc) kn->iattr->ia_ctime = kn->iattr->ia_atime; simple_xattrs_init(&kn->iattr->xattrs); - atomic_set(&kn->iattr->nr_user_xattrs, 0); - atomic_set(&kn->iattr->user_xattr_size, 0); out_unlock: ret = kn->iattr; mutex_unlock(&iattr_mutex); @@ -203,7 +201,7 @@ static void kernfs_init_inode(struct kernfs_node *kn, struct inode *inode) inode->i_private = kn; inode->i_mapping->a_ops = &kernfs_aops; inode->i_op = &kernfs_iops; - inode->i_generation = kernfs_gen(kn); + inode->i_generation = kn->id.generation; set_default_inode_attr(inode, kn->mode); kernfs_refresh_inode(kn, inode); @@ -249,7 +247,7 @@ struct inode *kernfs_get_inode(struct super_block *sb, struct kernfs_node *kn) { struct inode *inode; - inode = iget_locked(sb, kernfs_ino(kn)); + inode = iget_locked(sb, kn->id.ino); if (inode && (inode->i_state & I_NEW)) kernfs_init_inode(kn, inode); @@ -305,7 +303,7 @@ int kernfs_xattr_set(struct kernfs_node *kn, const char *name, if (!attrs) return -ENOMEM; - return simple_xattr_set(&attrs->xattrs, name, value, size, flags, NULL); + return simple_xattr_set(&attrs->xattrs, name, value, size, flags); } static int kernfs_vfs_xattr_get(const struct xattr_handler *handler, @@ -330,86 +328,6 @@ static int kernfs_vfs_xattr_set(const struct xattr_handler *handler, return kernfs_xattr_set(kn, name, value, size, flags); } -static int kernfs_vfs_user_xattr_add(struct kernfs_node *kn, - const char *full_name, - struct simple_xattrs *xattrs, - const void *value, size_t size, int flags) -{ - atomic_t *sz = &kn->iattr->user_xattr_size; - atomic_t *nr = &kn->iattr->nr_user_xattrs; - ssize_t removed_size; - int ret; - - if (atomic_inc_return(nr) > KERNFS_MAX_USER_XATTRS) { - ret = -ENOSPC; - goto dec_count_out; - } - - if (atomic_add_return(size, sz) > KERNFS_USER_XATTR_SIZE_LIMIT) { - ret = -ENOSPC; - goto dec_size_out; - } - - ret = simple_xattr_set(xattrs, full_name, value, size, flags, - &removed_size); - - if (!ret && removed_size >= 0) - size = removed_size; - else if (!ret) - return 0; -dec_size_out: - atomic_sub(size, sz); -dec_count_out: - atomic_dec(nr); - return ret; -} - -static int kernfs_vfs_user_xattr_rm(struct kernfs_node *kn, - const char *full_name, - struct simple_xattrs *xattrs, - const void *value, size_t size, int flags) -{ - atomic_t *sz = &kn->iattr->user_xattr_size; - atomic_t *nr = &kn->iattr->nr_user_xattrs; - ssize_t removed_size; - int ret; - - ret = simple_xattr_set(xattrs, full_name, value, size, flags, - &removed_size); - - if (removed_size >= 0) { - atomic_sub(removed_size, sz); - atomic_dec(nr); - } - - return ret; -} - -static int kernfs_vfs_user_xattr_set(const struct xattr_handler *handler, - struct dentry *unused, struct inode *inode, - const char *suffix, const void *value, - size_t size, int flags) -{ - const char *full_name = xattr_full_name(handler, suffix); - struct kernfs_node *kn = inode->i_private; - struct kernfs_iattrs *attrs; - - if (!(kernfs_root(kn)->flags & KERNFS_ROOT_SUPPORT_USER_XATTR)) - return -EOPNOTSUPP; - - attrs = kernfs_iattrs(kn); - if (!attrs) - return -ENOMEM; - - if (value) - return kernfs_vfs_user_xattr_add(kn, full_name, &attrs->xattrs, - value, size, flags); - else - return kernfs_vfs_user_xattr_rm(kn, full_name, &attrs->xattrs, - value, size, flags); - -} - static const struct xattr_handler kernfs_trusted_xattr_handler = { .prefix = XATTR_TRUSTED_PREFIX, .get = kernfs_vfs_xattr_get, @@ -422,15 +340,8 @@ static const struct xattr_handler kernfs_security_xattr_handler = { .set = kernfs_vfs_xattr_set, }; -static const struct xattr_handler kernfs_user_xattr_handler = { - .prefix = XATTR_USER_PREFIX, - .get = kernfs_vfs_xattr_get, - .set = kernfs_vfs_user_xattr_set, -}; - const struct xattr_handler *kernfs_xattr_handlers[] = { &kernfs_trusted_xattr_handler, &kernfs_security_xattr_handler, - &kernfs_user_xattr_handler, NULL }; diff --git a/fs/kernfs/kernfs-internal.h b/fs/kernfs/kernfs-internal.h index 5e00625e1974..02ce570a9a3c 100644 --- a/fs/kernfs/kernfs-internal.h +++ b/fs/kernfs/kernfs-internal.h @@ -26,8 +26,6 @@ struct kernfs_iattrs { struct timespec64 ia_ctime; struct simple_xattrs xattrs; - atomic_t nr_user_xattrs; - atomic_t user_xattr_size; }; /* +1 to avoid triggering overflow warning when negating it */ diff --git a/fs/kernfs/mount.c b/fs/kernfs/mount.c index 120e530e0550..d62cec6d838d 100644 --- a/fs/kernfs/mount.c +++ b/fs/kernfs/mount.c @@ -57,14 +57,15 @@ const struct super_operations kernfs_sops = { * Similar to kernfs_fh_get_inode, this one gets kernfs node from inode * number and generation */ -struct kernfs_node *kernfs_get_node_by_id(struct kernfs_root *root, u64 id) +struct kernfs_node *kernfs_get_node_by_id(struct kernfs_root *root, + const union kernfs_node_id *id) { struct kernfs_node *kn; - kn = kernfs_find_and_get_node_by_ino(root, kernfs_id_ino(id)); + kn = kernfs_find_and_get_node_by_ino(root, id->ino); if (!kn) return NULL; - if (kernfs_gen(kn) != kernfs_id_gen(id)) { + if (kn->id.generation != id->generation) { kernfs_put(kn); return NULL; } diff --git a/fs/minix/inode.c b/fs/minix/inode.c index c026706aec0c..3fffc709afd4 100644 --- a/fs/minix/inode.c +++ b/fs/minix/inode.c @@ -470,14 +470,8 @@ void minix_set_inode(struct inode *inode, dev_t rdev) inode->i_op = &minix_symlink_inode_operations; inode_nohighmem(inode); inode->i_mapping->a_ops = &minix_aops; - } else if (S_ISCHR(inode->i_mode) || S_ISBLK(inode->i_mode) || - S_ISFIFO(inode->i_mode) || S_ISSOCK(inode->i_mode)) { + } else init_special_inode(inode, inode->i_mode, rdev); - } else { - printk(KERN_DEBUG "MINIX-fs: Invalid file type 0%04o for inode %lu.\n", - inode->i_mode, inode->i_ino); - make_bad_inode(inode); - } } /* diff --git a/fs/namespace.c b/fs/namespace.c index 176bccdf6f30..60c6b7125a17 100644 --- a/fs/namespace.c +++ b/fs/namespace.c @@ -62,15 +62,6 @@ static int __init set_mphash_entries(char *str) } __setup("mphash_entries=", set_mphash_entries); -static char * __initdata initramfs_options; -static int __init initramfs_options_setup(char *str) -{ - initramfs_options = str; - return 1; -} - -__setup("initramfs_options=", initramfs_options_setup); - static u64 event; static DEFINE_IDA(mnt_id_ida); static DEFINE_IDA(mnt_group_ida); @@ -2618,7 +2609,6 @@ static int do_remount(struct path *path, int ms_flags, int sb_flags, if (IS_ERR(fc)) return PTR_ERR(fc); - fc->oldapi = true; err = parse_monolithic_mount_data(fc, data); if (!err) { down_write(&sb->s_umount); @@ -3869,7 +3859,7 @@ static void __init init_mount_tree(void) struct mnt_namespace *ns; struct path root; - mnt = vfs_kern_mount(&rootfs_fs_type, 0, "rootfs", initramfs_options); + mnt = vfs_kern_mount(&rootfs_fs_type, 0, "rootfs", NULL); if (IS_ERR(mnt)) panic("Can't create rootfs"); diff --git a/fs/nfs/blocklayout/extent_tree.c b/fs/nfs/blocklayout/extent_tree.c index 0add0f329816..055ec818eaaa 100644 --- a/fs/nfs/blocklayout/extent_tree.c +++ b/fs/nfs/blocklayout/extent_tree.c @@ -591,7 +591,7 @@ ext_tree_prepare_commit(struct nfs4_layoutcommit_args *arg) if (!arg->layoutupdate_pages) return -ENOMEM; - start_p = __vmalloc(buffer_size, GFP_NOFS); + start_p = __vmalloc(buffer_size, GFP_NOFS, PAGE_KERNEL); if (!start_p) { kfree(arg->layoutupdate_pages); return -ENOMEM; diff --git a/fs/nfs/inode.c b/fs/nfs/inode.c index a4605b17f047..4f0d2fc810e4 100644 --- a/fs/nfs/inode.c +++ b/fs/nfs/inode.c @@ -310,7 +310,7 @@ nfs_find_actor(struct inode *inode, void *opaque) if (NFS_FILEID(inode) != fattr->fileid) return 0; - if (inode_wrong_type(inode, fattr->mode)) + if ((S_IFMT & inode->i_mode) != (S_IFMT & fattr->mode)) return 0; if (nfs_compare_fh(NFS_FH(inode), fh)) return 0; @@ -1418,7 +1418,7 @@ static int nfs_check_inode_attributes(struct inode *inode, struct nfs_fattr *fat return 0; return -ESTALE; } - if ((fattr->valid & NFS_ATTR_FATTR_TYPE) && inode_wrong_type(inode, fattr->mode)) + if ((fattr->valid & NFS_ATTR_FATTR_TYPE) && (inode->i_mode & S_IFMT) != (fattr->mode & S_IFMT)) return -ESTALE; @@ -1834,7 +1834,7 @@ static int nfs_update_inode(struct inode *inode, struct nfs_fattr *fattr) /* * Make sure the inode's type hasn't changed. */ - if ((fattr->valid & NFS_ATTR_FATTR_TYPE) && inode_wrong_type(inode, fattr->mode)) { + if ((fattr->valid & NFS_ATTR_FATTR_TYPE) && (inode->i_mode & S_IFMT) != (fattr->mode & S_IFMT)) { /* * Big trouble! The inode has become a different object. */ diff --git a/fs/nfs/nfs4client.c b/fs/nfs/nfs4client.c index dcef5785c152..eeab44727a76 100644 --- a/fs/nfs/nfs4client.c +++ b/fs/nfs/nfs4client.c @@ -221,7 +221,6 @@ struct nfs_client *nfs4_alloc_client(const struct nfs_client_initdata *cl_init) clp->cl_state = 1 << NFS4CLNT_LEASE_EXPIRED; clp->cl_mvops = nfs_v4_minor_ops[cl_init->minorversion]; clp->cl_mig_gen = 1; - clp->cl_last_renewal = jiffies; #if IS_ENABLED(CONFIG_NFS_V4_1) init_waitqueue_head(&clp->cl_lock_waitq); #endif diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c index 22bb7a459502..2c57b3d7ed5c 100644 --- a/fs/nfs/nfs4proc.c +++ b/fs/nfs/nfs4proc.c @@ -355,9 +355,7 @@ static void nfs4_setup_readdir(u64 cookie, __be32 *verifier, struct dentry *dent *p++ = htonl(attrs); /* bitmap */ *p++ = htonl(12); /* attribute buffer length */ *p++ = htonl(NF4DIR); - spin_lock(&dentry->d_lock); p = xdr_encode_hyper(p, NFS_FILEID(d_inode(dentry->d_parent))); - spin_unlock(&dentry->d_lock); readdir->pgbase = (char *)p - (char *)start; readdir->count -= readdir->pgbase; @@ -7317,10 +7315,10 @@ int nfs4_lock_delegation_recall(struct file_lock *fl, struct nfs4_state *state, return err; do { err = _nfs4_do_setlk(state, F_SETLK, fl, NFS_LOCK_NEW); - if (err != -NFS4ERR_DELAY && err != -NFS4ERR_GRACE) + if (err != -NFS4ERR_DELAY) break; ssleep(1); - } while (err == -NFS4ERR_DELAY || err == -NFSERR_GRACE); + } while (err == -NFS4ERR_DELAY); return nfs4_handle_delegation_recall_error(server, state, stateid, fl, err); } @@ -8690,7 +8688,7 @@ static int nfs4_verify_back_channel_attrs(struct nfs41_create_session_args *args goto out; if (rcvd->max_rqst_sz > sent->max_rqst_sz) return -EINVAL; - if (rcvd->max_resp_sz > sent->max_resp_sz) + if (rcvd->max_resp_sz < sent->max_resp_sz) return -EINVAL; if (rcvd->max_resp_sz_cached > sent->max_resp_sz_cached) return -EINVAL; diff --git a/fs/nfs/nfs4state.c b/fs/nfs/nfs4state.c index 49defb02cc20..b64a3751c3e4 100644 --- a/fs/nfs/nfs4state.c +++ b/fs/nfs/nfs4state.c @@ -2660,9 +2660,6 @@ out_error: case -ENETUNREACH: nfs_mark_client_ready(clp, -EIO); break; - case -EINVAL: - nfs_mark_client_ready(clp, status); - break; default: ssleep(1); break; diff --git a/fs/nfsd/blocklayout.c b/fs/nfsd/blocklayout.c index e620c1662e7b..9bbaa671c079 100644 --- a/fs/nfsd/blocklayout.c +++ b/fs/nfsd/blocklayout.c @@ -120,6 +120,7 @@ static __be32 nfsd4_block_commit_blocks(struct inode *inode, struct nfsd4_layoutcommit *lcp, struct iomap *iomaps, int nr_iomaps) { + loff_t new_size = lcp->lc_last_wr + 1; struct iattr iattr = { .ia_valid = 0 }; int error; @@ -129,9 +130,9 @@ nfsd4_block_commit_blocks(struct inode *inode, struct nfsd4_layoutcommit *lcp, iattr.ia_valid |= ATTR_ATIME | ATTR_CTIME | ATTR_MTIME; iattr.ia_atime = iattr.ia_ctime = iattr.ia_mtime = lcp->lc_mtime; - if (lcp->lc_size_chg) { + if (new_size > i_size_read(inode)) { iattr.ia_valid |= ATTR_SIZE; - iattr.ia_size = lcp->lc_newsize; + iattr.ia_size = new_size; } error = inode->i_sb->s_export_op->commit_blocks(inode, iomaps, diff --git a/fs/nfsd/flexfilelayout.c b/fs/nfsd/flexfilelayout.c index c2e1a985412c..db7ef07ae50c 100644 --- a/fs/nfsd/flexfilelayout.c +++ b/fs/nfsd/flexfilelayout.c @@ -124,13 +124,6 @@ nfsd4_ff_proc_getdeviceinfo(struct super_block *sb, struct svc_rqst *rqstp, return 0; } -static __be32 -nfsd4_ff_proc_layoutcommit(struct inode *inode, - struct nfsd4_layoutcommit *lcp) -{ - return nfs_ok; -} - const struct nfsd4_layout_ops ff_layout_ops = { .notify_types = NOTIFY_DEVICEID4_DELETE | NOTIFY_DEVICEID4_CHANGE, @@ -139,5 +132,4 @@ const struct nfsd4_layout_ops ff_layout_ops = { .encode_getdeviceinfo = nfsd4_ff_encode_getdeviceinfo, .proc_layoutget = nfsd4_ff_proc_layoutget, .encode_layoutget = nfsd4_ff_encode_layoutget, - .proc_layoutcommit = nfsd4_ff_proc_layoutcommit, }; diff --git a/fs/nfsd/lockd.c b/fs/nfsd/lockd.c index 64797df7aee4..3f5b3d7b62b7 100644 --- a/fs/nfsd/lockd.c +++ b/fs/nfsd/lockd.c @@ -44,21 +44,6 @@ nlm_fopen(struct svc_rqst *rqstp, struct nfs_fh *f, struct file **filp) switch (nfserr) { case nfs_ok: return 0; - case nfserr_jukebox: - /* this error can indicate a presence of a conflicting - * delegation to an NLM lock request. Options are: - * (1) For now, drop this request and make the client - * retry. When delegation is returned, client's lock retry - * will complete. - * (2) NLM4_DENIED as per "spec" signals to the client - * that the lock is unavailable now but client can retry. - * Linux client implementation does not. It treats - * NLM4_DENIED same as NLM4_FAILED and errors the request. - * (3) For the future, treat this as blocked lock and try - * to callback when the delegation is returned but might - * not have a proper lock request to block on. - */ - fallthrough; case nfserr_dropit: return nlm_drop_reply; case nfserr_stale: diff --git a/fs/nfsd/nfs4proc.c b/fs/nfsd/nfs4proc.c index df1a86dff571..527d6b29dffb 100644 --- a/fs/nfsd/nfs4proc.c +++ b/fs/nfsd/nfs4proc.c @@ -1701,6 +1701,7 @@ nfsd4_layoutcommit(struct svc_rqst *rqstp, const struct nfsd4_layout_seg *seg = &lcp->lc_seg; struct svc_fh *current_fh = &cstate->current_fh; const struct nfsd4_layout_ops *ops; + loff_t new_size = lcp->lc_last_wr + 1; struct inode *inode; struct nfs4_layout_stateid *ls; __be32 nfserr; @@ -1715,20 +1716,18 @@ nfsd4_layoutcommit(struct svc_rqst *rqstp, goto out; inode = d_inode(current_fh->fh_dentry); - lcp->lc_size_chg = false; - if (lcp->lc_newoffset) { - loff_t new_size = lcp->lc_last_wr + 1; - - nfserr = nfserr_inval; - if (new_size <= seg->offset) - goto out; - if (new_size > seg->offset + seg->length) - goto out; - - if (new_size > i_size_read(inode)) { - lcp->lc_size_chg = true; - lcp->lc_newsize = new_size; - } + nfserr = nfserr_inval; + if (new_size <= seg->offset) { + dprintk("pnfsd: last write before layout segment\n"); + goto out; + } + if (new_size > seg->offset + seg->length) { + dprintk("pnfsd: last write beyond layout segment\n"); + goto out; + } + if (!lcp->lc_newoffset && new_size > i_size_read(inode)) { + dprintk("pnfsd: layoutcommit beyond EOF\n"); + goto out; } nfserr = nfsd4_preprocess_layout_stateid(rqstp, cstate, &lcp->lc_sid, @@ -1745,6 +1744,13 @@ nfsd4_layoutcommit(struct svc_rqst *rqstp, /* LAYOUTCOMMIT does not require any serialization */ mutex_unlock(&ls->ls_mutex); + if (new_size > i_size_read(inode)) { + lcp->lc_size_chg = 1; + lcp->lc_newsize = new_size; + } else { + lcp->lc_size_chg = 0; + } + nfserr = ops->proc_layoutcommit(inode, lcp); nfs4_put_stid(&ls->ls_stid); out: diff --git a/fs/nfsd/nfsproc.c b/fs/nfsd/nfsproc.c index 5f6186b2ca9b..4aca93e11af7 100644 --- a/fs/nfsd/nfsproc.c +++ b/fs/nfsd/nfsproc.c @@ -376,7 +376,7 @@ nfsd_proc_create(struct svc_rqst *rqstp) /* Make sure the type and device matches */ nfserr = nfserr_exist; - if (inode && inode_wrong_type(inode, type)) + if (inode && type != (inode->i_mode & S_IFMT)) goto out_unlock; } diff --git a/fs/notify/fanotify/fanotify_user.c b/fs/notify/fanotify/fanotify_user.c index e774f7851bc0..ec4eadf459ae 100644 --- a/fs/notify/fanotify/fanotify_user.c +++ b/fs/notify/fanotify/fanotify_user.c @@ -523,7 +523,7 @@ static const struct file_operations fanotify_fops = { .fasync = NULL, .release = fanotify_release, .unlocked_ioctl = fanotify_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = fanotify_ioctl, .llseek = noop_llseek, }; diff --git a/fs/nsfs.c b/fs/nsfs.c index 30c842b4228a..a0431642c6b5 100644 --- a/fs/nsfs.c +++ b/fs/nsfs.c @@ -52,7 +52,7 @@ static void nsfs_evict(struct inode *inode) ns->ops->put(ns); } -static int __ns_get_path(struct path *path, struct ns_common *ns) +static void *__ns_get_path(struct path *path, struct ns_common *ns) { struct vfsmount *mnt = nsfs_mnt; struct dentry *dentry; @@ -71,13 +71,13 @@ static int __ns_get_path(struct path *path, struct ns_common *ns) got_it: path->mnt = mntget(mnt); path->dentry = dentry; - return 0; + return NULL; slow: rcu_read_unlock(); inode = new_inode_pseudo(mnt->mnt_sb); if (!inode) { ns->ops->put(ns); - return -ENOMEM; + return ERR_PTR(-ENOMEM); } inode->i_ino = ns->inum; inode->i_mtime = inode->i_atime = inode->i_ctime = current_time(inode); @@ -89,7 +89,7 @@ slow: dentry = d_alloc_anon(mnt->mnt_sb); if (!dentry) { iput(inode); - return -ENOMEM; + return ERR_PTR(-ENOMEM); } d_instantiate(dentry, inode); dentry->d_fsdata = (void *)ns->ops; @@ -98,22 +98,23 @@ slow: d_delete(dentry); /* make sure ->d_prune() does nothing */ dput(dentry); cpu_relax(); - return -EAGAIN; + return ERR_PTR(-EAGAIN); } goto got_it; } -int ns_get_path_cb(struct path *path, ns_get_path_helper_t *ns_get_cb, +void *ns_get_path_cb(struct path *path, ns_get_path_helper_t *ns_get_cb, void *private_data) { - int ret; + void *ret; do { struct ns_common *ns = ns_get_cb(private_data); if (!ns) - return -ENOENT; + return ERR_PTR(-ENOENT); + ret = __ns_get_path(path, ns); - } while (ret == -EAGAIN); + } while (ret == ERR_PTR(-EAGAIN)); return ret; } @@ -130,7 +131,7 @@ static struct ns_common *ns_get_path_task(void *private_data) return args->ns_ops->get(args->task); } -int ns_get_path(struct path *path, struct task_struct *task, +void *ns_get_path(struct path *path, struct task_struct *task, const struct proc_ns_operations *ns_ops) { struct ns_get_path_task_args args = { @@ -146,7 +147,7 @@ int open_related_ns(struct ns_common *ns, { struct path path = {}; struct file *f; - int err; + void *err; int fd; fd = get_unused_fd_flags(O_CLOEXEC); @@ -163,11 +164,11 @@ int open_related_ns(struct ns_common *ns, } err = __ns_get_path(&path, relative); - } while (err == -EAGAIN); + } while (err == ERR_PTR(-EAGAIN)); - if (err) { + if (IS_ERR(err)) { put_unused_fd(fd); - return err; + return PTR_ERR(err); } f = dentry_open(&path, O_RDONLY, current_cred()); @@ -244,20 +245,6 @@ out_invalid: return ERR_PTR(-EINVAL); } -/** - * ns_match() - Returns true if current namespace matches dev/ino provided. - * @ns_common: current ns - * @dev: dev_t from nsfs that will be matched against current nsfs - * @ino: ino_t from nsfs that will be matched against current nsfs - * - * Return: true if dev and ino matches the current nsfs. - */ -bool ns_match(const struct ns_common *ns, dev_t dev, ino_t ino) -{ - return (ns->inum == ino) && (nsfs_mnt->mnt_sb->s_dev == dev); -} - - static int nsfs_show_path(struct seq_file *seq, struct dentry *dentry) { struct inode *inode = d_inode(dentry); diff --git a/fs/ntfs/malloc.h b/fs/ntfs/malloc.h index 7068425735f1..842b0bfc3ac9 100644 --- a/fs/ntfs/malloc.h +++ b/fs/ntfs/malloc.h @@ -34,7 +34,7 @@ static inline void *__ntfs_malloc(unsigned long size, gfp_t gfp_mask) /* return (void *)__get_free_page(gfp_mask); */ } if (likely((size >> PAGE_SHIFT) < totalram_pages())) - return __vmalloc(size, gfp_mask); + return __vmalloc(size, gfp_mask, PAGE_KERNEL); return NULL; } diff --git a/fs/ocfs2/move_extents.c b/fs/ocfs2/move_extents.c index 3cc28afe9815..98e77ea957ff 100644 --- a/fs/ocfs2/move_extents.c +++ b/fs/ocfs2/move_extents.c @@ -870,11 +870,6 @@ static int __ocfs2_move_extents_range(struct buffer_head *di_bh, mlog_errno(ret); goto out; } - /* - * Invalidate extent cache after moving/defragging to prevent - * stale cached data with outdated extent flags. - */ - ocfs2_extent_map_trunc(inode, cpos); context->clusters_moved += alloc_size; next: diff --git a/fs/ocfs2/stack_user.c b/fs/ocfs2/stack_user.c index c7a0625954c6..7397064c3f35 100644 --- a/fs/ocfs2/stack_user.c +++ b/fs/ocfs2/stack_user.c @@ -1032,7 +1032,6 @@ static int user_cluster_connect(struct ocfs2_cluster_connection *conn) printk(KERN_ERR "ocfs2: Could not determine" " locking version\n"); user_cluster_disconnect(conn); - lc = NULL; goto out; } wait_event(lc->oc_wait, (atomic_read(&lc->oc_this_node) > 0)); diff --git a/fs/open.c b/fs/open.c index 3f9f5fda8ebf..5c0043d4b807 100644 --- a/fs/open.c +++ b/fs/open.c @@ -886,20 +886,18 @@ EXPORT_SYMBOL(finish_open); * finish_no_open - finish ->atomic_open() without opening the file * * @file: file pointer - * @dentry: dentry, ERR_PTR(-E...) or NULL (as returned from ->lookup()) + * @dentry: dentry or NULL (as returned from ->lookup()) * - * This can be used to set the result of a lookup in ->atomic_open(). + * This can be used to set the result of a successful lookup in ->atomic_open(). * * NB: unlike finish_open() this function does consume the dentry reference and * the caller need not dput() it. * - * Returns 0 or -E..., which must be the return value of ->atomic_open() after - * having called this function. + * Returns "0" which must be the return value of ->atomic_open() after having + * called this function. */ int finish_no_open(struct file *file, struct dentry *dentry) { - if (IS_ERR(dentry)) - return PTR_ERR(dentry); file->f_path.dentry = dentry; return 0; } @@ -1211,23 +1209,6 @@ SYSCALL_DEFINE1(close, unsigned int, fd) return retval; } -/** - * close_range() - Close all file descriptors in a given range. - * - * @fd: starting file descriptor to close - * @max_fd: last file descriptor to close - * @flags: reserved for future extensions - * - * This closes a range of file descriptors. All file descriptors - * from @fd up to and including @max_fd are closed. - * Currently, errors to close a given file descriptor are ignored. - */ -SYSCALL_DEFINE3(close_range, unsigned int, fd, unsigned int, max_fd, - unsigned int, flags) -{ - return __close_range(fd, max_fd, flags); -} - /* * This routine simulates a hangup on the tty, to arrange that users * are given clean terminals at login time. diff --git a/fs/orangefs/xattr.c b/fs/orangefs/xattr.c index 61a76b5afb43..ef4180bff7bb 100644 --- a/fs/orangefs/xattr.c +++ b/fs/orangefs/xattr.c @@ -54,9 +54,7 @@ static inline int convert_to_internal_xattr_flags(int setxattr_flags) static unsigned int xattr_key(const char *key) { unsigned int i = 0; - if (!key) - return 0; - while (*key) + while (key) i += *key++; return i % 16; } @@ -177,8 +175,8 @@ ssize_t orangefs_inode_getxattr(struct inode *inode, const char *name, cx->length = -1; cx->timeout = jiffies + orangefs_getattr_timeout_msecs*HZ/1000; - hlist_add_head( &cx->node, - &orangefs_inode->xattr_cache[xattr_key(cx->key)]); + hash_add(orangefs_inode->xattr_cache, &cx->node, + xattr_key(cx->key)); } } goto out_release_op; @@ -231,8 +229,8 @@ ssize_t orangefs_inode_getxattr(struct inode *inode, const char *name, memcpy(cx->val, buffer, length); cx->length = length; cx->timeout = jiffies + HZ; - hlist_add_head(&cx->node, - &orangefs_inode->xattr_cache[xattr_key(cx->key)]); + hash_add(orangefs_inode->xattr_cache, &cx->node, + xattr_key(cx->key)); } } diff --git a/fs/overlayfs/namei.c b/fs/overlayfs/namei.c index f7f259614143..bcfb0b11b819 100644 --- a/fs/overlayfs/namei.c +++ b/fs/overlayfs/namei.c @@ -345,7 +345,7 @@ int ovl_check_origin_fh(struct ovl_fs *ofs, struct ovl_fh *fh, bool connected, return PTR_ERR(origin); if (upperdentry && !ovl_is_whiteout(upperdentry) && - inode_wrong_type(d_inode(upperdentry), d_inode(origin)->i_mode)) + ((d_inode(origin)->i_mode ^ d_inode(upperdentry)->i_mode) & S_IFMT)) goto invalid; if (!*stackp) @@ -717,7 +717,7 @@ struct dentry *ovl_lookup_index(struct ovl_fs *ofs, struct dentry *upper, index = ERR_PTR(-ESTALE); goto out; } else if (ovl_dentry_weird(index) || ovl_is_whiteout(index) || - inode_wrong_type(inode, d_inode(origin)->i_mode)) { + ((inode->i_mode ^ d_inode(origin)->i_mode) & S_IFMT)) { /* * Index should always be of the same file type as origin * except for the case of a whiteout index. A whiteout diff --git a/fs/proc/array.c b/fs/proc/array.c index be8a186d21ad..46dcb6f0eccf 100644 --- a/fs/proc/array.c +++ b/fs/proc/array.c @@ -342,10 +342,6 @@ static inline void task_seccomp(struct seq_file *m, struct task_struct *p) seq_put_decimal_ull(m, "NoNewPrivs:\t", task_no_new_privs(p)); #ifdef CONFIG_SECCOMP seq_put_decimal_ull(m, "\nSeccomp:\t", p->seccomp.mode); -#ifdef CONFIG_SECCOMP_FILTER - seq_put_decimal_ull(m, "\nSeccomp_filters:\t", - atomic_read(&p->seccomp.filter_count)); -#endif #endif seq_puts(m, "\nSpeculation_Store_Bypass:\t"); switch (arch_prctl_spec_ctrl_get(p, PR_SPEC_STORE_BYPASS)) { diff --git a/fs/proc/base.c b/fs/proc/base.c index 791ade1d1019..6cac23a218a5 100644 --- a/fs/proc/base.c +++ b/fs/proc/base.c @@ -2211,16 +2211,16 @@ struct map_files_info { }; /* - * Only allow CAP_SYS_ADMIN and CAP_CHECKPOINT_RESTORE to follow the links, due - * to concerns about how the symlinks may be used to bypass permissions on - * ancestor directories in the path to the file in question. + * Only allow CAP_SYS_ADMIN to follow the links, due to concerns about how the + * symlinks may be used to bypass permissions on ancestor directories in the + * path to the file in question. */ static const char * proc_map_files_get_link(struct dentry *dentry, struct inode *inode, struct delayed_call *done) { - if (!checkpoint_restore_ns_capable(&init_user_ns)) + if (!capable(CAP_SYS_ADMIN)) return ERR_PTR(-EPERM); return proc_pid_get_link(dentry, inode, done); @@ -3330,7 +3330,7 @@ static const struct pid_entry tgid_base_stuff[] = { DIR("task", S_IRUGO|S_IXUGO, proc_task_inode_operations, proc_task_operations), DIR("fd", S_IRUSR|S_IXUSR, proc_fd_inode_operations, proc_fd_operations), DIR("map_files", S_IRUSR|S_IXUSR, proc_map_files_inode_operations, proc_map_files_operations), - DIR("fdinfo", S_IRUGO|S_IXUGO, proc_fdinfo_inode_operations, proc_fdinfo_operations), + DIR("fdinfo", S_IRUSR|S_IXUSR, proc_fdinfo_inode_operations, proc_fdinfo_operations), DIR("ns", S_IRUSR|S_IXUGO, proc_ns_dir_inode_operations, proc_ns_dir_operations), #ifdef CONFIG_NET DIR("net", S_IRUGO|S_IXUGO, proc_net_inode_operations, proc_net_operations), @@ -3750,7 +3750,7 @@ static const struct inode_operations proc_tid_comm_inode_operations = { */ static const struct pid_entry tid_base_stuff[] = { DIR("fd", S_IRUSR|S_IXUSR, proc_fd_inode_operations, proc_fd_operations), - DIR("fdinfo", S_IRUGO|S_IXUGO, proc_fdinfo_inode_operations, proc_fdinfo_operations), + DIR("fdinfo", S_IRUSR|S_IXUSR, proc_fdinfo_inode_operations, proc_fdinfo_operations), DIR("ns", S_IRUSR|S_IXUGO, proc_ns_dir_inode_operations, proc_ns_dir_operations), #ifdef CONFIG_NET DIR("net", S_IRUGO|S_IXUGO, proc_net_inode_operations, proc_net_operations), diff --git a/fs/proc/fd.c b/fs/proc/fd.c index 6b634c0a9b6e..81882a13212d 100644 --- a/fs/proc/fd.c +++ b/fs/proc/fd.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -54,10 +53,9 @@ static int seq_show(struct seq_file *m, void *v) if (ret) return ret; - seq_printf(m, "pos:\t%lli\nflags:\t0%o\nmnt_id:\t%i\nino:\t%lu\n", + seq_printf(m, "pos:\t%lli\nflags:\t0%o\nmnt_id:\t%i\n", (long long)file->f_pos, f_flags, - real_mount(file->f_path.mnt)->mnt_id, - file_inode(file)->i_ino); + real_mount(file->f_path.mnt)->mnt_id); show_fd_locks(m, file, files); if (seq_has_overflowed(m)) @@ -71,30 +69,8 @@ out: return 0; } -static int proc_fdinfo_access_allowed(struct inode *inode) -{ - bool allowed = false; - struct task_struct *task = get_proc_task(inode); - - if (!task) - return -ESRCH; - - allowed = ptrace_may_access(task, PTRACE_MODE_READ_FSCREDS); - put_task_struct(task); - - if (!allowed) - return -EACCES; - - return 0; -} - static int seq_fdinfo_open(struct inode *inode, struct file *file) { - int ret = proc_fdinfo_access_allowed(inode); - - if (ret) - return ret; - return single_open(file, seq_show, inode); } @@ -349,7 +325,7 @@ static struct dentry *proc_fdinfo_instantiate(struct dentry *dentry, struct proc_inode *ei; struct inode *inode; - inode = proc_pid_make_inode(dentry->d_sb, task, S_IFREG | S_IRUGO); + inode = proc_pid_make_inode(dentry->d_sb, task, S_IFREG | S_IRUSR); if (!inode) return ERR_PTR(-ENOENT); @@ -375,23 +351,12 @@ static int proc_readfdinfo(struct file *file, struct dir_context *ctx) proc_fdinfo_instantiate); } -static int proc_open_fdinfo(struct inode *inode, struct file *file) -{ - int ret = proc_fdinfo_access_allowed(inode); - - if (ret) - return ret; - - return 0; -} - const struct inode_operations proc_fdinfo_inode_operations = { .lookup = proc_lookupfdinfo, .setattr = proc_setattr, }; const struct file_operations proc_fdinfo_operations = { - .open = proc_open_fdinfo, .read = generic_read_dir, .iterate_shared = proc_readfdinfo, .llseek = generic_file_llseek, diff --git a/fs/proc/generic.c b/fs/proc/generic.c index c4a7d96787f3..372b4dad4863 100644 --- a/fs/proc/generic.c +++ b/fs/proc/generic.c @@ -671,12 +671,6 @@ void pde_put(struct proc_dir_entry *pde) } } -static void pde_erase(struct proc_dir_entry *pde, struct proc_dir_entry *parent) -{ - rb_erase(&pde->subdir_node, &parent->subdir); - RB_CLEAR_NODE(&pde->subdir_node); -} - /* * Remove a /proc entry and free it if it's not currently in use. */ @@ -695,7 +689,7 @@ void remove_proc_entry(const char *name, struct proc_dir_entry *parent) de = pde_subdir_find(parent, fn, len); if (de) { - pde_erase(de, parent); + rb_erase(&de->subdir_node, &parent->subdir); if (S_ISDIR(de->mode)) { parent->nlink--; } @@ -733,13 +727,13 @@ int remove_proc_subtree(const char *name, struct proc_dir_entry *parent) write_unlock(&proc_subdir_lock); return -ENOENT; } - pde_erase(root, parent); + rb_erase(&root->subdir_node, &parent->subdir); de = root; while (1) { next = pde_subdir_first(de); if (next) { - pde_erase(next, de); + rb_erase(&next->subdir_node, &de->subdir); de = next; continue; } diff --git a/fs/proc/kcore.c b/fs/proc/kcore.c index f22e642f881e..d1cabccc02b7 100644 --- a/fs/proc/kcore.c +++ b/fs/proc/kcore.c @@ -510,8 +510,7 @@ read_kcore(struct file *file, char __user *buffer, size_t buflen, loff_t *fpos) * Using bounce buffer to bypass the * hardened user copy kernel text checks. */ - if (copy_from_kernel_nofault(buf, (void *)start, - tsz)) { + if (probe_kernel_read(buf, (void *) start, tsz)) { if (clear_user(buffer, tsz)) { ret = -EFAULT; goto out; diff --git a/fs/proc/namespaces.c b/fs/proc/namespaces.c index 08dd94df1a66..dd2b35f78b09 100644 --- a/fs/proc/namespaces.c +++ b/fs/proc/namespaces.c @@ -42,14 +42,14 @@ static const char *proc_ns_get_link(struct dentry *dentry, const struct proc_ns_operations *ns_ops = PROC_I(inode)->ns_ops; struct task_struct *task; struct path ns_path; - int error = -EACCES; + void *error = ERR_PTR(-EACCES); if (!dentry) return ERR_PTR(-ECHILD); task = get_proc_task(inode); if (!task) - return ERR_PTR(-EACCES); + return error; if (ptrace_may_access(task, PTRACE_MODE_READ_FSCREDS)) { error = ns_get_path(&ns_path, task, ns_ops); @@ -57,7 +57,7 @@ static const char *proc_ns_get_link(struct dentry *dentry, nd_jump_link(&ns_path); } put_task_struct(task); - return ERR_PTR(error); + return error; } static int proc_ns_readlink(struct dentry *dentry, char __user *buffer, int buflen) diff --git a/fs/proc/proc_net.c b/fs/proc/proc_net.c index be90c3cf67d0..9cd5b47199cb 100644 --- a/fs/proc/proc_net.c +++ b/fs/proc/proc_net.c @@ -82,25 +82,6 @@ static const struct file_operations proc_net_seq_fops = { .release = seq_release_net, }; -int bpf_iter_init_seq_net(void *priv_data, struct bpf_iter_aux_info *aux) -{ -#ifdef CONFIG_NET_NS - struct seq_net_private *p = priv_data; - - p->net = get_net(current->nsproxy->net_ns); -#endif - return 0; -} - -void bpf_iter_fini_seq_net(void *priv_data) -{ -#ifdef CONFIG_NET_NS - struct seq_net_private *p = priv_data; - - put_net(p->net); -#endif -} - struct proc_dir_entry *proc_create_net_data(const char *name, umode_t mode, struct proc_dir_entry *parent, const struct seq_operations *ops, unsigned int state_size, void *data) diff --git a/fs/proc/proc_sysctl.c b/fs/proc/proc_sysctl.c index 7bcbf2b84055..c8dad2006980 100644 --- a/fs/proc/proc_sysctl.c +++ b/fs/proc/proc_sysctl.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -574,14 +573,13 @@ out: return err; } -static ssize_t proc_sys_call_handler(struct kiocb *iocb, struct iov_iter *iter, - int write) +static ssize_t proc_sys_call_handler(struct file *filp, void __user *buf, + size_t count, loff_t *ppos, int write) { - struct inode *inode = file_inode(iocb->ki_filp); + struct inode *inode = file_inode(filp); struct ctl_table_header *head = grab_header(inode); struct ctl_table *table = PROC_I(inode)->sysctl_entry; - size_t count = iov_iter_count(iter); - char *kbuf; + void *new_buf = NULL; ssize_t error; if (IS_ERR(head)) @@ -600,54 +598,43 @@ static ssize_t proc_sys_call_handler(struct kiocb *iocb, struct iov_iter *iter, if (!table->proc_handler) goto out; - /* don't even try if the size is too large */ - error = -ENOMEM; - if (count >= KMALLOC_MAX_SIZE) - goto out; - kbuf = kvzalloc(count + 1, GFP_KERNEL); - if (!kbuf) - goto out; - - if (write) { - error = -EFAULT; - if (!copy_from_iter_full(kbuf, count, iter)) - goto out_free_buf; - kbuf[count] = '\0'; - } - - error = BPF_CGROUP_RUN_PROG_SYSCTL(head, table, write, &kbuf, &count, - &iocb->ki_pos); + error = BPF_CGROUP_RUN_PROG_SYSCTL(head, table, write, buf, &count, + ppos, &new_buf); if (error) - goto out_free_buf; + goto out; /* careful: calling conventions are nasty here */ - error = table->proc_handler(table, write, kbuf, &count, &iocb->ki_pos); - if (error) - goto out_free_buf; + if (new_buf) { + mm_segment_t old_fs; - if (!write) { - error = -EFAULT; - if (copy_to_iter(kbuf, count, iter) < count) - goto out_free_buf; + old_fs = get_fs(); + set_fs(KERNEL_DS); + error = table->proc_handler(table, write, (void __user *)new_buf, + &count, ppos); + set_fs(old_fs); + kfree(new_buf); + } else { + error = table->proc_handler(table, write, buf, &count, ppos); } - error = count; -out_free_buf: - kvfree(kbuf); + if (!error) + error = count; out: sysctl_head_finish(head); return error; } -static ssize_t proc_sys_read(struct kiocb *iocb, struct iov_iter *iter) +static ssize_t proc_sys_read(struct file *filp, char __user *buf, + size_t count, loff_t *ppos) { - return proc_sys_call_handler(iocb, iter, 0); + return proc_sys_call_handler(filp, (void __user *)buf, count, ppos, 0); } -static ssize_t proc_sys_write(struct kiocb *iocb, struct iov_iter *iter) +static ssize_t proc_sys_write(struct file *filp, const char __user *buf, + size_t count, loff_t *ppos) { - return proc_sys_call_handler(iocb, iter, 1); + return proc_sys_call_handler(filp, (void __user *)buf, count, ppos, 1); } static int proc_sys_open(struct inode *inode, struct file *filp) @@ -884,10 +871,8 @@ static int proc_sys_getattr(const struct path *path, struct kstat *stat, static const struct file_operations proc_sys_file_operations = { .open = proc_sys_open, .poll = proc_sys_poll, - .read_iter = proc_sys_read, - .write_iter = proc_sys_write, - .splice_read = generic_file_splice_read, - .splice_write = iter_file_splice_write, + .read = proc_sys_read, + .write = proc_sys_write, .llseek = default_llseek, }; diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c index 163b1c501e52..42c2ac0cc8fc 100644 --- a/fs/quota/dquot.c +++ b/fs/quota/dquot.c @@ -2947,7 +2947,7 @@ const struct quotactl_ops dquot_quotactl_sysfile_ops = { EXPORT_SYMBOL(dquot_quotactl_sysfile_ops); static int do_proc_dqstats(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { unsigned int type = (unsigned long *)table->data - dqstats.stat; s64 value = percpu_counter_sum(&dqstats.counter[type]); diff --git a/fs/read_write.c b/fs/read_write.c index 301c4a4ba1d0..93d06b4c5f78 100644 --- a/fs/read_write.c +++ b/fs/read_write.c @@ -939,34 +939,6 @@ out: return ret; } -ssize_t vfs_iocb_iter_read(struct file *file, struct kiocb *iocb, - struct iov_iter *iter) -{ - size_t tot_len; - ssize_t ret = 0; - - if (!file->f_op->read_iter) - return -EINVAL; - if (!(file->f_mode & FMODE_READ)) - return -EBADF; - if (!(file->f_mode & FMODE_CAN_READ)) - return -EINVAL; - - tot_len = iov_iter_count(iter); - if (!tot_len) - goto out; - ret = rw_verify_area(READ, file, &iocb->ki_pos, tot_len); - if (ret < 0) - return ret; - - ret = call_read_iter(file, iocb, iter); -out: - if (ret >= 0) - fsnotify_access(file); - return ret; -} -EXPORT_SYMBOL(vfs_iocb_iter_read); - ssize_t vfs_iter_read(struct file *file, struct iov_iter *iter, loff_t *ppos, rwf_t flags) { @@ -1003,34 +975,6 @@ static ssize_t do_iter_write(struct file *file, struct iov_iter *iter, return ret; } -ssize_t vfs_iocb_iter_write(struct file *file, struct kiocb *iocb, - struct iov_iter *iter) -{ - size_t tot_len; - ssize_t ret = 0; - - if (!file->f_op->write_iter) - return -EINVAL; - if (!(file->f_mode & FMODE_WRITE)) - return -EBADF; - if (!(file->f_mode & FMODE_CAN_WRITE)) - return -EINVAL; - - tot_len = iov_iter_count(iter); - if (!tot_len) - return 0; - ret = rw_verify_area(WRITE, file, &iocb->ki_pos, tot_len); - if (ret < 0) - return ret; - - ret = call_write_iter(file, iocb, iter); - if (ret > 0) - fsnotify_modify(file); - - return ret; -} -EXPORT_SYMBOL(vfs_iocb_iter_write); - ssize_t vfs_iter_write(struct file *file, struct iov_iter *iter, loff_t *ppos, rwf_t flags) { diff --git a/fs/squashfs/inode.c b/fs/squashfs/inode.c index 42c97c68db63..95a9ff9e2399 100644 --- a/fs/squashfs/inode.c +++ b/fs/squashfs/inode.c @@ -140,17 +140,8 @@ int squashfs_read_inode(struct inode *inode, long long ino) if (err < 0) goto failed_read; - inode->i_size = le32_to_cpu(sqsh_ino->file_size); frag = le32_to_cpu(sqsh_ino->fragment); if (frag != SQUASHFS_INVALID_FRAG) { - /* - * the file cannot have a fragment (tailend) and have a - * file size a multiple of the block size - */ - if ((inode->i_size & (msblk->block_size - 1)) == 0) { - err = -EINVAL; - goto failed_read; - } frag_offset = le32_to_cpu(sqsh_ino->offset); frag_size = squashfs_frag_lookup(sb, frag, &frag_blk); if (frag_size < 0) { @@ -164,6 +155,7 @@ int squashfs_read_inode(struct inode *inode, long long ino) } set_nlink(inode, 1); + inode->i_size = le32_to_cpu(sqsh_ino->file_size); inode->i_fop = &generic_ro_fops; inode->i_mode |= S_IFREG; inode->i_blocks = ((inode->i_size - 1) >> 9) + 1; @@ -173,7 +165,6 @@ int squashfs_read_inode(struct inode *inode, long long ino) squashfs_i(inode)->start = le32_to_cpu(sqsh_ino->start_block); squashfs_i(inode)->block_list_start = block; squashfs_i(inode)->offset = offset; - squashfs_i(inode)->parent = 0; inode->i_data.a_ops = &squashfs_aops; TRACE("File inode %x:%x, start_block %llx, block_list_start " @@ -192,21 +183,8 @@ int squashfs_read_inode(struct inode *inode, long long ino) if (err < 0) goto failed_read; - inode->i_size = le64_to_cpu(sqsh_ino->file_size); - if (inode->i_size < 0) { - err = -EINVAL; - goto failed_read; - } frag = le32_to_cpu(sqsh_ino->fragment); if (frag != SQUASHFS_INVALID_FRAG) { - /* - * the file cannot have a fragment (tailend) and have a - * file size a multiple of the block size - */ - if ((inode->i_size & (msblk->block_size - 1)) == 0) { - err = -EINVAL; - goto failed_read; - } frag_offset = le32_to_cpu(sqsh_ino->offset); frag_size = squashfs_frag_lookup(sb, frag, &frag_blk); if (frag_size < 0) { @@ -221,6 +199,7 @@ int squashfs_read_inode(struct inode *inode, long long ino) xattr_id = le32_to_cpu(sqsh_ino->xattr); set_nlink(inode, le32_to_cpu(sqsh_ino->nlink)); + inode->i_size = le64_to_cpu(sqsh_ino->file_size); inode->i_op = &squashfs_inode_ops; inode->i_fop = &generic_ro_fops; inode->i_mode |= S_IFREG; @@ -233,7 +212,6 @@ int squashfs_read_inode(struct inode *inode, long long ino) squashfs_i(inode)->start = le64_to_cpu(sqsh_ino->start_block); squashfs_i(inode)->block_list_start = block; squashfs_i(inode)->offset = offset; - squashfs_i(inode)->parent = 0; inode->i_data.a_ops = &squashfs_aops; TRACE("File inode %x:%x, start_block %llx, block_list_start " @@ -314,7 +292,6 @@ int squashfs_read_inode(struct inode *inode, long long ino) inode->i_mode |= S_IFLNK; squashfs_i(inode)->start = block; squashfs_i(inode)->offset = offset; - squashfs_i(inode)->parent = 0; if (type == SQUASHFS_LSYMLINK_TYPE) { __le32 xattr; @@ -352,7 +329,6 @@ int squashfs_read_inode(struct inode *inode, long long ino) set_nlink(inode, le32_to_cpu(sqsh_ino->nlink)); rdev = le32_to_cpu(sqsh_ino->rdev); init_special_inode(inode, inode->i_mode, new_decode_dev(rdev)); - squashfs_i(inode)->parent = 0; TRACE("Device inode %x:%x, rdev %x\n", SQUASHFS_INODE_BLK(ino), offset, rdev); @@ -377,7 +353,6 @@ int squashfs_read_inode(struct inode *inode, long long ino) set_nlink(inode, le32_to_cpu(sqsh_ino->nlink)); rdev = le32_to_cpu(sqsh_ino->rdev); init_special_inode(inode, inode->i_mode, new_decode_dev(rdev)); - squashfs_i(inode)->parent = 0; TRACE("Device inode %x:%x, rdev %x\n", SQUASHFS_INODE_BLK(ino), offset, rdev); @@ -398,7 +373,6 @@ int squashfs_read_inode(struct inode *inode, long long ino) inode->i_mode |= S_IFSOCK; set_nlink(inode, le32_to_cpu(sqsh_ino->nlink)); init_special_inode(inode, inode->i_mode, 0); - squashfs_i(inode)->parent = 0; break; } case SQUASHFS_LFIFO_TYPE: @@ -418,7 +392,6 @@ int squashfs_read_inode(struct inode *inode, long long ino) inode->i_op = &squashfs_inode_ops; set_nlink(inode, le32_to_cpu(sqsh_ino->nlink)); init_special_inode(inode, inode->i_mode, 0); - squashfs_i(inode)->parent = 0; break; } default: diff --git a/fs/squashfs/squashfs_fs_i.h b/fs/squashfs/squashfs_fs_i.h index 8e497ac07b9a..2c82d6f2a456 100644 --- a/fs/squashfs/squashfs_fs_i.h +++ b/fs/squashfs/squashfs_fs_i.h @@ -16,7 +16,6 @@ struct squashfs_inode_info { u64 xattr; unsigned int xattr_size; int xattr_count; - int parent; union { struct { u64 fragment_block; @@ -28,6 +27,7 @@ struct squashfs_inode_info { u64 dir_idx_start; int dir_idx_offset; int dir_idx_cnt; + int parent; }; }; struct inode vfs_inode; diff --git a/fs/ubifs/debug.c b/fs/ubifs/debug.c index 5040fdb5409b..b5efbaf7eac2 100644 --- a/fs/ubifs/debug.c +++ b/fs/ubifs/debug.c @@ -815,7 +815,7 @@ void ubifs_dump_leb(const struct ubifs_info *c, int lnum) pr_err("(pid %d) start dumping LEB %d\n", current->pid, lnum); - buf = __vmalloc(c->leb_size, GFP_NOFS); + buf = __vmalloc(c->leb_size, GFP_NOFS, PAGE_KERNEL); if (!buf) { ubifs_err(c, "cannot allocate memory for dumping LEB %d", lnum); return; diff --git a/fs/ubifs/lprops.c b/fs/ubifs/lprops.c index 22bfda158f7f..29826c51883a 100644 --- a/fs/ubifs/lprops.c +++ b/fs/ubifs/lprops.c @@ -1095,7 +1095,7 @@ static int scan_check_cb(struct ubifs_info *c, return LPT_SCAN_CONTINUE; } - buf = __vmalloc(c->leb_size, GFP_NOFS); + buf = __vmalloc(c->leb_size, GFP_NOFS, PAGE_KERNEL); if (!buf) return -ENOMEM; diff --git a/fs/ubifs/lpt_commit.c b/fs/ubifs/lpt_commit.c index d76a19e460cd..ff5e0411cf2d 100644 --- a/fs/ubifs/lpt_commit.c +++ b/fs/ubifs/lpt_commit.c @@ -1596,7 +1596,7 @@ static int dbg_check_ltab_lnum(struct ubifs_info *c, int lnum) if (!dbg_is_chk_lprops(c)) return 0; - buf = p = __vmalloc(c->leb_size, GFP_NOFS); + buf = p = __vmalloc(c->leb_size, GFP_NOFS, PAGE_KERNEL); if (!buf) { ubifs_err(c, "cannot allocate memory for ltab checking"); return 0; @@ -1845,7 +1845,7 @@ static void dump_lpt_leb(const struct ubifs_info *c, int lnum) void *buf, *p; pr_err("(pid %d) start dumping LEB %d\n", current->pid, lnum); - buf = p = __vmalloc(c->leb_size, GFP_NOFS); + buf = p = __vmalloc(c->leb_size, GFP_NOFS, PAGE_KERNEL); if (!buf) { ubifs_err(c, "cannot allocate memory to dump LPT"); return; diff --git a/fs/ubifs/orphan.c b/fs/ubifs/orphan.c index 0fb61956146d..b0117878b3a0 100644 --- a/fs/ubifs/orphan.c +++ b/fs/ubifs/orphan.c @@ -979,7 +979,7 @@ static int dbg_scan_orphans(struct ubifs_info *c, struct check_info *ci) if (c->no_orphs) return 0; - buf = __vmalloc(c->leb_size, GFP_NOFS); + buf = __vmalloc(c->leb_size, GFP_NOFS, PAGE_KERNEL); if (!buf) { ubifs_err(c, "cannot allocate memory to check orphans"); return 0; diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index d67fd6a875bd..0b114f685be1 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -2189,8 +2189,6 @@ static int ubifs_fill_super(struct super_block *sb, void *data, int silent) c->vi.vol_id); if (err) goto out_close; - sb->s_bdi->ra_pages = 0; - sb->s_bdi->io_pages = 0; sb->s_fs_info = c; sb->s_magic = UBIFS_SUPER_MAGIC; diff --git a/fs/udf/inode.c b/fs/udf/inode.c index e3fa86bb8021..7d878e36759b 100644 --- a/fs/udf/inode.c +++ b/fs/udf/inode.c @@ -2202,9 +2202,6 @@ int8_t udf_current_aext(struct inode *inode, struct extent_position *epos, if (check_add_overflow(sizeof(struct allocExtDesc), le32_to_cpu(header->lengthAllocDescs), &alen)) return -1; - - if (alen > epos->bh->b_size) - return -1; } switch (iinfo->i_alloc_type) { diff --git a/fs/userfaultfd.c b/fs/userfaultfd.c index 69321d466379..de1203b48bb9 100644 --- a/fs/userfaultfd.c +++ b/fs/userfaultfd.c @@ -2017,7 +2017,7 @@ static const struct file_operations userfaultfd_fops = { .poll = userfaultfd_poll, .read = userfaultfd_read, .unlocked_ioctl = userfaultfd_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = userfaultfd_ioctl, .llseek = noop_llseek, }; diff --git a/fs/xattr.c b/fs/xattr.c index dc1ef6eb43e2..b2855070757e 100644 --- a/fs/xattr.c +++ b/fs/xattr.c @@ -930,7 +930,6 @@ int simple_xattr_get(struct simple_xattrs *xattrs, const char *name, * @value: value of the xattr. If %NULL, will remove the attribute. * @size: size of the new xattr * @flags: %XATTR_{CREATE|REPLACE} - * @removed_size: returns size of the removed xattr, -1 if none removed * * %XATTR_CREATE is set, the xattr shouldn't exist already; otherwise fails * with -EEXIST. If %XATTR_REPLACE is set, the xattr should exist; @@ -939,8 +938,7 @@ int simple_xattr_get(struct simple_xattrs *xattrs, const char *name, * Returns 0 on success, -errno on failure. */ int simple_xattr_set(struct simple_xattrs *xattrs, const char *name, - const void *value, size_t size, int flags, - ssize_t *removed_size) + const void *value, size_t size, int flags) { struct simple_xattr *xattr; struct simple_xattr *new_xattr = NULL; @@ -967,12 +965,8 @@ int simple_xattr_set(struct simple_xattrs *xattrs, const char *name, err = -EEXIST; } else if (new_xattr) { list_replace(&xattr->list, &new_xattr->list); - if (removed_size) - *removed_size = xattr->size; } else { list_del(&xattr->list); - if (removed_size) - *removed_size = xattr->size; } goto out; } @@ -984,9 +978,6 @@ int simple_xattr_set(struct simple_xattrs *xattrs, const char *name, list_add(&new_xattr->list, &xattrs->head); xattr = NULL; } - - if (removed_size) - *removed_size = -1; out: spin_unlock(&xattrs->lock); if (xattr) { diff --git a/fs/xfs/kmem.c b/fs/xfs/kmem.c index ca4cda596da6..da031b93e182 100644 --- a/fs/xfs/kmem.c +++ b/fs/xfs/kmem.c @@ -48,7 +48,7 @@ __kmem_vmalloc(size_t size, xfs_km_flags_t flags) if (flags & KM_NOFS) nofs_flag = memalloc_nofs_save(); - ptr = __vmalloc(size, lflags); + ptr = __vmalloc(size, lflags, PAGE_KERNEL); if (flags & KM_NOFS) memalloc_nofs_restore(nofs_flag); diff --git a/fs/xfs/xfs_sysctl.c b/fs/xfs/xfs_sysctl.c index 021ef96d0542..31b3bdbd2eba 100644 --- a/fs/xfs/xfs_sysctl.c +++ b/fs/xfs/xfs_sysctl.c @@ -13,7 +13,7 @@ STATIC int xfs_stats_clear_proc_handler( struct ctl_table *ctl, int write, - void *buffer, + void __user *buffer, size_t *lenp, loff_t *ppos) { @@ -33,7 +33,7 @@ STATIC int xfs_panic_mask_proc_handler( struct ctl_table *ctl, int write, - void *buffer, + void __user *buffer, size_t *lenp, loff_t *ppos) { diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h index fc40d6e4f400..15f77361eb13 100644 --- a/include/asm-generic/pgtable.h +++ b/include/asm-generic/pgtable.h @@ -226,22 +226,6 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addres } #endif -/* - * On some architectures hardware does not set page access bit when accessing - * memory page, it is responsibilty of software setting this bit. It brings - * out extra page fault penalty to track page access bit. For optimization page - * access bit can be set during all page fault flow on these arches. - * To be differentiate with macro pte_mkyoung, this macro is used on platforms - * where software maintains page access bit. - */ -#ifndef pte_sw_mkyoung -static inline pte_t pte_sw_mkyoung(pte_t pte) -{ - return pte; -} -#define pte_sw_mkyoung pte_sw_mkyoung -#endif - #ifndef pte_savedwrite #define pte_savedwrite pte_write #endif diff --git a/include/asm-generic/seccomp.h b/include/asm-generic/seccomp.h index 6b6f42bc58f9..1321ac7821d7 100644 --- a/include/asm-generic/seccomp.h +++ b/include/asm-generic/seccomp.h @@ -33,7 +33,7 @@ static inline const int *get_compat_mode1_syscalls(void) static const int mode1_syscalls_32[] = { __NR_seccomp_read_32, __NR_seccomp_write_32, __NR_seccomp_exit_32, __NR_seccomp_sigreturn_32, - -1, /* negative terminated */ + 0, /* null terminated */ }; return mode1_syscalls_32; } diff --git a/include/asm-generic/tlb.h b/include/asm-generic/tlb.h index fd5f54b9c863..b06240b67199 100644 --- a/include/asm-generic/tlb.h +++ b/include/asm-generic/tlb.h @@ -26,15 +26,6 @@ # define nmi_uaccess_okay() true #endif -/* - * Blindly accessing user memory from NMI context can be dangerous - * if we're in the middle of switching the current user task or switching - * the loaded mm. - */ -#ifndef nmi_uaccess_okay -# define nmi_uaccess_okay() true -#endif - #ifdef CONFIG_MMU /* diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h index 9c95bbc9bd25..b7f1f239cd9b 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -623,10 +623,6 @@ __start_BTF = .; \ KEEP(*(.BTF)) \ __stop_BTF = .; \ - } \ - . = ALIGN(4); \ - .BTF_ids : AT(ADDR(.BTF_ids) - LOAD_OFFSET) { \ - *(.BTF_ids) \ } #else #define BTF diff --git a/include/linux/ata.h b/include/linux/ata.h index 7e8d690df254..6d2d31b03b4d 100644 --- a/include/linux/ata.h +++ b/include/linux/ata.h @@ -557,7 +557,6 @@ struct ata_bmdma_prd { #define ata_id_has_ncq(id) ((id)[ATA_ID_SATA_CAPABILITY] & (1 << 8)) #define ata_id_queue_depth(id) (((id)[ATA_ID_QUEUE_DEPTH] & 0x1f) + 1) #define ata_id_removable(id) ((id)[ATA_ID_CONFIG] & (1 << 7)) -#define ata_id_is_locked(id) (((id)[ATA_ID_DLF] & 0x7) == 0x7) #define ata_id_has_atapi_AN(id) \ ((((id)[ATA_ID_SATA_CAPABILITY] != 0x0000) && \ ((id)[ATA_ID_SATA_CAPABILITY] != 0xffff)) && \ diff --git a/include/linux/bpf-cgroup.h b/include/linux/bpf-cgroup.h index 91b966978541..169fd25f6bc2 100644 --- a/include/linux/bpf-cgroup.h +++ b/include/linux/bpf-cgroup.h @@ -20,25 +20,14 @@ struct bpf_sock_ops_kern; struct bpf_cgroup_storage; struct ctl_table; struct ctl_table_header; -struct task_struct; #ifdef CONFIG_CGROUP_BPF extern struct static_key_false cgroup_bpf_enabled_key; #define cgroup_bpf_enabled static_branch_unlikely(&cgroup_bpf_enabled_key) -#define BPF_CGROUP_STORAGE_NEST_MAX 8 - -struct bpf_cgroup_storage_info { - struct task_struct *task; - struct bpf_cgroup_storage *storage[MAX_BPF_CGROUP_STORAGE_TYPE]; -}; - -/* For each cpu, permit maximum BPF_CGROUP_STORAGE_NEST_MAX number of tasks - * to use bpf cgroup storage simultaneously. - */ -DECLARE_PER_CPU(struct bpf_cgroup_storage_info, - bpf_cgroup_storage_info[BPF_CGROUP_STORAGE_NEST_MAX]); +DECLARE_PER_CPU(struct bpf_cgroup_storage*, + bpf_cgroup_storage[MAX_BPF_CGROUP_STORAGE_TYPE]); #define for_each_cgroup_storage_type(stype) \ for (stype = 0; stype < MAX_BPF_CGROUP_STORAGE_TYPE; stype++) @@ -47,7 +36,7 @@ struct bpf_cgroup_storage_map; struct bpf_storage_buffer { struct rcu_head rcu; - char data[]; + char data[0]; }; struct bpf_cgroup_storage { @@ -57,22 +46,14 @@ struct bpf_cgroup_storage { }; struct bpf_cgroup_storage_map *map; struct bpf_cgroup_storage_key key; - struct list_head list_map; - struct list_head list_cg; + struct list_head list; struct rb_node node; struct rcu_head rcu; }; -struct bpf_cgroup_link { - struct bpf_link link; - struct cgroup *cgroup; - enum bpf_attach_type type; -}; - struct bpf_prog_list { struct list_head node; struct bpf_prog *prog; - struct bpf_cgroup_link *link; struct bpf_cgroup_storage *storage[MAX_BPF_CGROUP_STORAGE_TYPE]; }; @@ -90,9 +71,6 @@ struct cgroup_bpf { struct list_head progs[MAX_BPF_ATTACH_TYPE]; u32 flags[MAX_BPF_ATTACH_TYPE]; - /* list of cgroup shared storages */ - struct list_head storages; - /* temp storage for effective prog array used by prog_attach/detach */ struct bpf_prog_array *inactive; @@ -106,23 +84,18 @@ struct cgroup_bpf { int cgroup_bpf_inherit(struct cgroup *cgrp); void cgroup_bpf_offline(struct cgroup *cgrp); -int __cgroup_bpf_attach(struct cgroup *cgrp, - struct bpf_prog *prog, struct bpf_prog *replace_prog, - struct bpf_cgroup_link *link, +int __cgroup_bpf_attach(struct cgroup *cgrp, struct bpf_prog *prog, enum bpf_attach_type type, u32 flags); int __cgroup_bpf_detach(struct cgroup *cgrp, struct bpf_prog *prog, - struct bpf_cgroup_link *link, enum bpf_attach_type type); int __cgroup_bpf_query(struct cgroup *cgrp, const union bpf_attr *attr, union bpf_attr __user *uattr); /* Wrapper for __cgroup_bpf_*() protected by cgroup_mutex */ -int cgroup_bpf_attach(struct cgroup *cgrp, - struct bpf_prog *prog, struct bpf_prog *replace_prog, - struct bpf_cgroup_link *link, enum bpf_attach_type type, - u32 flags); +int cgroup_bpf_attach(struct cgroup *cgrp, struct bpf_prog *prog, + enum bpf_attach_type type, u32 flags); int cgroup_bpf_detach(struct cgroup *cgrp, struct bpf_prog *prog, - enum bpf_attach_type type); + enum bpf_attach_type type, u32 flags); int cgroup_bpf_query(struct cgroup *cgrp, const union bpf_attr *attr, union bpf_attr __user *uattr); @@ -147,7 +120,8 @@ int __cgroup_bpf_check_dev_permission(short dev_type, u32 major, u32 minor, int __cgroup_bpf_run_filter_sysctl(struct ctl_table_header *head, struct ctl_table *table, int write, - char **buf, size_t *pcount, loff_t *ppos, + void __user *buf, size_t *pcount, + loff_t *ppos, void **new_buf, enum bpf_attach_type type); int __cgroup_bpf_run_filter_setsockopt(struct sock *sock, int *level, @@ -167,47 +141,15 @@ static inline enum bpf_cgroup_storage_type cgroup_storage_type( return BPF_CGROUP_STORAGE_SHARED; } -static inline int bpf_cgroup_storage_set(struct bpf_cgroup_storage - *storage[MAX_BPF_CGROUP_STORAGE_TYPE]) +static inline void bpf_cgroup_storage_set(struct bpf_cgroup_storage + *storage[MAX_BPF_CGROUP_STORAGE_TYPE]) { enum bpf_cgroup_storage_type stype; - int i, err = 0; - preempt_disable(); - for (i = 0; i < BPF_CGROUP_STORAGE_NEST_MAX; i++) { - if (unlikely(this_cpu_read(bpf_cgroup_storage_info[i].task) != NULL)) - continue; - - this_cpu_write(bpf_cgroup_storage_info[i].task, current); - for_each_cgroup_storage_type(stype) - this_cpu_write(bpf_cgroup_storage_info[i].storage[stype], - storage[stype]); - goto out; - } - err = -EBUSY; - WARN_ON_ONCE(1); - -out: - preempt_enable(); - return err; + for_each_cgroup_storage_type(stype) + this_cpu_write(bpf_cgroup_storage[stype], storage[stype]); } -static inline void bpf_cgroup_storage_unset(void) -{ - int i; - - for (i = BPF_CGROUP_STORAGE_NEST_MAX - 1; i >= 0; i--) { - if (likely(this_cpu_read(bpf_cgroup_storage_info[i].task) != current)) - continue; - - this_cpu_write(bpf_cgroup_storage_info[i].task, NULL); - return; - } -} - -struct bpf_cgroup_storage * -cgroup_storage_lookup(struct bpf_cgroup_storage_map *map, - void *key, bool locked); struct bpf_cgroup_storage *bpf_cgroup_storage_alloc(struct bpf_prog *prog, enum bpf_cgroup_storage_type stype); void bpf_cgroup_storage_free(struct bpf_cgroup_storage *storage); @@ -215,7 +157,8 @@ void bpf_cgroup_storage_link(struct bpf_cgroup_storage *storage, struct cgroup *cgroup, enum bpf_attach_type type); void bpf_cgroup_storage_unlink(struct bpf_cgroup_storage *storage); -int bpf_cgroup_storage_assign(struct bpf_prog_aux *aux, struct bpf_map *map); +int bpf_cgroup_storage_assign(struct bpf_prog *prog, struct bpf_map *map); +void bpf_cgroup_storage_release(struct bpf_prog *prog, struct bpf_map *map); int bpf_percpu_cgroup_storage_copy(struct bpf_map *map, void *key, void *value); int bpf_percpu_cgroup_storage_update(struct bpf_map *map, void *key, @@ -256,9 +199,6 @@ int bpf_percpu_cgroup_storage_update(struct bpf_map *map, void *key, #define BPF_CGROUP_RUN_PROG_INET_SOCK(sk) \ BPF_CGROUP_RUN_SK_PROG(sk, BPF_CGROUP_INET_SOCK_CREATE) -#define BPF_CGROUP_RUN_PROG_INET_SOCK_RELEASE(sk) \ - BPF_CGROUP_RUN_SK_PROG(sk, BPF_CGROUP_INET_SOCK_RELEASE) - #define BPF_CGROUP_RUN_PROG_INET4_POST_BIND(sk) \ BPF_CGROUP_RUN_SK_PROG(sk, BPF_CGROUP_INET4_POST_BIND) @@ -319,31 +259,6 @@ int bpf_percpu_cgroup_storage_update(struct bpf_map *map, void *key, #define BPF_CGROUP_RUN_PROG_UDP6_RECVMSG_LOCK(sk, uaddr) \ BPF_CGROUP_RUN_SA_PROG_LOCK(sk, uaddr, BPF_CGROUP_UDP6_RECVMSG, NULL) -/* The SOCK_OPS"_SK" macro should be used when sock_ops->sk is not a - * fullsock and its parent fullsock cannot be traced by - * sk_to_full_sk(). - * - * e.g. sock_ops->sk is a request_sock and it is under syncookie mode. - * Its listener-sk is not attached to the rsk_listener. - * In this case, the caller holds the listener-sk (unlocked), - * set its sock_ops->sk to req_sk, and call this SOCK_OPS"_SK" with - * the listener-sk such that the cgroup-bpf-progs of the - * listener-sk will be run. - * - * Regardless of syncookie mode or not, - * calling bpf_setsockopt on listener-sk will not make sense anyway, - * so passing 'sock_ops->sk == req_sk' to the bpf prog is appropriate here. - */ -#define BPF_CGROUP_RUN_PROG_SOCK_OPS_SK(sock_ops, sk) \ -({ \ - int __ret = 0; \ - if (cgroup_bpf_enabled) \ - __ret = __cgroup_bpf_run_filter_sock_ops(sk, \ - sock_ops, \ - BPF_CGROUP_SOCK_OPS); \ - __ret; \ -}) - #define BPF_CGROUP_RUN_PROG_SOCK_OPS(sock_ops) \ ({ \ int __ret = 0; \ @@ -369,12 +284,12 @@ int bpf_percpu_cgroup_storage_update(struct bpf_map *map, void *key, }) -#define BPF_CGROUP_RUN_PROG_SYSCTL(head, table, write, buf, count, pos) \ +#define BPF_CGROUP_RUN_PROG_SYSCTL(head, table, write, buf, count, pos, nbuf) \ ({ \ int __ret = 0; \ if (cgroup_bpf_enabled) \ __ret = __cgroup_bpf_run_filter_sysctl(head, table, write, \ - buf, count, pos, \ + buf, count, pos, nbuf, \ BPF_CGROUP_SYSCTL); \ __ret; \ }) @@ -415,7 +330,6 @@ int cgroup_bpf_prog_attach(const union bpf_attr *attr, enum bpf_prog_type ptype, struct bpf_prog *prog); int cgroup_bpf_prog_detach(const union bpf_attr *attr, enum bpf_prog_type ptype); -int cgroup_bpf_link_attach(const union bpf_attr *attr, struct bpf_prog *prog); int cgroup_bpf_prog_query(const union bpf_attr *attr, union bpf_attr __user *uattr); #else @@ -438,23 +352,18 @@ static inline int cgroup_bpf_prog_detach(const union bpf_attr *attr, return -EINVAL; } -static inline int cgroup_bpf_link_attach(const union bpf_attr *attr, - struct bpf_prog *prog) -{ - return -EINVAL; -} - static inline int cgroup_bpf_prog_query(const union bpf_attr *attr, union bpf_attr __user *uattr) { return -EINVAL; } -static inline int bpf_cgroup_storage_set( - struct bpf_cgroup_storage *storage[MAX_BPF_CGROUP_STORAGE_TYPE]) { return 0; } -static inline void bpf_cgroup_storage_unset(void) {} -static inline int bpf_cgroup_storage_assign(struct bpf_prog_aux *aux, +static inline void bpf_cgroup_storage_set( + struct bpf_cgroup_storage *storage[MAX_BPF_CGROUP_STORAGE_TYPE]) {} +static inline int bpf_cgroup_storage_assign(struct bpf_prog *prog, struct bpf_map *map) { return 0; } +static inline void bpf_cgroup_storage_release(struct bpf_prog *prog, + struct bpf_map *map) {} static inline struct bpf_cgroup_storage *bpf_cgroup_storage_alloc( struct bpf_prog *prog, enum bpf_cgroup_storage_type stype) { return NULL; } static inline void bpf_cgroup_storage_free( @@ -469,12 +378,10 @@ static inline int bpf_percpu_cgroup_storage_update(struct bpf_map *map, } #define cgroup_bpf_enabled (0) -#define BPF_CGROUP_RUN_SA_PROG_LOCK(sk, uaddr, type, t_ctx) ({ 0; }) #define BPF_CGROUP_PRE_CONNECT_ENABLED(sk) (0) #define BPF_CGROUP_RUN_PROG_INET_INGRESS(sk,skb) ({ 0; }) #define BPF_CGROUP_RUN_PROG_INET_EGRESS(sk,skb) ({ 0; }) #define BPF_CGROUP_RUN_PROG_INET_SOCK(sk) ({ 0; }) -#define BPF_CGROUP_RUN_PROG_INET_SOCK_RELEASE(sk) ({ 0; }) #define BPF_CGROUP_RUN_PROG_INET4_BIND(sk, uaddr) ({ 0; }) #define BPF_CGROUP_RUN_PROG_INET6_BIND(sk, uaddr) ({ 0; }) #define BPF_CGROUP_RUN_PROG_INET4_POST_BIND(sk) ({ 0; }) @@ -489,7 +396,7 @@ static inline int bpf_percpu_cgroup_storage_update(struct bpf_map *map, #define BPF_CGROUP_RUN_PROG_UDP6_RECVMSG_LOCK(sk, uaddr) ({ 0; }) #define BPF_CGROUP_RUN_PROG_SOCK_OPS(sock_ops) ({ 0; }) #define BPF_CGROUP_RUN_PROG_DEVICE_CGROUP(type,major,minor,access) ({ 0; }) -#define BPF_CGROUP_RUN_PROG_SYSCTL(head,table,write,buf,count,pos) ({ 0; }) +#define BPF_CGROUP_RUN_PROG_SYSCTL(head,table,write,buf,count,pos,nbuf) ({ 0; }) #define BPF_CGROUP_GETSOCKOPT_MAX_OPTLEN(optlen) ({ 0; }) #define BPF_CGROUP_RUN_PROG_GETSOCKOPT(sock, level, optname, optval, \ optlen, max_optlen, retval) ({ retval; }) diff --git a/include/linux/bpf-netns.h b/include/linux/bpf-netns.h deleted file mode 100644 index 722f799c1a2e..000000000000 --- a/include/linux/bpf-netns.h +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _BPF_NETNS_H -#define _BPF_NETNS_H - -#include -#include - -enum netns_bpf_attach_type { - NETNS_BPF_INVALID = -1, - NETNS_BPF_FLOW_DISSECTOR = 0, - NETNS_BPF_SK_LOOKUP, - MAX_NETNS_BPF_ATTACH_TYPE -}; - -static inline enum netns_bpf_attach_type -to_netns_bpf_attach_type(enum bpf_attach_type attach_type) -{ - switch (attach_type) { - case BPF_FLOW_DISSECTOR: - return NETNS_BPF_FLOW_DISSECTOR; - case BPF_SK_LOOKUP: - return NETNS_BPF_SK_LOOKUP; - default: - return NETNS_BPF_INVALID; - } -} - -/* Protects updates to netns_bpf */ -extern struct mutex netns_bpf_mutex; - -union bpf_attr; -struct bpf_prog; - -#ifdef CONFIG_NET -int netns_bpf_prog_query(const union bpf_attr *attr, - union bpf_attr __user *uattr); -int netns_bpf_prog_attach(const union bpf_attr *attr, - struct bpf_prog *prog); -int netns_bpf_prog_detach(const union bpf_attr *attr, enum bpf_prog_type ptype); -int netns_bpf_link_create(const union bpf_attr *attr, - struct bpf_prog *prog); -#else -static inline int netns_bpf_prog_query(const union bpf_attr *attr, - union bpf_attr __user *uattr) -{ - return -EOPNOTSUPP; -} - -static inline int netns_bpf_prog_attach(const union bpf_attr *attr, - struct bpf_prog *prog) -{ - return -EOPNOTSUPP; -} - -static inline int netns_bpf_prog_detach(const union bpf_attr *attr, - enum bpf_prog_type ptype) -{ - return -EOPNOTSUPP; -} - -static inline int netns_bpf_link_create(const union bpf_attr *attr, - struct bpf_prog *prog) -{ - return -EOPNOTSUPP; -} -#endif - -#endif /* _BPF_NETNS_H */ diff --git a/include/linux/bpf.h b/include/linux/bpf.h index ed1d4cb6a99b..a120c58a4883 100644 --- a/include/linux/bpf.h +++ b/include/linux/bpf.h @@ -12,46 +12,21 @@ #include #include #include -#include #include #include -#include -#include -#include -#include -#include -#include -#include struct bpf_verifier_env; -struct bpf_verifier_log; struct perf_event; struct bpf_prog; -struct bpf_prog_aux; struct bpf_map; struct sock; struct seq_file; struct btf; struct btf_type; -struct exception_table_entry; -struct seq_operations; -struct bpf_iter_aux_info; -struct bpf_local_storage; -struct bpf_local_storage_map; extern struct idr btf_idr; extern spinlock_t btf_idr_lock; -typedef int (*bpf_iter_init_seq_priv_t)(void *private_data, - struct bpf_iter_aux_info *aux); -typedef void (*bpf_iter_fini_seq_priv_t)(void *private_data); -struct bpf_iter_seq_info { - const struct seq_operations *seq_ops; - bpf_iter_init_seq_priv_t init_seq_private; - bpf_iter_fini_seq_priv_t fini_seq_private; - u32 seq_priv_size; -}; - /* map is generic key/value storage optionally accesible by eBPF programs */ struct bpf_map_ops { /* funcs callable from userspace (via syscall) */ @@ -62,15 +37,6 @@ struct bpf_map_ops { int (*map_get_next_key)(struct bpf_map *map, void *key, void *next_key); void (*map_release_uref)(struct bpf_map *map); void *(*map_lookup_elem_sys_only)(struct bpf_map *map, void *key); - int (*map_lookup_batch)(struct bpf_map *map, const union bpf_attr *attr, - union bpf_attr __user *uattr); - int (*map_lookup_and_delete_batch)(struct bpf_map *map, - const union bpf_attr *attr, - union bpf_attr __user *uattr); - int (*map_update_batch)(struct bpf_map *map, const union bpf_attr *attr, - union bpf_attr __user *uattr); - int (*map_delete_batch)(struct bpf_map *map, const union bpf_attr *attr, - union bpf_attr __user *uattr); /* funcs callable from userspace and from eBPF programs */ void *(*map_lookup_elem)(struct bpf_map *map, void *key); @@ -84,7 +50,7 @@ struct bpf_map_ops { void *(*map_fd_get_ptr)(struct bpf_map *map, struct file *map_file, int fd); void (*map_fd_put_ptr)(void *ptr); - int (*map_gen_lookup)(struct bpf_map *map, struct bpf_insn *insn_buf); + u32 (*map_gen_lookup)(struct bpf_map *map, struct bpf_insn *insn_buf); u32 (*map_fd_sys_lookup_elem)(void *ptr); void (*map_seq_show_elem)(struct bpf_map *map, void *key, struct seq_file *m); @@ -93,49 +59,11 @@ struct bpf_map_ops { const struct btf_type *key_type, const struct btf_type *value_type); - /* Prog poke tracking helpers. */ - int (*map_poke_track)(struct bpf_map *map, struct bpf_prog_aux *aux); - void (*map_poke_untrack)(struct bpf_map *map, struct bpf_prog_aux *aux); - void (*map_poke_run)(struct bpf_map *map, u32 key, struct bpf_prog *old, - struct bpf_prog *new); - /* Direct value access helpers. */ int (*map_direct_value_addr)(const struct bpf_map *map, u64 *imm, u32 off); int (*map_direct_value_meta)(const struct bpf_map *map, u64 imm, u32 *off); - int (*map_mmap)(struct bpf_map *map, struct vm_area_struct *vma); - __poll_t (*map_poll)(struct bpf_map *map, struct file *filp, - struct poll_table_struct *pts); - - /* Functions called by bpf_local_storage maps */ - int (*map_local_storage_charge)(struct bpf_local_storage_map *smap, - void *owner, u32 size); - void (*map_local_storage_uncharge)(struct bpf_local_storage_map *smap, - void *owner, u32 size); - struct bpf_local_storage __rcu ** (*map_owner_storage_ptr)(void *owner); - - /* map_meta_equal must be implemented for maps that can be - * used as an inner map. It is a runtime check to ensure - * an inner map can be inserted to an outer map. - * - * Some properties of the inner map has been used during the - * verification time. When inserting an inner map at the runtime, - * map_meta_equal has to ensure the inserting map has the same - * properties that the verifier has used earlier. - */ - bool (*map_meta_equal)(const struct bpf_map *meta0, - const struct bpf_map *meta1); - - /* BTF name and id of struct allocated by map_alloc */ - const char * const map_btf_name; - int *map_btf_id; - - /* bpf_iter info used to open a seq_file */ - const struct bpf_iter_seq_info *iter_seq_info; - - ANDROID_KABI_RESERVE(1); - ANDROID_KABI_RESERVE(2); }; struct bpf_map_memory { @@ -164,20 +92,17 @@ struct bpf_map { u32 btf_value_type_id; struct btf *btf; struct bpf_map_memory memory; - char name[BPF_OBJ_NAME_LEN]; - u32 btf_vmlinux_value_type_id; - bool bypass_spec_v1; - bool frozen; /* write-once; write-protected by freeze_mutex */ - /* 22 bytes hole */ + bool unpriv_array; + bool frozen; /* write-once */ + /* 48 bytes hole */ /* The 3rd and 4th cacheline with misc members to avoid false sharing * particularly with refcounting. */ - atomic64_t refcnt ____cacheline_aligned; - atomic64_t usercnt; + atomic_t refcnt ____cacheline_aligned; + atomic_t usercnt; struct work_struct work; - struct mutex freeze_mutex; - atomic64_t writecnt; + char name[BPF_OBJ_NAME_LEN]; }; static inline bool map_value_has_spin_lock(const struct bpf_map *map) @@ -209,7 +134,6 @@ static inline void copy_map_value(struct bpf_map *map, void *dst, void *src) } void copy_map_value_locked(struct bpf_map *map, void *dst, void *src, bool lock_src); -int bpf_obj_name_cpy(char *dst, const char *src, unsigned int size); struct bpf_offload_dev; struct bpf_offloaded_map; @@ -222,8 +146,6 @@ struct bpf_map_dev_ops { int (*map_update_elem)(struct bpf_offloaded_map *map, void *key, void *value, u64 flags); int (*map_delete_elem)(struct bpf_offloaded_map *map, void *key); - - ANDROID_KABI_RESERVE(1); }; struct bpf_offloaded_map { @@ -246,8 +168,7 @@ static inline bool bpf_map_offload_neutral(const struct bpf_map *map) static inline bool bpf_map_support_seq_show(const struct bpf_map *map) { - return (map->btf_value_type_id || map->btf_vmlinux_value_type_id) && - map->ops->map_seq_show_elem; + return map->btf && map->ops->map_seq_show_elem; } int map_check_no_btf(const struct bpf_map *map, @@ -255,9 +176,6 @@ int map_check_no_btf(const struct bpf_map *map, const struct btf_type *key_type, const struct btf_type *value_type); -bool bpf_map_meta_equal(const struct bpf_map *meta0, - const struct bpf_map *meta1); - extern const struct bpf_map_ops bpf_map_offload_ops; /* function argument constraints */ @@ -287,21 +205,12 @@ enum bpf_arg_type { ARG_CONST_SIZE_OR_ZERO, /* number of bytes accessed from memory or 0 */ ARG_PTR_TO_CTX, /* pointer to context */ - ARG_PTR_TO_CTX_OR_NULL, /* pointer to context or NULL */ ARG_ANYTHING, /* any (initialized) argument is ok */ ARG_PTR_TO_SPIN_LOCK, /* pointer to bpf_spin_lock */ ARG_PTR_TO_SOCK_COMMON, /* pointer to sock_common */ ARG_PTR_TO_INT, /* pointer to int */ ARG_PTR_TO_LONG, /* pointer to long */ ARG_PTR_TO_SOCKET, /* pointer to bpf_sock (fullsock) */ - ARG_PTR_TO_SOCKET_OR_NULL, /* pointer to bpf_sock (fullsock) or NULL */ - ARG_PTR_TO_BTF_ID, /* pointer to in-kernel struct */ - ARG_PTR_TO_ALLOC_MEM, /* pointer to dynamically allocated memory */ - ARG_PTR_TO_ALLOC_MEM_OR_NULL, /* pointer to dynamically allocated memory or NULL */ - ARG_CONST_ALLOC_SIZE_OR_ZERO, /* number of allocated bytes requested */ - ARG_PTR_TO_BTF_ID_SOCK_COMMON, /* pointer to in-kernel sock_common or bpf-mirrored bpf_sock */ - ARG_PTR_TO_PERCPU_BTF_ID, /* pointer to in-kernel percpu type */ - __BPF_ARG_TYPE_MAX, }; /* type of values returned from helper functions */ @@ -313,10 +222,6 @@ enum bpf_return_type { RET_PTR_TO_SOCKET_OR_NULL, /* returns a pointer to a socket or NULL */ RET_PTR_TO_TCP_SOCK_OR_NULL, /* returns a pointer to a tcp_sock or NULL */ RET_PTR_TO_SOCK_COMMON_OR_NULL, /* returns a pointer to a sock_common or NULL */ - RET_PTR_TO_ALLOC_MEM_OR_NULL, /* returns a pointer to dynamically allocated memory or NULL */ - RET_PTR_TO_BTF_ID_OR_NULL, /* returns a pointer to a btf_id or NULL */ - RET_PTR_TO_MEM_OR_BTF_ID_OR_NULL, /* returns a pointer to a valid memory or a btf_id or NULL */ - RET_PTR_TO_MEM_OR_BTF_ID, /* returns a pointer to a valid memory or a btf_id */ }; /* eBPF function prototype used by verifier to allow BPF_CALLs from eBPF programs @@ -328,28 +233,11 @@ struct bpf_func_proto { bool gpl_only; bool pkt_access; enum bpf_return_type ret_type; - union { - struct { - enum bpf_arg_type arg1_type; - enum bpf_arg_type arg2_type; - enum bpf_arg_type arg3_type; - enum bpf_arg_type arg4_type; - enum bpf_arg_type arg5_type; - }; - enum bpf_arg_type arg_type[5]; - }; - union { - struct { - u32 *arg1_btf_id; - u32 *arg2_btf_id; - u32 *arg3_btf_id; - u32 *arg4_btf_id; - u32 *arg5_btf_id; - }; - u32 *arg_btf_id[5]; - }; - int *ret_btf_id; /* return value btf_id */ - bool (*allowed)(const struct bpf_prog *prog); + enum bpf_arg_type arg1_type; + enum bpf_arg_type arg2_type; + enum bpf_arg_type arg3_type; + enum bpf_arg_type arg4_type; + enum bpf_arg_type arg5_type; }; /* bpf_context is intentionally undefined structure. Pointer to bpf_context is @@ -393,29 +281,6 @@ enum bpf_reg_type { PTR_TO_TCP_SOCK_OR_NULL, /* reg points to struct tcp_sock or NULL */ PTR_TO_TP_BUFFER, /* reg points to a writable raw tp's buffer */ PTR_TO_XDP_SOCK, /* reg points to struct xdp_sock */ - /* PTR_TO_BTF_ID points to a kernel struct that does not need - * to be null checked by the BPF program. This does not imply the - * pointer is _not_ null and in practice this can easily be a null - * pointer when reading pointer chains. The assumption is program - * context will handle null pointer dereference typically via fault - * handling. The verifier must keep this in mind and can make no - * assumptions about null or non-null when doing branch analysis. - * Further, when passed into helpers the helpers can not, without - * additional context, assume the value is non-null. - */ - PTR_TO_BTF_ID, - /* PTR_TO_BTF_ID_OR_NULL points to a kernel struct that has not - * been checked for null. Used primarily to inform the verifier - * an explicit null check is required for this struct. - */ - PTR_TO_BTF_ID_OR_NULL, - PTR_TO_MEM, /* reg points to valid memory region */ - PTR_TO_MEM_OR_NULL, /* reg points to valid memory region or NULL */ - PTR_TO_RDONLY_BUF, /* reg points to a readonly buffer */ - PTR_TO_RDONLY_BUF_OR_NULL, /* reg points to a readonly buffer or NULL */ - PTR_TO_RDWR_BUF, /* reg points to a read/write buffer */ - PTR_TO_RDWR_BUF_OR_NULL, /* reg points to a read/write buffer or NULL */ - PTR_TO_PERCPU_BTF_ID, /* reg points to a percpu kernel variable */ }; /* The information passed from prog-specific *_is_valid_access @@ -423,11 +288,7 @@ enum bpf_reg_type { */ struct bpf_insn_access_aux { enum bpf_reg_type reg_type; - union { - int ctx_field_size; - u32 btf_id; - }; - struct bpf_verifier_log *log; /* for verbose logs */ + int ctx_field_size; }; static inline void @@ -461,11 +322,6 @@ struct bpf_verifier_ops { const struct bpf_insn *src, struct bpf_insn *dst, struct bpf_prog *prog, u32 *target_size); - int (*btf_struct_access)(struct bpf_verifier_log *log, - const struct btf_type *t, int off, int size, - enum bpf_access_type atype, - u32 *next_btf_id); - ANDROID_KABI_RESERVE(1); }; struct bpf_prog_offload_ops { @@ -481,7 +337,6 @@ struct bpf_prog_offload_ops { int (*prepare)(struct bpf_prog *prog); int (*translate)(struct bpf_prog *prog); void (*destroy)(struct bpf_prog *prog); - ANDROID_KABI_RESERVE(1); }; struct bpf_prog_offload { @@ -504,287 +359,14 @@ enum bpf_cgroup_storage_type { #define MAX_BPF_CGROUP_STORAGE_TYPE __BPF_CGROUP_STORAGE_MAX -/* The longest tracepoint has 12 args. - * See include/trace/bpf_probe.h - */ -#define MAX_BPF_FUNC_ARGS 12 - struct bpf_prog_stats { u64 cnt; u64 nsecs; struct u64_stats_sync syncp; -} __aligned(2 * sizeof(u64)); - -struct btf_func_model { - u8 ret_size; - u8 nr_args; - u8 arg_size[MAX_BPF_FUNC_ARGS]; -}; - -/* Restore arguments before returning from trampoline to let original function - * continue executing. This flag is used for fentry progs when there are no - * fexit progs. - */ -#define BPF_TRAMP_F_RESTORE_REGS BIT(0) -/* Call original function after fentry progs, but before fexit progs. - * Makes sense for fentry/fexit, normal calls and indirect calls. - */ -#define BPF_TRAMP_F_CALL_ORIG BIT(1) -/* Skip current frame and return to parent. Makes sense for fentry/fexit - * programs only. Should not be used with normal calls and indirect calls. - */ -#define BPF_TRAMP_F_SKIP_FRAME BIT(2) -/* Return the return value of fentry prog. Only used by bpf_struct_ops. */ -#define BPF_TRAMP_F_RET_FENTRY_RET BIT(4) - -/* Each call __bpf_prog_enter + call bpf_func + call __bpf_prog_exit is ~50 - * bytes on x86. Pick a number to fit into BPF_IMAGE_SIZE / 2 - */ -#define BPF_MAX_TRAMP_PROGS 40 - -struct bpf_tramp_progs { - struct bpf_prog *progs[BPF_MAX_TRAMP_PROGS]; - int nr_progs; -}; - -/* Different use cases for BPF trampoline: - * 1. replace nop at the function entry (kprobe equivalent) - * flags = BPF_TRAMP_F_RESTORE_REGS - * fentry = a set of programs to run before returning from trampoline - * - * 2. replace nop at the function entry (kprobe + kretprobe equivalent) - * flags = BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_SKIP_FRAME - * orig_call = fentry_ip + MCOUNT_INSN_SIZE - * fentry = a set of program to run before calling original function - * fexit = a set of program to run after original function - * - * 3. replace direct call instruction anywhere in the function body - * or assign a function pointer for indirect call (like tcp_congestion_ops->cong_avoid) - * With flags = 0 - * fentry = a set of programs to run before returning from trampoline - * With flags = BPF_TRAMP_F_CALL_ORIG - * orig_call = original callback addr or direct function addr - * fentry = a set of program to run before calling original function - * fexit = a set of program to run after original function - */ -struct bpf_tramp_image; -int arch_prepare_bpf_trampoline(struct bpf_tramp_image *tr, void *image, void *image_end, - const struct btf_func_model *m, u32 flags, - struct bpf_tramp_progs *tprogs, - void *orig_call); -/* these two functions are called from generated trampoline */ -u64 notrace __bpf_prog_enter(void); -void notrace __bpf_prog_exit(struct bpf_prog *prog, u64 start); -void notrace __bpf_prog_enter_sleepable(void); -void notrace __bpf_prog_exit_sleepable(void); -void notrace __bpf_tramp_enter(struct bpf_tramp_image *tr); -void notrace __bpf_tramp_exit(struct bpf_tramp_image *tr); - -struct bpf_ksym { - unsigned long start; - unsigned long end; - char name[KSYM_NAME_LEN]; - struct list_head lnode; - struct latch_tree_node tnode; - bool prog; -}; - -enum bpf_tramp_prog_type { - BPF_TRAMP_FENTRY, - BPF_TRAMP_FEXIT, - BPF_TRAMP_MODIFY_RETURN, - BPF_TRAMP_MAX, - BPF_TRAMP_REPLACE, /* more than MAX */ -}; - -struct bpf_tramp_image { - void *image; - struct bpf_ksym ksym; - struct percpu_ref pcref; - void *ip_after_call; - void *ip_epilogue; - union { - struct rcu_head rcu; - struct work_struct work; - }; -}; - -struct bpf_trampoline { - /* hlist for trampoline_table */ - struct hlist_node hlist; - /* serializes access to fields of this trampoline */ - struct mutex mutex; - refcount_t refcnt; - u64 key; - struct { - struct btf_func_model model; - void *addr; - bool ftrace_managed; - } func; - /* if !NULL this is BPF_PROG_TYPE_EXT program that extends another BPF - * program by replacing one of its functions. func.addr is the address - * of the function it replaced. - */ - struct bpf_prog *extension_prog; - /* list of BPF programs using this trampoline */ - struct hlist_head progs_hlist[BPF_TRAMP_MAX]; - /* Number of attached programs. A counter per kind. */ - int progs_cnt[BPF_TRAMP_MAX]; - /* Executable image of trampoline */ - struct bpf_tramp_image *cur_image; - u64 selector; -}; - -struct bpf_attach_target_info { - struct btf_func_model fmodel; - long tgt_addr; - const char *tgt_name; - const struct btf_type *tgt_type; -}; - -#define BPF_DISPATCHER_MAX 48 /* Fits in 2048B */ - -struct bpf_dispatcher_prog { - struct bpf_prog *prog; - refcount_t users; -}; - -struct bpf_dispatcher { - /* dispatcher mutex */ - struct mutex mutex; - void *func; - struct bpf_dispatcher_prog progs[BPF_DISPATCHER_MAX]; - int num_progs; - void *image; - u32 image_off; - struct bpf_ksym ksym; -}; - -static __always_inline __nocfi unsigned int bpf_dispatcher_nop_func( - const void *ctx, - const struct bpf_insn *insnsi, - unsigned int (*bpf_func)(const void *, - const struct bpf_insn *)) -{ - return bpf_func(ctx, insnsi); -} -#ifdef CONFIG_BPF_JIT -int bpf_trampoline_link_prog(struct bpf_prog *prog, struct bpf_trampoline *tr); -int bpf_trampoline_unlink_prog(struct bpf_prog *prog, struct bpf_trampoline *tr); -struct bpf_trampoline *bpf_trampoline_get(u64 key, - struct bpf_attach_target_info *tgt_info); -void bpf_trampoline_put(struct bpf_trampoline *tr); -int arch_prepare_bpf_dispatcher(void *image, s64 *funcs, int num_funcs); -#define BPF_DISPATCHER_INIT(_name) { \ - .mutex = __MUTEX_INITIALIZER(_name.mutex), \ - .func = &_name##_func, \ - .progs = {}, \ - .num_progs = 0, \ - .image = NULL, \ - .image_off = 0, \ - .ksym = { \ - .name = #_name, \ - .lnode = LIST_HEAD_INIT(_name.ksym.lnode), \ - }, \ -} - -#define DEFINE_BPF_DISPATCHER(name) \ - noinline __nocfi unsigned int bpf_dispatcher_##name##_func( \ - const void *ctx, \ - const struct bpf_insn *insnsi, \ - unsigned int (*bpf_func)(const void *, \ - const struct bpf_insn *)) \ - { \ - return bpf_func(ctx, insnsi); \ - } \ - EXPORT_SYMBOL(bpf_dispatcher_##name##_func); \ - struct bpf_dispatcher bpf_dispatcher_##name = \ - BPF_DISPATCHER_INIT(bpf_dispatcher_##name); -#define DECLARE_BPF_DISPATCHER(name) \ - unsigned int bpf_dispatcher_##name##_func( \ - const void *ctx, \ - const struct bpf_insn *insnsi, \ - unsigned int (*bpf_func)(const void *, \ - const struct bpf_insn *)); \ - extern struct bpf_dispatcher bpf_dispatcher_##name; -#define BPF_DISPATCHER_FUNC(name) bpf_dispatcher_##name##_func -#define BPF_DISPATCHER_PTR(name) (&bpf_dispatcher_##name) -void bpf_dispatcher_change_prog(struct bpf_dispatcher *d, struct bpf_prog *from, - struct bpf_prog *to); -/* Called only from JIT-enabled code, so there's no need for stubs. */ -void *bpf_jit_alloc_exec_page(void); -void bpf_image_ksym_add(void *data, struct bpf_ksym *ksym); -void bpf_image_ksym_del(struct bpf_ksym *ksym); -void bpf_ksym_add(struct bpf_ksym *ksym); -void bpf_ksym_del(struct bpf_ksym *ksym); -int bpf_jit_charge_modmem(u32 pages); -void bpf_jit_uncharge_modmem(u32 pages); -#else -static inline int bpf_trampoline_link_prog(struct bpf_prog *prog, - struct bpf_trampoline *tr) -{ - return -ENOTSUPP; -} -static inline int bpf_trampoline_unlink_prog(struct bpf_prog *prog, - struct bpf_trampoline *tr) -{ - return -ENOTSUPP; -} -static inline struct bpf_trampoline *bpf_trampoline_get(u64 key, - struct bpf_attach_target_info *tgt_info) -{ - return NULL; -} -static inline void bpf_trampoline_put(struct bpf_trampoline *tr) {} -#define DEFINE_BPF_DISPATCHER(name) -#define DECLARE_BPF_DISPATCHER(name) -#define BPF_DISPATCHER_FUNC(name) bpf_dispatcher_nop_func -#define BPF_DISPATCHER_PTR(name) NULL -static inline void bpf_dispatcher_change_prog(struct bpf_dispatcher *d, - struct bpf_prog *from, - struct bpf_prog *to) {} -static inline bool is_bpf_image_address(unsigned long address) -{ - return false; -} -#endif - -struct bpf_func_info_aux { - u16 linkage; - bool unreliable; -}; - -enum bpf_jit_poke_reason { - BPF_POKE_REASON_TAIL_CALL, -}; - -/* Descriptor of pokes pointing /into/ the JITed image. */ -struct bpf_jit_poke_descriptor { - void *tailcall_target; - void *tailcall_bypass; - void *bypass_addr; - void *aux; - union { - struct { - struct bpf_map *map; - u32 key; - } tail_call; - }; - bool tailcall_target_stable; - u8 adj_off; - u16 reason; - u32 insn_idx; -}; - -/* reg_type info for ctx arguments */ -struct bpf_ctx_arg_aux { - u32 offset; - enum bpf_reg_type reg_type; - u32 btf_id; }; struct bpf_prog_aux { - atomic64_t refcnt; + atomic_t refcnt; u32 used_map_cnt; u32 max_ctx_offset; u32 max_pkt_offset; @@ -793,35 +375,14 @@ struct bpf_prog_aux { u32 id; u32 func_cnt; /* used by non-func prog as the number of func progs */ u32 func_idx; /* 0 for non-func prog, the index in func array for func prog */ - u32 attach_btf_id; /* in-kernel BTF type id to attach to */ - u32 ctx_arg_info_size; - u32 max_rdonly_access; - u32 max_rdwr_access; - const struct bpf_ctx_arg_aux *ctx_arg_info; - struct mutex dst_mutex; /* protects dst_* pointers below, *after* prog becomes visible */ - struct bpf_prog *dst_prog; - struct bpf_trampoline *dst_trampoline; - enum bpf_prog_type saved_dst_prog_type; - enum bpf_attach_type saved_dst_attach_type; bool verifier_zext; /* Zero extensions has been inserted by verifier. */ bool offload_requested; - bool attach_btf_trace; /* true if attaching to BTF-enabled raw tp */ - bool func_proto_unreliable; - bool sleepable; - bool tail_call_reachable; - struct hlist_node tramp_hlist; - /* BTF_KIND_FUNC_PROTO for valid attach_btf_id */ - const struct btf_type *attach_func_proto; - /* function name for valid attach_btf_id */ - const char *attach_func_name; struct bpf_prog **func; void *jit_data; /* JIT specific data. arch dependent */ - struct bpf_jit_poke_descriptor *poke_tab; - u32 size_poke_tab; - struct bpf_ksym ksym; + struct latch_tree_node ksym_tnode; + struct list_head ksym_lnode; const struct bpf_prog_ops *ops; struct bpf_map **used_maps; - struct mutex used_maps_mutex; /* mutex for used_maps and used_map_cnt */ struct bpf_prog *prog; struct user_struct *user; u64 load_time; /* ns since boottime */ @@ -833,7 +394,6 @@ struct bpf_prog_aux { struct bpf_prog_offload *offload; struct btf *btf; struct bpf_func_info *func_info; - struct bpf_func_info_aux *func_info_aux; /* bpf_line_info loaded from userspace. linfo->insn_off * has the xlated insn offset. * Both the main and sub prog share the same linfo. @@ -856,136 +416,24 @@ struct bpf_prog_aux { * main prog always has linfo_idx == 0 */ u32 linfo_idx; - u32 num_exentries; - struct exception_table_entry *extable; struct bpf_prog_stats __percpu *stats; union { struct work_struct work; struct rcu_head rcu; }; - ANDROID_KABI_RESERVE(1); }; -struct bpf_array_aux { - /* 'Ownership' of prog array is claimed by the first program that - * is going to use this map or by the first program which FD is - * stored in the map to make sure that all callers and callees have - * the same prog type and JITed flag. - */ - struct { - spinlock_t lock; - enum bpf_prog_type type; - bool jited; - } owner; - /* Programs with direct jumps into programs part of this array. */ - struct list_head poke_progs; - struct bpf_map *map; - struct mutex poke_mutex; - struct work_struct work; -}; - -struct bpf_link { - atomic64_t refcnt; - u32 id; - enum bpf_link_type type; - const struct bpf_link_ops *ops; - struct bpf_prog *prog; - struct work_struct work; -}; - -struct bpf_link_ops { - void (*release)(struct bpf_link *link); - void (*dealloc)(struct bpf_link *link); - int (*detach)(struct bpf_link *link); - int (*update_prog)(struct bpf_link *link, struct bpf_prog *new_prog, - struct bpf_prog *old_prog); - void (*show_fdinfo)(const struct bpf_link *link, struct seq_file *seq); - int (*fill_link_info)(const struct bpf_link *link, - struct bpf_link_info *info); -}; - -struct bpf_link_primer { - struct bpf_link *link; - struct file *file; - int fd; - u32 id; -}; - -struct bpf_struct_ops_value; -struct btf_type; -struct btf_member; - -#define BPF_STRUCT_OPS_MAX_NR_MEMBERS 64 -struct bpf_struct_ops { - const struct bpf_verifier_ops *verifier_ops; - int (*init)(struct btf *btf); - int (*check_member)(const struct btf_type *t, - const struct btf_member *member); - int (*init_member)(const struct btf_type *t, - const struct btf_member *member, - void *kdata, const void *udata); - int (*reg)(void *kdata); - void (*unreg)(void *kdata); - const struct btf_type *type; - const struct btf_type *value_type; - const char *name; - struct btf_func_model func_models[BPF_STRUCT_OPS_MAX_NR_MEMBERS]; - u32 type_id; - u32 value_id; -}; - -#if defined(CONFIG_BPF_JIT) && defined(CONFIG_BPF_SYSCALL) -#define BPF_MODULE_OWNER ((void *)((0xeB9FUL << 2) + POISON_POINTER_DELTA)) -const struct bpf_struct_ops *bpf_struct_ops_find(u32 type_id); -void bpf_struct_ops_init(struct btf *btf, struct bpf_verifier_log *log); -bool bpf_struct_ops_get(const void *kdata); -void bpf_struct_ops_put(const void *kdata); -int bpf_struct_ops_map_sys_lookup_elem(struct bpf_map *map, void *key, - void *value); -static inline bool bpf_try_module_get(const void *data, struct module *owner) -{ - if (owner == BPF_MODULE_OWNER) - return bpf_struct_ops_get(data); - else - return try_module_get(owner); -} -static inline void bpf_module_put(const void *data, struct module *owner) -{ - if (owner == BPF_MODULE_OWNER) - bpf_struct_ops_put(data); - else - module_put(owner); -} -#else -static inline const struct bpf_struct_ops *bpf_struct_ops_find(u32 type_id) -{ - return NULL; -} -static inline void bpf_struct_ops_init(struct btf *btf, - struct bpf_verifier_log *log) -{ -} -static inline bool bpf_try_module_get(const void *data, struct module *owner) -{ - return try_module_get(owner); -} -static inline void bpf_module_put(const void *data, struct module *owner) -{ - module_put(owner); -} -static inline int bpf_struct_ops_map_sys_lookup_elem(struct bpf_map *map, - void *key, - void *value) -{ - return -EINVAL; -} -#endif - struct bpf_array { struct bpf_map map; u32 elem_size; u32 index_mask; - struct bpf_array_aux *aux; + /* 'ownership' of prog_array is claimed by the first program that + * is going to use this map or by the first program which FD is stored + * in the map to make sure that all callers and callees have the same + * prog_type and JITed flag + */ + enum bpf_prog_type owner_prog_type; + bool owner_jited; union { char value[0] __aligned(8); void *ptrs[0] __aligned(8); @@ -1034,7 +482,6 @@ struct bpf_event_entry { bool bpf_prog_array_compatible(struct bpf_array *array, const struct bpf_prog *fp); int bpf_prog_calc_tag(struct bpf_prog *fp); -const char *kernel_type_name(u32 btf_type_id); const struct bpf_func_proto *bpf_get_trace_printk_proto(void); @@ -1068,7 +515,7 @@ struct bpf_prog_array_item { struct bpf_prog_array { struct rcu_head rcu; - struct bpf_prog_array_item items[]; + struct bpf_prog_array_item items[0]; }; struct bpf_prog_array *bpf_prog_array_alloc(u32 prog_cnt, gfp_t flags); @@ -1080,9 +527,6 @@ int bpf_prog_array_copy_to_user(struct bpf_prog_array *progs, void bpf_prog_array_delete_safe(struct bpf_prog_array *progs, struct bpf_prog *old_prog); -int bpf_prog_array_delete_safe_at(struct bpf_prog_array *array, int index); -int bpf_prog_array_update_at(struct bpf_prog_array *array, int index, - struct bpf_prog *prog); int bpf_prog_array_copy_info(struct bpf_prog_array *array, u32 *prog_ids, u32 request_cnt, u32 *prog_cnt); @@ -1097,26 +541,21 @@ int bpf_prog_array_copy(struct bpf_prog_array *old_array, struct bpf_prog *_prog; \ struct bpf_prog_array *_array; \ u32 _ret = 1; \ - migrate_disable(); \ + preempt_disable(); \ rcu_read_lock(); \ _array = rcu_dereference(array); \ if (unlikely(check_non_null && !_array))\ goto _out; \ _item = &_array->items[0]; \ while ((_prog = READ_ONCE(_item->prog))) { \ - if (!set_cg_storage) { \ - _ret &= func(_prog, ctx); \ - } else { \ - if (unlikely(bpf_cgroup_storage_set(_item->cgroup_storage))) \ - break; \ - _ret &= func(_prog, ctx); \ - bpf_cgroup_storage_unset(); \ - } \ + if (set_cg_storage) \ + bpf_cgroup_storage_set(_item->cgroup_storage); \ + _ret &= func(_prog, ctx); \ _item++; \ } \ _out: \ rcu_read_unlock(); \ - migrate_enable(); \ + preempt_enable(); \ _ret; \ }) @@ -1150,21 +589,19 @@ _out: \ u32 ret; \ u32 _ret = 1; \ u32 _cn = 0; \ - migrate_disable(); \ + preempt_disable(); \ rcu_read_lock(); \ _array = rcu_dereference(array); \ _item = &_array->items[0]; \ while ((_prog = READ_ONCE(_item->prog))) { \ - if (unlikely(bpf_cgroup_storage_set(_item->cgroup_storage))) \ - break; \ + bpf_cgroup_storage_set(_item->cgroup_storage); \ ret = func(_prog, ctx); \ - bpf_cgroup_storage_unset(); \ _ret &= (ret & 1); \ _cn |= (ret & 2); \ _item++; \ } \ rcu_read_unlock(); \ - migrate_enable(); \ + preempt_enable(); \ if (_ret) \ _ret = (_cn ? NET_XMIT_CN : NET_XMIT_SUCCESS); \ else \ @@ -1180,52 +617,18 @@ _out: \ #ifdef CONFIG_BPF_SYSCALL DECLARE_PER_CPU(int, bpf_prog_active); -extern struct mutex bpf_stats_enabled_mutex; - -/* - * Block execution of BPF programs attached to instrumentation (perf, - * kprobes, tracepoints) to prevent deadlocks on map operations as any of - * these events can happen inside a region which holds a map bucket lock - * and can deadlock on it. - * - * Use the preemption safe inc/dec variants on RT because migrate disable - * is preemptible on RT and preemption in the middle of the RMW operation - * might lead to inconsistent state. Use the raw variants for non RT - * kernels as migrate_disable() maps to preempt_disable() so the slightly - * more expensive save operation can be avoided. - */ -static inline void bpf_disable_instrumentation(void) -{ - migrate_disable(); - if (IS_ENABLED(CONFIG_PREEMPT_RT)) - this_cpu_inc(bpf_prog_active); - else - __this_cpu_inc(bpf_prog_active); -} - -static inline void bpf_enable_instrumentation(void) -{ - if (IS_ENABLED(CONFIG_PREEMPT_RT)) - this_cpu_dec(bpf_prog_active); - else - __this_cpu_dec(bpf_prog_active); - migrate_enable(); -} extern const struct file_operations bpf_map_fops; extern const struct file_operations bpf_prog_fops; -extern const struct file_operations bpf_iter_fops; -#define BPF_PROG_TYPE(_id, _name, prog_ctx_type, kern_ctx_type) \ +#define BPF_PROG_TYPE(_id, _name) \ extern const struct bpf_prog_ops _name ## _prog_ops; \ extern const struct bpf_verifier_ops _name ## _verifier_ops; #define BPF_MAP_TYPE(_id, _ops) \ extern const struct bpf_map_ops _ops; -#define BPF_LINK_TYPE(_id, _name) #include #undef BPF_PROG_TYPE #undef BPF_MAP_TYPE -#undef BPF_LINK_TYPE extern const struct bpf_prog_ops bpf_offload_prog_ops; extern const struct bpf_verifier_ops tc_cls_act_analyzer_ops; @@ -1234,9 +637,9 @@ extern const struct bpf_verifier_ops xdp_analyzer_ops; struct bpf_prog *bpf_prog_get(u32 ufd); struct bpf_prog *bpf_prog_get_type_dev(u32 ufd, enum bpf_prog_type type, bool attach_drv); -void bpf_prog_add(struct bpf_prog *prog, int i); +struct bpf_prog * __must_check bpf_prog_add(struct bpf_prog *prog, int i); void bpf_prog_sub(struct bpf_prog *prog, int i); -void bpf_prog_inc(struct bpf_prog *prog); +struct bpf_prog * __must_check bpf_prog_inc(struct bpf_prog *prog); struct bpf_prog * __must_check bpf_prog_inc_not_zero(struct bpf_prog *prog); void bpf_prog_put(struct bpf_prog *prog); int __bpf_prog_charge(struct user_struct *user, u32 pages); @@ -1245,12 +648,11 @@ void __bpf_prog_uncharge(struct user_struct *user, u32 pages); void bpf_prog_free_id(struct bpf_prog *prog, bool do_idr_lock); void bpf_map_free_id(struct bpf_map *map, bool do_idr_lock); -struct bpf_map *bpf_map_get(u32 ufd); struct bpf_map *bpf_map_get_with_uref(u32 ufd); struct bpf_map *__bpf_map_get(struct fd f); -void bpf_map_inc(struct bpf_map *map); -void bpf_map_inc_with_uref(struct bpf_map *map); -struct bpf_map * __must_check bpf_map_inc_not_zero(struct bpf_map *map); +struct bpf_map * __must_check bpf_map_inc(struct bpf_map *map, bool uref); +struct bpf_map * __must_check bpf_map_inc_not_zero(struct bpf_map *map, + bool uref); void bpf_map_put_with_uref(struct bpf_map *map); void bpf_map_put(struct bpf_map *map); int bpf_map_charge_memlock(struct bpf_map *map, u32 pages); @@ -1260,122 +662,17 @@ void bpf_map_charge_finish(struct bpf_map_memory *mem); void bpf_map_charge_move(struct bpf_map_memory *dst, struct bpf_map_memory *src); void *bpf_map_area_alloc(u64 size, int numa_node); -void *bpf_map_area_mmapable_alloc(u64 size, int numa_node); void bpf_map_area_free(void *base); -bool bpf_map_write_active(const struct bpf_map *map); void bpf_map_init_from_attr(struct bpf_map *map, union bpf_attr *attr); -int generic_map_lookup_batch(struct bpf_map *map, - const union bpf_attr *attr, - union bpf_attr __user *uattr); -int generic_map_update_batch(struct bpf_map *map, - const union bpf_attr *attr, - union bpf_attr __user *uattr); -int generic_map_delete_batch(struct bpf_map *map, - const union bpf_attr *attr, - union bpf_attr __user *uattr); -struct bpf_map *bpf_map_get_curr_or_next(u32 *id); -struct bpf_prog *bpf_prog_get_curr_or_next(u32 *id); extern int sysctl_unprivileged_bpf_disabled; -static inline bool bpf_allow_ptr_leaks(void) -{ - return perfmon_capable(); -} - -static inline bool bpf_allow_uninit_stack(void) -{ - return perfmon_capable(); -} - -static inline bool bpf_allow_ptr_to_map_access(void) -{ - return perfmon_capable(); -} - -static inline bool bpf_bypass_spec_v1(void) -{ - return perfmon_capable(); -} - -static inline bool bpf_bypass_spec_v4(void) -{ - return perfmon_capable(); -} - int bpf_map_new_fd(struct bpf_map *map, int flags); int bpf_prog_new_fd(struct bpf_prog *prog); -void bpf_link_init(struct bpf_link *link, enum bpf_link_type type, - const struct bpf_link_ops *ops, struct bpf_prog *prog); -int bpf_link_prime(struct bpf_link *link, struct bpf_link_primer *primer); -int bpf_link_settle(struct bpf_link_primer *primer); -void bpf_link_cleanup(struct bpf_link_primer *primer); -void bpf_link_inc(struct bpf_link *link); -void bpf_link_put(struct bpf_link *link); -int bpf_link_new_fd(struct bpf_link *link); -struct file *bpf_link_new_file(struct bpf_link *link, int *reserved_fd); -struct bpf_link *bpf_link_get_from_fd(u32 ufd); - int bpf_obj_pin_user(u32 ufd, const char __user *pathname); int bpf_obj_get_user(const char __user *pathname, int flags); -#define BPF_ITER_FUNC_PREFIX "bpf_iter_" -#define DEFINE_BPF_ITER_FUNC(target, args...) \ - extern int bpf_iter_ ## target(args); \ - int __init bpf_iter_ ## target(args) { return 0; } - -struct bpf_iter_aux_info { - struct bpf_map *map; -}; - -typedef int (*bpf_iter_attach_target_t)(struct bpf_prog *prog, - union bpf_iter_link_info *linfo, - struct bpf_iter_aux_info *aux); -typedef void (*bpf_iter_detach_target_t)(struct bpf_iter_aux_info *aux); -typedef void (*bpf_iter_show_fdinfo_t) (const struct bpf_iter_aux_info *aux, - struct seq_file *seq); -typedef int (*bpf_iter_fill_link_info_t)(const struct bpf_iter_aux_info *aux, - struct bpf_link_info *info); - -#define BPF_ITER_CTX_ARG_MAX 2 -struct bpf_iter_reg { - const char *target; - bpf_iter_attach_target_t attach_target; - bpf_iter_detach_target_t detach_target; - bpf_iter_show_fdinfo_t show_fdinfo; - bpf_iter_fill_link_info_t fill_link_info; - u32 ctx_arg_info_size; - struct bpf_ctx_arg_aux ctx_arg_info[BPF_ITER_CTX_ARG_MAX]; - const struct bpf_iter_seq_info *seq_info; -}; - -struct bpf_iter_meta { - __bpf_md_ptr(struct seq_file *, seq); - u64 session_id; - u64 seq_num; -}; - -struct bpf_iter__bpf_map_elem { - __bpf_md_ptr(struct bpf_iter_meta *, meta); - __bpf_md_ptr(struct bpf_map *, map); - __bpf_md_ptr(void *, key); - __bpf_md_ptr(void *, value); -}; - -int bpf_iter_reg_target(const struct bpf_iter_reg *reg_info); -void bpf_iter_unreg_target(const struct bpf_iter_reg *reg_info); -bool bpf_iter_prog_supported(struct bpf_prog *prog); -int bpf_iter_link_attach(const union bpf_attr *attr, struct bpf_prog *prog); -int bpf_iter_new_fd(struct bpf_link *link); -bool bpf_link_is_iter(struct bpf_link *link); -struct bpf_prog *bpf_iter_get_info(struct bpf_iter_meta *meta, bool in_stop); -int bpf_iter_run_prog(struct bpf_prog *prog, void *ctx); -void bpf_iter_map_show_fdinfo(const struct bpf_iter_aux_info *aux, - struct seq_file *seq); -int bpf_iter_map_fill_link_info(const struct bpf_iter_aux_info *aux, - struct bpf_link_info *info); - int bpf_percpu_hash_copy(struct bpf_map *map, void *key, void *value); int bpf_percpu_array_copy(struct bpf_map *map, void *key, void *value); int bpf_percpu_hash_update(struct bpf_map *map, void *key, void *value, @@ -1420,28 +717,22 @@ int bpf_check(struct bpf_prog **fp, union bpf_attr *attr, void bpf_patch_call_args(struct bpf_insn *insn, u32 stack_depth); #endif -struct btf *bpf_get_btf_vmlinux(void); - /* Map specifics */ struct xdp_buff; struct sk_buff; struct bpf_dtab_netdev *__dev_map_lookup_elem(struct bpf_map *map, u32 key); struct bpf_dtab_netdev *__dev_map_hash_lookup_elem(struct bpf_map *map, u32 key); -void __dev_flush(void); -int dev_xdp_enqueue(struct net_device *dev, struct xdp_buff *xdp, - struct net_device *dev_rx); +void __dev_map_flush(struct bpf_map *map); int dev_map_enqueue(struct bpf_dtab_netdev *dst, struct xdp_buff *xdp, struct net_device *dev_rx); int dev_map_generic_redirect(struct bpf_dtab_netdev *dst, struct sk_buff *skb, struct bpf_prog *xdp_prog); -bool dev_map_can_have_prog(struct bpf_map *map); struct bpf_cpu_map_entry *__cpu_map_lookup_elem(struct bpf_map *map, u32 key); -void __cpu_map_flush(void); +void __cpu_map_flush(struct bpf_map *map); int cpu_map_enqueue(struct bpf_cpu_map_entry *rcpu, struct xdp_buff *xdp, struct net_device *dev_rx); -bool cpu_map_prog_allowed(struct bpf_map *map); /* Return map's numa specified by userspace */ static inline int bpf_map_attr_numa_node(const union bpf_attr *attr) @@ -1457,43 +748,9 @@ int bpf_prog_test_run_xdp(struct bpf_prog *prog, const union bpf_attr *kattr, union bpf_attr __user *uattr); int bpf_prog_test_run_skb(struct bpf_prog *prog, const union bpf_attr *kattr, union bpf_attr __user *uattr); -int bpf_prog_test_run_tracing(struct bpf_prog *prog, - const union bpf_attr *kattr, - union bpf_attr __user *uattr); int bpf_prog_test_run_flow_dissector(struct bpf_prog *prog, const union bpf_attr *kattr, union bpf_attr __user *uattr); -int bpf_prog_test_run_raw_tp(struct bpf_prog *prog, - const union bpf_attr *kattr, - union bpf_attr __user *uattr); -bool btf_ctx_access(int off, int size, enum bpf_access_type type, - const struct bpf_prog *prog, - struct bpf_insn_access_aux *info); -int btf_struct_access(struct bpf_verifier_log *log, - const struct btf_type *t, int off, int size, - enum bpf_access_type atype, - u32 *next_btf_id); -bool btf_struct_ids_match(struct bpf_verifier_log *log, - int off, u32 id, u32 need_type_id); - -int btf_distill_func_proto(struct bpf_verifier_log *log, - struct btf *btf, - const struct btf_type *func_proto, - const char *func_name, - struct btf_func_model *m); - -struct bpf_reg_state; -int btf_check_func_arg_match(struct bpf_verifier_env *env, int subprog, - struct bpf_reg_state *regs); -int btf_prepare_func_args(struct bpf_verifier_env *env, int subprog, - struct bpf_reg_state *reg); -int btf_check_type_match(struct bpf_verifier_log *log, const struct bpf_prog *prog, - struct btf *btf, const struct btf_type *t); - -struct bpf_prog *bpf_prog_by_id(u32 id); -struct bpf_link *bpf_link_by_id(u32 id); - -const struct bpf_func_proto *bpf_base_func_proto(enum bpf_func_id func_id); static inline bool unprivileged_ebpf_enabled(void) { @@ -1513,8 +770,10 @@ static inline struct bpf_prog *bpf_prog_get_type_dev(u32 ufd, return ERR_PTR(-EOPNOTSUPP); } -static inline void bpf_prog_add(struct bpf_prog *prog, int i) +static inline struct bpf_prog * __must_check bpf_prog_add(struct bpf_prog *prog, + int i) { + return ERR_PTR(-EOPNOTSUPP); } static inline void bpf_prog_sub(struct bpf_prog *prog, int i) @@ -1525,8 +784,9 @@ static inline void bpf_prog_put(struct bpf_prog *prog) { } -static inline void bpf_prog_inc(struct bpf_prog *prog) +static inline struct bpf_prog * __must_check bpf_prog_inc(struct bpf_prog *prog) { + return ERR_PTR(-EOPNOTSUPP); } static inline struct bpf_prog *__must_check @@ -1544,35 +804,6 @@ static inline void __bpf_prog_uncharge(struct user_struct *user, u32 pages) { } -static inline void bpf_link_init(struct bpf_link *link, enum bpf_link_type type, - const struct bpf_link_ops *ops, - struct bpf_prog *prog) -{ -} - -static inline int bpf_link_prime(struct bpf_link *link, - struct bpf_link_primer *primer) -{ - return -EOPNOTSUPP; -} - -static inline int bpf_link_settle(struct bpf_link_primer *primer) -{ - return -EOPNOTSUPP; -} - -static inline void bpf_link_cleanup(struct bpf_link_primer *primer) -{ -} - -static inline void bpf_link_inc(struct bpf_link *link) -{ -} - -static inline void bpf_link_put(struct bpf_link *link) -{ -} - static inline int bpf_obj_get_user(const char __user *pathname, int flags) { return -EOPNOTSUPP; @@ -1589,25 +820,14 @@ static inline struct net_device *__dev_map_hash_lookup_elem(struct bpf_map *map { return NULL; } -static inline bool dev_map_can_have_prog(struct bpf_map *map) -{ - return false; -} -static inline void __dev_flush(void) +static inline void __dev_map_flush(struct bpf_map *map) { } struct xdp_buff; struct bpf_dtab_netdev; -static inline -int dev_xdp_enqueue(struct net_device *dev, struct xdp_buff *xdp, - struct net_device *dev_rx) -{ - return 0; -} - static inline int dev_map_enqueue(struct bpf_dtab_netdev *dst, struct xdp_buff *xdp, struct net_device *dev_rx) @@ -1630,7 +850,7 @@ struct bpf_cpu_map_entry *__cpu_map_lookup_elem(struct bpf_map *map, u32 key) return NULL; } -static inline void __cpu_map_flush(void) +static inline void __cpu_map_flush(struct bpf_map *map) { } @@ -1641,11 +861,6 @@ static inline int cpu_map_enqueue(struct bpf_cpu_map_entry *rcpu, return 0; } -static inline bool cpu_map_prog_allowed(struct bpf_map *map) -{ - return false; -} - static inline struct bpf_prog *bpf_prog_get_type_path(const char *name, enum bpf_prog_type type) { @@ -1666,13 +881,6 @@ static inline int bpf_prog_test_run_skb(struct bpf_prog *prog, return -ENOTSUPP; } -static inline int bpf_prog_test_run_tracing(struct bpf_prog *prog, - const union bpf_attr *kattr, - union bpf_attr __user *uattr) -{ - return -ENOTSUPP; -} - static inline int bpf_prog_test_run_flow_dissector(struct bpf_prog *prog, const union bpf_attr *kattr, union bpf_attr __user *uattr) @@ -1680,21 +888,6 @@ static inline int bpf_prog_test_run_flow_dissector(struct bpf_prog *prog, return -ENOTSUPP; } -static inline void bpf_map_put(struct bpf_map *map) -{ -} - -static inline struct bpf_prog *bpf_prog_by_id(u32 id) -{ - return ERR_PTR(-ENOTSUPP); -} - -static inline const struct bpf_func_proto * -bpf_base_func_proto(enum bpf_func_id func_id) -{ - return NULL; -} - static inline bool unprivileged_ebpf_enabled(void) { return false; @@ -1708,9 +901,6 @@ static inline struct bpf_prog *bpf_prog_get_type(u32 ufd, return bpf_prog_get_type_dev(ufd, type, false); } -void __bpf_free_used_maps(struct bpf_prog_aux *aux, - struct bpf_map **used_maps, u32 len); - bool bpf_prog_get_ok(struct bpf_prog *, enum bpf_prog_type *, bool); int bpf_prog_offload_compile(struct bpf_prog *prog); @@ -1783,27 +973,12 @@ static inline void bpf_map_offload_map_free(struct bpf_map *map) } #endif /* CONFIG_NET && CONFIG_BPF_SYSCALL */ -#if defined(CONFIG_INET) && defined(CONFIG_BPF_SYSCALL) +#if defined(CONFIG_BPF_STREAM_PARSER) int sock_map_prog_update(struct bpf_map *map, struct bpf_prog *prog, struct bpf_prog *old, u32 which); int sock_map_get_from_fd(const union bpf_attr *attr, struct bpf_prog *prog); int sock_map_prog_detach(const union bpf_attr *attr, enum bpf_prog_type ptype); -int sock_map_update_elem_sys(struct bpf_map *map, void *key, void *value, u64 flags); -void sock_map_unhash(struct sock *sk); -void sock_map_destroy(struct sock *sk); -void sock_map_close(struct sock *sk, long timeout); - -void bpf_sk_reuseport_detach(struct sock *sk); -int bpf_fd_reuseport_array_lookup_elem(struct bpf_map *map, void *key, - void *value); -int bpf_fd_reuseport_array_update_elem(struct bpf_map *map, void *key, - void *value, u64 map_flags); #else -static inline void bpf_sk_reuseport_detach(struct sock *sk) -{ -} - -#ifdef CONFIG_BPF_SYSCALL static inline int sock_map_prog_update(struct bpf_map *map, struct bpf_prog *prog, struct bpf_prog *old, u32 which) @@ -1822,13 +997,45 @@ static inline int sock_map_prog_detach(const union bpf_attr *attr, { return -EOPNOTSUPP; } +#endif -static inline int sock_map_update_elem_sys(struct bpf_map *map, void *key, void *value, - u64 flags) +#if defined(CONFIG_XDP_SOCKETS) +struct xdp_sock; +struct xdp_sock *__xsk_map_lookup_elem(struct bpf_map *map, u32 key); +int __xsk_map_redirect(struct bpf_map *map, struct xdp_buff *xdp, + struct xdp_sock *xs); +void __xsk_map_flush(struct bpf_map *map); +#else +struct xdp_sock; +static inline struct xdp_sock *__xsk_map_lookup_elem(struct bpf_map *map, + u32 key) +{ + return NULL; +} + +static inline int __xsk_map_redirect(struct bpf_map *map, struct xdp_buff *xdp, + struct xdp_sock *xs) { return -EOPNOTSUPP; } +static inline void __xsk_map_flush(struct bpf_map *map) +{ +} +#endif + +#if defined(CONFIG_INET) && defined(CONFIG_BPF_SYSCALL) +void bpf_sk_reuseport_detach(struct sock *sk); +int bpf_fd_reuseport_array_lookup_elem(struct bpf_map *map, void *key, + void *value); +int bpf_fd_reuseport_array_update_elem(struct bpf_map *map, void *key, + void *value, u64 map_flags); +#else +static inline void bpf_sk_reuseport_detach(struct sock *sk) +{ +} + +#ifdef CONFIG_BPF_SYSCALL static inline int bpf_fd_reuseport_array_lookup_elem(struct bpf_map *map, void *key, void *value) { @@ -1863,13 +1070,9 @@ extern const struct bpf_func_proto bpf_get_current_uid_gid_proto; extern const struct bpf_func_proto bpf_get_current_comm_proto; extern const struct bpf_func_proto bpf_get_stackid_proto; extern const struct bpf_func_proto bpf_get_stack_proto; -extern const struct bpf_func_proto bpf_get_task_stack_proto; -extern const struct bpf_func_proto bpf_get_stackid_proto_pe; -extern const struct bpf_func_proto bpf_get_stack_proto_pe; extern const struct bpf_func_proto bpf_sock_map_update_proto; extern const struct bpf_func_proto bpf_sock_hash_update_proto; extern const struct bpf_func_proto bpf_get_current_cgroup_id_proto; -extern const struct bpf_func_proto bpf_get_current_ancestor_cgroup_id_proto; extern const struct bpf_func_proto bpf_msg_redirect_hash_proto; extern const struct bpf_func_proto bpf_msg_redirect_map_proto; extern const struct bpf_func_proto bpf_sk_redirect_hash_proto; @@ -1880,34 +1083,10 @@ extern const struct bpf_func_proto bpf_get_local_storage_proto; extern const struct bpf_func_proto bpf_strtol_proto; extern const struct bpf_func_proto bpf_strtoul_proto; extern const struct bpf_func_proto bpf_tcp_sock_proto; -extern const struct bpf_func_proto bpf_jiffies64_proto; -extern const struct bpf_func_proto bpf_get_ns_current_pid_tgid_proto; -extern const struct bpf_func_proto bpf_event_output_data_proto; -extern const struct bpf_func_proto bpf_ringbuf_output_proto; -extern const struct bpf_func_proto bpf_ringbuf_reserve_proto; -extern const struct bpf_func_proto bpf_ringbuf_submit_proto; -extern const struct bpf_func_proto bpf_ringbuf_discard_proto; -extern const struct bpf_func_proto bpf_ringbuf_query_proto; -extern const struct bpf_func_proto bpf_skc_to_tcp6_sock_proto; -extern const struct bpf_func_proto bpf_skc_to_tcp_sock_proto; -extern const struct bpf_func_proto bpf_skc_to_tcp_timewait_sock_proto; -extern const struct bpf_func_proto bpf_skc_to_tcp_request_sock_proto; -extern const struct bpf_func_proto bpf_skc_to_udp6_sock_proto; -extern const struct bpf_func_proto bpf_copy_from_user_proto; -extern const struct bpf_func_proto bpf_snprintf_btf_proto; -extern const struct bpf_func_proto bpf_per_cpu_ptr_proto; -extern const struct bpf_func_proto bpf_this_cpu_ptr_proto; - -const struct bpf_func_proto *bpf_tracing_func_proto( - enum bpf_func_id func_id, const struct bpf_prog *prog); - -const struct bpf_func_proto *tracing_prog_func_proto( - enum bpf_func_id func_id, const struct bpf_prog *prog); /* Shared helpers among cBPF and eBPF. */ void bpf_user_rnd_init_once(void); u64 bpf_user_rnd_u32(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5); -u64 bpf_get_raw_cpu_id(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5); #if defined(CONFIG_NET) bool bpf_sock_common_is_valid_access(int off, int size, @@ -1944,15 +1123,6 @@ static inline u32 bpf_sock_convert_ctx_access(enum bpf_access_type type, #endif #ifdef CONFIG_INET -struct sk_reuseport_kern { - struct sk_buff *skb; - struct sock *sk; - struct sock *selected_sk; - void *data_end; - u32 hash; - u32 reuseport_id; - bool bind_inany; -}; bool bpf_tcp_sock_is_valid_access(int off, int size, enum bpf_access_type type, struct bpf_insn_access_aux *info); @@ -2003,15 +1173,4 @@ static inline u32 bpf_xdp_sock_convert_ctx_access(enum bpf_access_type type, } #endif /* CONFIG_INET */ -enum bpf_text_poke_type { - BPF_MOD_CALL, - BPF_MOD_JUMP, -}; - -int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t, - void *addr1, void *addr2); - -struct btf_id_set; -bool btf_id_set_contains(const struct btf_id_set *set, u32 id); - #endif /* _LINUX_BPF_H */ diff --git a/include/linux/bpf_local_storage.h b/include/linux/bpf_local_storage.h deleted file mode 100644 index b2c9463f36a1..000000000000 --- a/include/linux/bpf_local_storage.h +++ /dev/null @@ -1,163 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 Facebook - * Copyright 2020 Google LLC. - */ - -#ifndef _BPF_LOCAL_STORAGE_H -#define _BPF_LOCAL_STORAGE_H - -#include -#include -#include -#include -#include -#include - -#define BPF_LOCAL_STORAGE_CACHE_SIZE 16 - -struct bpf_local_storage_map_bucket { - struct hlist_head list; - raw_spinlock_t lock; -}; - -/* Thp map is not the primary owner of a bpf_local_storage_elem. - * Instead, the container object (eg. sk->sk_bpf_storage) is. - * - * The map (bpf_local_storage_map) is for two purposes - * 1. Define the size of the "local storage". It is - * the map's value_size. - * - * 2. Maintain a list to keep track of all elems such - * that they can be cleaned up during the map destruction. - * - * When a bpf local storage is being looked up for a - * particular object, the "bpf_map" pointer is actually used - * as the "key" to search in the list of elem in - * the respective bpf_local_storage owned by the object. - * - * e.g. sk->sk_bpf_storage is the mini-map with the "bpf_map" pointer - * as the searching key. - */ -struct bpf_local_storage_map { - struct bpf_map map; - /* Lookup elem does not require accessing the map. - * - * Updating/Deleting requires a bucket lock to - * link/unlink the elem from the map. Having - * multiple buckets to improve contention. - */ - struct bpf_local_storage_map_bucket *buckets; - u32 bucket_log; - u16 elem_size; - u16 cache_idx; -}; - -struct bpf_local_storage_data { - /* smap is used as the searching key when looking up - * from the object's bpf_local_storage. - * - * Put it in the same cacheline as the data to minimize - * the number of cachelines access during the cache hit case. - */ - struct bpf_local_storage_map __rcu *smap; - u8 data[] __aligned(8); -}; - -/* Linked to bpf_local_storage and bpf_local_storage_map */ -struct bpf_local_storage_elem { - struct hlist_node map_node; /* Linked to bpf_local_storage_map */ - struct hlist_node snode; /* Linked to bpf_local_storage */ - struct bpf_local_storage __rcu *local_storage; - struct rcu_head rcu; - /* 8 bytes hole */ - /* The data is stored in aother cacheline to minimize - * the number of cachelines access during a cache hit. - */ - struct bpf_local_storage_data sdata ____cacheline_aligned; -}; - -struct bpf_local_storage { - struct bpf_local_storage_data __rcu *cache[BPF_LOCAL_STORAGE_CACHE_SIZE]; - struct hlist_head list; /* List of bpf_local_storage_elem */ - void *owner; /* The object that owns the above "list" of - * bpf_local_storage_elem. - */ - struct rcu_head rcu; - raw_spinlock_t lock; /* Protect adding/removing from the "list" */ -}; - -/* U16_MAX is much more than enough for sk local storage - * considering a tcp_sock is ~2k. - */ -#define BPF_LOCAL_STORAGE_MAX_VALUE_SIZE \ - min_t(u32, \ - (KMALLOC_MAX_SIZE - MAX_BPF_STACK - \ - sizeof(struct bpf_local_storage_elem)), \ - (U16_MAX - sizeof(struct bpf_local_storage_elem))) - -#define SELEM(_SDATA) \ - container_of((_SDATA), struct bpf_local_storage_elem, sdata) -#define SDATA(_SELEM) (&(_SELEM)->sdata) - -#define BPF_LOCAL_STORAGE_CACHE_SIZE 16 - -struct bpf_local_storage_cache { - spinlock_t idx_lock; - u64 idx_usage_counts[BPF_LOCAL_STORAGE_CACHE_SIZE]; -}; - -#define DEFINE_BPF_STORAGE_CACHE(name) \ -static struct bpf_local_storage_cache name = { \ - .idx_lock = __SPIN_LOCK_UNLOCKED(name.idx_lock), \ -} - -u16 bpf_local_storage_cache_idx_get(struct bpf_local_storage_cache *cache); -void bpf_local_storage_cache_idx_free(struct bpf_local_storage_cache *cache, - u16 idx); - -/* Helper functions for bpf_local_storage */ -int bpf_local_storage_map_alloc_check(union bpf_attr *attr); - -struct bpf_local_storage_map *bpf_local_storage_map_alloc(union bpf_attr *attr); - -struct bpf_local_storage_data * -bpf_local_storage_lookup(struct bpf_local_storage *local_storage, - struct bpf_local_storage_map *smap, - bool cacheit_lockit); - -void bpf_local_storage_map_free(struct bpf_local_storage_map *smap); - -int bpf_local_storage_map_check_btf(const struct bpf_map *map, - const struct btf *btf, - const struct btf_type *key_type, - const struct btf_type *value_type); - -void bpf_selem_link_storage_nolock(struct bpf_local_storage *local_storage, - struct bpf_local_storage_elem *selem); - -bool bpf_selem_unlink_storage_nolock(struct bpf_local_storage *local_storage, - struct bpf_local_storage_elem *selem, - bool uncharge_omem); - -void bpf_selem_unlink(struct bpf_local_storage_elem *selem); - -void bpf_selem_link_map(struct bpf_local_storage_map *smap, - struct bpf_local_storage_elem *selem); - -void bpf_selem_unlink_map(struct bpf_local_storage_elem *selem); - -struct bpf_local_storage_elem * -bpf_selem_alloc(struct bpf_local_storage_map *smap, void *owner, void *value, - bool charge_mem); - -int -bpf_local_storage_alloc(void *owner, - struct bpf_local_storage_map *smap, - struct bpf_local_storage_elem *first_selem); - -struct bpf_local_storage_data * -bpf_local_storage_update(void *owner, struct bpf_local_storage_map *smap, - void *value, u64 map_flags); - -#endif /* _BPF_LOCAL_STORAGE_H */ diff --git a/include/linux/bpf_lsm.h b/include/linux/bpf_lsm.h deleted file mode 100644 index aaacb6aafc87..000000000000 --- a/include/linux/bpf_lsm.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -/* - * Copyright (C) 2020 Google LLC. - */ - -#ifndef _LINUX_BPF_LSM_H -#define _LINUX_BPF_LSM_H - -#include -#include - -#ifdef CONFIG_BPF_LSM - -#define LSM_HOOK(RET, DEFAULT, NAME, ...) \ - RET bpf_lsm_##NAME(__VA_ARGS__); -#include -#undef LSM_HOOK - -struct bpf_storage_blob { - struct bpf_local_storage __rcu *storage; -}; - -extern struct lsm_blob_sizes bpf_lsm_blob_sizes; - -int bpf_lsm_verify_prog(struct bpf_verifier_log *vlog, - const struct bpf_prog *prog); - -static inline struct bpf_storage_blob *bpf_inode( - const struct inode *inode) -{ - if (unlikely(!inode->i_security)) - return NULL; - - return inode->i_security + bpf_lsm_blob_sizes.lbs_inode; -} - -extern const struct bpf_func_proto bpf_inode_storage_get_proto; -extern const struct bpf_func_proto bpf_inode_storage_delete_proto; -void bpf_inode_storage_free(struct inode *inode); - -#else /* !CONFIG_BPF_LSM */ - -static inline int bpf_lsm_verify_prog(struct bpf_verifier_log *vlog, - const struct bpf_prog *prog) -{ - return -EOPNOTSUPP; -} - -static inline struct bpf_storage_blob *bpf_inode( - const struct inode *inode) -{ - return NULL; -} - -static inline void bpf_inode_storage_free(struct inode *inode) -{ -} - -#endif /* CONFIG_BPF_LSM */ - -#endif /* _LINUX_BPF_LSM_H */ diff --git a/include/linux/bpf_types.h b/include/linux/bpf_types.h index 2d8b63574aa8..36a9c2325176 100644 --- a/include/linux/bpf_types.h +++ b/include/linux/bpf_types.h @@ -2,83 +2,41 @@ /* internal file - do not include directly */ #ifdef CONFIG_NET -BPF_PROG_TYPE(BPF_PROG_TYPE_SOCKET_FILTER, sk_filter, - struct __sk_buff, struct sk_buff) -BPF_PROG_TYPE(BPF_PROG_TYPE_SCHED_CLS, tc_cls_act, - struct __sk_buff, struct sk_buff) -BPF_PROG_TYPE(BPF_PROG_TYPE_SCHED_ACT, tc_cls_act, - struct __sk_buff, struct sk_buff) -BPF_PROG_TYPE(BPF_PROG_TYPE_XDP, xdp, - struct xdp_md, struct xdp_buff) +BPF_PROG_TYPE(BPF_PROG_TYPE_SOCKET_FILTER, sk_filter) +BPF_PROG_TYPE(BPF_PROG_TYPE_SCHED_CLS, tc_cls_act) +BPF_PROG_TYPE(BPF_PROG_TYPE_SCHED_ACT, tc_cls_act) +BPF_PROG_TYPE(BPF_PROG_TYPE_XDP, xdp) #ifdef CONFIG_CGROUP_BPF -BPF_PROG_TYPE(BPF_PROG_TYPE_CGROUP_SKB, cg_skb, - struct __sk_buff, struct sk_buff) -BPF_PROG_TYPE(BPF_PROG_TYPE_CGROUP_SOCK, cg_sock, - struct bpf_sock, struct sock) -BPF_PROG_TYPE(BPF_PROG_TYPE_CGROUP_SOCK_ADDR, cg_sock_addr, - struct bpf_sock_addr, struct bpf_sock_addr_kern) +BPF_PROG_TYPE(BPF_PROG_TYPE_CGROUP_SKB, cg_skb) +BPF_PROG_TYPE(BPF_PROG_TYPE_CGROUP_SOCK, cg_sock) +BPF_PROG_TYPE(BPF_PROG_TYPE_CGROUP_SOCK_ADDR, cg_sock_addr) #endif -BPF_PROG_TYPE(BPF_PROG_TYPE_LWT_IN, lwt_in, - struct __sk_buff, struct sk_buff) -BPF_PROG_TYPE(BPF_PROG_TYPE_LWT_OUT, lwt_out, - struct __sk_buff, struct sk_buff) -BPF_PROG_TYPE(BPF_PROG_TYPE_LWT_XMIT, lwt_xmit, - struct __sk_buff, struct sk_buff) -BPF_PROG_TYPE(BPF_PROG_TYPE_LWT_SEG6LOCAL, lwt_seg6local, - struct __sk_buff, struct sk_buff) -BPF_PROG_TYPE(BPF_PROG_TYPE_SOCK_OPS, sock_ops, - struct bpf_sock_ops, struct bpf_sock_ops_kern) -BPF_PROG_TYPE(BPF_PROG_TYPE_SK_SKB, sk_skb, - struct __sk_buff, struct sk_buff) -BPF_PROG_TYPE(BPF_PROG_TYPE_SK_MSG, sk_msg, - struct sk_msg_md, struct sk_msg) -BPF_PROG_TYPE(BPF_PROG_TYPE_FLOW_DISSECTOR, flow_dissector, - struct __sk_buff, struct bpf_flow_dissector) +BPF_PROG_TYPE(BPF_PROG_TYPE_LWT_IN, lwt_in) +BPF_PROG_TYPE(BPF_PROG_TYPE_LWT_OUT, lwt_out) +BPF_PROG_TYPE(BPF_PROG_TYPE_LWT_XMIT, lwt_xmit) +BPF_PROG_TYPE(BPF_PROG_TYPE_LWT_SEG6LOCAL, lwt_seg6local) +BPF_PROG_TYPE(BPF_PROG_TYPE_SOCK_OPS, sock_ops) +BPF_PROG_TYPE(BPF_PROG_TYPE_SK_SKB, sk_skb) +BPF_PROG_TYPE(BPF_PROG_TYPE_SK_MSG, sk_msg) +BPF_PROG_TYPE(BPF_PROG_TYPE_FLOW_DISSECTOR, flow_dissector) #endif #ifdef CONFIG_BPF_EVENTS -BPF_PROG_TYPE(BPF_PROG_TYPE_KPROBE, kprobe, - bpf_user_pt_regs_t, struct pt_regs) -BPF_PROG_TYPE(BPF_PROG_TYPE_TRACEPOINT, tracepoint, - __u64, u64) -BPF_PROG_TYPE(BPF_PROG_TYPE_PERF_EVENT, perf_event, - struct bpf_perf_event_data, struct bpf_perf_event_data_kern) -BPF_PROG_TYPE(BPF_PROG_TYPE_RAW_TRACEPOINT, raw_tracepoint, - struct bpf_raw_tracepoint_args, u64) -BPF_PROG_TYPE(BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE, raw_tracepoint_writable, - struct bpf_raw_tracepoint_args, u64) -BPF_PROG_TYPE(BPF_PROG_TYPE_TRACING, tracing, - void *, void *) +BPF_PROG_TYPE(BPF_PROG_TYPE_KPROBE, kprobe) +BPF_PROG_TYPE(BPF_PROG_TYPE_TRACEPOINT, tracepoint) +BPF_PROG_TYPE(BPF_PROG_TYPE_PERF_EVENT, perf_event) +BPF_PROG_TYPE(BPF_PROG_TYPE_RAW_TRACEPOINT, raw_tracepoint) +BPF_PROG_TYPE(BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE, raw_tracepoint_writable) #endif #ifdef CONFIG_CGROUP_BPF -BPF_PROG_TYPE(BPF_PROG_TYPE_CGROUP_DEVICE, cg_dev, - struct bpf_cgroup_dev_ctx, struct bpf_cgroup_dev_ctx) -BPF_PROG_TYPE(BPF_PROG_TYPE_CGROUP_SYSCTL, cg_sysctl, - struct bpf_sysctl, struct bpf_sysctl_kern) -BPF_PROG_TYPE(BPF_PROG_TYPE_CGROUP_SOCKOPT, cg_sockopt, - struct bpf_sockopt, struct bpf_sockopt_kern) +BPF_PROG_TYPE(BPF_PROG_TYPE_CGROUP_DEVICE, cg_dev) +BPF_PROG_TYPE(BPF_PROG_TYPE_CGROUP_SYSCTL, cg_sysctl) +BPF_PROG_TYPE(BPF_PROG_TYPE_CGROUP_SOCKOPT, cg_sockopt) #endif #ifdef CONFIG_BPF_LIRC_MODE2 -BPF_PROG_TYPE(BPF_PROG_TYPE_LIRC_MODE2, lirc_mode2, - __u32, u32) +BPF_PROG_TYPE(BPF_PROG_TYPE_LIRC_MODE2, lirc_mode2) #endif #ifdef CONFIG_INET -BPF_PROG_TYPE(BPF_PROG_TYPE_SK_REUSEPORT, sk_reuseport, - struct sk_reuseport_md, struct sk_reuseport_kern) -BPF_PROG_TYPE(BPF_PROG_TYPE_SK_LOOKUP, sk_lookup, - struct bpf_sk_lookup, struct bpf_sk_lookup_kern) -#endif -#if defined(CONFIG_BPF_JIT) -BPF_PROG_TYPE(BPF_PROG_TYPE_STRUCT_OPS, bpf_struct_ops, - void *, void *) -BPF_PROG_TYPE(BPF_PROG_TYPE_EXT, bpf_extension, - void *, void *) -#ifdef CONFIG_BPF_LSM -BPF_PROG_TYPE(BPF_PROG_TYPE_LSM, lsm, - void *, void *) -#endif /* CONFIG_BPF_LSM */ -#endif -#ifdef CONFIG_FUSE_BPF -BPF_PROG_TYPE(BPF_PROG_TYPE_FUSE, fuse, struct fuse_bpf_args, struct fuse_bpf_args) +BPF_PROG_TYPE(BPF_PROG_TYPE_SK_REUSEPORT, sk_reuseport) #endif BPF_MAP_TYPE(BPF_MAP_TYPE_ARRAY, array_map_ops) @@ -106,33 +64,17 @@ BPF_MAP_TYPE(BPF_MAP_TYPE_HASH_OF_MAPS, htab_of_maps_map_ops) BPF_MAP_TYPE(BPF_MAP_TYPE_DEVMAP, dev_map_ops) BPF_MAP_TYPE(BPF_MAP_TYPE_DEVMAP_HASH, dev_map_hash_ops) BPF_MAP_TYPE(BPF_MAP_TYPE_SK_STORAGE, sk_storage_map_ops) -#ifdef CONFIG_BPF_LSM -BPF_MAP_TYPE(BPF_MAP_TYPE_INODE_STORAGE, inode_storage_map_ops) +#if defined(CONFIG_BPF_STREAM_PARSER) +BPF_MAP_TYPE(BPF_MAP_TYPE_SOCKMAP, sock_map_ops) +BPF_MAP_TYPE(BPF_MAP_TYPE_SOCKHASH, sock_hash_ops) #endif BPF_MAP_TYPE(BPF_MAP_TYPE_CPUMAP, cpu_map_ops) #if defined(CONFIG_XDP_SOCKETS) BPF_MAP_TYPE(BPF_MAP_TYPE_XSKMAP, xsk_map_ops) #endif #ifdef CONFIG_INET -BPF_MAP_TYPE(BPF_MAP_TYPE_SOCKMAP, sock_map_ops) -BPF_MAP_TYPE(BPF_MAP_TYPE_SOCKHASH, sock_hash_ops) BPF_MAP_TYPE(BPF_MAP_TYPE_REUSEPORT_SOCKARRAY, reuseport_array_ops) #endif #endif BPF_MAP_TYPE(BPF_MAP_TYPE_QUEUE, queue_map_ops) BPF_MAP_TYPE(BPF_MAP_TYPE_STACK, stack_map_ops) -#if defined(CONFIG_BPF_JIT) -BPF_MAP_TYPE(BPF_MAP_TYPE_STRUCT_OPS, bpf_struct_ops_map_ops) -#endif -BPF_MAP_TYPE(BPF_MAP_TYPE_RINGBUF, ringbuf_map_ops) - -BPF_LINK_TYPE(BPF_LINK_TYPE_RAW_TRACEPOINT, raw_tracepoint) -BPF_LINK_TYPE(BPF_LINK_TYPE_TRACING, tracing) -#ifdef CONFIG_CGROUP_BPF -BPF_LINK_TYPE(BPF_LINK_TYPE_CGROUP, cgroup) -#endif -BPF_LINK_TYPE(BPF_LINK_TYPE_ITER, iter) -#ifdef CONFIG_NET -BPF_LINK_TYPE(BPF_LINK_TYPE_NETNS, netns) -BPF_LINK_TYPE(BPF_LINK_TYPE_XDP, xdp) -#endif diff --git a/include/linux/bpf_verifier.h b/include/linux/bpf_verifier.h index f09a5bbc9b8b..ee10a9f06b97 100644 --- a/include/linux/bpf_verifier.h +++ b/include/linux/bpf_verifier.h @@ -7,7 +7,6 @@ #include /* for enum bpf_reg_type */ #include /* for MAX_BPF_STACK */ #include -#include /* Maximum variable offset umax_value permitted when resolving memory accesses. * In practice this is far bigger than any realistic pointer offset; this limit @@ -46,17 +45,13 @@ struct bpf_reg_state { enum bpf_reg_type type; union { /* valid when type == PTR_TO_PACKET */ - int range; + u16 range; /* valid when type == CONST_PTR_TO_MAP | PTR_TO_MAP_VALUE | * PTR_TO_MAP_VALUE_OR_NULL */ struct bpf_map *map_ptr; - u32 btf_id; /* for PTR_TO_BTF_ID */ - - u32 mem_size; /* for PTR_TO_MEM | PTR_TO_MEM_OR_NULL */ - /* Max size from any of the above. */ unsigned long raw; }; @@ -66,8 +61,6 @@ struct bpf_reg_state { * offset, so they can share range knowledge. * For PTR_TO_MAP_VALUE_OR_NULL this is used to share which map value we * came from, when one is tested for != NULL. - * For PTR_TO_MEM_OR_NULL this is used to identify memory allocation - * for the purpose of tracking that it's freed. * For PTR_TO_SOCKET this is used to share which pointers retain the * same reference to the socket, to determine proper reference freeing. */ @@ -128,10 +121,6 @@ struct bpf_reg_state { s64 smax_value; /* maximum possible (s64)value */ u64 umin_value; /* minimum possible (u64)value */ u64 umax_value; /* maximum possible (u64)value */ - s32 s32_min_value; /* minimum possible (s32)value */ - s32 s32_max_value; /* maximum possible (s32)value */ - u32 u32_min_value; /* minimum possible (u32)value */ - u32 u32_max_value; /* maximum possible (u32)value */ /* parentage chain for liveness checking */ struct bpf_reg_state *parent; /* Inside the callee two registers can be both PTR_TO_STACK like @@ -188,7 +177,7 @@ struct bpf_func_state { * 0 = main function, 1 = first callee. */ u32 frameno; - /* subprog number == index within subprog_info + /* subprog number == index within subprog_stack_depth * zero == main subprog */ u32 subprogno; @@ -291,27 +280,6 @@ struct bpf_verifier_state { iter < frame->allocated_stack / BPF_REG_SIZE; \ iter++, reg = bpf_get_spilled_reg(iter, frame)) -/* Invoke __expr over regsiters in __vst, setting __state and __reg */ -#define bpf_for_each_reg_in_vstate(__vst, __state, __reg, __expr) \ - ({ \ - struct bpf_verifier_state *___vstate = __vst; \ - int ___i, ___j; \ - for (___i = 0; ___i <= ___vstate->curframe; ___i++) { \ - struct bpf_reg_state *___regs; \ - __state = ___vstate->frame[___i]; \ - ___regs = __state->regs; \ - for (___j = 0; ___j < MAX_BPF_REG; ___j++) { \ - __reg = &___regs[___j]; \ - (void)(__expr); \ - } \ - bpf_for_each_spilled_reg(___j, __state, __reg) { \ - if (!__reg) \ - continue; \ - (void)(__expr); \ - } \ - } \ - }) - /* linked list of verifier states used to prune search */ struct bpf_verifier_state_list { struct bpf_verifier_state state; @@ -331,31 +299,21 @@ struct bpf_verifier_state_list { struct bpf_insn_aux_data { union { enum bpf_reg_type ptr_type; /* pointer type for load/store insns */ - unsigned long map_ptr_state; /* pointer/poison value for maps */ + unsigned long map_state; /* pointer/poison value for maps */ s32 call_imm; /* saved imm field of call insn */ u32 alu_limit; /* limit for add/sub register with pointer */ struct { u32 map_index; /* index into used_maps[] */ u32 map_off; /* offset from value base address */ }; - struct { - enum bpf_reg_type reg_type; /* type of pseudo_btf_id */ - union { - u32 btf_id; /* btf_id for struct typed var */ - u32 mem_size; /* mem_size for non-struct typed var */ - }; - } btf_var; }; - u64 map_key_state; /* constant (32 bit) key tracking for maps */ int ctx_field_size; /* the ctx field size for load insn, maybe 0 */ - u32 seen; /* this insn was processed by the verifier at env->pass_cnt */ + bool seen; /* this insn was processed by the verifier */ bool sanitize_stack_spill; /* subject to Spectre v4 sanitation */ bool zext_dst; /* this insn zero extends dst reg */ u8 alu_state; /* used in combination with alu_limit */ - - /* below fields are initialized once */ - unsigned int orig_idx; /* original instruction index */ bool prune_point; + unsigned int orig_idx; /* original instruction index */ }; #define MAX_USED_MAPS 64 /* max number of maps accessed by one eBPF program */ @@ -380,34 +338,19 @@ static inline bool bpf_verifier_log_full(const struct bpf_verifier_log *log) #define BPF_LOG_STATS 4 #define BPF_LOG_LEVEL (BPF_LOG_LEVEL1 | BPF_LOG_LEVEL2) #define BPF_LOG_MASK (BPF_LOG_LEVEL | BPF_LOG_STATS) -#define BPF_LOG_KERNEL (BPF_LOG_MASK + 1) /* kernel internal flag */ static inline bool bpf_verifier_log_needed(const struct bpf_verifier_log *log) { - return log && - ((log->level && log->ubuf && !bpf_verifier_log_full(log)) || - log->level == BPF_LOG_KERNEL); -} - -static inline bool -bpf_verifier_log_attr_valid(const struct bpf_verifier_log *log) -{ - return log->len_total >= 128 && log->len_total <= UINT_MAX >> 2 && - log->level && log->ubuf && !(log->level & ~BPF_LOG_MASK); + return log->level && log->ubuf && !bpf_verifier_log_full(log); } #define BPF_MAX_SUBPROGS 256 struct bpf_subprog_info { - /* 'start' has to be the first field otherwise find_subprog() won't work */ u32 start; /* insn idx of function entry point */ u32 linfo_idx; /* The idx to the main_prog->aux->linfo */ u16 stack_depth; /* max. stack depth used by this function */ bool has_tail_call; - bool tail_call_reachable; - bool has_ld_abs; - - ANDROID_KABI_RESERVE(1); }; /* single container for all structs @@ -430,11 +373,6 @@ struct bpf_verifier_env { u32 id_gen; /* used to generate unique reg IDs */ bool explore_alu_limits; bool allow_ptr_leaks; - bool allow_uninit_stack; - bool allow_ptr_to_map_access; - bool bpf_capable; - bool bypass_spec_v1; - bool bypass_spec_v4; bool seen_direct_write; struct bpf_insn_aux_data *insn_aux_data; /* array of per-insn state */ const struct bpf_line_info *prev_linfo; @@ -446,7 +384,6 @@ struct bpf_verifier_env { int *insn_stack; int cur_stack; } cfg; - u32 pass_cnt; /* number of times do_check() was called */ u32 subprog_cnt; /* number of instructions analyzed by the verifier */ u32 prev_insn_processed, insn_processed; @@ -465,17 +402,12 @@ struct bpf_verifier_env { u32 peak_states; /* longest register parentage chain walked for liveness marking */ u32 longest_mark_read_walk; - - ANDROID_KABI_RESERVE(1); - ANDROID_KABI_RESERVE(2); }; __printf(2, 0) void bpf_verifier_vlog(struct bpf_verifier_log *log, const char *fmt, va_list args); __printf(2, 3) void bpf_verifier_log_write(struct bpf_verifier_env *env, const char *fmt, ...); -__printf(2, 3) void bpf_log(struct bpf_verifier_log *log, - const char *fmt, ...); static inline struct bpf_func_state *cur_func(struct bpf_verifier_env *env) { @@ -499,20 +431,4 @@ bpf_prog_offload_replace_insn(struct bpf_verifier_env *env, u32 off, void bpf_prog_offload_remove_insns(struct bpf_verifier_env *env, u32 off, u32 cnt); -int check_ctx_reg(struct bpf_verifier_env *env, - const struct bpf_reg_state *reg, int regno); - -/* this lives here instead of in bpf.h because it needs to dereference tgt_prog */ -static inline u64 bpf_trampoline_compute_key(const struct bpf_prog *tgt_prog, - u32 btf_id) -{ - return tgt_prog ? (((u64)tgt_prog->aux->id) << 32 | btf_id) : btf_id; -} - -int bpf_check_attach_target(struct bpf_verifier_log *log, - const struct bpf_prog *prog, - const struct bpf_prog *tgt_prog, - u32 btf_id, - struct bpf_attach_target_info *tgt_info); - #endif /* _LINUX_BPF_VERIFIER_H */ diff --git a/include/linux/bpfilter.h b/include/linux/bpfilter.h index 2ae3c8e1d83c..d815622cd31e 100644 --- a/include/linux/bpfilter.h +++ b/include/linux/bpfilter.h @@ -3,23 +3,22 @@ #define _LINUX_BPFILTER_H #include -#include -#include +#include struct sock; -int bpfilter_ip_set_sockopt(struct sock *sk, int optname, sockptr_t optval, +int bpfilter_ip_set_sockopt(struct sock *sk, int optname, char __user *optval, unsigned int optlen); int bpfilter_ip_get_sockopt(struct sock *sk, int optname, char __user *optval, int __user *optlen); -void bpfilter_umh_cleanup(struct umd_info *info); - struct bpfilter_umh_ops { - struct umd_info info; + struct umh_info info; /* since ip_getsockopt() can run in parallel, serialize access to umh */ struct mutex lock; - int (*sockopt)(struct sock *sk, int optname, sockptr_t optval, + int (*sockopt)(struct sock *sk, int optname, + char __user *optval, unsigned int optlen, bool is_set); int (*start)(void); + bool stop; }; extern struct bpfilter_umh_ops bpfilter_ops; #endif diff --git a/include/linux/btf.h b/include/linux/btf.h index 2bf641829664..64cdf2a23d42 100644 --- a/include/linux/btf.h +++ b/include/linux/btf.h @@ -5,16 +5,11 @@ #define _LINUX_BTF_H 1 #include -#include -#include - -#define BTF_TYPE_EMIT(type) ((void)(type *)0) struct btf; struct btf_member; struct btf_type; union bpf_attr; -struct btf_show; extern const struct file_operations btf_fops; @@ -48,45 +43,8 @@ int btf_get_info_by_fd(const struct btf *btf, const struct btf_type *btf_type_id_size(const struct btf *btf, u32 *type_id, u32 *ret_size); - -/* - * Options to control show behaviour. - * - BTF_SHOW_COMPACT: no formatting around type information - * - BTF_SHOW_NONAME: no struct/union member names/types - * - BTF_SHOW_PTR_RAW: show raw (unobfuscated) pointer values; - * equivalent to %px. - * - BTF_SHOW_ZERO: show zero-valued struct/union members; they - * are not displayed by default - * - BTF_SHOW_UNSAFE: skip use of bpf_probe_read() to safely read - * data before displaying it. - */ -#define BTF_SHOW_COMPACT BTF_F_COMPACT -#define BTF_SHOW_NONAME BTF_F_NONAME -#define BTF_SHOW_PTR_RAW BTF_F_PTR_RAW -#define BTF_SHOW_ZERO BTF_F_ZERO -#define BTF_SHOW_UNSAFE (1ULL << 4) - void btf_type_seq_show(const struct btf *btf, u32 type_id, void *obj, struct seq_file *m); -int btf_type_seq_show_flags(const struct btf *btf, u32 type_id, void *obj, - struct seq_file *m, u64 flags); - -/* - * Copy len bytes of string representation of obj of BTF type_id into buf. - * - * @btf: struct btf object - * @type_id: type id of type obj points to - * @obj: pointer to typed data - * @buf: buffer to write to - * @len: maximum length to write to buf - * @flags: show options (see above) - * - * Return: length that would have been/was copied as per snprintf, or - * negative error. - */ -int btf_type_snprintf_show(const struct btf *btf, u32 type_id, void *obj, - char *buf, int len, u64 flags); - int btf_get_fd_by_id(u32 id); u32 btf_id(const struct btf *btf); bool btf_member_is_reg_int(const struct btf *btf, const struct btf_type *s, @@ -94,122 +52,10 @@ bool btf_member_is_reg_int(const struct btf *btf, const struct btf_type *s, u32 expected_offset, u32 expected_size); int btf_find_spin_lock(const struct btf *btf, const struct btf_type *t); bool btf_type_is_void(const struct btf_type *t); -s32 btf_find_by_name_kind(const struct btf *btf, const char *name, u8 kind); -const struct btf_type *btf_type_skip_modifiers(const struct btf *btf, - u32 id, u32 *res_id); -const struct btf_type *btf_type_resolve_ptr(const struct btf *btf, - u32 id, u32 *res_id); -const struct btf_type *btf_type_resolve_func_ptr(const struct btf *btf, - u32 id, u32 *res_id); -const struct btf_type * -btf_resolve_size(const struct btf *btf, const struct btf_type *type, - u32 *type_size); - -#define for_each_member(i, struct_type, member) \ - for (i = 0, member = btf_type_member(struct_type); \ - i < btf_type_vlen(struct_type); \ - i++, member++) - -#define for_each_vsi(i, datasec_type, member) \ - for (i = 0, member = btf_type_var_secinfo(datasec_type); \ - i < btf_type_vlen(datasec_type); \ - i++, member++) - -static inline bool btf_type_is_ptr(const struct btf_type *t) -{ - return BTF_INFO_KIND(t->info) == BTF_KIND_PTR; -} - -static inline bool btf_type_is_int(const struct btf_type *t) -{ - return BTF_INFO_KIND(t->info) == BTF_KIND_INT; -} - -static inline bool btf_type_is_small_int(const struct btf_type *t) -{ - return btf_type_is_int(t) && t->size <= sizeof(u64); -} - -static inline bool btf_type_is_enum(const struct btf_type *t) -{ - return BTF_INFO_KIND(t->info) == BTF_KIND_ENUM; -} - -static inline bool btf_type_is_typedef(const struct btf_type *t) -{ - return BTF_INFO_KIND(t->info) == BTF_KIND_TYPEDEF; -} - -static inline bool btf_type_is_func(const struct btf_type *t) -{ - return BTF_INFO_KIND(t->info) == BTF_KIND_FUNC; -} - -static inline bool btf_type_is_func_proto(const struct btf_type *t) -{ - return BTF_INFO_KIND(t->info) == BTF_KIND_FUNC_PROTO; -} - -static inline bool btf_type_is_var(const struct btf_type *t) -{ - return BTF_INFO_KIND(t->info) == BTF_KIND_VAR; -} - -/* union is only a special case of struct: - * all its offsetof(member) == 0 - */ -static inline bool btf_type_is_struct(const struct btf_type *t) -{ - u8 kind = BTF_INFO_KIND(t->info); - - return kind == BTF_KIND_STRUCT || kind == BTF_KIND_UNION; -} - -static inline u16 btf_type_vlen(const struct btf_type *t) -{ - return BTF_INFO_VLEN(t->info); -} - -static inline u16 btf_func_linkage(const struct btf_type *t) -{ - return BTF_INFO_VLEN(t->info); -} - -static inline bool btf_type_kflag(const struct btf_type *t) -{ - return BTF_INFO_KFLAG(t->info); -} - -static inline u32 btf_member_bit_offset(const struct btf_type *struct_type, - const struct btf_member *member) -{ - return btf_type_kflag(struct_type) ? BTF_MEMBER_BIT_OFFSET(member->offset) - : member->offset; -} - -static inline u32 btf_member_bitfield_size(const struct btf_type *struct_type, - const struct btf_member *member) -{ - return btf_type_kflag(struct_type) ? BTF_MEMBER_BITFIELD_SIZE(member->offset) - : 0; -} - -static inline const struct btf_member *btf_type_member(const struct btf_type *t) -{ - return (const struct btf_member *)(t + 1); -} - -static inline const struct btf_var_secinfo *btf_type_var_secinfo( - const struct btf_type *t) -{ - return (const struct btf_var_secinfo *)(t + 1); -} #ifdef CONFIG_BPF_SYSCALL const struct btf_type *btf_type_by_id(const struct btf *btf, u32 type_id); const char *btf_name_by_offset(const struct btf *btf, u32 offset); -struct btf *btf_parse_vmlinux(void); -struct btf *bpf_prog_get_target_btf(const struct bpf_prog *prog); #else static inline const struct btf_type *btf_type_by_id(const struct btf *btf, u32 type_id) diff --git a/include/linux/btf_ids.h b/include/linux/btf_ids.h deleted file mode 100644 index c196884a7faf..000000000000 --- a/include/linux/btf_ids.h +++ /dev/null @@ -1,187 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef _LINUX_BTF_IDS_H -#define _LINUX_BTF_IDS_H - -struct btf_id_set { - u32 cnt; - u32 ids[]; -}; - -#ifdef CONFIG_DEBUG_INFO_BTF - -#include /* for __PASTE */ - -/* - * Following macros help to define lists of BTF IDs placed - * in .BTF_ids section. They are initially filled with zeros - * (during compilation) and resolved later during the - * linking phase by resolve_btfids tool. - * - * Any change in list layout must be reflected in resolve_btfids - * tool logic. - */ - -#define BTF_IDS_SECTION ".BTF_ids" - -#define ____BTF_ID(symbol) \ -asm( \ -".pushsection " BTF_IDS_SECTION ",\"a\"; \n" \ -".local " #symbol " ; \n" \ -".type " #symbol ", @object; \n" \ -".size " #symbol ", 4; \n" \ -#symbol ": \n" \ -".zero 4 \n" \ -".popsection; \n"); - -#define __BTF_ID(symbol) \ - ____BTF_ID(symbol) - -#define __ID(prefix) \ - __PASTE(prefix, __COUNTER__) - -/* - * The BTF_ID defines unique symbol for each ID pointing - * to 4 zero bytes. - */ -#define BTF_ID(prefix, name) \ - __BTF_ID(__ID(__BTF_ID__##prefix##__##name##__)) - -/* - * The BTF_ID_LIST macro defines pure (unsorted) list - * of BTF IDs, with following layout: - * - * BTF_ID_LIST(list1) - * BTF_ID(type1, name1) - * BTF_ID(type2, name2) - * - * list1: - * __BTF_ID__type1__name1__1: - * .zero 4 - * __BTF_ID__type2__name2__2: - * .zero 4 - * - */ -#define __BTF_ID_LIST(name, scope) \ -asm( \ -".pushsection " BTF_IDS_SECTION ",\"a\"; \n" \ -"." #scope " " #name "; \n" \ -#name ":; \n" \ -".popsection; \n"); - -#define BTF_ID_LIST(name) \ -__BTF_ID_LIST(name, local) \ -extern u32 name[]; - -#define BTF_ID_LIST_GLOBAL(name) \ -__BTF_ID_LIST(name, globl) - -/* The BTF_ID_LIST_SINGLE macro defines a BTF_ID_LIST with - * a single entry. - */ -#define BTF_ID_LIST_SINGLE(name, prefix, typename) \ - BTF_ID_LIST(name) \ - BTF_ID(prefix, typename) - -/* - * The BTF_ID_UNUSED macro defines 4 zero bytes. - * It's used when we want to define 'unused' entry - * in BTF_ID_LIST, like: - * - * BTF_ID_LIST(bpf_skb_output_btf_ids) - * BTF_ID(struct, sk_buff) - * BTF_ID_UNUSED - * BTF_ID(struct, task_struct) - */ - -#define BTF_ID_UNUSED \ -asm( \ -".pushsection " BTF_IDS_SECTION ",\"a\"; \n" \ -".zero 4 \n" \ -".popsection; \n"); - -/* - * The BTF_SET_START/END macros pair defines sorted list of - * BTF IDs plus its members count, with following layout: - * - * BTF_SET_START(list) - * BTF_ID(type1, name1) - * BTF_ID(type2, name2) - * BTF_SET_END(list) - * - * __BTF_ID__set__list: - * .zero 4 - * list: - * __BTF_ID__type1__name1__3: - * .zero 4 - * __BTF_ID__type2__name2__4: - * .zero 4 - * - */ -#define __BTF_SET_START(name, scope) \ -asm( \ -".pushsection " BTF_IDS_SECTION ",\"a\"; \n" \ -"." #scope " __BTF_ID__set__" #name "; \n" \ -"__BTF_ID__set__" #name ":; \n" \ -".zero 4 \n" \ -".popsection; \n"); - -#define BTF_SET_START(name) \ -__BTF_ID_LIST(name, local) \ -__BTF_SET_START(name, local) - -#define BTF_SET_START_GLOBAL(name) \ -__BTF_ID_LIST(name, globl) \ -__BTF_SET_START(name, globl) - -#define BTF_SET_END(name) \ -asm( \ -".pushsection " BTF_IDS_SECTION ",\"a\"; \n" \ -".size __BTF_ID__set__" #name ", .-" #name " \n" \ -".popsection; \n"); \ -extern struct btf_id_set name; - -#else - -#define BTF_ID_LIST(name) static u32 name[5]; -#define BTF_ID(prefix, name) -#define BTF_ID_UNUSED -#define BTF_ID_LIST_GLOBAL(name) u32 name[1]; -#define BTF_ID_LIST_SINGLE(name, prefix, typename) static u32 name[1]; -#define BTF_SET_START(name) static struct btf_id_set name = { 0 }; -#define BTF_SET_START_GLOBAL(name) static struct btf_id_set name = { 0 }; -#define BTF_SET_END(name) - -#endif /* CONFIG_DEBUG_INFO_BTF */ - -#ifdef CONFIG_NET -/* Define a list of socket types which can be the argument for - * skc_to_*_sock() helpers. All these sockets should have - * sock_common as the first argument in its memory layout. - */ -#define BTF_SOCK_TYPE_xxx \ - BTF_SOCK_TYPE(BTF_SOCK_TYPE_INET, inet_sock) \ - BTF_SOCK_TYPE(BTF_SOCK_TYPE_INET_CONN, inet_connection_sock) \ - BTF_SOCK_TYPE(BTF_SOCK_TYPE_INET_REQ, inet_request_sock) \ - BTF_SOCK_TYPE(BTF_SOCK_TYPE_INET_TW, inet_timewait_sock) \ - BTF_SOCK_TYPE(BTF_SOCK_TYPE_REQ, request_sock) \ - BTF_SOCK_TYPE(BTF_SOCK_TYPE_SOCK, sock) \ - BTF_SOCK_TYPE(BTF_SOCK_TYPE_SOCK_COMMON, sock_common) \ - BTF_SOCK_TYPE(BTF_SOCK_TYPE_TCP, tcp_sock) \ - BTF_SOCK_TYPE(BTF_SOCK_TYPE_TCP_REQ, tcp_request_sock) \ - BTF_SOCK_TYPE(BTF_SOCK_TYPE_TCP_TW, tcp_timewait_sock) \ - BTF_SOCK_TYPE(BTF_SOCK_TYPE_TCP6, tcp6_sock) \ - BTF_SOCK_TYPE(BTF_SOCK_TYPE_UDP, udp_sock) \ - BTF_SOCK_TYPE(BTF_SOCK_TYPE_UDP6, udp6_sock) - -enum { -#define BTF_SOCK_TYPE(name, str) name, -BTF_SOCK_TYPE_xxx -#undef BTF_SOCK_TYPE -MAX_BTF_SOCK_TYPE, -}; - -extern u32 btf_sock_ids[]; -#endif - -#endif diff --git a/include/linux/capability.h b/include/linux/capability.h index 1e7fe311cabe..ecce0f43c73a 100644 --- a/include/linux/capability.h +++ b/include/linux/capability.h @@ -251,21 +251,6 @@ extern bool privileged_wrt_inode_uidgid(struct user_namespace *ns, const struct extern bool capable_wrt_inode_uidgid(const struct inode *inode, int cap); extern bool file_ns_capable(const struct file *file, struct user_namespace *ns, int cap); extern bool ptracer_capable(struct task_struct *tsk, struct user_namespace *ns); -static inline bool perfmon_capable(void) -{ - return capable(CAP_PERFMON) || capable(CAP_SYS_ADMIN); -} - -static inline bool bpf_capable(void) -{ - return capable(CAP_BPF) || capable(CAP_SYS_ADMIN); -} - -static inline bool checkpoint_restore_ns_capable(struct user_namespace *ns) -{ - return ns_capable(ns, CAP_CHECKPOINT_RESTORE) || - ns_capable(ns, CAP_SYS_ADMIN); -} /* audit system wants to get cap info from files as well */ extern int get_vfs_caps_from_disk(const struct dentry *dentry, struct cpu_vfs_cap_data *cpu_caps); diff --git a/include/linux/cgroup-defs.h b/include/linux/cgroup-defs.h index 0181f595b43d..b46705a495aa 100644 --- a/include/linux/cgroup-defs.h +++ b/include/linux/cgroup-defs.h @@ -94,11 +94,6 @@ enum { * Enable legacy local memory.events. */ CGRP_ROOT_MEMORY_LOCAL_EVENTS = (1 << 5), - - /* - * Enable recursive subtree protection - */ - CGRP_ROOT_MEMORY_RECURSIVE_PROT = (1 << 6), }; /* cftype->flags */ @@ -367,6 +362,16 @@ struct cgroup { unsigned long flags; /* "unsigned long" so bitops work */ + /* + * idr allocated in-hierarchy ID. + * + * ID 0 is not used, the ID of the root cgroup is always 1, and a + * new cgroup will be assigned with a smallest available ID. + * + * Allocating/Removing ID must be protected by cgroup_mutex. + */ + int id; + /* * The depth this cgroup is at. The root is at depth zero and each * step down the hierarchy increments the level. This along with @@ -491,7 +496,7 @@ struct cgroup { struct cgroup_freezer_state freezer; /* ids of the ancestors at each level including self */ - u64 ancestor_ids[]; + int ancestor_ids[]; }; /* @@ -512,7 +517,7 @@ struct cgroup_root { struct cgroup cgrp; /* for cgrp->ancestor_ids[0] */ - u64 cgrp_ancestor_id_storage; + int cgrp_ancestor_id_storage; /* Number of cgroups in the hierarchy, used only for /proc/cgroups */ atomic_t nr_cgrps; @@ -523,6 +528,9 @@ struct cgroup_root { /* Hierarchy-specific flags */ unsigned int flags; + /* IDs for cgroups in this hierarchy */ + struct idr cgroup_idr; + /* The path to use for release notifications. */ char release_agent_path[PATH_MAX]; diff --git a/include/linux/cgroup.h b/include/linux/cgroup.h index 5f216fd7e820..bf290358507c 100644 --- a/include/linux/cgroup.h +++ b/include/linux/cgroup.h @@ -308,11 +308,6 @@ void css_task_iter_end(struct css_task_iter *it); * Inline functions. */ -static inline u64 cgroup_id(struct cgroup *cgrp) -{ - return cgrp->kn->id; -} - /** * css_get - obtain a reference on the specified css * @css: target css @@ -574,7 +569,7 @@ static inline bool cgroup_is_descendant(struct cgroup *cgrp, { if (cgrp->root != ancestor->root || cgrp->level < ancestor->level) return false; - return cgrp->ancestor_ids[ancestor->level] == cgroup_id(ancestor); + return cgrp->ancestor_ids[ancestor->level] == ancestor->id; } /** @@ -625,7 +620,7 @@ static inline bool cgroup_is_populated(struct cgroup *cgrp) /* returns ino associated with a cgroup */ static inline ino_t cgroup_ino(struct cgroup *cgrp) { - return kernfs_ino(cgrp->kn); + return cgrp->kn->id.ino; } /* cft/css accessors for cftype->write() operation */ @@ -698,13 +693,18 @@ static inline void cgroup_kthread_ready(void) current->no_cgroup_migration = 0; } -void cgroup_path_from_kernfs_id(u64 id, char *buf, size_t buflen); +static inline union kernfs_node_id *cgroup_get_kernfs_id(struct cgroup *cgrp) +{ + return &cgrp->kn->id; +} + +void cgroup_path_from_kernfs_id(const union kernfs_node_id *id, + char *buf, size_t buflen); #else /* !CONFIG_CGROUPS */ struct cgroup_subsys_state; struct cgroup; -static inline u64 cgroup_id(struct cgroup *cgrp) { return 1; } static inline void css_get(struct cgroup_subsys_state *css) {} static inline void css_put(struct cgroup_subsys_state *css) {} static inline int cgroup_attach_task_all(struct task_struct *from, @@ -724,6 +724,10 @@ static inline int cgroup_init_early(void) { return 0; } static inline int cgroup_init(void) { return 0; } static inline void cgroup_init_kthreadd(void) {} static inline void cgroup_kthread_ready(void) {} +static inline union kernfs_node_id *cgroup_get_kernfs_id(struct cgroup *cgrp) +{ + return NULL; +} static inline struct cgroup *cgroup_parent(struct cgroup *cgrp) { @@ -746,8 +750,8 @@ static inline bool task_under_cgroup_hierarchy(struct task_struct *task, return true; } -static inline void cgroup_path_from_kernfs_id(u64 id, char *buf, size_t buflen) -{} +static inline void cgroup_path_from_kernfs_id(const union kernfs_node_id *id, + char *buf, size_t buflen) {} #endif /* !CONFIG_CGROUPS */ #ifdef CONFIG_CGROUPS diff --git a/include/linux/compaction.h b/include/linux/compaction.h index a0eabfbeb0e1..4b898cdbdf05 100644 --- a/include/linux/compaction.h +++ b/include/linux/compaction.h @@ -86,7 +86,7 @@ static inline unsigned long compact_gap(unsigned int order) #ifdef CONFIG_COMPACTION extern int sysctl_compact_memory; extern int sysctl_compaction_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos); + void __user *buffer, size_t *length, loff_t *ppos); extern int sysctl_extfrag_threshold; extern int sysctl_compact_unevictable_allowed; diff --git a/include/linux/compat.h b/include/linux/compat.h index 176b716c9153..fd4604000669 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -539,12 +539,6 @@ asmlinkage long compat_sys_epoll_pwait(int epfd, int maxevents, int timeout, const compat_sigset_t __user *sigmask, compat_size_t sigsetsize); -asmlinkage long compat_sys_epoll_pwait2(int epfd, - struct epoll_event __user *events, - int maxevents, - const struct __kernel_timespec __user *timeout, - const compat_sigset_t __user *sigmask, - compat_size_t sigsetsize); /* fs/fcntl.c */ asmlinkage long compat_sys_fcntl(unsigned int fd, unsigned int cmd, diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h index 04f9f6d8b786..884d84a86d5b 100644 --- a/include/linux/compiler_types.h +++ b/include/linux/compiler_types.h @@ -165,9 +165,10 @@ struct ftrace_likely_data { /* * GCC does not warn about unused static inline functions for -Wunused-function. * Suppress the warning in clang as well by using __maybe_unused, but enable it - * for W=2 build. This will allow clang to find unused functions. + * for W=1 build. This will allow clang to find unused functions. Remove the + * __inline_maybe_unused entirely after fixing most of -Wunused-function warnings. */ -#ifdef KBUILD_EXTRA_WARN2 +#ifdef KBUILD_EXTRA_WARN1 #define __inline_maybe_unused #else #define __inline_maybe_unused __maybe_unused diff --git a/include/linux/cookie.h b/include/linux/cookie.h deleted file mode 100644 index 0c159f585109..000000000000 --- a/include/linux/cookie.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __LINUX_COOKIE_H -#define __LINUX_COOKIE_H - -#include -#include -#include - -struct pcpu_gen_cookie { - local_t nesting; - u64 last; -} __aligned(16); - -struct gen_cookie { - struct pcpu_gen_cookie __percpu *local; - atomic64_t forward_last ____cacheline_aligned_in_smp; - atomic64_t reverse_last; -}; - -#define COOKIE_LOCAL_BATCH 4096 - -#define DEFINE_COOKIE(name) \ - static DEFINE_PER_CPU(struct pcpu_gen_cookie, __##name); \ - static struct gen_cookie name = { \ - .local = &__##name, \ - .forward_last = ATOMIC64_INIT(0), \ - .reverse_last = ATOMIC64_INIT(0), \ - } - -static __always_inline u64 gen_cookie_next(struct gen_cookie *gc) -{ - struct pcpu_gen_cookie *local = this_cpu_ptr(gc->local); - u64 val; - - if (likely(local_inc_return(&local->nesting) == 1)) { - val = local->last; - if (__is_defined(CONFIG_SMP) && - unlikely((val & (COOKIE_LOCAL_BATCH - 1)) == 0)) { - s64 next = atomic64_add_return(COOKIE_LOCAL_BATCH, - &gc->forward_last); - val = next - COOKIE_LOCAL_BATCH; - } - local->last = ++val; - } else { - val = atomic64_dec_return(&gc->reverse_last); - } - local_dec(&local->nesting); - return val; -} - -#endif /* __LINUX_COOKIE_H */ diff --git a/include/linux/cryptohash.h b/include/linux/cryptohash.h index c324ffca96e0..f6ba4c3e60d7 100644 --- a/include/linux/cryptohash.h +++ b/include/linux/cryptohash.h @@ -4,15 +4,11 @@ #include -/* - * An implementation of SHA-1's compression function. Don't use in new code! - * You shouldn't be using SHA-1, and even if you *have* to use SHA-1, this isn't - * the correct way to hash something with SHA-1 (use crypto_shash instead). - */ -#define SHA1_DIGEST_WORDS 5 -#define SHA1_BLOCK_SIZE 64 -#define SHA1_WORKSPACE_WORDS 16 -void sha1_init(__u32 *buf); -void sha1_transform(__u32 *digest, const char *data, __u32 *W); +#define SHA_DIGEST_WORDS 5 +#define SHA_MESSAGE_BYTES (512 /*bits*/ / 8) +#define SHA_WORKSPACE_WORDS 16 + +void sha_init(__u32 *buf); +void sha_transform(__u32 *digest, const char *data, __u32 *W); #endif diff --git a/include/linux/dax.h b/include/linux/dax.h index d307f6cc7e0b..72a7f03a59f4 100644 --- a/include/linux/dax.h +++ b/include/linux/dax.h @@ -34,8 +34,6 @@ struct dax_operations { /* copy_to_iter: required operation for fs-dax direct-i/o */ size_t (*copy_to_iter)(struct dax_device *, pgoff_t, void *, size_t, struct iov_iter *); - /* zero_page_range: required operation. Zero page range */ - int (*zero_page_range)(struct dax_device *, pgoff_t, size_t); }; extern struct attribute_group dax_attribute_group; @@ -228,8 +226,6 @@ size_t dax_copy_from_iter(struct dax_device *dax_dev, pgoff_t pgoff, void *addr, size_t bytes, struct iov_iter *i); size_t dax_copy_to_iter(struct dax_device *dax_dev, pgoff_t pgoff, void *addr, size_t bytes, struct iov_iter *i); -int dax_zero_page_range(struct dax_device *dax_dev, pgoff_t pgoff, - size_t nr_pages); void dax_flush(struct dax_device *dax_dev, void *addr, size_t size); ssize_t dax_iomap_rw(struct kiocb *iocb, struct iov_iter *iter, diff --git a/include/linux/device.h b/include/linux/device.h index 3b0465da5405..13120bfc4cf8 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -1512,9 +1512,6 @@ static inline bool device_pm_not_required(struct device *dev) static inline void device_set_pm_not_required(struct device *dev) { dev->power.no_pm = true; -#ifdef CONFIG_PM - dev->power.no_callbacks = true; -#endif } static inline void dev_pm_syscore_device(struct device *dev, bool val) diff --git a/include/linux/extable.h b/include/linux/extable.h index 4ab9e78f313b..81ecfaa83ad3 100644 --- a/include/linux/extable.h +++ b/include/linux/extable.h @@ -33,14 +33,4 @@ search_module_extables(unsigned long addr) } #endif /*CONFIG_MODULES*/ -#ifdef CONFIG_BPF_JIT -const struct exception_table_entry *search_bpf_extables(unsigned long addr); -#else -static inline const struct exception_table_entry * -search_bpf_extables(unsigned long addr) -{ - return NULL; -} -#endif - #endif /* _LINUX_EXTABLE_H */ diff --git a/include/linux/fdtable.h b/include/linux/fdtable.h index a8621c595eec..f07c55ea0c22 100644 --- a/include/linux/fdtable.h +++ b/include/linux/fdtable.h @@ -109,10 +109,7 @@ struct files_struct *get_files_struct(struct task_struct *); void put_files_struct(struct files_struct *fs); void reset_files_struct(struct files_struct *); int unshare_files(struct files_struct **); -struct fd_range { - unsigned int from, to; -}; -struct files_struct *dup_fd(struct files_struct *, struct fd_range *) __latent_entropy; +struct files_struct *dup_fd(struct files_struct *, int *) __latent_entropy; void do_close_on_exec(struct files_struct *); int iterate_fd(struct files_struct *, unsigned, int (*)(const void *, struct file *, unsigned), @@ -124,7 +121,6 @@ extern void __fd_install(struct files_struct *files, unsigned int fd, struct file *file); extern int __close_fd(struct files_struct *files, unsigned int fd); -extern int __close_range(unsigned int fd, unsigned int max_fd, unsigned int flags); extern int __close_fd_get_file(unsigned int fd, struct file **res); extern struct kmem_cache *files_cachep; diff --git a/include/linux/filter.h b/include/linux/filter.h index eb480112d406..8d43a74ea923 100644 --- a/include/linux/filter.h +++ b/include/linux/filter.h @@ -21,7 +21,6 @@ #include #include #include -#include #include @@ -66,9 +65,6 @@ struct ctl_table_header; /* unused opcode to mark special call to bpf_tail_call() helper */ #define BPF_TAIL_CALL 0xf0 -/* unused opcode to mark special load instruction. Same as BPF_ABS */ -#define BPF_PROBE_MEM 0x20 - /* unused opcode to mark call to interpreter with arguments */ #define BPF_CALL_ARGS 0xe0 @@ -521,11 +517,13 @@ static inline bool insn_is_zext(const struct bpf_insn *insn) offsetof(TYPE, MEMBER); \ }) +#ifdef CONFIG_COMPAT /* A struct sock_filter is architecture independent. */ struct compat_sock_fprog { u16 len; compat_uptr_t filter; /* struct sock_filter * */ }; +#endif struct sock_fprog_kern { u16 len; @@ -534,15 +532,13 @@ struct sock_fprog_kern { #define BPF_BINARY_HEADER_MAGIC 0x05de0e82 -/* Some arches need doubleword alignment for their instructions and/or data */ -#define BPF_IMAGE_ALIGNMENT 8 - struct bpf_binary_header { #ifdef CONFIG_CFI_CLANG u32 magic; #endif u32 pages; - u8 image[] __aligned(BPF_IMAGE_ALIGNMENT); + /* Some arches need word alignment for their instructions */ + u8 image[] __aligned(4); }; struct bpf_prog { @@ -556,8 +552,7 @@ struct bpf_prog { is_func:1, /* program is a bpf function */ kprobe_override:1, /* Do we override a kprobe? */ has_callchain_buf:1, /* callchain buffer allocated? */ - enforce_expected_attach_type:1, /* Enforce expected_attach_type checking at attach time */ - call_get_stack:1; /* Do we call bpf_get_stack() or bpf_get_stackid() */ + enforce_expected_attach_type:1; /* Enforce expected_attach_type checking at attach time */ enum bpf_prog_type type; /* Type of BPF program */ enum bpf_attach_type expected_attach_type; /* For some prog types */ u32 len; /* Number of filter blocks */ @@ -637,48 +632,23 @@ static inline void bpf_jit_set_header_magic(struct bpf_binary_header *hdr) } #endif -#define __BPF_PROG_RUN(prog, ctx, dfunc) ({ \ - u32 ret; \ - cant_sleep(); \ - if (static_branch_unlikely(&bpf_stats_enabled_key)) { \ - struct bpf_prog_stats *stats; \ - u64 start = sched_clock(); \ - ret = dfunc(ctx, (prog)->insnsi, (prog)->bpf_func); \ - stats = this_cpu_ptr(prog->aux->stats); \ - u64_stats_update_begin(&stats->syncp); \ - stats->cnt++; \ - stats->nsecs += sched_clock() - start; \ - u64_stats_update_end(&stats->syncp); \ - } else { \ - ret = dfunc(ctx, (prog)->insnsi, (prog)->bpf_func); \ - } \ +#define BPF_PROG_RUN(prog, ctx) ({ \ + u32 ret; \ + cant_sleep(); \ + if (static_branch_unlikely(&bpf_stats_enabled_key)) { \ + struct bpf_prog_stats *stats; \ + u64 start = sched_clock(); \ + ret = bpf_call_func(prog, ctx); \ + stats = this_cpu_ptr(prog->aux->stats); \ + u64_stats_update_begin(&stats->syncp); \ + stats->cnt++; \ + stats->nsecs += sched_clock() - start; \ + u64_stats_update_end(&stats->syncp); \ + } else { \ + ret = bpf_call_func(prog, ctx); \ + } \ ret; }) -#define BPF_PROG_RUN(prog, ctx) \ - __BPF_PROG_RUN(prog, ctx, bpf_dispatcher_nop_func) - -/* - * Use in preemptible and therefore migratable context to make sure that - * the execution of the BPF program runs on one CPU. - * - * This uses migrate_disable/enable() explicitly to document that the - * invocation of a BPF program does not require reentrancy protection - * against a BPF program which is invoked from a preempting task. - * - * For non RT enabled kernels migrate_disable/enable() maps to - * preempt_disable/enable(), i.e. it disables also preemption. - */ -static inline u32 bpf_prog_run_pin_on_cpu(const struct bpf_prog *prog, - const void *ctx) -{ - u32 ret; - - migrate_disable(); - ret = __BPF_PROG_RUN(prog, ctx, bpf_dispatcher_nop_func); - migrate_enable(); - return ret; -} - #define BPF_SKB_CB_LEN QDISC_CB_PRIV_LEN struct bpf_skb_data_end { @@ -687,21 +657,13 @@ struct bpf_skb_data_end { void *data_end; }; -struct bpf_nh_params { - u32 nh_family; - union { - u32 ipv4_nh; - struct in6_addr ipv6_nh; - }; -}; - struct bpf_redirect_info { u32 flags; u32 tgt_index; void *tgt_value; struct bpf_map *map; + struct bpf_map *map_to_flush; u32 kern_flags; - struct bpf_nh_params nh; }; DECLARE_PER_CPU(struct bpf_redirect_info, bpf_redirect_info); @@ -764,7 +726,6 @@ static inline u8 *bpf_skb_cb(struct sk_buff *skb) return qdisc_skb_cb(skb)->data; } -/* Must be invoked with migration disabled */ static inline u32 __bpf_prog_run_save_cb(const struct bpf_prog *prog, struct sk_buff *skb) { @@ -790,9 +751,9 @@ static inline u32 bpf_prog_run_save_cb(const struct bpf_prog *prog, { u32 res; - migrate_disable(); + preempt_disable(); res = __bpf_prog_run_save_cb(prog, skb); - migrate_enable(); + preempt_enable(); return res; } @@ -811,8 +772,6 @@ static inline u32 bpf_prog_run_clear_cb(const struct bpf_prog *prog, return res; } -DECLARE_BPF_DISPATCHER(xdp) - static __always_inline u32 bpf_prog_run_xdp(const struct bpf_prog *prog, struct xdp_buff *xdp) { @@ -822,11 +781,9 @@ static __always_inline u32 bpf_prog_run_xdp(const struct bpf_prog *prog, * already takes rcu_read_lock() when fetching the program, so * it's not necessary here anymore. */ - return __BPF_PROG_RUN(prog, xdp, BPF_DISPATCHER_FUNC(xdp)); + return BPF_PROG_RUN(prog, xdp); } -void bpf_prog_change_xdp(struct bpf_prog *prev_prog, struct bpf_prog *prog); - static inline u32 bpf_prog_insn_size(const struct bpf_prog *prog) { return prog->len * sizeof(struct bpf_insn); @@ -835,7 +792,7 @@ static inline u32 bpf_prog_insn_size(const struct bpf_prog *prog) static inline u32 bpf_prog_tag_scratch_size(const struct bpf_prog *prog) { return round_up(bpf_prog_insn_size(prog) + - sizeof(__be64) + 1, SHA1_BLOCK_SIZE); + sizeof(__be64) + 1, SHA_MESSAGE_BYTES); } static inline unsigned int bpf_prog_size(unsigned int proglen) @@ -959,7 +916,8 @@ int sk_reuseport_attach_filter(struct sock_fprog *fprog, struct sock *sk); int sk_reuseport_attach_bpf(u32 ufd, struct sock *sk); void sk_reuseport_prog_free(struct bpf_prog *prog); int sk_detach_filter(struct sock *sk); -int sk_get_filter(struct sock *sk, sockptr_t optval, unsigned int len); +int sk_get_filter(struct sock *sk, struct sock_filter __user *filter, + unsigned int len); bool sk_filter_charge(struct sock *sk, struct sk_filter *fp); void sk_filter_uncharge(struct sock *sk, struct sk_filter *fp); @@ -1024,7 +982,7 @@ static inline int xdp_ok_fwd_dev(const struct net_device *fwd, return 0; } -/* The pair of xdp_do_redirect and xdp_do_flush MUST be called in the +/* The pair of xdp_do_redirect and xdp_do_flush_map MUST be called in the * same cpu context. Further for best results no more than a single map * for the do_redirect/do_flush pair should be used. This limitation is * because we only track one map and force a flush when the map changes. @@ -1035,13 +993,7 @@ int xdp_do_generic_redirect(struct net_device *dev, struct sk_buff *skb, int xdp_do_redirect(struct net_device *dev, struct xdp_buff *xdp, struct bpf_prog *prog); -void xdp_do_flush(void); - -/* The xdp_do_flush_map() helper has been renamed to drop the _map suffix, as - * it is no longer only flushing maps. Keep this define for compatibility - * until all drivers are updated - do not use xdp_do_flush_map() in new code! - */ -#define xdp_do_flush_map xdp_do_flush +void xdp_do_flush_map(void); void bpf_warn_invalid_xdp_action(u32 act); @@ -1078,9 +1030,6 @@ void *bpf_jit_alloc_exec(unsigned long size); void bpf_jit_free_exec(void *addr); void bpf_jit_free(struct bpf_prog *fp); -int bpf_jit_add_poke_descriptor(struct bpf_prog *prog, - struct bpf_jit_poke_descriptor *poke); - int bpf_jit_get_func_addr(const struct bpf_prog *prog, const struct bpf_insn *insn, bool extra_pass, u64 *func_addr, bool *func_addr_fixed); @@ -1091,7 +1040,7 @@ void bpf_jit_prog_release_other(struct bpf_prog *fp, struct bpf_prog *fp_other); static inline void bpf_jit_dump(unsigned int flen, unsigned int proglen, u32 pass, void *image) { - pr_err("flen=%u proglen=%u pass=%u image=%p from=%s pid=%d\n", flen, + pr_err("flen=%u proglen=%u pass=%u image=%pK from=%s pid=%d\n", flen, proglen, pass, image, current->comm, task_pid_nr(current)); if (image) @@ -1170,6 +1119,7 @@ bpf_address_lookup(unsigned long addr, unsigned long *size, void bpf_prog_kallsyms_add(struct bpf_prog *fp); void bpf_prog_kallsyms_del(struct bpf_prog *fp); +void bpf_get_prog_name(const struct bpf_prog *prog, char *sym); #else /* CONFIG_BPF_JIT */ @@ -1183,13 +1133,6 @@ static inline bool bpf_prog_ebpf_jited(const struct bpf_prog *fp) return false; } -static inline int -bpf_jit_add_poke_descriptor(struct bpf_prog *prog, - struct bpf_jit_poke_descriptor *poke) -{ - return -ENOTSUPP; -} - static inline void bpf_jit_free(struct bpf_prog *fp) { bpf_prog_unlock_free(fp); @@ -1233,6 +1176,11 @@ static inline void bpf_prog_kallsyms_del(struct bpf_prog *fp) { } +static inline void bpf_get_prog_name(const struct bpf_prog *prog, char *sym) +{ + sym[0] = '\0'; +} + #endif /* CONFIG_BPF_JIT */ void bpf_prog_kallsyms_del_all(struct bpf_prog *fp); @@ -1322,17 +1270,13 @@ struct bpf_sock_addr_kern { struct bpf_sock_ops_kern { struct sock *sk; + u32 op; union { u32 args[4]; u32 reply; u32 replylong[4]; }; - struct sk_buff *syn_skb; - struct sk_buff *skb; - void *skb_data_end; - u8 op; - u8 is_fullsock; - u8 remaining_opt_len; + u32 is_fullsock; u64 temp; /* temp and everything after is not * initialized to 0 before calling * the BPF program. New fields that @@ -1368,153 +1312,4 @@ struct bpf_sockopt_kern { s32 retval; }; -int copy_bpf_fprog_from_user(struct sock_fprog *dst, sockptr_t src, int len); - -struct bpf_sk_lookup_kern { - u16 family; - u16 protocol; - struct { - __be32 saddr; - __be32 daddr; - } v4; - struct { - const struct in6_addr *saddr; - const struct in6_addr *daddr; - } v6; - __be16 sport; - u16 dport; - struct sock *selected_sk; - bool no_reuseport; -}; - -extern struct static_key_false bpf_sk_lookup_enabled; - -/* Runners for BPF_SK_LOOKUP programs to invoke on socket lookup. - * - * Allowed return values for a BPF SK_LOOKUP program are SK_PASS and - * SK_DROP. Their meaning is as follows: - * - * SK_PASS && ctx.selected_sk != NULL: use selected_sk as lookup result - * SK_PASS && ctx.selected_sk == NULL: continue to htable-based socket lookup - * SK_DROP : terminate lookup with -ECONNREFUSED - * - * This macro aggregates return values and selected sockets from - * multiple BPF programs according to following rules in order: - * - * 1. If any program returned SK_PASS and a non-NULL ctx.selected_sk, - * macro result is SK_PASS and last ctx.selected_sk is used. - * 2. If any program returned SK_DROP return value, - * macro result is SK_DROP. - * 3. Otherwise result is SK_PASS and ctx.selected_sk is NULL. - * - * Caller must ensure that the prog array is non-NULL, and that the - * array as well as the programs it contains remain valid. - */ -#define BPF_PROG_SK_LOOKUP_RUN_ARRAY(array, ctx, func) \ - ({ \ - struct bpf_sk_lookup_kern *_ctx = &(ctx); \ - struct bpf_prog_array_item *_item; \ - struct sock *_selected_sk = NULL; \ - bool _no_reuseport = false; \ - struct bpf_prog *_prog; \ - bool _all_pass = true; \ - u32 _ret; \ - \ - migrate_disable(); \ - _item = &(array)->items[0]; \ - while ((_prog = READ_ONCE(_item->prog))) { \ - /* restore most recent selection */ \ - _ctx->selected_sk = _selected_sk; \ - _ctx->no_reuseport = _no_reuseport; \ - \ - _ret = func(_prog, _ctx); \ - if (_ret == SK_PASS && _ctx->selected_sk) { \ - /* remember last non-NULL socket */ \ - _selected_sk = _ctx->selected_sk; \ - _no_reuseport = _ctx->no_reuseport; \ - } else if (_ret == SK_DROP && _all_pass) { \ - _all_pass = false; \ - } \ - _item++; \ - } \ - _ctx->selected_sk = _selected_sk; \ - _ctx->no_reuseport = _no_reuseport; \ - migrate_enable(); \ - _all_pass || _selected_sk ? SK_PASS : SK_DROP; \ - }) - -static inline bool bpf_sk_lookup_run_v4(struct net *net, int protocol, - const __be32 saddr, const __be16 sport, - const __be32 daddr, const u16 dport, - struct sock **psk) -{ - struct bpf_prog_array *run_array; - struct sock *selected_sk = NULL; - bool no_reuseport = false; - - rcu_read_lock(); - run_array = rcu_dereference(net->bpf.run_array[NETNS_BPF_SK_LOOKUP]); - if (run_array) { - struct bpf_sk_lookup_kern ctx = { - .family = AF_INET, - .protocol = protocol, - .v4.saddr = saddr, - .v4.daddr = daddr, - .sport = sport, - .dport = dport, - }; - u32 act; - - act = BPF_PROG_SK_LOOKUP_RUN_ARRAY(run_array, ctx, BPF_PROG_RUN); - if (act == SK_PASS) { - selected_sk = ctx.selected_sk; - no_reuseport = ctx.no_reuseport; - } else { - selected_sk = ERR_PTR(-ECONNREFUSED); - } - } - rcu_read_unlock(); - *psk = selected_sk; - return no_reuseport; -} - -#if IS_ENABLED(CONFIG_IPV6) -static inline bool bpf_sk_lookup_run_v6(struct net *net, int protocol, - const struct in6_addr *saddr, - const __be16 sport, - const struct in6_addr *daddr, - const u16 dport, - struct sock **psk) -{ - struct bpf_prog_array *run_array; - struct sock *selected_sk = NULL; - bool no_reuseport = false; - - rcu_read_lock(); - run_array = rcu_dereference(net->bpf.run_array[NETNS_BPF_SK_LOOKUP]); - if (run_array) { - struct bpf_sk_lookup_kern ctx = { - .family = AF_INET6, - .protocol = protocol, - .v6.saddr = saddr, - .v6.daddr = daddr, - .sport = sport, - .dport = dport, - }; - u32 act; - - act = BPF_PROG_SK_LOOKUP_RUN_ARRAY(run_array, ctx, BPF_PROG_RUN); - if (act == SK_PASS) { - selected_sk = ctx.selected_sk; - no_reuseport = ctx.no_reuseport; - } else { - selected_sk = ERR_PTR(-ECONNREFUSED); - } - } - rcu_read_unlock(); - *psk = selected_sk; - return no_reuseport; -} -#endif /* IS_ENABLED(CONFIG_IPV6) */ - #endif /* __LINUX_FILTER_H__ */ diff --git a/include/linux/fs.h b/include/linux/fs.h index e79b51ff5807..d94140ca111d 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -2167,18 +2167,6 @@ static inline void init_sync_kiocb(struct kiocb *kiocb, struct file *filp) }; } -static inline void kiocb_clone(struct kiocb *kiocb, struct kiocb *kiocb_src, - struct file *filp) -{ - *kiocb = (struct kiocb) { - .ki_filp = filp, - .ki_flags = kiocb_src->ki_flags, - .ki_hint = kiocb_src->ki_hint, - .ki_ioprio = kiocb_src->ki_ioprio, - .ki_pos = kiocb_src->ki_pos, - }; -} - /* * Inode state bits. Protected by inode->i_lock * @@ -2997,11 +2985,6 @@ static inline bool execute_ok(struct inode *inode) return (inode->i_mode & S_IXUGO) || S_ISDIR(inode->i_mode); } -static inline bool inode_wrong_type(const struct inode *inode, umode_t mode) -{ - return (inode->i_mode ^ mode) & S_IFMT; -} - static inline void file_start_write(struct file *file) { if (!S_ISREG(file_inode(file)->i_mode)) @@ -3232,10 +3215,6 @@ ssize_t vfs_iter_read(struct file *file, struct iov_iter *iter, loff_t *ppos, rwf_t flags); ssize_t vfs_iter_write(struct file *file, struct iov_iter *iter, loff_t *ppos, rwf_t flags); -ssize_t vfs_iocb_iter_read(struct file *file, struct kiocb *iocb, - struct iov_iter *iter); -ssize_t vfs_iocb_iter_write(struct file *file, struct kiocb *iocb, - struct iov_iter *iter); /* fs/block_dev.c */ extern ssize_t blkdev_read_iter(struct kiocb *iocb, struct iov_iter *to); @@ -3661,11 +3640,11 @@ ssize_t simple_attr_write_signed(struct file *file, const char __user *buf, struct ctl_table; int proc_nr_files(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); int proc_nr_dentry(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); int proc_nr_inodes(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); int __init get_filesystem_list(char *buf); #define __FMODE_EXEC ((__force int) FMODE_EXEC) diff --git a/include/linux/fs_context.h b/include/linux/fs_context.h index d5a73cd318f8..ebcb91a57e86 100644 --- a/include/linux/fs_context.h +++ b/include/linux/fs_context.h @@ -105,7 +105,6 @@ struct fs_context { enum fs_context_phase phase:8; /* The phase the context is in */ bool need_free:1; /* Need to call ops->free() */ bool global:1; /* Goes into &init_user_ns */ - bool oldapi:1; /* Coming from mount(2) */ }; struct fs_context_operations { diff --git a/include/linux/ftrace.h b/include/linux/ftrace.h index a96941c30991..52c1c6feef89 100644 --- a/include/linux/ftrace.h +++ b/include/linux/ftrace.h @@ -81,7 +81,8 @@ static inline int ftrace_mod_get_kallsym(unsigned int symnum, unsigned long *val extern int ftrace_enabled; extern int ftrace_enable_sysctl(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, + loff_t *ppos); struct ftrace_ops; @@ -141,10 +142,6 @@ ftrace_func_t ftrace_ops_get_func(struct ftrace_ops *ops); * PID - Is affected by set_ftrace_pid (allows filtering on those pids) * RCU - Set when the ops can only be called when RCU is watching. * TRACE_ARRAY - The ops->private points to a trace_array descriptor. - * PERMANENT - Set when the ops is permanent and should not be affected by - * ftrace_enabled. - * DIRECT - Used by the direct ftrace_ops helper for direct functions - * (internal ftrace only, should not be used by others) */ enum { FTRACE_OPS_FL_ENABLED = 1 << 0, @@ -163,8 +160,6 @@ enum { FTRACE_OPS_FL_PID = 1 << 13, FTRACE_OPS_FL_RCU = 1 << 14, FTRACE_OPS_FL_TRACE_ARRAY = 1 << 15, - FTRACE_OPS_FL_PERMANENT = 1 << 16, - FTRACE_OPS_FL_DIRECT = 1 << 17, }; #ifdef CONFIG_DYNAMIC_FTRACE @@ -244,44 +239,13 @@ static inline void ftrace_free_init_mem(void) { } static inline void ftrace_free_mem(struct module *mod, void *start, void *end) { } #endif /* CONFIG_FUNCTION_TRACER */ -#ifdef CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS -int register_ftrace_direct(unsigned long ip, unsigned long addr); -int unregister_ftrace_direct(unsigned long ip, unsigned long addr); -int modify_ftrace_direct(unsigned long ip, unsigned long old_addr, unsigned long new_addr); -#else -static inline int register_ftrace_direct(unsigned long ip, unsigned long addr) -{ - return -ENODEV; -} -static inline int unregister_ftrace_direct(unsigned long ip, unsigned long addr) -{ - return -ENODEV; -} -static inline int modify_ftrace_direct(unsigned long ip, - unsigned long old_addr, unsigned long new_addr) -{ - return -ENODEV; -} -#endif /* CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS */ - -#ifndef CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS -/* - * This must be implemented by the architecture. - * It is the way the ftrace direct_ops helper, when called - * via ftrace (because there's other callbacks besides the - * direct call), can inform the architecture's trampoline that this - * routine has a direct caller, and what the caller is. - */ -static inline void arch_ftrace_set_direct_caller(struct pt_regs *regs, - unsigned long addr) { } -#endif /* CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS */ - #ifdef CONFIG_STACK_TRACER extern int stack_tracer_enabled; -int stack_trace_sysctl(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos); +int stack_trace_sysctl(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); /* DO NOT MODIFY THIS VARIABLE DIRECTLY! */ DECLARE_PER_CPU(int, disable_stack_tracer); @@ -366,7 +330,6 @@ bool is_ftrace_trampoline(unsigned long addr); * REGS_EN - the function is set up to save regs. * IPMODIFY - the record allows for the IP address to be changed. * DISABLED - the record is not ready to be touched yet - * DIRECT - there is a direct function to call * * When a new ftrace_ops is registered and wants a function to save * pt_regs, the rec->flag REGS is set. When the function has been @@ -382,12 +345,10 @@ enum { FTRACE_FL_TRAMP_EN = (1UL << 27), FTRACE_FL_IPMODIFY = (1UL << 26), FTRACE_FL_DISABLED = (1UL << 25), - FTRACE_FL_DIRECT = (1UL << 24), - FTRACE_FL_DIRECT_EN = (1UL << 23), }; -#define FTRACE_REF_MAX_SHIFT 23 -#define FTRACE_FL_BITS 9 +#define FTRACE_REF_MAX_SHIFT 25 +#define FTRACE_FL_BITS 7 #define FTRACE_FL_MASKED_BITS ((1UL << FTRACE_FL_BITS) - 1) #define FTRACE_FL_MASK (FTRACE_FL_MASKED_BITS << FTRACE_REF_MAX_SHIFT) #define FTRACE_REF_MAX ((1UL << FTRACE_REF_MAX_SHIFT) - 1) @@ -967,7 +928,8 @@ extern void disable_trace_on_warning(void); extern int __disable_trace_on_warning; int tracepoint_printk_sysctl(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, + loff_t *ppos); #else /* CONFIG_TRACING */ static inline void disable_trace_on_warning(void) { } diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h index ab4172813c63..17f6b1a34aef 100644 --- a/include/linux/hugetlb.h +++ b/include/linux/hugetlb.h @@ -62,13 +62,14 @@ struct hugepage_subpool *hugepage_new_subpool(struct hstate *h, long max_hpages, void hugepage_put_subpool(struct hugepage_subpool *spool); void reset_vma_resv_huge_pages(struct vm_area_struct *vma); -int hugetlb_sysctl_handler(struct ctl_table *, int, void *, size_t *, loff_t *); -int hugetlb_overcommit_handler(struct ctl_table *, int, void *, size_t *, - loff_t *); -int hugetlb_treat_movable_handler(struct ctl_table *, int, void *, size_t *, - loff_t *); -int hugetlb_mempolicy_sysctl_handler(struct ctl_table *, int, void *, size_t *, - loff_t *); +int hugetlb_sysctl_handler(struct ctl_table *, int, void __user *, size_t *, loff_t *); +int hugetlb_overcommit_handler(struct ctl_table *, int, void __user *, size_t *, loff_t *); +int hugetlb_treat_movable_handler(struct ctl_table *, int, void __user *, size_t *, loff_t *); + +#ifdef CONFIG_NUMA +int hugetlb_mempolicy_sysctl_handler(struct ctl_table *, int, + void __user *, size_t *, loff_t *); +#endif int copy_hugetlb_page_range(struct mm_struct *, struct mm_struct *, struct vm_area_struct *); long follow_hugetlb_page(struct mm_struct *, struct vm_area_struct *, diff --git a/include/linux/if_bridge.h b/include/linux/if_bridge.h index e06623fa5b80..9e2ad3b81690 100644 --- a/include/linux/if_bridge.h +++ b/include/linux/if_bridge.h @@ -162,9 +162,5 @@ extern br_notify_hook_t __rcu *br_notify_hook; typedef int (br_multicast_handle_hook_t)(const struct net_bridge_port *src, struct sk_buff *skb); extern br_multicast_handle_hook_t __rcu *br_multicast_handle_hook; -typedef struct net_bridge_port *br_get_dst_hook_t( - const struct net_bridge_port *src, - struct sk_buff **skb); -extern br_get_dst_hook_t __rcu *br_get_dst_hook; #endif #endif diff --git a/include/linux/iio/frequency/adf4350.h b/include/linux/iio/frequency/adf4350.h index 531d9903446c..ce9490bfeb89 100644 --- a/include/linux/iio/frequency/adf4350.h +++ b/include/linux/iio/frequency/adf4350.h @@ -51,7 +51,7 @@ /* REG3 Bit Definitions */ #define ADF4350_REG3_12BIT_CLKDIV(x) ((x) << 3) -#define ADF4350_REG3_12BIT_CLKDIV_MODE(x) ((x) << 15) +#define ADF4350_REG3_12BIT_CLKDIV_MODE(x) ((x) << 16) #define ADF4350_REG3_12BIT_CSR_EN (1 << 18) #define ADF4351_REG3_CHARGE_CANCELLATION_EN (1 << 21) #define ADF4351_REG3_ANTI_BACKLASH_3ns_EN (1 << 22) diff --git a/include/linux/io-pgtable-fast.h b/include/linux/io-pgtable-fast.h index 95b05a85f61c..245f86fbbe46 100644 --- a/include/linux/io-pgtable-fast.h +++ b/include/linux/io-pgtable-fast.h @@ -44,7 +44,7 @@ struct av8l_fast_io_pgtable { int av8l_fast_map_public(struct io_pgtable_ops *ops, unsigned long iova, phys_addr_t paddr, size_t size, int prot); -size_t av8l_fast_unmap_public(struct io_pgtable_ops *ops, unsigned long iova, +void av8l_fast_unmap_public(struct io_pgtable_ops *ops, unsigned long iova, size_t size); int av8l_fast_map_sg_public(struct io_pgtable_ops *ops, @@ -63,10 +63,9 @@ av8l_fast_map_public(struct io_pgtable_ops *ops, unsigned long iova, { return -EINVAL; } -static inline size_t av8l_fast_unmap_public(struct io_pgtable_ops *ops, +static inline void av8l_fast_unmap_public(struct io_pgtable_ops *ops, unsigned long iova, size_t size) { - return 0; } static inline int av8l_fast_map_sg_public(struct io_pgtable_ops *ops, diff --git a/include/linux/ipv6.h b/include/linux/ipv6.h index 6003273ec2e9..6f006ccbdca7 100644 --- a/include/linux/ipv6.h +++ b/include/linux/ipv6.h @@ -33,7 +33,6 @@ struct ipv6_devconf { __s32 max_addresses; __s32 accept_ra_defrtr; __s32 accept_ra_min_hop_limit; - __s32 accept_ra_min_lft; __s32 accept_ra_pinfo; __s32 ignore_routes_with_linkdown; #ifdef CONFIG_IPV6_ROUTER_PREF diff --git a/include/linux/irq_work.h b/include/linux/irq_work.h index 02da997ad12c..b11fcdfd0770 100644 --- a/include/linux/irq_work.h +++ b/include/linux/irq_work.h @@ -22,7 +22,7 @@ #define IRQ_WORK_CLAIMED (IRQ_WORK_PENDING | IRQ_WORK_BUSY) struct irq_work { - atomic_t flags; + unsigned long flags; struct llist_node llnode; void (*func)(struct irq_work *); }; @@ -30,15 +30,11 @@ struct irq_work { static inline void init_irq_work(struct irq_work *work, void (*func)(struct irq_work *)) { - atomic_set(&work->flags, 0); + work->flags = 0; work->func = func; } -#define DEFINE_IRQ_WORK(name, _f) struct irq_work name = { \ - .flags = ATOMIC_INIT(0), \ - .func = (_f) \ -} - +#define DEFINE_IRQ_WORK(name, _f) struct irq_work name = { .func = (_f), } bool irq_work_queue(struct irq_work *work); bool irq_work_queue_on(struct irq_work *work, int cpu); diff --git a/include/linux/kernfs.h b/include/linux/kernfs.h index aa6c9f95c397..88293d22a0a7 100644 --- a/include/linux/kernfs.h +++ b/include/linux/kernfs.h @@ -38,10 +38,8 @@ enum kernfs_node_type { KERNFS_LINK = 0x0004, }; -#define KERNFS_TYPE_MASK 0x000f -#define KERNFS_FLAG_MASK ~KERNFS_TYPE_MASK -#define KERNFS_MAX_USER_XATTRS 128 -#define KERNFS_USER_XATTR_SIZE_LIMIT (128 << 10) +#define KERNFS_TYPE_MASK 0x000f +#define KERNFS_FLAG_MASK ~KERNFS_TYPE_MASK enum kernfs_node_flag { KERNFS_ACTIVATED = 0x0010, @@ -81,11 +79,6 @@ enum kernfs_root_flag { * fhandle to access nodes of the fs. */ KERNFS_ROOT_SUPPORT_EXPORTOP = 0x0004, - - /* - * Support user xattrs to be written to nodes rooted at this root. - */ - KERNFS_ROOT_SUPPORT_USER_XATTR = 0x0008, }; /* type-specific structures for kernfs_node union members */ @@ -112,6 +105,21 @@ struct kernfs_elem_attr { struct kernfs_node *notify_next; /* for kernfs_notify() */ }; +/* represent a kernfs node */ +union kernfs_node_id { + struct { + /* + * blktrace will export this struct as a simplified 'struct + * fid' (which is a big data struction), so userspace can use + * it to find kernfs node. The layout must match the first two + * fields of 'struct fid' exactly. + */ + u32 ino; + u32 generation; + }; + u64 id; +}; + /* * kernfs_node - the building block of kernfs hierarchy. Each and every * kernfs node is represented by single kernfs_node. Most fields are @@ -148,12 +156,7 @@ struct kernfs_node { void *priv; - /* - * 64bit unique ID. Lower 32bits carry the inode number and lower - * generation. - */ - u64 id; - + union kernfs_node_id id; unsigned short flags; umode_t mode; struct kernfs_iattrs *iattr; @@ -298,26 +301,6 @@ static inline enum kernfs_node_type kernfs_type(struct kernfs_node *kn) return kn->flags & KERNFS_TYPE_MASK; } -static inline ino_t kernfs_id_ino(u64 id) -{ - return (u32)id; -} - -static inline u32 kernfs_id_gen(u64 id) -{ - return id >> 32; -} - -static inline ino_t kernfs_ino(struct kernfs_node *kn) -{ - return kernfs_id_ino(kn->id); -} - -static inline ino_t kernfs_gen(struct kernfs_node *kn) -{ - return kernfs_id_gen(kn->id); -} - /** * kernfs_enable_ns - enable namespace under a directory * @kn: directory of interest, should be empty @@ -409,7 +392,8 @@ void kernfs_kill_sb(struct super_block *sb); void kernfs_init(void); -struct kernfs_node *kernfs_get_node_by_id(struct kernfs_root *root, u64 id); +struct kernfs_node *kernfs_get_node_by_id(struct kernfs_root *root, + const union kernfs_node_id *id); #else /* CONFIG_KERNFS */ static inline enum kernfs_node_type kernfs_type(struct kernfs_node *kn) diff --git a/include/linux/kfence.h b/include/linux/kfence.h deleted file mode 100644 index 3fe6dd8a18c1..000000000000 --- a/include/linux/kfence.h +++ /dev/null @@ -1,223 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Kernel Electric-Fence (KFENCE). Public interface for allocator and fault - * handler integration. For more info see Documentation/dev-tools/kfence.rst. - * - * Copyright (C) 2020, Google LLC. - */ - -#ifndef _LINUX_KFENCE_H -#define _LINUX_KFENCE_H - -#include -#include - -#ifdef CONFIG_KFENCE - -/* - * We allocate an even number of pages, as it simplifies calculations to map - * address to metadata indices; effectively, the very first page serves as an - * extended guard page, but otherwise has no special purpose. - */ -#define KFENCE_POOL_SIZE ((CONFIG_KFENCE_NUM_OBJECTS + 1) * 2 * PAGE_SIZE) -extern char *__kfence_pool; - -#ifdef CONFIG_KFENCE_STATIC_KEYS -#include -DECLARE_STATIC_KEY_FALSE(kfence_allocation_key); -#else -#include -extern atomic_t kfence_allocation_gate; -#endif - -/** - * is_kfence_address() - check if an address belongs to KFENCE pool - * @addr: address to check - * - * Return: true or false depending on whether the address is within the KFENCE - * object range. - * - * KFENCE objects live in a separate page range and are not to be intermixed - * with regular heap objects (e.g. KFENCE objects must never be added to the - * allocator freelists). Failing to do so may and will result in heap - * corruptions, therefore is_kfence_address() must be used to check whether - * an object requires specific handling. - * - * Note: This function may be used in fast-paths, and is performance critical. - * Future changes should take this into account; for instance, we want to avoid - * introducing another load and therefore need to keep KFENCE_POOL_SIZE a - * constant (until immediate patching support is added to the kernel). - */ -static __always_inline bool is_kfence_address(const void *addr) -{ - /* - * The __kfence_pool != NULL check is required to deal with the case - * where __kfence_pool == NULL && addr < KFENCE_POOL_SIZE. Keep it in - * the slow-path after the range-check! - */ - return unlikely((unsigned long)((char *)addr - __kfence_pool) < KFENCE_POOL_SIZE && __kfence_pool); -} - -/** - * kfence_alloc_pool() - allocate the KFENCE pool via memblock - */ -void __init kfence_alloc_pool(void); - -/** - * kfence_init() - perform KFENCE initialization at boot time - * - * Requires that kfence_alloc_pool() was called before. This sets up the - * allocation gate timer, and requires that workqueues are available. - */ -void __init kfence_init(void); - -/** - * kfence_shutdown_cache() - handle shutdown_cache() for KFENCE objects - * @s: cache being shut down - * - * Before shutting down a cache, one must ensure there are no remaining objects - * allocated from it. Because KFENCE objects are not referenced from the cache - * directly, we need to check them here. - * - * Note that shutdown_cache() is internal to SL*B, and kmem_cache_destroy() does - * not return if allocated objects still exist: it prints an error message and - * simply aborts destruction of a cache, leaking memory. - * - * If the only such objects are KFENCE objects, we will not leak the entire - * cache, but instead try to provide more useful debug info by making allocated - * objects "zombie allocations". Objects may then still be used or freed (which - * is handled gracefully), but usage will result in showing KFENCE error reports - * which include stack traces to the user of the object, the original allocation - * site, and caller to shutdown_cache(). - */ -void kfence_shutdown_cache(struct kmem_cache *s); - -/* - * Allocate a KFENCE object. Allocators must not call this function directly, - * use kfence_alloc() instead. - */ -void *__kfence_alloc(struct kmem_cache *s, size_t size, gfp_t flags); - -/** - * kfence_alloc() - allocate a KFENCE object with a low probability - * @s: struct kmem_cache with object requirements - * @size: exact size of the object to allocate (can be less than @s->size - * e.g. for kmalloc caches) - * @flags: GFP flags - * - * Return: - * * NULL - must proceed with allocating as usual, - * * non-NULL - pointer to a KFENCE object. - * - * kfence_alloc() should be inserted into the heap allocation fast path, - * allowing it to transparently return KFENCE-allocated objects with a low - * probability using a static branch (the probability is controlled by the - * kfence.sample_interval boot parameter). - */ -static __always_inline void *kfence_alloc(struct kmem_cache *s, size_t size, gfp_t flags) -{ -#ifdef CONFIG_KFENCE_STATIC_KEYS - if (static_branch_unlikely(&kfence_allocation_key)) -#else - if (unlikely(!atomic_read(&kfence_allocation_gate))) -#endif - return __kfence_alloc(s, size, flags); - return NULL; -} - -/** - * kfence_ksize() - get actual amount of memory allocated for a KFENCE object - * @addr: pointer to a heap object - * - * Return: - * * 0 - not a KFENCE object, must call __ksize() instead, - * * non-0 - this many bytes can be accessed without causing a memory error. - * - * kfence_ksize() returns the number of bytes requested for a KFENCE object at - * allocation time. This number may be less than the object size of the - * corresponding struct kmem_cache. - */ -size_t kfence_ksize(const void *addr); - -/** - * kfence_object_start() - find the beginning of a KFENCE object - * @addr: address within a KFENCE-allocated object - * - * Return: address of the beginning of the object. - * - * SL[AU]B-allocated objects are laid out within a page one by one, so it is - * easy to calculate the beginning of an object given a pointer inside it and - * the object size. The same is not true for KFENCE, which places a single - * object at either end of the page. This helper function is used to find the - * beginning of a KFENCE-allocated object. - */ -void *kfence_object_start(const void *addr); - -/** - * __kfence_free() - release a KFENCE heap object to KFENCE pool - * @addr: object to be freed - * - * Requires: is_kfence_address(addr) - * - * Release a KFENCE object and mark it as freed. - */ -void __kfence_free(void *addr); - -/** - * kfence_free() - try to release an arbitrary heap object to KFENCE pool - * @addr: object to be freed - * - * Return: - * * false - object doesn't belong to KFENCE pool and was ignored, - * * true - object was released to KFENCE pool. - * - * Release a KFENCE object and mark it as freed. May be called on any object, - * even non-KFENCE objects, to simplify integration of the hooks into the - * allocator's free codepath. The allocator must check the return value to - * determine if it was a KFENCE object or not. - */ -static __always_inline __must_check bool kfence_free(void *addr) -{ - if (!is_kfence_address(addr)) - return false; - __kfence_free(addr); - return true; -} - -/** - * kfence_handle_page_fault() - perform page fault handling for KFENCE pages - * @addr: faulting address - * @is_write: is access a write - * @regs: current struct pt_regs (can be NULL, but shows full stack trace) - * - * Return: - * * false - address outside KFENCE pool, - * * true - page fault handled by KFENCE, no additional handling required. - * - * A page fault inside KFENCE pool indicates a memory error, such as an - * out-of-bounds access, a use-after-free or an invalid memory access. In these - * cases KFENCE prints an error message and marks the offending page as - * present, so that the kernel can proceed. - */ -bool __must_check kfence_handle_page_fault(unsigned long addr, bool is_write, struct pt_regs *regs); - -#else /* CONFIG_KFENCE */ - -static inline bool is_kfence_address(const void *addr) { return false; } -static inline void kfence_alloc_pool(void) { } -static inline void kfence_init(void) { } -static inline void kfence_shutdown_cache(struct kmem_cache *s) { } -static inline void *kfence_alloc(struct kmem_cache *s, size_t size, gfp_t flags) { return NULL; } -static inline size_t kfence_ksize(const void *addr) { return 0; } -static inline void *kfence_object_start(const void *addr) { return NULL; } -static inline void __kfence_free(void *addr) { } -static inline bool __must_check kfence_free(void *addr) { return false; } -static inline bool __must_check kfence_handle_page_fault(unsigned long addr, bool is_write, - struct pt_regs *regs) -{ - return false; -} - -#endif - -#endif /* _LINUX_KFENCE_H */ diff --git a/include/linux/kprobes.h b/include/linux/kprobes.h index a30554f14576..0be024dffa0c 100644 --- a/include/linux/kprobes.h +++ b/include/linux/kprobes.h @@ -314,7 +314,7 @@ DEFINE_INSN_CACHE_OPS(optinsn); #ifdef CONFIG_SYSCTL extern int sysctl_kprobes_optimization; extern int proc_kprobes_optimization_handler(struct ctl_table *table, - int write, void *buffer, + int write, void __user *buffer, size_t *length, loff_t *ppos); #endif extern void wait_for_kprobe_optimizer(void); diff --git a/include/linux/latencytop.h b/include/linux/latencytop.h index abe3d95f795b..9022f0c2e2e4 100644 --- a/include/linux/latencytop.h +++ b/include/linux/latencytop.h @@ -38,8 +38,8 @@ account_scheduler_latency(struct task_struct *task, int usecs, int inter) void clear_tsk_latency_tracing(struct task_struct *p); -int sysctl_latencytop(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos); +extern int sysctl_latencytop(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, loff_t *ppos); #else diff --git a/include/linux/limits.h b/include/linux/limits.h index b568b9c30bbf..7fc497ee1393 100644 --- a/include/linux/limits.h +++ b/include/linux/limits.h @@ -16,7 +16,6 @@ #define S16_MAX ((s16)(U16_MAX >> 1)) #define S16_MIN ((s16)(-S16_MAX - 1)) #define U32_MAX ((u32)~0U) -#define U32_MIN ((u32)0) #define S32_MAX ((s32)(U32_MAX >> 1)) #define S32_MIN ((s32)(-S32_MAX - 1)) #define U64_MAX ((u64)~0ULL) diff --git a/include/linux/list.h b/include/linux/list.h index 792b95fd81aa..231ff089f7d1 100644 --- a/include/linux/list.h +++ b/include/linux/list.h @@ -776,16 +776,6 @@ static inline int hlist_unhashed(const struct hlist_node *h) return !h->pprev; } -/* This variant of hlist_unhashed() must be used in lockless contexts - * to avoid potential load-tearing. - * The READ_ONCE() is paired with the various WRITE_ONCE() in hlist - * helpers that are defined below. - */ -static inline int hlist_unhashed_lockless(const struct hlist_node *h) -{ - return !READ_ONCE(h->pprev); -} - static inline int hlist_empty(const struct hlist_head *h) { return !READ_ONCE(h->first); @@ -798,7 +788,7 @@ static inline void __hlist_del(struct hlist_node *n) WRITE_ONCE(*pprev, next); if (next) - WRITE_ONCE(next->pprev, pprev); + next->pprev = pprev; } static inline void hlist_del(struct hlist_node *n) @@ -819,32 +809,32 @@ static inline void hlist_del_init(struct hlist_node *n) static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) { struct hlist_node *first = h->first; - WRITE_ONCE(n->next, first); + n->next = first; if (first) - WRITE_ONCE(first->pprev, &n->next); + first->pprev = &n->next; WRITE_ONCE(h->first, n); - WRITE_ONCE(n->pprev, &h->first); + n->pprev = &h->first; } /* next must be != NULL */ static inline void hlist_add_before(struct hlist_node *n, struct hlist_node *next) { - WRITE_ONCE(n->pprev, next->pprev); - WRITE_ONCE(n->next, next); - WRITE_ONCE(next->pprev, &n->next); + n->pprev = next->pprev; + n->next = next; + next->pprev = &n->next; WRITE_ONCE(*(n->pprev), n); } static inline void hlist_add_behind(struct hlist_node *n, struct hlist_node *prev) { - WRITE_ONCE(n->next, prev->next); - WRITE_ONCE(prev->next, n); - WRITE_ONCE(n->pprev, &prev->next); + n->next = prev->next; + prev->next = n; + n->pprev = &prev->next; if (n->next) - WRITE_ONCE(n->next->pprev, &n->next); + n->next->pprev = &n->next; } /* after that we'll appear to be on some hlist and hlist_del will work */ diff --git a/include/linux/lsm_hook_defs.h b/include/linux/lsm_hook_defs.h deleted file mode 100644 index 77a245ac452e..000000000000 --- a/include/linux/lsm_hook_defs.h +++ /dev/null @@ -1,385 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -/* - * Linux Security Module Hook declarations. - * - * Copyright (C) 2001 WireX Communications, Inc - * Copyright (C) 2001 Greg Kroah-Hartman - * Copyright (C) 2001 Networks Associates Technology, Inc - * Copyright (C) 2001 James Morris - * Copyright (C) 2001 Silicon Graphics, Inc. (Trust Technology Group) - * Copyright (C) 2015 Intel Corporation. - * Copyright (C) 2015 Casey Schaufler - * Copyright (C) 2016 Mellanox Techonologies - * Copyright (C) 2020 Google LLC. - */ - -/* - * The macro LSM_HOOK is used to define the data structures required by the - * the LSM framework using the pattern: - * - * LSM_HOOK(, , , args...) - * - * struct security_hook_heads { - * #define LSM_HOOK(RET, DEFAULT, NAME, ...) struct hlist_head NAME; - * #include - * #undef LSM_HOOK - * }; - */ -LSM_HOOK(int, 0, binder_set_context_mgr, const struct cred *mgr) -LSM_HOOK(int, 0, binder_transaction, const struct cred *from, - const struct cred *to) -LSM_HOOK(int, 0, binder_transfer_binder, const struct cred *from, - const struct cred *to) -LSM_HOOK(int, 0, binder_transfer_file, const struct cred *from, - const struct cred *to, struct file *file) -LSM_HOOK(int, 0, ptrace_access_check, struct task_struct *child, - unsigned int mode) -LSM_HOOK(int, 0, ptrace_traceme, struct task_struct *parent) -LSM_HOOK(int, 0, capget, struct task_struct *target, kernel_cap_t *effective, - kernel_cap_t *inheritable, kernel_cap_t *permitted) -LSM_HOOK(int, 0, capset, struct cred *new, const struct cred *old, - const kernel_cap_t *effective, const kernel_cap_t *inheritable, - const kernel_cap_t *permitted) -LSM_HOOK(int, 0, capable, const struct cred *cred, struct user_namespace *ns, - int cap, unsigned int opts) -LSM_HOOK(int, 0, quotactl, int cmds, int type, int id, struct super_block *sb) -LSM_HOOK(int, 0, quota_on, struct dentry *dentry) -LSM_HOOK(int, 0, syslog, int type) -LSM_HOOK(int, 0, settime, const struct timespec64 *ts, - const struct timezone *tz) -LSM_HOOK(int, 0, vm_enough_memory, struct mm_struct *mm, long pages) -LSM_HOOK(int, 0, bprm_set_creds, struct linux_binprm *bprm) -LSM_HOOK(int, 0, bprm_check_security, struct linux_binprm *bprm) -LSM_HOOK(void, LSM_RET_VOID, bprm_committing_creds, struct linux_binprm *bprm) -LSM_HOOK(void, LSM_RET_VOID, bprm_committed_creds, struct linux_binprm *bprm) -LSM_HOOK(int, 0, fs_context_dup, struct fs_context *fc, - struct fs_context *src_sc) -LSM_HOOK(int, 0, fs_context_parse_param, struct fs_context *fc, - struct fs_parameter *param) -LSM_HOOK(int, 0, sb_alloc_security, struct super_block *sb) -LSM_HOOK(void, LSM_RET_VOID, sb_free_security, struct super_block *sb) -LSM_HOOK(void, LSM_RET_VOID, sb_free_mnt_opts, void *mnt_opts) -LSM_HOOK(int, 0, sb_eat_lsm_opts, char *orig, void **mnt_opts) -LSM_HOOK(int, 0, sb_remount, struct super_block *sb, void *mnt_opts) -LSM_HOOK(int, 0, sb_kern_mount, struct super_block *sb) -LSM_HOOK(int, 0, sb_show_options, struct seq_file *m, struct super_block *sb) -LSM_HOOK(int, 0, sb_statfs, struct dentry *dentry) -LSM_HOOK(int, 0, sb_mount, const char *dev_name, const struct path *path, - const char *type, unsigned long flags, void *data) -LSM_HOOK(int, 0, sb_umount, struct vfsmount *mnt, int flags) -LSM_HOOK(int, 0, sb_pivotroot, const struct path *old_path, - const struct path *new_path) -LSM_HOOK(int, 0, sb_set_mnt_opts, struct super_block *sb, void *mnt_opts, - unsigned long kern_flags, unsigned long *set_kern_flags) -LSM_HOOK(int, 0, sb_clone_mnt_opts, const struct super_block *oldsb, - struct super_block *newsb, unsigned long kern_flags, - unsigned long *set_kern_flags) -LSM_HOOK(int, 0, sb_add_mnt_opt, const char *option, const char *val, - int len, void **mnt_opts) -LSM_HOOK(int, 0, move_mount, const struct path *from_path, - const struct path *to_path) -LSM_HOOK(int, 0, dentry_init_security, struct dentry *dentry, - int mode, const struct qstr *name, void **ctx, u32 *ctxlen) -LSM_HOOK(int, 0, dentry_create_files_as, struct dentry *dentry, int mode, - struct qstr *name, const struct cred *old, struct cred *new) - -#ifdef CONFIG_SECURITY_PATH -LSM_HOOK(int, 0, path_unlink, const struct path *dir, struct dentry *dentry) -LSM_HOOK(int, 0, path_mkdir, const struct path *dir, struct dentry *dentry, - umode_t mode) -LSM_HOOK(int, 0, path_rmdir, const struct path *dir, struct dentry *dentry) -LSM_HOOK(int, 0, path_mknod, const struct path *dir, struct dentry *dentry, - umode_t mode, unsigned int dev) -LSM_HOOK(int, 0, path_truncate, const struct path *path) -LSM_HOOK(int, 0, path_symlink, const struct path *dir, struct dentry *dentry, - const char *old_name) -LSM_HOOK(int, 0, path_link, struct dentry *old_dentry, - const struct path *new_dir, struct dentry *new_dentry) -LSM_HOOK(int, 0, path_rename, const struct path *old_dir, - struct dentry *old_dentry, const struct path *new_dir, - struct dentry *new_dentry) -LSM_HOOK(int, 0, path_chmod, const struct path *path, umode_t mode) -LSM_HOOK(int, 0, path_chown, const struct path *path, kuid_t uid, kgid_t gid) -LSM_HOOK(int, 0, path_chroot, const struct path *path) -#endif /* CONFIG_SECURITY_PATH */ - -/* Needed for inode based security check */ -LSM_HOOK(int, 0, path_notify, const struct path *path, u64 mask, - unsigned int obj_type) -LSM_HOOK(int, 0, inode_alloc_security, struct inode *inode) -LSM_HOOK(void, LSM_RET_VOID, inode_free_security, struct inode *inode) -LSM_HOOK(int, 0, inode_init_security, struct inode *inode, - struct inode *dir, const struct qstr *qstr, const char **name, - void **value, size_t *len) -LSM_HOOK(int, 0, inode_init_security_anon, struct inode *inode, - const struct qstr *name, const struct inode *context_inode) -LSM_HOOK(int, 0, inode_create, struct inode *dir, struct dentry *dentry, - umode_t mode) -LSM_HOOK(int, 0, inode_link, struct dentry *old_dentry, struct inode *dir, - struct dentry *new_dentry) -LSM_HOOK(int, 0, inode_unlink, struct inode *dir, struct dentry *dentry) -LSM_HOOK(int, 0, inode_symlink, struct inode *dir, struct dentry *dentry, - const char *old_name) -LSM_HOOK(int, 0, inode_mkdir, struct inode *dir, struct dentry *dentry, - umode_t mode) -LSM_HOOK(int, 0, inode_rmdir, struct inode *dir, struct dentry *dentry) -LSM_HOOK(int, 0, inode_mknod, struct inode *dir, struct dentry *dentry, - umode_t mode, dev_t dev) -LSM_HOOK(int, 0, inode_rename, struct inode *old_dir, struct dentry *old_dentry, - struct inode *new_dir, struct dentry *new_dentry) -LSM_HOOK(int, 0, inode_readlink, struct dentry *dentry) -LSM_HOOK(int, 0, inode_follow_link, struct dentry *dentry, struct inode *inode, - bool rcu) -LSM_HOOK(int, 0, inode_permission, struct inode *inode, int mask) -LSM_HOOK(int, 0, inode_setattr, struct dentry *dentry, struct iattr *attr) -LSM_HOOK(int, 0, inode_getattr, const struct path *path) -LSM_HOOK(int, 0, inode_setxattr, struct dentry *dentry, const char *name, - const void *value, size_t size, int flags) -LSM_HOOK(void, LSM_RET_VOID, inode_post_setxattr, struct dentry *dentry, - const char *name, const void *value, size_t size, int flags) -LSM_HOOK(int, 0, inode_getxattr, struct dentry *dentry, const char *name) -LSM_HOOK(int, 0, inode_listxattr, struct dentry *dentry) -LSM_HOOK(int, 0, inode_removexattr, struct dentry *dentry, const char *name) -LSM_HOOK(int, 0, inode_need_killpriv, struct dentry *dentry) -LSM_HOOK(int, 0, inode_killpriv, struct dentry *dentry) -LSM_HOOK(int, -EOPNOTSUPP, inode_getsecurity, struct inode *inode, - const char *name, void **buffer, bool alloc) -LSM_HOOK(int, -EOPNOTSUPP, inode_setsecurity, struct inode *inode, - const char *name, const void *value, size_t size, int flags) -LSM_HOOK(int, 0, inode_listsecurity, struct inode *inode, char *buffer, - size_t buffer_size) -LSM_HOOK(void, LSM_RET_VOID, inode_getsecid, struct inode *inode, u32 *secid) -LSM_HOOK(int, 0, inode_copy_up, struct dentry *src, struct cred **new) -LSM_HOOK(int, 0, inode_copy_up_xattr, const char *name) -LSM_HOOK(int, 0, kernfs_init_security, struct kernfs_node *kn_dir, - struct kernfs_node *kn) -LSM_HOOK(int, 0, file_permission, struct file *file, int mask) -LSM_HOOK(int, 0, file_alloc_security, struct file *file) -LSM_HOOK(void, LSM_RET_VOID, file_free_security, struct file *file) -LSM_HOOK(int, 0, file_ioctl, struct file *file, unsigned int cmd, - unsigned long arg) -LSM_HOOK(int, 0, file_ioctl_compat, struct file *file, unsigned int cmd, - unsigned long arg) -LSM_HOOK(int, 0, mmap_addr, unsigned long addr) -LSM_HOOK(int, 0, mmap_file, struct file *file, unsigned long reqprot, - unsigned long prot, unsigned long flags) -LSM_HOOK(int, 0, file_mprotect, struct vm_area_struct *vma, - unsigned long reqprot, unsigned long prot) -LSM_HOOK(int, 0, file_lock, struct file *file, unsigned int cmd) -LSM_HOOK(int, 0, file_fcntl, struct file *file, unsigned int cmd, - unsigned long arg) -LSM_HOOK(void, LSM_RET_VOID, file_set_fowner, struct file *file) -LSM_HOOK(int, 0, file_send_sigiotask, struct task_struct *tsk, - struct fown_struct *fown, int sig) -LSM_HOOK(int, 0, file_receive, struct file *file) -LSM_HOOK(int, 0, file_open, struct file *file) -LSM_HOOK(int, 0, task_alloc, struct task_struct *task, - unsigned long clone_flags) -LSM_HOOK(void, LSM_RET_VOID, task_free, struct task_struct *task) -LSM_HOOK(int, 0, cred_alloc_blank, struct cred *cred, gfp_t gfp) -LSM_HOOK(void, LSM_RET_VOID, cred_free, struct cred *cred) -LSM_HOOK(int, 0, cred_prepare, struct cred *new, const struct cred *old, - gfp_t gfp) -LSM_HOOK(void, LSM_RET_VOID, cred_transfer, struct cred *new, - const struct cred *old) -LSM_HOOK(void, LSM_RET_VOID, cred_getsecid, const struct cred *c, u32 *secid) -LSM_HOOK(int, 0, kernel_act_as, struct cred *new, u32 secid) -LSM_HOOK(int, 0, kernel_create_files_as, struct cred *new, struct inode *inode) -LSM_HOOK(int, 0, kernel_module_request, char *kmod_name) -LSM_HOOK(int, 0, kernel_load_data, enum kernel_load_data_id id) -LSM_HOOK(int, 0, kernel_read_file, struct file *file, - enum kernel_read_file_id id) -LSM_HOOK(int, 0, kernel_post_read_file, struct file *file, char *buf, - loff_t size, enum kernel_read_file_id id) -LSM_HOOK(int, 0, task_fix_setuid, struct cred *new, const struct cred *old, - int flags) -LSM_HOOK(int, 0, task_setpgid, struct task_struct *p, pid_t pgid) -LSM_HOOK(int, 0, task_getpgid, struct task_struct *p) -LSM_HOOK(int, 0, task_getsid, struct task_struct *p) -LSM_HOOK(void, LSM_RET_VOID, task_getsecid, struct task_struct *p, u32 *secid) -LSM_HOOK(int, 0, task_setnice, struct task_struct *p, int nice) -LSM_HOOK(int, 0, task_setioprio, struct task_struct *p, int ioprio) -LSM_HOOK(int, 0, task_getioprio, struct task_struct *p) -LSM_HOOK(int, 0, task_prlimit, const struct cred *cred, - const struct cred *tcred, unsigned int flags) -LSM_HOOK(int, 0, task_setrlimit, struct task_struct *p, unsigned int resource, - struct rlimit *new_rlim) -LSM_HOOK(int, 0, task_setscheduler, struct task_struct *p) -LSM_HOOK(int, 0, task_getscheduler, struct task_struct *p) -LSM_HOOK(int, 0, task_movememory, struct task_struct *p) -LSM_HOOK(int, 0, task_kill, struct task_struct *p, struct kernel_siginfo *info, - int sig, const struct cred *cred) -LSM_HOOK(int, -ENOSYS, task_prctl, int option, unsigned long arg2, - unsigned long arg3, unsigned long arg4, unsigned long arg5) -LSM_HOOK(void, LSM_RET_VOID, task_to_inode, struct task_struct *p, - struct inode *inode) -LSM_HOOK(int, 0, ipc_permission, struct kern_ipc_perm *ipcp, short flag) -LSM_HOOK(void, LSM_RET_VOID, ipc_getsecid, struct kern_ipc_perm *ipcp, - u32 *secid) -LSM_HOOK(int, 0, msg_msg_alloc_security, struct msg_msg *msg) -LSM_HOOK(void, LSM_RET_VOID, msg_msg_free_security, struct msg_msg *msg) -LSM_HOOK(int, 0, msg_queue_alloc_security, struct kern_ipc_perm *perm) -LSM_HOOK(void, LSM_RET_VOID, msg_queue_free_security, - struct kern_ipc_perm *perm) -LSM_HOOK(int, 0, msg_queue_associate, struct kern_ipc_perm *perm, int msqflg) -LSM_HOOK(int, 0, msg_queue_msgctl, struct kern_ipc_perm *perm, int cmd) -LSM_HOOK(int, 0, msg_queue_msgsnd, struct kern_ipc_perm *perm, - struct msg_msg *msg, int msqflg) -LSM_HOOK(int, 0, msg_queue_msgrcv, struct kern_ipc_perm *perm, - struct msg_msg *msg, struct task_struct *target, long type, int mode) -LSM_HOOK(int, 0, shm_alloc_security, struct kern_ipc_perm *perm) -LSM_HOOK(void, LSM_RET_VOID, shm_free_security, struct kern_ipc_perm *perm) -LSM_HOOK(int, 0, shm_associate, struct kern_ipc_perm *perm, int shmflg) -LSM_HOOK(int, 0, shm_shmctl, struct kern_ipc_perm *perm, int cmd) -LSM_HOOK(int, 0, shm_shmat, struct kern_ipc_perm *perm, char __user *shmaddr, - int shmflg) -LSM_HOOK(int, 0, sem_alloc_security, struct kern_ipc_perm *perm) -LSM_HOOK(void, LSM_RET_VOID, sem_free_security, struct kern_ipc_perm *perm) -LSM_HOOK(int, 0, sem_associate, struct kern_ipc_perm *perm, int semflg) -LSM_HOOK(int, 0, sem_semctl, struct kern_ipc_perm *perm, int cmd) -LSM_HOOK(int, 0, sem_semop, struct kern_ipc_perm *perm, struct sembuf *sops, - unsigned nsops, int alter) -LSM_HOOK(int, 0, netlink_send, struct sock *sk, struct sk_buff *skb) -LSM_HOOK(void, LSM_RET_VOID, d_instantiate, struct dentry *dentry, - struct inode *inode) -LSM_HOOK(int, -EINVAL, getprocattr, struct task_struct *p, char *name, - char **value) -LSM_HOOK(int, -EINVAL, setprocattr, const char *name, void *value, size_t size) -LSM_HOOK(int, 0, ismaclabel, const char *name) -LSM_HOOK(int, 0, secid_to_secctx, u32 secid, char **secdata, - u32 *seclen) -LSM_HOOK(int, 0, secctx_to_secid, const char *secdata, u32 seclen, u32 *secid) -LSM_HOOK(void, LSM_RET_VOID, release_secctx, char *secdata, u32 seclen) -LSM_HOOK(void, LSM_RET_VOID, inode_invalidate_secctx, struct inode *inode) -LSM_HOOK(int, 0, inode_notifysecctx, struct inode *inode, void *ctx, u32 ctxlen) -LSM_HOOK(int, 0, inode_setsecctx, struct dentry *dentry, void *ctx, u32 ctxlen) -LSM_HOOK(int, 0, inode_getsecctx, struct inode *inode, void **ctx, - u32 *ctxlen) - -#ifdef CONFIG_SECURITY_NETWORK -LSM_HOOK(int, 0, unix_stream_connect, struct sock *sock, struct sock *other, - struct sock *newsk) -LSM_HOOK(int, 0, unix_may_send, struct socket *sock, struct socket *other) -LSM_HOOK(int, 0, socket_create, int family, int type, int protocol, int kern) -LSM_HOOK(int, 0, socket_post_create, struct socket *sock, int family, int type, - int protocol, int kern) -LSM_HOOK(int, 0, socket_socketpair, struct socket *socka, struct socket *sockb) -LSM_HOOK(int, 0, socket_bind, struct socket *sock, struct sockaddr *address, - int addrlen) -LSM_HOOK(int, 0, socket_connect, struct socket *sock, struct sockaddr *address, - int addrlen) -LSM_HOOK(int, 0, socket_listen, struct socket *sock, int backlog) -LSM_HOOK(int, 0, socket_accept, struct socket *sock, struct socket *newsock) -LSM_HOOK(int, 0, socket_sendmsg, struct socket *sock, struct msghdr *msg, - int size) -LSM_HOOK(int, 0, socket_recvmsg, struct socket *sock, struct msghdr *msg, - int size, int flags) -LSM_HOOK(int, 0, socket_getsockname, struct socket *sock) -LSM_HOOK(int, 0, socket_getpeername, struct socket *sock) -LSM_HOOK(int, 0, socket_getsockopt, struct socket *sock, int level, int optname) -LSM_HOOK(int, 0, socket_setsockopt, struct socket *sock, int level, int optname) -LSM_HOOK(int, 0, socket_shutdown, struct socket *sock, int how) -LSM_HOOK(int, 0, socket_sock_rcv_skb, struct sock *sk, struct sk_buff *skb) -LSM_HOOK(int, 0, socket_getpeersec_stream, struct socket *sock, - char __user *optval, int __user *optlen, unsigned len) -LSM_HOOK(int, 0, socket_getpeersec_dgram, struct socket *sock, - struct sk_buff *skb, u32 *secid) -LSM_HOOK(int, 0, sk_alloc_security, struct sock *sk, int family, gfp_t priority) -LSM_HOOK(void, LSM_RET_VOID, sk_free_security, struct sock *sk) -LSM_HOOK(void, LSM_RET_VOID, sk_clone_security, const struct sock *sk, - struct sock *newsk) -LSM_HOOK(void, LSM_RET_VOID, sk_getsecid, struct sock *sk, u32 *secid) -LSM_HOOK(void, LSM_RET_VOID, sock_graft, struct sock *sk, struct socket *parent) -LSM_HOOK(int, 0, inet_conn_request, struct sock *sk, struct sk_buff *skb, - struct request_sock *req) -LSM_HOOK(void, LSM_RET_VOID, inet_csk_clone, struct sock *newsk, - const struct request_sock *req) -LSM_HOOK(void, LSM_RET_VOID, inet_conn_established, struct sock *sk, - struct sk_buff *skb) -LSM_HOOK(int, 0, secmark_relabel_packet, u32 secid) -LSM_HOOK(void, LSM_RET_VOID, secmark_refcount_inc, void) -LSM_HOOK(void, LSM_RET_VOID, secmark_refcount_dec, void) -LSM_HOOK(void, LSM_RET_VOID, req_classify_flow, const struct request_sock *req, - struct flowi *fl) -LSM_HOOK(int, 0, tun_dev_alloc_security, void **security) -LSM_HOOK(void, LSM_RET_VOID, tun_dev_free_security, void *security) -LSM_HOOK(int, 0, tun_dev_create, void) -LSM_HOOK(int, 0, tun_dev_attach_queue, void *security) -LSM_HOOK(int, 0, tun_dev_attach, struct sock *sk, void *security) -LSM_HOOK(int, 0, tun_dev_open, void *security) -LSM_HOOK(int, 0, sctp_assoc_request, struct sctp_endpoint *ep, - struct sk_buff *skb) -LSM_HOOK(int, 0, sctp_bind_connect, struct sock *sk, int optname, - struct sockaddr *address, int addrlen) -LSM_HOOK(void, LSM_RET_VOID, sctp_sk_clone, struct sctp_endpoint *ep, - struct sock *sk, struct sock *newsk) -#endif /* CONFIG_SECURITY_NETWORK */ - -#ifdef CONFIG_SECURITY_INFINIBAND -LSM_HOOK(int, 0, ib_pkey_access, void *sec, u64 subnet_prefix, u16 pkey) -LSM_HOOK(int, 0, ib_endport_manage_subnet, void *sec, const char *dev_name, - u8 port_num) -LSM_HOOK(int, 0, ib_alloc_security, void **sec) -LSM_HOOK(void, LSM_RET_VOID, ib_free_security, void *sec) -#endif /* CONFIG_SECURITY_INFINIBAND */ - -#ifdef CONFIG_SECURITY_NETWORK_XFRM -LSM_HOOK(int, 0, xfrm_policy_alloc_security, struct xfrm_sec_ctx **ctxp, - struct xfrm_user_sec_ctx *sec_ctx, gfp_t gfp) -LSM_HOOK(int, 0, xfrm_policy_clone_security, struct xfrm_sec_ctx *old_ctx, - struct xfrm_sec_ctx **new_ctx) -LSM_HOOK(void, LSM_RET_VOID, xfrm_policy_free_security, - struct xfrm_sec_ctx *ctx) -LSM_HOOK(int, 0, xfrm_policy_delete_security, struct xfrm_sec_ctx *ctx) -LSM_HOOK(int, 0, xfrm_state_alloc, struct xfrm_state *x, - struct xfrm_user_sec_ctx *sec_ctx) -LSM_HOOK(int, 0, xfrm_state_alloc_acquire, struct xfrm_state *x, - struct xfrm_sec_ctx *polsec, u32 secid) -LSM_HOOK(void, LSM_RET_VOID, xfrm_state_free_security, struct xfrm_state *x) -LSM_HOOK(int, 0, xfrm_state_delete_security, struct xfrm_state *x) -LSM_HOOK(int, 0, xfrm_policy_lookup, struct xfrm_sec_ctx *ctx, u32 fl_secid, - u8 dir) -LSM_HOOK(int, 1, xfrm_state_pol_flow_match, struct xfrm_state *x, - struct xfrm_policy *xp, const struct flowi *fl) -LSM_HOOK(int, 0, xfrm_decode_session, struct sk_buff *skb, u32 *secid, - int ckall) -#endif /* CONFIG_SECURITY_NETWORK_XFRM */ - -/* key management security hooks */ -#ifdef CONFIG_KEYS -LSM_HOOK(int, 0, key_alloc, struct key *key, const struct cred *cred, - unsigned long flags) -LSM_HOOK(void, LSM_RET_VOID, key_free, struct key *key) -LSM_HOOK(int, 0, key_permission, key_ref_t key_ref, const struct cred *cred, - unsigned perm) -LSM_HOOK(int, 0, key_getsecurity, struct key *key, char **_buffer) -#endif /* CONFIG_KEYS */ - -#ifdef CONFIG_AUDIT -LSM_HOOK(int, 0, audit_rule_init, u32 field, u32 op, char *rulestr, - void **lsmrule) -LSM_HOOK(int, 0, audit_rule_known, struct audit_krule *krule) -LSM_HOOK(int, 0, audit_rule_match, u32 secid, u32 field, u32 op, void *lsmrule) -LSM_HOOK(void, LSM_RET_VOID, audit_rule_free, void *lsmrule) -#endif /* CONFIG_AUDIT */ - -#ifdef CONFIG_BPF_SYSCALL -LSM_HOOK(int, 0, bpf, int cmd, union bpf_attr *attr, unsigned int size) -LSM_HOOK(int, 0, bpf_map, struct bpf_map *map, fmode_t fmode) -LSM_HOOK(int, 0, bpf_prog, struct bpf_prog *prog) -LSM_HOOK(int, 0, bpf_map_alloc_security, struct bpf_map *map) -LSM_HOOK(void, LSM_RET_VOID, bpf_map_free_security, struct bpf_map *map) -LSM_HOOK(int, 0, bpf_prog_alloc_security, struct bpf_prog_aux *aux) -LSM_HOOK(void, LSM_RET_VOID, bpf_prog_free_security, struct bpf_prog_aux *aux) -#endif /* CONFIG_BPF_SYSCALL */ - -LSM_HOOK(int, 0, locked_down, enum lockdown_reason what) - -#ifdef CONFIG_PERF_EVENTS -LSM_HOOK(int, 0, perf_event_open, struct perf_event_attr *attr, int type) -LSM_HOOK(int, 0, perf_event_alloc, struct perf_event *event) -LSM_HOOK(void, LSM_RET_VOID, perf_event_free, struct perf_event *event) -LSM_HOOK(int, 0, perf_event_read, struct perf_event *event) -LSM_HOOK(int, 0, perf_event_write, struct perf_event *event) -#endif /* CONFIG_PERF_EVENTS */ diff --git a/include/linux/lsm_hooks.h b/include/linux/lsm_hooks.h index b81f8ba8f647..1412eec56327 100644 --- a/include/linux/lsm_hooks.h +++ b/include/linux/lsm_hooks.h @@ -1471,15 +1471,632 @@ * @what: kernel feature being accessed */ union security_list_options { - #define LSM_HOOK(RET, DEFAULT, NAME, ...) RET (*NAME)(__VA_ARGS__); - #include "lsm_hook_defs.h" - #undef LSM_HOOK + int (*binder_set_context_mgr)(const struct cred *mgr); + int (*binder_transaction)(const struct cred *from, + const struct cred *to); + int (*binder_transfer_binder)(const struct cred *from, + const struct cred *to); + int (*binder_transfer_file)(const struct cred *from, + const struct cred *to, + struct file *file); + + int (*ptrace_access_check)(struct task_struct *child, + unsigned int mode); + int (*ptrace_traceme)(struct task_struct *parent); + int (*capget)(struct task_struct *target, kernel_cap_t *effective, + kernel_cap_t *inheritable, kernel_cap_t *permitted); + int (*capset)(struct cred *new, const struct cred *old, + const kernel_cap_t *effective, + const kernel_cap_t *inheritable, + const kernel_cap_t *permitted); + int (*capable)(const struct cred *cred, + struct user_namespace *ns, + int cap, + unsigned int opts); + int (*quotactl)(int cmds, int type, int id, struct super_block *sb); + int (*quota_on)(struct dentry *dentry); + int (*syslog)(int type); + int (*settime)(const struct timespec64 *ts, const struct timezone *tz); + int (*vm_enough_memory)(struct mm_struct *mm, long pages); + + int (*bprm_set_creds)(struct linux_binprm *bprm); + int (*bprm_check_security)(struct linux_binprm *bprm); + void (*bprm_committing_creds)(struct linux_binprm *bprm); + void (*bprm_committed_creds)(struct linux_binprm *bprm); + + int (*fs_context_dup)(struct fs_context *fc, struct fs_context *src_sc); + int (*fs_context_parse_param)(struct fs_context *fc, struct fs_parameter *param); + + int (*sb_alloc_security)(struct super_block *sb); + void (*sb_free_security)(struct super_block *sb); + void (*sb_free_mnt_opts)(void *mnt_opts); + int (*sb_eat_lsm_opts)(char *orig, void **mnt_opts); + int (*sb_remount)(struct super_block *sb, void *mnt_opts); + int (*sb_kern_mount)(struct super_block *sb); + int (*sb_show_options)(struct seq_file *m, struct super_block *sb); + int (*sb_statfs)(struct dentry *dentry); + int (*sb_mount)(const char *dev_name, const struct path *path, + const char *type, unsigned long flags, void *data); + int (*sb_umount)(struct vfsmount *mnt, int flags); + int (*sb_pivotroot)(const struct path *old_path, const struct path *new_path); + int (*sb_set_mnt_opts)(struct super_block *sb, + void *mnt_opts, + unsigned long kern_flags, + unsigned long *set_kern_flags); + int (*sb_clone_mnt_opts)(const struct super_block *oldsb, + struct super_block *newsb, + unsigned long kern_flags, + unsigned long *set_kern_flags); + int (*sb_add_mnt_opt)(const char *option, const char *val, int len, + void **mnt_opts); + int (*move_mount)(const struct path *from_path, const struct path *to_path); + int (*dentry_init_security)(struct dentry *dentry, int mode, + const struct qstr *name, void **ctx, + u32 *ctxlen); + int (*dentry_create_files_as)(struct dentry *dentry, int mode, + struct qstr *name, + const struct cred *old, + struct cred *new); + + +#ifdef CONFIG_SECURITY_PATH + int (*path_unlink)(const struct path *dir, struct dentry *dentry); + int (*path_mkdir)(const struct path *dir, struct dentry *dentry, + umode_t mode); + int (*path_rmdir)(const struct path *dir, struct dentry *dentry); + int (*path_mknod)(const struct path *dir, struct dentry *dentry, + umode_t mode, unsigned int dev); + int (*path_truncate)(const struct path *path); + int (*path_symlink)(const struct path *dir, struct dentry *dentry, + const char *old_name); + int (*path_link)(struct dentry *old_dentry, const struct path *new_dir, + struct dentry *new_dentry); + int (*path_rename)(const struct path *old_dir, struct dentry *old_dentry, + const struct path *new_dir, + struct dentry *new_dentry); + int (*path_chmod)(const struct path *path, umode_t mode); + int (*path_chown)(const struct path *path, kuid_t uid, kgid_t gid); + int (*path_chroot)(const struct path *path); +#endif + /* Needed for inode based security check */ + int (*path_notify)(const struct path *path, u64 mask, + unsigned int obj_type); + int (*inode_alloc_security)(struct inode *inode); + void (*inode_free_security)(struct inode *inode); + int (*inode_init_security)(struct inode *inode, struct inode *dir, + const struct qstr *qstr, + const char **name, void **value, + size_t *len); + int (*inode_init_security_anon)(struct inode *inode, + const struct qstr *name, + const struct inode *context_inode); + int (*inode_create)(struct inode *dir, struct dentry *dentry, + umode_t mode); + int (*inode_link)(struct dentry *old_dentry, struct inode *dir, + struct dentry *new_dentry); + int (*inode_unlink)(struct inode *dir, struct dentry *dentry); + int (*inode_symlink)(struct inode *dir, struct dentry *dentry, + const char *old_name); + int (*inode_mkdir)(struct inode *dir, struct dentry *dentry, + umode_t mode); + int (*inode_rmdir)(struct inode *dir, struct dentry *dentry); + int (*inode_mknod)(struct inode *dir, struct dentry *dentry, + umode_t mode, dev_t dev); + int (*inode_rename)(struct inode *old_dir, struct dentry *old_dentry, + struct inode *new_dir, + struct dentry *new_dentry); + int (*inode_readlink)(struct dentry *dentry); + int (*inode_follow_link)(struct dentry *dentry, struct inode *inode, + bool rcu); + int (*inode_permission)(struct inode *inode, int mask); + int (*inode_setattr)(struct dentry *dentry, struct iattr *attr); + int (*inode_getattr)(const struct path *path); + int (*inode_setxattr)(struct dentry *dentry, const char *name, + const void *value, size_t size, int flags); + void (*inode_post_setxattr)(struct dentry *dentry, const char *name, + const void *value, size_t size, + int flags); + int (*inode_getxattr)(struct dentry *dentry, const char *name); + int (*inode_listxattr)(struct dentry *dentry); + int (*inode_removexattr)(struct dentry *dentry, const char *name); + int (*inode_need_killpriv)(struct dentry *dentry); + int (*inode_killpriv)(struct dentry *dentry); + int (*inode_getsecurity)(struct inode *inode, const char *name, + void **buffer, bool alloc); + int (*inode_setsecurity)(struct inode *inode, const char *name, + const void *value, size_t size, + int flags); + int (*inode_listsecurity)(struct inode *inode, char *buffer, + size_t buffer_size); + void (*inode_getsecid)(struct inode *inode, u32 *secid); + int (*inode_copy_up)(struct dentry *src, struct cred **new); + int (*inode_copy_up_xattr)(const char *name); + + int (*kernfs_init_security)(struct kernfs_node *kn_dir, + struct kernfs_node *kn); + + int (*file_permission)(struct file *file, int mask); + int (*file_alloc_security)(struct file *file); + void (*file_free_security)(struct file *file); + int (*file_ioctl)(struct file *file, unsigned int cmd, + unsigned long arg); + int (*file_ioctl_compat)(struct file *file, unsigned int cmd, + unsigned long arg); + int (*mmap_addr)(unsigned long addr); + int (*mmap_file)(struct file *file, unsigned long reqprot, + unsigned long prot, unsigned long flags); + int (*file_mprotect)(struct vm_area_struct *vma, unsigned long reqprot, + unsigned long prot); + int (*file_lock)(struct file *file, unsigned int cmd); + int (*file_fcntl)(struct file *file, unsigned int cmd, + unsigned long arg); + void (*file_set_fowner)(struct file *file); + int (*file_send_sigiotask)(struct task_struct *tsk, + struct fown_struct *fown, int sig); + int (*file_receive)(struct file *file); + int (*file_open)(struct file *file); + + int (*task_alloc)(struct task_struct *task, unsigned long clone_flags); + void (*task_free)(struct task_struct *task); + int (*cred_alloc_blank)(struct cred *cred, gfp_t gfp); + void (*cred_free)(struct cred *cred); + int (*cred_prepare)(struct cred *new, const struct cred *old, + gfp_t gfp); + void (*cred_transfer)(struct cred *new, const struct cred *old); + void (*cred_getsecid)(const struct cred *c, u32 *secid); + int (*kernel_act_as)(struct cred *new, u32 secid); + int (*kernel_create_files_as)(struct cred *new, struct inode *inode); + int (*kernel_module_request)(char *kmod_name); + int (*kernel_load_data)(enum kernel_load_data_id id); + int (*kernel_read_file)(struct file *file, enum kernel_read_file_id id); + int (*kernel_post_read_file)(struct file *file, char *buf, loff_t size, + enum kernel_read_file_id id); + int (*task_fix_setuid)(struct cred *new, const struct cred *old, + int flags); + int (*task_setpgid)(struct task_struct *p, pid_t pgid); + int (*task_getpgid)(struct task_struct *p); + int (*task_getsid)(struct task_struct *p); + void (*task_getsecid)(struct task_struct *p, u32 *secid); + int (*task_setnice)(struct task_struct *p, int nice); + int (*task_setioprio)(struct task_struct *p, int ioprio); + int (*task_getioprio)(struct task_struct *p); + int (*task_prlimit)(const struct cred *cred, const struct cred *tcred, + unsigned int flags); + int (*task_setrlimit)(struct task_struct *p, unsigned int resource, + struct rlimit *new_rlim); + int (*task_setscheduler)(struct task_struct *p); + int (*task_getscheduler)(struct task_struct *p); + int (*task_movememory)(struct task_struct *p); + int (*task_kill)(struct task_struct *p, struct kernel_siginfo *info, + int sig, const struct cred *cred); + int (*task_prctl)(int option, unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5); + void (*task_to_inode)(struct task_struct *p, struct inode *inode); + + int (*ipc_permission)(struct kern_ipc_perm *ipcp, short flag); + void (*ipc_getsecid)(struct kern_ipc_perm *ipcp, u32 *secid); + + int (*msg_msg_alloc_security)(struct msg_msg *msg); + void (*msg_msg_free_security)(struct msg_msg *msg); + + int (*msg_queue_alloc_security)(struct kern_ipc_perm *perm); + void (*msg_queue_free_security)(struct kern_ipc_perm *perm); + int (*msg_queue_associate)(struct kern_ipc_perm *perm, int msqflg); + int (*msg_queue_msgctl)(struct kern_ipc_perm *perm, int cmd); + int (*msg_queue_msgsnd)(struct kern_ipc_perm *perm, struct msg_msg *msg, + int msqflg); + int (*msg_queue_msgrcv)(struct kern_ipc_perm *perm, struct msg_msg *msg, + struct task_struct *target, long type, + int mode); + + int (*shm_alloc_security)(struct kern_ipc_perm *perm); + void (*shm_free_security)(struct kern_ipc_perm *perm); + int (*shm_associate)(struct kern_ipc_perm *perm, int shmflg); + int (*shm_shmctl)(struct kern_ipc_perm *perm, int cmd); + int (*shm_shmat)(struct kern_ipc_perm *perm, char __user *shmaddr, + int shmflg); + + int (*sem_alloc_security)(struct kern_ipc_perm *perm); + void (*sem_free_security)(struct kern_ipc_perm *perm); + int (*sem_associate)(struct kern_ipc_perm *perm, int semflg); + int (*sem_semctl)(struct kern_ipc_perm *perm, int cmd); + int (*sem_semop)(struct kern_ipc_perm *perm, struct sembuf *sops, + unsigned nsops, int alter); + + int (*netlink_send)(struct sock *sk, struct sk_buff *skb); + + void (*d_instantiate)(struct dentry *dentry, struct inode *inode); + + int (*getprocattr)(struct task_struct *p, char *name, char **value); + int (*setprocattr)(const char *name, void *value, size_t size); + int (*ismaclabel)(const char *name); + int (*secid_to_secctx)(u32 secid, char **secdata, u32 *seclen); + int (*secctx_to_secid)(const char *secdata, u32 seclen, u32 *secid); + void (*release_secctx)(char *secdata, u32 seclen); + + void (*inode_invalidate_secctx)(struct inode *inode); + int (*inode_notifysecctx)(struct inode *inode, void *ctx, u32 ctxlen); + int (*inode_setsecctx)(struct dentry *dentry, void *ctx, u32 ctxlen); + int (*inode_getsecctx)(struct inode *inode, void **ctx, u32 *ctxlen); + +#ifdef CONFIG_SECURITY_NETWORK + int (*unix_stream_connect)(struct sock *sock, struct sock *other, + struct sock *newsk); + int (*unix_may_send)(struct socket *sock, struct socket *other); + + int (*socket_create)(int family, int type, int protocol, int kern); + int (*socket_post_create)(struct socket *sock, int family, int type, + int protocol, int kern); + int (*socket_socketpair)(struct socket *socka, struct socket *sockb); + int (*socket_bind)(struct socket *sock, struct sockaddr *address, + int addrlen); + int (*socket_connect)(struct socket *sock, struct sockaddr *address, + int addrlen); + int (*socket_listen)(struct socket *sock, int backlog); + int (*socket_accept)(struct socket *sock, struct socket *newsock); + int (*socket_sendmsg)(struct socket *sock, struct msghdr *msg, + int size); + int (*socket_recvmsg)(struct socket *sock, struct msghdr *msg, + int size, int flags); + int (*socket_getsockname)(struct socket *sock); + int (*socket_getpeername)(struct socket *sock); + int (*socket_getsockopt)(struct socket *sock, int level, int optname); + int (*socket_setsockopt)(struct socket *sock, int level, int optname); + int (*socket_shutdown)(struct socket *sock, int how); + int (*socket_sock_rcv_skb)(struct sock *sk, struct sk_buff *skb); + int (*socket_getpeersec_stream)(struct socket *sock, + char __user *optval, + int __user *optlen, unsigned len); + int (*socket_getpeersec_dgram)(struct socket *sock, + struct sk_buff *skb, u32 *secid); + int (*sk_alloc_security)(struct sock *sk, int family, gfp_t priority); + void (*sk_free_security)(struct sock *sk); + void (*sk_clone_security)(const struct sock *sk, struct sock *newsk); + void (*sk_getsecid)(struct sock *sk, u32 *secid); + void (*sock_graft)(struct sock *sk, struct socket *parent); + int (*inet_conn_request)(struct sock *sk, struct sk_buff *skb, + struct request_sock *req); + void (*inet_csk_clone)(struct sock *newsk, + const struct request_sock *req); + void (*inet_conn_established)(struct sock *sk, struct sk_buff *skb); + int (*secmark_relabel_packet)(u32 secid); + void (*secmark_refcount_inc)(void); + void (*secmark_refcount_dec)(void); + void (*req_classify_flow)(const struct request_sock *req, + struct flowi *fl); + int (*tun_dev_alloc_security)(void **security); + void (*tun_dev_free_security)(void *security); + int (*tun_dev_create)(void); + int (*tun_dev_attach_queue)(void *security); + int (*tun_dev_attach)(struct sock *sk, void *security); + int (*tun_dev_open)(void *security); + int (*sctp_assoc_request)(struct sctp_endpoint *ep, + struct sk_buff *skb); + int (*sctp_bind_connect)(struct sock *sk, int optname, + struct sockaddr *address, int addrlen); + void (*sctp_sk_clone)(struct sctp_endpoint *ep, struct sock *sk, + struct sock *newsk); +#endif /* CONFIG_SECURITY_NETWORK */ + +#ifdef CONFIG_SECURITY_INFINIBAND + int (*ib_pkey_access)(void *sec, u64 subnet_prefix, u16 pkey); + int (*ib_endport_manage_subnet)(void *sec, const char *dev_name, + u8 port_num); + int (*ib_alloc_security)(void **sec); + void (*ib_free_security)(void *sec); +#endif /* CONFIG_SECURITY_INFINIBAND */ + +#ifdef CONFIG_SECURITY_NETWORK_XFRM + int (*xfrm_policy_alloc_security)(struct xfrm_sec_ctx **ctxp, + struct xfrm_user_sec_ctx *sec_ctx, + gfp_t gfp); + int (*xfrm_policy_clone_security)(struct xfrm_sec_ctx *old_ctx, + struct xfrm_sec_ctx **new_ctx); + void (*xfrm_policy_free_security)(struct xfrm_sec_ctx *ctx); + int (*xfrm_policy_delete_security)(struct xfrm_sec_ctx *ctx); + int (*xfrm_state_alloc)(struct xfrm_state *x, + struct xfrm_user_sec_ctx *sec_ctx); + int (*xfrm_state_alloc_acquire)(struct xfrm_state *x, + struct xfrm_sec_ctx *polsec, + u32 secid); + void (*xfrm_state_free_security)(struct xfrm_state *x); + int (*xfrm_state_delete_security)(struct xfrm_state *x); + int (*xfrm_policy_lookup)(struct xfrm_sec_ctx *ctx, u32 fl_secid, + u8 dir); + int (*xfrm_state_pol_flow_match)(struct xfrm_state *x, + struct xfrm_policy *xp, + const struct flowi *fl); + int (*xfrm_decode_session)(struct sk_buff *skb, u32 *secid, int ckall); +#endif /* CONFIG_SECURITY_NETWORK_XFRM */ + + /* key management security hooks */ +#ifdef CONFIG_KEYS + int (*key_alloc)(struct key *key, const struct cred *cred, + unsigned long flags); + void (*key_free)(struct key *key); + int (*key_permission)(key_ref_t key_ref, const struct cred *cred, + unsigned perm); + int (*key_getsecurity)(struct key *key, char **_buffer); +#endif /* CONFIG_KEYS */ + +#ifdef CONFIG_AUDIT + int (*audit_rule_init)(u32 field, u32 op, char *rulestr, + void **lsmrule); + int (*audit_rule_known)(struct audit_krule *krule); + int (*audit_rule_match)(u32 secid, u32 field, u32 op, void *lsmrule); + void (*audit_rule_free)(void *lsmrule); +#endif /* CONFIG_AUDIT */ + +#ifdef CONFIG_BPF_SYSCALL + int (*bpf)(int cmd, union bpf_attr *attr, + unsigned int size); + int (*bpf_map)(struct bpf_map *map, fmode_t fmode); + int (*bpf_prog)(struct bpf_prog *prog); + int (*bpf_map_alloc_security)(struct bpf_map *map); + void (*bpf_map_free_security)(struct bpf_map *map); + int (*bpf_prog_alloc_security)(struct bpf_prog_aux *aux); + void (*bpf_prog_free_security)(struct bpf_prog_aux *aux); +#endif /* CONFIG_BPF_SYSCALL */ + int (*locked_down)(enum lockdown_reason what); +#ifdef CONFIG_PERF_EVENTS + int (*perf_event_open)(struct perf_event_attr *attr, int type); + int (*perf_event_alloc)(struct perf_event *event); + void (*perf_event_free)(struct perf_event *event); + int (*perf_event_read)(struct perf_event *event); + int (*perf_event_write)(struct perf_event *event); + +#endif }; struct security_hook_heads { - #define LSM_HOOK(RET, DEFAULT, NAME, ...) struct hlist_head NAME; - #include "lsm_hook_defs.h" - #undef LSM_HOOK + struct hlist_head binder_set_context_mgr; + struct hlist_head binder_transaction; + struct hlist_head binder_transfer_binder; + struct hlist_head binder_transfer_file; + struct hlist_head ptrace_access_check; + struct hlist_head ptrace_traceme; + struct hlist_head capget; + struct hlist_head capset; + struct hlist_head capable; + struct hlist_head quotactl; + struct hlist_head quota_on; + struct hlist_head syslog; + struct hlist_head settime; + struct hlist_head vm_enough_memory; + struct hlist_head bprm_set_creds; + struct hlist_head bprm_check_security; + struct hlist_head bprm_committing_creds; + struct hlist_head bprm_committed_creds; + struct hlist_head fs_context_dup; + struct hlist_head fs_context_parse_param; + struct hlist_head sb_alloc_security; + struct hlist_head sb_free_security; + struct hlist_head sb_free_mnt_opts; + struct hlist_head sb_eat_lsm_opts; + struct hlist_head sb_remount; + struct hlist_head sb_kern_mount; + struct hlist_head sb_show_options; + struct hlist_head sb_statfs; + struct hlist_head sb_mount; + struct hlist_head sb_umount; + struct hlist_head sb_pivotroot; + struct hlist_head sb_set_mnt_opts; + struct hlist_head sb_clone_mnt_opts; + struct hlist_head sb_add_mnt_opt; + struct hlist_head move_mount; + struct hlist_head dentry_init_security; + struct hlist_head dentry_create_files_as; +#ifdef CONFIG_SECURITY_PATH + struct hlist_head path_unlink; + struct hlist_head path_mkdir; + struct hlist_head path_rmdir; + struct hlist_head path_mknod; + struct hlist_head path_truncate; + struct hlist_head path_symlink; + struct hlist_head path_link; + struct hlist_head path_rename; + struct hlist_head path_chmod; + struct hlist_head path_chown; + struct hlist_head path_chroot; +#endif + /* Needed for inode based modules as well */ + struct hlist_head path_notify; + struct hlist_head inode_alloc_security; + struct hlist_head inode_free_security; + struct hlist_head inode_init_security; + struct hlist_head inode_init_security_anon; + struct hlist_head inode_create; + struct hlist_head inode_link; + struct hlist_head inode_unlink; + struct hlist_head inode_symlink; + struct hlist_head inode_mkdir; + struct hlist_head inode_rmdir; + struct hlist_head inode_mknod; + struct hlist_head inode_rename; + struct hlist_head inode_readlink; + struct hlist_head inode_follow_link; + struct hlist_head inode_permission; + struct hlist_head inode_setattr; + struct hlist_head inode_getattr; + struct hlist_head inode_setxattr; + struct hlist_head inode_post_setxattr; + struct hlist_head inode_getxattr; + struct hlist_head inode_listxattr; + struct hlist_head inode_removexattr; + struct hlist_head inode_need_killpriv; + struct hlist_head inode_killpriv; + struct hlist_head inode_getsecurity; + struct hlist_head inode_setsecurity; + struct hlist_head inode_listsecurity; + struct hlist_head inode_getsecid; + struct hlist_head inode_copy_up; + struct hlist_head inode_copy_up_xattr; + struct hlist_head kernfs_init_security; + struct hlist_head file_permission; + struct hlist_head file_alloc_security; + struct hlist_head file_free_security; + struct hlist_head file_ioctl; + struct hlist_head file_ioctl_compat; + struct hlist_head mmap_addr; + struct hlist_head mmap_file; + struct hlist_head file_mprotect; + struct hlist_head file_lock; + struct hlist_head file_fcntl; + struct hlist_head file_set_fowner; + struct hlist_head file_send_sigiotask; + struct hlist_head file_receive; + struct hlist_head file_open; + struct hlist_head task_alloc; + struct hlist_head task_free; + struct hlist_head cred_alloc_blank; + struct hlist_head cred_free; + struct hlist_head cred_prepare; + struct hlist_head cred_transfer; + struct hlist_head cred_getsecid; + struct hlist_head kernel_act_as; + struct hlist_head kernel_create_files_as; + struct hlist_head kernel_load_data; + struct hlist_head kernel_read_file; + struct hlist_head kernel_post_read_file; + struct hlist_head kernel_module_request; + struct hlist_head task_fix_setuid; + struct hlist_head task_setpgid; + struct hlist_head task_getpgid; + struct hlist_head task_getsid; + struct hlist_head task_getsecid; + struct hlist_head task_setnice; + struct hlist_head task_setioprio; + struct hlist_head task_getioprio; + struct hlist_head task_prlimit; + struct hlist_head task_setrlimit; + struct hlist_head task_setscheduler; + struct hlist_head task_getscheduler; + struct hlist_head task_movememory; + struct hlist_head task_kill; + struct hlist_head task_prctl; + struct hlist_head task_to_inode; + struct hlist_head ipc_permission; + struct hlist_head ipc_getsecid; + struct hlist_head msg_msg_alloc_security; + struct hlist_head msg_msg_free_security; + struct hlist_head msg_queue_alloc_security; + struct hlist_head msg_queue_free_security; + struct hlist_head msg_queue_associate; + struct hlist_head msg_queue_msgctl; + struct hlist_head msg_queue_msgsnd; + struct hlist_head msg_queue_msgrcv; + struct hlist_head shm_alloc_security; + struct hlist_head shm_free_security; + struct hlist_head shm_associate; + struct hlist_head shm_shmctl; + struct hlist_head shm_shmat; + struct hlist_head sem_alloc_security; + struct hlist_head sem_free_security; + struct hlist_head sem_associate; + struct hlist_head sem_semctl; + struct hlist_head sem_semop; + struct hlist_head netlink_send; + struct hlist_head d_instantiate; + struct hlist_head getprocattr; + struct hlist_head setprocattr; + struct hlist_head ismaclabel; + struct hlist_head secid_to_secctx; + struct hlist_head secctx_to_secid; + struct hlist_head release_secctx; + struct hlist_head inode_invalidate_secctx; + struct hlist_head inode_notifysecctx; + struct hlist_head inode_setsecctx; + struct hlist_head inode_getsecctx; +#ifdef CONFIG_SECURITY_NETWORK + struct hlist_head unix_stream_connect; + struct hlist_head unix_may_send; + struct hlist_head socket_create; + struct hlist_head socket_post_create; + struct hlist_head socket_socketpair; + struct hlist_head socket_bind; + struct hlist_head socket_connect; + struct hlist_head socket_listen; + struct hlist_head socket_accept; + struct hlist_head socket_sendmsg; + struct hlist_head socket_recvmsg; + struct hlist_head socket_getsockname; + struct hlist_head socket_getpeername; + struct hlist_head socket_getsockopt; + struct hlist_head socket_setsockopt; + struct hlist_head socket_shutdown; + struct hlist_head socket_sock_rcv_skb; + struct hlist_head socket_getpeersec_stream; + struct hlist_head socket_getpeersec_dgram; + struct hlist_head sk_alloc_security; + struct hlist_head sk_free_security; + struct hlist_head sk_clone_security; + struct hlist_head sk_getsecid; + struct hlist_head sock_graft; + struct hlist_head inet_conn_request; + struct hlist_head inet_csk_clone; + struct hlist_head inet_conn_established; + struct hlist_head secmark_relabel_packet; + struct hlist_head secmark_refcount_inc; + struct hlist_head secmark_refcount_dec; + struct hlist_head req_classify_flow; + struct hlist_head tun_dev_alloc_security; + struct hlist_head tun_dev_free_security; + struct hlist_head tun_dev_create; + struct hlist_head tun_dev_attach_queue; + struct hlist_head tun_dev_attach; + struct hlist_head tun_dev_open; + struct hlist_head sctp_assoc_request; + struct hlist_head sctp_bind_connect; + struct hlist_head sctp_sk_clone; +#endif /* CONFIG_SECURITY_NETWORK */ +#ifdef CONFIG_SECURITY_INFINIBAND + struct hlist_head ib_pkey_access; + struct hlist_head ib_endport_manage_subnet; + struct hlist_head ib_alloc_security; + struct hlist_head ib_free_security; +#endif /* CONFIG_SECURITY_INFINIBAND */ +#ifdef CONFIG_SECURITY_NETWORK_XFRM + struct hlist_head xfrm_policy_alloc_security; + struct hlist_head xfrm_policy_clone_security; + struct hlist_head xfrm_policy_free_security; + struct hlist_head xfrm_policy_delete_security; + struct hlist_head xfrm_state_alloc; + struct hlist_head xfrm_state_alloc_acquire; + struct hlist_head xfrm_state_free_security; + struct hlist_head xfrm_state_delete_security; + struct hlist_head xfrm_policy_lookup; + struct hlist_head xfrm_state_pol_flow_match; + struct hlist_head xfrm_decode_session; +#endif /* CONFIG_SECURITY_NETWORK_XFRM */ +#ifdef CONFIG_KEYS + struct hlist_head key_alloc; + struct hlist_head key_free; + struct hlist_head key_permission; + struct hlist_head key_getsecurity; +#endif /* CONFIG_KEYS */ +#ifdef CONFIG_AUDIT + struct hlist_head audit_rule_init; + struct hlist_head audit_rule_known; + struct hlist_head audit_rule_match; + struct hlist_head audit_rule_free; +#endif /* CONFIG_AUDIT */ +#ifdef CONFIG_BPF_SYSCALL + struct hlist_head bpf; + struct hlist_head bpf_map; + struct hlist_head bpf_prog; + struct hlist_head bpf_map_alloc_security; + struct hlist_head bpf_map_free_security; + struct hlist_head bpf_prog_alloc_security; + struct hlist_head bpf_prog_free_security; +#endif /* CONFIG_BPF_SYSCALL */ + struct hlist_head locked_down; +#ifdef CONFIG_PERF_EVENTS + struct hlist_head perf_event_open; + struct hlist_head perf_event_alloc; + struct hlist_head perf_event_free; + struct hlist_head perf_event_read; + struct hlist_head perf_event_write; +#endif } __randomize_layout; /* @@ -1505,12 +2122,6 @@ struct lsm_blob_sizes { int lbs_task; }; -/* - * LSM_RET_VOID is used as the default value in LSM_HOOK definitions for void - * LSM hooks (in include/linux/lsm_hook_defs.h). - */ -#define LSM_RET_VOID ((void) 0) - /* * Initializing a security_hook_list structure takes * up a lot of space in a source file. This macro takes diff --git a/include/linux/mm.h b/include/linux/mm.h index 87f7c6b8bd9f..883d81d50d50 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -218,10 +218,10 @@ extern int sysctl_overcommit_memory; extern int sysctl_overcommit_ratio; extern unsigned long sysctl_overcommit_kbytes; -int overcommit_ratio_handler(struct ctl_table *, int, void *, size_t *, - loff_t *); -int overcommit_kbytes_handler(struct ctl_table *, int, void *, size_t *, - loff_t *); +extern int overcommit_ratio_handler(struct ctl_table *, int, void __user *, + size_t *, loff_t *); +extern int overcommit_kbytes_handler(struct ctl_table *, int, void __user *, + size_t *, loff_t *); #define nth_page(page,n) pfn_to_page(page_to_pfn((page)) + (n)) @@ -303,7 +303,7 @@ extern unsigned int kobjsize(const void *objp); #define VM_MIXEDMAP 0x10000000 /* Can contain "struct page" and pure PFN pages */ #define VM_HUGEPAGE 0x20000000 /* MADV_HUGEPAGE marked this vma */ #define VM_NOHUGEPAGE 0x40000000 /* MADV_NOHUGEPAGE marked this vma */ -#define VM_MERGEABLE BIT(31) /* KSM may merge identical pages */ +#define VM_MERGEABLE 0x80000000 /* KSM may merge identical pages */ #ifdef CONFIG_ARCH_USES_HIGH_VMA_FLAGS #define VM_HIGH_ARCH_BIT_0 32 /* bit only usable on 64-bit architectures */ @@ -2896,8 +2896,8 @@ extern bool process_shares_mm(struct task_struct *p, struct mm_struct *mm); #ifdef CONFIG_SYSCTL extern int sysctl_drop_caches; -int drop_caches_sysctl_handler(struct ctl_table *, int, void *, size_t *, - loff_t *); +int drop_caches_sysctl_handler(struct ctl_table *, int, + void __user *, size_t *, loff_t *); #endif void drop_slab(void); diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h index eb6bc4479106..3bae2136989a 100644 --- a/include/linux/mmzone.h +++ b/include/linux/mmzone.h @@ -983,26 +983,26 @@ static inline int is_highmem(struct zone *zone) /* These two functions are used to setup the per zone pages min values */ struct ctl_table; int kswapd_threads_sysctl_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, + void __user *buffer, size_t *length, loff_t *pos); int min_free_kbytes_sysctl_handler(struct ctl_table *, int, - void *, size_t *, loff_t *); + void __user *, size_t *, loff_t *); int watermark_boost_factor_sysctl_handler(struct ctl_table *, int, - void *, size_t *, loff_t *); + void __user *, size_t *, loff_t *); int watermark_scale_factor_sysctl_handler(struct ctl_table *, int, - void *, size_t *, loff_t *); + void __user *, size_t *, loff_t *); extern int sysctl_lowmem_reserve_ratio[MAX_NR_ZONES]; -int lowmem_reserve_ratio_sysctl_handler(struct ctl_table *, int, void *, - size_t *, loff_t *); +int lowmem_reserve_ratio_sysctl_handler(struct ctl_table *, int, + void __user *, size_t *, loff_t *); int percpu_pagelist_fraction_sysctl_handler(struct ctl_table *, int, - void *, size_t *, loff_t *); + void __user *, size_t *, loff_t *); int sysctl_min_unmapped_ratio_sysctl_handler(struct ctl_table *, int, - void *, size_t *, loff_t *); + void __user *, size_t *, loff_t *); int sysctl_min_slab_ratio_sysctl_handler(struct ctl_table *, int, - void *, size_t *, loff_t *); + void __user *, size_t *, loff_t *); -int numa_zonelist_order_handler(struct ctl_table *, int, - void *, size_t *, loff_t *); +extern int numa_zonelist_order_handler(struct ctl_table *, int, + void __user *, size_t *, loff_t *); extern char numa_zonelist_order[]; #define NUMA_ZONELIST_ORDER_LEN 16 diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index eb40c638684f..7d048d775eff 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -54,7 +54,6 @@ struct netpoll_info; struct device; struct phy_device; struct dsa_port; -struct ip_tunnel_parm; struct macsec_context; struct macsec_ops; @@ -66,8 +65,6 @@ struct wpan_dev; struct mpls_dev; /* UDP Tunnel offloads */ struct udp_tunnel_info; -struct udp_tunnel_nic_info; -struct udp_tunnel_nic; struct bpf_prog; struct xdp_buff; @@ -905,20 +902,6 @@ enum bpf_netdev_command { struct bpf_prog_offload_ops; struct netlink_ext_ack; struct xdp_umem; -struct xdp_dev_bulk_queue; -struct bpf_xdp_link; - -enum bpf_xdp_mode { - XDP_MODE_SKB = 0, - XDP_MODE_DRV = 1, - XDP_MODE_HW = 2, - __MAX_XDP_MODE -}; - -struct bpf_xdp_entity { - struct bpf_prog *prog; - struct bpf_xdp_link *link; -}; struct netdev_bpf { enum bpf_netdev_command command; @@ -976,11 +959,6 @@ struct devlink; struct tlsdev_ops; -struct netdev_net_notifier { - struct list_head list; - struct notifier_block *nb; -}; - /* * This structure defines the management hooks for network devices. * The following hooks can be defined; unless noted otherwise, they are @@ -1298,12 +1276,6 @@ struct netdev_net_notifier { * Get devlink port instance associated with a given netdev. * Called with a reference on the netdevice and devlink locks only, * rtnl_lock is not held. - * int (*ndo_tunnel_ctl)(struct net_device *dev, struct ip_tunnel_parm *p, - * int cmd); - * Add, change, delete or get information on an IPv4 tunnel. - * struct net_device *(*ndo_get_peer_dev)(struct net_device *dev); - * If a device is paired with a peer device, return the peer instance. - * The caller must be under RCU read context. */ struct net_device_ops { int (*ndo_init)(struct net_device *dev); @@ -1501,9 +1473,6 @@ struct net_device_ops { int (*ndo_xsk_wakeup)(struct net_device *dev, u32 queue_id, u32 flags); struct devlink_port * (*ndo_get_devlink_port)(struct net_device *dev); - int (*ndo_tunnel_ctl)(struct net_device *dev, - struct ip_tunnel_parm *p, int cmd); - struct net_device * (*ndo_get_peer_dev)(struct net_device *dev); ANDROID_KABI_RESERVE(1); ANDROID_KABI_RESERVE(2); @@ -1846,16 +1815,8 @@ enum netdev_priv_flags { * * @wol_enabled: Wake-on-LAN is enabled * - * @net_notifier_list: List of per-net netdev notifier block - * that follow this device when it is moved - * to another network namespace. - * * @macsec_ops: MACsec offloading ops * - * @udp_tunnel_nic_info: static structure describing the UDP tunnel - * offload capabilities of the device - * @udp_tunnel_nic: UDP tunnel offload state - * * FIXME: cleanup struct net_device such that network protocol info * moves out. */ @@ -2048,10 +2009,12 @@ struct net_device { unsigned int num_tx_queues; unsigned int real_num_tx_queues; struct Qdisc __rcu *qdisc; +#ifdef CONFIG_NET_SCHED + DECLARE_HASHTABLE (qdisc_hash, 4); +#endif unsigned int tx_queue_len; spinlock_t tx_global_lock; - - struct xdp_dev_bulk_queue __percpu *xdp_bulkq; + int watchdog_timeo; #ifdef CONFIG_XPS struct xps_dev_maps __rcu *xps_cpus_map; @@ -2061,15 +2024,11 @@ struct net_device { struct mini_Qdisc __rcu *miniq_egress; #endif -#ifdef CONFIG_NET_SCHED - DECLARE_HASHTABLE (qdisc_hash, 4); -#endif /* These may be needed for future network-power-down code. */ struct timer_list watchdog_timer; - int watchdog_timeo; - struct list_head todo_list; int __percpu *pcpu_refcnt; + struct list_head todo_list; struct list_head link_watch_list; @@ -2146,17 +2105,10 @@ struct net_device { bool proto_down; unsigned wol_enabled:1; - struct list_head net_notifier_list; - #if IS_ENABLED(CONFIG_MACSEC) /* MACsec management functions */ const struct macsec_ops *macsec_ops; #endif - const struct udp_tunnel_nic_info *udp_tunnel_nic_info; - struct udp_tunnel_nic *udp_tunnel_nic; - - /* protected by rtnl_lock */ - struct bpf_xdp_entity xdp_state[__MAX_XDP_MODE]; ANDROID_KABI_RESERVE(1); ANDROID_KABI_RESERVE(2); @@ -2512,18 +2464,6 @@ struct pcpu_lstats { struct u64_stats_sync syncp; } __aligned(2 * sizeof(u64)); -void dev_lstats_read(struct net_device *dev, u64 *packets, u64 *bytes); - -static inline void dev_lstats_add(struct net_device *dev, unsigned int len) -{ - struct pcpu_lstats *lstats = this_cpu_ptr(dev->lstats); - - u64_stats_update_begin(&lstats->syncp); - lstats->bytes += len; - lstats->packets++; - u64_stats_update_end(&lstats->syncp); -} - #define __netdev_alloc_pcpu_stats(type, gfp) \ ({ \ typeof(type) __percpu *pcpu_stats = alloc_percpu_gfp(type, gfp);\ @@ -2614,22 +2554,11 @@ enum netdev_cmd { NETDEV_CVLAN_FILTER_DROP_INFO, NETDEV_SVLAN_FILTER_PUSH_INFO, NETDEV_SVLAN_FILTER_DROP_INFO, - NETDEV_BR_JOIN, - NETDEV_BR_LEAVE, }; const char *netdev_cmd_to_name(enum netdev_cmd cmd); int register_netdevice_notifier(struct notifier_block *nb); int unregister_netdevice_notifier(struct notifier_block *nb); -int register_netdevice_notifier_net(struct net *net, struct notifier_block *nb); -int unregister_netdevice_notifier_net(struct net *net, - struct notifier_block *nb); -int register_netdevice_notifier_dev_net(struct net_device *dev, - struct notifier_block *nb, - struct netdev_net_notifier *nn); -int unregister_netdevice_notifier_dev_net(struct net_device *dev, - struct notifier_block *nb, - struct netdev_net_notifier *nn); struct netdev_notifier_info { struct net_device *dev; @@ -2700,9 +2629,6 @@ extern rwlock_t dev_base_lock; /* Device list lock */ list_for_each_entry_safe(d, n, &(net)->dev_base_head, dev_list) #define for_each_netdev_continue(net, d) \ list_for_each_entry_continue(d, &(net)->dev_base_head, dev_list) -#define for_each_netdev_continue_reverse(net, d) \ - list_for_each_entry_continue_reverse(d, &(net)->dev_base_head, \ - dev_list) #define for_each_netdev_continue_rcu(net, d) \ list_for_each_entry_continue_rcu(d, &(net)->dev_base_head, dev_list) #define for_each_netdev_in_bond_rcu(bond, slave) \ @@ -3842,10 +3768,9 @@ struct sk_buff *dev_hard_start_xmit(struct sk_buff *skb, struct net_device *dev, typedef int (*bpf_op_t)(struct net_device *dev, struct netdev_bpf *bpf); int dev_change_xdp_fd(struct net_device *dev, struct netlink_ext_ack *extack, - int fd, int expected_fd, u32 flags); -int bpf_xdp_link_attach(const union bpf_attr *attr, struct bpf_prog *prog); -u32 dev_xdp_prog_id(struct net_device *dev, enum bpf_xdp_mode mode); - + int fd, u32 flags); +u32 __dev_xdp_query(struct net_device *dev, bpf_op_t xdp_op, + enum bpf_netdev_command cmd); int xdp_umem_query(struct net_device *dev, u16 queue_id); int __dev_forward_skb(struct net_device *dev, struct sk_buff *skb); @@ -4784,15 +4709,6 @@ static inline bool netif_is_l3_slave(const struct net_device *dev) return dev->priv_flags & IFF_L3MDEV_SLAVE; } -static inline int dev_sdif(const struct net_device *dev) -{ -#ifdef CONFIG_NET_L3_MASTER_DEV - if (netif_is_l3_slave(dev)) - return dev->ifindex; -#endif - return 0; -} - static inline bool netif_is_bridge_master(const struct net_device *dev) { return dev->priv_flags & IFF_EBRIDGE; diff --git a/include/linux/nmi.h b/include/linux/nmi.h index a86d0cf709bb..1fb7f8c5eb8f 100644 --- a/include/linux/nmi.h +++ b/include/linux/nmi.h @@ -225,11 +225,16 @@ static inline void watchdog_update_hrtimer_threshold(u64 period) { } #endif struct ctl_table; -int proc_watchdog(struct ctl_table *, int, void *, size_t *, loff_t *); -int proc_nmi_watchdog(struct ctl_table *, int , void *, size_t *, loff_t *); -int proc_soft_watchdog(struct ctl_table *, int , void *, size_t *, loff_t *); -int proc_watchdog_thresh(struct ctl_table *, int , void *, size_t *, loff_t *); -int proc_watchdog_cpumask(struct ctl_table *, int, void *, size_t *, loff_t *); +extern int proc_watchdog(struct ctl_table *, int , + void __user *, size_t *, loff_t *); +extern int proc_nmi_watchdog(struct ctl_table *, int , + void __user *, size_t *, loff_t *); +extern int proc_soft_watchdog(struct ctl_table *, int , + void __user *, size_t *, loff_t *); +extern int proc_watchdog_thresh(struct ctl_table *, int , + void __user *, size_t *, loff_t *); +extern int proc_watchdog_cpumask(struct ctl_table *, int, + void __user *, size_t *, loff_t *); #ifdef CONFIG_HAVE_ACPI_APEI_NMI #include diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index a63486d6a710..bb9d6c1d2a6d 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -1233,8 +1233,6 @@ get_perf_callchain(struct pt_regs *regs, u32 init_nr, bool kernel, bool user, extern struct perf_callchain_entry *perf_callchain(struct perf_event *event, struct pt_regs *regs); extern int get_callchain_buffers(int max_stack); extern void put_callchain_buffers(void); -extern struct perf_callchain_entry *get_callchain_entry(int *rctx); -extern void put_callchain_entry(int rctx); extern int sysctl_perf_event_max_stack; extern int sysctl_perf_event_max_contexts_per_stack; @@ -1271,12 +1269,15 @@ extern int sysctl_perf_cpu_time_max_percent; extern void perf_sample_event_took(u64 sample_len_ns); -int perf_proc_update_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); -int perf_cpu_time_max_percent_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); +extern int perf_proc_update_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); +extern int perf_cpu_time_max_percent_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); + int perf_event_max_stack_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); /* Access to perf_event_open(2) syscall. */ #define PERF_SECURITY_OPEN 0 diff --git a/include/linux/pid.h b/include/linux/pid.h index 064847e90cf0..8c836713d6c4 100644 --- a/include/linux/pid.h +++ b/include/linux/pid.h @@ -126,8 +126,7 @@ extern struct pid *find_vpid(int nr); extern struct pid *find_get_pid(int nr); extern struct pid *find_ge_pid(int nr, struct pid_namespace *); -extern struct pid *alloc_pid(struct pid_namespace *ns, pid_t *set_tid, - size_t set_tid_size); +extern struct pid *alloc_pid(struct pid_namespace *ns); extern void free_pid(struct pid *pid); extern void disable_pid_allocation(struct pid_namespace *ns); diff --git a/include/linux/pid_namespace.h b/include/linux/pid_namespace.h index 2ed6af88794b..49538b172483 100644 --- a/include/linux/pid_namespace.h +++ b/include/linux/pid_namespace.h @@ -12,8 +12,6 @@ #include #include -/* MAX_PID_NS_LEVEL is needed for limiting size of 'struct pid' */ -#define MAX_PID_NS_LEVEL 32 struct fs_pin; diff --git a/include/linux/printk.h b/include/linux/printk.h index e1f9796c4e64..f11f64f6401e 100644 --- a/include/linux/printk.h +++ b/include/linux/printk.h @@ -195,7 +195,7 @@ extern int printk_delay_msec; extern int dmesg_restrict; extern int -devkmsg_sysctl_set_loglvl(struct ctl_table *table, int write, void *buf, +devkmsg_sysctl_set_loglvl(struct ctl_table *table, int write, void __user *buf, size_t *lenp, loff_t *ppos); extern void wake_up_klogd(void); diff --git a/include/linux/proc_fs.h b/include/linux/proc_fs.h index fed6b1fd585d..b8d41d0e7b46 100644 --- a/include/linux/proc_fs.h +++ b/include/linux/proc_fs.h @@ -76,10 +76,6 @@ struct proc_dir_entry *proc_create_net_single_write(const char *name, umode_t mo void *data); extern struct pid *tgid_pidfd_to_pid(const struct file *file); -struct bpf_iter_aux_info; -extern int bpf_iter_init_seq_net(void *priv_data, struct bpf_iter_aux_info *aux); -extern void bpf_iter_fini_seq_net(void *priv_data); - #ifdef CONFIG_PROC_PID_ARCH_STATUS /* * The architecture which selects CONFIG_PROC_PID_ARCH_STATUS must diff --git a/include/linux/proc_ns.h b/include/linux/proc_ns.h index 79499c110e60..d31cb6215905 100644 --- a/include/linux/proc_ns.h +++ b/include/linux/proc_ns.h @@ -76,14 +76,12 @@ static inline int ns_alloc_inum(struct ns_common *ns) extern struct file *proc_ns_fget(int fd); #define get_proc_ns(inode) ((struct ns_common *)(inode)->i_private) -extern int ns_get_path(struct path *path, struct task_struct *task, +extern void *ns_get_path(struct path *path, struct task_struct *task, const struct proc_ns_operations *ns_ops); typedef struct ns_common *ns_get_path_helper_t(void *); -extern int ns_get_path_cb(struct path *path, ns_get_path_helper_t ns_get_cb, +extern void *ns_get_path_cb(struct path *path, ns_get_path_helper_t ns_get_cb, void *private_data); -extern bool ns_match(const struct ns_common *ns, dev_t dev, ino_t ino); - extern int ns_get_name(char *buf, size_t size, struct task_struct *task, const struct proc_ns_operations *ns_ops); extern void nsfs_init(void); diff --git a/include/linux/random.h b/include/linux/random.h index 7e742ef51a83..8ed2e245d51e 100644 --- a/include/linux/random.h +++ b/include/linux/random.h @@ -64,8 +64,7 @@ static inline unsigned long get_random_canary(void) return get_random_long() & CANARY_MASK; } -void __init random_init_early(const char *command_line); -void __init random_init(void); +int __init random_init(const char *command_line); bool rng_is_initialized(void); int wait_for_random_bytes(void); int register_random_ready_notifier(struct notifier_block *nb); diff --git a/include/linux/rculist.h b/include/linux/rculist.h index 0122240e205d..4158b7212936 100644 --- a/include/linux/rculist.h +++ b/include/linux/rculist.h @@ -173,7 +173,7 @@ static inline void hlist_del_init_rcu(struct hlist_node *n) { if (!hlist_unhashed(n)) { __hlist_del(n); - WRITE_ONCE(n->pprev, NULL); + n->pprev = NULL; } } @@ -473,7 +473,7 @@ static inline void list_splice_tail_init_rcu(struct list_head *list, static inline void hlist_del_rcu(struct hlist_node *n) { __hlist_del(n); - WRITE_ONCE(n->pprev, LIST_POISON2); + n->pprev = LIST_POISON2; } /** @@ -489,11 +489,11 @@ static inline void hlist_replace_rcu(struct hlist_node *old, struct hlist_node *next = old->next; new->next = next; - WRITE_ONCE(new->pprev, old->pprev); + new->pprev = old->pprev; rcu_assign_pointer(*(struct hlist_node __rcu **)new->pprev, new); if (next) - WRITE_ONCE(new->next->pprev, &new->next); - WRITE_ONCE(old->pprev, LIST_POISON2); + new->next->pprev = &new->next; + old->pprev = LIST_POISON2; } /* @@ -528,10 +528,10 @@ static inline void hlist_add_head_rcu(struct hlist_node *n, struct hlist_node *first = h->first; n->next = first; - WRITE_ONCE(n->pprev, &h->first); + n->pprev = &h->first; rcu_assign_pointer(hlist_first_rcu(h), n); if (first) - WRITE_ONCE(first->pprev, &n->next); + first->pprev = &n->next; } /** @@ -564,7 +564,7 @@ static inline void hlist_add_tail_rcu(struct hlist_node *n, if (last) { n->next = last->next; - WRITE_ONCE(n->pprev, &last->next); + n->pprev = &last->next; rcu_assign_pointer(hlist_next_rcu(last), n); } else { hlist_add_head_rcu(n, h); @@ -592,10 +592,10 @@ static inline void hlist_add_tail_rcu(struct hlist_node *n, static inline void hlist_add_before_rcu(struct hlist_node *n, struct hlist_node *next) { - WRITE_ONCE(n->pprev, next->pprev); + n->pprev = next->pprev; n->next = next; rcu_assign_pointer(hlist_pprev_rcu(n), n); - WRITE_ONCE(next->pprev, &n->next); + next->pprev = &n->next; } /** @@ -620,10 +620,10 @@ static inline void hlist_add_behind_rcu(struct hlist_node *n, struct hlist_node *prev) { n->next = prev->next; - WRITE_ONCE(n->pprev, &prev->next); + n->pprev = &prev->next; rcu_assign_pointer(hlist_next_rcu(prev), n); if (n->next) - WRITE_ONCE(n->next->pprev, &n->next); + n->next->pprev = &n->next; } #define __hlist_for_each_rcu(pos, head) \ diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h index eff357328c3c..bc4b5c905a60 100644 --- a/include/linux/rcupdate.h +++ b/include/linux/rcupdate.h @@ -37,7 +37,6 @@ /* Exported common interfaces */ void call_rcu(struct rcu_head *head, rcu_callback_t func); void rcu_barrier_tasks(void); -void rcu_barrier_tasks_rude(void); void synchronize_rcu(void); #ifdef CONFIG_PREEMPT_RCU @@ -132,7 +131,7 @@ static inline void rcu_nocb_flush_deferred_wakeup(void) { } * Note a quasi-voluntary context switch for RCU-tasks's benefit. * This is a macro rather than an inline function to avoid #include hell. */ -#ifdef CONFIG_TASKS_RCU_GENERIC +#ifdef CONFIG_TASKS_RCU #define rcu_tasks_qs(t) \ do { \ if (READ_ONCE((t)->rcu_tasks_holdout)) \ @@ -141,18 +140,16 @@ static inline void rcu_nocb_flush_deferred_wakeup(void) { } #define rcu_note_voluntary_context_switch(t) rcu_tasks_qs(t) void call_rcu_tasks(struct rcu_head *head, rcu_callback_t func); void synchronize_rcu_tasks(void); -void call_rcu_tasks_rude(struct rcu_head *head, rcu_callback_t func); -void synchronize_rcu_tasks_rude(void); void exit_tasks_rcu_start(void); void exit_tasks_rcu_finish(void); -#else /* #ifdef CONFIG_TASKS_RCU_GENERIC */ +#else /* #ifdef CONFIG_TASKS_RCU */ #define rcu_tasks_qs(t) do { } while (0) #define rcu_note_voluntary_context_switch(t) do { } while (0) #define call_rcu_tasks call_rcu #define synchronize_rcu_tasks synchronize_rcu static inline void exit_tasks_rcu_start(void) { } static inline void exit_tasks_rcu_finish(void) { } -#endif /* #else #ifdef CONFIG_TASKS_RCU_GENERIC */ +#endif /* #else #ifdef CONFIG_TASKS_RCU */ /** * cond_resched_tasks_rcu_qs - Report potential quiescent states to RCU diff --git a/include/linux/rcupdate_trace.h b/include/linux/rcupdate_trace.h deleted file mode 100644 index ed97e10817bd..000000000000 --- a/include/linux/rcupdate_trace.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Read-Copy Update mechanism for mutual exclusion, adapted for tracing. - * - * Copyright (C) 2020 Paul E. McKenney. - */ - -#ifndef __LINUX_RCUPDATE_TRACE_H -#define __LINUX_RCUPDATE_TRACE_H - -#include -#include - -#ifdef CONFIG_DEBUG_LOCK_ALLOC - -extern struct lockdep_map rcu_trace_lock_map; - -static inline int rcu_read_lock_trace_held(void) -{ - return lock_is_held(&rcu_trace_lock_map); -} - -#else /* #ifdef CONFIG_DEBUG_LOCK_ALLOC */ - -static inline int rcu_read_lock_trace_held(void) -{ - return 1; -} - -#endif /* #else #ifdef CONFIG_DEBUG_LOCK_ALLOC */ - -#ifdef CONFIG_TASKS_TRACE_RCU - -void rcu_read_unlock_trace_special(struct task_struct *t); - -/** - * rcu_read_lock_trace - mark beginning of RCU-trace read-side critical section - * - * When synchronize_rcu_trace() is invoked by one task, then that task - * is guaranteed to block until all other tasks exit their read-side - * critical sections. Similarly, if call_rcu_trace() is invoked on one - * task while other tasks are within RCU read-side critical sections, - * invocation of the corresponding RCU callback is deferred until after - * the all the other tasks exit their critical sections. - * - * For more details, please see the documentation for rcu_read_lock(). - */ -static inline void rcu_read_lock_trace(void) -{ - struct task_struct *t = current; - - WRITE_ONCE(t->trc_reader_nesting, READ_ONCE(t->trc_reader_nesting) + 1); - rcu_lock_acquire(&rcu_trace_lock_map); -} - -/** - * rcu_read_unlock_trace - mark end of RCU-trace read-side critical section - * - * Pairs with a preceding call to rcu_read_lock_trace(), and nesting is - * allowed. Invoking a rcu_read_unlock_trace() when there is no matching - * rcu_read_lock_trace() is verboten, and will result in lockdep complaints. - * - * For more details, please see the documentation for rcu_read_unlock(). - */ -static inline void rcu_read_unlock_trace(void) -{ - int nesting; - struct task_struct *t = current; - - rcu_lock_release(&rcu_trace_lock_map); - nesting = READ_ONCE(t->trc_reader_nesting) - 1; - WRITE_ONCE(t->trc_reader_nesting, nesting); - if (likely(!READ_ONCE(t->trc_reader_need_end)) || nesting) - return; // We assume shallow reader nesting. - rcu_read_unlock_trace_special(t); -} - -void call_rcu_tasks_trace(struct rcu_head *rhp, rcu_callback_t func); -void synchronize_rcu_tasks_trace(void); -void rcu_barrier_tasks_trace(void); - -#endif /* #ifdef CONFIG_TASKS_TRACE_RCU */ - -#endif /* __LINUX_RCUPDATE_TRACE_H */ diff --git a/include/linux/sched.h b/include/linux/sched.h index eb066485d67b..ee54107144dd 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -898,14 +898,6 @@ struct task_struct { struct list_head rcu_tasks_holdout_list; #endif /* #ifdef CONFIG_TASKS_RCU */ -#ifdef CONFIG_TASKS_TRACE_RCU - int trc_reader_nesting; - int trc_ipi_to_cpu; - bool trc_reader_need_end; - bool trc_reader_checked; - struct list_head trc_holdout_list; -#endif /* #ifdef CONFIG_TASKS_TRACE_RCU */ - struct sched_info sched_info; struct list_head tasks; @@ -2187,6 +2179,14 @@ static inline void rseq_execve(struct task_struct *t) #endif +void __exit_umh(struct task_struct *tsk); + +static inline void exit_umh(struct task_struct *tsk) +{ + if (unlikely(tsk->flags & PF_UMH)) + __exit_umh(tsk); +} + #ifdef CONFIG_DEBUG_RSEQ void rseq_syscall(struct pt_regs *regs); diff --git a/include/linux/sched/signal.h b/include/linux/sched/signal.h index df80d15b888e..797bbafb95c0 100644 --- a/include/linux/sched/signal.h +++ b/include/linux/sched/signal.h @@ -691,8 +691,6 @@ static inline int thread_group_empty(struct task_struct *p) extern struct sighand_struct *__lock_task_sighand(struct task_struct *task, unsigned long *flags); -extern bool thread_group_exited(struct pid *pid); - static inline struct sighand_struct *lock_task_sighand(struct task_struct *task, unsigned long *flags) { diff --git a/include/linux/sched/sysctl.h b/include/linux/sched/sysctl.h index e3d1029bdbaf..b6fdfd97a8f3 100644 --- a/include/linux/sched/sysctl.h +++ b/include/linux/sched/sysctl.h @@ -14,7 +14,7 @@ extern unsigned long sysctl_hung_task_check_interval_secs; extern int sysctl_hung_task_warnings; extern int sysctl_hung_task_selective_monitoring; extern int proc_dohung_task_timeout_secs(struct ctl_table *table, int write, - void *buffer, + void __user *buffer, size_t *lenp, loff_t *ppos); #else /* Avoid need for ifdefs elsewhere in the code */ @@ -113,7 +113,8 @@ extern __read_mostly unsigned int sysctl_sched_migration_cost; extern __read_mostly unsigned int sysctl_sched_nr_migrate; int sched_proc_update_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos); + void __user *buffer, size_t *length, + loff_t *ppos); #endif /* @@ -141,21 +142,33 @@ extern unsigned int sysctl_sched_autogroup_enabled; extern int sysctl_sched_rr_timeslice; extern int sched_rr_timeslice; -int sched_rr_handler(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos); -int sched_rt_handler(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos); -int sysctl_sched_uclamp_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); -int sysctl_numa_balancing(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos); -int sysctl_schedstats(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos); +extern int sched_rr_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); + +extern int sched_rt_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); + +#ifdef CONFIG_UCLAMP_TASK +extern int sysctl_sched_uclamp_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); +#endif + +extern int sysctl_numa_balancing(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); + +extern int sysctl_schedstats(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); #if defined(CONFIG_ENERGY_MODEL) && defined(CONFIG_CPU_FREQ_GOV_SCHEDUTIL) extern unsigned int sysctl_sched_energy_aware; -int sched_energy_aware_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); +extern int sched_energy_aware_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); #endif #define LIB_PATH_LENGTH 512 diff --git a/include/linux/sched/task.h b/include/linux/sched/task.h index b53ee6d7111d..e3c20a4f81f5 100644 --- a/include/linux/sched/task.h +++ b/include/linux/sched/task.h @@ -26,9 +26,6 @@ struct kernel_clone_args { unsigned long stack; unsigned long stack_size; unsigned long tls; - pid_t *set_tid; - /* Number of elements in *set_tid */ - size_t set_tid_size; }; /* diff --git a/include/linux/seccomp.h b/include/linux/seccomp.h index a6f90d9cea47..84868d37b35d 100644 --- a/include/linux/seccomp.h +++ b/include/linux/seccomp.h @@ -12,7 +12,6 @@ #ifdef CONFIG_SECCOMP #include -#include #include struct seccomp_filter; @@ -29,7 +28,6 @@ struct seccomp_filter; */ struct seccomp { int mode; - atomic_t filter_count; struct seccomp_filter *filter; }; @@ -83,10 +81,10 @@ static inline int seccomp_mode(struct seccomp *s) #endif /* CONFIG_SECCOMP */ #ifdef CONFIG_SECCOMP_FILTER -extern void seccomp_filter_release(struct task_struct *tsk); +extern void put_seccomp_filter(struct task_struct *tsk); extern void get_seccomp_filter(struct task_struct *tsk); #else /* CONFIG_SECCOMP_FILTER */ -static inline void seccomp_filter_release(struct task_struct *tsk) +static inline void put_seccomp_filter(struct task_struct *tsk) { return; } diff --git a/include/linux/security.h b/include/linux/security.h index 8261a0646956..a8c99a229795 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -118,7 +118,6 @@ enum lockdown_reason { LOCKDOWN_MMIOTRACE, LOCKDOWN_DEBUGFS, LOCKDOWN_XMON_WR, - LOCKDOWN_BPF_WRITE_USER, LOCKDOWN_DBG_WRITE_KERNEL, LOCKDOWN_INTEGRITY_MAX, LOCKDOWN_KCORE, @@ -213,7 +212,7 @@ struct request_sock; #ifdef CONFIG_MMU extern int mmap_min_addr_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); #endif /* security_inode_init_security callback function to write xattrs */ diff --git a/include/linux/shdma-base.h b/include/linux/shdma-base.h index 03ba4dab2ef7..6dfd05ef5c2d 100644 --- a/include/linux/shdma-base.h +++ b/include/linux/shdma-base.h @@ -96,7 +96,7 @@ struct shdma_ops { int (*desc_setup)(struct shdma_chan *, struct shdma_desc *, dma_addr_t, dma_addr_t, size_t *); int (*set_slave)(struct shdma_chan *, int, dma_addr_t, bool); - int (*setup_xfer)(struct shdma_chan *, int); + void (*setup_xfer)(struct shdma_chan *, int); void (*start_xfer)(struct shdma_chan *, struct shdma_desc *); struct shdma_desc *(*embedded_desc)(void *, int); bool (*chan_irq)(struct shdma_chan *, int); diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h index add201a31f2c..254f824f0255 100644 --- a/include/linux/skbuff.h +++ b/include/linux/skbuff.h @@ -1285,6 +1285,32 @@ void skb_flow_dissector_init(struct flow_dissector *flow_dissector, const struct flow_dissector_key *key, unsigned int key_count); +#ifdef CONFIG_NET +int skb_flow_dissector_prog_query(const union bpf_attr *attr, + union bpf_attr __user *uattr); +int skb_flow_dissector_bpf_prog_attach(const union bpf_attr *attr, + struct bpf_prog *prog); + +int skb_flow_dissector_bpf_prog_detach(const union bpf_attr *attr); +#else +static inline int skb_flow_dissector_prog_query(const union bpf_attr *attr, + union bpf_attr __user *uattr) +{ + return -EOPNOTSUPP; +} + +static inline int skb_flow_dissector_bpf_prog_attach(const union bpf_attr *attr, + struct bpf_prog *prog) +{ + return -EOPNOTSUPP; +} + +static inline int skb_flow_dissector_bpf_prog_detach(const union bpf_attr *attr) +{ + return -EOPNOTSUPP; +} +#endif + struct bpf_flow_dissector; bool bpf_flow_dissect(struct bpf_prog *prog, struct bpf_flow_dissector *ctx, __be16 proto, int nhoff, int hlen, unsigned int flags); @@ -1626,22 +1652,6 @@ static inline int skb_unclone(struct sk_buff *skb, gfp_t pri) return 0; } -/* This variant of skb_unclone() makes sure skb->truesize is not changed */ -static inline int skb_unclone_keeptruesize(struct sk_buff *skb, gfp_t pri) -{ - might_sleep_if(gfpflags_allow_blocking(pri)); - - if (skb_cloned(skb)) { - unsigned int save = skb->truesize; - int res; - - res = pskb_expand_head(skb, 0, 0, pri); - skb->truesize = save; - return res; - } - return 0; -} - /** * skb_header_cloned - is the header a clone * @skb: buffer to check @@ -2582,11 +2592,6 @@ static inline int skb_mac_header_was_set(const struct sk_buff *skb) return skb->mac_header != (typeof(skb->mac_header))~0U; } -static inline void skb_unset_mac_header(struct sk_buff *skb) -{ - skb->mac_header = (typeof(skb->mac_header))~0U; -} - static inline void skb_reset_mac_header(struct sk_buff *skb) { skb->mac_header = skb->data - skb->head; @@ -4000,14 +4005,6 @@ static inline void __skb_incr_checksum_unnecessary(struct sk_buff *skb) } } -static inline void __skb_reset_checksum_unnecessary(struct sk_buff *skb) -{ - if (skb->ip_summed == CHECKSUM_UNNECESSARY) { - skb->ip_summed = CHECKSUM_NONE; - skb->csum_level = 0; - } -} - /* Check if we need to perform checksum complete validation. * * Returns true if checksum complete is needed, false otherwise diff --git a/include/linux/skmsg.h b/include/linux/skmsg.h index 3d31b629bcbf..613d04526032 100644 --- a/include/linux/skmsg.h +++ b/include/linux/skmsg.h @@ -29,7 +29,7 @@ struct sk_msg_sg { u32 end; u32 size; u32 copybreak; - unsigned long copy; + bool copy[MAX_MSG_FRAGS]; /* The extra two elements: * 1) used for chaining the front and sections when the list becomes * partitioned (e.g. end < start). The crypto APIs require the @@ -38,7 +38,6 @@ struct sk_msg_sg { */ struct scatterlist data[MAX_MSG_FRAGS + 2]; }; -static_assert(BITS_PER_LONG >= MAX_MSG_FRAGS); /* UAPI in filter.c depends on struct sk_msg_sg being first element. */ struct sk_msg { @@ -71,9 +70,7 @@ struct sk_psock_link { }; struct sk_psock_parser { -#if IS_ENABLED(CONFIG_BPF_STREAM_PARSER) struct strparser strp; -#endif bool enabled; void (*saved_data_ready)(struct sock *sk); }; @@ -100,7 +97,6 @@ struct sk_psock { spinlock_t link_lock; refcount_t refcnt; void (*saved_unhash)(struct sock *sk); - void (*saved_destroy)(struct sock *sk); void (*saved_close)(struct sock *sk, long timeout); void (*saved_write_space)(struct sock *sk); struct proto *sk_proto; @@ -235,7 +231,7 @@ static inline void sk_msg_compute_data_pointers(struct sk_msg *msg) { struct scatterlist *sge = sk_msg_elem(msg, msg->sg.start); - if (test_bit(msg->sg.start, &msg->sg.copy)) { + if (msg->sg.copy[msg->sg.start]) { msg->data = NULL; msg->data_end = NULL; } else { @@ -254,7 +250,7 @@ static inline void sk_msg_page_add(struct sk_msg *msg, struct page *page, sg_set_page(sge, page, len, offset); sg_unmark_end(sge); - __set_bit(msg->sg.end, &msg->sg.copy); + msg->sg.copy[msg->sg.end] = true; msg->sg.size += len; sk_msg_iter_next(msg, end); } @@ -262,10 +258,7 @@ static inline void sk_msg_page_add(struct sk_msg *msg, struct page *page, static inline void sk_msg_sg_copy(struct sk_msg *msg, u32 i, bool copy_state) { do { - if (copy_state) - __set_bit(i, &msg->sg.copy); - else - __clear_bit(i, &msg->sg.copy); + msg->sg.copy[i] = copy_state; sk_msg_iter_var_next(i); if (i == msg->sg.end) break; @@ -308,27 +301,9 @@ static inline void sk_psock_report_error(struct sk_psock *psock, int err) struct sk_psock *sk_psock_init(struct sock *sk, int node); -#if IS_ENABLED(CONFIG_BPF_STREAM_PARSER) int sk_psock_init_strp(struct sock *sk, struct sk_psock *psock); void sk_psock_start_strp(struct sock *sk, struct sk_psock *psock); void sk_psock_stop_strp(struct sock *sk, struct sk_psock *psock); -#else -static inline int sk_psock_init_strp(struct sock *sk, struct sk_psock *psock) -{ - return -EOPNOTSUPP; -} - -static inline void sk_psock_start_strp(struct sock *sk, struct sk_psock *psock) -{ -} - -static inline void sk_psock_stop_strp(struct sock *sk, struct sk_psock *psock) -{ -} -#endif - -void sk_psock_start_verdict(struct sock *sk, struct sk_psock *psock); -void sk_psock_stop_verdict(struct sock *sk, struct sk_psock *psock); int sk_psock_msg_verdict(struct sock *sk, struct sk_psock *psock, struct sk_msg *msg); @@ -345,6 +320,14 @@ static inline void sk_psock_free_link(struct sk_psock_link *link) } struct sk_psock_link *sk_psock_link_pop(struct sk_psock *psock); +#if defined(CONFIG_BPF_STREAM_PARSER) +void sk_psock_unlink(struct sock *sk, struct sk_psock_link *link); +#else +static inline void sk_psock_unlink(struct sock *sk, + struct sk_psock_link *link) +{ +} +#endif void __sk_psock_purge_ingress_msg(struct sk_psock *psock); @@ -361,8 +344,12 @@ static inline void sk_psock_update_proto(struct sock *sk, struct sk_psock *psock, struct proto *ops) { - /* Pairs with lockless read in sk_clone_lock() */ - WRITE_ONCE(sk->sk_prot, ops); + psock->saved_unhash = sk->sk_prot->unhash; + psock->saved_close = sk->sk_prot->close; + psock->saved_write_space = sk->sk_write_space; + + psock->sk_proto = sk->sk_prot; + sk->sk_prot = ops; } static inline void sk_psock_restore_proto(struct sock *sk, @@ -409,6 +396,26 @@ static inline bool sk_psock_test_state(const struct sk_psock *psock, return test_bit(bit, &psock->state); } +static inline struct sk_psock *sk_psock_get_checked(struct sock *sk) +{ + struct sk_psock *psock; + + rcu_read_lock(); + psock = sk_psock(sk); + if (psock) { + if (sk->sk_prot->recvmsg != tcp_bpf_recvmsg) { + psock = ERR_PTR(-EBUSY); + goto out; + } + + if (!refcount_inc_not_zero(&psock->refcnt)) + psock = ERR_PTR(-EBUSY); + } +out: + rcu_read_unlock(); + return psock; +} + static inline struct sk_psock *sk_psock_get(struct sock *sk) { struct sk_psock *psock; diff --git a/include/linux/sock_diag.h b/include/linux/sock_diag.h index 0b9ecd8cf979..15fe980a27ea 100644 --- a/include/linux/sock_diag.h +++ b/include/linux/sock_diag.h @@ -25,19 +25,7 @@ void sock_diag_unregister(const struct sock_diag_handler *h); void sock_diag_register_inet_compat(int (*fn)(struct sk_buff *skb, struct nlmsghdr *nlh)); void sock_diag_unregister_inet_compat(int (*fn)(struct sk_buff *skb, struct nlmsghdr *nlh)); -u64 __sock_gen_cookie(struct sock *sk); - -static inline u64 sock_gen_cookie(struct sock *sk) -{ - u64 cookie; - - preempt_disable(); - cookie = __sock_gen_cookie(sk); - preempt_enable(); - - return cookie; -} - +u64 sock_gen_cookie(struct sock *sk); int sock_diag_check_cookie(struct sock *sk, const __u32 *cookie); void sock_diag_save_cookie(struct sock *sk, __u32 *cookie); diff --git a/include/linux/sockptr.h b/include/linux/sockptr.h deleted file mode 100644 index e3defc775f38..000000000000 --- a/include/linux/sockptr.h +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2020 Christoph Hellwig. - * - * Support for "universal" pointers that can point to either kernel or userspace - * memory. - */ -#ifndef _LINUX_SOCKPTR_H -#define _LINUX_SOCKPTR_H - -#include -#include - -typedef struct { - union { - void *kernel; - void __user *user; - }; - bool is_kernel : 1; -} sockptr_t; - -static inline bool sockptr_is_kernel(sockptr_t sockptr) -{ - return sockptr.is_kernel; -} - -static inline sockptr_t KERNEL_SOCKPTR(void *p) -{ - return (sockptr_t) { .kernel = p, .is_kernel = true }; -} - -static inline sockptr_t USER_SOCKPTR(void __user *p) -{ - return (sockptr_t) { .user = p }; -} - -static inline bool sockptr_is_null(sockptr_t sockptr) -{ - return !sockptr.user && !sockptr.kernel; -} - -static inline int copy_from_sockptr_offset(void *dst, sockptr_t src, - size_t offset, size_t size) -{ - if (!sockptr_is_kernel(src)) - return copy_from_user(dst, src.user + offset, size); - memcpy(dst, src.kernel + offset, size); - return 0; -} - -static inline int copy_from_sockptr(void *dst, sockptr_t src, size_t size) -{ - return copy_from_sockptr_offset(dst, src, 0, size); -} - -static inline int copy_to_sockptr_offset(sockptr_t dst, size_t offset, - const void *src, size_t size) -{ - if (!sockptr_is_kernel(dst)) - return copy_to_user(dst.user + offset, src, size); - memcpy(dst.kernel + offset, src, size); - return 0; -} - -static inline int copy_to_sockptr(sockptr_t dst, const void *src, size_t size) -{ - return copy_to_sockptr_offset(dst, 0, src, size); -} - -static inline void *memdup_sockptr(sockptr_t src, size_t len) -{ - void *p = kmalloc_track_caller(len, GFP_USER | __GFP_NOWARN); - - if (!p) - return ERR_PTR(-ENOMEM); - if (copy_from_sockptr(p, src, len)) { - kfree(p); - return ERR_PTR(-EFAULT); - } - return p; -} - -static inline void *memdup_sockptr_nul(sockptr_t src, size_t len) -{ - char *p = kmalloc_track_caller(len + 1, GFP_KERNEL); - - if (!p) - return ERR_PTR(-ENOMEM); - if (copy_from_sockptr(p, src, len)) { - kfree(p); - return ERR_PTR(-EFAULT); - } - p[len] = '\0'; - return p; -} - -static inline long strncpy_from_sockptr(char *dst, sockptr_t src, size_t count) -{ - if (sockptr_is_kernel(src)) { - size_t len = min(strnlen(src.kernel, count - 1) + 1, count); - - memcpy(dst, src.kernel, len); - return len; - } - return strncpy_from_user(dst, src.user, count); -} - -#endif /* _LINUX_SOCKPTR_H */ diff --git a/include/linux/stackleak.h b/include/linux/stackleak.h index a59db2f08e76..3d5c3271a9a8 100644 --- a/include/linux/stackleak.h +++ b/include/linux/stackleak.h @@ -25,7 +25,7 @@ static inline void stackleak_task_init(struct task_struct *t) #ifdef CONFIG_STACKLEAK_RUNTIME_DISABLE int stack_erasing_sysctl(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); #endif #else /* !CONFIG_GCC_PLUGIN_STACKLEAK */ diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h index 46c7184e8ec5..e4c934ca7c95 100644 --- a/include/linux/syscalls.h +++ b/include/linux/syscalls.h @@ -364,11 +364,6 @@ asmlinkage long sys_epoll_pwait(int epfd, struct epoll_event __user *events, int maxevents, int timeout, const sigset_t __user *sigmask, size_t sigsetsize); -asmlinkage long sys_epoll_pwait2(int epfd, struct epoll_event __user *events, - int maxevents, - const struct __kernel_timespec __user *timeout, - const sigset_t __user *sigmask, - size_t sigsetsize); /* fs/fcntl.c */ asmlinkage long sys_dup(unsigned int fildes); @@ -446,8 +441,6 @@ asmlinkage long sys_fchown(unsigned int fd, uid_t user, gid_t group); asmlinkage long sys_openat(int dfd, const char __user *filename, int flags, umode_t mode); asmlinkage long sys_close(unsigned int fd); -asmlinkage long sys_close_range(unsigned int fd, unsigned int max_fd, - unsigned int flags); asmlinkage long sys_vhangup(void); /* fs/pipe.c */ diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h index 3b66a8078ef2..31662b264d17 100644 --- a/include/linux/sysctl.h +++ b/include/linux/sysctl.h @@ -44,31 +44,41 @@ struct ctl_dir; extern const int sysctl_vals[]; -typedef int proc_handler(struct ctl_table *ctl, int write, void *buffer, - size_t *lenp, loff_t *ppos); +typedef int proc_handler (struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos); -int proc_dostring(struct ctl_table *, int, void *, size_t *, loff_t *); -int proc_dointvec(struct ctl_table *, int, void *, size_t *, loff_t *); -int proc_douintvec(struct ctl_table *, int, void *, size_t *, loff_t *); -int proc_dointvec_minmax(struct ctl_table *, int, void *, size_t *, loff_t *); -int proc_douintvec_minmax(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos); -int proc_dointvec_jiffies(struct ctl_table *, int, void *, size_t *, loff_t *); -int proc_dointvec_userhz_jiffies(struct ctl_table *, int, void *, size_t *, - loff_t *); -int proc_dointvec_ms_jiffies(struct ctl_table *, int, void *, size_t *, - loff_t *); -int proc_doulongvec_minmax(struct ctl_table *, int, void *, size_t *, - loff_t *); -int proc_doulongvec_ms_jiffies_minmax(struct ctl_table *table, int, - void *, size_t *, loff_t *); -int proc_do_large_bitmap(struct ctl_table *, int, void *, size_t *, loff_t *); -int proc_do_static_key(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos); -int proc_douintvec_capacity(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos); -int proc_douintvec_ravg_window(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos); +extern int proc_dostring(struct ctl_table *, int, + void __user *, size_t *, loff_t *); +extern int proc_dointvec(struct ctl_table *, int, + void __user *, size_t *, loff_t *); +extern int proc_douintvec(struct ctl_table *, int, + void __user *, size_t *, loff_t *); +extern int proc_dointvec_minmax(struct ctl_table *, int, + void __user *, size_t *, loff_t *); +extern int proc_douintvec_minmax(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); +extern int proc_dointvec_jiffies(struct ctl_table *, int, + void __user *, size_t *, loff_t *); +extern int proc_dointvec_userhz_jiffies(struct ctl_table *, int, + void __user *, size_t *, loff_t *); +extern int proc_dointvec_ms_jiffies(struct ctl_table *, int, + void __user *, size_t *, loff_t *); +extern int proc_doulongvec_minmax(struct ctl_table *, int, + void __user *, size_t *, loff_t *); +extern int proc_doulongvec_ms_jiffies_minmax(struct ctl_table *table, int, + void __user *, size_t *, loff_t *); +extern int proc_do_large_bitmap(struct ctl_table *, int, + void __user *, size_t *, loff_t *); +extern int proc_do_static_key(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); +extern int proc_douintvec_capacity(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); +extern int proc_douintvec_ravg_window(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); /* * Register a set of sysctl names by calling register_sysctl_table @@ -239,7 +249,7 @@ static inline void setup_sysctl_set(struct ctl_table_set *p, #endif /* CONFIG_SYSCTL */ -int sysctl_max_threads(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos); +int sysctl_max_threads(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, loff_t *ppos); #endif /* _LINUX_SYSCTL_H */ diff --git a/include/linux/tcp.h b/include/linux/tcp.h index 67d2d7cc0946..f04f0cd4da88 100644 --- a/include/linux/tcp.h +++ b/include/linux/tcp.h @@ -92,8 +92,6 @@ struct tcp_options_received { smc_ok : 1, /* SMC seen on SYN packet */ snd_wscale : 4, /* Window scaling received from sender */ rcv_wscale : 4; /* Window scaling to send to receiver */ - u8 saw_unknown:1, /* Received unknown option */ - unused:7; u8 num_sacks; /* Number of SACK blocks */ u16 user_mss; /* mss requested by user in ioctl */ u16 mss_clamp; /* Maximal mss, negotiated at connection setup */ @@ -241,13 +239,14 @@ struct tcp_sock { repair : 1, frto : 1;/* F-RTO (RFC5682) activated in CA_Loss */ u8 repair_queue; - u8 save_syn:2, /* Save headers of SYN packet */ - syn_data:1, /* SYN includes data */ + u8 syn_data:1, /* SYN includes data */ syn_fastopen:1, /* SYN includes Fast Open option */ syn_fastopen_exp:1,/* SYN includes Fast Open exp. option */ syn_fastopen_ch:1, /* Active TFO re-enabling probe */ syn_data_acked:1,/* data in SYN is acked by SYN-ACK */ - is_cwnd_limited:1;/* forward progress limited by snd_cwnd? */ + save_syn:1, /* Save headers of SYN packet */ + is_cwnd_limited:1,/* forward progress limited by snd_cwnd? */ + syn_smc:1; /* SYN includes SMC */ u32 tlp_high_seq; /* snd_nxt at the time of TLP */ u32 tcp_tx_delay; /* delay (in usec) added to TX packets */ @@ -396,9 +395,6 @@ struct tcp_sock { u32 mtu_info; /* We received an ICMP_FRAG_NEEDED / ICMPV6_PKT_TOOBIG * while socket was owned by user. */ -#if IS_ENABLED(CONFIG_SMC) - bool syn_smc; /* SYN includes SMC */ -#endif #ifdef CONFIG_TCP_MD5SIG /* TCP AF-Specific parts; only used by MD5 Signature support so far */ @@ -414,7 +410,7 @@ struct tcp_sock { * socket. Used to retransmit SYNACKs etc. */ struct request_sock __rcu *fastopen_rsk; - struct saved_syn *saved_syn; + u32 *saved_syn; }; enum tsq_enum { @@ -492,12 +488,6 @@ static inline void tcp_saved_syn_free(struct tcp_sock *tp) tp->saved_syn = NULL; } -static inline u32 tcp_saved_syn_len(const struct saved_syn *saved_syn) -{ - return saved_syn->mac_hdrlen + saved_syn->network_hdrlen + - saved_syn->tcp_hdrlen; -} - struct sk_buff *tcp_get_timestamping_opt_stats(const struct sock *sk); static inline u16 tcp_mss_clamp(const struct tcp_sock *tp, u16 mss) @@ -513,7 +503,4 @@ static inline u16 tcp_mss_clamp(const struct tcp_sock *tp, u16 mss) int tcp_skb_shift(struct sk_buff *to, struct sk_buff *from, int pcount, int shiftlen); -int tcp_sock_set_keepidle_locked(struct sock *sk, int val); -int tcp_sock_set_keepidle(struct sock *sk, int val); - #endif /* _LINUX_TCP_H */ diff --git a/include/linux/timer.h b/include/linux/timer.h index 01ae0aaf6abe..d3bcda932baf 100644 --- a/include/linux/timer.h +++ b/include/linux/timer.h @@ -209,7 +209,8 @@ struct ctl_table; extern unsigned int sysctl_timer_migration; int timer_migration_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, + loff_t *ppos); #endif unsigned long __round_jiffies(unsigned long j, int cpu); diff --git a/include/linux/tnum.h b/include/linux/tnum.h index 498dbcedb451..ea627d1ab7e3 100644 --- a/include/linux/tnum.h +++ b/include/linux/tnum.h @@ -86,16 +86,4 @@ int tnum_strn(char *str, size_t size, struct tnum a); /* Format a tnum as tristate binary expansion */ int tnum_sbin(char *str, size_t size, struct tnum a); -/* Returns the 32-bit subreg */ -struct tnum tnum_subreg(struct tnum a); -/* Returns the tnum with the lower 32-bit subreg cleared */ -struct tnum tnum_clear_subreg(struct tnum a); -/* Returns the tnum with the lower 32-bit subreg set to value */ -struct tnum tnum_const_subreg(struct tnum a, u32 value); -/* Returns true if 32-bit subreg @a is a known constant*/ -static inline bool tnum_subreg_is_const(struct tnum a) -{ - return !(tnum_subreg(a)).mask; -} - #endif /* _LINUX_TNUM_H */ diff --git a/include/linux/touchscreen_mmi.h b/include/linux/touchscreen_mmi.h index 7443639e086c..3655136150a1 100644 --- a/include/linux/touchscreen_mmi.h +++ b/include/linux/touchscreen_mmi.h @@ -137,9 +137,6 @@ struct drm_panel_notifier *evdata = evd; \ ((event == DRM_PANEL_EVENT_BLANK) && \ (*blank == DRM_PANEL_BLANK_UNBLANK)) -#define EVENT_DISPLAY_LP \ - (*blank == DRM_PANEL_BLANK_LP) - #else /* CONFIG_DRM_PANEL_NOTIFICATIONS */ #if LINUX_VERSION_CODE <= KERNEL_VERSION(4,14,0) #if defined(CONFIG_DRM_MSM) diff --git a/include/linux/uaccess.h b/include/linux/uaccess.h index 59c5d58f0c1c..70941f49d66e 100644 --- a/include/linux/uaccess.h +++ b/include/linux/uaccess.h @@ -305,31 +305,68 @@ copy_struct_from_user(void *dst, size_t ksize, const void __user *src, return 0; } -bool copy_from_kernel_nofault_allowed(const void *unsafe_src, size_t size); +/* + * probe_kernel_read(): safely attempt to read from a location + * @dst: pointer to the buffer that shall take the data + * @src: address to read from + * @size: size of the data chunk + * + * Safely read from address @src to the buffer at @dst. If a kernel fault + * happens, handle that and return -EFAULT. + */ +extern long probe_kernel_read(void *dst, const void *src, size_t size); +extern long __probe_kernel_read(void *dst, const void *src, size_t size); -long copy_from_kernel_nofault(void *dst, const void *src, size_t size); -long notrace copy_to_kernel_nofault(void *dst, const void *src, size_t size); +/* + * probe_user_read(): safely attempt to read from a location in user space + * @dst: pointer to the buffer that shall take the data + * @src: address to read from + * @size: size of the data chunk + * + * Safely read from address @src to the buffer at @dst. If a kernel fault + * happens, handle that and return -EFAULT. + */ +extern long probe_user_read(void *dst, const void __user *src, size_t size); +extern long __probe_user_read(void *dst, const void __user *src, size_t size); -long copy_from_user_nofault(void *dst, const void __user *src, size_t size); -long notrace copy_to_user_nofault(void __user *dst, const void *src, - size_t size); +/* + * probe_kernel_write(): safely attempt to write to a location + * @dst: address to write to + * @src: pointer to the data that shall be written + * @size: size of the data chunk + * + * Safely write to address @dst from the buffer at @src. If a kernel fault + * happens, handle that and return -EFAULT. + */ +extern long notrace probe_kernel_write(void *dst, const void *src, size_t size); +extern long notrace __probe_kernel_write(void *dst, const void *src, size_t size); -long strncpy_from_kernel_nofault(char *dst, const void *unsafe_addr, - long count); +/* + * probe_user_write(): safely attempt to write to a location in user space + * @dst: address to write to + * @src: pointer to the data that shall be written + * @size: size of the data chunk + * + * Safely write to address @dst from the buffer at @src. If a kernel fault + * happens, handle that and return -EFAULT. + */ +extern long notrace probe_user_write(void __user *dst, const void *src, size_t size); +extern long notrace __probe_user_write(void __user *dst, const void *src, size_t size); -long strncpy_from_user_nofault(char *dst, const void __user *unsafe_addr, - long count); +extern long strncpy_from_unsafe(char *dst, const void *unsafe_addr, long count); +extern long strncpy_from_unsafe_user(char *dst, const void __user *unsafe_addr, + long count); extern long strnlen_unsafe_user(const void __user *unsafe_addr, long count); /** - * get_kernel_nofault(): safely attempt to read from a location - * @val: read into this variable - * @ptr: address to read from + * probe_kernel_address(): safely attempt to read from a location + * @addr: address to read from + * @retval: read into this variable * * Returns 0 on success, or -EFAULT. */ -#define get_kernel_nofault(val, ptr) \ - copy_from_kernel_nofault(&(val), (ptr), sizeof(val)) +#define probe_kernel_address(addr, retval) \ + probe_kernel_read(&retval, addr, sizeof(retval)) #ifndef user_access_begin #define user_access_begin(ptr,len) access_ok(ptr, len) diff --git a/include/linux/umh.h b/include/linux/umh.h index 73173c4a07e5..0c08de356d0d 100644 --- a/include/linux/umh.h +++ b/include/linux/umh.h @@ -25,6 +25,7 @@ struct subprocess_info { struct file *file; int wait; int retval; + pid_t pid; int (*init)(struct subprocess_info *info, struct cred *new); void (*cleanup)(struct subprocess_info *info); void *data; @@ -39,6 +40,19 @@ call_usermodehelper_setup(const char *path, char **argv, char **envp, int (*init)(struct subprocess_info *info, struct cred *new), void (*cleanup)(struct subprocess_info *), void *data); +struct subprocess_info *call_usermodehelper_setup_file(struct file *file, + int (*init)(struct subprocess_info *info, struct cred *new), + void (*cleanup)(struct subprocess_info *), void *data); +struct umh_info { + const char *cmdline; + struct file *pipe_to_umh; + struct file *pipe_from_umh; + struct list_head list; + void (*cleanup)(struct umh_info *info); + pid_t pid; +}; +int fork_usermode_blob(void *data, size_t len, struct umh_info *info); + extern int call_usermodehelper_exec(struct subprocess_info *info, int wait); diff --git a/include/linux/usb.h b/include/linux/usb.h index 14f72024d108..382a5725ee6a 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -1992,17 +1992,21 @@ usb_pipe_endpoint(struct usb_device *dev, unsigned int pipe) return eps[usb_pipeendpoint(pipe)]; } -static inline u16 usb_maxpacket(struct usb_device *udev, int pipe, - /* int is_out deprecated */ ...) +/*-------------------------------------------------------------------------*/ + +static inline __u16 +usb_maxpacket(struct usb_device *udev, int pipe, int is_out) { struct usb_host_endpoint *ep; unsigned epnum = usb_pipeendpoint(pipe); - if (usb_pipeout(pipe)) + if (is_out) { + WARN_ON(usb_pipein(pipe)); ep = udev->ep_out[epnum]; - else + } else { + WARN_ON(usb_pipeout(pipe)); ep = udev->ep_in[epnum]; - + } if (!ep) return 0; @@ -2010,6 +2014,8 @@ static inline u16 usb_maxpacket(struct usb_device *udev, int pipe, return usb_endpoint_maxp(&ep->desc); } +/* ----------------------------------------------------------------------- */ + /* translate USB error codes to codes user space understands */ static inline int usb_translate_errors(int error_code) { diff --git a/include/linux/usermode_driver.h b/include/linux/usermode_driver.h deleted file mode 100644 index a1e02831de67..000000000000 --- a/include/linux/usermode_driver.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __LINUX_USERMODE_DRIVER_H__ -#define __LINUX_USERMODE_DRIVER_H__ - -#include -#include - -#ifdef CONFIG_BPFILTER -void __exit_umh(struct task_struct *tsk); - -static inline void exit_umh(struct task_struct *tsk) -{ - if (unlikely(tsk->flags & PF_UMH)) - __exit_umh(tsk); -} -#else -static inline void exit_umh(struct task_struct *tsk) -{ -} -#endif - -struct umd_info { - const char *driver_name; - struct file *pipe_to_umh; - struct file *pipe_from_umh; - struct list_head list; - void (*cleanup)(struct umd_info *info); - struct path wd; - struct pid *tgid; -}; -int umd_load_blob(struct umd_info *info, const void *data, size_t len); -int umd_unload_blob(struct umd_info *info); -int fork_usermode_driver(struct umd_info *info); -void umd_cleanup_helper(struct umd_info *info); - -#endif /* __LINUX_USERMODE_DRIVER_H__ */ diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h index 3469d890d9e1..ad4d4697a167 100644 --- a/include/linux/virtio_config.h +++ b/include/linux/virtio_config.h @@ -10,11 +10,6 @@ struct irq_affinity; -struct virtio_shm_region { - u64 addr; - u64 len; -}; - /** * virtio_config_ops - operations for configuring a virtio device * Note: Do not assume that a transport implements all of the operations @@ -71,7 +66,6 @@ struct virtio_shm_region { * the caller can then copy. * @set_vq_affinity: set the affinity for a virtqueue (optional). * @get_vq_affinity: get the affinity for a virtqueue (optional). - * @get_shm_region: get a shared memory region based on the index. */ typedef void vq_callback_t(struct virtqueue *); struct virtio_config_ops { @@ -95,8 +89,6 @@ struct virtio_config_ops { const struct cpumask *cpu_mask); const struct cpumask *(*get_vq_affinity)(struct virtio_device *vdev, int index); - bool (*get_shm_region)(struct virtio_device *vdev, - struct virtio_shm_region *region, u8 id); }; /* If driver didn't advertise the feature, it will never appear. */ @@ -259,15 +251,6 @@ int virtqueue_set_affinity(struct virtqueue *vq, const struct cpumask *cpu_mask) return 0; } -static inline -bool virtio_get_shm_region(struct virtio_device *vdev, - struct virtio_shm_region *region, u8 id) -{ - if (!vdev->config->get_shm_region) - return false; - return vdev->config->get_shm_region(vdev, region, id); -} - static inline bool virtio_is_little_endian(struct virtio_device *vdev) { return virtio_has_feature(vdev, VIRTIO_F_VERSION_1) || diff --git a/include/linux/vmalloc.h b/include/linux/vmalloc.h index 588a0675bfc4..7e1c887d10a4 100644 --- a/include/linux/vmalloc.h +++ b/include/linux/vmalloc.h @@ -94,11 +94,10 @@ extern void *vzalloc(unsigned long size); extern void *vmalloc_user(unsigned long size); extern void *vmalloc_node(unsigned long size, int node); extern void *vzalloc_node(unsigned long size, int node); -extern void *vmalloc_user_node_flags(unsigned long size, int node, gfp_t flags); extern void *vmalloc_exec(unsigned long size); extern void *vmalloc_32(unsigned long size); extern void *vmalloc_32_user(unsigned long size); -extern void *__vmalloc(unsigned long size, gfp_t gfp_mask); +extern void *__vmalloc(unsigned long size, gfp_t gfp_mask, pgprot_t prot); extern void *__vmalloc_node_range(unsigned long size, unsigned long align, unsigned long start, unsigned long end, gfp_t gfp_mask, pgprot_t prot, unsigned long vm_flags, int node, diff --git a/include/linux/vmstat.h b/include/linux/vmstat.h index d9739bd4991f..bdeda4b079fe 100644 --- a/include/linux/vmstat.h +++ b/include/linux/vmstat.h @@ -16,8 +16,8 @@ extern int sysctl_stat_interval; #define DISABLE_NUMA_STAT 0 extern int sysctl_vm_numa_stat; DECLARE_STATIC_KEY_TRUE(vm_numa_stat_key); -int sysctl_vm_numa_stat_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos); +extern int sysctl_vm_numa_stat_handler(struct ctl_table *table, + int write, void __user *buffer, size_t *length, loff_t *ppos); #endif struct reclaim_stat { @@ -268,8 +268,8 @@ void cpu_vm_stats_fold(int cpu); void refresh_zone_stat_thresholds(void); struct ctl_table; -int vmstat_refresh(struct ctl_table *, int write, void *buffer, size_t *lenp, - loff_t *ppos); +int vmstat_refresh(struct ctl_table *, int write, + void __user *buffer, size_t *lenp, loff_t *ppos); void drain_zonestat(struct zone *zone, struct per_cpu_pageset *); diff --git a/include/linux/wait.h b/include/linux/wait.h index 4408cd2ad779..f294f9b74cd9 100644 --- a/include/linux/wait.h +++ b/include/linux/wait.h @@ -1176,6 +1176,4 @@ int autoremove_wake_function(struct wait_queue_entry *wq_entry, unsigned mode, i (wait)->flags = 0; \ } while (0) -bool try_invoke_on_locked_down_task(struct task_struct *p, bool (*func)(struct task_struct *t, void *arg), void *arg); - #endif /* _LINUX_WAIT_H */ diff --git a/include/linux/writeback.h b/include/linux/writeback.h index f8a7e1a850fb..a19d845dd7eb 100644 --- a/include/linux/writeback.h +++ b/include/linux/writeback.h @@ -362,18 +362,24 @@ extern int vm_highmem_is_dirtyable; extern int block_dump; extern int laptop_mode; -int dirty_background_ratio_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); -int dirty_background_bytes_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); -int dirty_ratio_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); -int dirty_bytes_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); +extern int dirty_background_ratio_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); +extern int dirty_background_bytes_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); +extern int dirty_ratio_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); +extern int dirty_bytes_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); int dirtytime_interval_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); -int dirty_writeback_centisecs_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); + +struct ctl_table; +int dirty_writeback_centisecs_handler(struct ctl_table *, int, + void __user *, size_t *, loff_t *); void global_dirty_limits(unsigned long *pbackground, unsigned long *pdirty); unsigned long wb_calc_thresh(struct bdi_writeback *wb, unsigned long thresh); diff --git a/include/linux/xattr.h b/include/linux/xattr.h index aecc330c1cc5..0d970fdc66e1 100644 --- a/include/linux/xattr.h +++ b/include/linux/xattr.h @@ -105,8 +105,7 @@ struct simple_xattr *simple_xattr_alloc(const void *value, size_t size); int simple_xattr_get(struct simple_xattrs *xattrs, const char *name, void *buffer, size_t size); int simple_xattr_set(struct simple_xattrs *xattrs, const char *name, - const void *value, size_t size, int flags, - ssize_t *removed_size); + const void *value, size_t size, int flags); ssize_t simple_xattr_list(struct inode *inode, struct simple_xattrs *xattrs, char *buffer, size_t size); void simple_xattr_list_add(struct simple_xattrs *xattrs, diff --git a/include/net/bpf_sk_storage.h b/include/net/bpf_sk_storage.h index 3c516dd07caf..8e4f831d2e52 100644 --- a/include/net/bpf_sk_storage.h +++ b/include/net/bpf_sk_storage.h @@ -3,17 +3,6 @@ #ifndef _BPF_SK_STORAGE_H #define _BPF_SK_STORAGE_H -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - struct sock; void bpf_sk_storage_free(struct sock *sk); @@ -21,42 +10,14 @@ void bpf_sk_storage_free(struct sock *sk); extern const struct bpf_func_proto bpf_sk_storage_get_proto; extern const struct bpf_func_proto bpf_sk_storage_delete_proto; -struct bpf_local_storage_elem; -struct bpf_sk_storage_diag; -struct sk_buff; -struct nlattr; -struct sock; - #ifdef CONFIG_BPF_SYSCALL int bpf_sk_storage_clone(const struct sock *sk, struct sock *newsk); -struct bpf_sk_storage_diag * -bpf_sk_storage_diag_alloc(const struct nlattr *nla_stgs); -void bpf_sk_storage_diag_free(struct bpf_sk_storage_diag *diag); -int bpf_sk_storage_diag_put(struct bpf_sk_storage_diag *diag, - struct sock *sk, struct sk_buff *skb, - int stg_array_type, - unsigned int *res_diag_size); #else static inline int bpf_sk_storage_clone(const struct sock *sk, struct sock *newsk) { return 0; } -static inline struct bpf_sk_storage_diag * -bpf_sk_storage_diag_alloc(const struct nlattr *nla) -{ - return NULL; -} -static inline void bpf_sk_storage_diag_free(struct bpf_sk_storage_diag *diag) -{ -} -static inline int bpf_sk_storage_diag_put(struct bpf_sk_storage_diag *diag, - struct sock *sk, struct sk_buff *skb, - int stg_array_type, - unsigned int *res_diag_size) -{ - return 0; -} #endif #endif /* _BPF_SK_STORAGE_H */ diff --git a/include/net/checksum.h b/include/net/checksum.h index 25b66833e69b..e13d5ecf71cd 100644 --- a/include/net/checksum.h +++ b/include/net/checksum.h @@ -152,7 +152,7 @@ void inet_proto_csum_replace16(__sum16 *sum, struct sk_buff *skb, const __be32 *from, const __be32 *to, bool pseudohdr); void inet_proto_csum_replace_by_diff(__sum16 *sum, struct sk_buff *skb, - __wsum diff, bool pseudohdr, bool ipv6); + __wsum diff, bool pseudohdr); static __always_inline void inet_proto_csum_replace2(__sum16 *sum, struct sk_buff *skb, diff --git a/include/net/cls_cgroup.h b/include/net/cls_cgroup.h index 668aeee9b3f6..4295de3e6a4b 100644 --- a/include/net/cls_cgroup.h +++ b/include/net/cls_cgroup.h @@ -45,14 +45,9 @@ static inline void sock_update_classid(struct sock_cgroup_data *skcd) sock_cgroup_set_classid(skcd, classid); } -static inline u32 __task_get_classid(struct task_struct *task) -{ - return task_cls_state(task)->classid; -} - static inline u32 task_get_classid(const struct sk_buff *skb) { - u32 classid = __task_get_classid(current); + u32 classid = task_cls_state(current)->classid; /* Due to the nature of the classifier it is required to ignore all * packets originating from softirq context as accessing `current' @@ -63,7 +58,7 @@ static inline u32 task_get_classid(const struct sk_buff *skb) * calls by looking at the number of nested bh disable calls because * softirqs always disables bh. */ - if (softirq_count()) { + if (in_serving_softirq()) { struct sock *sk = skb_to_full_sk(skb); /* If there is an sock_cgroup_classid we'll use that. */ diff --git a/include/net/cnss.h b/include/net/cnss.h index 77bc3157c2aa..9c99bdc2032d 100644 --- a/include/net/cnss.h +++ b/include/net/cnss.h @@ -10,6 +10,7 @@ #include #include +#ifdef CONFIG_CNSS #define MAX_FIRMWARE_SIZE (1 * 1024 * 1024) #define CNSS_MAX_FILE_NAME 20 #define PINCTRL_SLEEP 0 @@ -176,6 +177,7 @@ int cnss_pm_runtime_request(struct device *dev, enum cnss_runtime_request request); void cnss_set_cc_source(enum cnss_cc_src cc_source); enum cnss_cc_src cnss_get_cc_source(void); +#endif void cnss_pm_wake_lock_init(struct wakeup_source **ws, const char *name); void cnss_pm_wake_lock(struct wakeup_source *ws); diff --git a/include/net/compat.h b/include/net/compat.h index b4fe96750e64..f277653c7e17 100644 --- a/include/net/compat.h +++ b/include/net/compat.h @@ -40,6 +40,7 @@ struct compat_cmsghdr { int get_compat_msghdr(struct msghdr *, struct compat_msghdr __user *, struct sockaddr __user **, struct iovec **); +struct sock_fprog __user *get_compat_bpf_fprog(char __user *optval); int put_cmsg_compat(struct msghdr*, int, int, int, void *); int cmsghdr_from_user_compat_to_kern(struct msghdr *, struct sock *, diff --git a/include/net/flow_dissector.h b/include/net/flow_dissector.h index 6edd03b44506..efd7987982a8 100644 --- a/include/net/flow_dissector.h +++ b/include/net/flow_dissector.h @@ -8,10 +8,6 @@ #include #include -struct bpf_prog; -struct net; -struct sk_buff; - /** * struct flow_dissector_key_control: * @thoff: Transport header offset @@ -180,16 +176,19 @@ struct flow_dissector_key_ports_range { /** * flow_dissector_key_icmp: + * @ports: type and code of ICMP header + * icmp: ICMP type (high) and code (low) * type: ICMP type * code: ICMP code - * id: session identifier */ struct flow_dissector_key_icmp { - struct { - u8 type; - u8 code; + union { + __be16 icmp; + struct { + u8 type; + u8 code; + }; }; - u16 id; }; /** @@ -304,8 +303,6 @@ struct flow_keys { struct flow_dissector_key_vlan cvlan; struct flow_dissector_key_keyid keyid; struct flow_dissector_key_ports ports; - struct flow_dissector_key_icmp icmp; - /* 'addrs' must be the last member */ struct flow_dissector_key_addrs addrs; }; @@ -339,9 +336,6 @@ static inline bool flow_keys_have_l4(const struct flow_keys *keys) } u32 flow_hash_from_keys(struct flow_keys *keys); -void skb_flow_get_icmp_tci(const struct sk_buff *skb, - struct flow_dissector_key_icmp *key_icmp, - void *data, int thoff, int hlen); static inline bool dissector_uses_key(const struct flow_dissector *flow_dissector, enum flow_dissector_key_id key_id) @@ -371,9 +365,4 @@ flow_dissector_init_keys(struct flow_dissector_key_control *key_control, memset(key_basic, 0, sizeof(*key_basic)); } -#ifdef CONFIG_BPF_SYSCALL -int flow_dissector_bpf_prog_attach_check(struct net *net, - struct bpf_prog *prog); -#endif /* CONFIG_BPF_SYSCALL */ - #endif diff --git a/include/net/inet6_hashtables.h b/include/net/inet6_hashtables.h index 705a1833e1ff..fe96bf247aac 100644 --- a/include/net/inet6_hashtables.h +++ b/include/net/inet6_hashtables.h @@ -48,13 +48,6 @@ struct sock *__inet6_lookup_established(struct net *net, const u16 hnum, const int dif, const int sdif); -struct sock *inet6_lookup_reuseport(struct net *net, struct sock *sk, - struct sk_buff *skb, int doff, - const struct in6_addr *saddr, - __be16 sport, - const struct in6_addr *daddr, - unsigned short hnum); - struct sock *inet6_lookup_listener(struct net *net, struct inet_hashinfo *hashinfo, struct sk_buff *skb, int doff, @@ -92,8 +85,9 @@ static inline struct sock *__inet6_lookup_skb(struct inet_hashinfo *hashinfo, int iif, int sdif, bool *refcounted) { - struct sock *sk = skb_steal_sock(skb, refcounted); + struct sock *sk = skb_steal_sock(skb); + *refcounted = true; if (sk) return sk; diff --git a/include/net/inet_common.h b/include/net/inet_common.h index cb2818862919..ae2ba897675c 100644 --- a/include/net/inet_common.h +++ b/include/net/inet_common.h @@ -35,14 +35,8 @@ int inet_shutdown(struct socket *sock, int how); int inet_listen(struct socket *sock, int backlog); void inet_sock_destruct(struct sock *sk); int inet_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len); -/* Don't allocate port at this moment, defer to connect. */ -#define BIND_FORCE_ADDRESS_NO_PORT (1 << 0) -/* Grab and release socket lock. */ -#define BIND_WITH_LOCK (1 << 1) -/* Called from BPF program. */ -#define BIND_FROM_BPF (1 << 2) int __inet_bind(struct sock *sk, struct sockaddr *uaddr, int addr_len, - u32 flags); + bool force_bind_address_no_port, bool with_lock); int inet_getname(struct socket *sock, struct sockaddr *uaddr, int peer); int inet_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg); diff --git a/include/net/inet_connection_sock.h b/include/net/inet_connection_sock.h index 6823bcbc9f81..c9f9ed10bf21 100644 --- a/include/net/inet_connection_sock.h +++ b/include/net/inet_connection_sock.h @@ -95,8 +95,6 @@ struct inet_connection_sock { struct timer_list icsk_retransmit_timer; struct timer_list icsk_delack_timer; __u32 icsk_rto; - __u32 icsk_rto_min; - __u32 icsk_delack_max; __u32 icsk_pmtu_cookie; const struct tcp_congestion_ops *icsk_ca_ops; const struct inet_connection_sock_af_ops *icsk_af_ops; @@ -359,9 +357,4 @@ static inline void inet_csk_inc_pingpong_cnt(struct sock *sk) if (icsk->icsk_ack.pingpong < U8_MAX) icsk->icsk_ack.pingpong++; } - -static inline bool inet_csk_has_ulp(struct sock *sk) -{ - return inet_sk(sk)->is_icsk && !!inet_csk(sk)->icsk_ulp_ops; -} #endif /* _INET_CONNECTION_SOCK_H */ diff --git a/include/net/inet_hashtables.h b/include/net/inet_hashtables.h index ee9cd10cee64..a186c245a6f4 100644 --- a/include/net/inet_hashtables.h +++ b/include/net/inet_hashtables.h @@ -329,11 +329,6 @@ struct sock *__inet_lookup_established(struct net *net, const __be32 daddr, const u16 hnum, const int dif, const int sdif); -struct sock *inet_lookup_reuseport(struct net *net, struct sock *sk, - struct sk_buff *skb, int doff, - __be32 saddr, __be16 sport, - __be32 daddr, unsigned short hnum); - static inline struct sock * inet_lookup_established(struct net *net, struct inet_hashinfo *hashinfo, const __be32 saddr, const __be16 sport, @@ -391,9 +386,10 @@ static inline struct sock *__inet_lookup_skb(struct inet_hashinfo *hashinfo, const int sdif, bool *refcounted) { - struct sock *sk = skb_steal_sock(skb, refcounted); + struct sock *sk = skb_steal_sock(skb); const struct iphdr *iph = ip_hdr(skb); + *refcounted = true; if (sk) return sk; diff --git a/include/net/ip6_fib.h b/include/net/ip6_fib.h index 07cf387b55b9..8a7d8b895593 100644 --- a/include/net/ip6_fib.h +++ b/include/net/ip6_fib.h @@ -504,13 +504,6 @@ static inline bool fib6_metric_locked(struct fib6_info *f6i, int metric) return !!(f6i->fib6_metrics->metrics[RTAX_LOCK - 1] & (1 << metric)); } -#if IS_BUILTIN(CONFIG_IPV6) && defined(CONFIG_BPF_SYSCALL) -struct bpf_iter__ipv6_route { - __bpf_md_ptr(struct bpf_iter_meta *, meta); - __bpf_md_ptr(struct fib6_info *, rt); -}; -#endif - #ifdef CONFIG_IPV6_MULTIPLE_TABLES int fib6_rules_init(void); void fib6_rules_cleanup(void); diff --git a/include/net/ip_tunnels.h b/include/net/ip_tunnels.h index b6e2b045700b..357c45d28142 100644 --- a/include/net/ip_tunnels.h +++ b/include/net/ip_tunnels.h @@ -269,8 +269,7 @@ void ip_tunnel_xmit(struct sk_buff *skb, struct net_device *dev, const struct iphdr *tnl_params, const u8 protocol); void ip_md_tunnel_xmit(struct sk_buff *skb, struct net_device *dev, const u8 proto, int tunnel_hlen); -int ip_tunnel_ctl(struct net_device *dev, struct ip_tunnel_parm *p, int cmd); -int ip_tunnel_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); +int ip_tunnel_ioctl(struct net_device *dev, struct ip_tunnel_parm *p, int cmd); int __ip_tunnel_change_mtu(struct net_device *dev, int new_mtu, bool strict); int ip_tunnel_change_mtu(struct net_device *dev, int new_mtu); @@ -458,21 +457,6 @@ void iptunnel_xmit(struct sock *sk, struct rtable *rt, struct sk_buff *skb, struct metadata_dst *iptunnel_metadata_reply(struct metadata_dst *md, gfp_t flags); -static inline void ip_tunnel_adj_headroom(struct net_device *dev, - unsigned int headroom) -{ - /* we must cap headroom to some upperlimit, else pskb_expand_head - * will overflow header offsets in skb_headers_offset_update(). - */ - const unsigned int max_allowed = 512; - - if (headroom > max_allowed) - headroom = max_allowed; - - if (headroom > READ_ONCE(dev->needed_headroom)) - WRITE_ONCE(dev->needed_headroom, headroom); -} - int iptunnel_handle_offloads(struct sk_buff *skb, int gso_type_mask); static inline int iptunnel_pull_offloads(struct sk_buff *skb) diff --git a/include/net/ipv6_stubs.h b/include/net/ipv6_stubs.h index f1704385dbc1..3e7d2c0e79ca 100644 --- a/include/net/ipv6_stubs.h +++ b/include/net/ipv6_stubs.h @@ -63,7 +63,7 @@ extern const struct ipv6_stub *ipv6_stub __read_mostly; /* A stub used by bpf helpers. Similarly ugly as ipv6_stub */ struct ipv6_bpf_stub { int (*inet6_bind)(struct sock *sk, struct sockaddr *uaddr, int addr_len, - u32 flags); + bool force_bind_address_no_port, bool with_lock); struct sock *(*udp6_lib_lookup)(struct net *net, const struct in6_addr *saddr, __be16 sport, const struct in6_addr *daddr, __be16 dport, diff --git a/include/net/ndisc.h b/include/net/ndisc.h index c9e18080ca3a..6cb3e6c11132 100644 --- a/include/net/ndisc.h +++ b/include/net/ndisc.h @@ -494,7 +494,7 @@ int igmp6_event_report(struct sk_buff *skb); #ifdef CONFIG_SYSCTL int ndisc_ifinfo_sysctl_change(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); int ndisc_ifinfo_sysctl_strategy(struct ctl_table *ctl, void __user *oldval, size_t __user *oldlenp, void __user *newval, size_t newlen); diff --git a/include/net/neighbour.h b/include/net/neighbour.h index 7b4063668ec9..4a0720ddc477 100644 --- a/include/net/neighbour.h +++ b/include/net/neighbour.h @@ -387,12 +387,13 @@ void *neigh_seq_next(struct seq_file *, void *, loff_t *); void neigh_seq_stop(struct seq_file *, void *); int neigh_proc_dointvec(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); int neigh_proc_dointvec_jiffies(struct ctl_table *ctl, int write, - void *buffer, + void __user *buffer, size_t *lenp, loff_t *ppos); int neigh_proc_dointvec_ms_jiffies(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, + size_t *lenp, loff_t *ppos); int neigh_sysctl_register(struct net_device *dev, struct neigh_parms *p, proc_handler *proc_handler); diff --git a/include/net/net_namespace.h b/include/net/net_namespace.h index ac4e0f2c3978..c027c5e45e16 100644 --- a/include/net/net_namespace.h +++ b/include/net/net_namespace.h @@ -33,11 +33,9 @@ #include #include #include -#include #include #include #include -#include struct user_namespace; struct proc_dir_entry; @@ -106,8 +104,6 @@ struct net { struct hlist_head *dev_name_head; struct hlist_head *dev_index_head; - struct raw_notifier_head netdev_chain; - /* Note that @hash_mix can be read millions times per second, * it is critical that it is on a read_mostly cache line. */ @@ -163,16 +159,12 @@ struct net { #endif struct net_generic __rcu *gen; - /* Used to store attached BPF programs */ - struct netns_bpf bpf; + struct bpf_prog __rcu *flow_dissector_prog; /* Note : following structs are cache line aligned */ #ifdef CONFIG_XFRM struct netns_xfrm xfrm; #endif - - atomic64_t net_cookie; /* written once */ - #if IS_ENABLED(CONFIG_IP_VS) struct netns_ipvs *ipvs; #endif @@ -350,8 +342,7 @@ static inline struct net *read_pnet_rcu(const possible_net_t *pnet) /* Protected by net_rwsem */ #define for_each_net(VAR) \ list_for_each_entry(VAR, &net_namespace_list, list) -#define for_each_net_continue_reverse(VAR) \ - list_for_each_entry_continue_reverse(VAR, &net_namespace_list, list) + #define for_each_net_rcu(VAR) \ list_for_each_entry_rcu(VAR, &net_namespace_list, list) diff --git a/include/net/netns/bpf.h b/include/net/netns/bpf.h deleted file mode 100644 index 0ca6a1b87185..000000000000 --- a/include/net/netns/bpf.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * BPF programs attached to network namespace - */ - -#ifndef __NETNS_BPF_H__ -#define __NETNS_BPF_H__ - -#include - -struct bpf_prog; -struct bpf_prog_array; - -struct netns_bpf { - /* Array of programs to run compiled from progs or links */ - struct bpf_prog_array __rcu *run_array[MAX_NETNS_BPF_ATTACH_TYPE]; - struct bpf_prog *progs[MAX_NETNS_BPF_ATTACH_TYPE]; - struct list_head links[MAX_NETNS_BPF_ATTACH_TYPE]; -}; - -#endif /* __NETNS_BPF_H__ */ diff --git a/include/net/nfc/nci_core.h b/include/net/nfc/nci_core.h index beea7e014b15..004e49f74841 100644 --- a/include/net/nfc/nci_core.h +++ b/include/net/nfc/nci_core.h @@ -52,7 +52,7 @@ enum nci_state { #define NCI_RF_DISC_SELECT_TIMEOUT 5000 #define NCI_RF_DEACTIVATE_TIMEOUT 30000 #define NCI_CMD_TIMEOUT 5000 -#define NCI_DATA_TIMEOUT 3000 +#define NCI_DATA_TIMEOUT 700 struct nci_dev; diff --git a/include/net/pkt_sched.h b/include/net/pkt_sched.h index 663e8b78bec6..fd99650a2e22 100644 --- a/include/net/pkt_sched.h +++ b/include/net/pkt_sched.h @@ -109,6 +109,7 @@ struct qdisc_rate_table *qdisc_get_rtab(struct tc_ratespec *r, struct netlink_ext_ack *extack); void qdisc_put_rtab(struct qdisc_rate_table *tab); void qdisc_put_stab(struct qdisc_size_table *tab); +void qdisc_warn_nonwc(const char *txt, struct Qdisc *qdisc); bool sch_direct_xmit(struct sk_buff *skb, struct Qdisc *q, struct net_device *dev, struct netdev_queue *txq, spinlock_t *root_lock, bool validate); @@ -175,28 +176,4 @@ struct tc_taprio_qopt_offload *taprio_offload_get(struct tc_taprio_qopt_offload *offload); void taprio_offload_free(struct tc_taprio_qopt_offload *offload); -static inline void qdisc_warn_nonwc(const char *txt, struct Qdisc *qdisc) -{ - if (!(qdisc->flags & TCQ_F_WARN_NONWC)) { - pr_warn("%s: %s qdisc %X: is non-work-conserving?\n", - txt, qdisc->ops->id, qdisc->handle >> 16); - qdisc->flags |= TCQ_F_WARN_NONWC; - } -} - -static inline unsigned int qdisc_peek_len(struct Qdisc *sch) -{ - struct sk_buff *skb; - unsigned int len; - - skb = sch->ops->peek(sch); - if (unlikely(skb == NULL)) { - qdisc_warn_nonwc("qdisc_peek_len", sch); - return 0; - } - len = qdisc_pkt_len(skb); - - return len; -} - #endif diff --git a/include/net/request_sock.h b/include/net/request_sock.h index 8c99af5ea891..cf8b33213bbc 100644 --- a/include/net/request_sock.h +++ b/include/net/request_sock.h @@ -41,13 +41,6 @@ struct request_sock_ops { int inet_rtx_syn_ack(const struct sock *parent, struct request_sock *req); -struct saved_syn { - u32 mac_hdrlen; - u32 network_hdrlen; - u32 tcp_hdrlen; - u8 data[]; -}; - /* struct request_sock - mini sock to represent a connection request */ struct request_sock { @@ -67,7 +60,7 @@ struct request_sock { struct timer_list rsk_timer; const struct request_sock_ops *rsk_ops; struct sock *sk; - struct saved_syn *saved_syn; + u32 *saved_syn; u32 secid; u32 peer_secid; }; diff --git a/include/net/seg6.h b/include/net/seg6.h index 9d19c15e8545..640724b35273 100644 --- a/include/net/seg6.h +++ b/include/net/seg6.h @@ -57,7 +57,7 @@ extern void seg6_iptunnel_exit(void); extern int seg6_local_init(void); extern void seg6_local_exit(void); -extern bool seg6_validate_srh(struct ipv6_sr_hdr *srh, int len, bool reduced); +extern bool seg6_validate_srh(struct ipv6_sr_hdr *srh, int len); extern int seg6_do_srh_encap(struct sk_buff *skb, struct ipv6_sr_hdr *osrh, int proto); extern int seg6_do_srh_inline(struct sk_buff *skb, struct ipv6_sr_hdr *osrh); diff --git a/include/net/sock.h b/include/net/sock.h index a9b502b258f0..8462ffa5a131 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -233,7 +233,7 @@ struct sock_common { /* public: */ }; -struct bpf_local_storage; +struct bpf_sk_storage; /** * struct sock - network layer representation of sockets @@ -441,15 +441,31 @@ struct sock { * Because of non atomicity rules, all * changes are protected by socket lock. */ - u8 sk_padding : 1, + unsigned int __sk_flags_offset[0]; +#ifdef __BIG_ENDIAN_BITFIELD +#define SK_FL_PROTO_SHIFT 16 +#define SK_FL_PROTO_MASK 0x00ff0000 + +#define SK_FL_TYPE_SHIFT 0 +#define SK_FL_TYPE_MASK 0x0000ffff +#else +#define SK_FL_PROTO_SHIFT 8 +#define SK_FL_PROTO_MASK 0x0000ff00 + +#define SK_FL_TYPE_SHIFT 16 +#define SK_FL_TYPE_MASK 0xffff0000 +#endif + + unsigned int sk_padding : 1, sk_kern_sock : 1, sk_no_check_tx : 1, sk_no_check_rx : 1, - sk_userlocks : 4; - u8 sk_pacing_shift; - u16 sk_type; - u16 sk_protocol; + sk_userlocks : 4, + sk_protocol : 8, + sk_type : 16; +#define SK_PROTOCOL_MAX U8_MAX u16 sk_gso_max_segs; + u8 sk_pacing_shift; unsigned long sk_lingertime; struct proto *sk_prot_creator; rwlock_t sk_callback_lock; @@ -502,7 +518,7 @@ struct sock { void (*sk_destruct)(struct sock *sk); struct sock_reuseport __rcu *sk_reuseport_cb; #ifdef CONFIG_BPF_SYSCALL - struct bpf_local_storage __rcu *sk_bpf_storage; + struct bpf_sk_storage __rcu *sk_bpf_storage; #endif struct rcu_head sk_rcu; @@ -532,44 +548,10 @@ enum sk_pacing { SK_PACING_FQ = 2, }; -/* Pointer stored in sk_user_data might not be suitable for copying - * when cloning the socket. For instance, it can point to a reference - * counted object. sk_user_data bottom bit is set if pointer must not - * be copied. - */ -#define SK_USER_DATA_NOCOPY 1UL -#define SK_USER_DATA_BPF 2UL /* Managed by BPF */ -#define SK_USER_DATA_PTRMASK ~(SK_USER_DATA_NOCOPY | SK_USER_DATA_BPF) - -/** - * sk_user_data_is_nocopy - Test if sk_user_data pointer must not be copied - * @sk: socket - */ -static inline bool sk_user_data_is_nocopy(const struct sock *sk) -{ - return ((uintptr_t)sk->sk_user_data & SK_USER_DATA_NOCOPY); -} - #define __sk_user_data(sk) ((*((void __rcu **)&(sk)->sk_user_data))) -#define rcu_dereference_sk_user_data(sk) \ -({ \ - void *__tmp = rcu_dereference(__sk_user_data((sk))); \ - (void *)((uintptr_t)__tmp & SK_USER_DATA_PTRMASK); \ -}) -#define rcu_assign_sk_user_data(sk, ptr) \ -({ \ - uintptr_t __tmp = (uintptr_t)(ptr); \ - WARN_ON_ONCE(__tmp & ~SK_USER_DATA_PTRMASK); \ - rcu_assign_pointer(__sk_user_data((sk)), __tmp); \ -}) -#define rcu_assign_sk_user_data_nocopy(sk, ptr) \ -({ \ - uintptr_t __tmp = (uintptr_t)(ptr); \ - WARN_ON_ONCE(__tmp & ~SK_USER_DATA_PTRMASK); \ - rcu_assign_pointer(__sk_user_data((sk)), \ - __tmp | SK_USER_DATA_NOCOPY); \ -}) +#define rcu_dereference_sk_user_data(sk) rcu_dereference(__sk_user_data((sk))) +#define rcu_assign_sk_user_data(sk, ptr) rcu_assign_pointer(__sk_user_data((sk)), ptr) /* * SK_CAN_REUSE and SK_NO_REUSE on a socket mean that the socket is OK @@ -887,14 +869,6 @@ static inline void sock_reset_flag(struct sock *sk, enum sock_flags flag) __clear_bit(flag, &sk->sk_flags); } -static inline void sock_valbool_flag(struct sock *sk, int bit, int valbool) -{ - if (valbool) - sock_set_flag(sk, bit); - else - sock_reset_flag(sk, bit); -} - static inline bool sock_flag(const struct sock *sk, enum sock_flags flag) { return test_bit(flag, &sk->sk_flags); @@ -1730,7 +1704,6 @@ void sock_rfree(struct sk_buff *skb); void sock_efree(struct sk_buff *skb); #ifdef CONFIG_INET void sock_edemux(struct sk_buff *skb); -void sock_pfree(struct sk_buff *skb); #else #define sock_edemux sock_efree #endif @@ -2643,14 +2616,16 @@ void sock_net_set(struct sock *sk, struct net *net) write_pnet(&sk->sk_net, net); } -static inline bool -skb_sk_is_prefetched(struct sk_buff *skb) +static inline struct sock *skb_steal_sock(struct sk_buff *skb) { -#ifdef CONFIG_INET - return skb->destructor == sock_pfree; -#else - return false; -#endif /* CONFIG_INET */ + if (skb->sk) { + struct sock *sk = skb->sk; + + skb->destructor = NULL; + skb->sk = NULL; + return sk; + } + return NULL; } /* This helper checks if a socket is a full socket, @@ -2661,35 +2636,6 @@ static inline bool sk_fullsock(const struct sock *sk) return (1 << sk->sk_state) & ~(TCPF_TIME_WAIT | TCPF_NEW_SYN_RECV); } -static inline bool -sk_is_refcounted(struct sock *sk) -{ - /* Only full sockets have sk->sk_flags. */ - return !sk_fullsock(sk) || !sock_flag(sk, SOCK_RCU_FREE); -} - -/** - * skb_steal_sock - * @skb to steal the socket from - * @refcounted is set to true if the socket is reference-counted - */ -static inline struct sock * -skb_steal_sock(struct sk_buff *skb, bool *refcounted) -{ - if (skb->sk) { - struct sock *sk = skb->sk; - - *refcounted = true; - if (skb_sk_is_prefetched(skb)) - *refcounted = sk_is_refcounted(sk); - skb->destructor = NULL; - skb->sk = NULL; - return sk; - } - *refcounted = false; - return NULL; -} - /* Checks if this SKB belongs to an HW offloaded socket * and whether any SW fallbacks are required based on dev. * Check decrypted mark in case skb_orphan() cleared socket. @@ -2805,6 +2751,4 @@ static inline bool sk_dev_equal_l3scope(struct sock *sk, int dif) return false; } -int sock_bindtoindex(struct sock *sk, int ifindex, bool lock_sk); - #endif /* _SOCK_H */ diff --git a/include/net/sock_reuseport.h b/include/net/sock_reuseport.h index 3ecaa15d1850..43f4a818d88f 100644 --- a/include/net/sock_reuseport.h +++ b/include/net/sock_reuseport.h @@ -55,4 +55,6 @@ static inline bool reuseport_has_conns(struct sock *sk, bool set) return ret; } +int reuseport_get_id(struct sock_reuseport *reuse); + #endif /* _SOCK_REUSEPORT_H */ diff --git a/include/net/tcp.h b/include/net/tcp.h index 7a50f6984b80..0d4497e5b508 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -356,10 +356,10 @@ ssize_t tcp_splice_read(struct socket *sk, loff_t *ppos, /* sysctl master controller */ extern int tcp_use_userconfig_sysctl_handler(struct ctl_table *table, - int write, void *buffer, size_t *length, + int write, void __user *buffer, size_t *length, loff_t *ppos); extern int tcp_proc_delayed_ack_control(struct ctl_table *table, int write, - void *buffer, size_t *length, + void __user *buffer, size_t *length, loff_t *ppos); void tcp_enter_quickack_mode(struct sock *sk, unsigned int max_quickacks); @@ -411,7 +411,7 @@ bool tcp_peer_is_proven(struct request_sock *req, struct dst_entry *dst); void __tcp_close(struct sock *sk, long timeout); void tcp_close(struct sock *sk, long timeout); void tcp_init_sock(struct sock *sk); -void tcp_init_transfer(struct sock *sk, int bpf_op, struct sk_buff *skb); +void tcp_init_transfer(struct sock *sk, int bpf_op); __poll_t tcp_poll(struct file *file, struct socket *sock, struct poll_table_struct *wait); int tcp_getsockopt(struct sock *sk, int level, int optname, @@ -475,8 +475,7 @@ enum tcp_synack_type { struct sk_buff *tcp_make_synack(const struct sock *sk, struct dst_entry *dst, struct request_sock *req, struct tcp_fastopen_cookie *foc, - enum tcp_synack_type synack_type, - struct sk_buff *syn_skb); + enum tcp_synack_type synack_type); int tcp_disconnect(struct sock *sk, int flags); void tcp_finish_connect(struct sock *sk, struct sk_buff *skb); @@ -721,7 +720,7 @@ static inline void tcp_fast_path_check(struct sock *sk) static inline u32 tcp_rto_min(struct sock *sk) { const struct dst_entry *dst = __sk_dst_get(sk); - u32 rto_min = inet_csk(sk)->icsk_rto_min; + u32 rto_min = TCP_RTO_MIN; if (dst && dst_metric_locked(dst, RTAX_RTO_MIN)) rto_min = dst_metric_rtt(dst, RTAX_RTO_MIN); @@ -1035,7 +1034,6 @@ enum tcp_ca_ack_event_flags { #define TCP_CONG_NON_RESTRICTED 0x1 /* Requires ECN/ECT set on all packets */ #define TCP_CONG_NEEDS_ECN 0x2 -#define TCP_CONG_MASK (TCP_CONG_NON_RESTRICTED | TCP_CONG_NEEDS_ECN) union tcp_cc_info; @@ -1121,7 +1119,7 @@ void tcp_get_available_congestion_control(char *buf, size_t len); void tcp_get_allowed_congestion_control(char *buf, size_t len); int tcp_set_allowed_congestion_control(char *allowed); int tcp_set_congestion_control(struct sock *sk, const char *name, bool load, - bool cap_net_admin); + bool reinit, bool cap_net_admin); u32 tcp_slow_start(struct tcp_sock *tp, u32 acked); void tcp_cong_avoid_ai(struct tcp_sock *tp, u32 w, u32 acked); @@ -1130,7 +1128,6 @@ u32 tcp_reno_undo_cwnd(struct sock *sk); void tcp_reno_cong_avoid(struct sock *sk, u32 ack, u32 acked); extern struct tcp_congestion_ops tcp_reno; -struct tcp_congestion_ops *tcp_ca_find(const char *name); struct tcp_congestion_ops *tcp_ca_find_key(u32 key); u32 tcp_ca_get_key_by_name(struct net *net, const char *name, bool *ecn_ca); #ifdef CONFIG_INET @@ -1959,7 +1956,6 @@ struct tcp_iter_state { struct seq_net_private p; enum tcp_seq_states state; struct sock *syn_wait_sk; - struct tcp_seq_afinfo *bpf_seq_afinfo; int bucket, offset, sbucket, num; loff_t last_pos; }; @@ -2049,8 +2045,7 @@ struct tcp_request_sock_ops { int (*send_synack)(const struct sock *sk, struct dst_entry *dst, struct flowi *fl, struct request_sock *req, struct tcp_fastopen_cookie *foc, - enum tcp_synack_type synack_type, - struct sk_buff *syn_skb); + enum tcp_synack_type synack_type); }; extern const struct tcp_request_sock_ops tcp_request_sock_ipv4_ops; @@ -2243,75 +2238,17 @@ void tcp_update_ulp(struct sock *sk, struct proto *p, __MODULE_INFO(alias, alias_userspace, name); \ __MODULE_INFO(alias, alias_tcp_ulp, "tcp-ulp-" name) -#ifdef CONFIG_NET_SOCK_MSG struct sk_msg; struct sk_psock; -#ifdef CONFIG_BPF_SYSCALL -struct proto *tcp_bpf_get_proto(struct sock *sk, struct sk_psock *psock); -void tcp_bpf_clone(const struct sock *sk, struct sock *newsk); -#endif /* CONFIG_BPF_SYSCALL */ - +int tcp_bpf_init(struct sock *sk); +void tcp_bpf_reinit(struct sock *sk); int tcp_bpf_sendmsg_redir(struct sock *sk, struct sk_msg *msg, u32 bytes, int flags); +int tcp_bpf_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, + int nonblock, int flags, int *addr_len); int __tcp_bpf_recvmsg(struct sock *sk, struct sk_psock *psock, struct msghdr *msg, int len, int flags); -#endif /* CONFIG_NET_SOCK_MSG */ - -#if !defined(CONFIG_BPF_SYSCALL) || !defined(CONFIG_NET_SOCK_MSG) -static inline void tcp_bpf_clone(const struct sock *sk, struct sock *newsk) -{ -} -#endif - -#ifdef CONFIG_CGROUP_BPF -/* Copy the listen sk's HDR_OPT_CB flags to its child. - * - * During 3-Way-HandShake, the synack is usually sent from - * the listen sk with the HDR_OPT_CB flags set so that - * bpf-prog will be called to write the BPF hdr option. - * - * In fastopen, the child sk is used to send synack instead - * of the listen sk. Thus, inheriting the HDR_OPT_CB flags - * from the listen sk gives the bpf-prog a chance to write - * BPF hdr option in the synack pkt during fastopen. - * - * Both fastopen and non-fastopen child will inherit the - * HDR_OPT_CB flags to keep the bpf-prog having a consistent - * behavior when deciding to clear this cb flags (or not) - * during the PASSIVE_ESTABLISHED_CB. - * - * In the future, other cb flags could be inherited here also. - */ -static inline void bpf_skops_init_child(const struct sock *sk, - struct sock *child) -{ - tcp_sk(child)->bpf_sock_ops_cb_flags = - tcp_sk(sk)->bpf_sock_ops_cb_flags & - (BPF_SOCK_OPS_PARSE_ALL_HDR_OPT_CB_FLAG | - BPF_SOCK_OPS_PARSE_UNKNOWN_HDR_OPT_CB_FLAG | - BPF_SOCK_OPS_WRITE_HDR_OPT_CB_FLAG); -} - -static inline void bpf_skops_init_skb(struct bpf_sock_ops_kern *skops, - struct sk_buff *skb, - unsigned int end_offset) -{ - skops->skb = skb; - skops->skb_data_end = skb->data + end_offset; -} -#else -static inline void bpf_skops_init_child(const struct sock *sk, - struct sock *child) -{ -} - -static inline void bpf_skops_init_skb(struct bpf_sock_ops_kern *skops, - struct sk_buff *skb, - unsigned int end_offset) -{ -} -#endif /* Call BPF_SOCK_OPS program that returns an int. If the return value * is < 0, then the BPF op failed (for example if the loaded BPF diff --git a/include/net/udp.h b/include/net/udp.h index 429084c8a561..4327ca0754e0 100644 --- a/include/net/udp.h +++ b/include/net/udp.h @@ -300,7 +300,7 @@ struct sk_buff *skb_udp_tunnel_segment(struct sk_buff *skb, int udp_lib_getsockopt(struct sock *sk, int level, int optname, char __user *optval, int __user *optlen); int udp_lib_setsockopt(struct sock *sk, int level, int optname, - sockptr_t optval, unsigned int optlen, + char __user *optval, unsigned int optlen, int (*push_pending_frames)(struct sock *)); struct sock *udp4_lib_lookup(struct net *net, __be32 saddr, __be16 sport, __be32 daddr, __be16 dport, int dif); @@ -441,7 +441,6 @@ struct udp_seq_afinfo { struct udp_iter_state { struct seq_net_private p; int bucket; - struct udp_seq_afinfo *bpf_seq_afinfo; }; void *udp_seq_start(struct seq_file *seq, loff_t *pos); @@ -519,9 +518,4 @@ drop: return NULL; } -#ifdef CONFIG_BPF_SYSCALL -struct sk_psock; -struct proto *udp_bpf_get_proto(struct sock *sk, struct sk_psock *psock); -#endif - #endif /* _UDP_H */ diff --git a/include/net/udp_tunnel.h b/include/net/udp_tunnel.h index bb22a3ce1431..27bf9f4dd1d4 100644 --- a/include/net/udp_tunnel.h +++ b/include/net/udp_tunnel.h @@ -115,7 +115,6 @@ struct udp_tunnel_info { unsigned short type; sa_family_t sa_family; __be16 port; - u8 hw_priv; }; /* Notify network devices of offloadable types */ @@ -183,140 +182,4 @@ static inline void udp_tunnel_encap_enable(struct socket *sock) udp_encap_enable(); } -#define UDP_TUNNEL_NIC_MAX_TABLES 4 - -enum udp_tunnel_nic_info_flags { - /* Device callbacks may sleep */ - UDP_TUNNEL_NIC_INFO_MAY_SLEEP = BIT(0), - /* Device only supports offloads when it's open, all ports - * will be removed before close and re-added after open. - */ - UDP_TUNNEL_NIC_INFO_OPEN_ONLY = BIT(1), - /* Device supports only IPv4 tunnels */ - UDP_TUNNEL_NIC_INFO_IPV4_ONLY = BIT(2), -}; - -/** - * struct udp_tunnel_nic_info - driver UDP tunnel offload information - * @set_port: callback for adding a new port - * @unset_port: callback for removing a port - * @sync_table: callback for syncing the entire port table at once - * @flags: device flags from enum udp_tunnel_nic_info_flags - * @tables: UDP port tables this device has - * @tables.n_entries: number of entries in this table - * @tables.tunnel_types: types of tunnels this table accepts - * - * Drivers are expected to provide either @set_port and @unset_port callbacks - * or the @sync_table callback. Callbacks are invoked with rtnl lock held. - * - * Known limitations: - * - UDP tunnel port notifications are fundamentally best-effort - - * it is likely the driver will both see skbs which use a UDP tunnel port, - * while not being a tunneled skb, and tunnel skbs from other ports - - * drivers should only use these ports for non-critical RX-side offloads, - * e.g. the checksum offload; - * - none of the devices care about the socket family at present, so we don't - * track it. Please extend this code if you care. - */ -struct udp_tunnel_nic_info { - /* one-by-one */ - int (*set_port)(struct net_device *dev, - unsigned int table, unsigned int entry, - struct udp_tunnel_info *ti); - int (*unset_port)(struct net_device *dev, - unsigned int table, unsigned int entry, - struct udp_tunnel_info *ti); - - /* all at once */ - int (*sync_table)(struct net_device *dev, unsigned int table); - - unsigned int flags; - - struct udp_tunnel_nic_table_info { - unsigned int n_entries; - unsigned int tunnel_types; - } tables[UDP_TUNNEL_NIC_MAX_TABLES]; -}; - -/* UDP tunnel module dependencies - * - * Tunnel drivers are expected to have a hard dependency on the udp_tunnel - * module. NIC drivers are not, they just attach their - * struct udp_tunnel_nic_info to the netdev and wait for callbacks to come. - * Loading a tunnel driver will cause the udp_tunnel module to be loaded - * and only then will all the required state structures be allocated. - * Since we want a weak dependency from the drivers and the core to udp_tunnel - * we call things through the following stubs. - */ -struct udp_tunnel_nic_ops { - void (*get_port)(struct net_device *dev, unsigned int table, - unsigned int idx, struct udp_tunnel_info *ti); - void (*set_port_priv)(struct net_device *dev, unsigned int table, - unsigned int idx, u8 priv); - void (*add_port)(struct net_device *dev, struct udp_tunnel_info *ti); - void (*del_port)(struct net_device *dev, struct udp_tunnel_info *ti); - void (*reset_ntf)(struct net_device *dev); -}; - -#ifdef CONFIG_INET -extern const struct udp_tunnel_nic_ops *udp_tunnel_nic_ops; -#else -#define udp_tunnel_nic_ops ((struct udp_tunnel_nic_ops *)NULL) -#endif - -static inline void -udp_tunnel_nic_get_port(struct net_device *dev, unsigned int table, - unsigned int idx, struct udp_tunnel_info *ti) -{ - /* This helper is used from .sync_table, we indicate empty entries - * by zero'ed @ti. Drivers which need to know the details of a port - * when it gets deleted should use the .set_port / .unset_port - * callbacks. - * Zero out here, otherwise !CONFIG_INET causes uninitilized warnings. - */ - memset(ti, 0, sizeof(*ti)); - - if (udp_tunnel_nic_ops) - udp_tunnel_nic_ops->get_port(dev, table, idx, ti); -} - -static inline void -udp_tunnel_nic_set_port_priv(struct net_device *dev, unsigned int table, - unsigned int idx, u8 priv) -{ - if (udp_tunnel_nic_ops) - udp_tunnel_nic_ops->set_port_priv(dev, table, idx, priv); -} - -static inline void -udp_tunnel_nic_add_port(struct net_device *dev, struct udp_tunnel_info *ti) -{ - if (udp_tunnel_nic_ops) - udp_tunnel_nic_ops->add_port(dev, ti); -} - -static inline void -udp_tunnel_nic_del_port(struct net_device *dev, struct udp_tunnel_info *ti) -{ - if (udp_tunnel_nic_ops) - udp_tunnel_nic_ops->del_port(dev, ti); -} - -/** - * udp_tunnel_nic_reset_ntf() - device-originating reset notification - * @dev: network interface device structure - * - * Called by the driver to inform the core that the entire UDP tunnel port - * state has been lost, usually due to device reset. Core will assume device - * forgot all the ports and issue .set_port and .sync_table callbacks as - * necessary. - * - * This function must be called with rtnl lock held, and will issue all - * the callbacks before returning. - */ -static inline void udp_tunnel_nic_reset_ntf(struct net_device *dev) -{ - if (udp_tunnel_nic_ops) - udp_tunnel_nic_ops->reset_ntf(dev); -} #endif diff --git a/include/net/xdp.h b/include/net/xdp.h index 7a5f4405d251..40c6d3398458 100644 --- a/include/net/xdp.h +++ b/include/net/xdp.h @@ -6,8 +6,6 @@ #ifndef __LINUX_NET_XDP_H__ #define __LINUX_NET_XDP_H__ -#include /* skb_shared_info */ - /** * DOC: XDP RX-queue information * @@ -65,10 +63,6 @@ struct xdp_rxq_info { struct xdp_mem_info mem; } ____cacheline_aligned; /* perf critical, avoid false-sharing */ -struct xdp_txq_info { - struct net_device *dev; -}; - struct xdp_buff { void *data; void *data_end; @@ -76,26 +70,13 @@ struct xdp_buff { void *data_hard_start; unsigned long handle; struct xdp_rxq_info *rxq; - struct xdp_txq_info *txq; - u32 frame_sz; /* frame size to deduce data_hard_end/reserved tailroom*/ }; -/* Reserve memory area at end-of data area. - * - * This macro reserves tailroom in the XDP buffer by limiting the - * XDP/BPF data access to data_hard_end. Notice same area (and size) - * is used for XDP_PASS, when constructing the SKB via build_skb(). - */ -#define xdp_data_hard_end(xdp) \ - ((xdp)->data_hard_start + (xdp)->frame_sz - \ - SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) - struct xdp_frame { void *data; u16 len; u16 headroom; - u32 metasize:8; - u32 frame_sz:24; + u16 metasize; /* Lifetime of xdp_rxq_info is limited to NAPI/enqueue time, * while mem info is valid on remote CPU. */ @@ -103,11 +84,6 @@ struct xdp_frame { struct net_device *dev_rx; /* used by cpumap */ }; -struct xdp_cpumap_stats { - unsigned int pass; - unsigned int drop; -}; - /* Clear kernel pointers in xdp_frame */ static inline void xdp_scrub_frame(struct xdp_frame *frame) { @@ -115,63 +91,33 @@ static inline void xdp_scrub_frame(struct xdp_frame *frame) frame->dev_rx = NULL; } -/* Avoids inlining WARN macro in fast-path */ -void xdp_warn(const char *msg, const char *func, const int line); -#define XDP_WARN(msg) xdp_warn(msg, __func__, __LINE__) - struct xdp_frame *xdp_convert_zc_to_xdp_frame(struct xdp_buff *xdp); +/* Convert xdp_buff to xdp_frame */ static inline -void xdp_convert_frame_to_buff(struct xdp_frame *frame, struct xdp_buff *xdp) +struct xdp_frame *convert_to_xdp_frame(struct xdp_buff *xdp) { - xdp->data_hard_start = frame->data - frame->headroom - sizeof(*frame); - xdp->data = frame->data; - xdp->data_end = frame->data + frame->len; - xdp->data_meta = frame->data - frame->metasize; - xdp->frame_sz = frame->frame_sz; -} + struct xdp_frame *xdp_frame; + int metasize; + int headroom; -static inline -int xdp_update_frame_from_buff(struct xdp_buff *xdp, - struct xdp_frame *xdp_frame) -{ - int metasize, headroom; + if (xdp->rxq->mem.type == MEM_TYPE_ZERO_COPY) + return xdp_convert_zc_to_xdp_frame(xdp); /* Assure headroom is available for storing info */ headroom = xdp->data - xdp->data_hard_start; metasize = xdp->data - xdp->data_meta; metasize = metasize > 0 ? metasize : 0; if (unlikely((headroom - metasize) < sizeof(*xdp_frame))) - return -ENOSPC; + return NULL; - /* Catch if driver didn't reserve tailroom for skb_shared_info */ - if (unlikely(xdp->data_end > xdp_data_hard_end(xdp))) { - XDP_WARN("Driver BUG: missing reserved tailroom"); - return -ENOSPC; - } + /* Store info in top of packet */ + xdp_frame = xdp->data_hard_start; xdp_frame->data = xdp->data; xdp_frame->len = xdp->data_end - xdp->data; xdp_frame->headroom = headroom - sizeof(*xdp_frame); xdp_frame->metasize = metasize; - xdp_frame->frame_sz = xdp->frame_sz; - - return 0; -} - -/* Convert xdp_buff to xdp_frame */ -static inline -struct xdp_frame *xdp_convert_buff_to_frame(struct xdp_buff *xdp) -{ - struct xdp_frame *xdp_frame; - - if (xdp->rxq->mem.type == MEM_TYPE_ZERO_COPY) - return xdp_convert_zc_to_xdp_frame(xdp); - - /* Store info in top of packet */ - xdp_frame = xdp->data_hard_start; - if (unlikely(xdp_update_frame_from_buff(xdp, xdp_frame) < 0)) - return NULL; /* rxq only valid until napi_schedule ends, convert to xdp_mem_info */ xdp_frame->mem = xdp->rxq->mem; @@ -235,6 +181,4 @@ bool xdp_attachment_flags_ok(struct xdp_attachment_info *info, void xdp_attachment_setup(struct xdp_attachment_info *info, struct netdev_bpf *bpf); -#define DEV_MAP_BULK_SIZE 16 - #endif /* __LINUX_NET_XDP_H__ */ diff --git a/include/net/xdp_sock.h b/include/net/xdp_sock.h index 80f53acb15ac..c9398ce7960f 100644 --- a/include/net/xdp_sock.h +++ b/include/net/xdp_sock.h @@ -66,10 +66,14 @@ struct xdp_umem { struct list_head xsk_list; }; -struct xsk_map { - struct bpf_map map; - spinlock_t lock; /* Synchronize map updates */ - struct xdp_sock *xsk_map[]; +/* Nodes are linked in the struct xdp_sock map_list field, and used to + * track which maps a certain socket reside in. + */ +struct xsk_map; +struct xsk_map_node { + struct list_head node; + struct xsk_map *map; + struct xdp_sock **map_entry; }; struct xdp_sock { @@ -105,6 +109,9 @@ struct xdp_sock { struct xdp_buff; #ifdef CONFIG_XDP_SOCKETS int xsk_generic_rcv(struct xdp_sock *xs, struct xdp_buff *xdp); +int xsk_rcv(struct xdp_sock *xs, struct xdp_buff *xdp); +void xsk_flush(struct xdp_sock *xs); +bool xsk_is_setup_for_bpf_map(struct xdp_sock *xs); /* Used from netdev driver */ bool xsk_umem_has_addrs(struct xdp_umem *umem, u32 cnt); u64 *xsk_umem_peek_addr(struct xdp_umem *umem, u64 *addr); @@ -123,21 +130,10 @@ void xsk_clear_rx_need_wakeup(struct xdp_umem *umem); void xsk_clear_tx_need_wakeup(struct xdp_umem *umem); bool xsk_umem_uses_need_wakeup(struct xdp_umem *umem); -int __xsk_map_redirect(struct xdp_sock *xs, struct xdp_buff *xdp); -void __xsk_map_flush(void); - -static inline struct xdp_sock *__xsk_map_lookup_elem(struct bpf_map *map, - u32 key) -{ - struct xsk_map *m = container_of(map, struct xsk_map, map); - struct xdp_sock *xs; - - if (key >= map->max_entries) - return NULL; - - xs = READ_ONCE(m->xsk_map[key]); - return xs; -} +void xsk_map_try_sock_delete(struct xsk_map *map, struct xdp_sock *xs, + struct xdp_sock **map_entry); +int xsk_map_inc(struct xsk_map *map); +void xsk_map_put(struct xsk_map *map); static inline u64 xsk_umem_extract_addr(u64 addr) { @@ -228,6 +224,20 @@ static inline int xsk_generic_rcv(struct xdp_sock *xs, struct xdp_buff *xdp) return -ENOTSUPP; } +static inline int xsk_rcv(struct xdp_sock *xs, struct xdp_buff *xdp) +{ + return -ENOTSUPP; +} + +static inline void xsk_flush(struct xdp_sock *xs) +{ +} + +static inline bool xsk_is_setup_for_bpf_map(struct xdp_sock *xs) +{ + return false; +} + static inline bool xsk_umem_has_addrs(struct xdp_umem *umem, u32 cnt) { return false; @@ -347,20 +357,6 @@ static inline u64 xsk_umem_adjust_offset(struct xdp_umem *umem, u64 handle, return 0; } -static inline int __xsk_map_redirect(struct xdp_sock *xs, struct xdp_buff *xdp) -{ - return -EOPNOTSUPP; -} - -static inline void __xsk_map_flush(void) -{ -} - -static inline struct xdp_sock *__xsk_map_lookup_elem(struct bpf_map *map, - u32 key) -{ - return NULL; -} #endif /* CONFIG_XDP_SOCKETS */ #endif /* _LINUX_XDP_SOCK_H */ diff --git a/include/scsi/libsas.h b/include/scsi/libsas.h index 8461fad88a11..4e2d61e8fb1e 100644 --- a/include/scsi/libsas.h +++ b/include/scsi/libsas.h @@ -620,24 +620,6 @@ extern struct sas_task *sas_alloc_task(gfp_t flags); extern struct sas_task *sas_alloc_slow_task(gfp_t flags); extern void sas_free_task(struct sas_task *task); -static inline struct request *sas_task_find_rq(struct sas_task *task) -{ - struct scsi_cmnd *scmd; - - if (task->task_proto & SAS_PROTOCOL_STP_ALL) { - struct ata_queued_cmd *qc = task->uldd_task; - - scmd = qc ? qc->scsicmd : NULL; - } else { - scmd = task->uldd_task; - } - - if (!scmd) - return NULL; - - return scsi_cmd_to_rq(scmd); -} - struct sas_domain_function_template { /* The class calls these to notify the LLDD of an event. */ void (*lldd_port_formed)(struct asd_sas_phy *); diff --git a/include/trace/events/cgroup.h b/include/trace/events/cgroup.h index 7f42a3de59e6..a566cc521476 100644 --- a/include/trace/events/cgroup.h +++ b/include/trace/events/cgroup.h @@ -66,7 +66,7 @@ DECLARE_EVENT_CLASS(cgroup, TP_fast_assign( __entry->root = cgrp->root->hierarchy_id; - __entry->id = cgroup_id(cgrp); + __entry->id = cgrp->id; __entry->level = cgrp->level; __assign_str(path, path); ), @@ -135,7 +135,7 @@ DECLARE_EVENT_CLASS(cgroup_migrate, TP_fast_assign( __entry->dst_root = dst_cgrp->root->hierarchy_id; - __entry->dst_id = cgroup_id(dst_cgrp); + __entry->dst_id = dst_cgrp->id; __entry->dst_level = dst_cgrp->level; __assign_str(dst_path, path); __entry->pid = task->pid; @@ -179,7 +179,7 @@ DECLARE_EVENT_CLASS(cgroup_event, TP_fast_assign( __entry->root = cgrp->root->hierarchy_id; - __entry->id = cgroup_id(cgrp); + __entry->id = cgrp->id; __entry->level = cgrp->level; __assign_str(path, path); __entry->val = val; diff --git a/include/trace/events/error_report.h b/include/trace/events/error_report.h deleted file mode 100644 index 96f64bf218b2..000000000000 --- a/include/trace/events/error_report.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Declarations for error reporting tracepoints. - * - * Copyright (C) 2021, Google LLC. - */ -#undef TRACE_SYSTEM -#define TRACE_SYSTEM error_report - -#if !defined(_TRACE_ERROR_REPORT_H) || defined(TRACE_HEADER_MULTI_READ) -#define _TRACE_ERROR_REPORT_H - -#include - -#ifndef __ERROR_REPORT_DECLARE_TRACE_ENUMS_ONCE_ONLY -#define __ERROR_REPORT_DECLARE_TRACE_ENUMS_ONCE_ONLY - -enum error_detector { - ERROR_DETECTOR_KFENCE, - ERROR_DETECTOR_KASAN -}; - -#endif /* __ERROR_REPORT_DECLARE_TRACE_ENUMS_ONCE_ONLY */ - -#define error_detector_list \ - EM(ERROR_DETECTOR_KFENCE, "kfence") \ - EMe(ERROR_DETECTOR_KASAN, "kasan") -/* Always end the list with an EMe. */ - -#undef EM -#undef EMe - -#define EM(a, b) TRACE_DEFINE_ENUM(a); -#define EMe(a, b) TRACE_DEFINE_ENUM(a); - -error_detector_list - -#undef EM -#undef EMe - -#define EM(a, b) { a, b }, -#define EMe(a, b) { a, b } - -#define show_error_detector_list(val) \ - __print_symbolic(val, error_detector_list) - -DECLARE_EVENT_CLASS(error_report_template, - TP_PROTO(enum error_detector error_detector, unsigned long id), - TP_ARGS(error_detector, id), - TP_STRUCT__entry(__field(enum error_detector, error_detector) - __field(unsigned long, id)), - TP_fast_assign(__entry->error_detector = error_detector; - __entry->id = id;), - TP_printk("[%s] %lx", - show_error_detector_list(__entry->error_detector), - __entry->id)); - -/** - * error_report_end - called after printing the error report - * @error_detector: short string describing the error detection tool - * @id: pseudo-unique descriptor identifying the report - * (e.g. the memory access address) - * - * This event occurs right after a debugging tool finishes printing the error - * report. - */ -DEFINE_EVENT(error_report_template, error_report_end, - TP_PROTO(enum error_detector error_detector, unsigned long id), - TP_ARGS(error_detector, id)); - -#endif /* _TRACE_ERROR_REPORT_H */ - -/* This part must be outside protection */ -#include diff --git a/include/trace/events/sock.h b/include/trace/events/sock.h index 84140f3a81a5..ad11938c0972 100644 --- a/include/trace/events/sock.h +++ b/include/trace/events/sock.h @@ -149,7 +149,7 @@ TRACE_EVENT(inet_sock_set_state, __field(__u16, sport) __field(__u16, dport) __field(__u16, family) - __field(__u16, protocol) + __field(__u8, protocol) __array(__u8, saddr, 4) __array(__u8, daddr, 4) __array(__u8, saddr_v6, 16) diff --git a/include/trace/events/writeback.h b/include/trace/events/writeback.h index 117d6b0a8494..b70c32e4a491 100644 --- a/include/trace/events/writeback.h +++ b/include/trace/events/writeback.h @@ -150,7 +150,7 @@ DEFINE_EVENT(writeback_dirty_inode_template, writeback_dirty_inode, static inline unsigned int __trace_wb_assign_cgroup(struct bdi_writeback *wb) { - return cgroup_ino(wb->memcg_css->cgroup); + return wb->memcg_css->cgroup->kn->id.ino; } static inline unsigned int __trace_wbc_assign_cgroup(struct writeback_control *wbc) @@ -258,7 +258,7 @@ TRACE_EVENT(track_foreign_dirty, __entry->ino = inode ? inode->i_ino : 0; __entry->memcg_id = wb->memcg_css->id; __entry->cgroup_ino = __trace_wb_assign_cgroup(wb); - __entry->page_cgroup_ino = cgroup_ino(page->mem_cgroup->css.cgroup); + __entry->page_cgroup_ino = page->mem_cgroup->css.cgroup->kn->id.ino; ), TP_printk("bdi %s[%llu]: ino=%lu memcg_id=%u cgroup_ino=%u page_cgroup_ino=%u", diff --git a/include/trace/events/xdp.h b/include/trace/events/xdp.h index 182b9e20cdff..c79943e82a54 100644 --- a/include/trace/events/xdp.h +++ b/include/trace/events/xdp.h @@ -79,26 +79,14 @@ TRACE_EVENT(xdp_bulk_tx, __entry->sent, __entry->drops, __entry->err) ); -#ifndef __DEVMAP_OBJ_TYPE -#define __DEVMAP_OBJ_TYPE -struct _bpf_dtab_netdev { - struct net_device *dev; -}; -#endif /* __DEVMAP_OBJ_TYPE */ - -#define devmap_ifindex(tgt, map) \ - (((map->map_type == BPF_MAP_TYPE_DEVMAP || \ - map->map_type == BPF_MAP_TYPE_DEVMAP_HASH)) ? \ - ((struct _bpf_dtab_netdev *)tgt)->dev->ifindex : 0) - DECLARE_EVENT_CLASS(xdp_redirect_template, TP_PROTO(const struct net_device *dev, const struct bpf_prog *xdp, - const void *tgt, int err, - const struct bpf_map *map, u32 index), + int to_ifindex, int err, + const struct bpf_map *map, u32 map_index), - TP_ARGS(dev, xdp, tgt, err, map, index), + TP_ARGS(dev, xdp, to_ifindex, err, map, map_index), TP_STRUCT__entry( __field(int, prog_id) @@ -115,71 +103,96 @@ DECLARE_EVENT_CLASS(xdp_redirect_template, __entry->act = XDP_REDIRECT; __entry->ifindex = dev->ifindex; __entry->err = err; - __entry->to_ifindex = map ? devmap_ifindex(tgt, map) : - index; + __entry->to_ifindex = to_ifindex; __entry->map_id = map ? map->id : 0; - __entry->map_index = map ? index : 0; + __entry->map_index = map_index; ), - TP_printk("prog_id=%d action=%s ifindex=%d to_ifindex=%d err=%d" - " map_id=%d map_index=%d", + TP_printk("prog_id=%d action=%s ifindex=%d to_ifindex=%d err=%d", __entry->prog_id, __print_symbolic(__entry->act, __XDP_ACT_SYM_TAB), __entry->ifindex, __entry->to_ifindex, - __entry->err, __entry->map_id, __entry->map_index) + __entry->err) ); DEFINE_EVENT(xdp_redirect_template, xdp_redirect, TP_PROTO(const struct net_device *dev, const struct bpf_prog *xdp, - const void *tgt, int err, - const struct bpf_map *map, u32 index), - TP_ARGS(dev, xdp, tgt, err, map, index) + int to_ifindex, int err, + const struct bpf_map *map, u32 map_index), + TP_ARGS(dev, xdp, to_ifindex, err, map, map_index) ); DEFINE_EVENT(xdp_redirect_template, xdp_redirect_err, TP_PROTO(const struct net_device *dev, const struct bpf_prog *xdp, - const void *tgt, int err, - const struct bpf_map *map, u32 index), - TP_ARGS(dev, xdp, tgt, err, map, index) + int to_ifindex, int err, + const struct bpf_map *map, u32 map_index), + TP_ARGS(dev, xdp, to_ifindex, err, map, map_index) ); #define _trace_xdp_redirect(dev, xdp, to) \ - trace_xdp_redirect(dev, xdp, NULL, 0, NULL, to); + trace_xdp_redirect(dev, xdp, to, 0, NULL, 0); #define _trace_xdp_redirect_err(dev, xdp, to, err) \ - trace_xdp_redirect_err(dev, xdp, NULL, err, NULL, to); + trace_xdp_redirect_err(dev, xdp, to, err, NULL, 0); -#define _trace_xdp_redirect_map(dev, xdp, to, map, index) \ - trace_xdp_redirect(dev, xdp, to, 0, map, index); - -#define _trace_xdp_redirect_map_err(dev, xdp, to, map, index, err) \ - trace_xdp_redirect_err(dev, xdp, to, err, map, index); - -/* not used anymore, but kept around so as not to break old programs */ -DEFINE_EVENT(xdp_redirect_template, xdp_redirect_map, +DEFINE_EVENT_PRINT(xdp_redirect_template, xdp_redirect_map, TP_PROTO(const struct net_device *dev, const struct bpf_prog *xdp, - const void *tgt, int err, - const struct bpf_map *map, u32 index), - TP_ARGS(dev, xdp, tgt, err, map, index) + int to_ifindex, int err, + const struct bpf_map *map, u32 map_index), + TP_ARGS(dev, xdp, to_ifindex, err, map, map_index), + TP_printk("prog_id=%d action=%s ifindex=%d to_ifindex=%d err=%d" + " map_id=%d map_index=%d", + __entry->prog_id, + __print_symbolic(__entry->act, __XDP_ACT_SYM_TAB), + __entry->ifindex, __entry->to_ifindex, + __entry->err, + __entry->map_id, __entry->map_index) ); -DEFINE_EVENT(xdp_redirect_template, xdp_redirect_map_err, +DEFINE_EVENT_PRINT(xdp_redirect_template, xdp_redirect_map_err, TP_PROTO(const struct net_device *dev, const struct bpf_prog *xdp, - const void *tgt, int err, - const struct bpf_map *map, u32 index), - TP_ARGS(dev, xdp, tgt, err, map, index) + int to_ifindex, int err, + const struct bpf_map *map, u32 map_index), + TP_ARGS(dev, xdp, to_ifindex, err, map, map_index), + TP_printk("prog_id=%d action=%s ifindex=%d to_ifindex=%d err=%d" + " map_id=%d map_index=%d", + __entry->prog_id, + __print_symbolic(__entry->act, __XDP_ACT_SYM_TAB), + __entry->ifindex, __entry->to_ifindex, + __entry->err, + __entry->map_id, __entry->map_index) ); +#ifndef __DEVMAP_OBJ_TYPE +#define __DEVMAP_OBJ_TYPE +struct _bpf_dtab_netdev { + struct net_device *dev; +}; +#endif /* __DEVMAP_OBJ_TYPE */ + +#define devmap_ifindex(fwd, map) \ + ((map->map_type == BPF_MAP_TYPE_DEVMAP || \ + map->map_type == BPF_MAP_TYPE_DEVMAP_HASH) ? \ + ((struct _bpf_dtab_netdev *)fwd)->dev->ifindex : 0) + +#define _trace_xdp_redirect_map(dev, xdp, fwd, map, idx) \ + trace_xdp_redirect_map(dev, xdp, devmap_ifindex(fwd, map), \ + 0, map, idx) + +#define _trace_xdp_redirect_map_err(dev, xdp, fwd, map, idx, err) \ + trace_xdp_redirect_map_err(dev, xdp, devmap_ifindex(fwd, map), \ + err, map, idx) + TRACE_EVENT(xdp_cpumap_kthread, TP_PROTO(int map_id, unsigned int processed, unsigned int drops, - int sched, struct xdp_cpumap_stats *xdp_stats), + int sched), - TP_ARGS(map_id, processed, drops, sched, xdp_stats), + TP_ARGS(map_id, processed, drops, sched), TP_STRUCT__entry( __field(int, map_id) @@ -188,8 +201,6 @@ TRACE_EVENT(xdp_cpumap_kthread, __field(unsigned int, drops) __field(unsigned int, processed) __field(int, sched) - __field(unsigned int, xdp_pass) - __field(unsigned int, xdp_drop) ), TP_fast_assign( @@ -199,20 +210,16 @@ TRACE_EVENT(xdp_cpumap_kthread, __entry->drops = drops; __entry->processed = processed; __entry->sched = sched; - __entry->xdp_pass = xdp_stats->pass; - __entry->xdp_drop = xdp_stats->drop; ), TP_printk("kthread" " cpu=%d map_id=%d action=%s" " processed=%u drops=%u" - " sched=%d" - " xdp_pass=%u xdp_drop=%u", + " sched=%d", __entry->cpu, __entry->map_id, __print_symbolic(__entry->act, __XDP_ACT_SYM_TAB), __entry->processed, __entry->drops, - __entry->sched, - __entry->xdp_pass, __entry->xdp_drop) + __entry->sched) ); TRACE_EVENT(xdp_cpumap_enqueue, @@ -252,38 +259,43 @@ TRACE_EVENT(xdp_cpumap_enqueue, TRACE_EVENT(xdp_devmap_xmit, - TP_PROTO(const struct net_device *from_dev, - const struct net_device *to_dev, - int sent, int drops, int err), + TP_PROTO(const struct bpf_map *map, u32 map_index, + int sent, int drops, + const struct net_device *from_dev, + const struct net_device *to_dev, int err), - TP_ARGS(from_dev, to_dev, sent, drops, err), + TP_ARGS(map, map_index, sent, drops, from_dev, to_dev, err), TP_STRUCT__entry( - __field(int, from_ifindex) + __field(int, map_id) __field(u32, act) - __field(int, to_ifindex) + __field(u32, map_index) __field(int, drops) __field(int, sent) + __field(int, from_ifindex) + __field(int, to_ifindex) __field(int, err) ), TP_fast_assign( - __entry->from_ifindex = from_dev->ifindex; + __entry->map_id = map->id; __entry->act = XDP_REDIRECT; - __entry->to_ifindex = to_dev->ifindex; + __entry->map_index = map_index; __entry->drops = drops; __entry->sent = sent; + __entry->from_ifindex = from_dev->ifindex; + __entry->to_ifindex = to_dev->ifindex; __entry->err = err; ), TP_printk("ndo_xdp_xmit" - " from_ifindex=%d to_ifindex=%d action=%s" + " map_id=%d map_index=%d action=%s" " sent=%d drops=%d" - " err=%d", - __entry->from_ifindex, __entry->to_ifindex, + " from_ifindex=%d to_ifindex=%d err=%d", + __entry->map_id, __entry->map_index, __print_symbolic(__entry->act, __XDP_ACT_SYM_TAB), __entry->sent, __entry->drops, - __entry->err) + __entry->from_ifindex, __entry->to_ifindex, __entry->err) ); /* Expect users already include , but not xdp_priv.h */ diff --git a/include/uapi/asm-generic/socket.h b/include/uapi/asm-generic/socket.h index 645606824258..77f7c1638eb1 100644 --- a/include/uapi/asm-generic/socket.h +++ b/include/uapi/asm-generic/socket.h @@ -119,8 +119,6 @@ #define SO_DETACH_REUSEPORT_BPF 68 -#define SO_NETNS_COOKIE 71 - #if !defined(__KERNEL__) #if __BITS_PER_LONG == 64 || (defined(__x86_64__) && defined(__ILP32__)) diff --git a/include/uapi/asm-generic/unistd.h b/include/uapi/asm-generic/unistd.h index d30344b6d2f3..674a0b04693c 100644 --- a/include/uapi/asm-generic/unistd.h +++ b/include/uapi/asm-generic/unistd.h @@ -850,15 +850,11 @@ __SYSCALL(__NR_pidfd_open, sys_pidfd_open) #define __NR_clone3 435 __SYSCALL(__NR_clone3, sys_clone3) #endif -#define __NR_close_range 436 -__SYSCALL(__NR_close_range, sys_close_range) #define __NR_process_madvise 440 __SYSCALL(__NR_process_madvise, sys_process_madvise) -#define __NR_epoll_pwait2 441 -__SC_COMP(__NR_epoll_pwait2, sys_epoll_pwait2, compat_sys_epoll_pwait2) #undef __NR_syscalls -#define __NR_syscalls 442 +#define __NR_syscalls 441 /* * 32 bit systems traditionally used different diff --git a/include/uapi/linux/audit.h b/include/uapi/linux/audit.h index 9741076aa129..a79f8c285a10 100644 --- a/include/uapi/linux/audit.h +++ b/include/uapi/linux/audit.h @@ -116,7 +116,6 @@ #define AUDIT_FANOTIFY 1331 /* Fanotify access decision */ #define AUDIT_TIME_INJOFFSET 1332 /* Timekeeping offset injected */ #define AUDIT_TIME_ADJNTPVAL 1333 /* NTP value adjustment */ -#define AUDIT_BPF 1334 /* BPF subsystem */ #define AUDIT_AVC 1400 /* SE Linux avc denial or grant */ #define AUDIT_SELINUX_ERR 1401 /* Internal SE Linux Errors */ diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h index f1307ab8c21b..a3e56509d219 100644 --- a/include/uapi/linux/bpf.h +++ b/include/uapi/linux/bpf.h @@ -73,7 +73,7 @@ struct bpf_insn { /* Key of an a BPF_MAP_TYPE_LPM_TRIE entry */ struct bpf_lpm_trie_key { __u32 prefixlen; /* up to 32 for AF_INET, 128 for AF_INET6 */ - __u8 data[]; /* Arbitrary size */ + __u8 data[0]; /* Arbitrary size */ }; struct bpf_cgroup_storage_key { @@ -81,12 +81,6 @@ struct bpf_cgroup_storage_key { __u32 attach_type; /* program attach type */ }; -union bpf_iter_link_info { - struct { - __u32 map_fd; - } map; -}; - /* BPF syscall commands, see bpf(2) man-page for details. */ enum bpf_cmd { BPF_MAP_CREATE, @@ -113,18 +107,6 @@ enum bpf_cmd { BPF_MAP_LOOKUP_AND_DELETE_ELEM, BPF_MAP_FREEZE, BPF_BTF_GET_NEXT_ID, - BPF_MAP_LOOKUP_BATCH, - BPF_MAP_LOOKUP_AND_DELETE_BATCH, - BPF_MAP_UPDATE_BATCH, - BPF_MAP_DELETE_BATCH, - BPF_LINK_CREATE, - BPF_LINK_UPDATE, - BPF_LINK_GET_FD_BY_ID, - BPF_LINK_GET_NEXT_ID, - BPF_ENABLE_STATS, - BPF_ITER_CREATE, - BPF_LINK_DETACH, - BPF_PROG_BIND_MAP, }; enum bpf_map_type { @@ -154,9 +136,6 @@ enum bpf_map_type { BPF_MAP_TYPE_STACK, BPF_MAP_TYPE_SK_STORAGE, BPF_MAP_TYPE_DEVMAP_HASH, - BPF_MAP_TYPE_STRUCT_OPS, - BPF_MAP_TYPE_RINGBUF, - BPF_MAP_TYPE_INODE_STORAGE, }; /* Note that tracing related programs such as @@ -194,12 +173,6 @@ enum bpf_prog_type { BPF_PROG_TYPE_CGROUP_SYSCTL, BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE, BPF_PROG_TYPE_CGROUP_SOCKOPT, - BPF_PROG_TYPE_TRACING, - BPF_PROG_TYPE_STRUCT_OPS, - BPF_PROG_TYPE_EXT, - BPF_PROG_TYPE_LSM, - BPF_PROG_TYPE_SK_LOOKUP, - BPF_PROG_TYPE_FUSE, }; enum bpf_attach_type { @@ -226,38 +199,11 @@ enum bpf_attach_type { BPF_CGROUP_UDP6_RECVMSG, BPF_CGROUP_GETSOCKOPT, BPF_CGROUP_SETSOCKOPT, - BPF_TRACE_RAW_TP, - BPF_TRACE_FENTRY, - BPF_TRACE_FEXIT, - BPF_MODIFY_RETURN, - BPF_LSM_MAC, - BPF_TRACE_ITER, - BPF_CGROUP_INET4_GETPEERNAME, - BPF_CGROUP_INET6_GETPEERNAME, - BPF_CGROUP_INET4_GETSOCKNAME, - BPF_CGROUP_INET6_GETSOCKNAME, - BPF_XDP_DEVMAP, - BPF_CGROUP_INET_SOCK_RELEASE, - BPF_XDP_CPUMAP, - BPF_SK_LOOKUP, - BPF_XDP, __MAX_BPF_ATTACH_TYPE }; #define MAX_BPF_ATTACH_TYPE __MAX_BPF_ATTACH_TYPE -enum bpf_link_type { - BPF_LINK_TYPE_UNSPEC = 0, - BPF_LINK_TYPE_RAW_TRACEPOINT = 1, - BPF_LINK_TYPE_TRACING = 2, - BPF_LINK_TYPE_CGROUP = 3, - BPF_LINK_TYPE_ITER = 4, - BPF_LINK_TYPE_NETNS = 5, - BPF_LINK_TYPE_XDP = 6, - - MAX_BPF_LINK_TYPE, -}; - /* cgroup-bpf attach flags used in BPF_PROG_ATTACH command * * NONE(default): No further bpf programs allowed in the subtree. @@ -281,11 +227,6 @@ enum bpf_link_type { * When children program makes decision (like picking TCP CA or sock bind) * parent program has a chance to override it. * - * With BPF_F_ALLOW_MULTI a new program is added to the end of the list of - * programs for a cgroup. Though it's possible to replace an old program at - * any position by also specifying BPF_F_REPLACE flag and position itself in - * replace_bpf_fd attribute. Old program at this position will be released. - * * A cgroup with MULTI or OVERRIDE flag allows any attach flags in sub-cgroups. * A cgroup with NONE doesn't allow any programs in sub-cgroups. * Ex1: @@ -304,7 +245,6 @@ enum bpf_link_type { */ #define BPF_F_ALLOW_OVERRIDE (1U << 0) #define BPF_F_ALLOW_MULTI (1U << 1) -#define BPF_F_REPLACE (1U << 2) /* If BPF_F_STRICT_ALIGNMENT is used in BPF_PROG_LOAD command, the * verifier will perform strict alignment checking as if the kernel @@ -348,45 +288,19 @@ enum bpf_link_type { /* The verifier internal test flag. Behavior is undefined */ #define BPF_F_TEST_STATE_FREQ (1U << 3) -/* If BPF_F_SLEEPABLE is used in BPF_PROG_LOAD command, the verifier will - * restrict map and helper usage for such programs. Sleepable BPF programs can - * only be attached to hooks where kernel execution context allows sleeping. - * Such programs are allowed to use helpers that may sleep like - * bpf_copy_from_user(). - */ -#define BPF_F_SLEEPABLE (1U << 4) - /* When BPF ldimm64's insn[0].src_reg != 0 then this can have - * the following extensions: + * two extensions: * - * insn[0].src_reg: BPF_PSEUDO_MAP_FD - * insn[0].imm: map fd - * insn[1].imm: 0 - * insn[0].off: 0 - * insn[1].off: 0 - * ldimm64 rewrite: address of map - * verifier type: CONST_PTR_TO_MAP + * insn[0].src_reg: BPF_PSEUDO_MAP_FD BPF_PSEUDO_MAP_VALUE + * insn[0].imm: map fd map fd + * insn[1].imm: 0 offset into value + * insn[0].off: 0 0 + * insn[1].off: 0 0 + * ldimm64 rewrite: address of map address of map[0]+offset + * verifier type: CONST_PTR_TO_MAP PTR_TO_MAP_VALUE */ #define BPF_PSEUDO_MAP_FD 1 -/* insn[0].src_reg: BPF_PSEUDO_MAP_VALUE - * insn[0].imm: map fd - * insn[1].imm: offset into value - * insn[0].off: 0 - * insn[1].off: 0 - * ldimm64 rewrite: address of map[0]+offset - * verifier type: PTR_TO_MAP_VALUE - */ #define BPF_PSEUDO_MAP_VALUE 2 -/* insn[0].src_reg: BPF_PSEUDO_BTF_ID - * insn[0].imm: kernel btd id of VAR - * insn[1].imm: 0 - * insn[0].off: 0 - * insn[1].off: 0 - * ldimm64 rewrite: address of the kernel variable - * verifier type: PTR_TO_BTF_ID or PTR_TO_MEM, depending on whether the var - * is struct/union. - */ -#define BPF_PSEUDO_BTF_ID 3 /* when bpf_call->src_reg == BPF_PSEUDO_CALL, bpf_call->imm == pc-relative * offset to another bpf function @@ -394,72 +308,45 @@ enum bpf_link_type { #define BPF_PSEUDO_CALL 1 /* flags for BPF_MAP_UPDATE_ELEM command */ -enum { - BPF_ANY = 0, /* create new element or update existing */ - BPF_NOEXIST = 1, /* create new element if it didn't exist */ - BPF_EXIST = 2, /* update existing element */ - BPF_F_LOCK = 4, /* spin_lock-ed map_lookup/map_update */ -}; +#define BPF_ANY 0 /* create new element or update existing */ +#define BPF_NOEXIST 1 /* create new element if it didn't exist */ +#define BPF_EXIST 2 /* update existing element */ +#define BPF_F_LOCK 4 /* spin_lock-ed map_lookup/map_update */ /* flags for BPF_MAP_CREATE command */ -enum { - BPF_F_NO_PREALLOC = (1U << 0), +#define BPF_F_NO_PREALLOC (1U << 0) /* Instead of having one common LRU list in the * BPF_MAP_TYPE_LRU_[PERCPU_]HASH map, use a percpu LRU list * which can scale and perform better. * Note, the LRU nodes (including free nodes) cannot be moved * across different LRU lists. */ - BPF_F_NO_COMMON_LRU = (1U << 1), +#define BPF_F_NO_COMMON_LRU (1U << 1) /* Specify numa node during map creation */ - BPF_F_NUMA_NODE = (1U << 2), +#define BPF_F_NUMA_NODE (1U << 2) + +#define BPF_OBJ_NAME_LEN 16U /* Flags for accessing BPF object from syscall side. */ - BPF_F_RDONLY = (1U << 3), - BPF_F_WRONLY = (1U << 4), +#define BPF_F_RDONLY (1U << 3) +#define BPF_F_WRONLY (1U << 4) /* Flag for stack_map, store build_id+offset instead of pointer */ - BPF_F_STACK_BUILD_ID = (1U << 5), +#define BPF_F_STACK_BUILD_ID (1U << 5) /* Zero-initialize hash function seed. This should only be used for testing. */ - BPF_F_ZERO_SEED = (1U << 6), +#define BPF_F_ZERO_SEED (1U << 6) /* Flags for accessing BPF object from program side. */ - BPF_F_RDONLY_PROG = (1U << 7), - BPF_F_WRONLY_PROG = (1U << 8), +#define BPF_F_RDONLY_PROG (1U << 7) +#define BPF_F_WRONLY_PROG (1U << 8) /* Clone map from listener for newly accepted socket */ - BPF_F_CLONE = (1U << 9), +#define BPF_F_CLONE (1U << 9) -/* Enable memory-mapping BPF map */ - BPF_F_MMAPABLE = (1U << 10), - -/* Share perf_event among processes */ - BPF_F_PRESERVE_ELEMS = (1U << 11), - -/* Create a map that is suitable to be an inner map with dynamic max entries */ - BPF_F_INNER_MAP = (1U << 12), -}; - -/* Flags for BPF_PROG_QUERY. */ - -/* Query effective (directly attached + inherited from ancestor cgroups) - * programs that will be executed for events within a cgroup. - * attach_flags with this flag are returned only for directly attached programs. - */ +/* flags for BPF_PROG_QUERY */ #define BPF_F_QUERY_EFFECTIVE (1U << 0) -/* Flags for BPF_PROG_TEST_RUN */ - -/* If set, run the test on the cpu specified by bpf_attr.test.cpu */ -#define BPF_F_TEST_RUN_ON_CPU (1U << 0) - -/* type for BPF_ENABLE_STATS */ -enum bpf_stats_type { - /* enabled run_time_ns and run_cnt */ - BPF_STATS_RUN_TIME = 0, -}; - enum bpf_stack_build_id_status { /* user space need an empty entry to identify end of a trace */ BPF_STACK_BUILD_ID_EMPTY = 0, @@ -479,8 +366,6 @@ struct bpf_stack_build_id { }; }; -#define BPF_OBJ_NAME_LEN 16U - union bpf_attr { struct { /* anonymous struct used by BPF_MAP_CREATE command */ __u32 map_type; /* one of enum bpf_map_type */ @@ -499,10 +384,6 @@ union bpf_attr { __u32 btf_fd; /* fd pointing to a BTF type data */ __u32 btf_key_type_id; /* BTF type_id of the key */ __u32 btf_value_type_id; /* BTF type_id of the value */ - __u32 btf_vmlinux_value_type_id;/* BTF type_id of a kernel- - * struct stored as the - * map value - */ }; struct { /* anonymous struct used by BPF_MAP_*_ELEM commands */ @@ -515,23 +396,6 @@ union bpf_attr { __u64 flags; }; - struct { /* struct used by BPF_MAP_*_BATCH commands */ - __aligned_u64 in_batch; /* start batch, - * NULL to start from beginning - */ - __aligned_u64 out_batch; /* output: next start batch */ - __aligned_u64 keys; - __aligned_u64 values; - __u32 count; /* input/output: - * input: # of key/value - * elements - * output: # of filled elements - */ - __u32 map_fd; - __u64 elem_flags; - __u64 flags; - } batch; - struct { /* anonymous struct used by BPF_PROG_LOAD command */ __u32 prog_type; /* one of enum bpf_prog_type */ __u32 insn_cnt; @@ -556,8 +420,6 @@ union bpf_attr { __u32 line_info_rec_size; /* userspace bpf_line_info size */ __aligned_u64 line_info; /* line info */ __u32 line_info_cnt; /* number of bpf_line_info records */ - __u32 attach_btf_id; /* in-kernel BTF type id to attach to */ - __u32 attach_prog_fd; /* 0 to attach to vmlinux */ }; struct { /* anonymous struct used by BPF_OBJ_* commands */ @@ -571,10 +433,6 @@ union bpf_attr { __u32 attach_bpf_fd; /* eBPF program to attach */ __u32 attach_type; __u32 attach_flags; - __u32 replace_bpf_fd; /* previously attached eBPF - * program to replace if - * BPF_F_REPLACE is used - */ }; struct { /* anonymous struct used by BPF_PROG_TEST_RUN command */ @@ -596,8 +454,6 @@ union bpf_attr { */ __aligned_u64 ctx_in; __aligned_u64 ctx_out; - __u32 flags; - __u32 cpu; } test; struct { /* anonymous struct used by BPF_*_GET_*_ID */ @@ -606,7 +462,6 @@ union bpf_attr { __u32 prog_id; __u32 map_id; __u32 btf_id; - __u32 link_id; }; __u32 next_id; __u32 open_flags; @@ -627,7 +482,7 @@ union bpf_attr { __u32 prog_cnt; } query; - struct { /* anonymous struct used by BPF_RAW_TRACEPOINT_OPEN command */ + struct { __u64 name; __u32 prog_fd; } raw_tracepoint; @@ -655,53 +510,6 @@ union bpf_attr { __u64 probe_offset; /* output: probe_offset */ __u64 probe_addr; /* output: probe_addr */ } task_fd_query; - - struct { /* struct used by BPF_LINK_CREATE command */ - __u32 prog_fd; /* eBPF program to attach */ - union { - __u32 target_fd; /* object to attach to */ - __u32 target_ifindex; /* target ifindex */ - }; - __u32 attach_type; /* attach type */ - __u32 flags; /* extra flags */ - union { - __u32 target_btf_id; /* btf_id of target to attach to */ - struct { - __aligned_u64 iter_info; /* extra bpf_iter_link_info */ - __u32 iter_info_len; /* iter_info length */ - }; - }; - } link_create; - - struct { /* struct used by BPF_LINK_UPDATE command */ - __u32 link_fd; /* link fd */ - /* new program fd to update link with */ - __u32 new_prog_fd; - __u32 flags; /* extra flags */ - /* expected link's program fd; is specified only if - * BPF_F_REPLACE flag is set in flags */ - __u32 old_prog_fd; - } link_update; - - struct { - __u32 link_fd; - } link_detach; - - struct { /* struct used by BPF_ENABLE_STATS command */ - __u32 type; - } enable_stats; - - struct { /* struct used by BPF_ITER_CREATE command */ - __u32 link_fd; - __u32 flags; - } iter_create; - - struct { /* struct used by BPF_PROG_BIND_MAP command */ - __u32 prog_fd; - __u32 map_fd; - __u32 flags; /* extra flags */ - } prog_bind_map; - } __attribute__((aligned(8))); /* The description below is an attempt at providing documentation to eBPF @@ -728,7 +536,7 @@ union bpf_attr { * Map value associated to *key*, or **NULL** if no entry was * found. * - * long bpf_map_update_elem(struct bpf_map *map, const void *key, const void *value, u64 flags) + * int bpf_map_update_elem(struct bpf_map *map, const void *key, const void *value, u64 flags) * Description * Add or update the value of the entry associated to *key* in * *map* with *value*. *flags* is one of: @@ -746,19 +554,16 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_map_delete_elem(struct bpf_map *map, const void *key) + * int bpf_map_delete_elem(struct bpf_map *map, const void *key) * Description * Delete entry with *key* from *map*. * Return * 0 on success, or a negative error in case of failure. * - * long bpf_probe_read(void *dst, u32 size, const void *unsafe_ptr) + * int bpf_probe_read(void *dst, u32 size, const void *src) * Description * For tracing programs, safely attempt to read *size* bytes from - * kernel space address *unsafe_ptr* and store the data in *dst*. - * - * Generally, use **bpf_probe_read_user**\ () or - * **bpf_probe_read_kernel**\ () instead. + * address *src* and store the data in *dst*. * Return * 0 on success, or a negative error in case of failure. * @@ -766,11 +571,11 @@ union bpf_attr { * Description * Return the time elapsed since system boot, in nanoseconds. * Does not include time the system was suspended. - * See: **clock_gettime**\ (**CLOCK_MONOTONIC**) + * See: clock_gettime(CLOCK_MONOTONIC) * Return * Current *ktime*. * - * long bpf_trace_printk(const char *fmt, u32 fmt_size, ...) + * int bpf_trace_printk(const char *fmt, u32 fmt_size, ...) * Description * This helper is a "printk()-like" facility for debugging. It * prints a message defined by format *fmt* (of size *fmt_size*) @@ -820,7 +625,7 @@ union bpf_attr { * * Also, note that **bpf_trace_printk**\ () is slow, and should * only be used for debugging purposes. For this reason, a notice - * block (spanning several lines) is printed to kernel logs and + * bloc (spanning several lines) is printed to kernel logs and * states that the helper should not be used "for production use" * the first time this helper is used (or more precisely, when * **trace_printk**\ () buffers are allocated). For passing values @@ -850,7 +655,7 @@ union bpf_attr { * Return * The SMP id of the processor running the program. * - * long bpf_skb_store_bytes(struct sk_buff *skb, u32 offset, const void *from, u32 len, u64 flags) + * int bpf_skb_store_bytes(struct sk_buff *skb, u32 offset, const void *from, u32 len, u64 flags) * Description * Store *len* bytes from address *from* into the packet * associated to *skb*, at *offset*. *flags* are a combination of @@ -867,7 +672,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_l3_csum_replace(struct sk_buff *skb, u32 offset, u64 from, u64 to, u64 size) + * int bpf_l3_csum_replace(struct sk_buff *skb, u32 offset, u64 from, u64 to, u64 size) * Description * Recompute the layer 3 (e.g. IP) checksum for the packet * associated to *skb*. Computation is incremental, so the helper @@ -892,7 +697,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_l4_csum_replace(struct sk_buff *skb, u32 offset, u64 from, u64 to, u64 flags) + * int bpf_l4_csum_replace(struct sk_buff *skb, u32 offset, u64 from, u64 to, u64 flags) * Description * Recompute the layer 4 (e.g. TCP, UDP or ICMP) checksum for the * packet associated to *skb*. Computation is incremental, so the @@ -910,7 +715,6 @@ union bpf_attr { * for updates resulting in a null checksum the value is set to * **CSUM_MANGLED_0** instead. Flag **BPF_F_PSEUDO_HDR** indicates * the checksum is to be computed against a pseudo-header. - * Flag **BPF_F_IPV6** should be set for IPv6 packets. * * This helper works in combination with **bpf_csum_diff**\ (), * which does not update the checksum in-place, but offers more @@ -925,7 +729,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_tail_call(void *ctx, struct bpf_map *prog_array_map, u32 index) + * int bpf_tail_call(void *ctx, struct bpf_map *prog_array_map, u32 index) * Description * This special helper is used to trigger a "tail call", or in * other words, to jump into another eBPF program. The same stack @@ -956,7 +760,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_clone_redirect(struct sk_buff *skb, u32 ifindex, u64 flags) + * int bpf_clone_redirect(struct sk_buff *skb, u32 ifindex, u64 flags) * Description * Clone and redirect the packet associated to *skb* to another * net device of index *ifindex*. Both ingress and egress @@ -994,7 +798,7 @@ union bpf_attr { * A 64-bit integer containing the current GID and UID, and * created as such: *current_gid* **<< 32 \|** *current_uid*. * - * long bpf_get_current_comm(void *buf, u32 size_of_buf) + * int bpf_get_current_comm(char *buf, u32 size_of_buf) * Description * Copy the **comm** attribute of the current task into *buf* of * *size_of_buf*. The **comm** attribute contains the name of @@ -1031,7 +835,7 @@ union bpf_attr { * Return * The classid, or 0 for the default unconfigured classid. * - * long bpf_skb_vlan_push(struct sk_buff *skb, __be16 vlan_proto, u16 vlan_tci) + * int bpf_skb_vlan_push(struct sk_buff *skb, __be16 vlan_proto, u16 vlan_tci) * Description * Push a *vlan_tci* (VLAN tag control information) of protocol * *vlan_proto* to the packet associated to *skb*, then update @@ -1047,7 +851,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_vlan_pop(struct sk_buff *skb) + * int bpf_skb_vlan_pop(struct sk_buff *skb) * Description * Pop a VLAN header from the packet associated to *skb*. * @@ -1059,7 +863,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_get_tunnel_key(struct sk_buff *skb, struct bpf_tunnel_key *key, u32 size, u64 flags) + * int bpf_skb_get_tunnel_key(struct sk_buff *skb, struct bpf_tunnel_key *key, u32 size, u64 flags) * Description * Get tunnel metadata. This helper takes a pointer *key* to an * empty **struct bpf_tunnel_key** of **size**, that will be @@ -1089,14 +893,14 @@ union bpf_attr { * * int ret; * struct bpf_tunnel_key key = {}; - * + * * ret = bpf_skb_get_tunnel_key(skb, &key, sizeof(key), 0); * if (ret < 0) * return TC_ACT_SHOT; // drop packet - * + * * if (key.remote_ipv4 != 0x0a000001) * return TC_ACT_SHOT; // drop packet - * + * * return TC_ACT_OK; // accept packet * * This interface can also be used with all encapsulation devices @@ -1110,7 +914,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_set_tunnel_key(struct sk_buff *skb, struct bpf_tunnel_key *key, u32 size, u64 flags) + * int bpf_skb_set_tunnel_key(struct sk_buff *skb, struct bpf_tunnel_key *key, u32 size, u64 flags) * Description * Populate tunnel metadata for packet associated to *skb.* The * tunnel metadata is set to the contents of *key*, of *size*. The @@ -1176,7 +980,7 @@ union bpf_attr { * The value of the perf event counter read from the map, or a * negative error code in case of failure. * - * long bpf_redirect(u32 ifindex, u64 flags) + * int bpf_redirect(u32 ifindex, u64 flags) * Description * Redirect the packet to another net device of index *ifindex*. * This helper is somewhat similar to **bpf_clone_redirect**\ @@ -1190,9 +994,9 @@ union bpf_attr { * supports redirection to the egress interface, and accepts no * flag at all. * - * The same effect can also be attained with the more generic - * **bpf_redirect_map**\ (), which uses a BPF map to store the - * redirect target instead of providing it directly to the helper. + * The same effect can be attained with the more generic + * **bpf_redirect_map**\ (), which requires specific maps to be + * used but offers better performance. * Return * For XDP, the helper returns **XDP_REDIRECT** on success or * **XDP_ABORTED** on error. For other program types, the values @@ -1203,7 +1007,7 @@ union bpf_attr { * Description * Retrieve the realm or the route, that is to say the * **tclassid** field of the destination for the *skb*. The - * identifier retrieved is a user-provided tag, similar to the + * indentifier retrieved is a user-provided tag, similar to the * one used with the net_cls cgroup (see description for * **bpf_get_cgroup_classid**\ () helper), but here this tag is * held by a route (a destination entry), not by a task. @@ -1223,7 +1027,7 @@ union bpf_attr { * The realm of the route for the packet associated to *skb*, or 0 * if none was found. * - * long bpf_perf_event_output(void *ctx, struct bpf_map *map, u64 flags, void *data, u64 size) + * int bpf_perf_event_output(struct pt_regs *ctx, struct bpf_map *map, u64 flags, void *data, u64 size) * Description * Write raw *data* blob into a special BPF perf event held by * *map* of type **BPF_MAP_TYPE_PERF_EVENT_ARRAY**. This perf @@ -1268,7 +1072,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_load_bytes(const void *skb, u32 offset, void *to, u32 len) + * int bpf_skb_load_bytes(const struct sk_buff *skb, u32 offset, void *to, u32 len) * Description * This helper was provided as an easy way to load data from a * packet. It can be used to load *len* bytes from *offset* from @@ -1285,7 +1089,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_get_stackid(void *ctx, struct bpf_map *map, u64 flags) + * int bpf_get_stackid(struct pt_regs *ctx, struct bpf_map *map, u64 flags) * Description * Walk a user or a kernel stack and return its id. To achieve * this, the helper needs *ctx*, which is a pointer to the context @@ -1354,7 +1158,7 @@ union bpf_attr { * The checksum result, or a negative error code in case of * failure. * - * long bpf_skb_get_tunnel_opt(struct sk_buff *skb, void *opt, u32 size) + * int bpf_skb_get_tunnel_opt(struct sk_buff *skb, u8 *opt, u32 size) * Description * Retrieve tunnel options metadata for the packet associated to * *skb*, and store the raw tunnel option data to the buffer *opt* @@ -1372,7 +1176,7 @@ union bpf_attr { * Return * The size of the option data retrieved. * - * long bpf_skb_set_tunnel_opt(struct sk_buff *skb, void *opt, u32 size) + * int bpf_skb_set_tunnel_opt(struct sk_buff *skb, u8 *opt, u32 size) * Description * Set tunnel options metadata for the packet associated to *skb* * to the option data contained in the raw buffer *opt* of *size*. @@ -1382,7 +1186,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_change_proto(struct sk_buff *skb, __be16 proto, u64 flags) + * int bpf_skb_change_proto(struct sk_buff *skb, __be16 proto, u64 flags) * Description * Change the protocol of the *skb* to *proto*. Currently * supported are transition from IPv4 to IPv6, and from IPv6 to @@ -1409,7 +1213,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_change_type(struct sk_buff *skb, u32 type) + * int bpf_skb_change_type(struct sk_buff *skb, u32 type) * Description * Change the packet type for the packet associated to *skb*. This * comes down to setting *skb*\ **->pkt_type** to *type*, except @@ -1436,7 +1240,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_under_cgroup(struct sk_buff *skb, struct bpf_map *map, u32 index) + * int bpf_skb_under_cgroup(struct sk_buff *skb, struct bpf_map *map, u32 index) * Description * Check whether *skb* is a descendant of the cgroup2 held by * *map* of type **BPF_MAP_TYPE_CGROUP_ARRAY**, at *index*. @@ -1467,7 +1271,7 @@ union bpf_attr { * Return * A pointer to the current task struct. * - * long bpf_probe_write_user(void *dst, const void *src, u32 len) + * int bpf_probe_write_user(void *dst, const void *src, u32 len) * Description * Attempt in a safe way to write *len* bytes from the buffer * *src* to *dst* in memory. It only works for threads that are in @@ -1486,7 +1290,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_current_task_under_cgroup(struct bpf_map *map, u32 index) + * int bpf_current_task_under_cgroup(struct bpf_map *map, u32 index) * Description * Check whether the probe is being run is the context of a given * subset of the cgroup2 hierarchy. The cgroup2 to test is held by @@ -1498,7 +1302,7 @@ union bpf_attr { * * 0, if current task does not belong to the cgroup2. * * A negative error code, if an error occurred. * - * long bpf_skb_change_tail(struct sk_buff *skb, u32 len, u64 flags) + * int bpf_skb_change_tail(struct sk_buff *skb, u32 len, u64 flags) * Description * Resize (trim or grow) the packet associated to *skb* to the * new *len*. The *flags* are reserved for future usage, and must @@ -1522,7 +1326,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_pull_data(struct sk_buff *skb, u32 len) + * int bpf_skb_pull_data(struct sk_buff *skb, u32 len) * Description * Pull in non-linear data in case the *skb* is non-linear and not * all of *len* are part of the linear section. Make *len* bytes @@ -1578,7 +1382,7 @@ union bpf_attr { * recalculation the next time the kernel tries to access this * hash or when the **bpf_get_hash_recalc**\ () helper is called. * - * long bpf_get_numa_node_id(void) + * int bpf_get_numa_node_id(void) * Description * Return the id of the current NUMA node. The primary use case * for this helper is the selection of sockets for the local NUMA @@ -1589,7 +1393,7 @@ union bpf_attr { * Return * The id of current NUMA node. * - * long bpf_skb_change_head(struct sk_buff *skb, u32 len, u64 flags) + * int bpf_skb_change_head(struct sk_buff *skb, u32 len, u64 flags) * Description * Grows headroom of packet associated to *skb* and adjusts the * offset of the MAC header accordingly, adding *len* bytes of @@ -1610,7 +1414,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_xdp_adjust_head(struct xdp_buff *xdp_md, int delta) + * int bpf_xdp_adjust_head(struct xdp_buff *xdp_md, int delta) * Description * Adjust (move) *xdp_md*\ **->data** by *delta* bytes. Note that * it is possible to use a negative value for *delta*. This helper @@ -1625,14 +1429,45 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_probe_read_str(void *dst, u32 size, const void *unsafe_ptr) + * int bpf_probe_read_str(void *dst, int size, const void *unsafe_ptr) * Description - * Copy a NUL terminated string from an unsafe kernel address - * *unsafe_ptr* to *dst*. See **bpf_probe_read_kernel_str**\ () for - * more details. + * Copy a NUL terminated string from an unsafe address + * *unsafe_ptr* to *dst*. The *size* should include the + * terminating NUL byte. In case the string length is smaller than + * *size*, the target is not padded with further NUL bytes. If the + * string length is larger than *size*, just *size*-1 bytes are + * copied and the last byte is set to NUL. * - * Generally, use **bpf_probe_read_user_str**\ () or - * **bpf_probe_read_kernel_str**\ () instead. + * On success, the length of the copied string is returned. This + * makes this helper useful in tracing programs for reading + * strings, and more importantly to get its length at runtime. See + * the following snippet: + * + * :: + * + * SEC("kprobe/sys_open") + * void bpf_sys_open(struct pt_regs *ctx) + * { + * char buf[PATHLEN]; // PATHLEN is defined to 256 + * int res = bpf_probe_read_str(buf, sizeof(buf), + * ctx->di); + * + * // Consume buf, for example push it to + * // userspace via bpf_perf_event_output(); we + * // can use res (the string length) as event + * // size, after checking its boundaries. + * } + * + * In comparison, using **bpf_probe_read()** helper here instead + * to read the string would require to estimate the length at + * compile time, and would often result in copying more memory + * than necessary. + * + * Another useful use case is when parsing individual process + * arguments or individual environment variables navigating + * *current*\ **->mm->arg_start** and *current*\ + * **->mm->env_start**: using this helper and the return value, + * one can quickly iterate at the right offset of the memory area. * Return * On success, the strictly positive length of the string, * including the trailing NUL character. On error, a negative @@ -1660,7 +1495,7 @@ union bpf_attr { * * u64 bpf_get_socket_cookie(struct bpf_sock_ops *ctx) * Description - * Equivalent to **bpf_get_socket_cookie**\ () helper that accepts + * Equivalent to bpf_get_socket_cookie() helper that accepts * *skb*, but gets socket from **struct bpf_sock_ops** context. * Return * A 8-byte long non-decreasing number. @@ -1673,14 +1508,14 @@ union bpf_attr { * is returned (note that **overflowuid** might also be the actual * UID value for the socket). * - * long bpf_set_hash(struct sk_buff *skb, u32 hash) + * u32 bpf_set_hash(struct sk_buff *skb, u32 hash) * Description * Set the full hash for *skb* (set the field *skb*\ **->hash**) * to value *hash*. * Return * 0 * - * long bpf_setsockopt(void *bpf_socket, int level, int optname, void *optval, int optlen) + * int bpf_setsockopt(struct bpf_sock_ops *bpf_socket, int level, int optname, char *optval, int optlen) * Description * Emulate a call to **setsockopt()** on the socket associated to * *bpf_socket*, which must be a full socket. The *level* at @@ -1688,41 +1523,25 @@ union bpf_attr { * must be specified, see **setsockopt(2)** for more information. * The option value of length *optlen* is pointed by *optval*. * - * *bpf_socket* should be one of the following: - * - * * **struct bpf_sock_ops** for **BPF_PROG_TYPE_SOCK_OPS**. - * * **struct bpf_sock_addr** for **BPF_CGROUP_INET4_CONNECT** - * and **BPF_CGROUP_INET6_CONNECT**. - * * This helper actually implements a subset of **setsockopt()**. * It supports the following *level*\ s: * * * **SOL_SOCKET**, which supports the following *optname*\ s: * **SO_RCVBUF**, **SO_SNDBUF**, **SO_MAX_PACING_RATE**, - * **SO_PRIORITY**, **SO_RCVLOWAT**, **SO_MARK**, - * **SO_BINDTODEVICE**, **SO_KEEPALIVE**. + * **SO_PRIORITY**, **SO_RCVLOWAT**, **SO_MARK**. * * **IPPROTO_TCP**, which supports the following *optname*\ s: * **TCP_CONGESTION**, **TCP_BPF_IW**, - * **TCP_BPF_SNDCWND_CLAMP**, **TCP_SAVE_SYN**, - * **TCP_KEEPIDLE**, **TCP_KEEPINTVL**, **TCP_KEEPCNT**, - * **TCP_SYNCNT**, **TCP_USER_TIMEOUT**, **TCP_NOTSENT_LOWAT**. + * **TCP_BPF_SNDCWND_CLAMP**. * * **IPPROTO_IP**, which supports *optname* **IP_TOS**. * * **IPPROTO_IPV6**, which supports *optname* **IPV6_TCLASS**. * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_adjust_room(struct sk_buff *skb, s32 len_diff, u32 mode, u64 flags) + * int bpf_skb_adjust_room(struct sk_buff *skb, s32 len_diff, u32 mode, u64 flags) * Description * Grow or shrink the room for data in the packet associated to * *skb* by *len_diff*, and according to the selected *mode*. * - * By default, the helper will reset any offloaded checksum - * indicator of the skb to CHECKSUM_NONE. This can be avoided - * by the following flag: - * - * * **BPF_F_ADJ_ROOM_NO_CSUM_RESET**: Do not reset offloaded - * checksum data of the skb to CHECKSUM_NONE. - * * There are two supported modes at this time: * * * **BPF_ADJ_ROOM_MAC**: Adjust room at the mac layer @@ -1757,7 +1576,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_redirect_map(struct bpf_map *map, u32 key, u64 flags) + * int bpf_redirect_map(struct bpf_map *map, u32 key, u64 flags) * Description * Redirect the packet to the endpoint referenced by *map* at * index *key*. Depending on its type, this *map* can contain @@ -1768,17 +1587,19 @@ union bpf_attr { * * The lower two bits of *flags* are used as the return code if * the map lookup fails. This is so that the return value can be - * one of the XDP program return codes up to **XDP_TX**, as chosen - * by the caller. Any higher bits in the *flags* argument must be + * one of the XDP program return codes up to XDP_TX, as chosen by + * the caller. Any higher bits in the *flags* argument must be * unset. * - * See also **bpf_redirect**\ (), which only supports redirecting - * to an ifindex, but doesn't require a map to do so. + * When used to redirect packets to net devices, this helper + * provides a high performance increase over **bpf_redirect**\ (). + * This is due to various implementation details of the underlying + * mechanisms, one of which is the fact that **bpf_redirect_map**\ + * () tries to send packet as a "bulk" to the device. * Return - * **XDP_REDIRECT** on success, or the value of the two lower bits - * of the *flags* argument on error. + * **XDP_REDIRECT** on success, or **XDP_ABORTED** on error. * - * long bpf_sk_redirect_map(struct sk_buff *skb, struct bpf_map *map, u32 key, u64 flags) + * int bpf_sk_redirect_map(struct bpf_map *map, u32 key, u64 flags) * Description * Redirect the packet to the socket referenced by *map* (of type * **BPF_MAP_TYPE_SOCKMAP**) at index *key*. Both ingress and @@ -1789,7 +1610,7 @@ union bpf_attr { * Return * **SK_PASS** on success, or **SK_DROP** on error. * - * long bpf_sock_map_update(struct bpf_sock_ops *skops, struct bpf_map *map, void *key, u64 flags) + * int bpf_sock_map_update(struct bpf_sock_ops *skops, struct bpf_map *map, void *key, u64 flags) * Description * Add an entry to, or update a *map* referencing sockets. The * *skops* is used as a new value for the entry associated to @@ -1808,7 +1629,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_xdp_adjust_meta(struct xdp_buff *xdp_md, int delta) + * int bpf_xdp_adjust_meta(struct xdp_buff *xdp_md, int delta) * Description * Adjust the address pointed by *xdp_md*\ **->data_meta** by * *delta* (which can be positive or negative). Note that this @@ -1837,7 +1658,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_perf_event_read_value(struct bpf_map *map, u64 flags, struct bpf_perf_event_value *buf, u32 buf_size) + * int bpf_perf_event_read_value(struct bpf_map *map, u64 flags, struct bpf_perf_event_value *buf, u32 buf_size) * Description * Read the value of a perf event counter, and store it into *buf* * of size *buf_size*. This helper relies on a *map* of type @@ -1881,13 +1702,13 @@ union bpf_attr { * the time running for event since last normalization. The * enabled and running times are accumulated since the perf event * open. To achieve scaling factor between two invocations of an - * eBPF program, users can use CPU id as the key (which is + * eBPF program, users can can use CPU id as the key (which is * typical for perf array usage model) to remember the previous * value and do the calculation inside the eBPF program. * Return * 0 on success, or a negative error in case of failure. * - * long bpf_perf_prog_read_value(struct bpf_perf_event_data *ctx, struct bpf_perf_event_value *buf, u32 buf_size) + * int bpf_perf_prog_read_value(struct bpf_perf_event_data *ctx, struct bpf_perf_event_value *buf, u32 buf_size) * Description * For en eBPF program attached to a perf event, retrieve the * value of the event counter associated to *ctx* and store it in @@ -1898,7 +1719,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_getsockopt(void *bpf_socket, int level, int optname, void *optval, int optlen) + * int bpf_getsockopt(struct bpf_sock_ops *bpf_socket, int level, int optname, char *optval, int optlen) * Description * Emulate a call to **getsockopt()** on the socket associated to * *bpf_socket*, which must be a full socket. The *level* at @@ -1907,12 +1728,6 @@ union bpf_attr { * The retrieved value is stored in the structure pointed by * *opval* and of length *optlen*. * - * *bpf_socket* should be one of the following: - * - * * **struct bpf_sock_ops** for **BPF_PROG_TYPE_SOCK_OPS**. - * * **struct bpf_sock_addr** for **BPF_CGROUP_INET4_CONNECT** - * and **BPF_CGROUP_INET6_CONNECT**. - * * This helper actually implements a subset of **getsockopt()**. * It supports the following *level*\ s: * @@ -1923,14 +1738,14 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_override_return(struct pt_regs *regs, u64 rc) + * int bpf_override_return(struct pt_regs *regs, u64 rc) * Description * Used for error injection, this helper uses kprobes to override * the return value of the probed function, and to set it to *rc*. * The first argument is the context *regs* on which the kprobe * works. * - * This helper works by setting the PC (program counter) + * This helper works by setting setting the PC (program counter) * to an override function which is run in place of the original * probed function. This means the probed function is not run at * all. The replacement function just returns with the required @@ -1948,7 +1763,7 @@ union bpf_attr { * Return * 0 * - * long bpf_sock_ops_cb_flags_set(struct bpf_sock_ops *bpf_sock, int argval) + * int bpf_sock_ops_cb_flags_set(struct bpf_sock_ops *bpf_sock, int argval) * Description * Attempt to set the value of the **bpf_sock_ops_cb_flags** field * for the full TCP socket associated to *bpf_sock_ops* to @@ -1992,7 +1807,7 @@ union bpf_attr { * be set is returned (which comes down to 0 if all bits were set * as required). * - * long bpf_msg_redirect_map(struct sk_msg_buff *msg, struct bpf_map *map, u32 key, u64 flags) + * int bpf_msg_redirect_map(struct sk_msg_buff *msg, struct bpf_map *map, u32 key, u64 flags) * Description * This helper is used in programs implementing policies at the * socket level. If the message *msg* is allowed to pass (i.e. if @@ -2006,7 +1821,7 @@ union bpf_attr { * Return * **SK_PASS** on success, or **SK_DROP** on error. * - * long bpf_msg_apply_bytes(struct sk_msg_buff *msg, u32 bytes) + * int bpf_msg_apply_bytes(struct sk_msg_buff *msg, u32 bytes) * Description * For socket policies, apply the verdict of the eBPF program to * the next *bytes* (number of bytes) of message *msg*. @@ -2040,7 +1855,7 @@ union bpf_attr { * Return * 0 * - * long bpf_msg_cork_bytes(struct sk_msg_buff *msg, u32 bytes) + * int bpf_msg_cork_bytes(struct sk_msg_buff *msg, u32 bytes) * Description * For socket policies, prevent the execution of the verdict eBPF * program for message *msg* until *bytes* (byte number) have been @@ -2058,7 +1873,7 @@ union bpf_attr { * Return * 0 * - * long bpf_msg_pull_data(struct sk_msg_buff *msg, u32 start, u32 end, u64 flags) + * int bpf_msg_pull_data(struct sk_msg_buff *msg, u32 start, u32 end, u64 flags) * Description * For socket policies, pull in non-linear data from user space * for *msg* and set pointers *msg*\ **->data** and *msg*\ @@ -2089,7 +1904,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_bind(struct bpf_sock_addr *ctx, struct sockaddr *addr, int addr_len) + * int bpf_bind(struct bpf_sock_addr *ctx, struct sockaddr *addr, int addr_len) * Description * Bind the socket associated to *ctx* to the address pointed by * *addr*, of length *addr_len*. This allows for making outgoing @@ -2099,19 +1914,18 @@ union bpf_attr { * * This helper works for IPv4 and IPv6, TCP and UDP sockets. The * domain (*addr*\ **->sa_family**) must be **AF_INET** (or - * **AF_INET6**). It's advised to pass zero port (**sin_port** - * or **sin6_port**) which triggers IP_BIND_ADDRESS_NO_PORT-like - * behavior and lets the kernel efficiently pick up an unused - * port as long as 4-tuple is unique. Passing non-zero port might - * lead to degraded performance. + * **AF_INET6**). Looking for a free port to bind to can be + * expensive, therefore binding to port is not permitted by the + * helper: *addr*\ **->sin_port** (or **sin6_port**, respectively) + * must be set to zero. * Return * 0 on success, or a negative error in case of failure. * - * long bpf_xdp_adjust_tail(struct xdp_buff *xdp_md, int delta) + * int bpf_xdp_adjust_tail(struct xdp_buff *xdp_md, int delta) * Description * Adjust (move) *xdp_md*\ **->data_end** by *delta* bytes. It is - * possible to both shrink and grow the packet tail. - * Shrink done via *delta* being a negative integer. + * only possible to shrink the packet as of this writing, + * therefore *delta* must be a negative integer. * * A call to this helper is susceptible to change the underlying * packet buffer. Therefore, at load time, all checks on pointers @@ -2121,7 +1935,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_get_xfrm_state(struct sk_buff *skb, u32 index, struct bpf_xfrm_state *xfrm_state, u32 size, u64 flags) + * int bpf_skb_get_xfrm_state(struct sk_buff *skb, u32 index, struct bpf_xfrm_state *xfrm_state, u32 size, u64 flags) * Description * Retrieve the XFRM state (IP transform framework, see also * **ip-xfrm(8)**) at *index* in XFRM "security path" for *skb*. @@ -2137,7 +1951,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_get_stack(void *ctx, void *buf, u32 size, u64 flags) + * int bpf_get_stack(struct pt_regs *regs, void *buf, u32 size, u64 flags) * Description * Return a user or a kernel stack in bpf program provided buffer. * To achieve this, the helper needs *ctx*, which is a pointer @@ -2167,10 +1981,10 @@ union bpf_attr { * * # sysctl kernel.perf_event_max_stack= * Return - * The non-negative copied *buf* length equal to or less than - * *size* on success, or a negative error in case of failure. + * A non-negative value equal to or less than *size* on success, + * or a negative error in case of failure. * - * long bpf_skb_load_bytes_relative(const void *skb, u32 offset, void *to, u32 len, u32 start_header) + * int bpf_skb_load_bytes_relative(const struct sk_buff *skb, u32 offset, void *to, u32 len, u32 start_header) * Description * This helper is similar to **bpf_skb_load_bytes**\ () in that * it provides an easy way to load *len* bytes from *offset* @@ -2192,7 +2006,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_fib_lookup(void *ctx, struct bpf_fib_lookup *params, int plen, u32 flags) + * int bpf_fib_lookup(void *ctx, struct bpf_fib_lookup *params, int plen, u32 flags) * Description * Do FIB lookup in kernel tables using parameters in *params*. * If lookup is successful and result shows packet is to be @@ -2223,7 +2037,7 @@ union bpf_attr { * * > 0 one of **BPF_FIB_LKUP_RET_** codes explaining why the * packet is not forwarded or needs assist from full stack * - * long bpf_sock_hash_update(struct bpf_sock_ops *skops, struct bpf_map *map, void *key, u64 flags) + * int bpf_sock_hash_update(struct bpf_sock_ops_kern *skops, struct bpf_map *map, void *key, u64 flags) * Description * Add an entry to, or update a sockhash *map* referencing sockets. * The *skops* is used as a new value for the entry associated to @@ -2242,7 +2056,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_msg_redirect_hash(struct sk_msg_buff *msg, struct bpf_map *map, void *key, u64 flags) + * int bpf_msg_redirect_hash(struct sk_msg_buff *msg, struct bpf_map *map, void *key, u64 flags) * Description * This helper is used in programs implementing policies at the * socket level. If the message *msg* is allowed to pass (i.e. if @@ -2256,11 +2070,11 @@ union bpf_attr { * Return * **SK_PASS** on success, or **SK_DROP** on error. * - * long bpf_sk_redirect_hash(struct sk_buff *skb, struct bpf_map *map, void *key, u64 flags) + * int bpf_sk_redirect_hash(struct sk_buff *skb, struct bpf_map *map, void *key, u64 flags) * Description * This helper is used in programs implementing policies at the * skb socket level. If the sk_buff *skb* is allowed to pass (i.e. - * if the verdict eBPF program returns **SK_PASS**), redirect it + * if the verdeict eBPF program returns **SK_PASS**), redirect it * to the socket referenced by *map* (of type * **BPF_MAP_TYPE_SOCKHASH**) using hash *key*. Both ingress and * egress interfaces can be used for redirection. The @@ -2270,7 +2084,7 @@ union bpf_attr { * Return * **SK_PASS** on success, or **SK_DROP** on error. * - * long bpf_lwt_push_encap(struct sk_buff *skb, u32 type, void *hdr, u32 len) + * int bpf_lwt_push_encap(struct sk_buff *skb, u32 type, void *hdr, u32 len) * Description * Encapsulate the packet associated to *skb* within a Layer 3 * protocol header. This header is provided in the buffer at @@ -2307,7 +2121,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_lwt_seg6_store_bytes(struct sk_buff *skb, u32 offset, const void *from, u32 len) + * int bpf_lwt_seg6_store_bytes(struct sk_buff *skb, u32 offset, const void *from, u32 len) * Description * Store *len* bytes from address *from* into the packet * associated to *skb*, at *offset*. Only the flags, tag and TLVs @@ -2322,7 +2136,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_lwt_seg6_adjust_srh(struct sk_buff *skb, u32 offset, s32 delta) + * int bpf_lwt_seg6_adjust_srh(struct sk_buff *skb, u32 offset, s32 delta) * Description * Adjust the size allocated to TLVs in the outermost IPv6 * Segment Routing Header contained in the packet associated to @@ -2338,7 +2152,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_lwt_seg6_action(struct sk_buff *skb, u32 action, void *param, u32 param_len) + * int bpf_lwt_seg6_action(struct sk_buff *skb, u32 action, void *param, u32 param_len) * Description * Apply an IPv6 Segment Routing action of type *action* to the * packet associated to *skb*. Each action takes a parameter @@ -2367,7 +2181,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_rc_repeat(void *ctx) + * int bpf_rc_repeat(void *ctx) * Description * This helper is used in programs implementing IR decoding, to * report a successfully decoded repeat key message. This delays @@ -2386,7 +2200,7 @@ union bpf_attr { * Return * 0 * - * long bpf_rc_keydown(void *ctx, u32 protocol, u64 scancode, u32 toggle) + * int bpf_rc_keydown(void *ctx, u32 protocol, u64 scancode, u32 toggle) * Description * This helper is used in programs implementing IR decoding, to * report a successfully decoded key press with *scancode*, @@ -2397,7 +2211,7 @@ union bpf_attr { * **bpf_rc_keydown**\ () again with the same values, or calling * **bpf_rc_repeat**\ (). * - * Some protocols include a toggle bit, in case the button was + * Some protocols include a toggle bit, in case the button was * released and pressed again between consecutive scancodes. * * The *ctx* should point to the lirc sample as passed into @@ -2451,7 +2265,7 @@ union bpf_attr { * Return * A pointer to the local storage area. * - * long bpf_sk_select_reuseport(struct sk_reuseport_md *reuse, struct bpf_map *map, void *key, u64 flags) + * int bpf_sk_select_reuseport(struct sk_reuseport_md *reuse, struct bpf_map *map, void *key, u64 flags) * Description * Select a **SO_REUSEPORT** socket from a * **BPF_MAP_TYPE_REUSEPORT_SOCKARRAY** *map*. @@ -2496,7 +2310,7 @@ union bpf_attr { * Look for an IPv6 socket. * * If the *netns* is a negative signed 32-bit integer, then the - * socket lookup table in the netns associated with the *ctx* + * socket lookup table in the netns associated with the *ctx* will * will be used. For the TC hooks, this is the netns of the device * in the skb. For socket hooks, this is the netns of the socket. * If *netns* is any other signed 32-bit value greater than or @@ -2533,7 +2347,7 @@ union bpf_attr { * Look for an IPv6 socket. * * If the *netns* is a negative signed 32-bit integer, then the - * socket lookup table in the netns associated with the *ctx* + * socket lookup table in the netns associated with the *ctx* will * will be used. For the TC hooks, this is the netns of the device * in the skb. For socket hooks, this is the netns of the socket. * If *netns* is any other signed 32-bit value greater than or @@ -2552,7 +2366,7 @@ union bpf_attr { * result is from *reuse*\ **->socks**\ [] using the hash of the * tuple. * - * long bpf_sk_release(void *sock) + * int bpf_sk_release(struct bpf_sock *sock) * Description * Release the reference held by *sock*. *sock* must be a * non-**NULL** pointer that was returned from @@ -2560,7 +2374,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_map_push_elem(struct bpf_map *map, const void *value, u64 flags) + * int bpf_map_push_elem(struct bpf_map *map, const void *value, u64 flags) * Description * Push an element *value* in *map*. *flags* is one of: * @@ -2570,19 +2384,19 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_map_pop_elem(struct bpf_map *map, void *value) + * int bpf_map_pop_elem(struct bpf_map *map, void *value) * Description * Pop an element from *map*. * Return * 0 on success, or a negative error in case of failure. * - * long bpf_map_peek_elem(struct bpf_map *map, void *value) + * int bpf_map_peek_elem(struct bpf_map *map, void *value) * Description * Get an element from *map* without removing it. * Return * 0 on success, or a negative error in case of failure. * - * long bpf_msg_push_data(struct sk_msg_buff *msg, u32 start, u32 len, u64 flags) + * int bpf_msg_push_data(struct sk_buff *skb, u32 start, u32 len, u64 flags) * Description * For socket policies, insert *len* bytes into *msg* at offset * *start*. @@ -2598,9 +2412,9 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_msg_pop_data(struct sk_msg_buff *msg, u32 start, u32 len, u64 flags) + * int bpf_msg_pop_data(struct sk_msg_buff *msg, u32 start, u32 pop, u64 flags) * Description - * Will remove *len* bytes from a *msg* starting at byte *start*. + * Will remove *pop* bytes from a *msg* starting at byte *start*. * This may result in **ENOMEM** errors under certain situations if * an allocation and copy are required due to a full ring buffer. * However, the helper will try to avoid doing the allocation @@ -2610,7 +2424,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_rc_pointer_rel(void *ctx, s32 rel_x, s32 rel_y) + * int bpf_rc_pointer_rel(void *ctx, s32 rel_x, s32 rel_y) * Description * This helper is used in programs implementing IR decoding, to * report a successfully decoded pointer movement. @@ -2624,7 +2438,7 @@ union bpf_attr { * Return * 0 * - * long bpf_spin_lock(struct bpf_spin_lock *lock) + * int bpf_spin_lock(struct bpf_spin_lock *lock) * Description * Acquire a spinlock represented by the pointer *lock*, which is * stored as part of a value of a map. Taking the lock allows to @@ -2672,7 +2486,7 @@ union bpf_attr { * Return * 0 * - * long bpf_spin_unlock(struct bpf_spin_lock *lock) + * int bpf_spin_unlock(struct bpf_spin_lock *lock) * Description * Release the *lock* previously locked by a call to * **bpf_spin_lock**\ (\ *lock*\ ). @@ -2695,7 +2509,7 @@ union bpf_attr { * A **struct bpf_tcp_sock** pointer on success, or **NULL** in * case of failure. * - * long bpf_skb_ecn_set_ce(struct sk_buff *skb) + * int bpf_skb_ecn_set_ce(struct sk_buf *skb) * Description * Set ECN (Explicit Congestion Notification) field of IP header * to **CE** (Congestion Encountered) if current value is **ECT** @@ -2732,7 +2546,7 @@ union bpf_attr { * result is from *reuse*\ **->socks**\ [] using the hash of the * tuple. * - * long bpf_tcp_check_syncookie(void *sk, void *iph, u32 iph_len, struct tcphdr *th, u32 th_len) + * int bpf_tcp_check_syncookie(struct bpf_sock *sk, void *iph, u32 iph_len, struct tcphdr *th, u32 th_len) * Description * Check whether *iph* and *th* contain a valid SYN cookie ACK for * the listening socket in *sk*. @@ -2743,11 +2557,12 @@ union bpf_attr { * * *th* points to the start of the TCP header, while *th_len* * contains **sizeof**\ (**struct tcphdr**). + * * Return * 0 if *iph* and *th* are a valid SYN cookie ACK, or a negative * error otherwise. * - * long bpf_sysctl_get_name(struct bpf_sysctl *ctx, char *buf, size_t buf_len, u64 flags) + * int bpf_sysctl_get_name(struct bpf_sysctl *ctx, char *buf, size_t buf_len, u64 flags) * Description * Get name of sysctl in /proc/sys/ and copy it into provided by * program buffer *buf* of size *buf_len*. @@ -2763,7 +2578,7 @@ union bpf_attr { * **-E2BIG** if the buffer wasn't big enough (*buf* will contain * truncated name in this case). * - * long bpf_sysctl_get_current_value(struct bpf_sysctl *ctx, char *buf, size_t buf_len) + * int bpf_sysctl_get_current_value(struct bpf_sysctl *ctx, char *buf, size_t buf_len) * Description * Get current value of sysctl as it is presented in /proc/sys * (incl. newline, etc), and copy it as a string into provided @@ -2782,7 +2597,7 @@ union bpf_attr { * **-EINVAL** if current value was unavailable, e.g. because * sysctl is uninitialized and read returns -EIO for it. * - * long bpf_sysctl_get_new_value(struct bpf_sysctl *ctx, char *buf, size_t buf_len) + * int bpf_sysctl_get_new_value(struct bpf_sysctl *ctx, char *buf, size_t buf_len) * Description * Get new value being written by user space to sysctl (before * the actual write happens) and copy it as a string into @@ -2799,7 +2614,7 @@ union bpf_attr { * * **-EINVAL** if sysctl is being read. * - * long bpf_sysctl_set_new_value(struct bpf_sysctl *ctx, const char *buf, size_t buf_len) + * int bpf_sysctl_set_new_value(struct bpf_sysctl *ctx, const char *buf, size_t buf_len) * Description * Override new value being written by user space to sysctl with * value provided by program in buffer *buf* of size *buf_len*. @@ -2816,7 +2631,7 @@ union bpf_attr { * * **-EINVAL** if sysctl is being read. * - * long bpf_strtol(const char *buf, size_t buf_len, u64 flags, long *res) + * int bpf_strtol(const char *buf, size_t buf_len, u64 flags, long *res) * Description * Convert the initial part of the string from buffer *buf* of * size *buf_len* to a long integer according to the given base @@ -2840,7 +2655,7 @@ union bpf_attr { * * **-ERANGE** if resulting value was out of range. * - * long bpf_strtoul(const char *buf, size_t buf_len, u64 flags, unsigned long *res) + * int bpf_strtoul(const char *buf, size_t buf_len, u64 flags, unsigned long *res) * Description * Convert the initial part of the string from buffer *buf* of * size *buf_len* to an unsigned long integer according to the @@ -2863,7 +2678,7 @@ union bpf_attr { * * **-ERANGE** if resulting value was out of range. * - * void *bpf_sk_storage_get(struct bpf_map *map, void *sk, void *value, u64 flags) + * void *bpf_sk_storage_get(struct bpf_map *map, struct bpf_sock *sk, void *value, u64 flags) * Description * Get a bpf-local-storage from a *sk*. * @@ -2879,9 +2694,6 @@ union bpf_attr { * "type". The bpf-local-storage "type" (i.e. the *map*) is * searched against all bpf-local-storages residing at *sk*. * - * *sk* is a kernel **struct sock** pointer for LSM program. - * *sk* is a **struct bpf_sock** pointer for other program types. - * * An optional *flags* (**BPF_SK_STORAGE_GET_F_CREATE**) can be * used such that a new bpf-local-storage will be * created if one does not exist. *value* can be used @@ -2894,19 +2706,17 @@ union bpf_attr { * **NULL** if not found or there was an error in adding * a new bpf-local-storage. * - * long bpf_sk_storage_delete(struct bpf_map *map, void *sk) + * int bpf_sk_storage_delete(struct bpf_map *map, struct bpf_sock *sk) * Description * Delete a bpf-local-storage from a *sk*. * Return * 0 on success. * * **-ENOENT** if the bpf-local-storage cannot be found. - * **-EINVAL** if sk is not a fullsock (e.g. a request_sock). * - * long bpf_send_signal(u32 sig) + * int bpf_send_signal(u32 sig) * Description - * Send signal *sig* to the process of the current task. - * The signal may be delivered to any of this process's threads. + * Send signal *sig* to the current task. * Return * 0 on success or successfully queued. * @@ -2918,7 +2728,7 @@ union bpf_attr { * * **-EAGAIN** if bpf program can try again. * - * s64 bpf_tcp_gen_syncookie(void *sk, void *iph, u32 iph_len, struct tcphdr *th, u32 th_len) + * s64 bpf_tcp_gen_syncookie(struct bpf_sock *sk, void *iph, u32 iph_len, struct tcphdr *th, u32 th_len) * Description * Try to issue a SYN cookie for the packet with corresponding * IP/TCP headers, *iph* and *th*, on the listening socket in *sk*. @@ -2929,6 +2739,7 @@ union bpf_attr { * * *th* points to the start of the TCP header, while *th_len* * contains the length of the TCP header. + * * Return * On success, lower 32 bits hold the generated SYN cookie in * followed by 16 bits which hold the MSS value for that cookie, @@ -2951,812 +2762,6 @@ union bpf_attr { * See: clock_gettime(CLOCK_BOOTTIME) * Return * Current *ktime*. - * - * long bpf_skb_output(void *ctx, struct bpf_map *map, u64 flags, void *data, u64 size) - * Description - * Write raw *data* blob into a special BPF perf event held by - * *map* of type **BPF_MAP_TYPE_PERF_EVENT_ARRAY**. This perf - * event must have the following attributes: **PERF_SAMPLE_RAW** - * as **sample_type**, **PERF_TYPE_SOFTWARE** as **type**, and - * **PERF_COUNT_SW_BPF_OUTPUT** as **config**. - * - * The *flags* are used to indicate the index in *map* for which - * the value must be put, masked with **BPF_F_INDEX_MASK**. - * Alternatively, *flags* can be set to **BPF_F_CURRENT_CPU** - * to indicate that the index of the current CPU core should be - * used. - * - * The value to write, of *size*, is passed through eBPF stack and - * pointed by *data*. - * - * *ctx* is a pointer to in-kernel struct sk_buff. - * - * This helper is similar to **bpf_perf_event_output**\ () but - * restricted to raw_tracepoint bpf programs. - * Return - * 0 on success, or a negative error in case of failure. - * - * long bpf_probe_read_user(void *dst, u32 size, const void *unsafe_ptr) - * Description - * Safely attempt to read *size* bytes from user space address - * *unsafe_ptr* and store the data in *dst*. - * Return - * 0 on success, or a negative error in case of failure. - * - * long bpf_probe_read_kernel(void *dst, u32 size, const void *unsafe_ptr) - * Description - * Safely attempt to read *size* bytes from kernel space address - * *unsafe_ptr* and store the data in *dst*. - * Return - * 0 on success, or a negative error in case of failure. - * - * long bpf_probe_read_user_str(void *dst, u32 size, const void *unsafe_ptr) - * Description - * Copy a NUL terminated string from an unsafe user address - * *unsafe_ptr* to *dst*. The *size* should include the - * terminating NUL byte. In case the string length is smaller than - * *size*, the target is not padded with further NUL bytes. If the - * string length is larger than *size*, just *size*-1 bytes are - * copied and the last byte is set to NUL. - * - * On success, the length of the copied string is returned. This - * makes this helper useful in tracing programs for reading - * strings, and more importantly to get its length at runtime. See - * the following snippet: - * - * :: - * - * SEC("kprobe/sys_open") - * void bpf_sys_open(struct pt_regs *ctx) - * { - * char buf[PATHLEN]; // PATHLEN is defined to 256 - * int res = bpf_probe_read_user_str(buf, sizeof(buf), - * ctx->di); - * - * // Consume buf, for example push it to - * // userspace via bpf_perf_event_output(); we - * // can use res (the string length) as event - * // size, after checking its boundaries. - * } - * - * In comparison, using **bpf_probe_read_user**\ () helper here - * instead to read the string would require to estimate the length - * at compile time, and would often result in copying more memory - * than necessary. - * - * Another useful use case is when parsing individual process - * arguments or individual environment variables navigating - * *current*\ **->mm->arg_start** and *current*\ - * **->mm->env_start**: using this helper and the return value, - * one can quickly iterate at the right offset of the memory area. - * Return - * On success, the strictly positive length of the string, - * including the trailing NUL character. On error, a negative - * value. - * - * long bpf_probe_read_kernel_str(void *dst, u32 size, const void *unsafe_ptr) - * Description - * Copy a NUL terminated string from an unsafe kernel address *unsafe_ptr* - * to *dst*. Same semantics as with **bpf_probe_read_user_str**\ () apply. - * Return - * On success, the strictly positive length of the string, including - * the trailing NUL character. On error, a negative value. - * - * long bpf_tcp_send_ack(void *tp, u32 rcv_nxt) - * Description - * Send out a tcp-ack. *tp* is the in-kernel struct **tcp_sock**. - * *rcv_nxt* is the ack_seq to be sent out. - * Return - * 0 on success, or a negative error in case of failure. - * - * long bpf_send_signal_thread(u32 sig) - * Description - * Send signal *sig* to the thread corresponding to the current task. - * Return - * 0 on success or successfully queued. - * - * **-EBUSY** if work queue under nmi is full. - * - * **-EINVAL** if *sig* is invalid. - * - * **-EPERM** if no permission to send the *sig*. - * - * **-EAGAIN** if bpf program can try again. - * - * u64 bpf_jiffies64(void) - * Description - * Obtain the 64bit jiffies - * Return - * The 64 bit jiffies - * - * long bpf_read_branch_records(struct bpf_perf_event_data *ctx, void *buf, u32 size, u64 flags) - * Description - * For an eBPF program attached to a perf event, retrieve the - * branch records (**struct perf_branch_entry**) associated to *ctx* - * and store it in the buffer pointed by *buf* up to size - * *size* bytes. - * Return - * On success, number of bytes written to *buf*. On error, a - * negative value. - * - * The *flags* can be set to **BPF_F_GET_BRANCH_RECORDS_SIZE** to - * instead return the number of bytes required to store all the - * branch entries. If this flag is set, *buf* may be NULL. - * - * **-EINVAL** if arguments invalid or **size** not a multiple - * of **sizeof**\ (**struct perf_branch_entry**\ ). - * - * **-ENOENT** if architecture does not support branch records. - * - * long bpf_get_ns_current_pid_tgid(u64 dev, u64 ino, struct bpf_pidns_info *nsdata, u32 size) - * Description - * Returns 0 on success, values for *pid* and *tgid* as seen from the current - * *namespace* will be returned in *nsdata*. - * Return - * 0 on success, or one of the following in case of failure: - * - * **-EINVAL** if dev and inum supplied don't match dev_t and inode number - * with nsfs of current task, or if dev conversion to dev_t lost high bits. - * - * **-ENOENT** if pidns does not exists for the current task. - * - * long bpf_xdp_output(void *ctx, struct bpf_map *map, u64 flags, void *data, u64 size) - * Description - * Write raw *data* blob into a special BPF perf event held by - * *map* of type **BPF_MAP_TYPE_PERF_EVENT_ARRAY**. This perf - * event must have the following attributes: **PERF_SAMPLE_RAW** - * as **sample_type**, **PERF_TYPE_SOFTWARE** as **type**, and - * **PERF_COUNT_SW_BPF_OUTPUT** as **config**. - * - * The *flags* are used to indicate the index in *map* for which - * the value must be put, masked with **BPF_F_INDEX_MASK**. - * Alternatively, *flags* can be set to **BPF_F_CURRENT_CPU** - * to indicate that the index of the current CPU core should be - * used. - * - * The value to write, of *size*, is passed through eBPF stack and - * pointed by *data*. - * - * *ctx* is a pointer to in-kernel struct xdp_buff. - * - * This helper is similar to **bpf_perf_eventoutput**\ () but - * restricted to raw_tracepoint bpf programs. - * Return - * 0 on success, or a negative error in case of failure. - * - * u64 bpf_get_netns_cookie(void *ctx) - * Description - * Retrieve the cookie (generated by the kernel) of the network - * namespace the input *ctx* is associated with. The network - * namespace cookie remains stable for its lifetime and provides - * a global identifier that can be assumed unique. If *ctx* is - * NULL, then the helper returns the cookie for the initial - * network namespace. The cookie itself is very similar to that - * of **bpf_get_socket_cookie**\ () helper, but for network - * namespaces instead of sockets. - * Return - * A 8-byte long opaque number. - * - * u64 bpf_get_current_ancestor_cgroup_id(int ancestor_level) - * Description - * Return id of cgroup v2 that is ancestor of the cgroup associated - * with the current task at the *ancestor_level*. The root cgroup - * is at *ancestor_level* zero and each step down the hierarchy - * increments the level. If *ancestor_level* == level of cgroup - * associated with the current task, then return value will be the - * same as that of **bpf_get_current_cgroup_id**\ (). - * - * The helper is useful to implement policies based on cgroups - * that are upper in hierarchy than immediate cgroup associated - * with the current task. - * - * The format of returned id and helper limitations are same as in - * **bpf_get_current_cgroup_id**\ (). - * Return - * The id is returned or 0 in case the id could not be retrieved. - * - * long bpf_sk_assign(struct sk_buff *skb, void *sk, u64 flags) - * Description - * Helper is overloaded depending on BPF program type. This - * description applies to **BPF_PROG_TYPE_SCHED_CLS** and - * **BPF_PROG_TYPE_SCHED_ACT** programs. - * - * Assign the *sk* to the *skb*. When combined with appropriate - * routing configuration to receive the packet towards the socket, - * will cause *skb* to be delivered to the specified socket. - * Subsequent redirection of *skb* via **bpf_redirect**\ (), - * **bpf_clone_redirect**\ () or other methods outside of BPF may - * interfere with successful delivery to the socket. - * - * This operation is only valid from TC ingress path. - * - * The *flags* argument must be zero. - * Return - * 0 on success, or a negative error in case of failure: - * - * **-EINVAL** if specified *flags* are not supported. - * - * **-ENOENT** if the socket is unavailable for assignment. - * - * **-ENETUNREACH** if the socket is unreachable (wrong netns). - * - * **-EOPNOTSUPP** if the operation is not supported, for example - * a call from outside of TC ingress. - * - * **-ESOCKTNOSUPPORT** if the socket type is not supported - * (reuseport). - * - * long bpf_sk_assign(struct bpf_sk_lookup *ctx, struct bpf_sock *sk, u64 flags) - * Description - * Helper is overloaded depending on BPF program type. This - * description applies to **BPF_PROG_TYPE_SK_LOOKUP** programs. - * - * Select the *sk* as a result of a socket lookup. - * - * For the operation to succeed passed socket must be compatible - * with the packet description provided by the *ctx* object. - * - * L4 protocol (**IPPROTO_TCP** or **IPPROTO_UDP**) must - * be an exact match. While IP family (**AF_INET** or - * **AF_INET6**) must be compatible, that is IPv6 sockets - * that are not v6-only can be selected for IPv4 packets. - * - * Only TCP listeners and UDP unconnected sockets can be - * selected. *sk* can also be NULL to reset any previous - * selection. - * - * *flags* argument can combination of following values: - * - * * **BPF_SK_LOOKUP_F_REPLACE** to override the previous - * socket selection, potentially done by a BPF program - * that ran before us. - * - * * **BPF_SK_LOOKUP_F_NO_REUSEPORT** to skip - * load-balancing within reuseport group for the socket - * being selected. - * - * On success *ctx->sk* will point to the selected socket. - * - * Return - * 0 on success, or a negative errno in case of failure. - * - * * **-EAFNOSUPPORT** if socket family (*sk->family*) is - * not compatible with packet family (*ctx->family*). - * - * * **-EEXIST** if socket has been already selected, - * potentially by another program, and - * **BPF_SK_LOOKUP_F_REPLACE** flag was not specified. - * - * * **-EINVAL** if unsupported flags were specified. - * - * * **-EPROTOTYPE** if socket L4 protocol - * (*sk->protocol*) doesn't match packet protocol - * (*ctx->protocol*). - * - * * **-ESOCKTNOSUPPORT** if socket is not in allowed - * state (TCP listening or UDP unconnected). - * - * u64 bpf_ktime_get_boot_ns(void) - * Description - * Return the time elapsed since system boot, in nanoseconds. - * Does include the time the system was suspended. - * See: **clock_gettime**\ (**CLOCK_BOOTTIME**) - * Return - * Current *ktime*. - * - * long bpf_seq_printf(struct seq_file *m, const char *fmt, u32 fmt_size, const void *data, u32 data_len) - * Description - * **bpf_seq_printf**\ () uses seq_file **seq_printf**\ () to print - * out the format string. - * The *m* represents the seq_file. The *fmt* and *fmt_size* are for - * the format string itself. The *data* and *data_len* are format string - * arguments. The *data* are a **u64** array and corresponding format string - * values are stored in the array. For strings and pointers where pointees - * are accessed, only the pointer values are stored in the *data* array. - * The *data_len* is the size of *data* in bytes. - * - * Formats **%s**, **%p{i,I}{4,6}** requires to read kernel memory. - * Reading kernel memory may fail due to either invalid address or - * valid address but requiring a major memory fault. If reading kernel memory - * fails, the string for **%s** will be an empty string, and the ip - * address for **%p{i,I}{4,6}** will be 0. Not returning error to - * bpf program is consistent with what **bpf_trace_printk**\ () does for now. - * Return - * 0 on success, or a negative error in case of failure: - * - * **-EBUSY** if per-CPU memory copy buffer is busy, can try again - * by returning 1 from bpf program. - * - * **-EINVAL** if arguments are invalid, or if *fmt* is invalid/unsupported. - * - * **-E2BIG** if *fmt* contains too many format specifiers. - * - * **-EOVERFLOW** if an overflow happened: The same object will be tried again. - * - * long bpf_seq_write(struct seq_file *m, const void *data, u32 len) - * Description - * **bpf_seq_write**\ () uses seq_file **seq_write**\ () to write the data. - * The *m* represents the seq_file. The *data* and *len* represent the - * data to write in bytes. - * Return - * 0 on success, or a negative error in case of failure: - * - * **-EOVERFLOW** if an overflow happened: The same object will be tried again. - * - * u64 bpf_sk_cgroup_id(void *sk) - * Description - * Return the cgroup v2 id of the socket *sk*. - * - * *sk* must be a non-**NULL** pointer to a socket, e.g. one - * returned from **bpf_sk_lookup_xxx**\ (), - * **bpf_sk_fullsock**\ (), etc. The format of returned id is - * same as in **bpf_skb_cgroup_id**\ (). - * - * This helper is available only if the kernel was compiled with - * the **CONFIG_SOCK_CGROUP_DATA** configuration option. - * Return - * The id is returned or 0 in case the id could not be retrieved. - * - * u64 bpf_sk_ancestor_cgroup_id(void *sk, int ancestor_level) - * Description - * Return id of cgroup v2 that is ancestor of cgroup associated - * with the *sk* at the *ancestor_level*. The root cgroup is at - * *ancestor_level* zero and each step down the hierarchy - * increments the level. If *ancestor_level* == level of cgroup - * associated with *sk*, then return value will be same as that - * of **bpf_sk_cgroup_id**\ (). - * - * The helper is useful to implement policies based on cgroups - * that are upper in hierarchy than immediate cgroup associated - * with *sk*. - * - * The format of returned id and helper limitations are same as in - * **bpf_sk_cgroup_id**\ (). - * Return - * The id is returned or 0 in case the id could not be retrieved. - * - * long bpf_ringbuf_output(void *ringbuf, void *data, u64 size, u64 flags) - * Description - * Copy *size* bytes from *data* into a ring buffer *ringbuf*. - * If **BPF_RB_NO_WAKEUP** is specified in *flags*, no notification - * of new data availability is sent. - * If **BPF_RB_FORCE_WAKEUP** is specified in *flags*, notification - * of new data availability is sent unconditionally. - * Return - * 0 on success, or a negative error in case of failure. - * - * void *bpf_ringbuf_reserve(void *ringbuf, u64 size, u64 flags) - * Description - * Reserve *size* bytes of payload in a ring buffer *ringbuf*. - * Return - * Valid pointer with *size* bytes of memory available; NULL, - * otherwise. - * - * void bpf_ringbuf_submit(void *data, u64 flags) - * Description - * Submit reserved ring buffer sample, pointed to by *data*. - * If **BPF_RB_NO_WAKEUP** is specified in *flags*, no notification - * of new data availability is sent. - * If **BPF_RB_FORCE_WAKEUP** is specified in *flags*, notification - * of new data availability is sent unconditionally. - * Return - * Nothing. Always succeeds. - * - * void bpf_ringbuf_discard(void *data, u64 flags) - * Description - * Discard reserved ring buffer sample, pointed to by *data*. - * If **BPF_RB_NO_WAKEUP** is specified in *flags*, no notification - * of new data availability is sent. - * If **BPF_RB_FORCE_WAKEUP** is specified in *flags*, notification - * of new data availability is sent unconditionally. - * Return - * Nothing. Always succeeds. - * - * u64 bpf_ringbuf_query(void *ringbuf, u64 flags) - * Description - * Query various characteristics of provided ring buffer. What - * exactly is queries is determined by *flags*: - * - * * **BPF_RB_AVAIL_DATA**: Amount of data not yet consumed. - * * **BPF_RB_RING_SIZE**: The size of ring buffer. - * * **BPF_RB_CONS_POS**: Consumer position (can wrap around). - * * **BPF_RB_PROD_POS**: Producer(s) position (can wrap around). - * - * Data returned is just a momentary snapshot of actual values - * and could be inaccurate, so this facility should be used to - * power heuristics and for reporting, not to make 100% correct - * calculation. - * Return - * Requested value, or 0, if *flags* are not recognized. - * - * long bpf_csum_level(struct sk_buff *skb, u64 level) - * Description - * Change the skbs checksum level by one layer up or down, or - * reset it entirely to none in order to have the stack perform - * checksum validation. The level is applicable to the following - * protocols: TCP, UDP, GRE, SCTP, FCOE. For example, a decap of - * | ETH | IP | UDP | GUE | IP | TCP | into | ETH | IP | TCP | - * through **bpf_skb_adjust_room**\ () helper with passing in - * **BPF_F_ADJ_ROOM_NO_CSUM_RESET** flag would require one call - * to **bpf_csum_level**\ () with **BPF_CSUM_LEVEL_DEC** since - * the UDP header is removed. Similarly, an encap of the latter - * into the former could be accompanied by a helper call to - * **bpf_csum_level**\ () with **BPF_CSUM_LEVEL_INC** if the - * skb is still intended to be processed in higher layers of the - * stack instead of just egressing at tc. - * - * There are three supported level settings at this time: - * - * * **BPF_CSUM_LEVEL_INC**: Increases skb->csum_level for skbs - * with CHECKSUM_UNNECESSARY. - * * **BPF_CSUM_LEVEL_DEC**: Decreases skb->csum_level for skbs - * with CHECKSUM_UNNECESSARY. - * * **BPF_CSUM_LEVEL_RESET**: Resets skb->csum_level to 0 and - * sets CHECKSUM_NONE to force checksum validation by the stack. - * * **BPF_CSUM_LEVEL_QUERY**: No-op, returns the current - * skb->csum_level. - * Return - * 0 on success, or a negative error in case of failure. In the - * case of **BPF_CSUM_LEVEL_QUERY**, the current skb->csum_level - * is returned or the error code -EACCES in case the skb is not - * subject to CHECKSUM_UNNECESSARY. - * - * struct tcp6_sock *bpf_skc_to_tcp6_sock(void *sk) - * Description - * Dynamically cast a *sk* pointer to a *tcp6_sock* pointer. - * Return - * *sk* if casting is valid, or **NULL** otherwise. - * - * struct tcp_sock *bpf_skc_to_tcp_sock(void *sk) - * Description - * Dynamically cast a *sk* pointer to a *tcp_sock* pointer. - * Return - * *sk* if casting is valid, or **NULL** otherwise. - * - * struct tcp_timewait_sock *bpf_skc_to_tcp_timewait_sock(void *sk) - * Description - * Dynamically cast a *sk* pointer to a *tcp_timewait_sock* pointer. - * Return - * *sk* if casting is valid, or **NULL** otherwise. - * - * struct tcp_request_sock *bpf_skc_to_tcp_request_sock(void *sk) - * Description - * Dynamically cast a *sk* pointer to a *tcp_request_sock* pointer. - * Return - * *sk* if casting is valid, or **NULL** otherwise. - * - * struct udp6_sock *bpf_skc_to_udp6_sock(void *sk) - * Description - * Dynamically cast a *sk* pointer to a *udp6_sock* pointer. - * Return - * *sk* if casting is valid, or **NULL** otherwise. - * - * long bpf_get_task_stack(struct task_struct *task, void *buf, u32 size, u64 flags) - * Description - * Return a user or a kernel stack in bpf program provided buffer. - * Note: the user stack will only be populated if the *task* is - * the current task; all other tasks will return -EOPNOTSUPP. - * To achieve this, the helper needs *task*, which is a valid - * pointer to **struct task_struct**. To store the stacktrace, the - * bpf program provides *buf* with a nonnegative *size*. - * - * The last argument, *flags*, holds the number of stack frames to - * skip (from 0 to 255), masked with - * **BPF_F_SKIP_FIELD_MASK**. The next bits can be used to set - * the following flags: - * - * **BPF_F_USER_STACK** - * Collect a user space stack instead of a kernel stack. - * The *task* must be the current task. - * **BPF_F_USER_BUILD_ID** - * Collect buildid+offset instead of ips for user stack, - * only valid if **BPF_F_USER_STACK** is also specified. - * - * **bpf_get_task_stack**\ () can collect up to - * **PERF_MAX_STACK_DEPTH** both kernel and user frames, subject - * to sufficient large buffer size. Note that - * this limit can be controlled with the **sysctl** program, and - * that it should be manually increased in order to profile long - * user stacks (such as stacks for Java programs). To do so, use: - * - * :: - * - * # sysctl kernel.perf_event_max_stack= - * Return - * The non-negative copied *buf* length equal to or less than - * *size* on success, or a negative error in case of failure. - * - * long bpf_load_hdr_opt(struct bpf_sock_ops *skops, void *searchby_res, u32 len, u64 flags) - * Description - * Load header option. Support reading a particular TCP header - * option for bpf program (**BPF_PROG_TYPE_SOCK_OPS**). - * - * If *flags* is 0, it will search the option from the - * *skops*\ **->skb_data**. The comment in **struct bpf_sock_ops** - * has details on what skb_data contains under different - * *skops*\ **->op**. - * - * The first byte of the *searchby_res* specifies the - * kind that it wants to search. - * - * If the searching kind is an experimental kind - * (i.e. 253 or 254 according to RFC6994). It also - * needs to specify the "magic" which is either - * 2 bytes or 4 bytes. It then also needs to - * specify the size of the magic by using - * the 2nd byte which is "kind-length" of a TCP - * header option and the "kind-length" also - * includes the first 2 bytes "kind" and "kind-length" - * itself as a normal TCP header option also does. - * - * For example, to search experimental kind 254 with - * 2 byte magic 0xeB9F, the searchby_res should be - * [ 254, 4, 0xeB, 0x9F, 0, 0, .... 0 ]. - * - * To search for the standard window scale option (3), - * the *searchby_res* should be [ 3, 0, 0, .... 0 ]. - * Note, kind-length must be 0 for regular option. - * - * Searching for No-Op (0) and End-of-Option-List (1) are - * not supported. - * - * *len* must be at least 2 bytes which is the minimal size - * of a header option. - * - * Supported flags: - * - * * **BPF_LOAD_HDR_OPT_TCP_SYN** to search from the - * saved_syn packet or the just-received syn packet. - * - * Return - * > 0 when found, the header option is copied to *searchby_res*. - * The return value is the total length copied. On failure, a - * negative error code is returned: - * - * **-EINVAL** if a parameter is invalid. - * - * **-ENOMSG** if the option is not found. - * - * **-ENOENT** if no syn packet is available when - * **BPF_LOAD_HDR_OPT_TCP_SYN** is used. - * - * **-ENOSPC** if there is not enough space. Only *len* number of - * bytes are copied. - * - * **-EFAULT** on failure to parse the header options in the - * packet. - * - * **-EPERM** if the helper cannot be used under the current - * *skops*\ **->op**. - * - * long bpf_store_hdr_opt(struct bpf_sock_ops *skops, const void *from, u32 len, u64 flags) - * Description - * Store header option. The data will be copied - * from buffer *from* with length *len* to the TCP header. - * - * The buffer *from* should have the whole option that - * includes the kind, kind-length, and the actual - * option data. The *len* must be at least kind-length - * long. The kind-length does not have to be 4 byte - * aligned. The kernel will take care of the padding - * and setting the 4 bytes aligned value to th->doff. - * - * This helper will check for duplicated option - * by searching the same option in the outgoing skb. - * - * This helper can only be called during - * **BPF_SOCK_OPS_WRITE_HDR_OPT_CB**. - * - * Return - * 0 on success, or negative error in case of failure: - * - * **-EINVAL** If param is invalid. - * - * **-ENOSPC** if there is not enough space in the header. - * Nothing has been written - * - * **-EEXIST** if the option already exists. - * - * **-EFAULT** on failrue to parse the existing header options. - * - * **-EPERM** if the helper cannot be used under the current - * *skops*\ **->op**. - * - * long bpf_reserve_hdr_opt(struct bpf_sock_ops *skops, u32 len, u64 flags) - * Description - * Reserve *len* bytes for the bpf header option. The - * space will be used by **bpf_store_hdr_opt**\ () later in - * **BPF_SOCK_OPS_WRITE_HDR_OPT_CB**. - * - * If **bpf_reserve_hdr_opt**\ () is called multiple times, - * the total number of bytes will be reserved. - * - * This helper can only be called during - * **BPF_SOCK_OPS_HDR_OPT_LEN_CB**. - * - * Return - * 0 on success, or negative error in case of failure: - * - * **-EINVAL** if a parameter is invalid. - * - * **-ENOSPC** if there is not enough space in the header. - * - * **-EPERM** if the helper cannot be used under the current - * *skops*\ **->op**. - * - * void *bpf_inode_storage_get(struct bpf_map *map, void *inode, void *value, u64 flags) - * Description - * Get a bpf_local_storage from an *inode*. - * - * Logically, it could be thought of as getting the value from - * a *map* with *inode* as the **key**. From this - * perspective, the usage is not much different from - * **bpf_map_lookup_elem**\ (*map*, **&**\ *inode*) except this - * helper enforces the key must be an inode and the map must also - * be a **BPF_MAP_TYPE_INODE_STORAGE**. - * - * Underneath, the value is stored locally at *inode* instead of - * the *map*. The *map* is used as the bpf-local-storage - * "type". The bpf-local-storage "type" (i.e. the *map*) is - * searched against all bpf_local_storage residing at *inode*. - * - * An optional *flags* (**BPF_LOCAL_STORAGE_GET_F_CREATE**) can be - * used such that a new bpf_local_storage will be - * created if one does not exist. *value* can be used - * together with **BPF_LOCAL_STORAGE_GET_F_CREATE** to specify - * the initial value of a bpf_local_storage. If *value* is - * **NULL**, the new bpf_local_storage will be zero initialized. - * Return - * A bpf_local_storage pointer is returned on success. - * - * **NULL** if not found or there was an error in adding - * a new bpf_local_storage. - * - * int bpf_inode_storage_delete(struct bpf_map *map, void *inode) - * Description - * Delete a bpf_local_storage from an *inode*. - * Return - * 0 on success. - * - * **-ENOENT** if the bpf_local_storage cannot be found. - * - * long bpf_d_path(struct path *path, char *buf, u32 sz) - * Description - * Return full path for given **struct path** object, which - * needs to be the kernel BTF *path* object. The path is - * returned in the provided buffer *buf* of size *sz* and - * is zero terminated. - * - * Return - * On success, the strictly positive length of the string, - * including the trailing NUL character. On error, a negative - * value. - * - * long bpf_copy_from_user(void *dst, u32 size, const void *user_ptr) - * Description - * Read *size* bytes from user space address *user_ptr* and store - * the data in *dst*. This is a wrapper of **copy_from_user**\ (). - * Return - * 0 on success, or a negative error in case of failure. - * - * long bpf_snprintf_btf(char *str, u32 str_size, struct btf_ptr *ptr, u32 btf_ptr_size, u64 flags) - * Description - * Use BTF to store a string representation of *ptr*->ptr in *str*, - * using *ptr*->type_id. This value should specify the type - * that *ptr*->ptr points to. LLVM __builtin_btf_type_id(type, 1) - * can be used to look up vmlinux BTF type ids. Traversing the - * data structure using BTF, the type information and values are - * stored in the first *str_size* - 1 bytes of *str*. Safe copy of - * the pointer data is carried out to avoid kernel crashes during - * operation. Smaller types can use string space on the stack; - * larger programs can use map data to store the string - * representation. - * - * The string can be subsequently shared with userspace via - * bpf_perf_event_output() or ring buffer interfaces. - * bpf_trace_printk() is to be avoided as it places too small - * a limit on string size to be useful. - * - * *flags* is a combination of - * - * **BTF_F_COMPACT** - * no formatting around type information - * **BTF_F_NONAME** - * no struct/union member names/types - * **BTF_F_PTR_RAW** - * show raw (unobfuscated) pointer values; - * equivalent to printk specifier %px. - * **BTF_F_ZERO** - * show zero-valued struct/union members; they - * are not displayed by default - * - * Return - * The number of bytes that were written (or would have been - * written if output had to be truncated due to string size), - * or a negative error in cases of failure. - * - * long bpf_seq_printf_btf(struct seq_file *m, struct btf_ptr *ptr, u32 ptr_size, u64 flags) - * Description - * Use BTF to write to seq_write a string representation of - * *ptr*->ptr, using *ptr*->type_id as per bpf_snprintf_btf(). - * *flags* are identical to those used for bpf_snprintf_btf. - * Return - * 0 on success or a negative error in case of failure. - * - * u64 bpf_skb_cgroup_classid(struct sk_buff *skb) - * Description - * See **bpf_get_cgroup_classid**\ () for the main description. - * This helper differs from **bpf_get_cgroup_classid**\ () in that - * the cgroup v1 net_cls class is retrieved only from the *skb*'s - * associated socket instead of the current process. - * Return - * The id is returned or 0 in case the id could not be retrieved. - * - * long bpf_redirect_neigh(u32 ifindex, struct bpf_redir_neigh *params, int plen, u64 flags) - * Description - * Redirect the packet to another net device of index *ifindex* - * and fill in L2 addresses from neighboring subsystem. This helper - * is somewhat similar to **bpf_redirect**\ (), except that it - * populates L2 addresses as well, meaning, internally, the helper - * relies on the neighbor lookup for the L2 address of the nexthop. - * - * The helper will perform a FIB lookup based on the skb's - * networking header to get the address of the next hop, unless - * this is supplied by the caller in the *params* argument. The - * *plen* argument indicates the len of *params* and should be set - * to 0 if *params* is NULL. - * - * The *flags* argument is reserved and must be 0. The helper is - * currently only supported for tc BPF program types, and enabled - * for IPv4 and IPv6 protocols. - * Return - * The helper returns **TC_ACT_REDIRECT** on success or - * **TC_ACT_SHOT** on error. - * - * void *bpf_per_cpu_ptr(const void *percpu_ptr, u32 cpu) - * Description - * Take a pointer to a percpu ksym, *percpu_ptr*, and return a - * pointer to the percpu kernel variable on *cpu*. A ksym is an - * extern variable decorated with '__ksym'. For ksym, there is a - * global var (either static or global) defined of the same name - * in the kernel. The ksym is percpu if the global var is percpu. - * The returned pointer points to the global percpu var on *cpu*. - * - * bpf_per_cpu_ptr() has the same semantic as per_cpu_ptr() in the - * kernel, except that bpf_per_cpu_ptr() may return NULL. This - * happens if *cpu* is larger than nr_cpu_ids. The caller of - * bpf_per_cpu_ptr() must check the returned value. - * Return - * A pointer pointing to the kernel percpu variable on *cpu*, or - * NULL, if *cpu* is invalid. - * - * void *bpf_this_cpu_ptr(const void *percpu_ptr) - * Description - * Take a pointer to a percpu ksym, *percpu_ptr*, and return a - * pointer to the percpu kernel variable on this cpu. See the - * description of 'ksym' in **bpf_per_cpu_ptr**\ (). - * - * bpf_this_cpu_ptr() has the same semantic as this_cpu_ptr() in - * the kernel. Different from **bpf_per_cpu_ptr**\ (), it would - * never return NULL. - * Return - * A pointer pointing to the kernel percpu variable on this cpu. - * - * long bpf_redirect_peer(u32 ifindex, u64 flags) - * Description - * Redirect the packet to another net device of index *ifindex*. - * This helper is somewhat similar to **bpf_redirect**\ (), except - * that the redirection happens to the *ifindex*' peer device and - * the netns switch takes place from ingress to ingress without - * going through the CPU's backlog queue. - * - * The *flags* argument is reserved and must be 0. The helper is - * currently only supported for tc BPF program types at the ingress - * hook and for veth device types. The peer device must reside in a - * different network namespace. - * Return - * The helper returns **TC_ACT_REDIRECT** on success or - * **TC_ACT_SHOT** on error. */ #define __BPF_FUNC_MAPPER(FN) \ FN(unspec), \ @@ -3884,38 +2889,7 @@ union bpf_attr { FN(get_netns_cookie), \ FN(get_current_ancestor_cgroup_id), \ FN(sk_assign), \ - FN(ktime_get_boot_ns), \ - FN(seq_printf), \ - FN(seq_write), \ - FN(sk_cgroup_id), \ - FN(sk_ancestor_cgroup_id), \ - FN(ringbuf_output), \ - FN(ringbuf_reserve), \ - FN(ringbuf_submit), \ - FN(ringbuf_discard), \ - FN(ringbuf_query), \ - FN(csum_level), \ - FN(skc_to_tcp6_sock), \ - FN(skc_to_tcp_sock), \ - FN(skc_to_tcp_timewait_sock), \ - FN(skc_to_tcp_request_sock), \ - FN(skc_to_udp6_sock), \ - FN(get_task_stack), \ - FN(load_hdr_opt), \ - FN(store_hdr_opt), \ - FN(reserve_hdr_opt), \ - FN(inode_storage_get), \ - FN(inode_storage_delete), \ - FN(d_path), \ - FN(copy_from_user), \ - FN(snprintf_btf), \ - FN(seq_printf_btf), \ - FN(skb_cgroup_classid), \ - FN(redirect_neigh), \ - FN(per_cpu_ptr), \ - FN(this_cpu_ptr), \ - FN(redirect_peer), \ - /* */ + FN(ktime_get_boot_ns), /* integer value in 'imm' field of BPF_CALL instruction selects which helper * function eBPF program intends to call @@ -3930,143 +2904,69 @@ enum bpf_func_id { /* All flags used by eBPF helper functions, placed here. */ /* BPF_FUNC_skb_store_bytes flags. */ -enum { - BPF_F_RECOMPUTE_CSUM = (1ULL << 0), - BPF_F_INVALIDATE_HASH = (1ULL << 1), -}; +#define BPF_F_RECOMPUTE_CSUM (1ULL << 0) +#define BPF_F_INVALIDATE_HASH (1ULL << 1) /* BPF_FUNC_l3_csum_replace and BPF_FUNC_l4_csum_replace flags. * First 4 bits are for passing the header field size. */ -enum { - BPF_F_HDR_FIELD_MASK = 0xfULL, -}; +#define BPF_F_HDR_FIELD_MASK 0xfULL /* BPF_FUNC_l4_csum_replace flags. */ -enum { - BPF_F_PSEUDO_HDR = (1ULL << 4), - BPF_F_MARK_MANGLED_0 = (1ULL << 5), - BPF_F_MARK_ENFORCE = (1ULL << 6), - BPF_F_IPV6 = (1ULL << 7), -}; +#define BPF_F_PSEUDO_HDR (1ULL << 4) +#define BPF_F_MARK_MANGLED_0 (1ULL << 5) +#define BPF_F_MARK_ENFORCE (1ULL << 6) /* BPF_FUNC_clone_redirect and BPF_FUNC_redirect flags. */ -enum { - BPF_F_INGRESS = (1ULL << 0), -}; +#define BPF_F_INGRESS (1ULL << 0) /* BPF_FUNC_skb_set_tunnel_key and BPF_FUNC_skb_get_tunnel_key flags. */ -enum { - BPF_F_TUNINFO_IPV6 = (1ULL << 0), -}; +#define BPF_F_TUNINFO_IPV6 (1ULL << 0) /* flags for both BPF_FUNC_get_stackid and BPF_FUNC_get_stack. */ -enum { - BPF_F_SKIP_FIELD_MASK = 0xffULL, - BPF_F_USER_STACK = (1ULL << 8), +#define BPF_F_SKIP_FIELD_MASK 0xffULL +#define BPF_F_USER_STACK (1ULL << 8) /* flags used by BPF_FUNC_get_stackid only. */ - BPF_F_FAST_STACK_CMP = (1ULL << 9), - BPF_F_REUSE_STACKID = (1ULL << 10), +#define BPF_F_FAST_STACK_CMP (1ULL << 9) +#define BPF_F_REUSE_STACKID (1ULL << 10) /* flags used by BPF_FUNC_get_stack only. */ - BPF_F_USER_BUILD_ID = (1ULL << 11), -}; +#define BPF_F_USER_BUILD_ID (1ULL << 11) /* BPF_FUNC_skb_set_tunnel_key flags. */ -enum { - BPF_F_ZERO_CSUM_TX = (1ULL << 1), - BPF_F_DONT_FRAGMENT = (1ULL << 2), - BPF_F_SEQ_NUMBER = (1ULL << 3), -}; +#define BPF_F_ZERO_CSUM_TX (1ULL << 1) +#define BPF_F_DONT_FRAGMENT (1ULL << 2) +#define BPF_F_SEQ_NUMBER (1ULL << 3) /* BPF_FUNC_perf_event_output, BPF_FUNC_perf_event_read and * BPF_FUNC_perf_event_read_value flags. */ -enum { - BPF_F_INDEX_MASK = 0xffffffffULL, - BPF_F_CURRENT_CPU = BPF_F_INDEX_MASK, +#define BPF_F_INDEX_MASK 0xffffffffULL +#define BPF_F_CURRENT_CPU BPF_F_INDEX_MASK /* BPF_FUNC_perf_event_output for sk_buff input context. */ - BPF_F_CTXLEN_MASK = (0xfffffULL << 32), -}; +#define BPF_F_CTXLEN_MASK (0xfffffULL << 32) /* Current network namespace */ -enum { - BPF_F_CURRENT_NETNS = (-1L), -}; - -/* BPF_FUNC_csum_level level values. */ -enum { - BPF_CSUM_LEVEL_QUERY, - BPF_CSUM_LEVEL_INC, - BPF_CSUM_LEVEL_DEC, - BPF_CSUM_LEVEL_RESET, -}; +#define BPF_F_CURRENT_NETNS (-1L) /* BPF_FUNC_skb_adjust_room flags. */ -enum { - BPF_F_ADJ_ROOM_FIXED_GSO = (1ULL << 0), - BPF_F_ADJ_ROOM_ENCAP_L3_IPV4 = (1ULL << 1), - BPF_F_ADJ_ROOM_ENCAP_L3_IPV6 = (1ULL << 2), - BPF_F_ADJ_ROOM_ENCAP_L4_GRE = (1ULL << 3), - BPF_F_ADJ_ROOM_ENCAP_L4_UDP = (1ULL << 4), - BPF_F_ADJ_ROOM_NO_CSUM_RESET = (1ULL << 5), -}; +#define BPF_F_ADJ_ROOM_FIXED_GSO (1ULL << 0) -enum { - BPF_ADJ_ROOM_ENCAP_L2_MASK = 0xff, - BPF_ADJ_ROOM_ENCAP_L2_SHIFT = 56, -}; +#define BPF_ADJ_ROOM_ENCAP_L2_MASK 0xff +#define BPF_ADJ_ROOM_ENCAP_L2_SHIFT 56 +#define BPF_F_ADJ_ROOM_ENCAP_L3_IPV4 (1ULL << 1) +#define BPF_F_ADJ_ROOM_ENCAP_L3_IPV6 (1ULL << 2) +#define BPF_F_ADJ_ROOM_ENCAP_L4_GRE (1ULL << 3) +#define BPF_F_ADJ_ROOM_ENCAP_L4_UDP (1ULL << 4) #define BPF_F_ADJ_ROOM_ENCAP_L2(len) (((__u64)len & \ BPF_ADJ_ROOM_ENCAP_L2_MASK) \ << BPF_ADJ_ROOM_ENCAP_L2_SHIFT) /* BPF_FUNC_sysctl_get_name flags. */ -enum { - BPF_F_SYSCTL_BASE_NAME = (1ULL << 0), -}; +#define BPF_F_SYSCTL_BASE_NAME (1ULL << 0) -/* BPF_FUNC__storage_get flags */ -enum { - BPF_LOCAL_STORAGE_GET_F_CREATE = (1ULL << 0), - /* BPF_SK_STORAGE_GET_F_CREATE is only kept for backward compatibility - * and BPF_LOCAL_STORAGE_GET_F_CREATE must be used instead. - */ - BPF_SK_STORAGE_GET_F_CREATE = BPF_LOCAL_STORAGE_GET_F_CREATE, -}; - -/* BPF_FUNC_read_branch_records flags. */ -enum { - BPF_F_GET_BRANCH_RECORDS_SIZE = (1ULL << 0), -}; - -/* BPF_FUNC_bpf_ringbuf_commit, BPF_FUNC_bpf_ringbuf_discard, and - * BPF_FUNC_bpf_ringbuf_output flags. - */ -enum { - BPF_RB_NO_WAKEUP = (1ULL << 0), - BPF_RB_FORCE_WAKEUP = (1ULL << 1), -}; - -/* BPF_FUNC_bpf_ringbuf_query flags */ -enum { - BPF_RB_AVAIL_DATA = 0, - BPF_RB_RING_SIZE = 1, - BPF_RB_CONS_POS = 2, - BPF_RB_PROD_POS = 3, -}; - -/* BPF ring buffer constants */ -enum { - BPF_RINGBUF_BUSY_BIT = (1U << 31), - BPF_RINGBUF_DISCARD_BIT = (1U << 30), - BPF_RINGBUF_HDR_SZ = 8, -}; - -/* BPF_FUNC_sk_assign flags in bpf_sk_lookup context. */ -enum { - BPF_SK_LOOKUP_F_REPLACE = (1ULL << 0), - BPF_SK_LOOKUP_F_NO_REUSEPORT = (1ULL << 1), -}; +/* BPF_FUNC_sk_storage_get flags */ +#define BPF_SK_STORAGE_GET_F_CREATE (1ULL << 0) /* Mode for BPF_FUNC_skb_adjust_room helper. */ enum bpf_adj_room_mode { @@ -4201,7 +3101,6 @@ struct bpf_sock { __u32 dst_ip4; __u32 dst_ip6[4]; __u32 state; - __s32 rx_queue_mapping; }; struct bpf_tcp_sock { @@ -4295,34 +3194,6 @@ struct xdp_md { /* Below access go through struct xdp_rxq_info */ __u32 ingress_ifindex; /* rxq->dev->ifindex */ __u32 rx_queue_index; /* rxq->queue_index */ - - __u32 egress_ifindex; /* txq->dev->ifindex */ -}; - -/* DEVMAP map-value layout - * - * The struct data-layout of map-value is a configuration interface. - * New members can only be added to the end of this structure. - */ -struct bpf_devmap_val { - __u32 ifindex; /* device index */ - union { - int fd; /* prog fd on map write */ - __u32 id; /* prog id on map read */ - } bpf_prog; -}; - -/* CPUMAP map-value layout - * - * The struct data-layout of map-value is a configuration interface. - * New members can only be added to the end of this structure. - */ -struct bpf_cpumap_val { - __u32 qsize; /* queue size to remote target CPU */ - union { - int fd; /* prog fd on map write */ - __u32 id; /* prog id on map read */ - } bpf_prog; }; enum sk_action { @@ -4345,8 +3216,6 @@ struct sk_msg_md { __u32 remote_port; /* Stored in network byte order */ __u32 local_port; /* stored in host byte order */ __u32 size; /* Total size of sk_msg */ - - __bpf_md_ptr(struct bpf_sock *, sk); /* current socket */ }; struct sk_reuseport_md { @@ -4423,7 +3292,7 @@ struct bpf_map_info { __u32 map_flags; char name[BPF_OBJ_NAME_LEN]; __u32 ifindex; - __u32 btf_vmlinux_value_type_id; + __u32 :32; __u64 netns_dev; __u64 netns_ino; __u32 btf_id; @@ -4437,44 +3306,9 @@ struct bpf_btf_info { __u32 id; } __attribute__((aligned(8))); -struct bpf_link_info { - __u32 type; - __u32 id; - __u32 prog_id; - union { - struct { - __aligned_u64 tp_name; /* in/out: tp_name buffer ptr */ - __u32 tp_name_len; /* in/out: tp_name buffer len */ - } raw_tracepoint; - struct { - __u32 attach_type; - } tracing; - struct { - __u64 cgroup_id; - __u32 attach_type; - } cgroup; - struct { - __aligned_u64 target_name; /* in/out: target_name buffer ptr */ - __u32 target_name_len; /* in/out: target_name buffer len */ - union { - struct { - __u32 map_id; - } map; - }; - } iter; - struct { - __u32 netns_ino; - __u32 attach_type; - } netns; - struct { - __u32 ifindex; - } xdp; - }; -} __attribute__((aligned(8))); - /* User bpf_sock_addr struct to access socket fields and sockaddr struct passed * by user and intended to be used by socket (e.g. to bind to, depends on - * attach type). + * attach attach type). */ struct bpf_sock_addr { __u32 user_family; /* Allows 4-byte read, but no write. */ @@ -4484,7 +3318,7 @@ struct bpf_sock_addr { __u32 user_ip6[4]; /* Allows 1,2,4,8-byte read and 4,8-byte write. * Stored in network byte order. */ - __u32 user_port; /* Allows 1,2,4-byte read and 4-byte write. + __u32 user_port; /* Allows 4-byte read and write. * Stored in network byte order */ __u32 family; /* Allows 4-byte read, but no write */ @@ -4549,90 +3383,16 @@ struct bpf_sock_ops { __u64 bytes_received; __u64 bytes_acked; __bpf_md_ptr(struct bpf_sock *, sk); - /* [skb_data, skb_data_end) covers the whole TCP header. - * - * BPF_SOCK_OPS_PARSE_HDR_OPT_CB: The packet received - * BPF_SOCK_OPS_HDR_OPT_LEN_CB: Not useful because the - * header has not been written. - * BPF_SOCK_OPS_WRITE_HDR_OPT_CB: The header and options have - * been written so far. - * BPF_SOCK_OPS_ACTIVE_ESTABLISHED_CB: The SYNACK that concludes - * the 3WHS. - * BPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB: The ACK that concludes - * the 3WHS. - * - * bpf_load_hdr_opt() can also be used to read a particular option. - */ - __bpf_md_ptr(void *, skb_data); - __bpf_md_ptr(void *, skb_data_end); - __u32 skb_len; /* The total length of a packet. - * It includes the header, options, - * and payload. - */ - __u32 skb_tcp_flags; /* tcp_flags of the header. It provides - * an easy way to check for tcp_flags - * without parsing skb_data. - * - * In particular, the skb_tcp_flags - * will still be available in - * BPF_SOCK_OPS_HDR_OPT_LEN even though - * the outgoing header has not - * been written yet. - */ }; /* Definitions for bpf_sock_ops_cb_flags */ -enum { - BPF_SOCK_OPS_RTO_CB_FLAG = (1<<0), - BPF_SOCK_OPS_RETRANS_CB_FLAG = (1<<1), - BPF_SOCK_OPS_STATE_CB_FLAG = (1<<2), - BPF_SOCK_OPS_RTT_CB_FLAG = (1<<3), - /* Call bpf for all received TCP headers. The bpf prog will be - * called under sock_ops->op == BPF_SOCK_OPS_PARSE_HDR_OPT_CB - * - * Please refer to the comment in BPF_SOCK_OPS_PARSE_HDR_OPT_CB - * for the header option related helpers that will be useful - * to the bpf programs. - * - * It could be used at the client/active side (i.e. connect() side) - * when the server told it that the server was in syncookie - * mode and required the active side to resend the bpf-written - * options. The active side can keep writing the bpf-options until - * it received a valid packet from the server side to confirm - * the earlier packet (and options) has been received. The later - * example patch is using it like this at the active side when the - * server is in syncookie mode. - * - * The bpf prog will usually turn this off in the common cases. - */ - BPF_SOCK_OPS_PARSE_ALL_HDR_OPT_CB_FLAG = (1<<4), - /* Call bpf when kernel has received a header option that - * the kernel cannot handle. The bpf prog will be called under - * sock_ops->op == BPF_SOCK_OPS_PARSE_HDR_OPT_CB. - * - * Please refer to the comment in BPF_SOCK_OPS_PARSE_HDR_OPT_CB - * for the header option related helpers that will be useful - * to the bpf programs. - */ - BPF_SOCK_OPS_PARSE_UNKNOWN_HDR_OPT_CB_FLAG = (1<<5), - /* Call bpf when the kernel is writing header options for the - * outgoing packet. The bpf prog will first be called - * to reserve space in a skb under - * sock_ops->op == BPF_SOCK_OPS_HDR_OPT_LEN_CB. Then - * the bpf prog will be called to write the header option(s) - * under sock_ops->op == BPF_SOCK_OPS_WRITE_HDR_OPT_CB. - * - * Please refer to the comment in BPF_SOCK_OPS_HDR_OPT_LEN_CB - * and BPF_SOCK_OPS_WRITE_HDR_OPT_CB for the header option - * related helpers that will be useful to the bpf programs. - * - * The kernel gets its chance to reserve space and write - * options first before the BPF program does. - */ - BPF_SOCK_OPS_WRITE_HDR_OPT_CB_FLAG = (1<<6), -/* Mask of all currently supported cb flags */ - BPF_SOCK_OPS_ALL_CB_FLAGS = 0x7F, -}; +#define BPF_SOCK_OPS_RTO_CB_FLAG (1<<0) +#define BPF_SOCK_OPS_RETRANS_CB_FLAG (1<<1) +#define BPF_SOCK_OPS_STATE_CB_FLAG (1<<2) +#define BPF_SOCK_OPS_RTT_CB_FLAG (1<<3) +#define BPF_SOCK_OPS_ALL_CB_FLAGS 0xF /* Mask of all currently + * supported cb flags + */ /* List of known BPF sock_ops operators. * New entries can only be added at the end @@ -4687,63 +3447,6 @@ enum { */ BPF_SOCK_OPS_RTT_CB, /* Called on every RTT. */ - BPF_SOCK_OPS_PARSE_HDR_OPT_CB, /* Parse the header option. - * It will be called to handle - * the packets received at - * an already established - * connection. - * - * sock_ops->skb_data: - * Referring to the received skb. - * It covers the TCP header only. - * - * bpf_load_hdr_opt() can also - * be used to search for a - * particular option. - */ - BPF_SOCK_OPS_HDR_OPT_LEN_CB, /* Reserve space for writing the - * header option later in - * BPF_SOCK_OPS_WRITE_HDR_OPT_CB. - * Arg1: bool want_cookie. (in - * writing SYNACK only) - * - * sock_ops->skb_data: - * Not available because no header has - * been written yet. - * - * sock_ops->skb_tcp_flags: - * The tcp_flags of the - * outgoing skb. (e.g. SYN, ACK, FIN). - * - * bpf_reserve_hdr_opt() should - * be used to reserve space. - */ - BPF_SOCK_OPS_WRITE_HDR_OPT_CB, /* Write the header options - * Arg1: bool want_cookie. (in - * writing SYNACK only) - * - * sock_ops->skb_data: - * Referring to the outgoing skb. - * It covers the TCP header - * that has already been written - * by the kernel and the - * earlier bpf-progs. - * - * sock_ops->skb_tcp_flags: - * The tcp_flags of the outgoing - * skb. (e.g. SYN, ACK, FIN). - * - * bpf_store_hdr_opt() should - * be used to write the - * option. - * - * bpf_load_hdr_opt() can also - * be used to search for a - * particular option that - * has already been written - * by the kernel or the - * earlier bpf-progs. - */ }; /* List of TCP states. There is a build check in net/ipv4/tcp.c to detect @@ -4768,67 +3471,8 @@ enum { BPF_TCP_MAX_STATES /* Leave at the end! */ }; -enum { - TCP_BPF_IW = 1001, /* Set TCP initial congestion window */ - TCP_BPF_SNDCWND_CLAMP = 1002, /* Set sndcwnd_clamp */ - TCP_BPF_DELACK_MAX = 1003, /* Max delay ack in usecs */ - TCP_BPF_RTO_MIN = 1004, /* Min delay ack in usecs */ - /* Copy the SYN pkt to optval - * - * BPF_PROG_TYPE_SOCK_OPS only. It is similar to the - * bpf_getsockopt(TCP_SAVED_SYN) but it does not limit - * to only getting from the saved_syn. It can either get the - * syn packet from: - * - * 1. the just-received SYN packet (only available when writing the - * SYNACK). It will be useful when it is not necessary to - * save the SYN packet for latter use. It is also the only way - * to get the SYN during syncookie mode because the syn - * packet cannot be saved during syncookie. - * - * OR - * - * 2. the earlier saved syn which was done by - * bpf_setsockopt(TCP_SAVE_SYN). - * - * The bpf_getsockopt(TCP_BPF_SYN*) option will hide where the - * SYN packet is obtained. - * - * If the bpf-prog does not need the IP[46] header, the - * bpf-prog can avoid parsing the IP header by using - * TCP_BPF_SYN. Otherwise, the bpf-prog can get both - * IP[46] and TCP header by using TCP_BPF_SYN_IP. - * - * >0: Total number of bytes copied - * -ENOSPC: Not enough space in optval. Only optlen number of - * bytes is copied. - * -ENOENT: The SYN skb is not available now and the earlier SYN pkt - * is not saved by setsockopt(TCP_SAVE_SYN). - */ - TCP_BPF_SYN = 1005, /* Copy the TCP header */ - TCP_BPF_SYN_IP = 1006, /* Copy the IP[46] and TCP header */ - TCP_BPF_SYN_MAC = 1007, /* Copy the MAC, IP[46], and TCP header */ -}; - -enum { - BPF_LOAD_HDR_OPT_TCP_SYN = (1ULL << 0), -}; - -/* args[0] value during BPF_SOCK_OPS_HDR_OPT_LEN_CB and - * BPF_SOCK_OPS_WRITE_HDR_OPT_CB. - */ -enum { - BPF_WRITE_HDR_TCP_CURRENT_MSS = 1, /* Kernel is finding the - * total option spaces - * required for an established - * sk in order to calculate the - * MSS. No skb is actually - * sent. - */ - BPF_WRITE_HDR_TCP_SYNACK_COOKIE = 2, /* Kernel is in syncookie mode - * when sending a SYN. - */ -}; +#define TCP_BPF_IW 1001 /* Set TCP initial congestion window */ +#define TCP_BPF_SNDCWND_CLAMP 1002 /* Set sndcwnd_clamp */ struct bpf_perf_event_value { __u64 counter; @@ -4836,16 +3480,12 @@ struct bpf_perf_event_value { __u64 running; }; -enum { - BPF_DEVCG_ACC_MKNOD = (1ULL << 0), - BPF_DEVCG_ACC_READ = (1ULL << 1), - BPF_DEVCG_ACC_WRITE = (1ULL << 2), -}; +#define BPF_DEVCG_ACC_MKNOD (1ULL << 0) +#define BPF_DEVCG_ACC_READ (1ULL << 1) +#define BPF_DEVCG_ACC_WRITE (1ULL << 2) -enum { - BPF_DEVCG_DEV_BLOCK = (1ULL << 0), - BPF_DEVCG_DEV_CHAR = (1ULL << 1), -}; +#define BPF_DEVCG_DEV_BLOCK (1ULL << 0) +#define BPF_DEVCG_DEV_CHAR (1ULL << 1) struct bpf_cgroup_dev_ctx { /* access_type encoded as (BPF_DEVCG_ACC_* << 16) | BPF_DEVCG_DEV_* */ @@ -4861,10 +3501,8 @@ struct bpf_raw_tracepoint_args { /* DIRECT: Skip the FIB rules and go to FIB table associated with device * OUTPUT: Do lookup from egress perspective; default is ingress */ -enum { - BPF_FIB_LOOKUP_DIRECT = (1U << 0), - BPF_FIB_LOOKUP_OUTPUT = (1U << 1), -}; +#define BPF_FIB_LOOKUP_DIRECT (1U << 0) +#define BPF_FIB_LOOKUP_OUTPUT (1U << 1) enum { BPF_FIB_LKUP_RET_SUCCESS, /* lookup successful */ @@ -4927,16 +3565,6 @@ struct bpf_fib_lookup { __u8 dmac[6]; /* ETH_ALEN */ }; -struct bpf_redir_neigh { - /* network family for lookup (AF_INET, AF_INET6) */ - __u32 nh_family; - /* network address of nexthop; skips fib lookup to find gateway */ - union { - __be32 ipv4_nh; - __u32 ipv6_nh[4]; /* in6_addr; network order */ - }; -}; - enum bpf_task_fd_type { BPF_FD_TYPE_RAW_TRACEPOINT, /* tp name */ BPF_FD_TYPE_TRACEPOINT, /* tp name */ @@ -4946,11 +3574,9 @@ enum bpf_task_fd_type { BPF_FD_TYPE_URETPROBE, /* filename + offset */ }; -enum { - BPF_FLOW_DISSECTOR_F_PARSE_1ST_FRAG = (1U << 0), - BPF_FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL = (1U << 1), - BPF_FLOW_DISSECTOR_F_STOP_AT_ENCAP = (1U << 2), -}; +#define BPF_FLOW_DISSECTOR_F_PARSE_1ST_FRAG (1U << 0) +#define BPF_FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL (1U << 1) +#define BPF_FLOW_DISSECTOR_F_STOP_AT_ENCAP (1U << 2) struct bpf_flow_keys { __u16 nhoff; @@ -5016,53 +3642,4 @@ struct bpf_sockopt { __s32 retval; }; -struct bpf_pidns_info { - __u32 pid; - __u32 tgid; -}; - -/* User accessible data for SK_LOOKUP programs. Add new fields at the end. */ -struct bpf_sk_lookup { - __bpf_md_ptr(struct bpf_sock *, sk); /* Selected socket */ - - __u32 family; /* Protocol family (AF_INET, AF_INET6) */ - __u32 protocol; /* IP protocol (IPPROTO_TCP, IPPROTO_UDP) */ - __u32 remote_ip4; /* Network byte order */ - __u32 remote_ip6[4]; /* Network byte order */ - __u32 remote_port; /* Network byte order */ - __u32 local_ip4; /* Network byte order */ - __u32 local_ip6[4]; /* Network byte order */ - __u32 local_port; /* Host byte order */ -}; - -/* - * struct btf_ptr is used for typed pointer representation; the - * type id is used to render the pointer data as the appropriate type - * via the bpf_snprintf_btf() helper described above. A flags field - - * potentially to specify additional details about the BTF pointer - * (rather than its mode of display) - is included for future use. - * Display flags - BTF_F_* - are passed to bpf_snprintf_btf separately. - */ -struct btf_ptr { - void *ptr; - __u32 type_id; - __u32 flags; /* BTF ptr flags; unused at present. */ -}; - -/* - * Flags to control bpf_snprintf_btf() behaviour. - * - BTF_F_COMPACT: no formatting around type information - * - BTF_F_NONAME: no struct/union member names/types - * - BTF_F_PTR_RAW: show raw (unobfuscated) pointer values; - * equivalent to %px. - * - BTF_F_ZERO: show zero-valued struct/union members; they - * are not displayed by default - */ -enum { - BTF_F_COMPACT = (1ULL << 0), - BTF_F_NONAME = (1ULL << 1), - BTF_F_PTR_RAW = (1ULL << 2), - BTF_F_ZERO = (1ULL << 3), -}; - #endif /* _UAPI__LINUX_BPF_H__ */ diff --git a/include/uapi/linux/btf.h b/include/uapi/linux/btf.h index 284037e56fa8..c02dec97e1ce 100644 --- a/include/uapi/linux/btf.h +++ b/include/uapi/linux/btf.h @@ -145,12 +145,6 @@ enum { BTF_VAR_GLOBAL_ALLOCATED, }; -enum btf_func_linkage { - BTF_FUNC_STATIC = 0, - BTF_FUNC_GLOBAL = 1, - BTF_FUNC_EXTERN = 2, -}; - /* BTF_KIND_VAR is followed by a single "struct btf_var" to describe * additional information related to the variable such as its linkage. */ diff --git a/include/uapi/linux/capability.h b/include/uapi/linux/capability.h index ecd623eea9fe..6e0d68e841cd 100644 --- a/include/uapi/linux/capability.h +++ b/include/uapi/linux/capability.h @@ -274,7 +274,6 @@ struct vfs_ns_cap_data { arbitrary SCSI commands */ /* Allow setting encryption key on loopback filesystem */ /* Allow setting zone reclaim policy */ -/* Allow everything under CAP_BPF and CAP_PERFMON for backward compatibility */ #define CAP_SYS_ADMIN 21 @@ -367,52 +366,8 @@ struct vfs_ns_cap_data { #define CAP_AUDIT_READ 37 -/* - * Allow system performance and observability privileged operations - * using perf_events, i915_perf and other kernel subsystems - */ -#define CAP_PERFMON 38 - -/* - * CAP_BPF allows the following BPF operations: - * - Creating all types of BPF maps - * - Advanced verifier features - * - Indirect variable access - * - Bounded loops - * - BPF to BPF function calls - * - Scalar precision tracking - * - Larger complexity limits - * - Dead code elimination - * - And potentially other features - * - Loading BPF Type Format (BTF) data - * - Retrieve xlated and JITed code of BPF programs - * - Use bpf_spin_lock() helper - * - * CAP_PERFMON relaxes the verifier checks further: - * - BPF progs can use of pointer-to-integer conversions - * - speculation attack hardening measures are bypassed - * - bpf_probe_read to read arbitrary kernel memory is allowed - * - bpf_trace_printk to print kernel memory is allowed - * - * CAP_SYS_ADMIN is required to use bpf_probe_write_user. - * - * CAP_SYS_ADMIN is required to iterate system wide loaded - * programs, maps, links, BTFs and convert their IDs to file descriptors. - * - * CAP_PERFMON and CAP_BPF are required to load tracing programs. - * CAP_NET_ADMIN and CAP_BPF are required to load networking programs. - */ -#define CAP_BPF 39 - - -/* Allow checkpoint/restore related operations */ -/* Allow PID selection during clone3() */ -/* Allow writing to ns_last_pid */ - -#define CAP_CHECKPOINT_RESTORE 40 - -#define CAP_LAST_CAP CAP_CHECKPOINT_RESTORE +#define CAP_LAST_CAP CAP_AUDIT_READ #define cap_valid(x) ((x) >= 0 && (x) <= CAP_LAST_CAP) diff --git a/include/uapi/linux/close_range.h b/include/uapi/linux/close_range.h deleted file mode 100644 index 2d804281554c..000000000000 --- a/include/uapi/linux/close_range.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _UAPI_LINUX_CLOSE_RANGE_H -#define _UAPI_LINUX_CLOSE_RANGE_H - -/* Unshare the file descriptor table before closing file descriptors. */ -#define CLOSE_RANGE_UNSHARE (1U << 1) - -/* Set the FD_CLOEXEC bit instead of closing the file descriptor. */ -#define CLOSE_RANGE_CLOEXEC (1U << 2) - -#endif /* _UAPI_LINUX_CLOSE_RANGE_H */ - diff --git a/include/uapi/linux/fuse.h b/include/uapi/linux/fuse.h index f0521a39a586..a62498fbad3e 100644 --- a/include/uapi/linux/fuse.h +++ b/include/uapi/linux/fuse.h @@ -172,9 +172,6 @@ * - add FUSE_WRITE_KILL_PRIV flag * - add FUSE_SETUPMAPPING and FUSE_REMOVEMAPPING * - add map_alignment to fuse_init_out, add FUSE_MAP_ALIGNMENT flag - * - * 7.32 - * - add flags to fuse_attr, add FUSE_ATTR_SUBMOUNT, add FUSE_SUBMOUNTS */ #ifndef _LINUX_FUSE_H @@ -210,7 +207,7 @@ #define FUSE_KERNEL_VERSION 7 /** Minor version number of this interface */ -#define FUSE_KERNEL_MINOR_VERSION 32 +#define FUSE_KERNEL_MINOR_VERSION 31 /** The node ID of the root inode */ #define FUSE_ROOT_ID 1 @@ -234,7 +231,7 @@ struct fuse_attr { uint32_t gid; uint32_t rdev; uint32_t blksize; - uint32_t flags; + uint32_t padding; }; struct fuse_kstatfs { @@ -316,10 +313,7 @@ struct fuse_file_lock { * FUSE_CACHE_SYMLINKS: cache READLINK responses * FUSE_NO_OPENDIR_SUPPORT: kernel supports zero-message opendir * FUSE_EXPLICIT_INVAL_DATA: only invalidate cached pages on explicit request - * FUSE_MAP_ALIGNMENT: init_out.map_alignment contains log2(byte alignment) for - * foffset and moffset fields in struct - * fuse_setupmapping_out and fuse_removemapping_one. - * FUSE_SUBMOUNTS: kernel supports auto-mounting directory submounts + * FUSE_MAP_ALIGNMENT: map_alignment field is valid */ #define FUSE_ASYNC_READ (1 << 0) #define FUSE_POSIX_LOCKS (1 << 1) @@ -348,7 +342,6 @@ struct fuse_file_lock { #define FUSE_NO_OPENDIR_SUPPORT (1 << 24) #define FUSE_EXPLICIT_INVAL_DATA (1 << 25) #define FUSE_MAP_ALIGNMENT (1 << 26) -#define FUSE_SUBMOUNTS (1 << 27) #define FUSE_PASSTHROUGH (1 << 31) /** @@ -425,13 +418,6 @@ struct fuse_file_lock { */ #define FUSE_FSYNC_FDATASYNC (1 << 0) -/** - * fuse_attr flags - * - * FUSE_ATTR_SUBMOUNT: Object is a submount root - */ -#define FUSE_ATTR_SUBMOUNT (1 << 0) - enum fuse_opcode { FUSE_LOOKUP = 1, FUSE_FORGET = 2, /* no reply */ @@ -516,23 +502,6 @@ struct fuse_entry_out { struct fuse_attr attr; }; -#define FUSE_ACTION_KEEP 0 -#define FUSE_ACTION_REMOVE 1 -#define FUSE_ACTION_REPLACE 2 - -struct fuse_entry_bpf_out { - uint64_t backing_action; - uint64_t backing_fd; - uint64_t bpf_action; - uint64_t bpf_fd; -}; - -struct fuse_entry_bpf { - struct fuse_entry_bpf_out out; - struct file *backing_file; - struct file *bpf_file; -}; - struct fuse_forget_in { uint64_t nlookup; }; @@ -651,12 +620,6 @@ struct fuse_read_in { uint32_t padding; }; -struct fuse_read_out { - uint64_t offset; - uint32_t again; - uint32_t padding; -}; - #define FUSE_COMPAT_WRITE_IN_SIZE 24 struct fuse_write_in { @@ -830,7 +793,7 @@ struct fuse_in_header { uint32_t uid; uint32_t gid; uint32_t pid; - uint32_t error_in; + uint32_t padding; }; struct fuse_out_header { @@ -935,82 +898,4 @@ struct fuse_copy_file_range_in { uint64_t flags; }; -#define FUSE_SETUPMAPPING_FLAG_WRITE (1ull << 0) -#define FUSE_SETUPMAPPING_FLAG_READ (1ull << 1) -struct fuse_setupmapping_in { - /* An already open handle */ - uint64_t fh; - /* Offset into the file to start the mapping */ - uint64_t foffset; - /* Length of mapping required */ - uint64_t len; - /* Flags, FUSE_SETUPMAPPING_FLAG_* */ - uint64_t flags; - /* Offset in Memory Window */ - uint64_t moffset; -}; - -struct fuse_removemapping_in { - /* number of fuse_removemapping_one follows */ - uint32_t count; -}; - -struct fuse_removemapping_one { - /* Offset into the dax window start the unmapping */ - uint64_t moffset; - /* Length of mapping required */ - uint64_t len; -}; - -#define FUSE_REMOVEMAPPING_MAX_ENTRY \ - (PAGE_SIZE / sizeof(struct fuse_removemapping_one)) - -/* - * Fuse BPF Args - * - * Used to communicate with bpf programs to allow checking or altering certain values. - * The end_offset allows the bpf verifier to check boundaries statically. This reflects - * the ends of the buffer. size shows the length that was actually used. - * - */ - -/** One input argument of a request */ -struct fuse_bpf_in_arg { - uint32_t size; - const void *value; - const void *end_offset; -}; - -/** One output argument of a request */ -struct fuse_bpf_arg { - uint32_t size; - void *value; - void *end_offset; -}; - -#define FUSE_MAX_IN_ARGS 5 -#define FUSE_MAX_OUT_ARGS 3 - -#define FUSE_BPF_FORCE (1 << 0) -#define FUSE_BPF_OUT_ARGVAR (1 << 6) - -struct fuse_bpf_args { - uint64_t nodeid; - uint32_t opcode; - uint32_t error_in; - uint32_t in_numargs; - uint32_t out_numargs; - uint32_t flags; - struct fuse_bpf_in_arg in_args[FUSE_MAX_IN_ARGS]; - struct fuse_bpf_arg out_args[FUSE_MAX_OUT_ARGS]; -}; - -#define FUSE_BPF_USER_FILTER 1 -#define FUSE_BPF_BACKING 2 -#define FUSE_BPF_POST_FILTER 4 - -#define FUSE_OPCODE_FILTER 0x0ffff -#define FUSE_PREFILTER 0x10000 -#define FUSE_POSTFILTER 0x20000 - #endif /* _LINUX_FUSE_H */ diff --git a/include/uapi/linux/if_link.h b/include/uapi/linux/if_link.h index 5d03e82b0d35..66e34f0a07fe 100644 --- a/include/uapi/linux/if_link.h +++ b/include/uapi/linux/if_link.h @@ -958,12 +958,11 @@ enum { #define XDP_FLAGS_SKB_MODE (1U << 1) #define XDP_FLAGS_DRV_MODE (1U << 2) #define XDP_FLAGS_HW_MODE (1U << 3) -#define XDP_FLAGS_REPLACE (1U << 4) #define XDP_FLAGS_MODES (XDP_FLAGS_SKB_MODE | \ XDP_FLAGS_DRV_MODE | \ XDP_FLAGS_HW_MODE) #define XDP_FLAGS_MASK (XDP_FLAGS_UPDATE_IF_NOEXIST | \ - XDP_FLAGS_MODES | XDP_FLAGS_REPLACE) + XDP_FLAGS_MODES) /* These are stored into IFLA_XDP_ATTACHED on dump. */ enum { @@ -983,7 +982,6 @@ enum { IFLA_XDP_DRV_PROG_ID, IFLA_XDP_SKB_PROG_ID, IFLA_XDP_HW_PROG_ID, - IFLA_XDP_EXPECTED_FD, __IFLA_XDP_MAX, }; diff --git a/include/uapi/linux/ipv6.h b/include/uapi/linux/ipv6.h index 45406a092e4e..9c0f4a92bcff 100644 --- a/include/uapi/linux/ipv6.h +++ b/include/uapi/linux/ipv6.h @@ -187,7 +187,6 @@ enum { DEVCONF_DISABLE_POLICY, DEVCONF_ACCEPT_RA_RT_INFO_MIN_PLEN, DEVCONF_NDISC_TCLASS, - DEVCONF_ACCEPT_RA_MIN_LFT, DEVCONF_MAX }; diff --git a/include/uapi/linux/msm_ipa.h b/include/uapi/linux/msm_ipa.h index 5f63c7b96479..8d2bb198379d 100644 --- a/include/uapi/linux/msm_ipa.h +++ b/include/uapi/linux/msm_ipa.h @@ -2,7 +2,7 @@ /* * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. * - * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _UAPI_MSM_IPA_H_ @@ -152,9 +152,8 @@ #define IPA_IOCTL_SET_EXT_ROUTER_MODE 95 #define IPA_IOCTL_ADD_DEL_DSCP_PCP_MAPPING 96 #define IPA_IOCTL_SEND_VLAN_MUXID_MAPPING 97 -#define IPA_IOCTL_SEND_TUNNEL_TEMPLATE_INFO 98 -#define IPA_IOCTL_QUERY_TUNNEL_FEATURE 99 -#define IPA_IOCTL_ADD_IPOGRE_MAPPING 100 +#define IPA_IOCTL_SEND_TUNNEL_TEMPLATE_INFO 98 +#define IPA_IOCTL_QUERY_TUNNEL_FEATURE 99 /** * max size of the header to be inserted */ @@ -977,12 +976,8 @@ enum ipa_eth_pdu_evt { #define IPA_ENABLE_ETH_PDU_MODE_EVENT_MAX IPA_ENABLE_ETH_PDU_MODE_EVENT_MAX }; -enum ipa_ipogre_event { - IPA_IPOGRE_NOTIFY_EVENT = IPA_ENABLE_ETH_PDU_MODE_EVENT_MAX, - IPA_IPOGRE_EVENT_MAX -#define IPA_IPOGRE_EVENT_MAX IPA_IPOGRE_EVENT_MAX -}; -#define IPA_EVENT_MAX_NUM (IPA_IPOGRE_EVENT_MAX) + +#define IPA_EVENT_MAX_NUM (IPA_ENABLE_ETH_PDU_MODE_EVENT_MAX) #define IPA_EVENT_MAX ((int)IPA_EVENT_MAX_NUM) /** @@ -1145,6 +1140,48 @@ static inline const char *exception_type_as_str(enum ipa_exception_type t) "???"; } +/** + * Macro ipa_exception_type_pppoe + * + * This macro is for describing which field is to be looked at for + * exception path consideration. + * + * NOTE 1: The field implies an offset into the packet under + * consideration. This offset will be calculated on behalf of + * the user of this API. + * + * NOTE 2: When exceptions are generated/sent in an ipa_exception + * structure, they will considered to be from the upload + * perspective. And when appropriate, a corresponding, and + * perhaps inverted, downlink exception will be automatically + * created on the callers behalf. As an example: If a + * FIELD_UDP_SRC_PORT is sent, an uplink exception will be + * created for udp source port, and a corresponding + * FIELD_UDP_DST_PORT will be automatically created for the + * downlink. + */ +#define FIELD_IP_PROTOCOL_PPPOE (FIELD_ETHER_TYPE + 1) +#define FIELD_TCP_SRC_PORT_PPPOE (FIELD_IP_PROTOCOL_PPPOE + 1) +#define FIELD_TCP_DST_PORT_PPPOE (FIELD_TCP_SRC_PORT_PPPOE + 1) +#define FIELD_UDP_SRC_PORT_PPPOE (FIELD_TCP_DST_PORT_PPPOE + 1) +#define FIELD_UDP_DST_PORT_PPPOE (FIELD_UDP_SRC_PORT_PPPOE + 1) +#define FIELD_ETHER_TYPE_PPPOE (FIELD_UDP_DST_PORT_PPPOE + 1) +#define FIELD_PPPOE_MAX (FIELD_ETHER_TYPE_PPPOE + 1) + +/* Function to read PPPoE exception in string format */ +static inline const char *pppoe_exception_type_as_str(uint32_t t) +{ + return + (t == FIELD_IP_PROTOCOL_PPPOE) ? "pppoe_ip_protocol" : + (t == FIELD_TCP_SRC_PORT_PPPOE) ? "pppoe_tcp_src_port" : + (t == FIELD_TCP_DST_PORT_PPPOE) ? "pppoe_tcp_dst_port" : + (t == FIELD_UDP_SRC_PORT_PPPOE) ? "pppoe_udp_src_port" : + (t == FIELD_UDP_DST_PORT_PPPOE) ? "pppoe_udp_dst_port" : + (t == FIELD_ETHER_TYPE_PPPOE) ? "pppoe_ether_type" : + (t == FIELD_PPPOE_MAX) ? "pppoe_max" : + "???"; +} + #define IP_TYPE_EXCEPTION(x) \ ((x) == FIELD_IP_PROTOCOL || \ (x) == FIELD_TCP_SRC_PORT || \ @@ -1225,6 +1262,7 @@ struct ipa_field_val_equation_gen { * @payload_length: Payload length. * @ext_attrib_mask: Extended attributes. * @l2tp_udp_next_hdr: next header in L2TP tunneling + * @p_exception : exception to enable for mpls-pppoe * @field_val_equ: for finding a value at a particular offset */ struct ipa_rule_attrib { @@ -1270,7 +1308,7 @@ struct ipa_rule_attrib { __u16 payload_length; __u32 ext_attrib_mask; __u8 l2tp_udp_next_hdr; - __u8 padding1; + __u8 p_exception; struct ipa_field_val_equation_gen fld_val_eq; }; @@ -1556,11 +1594,9 @@ enum ipa_hdr_proc_type { IPA_HDR_PROC_EoGRE_HEADER_REMOVE, IPA_HDR_PROC_WWAN_TO_ETHII_EX, IPA_HDR_PROC_GRE_HEADER_ADD, - IPA_HDR_PROC_GRE_HEADER_REMOVE, - IPA_HDR_PROC_IPOGRE_HEADER_ADD, - IPA_HDR_PROC_IPOGRE_HEADER_REMOVE + IPA_HDR_PROC_GRE_HEADER_REMOVE }; -#define IPA_HDR_PROC_MAX (IPA_HDR_PROC_IPOGRE_HEADER_REMOVE + 1) +#define IPA_HDR_PROC_MAX (IPA_HDR_PROC_GRE_HEADER_REMOVE + 1) /** * struct ipa_rt_rule - attributes of a routing rule @@ -1965,68 +2001,6 @@ struct ipa_ioc_eogre_info { struct IpaDscpVlanPcpMap_t map_info; }; -#define MAX_FLOW_PER_IPOGRE_TUNNEL 10 - -/** - * struct ipa_ipogre_info - - * @ipv4_src: Specifies source v4 address if GRE tunnel is ipv4 - * @ipv4_dst: Specifies destination v4 address if GRE tunnel is ipv4 - * @ipv6_src: Specifies source v6 address if GRE tunnel is ipv6 - * @ipv6_dst: Specifies destination v6 address if GRE tunnel is ipv6 - * @iptype: Specifies GRE tunnel's ip address type - * @tunnel_id: Specifies tunnel id - */ - -struct ipa_ipogre_tunnel_info { - uint32_t ipv4_src; - uint32_t ipv4_dst; - uint32_t ipv6_src[4]; - uint32_t ipv6_dst[4]; - enum ipa_ip_type iptype; - uint8_t tunnel_id; -} __packed; - -/** - * struct ipa_ipogre_info - - * @ipv4_src: Specifies source v4 address if GRE tunnel is ipv4 - * @ipv4_src_subnet: Specifies source v4 address subnet if GRE tunnel is ipv4 - * @ipv4_dst: Specifies destination v4 address if GRE tunnel is ipv4 - * @ipv4_dst_subnet: Specifies destination v4 address subnet if GRE tunnel is ipv4 - * @ipv6_src: Specifies source v6 address if GRE tunnel is ipv6 - * @ipv6_src_subnet: Specifies source v6 address subnet if GRE tunnel is ipv6 - * @ipv6_dst: Specifies destination v6 address if GRE tunnel is ipv6 - * @ipv6_dst_subnet: Specifies destination v6 address subnet if GRE tunnel is ipv6 - * @iptype: Specifies GRE tunnel's ip address type - * @protocol: Specifies protocol of the data traffic - */ - -struct ipa_ipogre_flow_info { - uint32_t ipv4_src; - uint32_t ipv4_src_subnet; - uint32_t ipv4_dst; - uint32_t ipv4_dst_subnet; - uint32_t ipv6_src[4]; - uint32_t ipv6_dst[4]; - uint32_t src_port; - uint32_t dst_port; - enum ipa_ip_type iptype; - uint8_t protocol; - uint8_t ipv6_src_subnet; - uint8_t ipv6_dst_subnet; -} __packed; - -/** - * struct ipa_ipogre_info - - * @ipogre_tunnel_info: Specifies tunnel information - * @ipogre_flow_info: Specifies flows to be offloaded - * @ipa_ipogre_num_flow: Specifies number of flow to be offloaded - */ - -struct ipa_ioc_ipogre_info { - struct ipa_ipogre_tunnel_info ipogre_tunnel_info; - struct ipa_ipogre_flow_info ipogre_flow_info[MAX_FLOW_PER_IPOGRE_TUNNEL]; - uint8_t ipa_ipogre_num_flow; -}; /** * struct ipa_eogre_header_add_procparams - * @eth_hdr_retained: Specifies if Ethernet header is retained or not @@ -2118,45 +2092,6 @@ struct ipa_gre_hdr_proc_ctx_params { struct ipa_gre_header_remove_procparams hdr_remove_param; }; -/** - * struct ipa_ipogre_header_add_procparams - - * @input_ip_version: Specifies if Input header is IPV4(0) or IPV6(1) - * @output_ip_version: Specifies if template header's outer IP is IPV4(0) - * or IPV6(1) - * @Tunnel_Id: Tunnel id associated with the header. - * @Mux_Id: Specifies mux id associated with the template header - */ -struct ipa_ipogre_header_add_procparams { - uint32_t input_ip_version : 1; - uint32_t output_ip_version : 1; - uint32_t tunnel_id : 4; - uint32_t mux_id : 8; - uint32_t reserved :18; -}; - -/** - * struct ipa_ipogre_header_remove_procparams - - * @hdr_len_remove: Specifies how much (in bytes) of the header needs - * to be removed - * @input_ip_version: Specifies if Input header is IPV4(0) or IPV6(1) - * @Tunnel_Id: Tunnel id associated with the header. - */ -struct ipa_ipogre_header_remove_procparams { - uint32_t hdr_len_remove : 8; - uint32_t input_ip_version : 1; - uint32_t tunnel_id : 4; - uint32_t reserved :19; -}; - -/** - * struct ipa_ipogre_hdr_proc_ctx_params - - * @hdr_add_param: parameters for header add - * @hdr_remove_param: parameters for header remove - */ -struct ipa_ipogre_hdr_proc_ctx_params { - struct ipa_ipogre_header_add_procparams hdr_add_param; - struct ipa_ipogre_header_remove_procparams hdr_remove_param; -}; /** * struct ipa_eth_II_to_eth_II_ex_procparams - * @input_ethhdr_negative_offset: Specifies where the ethernet hdr offset is @@ -2219,7 +2154,6 @@ struct ipa_hdr_proc_ctx_add { struct ipa_eth_II_to_eth_II_ex_procparams generic_params; struct ipa_wwan_to_eth_II_ex_procparams generic_params_v2; struct ipa_gre_hdr_proc_ctx_params gre_params; - struct ipa_ipogre_hdr_proc_ctx_params ipogre_params; }; #define IPA_L2TP_HDR_PROC_SUPPORT @@ -4330,10 +4264,6 @@ struct ipa_ioc_dscp_pcp_map_info { IPA_IOCTL_QUERY_TUNNEL_FEATURE, \ uint8_t) -#define IPA_IOC_ADD_IPoGRE_MAPPING _IOWR(IPA_IOC_MAGIC, \ - IPA_IOCTL_ADD_IPOGRE_MAPPING, \ - struct ipa_ioc_ipogre_info) - /* * unique magic number of the Tethering bridge ioctls */ diff --git a/include/uapi/linux/sched.h b/include/uapi/linux/sched.h index 4a0217832464..25b4fa00bad1 100644 --- a/include/uapi/linux/sched.h +++ b/include/uapi/linux/sched.h @@ -33,48 +33,31 @@ #define CLONE_NEWNET 0x40000000 /* New network namespace */ #define CLONE_IO 0x80000000 /* Clone io context */ -/* Flags for the clone3() syscall. */ -#define CLONE_CLEAR_SIGHAND 0x100000000ULL /* Clear any signal handler and reset to SIG_DFL. */ - #ifndef __ASSEMBLY__ /** * struct clone_args - arguments for the clone3 syscall - * @flags: Flags for the new process as listed above. - * All flags are valid except for CSIGNAL and - * CLONE_DETACHED. - * @pidfd: If CLONE_PIDFD is set, a pidfd will be - * returned in this argument. - * @child_tid: If CLONE_CHILD_SETTID is set, the TID of the - * child process will be returned in the child's - * memory. - * @parent_tid: If CLONE_PARENT_SETTID is set, the TID of - * the child process will be returned in the - * parent's memory. - * @exit_signal: The exit_signal the parent process will be - * sent when the child exits. - * @stack: Specify the location of the stack for the - * child process. - * Note, @stack is expected to point to the - * lowest address. The stack direction will be - * determined by the kernel and set up - * appropriately based on @stack_size. - * @stack_size: The size of the stack for the child process. - * @tls: If CLONE_SETTLS is set, the tls descriptor - * is set to tls. - * @set_tid: Pointer to an array of type *pid_t. The size - * of the array is defined using @set_tid_size. - * This array is used to select PIDs/TIDs for - * newly created processes. The first element in - * this defines the PID in the most nested PID - * namespace. Each additional element in the array - * defines the PID in the parent PID namespace of - * the original PID namespace. If the array has - * less entries than the number of currently - * nested PID namespaces only the PIDs in the - * corresponding namespaces are set. - * @set_tid_size: This defines the size of the array referenced - * in @set_tid. This cannot be larger than the - * kernel's limit of nested PID namespaces. + * @flags: Flags for the new process as listed above. + * All flags are valid except for CSIGNAL and + * CLONE_DETACHED. + * @pidfd: If CLONE_PIDFD is set, a pidfd will be + * returned in this argument. + * @child_tid: If CLONE_CHILD_SETTID is set, the TID of the + * child process will be returned in the child's + * memory. + * @parent_tid: If CLONE_PARENT_SETTID is set, the TID of + * the child process will be returned in the + * parent's memory. + * @exit_signal: The exit_signal the parent process will be + * sent when the child exits. + * @stack: Specify the location of the stack for the + * child process. + * Note, @stack is expected to point to the + * lowest address. The stack direction will be + * determined by the kernel and set up + * appropriately based on @stack_size. + * @stack_size: The size of the stack for the child process. + * @tls: If CLONE_SETTLS is set, the tls descriptor + * is set to tls. * * The structure is versioned by size and thus extensible. * New struct members must go at the end of the struct and @@ -89,13 +72,10 @@ struct clone_args { __aligned_u64 stack; __aligned_u64 stack_size; __aligned_u64 tls; - __aligned_u64 set_tid; - __aligned_u64 set_tid_size; }; #endif #define CLONE_ARGS_SIZE_VER0 64 /* sizeof first published struct */ -#define CLONE_ARGS_SIZE_VER1 80 /* sizeof second published struct */ /* * Scheduling policies diff --git a/include/uapi/linux/seccomp.h b/include/uapi/linux/seccomp.h index df1f4711d0b7..b5f901af79f0 100644 --- a/include/uapi/linux/seccomp.h +++ b/include/uapi/linux/seccomp.h @@ -76,35 +76,6 @@ struct seccomp_notif { struct seccomp_data data; }; -/* - * Valid flags for struct seccomp_notif_resp - * - * Note, the SECCOMP_USER_NOTIF_FLAG_CONTINUE flag must be used with caution! - * If set by the process supervising the syscalls of another process the - * syscall will continue. This is problematic because of an inherent TOCTOU. - * An attacker can exploit the time while the supervised process is waiting on - * a response from the supervising process to rewrite syscall arguments which - * are passed as pointers of the intercepted syscall. - * It should be absolutely clear that this means that the seccomp notifier - * _cannot_ be used to implement a security policy! It should only ever be used - * in scenarios where a more privileged process supervises the syscalls of a - * lesser privileged process to get around kernel-enforced security - * restrictions when the privileged process deems this safe. In other words, - * in order to continue a syscall the supervising process should be sure that - * another security mechanism or the kernel itself will sufficiently block - * syscalls if arguments are rewritten to something unsafe. - * - * Similar precautions should be applied when stacking SECCOMP_RET_USER_NOTIF - * or SECCOMP_RET_TRACE. For SECCOMP_RET_USER_NOTIF filters acting on the - * same syscall, the most recently added filter takes precedence. This means - * that the new SECCOMP_RET_USER_NOTIF filter can override any - * SECCOMP_IOCTL_NOTIF_SEND from earlier filters, essentially allowing all - * such filtered syscalls to be executed by sending the response - * SECCOMP_USER_NOTIF_FLAG_CONTINUE. Note that SECCOMP_RET_TRACE can equally - * be overriden by SECCOMP_USER_NOTIF_FLAG_CONTINUE. - */ -#define SECCOMP_USER_NOTIF_FLAG_CONTINUE BIT(0) - struct seccomp_notif_resp { __u64 id; __s64 val; diff --git a/include/uapi/linux/sock_diag.h b/include/uapi/linux/sock_diag.h index 5f74a5f6091d..e5925009a652 100644 --- a/include/uapi/linux/sock_diag.h +++ b/include/uapi/linux/sock_diag.h @@ -36,30 +36,4 @@ enum sknetlink_groups { }; #define SKNLGRP_MAX (__SKNLGRP_MAX - 1) -enum { - SK_DIAG_BPF_STORAGE_REQ_NONE, - SK_DIAG_BPF_STORAGE_REQ_MAP_FD, - __SK_DIAG_BPF_STORAGE_REQ_MAX, -}; - -#define SK_DIAG_BPF_STORAGE_REQ_MAX (__SK_DIAG_BPF_STORAGE_REQ_MAX - 1) - -enum { - SK_DIAG_BPF_STORAGE_REP_NONE, - SK_DIAG_BPF_STORAGE, - __SK_DIAG_BPF_STORAGE_REP_MAX, -}; - -#define SK_DIAB_BPF_STORAGE_REP_MAX (__SK_DIAG_BPF_STORAGE_REP_MAX - 1) - -enum { - SK_DIAG_BPF_STORAGE_NONE, - SK_DIAG_BPF_STORAGE_PAD, - SK_DIAG_BPF_STORAGE_MAP_ID, - SK_DIAG_BPF_STORAGE_MAP_VALUE, - __SK_DIAG_BPF_STORAGE_MAX, -}; - -#define SK_DIAG_BPF_STORAGE_MAX (__SK_DIAG_BPF_STORAGE_MAX - 1) - #endif /* _UAPI__SOCK_DIAG_H__ */ diff --git a/include/uapi/linux/usb/video.h b/include/uapi/linux/usb/video.h index c79b6049d9d7..c58854fb7d94 100644 --- a/include/uapi/linux/usb/video.h +++ b/include/uapi/linux/usb/video.h @@ -597,63 +597,5 @@ struct UVC_FRAME_MJPEG(n) { \ __le32 dwFrameInterval[n]; \ } __attribute__ ((packed)) -/* Frame Based Payload - 3.1.1. Frame Based Video Format Descriptor */ -struct uvc_format_framebased { - __u8 bLength; - __u8 bDescriptorType; - __u8 bDescriptorSubType; - __u8 bFormatIndex; - __u8 bNumFrameDescriptors; - __u8 guidFormat[16]; - __u8 bBitsPerPixel; - __u8 bDefaultFrameIndex; - __u8 bAspectRatioX; - __u8 bAspectRatioY; - __u8 bmInterfaceFlags; - __u8 bCopyProtect; - __u8 bVariableSize; -} __attribute__((__packed__)); - -#define UVC_DT_FORMAT_FRAMEBASED_SIZE 28 - -/* Frame Based Payload - 3.1.2. Frame Based Video Frame Descriptor */ -struct uvc_frame_framebased { - __u8 bLength; - __u8 bDescriptorType; - __u8 bDescriptorSubType; - __u8 bFrameIndex; - __u8 bmCapabilities; - __u16 wWidth; - __u16 wHeight; - __u32 dwMinBitRate; - __u32 dwMaxBitRate; - __u32 dwDefaultFrameInterval; - __u8 bFrameIntervalType; - __u32 dwBytesPerLine; - __u32 dwFrameInterval[]; -} __attribute__((__packed__)); - -#define UVC_DT_FRAME_FRAMEBASED_SIZE(n) (26+4*(n)) - -#define UVC_FRAME_FRAMEBASED(n) \ - uvc_frame_framebased_##n - -#define DECLARE_UVC_FRAME_FRAMEBASED(n) \ - struct UVC_FRAME_FRAMEBASED(n) { \ - __u8 bLength; \ - __u8 bDescriptorType; \ - __u8 bDescriptorSubType; \ - __u8 bFrameIndex; \ - __u8 bmCapabilities; \ - __u16 wWidth; \ - __u16 wHeight; \ - __u32 dwMinBitRate; \ - __u32 dwMaxBitRate; \ - __u32 dwDefaultFrameInterval; \ - __u8 bFrameIntervalType; \ - __u32 dwBytesPerLine; \ - __u32 dwFrameInterval[n]; \ - } __attribute__ ((packed)) - #endif /* __LINUX_USB_VIDEO_H */ diff --git a/include/uapi/linux/virtio_fs.h b/include/uapi/linux/virtio_fs.h index 2f64abce781f..b02eb2ac3d99 100644 --- a/include/uapi/linux/virtio_fs.h +++ b/include/uapi/linux/virtio_fs.h @@ -16,7 +16,4 @@ struct virtio_fs_config { __u32 num_request_queues; } __attribute__((packed)); -/* For the id field in virtio_pci_shm_cap */ -#define VIRTIO_FS_SHMCAP_ID_CACHE 0 - #endif /* _UAPI_LINUX_VIRTIO_FS_H */ diff --git a/init/Kconfig b/init/Kconfig index 3fe1fd2b9625..b78b5069ebb8 100644 --- a/init/Kconfig +++ b/init/Kconfig @@ -44,18 +44,6 @@ config CLANG_VERSION int default $(shell,$(srctree)/scripts/clang-version.sh $(CC)) -config AS_IS_GNU - def_bool $(success,test "$(as-name)" = GNU) - -config AS_IS_LLVM - def_bool $(success,test "$(as-name)" = LLVM) - -config AS_VERSION - int - # Use clang version if this is the integrated assembler - default CLANG_VERSION if AS_IS_LLVM - default $(as-version) - config CC_CAN_LINK bool default $(success,$(srctree)/scripts/cc-can-link.sh $(CC) $(CLANG_FLAGS) $(USERCFLAGS) $(USERLDFLAGS) $(m64-flag)) if 64BIT @@ -1681,32 +1669,15 @@ config KALLSYMS_BASE_RELATIVE # end of the "standard kernel features (expert users)" menu # syscall, maps, verifier - -config BPF_LSM - bool "LSM Instrumentation with BPF" - depends on BPF_SYSCALL - depends on SECURITY - depends on BPF_JIT - help - Enables instrumentation of the security hooks with eBPF programs for - implementing dynamic MAC and Audit Policies. - - If you are unsure how to answer this question, answer N. - config BPF_SYSCALL bool "Enable bpf() system call" select BPF select IRQ_WORK - select TASKS_TRACE_RCU - select NET_SOCK_MSG if INET default n help Enable the bpf() system call that allows to manipulate eBPF programs and maps via file descriptors. -config ARCH_WANT_DEFAULT_BPF_JIT - bool - config BPF_JIT_ALWAYS_ON bool "Permanently enable BPF JIT and remove BPF interpreter" depends on BPF_SYSCALL && HAVE_EBPF_JIT && BPF_JIT @@ -1724,12 +1695,6 @@ config BPF_UNPRIV_DEFAULT_OFF disable it by setting it to 1 (from which no other transition to 0 is possible anymore). -config BPF_JIT_DEFAULT_ON - def_bool ARCH_WANT_DEFAULT_BPF_JIT || BPF_JIT_ALWAYS_ON - depends on HAVE_EBPF_JIT && BPF_JIT - -source "kernel/bpf/preload/Kconfig" - config USERFAULTFD bool "Enable userfaultfd() system call" depends on MMU @@ -2390,9 +2355,6 @@ config ASN1 source "kernel/Kconfig.locks" -config ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE - bool - config ARCH_HAS_SYNC_CORE_BEFORE_USERMODE bool diff --git a/init/init_task.c b/init/init_task.c index b27ceec394d7..75eb17517bba 100644 --- a/init/init_task.c +++ b/init/init_task.c @@ -147,10 +147,6 @@ struct task_struct init_task .rcu_tasks_holdout_list = LIST_HEAD_INIT(init_task.rcu_tasks_holdout_list), .rcu_tasks_idle_cpu = -1, #endif -#ifdef CONFIG_TASKS_TRACE_RCU - .trc_reader_nesting = 0, - .trc_holdout_list = LIST_HEAD_INIT(init_task.trc_holdout_list), -#endif #ifdef CONFIG_CPUSETS .mems_allowed_seq = SEQCNT_ZERO(init_task.mems_allowed_seq), #endif @@ -193,9 +189,6 @@ struct task_struct init_task #ifdef CONFIG_SECURITY .security = NULL, #endif -#ifdef CONFIG_SECCOMP_FILTER - .seccomp = { .filter_count = ATOMIC_INIT(0) }, -#endif }; EXPORT_SYMBOL(init_task); diff --git a/init/main.c b/init/main.c index cb6c59db4188..ea899e9d7743 100644 --- a/init/main.c +++ b/init/main.c @@ -39,7 +39,6 @@ #include #include #include -#include #include #include #include @@ -558,7 +557,6 @@ static void __init mm_init(void) */ page_ext_init_flatmem(); init_debug_pagealloc(); - kfence_alloc_pool(); report_meminit(); mem_init(); /* page_owner must be initialized after buddy is ready */ @@ -625,9 +623,6 @@ asmlinkage __visible void __init start_kernel(void) parse_args("Setting init args", after_dashes, NULL, 0, -1, -1, NULL, set_init_arg); - /* Architectural and non-timekeeping rng init, before allocator init */ - random_init_early(command_line); - /* * These use large bootmem allocations and must precede * kmem_cache_init() @@ -692,11 +687,14 @@ asmlinkage __visible void __init start_kernel(void) timekeeping_init(); time_init(); - /* This must be after timekeeping is initialized */ - random_init(); - - /* These make use of the fully initialized rng */ - kfence_init(); + /* + * For best initial stack canary entropy, prepare it after: + * - setup_arch() for any UEFI RNG entropy and boot cmdline access + * - timekeeping_init() for ktime entropy used in random_init() + * - time_init() for making random_get_entropy() work on some platforms + * - random_init() to initialize the RNG from from early entropy sources + */ + random_init(command_line); boot_init_stack_canary(); perf_event_init(); diff --git a/ipc/ipc_sysctl.c b/ipc/ipc_sysctl.c index 3f312bf2b116..affd66537e87 100644 --- a/ipc/ipc_sysctl.c +++ b/ipc/ipc_sysctl.c @@ -24,7 +24,7 @@ static void *get_ipc(struct ctl_table *table) #ifdef CONFIG_PROC_SYSCTL static int proc_ipc_dointvec(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ctl_table ipc_table; @@ -35,7 +35,7 @@ static int proc_ipc_dointvec(struct ctl_table *table, int write, } static int proc_ipc_dointvec_minmax(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ctl_table ipc_table; @@ -46,7 +46,7 @@ static int proc_ipc_dointvec_minmax(struct ctl_table *table, int write, } static int proc_ipc_dointvec_minmax_orphans(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ipc_namespace *ns = current->nsproxy->ipc_ns; int err = proc_ipc_dointvec_minmax(table, write, buffer, lenp, ppos); @@ -59,7 +59,7 @@ static int proc_ipc_dointvec_minmax_orphans(struct ctl_table *table, int write, } static int proc_ipc_doulongvec_minmax(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ctl_table ipc_table; memcpy(&ipc_table, table, sizeof(ipc_table)); @@ -70,7 +70,7 @@ static int proc_ipc_doulongvec_minmax(struct ctl_table *table, int write, } static int proc_ipc_auto_msgmni(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ctl_table ipc_table; int dummy = 0; @@ -85,7 +85,7 @@ static int proc_ipc_auto_msgmni(struct ctl_table *table, int write, } static int proc_ipc_sem_dointvec(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int ret, semmni; struct ipc_namespace *ns = current->nsproxy->ipc_ns; diff --git a/ipc/mq_sysctl.c b/ipc/mq_sysctl.c index 72a92a08c848..7c00f28923a8 100644 --- a/ipc/mq_sysctl.c +++ b/ipc/mq_sysctl.c @@ -19,7 +19,7 @@ static void *get_mq(struct ctl_table *table) } static int proc_mq_dointvec(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ctl_table mq_table; memcpy(&mq_table, table, sizeof(mq_table)); @@ -29,7 +29,7 @@ static int proc_mq_dointvec(struct ctl_table *table, int write, } static int proc_mq_dointvec_minmax(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ctl_table mq_table; memcpy(&mq_table, table, sizeof(mq_table)); diff --git a/kernel/Makefile b/kernel/Makefile index 8db0893feda2..54a4b3311786 100644 --- a/kernel/Makefile +++ b/kernel/Makefile @@ -12,7 +12,6 @@ obj-y = fork.o exec_domain.o panic.o \ notifier.o ksysfs.o cred.o reboot.o \ async.o range.o smpboot.o ucount.o -obj-$(CONFIG_USERMODE_DRIVER) += usermode_driver.o obj-$(CONFIG_MODULES) += kmod.o obj-$(CONFIG_MULTIUSER) += groups.o diff --git a/kernel/bpf/Makefile b/kernel/bpf/Makefile index bfdc63dc74db..b0d78bc0b197 100644 --- a/kernel/bpf/Makefile +++ b/kernel/bpf/Makefile @@ -6,20 +6,18 @@ cflags-nogcse-$(CONFIG_X86)$(CONFIG_CC_IS_GCC) := -fno-gcse endif CFLAGS_core.o += $(call cc-disable-warning, override-init) $(cflags-nogcse-yy) -obj-$(CONFIG_BPF_SYSCALL) += syscall.o verifier.o inode.o helpers.o tnum.o bpf_iter.o map_iter.o task_iter.o prog_iter.o +obj-$(CONFIG_BPF_SYSCALL) += syscall.o verifier.o inode.o helpers.o tnum.o obj-$(CONFIG_BPF_SYSCALL) += hashtab.o arraymap.o percpu_freelist.o bpf_lru_list.o lpm_trie.o map_in_map.o -obj-$(CONFIG_BPF_SYSCALL) += local_storage.o queue_stack_maps.o ringbuf.o -obj-${CONFIG_BPF_LSM} += bpf_inode_storage.o +obj-$(CONFIG_BPF_SYSCALL) += local_storage.o queue_stack_maps.o obj-$(CONFIG_BPF_SYSCALL) += disasm.o -obj-$(CONFIG_BPF_JIT) += trampoline.o obj-$(CONFIG_BPF_SYSCALL) += btf.o -obj-$(CONFIG_BPF_JIT) += dispatcher.o ifeq ($(CONFIG_NET),y) obj-$(CONFIG_BPF_SYSCALL) += devmap.o obj-$(CONFIG_BPF_SYSCALL) += cpumap.o -obj-$(CONFIG_BPF_SYSCALL) += bpf_local_storage.o +ifeq ($(CONFIG_XDP_SOCKETS),y) +obj-$(CONFIG_BPF_SYSCALL) += xskmap.o +endif obj-$(CONFIG_BPF_SYSCALL) += offload.o -obj-$(CONFIG_BPF_SYSCALL) += net_namespace.o endif ifeq ($(CONFIG_PERF_EVENTS),y) obj-$(CONFIG_BPF_SYSCALL) += stackmap.o @@ -31,11 +29,3 @@ endif ifeq ($(CONFIG_SYSFS),y) obj-$(CONFIG_DEBUG_INFO_BTF) += sysfs_btf.o endif -ifeq ($(CONFIG_BPF_JIT),y) -obj-$(CONFIG_BPF_SYSCALL) += bpf_struct_ops.o -obj-${CONFIG_BPF_LSM} += bpf_lsm.o -endif -obj-$(CONFIG_BPF_PRELOAD) += preload/ -ifeq ($(CONFIG_FUSE_BPF),y) -obj-$(CONFIG_BPF_SYSCALL) += bpf_fuse.o -endif diff --git a/kernel/bpf/arraymap.c b/kernel/bpf/arraymap.c index 00546c9f4064..fa46e7a9bf3b 100644 --- a/kernel/bpf/arraymap.c +++ b/kernel/bpf/arraymap.c @@ -10,13 +10,11 @@ #include #include #include -#include #include "map_in_map.h" #define ARRAY_CREATE_FLAG_MASK \ - (BPF_F_NUMA_NODE | BPF_F_MMAPABLE | BPF_F_ACCESS_MASK | \ - BPF_F_PRESERVE_ELEMS | BPF_F_INNER_MAP) + (BPF_F_NUMA_NODE | BPF_F_ACCESS_MASK) static void bpf_array_free_percpu(struct bpf_array *array) { @@ -61,14 +59,6 @@ int array_map_alloc_check(union bpf_attr *attr) (percpu && numa_node != NUMA_NO_NODE)) return -EINVAL; - if (attr->map_type != BPF_MAP_TYPE_ARRAY && - attr->map_flags & (BPF_F_MMAPABLE | BPF_F_INNER_MAP)) - return -EINVAL; - - if (attr->map_type != BPF_MAP_TYPE_PERF_EVENT_ARRAY && - attr->map_flags & BPF_F_PRESERVE_ELEMS) - return -EINVAL; - if (attr->value_size > KMALLOC_MAX_SIZE) /* if value_size is bigger, the user space won't be able to * access the elements. @@ -86,7 +76,7 @@ static struct bpf_map *array_map_alloc(union bpf_attr *attr) bool percpu = attr->map_type == BPF_MAP_TYPE_PERCPU_ARRAY; int ret, numa_node = bpf_map_attr_numa_node(attr); u32 elem_size, index_mask, max_entries; - bool bypass_spec_v1 = bpf_bypass_spec_v1(); + bool unpriv = !capable(CAP_SYS_ADMIN); u64 cost, array_size, mask64; struct bpf_map_memory mem; struct bpf_array *array; @@ -104,7 +94,7 @@ static struct bpf_map *array_map_alloc(union bpf_attr *attr) mask64 -= 1; index_mask = mask64; - if (!bypass_spec_v1) { + if (unpriv) { /* round up array size to nearest power of 2, * since cpu will speculate within index_mask limits */ @@ -115,19 +105,10 @@ static struct bpf_map *array_map_alloc(union bpf_attr *attr) } array_size = sizeof(*array); - if (percpu) { + if (percpu) array_size += (u64) max_entries * sizeof(void *); - } else { - /* rely on vmalloc() to return page-aligned memory and - * ensure array->value is exactly page-aligned - */ - if (attr->map_flags & BPF_F_MMAPABLE) { - array_size = PAGE_ALIGN(array_size); - array_size += PAGE_ALIGN((u64) max_entries * elem_size); - } else { - array_size += (u64) max_entries * elem_size; - } - } + else + array_size += (u64) max_entries * elem_size; /* make sure there is no u32 overflow later in round_up() */ cost = array_size; @@ -139,26 +120,13 @@ static struct bpf_map *array_map_alloc(union bpf_attr *attr) return ERR_PTR(ret); /* allocate all map elements and zero-initialize them */ - if (attr->map_flags & BPF_F_MMAPABLE) { - void *data; - - /* kmalloc'ed memory can't be mmap'ed, use explicit vmalloc */ - data = bpf_map_area_mmapable_alloc(array_size, numa_node); - if (!data) { - bpf_map_charge_finish(&mem); - return ERR_PTR(-ENOMEM); - } - array = data + PAGE_ALIGN(sizeof(struct bpf_array)) - - offsetof(struct bpf_array, value); - } else { - array = bpf_map_area_alloc(array_size, numa_node); - } + array = bpf_map_area_alloc(array_size, numa_node); if (!array) { bpf_map_charge_finish(&mem); return ERR_PTR(-ENOMEM); } array->index_mask = index_mask; - array->map.bypass_spec_v1 = bypass_spec_v1; + array->map.unpriv_array = unpriv; /* copy mandatory map attributes */ bpf_map_init_from_attr(&array->map, attr); @@ -217,7 +185,7 @@ static int array_map_direct_value_meta(const struct bpf_map *map, u64 imm, } /* emit BPF instructions equivalent to C code of array_map_lookup_elem() */ -static int array_map_gen_lookup(struct bpf_map *map, struct bpf_insn *insn_buf) +static u32 array_map_gen_lookup(struct bpf_map *map, struct bpf_insn *insn_buf) { struct bpf_array *array = container_of(map, struct bpf_array, map); struct bpf_insn *insn = insn_buf; @@ -226,12 +194,9 @@ static int array_map_gen_lookup(struct bpf_map *map, struct bpf_insn *insn_buf) const int map_ptr = BPF_REG_1; const int index = BPF_REG_2; - if (map->map_flags & BPF_F_INNER_MAP) - return -EOPNOTSUPP; - *insn++ = BPF_ALU64_IMM(BPF_ADD, map_ptr, offsetof(struct bpf_array, value)); *insn++ = BPF_LDX_MEM(BPF_W, ret, index, 0); - if (!map->bypass_spec_v1) { + if (map->unpriv_array) { *insn++ = BPF_JMP_IMM(BPF_JGE, ret, map->max_entries, 4); *insn++ = BPF_ALU32_IMM(BPF_AND, ret, array->index_mask); } else { @@ -388,23 +353,22 @@ static int array_map_delete_elem(struct bpf_map *map, void *key) return -EINVAL; } -static void *array_map_vmalloc_addr(struct bpf_array *array) -{ - return (void *)round_down((unsigned long)array, PAGE_SIZE); -} - /* Called when map->refcnt goes to zero, either from workqueue or from syscall */ static void array_map_free(struct bpf_map *map) { struct bpf_array *array = container_of(map, struct bpf_array, map); + /* at this point bpf_prog->aux->refcnt == 0 and this map->refcnt == 0, + * so the programs (can be more than one that used this map) were + * disconnected from events. Wait for outstanding programs to complete + * and free the array + */ + synchronize_rcu(); + if (array->map.map_type == BPF_MAP_TYPE_PERCPU_ARRAY) bpf_array_free_percpu(array); - if (array->map.map_flags & BPF_F_MMAPABLE) - bpf_map_area_free(array_map_vmalloc_addr(array)); - else - bpf_map_area_free(array); + bpf_map_area_free(array); } static void array_map_seq_show_elem(struct bpf_map *map, void *key, @@ -483,176 +447,7 @@ static int array_map_check_btf(const struct bpf_map *map, return 0; } -static int array_map_mmap(struct bpf_map *map, struct vm_area_struct *vma) -{ - struct bpf_array *array = container_of(map, struct bpf_array, map); - pgoff_t pgoff = PAGE_ALIGN(sizeof(*array)) >> PAGE_SHIFT; - - if (!(map->map_flags & BPF_F_MMAPABLE)) - return -EINVAL; - - if (vma->vm_pgoff * PAGE_SIZE + (vma->vm_end - vma->vm_start) > - PAGE_ALIGN((u64)array->map.max_entries * array->elem_size)) - return -EINVAL; - - return remap_vmalloc_range(vma, array_map_vmalloc_addr(array), - vma->vm_pgoff + pgoff); -} - -static bool array_map_meta_equal(const struct bpf_map *meta0, - const struct bpf_map *meta1) -{ - if (!bpf_map_meta_equal(meta0, meta1)) - return false; - return meta0->map_flags & BPF_F_INNER_MAP ? true : - meta0->max_entries == meta1->max_entries; -} - -struct bpf_iter_seq_array_map_info { - struct bpf_map *map; - void *percpu_value_buf; - u32 index; -}; - -static void *bpf_array_map_seq_start(struct seq_file *seq, loff_t *pos) -{ - struct bpf_iter_seq_array_map_info *info = seq->private; - struct bpf_map *map = info->map; - struct bpf_array *array; - u32 index; - - if (info->index >= map->max_entries) - return NULL; - - if (*pos == 0) - ++*pos; - array = container_of(map, struct bpf_array, map); - index = info->index & array->index_mask; - if (info->percpu_value_buf) - return array->pptrs[index]; - return array->value + array->elem_size * index; -} - -static void *bpf_array_map_seq_next(struct seq_file *seq, void *v, loff_t *pos) -{ - struct bpf_iter_seq_array_map_info *info = seq->private; - struct bpf_map *map = info->map; - struct bpf_array *array; - u32 index; - - ++*pos; - ++info->index; - if (info->index >= map->max_entries) - return NULL; - - array = container_of(map, struct bpf_array, map); - index = info->index & array->index_mask; - if (info->percpu_value_buf) - return array->pptrs[index]; - return array->value + array->elem_size * index; -} - -static int __bpf_array_map_seq_show(struct seq_file *seq, void *v) -{ - struct bpf_iter_seq_array_map_info *info = seq->private; - struct bpf_iter__bpf_map_elem ctx = {}; - struct bpf_map *map = info->map; - struct bpf_iter_meta meta; - struct bpf_prog *prog; - int off = 0, cpu = 0; - void __percpu **pptr; - u32 size; - - meta.seq = seq; - prog = bpf_iter_get_info(&meta, v == NULL); - if (!prog) - return 0; - - ctx.meta = &meta; - ctx.map = info->map; - if (v) { - ctx.key = &info->index; - - if (!info->percpu_value_buf) { - ctx.value = v; - } else { - pptr = v; - size = round_up(map->value_size, 8); - for_each_possible_cpu(cpu) { - bpf_long_memcpy(info->percpu_value_buf + off, - per_cpu_ptr(pptr, cpu), - size); - off += size; - } - ctx.value = info->percpu_value_buf; - } - } - - return bpf_iter_run_prog(prog, &ctx); -} - -static int bpf_array_map_seq_show(struct seq_file *seq, void *v) -{ - return __bpf_array_map_seq_show(seq, v); -} - -static void bpf_array_map_seq_stop(struct seq_file *seq, void *v) -{ - if (!v) - (void)__bpf_array_map_seq_show(seq, NULL); -} - -static int bpf_iter_init_array_map(void *priv_data, - struct bpf_iter_aux_info *aux) -{ - struct bpf_iter_seq_array_map_info *seq_info = priv_data; - struct bpf_map *map = aux->map; - void *value_buf; - u32 buf_size; - - if (map->map_type == BPF_MAP_TYPE_PERCPU_ARRAY) { - buf_size = round_up(map->value_size, 8) * num_possible_cpus(); - value_buf = kmalloc(buf_size, GFP_USER | __GFP_NOWARN); - if (!value_buf) - return -ENOMEM; - - seq_info->percpu_value_buf = value_buf; - } - - /* bpf_iter_attach_map() acquires a map uref, and the uref may be - * released before or in the middle of iterating map elements, so - * acquire an extra map uref for iterator. - */ - bpf_map_inc_with_uref(map); - seq_info->map = map; - return 0; -} - -static void bpf_iter_fini_array_map(void *priv_data) -{ - struct bpf_iter_seq_array_map_info *seq_info = priv_data; - - bpf_map_put_with_uref(seq_info->map); - kfree(seq_info->percpu_value_buf); -} - -static const struct seq_operations bpf_array_map_seq_ops = { - .start = bpf_array_map_seq_start, - .next = bpf_array_map_seq_next, - .stop = bpf_array_map_seq_stop, - .show = bpf_array_map_seq_show, -}; - -static const struct bpf_iter_seq_info iter_seq_info = { - .seq_ops = &bpf_array_map_seq_ops, - .init_seq_private = bpf_iter_init_array_map, - .fini_seq_private = bpf_iter_fini_array_map, - .seq_priv_size = sizeof(struct bpf_iter_seq_array_map_info), -}; - -static int array_map_btf_id; const struct bpf_map_ops array_map_ops = { - .map_meta_equal = array_map_meta_equal, .map_alloc_check = array_map_alloc_check, .map_alloc = array_map_alloc, .map_free = array_map_free, @@ -663,19 +458,11 @@ const struct bpf_map_ops array_map_ops = { .map_gen_lookup = array_map_gen_lookup, .map_direct_value_addr = array_map_direct_value_addr, .map_direct_value_meta = array_map_direct_value_meta, - .map_mmap = array_map_mmap, .map_seq_show_elem = array_map_seq_show_elem, .map_check_btf = array_map_check_btf, - .map_lookup_batch = generic_map_lookup_batch, - .map_update_batch = generic_map_update_batch, - .map_btf_name = "bpf_array", - .map_btf_id = &array_map_btf_id, - .iter_seq_info = &iter_seq_info, }; -static int percpu_array_map_btf_id; const struct bpf_map_ops percpu_array_map_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc_check = array_map_alloc_check, .map_alloc = array_map_alloc, .map_free = array_map_free, @@ -685,9 +472,6 @@ const struct bpf_map_ops percpu_array_map_ops = { .map_delete_elem = array_map_delete_elem, .map_seq_show_elem = percpu_array_map_seq_show_elem, .map_check_btf = array_map_check_btf, - .map_btf_name = "bpf_array", - .map_btf_id = &percpu_array_map_btf_id, - .iter_seq_info = &iter_seq_info, }; static int fd_array_map_alloc_check(union bpf_attr *attr) @@ -706,6 +490,8 @@ static void fd_array_map_free(struct bpf_map *map) struct bpf_array *array = container_of(map, struct bpf_array, map); int i; + synchronize_rcu(); + /* make sure it's empty */ for (i = 0; i < array->map.max_entries; i++) BUG_ON(array->ptrs[i] != NULL); @@ -757,17 +543,10 @@ int bpf_fd_array_map_update_elem(struct bpf_map *map, struct file *map_file, if (IS_ERR(new_ptr)) return PTR_ERR(new_ptr); - if (map->ops->map_poke_run) { - mutex_lock(&array->aux->poke_mutex); - old_ptr = xchg(array->ptrs + index, new_ptr); - map->ops->map_poke_run(map, index, old_ptr, new_ptr); - mutex_unlock(&array->aux->poke_mutex); - } else { - old_ptr = xchg(array->ptrs + index, new_ptr); - } - + old_ptr = xchg(array->ptrs + index, new_ptr); if (old_ptr) map->ops->map_fd_put_ptr(old_ptr); + return 0; } @@ -780,15 +559,7 @@ static int fd_array_map_delete_elem(struct bpf_map *map, void *key) if (index >= array->map.max_entries) return -E2BIG; - if (map->ops->map_poke_run) { - mutex_lock(&array->aux->poke_mutex); - old_ptr = xchg(array->ptrs + index, NULL); - map->ops->map_poke_run(map, index, old_ptr, NULL); - mutex_unlock(&array->aux->poke_mutex); - } else { - old_ptr = xchg(array->ptrs + index, NULL); - } - + old_ptr = xchg(array->ptrs + index, NULL); if (old_ptr) { map->ops->map_fd_put_ptr(old_ptr); return 0; @@ -857,234 +628,18 @@ static void prog_array_map_seq_show_elem(struct bpf_map *map, void *key, rcu_read_unlock(); } -struct prog_poke_elem { - struct list_head list; - struct bpf_prog_aux *aux; -}; - -static int prog_array_map_poke_track(struct bpf_map *map, - struct bpf_prog_aux *prog_aux) -{ - struct prog_poke_elem *elem; - struct bpf_array_aux *aux; - int ret = 0; - - aux = container_of(map, struct bpf_array, map)->aux; - mutex_lock(&aux->poke_mutex); - list_for_each_entry(elem, &aux->poke_progs, list) { - if (elem->aux == prog_aux) - goto out; - } - - elem = kmalloc(sizeof(*elem), GFP_KERNEL); - if (!elem) { - ret = -ENOMEM; - goto out; - } - - INIT_LIST_HEAD(&elem->list); - /* We must track the program's aux info at this point in time - * since the program pointer itself may not be stable yet, see - * also comment in prog_array_map_poke_run(). - */ - elem->aux = prog_aux; - - list_add_tail(&elem->list, &aux->poke_progs); -out: - mutex_unlock(&aux->poke_mutex); - return ret; -} - -static void prog_array_map_poke_untrack(struct bpf_map *map, - struct bpf_prog_aux *prog_aux) -{ - struct prog_poke_elem *elem, *tmp; - struct bpf_array_aux *aux; - - aux = container_of(map, struct bpf_array, map)->aux; - mutex_lock(&aux->poke_mutex); - list_for_each_entry_safe(elem, tmp, &aux->poke_progs, list) { - if (elem->aux == prog_aux) { - list_del_init(&elem->list); - kfree(elem); - break; - } - } - mutex_unlock(&aux->poke_mutex); -} - -static void prog_array_map_poke_run(struct bpf_map *map, u32 key, - struct bpf_prog *old, - struct bpf_prog *new) -{ - u8 *old_addr, *new_addr, *old_bypass_addr; - struct prog_poke_elem *elem; - struct bpf_array_aux *aux; - - aux = container_of(map, struct bpf_array, map)->aux; - WARN_ON_ONCE(!mutex_is_locked(&aux->poke_mutex)); - - list_for_each_entry(elem, &aux->poke_progs, list) { - struct bpf_jit_poke_descriptor *poke; - int i, ret; - - for (i = 0; i < elem->aux->size_poke_tab; i++) { - poke = &elem->aux->poke_tab[i]; - - /* Few things to be aware of: - * - * 1) We can only ever access aux in this context, but - * not aux->prog since it might not be stable yet and - * there could be danger of use after free otherwise. - * 2) Initially when we start tracking aux, the program - * is not JITed yet and also does not have a kallsyms - * entry. We skip these as poke->tailcall_target_stable - * is not active yet. The JIT will do the final fixup - * before setting it stable. The various - * poke->tailcall_target_stable are successively - * activated, so tail call updates can arrive from here - * while JIT is still finishing its final fixup for - * non-activated poke entries. - * 3) On program teardown, the program's kallsym entry gets - * removed out of RCU callback, but we can only untrack - * from sleepable context, therefore bpf_arch_text_poke() - * might not see that this is in BPF text section and - * bails out with -EINVAL. As these are unreachable since - * RCU grace period already passed, we simply skip them. - * 4) Also programs reaching refcount of zero while patching - * is in progress is okay since we're protected under - * poke_mutex and untrack the programs before the JIT - * buffer is freed. When we're still in the middle of - * patching and suddenly kallsyms entry of the program - * gets evicted, we just skip the rest which is fine due - * to point 3). - * 5) Any other error happening below from bpf_arch_text_poke() - * is a unexpected bug. - */ - if (!READ_ONCE(poke->tailcall_target_stable)) - continue; - if (poke->reason != BPF_POKE_REASON_TAIL_CALL) - continue; - if (poke->tail_call.map != map || - poke->tail_call.key != key) - continue; - - old_bypass_addr = old ? NULL : poke->bypass_addr; - old_addr = old ? (u8 *)old->bpf_func + poke->adj_off : NULL; - new_addr = new ? (u8 *)new->bpf_func + poke->adj_off : NULL; - - if (new) { - ret = bpf_arch_text_poke(poke->tailcall_target, - BPF_MOD_JUMP, - old_addr, new_addr); - BUG_ON(ret < 0 && ret != -EINVAL); - if (!old) { - ret = bpf_arch_text_poke(poke->tailcall_bypass, - BPF_MOD_JUMP, - poke->bypass_addr, - NULL); - BUG_ON(ret < 0 && ret != -EINVAL); - } - } else { - ret = bpf_arch_text_poke(poke->tailcall_bypass, - BPF_MOD_JUMP, - old_bypass_addr, - poke->bypass_addr); - BUG_ON(ret < 0 && ret != -EINVAL); - /* let other CPUs finish the execution of program - * so that it will not possible to expose them - * to invalid nop, stack unwind, nop state - */ - if (!ret) - synchronize_rcu(); - ret = bpf_arch_text_poke(poke->tailcall_target, - BPF_MOD_JUMP, - old_addr, NULL); - BUG_ON(ret < 0 && ret != -EINVAL); - } - } - } -} - -static void prog_array_map_clear_deferred(struct work_struct *work) -{ - struct bpf_map *map = container_of(work, struct bpf_array_aux, - work)->map; - bpf_fd_array_map_clear(map); - bpf_map_put(map); -} - -static void prog_array_map_clear(struct bpf_map *map) -{ - struct bpf_array_aux *aux = container_of(map, struct bpf_array, - map)->aux; - bpf_map_inc(map); - schedule_work(&aux->work); -} - -static struct bpf_map *prog_array_map_alloc(union bpf_attr *attr) -{ - struct bpf_array_aux *aux; - struct bpf_map *map; - - aux = kzalloc(sizeof(*aux), GFP_KERNEL); - if (!aux) - return ERR_PTR(-ENOMEM); - - INIT_WORK(&aux->work, prog_array_map_clear_deferred); - INIT_LIST_HEAD(&aux->poke_progs); - mutex_init(&aux->poke_mutex); - spin_lock_init(&aux->owner.lock); - - map = array_map_alloc(attr); - if (IS_ERR(map)) { - kfree(aux); - return map; - } - - container_of(map, struct bpf_array, map)->aux = aux; - aux->map = map; - - return map; -} - -static void prog_array_map_free(struct bpf_map *map) -{ - struct prog_poke_elem *elem, *tmp; - struct bpf_array_aux *aux; - - aux = container_of(map, struct bpf_array, map)->aux; - list_for_each_entry_safe(elem, tmp, &aux->poke_progs, list) { - list_del_init(&elem->list); - kfree(elem); - } - kfree(aux); - fd_array_map_free(map); -} - -/* prog_array->aux->{type,jited} is a runtime binding. - * Doing static check alone in the verifier is not enough. - * Thus, prog_array_map cannot be used as an inner_map - * and map_meta_equal is not implemented. - */ -static int prog_array_map_btf_id; const struct bpf_map_ops prog_array_map_ops = { .map_alloc_check = fd_array_map_alloc_check, - .map_alloc = prog_array_map_alloc, - .map_free = prog_array_map_free, - .map_poke_track = prog_array_map_poke_track, - .map_poke_untrack = prog_array_map_poke_untrack, - .map_poke_run = prog_array_map_poke_run, + .map_alloc = array_map_alloc, + .map_free = fd_array_map_free, .map_get_next_key = array_map_get_next_key, .map_lookup_elem = fd_array_map_lookup_elem, .map_delete_elem = fd_array_map_delete_elem, .map_fd_get_ptr = prog_fd_array_get_ptr, .map_fd_put_ptr = prog_fd_array_put_ptr, .map_fd_sys_lookup_elem = prog_fd_array_sys_lookup_elem, - .map_release_uref = prog_array_map_clear, + .map_release_uref = bpf_fd_array_map_clear, .map_seq_show_elem = prog_array_map_seq_show_elem, - .map_btf_name = "bpf_array", - .map_btf_id = &prog_array_map_btf_id, }; static struct bpf_event_entry *bpf_event_entry_gen(struct file *perf_file, @@ -1154,9 +709,6 @@ static void perf_event_fd_array_release(struct bpf_map *map, struct bpf_event_entry *ee; int i; - if (map->map_flags & BPF_F_PRESERVE_ELEMS) - return; - rcu_read_lock(); for (i = 0; i < array->map.max_entries; i++) { ee = READ_ONCE(array->ptrs[i]); @@ -1166,19 +718,10 @@ static void perf_event_fd_array_release(struct bpf_map *map, rcu_read_unlock(); } -static void perf_event_fd_array_map_free(struct bpf_map *map) -{ - if (map->map_flags & BPF_F_PRESERVE_ELEMS) - bpf_fd_array_map_clear(map); - fd_array_map_free(map); -} - -static int perf_event_array_map_btf_id; const struct bpf_map_ops perf_event_array_map_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc_check = fd_array_map_alloc_check, .map_alloc = array_map_alloc, - .map_free = perf_event_fd_array_map_free, + .map_free = fd_array_map_free, .map_get_next_key = array_map_get_next_key, .map_lookup_elem = fd_array_map_lookup_elem, .map_delete_elem = fd_array_map_delete_elem, @@ -1186,8 +729,6 @@ const struct bpf_map_ops perf_event_array_map_ops = { .map_fd_put_ptr = perf_event_fd_array_put_ptr, .map_release = perf_event_fd_array_release, .map_check_btf = map_check_no_btf, - .map_btf_name = "bpf_array", - .map_btf_id = &perf_event_array_map_btf_id, }; #ifdef CONFIG_CGROUPS @@ -1210,9 +751,7 @@ static void cgroup_fd_array_free(struct bpf_map *map) fd_array_map_free(map); } -static int cgroup_array_map_btf_id; const struct bpf_map_ops cgroup_array_map_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc_check = fd_array_map_alloc_check, .map_alloc = array_map_alloc, .map_free = cgroup_fd_array_free, @@ -1222,8 +761,6 @@ const struct bpf_map_ops cgroup_array_map_ops = { .map_fd_get_ptr = cgroup_fd_array_get_ptr, .map_fd_put_ptr = cgroup_fd_array_put_ptr, .map_check_btf = map_check_no_btf, - .map_btf_name = "bpf_array", - .map_btf_id = &cgroup_array_map_btf_id, }; #endif @@ -1266,7 +803,7 @@ static void *array_of_map_lookup_elem(struct bpf_map *map, void *key) return READ_ONCE(*inner_map); } -static int array_of_map_gen_lookup(struct bpf_map *map, +static u32 array_of_map_gen_lookup(struct bpf_map *map, struct bpf_insn *insn_buf) { struct bpf_array *array = container_of(map, struct bpf_array, map); @@ -1278,7 +815,7 @@ static int array_of_map_gen_lookup(struct bpf_map *map, *insn++ = BPF_ALU64_IMM(BPF_ADD, map_ptr, offsetof(struct bpf_array, value)); *insn++ = BPF_LDX_MEM(BPF_W, ret, index, 0); - if (!map->bypass_spec_v1) { + if (map->unpriv_array) { *insn++ = BPF_JMP_IMM(BPF_JGE, ret, map->max_entries, 6); *insn++ = BPF_ALU32_IMM(BPF_AND, ret, array->index_mask); } else { @@ -1297,7 +834,6 @@ static int array_of_map_gen_lookup(struct bpf_map *map, return insn - insn_buf; } -static int array_of_maps_map_btf_id; const struct bpf_map_ops array_of_maps_map_ops = { .map_alloc_check = fd_array_map_alloc_check, .map_alloc = array_of_map_alloc, @@ -1310,6 +846,4 @@ const struct bpf_map_ops array_of_maps_map_ops = { .map_fd_sys_lookup_elem = bpf_map_fd_sys_lookup_elem, .map_gen_lookup = array_of_map_gen_lookup, .map_check_btf = map_check_no_btf, - .map_btf_name = "bpf_array", - .map_btf_id = &array_of_maps_map_btf_id, }; diff --git a/kernel/bpf/bpf_fuse.c b/kernel/bpf/bpf_fuse.c deleted file mode 100644 index 00738c84b76e..000000000000 --- a/kernel/bpf/bpf_fuse.c +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2021 Google LLC - -#include -#include - -static const struct bpf_func_proto * -fuse_prog_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) -{ - switch (func_id) { - case BPF_FUNC_trace_printk: - return bpf_get_trace_printk_proto(); - - case BPF_FUNC_get_current_uid_gid: - return &bpf_get_current_uid_gid_proto; - - case BPF_FUNC_get_current_pid_tgid: - return &bpf_get_current_pid_tgid_proto; - - case BPF_FUNC_map_lookup_elem: - return &bpf_map_lookup_elem_proto; - - case BPF_FUNC_map_update_elem: - return &bpf_map_update_elem_proto; - - default: - pr_debug("Invalid fuse bpf func %d\n", func_id); - return NULL; - } -} - -static bool fuse_prog_is_valid_access(int off, int size, - enum bpf_access_type type, - const struct bpf_prog *prog, - struct bpf_insn_access_aux *info) -{ - int i; - - if (off < 0 || off > offsetofend(struct fuse_bpf_args, out_args)) - return false; - - /* TODO This is garbage. Do it properly */ - for (i = 0; i < 5; i++) { - if (off == offsetof(struct fuse_bpf_args, in_args[i].value)) { - info->reg_type = PTR_TO_RDONLY_BUF; - info->ctx_field_size = 256; - if (type != BPF_READ) - return false; - return true; - } - } - for (i = 0; i < 3; i++) { - if (off == offsetof(struct fuse_bpf_args, out_args[i].value)) { - info->reg_type = PTR_TO_RDWR_BUF; - info->ctx_field_size = 256; - return true; - } - } - if (type != BPF_READ) - return false; - - return true; -} - -const struct bpf_verifier_ops fuse_verifier_ops = { - .get_func_proto = fuse_prog_func_proto, - .is_valid_access = fuse_prog_is_valid_access, -}; - -const struct bpf_prog_ops fuse_prog_ops = { -}; - diff --git a/kernel/bpf/bpf_inode_storage.c b/kernel/bpf/bpf_inode_storage.c deleted file mode 100644 index a4ac48c7dada..000000000000 --- a/kernel/bpf/bpf_inode_storage.c +++ /dev/null @@ -1,279 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 Facebook - * Copyright 2020 Google LLC. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DEFINE_BPF_STORAGE_CACHE(inode_cache); - -static struct bpf_local_storage __rcu ** -inode_storage_ptr(void *owner) -{ - struct inode *inode = owner; - struct bpf_storage_blob *bsb; - - bsb = bpf_inode(inode); - if (!bsb) - return NULL; - return &bsb->storage; -} - -static struct bpf_local_storage_data *inode_storage_lookup(struct inode *inode, - struct bpf_map *map, - bool cacheit_lockit) -{ - struct bpf_local_storage *inode_storage; - struct bpf_local_storage_map *smap; - struct bpf_storage_blob *bsb; - - bsb = bpf_inode(inode); - if (!bsb) - return NULL; - - inode_storage = rcu_dereference(bsb->storage); - if (!inode_storage) - return NULL; - - smap = (struct bpf_local_storage_map *)map; - return bpf_local_storage_lookup(inode_storage, smap, cacheit_lockit); -} - -void bpf_inode_storage_free(struct inode *inode) -{ - struct bpf_local_storage_elem *selem; - struct bpf_local_storage *local_storage; - bool free_inode_storage = false; - struct bpf_storage_blob *bsb; - struct hlist_node *n; - - bsb = bpf_inode(inode); - if (!bsb) - return; - - rcu_read_lock(); - - local_storage = rcu_dereference(bsb->storage); - if (!local_storage) { - rcu_read_unlock(); - return; - } - - /* Netiher the bpf_prog nor the bpf-map's syscall - * could be modifying the local_storage->list now. - * Thus, no elem can be added-to or deleted-from the - * local_storage->list by the bpf_prog or by the bpf-map's syscall. - * - * It is racing with bpf_local_storage_map_free() alone - * when unlinking elem from the local_storage->list and - * the map's bucket->list. - */ - raw_spin_lock_bh(&local_storage->lock); - hlist_for_each_entry_safe(selem, n, &local_storage->list, snode) { - /* Always unlink from map before unlinking from - * local_storage. - */ - bpf_selem_unlink_map(selem); - free_inode_storage = bpf_selem_unlink_storage_nolock( - local_storage, selem, false); - } - raw_spin_unlock_bh(&local_storage->lock); - rcu_read_unlock(); - - /* free_inoode_storage should always be true as long as - * local_storage->list was non-empty. - */ - if (free_inode_storage) - kfree_rcu(local_storage, rcu); -} - -static void *bpf_fd_inode_storage_lookup_elem(struct bpf_map *map, void *key) -{ - struct bpf_local_storage_data *sdata; - struct file *f; - int fd; - - fd = *(int *)key; - f = fget_raw(fd); - if (!f) - return ERR_PTR(-EBADF); - - sdata = inode_storage_lookup(f->f_inode, map, true); - fput(f); - return sdata ? sdata->data : NULL; -} - -static int bpf_fd_inode_storage_update_elem(struct bpf_map *map, void *key, - void *value, u64 map_flags) -{ - struct bpf_local_storage_data *sdata; - struct file *f; - int fd; - - fd = *(int *)key; - f = fget_raw(fd); - if (!f) - return -EBADF; - if (!inode_storage_ptr(f->f_inode)) { - fput(f); - return -EBADF; - } - - sdata = bpf_local_storage_update(f->f_inode, - (struct bpf_local_storage_map *)map, - value, map_flags); - fput(f); - return PTR_ERR_OR_ZERO(sdata); -} - -static int inode_storage_delete(struct inode *inode, struct bpf_map *map) -{ - struct bpf_local_storage_data *sdata; - - sdata = inode_storage_lookup(inode, map, false); - if (!sdata) - return -ENOENT; - - bpf_selem_unlink(SELEM(sdata)); - - return 0; -} - -static int bpf_fd_inode_storage_delete_elem(struct bpf_map *map, void *key) -{ - struct file *f; - int fd, err; - - fd = *(int *)key; - f = fget_raw(fd); - if (!f) - return -EBADF; - - err = inode_storage_delete(f->f_inode, map); - fput(f); - return err; -} - -BPF_CALL_4(bpf_inode_storage_get, struct bpf_map *, map, struct inode *, inode, - void *, value, u64, flags) -{ - struct bpf_local_storage_data *sdata; - - if (flags & ~(BPF_LOCAL_STORAGE_GET_F_CREATE)) - return (unsigned long)NULL; - - /* explicitly check that the inode_storage_ptr is not - * NULL as inode_storage_lookup returns NULL in this case and - * bpf_local_storage_update expects the owner to have a - * valid storage pointer. - */ - if (!inode || !inode_storage_ptr(inode)) - return (unsigned long)NULL; - - sdata = inode_storage_lookup(inode, map, true); - if (sdata) - return (unsigned long)sdata->data; - - /* This helper must only called from where the inode is gurranteed - * to have a refcount and cannot be freed. - */ - if (flags & BPF_LOCAL_STORAGE_GET_F_CREATE) { - sdata = bpf_local_storage_update( - inode, (struct bpf_local_storage_map *)map, value, - BPF_NOEXIST); - return IS_ERR(sdata) ? (unsigned long)NULL : - (unsigned long)sdata->data; - } - - return (unsigned long)NULL; -} - -BPF_CALL_2(bpf_inode_storage_delete, - struct bpf_map *, map, struct inode *, inode) -{ - if (!inode) - return -EINVAL; - - /* This helper must only called from where the inode is gurranteed - * to have a refcount and cannot be freed. - */ - return inode_storage_delete(inode, map); -} - -static int notsupp_get_next_key(struct bpf_map *map, void *key, - void *next_key) -{ - return -ENOTSUPP; -} - -static struct bpf_map *inode_storage_map_alloc(union bpf_attr *attr) -{ - struct bpf_local_storage_map *smap; - - smap = bpf_local_storage_map_alloc(attr); - if (IS_ERR(smap)) - return ERR_CAST(smap); - - smap->cache_idx = bpf_local_storage_cache_idx_get(&inode_cache); - return &smap->map; -} - -static void inode_storage_map_free(struct bpf_map *map) -{ - struct bpf_local_storage_map *smap; - - smap = (struct bpf_local_storage_map *)map; - bpf_local_storage_cache_idx_free(&inode_cache, smap->cache_idx); - bpf_local_storage_map_free(smap); -} - -static int inode_storage_map_btf_id; -const struct bpf_map_ops inode_storage_map_ops = { - .map_meta_equal = bpf_map_meta_equal, - .map_alloc_check = bpf_local_storage_map_alloc_check, - .map_alloc = inode_storage_map_alloc, - .map_free = inode_storage_map_free, - .map_get_next_key = notsupp_get_next_key, - .map_lookup_elem = bpf_fd_inode_storage_lookup_elem, - .map_update_elem = bpf_fd_inode_storage_update_elem, - .map_delete_elem = bpf_fd_inode_storage_delete_elem, - .map_check_btf = bpf_local_storage_map_check_btf, - .map_btf_name = "bpf_local_storage_map", - .map_btf_id = &inode_storage_map_btf_id, - .map_owner_storage_ptr = inode_storage_ptr, -}; - -BTF_ID_LIST_SINGLE(bpf_inode_storage_btf_ids, struct, inode) - -const struct bpf_func_proto bpf_inode_storage_get_proto = { - .func = bpf_inode_storage_get, - .gpl_only = false, - .ret_type = RET_PTR_TO_MAP_VALUE_OR_NULL, - .arg1_type = ARG_CONST_MAP_PTR, - .arg2_type = ARG_PTR_TO_BTF_ID, - .arg2_btf_id = &bpf_inode_storage_btf_ids[0], - .arg3_type = ARG_PTR_TO_MAP_VALUE_OR_NULL, - .arg4_type = ARG_ANYTHING, -}; - -const struct bpf_func_proto bpf_inode_storage_delete_proto = { - .func = bpf_inode_storage_delete, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_CONST_MAP_PTR, - .arg2_type = ARG_PTR_TO_BTF_ID, - .arg2_btf_id = &bpf_inode_storage_btf_ids[0], -}; diff --git a/kernel/bpf/bpf_iter.c b/kernel/bpf/bpf_iter.c deleted file mode 100644 index e8957e911de3..000000000000 --- a/kernel/bpf/bpf_iter.c +++ /dev/null @@ -1,663 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2020 Facebook */ - -#include -#include -#include -#include - -struct bpf_iter_target_info { - struct list_head list; - const struct bpf_iter_reg *reg_info; - u32 btf_id; /* cached value */ -}; - -struct bpf_iter_link { - struct bpf_link link; - struct bpf_iter_aux_info aux; - struct bpf_iter_target_info *tinfo; -}; - -struct bpf_iter_priv_data { - struct bpf_iter_target_info *tinfo; - const struct bpf_iter_seq_info *seq_info; - struct bpf_prog *prog; - u64 session_id; - u64 seq_num; - bool done_stop; - u8 target_private[] __aligned(8); -}; - -static struct list_head targets = LIST_HEAD_INIT(targets); -static DEFINE_MUTEX(targets_mutex); - -/* protect bpf_iter_link changes */ -static DEFINE_MUTEX(link_mutex); - -/* incremented on every opened seq_file */ -static atomic64_t session_id; - -static int prepare_seq_file(struct file *file, struct bpf_iter_link *link, - const struct bpf_iter_seq_info *seq_info); - -static void bpf_iter_inc_seq_num(struct seq_file *seq) -{ - struct bpf_iter_priv_data *iter_priv; - - iter_priv = container_of(seq->private, struct bpf_iter_priv_data, - target_private); - iter_priv->seq_num++; -} - -static void bpf_iter_dec_seq_num(struct seq_file *seq) -{ - struct bpf_iter_priv_data *iter_priv; - - iter_priv = container_of(seq->private, struct bpf_iter_priv_data, - target_private); - iter_priv->seq_num--; -} - -static void bpf_iter_done_stop(struct seq_file *seq) -{ - struct bpf_iter_priv_data *iter_priv; - - iter_priv = container_of(seq->private, struct bpf_iter_priv_data, - target_private); - iter_priv->done_stop = true; -} - -/* maximum visited objects before bailing out */ -#define MAX_ITER_OBJECTS 1000000 - -/* bpf_seq_read, a customized and simpler version for bpf iterator. - * no_llseek is assumed for this file. - * The following are differences from seq_read(): - * . fixed buffer size (PAGE_SIZE) - * . assuming no_llseek - * . stop() may call bpf program, handling potential overflow there - */ -static ssize_t bpf_seq_read(struct file *file, char __user *buf, size_t size, - loff_t *ppos) -{ - struct seq_file *seq = file->private_data; - size_t n, offs, copied = 0; - int err = 0, num_objs = 0; - void *p; - - mutex_lock(&seq->lock); - - if (!seq->buf) { - seq->size = PAGE_SIZE << 3; - seq->buf = kvmalloc(seq->size, GFP_KERNEL); - if (!seq->buf) { - err = -ENOMEM; - goto done; - } - } - - if (seq->count) { - n = min(seq->count, size); - err = copy_to_user(buf, seq->buf + seq->from, n); - if (err) { - err = -EFAULT; - goto done; - } - seq->count -= n; - seq->from += n; - copied = n; - goto done; - } - - seq->from = 0; - p = seq->op->start(seq, &seq->index); - if (!p) - goto stop; - if (IS_ERR(p)) { - err = PTR_ERR(p); - seq->op->stop(seq, p); - seq->count = 0; - goto done; - } - - err = seq->op->show(seq, p); - if (err > 0) { - /* object is skipped, decrease seq_num, so next - * valid object can reuse the same seq_num. - */ - bpf_iter_dec_seq_num(seq); - seq->count = 0; - } else if (err < 0 || seq_has_overflowed(seq)) { - if (!err) - err = -E2BIG; - seq->op->stop(seq, p); - seq->count = 0; - goto done; - } - - while (1) { - loff_t pos = seq->index; - - num_objs++; - offs = seq->count; - p = seq->op->next(seq, p, &seq->index); - if (pos == seq->index) { - pr_info_ratelimited("buggy seq_file .next function %ps " - "did not updated position index\n", - seq->op->next); - seq->index++; - } - - if (IS_ERR_OR_NULL(p)) - break; - - /* got a valid next object, increase seq_num */ - bpf_iter_inc_seq_num(seq); - - if (seq->count >= size) - break; - - if (num_objs >= MAX_ITER_OBJECTS) { - if (offs == 0) { - err = -EAGAIN; - seq->op->stop(seq, p); - goto done; - } - break; - } - - err = seq->op->show(seq, p); - if (err > 0) { - bpf_iter_dec_seq_num(seq); - seq->count = offs; - } else if (err < 0 || seq_has_overflowed(seq)) { - seq->count = offs; - if (offs == 0) { - if (!err) - err = -E2BIG; - seq->op->stop(seq, p); - goto done; - } - break; - } - } -stop: - offs = seq->count; - /* bpf program called if !p */ - seq->op->stop(seq, p); - if (!p) { - if (!seq_has_overflowed(seq)) { - bpf_iter_done_stop(seq); - } else { - seq->count = offs; - if (offs == 0) { - err = -E2BIG; - goto done; - } - } - } - - n = min(seq->count, size); - err = copy_to_user(buf, seq->buf, n); - if (err) { - err = -EFAULT; - goto done; - } - copied = n; - seq->count -= n; - seq->from = n; -done: - if (!copied) - copied = err; - else - *ppos += copied; - mutex_unlock(&seq->lock); - return copied; -} - -static const struct bpf_iter_seq_info * -__get_seq_info(struct bpf_iter_link *link) -{ - const struct bpf_iter_seq_info *seq_info; - - if (link->aux.map) { - seq_info = link->aux.map->ops->iter_seq_info; - if (seq_info) - return seq_info; - } - - return link->tinfo->reg_info->seq_info; -} - -static int iter_open(struct inode *inode, struct file *file) -{ - struct bpf_iter_link *link = inode->i_private; - - return prepare_seq_file(file, link, __get_seq_info(link)); -} - -static int iter_release(struct inode *inode, struct file *file) -{ - struct bpf_iter_priv_data *iter_priv; - struct seq_file *seq; - - seq = file->private_data; - if (!seq) - return 0; - - iter_priv = container_of(seq->private, struct bpf_iter_priv_data, - target_private); - - if (iter_priv->seq_info->fini_seq_private) - iter_priv->seq_info->fini_seq_private(seq->private); - - bpf_prog_put(iter_priv->prog); - seq->private = iter_priv; - - return seq_release_private(inode, file); -} - -const struct file_operations bpf_iter_fops = { - .open = iter_open, - .llseek = no_llseek, - .read = bpf_seq_read, - .release = iter_release, -}; - -/* The argument reg_info will be cached in bpf_iter_target_info. - * The common practice is to declare target reg_info as - * a const static variable and passed as an argument to - * bpf_iter_reg_target(). - */ -int bpf_iter_reg_target(const struct bpf_iter_reg *reg_info) -{ - struct bpf_iter_target_info *tinfo; - - tinfo = kzalloc(sizeof(*tinfo), GFP_KERNEL); - if (!tinfo) - return -ENOMEM; - - tinfo->reg_info = reg_info; - INIT_LIST_HEAD(&tinfo->list); - - mutex_lock(&targets_mutex); - list_add(&tinfo->list, &targets); - mutex_unlock(&targets_mutex); - - return 0; -} - -void bpf_iter_unreg_target(const struct bpf_iter_reg *reg_info) -{ - struct bpf_iter_target_info *tinfo; - bool found = false; - - mutex_lock(&targets_mutex); - list_for_each_entry(tinfo, &targets, list) { - if (reg_info == tinfo->reg_info) { - list_del(&tinfo->list); - kfree(tinfo); - found = true; - break; - } - } - mutex_unlock(&targets_mutex); - - WARN_ON(found == false); -} - -static void cache_btf_id(struct bpf_iter_target_info *tinfo, - struct bpf_prog *prog) -{ - tinfo->btf_id = prog->aux->attach_btf_id; -} - -bool bpf_iter_prog_supported(struct bpf_prog *prog) -{ - const char *attach_fname = prog->aux->attach_func_name; - u32 prog_btf_id = prog->aux->attach_btf_id; - const char *prefix = BPF_ITER_FUNC_PREFIX; - struct bpf_iter_target_info *tinfo; - int prefix_len = strlen(prefix); - bool supported = false; - - if (strncmp(attach_fname, prefix, prefix_len)) - return false; - - mutex_lock(&targets_mutex); - list_for_each_entry(tinfo, &targets, list) { - if (tinfo->btf_id && tinfo->btf_id == prog_btf_id) { - supported = true; - break; - } - if (!strcmp(attach_fname + prefix_len, tinfo->reg_info->target)) { - cache_btf_id(tinfo, prog); - supported = true; - break; - } - } - mutex_unlock(&targets_mutex); - - if (supported) { - prog->aux->ctx_arg_info_size = tinfo->reg_info->ctx_arg_info_size; - prog->aux->ctx_arg_info = tinfo->reg_info->ctx_arg_info; - } - - return supported; -} - -static void bpf_iter_link_release(struct bpf_link *link) -{ - struct bpf_iter_link *iter_link = - container_of(link, struct bpf_iter_link, link); - - if (iter_link->tinfo->reg_info->detach_target) - iter_link->tinfo->reg_info->detach_target(&iter_link->aux); -} - -static void bpf_iter_link_dealloc(struct bpf_link *link) -{ - struct bpf_iter_link *iter_link = - container_of(link, struct bpf_iter_link, link); - - kfree(iter_link); -} - -static int bpf_iter_link_replace(struct bpf_link *link, - struct bpf_prog *new_prog, - struct bpf_prog *old_prog) -{ - int ret = 0; - - mutex_lock(&link_mutex); - if (old_prog && link->prog != old_prog) { - ret = -EPERM; - goto out_unlock; - } - - if (link->prog->type != new_prog->type || - link->prog->expected_attach_type != new_prog->expected_attach_type || - link->prog->aux->attach_btf_id != new_prog->aux->attach_btf_id) { - ret = -EINVAL; - goto out_unlock; - } - - old_prog = xchg(&link->prog, new_prog); - bpf_prog_put(old_prog); - -out_unlock: - mutex_unlock(&link_mutex); - return ret; -} - -static void bpf_iter_link_show_fdinfo(const struct bpf_link *link, - struct seq_file *seq) -{ - struct bpf_iter_link *iter_link = - container_of(link, struct bpf_iter_link, link); - bpf_iter_show_fdinfo_t show_fdinfo; - - seq_printf(seq, - "target_name:\t%s\n", - iter_link->tinfo->reg_info->target); - - show_fdinfo = iter_link->tinfo->reg_info->show_fdinfo; - if (show_fdinfo) - show_fdinfo(&iter_link->aux, seq); -} - -static int bpf_iter_link_fill_link_info(const struct bpf_link *link, - struct bpf_link_info *info) -{ - struct bpf_iter_link *iter_link = - container_of(link, struct bpf_iter_link, link); - char __user *ubuf = u64_to_user_ptr(info->iter.target_name); - bpf_iter_fill_link_info_t fill_link_info; - u32 ulen = info->iter.target_name_len; - const char *target_name; - u32 target_len; - - if (!ulen ^ !ubuf) - return -EINVAL; - - target_name = iter_link->tinfo->reg_info->target; - target_len = strlen(target_name); - info->iter.target_name_len = target_len + 1; - - if (ubuf) { - if (ulen >= target_len + 1) { - if (copy_to_user(ubuf, target_name, target_len + 1)) - return -EFAULT; - } else { - char zero = '\0'; - - if (copy_to_user(ubuf, target_name, ulen - 1)) - return -EFAULT; - if (put_user(zero, ubuf + ulen - 1)) - return -EFAULT; - return -ENOSPC; - } - } - - fill_link_info = iter_link->tinfo->reg_info->fill_link_info; - if (fill_link_info) - return fill_link_info(&iter_link->aux, info); - - return 0; -} - -static const struct bpf_link_ops bpf_iter_link_lops = { - .release = bpf_iter_link_release, - .dealloc = bpf_iter_link_dealloc, - .update_prog = bpf_iter_link_replace, - .show_fdinfo = bpf_iter_link_show_fdinfo, - .fill_link_info = bpf_iter_link_fill_link_info, -}; - -bool bpf_link_is_iter(struct bpf_link *link) -{ - return link->ops == &bpf_iter_link_lops; -} - -int bpf_iter_link_attach(const union bpf_attr *attr, struct bpf_prog *prog) -{ - union bpf_iter_link_info __user *ulinfo; - struct bpf_link_primer link_primer; - struct bpf_iter_target_info *tinfo; - union bpf_iter_link_info linfo; - struct bpf_iter_link *link; - u32 prog_btf_id, linfo_len; - bool existed = false; - int err; - - if (attr->link_create.target_fd || attr->link_create.flags) - return -EINVAL; - - memset(&linfo, 0, sizeof(union bpf_iter_link_info)); - - ulinfo = u64_to_user_ptr(attr->link_create.iter_info); - linfo_len = attr->link_create.iter_info_len; - if (!ulinfo ^ !linfo_len) - return -EINVAL; - - if (ulinfo) { - err = bpf_check_uarg_tail_zero(ulinfo, sizeof(linfo), - linfo_len); - if (err) - return err; - linfo_len = min_t(u32, linfo_len, sizeof(linfo)); - if (copy_from_user(&linfo, ulinfo, linfo_len)) - return -EFAULT; - } - - prog_btf_id = prog->aux->attach_btf_id; - mutex_lock(&targets_mutex); - list_for_each_entry(tinfo, &targets, list) { - if (tinfo->btf_id == prog_btf_id) { - existed = true; - break; - } - } - mutex_unlock(&targets_mutex); - if (!existed) - return -ENOENT; - - link = kzalloc(sizeof(*link), GFP_USER | __GFP_NOWARN); - if (!link) - return -ENOMEM; - - bpf_link_init(&link->link, BPF_LINK_TYPE_ITER, &bpf_iter_link_lops, prog); - link->tinfo = tinfo; - - err = bpf_link_prime(&link->link, &link_primer); - if (err) { - kfree(link); - return err; - } - - if (tinfo->reg_info->attach_target) { - err = tinfo->reg_info->attach_target(prog, &linfo, &link->aux); - if (err) { - bpf_link_cleanup(&link_primer); - return err; - } - } - - return bpf_link_settle(&link_primer); -} - -static void init_seq_meta(struct bpf_iter_priv_data *priv_data, - struct bpf_iter_target_info *tinfo, - const struct bpf_iter_seq_info *seq_info, - struct bpf_prog *prog) -{ - priv_data->tinfo = tinfo; - priv_data->seq_info = seq_info; - priv_data->prog = prog; - priv_data->session_id = atomic64_inc_return(&session_id); - priv_data->seq_num = 0; - priv_data->done_stop = false; -} - -static int prepare_seq_file(struct file *file, struct bpf_iter_link *link, - const struct bpf_iter_seq_info *seq_info) -{ - struct bpf_iter_priv_data *priv_data; - struct bpf_iter_target_info *tinfo; - struct bpf_prog *prog; - u32 total_priv_dsize; - struct seq_file *seq; - int err = 0; - - mutex_lock(&link_mutex); - prog = link->link.prog; - bpf_prog_inc(prog); - mutex_unlock(&link_mutex); - - tinfo = link->tinfo; - total_priv_dsize = offsetof(struct bpf_iter_priv_data, target_private) + - seq_info->seq_priv_size; - priv_data = __seq_open_private(file, seq_info->seq_ops, - total_priv_dsize); - if (!priv_data) { - err = -ENOMEM; - goto release_prog; - } - - if (seq_info->init_seq_private) { - err = seq_info->init_seq_private(priv_data->target_private, &link->aux); - if (err) - goto release_seq_file; - } - - init_seq_meta(priv_data, tinfo, seq_info, prog); - seq = file->private_data; - seq->private = priv_data->target_private; - - return 0; - -release_seq_file: - seq_release_private(file->f_inode, file); - file->private_data = NULL; -release_prog: - bpf_prog_put(prog); - return err; -} - -int bpf_iter_new_fd(struct bpf_link *link) -{ - struct bpf_iter_link *iter_link; - struct file *file; - unsigned int flags; - int err, fd; - - if (link->ops != &bpf_iter_link_lops) - return -EINVAL; - - flags = O_RDONLY | O_CLOEXEC; - fd = get_unused_fd_flags(flags); - if (fd < 0) - return fd; - - file = anon_inode_getfile("bpf_iter", &bpf_iter_fops, NULL, flags); - if (IS_ERR(file)) { - err = PTR_ERR(file); - goto free_fd; - } - - iter_link = container_of(link, struct bpf_iter_link, link); - err = prepare_seq_file(file, iter_link, __get_seq_info(iter_link)); - if (err) - goto free_file; - - fd_install(fd, file); - return fd; - -free_file: - fput(file); -free_fd: - put_unused_fd(fd); - return err; -} - -struct bpf_prog *bpf_iter_get_info(struct bpf_iter_meta *meta, bool in_stop) -{ - struct bpf_iter_priv_data *iter_priv; - struct seq_file *seq; - void *seq_priv; - - seq = meta->seq; - if (seq->file->f_op != &bpf_iter_fops) - return NULL; - - seq_priv = seq->private; - iter_priv = container_of(seq_priv, struct bpf_iter_priv_data, - target_private); - - if (in_stop && iter_priv->done_stop) - return NULL; - - meta->session_id = iter_priv->session_id; - meta->seq_num = iter_priv->seq_num; - - return iter_priv->prog; -} - -int bpf_iter_run_prog(struct bpf_prog *prog, void *ctx) -{ - int ret; - - rcu_read_lock(); - migrate_disable(); - ret = BPF_PROG_RUN(prog, ctx); - migrate_enable(); - rcu_read_unlock(); - - /* bpf program can only return 0 or 1: - * 0 : okay - * 1 : retry the same object - * The bpf_iter_run_prog() return value - * will be seq_ops->show() return value. - */ - return ret == 0 ? 0 : -EAGAIN; -} diff --git a/kernel/bpf/bpf_local_storage.c b/kernel/bpf/bpf_local_storage.c deleted file mode 100644 index f75396572620..000000000000 --- a/kernel/bpf/bpf_local_storage.c +++ /dev/null @@ -1,610 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2019 Facebook */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define BPF_LOCAL_STORAGE_CREATE_FLAG_MASK (BPF_F_NO_PREALLOC | BPF_F_CLONE) - -static struct bpf_local_storage_map_bucket * -select_bucket(struct bpf_local_storage_map *smap, - struct bpf_local_storage_elem *selem) -{ - return &smap->buckets[hash_ptr(selem, smap->bucket_log)]; -} - -static int mem_charge(struct bpf_local_storage_map *smap, void *owner, u32 size) -{ - struct bpf_map *map = &smap->map; - - if (!map->ops->map_local_storage_charge) - return 0; - - return map->ops->map_local_storage_charge(smap, owner, size); -} - -static void mem_uncharge(struct bpf_local_storage_map *smap, void *owner, - u32 size) -{ - struct bpf_map *map = &smap->map; - - if (map->ops->map_local_storage_uncharge) - map->ops->map_local_storage_uncharge(smap, owner, size); -} - -static struct bpf_local_storage __rcu ** -owner_storage(struct bpf_local_storage_map *smap, void *owner) -{ - struct bpf_map *map = &smap->map; - - return map->ops->map_owner_storage_ptr(owner); -} - -static bool selem_linked_to_storage_lockless(const struct bpf_local_storage_elem *selem) -{ - return !hlist_unhashed_lockless(&selem->snode); -} - -static bool selem_linked_to_storage(const struct bpf_local_storage_elem *selem) -{ - return !hlist_unhashed(&selem->snode); -} - -static bool selem_linked_to_map_lockless(const struct bpf_local_storage_elem *selem) -{ - return !hlist_unhashed_lockless(&selem->map_node); -} - -static bool selem_linked_to_map(const struct bpf_local_storage_elem *selem) -{ - return !hlist_unhashed(&selem->map_node); -} - -struct bpf_local_storage_elem * -bpf_selem_alloc(struct bpf_local_storage_map *smap, void *owner, - void *value, bool charge_mem) -{ - struct bpf_local_storage_elem *selem; - - if (charge_mem && mem_charge(smap, owner, smap->elem_size)) - return NULL; - - selem = kzalloc(smap->elem_size, GFP_ATOMIC | __GFP_NOWARN); - if (selem) { - if (value) - copy_map_value(&smap->map, SDATA(selem)->data, value); - return selem; - } - - if (charge_mem) - mem_uncharge(smap, owner, smap->elem_size); - - return NULL; -} - -/* local_storage->lock must be held and selem->local_storage == local_storage. - * The caller must ensure selem->smap is still valid to be - * dereferenced for its smap->elem_size and smap->cache_idx. - */ -bool bpf_selem_unlink_storage_nolock(struct bpf_local_storage *local_storage, - struct bpf_local_storage_elem *selem, - bool uncharge_mem) -{ - struct bpf_local_storage_map *smap; - bool free_local_storage; - void *owner; - - smap = rcu_dereference(SDATA(selem)->smap); - owner = local_storage->owner; - - /* All uncharging on the owner must be done first. - * The owner may be freed once the last selem is unlinked - * from local_storage. - */ - if (uncharge_mem) - mem_uncharge(smap, owner, smap->elem_size); - - free_local_storage = hlist_is_singular_node(&selem->snode, - &local_storage->list); - if (free_local_storage) { - mem_uncharge(smap, owner, sizeof(struct bpf_local_storage)); - local_storage->owner = NULL; - - /* After this RCU_INIT, owner may be freed and cannot be used */ - RCU_INIT_POINTER(*owner_storage(smap, owner), NULL); - - /* local_storage is not freed now. local_storage->lock is - * still held and raw_spin_unlock_bh(&local_storage->lock) - * will be done by the caller. - * - * Although the unlock will be done under - * rcu_read_lock(), it is more intutivie to - * read if kfree_rcu(local_storage, rcu) is done - * after the raw_spin_unlock_bh(&local_storage->lock). - * - * Hence, a "bool free_local_storage" is returned - * to the caller which then calls the kfree_rcu() - * after unlock. - */ - } - hlist_del_init_rcu(&selem->snode); - if (rcu_access_pointer(local_storage->cache[smap->cache_idx]) == - SDATA(selem)) - RCU_INIT_POINTER(local_storage->cache[smap->cache_idx], NULL); - - kfree_rcu(selem, rcu); - - return free_local_storage; -} - -static void __bpf_selem_unlink_storage(struct bpf_local_storage_elem *selem) -{ - struct bpf_local_storage *local_storage; - bool free_local_storage = false; - - if (unlikely(!selem_linked_to_storage_lockless(selem))) - /* selem has already been unlinked from sk */ - return; - - local_storage = rcu_dereference(selem->local_storage); - raw_spin_lock_bh(&local_storage->lock); - if (likely(selem_linked_to_storage(selem))) - free_local_storage = bpf_selem_unlink_storage_nolock( - local_storage, selem, true); - raw_spin_unlock_bh(&local_storage->lock); - - if (free_local_storage) - kfree_rcu(local_storage, rcu); -} - -void bpf_selem_link_storage_nolock(struct bpf_local_storage *local_storage, - struct bpf_local_storage_elem *selem) -{ - RCU_INIT_POINTER(selem->local_storage, local_storage); - hlist_add_head_rcu(&selem->snode, &local_storage->list); -} - -void bpf_selem_unlink_map(struct bpf_local_storage_elem *selem) -{ - struct bpf_local_storage_map *smap; - struct bpf_local_storage_map_bucket *b; - - if (unlikely(!selem_linked_to_map_lockless(selem))) - /* selem has already be unlinked from smap */ - return; - - smap = rcu_dereference(SDATA(selem)->smap); - b = select_bucket(smap, selem); - raw_spin_lock_bh(&b->lock); - if (likely(selem_linked_to_map(selem))) - hlist_del_init_rcu(&selem->map_node); - raw_spin_unlock_bh(&b->lock); -} - -void bpf_selem_link_map(struct bpf_local_storage_map *smap, - struct bpf_local_storage_elem *selem) -{ - struct bpf_local_storage_map_bucket *b = select_bucket(smap, selem); - - raw_spin_lock_bh(&b->lock); - RCU_INIT_POINTER(SDATA(selem)->smap, smap); - hlist_add_head_rcu(&selem->map_node, &b->list); - raw_spin_unlock_bh(&b->lock); -} - -void bpf_selem_unlink(struct bpf_local_storage_elem *selem) -{ - /* Always unlink from map before unlinking from local_storage - * because selem will be freed after successfully unlinked from - * the local_storage. - */ - bpf_selem_unlink_map(selem); - __bpf_selem_unlink_storage(selem); -} - -struct bpf_local_storage_data * -bpf_local_storage_lookup(struct bpf_local_storage *local_storage, - struct bpf_local_storage_map *smap, - bool cacheit_lockit) -{ - struct bpf_local_storage_data *sdata; - struct bpf_local_storage_elem *selem; - - /* Fast path (cache hit) */ - sdata = rcu_dereference(local_storage->cache[smap->cache_idx]); - if (sdata && rcu_access_pointer(sdata->smap) == smap) - return sdata; - - /* Slow path (cache miss) */ - hlist_for_each_entry_rcu(selem, &local_storage->list, snode) - if (rcu_access_pointer(SDATA(selem)->smap) == smap) - break; - - if (!selem) - return NULL; - - sdata = SDATA(selem); - if (cacheit_lockit) { - /* spinlock is needed to avoid racing with the - * parallel delete. Otherwise, publishing an already - * deleted sdata to the cache will become a use-after-free - * problem in the next bpf_local_storage_lookup(). - */ - raw_spin_lock_bh(&local_storage->lock); - if (selem_linked_to_storage(selem)) - rcu_assign_pointer(local_storage->cache[smap->cache_idx], - sdata); - raw_spin_unlock_bh(&local_storage->lock); - } - - return sdata; -} - -static int check_flags(const struct bpf_local_storage_data *old_sdata, - u64 map_flags) -{ - if (old_sdata && (map_flags & ~BPF_F_LOCK) == BPF_NOEXIST) - /* elem already exists */ - return -EEXIST; - - if (!old_sdata && (map_flags & ~BPF_F_LOCK) == BPF_EXIST) - /* elem doesn't exist, cannot update it */ - return -ENOENT; - - return 0; -} - -int bpf_local_storage_alloc(void *owner, - struct bpf_local_storage_map *smap, - struct bpf_local_storage_elem *first_selem) -{ - struct bpf_local_storage *prev_storage, *storage; - struct bpf_local_storage **owner_storage_ptr; - int err; - - err = mem_charge(smap, owner, sizeof(*storage)); - if (err) - return err; - - storage = kzalloc(sizeof(*storage), GFP_ATOMIC | __GFP_NOWARN); - if (!storage) { - err = -ENOMEM; - goto uncharge; - } - - INIT_HLIST_HEAD(&storage->list); - raw_spin_lock_init(&storage->lock); - storage->owner = owner; - - bpf_selem_link_storage_nolock(storage, first_selem); - bpf_selem_link_map(smap, first_selem); - - owner_storage_ptr = - (struct bpf_local_storage **)owner_storage(smap, owner); - /* Publish storage to the owner. - * Instead of using any lock of the kernel object (i.e. owner), - * cmpxchg will work with any kernel object regardless what - * the running context is, bh, irq...etc. - * - * From now on, the owner->storage pointer (e.g. sk->sk_bpf_storage) - * is protected by the storage->lock. Hence, when freeing - * the owner->storage, the storage->lock must be held before - * setting owner->storage ptr to NULL. - */ - prev_storage = cmpxchg(owner_storage_ptr, NULL, storage); - if (unlikely(prev_storage)) { - bpf_selem_unlink_map(first_selem); - err = -EAGAIN; - goto uncharge; - - /* Note that even first_selem was linked to smap's - * bucket->list, first_selem can be freed immediately - * (instead of kfree_rcu) because - * bpf_local_storage_map_free() does a - * synchronize_rcu() before walking the bucket->list. - * Hence, no one is accessing selem from the - * bucket->list under rcu_read_lock(). - */ - } - - return 0; - -uncharge: - kfree(storage); - mem_uncharge(smap, owner, sizeof(*storage)); - return err; -} - -/* sk cannot be going away because it is linking new elem - * to sk->sk_bpf_storage. (i.e. sk->sk_refcnt cannot be 0). - * Otherwise, it will become a leak (and other memory issues - * during map destruction). - */ -struct bpf_local_storage_data * -bpf_local_storage_update(void *owner, struct bpf_local_storage_map *smap, - void *value, u64 map_flags) -{ - struct bpf_local_storage_data *old_sdata = NULL; - struct bpf_local_storage_elem *selem; - struct bpf_local_storage *local_storage; - int err; - - /* BPF_EXIST and BPF_NOEXIST cannot be both set */ - if (unlikely((map_flags & ~BPF_F_LOCK) > BPF_EXIST) || - /* BPF_F_LOCK can only be used in a value with spin_lock */ - unlikely((map_flags & BPF_F_LOCK) && - !map_value_has_spin_lock(&smap->map))) - return ERR_PTR(-EINVAL); - - local_storage = rcu_dereference(*owner_storage(smap, owner)); - if (!local_storage || hlist_empty(&local_storage->list)) { - /* Very first elem for the owner */ - err = check_flags(NULL, map_flags); - if (err) - return ERR_PTR(err); - - selem = bpf_selem_alloc(smap, owner, value, true); - if (!selem) - return ERR_PTR(-ENOMEM); - - err = bpf_local_storage_alloc(owner, smap, selem); - if (err) { - kfree(selem); - mem_uncharge(smap, owner, smap->elem_size); - return ERR_PTR(err); - } - - return SDATA(selem); - } - - if ((map_flags & BPF_F_LOCK) && !(map_flags & BPF_NOEXIST)) { - /* Hoping to find an old_sdata to do inline update - * such that it can avoid taking the local_storage->lock - * and changing the lists. - */ - old_sdata = - bpf_local_storage_lookup(local_storage, smap, false); - err = check_flags(old_sdata, map_flags); - if (err) - return ERR_PTR(err); - if (old_sdata && selem_linked_to_storage_lockless(SELEM(old_sdata))) { - copy_map_value_locked(&smap->map, old_sdata->data, - value, false); - return old_sdata; - } - } - - raw_spin_lock_bh(&local_storage->lock); - - /* Recheck local_storage->list under local_storage->lock */ - if (unlikely(hlist_empty(&local_storage->list))) { - /* A parallel del is happening and local_storage is going - * away. It has just been checked before, so very - * unlikely. Return instead of retry to keep things - * simple. - */ - err = -EAGAIN; - goto unlock_err; - } - - old_sdata = bpf_local_storage_lookup(local_storage, smap, false); - err = check_flags(old_sdata, map_flags); - if (err) - goto unlock_err; - - if (old_sdata && (map_flags & BPF_F_LOCK)) { - copy_map_value_locked(&smap->map, old_sdata->data, value, - false); - selem = SELEM(old_sdata); - goto unlock; - } - - /* local_storage->lock is held. Hence, we are sure - * we can unlink and uncharge the old_sdata successfully - * later. Hence, instead of charging the new selem now - * and then uncharge the old selem later (which may cause - * a potential but unnecessary charge failure), avoid taking - * a charge at all here (the "!old_sdata" check) and the - * old_sdata will not be uncharged later during - * bpf_selem_unlink_storage_nolock(). - */ - selem = bpf_selem_alloc(smap, owner, value, !old_sdata); - if (!selem) { - err = -ENOMEM; - goto unlock_err; - } - - /* First, link the new selem to the map */ - bpf_selem_link_map(smap, selem); - - /* Second, link (and publish) the new selem to local_storage */ - bpf_selem_link_storage_nolock(local_storage, selem); - - /* Third, remove old selem, SELEM(old_sdata) */ - if (old_sdata) { - bpf_selem_unlink_map(SELEM(old_sdata)); - bpf_selem_unlink_storage_nolock(local_storage, SELEM(old_sdata), - false); - } - -unlock: - raw_spin_unlock_bh(&local_storage->lock); - return SDATA(selem); - -unlock_err: - raw_spin_unlock_bh(&local_storage->lock); - return ERR_PTR(err); -} - -u16 bpf_local_storage_cache_idx_get(struct bpf_local_storage_cache *cache) -{ - u64 min_usage = U64_MAX; - u16 i, res = 0; - - spin_lock(&cache->idx_lock); - - for (i = 0; i < BPF_LOCAL_STORAGE_CACHE_SIZE; i++) { - if (cache->idx_usage_counts[i] < min_usage) { - min_usage = cache->idx_usage_counts[i]; - res = i; - - /* Found a free cache_idx */ - if (!min_usage) - break; - } - } - cache->idx_usage_counts[res]++; - - spin_unlock(&cache->idx_lock); - - return res; -} - -void bpf_local_storage_cache_idx_free(struct bpf_local_storage_cache *cache, - u16 idx) -{ - spin_lock(&cache->idx_lock); - cache->idx_usage_counts[idx]--; - spin_unlock(&cache->idx_lock); -} - -void bpf_local_storage_map_free(struct bpf_local_storage_map *smap) -{ - struct bpf_local_storage_elem *selem; - struct bpf_local_storage_map_bucket *b; - unsigned int i; - - /* Note that this map might be concurrently cloned from - * bpf_sk_storage_clone. Wait for any existing bpf_sk_storage_clone - * RCU read section to finish before proceeding. New RCU - * read sections should be prevented via bpf_map_inc_not_zero. - */ - synchronize_rcu(); - - /* bpf prog and the userspace can no longer access this map - * now. No new selem (of this map) can be added - * to the owner->storage or to the map bucket's list. - * - * The elem of this map can be cleaned up here - * or when the storage is freed e.g. - * by bpf_sk_storage_free() during __sk_destruct(). - */ - for (i = 0; i < (1U << smap->bucket_log); i++) { - b = &smap->buckets[i]; - - rcu_read_lock(); - /* No one is adding to b->list now */ - while ((selem = hlist_entry_safe( - rcu_dereference_raw(hlist_first_rcu(&b->list)), - struct bpf_local_storage_elem, map_node))) { - bpf_selem_unlink(selem); - cond_resched_rcu(); - } - rcu_read_unlock(); - } - - /* While freeing the storage we may still need to access the map. - * - * e.g. when bpf_sk_storage_free() has unlinked selem from the map - * which then made the above while((selem = ...)) loop - * exit immediately. - * - * However, while freeing the storage one still needs to access the - * smap->elem_size to do the uncharging in - * bpf_selem_unlink_storage_nolock(). - * - * Hence, wait another rcu grace period for the storage to be freed. - */ - synchronize_rcu(); - - kvfree(smap->buckets); - kfree(smap); -} - -int bpf_local_storage_map_alloc_check(union bpf_attr *attr) -{ - if (attr->map_flags & ~BPF_LOCAL_STORAGE_CREATE_FLAG_MASK || - !(attr->map_flags & BPF_F_NO_PREALLOC) || - attr->max_entries || - attr->key_size != sizeof(int) || !attr->value_size || - /* Enforce BTF for userspace sk dumping */ - !attr->btf_key_type_id || !attr->btf_value_type_id) - return -EINVAL; - - if (!bpf_capable()) - return -EPERM; - - if (attr->value_size > BPF_LOCAL_STORAGE_MAX_VALUE_SIZE) - return -E2BIG; - - return 0; -} - -struct bpf_local_storage_map *bpf_local_storage_map_alloc(union bpf_attr *attr) -{ - struct bpf_local_storage_map *smap; - unsigned int i; - u32 nbuckets; - u64 cost; - int ret; - - smap = kzalloc(sizeof(*smap), GFP_USER | __GFP_NOWARN); - if (!smap) - return ERR_PTR(-ENOMEM); - bpf_map_init_from_attr(&smap->map, attr); - - nbuckets = roundup_pow_of_two(num_possible_cpus()); - /* Use at least 2 buckets, select_bucket() is undefined behavior with 1 bucket */ - nbuckets = max_t(u32, 2, nbuckets); - smap->bucket_log = ilog2(nbuckets); - cost = sizeof(*smap->buckets) * nbuckets + sizeof(*smap); - - ret = bpf_map_charge_init(&smap->map.memory, cost); - if (ret < 0) { - kfree(smap); - return ERR_PTR(ret); - } - - smap->buckets = kvcalloc(sizeof(*smap->buckets), nbuckets, - GFP_USER | __GFP_NOWARN); - if (!smap->buckets) { - bpf_map_charge_finish(&smap->map.memory); - kfree(smap); - return ERR_PTR(-ENOMEM); - } - - for (i = 0; i < nbuckets; i++) { - INIT_HLIST_HEAD(&smap->buckets[i].list); - raw_spin_lock_init(&smap->buckets[i].lock); - } - - smap->elem_size = - sizeof(struct bpf_local_storage_elem) + attr->value_size; - - return smap; -} - -int bpf_local_storage_map_check_btf(const struct bpf_map *map, - const struct btf *btf, - const struct btf_type *key_type, - const struct btf_type *value_type) -{ - u32 int_data; - - if (BTF_INFO_KIND(key_type->info) != BTF_KIND_INT) - return -EINVAL; - - int_data = *(u32 *)(key_type + 1); - if (BTF_INT_BITS(int_data) != 32 || BTF_INT_OFFSET(int_data)) - return -EINVAL; - - return 0; -} diff --git a/kernel/bpf/bpf_lru_list.h b/kernel/bpf/bpf_lru_list.h index 9c12ee453c61..41f8fea530c8 100644 --- a/kernel/bpf/bpf_lru_list.h +++ b/kernel/bpf/bpf_lru_list.h @@ -30,7 +30,7 @@ struct bpf_lru_node { struct bpf_lru_list { struct list_head lists[NR_BPF_LRU_LIST_T]; unsigned int counts[NR_BPF_LRU_LIST_COUNT]; - /* The next inactive list rotation starts from here */ + /* The next inacitve list rotation starts from here */ struct list_head *next_inactive_rotation; raw_spinlock_t lock ____cacheline_aligned_in_smp; diff --git a/kernel/bpf/bpf_lsm.c b/kernel/bpf/bpf_lsm.c deleted file mode 100644 index 56cc5a915f67..000000000000 --- a/kernel/bpf/bpf_lsm.c +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* - * Copyright (C) 2020 Google LLC. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* For every LSM hook that allows attachment of BPF programs, declare a nop - * function where a BPF program can be attached. - */ -#define LSM_HOOK(RET, DEFAULT, NAME, ...) \ -noinline RET bpf_lsm_##NAME(__VA_ARGS__) \ -{ \ - return DEFAULT; \ -} - -#include -#undef LSM_HOOK - -#define LSM_HOOK(RET, DEFAULT, NAME, ...) BTF_ID(func, bpf_lsm_##NAME) -BTF_SET_START(bpf_lsm_hooks) -#include -#undef LSM_HOOK -BTF_SET_END(bpf_lsm_hooks) - -int bpf_lsm_verify_prog(struct bpf_verifier_log *vlog, - const struct bpf_prog *prog) -{ - if (!prog->gpl_compatible) { - bpf_log(vlog, - "LSM programs must have a GPL compatible license\n"); - return -EINVAL; - } - - if (!btf_id_set_contains(&bpf_lsm_hooks, prog->aux->attach_btf_id)) { - bpf_log(vlog, "attach_btf_id %u points to wrong type name %s\n", - prog->aux->attach_btf_id, prog->aux->attach_func_name); - return -EINVAL; - } - - return 0; -} - -static const struct bpf_func_proto * -bpf_lsm_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) -{ - switch (func_id) { - case BPF_FUNC_inode_storage_get: - return &bpf_inode_storage_get_proto; - case BPF_FUNC_inode_storage_delete: - return &bpf_inode_storage_delete_proto; - case BPF_FUNC_sk_storage_get: - return &bpf_sk_storage_get_proto; - case BPF_FUNC_sk_storage_delete: - return &bpf_sk_storage_delete_proto; - default: - return tracing_prog_func_proto(func_id, prog); - } -} - -const struct bpf_prog_ops lsm_prog_ops = { -}; - -const struct bpf_verifier_ops lsm_verifier_ops = { - .get_func_proto = bpf_lsm_func_proto, - .is_valid_access = btf_ctx_access, -}; diff --git a/kernel/bpf/bpf_struct_ops.c b/kernel/bpf/bpf_struct_ops.c deleted file mode 100644 index ac283f9b2332..000000000000 --- a/kernel/bpf/bpf_struct_ops.c +++ /dev/null @@ -1,653 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2019 Facebook */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -enum bpf_struct_ops_state { - BPF_STRUCT_OPS_STATE_INIT, - BPF_STRUCT_OPS_STATE_INUSE, - BPF_STRUCT_OPS_STATE_TOBEFREE, -}; - -#define BPF_STRUCT_OPS_COMMON_VALUE \ - refcount_t refcnt; \ - enum bpf_struct_ops_state state - -struct bpf_struct_ops_value { - BPF_STRUCT_OPS_COMMON_VALUE; - char data[] ____cacheline_aligned_in_smp; -}; - -struct bpf_struct_ops_map { - struct bpf_map map; - const struct bpf_struct_ops *st_ops; - /* protect map_update */ - struct mutex lock; - /* progs has all the bpf_prog that is populated - * to the func ptr of the kernel's struct - * (in kvalue.data). - */ - struct bpf_prog **progs; - /* image is a page that has all the trampolines - * that stores the func args before calling the bpf_prog. - * A PAGE_SIZE "image" is enough to store all trampoline for - * "progs[]". - */ - void *image; - /* uvalue->data stores the kernel struct - * (e.g. tcp_congestion_ops) that is more useful - * to userspace than the kvalue. For example, - * the bpf_prog's id is stored instead of the kernel - * address of a func ptr. - */ - struct bpf_struct_ops_value *uvalue; - /* kvalue.data stores the actual kernel's struct - * (e.g. tcp_congestion_ops) that will be - * registered to the kernel subsystem. - */ - struct bpf_struct_ops_value kvalue; -}; - -#define VALUE_PREFIX "bpf_struct_ops_" -#define VALUE_PREFIX_LEN (sizeof(VALUE_PREFIX) - 1) - -/* bpf_struct_ops_##_name (e.g. bpf_struct_ops_tcp_congestion_ops) is - * the map's value exposed to the userspace and its btf-type-id is - * stored at the map->btf_vmlinux_value_type_id. - * - */ -#define BPF_STRUCT_OPS_TYPE(_name) \ -extern struct bpf_struct_ops bpf_##_name; \ - \ -struct bpf_struct_ops_##_name { \ - BPF_STRUCT_OPS_COMMON_VALUE; \ - struct _name data ____cacheline_aligned_in_smp; \ -}; -#include "bpf_struct_ops_types.h" -#undef BPF_STRUCT_OPS_TYPE - -enum { -#define BPF_STRUCT_OPS_TYPE(_name) BPF_STRUCT_OPS_TYPE_##_name, -#include "bpf_struct_ops_types.h" -#undef BPF_STRUCT_OPS_TYPE - __NR_BPF_STRUCT_OPS_TYPE, -}; - -static struct bpf_struct_ops * const bpf_struct_ops[] = { -#define BPF_STRUCT_OPS_TYPE(_name) \ - [BPF_STRUCT_OPS_TYPE_##_name] = &bpf_##_name, -#include "bpf_struct_ops_types.h" -#undef BPF_STRUCT_OPS_TYPE -}; - -const struct bpf_verifier_ops bpf_struct_ops_verifier_ops = { -}; - -const struct bpf_prog_ops bpf_struct_ops_prog_ops = { -}; - -static const struct btf_type *module_type; - -void bpf_struct_ops_init(struct btf *btf, struct bpf_verifier_log *log) -{ - s32 type_id, value_id, module_id; - const struct btf_member *member; - struct bpf_struct_ops *st_ops; - const struct btf_type *t; - char value_name[128]; - const char *mname; - u32 i, j; - - /* Ensure BTF type is emitted for "struct bpf_struct_ops_##_name" */ -#define BPF_STRUCT_OPS_TYPE(_name) BTF_TYPE_EMIT(struct bpf_struct_ops_##_name); -#include "bpf_struct_ops_types.h" -#undef BPF_STRUCT_OPS_TYPE - - module_id = btf_find_by_name_kind(btf, "module", BTF_KIND_STRUCT); - if (module_id < 0) { - pr_warn("Cannot find struct module in btf_vmlinux\n"); - return; - } - module_type = btf_type_by_id(btf, module_id); - - for (i = 0; i < ARRAY_SIZE(bpf_struct_ops); i++) { - st_ops = bpf_struct_ops[i]; - - if (strlen(st_ops->name) + VALUE_PREFIX_LEN >= - sizeof(value_name)) { - pr_warn("struct_ops name %s is too long\n", - st_ops->name); - continue; - } - sprintf(value_name, "%s%s", VALUE_PREFIX, st_ops->name); - - value_id = btf_find_by_name_kind(btf, value_name, - BTF_KIND_STRUCT); - if (value_id < 0) { - pr_warn("Cannot find struct %s in btf_vmlinux\n", - value_name); - continue; - } - - type_id = btf_find_by_name_kind(btf, st_ops->name, - BTF_KIND_STRUCT); - if (type_id < 0) { - pr_warn("Cannot find struct %s in btf_vmlinux\n", - st_ops->name); - continue; - } - t = btf_type_by_id(btf, type_id); - if (btf_type_vlen(t) > BPF_STRUCT_OPS_MAX_NR_MEMBERS) { - pr_warn("Cannot support #%u members in struct %s\n", - btf_type_vlen(t), st_ops->name); - continue; - } - - for_each_member(j, t, member) { - const struct btf_type *func_proto; - - mname = btf_name_by_offset(btf, member->name_off); - if (!*mname) { - pr_warn("anon member in struct %s is not supported\n", - st_ops->name); - break; - } - - if (btf_member_bitfield_size(t, member)) { - pr_warn("bit field member %s in struct %s is not supported\n", - mname, st_ops->name); - break; - } - - func_proto = btf_type_resolve_func_ptr(btf, - member->type, - NULL); - if (func_proto && - btf_distill_func_proto(log, btf, - func_proto, mname, - &st_ops->func_models[j])) { - pr_warn("Error in parsing func ptr %s in struct %s\n", - mname, st_ops->name); - break; - } - } - - if (j == btf_type_vlen(t)) { - if (st_ops->init(btf)) { - pr_warn("Error in init bpf_struct_ops %s\n", - st_ops->name); - } else { - st_ops->type_id = type_id; - st_ops->type = t; - st_ops->value_id = value_id; - st_ops->value_type = btf_type_by_id(btf, - value_id); - } - } - } -} - -extern struct btf *btf_vmlinux; - -static const struct bpf_struct_ops * -bpf_struct_ops_find_value(u32 value_id) -{ - unsigned int i; - - if (!value_id || !btf_vmlinux) - return NULL; - - for (i = 0; i < ARRAY_SIZE(bpf_struct_ops); i++) { - if (bpf_struct_ops[i]->value_id == value_id) - return bpf_struct_ops[i]; - } - - return NULL; -} - -const struct bpf_struct_ops *bpf_struct_ops_find(u32 type_id) -{ - unsigned int i; - - if (!type_id || !btf_vmlinux) - return NULL; - - for (i = 0; i < ARRAY_SIZE(bpf_struct_ops); i++) { - if (bpf_struct_ops[i]->type_id == type_id) - return bpf_struct_ops[i]; - } - - return NULL; -} - -static int bpf_struct_ops_map_get_next_key(struct bpf_map *map, void *key, - void *next_key) -{ - if (key && *(u32 *)key == 0) - return -ENOENT; - - *(u32 *)next_key = 0; - return 0; -} - -int bpf_struct_ops_map_sys_lookup_elem(struct bpf_map *map, void *key, - void *value) -{ - struct bpf_struct_ops_map *st_map = (struct bpf_struct_ops_map *)map; - struct bpf_struct_ops_value *uvalue, *kvalue; - enum bpf_struct_ops_state state; - - if (unlikely(*(u32 *)key != 0)) - return -ENOENT; - - kvalue = &st_map->kvalue; - /* Pair with smp_store_release() during map_update */ - state = smp_load_acquire(&kvalue->state); - if (state == BPF_STRUCT_OPS_STATE_INIT) { - memset(value, 0, map->value_size); - return 0; - } - - /* No lock is needed. state and refcnt do not need - * to be updated together under atomic context. - */ - uvalue = (struct bpf_struct_ops_value *)value; - memcpy(uvalue, st_map->uvalue, map->value_size); - uvalue->state = state; - refcount_set(&uvalue->refcnt, refcount_read(&kvalue->refcnt)); - - return 0; -} - -static void *bpf_struct_ops_map_lookup_elem(struct bpf_map *map, void *key) -{ - return ERR_PTR(-EINVAL); -} - -static void bpf_struct_ops_map_put_progs(struct bpf_struct_ops_map *st_map) -{ - const struct btf_type *t = st_map->st_ops->type; - u32 i; - - for (i = 0; i < btf_type_vlen(t); i++) { - if (st_map->progs[i]) { - bpf_prog_put(st_map->progs[i]); - st_map->progs[i] = NULL; - } - } -} - -static int check_zero_holes(const struct btf_type *t, void *data) -{ - const struct btf_member *member; - u32 i, moff, msize, prev_mend = 0; - const struct btf_type *mtype; - - for_each_member(i, t, member) { - moff = btf_member_bit_offset(t, member) / 8; - if (moff > prev_mend && - memchr_inv(data + prev_mend, 0, moff - prev_mend)) - return -EINVAL; - - mtype = btf_type_by_id(btf_vmlinux, member->type); - mtype = btf_resolve_size(btf_vmlinux, mtype, &msize); - if (IS_ERR(mtype)) - return PTR_ERR(mtype); - prev_mend = moff + msize; - } - - if (t->size > prev_mend && - memchr_inv(data + prev_mend, 0, t->size - prev_mend)) - return -EINVAL; - - return 0; -} - -static int bpf_struct_ops_map_update_elem(struct bpf_map *map, void *key, - void *value, u64 flags) -{ - struct bpf_struct_ops_map *st_map = (struct bpf_struct_ops_map *)map; - const struct bpf_struct_ops *st_ops = st_map->st_ops; - struct bpf_struct_ops_value *uvalue, *kvalue; - const struct btf_member *member; - const struct btf_type *t = st_ops->type; - struct bpf_tramp_progs *tprogs = NULL; - void *udata, *kdata; - int prog_fd, err = 0; - void *image; - u32 i; - - if (flags) - return -EINVAL; - - if (*(u32 *)key != 0) - return -E2BIG; - - err = check_zero_holes(st_ops->value_type, value); - if (err) - return err; - - uvalue = (struct bpf_struct_ops_value *)value; - err = check_zero_holes(t, uvalue->data); - if (err) - return err; - - if (uvalue->state || refcount_read(&uvalue->refcnt)) - return -EINVAL; - - tprogs = kcalloc(BPF_TRAMP_MAX, sizeof(*tprogs), GFP_KERNEL); - if (!tprogs) - return -ENOMEM; - - uvalue = (struct bpf_struct_ops_value *)st_map->uvalue; - kvalue = (struct bpf_struct_ops_value *)&st_map->kvalue; - - mutex_lock(&st_map->lock); - - if (kvalue->state != BPF_STRUCT_OPS_STATE_INIT) { - err = -EBUSY; - goto unlock; - } - - memcpy(uvalue, value, map->value_size); - - udata = &uvalue->data; - kdata = &kvalue->data; - image = st_map->image; - - for_each_member(i, t, member) { - const struct btf_type *mtype, *ptype; - struct bpf_prog *prog; - u32 moff; - u32 flags; - - moff = btf_member_bit_offset(t, member) / 8; - ptype = btf_type_resolve_ptr(btf_vmlinux, member->type, NULL); - if (ptype == module_type) { - if (*(void **)(udata + moff)) - goto reset_unlock; - *(void **)(kdata + moff) = BPF_MODULE_OWNER; - continue; - } - - err = st_ops->init_member(t, member, kdata, udata); - if (err < 0) - goto reset_unlock; - - /* The ->init_member() has handled this member */ - if (err > 0) - continue; - - /* If st_ops->init_member does not handle it, - * we will only handle func ptrs and zero-ed members - * here. Reject everything else. - */ - - /* All non func ptr member must be 0 */ - if (!ptype || !btf_type_is_func_proto(ptype)) { - u32 msize; - - mtype = btf_type_by_id(btf_vmlinux, member->type); - mtype = btf_resolve_size(btf_vmlinux, mtype, &msize); - if (IS_ERR(mtype)) { - err = PTR_ERR(mtype); - goto reset_unlock; - } - - if (memchr_inv(udata + moff, 0, msize)) { - err = -EINVAL; - goto reset_unlock; - } - - continue; - } - - prog_fd = (int)(*(unsigned long *)(udata + moff)); - /* Similar check as the attr->attach_prog_fd */ - if (!prog_fd) - continue; - - prog = bpf_prog_get(prog_fd); - if (IS_ERR(prog)) { - err = PTR_ERR(prog); - goto reset_unlock; - } - st_map->progs[i] = prog; - - if (prog->type != BPF_PROG_TYPE_STRUCT_OPS || - prog->aux->attach_btf_id != st_ops->type_id || - prog->expected_attach_type != i) { - err = -EINVAL; - goto reset_unlock; - } - - tprogs[BPF_TRAMP_FENTRY].progs[0] = prog; - tprogs[BPF_TRAMP_FENTRY].nr_progs = 1; - flags = st_ops->func_models[i].ret_size > 0 ? - BPF_TRAMP_F_RET_FENTRY_RET : 0; - err = arch_prepare_bpf_trampoline(NULL, image, - st_map->image + PAGE_SIZE, - &st_ops->func_models[i], - flags, tprogs, NULL); - if (err < 0) - goto reset_unlock; - - *(void **)(kdata + moff) = image; - image += err; - - /* put prog_id to udata */ - *(unsigned long *)(udata + moff) = prog->aux->id; - } - - refcount_set(&kvalue->refcnt, 1); - bpf_map_inc(map); - - set_memory_ro((long)st_map->image, 1); - set_memory_x((long)st_map->image, 1); - err = st_ops->reg(kdata); - if (likely(!err)) { - /* Pair with smp_load_acquire() during lookup_elem(). - * It ensures the above udata updates (e.g. prog->aux->id) - * can be seen once BPF_STRUCT_OPS_STATE_INUSE is set. - */ - smp_store_release(&kvalue->state, BPF_STRUCT_OPS_STATE_INUSE); - goto unlock; - } - - /* Error during st_ops->reg(). It is very unlikely since - * the above init_member() should have caught it earlier - * before reg(). The only possibility is if there was a race - * in registering the struct_ops (under the same name) to - * a sub-system through different struct_ops's maps. - */ - set_memory_nx((long)st_map->image, 1); - set_memory_rw((long)st_map->image, 1); - bpf_map_put(map); - -reset_unlock: - bpf_struct_ops_map_put_progs(st_map); - memset(uvalue, 0, map->value_size); - memset(kvalue, 0, map->value_size); -unlock: - kfree(tprogs); - mutex_unlock(&st_map->lock); - return err; -} - -static int bpf_struct_ops_map_delete_elem(struct bpf_map *map, void *key) -{ - enum bpf_struct_ops_state prev_state; - struct bpf_struct_ops_map *st_map; - - st_map = (struct bpf_struct_ops_map *)map; - prev_state = cmpxchg(&st_map->kvalue.state, - BPF_STRUCT_OPS_STATE_INUSE, - BPF_STRUCT_OPS_STATE_TOBEFREE); - switch (prev_state) { - case BPF_STRUCT_OPS_STATE_INUSE: - st_map->st_ops->unreg(&st_map->kvalue.data); - if (refcount_dec_and_test(&st_map->kvalue.refcnt)) - bpf_map_put(map); - return 0; - case BPF_STRUCT_OPS_STATE_TOBEFREE: - return -EINPROGRESS; - case BPF_STRUCT_OPS_STATE_INIT: - return -ENOENT; - default: - WARN_ON_ONCE(1); - /* Should never happen. Treat it as not found. */ - return -ENOENT; - } -} - -static void bpf_struct_ops_map_seq_show_elem(struct bpf_map *map, void *key, - struct seq_file *m) -{ - void *value; - int err; - - value = kmalloc(map->value_size, GFP_USER | __GFP_NOWARN); - if (!value) - return; - - err = bpf_struct_ops_map_sys_lookup_elem(map, key, value); - if (!err) { - btf_type_seq_show(btf_vmlinux, map->btf_vmlinux_value_type_id, - value, m); - seq_puts(m, "\n"); - } - - kfree(value); -} - -static void bpf_struct_ops_map_free(struct bpf_map *map) -{ - struct bpf_struct_ops_map *st_map = (struct bpf_struct_ops_map *)map; - - if (st_map->progs) - bpf_struct_ops_map_put_progs(st_map); - bpf_map_area_free(st_map->progs); - bpf_jit_free_exec(st_map->image); - bpf_map_area_free(st_map->uvalue); - bpf_map_area_free(st_map); -} - -static int bpf_struct_ops_map_alloc_check(union bpf_attr *attr) -{ - if (attr->key_size != sizeof(unsigned int) || attr->max_entries != 1 || - attr->map_flags || !attr->btf_vmlinux_value_type_id) - return -EINVAL; - return 0; -} - -static struct bpf_map *bpf_struct_ops_map_alloc(union bpf_attr *attr) -{ - const struct bpf_struct_ops *st_ops; - size_t map_total_size, st_map_size; - struct bpf_struct_ops_map *st_map; - const struct btf_type *t, *vt; - struct bpf_map_memory mem; - struct bpf_map *map; - int err; - - if (!bpf_capable()) - return ERR_PTR(-EPERM); - - st_ops = bpf_struct_ops_find_value(attr->btf_vmlinux_value_type_id); - if (!st_ops) - return ERR_PTR(-ENOTSUPP); - - vt = st_ops->value_type; - if (attr->value_size != vt->size) - return ERR_PTR(-EINVAL); - - t = st_ops->type; - - st_map_size = sizeof(*st_map) + - /* kvalue stores the - * struct bpf_struct_ops_tcp_congestions_ops - */ - (vt->size - sizeof(struct bpf_struct_ops_value)); - map_total_size = st_map_size + - /* uvalue */ - sizeof(vt->size) + - /* struct bpf_progs **progs */ - btf_type_vlen(t) * sizeof(struct bpf_prog *); - err = bpf_map_charge_init(&mem, map_total_size); - if (err < 0) - return ERR_PTR(err); - - st_map = bpf_map_area_alloc(st_map_size, NUMA_NO_NODE); - if (!st_map) { - bpf_map_charge_finish(&mem); - return ERR_PTR(-ENOMEM); - } - st_map->st_ops = st_ops; - map = &st_map->map; - - st_map->uvalue = bpf_map_area_alloc(vt->size, NUMA_NO_NODE); - st_map->progs = - bpf_map_area_alloc(btf_type_vlen(t) * sizeof(struct bpf_prog *), - NUMA_NO_NODE); - st_map->image = bpf_jit_alloc_exec(PAGE_SIZE); - if (!st_map->uvalue || !st_map->progs || !st_map->image) { - bpf_struct_ops_map_free(map); - bpf_map_charge_finish(&mem); - return ERR_PTR(-ENOMEM); - } - - mutex_init(&st_map->lock); - set_vm_flush_reset_perms(st_map->image); - bpf_map_init_from_attr(map, attr); - bpf_map_charge_move(&map->memory, &mem); - - return map; -} - -static int bpf_struct_ops_map_btf_id; -const struct bpf_map_ops bpf_struct_ops_map_ops = { - .map_alloc_check = bpf_struct_ops_map_alloc_check, - .map_alloc = bpf_struct_ops_map_alloc, - .map_free = bpf_struct_ops_map_free, - .map_get_next_key = bpf_struct_ops_map_get_next_key, - .map_lookup_elem = bpf_struct_ops_map_lookup_elem, - .map_delete_elem = bpf_struct_ops_map_delete_elem, - .map_update_elem = bpf_struct_ops_map_update_elem, - .map_seq_show_elem = bpf_struct_ops_map_seq_show_elem, - .map_btf_name = "bpf_struct_ops_map", - .map_btf_id = &bpf_struct_ops_map_btf_id, -}; - -/* "const void *" because some subsystem is - * passing a const (e.g. const struct tcp_congestion_ops *) - */ -bool bpf_struct_ops_get(const void *kdata) -{ - struct bpf_struct_ops_value *kvalue; - - kvalue = container_of(kdata, struct bpf_struct_ops_value, data); - - return refcount_inc_not_zero(&kvalue->refcnt); -} - -void bpf_struct_ops_put(const void *kdata) -{ - struct bpf_struct_ops_value *kvalue; - - kvalue = container_of(kdata, struct bpf_struct_ops_value, data); - if (refcount_dec_and_test(&kvalue->refcnt)) { - struct bpf_struct_ops_map *st_map; - - st_map = container_of(kvalue, struct bpf_struct_ops_map, - kvalue); - bpf_map_put(&st_map->map); - } -} diff --git a/kernel/bpf/bpf_struct_ops_types.h b/kernel/bpf/bpf_struct_ops_types.h deleted file mode 100644 index 066d83ea1c99..000000000000 --- a/kernel/bpf/bpf_struct_ops_types.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* internal file - do not include directly */ - -#ifdef CONFIG_BPF_JIT -#ifdef CONFIG_INET -#include -BPF_STRUCT_OPS_TYPE(tcp_congestion_ops) -#endif -#endif diff --git a/kernel/bpf/btf.c b/kernel/bpf/btf.c index face6bda1c93..5189bc5ebd89 100644 --- a/kernel/bpf/btf.c +++ b/kernel/bpf/btf.c @@ -2,9 +2,6 @@ /* Copyright (c) 2018 Facebook */ #include -#include -#include -#include #include #include #include @@ -19,12 +16,6 @@ #include #include #include -#include -#include -#include -#include -#include -#include /* BTF (BPF Type Format) is the meta data format which describes * the data types of BPF program/map. Hence, it basically focus @@ -184,11 +175,21 @@ */ #define BTF_MAX_SIZE (16 * 1024 * 1024) +#define for_each_member(i, struct_type, member) \ + for (i = 0, member = btf_type_member(struct_type); \ + i < btf_type_vlen(struct_type); \ + i++, member++) + #define for_each_member_from(i, from, struct_type, member) \ for (i = from, member = btf_type_member(struct_type) + from; \ i < btf_type_vlen(struct_type); \ i++, member++) +#define for_each_vsi(i, struct_type, member) \ + for (i = 0, member = btf_type_var_secinfo(struct_type); \ + i < btf_type_vlen(struct_type); \ + i++, member++) + #define for_each_vsi_from(i, from, struct_type, member) \ for (i = from, member = btf_type_var_secinfo(struct_type) + from; \ i < btf_type_vlen(struct_type); \ @@ -275,96 +276,6 @@ static const char * const btf_kind_str[NR_BTF_KINDS] = { [BTF_KIND_DATASEC] = "DATASEC", }; -static const char *btf_type_str(const struct btf_type *t) -{ - return btf_kind_str[BTF_INFO_KIND(t->info)]; -} - -/* Chunk size we use in safe copy of data to be shown. */ -#define BTF_SHOW_OBJ_SAFE_SIZE 32 - -/* - * This is the maximum size of a base type value (equivalent to a - * 128-bit int); if we are at the end of our safe buffer and have - * less than 16 bytes space we can't be assured of being able - * to copy the next type safely, so in such cases we will initiate - * a new copy. - */ -#define BTF_SHOW_OBJ_BASE_TYPE_SIZE 16 - -/* Type name size */ -#define BTF_SHOW_NAME_SIZE 80 - -/* - * Common data to all BTF show operations. Private show functions can add - * their own data to a structure containing a struct btf_show and consult it - * in the show callback. See btf_type_show() below. - * - * One challenge with showing nested data is we want to skip 0-valued - * data, but in order to figure out whether a nested object is all zeros - * we need to walk through it. As a result, we need to make two passes - * when handling structs, unions and arrays; the first path simply looks - * for nonzero data, while the second actually does the display. The first - * pass is signalled by show->state.depth_check being set, and if we - * encounter a non-zero value we set show->state.depth_to_show to - * the depth at which we encountered it. When we have completed the - * first pass, we will know if anything needs to be displayed if - * depth_to_show > depth. See btf_[struct,array]_show() for the - * implementation of this. - * - * Another problem is we want to ensure the data for display is safe to - * access. To support this, the anonymous "struct {} obj" tracks the data - * object and our safe copy of it. We copy portions of the data needed - * to the object "copy" buffer, but because its size is limited to - * BTF_SHOW_OBJ_COPY_LEN bytes, multiple copies may be required as we - * traverse larger objects for display. - * - * The various data type show functions all start with a call to - * btf_show_start_type() which returns a pointer to the safe copy - * of the data needed (or if BTF_SHOW_UNSAFE is specified, to the - * raw data itself). btf_show_obj_safe() is responsible for - * using copy_from_kernel_nofault() to update the safe data if necessary - * as we traverse the object's data. skbuff-like semantics are - * used: - * - * - obj.head points to the start of the toplevel object for display - * - obj.size is the size of the toplevel object - * - obj.data points to the current point in the original data at - * which our safe data starts. obj.data will advance as we copy - * portions of the data. - * - * In most cases a single copy will suffice, but larger data structures - * such as "struct task_struct" will require many copies. The logic in - * btf_show_obj_safe() handles the logic that determines if a new - * copy_from_kernel_nofault() is needed. - */ -struct btf_show { - u64 flags; - void *target; /* target of show operation (seq file, buffer) */ - __printf(2, 0) void (*showfn)(struct btf_show *show, const char *fmt, va_list args); - const struct btf *btf; - /* below are used during iteration */ - struct { - u8 depth; - u8 depth_to_show; - u8 depth_check; - u8 array_member:1, - array_terminated:1; - u16 array_encoding; - u32 type_id; - int status; /* non-zero for error */ - const struct btf_type *type; - const struct btf_member *member; - char name[BTF_SHOW_NAME_SIZE]; /* space for member name/type */ - } state; - struct { - u32 size; - void *head; - void *data; - u8 safe[BTF_SHOW_OBJ_SAFE_SIZE]; - } obj; -}; - struct btf_kind_operations { s32 (*check_meta)(struct btf_verifier_env *env, const struct btf_type *t, @@ -381,9 +292,9 @@ struct btf_kind_operations { const struct btf_type *member_type); void (*log_details)(struct btf_verifier_env *env, const struct btf_type *t); - void (*show)(const struct btf *btf, const struct btf_type *t, + void (*seq_show)(const struct btf *btf, const struct btf_type *t, u32 type_id, void *data, u8 bits_offsets, - struct btf_show *show); + struct seq_file *m); }; static const struct btf_kind_operations * const kind_ops[NR_BTF_KINDS]; @@ -425,6 +336,16 @@ static bool btf_type_is_fwd(const struct btf_type *t) return BTF_INFO_KIND(t->info) == BTF_KIND_FWD; } +static bool btf_type_is_func(const struct btf_type *t) +{ + return BTF_INFO_KIND(t->info) == BTF_KIND_FUNC; +} + +static bool btf_type_is_func_proto(const struct btf_type *t) +{ + return BTF_INFO_KIND(t->info) == BTF_KIND_FUNC_PROTO; +} + static bool btf_type_nosize(const struct btf_type *t) { return btf_type_is_void(t) || btf_type_is_fwd(t) || @@ -436,6 +357,16 @@ static bool btf_type_nosize_or_null(const struct btf_type *t) return !t || btf_type_nosize(t); } +/* union is only a special case of struct: + * all its offsetof(member) == 0 + */ +static bool btf_type_is_struct(const struct btf_type *t) +{ + u8 kind = BTF_INFO_KIND(t->info); + + return kind == BTF_KIND_STRUCT || kind == BTF_KIND_UNION; +} + static bool __btf_type_is_struct(const struct btf_type *t) { return BTF_INFO_KIND(t->info) == BTF_KIND_STRUCT; @@ -446,70 +377,26 @@ static bool btf_type_is_array(const struct btf_type *t) return BTF_INFO_KIND(t->info) == BTF_KIND_ARRAY; } +static bool btf_type_is_ptr(const struct btf_type *t) +{ + return BTF_INFO_KIND(t->info) == BTF_KIND_PTR; +} + +static bool btf_type_is_int(const struct btf_type *t) +{ + return BTF_INFO_KIND(t->info) == BTF_KIND_INT; +} + +static bool btf_type_is_var(const struct btf_type *t) +{ + return BTF_INFO_KIND(t->info) == BTF_KIND_VAR; +} + static bool btf_type_is_datasec(const struct btf_type *t) { return BTF_INFO_KIND(t->info) == BTF_KIND_DATASEC; } -s32 btf_find_by_name_kind(const struct btf *btf, const char *name, u8 kind) -{ - const struct btf_type *t; - const char *tname; - u32 i; - - for (i = 1; i <= btf->nr_types; i++) { - t = btf->types[i]; - if (BTF_INFO_KIND(t->info) != kind) - continue; - - tname = btf_name_by_offset(btf, t->name_off); - if (!strcmp(tname, name)) - return i; - } - - return -ENOENT; -} - -const struct btf_type *btf_type_skip_modifiers(const struct btf *btf, - u32 id, u32 *res_id) -{ - const struct btf_type *t = btf_type_by_id(btf, id); - - while (btf_type_is_modifier(t)) { - id = t->type; - t = btf_type_by_id(btf, t->type); - } - - if (res_id) - *res_id = id; - - return t; -} - -const struct btf_type *btf_type_resolve_ptr(const struct btf *btf, - u32 id, u32 *res_id) -{ - const struct btf_type *t; - - t = btf_type_skip_modifiers(btf, id, NULL); - if (!btf_type_is_ptr(t)) - return NULL; - - return btf_type_skip_modifiers(btf, t->type, res_id); -} - -const struct btf_type *btf_type_resolve_func_ptr(const struct btf *btf, - u32 id, u32 *res_id) -{ - const struct btf_type *ptype; - - ptype = btf_type_resolve_ptr(btf, id, res_id); - if (ptype && btf_type_is_func_proto(ptype)) - return ptype; - - return NULL; -} - /* Types that act only as a source, not sink or intermediate * type when resolving. */ @@ -574,6 +461,30 @@ static const char *btf_int_encoding_str(u8 encoding) return "UNKN"; } +static u16 btf_type_vlen(const struct btf_type *t) +{ + return BTF_INFO_VLEN(t->info); +} + +static bool btf_type_kflag(const struct btf_type *t) +{ + return BTF_INFO_KFLAG(t->info); +} + +static u32 btf_member_bit_offset(const struct btf_type *struct_type, + const struct btf_member *member) +{ + return btf_type_kflag(struct_type) ? BTF_MEMBER_BIT_OFFSET(member->offset) + : member->offset; +} + +static u32 btf_member_bitfield_size(const struct btf_type *struct_type, + const struct btf_member *member) +{ + return btf_type_kflag(struct_type) ? BTF_MEMBER_BITFIELD_SIZE(member->offset) + : 0; +} + static u32 btf_type_int(const struct btf_type *t) { return *(u32 *)(t + 1); @@ -584,6 +495,11 @@ static const struct btf_array *btf_type_array(const struct btf_type *t) return (const struct btf_array *)(t + 1); } +static const struct btf_member *btf_type_member(const struct btf_type *t) +{ + return (const struct btf_member *)(t + 1); +} + static const struct btf_enum *btf_type_enum(const struct btf_type *t) { return (const struct btf_enum *)(t + 1); @@ -594,6 +510,11 @@ static const struct btf_var *btf_type_var(const struct btf_type *t) return (const struct btf_var *)(t + 1); } +static const struct btf_var_secinfo *btf_type_var_secinfo(const struct btf_type *t) +{ + return (const struct btf_var_secinfo *)(t + 1); +} + static const struct btf_kind_operations *btf_type_ops(const struct btf_type *t) { return kind_ops[BTF_INFO_KIND(t->info)]; @@ -605,30 +526,31 @@ static bool btf_name_offset_valid(const struct btf *btf, u32 offset) offset < btf->hdr.str_len; } -static bool __btf_name_char_ok(char c, bool first) +static bool __btf_name_char_ok(char c, bool first, bool dot_ok) { if ((first ? !isalpha(c) : !isalnum(c)) && c != '_' && - c != '.') + ((c == '.' && !dot_ok) || + c != '.')) return false; return true; } -static bool __btf_name_valid(const struct btf *btf, u32 offset) +static bool __btf_name_valid(const struct btf *btf, u32 offset, bool dot_ok) { /* offset must be valid */ const char *src = &btf->strings[offset]; const char *src_limit; - if (!__btf_name_char_ok(*src, true)) + if (!__btf_name_char_ok(*src, true, dot_ok)) return false; /* set a limit on identifier length */ src_limit = src + KSYM_NAME_LEN; src++; while (*src && src < src_limit) { - if (!__btf_name_char_ok(*src, false)) + if (!__btf_name_char_ok(*src, false, dot_ok)) return false; src++; } @@ -636,14 +558,17 @@ static bool __btf_name_valid(const struct btf *btf, u32 offset) return !*src; } +/* Only C-style identifier is permitted. This can be relaxed if + * necessary. + */ static bool btf_name_valid_identifier(const struct btf *btf, u32 offset) { - return __btf_name_valid(btf, offset); + return __btf_name_valid(btf, offset, false); } static bool btf_name_valid_section(const struct btf *btf, u32 offset) { - return __btf_name_valid(btf, offset); + return __btf_name_valid(btf, offset, true); } static const char *__btf_name_by_offset(const struct btf *btf, u32 offset) @@ -736,488 +661,6 @@ bool btf_member_is_reg_int(const struct btf *btf, const struct btf_type *s, return true; } -/* Similar to btf_type_skip_modifiers() but does not skip typedefs. */ -static const struct btf_type *btf_type_skip_qualifiers(const struct btf *btf, - u32 id) -{ - const struct btf_type *t = btf_type_by_id(btf, id); - - while (btf_type_is_modifier(t) && - BTF_INFO_KIND(t->info) != BTF_KIND_TYPEDEF) { - id = t->type; - t = btf_type_by_id(btf, t->type); - } - - return t; -} - -#define BTF_SHOW_MAX_ITER 10 - -#define BTF_KIND_BIT(kind) (1ULL << kind) - -/* - * Populate show->state.name with type name information. - * Format of type name is - * - * [.member_name = ] (type_name) - */ -static const char *btf_show_name(struct btf_show *show) -{ - /* BTF_MAX_ITER array suffixes "[]" */ - const char *array_suffixes = "[][][][][][][][][][]"; - const char *array_suffix = &array_suffixes[strlen(array_suffixes)]; - /* BTF_MAX_ITER pointer suffixes "*" */ - const char *ptr_suffixes = "**********"; - const char *ptr_suffix = &ptr_suffixes[strlen(ptr_suffixes)]; - const char *name = NULL, *prefix = "", *parens = ""; - const struct btf_member *m = show->state.member; - const struct btf_type *t = show->state.type; - const struct btf_array *array; - u32 id = show->state.type_id; - const char *member = NULL; - bool show_member = false; - u64 kinds = 0; - int i; - - show->state.name[0] = '\0'; - - /* - * Don't show type name if we're showing an array member; - * in that case we show the array type so don't need to repeat - * ourselves for each member. - */ - if (show->state.array_member) - return ""; - - /* Retrieve member name, if any. */ - if (m) { - member = btf_name_by_offset(show->btf, m->name_off); - show_member = strlen(member) > 0; - id = m->type; - } - - /* - * Start with type_id, as we have resolved the struct btf_type * - * via btf_modifier_show() past the parent typedef to the child - * struct, int etc it is defined as. In such cases, the type_id - * still represents the starting type while the struct btf_type * - * in our show->state points at the resolved type of the typedef. - */ - t = btf_type_by_id(show->btf, id); - if (!t) - return ""; - - /* - * The goal here is to build up the right number of pointer and - * array suffixes while ensuring the type name for a typedef - * is represented. Along the way we accumulate a list of - * BTF kinds we have encountered, since these will inform later - * display; for example, pointer types will not require an - * opening "{" for struct, we will just display the pointer value. - * - * We also want to accumulate the right number of pointer or array - * indices in the format string while iterating until we get to - * the typedef/pointee/array member target type. - * - * We start by pointing at the end of pointer and array suffix - * strings; as we accumulate pointers and arrays we move the pointer - * or array string backwards so it will show the expected number of - * '*' or '[]' for the type. BTF_SHOW_MAX_ITER of nesting of pointers - * and/or arrays and typedefs are supported as a precaution. - * - * We also want to get typedef name while proceeding to resolve - * type it points to so that we can add parentheses if it is a - * "typedef struct" etc. - */ - for (i = 0; i < BTF_SHOW_MAX_ITER; i++) { - - switch (BTF_INFO_KIND(t->info)) { - case BTF_KIND_TYPEDEF: - if (!name) - name = btf_name_by_offset(show->btf, - t->name_off); - kinds |= BTF_KIND_BIT(BTF_KIND_TYPEDEF); - id = t->type; - break; - case BTF_KIND_ARRAY: - kinds |= BTF_KIND_BIT(BTF_KIND_ARRAY); - parens = "["; - if (!t) - return ""; - array = btf_type_array(t); - if (array_suffix > array_suffixes) - array_suffix -= 2; - id = array->type; - break; - case BTF_KIND_PTR: - kinds |= BTF_KIND_BIT(BTF_KIND_PTR); - if (ptr_suffix > ptr_suffixes) - ptr_suffix -= 1; - id = t->type; - break; - default: - id = 0; - break; - } - if (!id) - break; - t = btf_type_skip_qualifiers(show->btf, id); - } - /* We may not be able to represent this type; bail to be safe */ - if (i == BTF_SHOW_MAX_ITER) - return ""; - - if (!name) - name = btf_name_by_offset(show->btf, t->name_off); - - switch (BTF_INFO_KIND(t->info)) { - case BTF_KIND_STRUCT: - case BTF_KIND_UNION: - prefix = BTF_INFO_KIND(t->info) == BTF_KIND_STRUCT ? - "struct" : "union"; - /* if it's an array of struct/union, parens is already set */ - if (!(kinds & (BTF_KIND_BIT(BTF_KIND_ARRAY)))) - parens = "{"; - break; - case BTF_KIND_ENUM: - prefix = "enum"; - break; - default: - break; - } - - /* pointer does not require parens */ - if (kinds & BTF_KIND_BIT(BTF_KIND_PTR)) - parens = ""; - /* typedef does not require struct/union/enum prefix */ - if (kinds & BTF_KIND_BIT(BTF_KIND_TYPEDEF)) - prefix = ""; - - if (!name) - name = ""; - - /* Even if we don't want type name info, we want parentheses etc */ - if (show->flags & BTF_SHOW_NONAME) - snprintf(show->state.name, sizeof(show->state.name), "%s", - parens); - else - snprintf(show->state.name, sizeof(show->state.name), - "%s%s%s(%s%s%s%s%s%s)%s", - /* first 3 strings comprise ".member = " */ - show_member ? "." : "", - show_member ? member : "", - show_member ? " = " : "", - /* ...next is our prefix (struct, enum, etc) */ - prefix, - strlen(prefix) > 0 && strlen(name) > 0 ? " " : "", - /* ...this is the type name itself */ - name, - /* ...suffixed by the appropriate '*', '[]' suffixes */ - strlen(ptr_suffix) > 0 ? " " : "", ptr_suffix, - array_suffix, parens); - - return show->state.name; -} - -static const char *__btf_show_indent(struct btf_show *show) -{ - const char *indents = " "; - const char *indent = &indents[strlen(indents)]; - - if ((indent - show->state.depth) >= indents) - return indent - show->state.depth; - return indents; -} - -static const char *btf_show_indent(struct btf_show *show) -{ - return show->flags & BTF_SHOW_COMPACT ? "" : __btf_show_indent(show); -} - -static const char *btf_show_newline(struct btf_show *show) -{ - return show->flags & BTF_SHOW_COMPACT ? "" : "\n"; -} - -static const char *btf_show_delim(struct btf_show *show) -{ - if (show->state.depth == 0) - return ""; - - if ((show->flags & BTF_SHOW_COMPACT) && show->state.type && - BTF_INFO_KIND(show->state.type->info) == BTF_KIND_UNION) - return "|"; - - return ","; -} - -__printf(2, 3) static void btf_show(struct btf_show *show, const char *fmt, ...) -{ - va_list args; - - if (!show->state.depth_check) { - va_start(args, fmt); - show->showfn(show, fmt, args); - va_end(args); - } -} - -/* Macros are used here as btf_show_type_value[s]() prepends and appends - * format specifiers to the format specifier passed in; these do the work of - * adding indentation, delimiters etc while the caller simply has to specify - * the type value(s) in the format specifier + value(s). - */ -#define btf_show_type_value(show, fmt, value) \ - do { \ - if ((value) != 0 || (show->flags & BTF_SHOW_ZERO) || \ - show->state.depth == 0) { \ - btf_show(show, "%s%s" fmt "%s%s", \ - btf_show_indent(show), \ - btf_show_name(show), \ - value, btf_show_delim(show), \ - btf_show_newline(show)); \ - if (show->state.depth > show->state.depth_to_show) \ - show->state.depth_to_show = show->state.depth; \ - } \ - } while (0) - -#define btf_show_type_values(show, fmt, ...) \ - do { \ - btf_show(show, "%s%s" fmt "%s%s", btf_show_indent(show), \ - btf_show_name(show), \ - __VA_ARGS__, btf_show_delim(show), \ - btf_show_newline(show)); \ - if (show->state.depth > show->state.depth_to_show) \ - show->state.depth_to_show = show->state.depth; \ - } while (0) - -/* How much is left to copy to safe buffer after @data? */ -static int btf_show_obj_size_left(struct btf_show *show, void *data) -{ - return show->obj.head + show->obj.size - data; -} - -/* Is object pointed to by @data of @size already copied to our safe buffer? */ -static bool btf_show_obj_is_safe(struct btf_show *show, void *data, int size) -{ - return data >= show->obj.data && - (data + size) < (show->obj.data + BTF_SHOW_OBJ_SAFE_SIZE); -} - -/* - * If object pointed to by @data of @size falls within our safe buffer, return - * the equivalent pointer to the same safe data. Assumes - * copy_from_kernel_nofault() has already happened and our safe buffer is - * populated. - */ -static void *__btf_show_obj_safe(struct btf_show *show, void *data, int size) -{ - if (btf_show_obj_is_safe(show, data, size)) - return show->obj.safe + (data - show->obj.data); - return NULL; -} - -/* - * Return a safe-to-access version of data pointed to by @data. - * We do this by copying the relevant amount of information - * to the struct btf_show obj.safe buffer using copy_from_kernel_nofault(). - * - * If BTF_SHOW_UNSAFE is specified, just return data as-is; no - * safe copy is needed. - * - * Otherwise we need to determine if we have the required amount - * of data (determined by the @data pointer and the size of the - * largest base type we can encounter (represented by - * BTF_SHOW_OBJ_BASE_TYPE_SIZE). Having that much data ensures - * that we will be able to print some of the current object, - * and if more is needed a copy will be triggered. - * Some objects such as structs will not fit into the buffer; - * in such cases additional copies when we iterate over their - * members may be needed. - * - * btf_show_obj_safe() is used to return a safe buffer for - * btf_show_start_type(); this ensures that as we recurse into - * nested types we always have safe data for the given type. - * This approach is somewhat wasteful; it's possible for example - * that when iterating over a large union we'll end up copying the - * same data repeatedly, but the goal is safety not performance. - * We use stack data as opposed to per-CPU buffers because the - * iteration over a type can take some time, and preemption handling - * would greatly complicate use of the safe buffer. - */ -static void *btf_show_obj_safe(struct btf_show *show, - const struct btf_type *t, - void *data) -{ - const struct btf_type *rt; - int size_left, size; - void *safe = NULL; - - if (show->flags & BTF_SHOW_UNSAFE) - return data; - - rt = btf_resolve_size(show->btf, t, &size); - if (IS_ERR(rt)) { - show->state.status = PTR_ERR(rt); - return NULL; - } - - /* - * Is this toplevel object? If so, set total object size and - * initialize pointers. Otherwise check if we still fall within - * our safe object data. - */ - if (show->state.depth == 0) { - show->obj.size = size; - show->obj.head = data; - } else { - /* - * If the size of the current object is > our remaining - * safe buffer we _may_ need to do a new copy. However - * consider the case of a nested struct; it's size pushes - * us over the safe buffer limit, but showing any individual - * struct members does not. In such cases, we don't need - * to initiate a fresh copy yet; however we definitely need - * at least BTF_SHOW_OBJ_BASE_TYPE_SIZE bytes left - * in our buffer, regardless of the current object size. - * The logic here is that as we resolve types we will - * hit a base type at some point, and we need to be sure - * the next chunk of data is safely available to display - * that type info safely. We cannot rely on the size of - * the current object here because it may be much larger - * than our current buffer (e.g. task_struct is 8k). - * All we want to do here is ensure that we can print the - * next basic type, which we can if either - * - the current type size is within the safe buffer; or - * - at least BTF_SHOW_OBJ_BASE_TYPE_SIZE bytes are left in - * the safe buffer. - */ - safe = __btf_show_obj_safe(show, data, - min(size, - BTF_SHOW_OBJ_BASE_TYPE_SIZE)); - } - - /* - * We need a new copy to our safe object, either because we haven't - * yet copied and are intializing safe data, or because the data - * we want falls outside the boundaries of the safe object. - */ - if (!safe) { - size_left = btf_show_obj_size_left(show, data); - if (size_left > BTF_SHOW_OBJ_SAFE_SIZE) - size_left = BTF_SHOW_OBJ_SAFE_SIZE; - show->state.status = copy_from_kernel_nofault(show->obj.safe, - data, size_left); - if (!show->state.status) { - show->obj.data = data; - safe = show->obj.safe; - } - } - - return safe; -} - -/* - * Set the type we are starting to show and return a safe data pointer - * to be used for showing the associated data. - */ -static void *btf_show_start_type(struct btf_show *show, - const struct btf_type *t, - u32 type_id, void *data) -{ - show->state.type = t; - show->state.type_id = type_id; - show->state.name[0] = '\0'; - - return btf_show_obj_safe(show, t, data); -} - -static void btf_show_end_type(struct btf_show *show) -{ - show->state.type = NULL; - show->state.type_id = 0; - show->state.name[0] = '\0'; -} - -static void *btf_show_start_aggr_type(struct btf_show *show, - const struct btf_type *t, - u32 type_id, void *data) -{ - void *safe_data = btf_show_start_type(show, t, type_id, data); - - if (!safe_data) - return safe_data; - - btf_show(show, "%s%s%s", btf_show_indent(show), - btf_show_name(show), - btf_show_newline(show)); - show->state.depth++; - return safe_data; -} - -static void btf_show_end_aggr_type(struct btf_show *show, - const char *suffix) -{ - show->state.depth--; - btf_show(show, "%s%s%s%s", btf_show_indent(show), suffix, - btf_show_delim(show), btf_show_newline(show)); - btf_show_end_type(show); -} - -static void btf_show_start_member(struct btf_show *show, - const struct btf_member *m) -{ - show->state.member = m; -} - -static void btf_show_start_array_member(struct btf_show *show) -{ - show->state.array_member = 1; - btf_show_start_member(show, NULL); -} - -static void btf_show_end_member(struct btf_show *show) -{ - show->state.member = NULL; -} - -static void btf_show_end_array_member(struct btf_show *show) -{ - show->state.array_member = 0; - btf_show_end_member(show); -} - -static void *btf_show_start_array_type(struct btf_show *show, - const struct btf_type *t, - u32 type_id, - u16 array_encoding, - void *data) -{ - show->state.array_encoding = array_encoding; - show->state.array_terminated = 0; - return btf_show_start_aggr_type(show, t, type_id, data); -} - -static void btf_show_end_array_type(struct btf_show *show) -{ - show->state.array_encoding = 0; - show->state.array_terminated = 0; - btf_show_end_aggr_type(show, "]"); -} - -static void *btf_show_start_struct_type(struct btf_show *show, - const struct btf_type *t, - u32 type_id, - void *data) -{ - return btf_show_start_aggr_type(show, t, type_id, data); -} - -static void btf_show_end_struct_type(struct btf_show *show) -{ - btf_show_end_aggr_type(show, "}"); -} - __printf(2, 3) static void __btf_verifier_log(struct bpf_verifier_log *log, const char *fmt, ...) { @@ -1255,13 +698,6 @@ __printf(4, 5) static void __btf_verifier_log_type(struct btf_verifier_env *env, if (!bpf_verifier_log_needed(log)) return; - /* btf verifier prints all types it is processing via - * btf_verifier_log_type(..., fmt = NULL). - * Skip those prints for in-kernel BTF verification. - */ - if (log->level == BPF_LOG_KERNEL && !fmt) - return; - __btf_verifier_log(log, "[%u] %s %s%s", env->log_type_id, btf_kind_str[kind], @@ -1299,8 +735,6 @@ static void btf_verifier_log_member(struct btf_verifier_env *env, if (!bpf_verifier_log_needed(log)) return; - if (log->level == BPF_LOG_KERNEL && !fmt) - return; /* The CHECK_META phase already did a btf dump. * * If member is logged again, it must hit an error in @@ -1343,8 +777,6 @@ static void btf_verifier_log_vsi(struct btf_verifier_env *env, if (!bpf_verifier_log_needed(log)) return; - if (log->level == BPF_LOG_KERNEL && !fmt) - return; if (env->phase != CHECK_META) btf_verifier_log_type(env, datasec_type, NULL); @@ -1370,8 +802,6 @@ static void btf_verifier_log_hdr(struct btf_verifier_env *env, if (!bpf_verifier_log_needed(log)) return; - if (log->level == BPF_LOG_KERNEL) - return; hdr = &btf->hdr; __btf_verifier_log(log, "magic: 0x%x\n", hdr->magic); __btf_verifier_log(log, "version: %u\n", hdr->version); @@ -1613,100 +1043,6 @@ static const struct resolve_vertex *env_stack_peak(struct btf_verifier_env *env) return env->top_stack ? &env->stack[env->top_stack - 1] : NULL; } -/* Resolve the size of a passed-in "type" - * - * type: is an array (e.g. u32 array[x][y]) - * return type: type "u32[x][y]", i.e. BTF_KIND_ARRAY, - * *type_size: (x * y * sizeof(u32)). Hence, *type_size always - * corresponds to the return type. - * *elem_type: u32 - * *elem_id: id of u32 - * *total_nelems: (x * y). Hence, individual elem size is - * (*type_size / *total_nelems) - * *type_id: id of type if it's changed within the function, 0 if not - * - * type: is not an array (e.g. const struct X) - * return type: type "struct X" - * *type_size: sizeof(struct X) - * *elem_type: same as return type ("struct X") - * *elem_id: 0 - * *total_nelems: 1 - * *type_id: id of type if it's changed within the function, 0 if not - */ -static const struct btf_type * -__btf_resolve_size(const struct btf *btf, const struct btf_type *type, - u32 *type_size, const struct btf_type **elem_type, - u32 *elem_id, u32 *total_nelems, u32 *type_id) -{ - const struct btf_type *array_type = NULL; - const struct btf_array *array = NULL; - u32 i, size, nelems = 1, id = 0; - - for (i = 0; i < MAX_RESOLVE_DEPTH; i++) { - switch (BTF_INFO_KIND(type->info)) { - /* type->size can be used */ - case BTF_KIND_INT: - case BTF_KIND_STRUCT: - case BTF_KIND_UNION: - case BTF_KIND_ENUM: - size = type->size; - goto resolved; - - case BTF_KIND_PTR: - size = sizeof(void *); - goto resolved; - - /* Modifiers */ - case BTF_KIND_TYPEDEF: - case BTF_KIND_VOLATILE: - case BTF_KIND_CONST: - case BTF_KIND_RESTRICT: - id = type->type; - type = btf_type_by_id(btf, type->type); - break; - - case BTF_KIND_ARRAY: - if (!array_type) - array_type = type; - array = btf_type_array(type); - if (nelems && array->nelems > U32_MAX / nelems) - return ERR_PTR(-EINVAL); - nelems *= array->nelems; - type = btf_type_by_id(btf, array->type); - break; - - /* type without size */ - default: - return ERR_PTR(-EINVAL); - } - } - - return ERR_PTR(-EINVAL); - -resolved: - if (nelems && size > U32_MAX / nelems) - return ERR_PTR(-EINVAL); - - *type_size = nelems * size; - if (total_nelems) - *total_nelems = nelems; - if (elem_type) - *elem_type = type; - if (elem_id) - *elem_id = array ? array->type : 0; - if (type_id && id) - *type_id = id; - - return array_type ? : type; -} - -const struct btf_type * -btf_resolve_size(const struct btf *btf, const struct btf_type *type, - u32 *type_size) -{ - return __btf_resolve_size(btf, type, type_size, NULL, NULL, NULL, NULL); -} - /* The input param "type_id" must point to a needs_resolve type */ static const struct btf_type *btf_type_id_resolve(const struct btf *btf, u32 *type_id) @@ -1807,11 +1143,11 @@ static int btf_df_resolve(struct btf_verifier_env *env, return -EINVAL; } -static void btf_df_show(const struct btf *btf, const struct btf_type *t, - u32 type_id, void *data, u8 bits_offsets, - struct btf_show *show) +static void btf_df_seq_show(const struct btf *btf, const struct btf_type *t, + u32 type_id, void *data, u8 bits_offsets, + struct seq_file *m) { - btf_show(show, "", BTF_INFO_KIND(t->info)); + seq_printf(m, "", BTF_INFO_KIND(t->info)); } static int btf_int_check_member(struct btf_verifier_env *env, @@ -1984,7 +1320,7 @@ static void btf_int_log(struct btf_verifier_env *env, btf_int_encoding_str(BTF_INT_ENCODING(int_data))); } -static void btf_int128_print(struct btf_show *show, void *data) +static void btf_int128_print(struct seq_file *m, void *data) { /* data points to a __int128 number. * Suppose @@ -2003,10 +1339,9 @@ static void btf_int128_print(struct btf_show *show, void *data) lower_num = *(u64 *)data; #endif if (upper_num == 0) - btf_show_type_value(show, "0x%llx", lower_num); + seq_printf(m, "0x%llx", lower_num); else - btf_show_type_values(show, "0x%llx%016llx", upper_num, - lower_num); + seq_printf(m, "0x%llx%016llx", upper_num, lower_num); } static void btf_int128_shift(u64 *print_num, u16 left_shift_bits, @@ -2050,8 +1385,8 @@ static void btf_int128_shift(u64 *print_num, u16 left_shift_bits, #endif } -static void btf_bitfield_show(void *data, u8 bits_offset, - u8 nr_bits, struct btf_show *show) +static void btf_bitfield_seq_show(void *data, u8 bits_offset, + u8 nr_bits, struct seq_file *m) { u16 left_shift_bits, right_shift_bits; u8 nr_copy_bytes; @@ -2071,14 +1406,14 @@ static void btf_bitfield_show(void *data, u8 bits_offset, right_shift_bits = BITS_PER_U128 - nr_bits; btf_int128_shift(print_num, left_shift_bits, right_shift_bits); - btf_int128_print(show, print_num); + btf_int128_print(m, print_num); } -static void btf_int_bits_show(const struct btf *btf, - const struct btf_type *t, - void *data, u8 bits_offset, - struct btf_show *show) +static void btf_int_bits_seq_show(const struct btf *btf, + const struct btf_type *t, + void *data, u8 bits_offset, + struct seq_file *m) { u32 int_data = btf_type_int(t); u8 nr_bits = BTF_INT_BITS(int_data); @@ -2091,77 +1426,55 @@ static void btf_int_bits_show(const struct btf *btf, total_bits_offset = bits_offset + BTF_INT_OFFSET(int_data); data += BITS_ROUNDDOWN_BYTES(total_bits_offset); bits_offset = BITS_PER_BYTE_MASKED(total_bits_offset); - btf_bitfield_show(data, bits_offset, nr_bits, show); + btf_bitfield_seq_show(data, bits_offset, nr_bits, m); } -static void btf_int_show(const struct btf *btf, const struct btf_type *t, - u32 type_id, void *data, u8 bits_offset, - struct btf_show *show) +static void btf_int_seq_show(const struct btf *btf, const struct btf_type *t, + u32 type_id, void *data, u8 bits_offset, + struct seq_file *m) { u32 int_data = btf_type_int(t); u8 encoding = BTF_INT_ENCODING(int_data); bool sign = encoding & BTF_INT_SIGNED; u8 nr_bits = BTF_INT_BITS(int_data); - void *safe_data; - - safe_data = btf_show_start_type(show, t, type_id, data); - if (!safe_data) - return; if (bits_offset || BTF_INT_OFFSET(int_data) || BITS_PER_BYTE_MASKED(nr_bits)) { - btf_int_bits_show(btf, t, safe_data, bits_offset, show); - goto out; + btf_int_bits_seq_show(btf, t, data, bits_offset, m); + return; } switch (nr_bits) { case 128: - btf_int128_print(show, safe_data); + btf_int128_print(m, data); break; case 64: if (sign) - btf_show_type_value(show, "%lld", *(s64 *)safe_data); + seq_printf(m, "%lld", *(s64 *)data); else - btf_show_type_value(show, "%llu", *(u64 *)safe_data); + seq_printf(m, "%llu", *(u64 *)data); break; case 32: if (sign) - btf_show_type_value(show, "%d", *(s32 *)safe_data); + seq_printf(m, "%d", *(s32 *)data); else - btf_show_type_value(show, "%u", *(u32 *)safe_data); + seq_printf(m, "%u", *(u32 *)data); break; case 16: if (sign) - btf_show_type_value(show, "%d", *(s16 *)safe_data); + seq_printf(m, "%d", *(s16 *)data); else - btf_show_type_value(show, "%u", *(u16 *)safe_data); + seq_printf(m, "%u", *(u16 *)data); break; case 8: - if (show->state.array_encoding == BTF_INT_CHAR) { - /* check for null terminator */ - if (show->state.array_terminated) - break; - if (*(char *)data == '\0') { - show->state.array_terminated = 1; - break; - } - if (isprint(*(char *)data)) { - btf_show_type_value(show, "'%c'", - *(char *)safe_data); - break; - } - } if (sign) - btf_show_type_value(show, "%d", *(s8 *)safe_data); + seq_printf(m, "%d", *(s8 *)data); else - btf_show_type_value(show, "%u", *(u8 *)safe_data); + seq_printf(m, "%u", *(u8 *)data); break; default: - btf_int_bits_show(btf, t, safe_data, bits_offset, show); - break; + btf_int_bits_seq_show(btf, t, data, bits_offset, m); } -out: - btf_show_end_type(show); } static const struct btf_kind_operations int_ops = { @@ -2170,7 +1483,7 @@ static const struct btf_kind_operations int_ops = { .check_member = btf_int_check_member, .check_kflag_member = btf_int_check_kflag_member, .log_details = btf_int_log, - .show = btf_int_show, + .seq_show = btf_int_seq_show, }; static int btf_modifier_check_member(struct btf_verifier_env *env, @@ -2434,44 +1747,31 @@ static int btf_ptr_resolve(struct btf_verifier_env *env, return 0; } -static void btf_modifier_show(const struct btf *btf, - const struct btf_type *t, - u32 type_id, void *data, - u8 bits_offset, struct btf_show *show) -{ - if (btf->resolved_ids) - t = btf_type_id_resolve(btf, &type_id); - else - t = btf_type_skip_modifiers(btf, type_id, NULL); - - btf_type_ops(t)->show(btf, t, type_id, data, bits_offset, show); -} - -static void btf_var_show(const struct btf *btf, const struct btf_type *t, - u32 type_id, void *data, u8 bits_offset, - struct btf_show *show) +static void btf_modifier_seq_show(const struct btf *btf, + const struct btf_type *t, + u32 type_id, void *data, + u8 bits_offset, struct seq_file *m) { t = btf_type_id_resolve(btf, &type_id); - btf_type_ops(t)->show(btf, t, type_id, data, bits_offset, show); + btf_type_ops(t)->seq_show(btf, t, type_id, data, bits_offset, m); } -static void btf_ptr_show(const struct btf *btf, const struct btf_type *t, - u32 type_id, void *data, u8 bits_offset, - struct btf_show *show) +static void btf_var_seq_show(const struct btf *btf, const struct btf_type *t, + u32 type_id, void *data, u8 bits_offset, + struct seq_file *m) { - void *safe_data; + t = btf_type_id_resolve(btf, &type_id); - safe_data = btf_show_start_type(show, t, type_id, data); - if (!safe_data) - return; + btf_type_ops(t)->seq_show(btf, t, type_id, data, bits_offset, m); +} - /* It is a hashed value unless BTF_SHOW_PTR_RAW is specified */ - if (show->flags & BTF_SHOW_PTR_RAW) - btf_show_type_value(show, "0x%px", *(void **)safe_data); - else - btf_show_type_value(show, "0x%p", *(void **)safe_data); - btf_show_end_type(show); +static void btf_ptr_seq_show(const struct btf *btf, const struct btf_type *t, + u32 type_id, void *data, u8 bits_offset, + struct seq_file *m) +{ + /* It is a hashed value */ + seq_printf(m, "%p", *(void **)data); } static void btf_ref_type_log(struct btf_verifier_env *env, @@ -2486,7 +1786,7 @@ static struct btf_kind_operations modifier_ops = { .check_member = btf_modifier_check_member, .check_kflag_member = btf_modifier_check_kflag_member, .log_details = btf_ref_type_log, - .show = btf_modifier_show, + .seq_show = btf_modifier_seq_show, }; static struct btf_kind_operations ptr_ops = { @@ -2495,7 +1795,7 @@ static struct btf_kind_operations ptr_ops = { .check_member = btf_ptr_check_member, .check_kflag_member = btf_generic_check_kflag_member, .log_details = btf_ref_type_log, - .show = btf_ptr_show, + .seq_show = btf_ptr_seq_show, }; static s32 btf_fwd_check_meta(struct btf_verifier_env *env, @@ -2536,7 +1836,7 @@ static struct btf_kind_operations fwd_ops = { .check_member = btf_df_check_member, .check_kflag_member = btf_df_check_kflag_member, .log_details = btf_fwd_type_log, - .show = btf_df_show, + .seq_show = btf_df_seq_show, }; static int btf_array_check_member(struct btf_verifier_env *env, @@ -2695,90 +1995,28 @@ static void btf_array_log(struct btf_verifier_env *env, array->type, array->index_type, array->nelems); } -static void __btf_array_show(const struct btf *btf, const struct btf_type *t, - u32 type_id, void *data, u8 bits_offset, - struct btf_show *show) +static void btf_array_seq_show(const struct btf *btf, const struct btf_type *t, + u32 type_id, void *data, u8 bits_offset, + struct seq_file *m) { const struct btf_array *array = btf_type_array(t); const struct btf_kind_operations *elem_ops; const struct btf_type *elem_type; - u32 i, elem_size = 0, elem_type_id; - u16 encoding = 0; + u32 i, elem_size, elem_type_id; elem_type_id = array->type; - elem_type = btf_type_skip_modifiers(btf, elem_type_id, NULL); - if (elem_type && btf_type_has_size(elem_type)) - elem_size = elem_type->size; - - if (elem_type && btf_type_is_int(elem_type)) { - u32 int_type = btf_type_int(elem_type); - - encoding = BTF_INT_ENCODING(int_type); - - /* - * BTF_INT_CHAR encoding never seems to be set for - * char arrays, so if size is 1 and element is - * printable as a char, we'll do that. - */ - if (elem_size == 1) - encoding = BTF_INT_CHAR; - } - - if (!btf_show_start_array_type(show, t, type_id, encoding, data)) - return; - - if (!elem_type) - goto out; + elem_type = btf_type_id_size(btf, &elem_type_id, &elem_size); elem_ops = btf_type_ops(elem_type); - + seq_puts(m, "["); for (i = 0; i < array->nelems; i++) { + if (i) + seq_puts(m, ","); - btf_show_start_array_member(show); - - elem_ops->show(btf, elem_type, elem_type_id, data, - bits_offset, show); + elem_ops->seq_show(btf, elem_type, elem_type_id, data, + bits_offset, m); data += elem_size; - - btf_show_end_array_member(show); - - if (show->state.array_terminated) - break; } -out: - btf_show_end_array_type(show); -} - -static void btf_array_show(const struct btf *btf, const struct btf_type *t, - u32 type_id, void *data, u8 bits_offset, - struct btf_show *show) -{ - const struct btf_member *m = show->state.member; - - /* - * First check if any members would be shown (are non-zero). - * See comments above "struct btf_show" definition for more - * details on how this works at a high-level. - */ - if (show->state.depth > 0 && !(show->flags & BTF_SHOW_ZERO)) { - if (!show->state.depth_check) { - show->state.depth_check = show->state.depth + 1; - show->state.depth_to_show = 0; - } - __btf_array_show(btf, t, type_id, data, bits_offset, show); - show->state.member = m; - - if (show->state.depth_check != show->state.depth + 1) - return; - show->state.depth_check = 0; - - if (show->state.depth_to_show <= show->state.depth) - return; - /* - * Reaching here indicates we have recursed and found - * non-zero array member(s). - */ - } - __btf_array_show(btf, t, type_id, data, bits_offset, show); + seq_puts(m, "]"); } static struct btf_kind_operations array_ops = { @@ -2787,7 +2025,7 @@ static struct btf_kind_operations array_ops = { .check_member = btf_array_check_member, .check_kflag_member = btf_generic_check_kflag_member, .log_details = btf_array_log, - .show = btf_array_show, + .seq_show = btf_array_seq_show, }; static int btf_struct_check_member(struct btf_verifier_env *env, @@ -3010,18 +2248,15 @@ int btf_find_spin_lock(const struct btf *btf, const struct btf_type *t) return off; } -static void __btf_struct_show(const struct btf *btf, const struct btf_type *t, - u32 type_id, void *data, u8 bits_offset, - struct btf_show *show) +static void btf_struct_seq_show(const struct btf *btf, const struct btf_type *t, + u32 type_id, void *data, u8 bits_offset, + struct seq_file *m) { + const char *seq = BTF_INFO_KIND(t->info) == BTF_KIND_UNION ? "|" : ","; const struct btf_member *member; - void *safe_data; u32 i; - safe_data = btf_show_start_struct_type(show, t, type_id, data); - if (!safe_data) - return; - + seq_puts(m, "{"); for_each_member(i, t, member) { const struct btf_type *member_type = btf_type_by_id(btf, member->type); @@ -3030,65 +2265,23 @@ static void __btf_struct_show(const struct btf *btf, const struct btf_type *t, u32 bytes_offset; u8 bits8_offset; - btf_show_start_member(show, member); + if (i) + seq_puts(m, seq); member_offset = btf_member_bit_offset(t, member); bitfield_size = btf_member_bitfield_size(t, member); bytes_offset = BITS_ROUNDDOWN_BYTES(member_offset); bits8_offset = BITS_PER_BYTE_MASKED(member_offset); if (bitfield_size) { - safe_data = btf_show_start_type(show, member_type, - member->type, - data + bytes_offset); - if (safe_data) - btf_bitfield_show(safe_data, - bits8_offset, - bitfield_size, show); - btf_show_end_type(show); + btf_bitfield_seq_show(data + bytes_offset, bits8_offset, + bitfield_size, m); } else { ops = btf_type_ops(member_type); - ops->show(btf, member_type, member->type, - data + bytes_offset, bits8_offset, show); + ops->seq_show(btf, member_type, member->type, + data + bytes_offset, bits8_offset, m); } - - btf_show_end_member(show); } - - btf_show_end_struct_type(show); -} - -static void btf_struct_show(const struct btf *btf, const struct btf_type *t, - u32 type_id, void *data, u8 bits_offset, - struct btf_show *show) -{ - const struct btf_member *m = show->state.member; - - /* - * First check if any members would be shown (are non-zero). - * See comments above "struct btf_show" definition for more - * details on how this works at a high-level. - */ - if (show->state.depth > 0 && !(show->flags & BTF_SHOW_ZERO)) { - if (!show->state.depth_check) { - show->state.depth_check = show->state.depth + 1; - show->state.depth_to_show = 0; - } - __btf_struct_show(btf, t, type_id, data, bits_offset, show); - /* Restore saved member data here */ - show->state.member = m; - if (show->state.depth_check != show->state.depth + 1) - return; - show->state.depth_check = 0; - - if (show->state.depth_to_show <= show->state.depth) - return; - /* - * Reaching here indicates we have recursed and found - * non-zero child values. - */ - } - - __btf_struct_show(btf, t, type_id, data, bits_offset, show); + seq_puts(m, "}"); } static struct btf_kind_operations struct_ops = { @@ -3097,7 +2290,7 @@ static struct btf_kind_operations struct_ops = { .check_member = btf_struct_check_member, .check_kflag_member = btf_generic_check_kflag_member, .log_details = btf_struct_log, - .show = btf_struct_show, + .seq_show = btf_struct_seq_show, }; static int btf_enum_check_member(struct btf_verifier_env *env, @@ -3212,8 +2405,7 @@ static s32 btf_enum_check_meta(struct btf_verifier_env *env, return -EINVAL; } - if (env->log.level == BPF_LOG_KERNEL) - continue; + btf_verifier_log(env, "\t%s val=%d\n", __btf_name_by_offset(btf, enums[i].name_off), enums[i].val); @@ -3228,35 +2420,24 @@ static void btf_enum_log(struct btf_verifier_env *env, btf_verifier_log(env, "size=%u vlen=%u", t->size, btf_type_vlen(t)); } -static void btf_enum_show(const struct btf *btf, const struct btf_type *t, - u32 type_id, void *data, u8 bits_offset, - struct btf_show *show) +static void btf_enum_seq_show(const struct btf *btf, const struct btf_type *t, + u32 type_id, void *data, u8 bits_offset, + struct seq_file *m) { const struct btf_enum *enums = btf_type_enum(t); u32 i, nr_enums = btf_type_vlen(t); - void *safe_data; - int v; - - safe_data = btf_show_start_type(show, t, type_id, data); - if (!safe_data) - return; - - v = *(int *)safe_data; + int v = *(int *)data; for (i = 0; i < nr_enums; i++) { - if (v != enums[i].val) - continue; - - btf_show_type_value(show, "%s", - __btf_name_by_offset(btf, - enums[i].name_off)); - - btf_show_end_type(show); - return; + if (v == enums[i].val) { + seq_printf(m, "%s", + __btf_name_by_offset(btf, + enums[i].name_off)); + return; + } } - btf_show_type_value(show, "%d", v); - btf_show_end_type(show); + seq_printf(m, "%d", v); } static struct btf_kind_operations enum_ops = { @@ -3265,7 +2446,7 @@ static struct btf_kind_operations enum_ops = { .check_member = btf_enum_check_member, .check_kflag_member = btf_enum_check_kflag_member, .log_details = btf_enum_log, - .show = btf_enum_show, + .seq_show = btf_enum_seq_show, }; static s32 btf_func_proto_check_meta(struct btf_verifier_env *env, @@ -3352,7 +2533,7 @@ static struct btf_kind_operations func_proto_ops = { .check_member = btf_df_check_member, .check_kflag_member = btf_df_check_kflag_member, .log_details = btf_func_proto_log, - .show = btf_df_show, + .seq_show = btf_df_seq_show, }; static s32 btf_func_check_meta(struct btf_verifier_env *env, @@ -3365,8 +2546,8 @@ static s32 btf_func_check_meta(struct btf_verifier_env *env, return -EINVAL; } - if (btf_type_vlen(t) > BTF_FUNC_GLOBAL) { - btf_verifier_log_type(env, t, "Invalid func linkage"); + if (btf_type_vlen(t)) { + btf_verifier_log_type(env, t, "vlen != 0"); return -EINVAL; } @@ -3386,7 +2567,7 @@ static struct btf_kind_operations func_ops = { .check_member = btf_df_check_member, .check_kflag_member = btf_df_check_kflag_member, .log_details = btf_ref_type_log, - .show = btf_df_show, + .seq_show = btf_df_seq_show, }; static s32 btf_var_check_meta(struct btf_verifier_env *env, @@ -3414,7 +2595,7 @@ static s32 btf_var_check_meta(struct btf_verifier_env *env, } if (!t->name_off || - !__btf_name_valid(env->btf, t->name_off)) { + !__btf_name_valid(env->btf, t->name_off, true)) { btf_verifier_log_type(env, t, "Invalid name"); return -EINVAL; } @@ -3450,7 +2631,7 @@ static const struct btf_kind_operations var_ops = { .check_member = btf_df_check_member, .check_kflag_member = btf_df_check_kflag_member, .log_details = btf_var_log, - .show = btf_var_show, + .seq_show = btf_var_seq_show, }; static s32 btf_datasec_check_meta(struct btf_verifier_env *env, @@ -3577,28 +2758,24 @@ static void btf_datasec_log(struct btf_verifier_env *env, btf_verifier_log(env, "size=%u vlen=%u", t->size, btf_type_vlen(t)); } -static void btf_datasec_show(const struct btf *btf, - const struct btf_type *t, u32 type_id, - void *data, u8 bits_offset, - struct btf_show *show) +static void btf_datasec_seq_show(const struct btf *btf, + const struct btf_type *t, u32 type_id, + void *data, u8 bits_offset, + struct seq_file *m) { const struct btf_var_secinfo *vsi; const struct btf_type *var; u32 i; - if (!btf_show_start_type(show, t, type_id, data)) - return; - - btf_show_type_value(show, "section (\"%s\") = {", - __btf_name_by_offset(btf, t->name_off)); + seq_printf(m, "section (\"%s\") = {", __btf_name_by_offset(btf, t->name_off)); for_each_vsi(i, t, vsi) { var = btf_type_by_id(btf, vsi->type); if (i) - btf_show(show, ","); - btf_type_ops(var)->show(btf, var, vsi->type, - data + vsi->offset, bits_offset, show); + seq_puts(m, ","); + btf_type_ops(var)->seq_show(btf, var, vsi->type, + data + vsi->offset, bits_offset, m); } - btf_show_end_type(show); + seq_puts(m, "}"); } static const struct btf_kind_operations datasec_ops = { @@ -3607,7 +2784,7 @@ static const struct btf_kind_operations datasec_ops = { .check_member = btf_df_check_member, .check_kflag_member = btf_df_check_kflag_member, .log_details = btf_datasec_log, - .show = btf_datasec_show, + .seq_show = btf_datasec_seq_show, }; static int btf_func_proto_check(struct btf_verifier_env *env, @@ -4138,7 +3315,8 @@ static struct btf *btf_parse(void __user *btf_data, u32 btf_data_size, log->len_total = log_size; /* log attributes have to be sane */ - if (!bpf_verifier_log_attr_valid(log)) { + if (log->len_total < 128 || log->len_total > UINT_MAX >> 8 || + !log->level || !log->ubuf) { err = -EINVAL; goto errout; } @@ -4195,1232 +3373,12 @@ errout: return ERR_PTR(err); } -extern char __weak _binary__btf_vmlinux_bin_start[]; -extern char __weak _binary__btf_vmlinux_bin_end[]; -extern struct btf *btf_vmlinux; - -#define BPF_MAP_TYPE(_id, _ops) -#define BPF_LINK_TYPE(_id, _name) -static union { - struct bpf_ctx_convert { -#define BPF_PROG_TYPE(_id, _name, prog_ctx_type, kern_ctx_type) \ - prog_ctx_type _id##_prog; \ - kern_ctx_type _id##_kern; -#include -#undef BPF_PROG_TYPE - } *__t; - /* 't' is written once under lock. Read many times. */ - const struct btf_type *t; -} bpf_ctx_convert; -enum { -#define BPF_PROG_TYPE(_id, _name, prog_ctx_type, kern_ctx_type) \ - __ctx_convert##_id, -#include -#undef BPF_PROG_TYPE - __ctx_convert_unused, /* to avoid empty enum in extreme .config */ -}; -static u8 bpf_ctx_convert_map[] = { -#define BPF_PROG_TYPE(_id, _name, prog_ctx_type, kern_ctx_type) \ - [_id] = __ctx_convert##_id, -#include -#undef BPF_PROG_TYPE - 0, /* avoid empty array */ -}; -#undef BPF_MAP_TYPE -#undef BPF_LINK_TYPE - -static const struct btf_member * -btf_get_prog_ctx_type(struct bpf_verifier_log *log, struct btf *btf, - const struct btf_type *t, enum bpf_prog_type prog_type, - int arg) -{ - const struct btf_type *conv_struct; - const struct btf_type *ctx_struct; - const struct btf_member *ctx_type; - const char *tname, *ctx_tname; - - conv_struct = bpf_ctx_convert.t; - if (!conv_struct) { - bpf_log(log, "btf_vmlinux is malformed\n"); - return NULL; - } - t = btf_type_by_id(btf, t->type); - while (btf_type_is_modifier(t)) - t = btf_type_by_id(btf, t->type); - if (!btf_type_is_struct(t)) { - /* Only pointer to struct is supported for now. - * That means that BPF_PROG_TYPE_TRACEPOINT with BTF - * is not supported yet. - * BPF_PROG_TYPE_RAW_TRACEPOINT is fine. - */ - if (log->level & BPF_LOG_LEVEL) - bpf_log(log, "arg#%d type is not a struct\n", arg); - return NULL; - } - tname = btf_name_by_offset(btf, t->name_off); - if (!tname) { - bpf_log(log, "arg#%d struct doesn't have a name\n", arg); - return NULL; - } - /* prog_type is valid bpf program type. No need for bounds check. */ - ctx_type = btf_type_member(conv_struct) + bpf_ctx_convert_map[prog_type] * 2; - /* ctx_struct is a pointer to prog_ctx_type in vmlinux. - * Like 'struct __sk_buff' - */ - ctx_struct = btf_type_by_id(btf_vmlinux, ctx_type->type); - if (!ctx_struct) - /* should not happen */ - return NULL; -again: - ctx_tname = btf_name_by_offset(btf_vmlinux, ctx_struct->name_off); - if (!ctx_tname) { - /* should not happen */ - bpf_log(log, "Please fix kernel include/linux/bpf_types.h\n"); - return NULL; - } - /* only compare that prog's ctx type name is the same as - * kernel expects. No need to compare field by field. - * It's ok for bpf prog to do: - * struct __sk_buff {}; - * int socket_filter_bpf_prog(struct __sk_buff *skb) - * { // no fields of skb are ever used } - */ - if (strcmp(ctx_tname, tname)) { - /* bpf_user_pt_regs_t is a typedef, so resolve it to - * underlying struct and check name again - */ - if (!btf_type_is_modifier(ctx_struct)) - return NULL; - while (btf_type_is_modifier(ctx_struct)) - ctx_struct = btf_type_by_id(btf_vmlinux, ctx_struct->type); - goto again; - } - return ctx_type; -} - -static const struct bpf_map_ops * const btf_vmlinux_map_ops[] = { -#define BPF_PROG_TYPE(_id, _name, prog_ctx_type, kern_ctx_type) -#define BPF_LINK_TYPE(_id, _name) -#define BPF_MAP_TYPE(_id, _ops) \ - [_id] = &_ops, -#include -#undef BPF_PROG_TYPE -#undef BPF_LINK_TYPE -#undef BPF_MAP_TYPE -}; - -static int btf_vmlinux_map_ids_init(const struct btf *btf, - struct bpf_verifier_log *log) -{ - const struct bpf_map_ops *ops; - int i, btf_id; - - for (i = 0; i < ARRAY_SIZE(btf_vmlinux_map_ops); ++i) { - ops = btf_vmlinux_map_ops[i]; - if (!ops || (!ops->map_btf_name && !ops->map_btf_id)) - continue; - if (!ops->map_btf_name || !ops->map_btf_id) { - bpf_log(log, "map type %d is misconfigured\n", i); - return -EINVAL; - } - btf_id = btf_find_by_name_kind(btf, ops->map_btf_name, - BTF_KIND_STRUCT); - if (btf_id < 0) - return btf_id; - *ops->map_btf_id = btf_id; - } - - return 0; -} - -static int btf_translate_to_vmlinux(struct bpf_verifier_log *log, - struct btf *btf, - const struct btf_type *t, - enum bpf_prog_type prog_type, - int arg) -{ - const struct btf_member *prog_ctx_type, *kern_ctx_type; - - prog_ctx_type = btf_get_prog_ctx_type(log, btf, t, prog_type, arg); - if (!prog_ctx_type) - return -ENOENT; - kern_ctx_type = prog_ctx_type + 1; - return kern_ctx_type->type; -} - -BTF_ID_LIST(bpf_ctx_convert_btf_id) -BTF_ID(struct, bpf_ctx_convert) - -struct btf *btf_parse_vmlinux(void) -{ - struct btf_verifier_env *env = NULL; - struct bpf_verifier_log *log; - struct btf *btf = NULL; - int err; - - env = kzalloc(sizeof(*env), GFP_KERNEL | __GFP_NOWARN); - if (!env) - return ERR_PTR(-ENOMEM); - - log = &env->log; - log->level = BPF_LOG_KERNEL; - - btf = kzalloc(sizeof(*btf), GFP_KERNEL | __GFP_NOWARN); - if (!btf) { - err = -ENOMEM; - goto errout; - } - env->btf = btf; - - btf->data = _binary__btf_vmlinux_bin_start; - btf->data_size = _binary__btf_vmlinux_bin_end - - _binary__btf_vmlinux_bin_start; - - err = btf_parse_hdr(env); - if (err) - goto errout; - - btf->nohdr_data = btf->data + btf->hdr.hdr_len; - - err = btf_parse_str_sec(env); - if (err) - goto errout; - - err = btf_check_all_metas(env); - if (err) - goto errout; - - /* btf_parse_vmlinux() runs under bpf_verifier_lock */ - bpf_ctx_convert.t = btf_type_by_id(btf, bpf_ctx_convert_btf_id[0]); - - /* find bpf map structs for map_ptr access checking */ - err = btf_vmlinux_map_ids_init(btf, log); - if (err < 0) - goto errout; - - bpf_struct_ops_init(btf, log); - - btf_verifier_env_free(env); - refcount_set(&btf->refcnt, 1); - return btf; - -errout: - btf_verifier_env_free(env); - if (btf) { - kvfree(btf->types); - kfree(btf); - } - return ERR_PTR(err); -} - -struct btf *bpf_prog_get_target_btf(const struct bpf_prog *prog) -{ - struct bpf_prog *tgt_prog = prog->aux->dst_prog; - - if (tgt_prog) { - return tgt_prog->aux->btf; - } else { - return btf_vmlinux; - } -} - -static bool is_string_ptr(struct btf *btf, const struct btf_type *t) -{ - /* t comes in already as a pointer */ - t = btf_type_by_id(btf, t->type); - - /* allow const */ - if (BTF_INFO_KIND(t->info) == BTF_KIND_CONST) - t = btf_type_by_id(btf, t->type); - - /* char, signed char, unsigned char */ - return btf_type_is_int(t) && t->size == 1; -} - -bool btf_ctx_access(int off, int size, enum bpf_access_type type, - const struct bpf_prog *prog, - struct bpf_insn_access_aux *info) -{ - const struct btf_type *t = prog->aux->attach_func_proto; - struct bpf_prog *tgt_prog = prog->aux->dst_prog; - struct btf *btf = bpf_prog_get_target_btf(prog); - const char *tname = prog->aux->attach_func_name; - struct bpf_verifier_log *log = info->log; - const struct btf_param *args; - u32 nr_args, arg; - int i, ret; - - if (off % 8) { - bpf_log(log, "func '%s' offset %d is not multiple of 8\n", - tname, off); - return false; - } - arg = off / 8; - args = (const struct btf_param *)(t + 1); - /* if (t == NULL) Fall back to default BPF prog with 5 u64 arguments */ - nr_args = t ? btf_type_vlen(t) : 5; - if (prog->aux->attach_btf_trace) { - /* skip first 'void *__data' argument in btf_trace_##name typedef */ - args++; - nr_args--; - } - - if (arg > nr_args) { - bpf_log(log, "func '%s' doesn't have %d-th argument\n", - tname, arg + 1); - return false; - } - - if (arg == nr_args) { - switch (prog->expected_attach_type) { - case BPF_LSM_MAC: - case BPF_TRACE_FEXIT: - /* When LSM programs are attached to void LSM hooks - * they use FEXIT trampolines and when attached to - * int LSM hooks, they use MODIFY_RETURN trampolines. - * - * While the LSM programs are BPF_MODIFY_RETURN-like - * the check: - * - * if (ret_type != 'int') - * return -EINVAL; - * - * is _not_ done here. This is still safe as LSM hooks - * have only void and int return types. - */ - if (!t) - return true; - t = btf_type_by_id(btf, t->type); - break; - case BPF_MODIFY_RETURN: - /* For now the BPF_MODIFY_RETURN can only be attached to - * functions that return an int. - */ - if (!t) - return false; - - t = btf_type_skip_modifiers(btf, t->type, NULL); - if (!btf_type_is_small_int(t)) { - bpf_log(log, - "ret type %s not allowed for fmod_ret\n", - btf_kind_str[BTF_INFO_KIND(t->info)]); - return false; - } - break; - default: - bpf_log(log, "func '%s' doesn't have %d-th argument\n", - tname, arg + 1); - return false; - } - } else { - if (!t) - /* Default prog with 5 args */ - return true; - t = btf_type_by_id(btf, args[arg].type); - } - - /* skip modifiers */ - while (btf_type_is_modifier(t)) - t = btf_type_by_id(btf, t->type); - if (btf_type_is_small_int(t) || btf_type_is_enum(t)) - /* accessing a scalar */ - return true; - if (!btf_type_is_ptr(t)) { - bpf_log(log, - "func '%s' arg%d '%s' has type %s. Only pointer access is allowed\n", - tname, arg, - __btf_name_by_offset(btf, t->name_off), - btf_kind_str[BTF_INFO_KIND(t->info)]); - return false; - } - - /* check for PTR_TO_RDONLY_BUF_OR_NULL or PTR_TO_RDWR_BUF_OR_NULL */ - for (i = 0; i < prog->aux->ctx_arg_info_size; i++) { - const struct bpf_ctx_arg_aux *ctx_arg_info = &prog->aux->ctx_arg_info[i]; - - if (ctx_arg_info->offset == off && - (ctx_arg_info->reg_type == PTR_TO_RDONLY_BUF_OR_NULL || - ctx_arg_info->reg_type == PTR_TO_RDWR_BUF_OR_NULL)) { - info->reg_type = ctx_arg_info->reg_type; - return true; - } - } - - if (t->type == 0) - /* This is a pointer to void. - * It is the same as scalar from the verifier safety pov. - * No further pointer walking is allowed. - */ - return true; - - if (is_string_ptr(btf, t)) - return true; - - /* this is a pointer to another type */ - for (i = 0; i < prog->aux->ctx_arg_info_size; i++) { - const struct bpf_ctx_arg_aux *ctx_arg_info = &prog->aux->ctx_arg_info[i]; - - if (ctx_arg_info->offset == off) { - info->reg_type = ctx_arg_info->reg_type; - info->btf_id = ctx_arg_info->btf_id; - return true; - } - } - - info->reg_type = PTR_TO_BTF_ID; - if (tgt_prog) { - enum bpf_prog_type tgt_type; - - if (tgt_prog->type == BPF_PROG_TYPE_EXT) - tgt_type = tgt_prog->aux->saved_dst_prog_type; - else - tgt_type = tgt_prog->type; - - ret = btf_translate_to_vmlinux(log, btf, t, tgt_type, arg); - if (ret > 0) { - info->btf_id = ret; - return true; - } else { - return false; - } - } - - info->btf_id = t->type; - t = btf_type_by_id(btf, t->type); - /* skip modifiers */ - while (btf_type_is_modifier(t)) { - info->btf_id = t->type; - t = btf_type_by_id(btf, t->type); - } - if (!btf_type_is_struct(t)) { - bpf_log(log, - "func '%s' arg%d type %s is not a struct\n", - tname, arg, btf_kind_str[BTF_INFO_KIND(t->info)]); - return false; - } - bpf_log(log, "func '%s' arg%d has btf_id %d type %s '%s'\n", - tname, arg, info->btf_id, btf_kind_str[BTF_INFO_KIND(t->info)], - __btf_name_by_offset(btf, t->name_off)); - return true; -} - -enum bpf_struct_walk_result { - /* < 0 error */ - WALK_SCALAR = 0, - WALK_PTR, - WALK_STRUCT, -}; - -static int btf_struct_walk(struct bpf_verifier_log *log, - const struct btf_type *t, int off, int size, - u32 *next_btf_id) -{ - u32 i, moff, mtrue_end, msize = 0, total_nelems = 0; - const struct btf_type *mtype, *elem_type = NULL; - const struct btf_member *member; - const char *tname, *mname; - u32 vlen, elem_id, mid; - -again: - tname = __btf_name_by_offset(btf_vmlinux, t->name_off); - if (!btf_type_is_struct(t)) { - bpf_log(log, "Type '%s' is not a struct\n", tname); - return -EINVAL; - } - - vlen = btf_type_vlen(t); - if (off + size > t->size) { - /* If the last element is a variable size array, we may - * need to relax the rule. - */ - struct btf_array *array_elem; - - if (vlen == 0) - goto error; - - member = btf_type_member(t) + vlen - 1; - mtype = btf_type_skip_modifiers(btf_vmlinux, member->type, - NULL); - if (!btf_type_is_array(mtype)) - goto error; - - array_elem = (struct btf_array *)(mtype + 1); - if (array_elem->nelems != 0) - goto error; - - moff = btf_member_bit_offset(t, member) / 8; - if (off < moff) - goto error; - - /* Only allow structure for now, can be relaxed for - * other types later. - */ - t = btf_type_skip_modifiers(btf_vmlinux, array_elem->type, - NULL); - if (!btf_type_is_struct(t)) - goto error; - - off = (off - moff) % t->size; - goto again; - -error: - bpf_log(log, "access beyond struct %s at off %u size %u\n", - tname, off, size); - return -EACCES; - } - - for_each_member(i, t, member) { - /* offset of the field in bytes */ - moff = btf_member_bit_offset(t, member) / 8; - if (off + size <= moff) - /* won't find anything, field is already too far */ - break; - - if (btf_member_bitfield_size(t, member)) { - u32 end_bit = btf_member_bit_offset(t, member) + - btf_member_bitfield_size(t, member); - - /* off <= moff instead of off == moff because clang - * does not generate a BTF member for anonymous - * bitfield like the ":16" here: - * struct { - * int :16; - * int x:8; - * }; - */ - if (off <= moff && - BITS_ROUNDUP_BYTES(end_bit) <= off + size) - return WALK_SCALAR; - - /* off may be accessing a following member - * - * or - * - * Doing partial access at either end of this - * bitfield. Continue on this case also to - * treat it as not accessing this bitfield - * and eventually error out as field not - * found to keep it simple. - * It could be relaxed if there was a legit - * partial access case later. - */ - continue; - } - - /* In case of "off" is pointing to holes of a struct */ - if (off < moff) - break; - - /* type of the field */ - mid = member->type; - mtype = btf_type_by_id(btf_vmlinux, member->type); - mname = __btf_name_by_offset(btf_vmlinux, member->name_off); - - mtype = __btf_resolve_size(btf_vmlinux, mtype, &msize, - &elem_type, &elem_id, &total_nelems, - &mid); - if (IS_ERR(mtype)) { - bpf_log(log, "field %s doesn't have size\n", mname); - return -EFAULT; - } - - mtrue_end = moff + msize; - if (off >= mtrue_end) - /* no overlap with member, keep iterating */ - continue; - - if (btf_type_is_array(mtype)) { - u32 elem_idx; - - /* __btf_resolve_size() above helps to - * linearize a multi-dimensional array. - * - * The logic here is treating an array - * in a struct as the following way: - * - * struct outer { - * struct inner array[2][2]; - * }; - * - * looks like: - * - * struct outer { - * struct inner array_elem0; - * struct inner array_elem1; - * struct inner array_elem2; - * struct inner array_elem3; - * }; - * - * When accessing outer->array[1][0], it moves - * moff to "array_elem2", set mtype to - * "struct inner", and msize also becomes - * sizeof(struct inner). Then most of the - * remaining logic will fall through without - * caring the current member is an array or - * not. - * - * Unlike mtype/msize/moff, mtrue_end does not - * change. The naming difference ("_true") tells - * that it is not always corresponding to - * the current mtype/msize/moff. - * It is the true end of the current - * member (i.e. array in this case). That - * will allow an int array to be accessed like - * a scratch space, - * i.e. allow access beyond the size of - * the array's element as long as it is - * within the mtrue_end boundary. - */ - - /* skip empty array */ - if (moff == mtrue_end) - continue; - - msize /= total_nelems; - elem_idx = (off - moff) / msize; - moff += elem_idx * msize; - mtype = elem_type; - mid = elem_id; - } - - /* the 'off' we're looking for is either equal to start - * of this field or inside of this struct - */ - if (btf_type_is_struct(mtype)) { - /* our field must be inside that union or struct */ - t = mtype; - - /* return if the offset matches the member offset */ - if (off == moff) { - *next_btf_id = mid; - return WALK_STRUCT; - } - - /* adjust offset we're looking for */ - off -= moff; - goto again; - } - - if (btf_type_is_ptr(mtype)) { - const struct btf_type *stype; - u32 id; - - if (msize != size || off != moff) { - bpf_log(log, - "cannot access ptr member %s with moff %u in struct %s with off %u size %u\n", - mname, moff, tname, off, size); - return -EACCES; - } - stype = btf_type_skip_modifiers(btf_vmlinux, mtype->type, &id); - if (btf_type_is_struct(stype)) { - *next_btf_id = id; - return WALK_PTR; - } - } - - /* Allow more flexible access within an int as long as - * it is within mtrue_end. - * Since mtrue_end could be the end of an array, - * that also allows using an array of int as a scratch - * space. e.g. skb->cb[]. - */ - if (off + size > mtrue_end) { - bpf_log(log, - "access beyond the end of member %s (mend:%u) in struct %s with off %u size %u\n", - mname, mtrue_end, tname, off, size); - return -EACCES; - } - - return WALK_SCALAR; - } - bpf_log(log, "struct %s doesn't have field at offset %d\n", tname, off); - return -EINVAL; -} - -int btf_struct_access(struct bpf_verifier_log *log, - const struct btf_type *t, int off, int size, - enum bpf_access_type atype __maybe_unused, - u32 *next_btf_id) -{ - int err; - u32 id; - - do { - err = btf_struct_walk(log, t, off, size, &id); - - switch (err) { - case WALK_PTR: - /* If we found the pointer or scalar on t+off, - * we're done. - */ - *next_btf_id = id; - return PTR_TO_BTF_ID; - case WALK_SCALAR: - return SCALAR_VALUE; - case WALK_STRUCT: - /* We found nested struct, so continue the search - * by diving in it. At this point the offset is - * aligned with the new type, so set it to 0. - */ - t = btf_type_by_id(btf_vmlinux, id); - off = 0; - break; - default: - /* It's either error or unknown return value.. - * scream and leave. - */ - if (WARN_ONCE(err > 0, "unknown btf_struct_walk return value")) - return -EINVAL; - return err; - } - } while (t); - - return -EINVAL; -} - -bool btf_struct_ids_match(struct bpf_verifier_log *log, - int off, u32 id, u32 need_type_id) -{ - const struct btf_type *type; - int err; - - /* Are we already done? */ - if (need_type_id == id && off == 0) - return true; - -again: - type = btf_type_by_id(btf_vmlinux, id); - if (!type) - return false; - err = btf_struct_walk(log, type, off, 1, &id); - if (err != WALK_STRUCT) - return false; - - /* We found nested struct object. If it matches - * the requested ID, we're done. Otherwise let's - * continue the search with offset 0 in the new - * type. - */ - if (need_type_id != id) { - off = 0; - goto again; - } - - return true; -} - -static int __get_type_size(struct btf *btf, u32 btf_id, - const struct btf_type **bad_type) -{ - const struct btf_type *t; - - if (!btf_id) - /* void */ - return 0; - t = btf_type_by_id(btf, btf_id); - while (t && btf_type_is_modifier(t)) - t = btf_type_by_id(btf, t->type); - if (!t) { - *bad_type = btf->types[0]; - return -EINVAL; - } - if (btf_type_is_ptr(t)) - /* kernel size of pointer. Not BPF's size of pointer*/ - return sizeof(void *); - if (btf_type_is_int(t) || btf_type_is_enum(t)) - return t->size; - *bad_type = t; - return -EINVAL; -} - -int btf_distill_func_proto(struct bpf_verifier_log *log, - struct btf *btf, - const struct btf_type *func, - const char *tname, - struct btf_func_model *m) -{ - const struct btf_param *args; - const struct btf_type *t; - u32 i, nargs; - int ret; - - if (!func) { - /* BTF function prototype doesn't match the verifier types. - * Fall back to 5 u64 args. - */ - for (i = 0; i < 5; i++) - m->arg_size[i] = 8; - m->ret_size = 8; - m->nr_args = 5; - return 0; - } - args = (const struct btf_param *)(func + 1); - nargs = btf_type_vlen(func); - if (nargs >= MAX_BPF_FUNC_ARGS) { - bpf_log(log, - "The function %s has %d arguments. Too many.\n", - tname, nargs); - return -EINVAL; - } - ret = __get_type_size(btf, func->type, &t); - if (ret < 0) { - bpf_log(log, - "The function %s return type %s is unsupported.\n", - tname, btf_kind_str[BTF_INFO_KIND(t->info)]); - return -EINVAL; - } - m->ret_size = ret; - - for (i = 0; i < nargs; i++) { - if (i == nargs - 1 && args[i].type == 0) { - bpf_log(log, - "The function %s with variable args is unsupported.\n", - tname); - return -EINVAL; - } - ret = __get_type_size(btf, args[i].type, &t); - if (ret < 0) { - bpf_log(log, - "The function %s arg%d type %s is unsupported.\n", - tname, i, btf_kind_str[BTF_INFO_KIND(t->info)]); - return -EINVAL; - } - if (ret == 0) { - bpf_log(log, - "The function %s has malformed void argument.\n", - tname); - return -EINVAL; - } - m->arg_size[i] = ret; - } - m->nr_args = nargs; - return 0; -} - -/* Compare BTFs of two functions assuming only scalars and pointers to context. - * t1 points to BTF_KIND_FUNC in btf1 - * t2 points to BTF_KIND_FUNC in btf2 - * Returns: - * EINVAL - function prototype mismatch - * EFAULT - verifier bug - * 0 - 99% match. The last 1% is validated by the verifier. - */ -static int btf_check_func_type_match(struct bpf_verifier_log *log, - struct btf *btf1, const struct btf_type *t1, - struct btf *btf2, const struct btf_type *t2) -{ - const struct btf_param *args1, *args2; - const char *fn1, *fn2, *s1, *s2; - u32 nargs1, nargs2, i; - - fn1 = btf_name_by_offset(btf1, t1->name_off); - fn2 = btf_name_by_offset(btf2, t2->name_off); - - if (btf_func_linkage(t1) != BTF_FUNC_GLOBAL) { - bpf_log(log, "%s() is not a global function\n", fn1); - return -EINVAL; - } - if (btf_func_linkage(t2) != BTF_FUNC_GLOBAL) { - bpf_log(log, "%s() is not a global function\n", fn2); - return -EINVAL; - } - - t1 = btf_type_by_id(btf1, t1->type); - if (!t1 || !btf_type_is_func_proto(t1)) - return -EFAULT; - t2 = btf_type_by_id(btf2, t2->type); - if (!t2 || !btf_type_is_func_proto(t2)) - return -EFAULT; - - args1 = (const struct btf_param *)(t1 + 1); - nargs1 = btf_type_vlen(t1); - args2 = (const struct btf_param *)(t2 + 1); - nargs2 = btf_type_vlen(t2); - - if (nargs1 != nargs2) { - bpf_log(log, "%s() has %d args while %s() has %d args\n", - fn1, nargs1, fn2, nargs2); - return -EINVAL; - } - - t1 = btf_type_skip_modifiers(btf1, t1->type, NULL); - t2 = btf_type_skip_modifiers(btf2, t2->type, NULL); - if (t1->info != t2->info) { - bpf_log(log, - "Return type %s of %s() doesn't match type %s of %s()\n", - btf_type_str(t1), fn1, - btf_type_str(t2), fn2); - return -EINVAL; - } - - for (i = 0; i < nargs1; i++) { - t1 = btf_type_skip_modifiers(btf1, args1[i].type, NULL); - t2 = btf_type_skip_modifiers(btf2, args2[i].type, NULL); - - if (t1->info != t2->info) { - bpf_log(log, "arg%d in %s() is %s while %s() has %s\n", - i, fn1, btf_type_str(t1), - fn2, btf_type_str(t2)); - return -EINVAL; - } - if (btf_type_has_size(t1) && t1->size != t2->size) { - bpf_log(log, - "arg%d in %s() has size %d while %s() has %d\n", - i, fn1, t1->size, - fn2, t2->size); - return -EINVAL; - } - - /* global functions are validated with scalars and pointers - * to context only. And only global functions can be replaced. - * Hence type check only those types. - */ - if (btf_type_is_int(t1) || btf_type_is_enum(t1)) - continue; - if (!btf_type_is_ptr(t1)) { - bpf_log(log, - "arg%d in %s() has unrecognized type\n", - i, fn1); - return -EINVAL; - } - t1 = btf_type_skip_modifiers(btf1, t1->type, NULL); - t2 = btf_type_skip_modifiers(btf2, t2->type, NULL); - if (!btf_type_is_struct(t1)) { - bpf_log(log, - "arg%d in %s() is not a pointer to context\n", - i, fn1); - return -EINVAL; - } - if (!btf_type_is_struct(t2)) { - bpf_log(log, - "arg%d in %s() is not a pointer to context\n", - i, fn2); - return -EINVAL; - } - /* This is an optional check to make program writing easier. - * Compare names of structs and report an error to the user. - * btf_prepare_func_args() already checked that t2 struct - * is a context type. btf_prepare_func_args() will check - * later that t1 struct is a context type as well. - */ - s1 = btf_name_by_offset(btf1, t1->name_off); - s2 = btf_name_by_offset(btf2, t2->name_off); - if (strcmp(s1, s2)) { - bpf_log(log, - "arg%d %s(struct %s *) doesn't match %s(struct %s *)\n", - i, fn1, s1, fn2, s2); - return -EINVAL; - } - } - return 0; -} - -/* Compare BTFs of given program with BTF of target program */ -int btf_check_type_match(struct bpf_verifier_log *log, const struct bpf_prog *prog, - struct btf *btf2, const struct btf_type *t2) -{ - struct btf *btf1 = prog->aux->btf; - const struct btf_type *t1; - u32 btf_id = 0; - - if (!prog->aux->func_info) { - bpf_log(log, "Program extension requires BTF\n"); - return -EINVAL; - } - - btf_id = prog->aux->func_info[0].type_id; - if (!btf_id) - return -EFAULT; - - t1 = btf_type_by_id(btf1, btf_id); - if (!t1 || !btf_type_is_func(t1)) - return -EFAULT; - - return btf_check_func_type_match(log, btf1, t1, btf2, t2); -} - -/* Compare BTF of a function with given bpf_reg_state. - * Returns: - * EFAULT - there is a verifier bug. Abort verification. - * EINVAL - there is a type mismatch or BTF is not available. - * 0 - BTF matches with what bpf_reg_state expects. - * Only PTR_TO_CTX and SCALAR_VALUE states are recognized. - */ -int btf_check_func_arg_match(struct bpf_verifier_env *env, int subprog, - struct bpf_reg_state *reg) -{ - struct bpf_verifier_log *log = &env->log; - struct bpf_prog *prog = env->prog; - struct btf *btf = prog->aux->btf; - const struct btf_param *args; - const struct btf_type *t; - u32 i, nargs, btf_id; - const char *tname; - - if (!prog->aux->func_info) - return -EINVAL; - - btf_id = prog->aux->func_info[subprog].type_id; - if (!btf_id) - return -EFAULT; - - if (prog->aux->func_info_aux[subprog].unreliable) - return -EINVAL; - - t = btf_type_by_id(btf, btf_id); - if (!t || !btf_type_is_func(t)) { - /* These checks were already done by the verifier while loading - * struct bpf_func_info - */ - bpf_log(log, "BTF of func#%d doesn't point to KIND_FUNC\n", - subprog); - return -EFAULT; - } - tname = btf_name_by_offset(btf, t->name_off); - - t = btf_type_by_id(btf, t->type); - if (!t || !btf_type_is_func_proto(t)) { - bpf_log(log, "Invalid BTF of func %s\n", tname); - return -EFAULT; - } - args = (const struct btf_param *)(t + 1); - nargs = btf_type_vlen(t); - if (nargs > 5) { - bpf_log(log, "Function %s has %d > 5 args\n", tname, nargs); - goto out; - } - /* check that BTF function arguments match actual types that the - * verifier sees. - */ - for (i = 0; i < nargs; i++) { - t = btf_type_by_id(btf, args[i].type); - while (btf_type_is_modifier(t)) - t = btf_type_by_id(btf, t->type); - if (btf_type_is_int(t) || btf_type_is_enum(t)) { - if (reg[i + 1].type == SCALAR_VALUE) - continue; - bpf_log(log, "R%d is not a scalar\n", i + 1); - goto out; - } - if (btf_type_is_ptr(t)) { - if (reg[i + 1].type == SCALAR_VALUE) { - bpf_log(log, "R%d is not a pointer\n", i + 1); - goto out; - } - /* If function expects ctx type in BTF check that caller - * is passing PTR_TO_CTX. - */ - if (btf_get_prog_ctx_type(log, btf, t, prog->type, i)) { - if (reg[i + 1].type != PTR_TO_CTX) { - bpf_log(log, - "arg#%d expected pointer to ctx, but got %s\n", - i, btf_kind_str[BTF_INFO_KIND(t->info)]); - goto out; - } - if (check_ctx_reg(env, ®[i + 1], i + 1)) - goto out; - continue; - } - } - bpf_log(log, "Unrecognized arg#%d type %s\n", - i, btf_kind_str[BTF_INFO_KIND(t->info)]); - goto out; - } - return 0; -out: - /* Compiler optimizations can remove arguments from static functions - * or mismatched type can be passed into a global function. - * In such cases mark the function as unreliable from BTF point of view. - */ - prog->aux->func_info_aux[subprog].unreliable = true; - return -EINVAL; -} - -/* Convert BTF of a function into bpf_reg_state if possible - * Returns: - * EFAULT - there is a verifier bug. Abort verification. - * EINVAL - cannot convert BTF. - * 0 - Successfully converted BTF into bpf_reg_state - * (either PTR_TO_CTX or SCALAR_VALUE). - */ -int btf_prepare_func_args(struct bpf_verifier_env *env, int subprog, - struct bpf_reg_state *reg) -{ - struct bpf_verifier_log *log = &env->log; - struct bpf_prog *prog = env->prog; - enum bpf_prog_type prog_type = prog->type; - struct btf *btf = prog->aux->btf; - const struct btf_param *args; - const struct btf_type *t; - u32 i, nargs, btf_id; - const char *tname; - - if (!prog->aux->func_info || - prog->aux->func_info_aux[subprog].linkage != BTF_FUNC_GLOBAL) { - bpf_log(log, "Verifier bug\n"); - return -EFAULT; - } - - btf_id = prog->aux->func_info[subprog].type_id; - if (!btf_id) { - bpf_log(log, "Global functions need valid BTF\n"); - return -EFAULT; - } - - t = btf_type_by_id(btf, btf_id); - if (!t || !btf_type_is_func(t)) { - /* These checks were already done by the verifier while loading - * struct bpf_func_info - */ - bpf_log(log, "BTF of func#%d doesn't point to KIND_FUNC\n", - subprog); - return -EFAULT; - } - tname = btf_name_by_offset(btf, t->name_off); - - if (log->level & BPF_LOG_LEVEL) - bpf_log(log, "Validating %s() func#%d...\n", - tname, subprog); - - if (prog->aux->func_info_aux[subprog].unreliable) { - bpf_log(log, "Verifier bug in function %s()\n", tname); - return -EFAULT; - } - if (prog_type == BPF_PROG_TYPE_EXT) - prog_type = prog->aux->dst_prog->type; - - t = btf_type_by_id(btf, t->type); - if (!t || !btf_type_is_func_proto(t)) { - bpf_log(log, "Invalid type of function %s()\n", tname); - return -EFAULT; - } - args = (const struct btf_param *)(t + 1); - nargs = btf_type_vlen(t); - if (nargs > 5) { - bpf_log(log, "Global function %s() with %d > 5 args. Buggy compiler.\n", - tname, nargs); - return -EINVAL; - } - /* check that function returns int */ - t = btf_type_by_id(btf, t->type); - while (btf_type_is_modifier(t)) - t = btf_type_by_id(btf, t->type); - if (!btf_type_is_int(t) && !btf_type_is_enum(t)) { - bpf_log(log, - "Global function %s() doesn't return scalar. Only those are supported.\n", - tname); - return -EINVAL; - } - /* Convert BTF function arguments into verifier types. - * Only PTR_TO_CTX and SCALAR are supported atm. - */ - for (i = 0; i < nargs; i++) { - t = btf_type_by_id(btf, args[i].type); - while (btf_type_is_modifier(t)) - t = btf_type_by_id(btf, t->type); - if (btf_type_is_int(t) || btf_type_is_enum(t)) { - reg[i + 1].type = SCALAR_VALUE; - continue; - } - if (btf_type_is_ptr(t) && - btf_get_prog_ctx_type(log, btf, t, prog_type, i)) { - reg[i + 1].type = PTR_TO_CTX; - continue; - } - bpf_log(log, "Arg#%d type %s in %s() is not supported yet.\n", - i, btf_kind_str[BTF_INFO_KIND(t->info)], tname); - return -EINVAL; - } - return 0; -} - -static void btf_type_show(const struct btf *btf, u32 type_id, void *obj, - struct btf_show *show) -{ - const struct btf_type *t = btf_type_by_id(btf, type_id); - - show->btf = btf; - memset(&show->state, 0, sizeof(show->state)); - memset(&show->obj, 0, sizeof(show->obj)); - - btf_type_ops(t)->show(btf, t, type_id, obj, 0, show); -} - -__printf(2, 0) static void btf_seq_show(struct btf_show *show, const char *fmt, - va_list args) -{ - seq_vprintf((struct seq_file *)show->target, fmt, args); -} - -int btf_type_seq_show_flags(const struct btf *btf, u32 type_id, - void *obj, struct seq_file *m, u64 flags) -{ - struct btf_show sseq; - - sseq.target = m; - sseq.showfn = btf_seq_show; - sseq.flags = flags; - - btf_type_show(btf, type_id, obj, &sseq); - - return sseq.state.status; -} - void btf_type_seq_show(const struct btf *btf, u32 type_id, void *obj, struct seq_file *m) { - (void) btf_type_seq_show_flags(btf, type_id, obj, m, - BTF_SHOW_NONAME | BTF_SHOW_COMPACT | - BTF_SHOW_ZERO | BTF_SHOW_UNSAFE); -} + const struct btf_type *t = btf_type_by_id(btf, type_id); -struct btf_show_snprintf { - struct btf_show show; - int len_left; /* space left in string */ - int len; /* length we would have written */ -}; - -__printf(2, 0) static void btf_snprintf_show(struct btf_show *show, const char *fmt, - va_list args) -{ - struct btf_show_snprintf *ssnprintf = (struct btf_show_snprintf *)show; - int len; - - len = vsnprintf(show->target, ssnprintf->len_left, fmt, args); - - if (len < 0) { - ssnprintf->len_left = 0; - ssnprintf->len = len; - } else if (len > ssnprintf->len_left) { - /* no space, drive on to get length we would have written */ - ssnprintf->len_left = 0; - ssnprintf->len += len; - } else { - ssnprintf->len_left -= len; - ssnprintf->len += len; - show->target += len; - } -} - -int btf_type_snprintf_show(const struct btf *btf, u32 type_id, void *obj, - char *buf, int len, u64 flags) -{ - struct btf_show_snprintf ssnprintf; - - ssnprintf.show.target = buf; - ssnprintf.show.flags = flags; - ssnprintf.show.showfn = btf_snprintf_show; - ssnprintf.len_left = len; - ssnprintf.len = 0; - - btf_type_show(btf, type_id, obj, (struct btf_show *)&ssnprintf); - - /* If we encontered an error, return it. */ - if (ssnprintf.show.state.status) - return ssnprintf.show.state.status; - - /* Otherwise return length we would have written */ - return ssnprintf.len; + btf_type_ops(t)->seq_show(btf, t, type_id, obj, 0, m); } #ifdef CONFIG_PROC_FS @@ -5560,15 +3518,3 @@ u32 btf_id(const struct btf *btf) { return btf->id; } - -static int btf_id_cmp_func(const void *a, const void *b) -{ - const int *pa = a, *pb = b; - - return *pa - *pb; -} - -bool btf_id_set_contains(const struct btf_id_set *set, u32 id) -{ - return bsearch(&id, set->ids, set->cnt, sizeof(u32), btf_id_cmp_func) != NULL; -} diff --git a/kernel/bpf/cgroup.c b/kernel/bpf/cgroup.c index 1cb71cb27ff1..08c1246c758e 100644 --- a/kernel/bpf/cgroup.c +++ b/kernel/bpf/cgroup.c @@ -28,78 +28,6 @@ void cgroup_bpf_offline(struct cgroup *cgrp) percpu_ref_kill(&cgrp->bpf.refcnt); } -static void bpf_cgroup_storages_free(struct bpf_cgroup_storage *storages[]) -{ - enum bpf_cgroup_storage_type stype; - - for_each_cgroup_storage_type(stype) - bpf_cgroup_storage_free(storages[stype]); -} - -static int bpf_cgroup_storages_alloc(struct bpf_cgroup_storage *storages[], - struct bpf_cgroup_storage *new_storages[], - enum bpf_attach_type type, - struct bpf_prog *prog, - struct cgroup *cgrp) -{ - enum bpf_cgroup_storage_type stype; - struct bpf_cgroup_storage_key key; - struct bpf_map *map; - - key.cgroup_inode_id = cgroup_id(cgrp); - key.attach_type = type; - - for_each_cgroup_storage_type(stype) { - map = prog->aux->cgroup_storage[stype]; - if (!map) - continue; - - storages[stype] = cgroup_storage_lookup((void *)map, &key, false); - if (storages[stype]) - continue; - - storages[stype] = bpf_cgroup_storage_alloc(prog, stype); - if (IS_ERR(storages[stype])) { - bpf_cgroup_storages_free(new_storages); - return -ENOMEM; - } - - new_storages[stype] = storages[stype]; - } - - return 0; -} - -static void bpf_cgroup_storages_assign(struct bpf_cgroup_storage *dst[], - struct bpf_cgroup_storage *src[]) -{ - enum bpf_cgroup_storage_type stype; - - for_each_cgroup_storage_type(stype) - dst[stype] = src[stype]; -} - -static void bpf_cgroup_storages_link(struct bpf_cgroup_storage *storages[], - struct cgroup *cgrp, - enum bpf_attach_type attach_type) -{ - enum bpf_cgroup_storage_type stype; - - for_each_cgroup_storage_type(stype) - bpf_cgroup_storage_link(storages[stype], cgrp, attach_type); -} - -/* Called when bpf_cgroup_link is auto-detached from dying cgroup. - * It drops cgroup and bpf_prog refcounts, and marks bpf_link as defunct. It - * doesn't free link memory, which will eventually be done by bpf_link's - * release() callback, when its last FD is closed. - */ -static void bpf_cgroup_link_auto_detach(struct bpf_cgroup_link *link) -{ - cgroup_put(link->cgroup); - link->cgroup = NULL; -} - /** * cgroup_bpf_release() - put references of all bpf programs and * release all cgroup bpf data @@ -109,24 +37,23 @@ static void cgroup_bpf_release(struct work_struct *work) { struct cgroup *p, *cgrp = container_of(work, struct cgroup, bpf.release_work); + enum bpf_cgroup_storage_type stype; struct bpf_prog_array *old_array; - struct list_head *storages = &cgrp->bpf.storages; - struct bpf_cgroup_storage *storage, *stmp; - unsigned int type; mutex_lock(&cgroup_mutex); for (type = 0; type < ARRAY_SIZE(cgrp->bpf.progs); type++) { struct list_head *progs = &cgrp->bpf.progs[type]; - struct bpf_prog_list *pl, *pltmp; + struct bpf_prog_list *pl, *tmp; - list_for_each_entry_safe(pl, pltmp, progs, node) { + list_for_each_entry_safe(pl, tmp, progs, node) { list_del(&pl->node); - if (pl->prog) - bpf_prog_put(pl->prog); - if (pl->link) - bpf_cgroup_link_auto_detach(pl->link); + bpf_prog_put(pl->prog); + for_each_cgroup_storage_type(stype) { + bpf_cgroup_storage_unlink(pl->storage[stype]); + bpf_cgroup_storage_free(pl->storage[stype]); + } kfree(pl); static_branch_dec(&cgroup_bpf_enabled_key); } @@ -136,11 +63,6 @@ static void cgroup_bpf_release(struct work_struct *work) bpf_prog_array_free(old_array); } - list_for_each_entry_safe(storage, stmp, storages, list_cg) { - bpf_cgroup_storage_unlink(storage); - bpf_cgroup_storage_free(storage); - } - mutex_unlock(&cgroup_mutex); for (p = cgroup_parent(cgrp); p; p = cgroup_parent(p)) @@ -163,18 +85,6 @@ static void cgroup_bpf_release_fn(struct percpu_ref *ref) queue_work(system_wq, &cgrp->bpf.release_work); } -/* Get underlying bpf_prog of bpf_prog_list entry, regardless if it's through - * link or direct prog. - */ -static struct bpf_prog *prog_list_prog(struct bpf_prog_list *pl) -{ - if (pl->prog) - return pl->prog; - if (pl->link) - return pl->link->link.prog; - return NULL; -} - /* count number of elements in the list. * it's slow but the list cannot be long */ @@ -184,7 +94,7 @@ static u32 prog_list_length(struct list_head *head) u32 cnt = 0; list_for_each_entry(pl, head, node) { - if (!prog_list_prog(pl)) + if (!pl->prog) continue; cnt++; } @@ -196,7 +106,8 @@ static u32 prog_list_length(struct list_head *head) * if parent has overridable or multi-prog, allow attaching */ static bool hierarchy_allows_attach(struct cgroup *cgrp, - enum bpf_attach_type type) + enum bpf_attach_type type, + u32 new_flags) { struct cgroup *p; @@ -228,7 +139,7 @@ static int compute_effective_progs(struct cgroup *cgrp, enum bpf_attach_type type, struct bpf_prog_array **array) { - struct bpf_prog_array_item *item; + enum bpf_cgroup_storage_type stype; struct bpf_prog_array *progs; struct bpf_prog_list *pl; struct cgroup *p = cgrp; @@ -253,13 +164,13 @@ static int compute_effective_progs(struct cgroup *cgrp, continue; list_for_each_entry(pl, &p->bpf.progs[type], node) { - if (!prog_list_prog(pl)) + if (!pl->prog) continue; - item = &progs->items[cnt]; - item->prog = prog_list_prog(pl); - bpf_cgroup_storages_assign(item->cgroup_storage, - pl->storage); + progs->items[cnt].prog = pl->prog; + for_each_cgroup_storage_type(stype) + progs->items[cnt].cgroup_storage[stype] = + pl->storage[stype]; cnt++; } } while ((p = cgroup_parent(p))); @@ -272,8 +183,8 @@ static void activate_effective_progs(struct cgroup *cgrp, enum bpf_attach_type type, struct bpf_prog_array *old_array) { - old_array = rcu_replace_pointer(cgrp->bpf.effective[type], old_array, - lockdep_is_held(&cgroup_mutex)); + rcu_swap_protected(cgrp->bpf.effective[type], old_array, + lockdep_is_held(&cgroup_mutex)); /* free prog array after grace period, since __cgroup_bpf_run_*() * might be still walking the array */ @@ -305,8 +216,6 @@ int cgroup_bpf_inherit(struct cgroup *cgrp) for (i = 0; i < NR; i++) INIT_LIST_HEAD(&cgrp->bpf.progs[i]); - INIT_LIST_HEAD(&cgrp->bpf.storages); - for (i = 0; i < NR; i++) if (compute_effective_progs(cgrp, i, &arrays[i])) goto cleanup; @@ -379,85 +288,36 @@ cleanup: #define BPF_CGROUP_MAX_PROGS 64 -static struct bpf_prog_list *find_attach_entry(struct list_head *progs, - struct bpf_prog *prog, - struct bpf_cgroup_link *link, - struct bpf_prog *replace_prog, - bool allow_multi) -{ - struct bpf_prog_list *pl; - - /* single-attach case */ - if (!allow_multi) { - if (list_empty(progs)) - return NULL; - return list_first_entry(progs, typeof(*pl), node); - } - - list_for_each_entry(pl, progs, node) { - if (prog && pl->prog == prog && prog != replace_prog) - /* disallow attaching the same prog twice */ - return ERR_PTR(-EINVAL); - if (link && pl->link == link) - /* disallow attaching the same link twice */ - return ERR_PTR(-EINVAL); - } - - /* direct prog multi-attach w/ replacement case */ - if (replace_prog) { - list_for_each_entry(pl, progs, node) { - if (pl->prog == replace_prog) - /* a match found */ - return pl; - } - /* prog to replace not found for cgroup */ - return ERR_PTR(-ENOENT); - } - - return NULL; -} - /** - * __cgroup_bpf_attach() - Attach the program or the link to a cgroup, and + * __cgroup_bpf_attach() - Attach the program to a cgroup, and * propagate the change to descendants * @cgrp: The cgroup which descendants to traverse * @prog: A program to attach - * @link: A link to attach - * @replace_prog: Previously attached program to replace if BPF_F_REPLACE is set * @type: Type of attach operation * @flags: Option flags * - * Exactly one of @prog or @link can be non-null. * Must be called with cgroup_mutex held. */ -int __cgroup_bpf_attach(struct cgroup *cgrp, - struct bpf_prog *prog, struct bpf_prog *replace_prog, - struct bpf_cgroup_link *link, +int __cgroup_bpf_attach(struct cgroup *cgrp, struct bpf_prog *prog, enum bpf_attach_type type, u32 flags) { - u32 saved_flags = (flags & (BPF_F_ALLOW_OVERRIDE | BPF_F_ALLOW_MULTI)); struct list_head *progs = &cgrp->bpf.progs[type]; struct bpf_prog *old_prog = NULL; struct bpf_cgroup_storage *storage[MAX_BPF_CGROUP_STORAGE_TYPE] = {}; - struct bpf_cgroup_storage *new_storage[MAX_BPF_CGROUP_STORAGE_TYPE] = {}; + struct bpf_cgroup_storage *old_storage[MAX_BPF_CGROUP_STORAGE_TYPE] = {}; + enum bpf_cgroup_storage_type stype; struct bpf_prog_list *pl; + bool pl_was_allocated; int err; - if (((flags & BPF_F_ALLOW_OVERRIDE) && (flags & BPF_F_ALLOW_MULTI)) || - ((flags & BPF_F_REPLACE) && !(flags & BPF_F_ALLOW_MULTI))) + if ((flags & BPF_F_ALLOW_OVERRIDE) && (flags & BPF_F_ALLOW_MULTI)) /* invalid combination */ return -EINVAL; - if (link && (prog || replace_prog)) - /* only either link or prog/replace_prog can be specified */ - return -EINVAL; - if (!!replace_prog != !!(flags & BPF_F_REPLACE)) - /* replace_prog implies BPF_F_REPLACE, and vice versa */ - return -EINVAL; - if (!hierarchy_allows_attach(cgrp, type)) + if (!hierarchy_allows_attach(cgrp, type, flags)) return -EPERM; - if (!list_empty(progs) && cgrp->bpf.flags[type] != saved_flags) + if (!list_empty(progs) && cgrp->bpf.flags[type] != flags) /* Disallow attaching non-overridable on top * of existing overridable in this cgroup. * Disallow attaching multi-prog if overridable or none @@ -467,297 +327,174 @@ int __cgroup_bpf_attach(struct cgroup *cgrp, if (prog_list_length(progs) >= BPF_CGROUP_MAX_PROGS) return -E2BIG; - pl = find_attach_entry(progs, prog, link, replace_prog, - flags & BPF_F_ALLOW_MULTI); - if (IS_ERR(pl)) - return PTR_ERR(pl); - - if (bpf_cgroup_storages_alloc(storage, new_storage, type, - prog ? : link->link.prog, cgrp)) - return -ENOMEM; - - if (pl) { - old_prog = pl->prog; - } else { - pl = kmalloc(sizeof(*pl), GFP_KERNEL); - if (!pl) { - bpf_cgroup_storages_free(new_storage); + for_each_cgroup_storage_type(stype) { + storage[stype] = bpf_cgroup_storage_alloc(prog, stype); + if (IS_ERR(storage[stype])) { + storage[stype] = NULL; + for_each_cgroup_storage_type(stype) + bpf_cgroup_storage_free(storage[stype]); return -ENOMEM; } - list_add_tail(&pl->node, progs); } - pl->prog = prog; - pl->link = link; - bpf_cgroup_storages_assign(pl->storage, storage); - cgrp->bpf.flags[type] = saved_flags; + if (flags & BPF_F_ALLOW_MULTI) { + list_for_each_entry(pl, progs, node) { + if (pl->prog == prog) { + /* disallow attaching the same prog twice */ + for_each_cgroup_storage_type(stype) + bpf_cgroup_storage_free(storage[stype]); + return -EINVAL; + } + } + + pl = kmalloc(sizeof(*pl), GFP_KERNEL); + if (!pl) { + for_each_cgroup_storage_type(stype) + bpf_cgroup_storage_free(storage[stype]); + return -ENOMEM; + } + + pl_was_allocated = true; + pl->prog = prog; + for_each_cgroup_storage_type(stype) + pl->storage[stype] = storage[stype]; + list_add_tail(&pl->node, progs); + } else { + if (list_empty(progs)) { + pl = kmalloc(sizeof(*pl), GFP_KERNEL); + if (!pl) { + for_each_cgroup_storage_type(stype) + bpf_cgroup_storage_free(storage[stype]); + return -ENOMEM; + } + pl_was_allocated = true; + list_add_tail(&pl->node, progs); + } else { + pl = list_first_entry(progs, typeof(*pl), node); + old_prog = pl->prog; + for_each_cgroup_storage_type(stype) { + old_storage[stype] = pl->storage[stype]; + bpf_cgroup_storage_unlink(old_storage[stype]); + } + pl_was_allocated = false; + } + pl->prog = prog; + for_each_cgroup_storage_type(stype) + pl->storage[stype] = storage[stype]; + } + + cgrp->bpf.flags[type] = flags; err = update_effective_progs(cgrp, type); if (err) goto cleanup; - if (old_prog) + static_branch_inc(&cgroup_bpf_enabled_key); + for_each_cgroup_storage_type(stype) { + if (!old_storage[stype]) + continue; + bpf_cgroup_storage_free(old_storage[stype]); + } + if (old_prog) { bpf_prog_put(old_prog); - else - static_branch_inc(&cgroup_bpf_enabled_key); - bpf_cgroup_storages_link(new_storage, cgrp, type); + static_branch_dec(&cgroup_bpf_enabled_key); + } + for_each_cgroup_storage_type(stype) + bpf_cgroup_storage_link(storage[stype], cgrp, type); return 0; cleanup: - if (old_prog) { - pl->prog = old_prog; - pl->link = NULL; + /* and cleanup the prog list */ + pl->prog = old_prog; + for_each_cgroup_storage_type(stype) { + bpf_cgroup_storage_free(pl->storage[stype]); + pl->storage[stype] = old_storage[stype]; + bpf_cgroup_storage_link(old_storage[stype], cgrp, type); } - bpf_cgroup_storages_free(new_storage); - if (!old_prog) { + if (pl_was_allocated) { list_del(&pl->node); kfree(pl); } return err; } -/* Swap updated BPF program for given link in effective program arrays across - * all descendant cgroups. This function is guaranteed to succeed. - */ -static void replace_effective_prog(struct cgroup *cgrp, - enum bpf_attach_type type, - struct bpf_cgroup_link *link) -{ - struct bpf_prog_array_item *item; - struct cgroup_subsys_state *css; - struct bpf_prog_array *progs; - struct bpf_prog_list *pl; - struct list_head *head; - struct cgroup *cg; - int pos; - - css_for_each_descendant_pre(css, &cgrp->self) { - struct cgroup *desc = container_of(css, struct cgroup, self); - - if (percpu_ref_is_zero(&desc->bpf.refcnt)) - continue; - - /* find position of link in effective progs array */ - for (pos = 0, cg = desc; cg; cg = cgroup_parent(cg)) { - if (pos && !(cg->bpf.flags[type] & BPF_F_ALLOW_MULTI)) - continue; - - head = &cg->bpf.progs[type]; - list_for_each_entry(pl, head, node) { - if (!prog_list_prog(pl)) - continue; - if (pl->link == link) - goto found; - pos++; - } - } -found: - BUG_ON(!cg); - progs = rcu_dereference_protected( - desc->bpf.effective[type], - lockdep_is_held(&cgroup_mutex)); - item = &progs->items[pos]; - WRITE_ONCE(item->prog, link->link.prog); - } -} - /** - * __cgroup_bpf_replace() - Replace link's program and propagate the change - * to descendants - * @cgrp: The cgroup which descendants to traverse - * @link: A link for which to replace BPF program - * @type: Type of attach operation - * - * Must be called with cgroup_mutex held. - */ -static int __cgroup_bpf_replace(struct cgroup *cgrp, - struct bpf_cgroup_link *link, - struct bpf_prog *new_prog) -{ - struct list_head *progs = &cgrp->bpf.progs[link->type]; - struct bpf_prog *old_prog; - struct bpf_prog_list *pl; - bool found = false; - - if (link->link.prog->type != new_prog->type) - return -EINVAL; - - list_for_each_entry(pl, progs, node) { - if (pl->link == link) { - found = true; - break; - } - } - if (!found) - return -ENOENT; - - old_prog = xchg(&link->link.prog, new_prog); - replace_effective_prog(cgrp, link->type, link); - bpf_prog_put(old_prog); - return 0; -} - -static int cgroup_bpf_replace(struct bpf_link *link, struct bpf_prog *new_prog, - struct bpf_prog *old_prog) -{ - struct bpf_cgroup_link *cg_link; - int ret; - - cg_link = container_of(link, struct bpf_cgroup_link, link); - - mutex_lock(&cgroup_mutex); - /* link might have been auto-released by dying cgroup, so fail */ - if (!cg_link->cgroup) { - ret = -ENOLINK; - goto out_unlock; - } - if (old_prog && link->prog != old_prog) { - ret = -EPERM; - goto out_unlock; - } - ret = __cgroup_bpf_replace(cg_link->cgroup, cg_link, new_prog); -out_unlock: - mutex_unlock(&cgroup_mutex); - return ret; -} - -static struct bpf_prog_list *find_detach_entry(struct list_head *progs, - struct bpf_prog *prog, - struct bpf_cgroup_link *link, - bool allow_multi) -{ - struct bpf_prog_list *pl; - - if (!allow_multi) { - if (list_empty(progs)) - /* report error when trying to detach and nothing is attached */ - return ERR_PTR(-ENOENT); - - /* to maintain backward compatibility NONE and OVERRIDE cgroups - * allow detaching with invalid FD (prog==NULL) in legacy mode - */ - return list_first_entry(progs, typeof(*pl), node); - } - - if (!prog && !link) - /* to detach MULTI prog the user has to specify valid FD - * of the program or link to be detached - */ - return ERR_PTR(-EINVAL); - - /* find the prog or link and detach it */ - list_for_each_entry(pl, progs, node) { - if (pl->prog == prog && pl->link == link) - return pl; - } - return ERR_PTR(-ENOENT); -} - -/** - * purge_effective_progs() - After compute_effective_progs fails to alloc new - * cgrp->bpf.inactive table we can recover by - * recomputing the array in place. - * - * @cgrp: The cgroup which descendants to travers - * @prog: A program to detach or NULL - * @link: A link to detach or NULL - * @type: Type of detach operation - */ -static void purge_effective_progs(struct cgroup *cgrp, struct bpf_prog *prog, - struct bpf_cgroup_link *link, - enum bpf_attach_type type) -{ - struct cgroup_subsys_state *css; - struct bpf_prog_array *progs; - struct bpf_prog_list *pl; - struct list_head *head; - struct cgroup *cg; - int pos; - - /* recompute effective prog array in place */ - css_for_each_descendant_pre(css, &cgrp->self) { - struct cgroup *desc = container_of(css, struct cgroup, self); - - if (percpu_ref_is_zero(&desc->bpf.refcnt)) - continue; - - /* find position of link or prog in effective progs array */ - for (pos = 0, cg = desc; cg; cg = cgroup_parent(cg)) { - if (pos && !(cg->bpf.flags[type] & BPF_F_ALLOW_MULTI)) - continue; - - head = &cg->bpf.progs[type]; - list_for_each_entry(pl, head, node) { - if (!prog_list_prog(pl)) - continue; - if (pl->prog == prog && pl->link == link) - goto found; - pos++; - } - } - - /* no link or prog match, skip the cgroup of this layer */ - continue; -found: - progs = rcu_dereference_protected( - desc->bpf.effective[type], - lockdep_is_held(&cgroup_mutex)); - - /* Remove the program from the array */ - WARN_ONCE(bpf_prog_array_delete_safe_at(progs, pos), - "Failed to purge a prog from array at index %d", pos); - } -} - -/** - * __cgroup_bpf_detach() - Detach the program or link from a cgroup, and + * __cgroup_bpf_detach() - Detach the program from a cgroup, and * propagate the change to descendants * @cgrp: The cgroup which descendants to traverse * @prog: A program to detach or NULL - * @prog: A link to detach or NULL * @type: Type of detach operation * - * At most one of @prog or @link can be non-NULL. * Must be called with cgroup_mutex held. */ int __cgroup_bpf_detach(struct cgroup *cgrp, struct bpf_prog *prog, - struct bpf_cgroup_link *link, enum bpf_attach_type type) + enum bpf_attach_type type) { struct list_head *progs = &cgrp->bpf.progs[type]; + enum bpf_cgroup_storage_type stype; u32 flags = cgrp->bpf.flags[type]; + struct bpf_prog *old_prog = NULL; struct bpf_prog_list *pl; - struct bpf_prog *old_prog; + int err; - if (prog && link) - /* only one of prog or link can be specified */ - return -EINVAL; - - pl = find_detach_entry(progs, prog, link, flags & BPF_F_ALLOW_MULTI); - if (IS_ERR(pl)) - return PTR_ERR(pl); - - /* mark it deleted, so it's ignored while recomputing effective */ - old_prog = pl->prog; - pl->prog = NULL; - pl->link = NULL; - - if (update_effective_progs(cgrp, type)) { - /* if update effective array failed replace the prog with a dummy prog*/ - pl->prog = old_prog; - pl->link = link; - purge_effective_progs(cgrp, old_prog, link, type); + if (flags & BPF_F_ALLOW_MULTI) { + if (!prog) + /* to detach MULTI prog the user has to specify valid FD + * of the program to be detached + */ + return -EINVAL; + } else { + if (list_empty(progs)) + /* report error when trying to detach and nothing is attached */ + return -ENOENT; } + if (flags & BPF_F_ALLOW_MULTI) { + /* find the prog and detach it */ + list_for_each_entry(pl, progs, node) { + if (pl->prog != prog) + continue; + old_prog = prog; + /* mark it deleted, so it's ignored while + * recomputing effective + */ + pl->prog = NULL; + break; + } + if (!old_prog) + return -ENOENT; + } else { + /* to maintain backward compatibility NONE and OVERRIDE cgroups + * allow detaching with invalid FD (prog==NULL) + */ + pl = list_first_entry(progs, typeof(*pl), node); + old_prog = pl->prog; + pl->prog = NULL; + } + + err = update_effective_progs(cgrp, type); + if (err) + goto cleanup; + /* now can actually delete it from this cgroup list */ list_del(&pl->node); + for_each_cgroup_storage_type(stype) { + bpf_cgroup_storage_unlink(pl->storage[stype]); + bpf_cgroup_storage_free(pl->storage[stype]); + } kfree(pl); if (list_empty(progs)) /* last program was detached, reset flags to zero */ cgrp->bpf.flags[type] = 0; - if (old_prog) - bpf_prog_put(old_prog); + + bpf_prog_put(old_prog); static_branch_dec(&cgroup_bpf_enabled_key); return 0; + +cleanup: + /* and restore back old_prog */ + pl->prog = old_prog; + return err; } /* Must be called with cgroup_mutex held to avoid races. */ @@ -769,7 +506,6 @@ int __cgroup_bpf_query(struct cgroup *cgrp, const union bpf_attr *attr, struct list_head *progs = &cgrp->bpf.progs[type]; u32 flags = cgrp->bpf.flags[type]; struct bpf_prog_array *effective; - struct bpf_prog *prog; int cnt, ret = 0, i; effective = rcu_dereference_protected(cgrp->bpf.effective[type], @@ -800,8 +536,7 @@ int __cgroup_bpf_query(struct cgroup *cgrp, const union bpf_attr *attr, i = 0; list_for_each_entry(pl, progs, node) { - prog = prog_list_prog(pl); - id = prog->aux->id; + id = pl->prog->aux->id; if (copy_to_user(prog_ids + i, &id, sizeof(id))) return -EFAULT; if (++i == cnt) @@ -814,7 +549,6 @@ int __cgroup_bpf_query(struct cgroup *cgrp, const union bpf_attr *attr, int cgroup_bpf_prog_attach(const union bpf_attr *attr, enum bpf_prog_type ptype, struct bpf_prog *prog) { - struct bpf_prog *replace_prog = NULL; struct cgroup *cgrp; int ret; @@ -822,20 +556,8 @@ int cgroup_bpf_prog_attach(const union bpf_attr *attr, if (IS_ERR(cgrp)) return PTR_ERR(cgrp); - if ((attr->attach_flags & BPF_F_ALLOW_MULTI) && - (attr->attach_flags & BPF_F_REPLACE)) { - replace_prog = bpf_prog_get_type(attr->replace_bpf_fd, ptype); - if (IS_ERR(replace_prog)) { - cgroup_put(cgrp); - return PTR_ERR(replace_prog); - } - } - - ret = cgroup_bpf_attach(cgrp, prog, replace_prog, NULL, - attr->attach_type, attr->attach_flags); - - if (replace_prog) - bpf_prog_put(replace_prog); + ret = cgroup_bpf_attach(cgrp, prog, attr->attach_type, + attr->attach_flags); cgroup_put(cgrp); return ret; } @@ -854,7 +576,7 @@ int cgroup_bpf_prog_detach(const union bpf_attr *attr, enum bpf_prog_type ptype) if (IS_ERR(prog)) prog = NULL; - ret = cgroup_bpf_detach(cgrp, prog, attr->attach_type); + ret = cgroup_bpf_detach(cgrp, prog, attr->attach_type, 0); if (prog) bpf_prog_put(prog); @@ -862,141 +584,6 @@ int cgroup_bpf_prog_detach(const union bpf_attr *attr, enum bpf_prog_type ptype) return ret; } -static void bpf_cgroup_link_release(struct bpf_link *link) -{ - struct bpf_cgroup_link *cg_link = - container_of(link, struct bpf_cgroup_link, link); - struct cgroup *cg; - - /* link might have been auto-detached by dying cgroup already, - * in that case our work is done here - */ - if (!cg_link->cgroup) - return; - - mutex_lock(&cgroup_mutex); - - /* re-check cgroup under lock again */ - if (!cg_link->cgroup) { - mutex_unlock(&cgroup_mutex); - return; - } - - WARN_ON(__cgroup_bpf_detach(cg_link->cgroup, NULL, cg_link, - cg_link->type)); - - cg = cg_link->cgroup; - cg_link->cgroup = NULL; - - mutex_unlock(&cgroup_mutex); - - cgroup_put(cg); -} - -static void bpf_cgroup_link_dealloc(struct bpf_link *link) -{ - struct bpf_cgroup_link *cg_link = - container_of(link, struct bpf_cgroup_link, link); - - kfree(cg_link); -} - -static int bpf_cgroup_link_detach(struct bpf_link *link) -{ - bpf_cgroup_link_release(link); - - return 0; -} - -static void bpf_cgroup_link_show_fdinfo(const struct bpf_link *link, - struct seq_file *seq) -{ - struct bpf_cgroup_link *cg_link = - container_of(link, struct bpf_cgroup_link, link); - u64 cg_id = 0; - - mutex_lock(&cgroup_mutex); - if (cg_link->cgroup) - cg_id = cgroup_id(cg_link->cgroup); - mutex_unlock(&cgroup_mutex); - - seq_printf(seq, - "cgroup_id:\t%llu\n" - "attach_type:\t%d\n", - cg_id, - cg_link->type); -} - -static int bpf_cgroup_link_fill_link_info(const struct bpf_link *link, - struct bpf_link_info *info) -{ - struct bpf_cgroup_link *cg_link = - container_of(link, struct bpf_cgroup_link, link); - u64 cg_id = 0; - - mutex_lock(&cgroup_mutex); - if (cg_link->cgroup) - cg_id = cgroup_id(cg_link->cgroup); - mutex_unlock(&cgroup_mutex); - - info->cgroup.cgroup_id = cg_id; - info->cgroup.attach_type = cg_link->type; - return 0; -} - -static const struct bpf_link_ops bpf_cgroup_link_lops = { - .release = bpf_cgroup_link_release, - .dealloc = bpf_cgroup_link_dealloc, - .detach = bpf_cgroup_link_detach, - .update_prog = cgroup_bpf_replace, - .show_fdinfo = bpf_cgroup_link_show_fdinfo, - .fill_link_info = bpf_cgroup_link_fill_link_info, -}; - -int cgroup_bpf_link_attach(const union bpf_attr *attr, struct bpf_prog *prog) -{ - struct bpf_link_primer link_primer; - struct bpf_cgroup_link *link; - struct cgroup *cgrp; - int err; - - if (attr->link_create.flags) - return -EINVAL; - - cgrp = cgroup_get_from_fd(attr->link_create.target_fd); - if (IS_ERR(cgrp)) - return PTR_ERR(cgrp); - - link = kzalloc(sizeof(*link), GFP_USER); - if (!link) { - err = -ENOMEM; - goto out_put_cgroup; - } - bpf_link_init(&link->link, BPF_LINK_TYPE_CGROUP, &bpf_cgroup_link_lops, - prog); - link->cgroup = cgrp; - link->type = attr->link_create.attach_type; - - err = bpf_link_prime(&link->link, &link_primer); - if (err) { - kfree(link); - goto out_put_cgroup; - } - - err = cgroup_bpf_attach(cgrp, NULL, NULL, link, link->type, - BPF_F_ALLOW_MULTI); - if (err) { - bpf_link_cleanup(&link_primer); - goto out_put_cgroup; - } - - return bpf_link_settle(&link_primer); - -out_put_cgroup: - cgroup_put(cgrp); - return err; -} - int cgroup_bpf_prog_query(const union bpf_attr *attr, union bpf_attr __user *uattr) { @@ -1193,21 +780,36 @@ int __cgroup_bpf_check_dev_permission(short dev_type, u32 major, u32 minor, return !allow; } +EXPORT_SYMBOL(__cgroup_bpf_check_dev_permission); static const struct bpf_func_proto * cgroup_base_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { + case BPF_FUNC_map_lookup_elem: + return &bpf_map_lookup_elem_proto; + case BPF_FUNC_map_update_elem: + return &bpf_map_update_elem_proto; + case BPF_FUNC_map_delete_elem: + return &bpf_map_delete_elem_proto; + case BPF_FUNC_map_push_elem: + return &bpf_map_push_elem_proto; + case BPF_FUNC_map_pop_elem: + return &bpf_map_pop_elem_proto; + case BPF_FUNC_map_peek_elem: + return &bpf_map_peek_elem_proto; case BPF_FUNC_get_current_uid_gid: return &bpf_get_current_uid_gid_proto; case BPF_FUNC_get_local_storage: return &bpf_get_local_storage_proto; case BPF_FUNC_get_current_cgroup_id: return &bpf_get_current_cgroup_id_proto; - case BPF_FUNC_perf_event_output: - return &bpf_event_output_data_proto; + case BPF_FUNC_trace_printk: + if (capable(CAP_SYS_ADMIN)) + return bpf_get_trace_printk_proto(); + /* fall through */ default: - return bpf_base_func_proto(func_id); + return NULL; } } @@ -1261,13 +863,16 @@ const struct bpf_verifier_ops cg_dev_verifier_ops = { * @head: sysctl table header * @table: sysctl table * @write: sysctl is being read (= 0) or written (= 1) - * @buf: pointer to buffer (in and out) + * @buf: pointer to buffer passed by user space * @pcount: value-result argument: value is size of buffer pointed to by @buf, * result is size of @new_buf if program set new value, initial value * otherwise * @ppos: value-result argument: value is position at which read from or write * to sysctl is happening, result is new position if program overrode it, * initial value otherwise + * @new_buf: pointer to pointer to new buffer that will be allocated if program + * overrides new value provided by user space on sysctl write + * NOTE: it's caller responsibility to free *new_buf if it was set * @type: type of program to be executed * * Program is run when sysctl is being accessed, either read or written, and @@ -1278,7 +883,8 @@ const struct bpf_verifier_ops cg_dev_verifier_ops = { */ int __cgroup_bpf_run_filter_sysctl(struct ctl_table_header *head, struct ctl_table *table, int write, - char **buf, size_t *pcount, loff_t *ppos, + void __user *buf, size_t *pcount, + loff_t *ppos, void **new_buf, enum bpf_attach_type type) { struct bpf_sysctl_kern ctx = { @@ -1293,28 +899,36 @@ int __cgroup_bpf_run_filter_sysctl(struct ctl_table_header *head, .new_updated = 0, }; struct cgroup *cgrp; - loff_t pos = 0; int ret; ctx.cur_val = kmalloc_track_caller(ctx.cur_len, GFP_KERNEL); - if (!ctx.cur_val || - table->proc_handler(table, 0, ctx.cur_val, &ctx.cur_len, &pos)) { + if (ctx.cur_val) { + mm_segment_t old_fs; + loff_t pos = 0; + + old_fs = get_fs(); + set_fs(KERNEL_DS); + if (table->proc_handler(table, 0, (void __user *)ctx.cur_val, + &ctx.cur_len, &pos)) { + /* Let BPF program decide how to proceed. */ + ctx.cur_len = 0; + } + set_fs(old_fs); + } else { /* Let BPF program decide how to proceed. */ ctx.cur_len = 0; } - if (write && *buf && *pcount) { + if (write && buf && *pcount) { /* BPF program should be able to override new value with a * buffer bigger than provided by user. */ ctx.new_val = kmalloc_track_caller(PAGE_SIZE, GFP_KERNEL); ctx.new_len = min_t(size_t, PAGE_SIZE, *pcount); - if (ctx.new_val) { - memcpy(ctx.new_val, *buf, ctx.new_len); - } else { + if (!ctx.new_val || + copy_from_user(ctx.new_val, buf, ctx.new_len)) /* Let BPF program decide how to proceed. */ ctx.new_len = 0; - } } rcu_read_lock(); @@ -1325,8 +939,7 @@ int __cgroup_bpf_run_filter_sysctl(struct ctl_table_header *head, kfree(ctx.cur_val); if (ret == 1 && ctx.new_updated) { - kfree(*buf); - *buf = ctx.new_val; + *new_buf = ctx.new_val; *pcount = ctx.new_len; } else { kfree(ctx.new_val); @@ -1334,6 +947,7 @@ int __cgroup_bpf_run_filter_sysctl(struct ctl_table_header *head, return ret == 1 ? 0 : -EPERM; } +EXPORT_SYMBOL(__cgroup_bpf_run_filter_sysctl); #ifdef CONFIG_NET static bool __cgroup_bpf_prog_array_is_empty(struct cgroup *cgrp, @@ -1452,6 +1066,7 @@ out: sockopt_free_buf(&ctx); return ret; } +EXPORT_SYMBOL(__cgroup_bpf_run_filter_setsockopt); int __cgroup_bpf_run_filter_getsockopt(struct sock *sk, int level, int optname, char __user *optval, @@ -1546,6 +1161,7 @@ out: sockopt_free_buf(&ctx); return ret; } +EXPORT_SYMBOL(__cgroup_bpf_run_filter_getsockopt); #endif static ssize_t sysctl_cpy_dir(const struct ctl_dir *dir, char **bufp, @@ -1855,7 +1471,7 @@ static bool cg_sockopt_is_valid_access(int off, int size, return prog->expected_attach_type == BPF_CGROUP_GETSOCKOPT; case offsetof(struct bpf_sockopt, optname): - fallthrough; + /* fallthrough */ case offsetof(struct bpf_sockopt, level): if (size != size_default) return false; diff --git a/kernel/bpf/core.c b/kernel/bpf/core.c index 7049d31888ea..705424f029f3 100644 --- a/kernel/bpf/core.c +++ b/kernel/bpf/core.c @@ -30,8 +30,6 @@ #include #include #include -#include -#include #include #include @@ -87,7 +85,7 @@ struct bpf_prog *bpf_prog_alloc_no_stats(unsigned int size, gfp_t gfp_extra_flag struct bpf_prog *fp; size = round_up(size, PAGE_SIZE); - fp = __vmalloc(size, gfp_flags); + fp = __vmalloc(size, gfp_flags, PAGE_KERNEL); if (fp == NULL) return NULL; @@ -102,9 +100,7 @@ struct bpf_prog *bpf_prog_alloc_no_stats(unsigned int size, gfp_t gfp_extra_flag fp->aux->prog = fp; fp->jit_requested = ebpf_jit_enabled(); - INIT_LIST_HEAD_RCU(&fp->aux->ksym.lnode); - mutex_init(&fp->aux->used_maps_mutex); - mutex_init(&fp->aux->dst_mutex); + INIT_LIST_HEAD_RCU(&fp->aux->ksym_lnode); return fp; } @@ -229,6 +225,8 @@ struct bpf_prog *bpf_prog_realloc(struct bpf_prog *fp_old, unsigned int size, u32 pages, delta; int ret; + BUG_ON(fp_old == NULL); + size = round_up(size, PAGE_SIZE); pages = size / PAGE_SIZE; if (pages <= fp_old->pages) @@ -239,7 +237,7 @@ struct bpf_prog *bpf_prog_realloc(struct bpf_prog *fp_old, unsigned int size, if (ret) return NULL; - fp = __vmalloc(size, gfp_flags); + fp = __vmalloc(size, gfp_flags, PAGE_KERNEL); if (fp == NULL) { __bpf_prog_uncharge(fp_old->aux->user, delta); } else { @@ -260,10 +258,7 @@ struct bpf_prog *bpf_prog_realloc(struct bpf_prog *fp_old, unsigned int size, void __bpf_prog_free(struct bpf_prog *fp) { if (fp->aux) { - mutex_destroy(&fp->aux->used_maps_mutex); - mutex_destroy(&fp->aux->dst_mutex); free_percpu(fp->aux->stats); - kfree(fp->aux->poke_tab); kfree(fp->aux); } vfree(fp); @@ -271,10 +266,10 @@ void __bpf_prog_free(struct bpf_prog *fp) int bpf_prog_calc_tag(struct bpf_prog *fp) { - const u32 bits_offset = SHA1_BLOCK_SIZE - sizeof(__be64); + const u32 bits_offset = SHA_MESSAGE_BYTES - sizeof(__be64); u32 raw_size = bpf_prog_tag_scratch_size(fp); - u32 digest[SHA1_DIGEST_WORDS]; - u32 ws[SHA1_WORKSPACE_WORDS]; + u32 digest[SHA_DIGEST_WORDS]; + u32 ws[SHA_WORKSPACE_WORDS]; u32 i, bsize, psize, blocks; struct bpf_insn *dst; bool was_ld_map; @@ -286,7 +281,7 @@ int bpf_prog_calc_tag(struct bpf_prog *fp) if (!raw) return -ENOMEM; - sha1_init(digest); + sha_init(digest); memset(ws, 0, sizeof(ws)); /* We need to take out the map fd for the digest calculation @@ -317,8 +312,8 @@ int bpf_prog_calc_tag(struct bpf_prog *fp) memset(&raw[psize], 0, raw_size - psize); raw[psize++] = 0x80; - bsize = round_up(psize, SHA1_BLOCK_SIZE); - blocks = bsize / SHA1_BLOCK_SIZE; + bsize = round_up(psize, SHA_MESSAGE_BYTES); + blocks = bsize / SHA_MESSAGE_BYTES; todo = raw; if (bsize - psize >= sizeof(__be64)) { bits = (__be64 *)(todo + bsize - sizeof(__be64)); @@ -329,12 +324,12 @@ int bpf_prog_calc_tag(struct bpf_prog *fp) *bits = cpu_to_be64((psize - 1) << 3); while (blocks--) { - sha1_transform(digest, todo, ws); - todo += SHA1_BLOCK_SIZE; + sha_transform(digest, todo, ws); + todo += SHA_MESSAGE_BYTES; } result = (__force __be32 *)digest; - for (i = 0; i < SHA1_DIGEST_WORDS; i++) + for (i = 0; i < SHA_DIGEST_WORDS; i++) result[i] = cpu_to_be32(digest[i]); memcpy(fp->tag, result, sizeof(fp->tag)); @@ -531,28 +526,28 @@ void bpf_prog_kallsyms_del_all(struct bpf_prog *fp) #ifdef CONFIG_BPF_JIT /* All BPF JIT sysctl knobs here. */ -int bpf_jit_enable __read_mostly = IS_BUILTIN(CONFIG_BPF_JIT_DEFAULT_ON); -int bpf_jit_kallsyms __read_mostly = IS_BUILTIN(CONFIG_BPF_JIT_DEFAULT_ON); +int bpf_jit_enable __read_mostly = IS_BUILTIN(CONFIG_BPF_JIT_ALWAYS_ON); int bpf_jit_harden __read_mostly; +int bpf_jit_kallsyms __read_mostly; long bpf_jit_limit __read_mostly; long bpf_jit_limit_max __read_mostly; -static void -bpf_prog_ksym_set_addr(struct bpf_prog *prog) +static __always_inline void +bpf_get_prog_addr_region(const struct bpf_prog *prog, + unsigned long *symbol_start, + unsigned long *symbol_end) { const struct bpf_binary_header *hdr = bpf_jit_binary_hdr(prog); unsigned long addr = (unsigned long)hdr; WARN_ON_ONCE(!bpf_prog_ebpf_jited(prog)); - prog->aux->ksym.start = (unsigned long) prog->bpf_func; - prog->aux->ksym.end = addr + hdr->pages * PAGE_SIZE; + *symbol_start = addr; + *symbol_end = addr + hdr->pages * PAGE_SIZE; } -static void -bpf_prog_ksym_set_name(struct bpf_prog *prog) +void bpf_get_prog_name(const struct bpf_prog *prog, char *sym) { - char *sym = prog->aux->ksym.name; const char *end = sym + KSYM_NAME_LEN; const struct btf_type *type; const char *func_name; @@ -586,31 +581,36 @@ bpf_prog_ksym_set_name(struct bpf_prog *prog) *sym = 0; } -static unsigned long bpf_get_ksym_start(struct latch_tree_node *n) +static __always_inline unsigned long +bpf_get_prog_addr_start(struct latch_tree_node *n) { - return container_of(n, struct bpf_ksym, tnode)->start; + unsigned long symbol_start, symbol_end; + const struct bpf_prog_aux *aux; + + aux = container_of(n, struct bpf_prog_aux, ksym_tnode); + bpf_get_prog_addr_region(aux->prog, &symbol_start, &symbol_end); + + return symbol_start; } static __always_inline bool bpf_tree_less(struct latch_tree_node *a, struct latch_tree_node *b) { - return bpf_get_ksym_start(a) < bpf_get_ksym_start(b); + return bpf_get_prog_addr_start(a) < bpf_get_prog_addr_start(b); } static __always_inline int bpf_tree_comp(void *key, struct latch_tree_node *n) { unsigned long val = (unsigned long)key; - const struct bpf_ksym *ksym; + unsigned long symbol_start, symbol_end; + const struct bpf_prog_aux *aux; - ksym = container_of(n, struct bpf_ksym, tnode); + aux = container_of(n, struct bpf_prog_aux, ksym_tnode); + bpf_get_prog_addr_region(aux->prog, &symbol_start, &symbol_end); - if (val < ksym->start) + if (val < symbol_start) return -1; - /* Ensure that we detect return addresses as part of the program, when - * the final instruction is a call for a program part of the stack - * trace. Therefore, do val > ksym->end instead of val >= ksym->end. - */ - if (val > ksym->end) + if (val >= symbol_end) return 1; return 0; @@ -625,29 +625,20 @@ static DEFINE_SPINLOCK(bpf_lock); static LIST_HEAD(bpf_kallsyms); static struct latch_tree_root bpf_tree __cacheline_aligned; -void bpf_ksym_add(struct bpf_ksym *ksym) +static void bpf_prog_ksym_node_add(struct bpf_prog_aux *aux) { - spin_lock_bh(&bpf_lock); - WARN_ON_ONCE(!list_empty(&ksym->lnode)); - list_add_tail_rcu(&ksym->lnode, &bpf_kallsyms); - latch_tree_insert(&ksym->tnode, &bpf_tree, &bpf_tree_ops); - spin_unlock_bh(&bpf_lock); + WARN_ON_ONCE(!list_empty(&aux->ksym_lnode)); + list_add_tail_rcu(&aux->ksym_lnode, &bpf_kallsyms); + latch_tree_insert(&aux->ksym_tnode, &bpf_tree, &bpf_tree_ops); } -static void __bpf_ksym_del(struct bpf_ksym *ksym) +static void bpf_prog_ksym_node_del(struct bpf_prog_aux *aux) { - if (list_empty(&ksym->lnode)) + if (list_empty(&aux->ksym_lnode)) return; - latch_tree_erase(&ksym->tnode, &bpf_tree, &bpf_tree_ops); - list_del_rcu(&ksym->lnode); -} - -void bpf_ksym_del(struct bpf_ksym *ksym) -{ - spin_lock_bh(&bpf_lock); - __bpf_ksym_del(ksym); - spin_unlock_bh(&bpf_lock); + latch_tree_erase(&aux->ksym_tnode, &bpf_tree, &bpf_tree_ops); + list_del_rcu(&aux->ksym_lnode); } static bool bpf_prog_kallsyms_candidate(const struct bpf_prog *fp) @@ -657,21 +648,19 @@ static bool bpf_prog_kallsyms_candidate(const struct bpf_prog *fp) static bool bpf_prog_kallsyms_verify_off(const struct bpf_prog *fp) { - return list_empty(&fp->aux->ksym.lnode) || - fp->aux->ksym.lnode.prev == LIST_POISON2; + return list_empty(&fp->aux->ksym_lnode) || + fp->aux->ksym_lnode.prev == LIST_POISON2; } void bpf_prog_kallsyms_add(struct bpf_prog *fp) { if (!bpf_prog_kallsyms_candidate(fp) || - !bpf_capable()) + !capable(CAP_SYS_ADMIN)) return; - bpf_prog_ksym_set_addr(fp); - bpf_prog_ksym_set_name(fp); - fp->aux->ksym.prog = true; - - bpf_ksym_add(&fp->aux->ksym); + spin_lock_bh(&bpf_lock); + bpf_prog_ksym_node_add(fp->aux); + spin_unlock_bh(&bpf_lock); } void bpf_prog_kallsyms_del(struct bpf_prog *fp) @@ -679,30 +668,36 @@ void bpf_prog_kallsyms_del(struct bpf_prog *fp) if (!bpf_prog_kallsyms_candidate(fp)) return; - bpf_ksym_del(&fp->aux->ksym); + spin_lock_bh(&bpf_lock); + bpf_prog_ksym_node_del(fp->aux); + spin_unlock_bh(&bpf_lock); } -static struct bpf_ksym *bpf_ksym_find(unsigned long addr) +static struct bpf_prog *bpf_prog_kallsyms_find(unsigned long addr) { struct latch_tree_node *n; + if (!bpf_jit_kallsyms_enabled()) + return NULL; + n = latch_tree_find((void *)addr, &bpf_tree, &bpf_tree_ops); - return n ? container_of(n, struct bpf_ksym, tnode) : NULL; + return n ? + container_of(n, struct bpf_prog_aux, ksym_tnode)->prog : + NULL; } const char *__bpf_address_lookup(unsigned long addr, unsigned long *size, unsigned long *off, char *sym) { - struct bpf_ksym *ksym; + unsigned long symbol_start, symbol_end; + struct bpf_prog *prog; char *ret = NULL; rcu_read_lock(); - ksym = bpf_ksym_find(addr); - if (ksym) { - unsigned long symbol_start = ksym->start; - unsigned long symbol_end = ksym->end; - - strncpy(sym, ksym->name, KSYM_NAME_LEN); + prog = bpf_prog_kallsyms_find(addr); + if (prog) { + bpf_get_prog_addr_region(prog, &symbol_start, &symbol_end); + bpf_get_prog_name(prog, sym); ret = sym; if (size) @@ -720,43 +715,16 @@ bool is_bpf_text_address(unsigned long addr) bool ret; rcu_read_lock(); - ret = bpf_ksym_find(addr) != NULL; + ret = bpf_prog_kallsyms_find(addr) != NULL; rcu_read_unlock(); return ret; } -static struct bpf_prog *bpf_prog_ksym_find(unsigned long addr) -{ - struct bpf_ksym *ksym = bpf_ksym_find(addr); - - return ksym && ksym->prog ? - container_of(ksym, struct bpf_prog_aux, ksym)->prog : - NULL; -} - -const struct exception_table_entry *search_bpf_extables(unsigned long addr) -{ - const struct exception_table_entry *e = NULL; - struct bpf_prog *prog; - - rcu_read_lock(); - prog = bpf_prog_ksym_find(addr); - if (!prog) - goto out; - if (!prog->aux->num_exentries) - goto out; - - e = search_extable(prog->aux->extable, prog->aux->num_exentries, addr); -out: - rcu_read_unlock(); - return e; -} - int bpf_get_kallsym(unsigned int symnum, unsigned long *value, char *type, char *sym) { - struct bpf_ksym *ksym; + struct bpf_prog_aux *aux; unsigned int it = 0; int ret = -ERANGE; @@ -764,13 +732,13 @@ int bpf_get_kallsym(unsigned int symnum, unsigned long *value, char *type, return ret; rcu_read_lock(); - list_for_each_entry_rcu(ksym, &bpf_kallsyms, lnode) { + list_for_each_entry_rcu(aux, &bpf_kallsyms, ksym_lnode) { if (it++ != symnum) continue; - strncpy(sym, ksym->name, KSYM_NAME_LEN); + bpf_get_prog_name(aux->prog, sym); - *value = ksym->start; + *value = (unsigned long)aux->prog->bpf_func; *type = BPF_SYM_ELF_TYPE; ret = 0; @@ -781,40 +749,6 @@ int bpf_get_kallsym(unsigned int symnum, unsigned long *value, char *type, return ret; } -int bpf_jit_add_poke_descriptor(struct bpf_prog *prog, - struct bpf_jit_poke_descriptor *poke) -{ - struct bpf_jit_poke_descriptor *tab = prog->aux->poke_tab; - static const u32 poke_tab_max = 1024; - u32 slot = prog->aux->size_poke_tab; - u32 size = slot + 1; - - if (size > poke_tab_max) - return -ENOSPC; - if (poke->tailcall_target || poke->tailcall_target_stable || - poke->tailcall_bypass || poke->adj_off || poke->bypass_addr) - return -EINVAL; - - switch (poke->reason) { - case BPF_POKE_REASON_TAIL_CALL: - if (!poke->tail_call.map) - return -EINVAL; - break; - default: - return -EINVAL; - } - - tab = krealloc(tab, size * sizeof(*poke), GFP_KERNEL); - if (!tab) - return -ENOMEM; - - memcpy(&tab[slot], poke, sizeof(*poke)); - prog->aux->size_poke_tab = size; - prog->aux->poke_tab = tab; - - return slot; -} - static atomic_long_t bpf_jit_current; /* Can be overridden by an arch's JIT compiler if it has a custom, @@ -840,11 +774,11 @@ static int __init bpf_jit_charge_init(void) } pure_initcall(bpf_jit_charge_init); -int bpf_jit_charge_modmem(u32 pages) +static int bpf_jit_charge_modmem(u32 pages) { if (atomic_long_add_return(pages, &bpf_jit_current) > (bpf_jit_limit >> PAGE_SHIFT)) { - if (!bpf_capable()) { + if (!capable(CAP_SYS_ADMIN)) { atomic_long_sub(pages, &bpf_jit_current); return -EPERM; } @@ -853,7 +787,7 @@ int bpf_jit_charge_modmem(u32 pages) return 0; } -void bpf_jit_uncharge_modmem(u32 pages) +static void bpf_jit_uncharge_modmem(u32 pages) { atomic_long_sub(pages, &bpf_jit_current); } @@ -884,9 +818,6 @@ bpf_jit_binary_alloc(unsigned int proglen, u8 **image_ptr, struct bpf_binary_header *hdr; u32 size, hole, start, pages; - WARN_ON_ONCE(!is_power_of_2(alignment) || - alignment > BPF_IMAGE_ALIGNMENT); - /* Most of BPF filters are really small, but if some of them * fill a page, allow at least 128 extra bytes to insert a * random section of illegal instructions. @@ -1118,7 +1049,7 @@ static struct bpf_prog *bpf_prog_clone_create(struct bpf_prog *fp_other, gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO | gfp_extra_flags; struct bpf_prog *fp; - fp = __vmalloc(fp_other->pages * PAGE_SIZE, gfp_flags); + fp = __vmalloc(fp_other->pages * PAGE_SIZE, gfp_flags, PAGE_KERNEL); if (fp != NULL) { /* aux->prog still points to the fp_other one, so * when promoting the clone to the real program, @@ -1379,12 +1310,6 @@ bool bpf_opcode_in_insntable(u8 code) } #ifndef CONFIG_BPF_JIT_ALWAYS_ON -u64 __weak bpf_probe_read_kernel(void *dst, u32 size, const void *unsafe_ptr) -{ - memset(dst, 0, size); - return -EFAULT; -} - /** * __bpf_prog_run - run eBPF program on a given context * @regs: is the array of MAX_BPF_EXT_REG eBPF pseudo-registers @@ -1405,10 +1330,6 @@ static u64 ___bpf_prog_run(u64 *regs, const struct bpf_insn *insn, u64 *stack) [BPF_JMP | BPF_CALL_ARGS] = &&JMP_CALL_ARGS, [BPF_JMP | BPF_TAIL_CALL] = &&JMP_TAIL_CALL, [BPF_ST | BPF_NOSPEC] = &&ST_NOSPEC, - [BPF_LDX | BPF_PROBE_MEM | BPF_B] = &&LDX_PROBE_MEM_B, - [BPF_LDX | BPF_PROBE_MEM | BPF_H] = &&LDX_PROBE_MEM_H, - [BPF_LDX | BPF_PROBE_MEM | BPF_W] = &&LDX_PROBE_MEM_W, - [BPF_LDX | BPF_PROBE_MEM | BPF_DW] = &&LDX_PROBE_MEM_DW, }; #undef BPF_INSN_3_LBL #undef BPF_INSN_2_LBL @@ -1598,7 +1519,7 @@ select_insn: /* ARG1 at this point is guaranteed to point to CTX from * the verifier side due to the fact that the tail call is - * handled like a helper, that is, bpf_tail_call_proto, + * handeled like a helper, that is, bpf_tail_call_proto, * where arg1_type is ARG_PTR_TO_CTX. */ insn = prog->insnsi; @@ -1671,11 +1592,6 @@ out: CONT; \ LDX_MEM_##SIZEOP: \ DST = *(SIZE *)(unsigned long) (SRC + insn->off); \ - CONT; \ - LDX_PROBE_MEM_##SIZEOP: \ - bpf_probe_read_kernel(&DST, sizeof(SIZE), \ - (const void *)(long) (SRC + insn->off)); \ - DST = *((SIZE *)&DST); \ CONT; LDST(B, u8) @@ -1683,7 +1599,6 @@ out: LDST(W, u32) LDST(DW, u64) #undef LDST - STX_XADD_W: /* lock xadd *(u32 *)(dst_reg + off16) += src_reg */ atomic_add((u32) SRC, (atomic_t *)(unsigned long) (DST + insn->off)); @@ -1791,34 +1706,28 @@ static unsigned int __bpf_prog_ret0_warn(const void *ctx, bool bpf_prog_array_compatible(struct bpf_array *array, const struct bpf_prog *fp) { - bool ret; - if (fp->kprobe_override) return false; - spin_lock(&array->aux->owner.lock); - - if (!array->aux->owner.type) { + if (!array->owner_prog_type) { /* There's no owner yet where we could check for * compatibility. */ - array->aux->owner.type = fp->type; - array->aux->owner.jited = fp->jited; - ret = true; - } else { - ret = array->aux->owner.type == fp->type && - array->aux->owner.jited == fp->jited; + array->owner_prog_type = fp->type; + array->owner_jited = fp->jited; + + return true; } - spin_unlock(&array->aux->owner.lock); - return ret; + + return array->owner_prog_type == fp->type && + array->owner_jited == fp->jited; } static int bpf_check_tail_call(const struct bpf_prog *fp) { struct bpf_prog_aux *aux = fp->aux; - int i, ret = 0; + int i; - mutex_lock(&aux->used_maps_mutex); for (i = 0; i < aux->used_map_cnt; i++) { struct bpf_map *map = aux->used_maps[i]; struct bpf_array *array; @@ -1827,15 +1736,11 @@ static int bpf_check_tail_call(const struct bpf_prog *fp) continue; array = container_of(map, struct bpf_array, map); - if (!bpf_prog_array_compatible(array, fp)) { - ret = -EINVAL; - goto out; - } + if (!bpf_prog_array_compatible(array, fp)) + return -EINVAL; } -out: - mutex_unlock(&aux->used_maps_mutex); - return ret; + return 0; } static void bpf_prog_select_func(struct bpf_prog *fp) @@ -2032,61 +1937,6 @@ void bpf_prog_array_delete_safe(struct bpf_prog_array *array, } } -/** - * bpf_prog_array_delete_safe_at() - Replaces the program at the given - * index into the program array with - * a dummy no-op program. - * @array: a bpf_prog_array - * @index: the index of the program to replace - * - * Skips over dummy programs, by not counting them, when calculating - * the position of the program to replace. - * - * Return: - * * 0 - Success - * * -EINVAL - Invalid index value. Must be a non-negative integer. - * * -ENOENT - Index out of range - */ -int bpf_prog_array_delete_safe_at(struct bpf_prog_array *array, int index) -{ - return bpf_prog_array_update_at(array, index, &dummy_bpf_prog.prog); -} - -/** - * bpf_prog_array_update_at() - Updates the program at the given index - * into the program array. - * @array: a bpf_prog_array - * @index: the index of the program to update - * @prog: the program to insert into the array - * - * Skips over dummy programs, by not counting them, when calculating - * the position of the program to update. - * - * Return: - * * 0 - Success - * * -EINVAL - Invalid index value. Must be a non-negative integer. - * * -ENOENT - Index out of range - */ -int bpf_prog_array_update_at(struct bpf_prog_array *array, int index, - struct bpf_prog *prog) -{ - struct bpf_prog_array_item *item; - - if (unlikely(index < 0)) - return -EINVAL; - - for (item = array->items; item->prog; item++) { - if (item->prog == &dummy_bpf_prog.prog) - continue; - if (!index) { - WRITE_ONCE(item->prog, prog); - return 0; - } - index--; - } - return -ENOENT; -} - int bpf_prog_array_copy(struct bpf_prog_array *old_array, struct bpf_prog *exclude_prog, struct bpf_prog *include_prog, @@ -2171,49 +2021,20 @@ int bpf_prog_array_copy_info(struct bpf_prog_array *array, : 0; } -void __bpf_free_used_maps(struct bpf_prog_aux *aux, - struct bpf_map **used_maps, u32 len) -{ - struct bpf_map *map; - u32 i; - - for (i = 0; i < len; i++) { - map = used_maps[i]; - if (map->ops->map_poke_untrack) - map->ops->map_poke_untrack(map, aux); - bpf_map_put(map); - } -} - -static void bpf_free_used_maps(struct bpf_prog_aux *aux) -{ - __bpf_free_used_maps(aux, aux->used_maps, aux->used_map_cnt); - kfree(aux->used_maps); -} - static void bpf_prog_free_deferred(struct work_struct *work) { struct bpf_prog_aux *aux; int i; aux = container_of(work, struct bpf_prog_aux, work); - bpf_free_used_maps(aux); if (bpf_prog_is_dev_bound(aux)) bpf_prog_offload_destroy(aux->prog); #ifdef CONFIG_PERF_EVENTS if (aux->prog->has_callchain_buf) put_callchain_buffers(); #endif - if (aux->dst_trampoline) - bpf_trampoline_put(aux->dst_trampoline); - for (i = 0; i < aux->func_cnt; i++) { - /* We can just unlink the subprog poke descriptor table as - * it was originally linked to the main program and is also - * released along with it. - */ - aux->func[i]->aux->poke_tab = NULL; + for (i = 0; i < aux->func_cnt; i++) bpf_jit_free(aux->func[i]); - } if (aux->func_cnt) { kfree(aux->func); bpf_prog_unlock_free(aux->prog); @@ -2227,8 +2048,6 @@ void bpf_prog_free(struct bpf_prog *fp) { struct bpf_prog_aux *aux = fp->aux; - if (aux->dst_prog) - bpf_prog_put(aux->dst_prog); INIT_WORK(&aux->work, bpf_prog_free_deferred); schedule_work(&aux->work); } @@ -2260,11 +2079,6 @@ BPF_CALL_0(bpf_user_rnd_u32) return res; } -BPF_CALL_0(bpf_get_raw_cpu_id) -{ - return raw_smp_processor_id(); -} - /* Weak definitions of helper functions in case we don't have bpf syscall. */ const struct bpf_func_proto bpf_map_lookup_elem_proto __weak; const struct bpf_func_proto bpf_map_update_elem_proto __weak; @@ -2274,7 +2088,6 @@ const struct bpf_func_proto bpf_map_pop_elem_proto __weak; const struct bpf_func_proto bpf_map_peek_elem_proto __weak; const struct bpf_func_proto bpf_spin_lock_proto __weak; const struct bpf_func_proto bpf_spin_unlock_proto __weak; -const struct bpf_func_proto bpf_jiffies64_proto __weak; const struct bpf_func_proto bpf_get_prandom_u32_proto __weak; const struct bpf_func_proto bpf_get_smp_processor_id_proto __weak; @@ -2286,11 +2099,7 @@ const struct bpf_func_proto bpf_get_current_pid_tgid_proto __weak; const struct bpf_func_proto bpf_get_current_uid_gid_proto __weak; const struct bpf_func_proto bpf_get_current_comm_proto __weak; const struct bpf_func_proto bpf_get_current_cgroup_id_proto __weak; -const struct bpf_func_proto bpf_get_current_ancestor_cgroup_id_proto __weak; const struct bpf_func_proto bpf_get_local_storage_proto __weak; -const struct bpf_func_proto bpf_get_ns_current_pid_tgid_proto __weak; -const struct bpf_func_proto bpf_snprintf_btf_proto __weak; -const struct bpf_func_proto bpf_seq_printf_btf_proto __weak; const struct bpf_func_proto * __weak bpf_get_trace_printk_proto(void) { @@ -2354,12 +2163,6 @@ int __weak skb_copy_bits(const struct sk_buff *skb, int offset, void *to, return -EFAULT; } -int __weak bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t, - void *addr1, void *addr2) -{ - return -ENOTSUPP; -} - DEFINE_STATIC_KEY_FALSE(bpf_stats_enabled_key); EXPORT_SYMBOL(bpf_stats_enabled_key); diff --git a/kernel/bpf/cpumap.c b/kernel/bpf/cpumap.c index d94e76fed316..19be747f4e5a 100644 --- a/kernel/bpf/cpumap.c +++ b/kernel/bpf/cpumap.c @@ -52,6 +52,7 @@ struct xdp_bulk_queue { struct bpf_cpu_map_entry { u32 cpu; /* kthread CPU and map index */ int map_id; /* Back reference to map */ + u32 qsize; /* Queue size placeholder for map lookup */ /* XDP can run multiple RX-ring queues, need __percpu enqueue store */ struct xdp_bulk_queue __percpu *bulkq; @@ -61,40 +62,34 @@ struct bpf_cpu_map_entry { /* Queue with potential multi-producers, and single-consumer kthread */ struct ptr_ring *queue; struct task_struct *kthread; - - struct bpf_cpumap_val value; - struct bpf_prog *prog; + struct work_struct kthread_stop_wq; atomic_t refcnt; /* Control when this struct can be free'ed */ struct rcu_head rcu; - - struct work_struct kthread_stop_wq; }; struct bpf_cpu_map { struct bpf_map map; /* Below members specific for map type */ struct bpf_cpu_map_entry **cpu_map; + struct list_head __percpu *flush_list; }; -static DEFINE_PER_CPU(struct list_head, cpu_map_flush_list); +static int bq_flush_to_queue(struct xdp_bulk_queue *bq, bool in_napi_ctx); static struct bpf_map *cpu_map_alloc(union bpf_attr *attr) { - u32 value_size = attr->value_size; struct bpf_cpu_map *cmap; int err = -ENOMEM; + int ret, cpu; u64 cost; - int ret; - if (!bpf_capable()) + if (!capable(CAP_SYS_ADMIN)) return ERR_PTR(-EPERM); /* check sanity of attributes */ if (attr->max_entries == 0 || attr->key_size != 4 || - (value_size != offsetofend(struct bpf_cpumap_val, qsize) && - value_size != offsetofend(struct bpf_cpumap_val, bpf_prog.fd)) || - attr->map_flags & ~BPF_F_NUMA_NODE) + attr->value_size != 4 || attr->map_flags & ~BPF_F_NUMA_NODE) return ERR_PTR(-EINVAL); cmap = kzalloc(sizeof(*cmap), GFP_USER); @@ -111,6 +106,7 @@ static struct bpf_map *cpu_map_alloc(union bpf_attr *attr) /* make sure page count doesn't overflow */ cost = (u64) cmap->map.max_entries * sizeof(struct bpf_cpu_map_entry *); + cost += sizeof(struct list_head) * num_possible_cpus(); /* Notice returns -EPERM on if map size is larger than memlock limit */ ret = bpf_map_charge_init(&cmap->map.memory, cost); @@ -119,14 +115,23 @@ static struct bpf_map *cpu_map_alloc(union bpf_attr *attr) goto free_cmap; } + cmap->flush_list = alloc_percpu(struct list_head); + if (!cmap->flush_list) + goto free_charge; + + for_each_possible_cpu(cpu) + INIT_LIST_HEAD(per_cpu_ptr(cmap->flush_list, cpu)); + /* Alloc array for possible remote "destination" CPUs */ cmap->cpu_map = bpf_map_area_alloc(cmap->map.max_entries * sizeof(struct bpf_cpu_map_entry *), cmap->map.numa_node); if (!cmap->cpu_map) - goto free_charge; + goto free_percpu; return &cmap->map; +free_percpu: + free_percpu(cmap->flush_list); free_charge: bpf_map_charge_finish(&cmap->map.memory); free_cmap: @@ -155,7 +160,8 @@ static void cpu_map_kthread_stop(struct work_struct *work) kthread_stop(rcpu->kthread); } -static struct sk_buff *cpu_map_build_skb(struct xdp_frame *xdpf, +static struct sk_buff *cpu_map_build_skb(struct bpf_cpu_map_entry *rcpu, + struct xdp_frame *xdpf, struct sk_buff *skb) { unsigned int hard_start_headroom; @@ -165,10 +171,25 @@ static struct sk_buff *cpu_map_build_skb(struct xdp_frame *xdpf, /* Part of headroom was reserved to xdpf */ hard_start_headroom = sizeof(struct xdp_frame) + xdpf->headroom; - /* Memory size backing xdp_frame data already have reserved - * room for build_skb to place skb_shared_info in tailroom. + /* build_skb need to place skb_shared_info after SKB end, and + * also want to know the memory "truesize". Thus, need to + * know the memory frame size backing xdp_buff. + * + * XDP was designed to have PAGE_SIZE frames, but this + * assumption is not longer true with ixgbe and i40e. It + * would be preferred to set frame_size to 2048 or 4096 + * depending on the driver. + * frame_size = 2048; + * frame_len = frame_size - sizeof(*xdp_frame); + * + * Instead, with info avail, skb_shared_info in placed after + * packet len. This, unfortunately fakes the truesize. + * Another disadvantage of this approach, the skb_shared_info + * is not at a fixed memory location, with mixed length + * packets, which is bad for cache-line hotness. */ - frame_size = xdpf->frame_sz; + frame_size = SKB_DATA_ALIGN(xdpf->len + hard_start_headroom) + + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); pkt_data_start = xdpf->data - hard_start_headroom; skb = build_skb_around(skb, pkt_data_start, frame_size); @@ -215,8 +236,6 @@ static void __cpu_map_ring_cleanup(struct ptr_ring *ring) static void put_cpu_map_entry(struct bpf_cpu_map_entry *rcpu) { if (atomic_dec_and_test(&rcpu->refcnt)) { - if (rcpu->prog) - bpf_prog_put(rcpu->prog); /* The queue should be empty at this point */ __cpu_map_ring_cleanup(rcpu->queue); ptr_ring_cleanup(rcpu->queue, NULL); @@ -225,62 +244,6 @@ static void put_cpu_map_entry(struct bpf_cpu_map_entry *rcpu) } } -static int cpu_map_bpf_prog_run_xdp(struct bpf_cpu_map_entry *rcpu, - void **frames, int n, - struct xdp_cpumap_stats *stats) -{ - struct xdp_rxq_info rxq = {}; - struct xdp_buff xdp; - int i, nframes = 0; - - if (!rcpu->prog) - return n; - - rcu_read_lock(); - - xdp_set_return_frame_no_direct(); - xdp.rxq = &rxq; - - for (i = 0; i < n; i++) { - struct xdp_frame *xdpf = frames[i]; - u32 act; - int err; - - rxq.dev = xdpf->dev_rx; - rxq.mem = xdpf->mem; - /* TODO: report queue_index to xdp_rxq_info */ - - xdp_convert_frame_to_buff(xdpf, &xdp); - - act = bpf_prog_run_xdp(rcpu->prog, &xdp); - switch (act) { - case XDP_PASS: - err = xdp_update_frame_from_buff(&xdp, xdpf); - if (err < 0) { - xdp_return_frame(xdpf); - stats->drop++; - } else { - frames[nframes++] = xdpf; - stats->pass++; - } - break; - default: - bpf_warn_invalid_xdp_action(act); - fallthrough; - case XDP_DROP: - xdp_return_frame(xdpf); - stats->drop++; - break; - } - } - - xdp_clear_return_frame_no_direct(); - - rcu_read_unlock(); - - return nframes; -} - #define CPUMAP_BATCH 8 static int cpu_map_kthread_run(void *data) @@ -296,12 +259,11 @@ static int cpu_map_kthread_run(void *data) * kthread_stop signal until queue is empty. */ while (!kthread_should_stop() || !__ptr_ring_empty(rcpu->queue)) { - struct xdp_cpumap_stats stats = {}; /* zero stats */ - gfp_t gfp = __GFP_ZERO | GFP_ATOMIC; unsigned int drops = 0, sched = 0; void *frames[CPUMAP_BATCH]; void *skbs[CPUMAP_BATCH]; - int i, n, m, nframes; + gfp_t gfp = __GFP_ZERO | GFP_ATOMIC; + int i, n, m; /* Release CPU reschedule checks */ if (__ptr_ring_empty(rcpu->queue)) { @@ -324,8 +286,8 @@ static int cpu_map_kthread_run(void *data) * kthread CPU pinned. Lockless access to ptr_ring * consume side valid as no-resize allowed of queue. */ - n = __ptr_ring_consume_batched(rcpu->queue, frames, - CPUMAP_BATCH); + n = ptr_ring_consume_batched(rcpu->queue, frames, CPUMAP_BATCH); + for (i = 0; i < n; i++) { void *f = frames[i]; struct page *page = virt_to_page(f); @@ -337,24 +299,20 @@ static int cpu_map_kthread_run(void *data) prefetchw(page); } - /* Support running another XDP prog on this CPU */ - nframes = cpu_map_bpf_prog_run_xdp(rcpu, frames, n, &stats); - if (nframes) { - m = kmem_cache_alloc_bulk(skbuff_head_cache, gfp, nframes, skbs); - if (unlikely(m == 0)) { - for (i = 0; i < nframes; i++) - skbs[i] = NULL; /* effect: xdp_return_frame */ - drops += nframes; - } + m = kmem_cache_alloc_bulk(skbuff_head_cache, gfp, n, skbs); + if (unlikely(m == 0)) { + for (i = 0; i < n; i++) + skbs[i] = NULL; /* effect: xdp_return_frame */ + drops = n; } local_bh_disable(); - for (i = 0; i < nframes; i++) { + for (i = 0; i < n; i++) { struct xdp_frame *xdpf = frames[i]; struct sk_buff *skb = skbs[i]; int ret; - skb = cpu_map_build_skb(xdpf, skb); + skb = cpu_map_build_skb(rcpu, xdpf, skb); if (!skb) { xdp_return_frame(xdpf); continue; @@ -366,7 +324,7 @@ static int cpu_map_kthread_run(void *data) drops++; } /* Feedback loop via tracepoint */ - trace_xdp_cpumap_kthread(rcpu->map_id, n, drops, sched, &stats); + trace_xdp_cpumap_kthread(rcpu->map_id, n, drops, sched); local_bh_enable(); /* resched point, may call do_softirq() */ } @@ -376,38 +334,13 @@ static int cpu_map_kthread_run(void *data) return 0; } -bool cpu_map_prog_allowed(struct bpf_map *map) +static struct bpf_cpu_map_entry *__cpu_map_entry_alloc(u32 qsize, u32 cpu, + int map_id) { - return map->map_type == BPF_MAP_TYPE_CPUMAP && - map->value_size != offsetofend(struct bpf_cpumap_val, qsize); -} - -static int __cpu_map_load_bpf_program(struct bpf_cpu_map_entry *rcpu, int fd) -{ - struct bpf_prog *prog; - - prog = bpf_prog_get_type(fd, BPF_PROG_TYPE_XDP); - if (IS_ERR(prog)) - return PTR_ERR(prog); - - if (prog->expected_attach_type != BPF_XDP_CPUMAP) { - bpf_prog_put(prog); - return -EINVAL; - } - - rcpu->value.bpf_prog.id = prog->aux->id; - rcpu->prog = prog; - - return 0; -} - -static struct bpf_cpu_map_entry * -__cpu_map_entry_alloc(struct bpf_cpumap_val *value, u32 cpu, int map_id) -{ - int numa, err, i, fd = value->bpf_prog.fd; gfp_t gfp = GFP_KERNEL | __GFP_NOWARN; struct bpf_cpu_map_entry *rcpu; struct xdp_bulk_queue *bq; + int numa, err, i; /* Have map->numa_node, but choose node of redirect target CPU */ numa = cpu_to_node(cpu); @@ -432,22 +365,19 @@ __cpu_map_entry_alloc(struct bpf_cpumap_val *value, u32 cpu, int map_id) if (!rcpu->queue) goto free_bulkq; - err = ptr_ring_init(rcpu->queue, value->qsize, gfp); + err = ptr_ring_init(rcpu->queue, qsize, gfp); if (err) goto free_queue; rcpu->cpu = cpu; rcpu->map_id = map_id; - rcpu->value.qsize = value->qsize; - - if (fd > 0 && __cpu_map_load_bpf_program(rcpu, fd)) - goto free_ptr_ring; + rcpu->qsize = qsize; /* Setup kthread */ rcpu->kthread = kthread_create_on_node(cpu_map_kthread_run, rcpu, numa, "cpumap/%d/map:%d", cpu, map_id); if (IS_ERR(rcpu->kthread)) - goto free_prog; + goto free_ptr_ring; get_cpu_map_entry(rcpu); /* 1-refcnt for being in cmap->cpu_map[] */ get_cpu_map_entry(rcpu); /* 1-refcnt for kthread */ @@ -458,9 +388,6 @@ __cpu_map_entry_alloc(struct bpf_cpumap_val *value, u32 cpu, int map_id) return rcpu; -free_prog: - if (rcpu->prog) - bpf_prog_put(rcpu->prog); free_ptr_ring: ptr_ring_cleanup(rcpu->queue, NULL); free_queue: @@ -475,14 +402,22 @@ free_rcu: static void __cpu_map_entry_free(struct rcu_head *rcu) { struct bpf_cpu_map_entry *rcpu; + int cpu; /* This cpu_map_entry have been disconnected from map and one - * RCU grace-period have elapsed. Thus, XDP cannot queue any + * RCU graze-period have elapsed. Thus, XDP cannot queue any * new packets and cannot change/set flush_needed that can * find this entry. */ rcpu = container_of(rcu, struct bpf_cpu_map_entry, rcu); + /* Flush remaining packets in percpu bulkq */ + for_each_online_cpu(cpu) { + struct xdp_bulk_queue *bq = per_cpu_ptr(rcpu->bulkq, cpu); + + /* No concurrent bq_enqueue can run at this point */ + bq_flush_to_queue(bq, false); + } free_percpu(rcpu->bulkq); /* Cannot kthread_stop() here, last put free rcpu resources */ put_cpu_map_entry(rcpu); @@ -504,7 +439,7 @@ static void __cpu_map_entry_free(struct rcu_head *rcu) * percpu bulkq to queue. Due to caller map_delete_elem() disable * preemption, cannot call kthread_stop() to make sure queue is empty. * Instead a work_queue is started for stopping kthread, - * cpu_map_kthread_stop, which waits for an RCU grace period before + * cpu_map_kthread_stop, which waits for an RCU graze period before * stopping kthread, emptying the queue. */ static void __cpu_map_entry_replace(struct bpf_cpu_map *cmap, @@ -537,12 +472,12 @@ static int cpu_map_update_elem(struct bpf_map *map, void *key, void *value, u64 map_flags) { struct bpf_cpu_map *cmap = container_of(map, struct bpf_cpu_map, map); - struct bpf_cpumap_val cpumap_value = {}; struct bpf_cpu_map_entry *rcpu; + /* Array index key correspond to CPU number */ u32 key_cpu = *(u32 *)key; - - memcpy(&cpumap_value, value, map->value_size); + /* Value is the queue size */ + u32 qsize = *(u32 *)value; if (unlikely(map_flags > BPF_EXIST)) return -EINVAL; @@ -550,18 +485,18 @@ static int cpu_map_update_elem(struct bpf_map *map, void *key, void *value, return -E2BIG; if (unlikely(map_flags == BPF_NOEXIST)) return -EEXIST; - if (unlikely(cpumap_value.qsize > 16384)) /* sanity limit on qsize */ + if (unlikely(qsize > 16384)) /* sanity limit on qsize */ return -EOVERFLOW; /* Make sure CPU is a valid possible cpu */ if (key_cpu >= nr_cpumask_bits || !cpu_possible(key_cpu)) return -ENODEV; - if (cpumap_value.qsize == 0) { + if (qsize == 0) { rcpu = NULL; /* Same as deleting */ } else { /* Updating qsize cause re-allocation of bpf_cpu_map_entry */ - rcpu = __cpu_map_entry_alloc(&cpumap_value, key_cpu, map->id); + rcpu = __cpu_map_entry_alloc(qsize, key_cpu, map->id); if (!rcpu) return -ENOMEM; rcpu->cmap = cmap; @@ -575,6 +510,7 @@ static int cpu_map_update_elem(struct bpf_map *map, void *key, void *value, static void cpu_map_free(struct bpf_map *map) { struct bpf_cpu_map *cmap = container_of(map, struct bpf_cpu_map, map); + int cpu; u32 i; /* At this point bpf_prog->aux->refcnt == 0 and this map->refcnt == 0, @@ -589,6 +525,18 @@ static void cpu_map_free(struct bpf_map *map) bpf_clear_redirect_map(map); synchronize_rcu(); + /* To ensure all pending flush operations have completed wait for flush + * list be empty on _all_ cpus. Because the above synchronize_rcu() + * ensures the map is disconnected from the program we can assume no new + * items will be added to the list. + */ + for_each_online_cpu(cpu) { + struct list_head *flush_list = per_cpu_ptr(cmap->flush_list, cpu); + + while (!list_empty(flush_list)) + cond_resched(); + } + /* For cpu_map the remote CPUs can still be using the entries * (struct bpf_cpu_map_entry). */ @@ -599,9 +547,10 @@ static void cpu_map_free(struct bpf_map *map) if (!rcpu) continue; - /* bq flush and cleanup happens after RCU grace-period */ + /* bq flush and cleanup happens after RCU graze-period */ __cpu_map_entry_replace(cmap, i, NULL); /* call_rcu */ } + free_percpu(cmap->flush_list); bpf_map_area_free(cmap->cpu_map); kfree(cmap); } @@ -623,7 +572,7 @@ static void *cpu_map_lookup_elem(struct bpf_map *map, void *key) struct bpf_cpu_map_entry *rcpu = __cpu_map_lookup_elem(map, *(u32 *)key); - return rcpu ? &rcpu->value : NULL; + return rcpu ? &rcpu->qsize : NULL; } static int cpu_map_get_next_key(struct bpf_map *map, void *key, void *next_key) @@ -643,9 +592,7 @@ static int cpu_map_get_next_key(struct bpf_map *map, void *key, void *next_key) return 0; } -static int cpu_map_btf_id; const struct bpf_map_ops cpu_map_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc = cpu_map_alloc, .map_free = cpu_map_free, .map_delete_elem = cpu_map_delete_elem, @@ -653,11 +600,9 @@ const struct bpf_map_ops cpu_map_ops = { .map_lookup_elem = cpu_map_lookup_elem, .map_get_next_key = cpu_map_get_next_key, .map_check_btf = map_check_no_btf, - .map_btf_name = "bpf_cpu_map", - .map_btf_id = &cpu_map_btf_id, }; -static void bq_flush_to_queue(struct xdp_bulk_queue *bq) +static int bq_flush_to_queue(struct xdp_bulk_queue *bq, bool in_napi_ctx) { struct bpf_cpu_map_entry *rcpu = bq->obj; unsigned int processed = 0, drops = 0; @@ -666,7 +611,7 @@ static void bq_flush_to_queue(struct xdp_bulk_queue *bq) int i; if (unlikely(!bq->count)) - return; + return 0; q = rcpu->queue; spin_lock(&q->producer_lock); @@ -678,7 +623,10 @@ static void bq_flush_to_queue(struct xdp_bulk_queue *bq) err = __ptr_ring_produce(q, xdpf); if (err) { drops++; - xdp_return_frame_rx_napi(xdpf); + if (likely(in_napi_ctx)) + xdp_return_frame_rx_napi(xdpf); + else + xdp_return_frame(xdpf); } processed++; } @@ -689,18 +637,19 @@ static void bq_flush_to_queue(struct xdp_bulk_queue *bq) /* Feedback loop via tracepoints */ trace_xdp_cpumap_enqueue(rcpu->map_id, processed, drops, to_cpu); + return 0; } /* Runs under RCU-read-side, plus in softirq under NAPI protection. * Thus, safe percpu variable access. */ -static void bq_enqueue(struct bpf_cpu_map_entry *rcpu, struct xdp_frame *xdpf) +static int bq_enqueue(struct bpf_cpu_map_entry *rcpu, struct xdp_frame *xdpf) { - struct list_head *flush_list = this_cpu_ptr(&cpu_map_flush_list); + struct list_head *flush_list = this_cpu_ptr(rcpu->cmap->flush_list); struct xdp_bulk_queue *bq = this_cpu_ptr(rcpu->bulkq); if (unlikely(bq->count == CPU_MAP_BULK_SIZE)) - bq_flush_to_queue(bq); + bq_flush_to_queue(bq, true); /* Notice, xdp_buff/page MUST be queued here, long enough for * driver to code invoking us to finished, due to driver @@ -715,6 +664,8 @@ static void bq_enqueue(struct bpf_cpu_map_entry *rcpu, struct xdp_frame *xdpf) if (!bq->flush_node.prev) list_add(&bq->flush_node, flush_list); + + return 0; } int cpu_map_enqueue(struct bpf_cpu_map_entry *rcpu, struct xdp_buff *xdp, @@ -722,7 +673,7 @@ int cpu_map_enqueue(struct bpf_cpu_map_entry *rcpu, struct xdp_buff *xdp, { struct xdp_frame *xdpf; - xdpf = xdp_convert_buff_to_frame(xdp); + xdpf = convert_to_xdp_frame(xdp); if (unlikely(!xdpf)) return -EOVERFLOW; @@ -733,26 +684,16 @@ int cpu_map_enqueue(struct bpf_cpu_map_entry *rcpu, struct xdp_buff *xdp, return 0; } -void __cpu_map_flush(void) +void __cpu_map_flush(struct bpf_map *map) { - struct list_head *flush_list = this_cpu_ptr(&cpu_map_flush_list); + struct bpf_cpu_map *cmap = container_of(map, struct bpf_cpu_map, map); + struct list_head *flush_list = this_cpu_ptr(cmap->flush_list); struct xdp_bulk_queue *bq, *tmp; list_for_each_entry_safe(bq, tmp, flush_list, flush_node) { - bq_flush_to_queue(bq); + bq_flush_to_queue(bq, true); /* If already running, costs spin_lock_irqsave + smb_mb */ wake_up_process(bq->obj->kthread); } } - -static int __init cpu_map_init(void) -{ - int cpu; - - for_each_possible_cpu(cpu) - INIT_LIST_HEAD(&per_cpu(cpu_map_flush_list, cpu)); - return 0; -} - -subsys_initcall(cpu_map_init); diff --git a/kernel/bpf/devmap.c b/kernel/bpf/devmap.c index e805811ac2c9..08ff40e3921c 100644 --- a/kernel/bpf/devmap.c +++ b/kernel/bpf/devmap.c @@ -52,11 +52,14 @@ #define DEV_CREATE_FLAG_MASK \ (BPF_F_NUMA_NODE | BPF_F_RDONLY | BPF_F_WRONLY) -struct xdp_dev_bulk_queue { +#define DEV_MAP_BULK_SIZE 16 +struct bpf_dtab_netdev; + +struct xdp_bulk_queue { struct xdp_frame *q[DEV_MAP_BULK_SIZE]; struct list_head flush_node; - struct net_device *dev; struct net_device *dev_rx; + struct bpf_dtab_netdev *obj; unsigned int count; }; @@ -64,15 +67,15 @@ struct bpf_dtab_netdev { struct net_device *dev; /* must be first member, due to tracepoint */ struct hlist_node index_hlist; struct bpf_dtab *dtab; - struct bpf_prog *xdp_prog; + struct xdp_bulk_queue __percpu *bulkq; struct rcu_head rcu; - unsigned int idx; - struct bpf_devmap_val val; + unsigned int idx; /* keep track of map index for tracepoint */ }; struct bpf_dtab { struct bpf_map map; struct bpf_dtab_netdev **netdev_map; /* DEVMAP type only */ + struct list_head __percpu *flush_list; struct list_head list; /* these are only used for DEVMAP_HASH type maps */ @@ -82,7 +85,6 @@ struct bpf_dtab { u32 n_buckets; }; -static DEFINE_PER_CPU(struct list_head, dev_flush_list); static DEFINE_SPINLOCK(dev_map_lock); static LIST_HEAD(dev_map_list); @@ -108,18 +110,12 @@ static inline struct hlist_head *dev_map_index_hash(struct bpf_dtab *dtab, static int dev_map_init_map(struct bpf_dtab *dtab, union bpf_attr *attr) { - u32 valsize = attr->value_size; - u64 cost = 0; - int err; + int err, cpu; + u64 cost; - /* check sanity of attributes. 2 value sizes supported: - * 4 bytes: ifindex - * 8 bytes: ifindex + prog fd - */ + /* check sanity of attributes */ if (attr->max_entries == 0 || attr->key_size != 4 || - (valsize != offsetofend(struct bpf_devmap_val, ifindex) && - valsize != offsetofend(struct bpf_devmap_val, bpf_prog.fd)) || - attr->map_flags & ~DEV_CREATE_FLAG_MASK) + attr->value_size != 4 || attr->map_flags & ~DEV_CREATE_FLAG_MASK) return -EINVAL; /* Lookup returns a pointer straight to dev->ifindex, so make sure the @@ -130,6 +126,9 @@ static int dev_map_init_map(struct bpf_dtab *dtab, union bpf_attr *attr) bpf_map_init_from_attr(&dtab->map, attr); + /* make sure page count doesn't overflow */ + cost = (u64) sizeof(struct list_head) * num_possible_cpus(); + if (attr->map_type == BPF_MAP_TYPE_DEVMAP_HASH) { /* hash table size must be power of 2; roundup_pow_of_two() can * overflow into UB on 32-bit arches, so check that first @@ -148,11 +147,18 @@ static int dev_map_init_map(struct bpf_dtab *dtab, union bpf_attr *attr) if (err) return -EINVAL; + dtab->flush_list = alloc_percpu(struct list_head); + if (!dtab->flush_list) + goto free_charge; + + for_each_possible_cpu(cpu) + INIT_LIST_HEAD(per_cpu_ptr(dtab->flush_list, cpu)); + if (attr->map_type == BPF_MAP_TYPE_DEVMAP_HASH) { dtab->dev_index_head = dev_map_create_hash(dtab->n_buckets, dtab->map.numa_node); if (!dtab->dev_index_head) - goto free_charge; + goto free_percpu; spin_lock_init(&dtab->index_lock); } else { @@ -160,11 +166,13 @@ static int dev_map_init_map(struct bpf_dtab *dtab, union bpf_attr *attr) sizeof(struct bpf_dtab_netdev *), dtab->map.numa_node); if (!dtab->netdev_map) - goto free_charge; + goto free_percpu; } return 0; +free_percpu: + free_percpu(dtab->flush_list); free_charge: bpf_map_charge_finish(&dtab->map.memory); return -ENOMEM; @@ -230,8 +238,7 @@ static void dev_map_free(struct bpf_map *map) hlist_for_each_entry_safe(dev, next, head, index_hlist) { hlist_del_rcu(&dev->index_hlist); - if (dev->xdp_prog) - bpf_prog_put(dev->xdp_prog); + free_percpu(dev->bulkq); dev_put(dev->dev); kfree(dev); } @@ -246,8 +253,7 @@ static void dev_map_free(struct bpf_map *map) if (!dev) continue; - if (dev->xdp_prog) - bpf_prog_put(dev->xdp_prog); + free_percpu(dev->bulkq); dev_put(dev->dev); kfree(dev); } @@ -255,6 +261,7 @@ static void dev_map_free(struct bpf_map *map) bpf_map_area_free(dtab->netdev_map); } + free_percpu(dtab->flush_list); kfree(dtab); } @@ -334,24 +341,15 @@ static int dev_map_hash_get_next_key(struct bpf_map *map, void *key, return -ENOENT; } -bool dev_map_can_have_prog(struct bpf_map *map) +static int bq_xmit_all(struct xdp_bulk_queue *bq, u32 flags) { - if ((map->map_type == BPF_MAP_TYPE_DEVMAP || - map->map_type == BPF_MAP_TYPE_DEVMAP_HASH) && - map->value_size != offsetofend(struct bpf_devmap_val, ifindex)) - return true; - - return false; -} - -static void bq_xmit_all(struct xdp_dev_bulk_queue *bq, u32 flags) -{ - struct net_device *dev = bq->dev; + struct bpf_dtab_netdev *obj = bq->obj; + struct net_device *dev = obj->dev; int sent = 0, drops = 0, err = 0; int i; if (unlikely(!bq->count)) - return; + return 0; for (i = 0; i < bq->count; i++) { struct xdp_frame *xdpf = bq->q[i]; @@ -369,10 +367,11 @@ static void bq_xmit_all(struct xdp_dev_bulk_queue *bq, u32 flags) out: bq->count = 0; - trace_xdp_devmap_xmit(bq->dev_rx, dev, sent, drops, err); + trace_xdp_devmap_xmit(&obj->dtab->map, obj->idx, + sent, drops, bq->dev_rx, dev, err); bq->dev_rx = NULL; __list_del_clearprev(&bq->flush_node); - return; + return 0; error: /* If ndo_xdp_xmit fails with an errno, no frames have been * xmit'ed and it's our responsibility to them free all. @@ -386,23 +385,23 @@ error: goto out; } -/* __dev_flush is called from xdp_do_flush() which _must_ be signaled +/* __dev_map_flush is called from xdp_do_flush_map() which _must_ be signaled * from the driver before returning from its napi->poll() routine. The poll() * routine is called either from busy_poll context or net_rx_action signaled * from NET_RX_SOFTIRQ. Either way the poll routine must complete before the * net device can be torn down. On devmap tear down we ensure the flush list * is empty before completing to ensure all flush operations have completed. - * When drivers update the bpf program they may need to ensure any flush ops - * are also complete. Using synchronize_rcu or call_rcu will suffice for this - * because both wait for napi context to exit. */ -void __dev_flush(void) +void __dev_map_flush(struct bpf_map *map) { - struct list_head *flush_list = this_cpu_ptr(&dev_flush_list); - struct xdp_dev_bulk_queue *bq, *tmp; + struct bpf_dtab *dtab = container_of(map, struct bpf_dtab, map); + struct list_head *flush_list = this_cpu_ptr(dtab->flush_list); + struct xdp_bulk_queue *bq, *tmp; + rcu_read_lock(); list_for_each_entry_safe(bq, tmp, flush_list, flush_node) bq_xmit_all(bq, XDP_XMIT_FLUSH); + rcu_read_unlock(); } /* rcu_read_lock (from syscall and BPF contexts) ensures that if a delete and/or @@ -424,11 +423,12 @@ struct bpf_dtab_netdev *__dev_map_lookup_elem(struct bpf_map *map, u32 key) /* Runs under RCU-read-side, plus in softirq under NAPI protection. * Thus, safe percpu variable access. */ -static void bq_enqueue(struct net_device *dev, struct xdp_frame *xdpf, - struct net_device *dev_rx) +static int bq_enqueue(struct bpf_dtab_netdev *obj, struct xdp_frame *xdpf, + struct net_device *dev_rx) + { - struct list_head *flush_list = this_cpu_ptr(&dev_flush_list); - struct xdp_dev_bulk_queue *bq = this_cpu_ptr(dev->xdp_bulkq); + struct list_head *flush_list = this_cpu_ptr(obj->dtab->flush_list); + struct xdp_bulk_queue *bq = this_cpu_ptr(obj->bulkq); if (unlikely(bq->count == DEV_MAP_BULK_SIZE)) bq_xmit_all(bq, 0); @@ -444,11 +444,14 @@ static void bq_enqueue(struct net_device *dev, struct xdp_frame *xdpf, if (!bq->flush_node.prev) list_add(&bq->flush_node, flush_list); + + return 0; } -static inline int __xdp_enqueue(struct net_device *dev, struct xdp_buff *xdp, - struct net_device *dev_rx) +int dev_map_enqueue(struct bpf_dtab_netdev *dst, struct xdp_buff *xdp, + struct net_device *dev_rx) { + struct net_device *dev = dst->dev; struct xdp_frame *xdpf; int err; @@ -459,59 +462,11 @@ static inline int __xdp_enqueue(struct net_device *dev, struct xdp_buff *xdp, if (unlikely(err)) return err; - xdpf = xdp_convert_buff_to_frame(xdp); + xdpf = convert_to_xdp_frame(xdp); if (unlikely(!xdpf)) return -EOVERFLOW; - bq_enqueue(dev, xdpf, dev_rx); - return 0; -} - -static struct xdp_buff *dev_map_run_prog(struct net_device *dev, - struct xdp_buff *xdp, - struct bpf_prog *xdp_prog) -{ - struct xdp_txq_info txq = { .dev = dev }; - u32 act; - - xdp_set_data_meta_invalid(xdp); - xdp->txq = &txq; - - act = bpf_prog_run_xdp(xdp_prog, xdp); - switch (act) { - case XDP_PASS: - return xdp; - case XDP_DROP: - break; - default: - bpf_warn_invalid_xdp_action(act); - fallthrough; - case XDP_ABORTED: - trace_xdp_exception(dev, xdp_prog, act); - break; - } - - xdp_return_buff(xdp); - return NULL; -} - -int dev_xdp_enqueue(struct net_device *dev, struct xdp_buff *xdp, - struct net_device *dev_rx) -{ - return __xdp_enqueue(dev, xdp, dev_rx); -} - -int dev_map_enqueue(struct bpf_dtab_netdev *dst, struct xdp_buff *xdp, - struct net_device *dev_rx) -{ - struct net_device *dev = dst->dev; - - if (dst->xdp_prog) { - xdp = dev_map_run_prog(dev, xdp, dst->xdp_prog); - if (!xdp) - return 0; - } - return __xdp_enqueue(dev, xdp, dev_rx); + return bq_enqueue(dst, xdpf, dev_rx); } int dev_map_generic_redirect(struct bpf_dtab_netdev *dst, struct sk_buff *skb, @@ -531,15 +486,18 @@ int dev_map_generic_redirect(struct bpf_dtab_netdev *dst, struct sk_buff *skb, static void *dev_map_lookup_elem(struct bpf_map *map, void *key) { struct bpf_dtab_netdev *obj = __dev_map_lookup_elem(map, *(u32 *)key); + struct net_device *dev = obj ? obj->dev : NULL; - return obj ? &obj->val : NULL; + return dev ? &dev->ifindex : NULL; } static void *dev_map_hash_lookup_elem(struct bpf_map *map, void *key) { struct bpf_dtab_netdev *obj = __dev_map_hash_lookup_elem(map, *(u32 *)key); - return obj ? &obj->val : NULL; + struct net_device *dev = obj ? obj->dev : NULL; + + return dev ? &dev->ifindex : NULL; } static void __dev_map_entry_free(struct rcu_head *rcu) @@ -547,8 +505,7 @@ static void __dev_map_entry_free(struct rcu_head *rcu) struct bpf_dtab_netdev *dev; dev = container_of(rcu, struct bpf_dtab_netdev, rcu); - if (dev->xdp_prog) - bpf_prog_put(dev->xdp_prog); + free_percpu(dev->bulkq); dev_put(dev->dev); kfree(dev); } @@ -599,49 +556,41 @@ static int dev_map_hash_delete_elem(struct bpf_map *map, void *key) static struct bpf_dtab_netdev *__dev_map_alloc_node(struct net *net, struct bpf_dtab *dtab, - struct bpf_devmap_val *val, + u32 ifindex, unsigned int idx) { - struct bpf_prog *prog = NULL; + gfp_t gfp = GFP_ATOMIC | __GFP_NOWARN; struct bpf_dtab_netdev *dev; + struct xdp_bulk_queue *bq; + int cpu; - dev = kmalloc_node(sizeof(*dev), GFP_ATOMIC | __GFP_NOWARN, - dtab->map.numa_node); + dev = kmalloc_node(sizeof(*dev), gfp, dtab->map.numa_node); if (!dev) return ERR_PTR(-ENOMEM); - dev->dev = dev_get_by_index(net, val->ifindex); - if (!dev->dev) - goto err_out; + dev->bulkq = __alloc_percpu_gfp(sizeof(*dev->bulkq), + sizeof(void *), gfp); + if (!dev->bulkq) { + kfree(dev); + return ERR_PTR(-ENOMEM); + } - if (val->bpf_prog.fd > 0) { - prog = bpf_prog_get_type_dev(val->bpf_prog.fd, - BPF_PROG_TYPE_XDP, false); - if (IS_ERR(prog)) - goto err_put_dev; - if (prog->expected_attach_type != BPF_XDP_DEVMAP) - goto err_put_prog; + for_each_possible_cpu(cpu) { + bq = per_cpu_ptr(dev->bulkq, cpu); + bq->obj = dev; + } + + dev->dev = dev_get_by_index(net, ifindex); + if (!dev->dev) { + free_percpu(dev->bulkq); + kfree(dev); + return ERR_PTR(-EINVAL); } dev->idx = idx; dev->dtab = dtab; - if (prog) { - dev->xdp_prog = prog; - dev->val.bpf_prog.id = prog->aux->id; - } else { - dev->xdp_prog = NULL; - dev->val.bpf_prog.id = 0; - } - dev->val.ifindex = val->ifindex; return dev; -err_put_prog: - bpf_prog_put(prog); -err_put_dev: - dev_put(dev->dev); -err_out: - kfree(dev); - return ERR_PTR(-EINVAL); } static int __dev_map_update_elem(struct net *net, struct bpf_map *map, @@ -649,7 +598,7 @@ static int __dev_map_update_elem(struct net *net, struct bpf_map *map, { struct bpf_dtab *dtab = container_of(map, struct bpf_dtab, map); struct bpf_dtab_netdev *dev, *old_dev; - struct bpf_devmap_val val = {}; + u32 ifindex = *(u32 *)value; u32 i = *(u32 *)key; if (unlikely(map_flags > BPF_EXIST)) @@ -659,16 +608,10 @@ static int __dev_map_update_elem(struct net *net, struct bpf_map *map, if (unlikely(map_flags == BPF_NOEXIST)) return -EEXIST; - /* already verified value_size <= sizeof val */ - memcpy(&val, value, map->value_size); - - if (!val.ifindex) { + if (!ifindex) { dev = NULL; - /* can not specify fd if ifindex is 0 */ - if (val.bpf_prog.fd > 0) - return -EINVAL; } else { - dev = __dev_map_alloc_node(net, dtab, &val, i); + dev = __dev_map_alloc_node(net, dtab, ifindex, i); if (IS_ERR(dev)) return PTR_ERR(dev); } @@ -696,15 +639,12 @@ static int __dev_map_hash_update_elem(struct net *net, struct bpf_map *map, { struct bpf_dtab *dtab = container_of(map, struct bpf_dtab, map); struct bpf_dtab_netdev *dev, *old_dev; - struct bpf_devmap_val val = {}; + u32 ifindex = *(u32 *)value; u32 idx = *(u32 *)key; unsigned long flags; int err = -EEXIST; - /* already verified value_size <= sizeof val */ - memcpy(&val, value, map->value_size); - - if (unlikely(map_flags > BPF_EXIST || !val.ifindex)) + if (unlikely(map_flags > BPF_EXIST || !ifindex)) return -EINVAL; spin_lock_irqsave(&dtab->index_lock, flags); @@ -713,7 +653,7 @@ static int __dev_map_hash_update_elem(struct net *net, struct bpf_map *map, if (old_dev && (map_flags & BPF_NOEXIST)) goto out_err; - dev = __dev_map_alloc_node(net, dtab, &val, idx); + dev = __dev_map_alloc_node(net, dtab, ifindex, idx); if (IS_ERR(dev)) { err = PTR_ERR(dev); goto out_err; @@ -751,9 +691,7 @@ static int dev_map_hash_update_elem(struct bpf_map *map, void *key, void *value, map, key, value, map_flags); } -static int dev_map_btf_id; const struct bpf_map_ops dev_map_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc = dev_map_alloc, .map_free = dev_map_free, .map_get_next_key = dev_map_get_next_key, @@ -761,13 +699,9 @@ const struct bpf_map_ops dev_map_ops = { .map_update_elem = dev_map_update_elem, .map_delete_elem = dev_map_delete_elem, .map_check_btf = map_check_no_btf, - .map_btf_name = "bpf_dtab", - .map_btf_id = &dev_map_btf_id, }; -static int dev_map_hash_map_btf_id; const struct bpf_map_ops dev_map_hash_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc = dev_map_alloc, .map_free = dev_map_free, .map_get_next_key = dev_map_hash_get_next_key, @@ -775,8 +709,6 @@ const struct bpf_map_ops dev_map_hash_ops = { .map_update_elem = dev_map_hash_update_elem, .map_delete_elem = dev_map_hash_delete_elem, .map_check_btf = map_check_no_btf, - .map_btf_name = "bpf_dtab", - .map_btf_id = &dev_map_hash_map_btf_id, }; static void dev_map_hash_remove_netdev(struct bpf_dtab *dtab, @@ -810,21 +742,9 @@ static int dev_map_notification(struct notifier_block *notifier, { struct net_device *netdev = netdev_notifier_info_to_dev(ptr); struct bpf_dtab *dtab; - int i, cpu; + int i; switch (event) { - case NETDEV_REGISTER: - if (!netdev->netdev_ops->ndo_xdp_xmit || netdev->xdp_bulkq) - break; - - /* will be freed in free_netdev() */ - netdev->xdp_bulkq = alloc_percpu(struct xdp_dev_bulk_queue); - if (!netdev->xdp_bulkq) - return NOTIFY_BAD; - - for_each_possible_cpu(cpu) - per_cpu_ptr(netdev->xdp_bulkq, cpu)->dev = netdev; - break; case NETDEV_UNREGISTER: /* This rcu_read_lock/unlock pair is needed because * dev_map_list is an RCU list AND to ensure a delete @@ -864,15 +784,10 @@ static struct notifier_block dev_map_notifier = { static int __init dev_map_init(void) { - int cpu; - /* Assure tracepoint shadow struct _bpf_dtab_netdev is in sync */ BUILD_BUG_ON(offsetof(struct bpf_dtab_netdev, dev) != offsetof(struct _bpf_dtab_netdev, dev)); register_netdevice_notifier(&dev_map_notifier); - - for_each_possible_cpu(cpu) - INIT_LIST_HEAD(&per_cpu(dev_flush_list, cpu)); return 0; } diff --git a/kernel/bpf/dispatcher.c b/kernel/bpf/dispatcher.c deleted file mode 100644 index 2444bd15cc2d..000000000000 --- a/kernel/bpf/dispatcher.c +++ /dev/null @@ -1,159 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright(c) 2019 Intel Corporation. */ - -#include -#include -#include - -/* The BPF dispatcher is a multiway branch code generator. The - * dispatcher is a mechanism to avoid the performance penalty of an - * indirect call, which is expensive when retpolines are enabled. A - * dispatch client registers a BPF program into the dispatcher, and if - * there is available room in the dispatcher a direct call to the BPF - * program will be generated. All calls to the BPF programs called via - * the dispatcher will then be a direct call, instead of an - * indirect. The dispatcher hijacks a trampoline function it via the - * __fentry__ of the trampoline. The trampoline function has the - * following signature: - * - * unsigned int trampoline(const void *ctx, const struct bpf_insn *insnsi, - * unsigned int (*bpf_func)(const void *, - * const struct bpf_insn *)); - */ - -static struct bpf_dispatcher_prog *bpf_dispatcher_find_prog( - struct bpf_dispatcher *d, struct bpf_prog *prog) -{ - int i; - - for (i = 0; i < BPF_DISPATCHER_MAX; i++) { - if (prog == d->progs[i].prog) - return &d->progs[i]; - } - return NULL; -} - -static struct bpf_dispatcher_prog *bpf_dispatcher_find_free( - struct bpf_dispatcher *d) -{ - return bpf_dispatcher_find_prog(d, NULL); -} - -static bool bpf_dispatcher_add_prog(struct bpf_dispatcher *d, - struct bpf_prog *prog) -{ - struct bpf_dispatcher_prog *entry; - - if (!prog) - return false; - - entry = bpf_dispatcher_find_prog(d, prog); - if (entry) { - refcount_inc(&entry->users); - return false; - } - - entry = bpf_dispatcher_find_free(d); - if (!entry) - return false; - - bpf_prog_inc(prog); - entry->prog = prog; - refcount_set(&entry->users, 1); - d->num_progs++; - return true; -} - -static bool bpf_dispatcher_remove_prog(struct bpf_dispatcher *d, - struct bpf_prog *prog) -{ - struct bpf_dispatcher_prog *entry; - - if (!prog) - return false; - - entry = bpf_dispatcher_find_prog(d, prog); - if (!entry) - return false; - - if (refcount_dec_and_test(&entry->users)) { - entry->prog = NULL; - bpf_prog_put(prog); - d->num_progs--; - return true; - } - return false; -} - -int __weak arch_prepare_bpf_dispatcher(void *image, s64 *funcs, int num_funcs) -{ - return -ENOTSUPP; -} - -static int bpf_dispatcher_prepare(struct bpf_dispatcher *d, void *image) -{ - s64 ips[BPF_DISPATCHER_MAX] = {}, *ipsp = &ips[0]; - int i; - - for (i = 0; i < BPF_DISPATCHER_MAX; i++) { - if (d->progs[i].prog) - *ipsp++ = (s64)(uintptr_t)d->progs[i].prog->bpf_func; - } - return arch_prepare_bpf_dispatcher(image, &ips[0], d->num_progs); -} - -static void bpf_dispatcher_update(struct bpf_dispatcher *d, int prev_num_progs) -{ - void *old, *new; - u32 noff; - int err; - - if (!prev_num_progs) { - old = NULL; - noff = 0; - } else { - old = d->image + d->image_off; - noff = d->image_off ^ (PAGE_SIZE / 2); - } - - new = d->num_progs ? d->image + noff : NULL; - if (new) { - if (bpf_dispatcher_prepare(d, new)) - return; - } - - err = bpf_arch_text_poke(d->func, BPF_MOD_JUMP, old, new); - if (err || !new) - return; - - d->image_off = noff; -} - -void bpf_dispatcher_change_prog(struct bpf_dispatcher *d, struct bpf_prog *from, - struct bpf_prog *to) -{ - bool changed = false; - int prev_num_progs; - - if (from == to) - return; - - mutex_lock(&d->mutex); - if (!d->image) { - d->image = bpf_jit_alloc_exec_page(); - if (!d->image) - goto out; - bpf_image_ksym_add(d->image, &d->ksym); - } - - prev_num_progs = d->num_progs; - changed |= bpf_dispatcher_remove_prog(d, from); - changed |= bpf_dispatcher_add_prog(d, to); - - if (!changed) - goto out; - - bpf_dispatcher_update(d, prev_num_progs); -out: - mutex_unlock(&d->mutex); -} diff --git a/kernel/bpf/hashtab.c b/kernel/bpf/hashtab.c index fdcbb7f6b1d5..ddcf0d46228c 100644 --- a/kernel/bpf/hashtab.c +++ b/kernel/bpf/hashtab.c @@ -9,7 +9,6 @@ #include #include #include -#include #include "percpu_freelist.h" #include "bpf_lru_list.h" #include "map_in_map.h" @@ -18,72 +17,9 @@ (BPF_F_NO_PREALLOC | BPF_F_NO_COMMON_LRU | BPF_F_NUMA_NODE | \ BPF_F_ACCESS_MASK | BPF_F_ZERO_SEED) -#define BATCH_OPS(_name) \ - .map_lookup_batch = \ - _name##_map_lookup_batch, \ - .map_lookup_and_delete_batch = \ - _name##_map_lookup_and_delete_batch, \ - .map_update_batch = \ - generic_map_update_batch, \ - .map_delete_batch = \ - generic_map_delete_batch - -/* - * The bucket lock has two protection scopes: - * - * 1) Serializing concurrent operations from BPF programs on differrent - * CPUs - * - * 2) Serializing concurrent operations from BPF programs and sys_bpf() - * - * BPF programs can execute in any context including perf, kprobes and - * tracing. As there are almost no limits where perf, kprobes and tracing - * can be invoked from the lock operations need to be protected against - * deadlocks. Deadlocks can be caused by recursion and by an invocation in - * the lock held section when functions which acquire this lock are invoked - * from sys_bpf(). BPF recursion is prevented by incrementing the per CPU - * variable bpf_prog_active, which prevents BPF programs attached to perf - * events, kprobes and tracing to be invoked before the prior invocation - * from one of these contexts completed. sys_bpf() uses the same mechanism - * by pinning the task to the current CPU and incrementing the recursion - * protection accross the map operation. - * - * This has subtle implications on PREEMPT_RT. PREEMPT_RT forbids certain - * operations like memory allocations (even with GFP_ATOMIC) from atomic - * contexts. This is required because even with GFP_ATOMIC the memory - * allocator calls into code pathes which acquire locks with long held lock - * sections. To ensure the deterministic behaviour these locks are regular - * spinlocks, which are converted to 'sleepable' spinlocks on RT. The only - * true atomic contexts on an RT kernel are the low level hardware - * handling, scheduling, low level interrupt handling, NMIs etc. None of - * these contexts should ever do memory allocations. - * - * As regular device interrupt handlers and soft interrupts are forced into - * thread context, the existing code which does - * spin_lock*(); alloc(GPF_ATOMIC); spin_unlock*(); - * just works. - * - * In theory the BPF locks could be converted to regular spinlocks as well, - * but the bucket locks and percpu_freelist locks can be taken from - * arbitrary contexts (perf, kprobes, tracepoints) which are required to be - * atomic contexts even on RT. These mechanisms require preallocated maps, - * so there is no need to invoke memory allocations within the lock held - * sections. - * - * BPF maps which need dynamic allocation are only used from (forced) - * thread context on RT and can therefore use regular spinlocks which in - * turn allows to invoke memory allocations from the lock held section. - * - * On a non RT kernel this distinction is neither possible nor required. - * spinlock maps to raw_spinlock and the extra code is optimized out by the - * compiler. - */ struct bucket { struct hlist_nulls_head head; - union { - raw_spinlock_t raw_lock; - spinlock_t lock; - }; + raw_spinlock_t lock; }; struct bpf_htab { @@ -110,7 +46,6 @@ struct htab_elem { union { struct bpf_htab *htab; struct pcpu_freelist_node fnode; - struct htab_elem *batch_flink; }; }; }; @@ -119,54 +54,9 @@ struct htab_elem { struct bpf_lru_node lru_node; }; u32 hash; - char key[] __aligned(8); + char key[0] __aligned(8); }; -static inline bool htab_is_prealloc(const struct bpf_htab *htab) -{ - return !(htab->map.map_flags & BPF_F_NO_PREALLOC); -} - -static inline bool htab_use_raw_lock(const struct bpf_htab *htab) -{ - return (!IS_ENABLED(CONFIG_PREEMPT_RT) || htab_is_prealloc(htab)); -} - -static void htab_init_buckets(struct bpf_htab *htab) -{ - unsigned i; - - for (i = 0; i < htab->n_buckets; i++) { - INIT_HLIST_NULLS_HEAD(&htab->buckets[i].head, i); - if (htab_use_raw_lock(htab)) - raw_spin_lock_init(&htab->buckets[i].raw_lock); - else - spin_lock_init(&htab->buckets[i].lock); - } -} - -static inline unsigned long htab_lock_bucket(const struct bpf_htab *htab, - struct bucket *b) -{ - unsigned long flags; - - if (htab_use_raw_lock(htab)) - raw_spin_lock_irqsave(&b->raw_lock, flags); - else - spin_lock_irqsave(&b->lock, flags); - return flags; -} - -static inline void htab_unlock_bucket(const struct bpf_htab *htab, - struct bucket *b, - unsigned long flags) -{ - if (htab_use_raw_lock(htab)) - raw_spin_unlock_irqrestore(&b->raw_lock, flags); - else - spin_unlock_irqrestore(&b->lock, flags); -} - static bool htab_lru_map_delete_node(void *arg, struct bpf_lru_node *node); static bool htab_is_lru(const struct bpf_htab *htab) @@ -181,6 +71,11 @@ static bool htab_is_percpu(const struct bpf_htab *htab) htab->map.map_type == BPF_MAP_TYPE_LRU_PERCPU_HASH; } +static bool htab_is_prealloc(const struct bpf_htab *htab) +{ + return !(htab->map.map_flags & BPF_F_NO_PREALLOC); +} + static inline void htab_elem_set_ptr(struct htab_elem *l, u32 key_size, void __percpu *pptr) { @@ -221,17 +116,6 @@ free_elems: bpf_map_area_free(htab->elems); } -/* The LRU list has a lock (lru_lock). Each htab bucket has a lock - * (bucket_lock). If both locks need to be acquired together, the lock - * order is always lru_lock -> bucket_lock and this only happens in - * bpf_lru_list.c logic. For example, certain code path of - * bpf_lru_pop_free(), which is called by function prealloc_lru_pop(), - * will acquire lru_lock first followed by acquiring bucket_lock. - * - * In hashtab.c, to avoid deadlock, lock acquisition of - * bucket_lock followed by lru_lock is not allowed. In such cases, - * bucket_lock needs to be released first before acquiring lru_lock. - */ static struct htab_elem *prealloc_lru_pop(struct bpf_htab *htab, void *key, u32 hash) { @@ -360,9 +244,9 @@ static int htab_map_alloc_check(union bpf_attr *attr) BUILD_BUG_ON(offsetof(struct htab_elem, fnode.next) != offsetof(struct htab_elem, hash_node.pprev)); - if (lru && !bpf_capable()) + if (lru && !capable(CAP_SYS_ADMIN)) /* LRU implementation is much complicated than other - * maps. Hence, limit to CAP_BPF. + * maps. Hence, limit to CAP_SYS_ADMIN for now. */ return -EPERM; @@ -425,8 +309,8 @@ static struct bpf_map *htab_map_alloc(union bpf_attr *attr) bool percpu_lru = (attr->map_flags & BPF_F_NO_COMMON_LRU); bool prealloc = !(attr->map_flags & BPF_F_NO_PREALLOC); struct bpf_htab *htab; + int err, i; u64 cost; - int err; htab = kzalloc(sizeof(*htab), GFP_USER); if (!htab) @@ -492,7 +376,10 @@ static struct bpf_map *htab_map_alloc(union bpf_attr *attr) else htab->hashrnd = get_random_int(); - htab_init_buckets(htab); + for (i = 0; i < htab->n_buckets; i++) { + INIT_HLIST_NULLS_HEAD(&htab->buckets[i].head, i); + raw_spin_lock_init(&htab->buckets[i].lock); + } if (prealloc) { err = prealloc_init(htab); @@ -585,7 +472,8 @@ static void *__htab_map_lookup_elem(struct bpf_map *map, void *key) struct htab_elem *l; u32 hash, key_size; - WARN_ON_ONCE(!rcu_read_lock_held() && !rcu_read_lock_trace_held()); + /* Must be called with rcu_read_lock. */ + WARN_ON_ONCE(!rcu_read_lock_held()); key_size = map->key_size; @@ -619,7 +507,7 @@ static void *htab_map_lookup_elem(struct bpf_map *map, void *key) * bpf_prog * __htab_map_lookup_elem */ -static int htab_map_gen_lookup(struct bpf_map *map, struct bpf_insn *insn_buf) +static u32 htab_map_gen_lookup(struct bpf_map *map, struct bpf_insn *insn_buf) { struct bpf_insn *insn = insn_buf; const int ret = BPF_REG_0; @@ -658,7 +546,7 @@ static void *htab_lru_map_lookup_elem_sys(struct bpf_map *map, void *key) return __htab_lru_map_lookup_elem(map, key, false); } -static int htab_lru_map_gen_lookup(struct bpf_map *map, +static u32 htab_lru_map_gen_lookup(struct bpf_map *map, struct bpf_insn *insn_buf) { struct bpf_insn *insn = insn_buf; @@ -699,7 +587,7 @@ static bool htab_lru_map_delete_node(void *arg, struct bpf_lru_node *node) b = __select_bucket(htab, tgt_l->hash); head = &b->head; - flags = htab_lock_bucket(htab, b); + raw_spin_lock_irqsave(&b->lock, flags); hlist_nulls_for_each_entry_rcu(l, n, head, hash_node) if (l == tgt_l) { @@ -707,7 +595,7 @@ static bool htab_lru_map_delete_node(void *arg, struct bpf_lru_node *node) break; } - htab_unlock_bucket(htab, b, flags); + raw_spin_unlock_irqrestore(&b->lock, flags); return l == tgt_l; } @@ -974,7 +862,7 @@ static int htab_map_update_elem(struct bpf_map *map, void *key, void *value, /* unknown flags */ return -EINVAL; - WARN_ON_ONCE(!rcu_read_lock_held() && !rcu_read_lock_trace_held()); + WARN_ON_ONCE(!rcu_read_lock_held()); key_size = map->key_size; @@ -1005,7 +893,8 @@ static int htab_map_update_elem(struct bpf_map *map, void *key, void *value, */ } - flags = htab_lock_bucket(htab, b); + /* bpf_map_update_elem() can be called in_irq() */ + raw_spin_lock_irqsave(&b->lock, flags); l_old = lookup_elem_raw(head, hash, key, key_size); @@ -1046,7 +935,7 @@ static int htab_map_update_elem(struct bpf_map *map, void *key, void *value, } ret = 0; err: - htab_unlock_bucket(htab, b, flags); + raw_spin_unlock_irqrestore(&b->lock, flags); return ret; } @@ -1065,7 +954,7 @@ static int htab_lru_map_update_elem(struct bpf_map *map, void *key, void *value, /* unknown flags */ return -EINVAL; - WARN_ON_ONCE(!rcu_read_lock_held() && !rcu_read_lock_trace_held()); + WARN_ON_ONCE(!rcu_read_lock_held()); key_size = map->key_size; @@ -1084,7 +973,8 @@ static int htab_lru_map_update_elem(struct bpf_map *map, void *key, void *value, return -ENOMEM; memcpy(l_new->key + round_up(map->key_size, 8), value, map->value_size); - flags = htab_lock_bucket(htab, b); + /* bpf_map_update_elem() can be called in_irq() */ + raw_spin_lock_irqsave(&b->lock, flags); l_old = lookup_elem_raw(head, hash, key, key_size); @@ -1103,7 +993,7 @@ static int htab_lru_map_update_elem(struct bpf_map *map, void *key, void *value, ret = 0; err: - htab_unlock_bucket(htab, b, flags); + raw_spin_unlock_irqrestore(&b->lock, flags); if (ret) bpf_lru_push_free(&htab->lru, &l_new->lru_node); @@ -1138,7 +1028,8 @@ static int __htab_percpu_map_update_elem(struct bpf_map *map, void *key, b = __select_bucket(htab, hash); head = &b->head; - flags = htab_lock_bucket(htab, b); + /* bpf_map_update_elem() can be called in_irq() */ + raw_spin_lock_irqsave(&b->lock, flags); l_old = lookup_elem_raw(head, hash, key, key_size); @@ -1161,7 +1052,7 @@ static int __htab_percpu_map_update_elem(struct bpf_map *map, void *key, } ret = 0; err: - htab_unlock_bucket(htab, b, flags); + raw_spin_unlock_irqrestore(&b->lock, flags); return ret; } @@ -1201,7 +1092,8 @@ static int __htab_lru_percpu_map_update_elem(struct bpf_map *map, void *key, return -ENOMEM; } - flags = htab_lock_bucket(htab, b); + /* bpf_map_update_elem() can be called in_irq() */ + raw_spin_lock_irqsave(&b->lock, flags); l_old = lookup_elem_raw(head, hash, key, key_size); @@ -1223,7 +1115,7 @@ static int __htab_lru_percpu_map_update_elem(struct bpf_map *map, void *key, } ret = 0; err: - htab_unlock_bucket(htab, b, flags); + raw_spin_unlock_irqrestore(&b->lock, flags); if (l_new) bpf_lru_push_free(&htab->lru, &l_new->lru_node); return ret; @@ -1253,7 +1145,7 @@ static int htab_map_delete_elem(struct bpf_map *map, void *key) u32 hash, key_size; int ret = -ENOENT; - WARN_ON_ONCE(!rcu_read_lock_held() && !rcu_read_lock_trace_held()); + WARN_ON_ONCE(!rcu_read_lock_held()); key_size = map->key_size; @@ -1261,7 +1153,7 @@ static int htab_map_delete_elem(struct bpf_map *map, void *key) b = __select_bucket(htab, hash); head = &b->head; - flags = htab_lock_bucket(htab, b); + raw_spin_lock_irqsave(&b->lock, flags); l = lookup_elem_raw(head, hash, key, key_size); @@ -1271,7 +1163,7 @@ static int htab_map_delete_elem(struct bpf_map *map, void *key) ret = 0; } - htab_unlock_bucket(htab, b, flags); + raw_spin_unlock_irqrestore(&b->lock, flags); return ret; } @@ -1285,7 +1177,7 @@ static int htab_lru_map_delete_elem(struct bpf_map *map, void *key) u32 hash, key_size; int ret = -ENOENT; - WARN_ON_ONCE(!rcu_read_lock_held() && !rcu_read_lock_trace_held()); + WARN_ON_ONCE(!rcu_read_lock_held()); key_size = map->key_size; @@ -1293,7 +1185,7 @@ static int htab_lru_map_delete_elem(struct bpf_map *map, void *key) b = __select_bucket(htab, hash); head = &b->head; - flags = htab_lock_bucket(htab, b); + raw_spin_lock_irqsave(&b->lock, flags); l = lookup_elem_raw(head, hash, key, key_size); @@ -1302,7 +1194,7 @@ static int htab_lru_map_delete_elem(struct bpf_map *map, void *key) ret = 0; } - htab_unlock_bucket(htab, b, flags); + raw_spin_unlock_irqrestore(&b->lock, flags); if (l) bpf_lru_push_free(&htab->lru, &l->lru_node); return ret; @@ -1329,10 +1221,12 @@ static void htab_map_free(struct bpf_map *map) { struct bpf_htab *htab = container_of(map, struct bpf_htab, map); - /* bpf_free_used_maps() or close(map_fd) will trigger this map_free callback. - * bpf_free_used_maps() is called after bpf prog is no longer executing. - * There is no need to synchronize_rcu() here to protect map elements. + /* at this point bpf_prog->aux->refcnt == 0 and this map->refcnt == 0, + * so the programs (can be more than one that used this map) were + * disconnected from events. Wait for outstanding critical sections in + * these programs to complete */ + synchronize_rcu(); /* some of free_htab_elem() callbacks for elements of this map may * not have executed. Wait for them. @@ -1369,476 +1263,7 @@ static void htab_map_seq_show_elem(struct bpf_map *map, void *key, rcu_read_unlock(); } -static int -__htab_map_lookup_and_delete_batch(struct bpf_map *map, - const union bpf_attr *attr, - union bpf_attr __user *uattr, - bool do_delete, bool is_lru_map, - bool is_percpu) -{ - struct bpf_htab *htab = container_of(map, struct bpf_htab, map); - u32 bucket_cnt, total, key_size, value_size, roundup_key_size; - void *keys = NULL, *values = NULL, *value, *dst_key, *dst_val; - void __user *uvalues = u64_to_user_ptr(attr->batch.values); - void __user *ukeys = u64_to_user_ptr(attr->batch.keys); - void *ubatch = u64_to_user_ptr(attr->batch.in_batch); - u32 batch, max_count, size, bucket_size; - struct htab_elem *node_to_free = NULL; - u64 elem_map_flags, map_flags; - struct hlist_nulls_head *head; - struct hlist_nulls_node *n; - unsigned long flags = 0; - bool locked = false; - struct htab_elem *l; - struct bucket *b; - int ret = 0; - - elem_map_flags = attr->batch.elem_flags; - if ((elem_map_flags & ~BPF_F_LOCK) || - ((elem_map_flags & BPF_F_LOCK) && !map_value_has_spin_lock(map))) - return -EINVAL; - - map_flags = attr->batch.flags; - if (map_flags) - return -EINVAL; - - max_count = attr->batch.count; - if (!max_count) - return 0; - - if (put_user(0, &uattr->batch.count)) - return -EFAULT; - - batch = 0; - if (ubatch && copy_from_user(&batch, ubatch, sizeof(batch))) - return -EFAULT; - - if (batch >= htab->n_buckets) - return -ENOENT; - - key_size = htab->map.key_size; - roundup_key_size = round_up(htab->map.key_size, 8); - value_size = htab->map.value_size; - size = round_up(value_size, 8); - if (is_percpu) - value_size = size * num_possible_cpus(); - total = 0; - /* while experimenting with hash tables with sizes ranging from 10 to - * 1000, it was observed that a bucket can have upto 5 entries. - */ - bucket_size = 5; - -alloc: - /* We cannot do copy_from_user or copy_to_user inside - * the rcu_read_lock. Allocate enough space here. - */ - keys = kvmalloc_array(key_size, bucket_size, GFP_USER | __GFP_NOWARN); - values = kvmalloc_array(value_size, bucket_size, GFP_USER | __GFP_NOWARN); - if (!keys || !values) { - ret = -ENOMEM; - goto after_loop; - } - -again: - bpf_disable_instrumentation(); - rcu_read_lock(); -again_nocopy: - dst_key = keys; - dst_val = values; - b = &htab->buckets[batch]; - head = &b->head; - /* do not grab the lock unless need it (bucket_cnt > 0). */ - if (locked) - flags = htab_lock_bucket(htab, b); - - bucket_cnt = 0; - hlist_nulls_for_each_entry_rcu(l, n, head, hash_node) - bucket_cnt++; - - if (bucket_cnt && !locked) { - locked = true; - goto again_nocopy; - } - - if (bucket_cnt > (max_count - total)) { - if (total == 0) - ret = -ENOSPC; - /* Note that since bucket_cnt > 0 here, it is implicit - * that the locked was grabbed, so release it. - */ - htab_unlock_bucket(htab, b, flags); - rcu_read_unlock(); - bpf_enable_instrumentation(); - goto after_loop; - } - - if (bucket_cnt > bucket_size) { - bucket_size = bucket_cnt; - /* Note that since bucket_cnt > 0 here, it is implicit - * that the locked was grabbed, so release it. - */ - htab_unlock_bucket(htab, b, flags); - rcu_read_unlock(); - bpf_enable_instrumentation(); - kvfree(keys); - kvfree(values); - goto alloc; - } - - /* Next block is only safe to run if you have grabbed the lock */ - if (!locked) - goto next_batch; - - hlist_nulls_for_each_entry_safe(l, n, head, hash_node) { - memcpy(dst_key, l->key, key_size); - - if (is_percpu) { - int off = 0, cpu; - void __percpu *pptr; - - pptr = htab_elem_get_ptr(l, map->key_size); - for_each_possible_cpu(cpu) { - bpf_long_memcpy(dst_val + off, - per_cpu_ptr(pptr, cpu), size); - off += size; - } - } else { - value = l->key + roundup_key_size; - if (elem_map_flags & BPF_F_LOCK) - copy_map_value_locked(map, dst_val, value, - true); - else - copy_map_value(map, dst_val, value); - check_and_init_map_lock(map, dst_val); - } - if (do_delete) { - hlist_nulls_del_rcu(&l->hash_node); - - /* bpf_lru_push_free() will acquire lru_lock, which - * may cause deadlock. See comments in function - * prealloc_lru_pop(). Let us do bpf_lru_push_free() - * after releasing the bucket lock. - */ - if (is_lru_map) { - l->batch_flink = node_to_free; - node_to_free = l; - } else { - free_htab_elem(htab, l); - } - } - dst_key += key_size; - dst_val += value_size; - } - - htab_unlock_bucket(htab, b, flags); - locked = false; - - while (node_to_free) { - l = node_to_free; - node_to_free = node_to_free->batch_flink; - bpf_lru_push_free(&htab->lru, &l->lru_node); - } - -next_batch: - /* If we are not copying data, we can go to next bucket and avoid - * unlocking the rcu. - */ - if (!bucket_cnt && (batch + 1 < htab->n_buckets)) { - batch++; - goto again_nocopy; - } - - rcu_read_unlock(); - bpf_enable_instrumentation(); - if (bucket_cnt && (copy_to_user(ukeys + total * key_size, keys, - key_size * bucket_cnt) || - copy_to_user(uvalues + total * value_size, values, - value_size * bucket_cnt))) { - ret = -EFAULT; - goto after_loop; - } - - total += bucket_cnt; - batch++; - if (batch >= htab->n_buckets) { - ret = -ENOENT; - goto after_loop; - } - goto again; - -after_loop: - if (ret == -EFAULT) - goto out; - - /* copy # of entries and next batch */ - ubatch = u64_to_user_ptr(attr->batch.out_batch); - if (copy_to_user(ubatch, &batch, sizeof(batch)) || - put_user(total, &uattr->batch.count)) - ret = -EFAULT; - -out: - kvfree(keys); - kvfree(values); - return ret; -} - -static int -htab_percpu_map_lookup_batch(struct bpf_map *map, const union bpf_attr *attr, - union bpf_attr __user *uattr) -{ - return __htab_map_lookup_and_delete_batch(map, attr, uattr, false, - false, true); -} - -static int -htab_percpu_map_lookup_and_delete_batch(struct bpf_map *map, - const union bpf_attr *attr, - union bpf_attr __user *uattr) -{ - return __htab_map_lookup_and_delete_batch(map, attr, uattr, true, - false, true); -} - -static int -htab_map_lookup_batch(struct bpf_map *map, const union bpf_attr *attr, - union bpf_attr __user *uattr) -{ - return __htab_map_lookup_and_delete_batch(map, attr, uattr, false, - false, false); -} - -static int -htab_map_lookup_and_delete_batch(struct bpf_map *map, - const union bpf_attr *attr, - union bpf_attr __user *uattr) -{ - return __htab_map_lookup_and_delete_batch(map, attr, uattr, true, - false, false); -} - -static int -htab_lru_percpu_map_lookup_batch(struct bpf_map *map, - const union bpf_attr *attr, - union bpf_attr __user *uattr) -{ - return __htab_map_lookup_and_delete_batch(map, attr, uattr, false, - true, true); -} - -static int -htab_lru_percpu_map_lookup_and_delete_batch(struct bpf_map *map, - const union bpf_attr *attr, - union bpf_attr __user *uattr) -{ - return __htab_map_lookup_and_delete_batch(map, attr, uattr, true, - true, true); -} - -static int -htab_lru_map_lookup_batch(struct bpf_map *map, const union bpf_attr *attr, - union bpf_attr __user *uattr) -{ - return __htab_map_lookup_and_delete_batch(map, attr, uattr, false, - true, false); -} - -static int -htab_lru_map_lookup_and_delete_batch(struct bpf_map *map, - const union bpf_attr *attr, - union bpf_attr __user *uattr) -{ - return __htab_map_lookup_and_delete_batch(map, attr, uattr, true, - true, false); -} - -struct bpf_iter_seq_hash_map_info { - struct bpf_map *map; - struct bpf_htab *htab; - void *percpu_value_buf; // non-zero means percpu hash - u32 bucket_id; - u32 skip_elems; -}; - -static struct htab_elem * -bpf_hash_map_seq_find_next(struct bpf_iter_seq_hash_map_info *info, - struct htab_elem *prev_elem) -{ - const struct bpf_htab *htab = info->htab; - u32 skip_elems = info->skip_elems; - u32 bucket_id = info->bucket_id; - struct hlist_nulls_head *head; - struct hlist_nulls_node *n; - struct htab_elem *elem; - struct bucket *b; - u32 i, count; - - if (bucket_id >= htab->n_buckets) - return NULL; - - /* try to find next elem in the same bucket */ - if (prev_elem) { - /* no update/deletion on this bucket, prev_elem should be still valid - * and we won't skip elements. - */ - n = rcu_dereference_raw(hlist_nulls_next_rcu(&prev_elem->hash_node)); - elem = hlist_nulls_entry_safe(n, struct htab_elem, hash_node); - if (elem) - return elem; - - /* not found, unlock and go to the next bucket */ - b = &htab->buckets[bucket_id++]; - rcu_read_unlock(); - skip_elems = 0; - } - - for (i = bucket_id; i < htab->n_buckets; i++) { - b = &htab->buckets[i]; - rcu_read_lock(); - - count = 0; - head = &b->head; - hlist_nulls_for_each_entry_rcu(elem, n, head, hash_node) { - if (count >= skip_elems) { - info->bucket_id = i; - info->skip_elems = count; - return elem; - } - count++; - } - - rcu_read_unlock(); - skip_elems = 0; - } - - info->bucket_id = i; - info->skip_elems = 0; - return NULL; -} - -static void *bpf_hash_map_seq_start(struct seq_file *seq, loff_t *pos) -{ - struct bpf_iter_seq_hash_map_info *info = seq->private; - struct htab_elem *elem; - - elem = bpf_hash_map_seq_find_next(info, NULL); - if (!elem) - return NULL; - - if (*pos == 0) - ++*pos; - return elem; -} - -static void *bpf_hash_map_seq_next(struct seq_file *seq, void *v, loff_t *pos) -{ - struct bpf_iter_seq_hash_map_info *info = seq->private; - - ++*pos; - ++info->skip_elems; - return bpf_hash_map_seq_find_next(info, v); -} - -static int __bpf_hash_map_seq_show(struct seq_file *seq, struct htab_elem *elem) -{ - struct bpf_iter_seq_hash_map_info *info = seq->private; - u32 roundup_key_size, roundup_value_size; - struct bpf_iter__bpf_map_elem ctx = {}; - struct bpf_map *map = info->map; - struct bpf_iter_meta meta; - int ret = 0, off = 0, cpu; - struct bpf_prog *prog; - void __percpu *pptr; - - meta.seq = seq; - prog = bpf_iter_get_info(&meta, elem == NULL); - if (prog) { - ctx.meta = &meta; - ctx.map = info->map; - if (elem) { - roundup_key_size = round_up(map->key_size, 8); - ctx.key = elem->key; - if (!info->percpu_value_buf) { - ctx.value = elem->key + roundup_key_size; - } else { - roundup_value_size = round_up(map->value_size, 8); - pptr = htab_elem_get_ptr(elem, map->key_size); - for_each_possible_cpu(cpu) { - bpf_long_memcpy(info->percpu_value_buf + off, - per_cpu_ptr(pptr, cpu), - roundup_value_size); - off += roundup_value_size; - } - ctx.value = info->percpu_value_buf; - } - } - ret = bpf_iter_run_prog(prog, &ctx); - } - - return ret; -} - -static int bpf_hash_map_seq_show(struct seq_file *seq, void *v) -{ - return __bpf_hash_map_seq_show(seq, v); -} - -static void bpf_hash_map_seq_stop(struct seq_file *seq, void *v) -{ - if (!v) - (void)__bpf_hash_map_seq_show(seq, NULL); - else - rcu_read_unlock(); -} - -static int bpf_iter_init_hash_map(void *priv_data, - struct bpf_iter_aux_info *aux) -{ - struct bpf_iter_seq_hash_map_info *seq_info = priv_data; - struct bpf_map *map = aux->map; - void *value_buf; - u32 buf_size; - - if (map->map_type == BPF_MAP_TYPE_PERCPU_HASH || - map->map_type == BPF_MAP_TYPE_LRU_PERCPU_HASH) { - buf_size = round_up(map->value_size, 8) * num_possible_cpus(); - value_buf = kmalloc(buf_size, GFP_USER | __GFP_NOWARN); - if (!value_buf) - return -ENOMEM; - - seq_info->percpu_value_buf = value_buf; - } - - bpf_map_inc_with_uref(map); - seq_info->map = map; - seq_info->htab = container_of(map, struct bpf_htab, map); - return 0; -} - -static void bpf_iter_fini_hash_map(void *priv_data) -{ - struct bpf_iter_seq_hash_map_info *seq_info = priv_data; - - bpf_map_put_with_uref(seq_info->map); - kfree(seq_info->percpu_value_buf); -} - -static const struct seq_operations bpf_hash_map_seq_ops = { - .start = bpf_hash_map_seq_start, - .next = bpf_hash_map_seq_next, - .stop = bpf_hash_map_seq_stop, - .show = bpf_hash_map_seq_show, -}; - -static const struct bpf_iter_seq_info iter_seq_info = { - .seq_ops = &bpf_hash_map_seq_ops, - .init_seq_private = bpf_iter_init_hash_map, - .fini_seq_private = bpf_iter_fini_hash_map, - .seq_priv_size = sizeof(struct bpf_iter_seq_hash_map_info), -}; - -static int htab_map_btf_id; const struct bpf_map_ops htab_map_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc_check = htab_map_alloc_check, .map_alloc = htab_map_alloc, .map_free = htab_map_free, @@ -1848,15 +1273,9 @@ const struct bpf_map_ops htab_map_ops = { .map_delete_elem = htab_map_delete_elem, .map_gen_lookup = htab_map_gen_lookup, .map_seq_show_elem = htab_map_seq_show_elem, - BATCH_OPS(htab), - .map_btf_name = "bpf_htab", - .map_btf_id = &htab_map_btf_id, - .iter_seq_info = &iter_seq_info, }; -static int htab_lru_map_btf_id; const struct bpf_map_ops htab_lru_map_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc_check = htab_map_alloc_check, .map_alloc = htab_map_alloc, .map_free = htab_map_free, @@ -1867,10 +1286,6 @@ const struct bpf_map_ops htab_lru_map_ops = { .map_delete_elem = htab_lru_map_delete_elem, .map_gen_lookup = htab_lru_map_gen_lookup, .map_seq_show_elem = htab_map_seq_show_elem, - BATCH_OPS(htab_lru), - .map_btf_name = "bpf_htab", - .map_btf_id = &htab_lru_map_btf_id, - .iter_seq_info = &iter_seq_info, }; /* Called from eBPF program */ @@ -1975,9 +1390,7 @@ static void htab_percpu_map_seq_show_elem(struct bpf_map *map, void *key, rcu_read_unlock(); } -static int htab_percpu_map_btf_id; const struct bpf_map_ops htab_percpu_map_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc_check = htab_map_alloc_check, .map_alloc = htab_map_alloc, .map_free = htab_map_free, @@ -1986,15 +1399,9 @@ const struct bpf_map_ops htab_percpu_map_ops = { .map_update_elem = htab_percpu_map_update_elem, .map_delete_elem = htab_map_delete_elem, .map_seq_show_elem = htab_percpu_map_seq_show_elem, - BATCH_OPS(htab_percpu), - .map_btf_name = "bpf_htab", - .map_btf_id = &htab_percpu_map_btf_id, - .iter_seq_info = &iter_seq_info, }; -static int htab_lru_percpu_map_btf_id; const struct bpf_map_ops htab_lru_percpu_map_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc_check = htab_map_alloc_check, .map_alloc = htab_map_alloc, .map_free = htab_map_free, @@ -2003,10 +1410,6 @@ const struct bpf_map_ops htab_lru_percpu_map_ops = { .map_update_elem = htab_lru_percpu_map_update_elem, .map_delete_elem = htab_lru_map_delete_elem, .map_seq_show_elem = htab_percpu_map_seq_show_elem, - BATCH_OPS(htab_lru_percpu), - .map_btf_name = "bpf_htab", - .map_btf_id = &htab_lru_percpu_map_btf_id, - .iter_seq_info = &iter_seq_info, }; static int fd_htab_map_alloc_check(union bpf_attr *attr) @@ -2105,7 +1508,7 @@ static void *htab_of_map_lookup_elem(struct bpf_map *map, void *key) return READ_ONCE(*inner_map); } -static int htab_of_map_gen_lookup(struct bpf_map *map, +static u32 htab_of_map_gen_lookup(struct bpf_map *map, struct bpf_insn *insn_buf) { struct bpf_insn *insn = insn_buf; @@ -2129,7 +1532,6 @@ static void htab_of_map_free(struct bpf_map *map) fd_htab_map_free(map); } -static int htab_of_maps_map_btf_id; const struct bpf_map_ops htab_of_maps_map_ops = { .map_alloc_check = fd_htab_map_alloc_check, .map_alloc = htab_of_map_alloc, @@ -2142,6 +1544,4 @@ const struct bpf_map_ops htab_of_maps_map_ops = { .map_fd_sys_lookup_elem = bpf_map_fd_sys_lookup_elem, .map_gen_lookup = htab_of_map_gen_lookup, .map_check_btf = map_check_no_btf, - .map_btf_name = "bpf_htab", - .map_btf_id = &htab_of_maps_map_btf_id, }; diff --git a/kernel/bpf/helpers.c b/kernel/bpf/helpers.c index fdc94de89086..5859edfb5ad9 100644 --- a/kernel/bpf/helpers.c +++ b/kernel/bpf/helpers.c @@ -3,7 +3,6 @@ */ #include #include -#include #include #include #include @@ -12,9 +11,6 @@ #include #include #include -#include -#include -#include #include "../../lib/kstrtox.h" @@ -24,12 +20,12 @@ * * Different map implementations will rely on rcu in map methods * lookup/update/delete, therefore eBPF programs must run under rcu lock - * if program is allowed to access maps, so check rcu_read_lock_held() or - * rcu_read_lock_trace_held() in all three functions. + * if program is allowed to access maps, so check rcu_read_lock_held in + * all three functions. */ BPF_CALL_2(bpf_map_lookup_elem, struct bpf_map *, map, void *, key) { - WARN_ON_ONCE(!rcu_read_lock_held() && !rcu_read_lock_trace_held()); + WARN_ON_ONCE(!rcu_read_lock_held()); return (unsigned long) map->ops->map_lookup_elem(map, key); } @@ -45,7 +41,7 @@ const struct bpf_func_proto bpf_map_lookup_elem_proto = { BPF_CALL_4(bpf_map_update_elem, struct bpf_map *, map, void *, key, void *, value, u64, flags) { - WARN_ON_ONCE(!rcu_read_lock_held() && !rcu_read_lock_trace_held()); + WARN_ON_ONCE(!rcu_read_lock_held()); return map->ops->map_update_elem(map, key, value, flags); } @@ -62,7 +58,7 @@ const struct bpf_func_proto bpf_map_update_elem_proto = { BPF_CALL_2(bpf_map_delete_elem, struct bpf_map *, map, void *, key) { - WARN_ON_ONCE(!rcu_read_lock_held() && !rcu_read_lock_trace_held()); + WARN_ON_ONCE(!rcu_read_lock_held()); return map->ops->map_delete_elem(map, key); } @@ -338,23 +334,12 @@ void copy_map_value_locked(struct bpf_map *map, void *dst, void *src, preempt_enable(); } -BPF_CALL_0(bpf_jiffies64) -{ - return get_jiffies_64(); -} - -const struct bpf_func_proto bpf_jiffies64_proto = { - .func = bpf_jiffies64, - .gpl_only = false, - .ret_type = RET_INTEGER, -}; - #ifdef CONFIG_CGROUPS BPF_CALL_0(bpf_get_current_cgroup_id) { struct cgroup *cgrp = task_dfl_cgroup(current); - return cgroup_id(cgrp); + return cgrp->kn->id.id; } const struct bpf_func_proto bpf_get_current_cgroup_id_proto = { @@ -363,27 +348,9 @@ const struct bpf_func_proto bpf_get_current_cgroup_id_proto = { .ret_type = RET_INTEGER, }; -BPF_CALL_1(bpf_get_current_ancestor_cgroup_id, int, ancestor_level) -{ - struct cgroup *cgrp = task_dfl_cgroup(current); - struct cgroup *ancestor; - - ancestor = cgroup_ancestor(cgrp, ancestor_level); - if (!ancestor) - return 0; - return cgroup_id(ancestor); -} - -const struct bpf_func_proto bpf_get_current_ancestor_cgroup_id_proto = { - .func = bpf_get_current_ancestor_cgroup_id, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_ANYTHING, -}; - #ifdef CONFIG_CGROUP_BPF -DECLARE_PER_CPU(struct bpf_cgroup_storage_info, - bpf_cgroup_storage_info[BPF_CGROUP_STORAGE_NEST_MAX]); +DECLARE_PER_CPU(struct bpf_cgroup_storage*, + bpf_cgroup_storage[MAX_BPF_CGROUP_STORAGE_TYPE]); BPF_CALL_2(bpf_get_local_storage, struct bpf_map *, map, u64, flags) { @@ -392,17 +359,10 @@ BPF_CALL_2(bpf_get_local_storage, struct bpf_map *, map, u64, flags) * verifier checks that its value is correct. */ enum bpf_cgroup_storage_type stype = cgroup_storage_type(map); - struct bpf_cgroup_storage *storage = NULL; + struct bpf_cgroup_storage *storage; void *ptr; - int i; - for (i = BPF_CGROUP_STORAGE_NEST_MAX - 1; i >= 0; i--) { - if (likely(this_cpu_read(bpf_cgroup_storage_info[i].task) != current)) - continue; - - storage = this_cpu_read(bpf_cgroup_storage_info[i].storage[stype]); - break; - } + storage = this_cpu_read(bpf_cgroup_storage[stype]); if (stype == BPF_CGROUP_STORAGE_SHARED) ptr = &READ_ONCE(storage->buf)->data[0]; @@ -549,211 +509,3 @@ const struct bpf_func_proto bpf_strtoul_proto = { .arg4_type = ARG_PTR_TO_LONG, }; #endif - -BPF_CALL_4(bpf_get_ns_current_pid_tgid, u64, dev, u64, ino, - struct bpf_pidns_info *, nsdata, u32, size) -{ - struct task_struct *task = current; - struct pid_namespace *pidns; - int err = -EINVAL; - - if (unlikely(size != sizeof(struct bpf_pidns_info))) - goto clear; - - if (unlikely((u64)(dev_t)dev != dev)) - goto clear; - - if (unlikely(!task)) - goto clear; - - pidns = task_active_pid_ns(task); - if (unlikely(!pidns)) { - err = -ENOENT; - goto clear; - } - - if (!ns_match(&pidns->ns, (dev_t)dev, ino)) - goto clear; - - nsdata->pid = task_pid_nr_ns(task, pidns); - nsdata->tgid = task_tgid_nr_ns(task, pidns); - return 0; -clear: - memset((void *)nsdata, 0, (size_t) size); - return err; -} - -const struct bpf_func_proto bpf_get_ns_current_pid_tgid_proto = { - .func = bpf_get_ns_current_pid_tgid, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_ANYTHING, - .arg2_type = ARG_ANYTHING, - .arg3_type = ARG_PTR_TO_UNINIT_MEM, - .arg4_type = ARG_CONST_SIZE, -}; - -static const struct bpf_func_proto bpf_get_raw_smp_processor_id_proto = { - .func = bpf_get_raw_cpu_id, - .gpl_only = false, - .ret_type = RET_INTEGER, -}; - -BPF_CALL_5(bpf_event_output_data, void *, ctx, struct bpf_map *, map, - u64, flags, void *, data, u64, size) -{ - if (unlikely(flags & ~(BPF_F_INDEX_MASK))) - return -EINVAL; - - return bpf_event_output(map, flags, data, size, NULL, 0, NULL); -} - -const struct bpf_func_proto bpf_event_output_data_proto = { - .func = bpf_event_output_data, - .gpl_only = true, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX, - .arg2_type = ARG_CONST_MAP_PTR, - .arg3_type = ARG_ANYTHING, - .arg4_type = ARG_PTR_TO_MEM, - .arg5_type = ARG_CONST_SIZE_OR_ZERO, -}; - -BPF_CALL_3(bpf_copy_from_user, void *, dst, u32, size, - const void __user *, user_ptr) -{ - int ret = copy_from_user(dst, user_ptr, size); - - if (unlikely(ret)) { - memset(dst, 0, size); - ret = -EFAULT; - } - - return ret; -} - -const struct bpf_func_proto bpf_copy_from_user_proto = { - .func = bpf_copy_from_user, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_UNINIT_MEM, - .arg2_type = ARG_CONST_SIZE_OR_ZERO, - .arg3_type = ARG_ANYTHING, -}; - -BPF_CALL_2(bpf_per_cpu_ptr, const void *, ptr, u32, cpu) -{ - if (cpu >= nr_cpu_ids) - return (unsigned long)NULL; - - return (unsigned long)per_cpu_ptr((const void __percpu *)ptr, cpu); -} - -const struct bpf_func_proto bpf_per_cpu_ptr_proto = { - .func = bpf_per_cpu_ptr, - .gpl_only = false, - .ret_type = RET_PTR_TO_MEM_OR_BTF_ID_OR_NULL, - .arg1_type = ARG_PTR_TO_PERCPU_BTF_ID, - .arg2_type = ARG_ANYTHING, -}; - -BPF_CALL_1(bpf_this_cpu_ptr, const void *, percpu_ptr) -{ - return (unsigned long)this_cpu_ptr((const void __percpu *)percpu_ptr); -} - -const struct bpf_func_proto bpf_this_cpu_ptr_proto = { - .func = bpf_this_cpu_ptr, - .gpl_only = false, - .ret_type = RET_PTR_TO_MEM_OR_BTF_ID, - .arg1_type = ARG_PTR_TO_PERCPU_BTF_ID, -}; - -const struct bpf_func_proto bpf_get_current_task_proto __weak; -const struct bpf_func_proto bpf_probe_read_user_proto __weak; -const struct bpf_func_proto bpf_probe_read_user_str_proto __weak; -const struct bpf_func_proto bpf_probe_read_kernel_proto __weak; -const struct bpf_func_proto bpf_probe_read_kernel_str_proto __weak; - -const struct bpf_func_proto * -bpf_base_func_proto(enum bpf_func_id func_id) -{ - switch (func_id) { - case BPF_FUNC_map_lookup_elem: - return &bpf_map_lookup_elem_proto; - case BPF_FUNC_map_update_elem: - return &bpf_map_update_elem_proto; - case BPF_FUNC_map_delete_elem: - return &bpf_map_delete_elem_proto; - case BPF_FUNC_map_push_elem: - return &bpf_map_push_elem_proto; - case BPF_FUNC_map_pop_elem: - return &bpf_map_pop_elem_proto; - case BPF_FUNC_map_peek_elem: - return &bpf_map_peek_elem_proto; - case BPF_FUNC_get_prandom_u32: - return &bpf_get_prandom_u32_proto; - case BPF_FUNC_get_smp_processor_id: - return &bpf_get_raw_smp_processor_id_proto; - case BPF_FUNC_get_numa_node_id: - return &bpf_get_numa_node_id_proto; - case BPF_FUNC_tail_call: - return &bpf_tail_call_proto; - case BPF_FUNC_ktime_get_ns: - return &bpf_ktime_get_ns_proto; - case BPF_FUNC_ktime_get_boot_ns: - return &bpf_ktime_get_boot_ns_proto; - case BPF_FUNC_ringbuf_output: - return &bpf_ringbuf_output_proto; - case BPF_FUNC_ringbuf_reserve: - return &bpf_ringbuf_reserve_proto; - case BPF_FUNC_ringbuf_submit: - return &bpf_ringbuf_submit_proto; - case BPF_FUNC_ringbuf_discard: - return &bpf_ringbuf_discard_proto; - case BPF_FUNC_ringbuf_query: - return &bpf_ringbuf_query_proto; - default: - break; - } - - if (!bpf_capable()) - return NULL; - - switch (func_id) { - case BPF_FUNC_spin_lock: - return &bpf_spin_lock_proto; - case BPF_FUNC_spin_unlock: - return &bpf_spin_unlock_proto; - case BPF_FUNC_jiffies64: - return &bpf_jiffies64_proto; - case BPF_FUNC_per_cpu_ptr: - return &bpf_per_cpu_ptr_proto; - case BPF_FUNC_this_cpu_ptr: - return &bpf_this_cpu_ptr_proto; - default: - break; - } - - if (!perfmon_capable()) - return NULL; - - switch (func_id) { - case BPF_FUNC_trace_printk: - return bpf_get_trace_printk_proto(); - case BPF_FUNC_get_current_task: - return &bpf_get_current_task_proto; - case BPF_FUNC_probe_read_user: - return &bpf_probe_read_user_proto; - case BPF_FUNC_probe_read_kernel: - return &bpf_probe_read_kernel_proto; - case BPF_FUNC_probe_read_user_str: - return &bpf_probe_read_user_str_proto; - case BPF_FUNC_probe_read_kernel_str: - return &bpf_probe_read_kernel_str_proto; - case BPF_FUNC_snprintf_btf: - return &bpf_snprintf_btf_proto; - default: - return NULL; - } -} diff --git a/kernel/bpf/inode.c b/kernel/bpf/inode.c index 99fc3532709a..375d93eb71c7 100644 --- a/kernel/bpf/inode.c +++ b/kernel/bpf/inode.c @@ -20,26 +20,21 @@ #include #include #include -#include "preload/bpf_preload.h" enum bpf_type { BPF_TYPE_UNSPEC = 0, BPF_TYPE_PROG, BPF_TYPE_MAP, - BPF_TYPE_LINK, }; static void *bpf_any_get(void *raw, enum bpf_type type) { switch (type) { case BPF_TYPE_PROG: - bpf_prog_inc(raw); + raw = bpf_prog_inc(raw); break; case BPF_TYPE_MAP: - bpf_map_inc_with_uref(raw); - break; - case BPF_TYPE_LINK: - bpf_link_inc(raw); + raw = bpf_map_inc(raw, true); break; default: WARN_ON_ONCE(1); @@ -58,9 +53,6 @@ static void bpf_any_put(void *raw, enum bpf_type type) case BPF_TYPE_MAP: bpf_map_put_with_uref(raw); break; - case BPF_TYPE_LINK: - bpf_link_put(raw); - break; default: WARN_ON_ONCE(1); break; @@ -71,32 +63,20 @@ static void *bpf_fd_probe_obj(u32 ufd, enum bpf_type *type) { void *raw; + *type = BPF_TYPE_MAP; raw = bpf_map_get_with_uref(ufd); - if (!IS_ERR(raw)) { - *type = BPF_TYPE_MAP; - return raw; - } - - raw = bpf_prog_get(ufd); - if (!IS_ERR(raw)) { + if (IS_ERR(raw)) { *type = BPF_TYPE_PROG; - return raw; + raw = bpf_prog_get(ufd); } - raw = bpf_link_get_from_fd(ufd); - if (!IS_ERR(raw)) { - *type = BPF_TYPE_LINK; - return raw; - } - - return ERR_PTR(-EINVAL); + return raw; } static const struct inode_operations bpf_dir_iops; static const struct inode_operations bpf_prog_iops = { }; static const struct inode_operations bpf_map_iops = { }; -static const struct inode_operations bpf_link_iops = { }; static struct inode *bpf_get_inode(struct super_block *sb, const struct inode *dir, @@ -134,8 +114,6 @@ static int bpf_inode_type(const struct inode *inode, enum bpf_type *type) *type = BPF_TYPE_PROG; else if (inode->i_op == &bpf_map_iops) *type = BPF_TYPE_MAP; - else if (inode->i_op == &bpf_link_iops) - *type = BPF_TYPE_LINK; else return -EACCES; @@ -359,23 +337,13 @@ static int bpf_mkmap(struct dentry *dentry, umode_t mode, void *arg) &bpffs_map_fops : &bpffs_obj_fops); } -static int bpf_mklink(struct dentry *dentry, umode_t mode, void *arg) -{ - struct bpf_link *link = arg; - - return bpf_mkobj_ops(dentry, mode, arg, &bpf_link_iops, - bpf_link_is_iter(link) ? - &bpf_iter_fops : &bpffs_obj_fops); -} - static struct dentry * bpf_lookup(struct inode *dir, struct dentry *dentry, unsigned flags) { /* Dots in names (e.g. "/sys/fs/bpf/foo.bar") are reserved for future - * extensions. That allows popoulate_bpffs() create special files. + * extensions. */ - if ((dir->i_mode & S_IALLUGO) && - strchr(dentry->d_name.name, '.')) + if (strchr(dentry->d_name.name, '.')) return ERR_PTR(-EPERM); return simple_lookup(dir, dentry, flags); @@ -413,28 +381,7 @@ static const struct inode_operations bpf_dir_iops = { .unlink = simple_unlink, }; -/* pin iterator link into bpffs */ -static int bpf_iter_link_pin_kernel(struct dentry *parent, - const char *name, struct bpf_link *link) -{ - umode_t mode = S_IFREG | S_IRUSR; - struct dentry *dentry; - int ret; - - inode_lock(parent->d_inode); - dentry = lookup_one_len(name, parent, strlen(name)); - if (IS_ERR(dentry)) { - inode_unlock(parent->d_inode); - return PTR_ERR(dentry); - } - ret = bpf_mkobj_ops(dentry, mode, link, &bpf_link_iops, - &bpf_iter_fops); - dput(dentry); - inode_unlock(parent->d_inode); - return ret; -} - -static int bpf_obj_do_pin(const char __user *pathname, void *raw, +static int bpf_obj_do_pin(const struct filename *pathname, void *raw, enum bpf_type type) { struct dentry *dentry; @@ -443,7 +390,7 @@ static int bpf_obj_do_pin(const char __user *pathname, void *raw, umode_t mode; int ret; - dentry = user_path_create(AT_FDCWD, pathname, &path, 0); + dentry = kern_path_create(AT_FDCWD, pathname->name, &path, 0); if (IS_ERR(dentry)) return PTR_ERR(dentry); @@ -466,9 +413,6 @@ static int bpf_obj_do_pin(const char __user *pathname, void *raw, case BPF_TYPE_MAP: ret = vfs_mkobj(dentry, mode, bpf_mkmap, raw); break; - case BPF_TYPE_LINK: - ret = vfs_mkobj(dentry, mode, bpf_mklink, raw); - break; default: ret = -EPERM; } @@ -479,22 +423,30 @@ out: int bpf_obj_pin_user(u32 ufd, const char __user *pathname) { + struct filename *pname; enum bpf_type type; void *raw; int ret; - raw = bpf_fd_probe_obj(ufd, &type); - if (IS_ERR(raw)) - return PTR_ERR(raw); + pname = getname(pathname); + if (IS_ERR(pname)) + return PTR_ERR(pname); - ret = bpf_obj_do_pin(pathname, raw, type); + raw = bpf_fd_probe_obj(ufd, &type); + if (IS_ERR(raw)) { + ret = PTR_ERR(raw); + goto out; + } + + ret = bpf_obj_do_pin(pname, raw, type); if (ret != 0) bpf_any_put(raw, type); - +out: + putname(pname); return ret; } -static void *bpf_obj_do_get(const char __user *pathname, +static void *bpf_obj_do_get(const struct filename *pathname, enum bpf_type *type, int flags) { struct inode *inode; @@ -502,7 +454,7 @@ static void *bpf_obj_do_get(const char __user *pathname, void *raw; int ret; - ret = user_path_at(AT_FDCWD, pathname, LOOKUP_FOLLOW, &path); + ret = kern_path(pathname->name, LOOKUP_FOLLOW, &path); if (ret) return ERR_PTR(ret); @@ -529,29 +481,36 @@ out: int bpf_obj_get_user(const char __user *pathname, int flags) { enum bpf_type type = BPF_TYPE_UNSPEC; + struct filename *pname; + int ret = -ENOENT; int f_flags; void *raw; - int ret; f_flags = bpf_get_file_flag(flags); if (f_flags < 0) return f_flags; - raw = bpf_obj_do_get(pathname, &type, f_flags); - if (IS_ERR(raw)) - return PTR_ERR(raw); + pname = getname(pathname); + if (IS_ERR(pname)) + return PTR_ERR(pname); + + raw = bpf_obj_do_get(pname, &type, f_flags); + if (IS_ERR(raw)) { + ret = PTR_ERR(raw); + goto out; + } if (type == BPF_TYPE_PROG) ret = bpf_prog_new_fd(raw); else if (type == BPF_TYPE_MAP) ret = bpf_map_new_fd(raw, f_flags); - else if (type == BPF_TYPE_LINK) - ret = (f_flags != O_RDWR) ? -EINVAL : bpf_link_new_fd(raw); else - return -ENOENT; + goto out; if (ret < 0) bpf_any_put(raw, type); +out: + putname(pname); return ret; } @@ -564,8 +523,6 @@ static struct bpf_prog *__get_prog_inode(struct inode *inode, enum bpf_prog_type if (inode->i_op == &bpf_map_iops) return ERR_PTR(-EINVAL); - if (inode->i_op == &bpf_link_iops) - return ERR_PTR(-EINVAL); if (inode->i_op != &bpf_prog_iops) return ERR_PTR(-EACCES); @@ -578,8 +535,7 @@ static struct bpf_prog *__get_prog_inode(struct inode *inode, enum bpf_prog_type if (!bpf_prog_get_ok(prog, &type, false)) return ERR_PTR(-EINVAL); - bpf_prog_inc(prog); - return prog; + return bpf_prog_inc(prog); } struct bpf_prog *bpf_prog_get_type_path(const char *name, enum bpf_prog_type type) @@ -668,91 +624,6 @@ static int bpf_parse_param(struct fs_context *fc, struct fs_parameter *param) return 0; } -struct bpf_preload_ops *bpf_preload_ops; -EXPORT_SYMBOL_GPL(bpf_preload_ops); - -static bool bpf_preload_mod_get(void) -{ - /* If bpf_preload.ko wasn't loaded earlier then load it now. - * When bpf_preload is built into vmlinux the module's __init - * function will populate it. - */ - if (!bpf_preload_ops) { - request_module("bpf_preload"); - if (!bpf_preload_ops) - return false; - } - /* And grab the reference, so the module doesn't disappear while the - * kernel is interacting with the kernel module and its UMD. - */ - if (!try_module_get(bpf_preload_ops->owner)) { - pr_err("bpf_preload module get failed.\n"); - return false; - } - return true; -} - -static void bpf_preload_mod_put(void) -{ - if (bpf_preload_ops) - /* now user can "rmmod bpf_preload" if necessary */ - module_put(bpf_preload_ops->owner); -} - -static DEFINE_MUTEX(bpf_preload_lock); - -static int populate_bpffs(struct dentry *parent) -{ - struct bpf_preload_info objs[BPF_PRELOAD_LINKS] = {}; - struct bpf_link *links[BPF_PRELOAD_LINKS] = {}; - int err = 0, i; - - /* grab the mutex to make sure the kernel interactions with bpf_preload - * UMD are serialized - */ - mutex_lock(&bpf_preload_lock); - - /* if bpf_preload.ko wasn't built into vmlinux then load it */ - if (!bpf_preload_mod_get()) - goto out; - - if (!bpf_preload_ops->info.tgid) { - /* preload() will start UMD that will load BPF iterator programs */ - err = bpf_preload_ops->preload(objs); - if (err) - goto out_put; - for (i = 0; i < BPF_PRELOAD_LINKS; i++) { - links[i] = bpf_link_by_id(objs[i].link_id); - if (IS_ERR(links[i])) { - err = PTR_ERR(links[i]); - goto out_put; - } - } - for (i = 0; i < BPF_PRELOAD_LINKS; i++) { - err = bpf_iter_link_pin_kernel(parent, - objs[i].link_name, links[i]); - if (err) - goto out_put; - /* do not unlink successfully pinned links even - * if later link fails to pin - */ - links[i] = NULL; - } - /* finish() will tell UMD process to exit */ - err = bpf_preload_ops->finish(); - if (err) - goto out_put; - } -out_put: - bpf_preload_mod_put(); -out: - mutex_unlock(&bpf_preload_lock); - for (i = 0; i < BPF_PRELOAD_LINKS && err; i++) - if (!IS_ERR_OR_NULL(links[i])) - bpf_link_put(links[i]); - return err; -} - static int bpf_fill_super(struct super_block *sb, struct fs_context *fc) { static const struct tree_descr bpf_rfiles[] = { { "" } }; @@ -769,8 +640,8 @@ static int bpf_fill_super(struct super_block *sb, struct fs_context *fc) inode = sb->s_root->d_inode; inode->i_op = &bpf_dir_iops; inode->i_mode &= ~S_IALLUGO; - populate_bpffs(sb->s_root); inode->i_mode |= S_ISVTX | opts->mode; + return 0; } @@ -820,8 +691,6 @@ static int __init bpf_init(void) { int ret; - mutex_init(&bpf_preload_lock); - ret = sysfs_create_mount_point(fs_kobj, "bpf"); if (ret) return ret; diff --git a/kernel/bpf/local_storage.c b/kernel/bpf/local_storage.c index 849ea1d39af5..addd6fdceec8 100644 --- a/kernel/bpf/local_storage.c +++ b/kernel/bpf/local_storage.c @@ -9,13 +9,10 @@ #include #include +DEFINE_PER_CPU(struct bpf_cgroup_storage*, bpf_cgroup_storage[MAX_BPF_CGROUP_STORAGE_TYPE]); + #ifdef CONFIG_CGROUP_BPF -DEFINE_PER_CPU(struct bpf_cgroup_storage_info, - bpf_cgroup_storage_info[BPF_CGROUP_STORAGE_NEST_MAX]); - -#include "../cgroup/cgroup-internal.h" - #define LOCAL_STORAGE_CREATE_FLAG_MASK \ (BPF_F_NUMA_NODE | BPF_F_ACCESS_MASK) @@ -23,6 +20,7 @@ struct bpf_cgroup_storage_map { struct bpf_map map; spinlock_t lock; + struct bpf_prog *prog; struct rb_root root; struct list_head list; }; @@ -32,41 +30,24 @@ static struct bpf_cgroup_storage_map *map_to_storage(struct bpf_map *map) return container_of(map, struct bpf_cgroup_storage_map, map); } -static bool attach_type_isolated(const struct bpf_map *map) +static int bpf_cgroup_storage_key_cmp( + const struct bpf_cgroup_storage_key *key1, + const struct bpf_cgroup_storage_key *key2) { - return map->key_size == sizeof(struct bpf_cgroup_storage_key); -} - -static int bpf_cgroup_storage_key_cmp(const struct bpf_cgroup_storage_map *map, - const void *_key1, const void *_key2) -{ - if (attach_type_isolated(&map->map)) { - const struct bpf_cgroup_storage_key *key1 = _key1; - const struct bpf_cgroup_storage_key *key2 = _key2; - - if (key1->cgroup_inode_id < key2->cgroup_inode_id) - return -1; - else if (key1->cgroup_inode_id > key2->cgroup_inode_id) - return 1; - else if (key1->attach_type < key2->attach_type) - return -1; - else if (key1->attach_type > key2->attach_type) - return 1; - } else { - const __u64 *cgroup_inode_id1 = _key1; - const __u64 *cgroup_inode_id2 = _key2; - - if (*cgroup_inode_id1 < *cgroup_inode_id2) - return -1; - else if (*cgroup_inode_id1 > *cgroup_inode_id2) - return 1; - } + if (key1->cgroup_inode_id < key2->cgroup_inode_id) + return -1; + else if (key1->cgroup_inode_id > key2->cgroup_inode_id) + return 1; + else if (key1->attach_type < key2->attach_type) + return -1; + else if (key1->attach_type > key2->attach_type) + return 1; return 0; } -struct bpf_cgroup_storage * -cgroup_storage_lookup(struct bpf_cgroup_storage_map *map, - void *key, bool locked) +static struct bpf_cgroup_storage *cgroup_storage_lookup( + struct bpf_cgroup_storage_map *map, struct bpf_cgroup_storage_key *key, + bool locked) { struct rb_root *root = &map->root; struct rb_node *node; @@ -80,7 +61,7 @@ cgroup_storage_lookup(struct bpf_cgroup_storage_map *map, storage = container_of(node, struct bpf_cgroup_storage, node); - switch (bpf_cgroup_storage_key_cmp(map, key, &storage->key)) { + switch (bpf_cgroup_storage_key_cmp(key, &storage->key)) { case -1: node = node->rb_left; break; @@ -112,7 +93,7 @@ static int cgroup_storage_insert(struct bpf_cgroup_storage_map *map, this = container_of(*new, struct bpf_cgroup_storage, node); parent = *new; - switch (bpf_cgroup_storage_key_cmp(map, &storage->key, &this->key)) { + switch (bpf_cgroup_storage_key_cmp(&storage->key, &this->key)) { case -1: new = &((*new)->rb_left); break; @@ -130,9 +111,10 @@ static int cgroup_storage_insert(struct bpf_cgroup_storage_map *map, return 0; } -static void *cgroup_storage_lookup_elem(struct bpf_map *_map, void *key) +static void *cgroup_storage_lookup_elem(struct bpf_map *_map, void *_key) { struct bpf_cgroup_storage_map *map = map_to_storage(_map); + struct bpf_cgroup_storage_key *key = _key; struct bpf_cgroup_storage *storage; storage = cgroup_storage_lookup(map, key, false); @@ -142,13 +124,17 @@ static void *cgroup_storage_lookup_elem(struct bpf_map *_map, void *key) return &READ_ONCE(storage->buf)->data[0]; } -static int cgroup_storage_update_elem(struct bpf_map *map, void *key, +static int cgroup_storage_update_elem(struct bpf_map *map, void *_key, void *value, u64 flags) { + struct bpf_cgroup_storage_key *key = _key; struct bpf_cgroup_storage *storage; struct bpf_storage_buffer *new; - if (unlikely(flags & ~(BPF_F_LOCK | BPF_EXIST))) + if (unlikely(flags & ~(BPF_F_LOCK | BPF_EXIST | BPF_NOEXIST))) + return -EINVAL; + + if (unlikely(flags & BPF_NOEXIST)) return -EINVAL; if (unlikely((flags & BPF_F_LOCK) && @@ -181,10 +167,11 @@ static int cgroup_storage_update_elem(struct bpf_map *map, void *key, return 0; } -int bpf_percpu_cgroup_storage_copy(struct bpf_map *_map, void *key, +int bpf_percpu_cgroup_storage_copy(struct bpf_map *_map, void *_key, void *value) { struct bpf_cgroup_storage_map *map = map_to_storage(_map); + struct bpf_cgroup_storage_key *key = _key; struct bpf_cgroup_storage *storage; int cpu, off = 0; u32 size; @@ -210,10 +197,11 @@ int bpf_percpu_cgroup_storage_copy(struct bpf_map *_map, void *key, return 0; } -int bpf_percpu_cgroup_storage_update(struct bpf_map *_map, void *key, +int bpf_percpu_cgroup_storage_update(struct bpf_map *_map, void *_key, void *value, u64 map_flags) { struct bpf_cgroup_storage_map *map = map_to_storage(_map); + struct bpf_cgroup_storage_key *key = _key; struct bpf_cgroup_storage *storage; int cpu, off = 0; u32 size; @@ -244,10 +232,12 @@ int bpf_percpu_cgroup_storage_update(struct bpf_map *_map, void *key, return 0; } -static int cgroup_storage_get_next_key(struct bpf_map *_map, void *key, +static int cgroup_storage_get_next_key(struct bpf_map *_map, void *_key, void *_next_key) { struct bpf_cgroup_storage_map *map = map_to_storage(_map); + struct bpf_cgroup_storage_key *key = _key; + struct bpf_cgroup_storage_key *next = _next_key; struct bpf_cgroup_storage *storage; spin_lock_bh(&map->lock); @@ -260,23 +250,17 @@ static int cgroup_storage_get_next_key(struct bpf_map *_map, void *key, if (!storage) goto enoent; - storage = list_next_entry(storage, list_map); + storage = list_next_entry(storage, list); if (!storage) goto enoent; } else { storage = list_first_entry(&map->list, - struct bpf_cgroup_storage, list_map); + struct bpf_cgroup_storage, list); } spin_unlock_bh(&map->lock); - - if (attach_type_isolated(&map->map)) { - struct bpf_cgroup_storage_key *next = _next_key; - *next = storage->key; - } else { - __u64 *next = _next_key; - *next = storage->key.cgroup_inode_id; - } + next->attach_type = storage->key.attach_type; + next->cgroup_inode_id = storage->key.cgroup_inode_id; return 0; enoent: @@ -291,8 +275,7 @@ static struct bpf_map *cgroup_storage_map_alloc(union bpf_attr *attr) struct bpf_map_memory mem; int ret; - if (attr->key_size != sizeof(struct bpf_cgroup_storage_key) && - attr->key_size != sizeof(__u64)) + if (attr->key_size != sizeof(struct bpf_cgroup_storage_key)) return ERR_PTR(-EINVAL); if (attr->value_size == 0) @@ -335,17 +318,6 @@ static struct bpf_map *cgroup_storage_map_alloc(union bpf_attr *attr) static void cgroup_storage_map_free(struct bpf_map *_map) { struct bpf_cgroup_storage_map *map = map_to_storage(_map); - struct list_head *storages = &map->list; - struct bpf_cgroup_storage *storage, *stmp; - - mutex_lock(&cgroup_mutex); - - list_for_each_entry_safe(storage, stmp, storages, list_map) { - bpf_cgroup_storage_unlink(storage); - bpf_cgroup_storage_free(storage); - } - - mutex_unlock(&cgroup_mutex); WARN_ON(!RB_EMPTY_ROOT(&map->root)); WARN_ON(!list_empty(&map->list)); @@ -363,63 +335,49 @@ static int cgroup_storage_check_btf(const struct bpf_map *map, const struct btf_type *key_type, const struct btf_type *value_type) { - if (attach_type_isolated(map)) { - struct btf_member *m; - u32 offset, size; + struct btf_member *m; + u32 offset, size; - /* Key is expected to be of struct bpf_cgroup_storage_key type, - * which is: - * struct bpf_cgroup_storage_key { - * __u64 cgroup_inode_id; - * __u32 attach_type; - * }; - */ + /* Key is expected to be of struct bpf_cgroup_storage_key type, + * which is: + * struct bpf_cgroup_storage_key { + * __u64 cgroup_inode_id; + * __u32 attach_type; + * }; + */ - /* - * Key_type must be a structure with two fields. - */ - if (BTF_INFO_KIND(key_type->info) != BTF_KIND_STRUCT || - BTF_INFO_VLEN(key_type->info) != 2) - return -EINVAL; + /* + * Key_type must be a structure with two fields. + */ + if (BTF_INFO_KIND(key_type->info) != BTF_KIND_STRUCT || + BTF_INFO_VLEN(key_type->info) != 2) + return -EINVAL; - /* - * The first field must be a 64 bit integer at 0 offset. - */ - m = (struct btf_member *)(key_type + 1); - size = FIELD_SIZEOF(struct bpf_cgroup_storage_key, cgroup_inode_id); - if (!btf_member_is_reg_int(btf, key_type, m, 0, size)) - return -EINVAL; + /* + * The first field must be a 64 bit integer at 0 offset. + */ + m = (struct btf_member *)(key_type + 1); + size = FIELD_SIZEOF(struct bpf_cgroup_storage_key, cgroup_inode_id); + if (!btf_member_is_reg_int(btf, key_type, m, 0, size)) + return -EINVAL; - /* - * The second field must be a 32 bit integer at 64 bit offset. - */ - m++; - offset = offsetof(struct bpf_cgroup_storage_key, attach_type); - size = FIELD_SIZEOF(struct bpf_cgroup_storage_key, attach_type); - if (!btf_member_is_reg_int(btf, key_type, m, offset, size)) - return -EINVAL; - } else { - u32 int_data; - - /* - * Key is expected to be u64, which stores the cgroup_inode_id - */ - - if (BTF_INFO_KIND(key_type->info) != BTF_KIND_INT) - return -EINVAL; - - int_data = *(u32 *)(key_type + 1); - if (BTF_INT_BITS(int_data) != 64 || BTF_INT_OFFSET(int_data)) - return -EINVAL; - } + /* + * The second field must be a 32 bit integer at 64 bit offset. + */ + m++; + offset = offsetof(struct bpf_cgroup_storage_key, attach_type); + size = FIELD_SIZEOF(struct bpf_cgroup_storage_key, attach_type); + if (!btf_member_is_reg_int(btf, key_type, m, offset, size)) + return -EINVAL; return 0; } -static void cgroup_storage_seq_show_elem(struct bpf_map *map, void *key, +static void cgroup_storage_seq_show_elem(struct bpf_map *map, void *_key, struct seq_file *m) { enum bpf_cgroup_storage_type stype = cgroup_storage_type(map); + struct bpf_cgroup_storage_key *key = _key; struct bpf_cgroup_storage *storage; int cpu; @@ -451,7 +409,6 @@ static void cgroup_storage_seq_show_elem(struct bpf_map *map, void *key, rcu_read_unlock(); } -static int cgroup_storage_map_btf_id; const struct bpf_map_ops cgroup_storage_map_ops = { .map_alloc = cgroup_storage_map_alloc, .map_free = cgroup_storage_map_free, @@ -461,20 +418,43 @@ const struct bpf_map_ops cgroup_storage_map_ops = { .map_delete_elem = cgroup_storage_delete_elem, .map_check_btf = cgroup_storage_check_btf, .map_seq_show_elem = cgroup_storage_seq_show_elem, - .map_btf_name = "bpf_cgroup_storage_map", - .map_btf_id = &cgroup_storage_map_btf_id, }; -int bpf_cgroup_storage_assign(struct bpf_prog_aux *aux, struct bpf_map *_map) +int bpf_cgroup_storage_assign(struct bpf_prog *prog, struct bpf_map *_map) { enum bpf_cgroup_storage_type stype = cgroup_storage_type(_map); + struct bpf_cgroup_storage_map *map = map_to_storage(_map); + int ret = -EBUSY; - if (aux->cgroup_storage[stype] && - aux->cgroup_storage[stype] != _map) - return -EBUSY; + spin_lock_bh(&map->lock); - aux->cgroup_storage[stype] = _map; - return 0; + if (map->prog && map->prog != prog) + goto unlock; + if (prog->aux->cgroup_storage[stype] && + prog->aux->cgroup_storage[stype] != _map) + goto unlock; + + map->prog = prog; + prog->aux->cgroup_storage[stype] = _map; + ret = 0; +unlock: + spin_unlock_bh(&map->lock); + + return ret; +} + +void bpf_cgroup_storage_release(struct bpf_prog *prog, struct bpf_map *_map) +{ + enum bpf_cgroup_storage_type stype = cgroup_storage_type(_map); + struct bpf_cgroup_storage_map *map = map_to_storage(_map); + + spin_lock_bh(&map->lock); + if (map->prog == prog) { + WARN_ON(prog->aux->cgroup_storage[stype] != _map); + map->prog = NULL; + prog->aux->cgroup_storage[stype] = NULL; + } + spin_unlock_bh(&map->lock); } static size_t bpf_cgroup_storage_calculate_size(struct bpf_map *map, u32 *pages) @@ -589,14 +569,13 @@ void bpf_cgroup_storage_link(struct bpf_cgroup_storage *storage, return; storage->key.attach_type = type; - storage->key.cgroup_inode_id = cgroup_id(cgroup); + storage->key.cgroup_inode_id = cgroup->kn->id.id; map = storage->map; spin_lock_bh(&map->lock); WARN_ON(cgroup_storage_insert(map, storage)); - list_add(&storage->list_map, &map->list); - list_add(&storage->list_cg, &cgroup->bpf.storages); + list_add(&storage->list, &map->list); spin_unlock_bh(&map->lock); } @@ -614,8 +593,7 @@ void bpf_cgroup_storage_unlink(struct bpf_cgroup_storage *storage) root = &map->root; rb_erase(&storage->node, root); - list_del(&storage->list_map); - list_del(&storage->list_cg); + list_del(&storage->list); spin_unlock_bh(&map->lock); } diff --git a/kernel/bpf/lpm_trie.c b/kernel/bpf/lpm_trie.c index d833d74c1c67..f726ceb8d7e9 100644 --- a/kernel/bpf/lpm_trie.c +++ b/kernel/bpf/lpm_trie.c @@ -25,7 +25,7 @@ struct lpm_trie_node { struct lpm_trie_node __rcu *child[2]; u32 prefixlen; u32 flags; - u8 data[]; + u8 data[0]; }; struct lpm_trie { @@ -34,7 +34,7 @@ struct lpm_trie { size_t n_entries; size_t max_prefixlen; size_t data_size; - spinlock_t lock; + raw_spinlock_t lock; }; /* This trie implements a longest prefix match algorithm that can be used to @@ -318,7 +318,7 @@ static int trie_update_elem(struct bpf_map *map, if (key->prefixlen > trie->max_prefixlen) return -EINVAL; - spin_lock_irqsave(&trie->lock, irq_flags); + raw_spin_lock_irqsave(&trie->lock, irq_flags); /* Allocate and fill a new node */ @@ -442,7 +442,7 @@ out: kfree(im_node); } - spin_unlock_irqrestore(&trie->lock, irq_flags); + raw_spin_unlock_irqrestore(&trie->lock, irq_flags); return ret; } @@ -462,7 +462,7 @@ static int trie_delete_elem(struct bpf_map *map, void *_key) if (key->prefixlen > trie->max_prefixlen) return -EINVAL; - spin_lock_irqsave(&trie->lock, irq_flags); + raw_spin_lock_irqsave(&trie->lock, irq_flags); /* Walk the tree looking for an exact key/length match and keeping * track of the path we traverse. We will need to know the node @@ -538,7 +538,7 @@ static int trie_delete_elem(struct bpf_map *map, void *_key) kfree_rcu(node, rcu); out: - spin_unlock_irqrestore(&trie->lock, irq_flags); + raw_spin_unlock_irqrestore(&trie->lock, irq_flags); return ret; } @@ -563,7 +563,7 @@ static struct bpf_map *trie_alloc(union bpf_attr *attr) u64 cost = sizeof(*trie), cost_per_node; int ret; - if (!bpf_capable()) + if (!capable(CAP_SYS_ADMIN)) return ERR_PTR(-EPERM); /* check sanity of attributes */ @@ -595,7 +595,7 @@ static struct bpf_map *trie_alloc(union bpf_attr *attr) if (ret) goto out_err; - spin_lock_init(&trie->lock); + raw_spin_lock_init(&trie->lock); return &trie->map; out_err: @@ -609,6 +609,11 @@ static void trie_free(struct bpf_map *map) struct lpm_trie_node __rcu **slot; struct lpm_trie_node *node; + /* Wait for outstanding programs to complete + * update/lookup/delete/get_next_key and free the trie. + */ + synchronize_rcu(); + /* Always start at the root and walk down to a node that has no * children. Then free that node, nullify its reference in the parent * and start over. @@ -750,9 +755,7 @@ static int trie_check_btf(const struct bpf_map *map, -EINVAL : 0; } -static int trie_map_btf_id; const struct bpf_map_ops trie_map_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc = trie_alloc, .map_free = trie_free, .map_get_next_key = trie_get_next_key, @@ -760,6 +763,4 @@ const struct bpf_map_ops trie_map_ops = { .map_update_elem = trie_update_elem, .map_delete_elem = trie_delete_elem, .map_check_btf = trie_check_btf, - .map_btf_name = "lpm_trie", - .map_btf_id = &trie_map_btf_id, }; diff --git a/kernel/bpf/map_in_map.c b/kernel/bpf/map_in_map.c index 39ab0b68cade..fab4fb134547 100644 --- a/kernel/bpf/map_in_map.c +++ b/kernel/bpf/map_in_map.c @@ -17,17 +17,23 @@ struct bpf_map *bpf_map_meta_alloc(int inner_map_ufd) if (IS_ERR(inner_map)) return inner_map; + /* prog_array->owner_prog_type and owner_jited + * is a runtime binding. Doing static check alone + * in the verifier is not enough. + */ + if (inner_map->map_type == BPF_MAP_TYPE_PROG_ARRAY || + inner_map->map_type == BPF_MAP_TYPE_CGROUP_STORAGE || + inner_map->map_type == BPF_MAP_TYPE_PERCPU_CGROUP_STORAGE) { + fdput(f); + return ERR_PTR(-ENOTSUPP); + } + /* Does not support >1 level map-in-map */ if (inner_map->inner_map_meta) { fdput(f); return ERR_PTR(-EINVAL); } - if (!inner_map->ops->map_meta_equal) { - fdput(f); - return ERR_PTR(-ENOTSUPP); - } - if (map_value_has_spin_lock(inner_map)) { fdput(f); return ERR_PTR(-ENOTSUPP); @@ -54,7 +60,7 @@ struct bpf_map *bpf_map_meta_alloc(int inner_map_ufd) /* Misc members not needed in bpf_map_meta_equal() check. */ inner_map_meta->ops = inner_map->ops; if (inner_map->ops == &array_map_ops) { - inner_map_meta->bypass_spec_v1 = inner_map->bypass_spec_v1; + inner_map_meta->unpriv_array = inner_map->unpriv_array; container_of(inner_map_meta, struct bpf_array, map)->index_mask = container_of(inner_map, struct bpf_array, map)->index_mask; } @@ -75,14 +81,15 @@ bool bpf_map_meta_equal(const struct bpf_map *meta0, return meta0->map_type == meta1->map_type && meta0->key_size == meta1->key_size && meta0->value_size == meta1->value_size && - meta0->map_flags == meta1->map_flags; + meta0->map_flags == meta1->map_flags && + meta0->max_entries == meta1->max_entries; } void *bpf_map_fd_get_ptr(struct bpf_map *map, struct file *map_file /* not used */, int ufd) { - struct bpf_map *inner_map, *inner_map_meta; + struct bpf_map *inner_map; struct fd f; f = fdget(ufd); @@ -90,9 +97,8 @@ void *bpf_map_fd_get_ptr(struct bpf_map *map, if (IS_ERR(inner_map)) return inner_map; - inner_map_meta = map->inner_map_meta; - if (inner_map_meta->ops->map_meta_equal(inner_map_meta, inner_map)) - bpf_map_inc(inner_map); + if (bpf_map_meta_equal(map->inner_map_meta, inner_map)) + inner_map = bpf_map_inc(inner_map, false); else inner_map = ERR_PTR(-EINVAL); diff --git a/kernel/bpf/map_in_map.h b/kernel/bpf/map_in_map.h index bcb7534afb3c..a507bf6ef8b9 100644 --- a/kernel/bpf/map_in_map.h +++ b/kernel/bpf/map_in_map.h @@ -11,6 +11,8 @@ struct bpf_map; struct bpf_map *bpf_map_meta_alloc(int inner_map_ufd); void bpf_map_meta_free(struct bpf_map *map_meta); +bool bpf_map_meta_equal(const struct bpf_map *meta0, + const struct bpf_map *meta1); void *bpf_map_fd_get_ptr(struct bpf_map *map, struct file *map_file, int ufd); void bpf_map_fd_put_ptr(void *ptr); diff --git a/kernel/bpf/map_iter.c b/kernel/bpf/map_iter.c deleted file mode 100644 index 6a9542af4212..000000000000 --- a/kernel/bpf/map_iter.c +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2020 Facebook */ -#include -#include -#include -#include -#include - -struct bpf_iter_seq_map_info { - u32 map_id; -}; - -static void *bpf_map_seq_start(struct seq_file *seq, loff_t *pos) -{ - struct bpf_iter_seq_map_info *info = seq->private; - struct bpf_map *map; - - map = bpf_map_get_curr_or_next(&info->map_id); - if (!map) - return NULL; - - if (*pos == 0) - ++*pos; - return map; -} - -static void *bpf_map_seq_next(struct seq_file *seq, void *v, loff_t *pos) -{ - struct bpf_iter_seq_map_info *info = seq->private; - - ++*pos; - ++info->map_id; - bpf_map_put((struct bpf_map *)v); - return bpf_map_get_curr_or_next(&info->map_id); -} - -struct bpf_iter__bpf_map { - __bpf_md_ptr(struct bpf_iter_meta *, meta); - __bpf_md_ptr(struct bpf_map *, map); -}; - -DEFINE_BPF_ITER_FUNC(bpf_map, struct bpf_iter_meta *meta, struct bpf_map *map) - -static int __bpf_map_seq_show(struct seq_file *seq, void *v, bool in_stop) -{ - struct bpf_iter__bpf_map ctx; - struct bpf_iter_meta meta; - struct bpf_prog *prog; - int ret = 0; - - ctx.meta = &meta; - ctx.map = v; - meta.seq = seq; - prog = bpf_iter_get_info(&meta, in_stop); - if (prog) - ret = bpf_iter_run_prog(prog, &ctx); - - return ret; -} - -static int bpf_map_seq_show(struct seq_file *seq, void *v) -{ - return __bpf_map_seq_show(seq, v, false); -} - -static void bpf_map_seq_stop(struct seq_file *seq, void *v) -{ - if (!v) - (void)__bpf_map_seq_show(seq, v, true); - else - bpf_map_put((struct bpf_map *)v); -} - -static const struct seq_operations bpf_map_seq_ops = { - .start = bpf_map_seq_start, - .next = bpf_map_seq_next, - .stop = bpf_map_seq_stop, - .show = bpf_map_seq_show, -}; - -BTF_ID_LIST(btf_bpf_map_id) -BTF_ID(struct, bpf_map) - -static const struct bpf_iter_seq_info bpf_map_seq_info = { - .seq_ops = &bpf_map_seq_ops, - .init_seq_private = NULL, - .fini_seq_private = NULL, - .seq_priv_size = sizeof(struct bpf_iter_seq_map_info), -}; - -static struct bpf_iter_reg bpf_map_reg_info = { - .target = "bpf_map", - .ctx_arg_info_size = 1, - .ctx_arg_info = { - { offsetof(struct bpf_iter__bpf_map, map), - PTR_TO_BTF_ID_OR_NULL }, - }, - .seq_info = &bpf_map_seq_info, -}; - -static int bpf_iter_attach_map(struct bpf_prog *prog, - union bpf_iter_link_info *linfo, - struct bpf_iter_aux_info *aux) -{ - u32 key_acc_size, value_acc_size, key_size, value_size; - struct bpf_map *map; - bool is_percpu = false; - int err = -EINVAL; - - if (!linfo->map.map_fd) - return -EBADF; - - map = bpf_map_get_with_uref(linfo->map.map_fd); - if (IS_ERR(map)) - return PTR_ERR(map); - - if (map->map_type == BPF_MAP_TYPE_PERCPU_HASH || - map->map_type == BPF_MAP_TYPE_LRU_PERCPU_HASH || - map->map_type == BPF_MAP_TYPE_PERCPU_ARRAY) - is_percpu = true; - else if (map->map_type != BPF_MAP_TYPE_HASH && - map->map_type != BPF_MAP_TYPE_LRU_HASH && - map->map_type != BPF_MAP_TYPE_ARRAY) - goto put_map; - - key_acc_size = prog->aux->max_rdonly_access; - value_acc_size = prog->aux->max_rdwr_access; - key_size = map->key_size; - if (!is_percpu) - value_size = map->value_size; - else - value_size = round_up(map->value_size, 8) * num_possible_cpus(); - - if (key_acc_size > key_size || value_acc_size > value_size) { - err = -EACCES; - goto put_map; - } - - aux->map = map; - return 0; - -put_map: - bpf_map_put_with_uref(map); - return err; -} - -static void bpf_iter_detach_map(struct bpf_iter_aux_info *aux) -{ - bpf_map_put_with_uref(aux->map); -} - -void bpf_iter_map_show_fdinfo(const struct bpf_iter_aux_info *aux, - struct seq_file *seq) -{ - seq_printf(seq, "map_id:\t%u\n", aux->map->id); -} - -int bpf_iter_map_fill_link_info(const struct bpf_iter_aux_info *aux, - struct bpf_link_info *info) -{ - info->iter.map.map_id = aux->map->id; - return 0; -} - -DEFINE_BPF_ITER_FUNC(bpf_map_elem, struct bpf_iter_meta *meta, - struct bpf_map *map, void *key, void *value) - -static const struct bpf_iter_reg bpf_map_elem_reg_info = { - .target = "bpf_map_elem", - .attach_target = bpf_iter_attach_map, - .detach_target = bpf_iter_detach_map, - .show_fdinfo = bpf_iter_map_show_fdinfo, - .fill_link_info = bpf_iter_map_fill_link_info, - .ctx_arg_info_size = 2, - .ctx_arg_info = { - { offsetof(struct bpf_iter__bpf_map_elem, key), - PTR_TO_RDONLY_BUF_OR_NULL }, - { offsetof(struct bpf_iter__bpf_map_elem, value), - PTR_TO_RDWR_BUF_OR_NULL }, - }, -}; - -static int __init bpf_map_iter_init(void) -{ - int ret; - - bpf_map_reg_info.ctx_arg_info[0].btf_id = *btf_bpf_map_id; - ret = bpf_iter_reg_target(&bpf_map_reg_info); - if (ret) - return ret; - - return bpf_iter_reg_target(&bpf_map_elem_reg_info); -} - -late_initcall(bpf_map_iter_init); diff --git a/kernel/bpf/net_namespace.c b/kernel/bpf/net_namespace.c deleted file mode 100644 index 542f275bf252..000000000000 --- a/kernel/bpf/net_namespace.c +++ /dev/null @@ -1,566 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include -#include -#include - -/* - * Functions to manage BPF programs attached to netns - */ - -struct bpf_netns_link { - struct bpf_link link; - enum bpf_attach_type type; - enum netns_bpf_attach_type netns_type; - - /* We don't hold a ref to net in order to auto-detach the link - * when netns is going away. Instead we rely on pernet - * pre_exit callback to clear this pointer. Must be accessed - * with netns_bpf_mutex held. - */ - struct net *net; - struct list_head node; /* node in list of links attached to net */ -}; - -/* Protects updates to netns_bpf */ -DEFINE_MUTEX(netns_bpf_mutex); - -static void netns_bpf_attach_type_unneed(enum netns_bpf_attach_type type) -{ - switch (type) { -#ifdef CONFIG_INET - case NETNS_BPF_SK_LOOKUP: - static_branch_dec(&bpf_sk_lookup_enabled); - break; -#endif - default: - break; - } -} - -static void netns_bpf_attach_type_need(enum netns_bpf_attach_type type) -{ - switch (type) { -#ifdef CONFIG_INET - case NETNS_BPF_SK_LOOKUP: - static_branch_inc(&bpf_sk_lookup_enabled); - break; -#endif - default: - break; - } -} - -/* Must be called with netns_bpf_mutex held. */ -static void netns_bpf_run_array_detach(struct net *net, - enum netns_bpf_attach_type type) -{ - struct bpf_prog_array *run_array; - - run_array = rcu_replace_pointer(net->bpf.run_array[type], NULL, - lockdep_is_held(&netns_bpf_mutex)); - bpf_prog_array_free(run_array); -} - -static int link_index(struct net *net, enum netns_bpf_attach_type type, - struct bpf_netns_link *link) -{ - struct bpf_netns_link *pos; - int i = 0; - - list_for_each_entry(pos, &net->bpf.links[type], node) { - if (pos == link) - return i; - i++; - } - return -ENOENT; -} - -static int link_count(struct net *net, enum netns_bpf_attach_type type) -{ - struct list_head *pos; - int i = 0; - - list_for_each(pos, &net->bpf.links[type]) - i++; - return i; -} - -static void fill_prog_array(struct net *net, enum netns_bpf_attach_type type, - struct bpf_prog_array *prog_array) -{ - struct bpf_netns_link *pos; - unsigned int i = 0; - - list_for_each_entry(pos, &net->bpf.links[type], node) { - prog_array->items[i].prog = pos->link.prog; - i++; - } -} - -static void bpf_netns_link_release(struct bpf_link *link) -{ - struct bpf_netns_link *net_link = - container_of(link, struct bpf_netns_link, link); - enum netns_bpf_attach_type type = net_link->netns_type; - struct bpf_prog_array *old_array, *new_array; - struct net *net; - int cnt, idx; - - mutex_lock(&netns_bpf_mutex); - - /* We can race with cleanup_net, but if we see a non-NULL - * struct net pointer, pre_exit has not run yet and wait for - * netns_bpf_mutex. - */ - net = net_link->net; - if (!net) - goto out_unlock; - - /* Mark attach point as unused */ - netns_bpf_attach_type_unneed(type); - - /* Remember link position in case of safe delete */ - idx = link_index(net, type, net_link); - list_del(&net_link->node); - - cnt = link_count(net, type); - if (!cnt) { - netns_bpf_run_array_detach(net, type); - goto out_unlock; - } - - old_array = rcu_dereference_protected(net->bpf.run_array[type], - lockdep_is_held(&netns_bpf_mutex)); - new_array = bpf_prog_array_alloc(cnt, GFP_KERNEL); - if (!new_array) { - WARN_ON(bpf_prog_array_delete_safe_at(old_array, idx)); - goto out_unlock; - } - fill_prog_array(net, type, new_array); - rcu_assign_pointer(net->bpf.run_array[type], new_array); - bpf_prog_array_free(old_array); - -out_unlock: - net_link->net = NULL; - mutex_unlock(&netns_bpf_mutex); -} - -static int bpf_netns_link_detach(struct bpf_link *link) -{ - bpf_netns_link_release(link); - return 0; -} - -static void bpf_netns_link_dealloc(struct bpf_link *link) -{ - struct bpf_netns_link *net_link = - container_of(link, struct bpf_netns_link, link); - - kfree(net_link); -} - -static int bpf_netns_link_update_prog(struct bpf_link *link, - struct bpf_prog *new_prog, - struct bpf_prog *old_prog) -{ - struct bpf_netns_link *net_link = - container_of(link, struct bpf_netns_link, link); - enum netns_bpf_attach_type type = net_link->netns_type; - struct bpf_prog_array *run_array; - struct net *net; - int idx, ret; - - if (old_prog && old_prog != link->prog) - return -EPERM; - if (new_prog->type != link->prog->type) - return -EINVAL; - - mutex_lock(&netns_bpf_mutex); - - net = net_link->net; - if (!net || !check_net(net)) { - /* Link auto-detached or netns dying */ - ret = -ENOLINK; - goto out_unlock; - } - - run_array = rcu_dereference_protected(net->bpf.run_array[type], - lockdep_is_held(&netns_bpf_mutex)); - idx = link_index(net, type, net_link); - ret = bpf_prog_array_update_at(run_array, idx, new_prog); - if (ret) - goto out_unlock; - - old_prog = xchg(&link->prog, new_prog); - bpf_prog_put(old_prog); - -out_unlock: - mutex_unlock(&netns_bpf_mutex); - return ret; -} - -static int bpf_netns_link_fill_info(const struct bpf_link *link, - struct bpf_link_info *info) -{ - const struct bpf_netns_link *net_link = - container_of(link, struct bpf_netns_link, link); - unsigned int inum = 0; - struct net *net; - - mutex_lock(&netns_bpf_mutex); - net = net_link->net; - if (net && check_net(net)) - inum = net->ns.inum; - mutex_unlock(&netns_bpf_mutex); - - info->netns.netns_ino = inum; - info->netns.attach_type = net_link->type; - return 0; -} - -static void bpf_netns_link_show_fdinfo(const struct bpf_link *link, - struct seq_file *seq) -{ - struct bpf_link_info info = {}; - - bpf_netns_link_fill_info(link, &info); - seq_printf(seq, - "netns_ino:\t%u\n" - "attach_type:\t%u\n", - info.netns.netns_ino, - info.netns.attach_type); -} - -static const struct bpf_link_ops bpf_netns_link_ops = { - .release = bpf_netns_link_release, - .dealloc = bpf_netns_link_dealloc, - .detach = bpf_netns_link_detach, - .update_prog = bpf_netns_link_update_prog, - .fill_link_info = bpf_netns_link_fill_info, - .show_fdinfo = bpf_netns_link_show_fdinfo, -}; - -/* Must be called with netns_bpf_mutex held. */ -static int __netns_bpf_prog_query(const union bpf_attr *attr, - union bpf_attr __user *uattr, - struct net *net, - enum netns_bpf_attach_type type) -{ - __u32 __user *prog_ids = u64_to_user_ptr(attr->query.prog_ids); - struct bpf_prog_array *run_array; - u32 prog_cnt = 0, flags = 0; - - run_array = rcu_dereference_protected(net->bpf.run_array[type], - lockdep_is_held(&netns_bpf_mutex)); - if (run_array) - prog_cnt = bpf_prog_array_length(run_array); - - if (copy_to_user(&uattr->query.attach_flags, &flags, sizeof(flags))) - return -EFAULT; - if (copy_to_user(&uattr->query.prog_cnt, &prog_cnt, sizeof(prog_cnt))) - return -EFAULT; - if (!attr->query.prog_cnt || !prog_ids || !prog_cnt) - return 0; - - return bpf_prog_array_copy_to_user(run_array, prog_ids, - attr->query.prog_cnt); -} - -int netns_bpf_prog_query(const union bpf_attr *attr, - union bpf_attr __user *uattr) -{ - enum netns_bpf_attach_type type; - struct net *net; - int ret; - - if (attr->query.query_flags) - return -EINVAL; - - type = to_netns_bpf_attach_type(attr->query.attach_type); - if (type < 0) - return -EINVAL; - - net = get_net_ns_by_fd(attr->query.target_fd); - if (IS_ERR(net)) - return PTR_ERR(net); - - mutex_lock(&netns_bpf_mutex); - ret = __netns_bpf_prog_query(attr, uattr, net, type); - mutex_unlock(&netns_bpf_mutex); - - put_net(net); - return ret; -} - -int netns_bpf_prog_attach(const union bpf_attr *attr, struct bpf_prog *prog) -{ - struct bpf_prog_array *run_array; - enum netns_bpf_attach_type type; - struct bpf_prog *attached; - struct net *net; - int ret; - - if (attr->target_fd || attr->attach_flags || attr->replace_bpf_fd) - return -EINVAL; - - type = to_netns_bpf_attach_type(attr->attach_type); - if (type < 0) - return -EINVAL; - - net = current->nsproxy->net_ns; - mutex_lock(&netns_bpf_mutex); - - /* Attaching prog directly is not compatible with links */ - if (!list_empty(&net->bpf.links[type])) { - ret = -EEXIST; - goto out_unlock; - } - - switch (type) { - case NETNS_BPF_FLOW_DISSECTOR: - ret = flow_dissector_bpf_prog_attach_check(net, prog); - break; - default: - ret = -EINVAL; - break; - } - if (ret) - goto out_unlock; - - attached = net->bpf.progs[type]; - if (attached == prog) { - /* The same program cannot be attached twice */ - ret = -EINVAL; - goto out_unlock; - } - - run_array = rcu_dereference_protected(net->bpf.run_array[type], - lockdep_is_held(&netns_bpf_mutex)); - if (run_array) { - WRITE_ONCE(run_array->items[0].prog, prog); - } else { - run_array = bpf_prog_array_alloc(1, GFP_KERNEL); - if (!run_array) { - ret = -ENOMEM; - goto out_unlock; - } - run_array->items[0].prog = prog; - rcu_assign_pointer(net->bpf.run_array[type], run_array); - } - - net->bpf.progs[type] = prog; - if (attached) - bpf_prog_put(attached); - -out_unlock: - mutex_unlock(&netns_bpf_mutex); - - return ret; -} - -/* Must be called with netns_bpf_mutex held. */ -static int __netns_bpf_prog_detach(struct net *net, - enum netns_bpf_attach_type type, - struct bpf_prog *old) -{ - struct bpf_prog *attached; - - /* Progs attached via links cannot be detached */ - if (!list_empty(&net->bpf.links[type])) - return -EINVAL; - - attached = net->bpf.progs[type]; - if (!attached || attached != old) - return -ENOENT; - netns_bpf_run_array_detach(net, type); - net->bpf.progs[type] = NULL; - bpf_prog_put(attached); - return 0; -} - -int netns_bpf_prog_detach(const union bpf_attr *attr, enum bpf_prog_type ptype) -{ - enum netns_bpf_attach_type type; - struct bpf_prog *prog; - int ret; - - if (attr->target_fd) - return -EINVAL; - - type = to_netns_bpf_attach_type(attr->attach_type); - if (type < 0) - return -EINVAL; - - prog = bpf_prog_get_type(attr->attach_bpf_fd, ptype); - if (IS_ERR(prog)) - return PTR_ERR(prog); - - mutex_lock(&netns_bpf_mutex); - ret = __netns_bpf_prog_detach(current->nsproxy->net_ns, type, prog); - mutex_unlock(&netns_bpf_mutex); - - bpf_prog_put(prog); - - return ret; -} - -static int netns_bpf_max_progs(enum netns_bpf_attach_type type) -{ - switch (type) { - case NETNS_BPF_FLOW_DISSECTOR: - return 1; - case NETNS_BPF_SK_LOOKUP: - return 64; - default: - return 0; - } -} - -static int netns_bpf_link_attach(struct net *net, struct bpf_link *link, - enum netns_bpf_attach_type type) -{ - struct bpf_netns_link *net_link = - container_of(link, struct bpf_netns_link, link); - struct bpf_prog_array *run_array; - int cnt, err; - - mutex_lock(&netns_bpf_mutex); - - cnt = link_count(net, type); - if (cnt >= netns_bpf_max_progs(type)) { - err = -E2BIG; - goto out_unlock; - } - /* Links are not compatible with attaching prog directly */ - if (net->bpf.progs[type]) { - err = -EEXIST; - goto out_unlock; - } - - switch (type) { - case NETNS_BPF_FLOW_DISSECTOR: - err = flow_dissector_bpf_prog_attach_check(net, link->prog); - break; - case NETNS_BPF_SK_LOOKUP: - err = 0; /* nothing to check */ - break; - default: - err = -EINVAL; - break; - } - if (err) - goto out_unlock; - - run_array = bpf_prog_array_alloc(cnt + 1, GFP_KERNEL); - if (!run_array) { - err = -ENOMEM; - goto out_unlock; - } - - list_add_tail(&net_link->node, &net->bpf.links[type]); - - fill_prog_array(net, type, run_array); - run_array = rcu_replace_pointer(net->bpf.run_array[type], run_array, - lockdep_is_held(&netns_bpf_mutex)); - bpf_prog_array_free(run_array); - - /* Mark attach point as used */ - netns_bpf_attach_type_need(type); - -out_unlock: - mutex_unlock(&netns_bpf_mutex); - return err; -} - -int netns_bpf_link_create(const union bpf_attr *attr, struct bpf_prog *prog) -{ - enum netns_bpf_attach_type netns_type; - struct bpf_link_primer link_primer; - struct bpf_netns_link *net_link; - enum bpf_attach_type type; - struct net *net; - int err; - - if (attr->link_create.flags) - return -EINVAL; - - type = attr->link_create.attach_type; - netns_type = to_netns_bpf_attach_type(type); - if (netns_type < 0) - return -EINVAL; - - net = get_net_ns_by_fd(attr->link_create.target_fd); - if (IS_ERR(net)) - return PTR_ERR(net); - - net_link = kzalloc(sizeof(*net_link), GFP_USER); - if (!net_link) { - err = -ENOMEM; - goto out_put_net; - } - bpf_link_init(&net_link->link, BPF_LINK_TYPE_NETNS, - &bpf_netns_link_ops, prog); - net_link->net = net; - net_link->type = type; - net_link->netns_type = netns_type; - - err = bpf_link_prime(&net_link->link, &link_primer); - if (err) { - kfree(net_link); - goto out_put_net; - } - - err = netns_bpf_link_attach(net, &net_link->link, netns_type); - if (err) { - bpf_link_cleanup(&link_primer); - goto out_put_net; - } - - put_net(net); - return bpf_link_settle(&link_primer); - -out_put_net: - put_net(net); - return err; -} - -static int __net_init netns_bpf_pernet_init(struct net *net) -{ - int type; - - for (type = 0; type < MAX_NETNS_BPF_ATTACH_TYPE; type++) - INIT_LIST_HEAD(&net->bpf.links[type]); - - return 0; -} - -static void __net_exit netns_bpf_pernet_pre_exit(struct net *net) -{ - enum netns_bpf_attach_type type; - struct bpf_netns_link *net_link; - - mutex_lock(&netns_bpf_mutex); - for (type = 0; type < MAX_NETNS_BPF_ATTACH_TYPE; type++) { - netns_bpf_run_array_detach(net, type); - list_for_each_entry(net_link, &net->bpf.links[type], node) { - net_link->net = NULL; /* auto-detach link */ - netns_bpf_attach_type_unneed(type); - } - if (net->bpf.progs[type]) - bpf_prog_put(net->bpf.progs[type]); - } - mutex_unlock(&netns_bpf_mutex); -} - -static struct pernet_operations netns_bpf_pernet_ops __net_initdata = { - .init = netns_bpf_pernet_init, - .pre_exit = netns_bpf_pernet_pre_exit, -}; - -static int __init netns_bpf_init(void) -{ - return register_pernet_subsys(&netns_bpf_pernet_ops); -} - -subsys_initcall(netns_bpf_init); diff --git a/kernel/bpf/offload.c b/kernel/bpf/offload.c index bd09290e3648..3668a0bc18ec 100644 --- a/kernel/bpf/offload.c +++ b/kernel/bpf/offload.c @@ -302,14 +302,14 @@ int bpf_prog_offload_info_fill(struct bpf_prog_info *info, struct inode *ns_inode; struct path ns_path; char __user *uinsns; - int res; + void *res; u32 ulen; res = ns_get_path_cb(&ns_path, bpf_prog_offload_info_fill_ns, &args); - if (res) { + if (IS_ERR(res)) { if (!info->ifindex) return -ENODEV; - return res; + return PTR_ERR(res); } down_read(&bpf_devs_lock); @@ -526,13 +526,13 @@ int bpf_map_offload_info_fill(struct bpf_map_info *info, struct bpf_map *map) }; struct inode *ns_inode; struct path ns_path; - int res; + void *res; res = ns_get_path_cb(&ns_path, bpf_map_offload_info_fill_ns, &args); - if (res) { + if (IS_ERR(res)) { if (!info->ifindex) return -ENODEV; - return res; + return PTR_ERR(res); } ns_inode = ns_path.dentry->d_inode; diff --git a/kernel/bpf/percpu_freelist.c b/kernel/bpf/percpu_freelist.c index bbab8bb4b2fd..6e090140b924 100644 --- a/kernel/bpf/percpu_freelist.c +++ b/kernel/bpf/percpu_freelist.c @@ -17,8 +17,6 @@ int pcpu_freelist_init(struct pcpu_freelist *s) raw_spin_lock_init(&head->lock); head->first = NULL; } - raw_spin_lock_init(&s->extralist.lock); - s->extralist.first = NULL; return 0; } @@ -27,65 +25,21 @@ void pcpu_freelist_destroy(struct pcpu_freelist *s) free_percpu(s->freelist); } -static inline void pcpu_freelist_push_node(struct pcpu_freelist_head *head, - struct pcpu_freelist_node *node) -{ - node->next = head->first; - head->first = node; -} - static inline void ___pcpu_freelist_push(struct pcpu_freelist_head *head, struct pcpu_freelist_node *node) { raw_spin_lock(&head->lock); - pcpu_freelist_push_node(head, node); + node->next = head->first; + head->first = node; raw_spin_unlock(&head->lock); } -static inline bool pcpu_freelist_try_push_extra(struct pcpu_freelist *s, - struct pcpu_freelist_node *node) -{ - if (!raw_spin_trylock(&s->extralist.lock)) - return false; - - pcpu_freelist_push_node(&s->extralist, node); - raw_spin_unlock(&s->extralist.lock); - return true; -} - -static inline void ___pcpu_freelist_push_nmi(struct pcpu_freelist *s, - struct pcpu_freelist_node *node) -{ - int cpu, orig_cpu; - - orig_cpu = cpu = raw_smp_processor_id(); - while (1) { - struct pcpu_freelist_head *head; - - head = per_cpu_ptr(s->freelist, cpu); - if (raw_spin_trylock(&head->lock)) { - pcpu_freelist_push_node(head, node); - raw_spin_unlock(&head->lock); - return; - } - cpu = cpumask_next(cpu, cpu_possible_mask); - if (cpu >= nr_cpu_ids) - cpu = 0; - - /* cannot lock any per cpu lock, try extralist */ - if (cpu == orig_cpu && - pcpu_freelist_try_push_extra(s, node)) - return; - } -} - void __pcpu_freelist_push(struct pcpu_freelist *s, struct pcpu_freelist_node *node) { - if (in_nmi()) - ___pcpu_freelist_push_nmi(s, node); - else - ___pcpu_freelist_push(this_cpu_ptr(s->freelist), node); + struct pcpu_freelist_head *head = this_cpu_ptr(s->freelist); + + ___pcpu_freelist_push(head, node); } void pcpu_freelist_push(struct pcpu_freelist *s, @@ -102,25 +56,32 @@ void pcpu_freelist_populate(struct pcpu_freelist *s, void *buf, u32 elem_size, u32 nr_elems) { struct pcpu_freelist_head *head; - unsigned int cpu, cpu_idx, i, j, n, m; + unsigned long flags; + int i, cpu, pcpu_entries; - n = nr_elems / num_possible_cpus(); - m = nr_elems % num_possible_cpus(); + pcpu_entries = nr_elems / num_possible_cpus() + 1; + i = 0; - cpu_idx = 0; + /* disable irq to workaround lockdep false positive + * in bpf usage pcpu_freelist_populate() will never race + * with pcpu_freelist_push() + */ + local_irq_save(flags); for_each_possible_cpu(cpu) { +again: head = per_cpu_ptr(s->freelist, cpu); - j = n + (cpu_idx < m ? 1 : 0); - for (i = 0; i < j; i++) { - /* No locking required as this is not visible yet. */ - pcpu_freelist_push_node(head, buf); - buf += elem_size; - } - cpu_idx++; + ___pcpu_freelist_push(head, buf); + i++; + buf += elem_size; + if (i == nr_elems) + break; + if (i % pcpu_entries) + goto again; } + local_irq_restore(flags); } -static struct pcpu_freelist_node *___pcpu_freelist_pop(struct pcpu_freelist *s) +struct pcpu_freelist_node *__pcpu_freelist_pop(struct pcpu_freelist *s) { struct pcpu_freelist_head *head; struct pcpu_freelist_node *node; @@ -141,59 +102,8 @@ static struct pcpu_freelist_node *___pcpu_freelist_pop(struct pcpu_freelist *s) if (cpu >= nr_cpu_ids) cpu = 0; if (cpu == orig_cpu) - break; + return NULL; } - - /* per cpu lists are all empty, try extralist */ - raw_spin_lock(&s->extralist.lock); - node = s->extralist.first; - if (node) - s->extralist.first = node->next; - raw_spin_unlock(&s->extralist.lock); - return node; -} - -static struct pcpu_freelist_node * -___pcpu_freelist_pop_nmi(struct pcpu_freelist *s) -{ - struct pcpu_freelist_head *head; - struct pcpu_freelist_node *node; - int orig_cpu, cpu; - - orig_cpu = cpu = raw_smp_processor_id(); - while (1) { - head = per_cpu_ptr(s->freelist, cpu); - if (raw_spin_trylock(&head->lock)) { - node = head->first; - if (node) { - head->first = node->next; - raw_spin_unlock(&head->lock); - return node; - } - raw_spin_unlock(&head->lock); - } - cpu = cpumask_next(cpu, cpu_possible_mask); - if (cpu >= nr_cpu_ids) - cpu = 0; - if (cpu == orig_cpu) - break; - } - - /* cannot pop from per cpu lists, try extralist */ - if (!raw_spin_trylock(&s->extralist.lock)) - return NULL; - node = s->extralist.first; - if (node) - s->extralist.first = node->next; - raw_spin_unlock(&s->extralist.lock); - return node; -} - -struct pcpu_freelist_node *__pcpu_freelist_pop(struct pcpu_freelist *s) -{ - if (in_nmi()) - return ___pcpu_freelist_pop_nmi(s); - return ___pcpu_freelist_pop(s); } struct pcpu_freelist_node *pcpu_freelist_pop(struct pcpu_freelist *s) diff --git a/kernel/bpf/percpu_freelist.h b/kernel/bpf/percpu_freelist.h index 3c76553cfe57..fbf8a8a28979 100644 --- a/kernel/bpf/percpu_freelist.h +++ b/kernel/bpf/percpu_freelist.h @@ -13,7 +13,6 @@ struct pcpu_freelist_head { struct pcpu_freelist { struct pcpu_freelist_head __percpu *freelist; - struct pcpu_freelist_head extralist; }; struct pcpu_freelist_node { diff --git a/kernel/bpf/preload/.gitignore b/kernel/bpf/preload/.gitignore deleted file mode 100644 index 856a4c5ad0dd..000000000000 --- a/kernel/bpf/preload/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -/FEATURE-DUMP.libbpf -/bpf_helper_defs.h -/feature -/bpf_preload_umd diff --git a/kernel/bpf/preload/Kconfig b/kernel/bpf/preload/Kconfig deleted file mode 100644 index 26bced262473..000000000000 --- a/kernel/bpf/preload/Kconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -config USERMODE_DRIVER - bool - default n - -menuconfig BPF_PRELOAD - bool "Preload BPF file system with kernel specific program and map iterators" - depends on BPF - depends on BPF_SYSCALL - # The dependency on !COMPILE_TEST prevents it from being enabled - # in allmodconfig or allyesconfig configurations - depends on !COMPILE_TEST - select USERMODE_DRIVER - help - This builds kernel module with several embedded BPF programs that are - pinned into BPF FS mount point as human readable files that are - useful in debugging and introspection of BPF programs and maps. - -if BPF_PRELOAD -config BPF_PRELOAD_UMD - tristate "bpf_preload kernel module with user mode driver" - depends on CC_CAN_LINK - depends on m || CC_CAN_LINK_STATIC - default m - help - This builds bpf_preload kernel module with embedded user mode driver. -endif diff --git a/kernel/bpf/preload/Makefile b/kernel/bpf/preload/Makefile deleted file mode 100644 index 1951332dd15f..000000000000 --- a/kernel/bpf/preload/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 - -LIBBPF_SRCS = $(srctree)/tools/lib/bpf/ -LIBBPF_A = $(obj)/libbpf.a -LIBBPF_OUT = $(abspath $(obj)) - -# Although not in use by libbpf's Makefile, set $(O) so that the "dummy" test -# in tools/scripts/Makefile.include always succeeds when building the kernel -# with $(O) pointing to a relative path, as in "make O=build bindeb-pkg". -$(LIBBPF_A): - $(Q)$(MAKE) -C $(LIBBPF_SRCS) O=$(LIBBPF_OUT)/ OUTPUT=$(LIBBPF_OUT)/ $(LIBBPF_OUT)/libbpf.a - -userccflags += -I $(srctree)/tools/include/ -I $(srctree)/tools/include/uapi \ - -I $(srctree)/tools/lib/ -Wno-unused-result - -userprogs := bpf_preload_umd - -clean-files := $(userprogs) bpf_helper_defs.h FEATURE-DUMP.libbpf staticobjs/ feature/ - -bpf_preload_umd-objs := iterators/iterators.o -bpf_preload_umd-userldlibs := $(LIBBPF_A) -lelf -lz - -$(obj)/bpf_preload_umd: $(LIBBPF_A) - -$(obj)/bpf_preload_umd_blob.o: $(obj)/bpf_preload_umd - -obj-$(CONFIG_BPF_PRELOAD_UMD) += bpf_preload.o -bpf_preload-objs += bpf_preload_kern.o bpf_preload_umd_blob.o diff --git a/kernel/bpf/preload/bpf_preload.h b/kernel/bpf/preload/bpf_preload.h deleted file mode 100644 index 2f9932276f2e..000000000000 --- a/kernel/bpf/preload/bpf_preload.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _BPF_PRELOAD_H -#define _BPF_PRELOAD_H - -#include -#include "iterators/bpf_preload_common.h" - -struct bpf_preload_ops { - struct umd_info info; - int (*preload)(struct bpf_preload_info *); - int (*finish)(void); - struct module *owner; -}; -extern struct bpf_preload_ops *bpf_preload_ops; -#define BPF_PRELOAD_LINKS 2 -#endif diff --git a/kernel/bpf/preload/bpf_preload_kern.c b/kernel/bpf/preload/bpf_preload_kern.c deleted file mode 100644 index 53736e52c1df..000000000000 --- a/kernel/bpf/preload/bpf_preload_kern.c +++ /dev/null @@ -1,102 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt -#include -#include -#include -#include -#include -#include "bpf_preload.h" - -extern char bpf_preload_umd_start; -extern char bpf_preload_umd_end; - -static int preload(struct bpf_preload_info *obj); -static int finish(void); - -static struct bpf_preload_ops umd_ops = { - .info.driver_name = "bpf_preload", - .preload = preload, - .finish = finish, - .owner = THIS_MODULE, -}; - -static int preload(struct bpf_preload_info *obj) -{ - int magic = BPF_PRELOAD_START; - loff_t pos = 0; - int i, err; - ssize_t n; - - err = fork_usermode_driver(&umd_ops.info); - if (err) - return err; - - /* send the start magic to let UMD proceed with loading BPF progs */ - n = kernel_write(umd_ops.info.pipe_to_umh, - &magic, sizeof(magic), &pos); - if (n != sizeof(magic)) - return -EPIPE; - - /* receive bpf_link IDs and names from UMD */ - pos = 0; - for (i = 0; i < BPF_PRELOAD_LINKS; i++) { - n = kernel_read(umd_ops.info.pipe_from_umh, - &obj[i], sizeof(*obj), &pos); - if (n != sizeof(*obj)) - return -EPIPE; - } - return 0; -} - -static int finish(void) -{ - int magic = BPF_PRELOAD_END; - struct pid *tgid; - loff_t pos = 0; - ssize_t n; - - /* send the last magic to UMD. It will do a normal exit. */ - n = kernel_write(umd_ops.info.pipe_to_umh, - &magic, sizeof(magic), &pos); - if (n != sizeof(magic)) - return -EPIPE; - - tgid = umd_ops.info.tgid; - if (tgid) { - wait_event(tgid->wait_pidfd, thread_group_exited(tgid)); - umd_cleanup_helper(&umd_ops.info); - } - return 0; -} - -static int __init load_umd(void) -{ - int err; - - err = umd_load_blob(&umd_ops.info, &bpf_preload_umd_start, - &bpf_preload_umd_end - &bpf_preload_umd_start); - if (err) - return err; - bpf_preload_ops = &umd_ops; - return err; -} - -static void __exit fini_umd(void) -{ - struct pid *tgid; - - bpf_preload_ops = NULL; - - /* kill UMD in case it's still there due to earlier error */ - tgid = umd_ops.info.tgid; - if (tgid) { - kill_pid(tgid, SIGKILL, 1); - - wait_event(tgid->wait_pidfd, thread_group_exited(tgid)); - umd_cleanup_helper(&umd_ops.info); - } - umd_unload_blob(&umd_ops.info); -} -late_initcall(load_umd); -module_exit(fini_umd); -MODULE_LICENSE("GPL"); diff --git a/kernel/bpf/preload/bpf_preload_umd_blob.S b/kernel/bpf/preload/bpf_preload_umd_blob.S deleted file mode 100644 index f1f40223b5c3..000000000000 --- a/kernel/bpf/preload/bpf_preload_umd_blob.S +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - .section .init.rodata, "a" - .global bpf_preload_umd_start -bpf_preload_umd_start: - .incbin "kernel/bpf/preload/bpf_preload_umd" - .global bpf_preload_umd_end -bpf_preload_umd_end: diff --git a/kernel/bpf/preload/iterators/.gitignore b/kernel/bpf/preload/iterators/.gitignore deleted file mode 100644 index ffdb70230c8b..000000000000 --- a/kernel/bpf/preload/iterators/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -/.output diff --git a/kernel/bpf/preload/iterators/Makefile b/kernel/bpf/preload/iterators/Makefile deleted file mode 100644 index 28fa8c1440f4..000000000000 --- a/kernel/bpf/preload/iterators/Makefile +++ /dev/null @@ -1,57 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -OUTPUT := .output -CLANG ?= clang -LLC ?= llc -LLVM_STRIP ?= llvm-strip -DEFAULT_BPFTOOL := $(OUTPUT)/sbin/bpftool -BPFTOOL ?= $(DEFAULT_BPFTOOL) -LIBBPF_SRC := $(abspath ../../../../tools/lib/bpf) -BPFOBJ := $(OUTPUT)/libbpf.a -BPF_INCLUDE := $(OUTPUT) -INCLUDES := -I$(OUTPUT) -I$(BPF_INCLUDE) -I$(abspath ../../../../tools/lib) \ - -I$(abspath ../../../../tools/include/uapi) -CFLAGS := -g -Wall - -abs_out := $(abspath $(OUTPUT)) -ifeq ($(V),1) -Q = -msg = -else -Q = @ -msg = @printf ' %-8s %s%s\n' "$(1)" "$(notdir $(2))" "$(if $(3), $(3))"; -MAKEFLAGS += --no-print-directory -submake_extras := feature_display=0 -endif - -.DELETE_ON_ERROR: - -.PHONY: all clean - -all: iterators.skel.h - -clean: - $(call msg,CLEAN) - $(Q)rm -rf $(OUTPUT) iterators - -iterators.skel.h: $(OUTPUT)/iterators.bpf.o | $(BPFTOOL) - $(call msg,GEN-SKEL,$@) - $(Q)$(BPFTOOL) gen skeleton $< > $@ - - -$(OUTPUT)/iterators.bpf.o: iterators.bpf.c $(BPFOBJ) | $(OUTPUT) - $(call msg,BPF,$@) - $(Q)$(CLANG) -g -O2 -target bpf $(INCLUDES) \ - -c $(filter %.c,$^) -o $@ && \ - $(LLVM_STRIP) -g $@ - -$(OUTPUT): - $(call msg,MKDIR,$@) - $(Q)mkdir -p $(OUTPUT) - -$(BPFOBJ): $(wildcard $(LIBBPF_SRC)/*.[ch] $(LIBBPF_SRC)/Makefile) | $(OUTPUT) - $(Q)$(MAKE) $(submake_extras) -C $(LIBBPF_SRC) \ - OUTPUT=$(abspath $(dir $@))/ $(abspath $@) - -$(DEFAULT_BPFTOOL): - $(Q)$(MAKE) $(submake_extras) -C ../../../../tools/bpf/bpftool \ - prefix= OUTPUT=$(abs_out)/ DESTDIR=$(abs_out) install diff --git a/kernel/bpf/preload/iterators/README b/kernel/bpf/preload/iterators/README deleted file mode 100644 index 7fd6d39a9ad2..000000000000 --- a/kernel/bpf/preload/iterators/README +++ /dev/null @@ -1,4 +0,0 @@ -WARNING: -If you change "iterators.bpf.c" do "make -j" in this directory to rebuild "iterators.skel.h". -Make sure to have clang 10 installed. -See Documentation/bpf/bpf_devel_QA.rst diff --git a/kernel/bpf/preload/iterators/bpf_preload_common.h b/kernel/bpf/preload/iterators/bpf_preload_common.h deleted file mode 100644 index 8464d1a48c05..000000000000 --- a/kernel/bpf/preload/iterators/bpf_preload_common.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _BPF_PRELOAD_COMMON_H -#define _BPF_PRELOAD_COMMON_H - -#define BPF_PRELOAD_START 0x5555 -#define BPF_PRELOAD_END 0xAAAA - -struct bpf_preload_info { - char link_name[16]; - int link_id; -}; - -#endif diff --git a/kernel/bpf/preload/iterators/iterators.bpf.c b/kernel/bpf/preload/iterators/iterators.bpf.c deleted file mode 100644 index 52aa7b38e8b8..000000000000 --- a/kernel/bpf/preload/iterators/iterators.bpf.c +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2020 Facebook */ -#include -#include -#include -#include - -#pragma clang attribute push (__attribute__((preserve_access_index)), apply_to = record) -struct seq_file; -struct bpf_iter_meta { - struct seq_file *seq; - __u64 session_id; - __u64 seq_num; -}; - -struct bpf_map { - __u32 id; - char name[16]; - __u32 max_entries; -}; - -struct bpf_iter__bpf_map { - struct bpf_iter_meta *meta; - struct bpf_map *map; -}; - -struct btf_type { - __u32 name_off; -}; - -struct btf_header { - __u32 str_len; -}; - -struct btf { - const char *strings; - struct btf_type **types; - struct btf_header hdr; -}; - -struct bpf_prog_aux { - __u32 id; - char name[16]; - const char *attach_func_name; - struct bpf_prog *dst_prog; - struct bpf_func_info *func_info; - struct btf *btf; -}; - -struct bpf_prog { - struct bpf_prog_aux *aux; -}; - -struct bpf_iter__bpf_prog { - struct bpf_iter_meta *meta; - struct bpf_prog *prog; -}; -#pragma clang attribute pop - -static const char *get_name(struct btf *btf, long btf_id, const char *fallback) -{ - struct btf_type **types, *t; - unsigned int name_off; - const char *str; - - if (!btf) - return fallback; - str = btf->strings; - types = btf->types; - bpf_probe_read_kernel(&t, sizeof(t), types + btf_id); - name_off = BPF_CORE_READ(t, name_off); - if (name_off >= btf->hdr.str_len) - return fallback; - return str + name_off; -} - -SEC("iter/bpf_map") -int dump_bpf_map(struct bpf_iter__bpf_map *ctx) -{ - struct seq_file *seq = ctx->meta->seq; - __u64 seq_num = ctx->meta->seq_num; - struct bpf_map *map = ctx->map; - - if (!map) - return 0; - - if (seq_num == 0) - BPF_SEQ_PRINTF(seq, " id name max_entries\n"); - - BPF_SEQ_PRINTF(seq, "%4u %-16s%6d\n", map->id, map->name, map->max_entries); - return 0; -} - -SEC("iter/bpf_prog") -int dump_bpf_prog(struct bpf_iter__bpf_prog *ctx) -{ - struct seq_file *seq = ctx->meta->seq; - __u64 seq_num = ctx->meta->seq_num; - struct bpf_prog *prog = ctx->prog; - struct bpf_prog_aux *aux; - - if (!prog) - return 0; - - aux = prog->aux; - if (seq_num == 0) - BPF_SEQ_PRINTF(seq, " id name attached\n"); - - BPF_SEQ_PRINTF(seq, "%4u %-16s %s %s\n", aux->id, - get_name(aux->btf, aux->func_info[0].type_id, aux->name), - aux->attach_func_name, aux->dst_prog->aux->name); - return 0; -} -char LICENSE[] SEC("license") = "GPL"; diff --git a/kernel/bpf/preload/iterators/iterators.c b/kernel/bpf/preload/iterators/iterators.c deleted file mode 100644 index b7ff87939172..000000000000 --- a/kernel/bpf/preload/iterators/iterators.c +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2020 Facebook */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "iterators.skel.h" -#include "bpf_preload_common.h" - -int to_kernel = -1; -int from_kernel = 0; - -static int send_link_to_kernel(struct bpf_link *link, const char *link_name) -{ - struct bpf_preload_info obj = {}; - struct bpf_link_info info = {}; - __u32 info_len = sizeof(info); - int err; - - err = bpf_obj_get_info_by_fd(bpf_link__fd(link), &info, &info_len); - if (err) - return err; - obj.link_id = info.id; - if (strlen(link_name) >= sizeof(obj.link_name)) - return -E2BIG; - strcpy(obj.link_name, link_name); - if (write(to_kernel, &obj, sizeof(obj)) != sizeof(obj)) - return -EPIPE; - return 0; -} - -int main(int argc, char **argv) -{ - struct rlimit rlim = { RLIM_INFINITY, RLIM_INFINITY }; - struct iterators_bpf *skel; - int err, magic; - int debug_fd; - - debug_fd = open("/dev/console", O_WRONLY | O_NOCTTY | O_CLOEXEC); - if (debug_fd < 0) - return 1; - to_kernel = dup(1); - close(1); - dup(debug_fd); - /* now stdin and stderr point to /dev/console */ - - read(from_kernel, &magic, sizeof(magic)); - if (magic != BPF_PRELOAD_START) { - printf("bad start magic %d\n", magic); - return 1; - } - setrlimit(RLIMIT_MEMLOCK, &rlim); - /* libbpf opens BPF object and loads it into the kernel */ - skel = iterators_bpf__open_and_load(); - if (!skel) { - /* iterators.skel.h is little endian. - * libbpf doesn't support automatic little->big conversion - * of BPF bytecode yet. - * The program load will fail in such case. - */ - printf("Failed load could be due to wrong endianness\n"); - return 1; - } - err = iterators_bpf__attach(skel); - if (err) - goto cleanup; - - /* send two bpf_link IDs with names to the kernel */ - err = send_link_to_kernel(skel->links.dump_bpf_map, "maps.debug"); - if (err) - goto cleanup; - err = send_link_to_kernel(skel->links.dump_bpf_prog, "progs.debug"); - if (err) - goto cleanup; - - /* The kernel will proceed with pinnging the links in bpffs. - * UMD will wait on read from pipe. - */ - read(from_kernel, &magic, sizeof(magic)); - if (magic != BPF_PRELOAD_END) { - printf("bad final magic %d\n", magic); - err = -EINVAL; - } -cleanup: - iterators_bpf__destroy(skel); - - return err != 0; -} diff --git a/kernel/bpf/preload/iterators/iterators.skel.h b/kernel/bpf/preload/iterators/iterators.skel.h deleted file mode 100644 index cf9a6a94b3a4..000000000000 --- a/kernel/bpf/preload/iterators/iterators.skel.h +++ /dev/null @@ -1,412 +0,0 @@ -/* SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) */ - -/* THIS FILE IS AUTOGENERATED! */ -#ifndef __ITERATORS_BPF_SKEL_H__ -#define __ITERATORS_BPF_SKEL_H__ - -#include -#include - -struct iterators_bpf { - struct bpf_object_skeleton *skeleton; - struct bpf_object *obj; - struct { - struct bpf_map *rodata; - } maps; - struct { - struct bpf_program *dump_bpf_map; - struct bpf_program *dump_bpf_prog; - } progs; - struct { - struct bpf_link *dump_bpf_map; - struct bpf_link *dump_bpf_prog; - } links; - struct iterators_bpf__rodata { - char dump_bpf_map____fmt[35]; - char dump_bpf_map____fmt_1[14]; - char dump_bpf_prog____fmt[32]; - char dump_bpf_prog____fmt_2[17]; - } *rodata; -}; - -static void -iterators_bpf__destroy(struct iterators_bpf *obj) -{ - if (!obj) - return; - if (obj->skeleton) - bpf_object__destroy_skeleton(obj->skeleton); - free(obj); -} - -static inline int -iterators_bpf__create_skeleton(struct iterators_bpf *obj); - -static inline struct iterators_bpf * -iterators_bpf__open_opts(const struct bpf_object_open_opts *opts) -{ - struct iterators_bpf *obj; - - obj = (struct iterators_bpf *)calloc(1, sizeof(*obj)); - if (!obj) - return NULL; - if (iterators_bpf__create_skeleton(obj)) - goto err; - if (bpf_object__open_skeleton(obj->skeleton, opts)) - goto err; - - return obj; -err: - iterators_bpf__destroy(obj); - return NULL; -} - -static inline struct iterators_bpf * -iterators_bpf__open(void) -{ - return iterators_bpf__open_opts(NULL); -} - -static inline int -iterators_bpf__load(struct iterators_bpf *obj) -{ - return bpf_object__load_skeleton(obj->skeleton); -} - -static inline struct iterators_bpf * -iterators_bpf__open_and_load(void) -{ - struct iterators_bpf *obj; - - obj = iterators_bpf__open(); - if (!obj) - return NULL; - if (iterators_bpf__load(obj)) { - iterators_bpf__destroy(obj); - return NULL; - } - return obj; -} - -static inline int -iterators_bpf__attach(struct iterators_bpf *obj) -{ - return bpf_object__attach_skeleton(obj->skeleton); -} - -static inline void -iterators_bpf__detach(struct iterators_bpf *obj) -{ - return bpf_object__detach_skeleton(obj->skeleton); -} - -static inline int -iterators_bpf__create_skeleton(struct iterators_bpf *obj) -{ - struct bpf_object_skeleton *s; - - s = (struct bpf_object_skeleton *)calloc(1, sizeof(*s)); - if (!s) - return -1; - obj->skeleton = s; - - s->sz = sizeof(*s); - s->name = "iterators_bpf"; - s->obj = &obj->obj; - - /* maps */ - s->map_cnt = 1; - s->map_skel_sz = sizeof(*s->maps); - s->maps = (struct bpf_map_skeleton *)calloc(s->map_cnt, s->map_skel_sz); - if (!s->maps) - goto err; - - s->maps[0].name = "iterator.rodata"; - s->maps[0].map = &obj->maps.rodata; - s->maps[0].mmaped = (void **)&obj->rodata; - - /* programs */ - s->prog_cnt = 2; - s->prog_skel_sz = sizeof(*s->progs); - s->progs = (struct bpf_prog_skeleton *)calloc(s->prog_cnt, s->prog_skel_sz); - if (!s->progs) - goto err; - - s->progs[0].name = "dump_bpf_map"; - s->progs[0].prog = &obj->progs.dump_bpf_map; - s->progs[0].link = &obj->links.dump_bpf_map; - - s->progs[1].name = "dump_bpf_prog"; - s->progs[1].prog = &obj->progs.dump_bpf_prog; - s->progs[1].link = &obj->links.dump_bpf_prog; - - s->data_sz = 7176; - s->data = (void *)"\ -\x7f\x45\x4c\x46\x02\x01\x01\0\0\0\0\0\0\0\0\0\x01\0\xf7\0\x01\0\0\0\0\0\0\0\0\ -\0\0\0\0\0\0\0\0\0\0\0\x48\x18\0\0\0\0\0\0\0\0\0\0\x40\0\0\0\0\0\x40\0\x0f\0\ -\x0e\0\x79\x12\0\0\0\0\0\0\x79\x26\0\0\0\0\0\0\x79\x17\x08\0\0\0\0\0\x15\x07\ -\x1a\0\0\0\0\0\x79\x21\x10\0\0\0\0\0\x55\x01\x08\0\0\0\0\0\xbf\xa4\0\0\0\0\0\0\ -\x07\x04\0\0\xe8\xff\xff\xff\xbf\x61\0\0\0\0\0\0\x18\x02\0\0\0\0\0\0\0\0\0\0\0\ -\0\0\0\xb7\x03\0\0\x23\0\0\0\xb7\x05\0\0\0\0\0\0\x85\0\0\0\x7e\0\0\0\x61\x71\0\ -\0\0\0\0\0\x7b\x1a\xe8\xff\0\0\0\0\xb7\x01\0\0\x04\0\0\0\xbf\x72\0\0\0\0\0\0\ -\x0f\x12\0\0\0\0\0\0\x7b\x2a\xf0\xff\0\0\0\0\x61\x71\x14\0\0\0\0\0\x7b\x1a\xf8\ -\xff\0\0\0\0\xbf\xa4\0\0\0\0\0\0\x07\x04\0\0\xe8\xff\xff\xff\xbf\x61\0\0\0\0\0\ -\0\x18\x02\0\0\x23\0\0\0\0\0\0\0\0\0\0\0\xb7\x03\0\0\x0e\0\0\0\xb7\x05\0\0\x18\ -\0\0\0\x85\0\0\0\x7e\0\0\0\xb7\0\0\0\0\0\0\0\x95\0\0\0\0\0\0\0\x79\x12\0\0\0\0\ -\0\0\x79\x26\0\0\0\0\0\0\x79\x11\x08\0\0\0\0\0\x15\x01\x3b\0\0\0\0\0\x79\x17\0\ -\0\0\0\0\0\x79\x21\x10\0\0\0\0\0\x55\x01\x08\0\0\0\0\0\xbf\xa4\0\0\0\0\0\0\x07\ -\x04\0\0\xd0\xff\xff\xff\xbf\x61\0\0\0\0\0\0\x18\x02\0\0\x31\0\0\0\0\0\0\0\0\0\ -\0\0\xb7\x03\0\0\x20\0\0\0\xb7\x05\0\0\0\0\0\0\x85\0\0\0\x7e\0\0\0\x7b\x6a\xc8\ -\xff\0\0\0\0\x61\x71\0\0\0\0\0\0\x7b\x1a\xd0\xff\0\0\0\0\xb7\x03\0\0\x04\0\0\0\ -\xbf\x79\0\0\0\0\0\0\x0f\x39\0\0\0\0\0\0\x79\x71\x28\0\0\0\0\0\x79\x78\x30\0\0\ -\0\0\0\x15\x08\x18\0\0\0\0\0\xb7\x02\0\0\0\0\0\0\x0f\x21\0\0\0\0\0\0\x61\x11\ -\x04\0\0\0\0\0\x79\x83\x08\0\0\0\0\0\x67\x01\0\0\x03\0\0\0\x0f\x13\0\0\0\0\0\0\ -\x79\x86\0\0\0\0\0\0\xbf\xa1\0\0\0\0\0\0\x07\x01\0\0\xf8\xff\xff\xff\xb7\x02\0\ -\0\x08\0\0\0\x85\0\0\0\x71\0\0\0\xb7\x01\0\0\0\0\0\0\x79\xa3\xf8\xff\0\0\0\0\ -\x0f\x13\0\0\0\0\0\0\xbf\xa1\0\0\0\0\0\0\x07\x01\0\0\xf4\xff\xff\xff\xb7\x02\0\ -\0\x04\0\0\0\x85\0\0\0\x71\0\0\0\xb7\x03\0\0\x04\0\0\0\x61\xa1\xf4\xff\0\0\0\0\ -\x61\x82\x10\0\0\0\0\0\x3d\x21\x02\0\0\0\0\0\x0f\x16\0\0\0\0\0\0\xbf\x69\0\0\0\ -\0\0\0\x7b\x9a\xd8\xff\0\0\0\0\x79\x71\x18\0\0\0\0\0\x7b\x1a\xe0\xff\0\0\0\0\ -\x79\x71\x20\0\0\0\0\0\x79\x11\0\0\0\0\0\0\x0f\x31\0\0\0\0\0\0\x7b\x1a\xe8\xff\ -\0\0\0\0\xbf\xa4\0\0\0\0\0\0\x07\x04\0\0\xd0\xff\xff\xff\x79\xa1\xc8\xff\0\0\0\ -\0\x18\x02\0\0\x51\0\0\0\0\0\0\0\0\0\0\0\xb7\x03\0\0\x11\0\0\0\xb7\x05\0\0\x20\ -\0\0\0\x85\0\0\0\x7e\0\0\0\xb7\0\0\0\0\0\0\0\x95\0\0\0\0\0\0\0\x20\x20\x69\x64\ -\x20\x6e\x61\x6d\x65\x20\x20\x20\x20\x20\x20\x20\x20\x20\x20\x20\x20\x20\x6d\ -\x61\x78\x5f\x65\x6e\x74\x72\x69\x65\x73\x0a\0\x25\x34\x75\x20\x25\x2d\x31\x36\ -\x73\x25\x36\x64\x0a\0\x20\x20\x69\x64\x20\x6e\x61\x6d\x65\x20\x20\x20\x20\x20\ -\x20\x20\x20\x20\x20\x20\x20\x20\x61\x74\x74\x61\x63\x68\x65\x64\x0a\0\x25\x34\ -\x75\x20\x25\x2d\x31\x36\x73\x20\x25\x73\x20\x25\x73\x0a\0\x47\x50\x4c\0\x9f\ -\xeb\x01\0\x18\0\0\0\0\0\0\0\x1c\x04\0\0\x1c\x04\0\0\x09\x05\0\0\0\0\0\0\0\0\0\ -\x02\x02\0\0\0\x01\0\0\0\x02\0\0\x04\x10\0\0\0\x13\0\0\0\x03\0\0\0\0\0\0\0\x18\ -\0\0\0\x04\0\0\0\x40\0\0\0\0\0\0\0\0\0\0\x02\x08\0\0\0\0\0\0\0\0\0\0\x02\x0d\0\ -\0\0\0\0\0\0\x01\0\0\x0d\x06\0\0\0\x1c\0\0\0\x01\0\0\0\x20\0\0\0\0\0\0\x01\x04\ -\0\0\0\x20\0\0\x01\x24\0\0\0\x01\0\0\x0c\x05\0\0\0\xaf\0\0\0\x03\0\0\x04\x18\0\ -\0\0\xbd\0\0\0\x09\0\0\0\0\0\0\0\xc1\0\0\0\x0b\0\0\0\x40\0\0\0\xcc\0\0\0\x0b\0\ -\0\0\x80\0\0\0\0\0\0\0\0\0\0\x02\x0a\0\0\0\xd4\0\0\0\0\0\0\x07\0\0\0\0\xdd\0\0\ -\0\0\0\0\x08\x0c\0\0\0\xe3\0\0\0\0\0\0\x01\x08\0\0\0\x40\0\0\0\xa4\x01\0\0\x03\ -\0\0\x04\x18\0\0\0\xac\x01\0\0\x0e\0\0\0\0\0\0\0\xaf\x01\0\0\x11\0\0\0\x20\0\0\ -\0\xb4\x01\0\0\x0e\0\0\0\xa0\0\0\0\xc0\x01\0\0\0\0\0\x08\x0f\0\0\0\xc6\x01\0\0\ -\0\0\0\x01\x04\0\0\0\x20\0\0\0\xd3\x01\0\0\0\0\0\x01\x01\0\0\0\x08\0\0\x01\0\0\ -\0\0\0\0\0\x03\0\0\0\0\x10\0\0\0\x12\0\0\0\x10\0\0\0\xd8\x01\0\0\0\0\0\x01\x04\ -\0\0\0\x20\0\0\0\0\0\0\0\0\0\0\x02\x14\0\0\0\x3c\x02\0\0\x02\0\0\x04\x10\0\0\0\ -\x13\0\0\0\x03\0\0\0\0\0\0\0\x4f\x02\0\0\x15\0\0\0\x40\0\0\0\0\0\0\0\0\0\0\x02\ -\x18\0\0\0\0\0\0\0\x01\0\0\x0d\x06\0\0\0\x1c\0\0\0\x13\0\0\0\x54\x02\0\0\x01\0\ -\0\x0c\x16\0\0\0\xa0\x02\0\0\x01\0\0\x04\x08\0\0\0\xa9\x02\0\0\x19\0\0\0\0\0\0\ -\0\0\0\0\0\0\0\0\x02\x1a\0\0\0\xfa\x02\0\0\x06\0\0\x04\x38\0\0\0\xac\x01\0\0\ -\x0e\0\0\0\0\0\0\0\xaf\x01\0\0\x11\0\0\0\x20\0\0\0\x07\x03\0\0\x1b\0\0\0\xc0\0\ -\0\0\x18\x03\0\0\x15\0\0\0\0\x01\0\0\x21\x03\0\0\x1d\0\0\0\x40\x01\0\0\x2b\x03\ -\0\0\x1e\0\0\0\x80\x01\0\0\0\0\0\0\0\0\0\x02\x1c\0\0\0\0\0\0\0\0\0\0\x0a\x10\0\ -\0\0\0\0\0\0\0\0\0\x02\x1f\0\0\0\0\0\0\0\0\0\0\x02\x20\0\0\0\x75\x03\0\0\x02\0\ -\0\x04\x08\0\0\0\x83\x03\0\0\x0e\0\0\0\0\0\0\0\x8c\x03\0\0\x0e\0\0\0\x20\0\0\0\ -\x2b\x03\0\0\x03\0\0\x04\x18\0\0\0\x96\x03\0\0\x1b\0\0\0\0\0\0\0\x9e\x03\0\0\ -\x21\0\0\0\x40\0\0\0\xa4\x03\0\0\x23\0\0\0\x80\0\0\0\0\0\0\0\0\0\0\x02\x22\0\0\ -\0\0\0\0\0\0\0\0\x02\x24\0\0\0\xa8\x03\0\0\x01\0\0\x04\x04\0\0\0\xb3\x03\0\0\ -\x0e\0\0\0\0\0\0\0\x1c\x04\0\0\x01\0\0\x04\x04\0\0\0\x25\x04\0\0\x0e\0\0\0\0\0\ -\0\0\0\0\0\0\0\0\0\x03\0\0\0\0\x1c\0\0\0\x12\0\0\0\x23\0\0\0\x9b\x04\0\0\0\0\0\ -\x0e\x25\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x03\0\0\0\0\x1c\0\0\0\x12\0\0\0\x0e\0\0\0\ -\xaf\x04\0\0\0\0\0\x0e\x27\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x03\0\0\0\0\x1c\0\0\0\ -\x12\0\0\0\x20\0\0\0\xc5\x04\0\0\0\0\0\x0e\x29\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x03\ -\0\0\0\0\x1c\0\0\0\x12\0\0\0\x11\0\0\0\xda\x04\0\0\0\0\0\x0e\x2b\0\0\0\0\0\0\0\ -\0\0\0\0\0\0\0\x03\0\0\0\0\x10\0\0\0\x12\0\0\0\x04\0\0\0\xf1\x04\0\0\0\0\0\x0e\ -\x2d\0\0\0\x01\0\0\0\xf9\x04\0\0\x04\0\0\x0f\0\0\0\0\x26\0\0\0\0\0\0\0\x23\0\0\ -\0\x28\0\0\0\x23\0\0\0\x0e\0\0\0\x2a\0\0\0\x31\0\0\0\x20\0\0\0\x2c\0\0\0\x51\0\ -\0\0\x11\0\0\0\x01\x05\0\0\x01\0\0\x0f\0\0\0\0\x2e\0\0\0\0\0\0\0\x04\0\0\0\0\ -\x62\x70\x66\x5f\x69\x74\x65\x72\x5f\x5f\x62\x70\x66\x5f\x6d\x61\x70\0\x6d\x65\ -\x74\x61\0\x6d\x61\x70\0\x63\x74\x78\0\x69\x6e\x74\0\x64\x75\x6d\x70\x5f\x62\ -\x70\x66\x5f\x6d\x61\x70\0\x69\x74\x65\x72\x2f\x62\x70\x66\x5f\x6d\x61\x70\0\ -\x30\x3a\x30\0\x2f\x68\x6f\x6d\x65\x2f\x61\x6c\x72\x75\x61\x2f\x62\x75\x69\x6c\ -\x64\x2f\x6c\x69\x6e\x75\x78\x2f\x6b\x65\x72\x6e\x65\x6c\x2f\x62\x70\x66\x2f\ -\x70\x72\x65\x6c\x6f\x61\x64\x2f\x69\x74\x65\x72\x61\x74\x6f\x72\x73\x2f\x69\ -\x74\x65\x72\x61\x74\x6f\x72\x73\x2e\x62\x70\x66\x2e\x63\0\x09\x73\x74\x72\x75\ -\x63\x74\x20\x73\x65\x71\x5f\x66\x69\x6c\x65\x20\x2a\x73\x65\x71\x20\x3d\x20\ -\x63\x74\x78\x2d\x3e\x6d\x65\x74\x61\x2d\x3e\x73\x65\x71\x3b\0\x62\x70\x66\x5f\ -\x69\x74\x65\x72\x5f\x6d\x65\x74\x61\0\x73\x65\x71\0\x73\x65\x73\x73\x69\x6f\ -\x6e\x5f\x69\x64\0\x73\x65\x71\x5f\x6e\x75\x6d\0\x73\x65\x71\x5f\x66\x69\x6c\ -\x65\0\x5f\x5f\x75\x36\x34\0\x6c\x6f\x6e\x67\x20\x6c\x6f\x6e\x67\x20\x75\x6e\ -\x73\x69\x67\x6e\x65\x64\x20\x69\x6e\x74\0\x30\x3a\x31\0\x09\x73\x74\x72\x75\ -\x63\x74\x20\x62\x70\x66\x5f\x6d\x61\x70\x20\x2a\x6d\x61\x70\x20\x3d\x20\x63\ -\x74\x78\x2d\x3e\x6d\x61\x70\x3b\0\x09\x69\x66\x20\x28\x21\x6d\x61\x70\x29\0\ -\x30\x3a\x32\0\x09\x5f\x5f\x75\x36\x34\x20\x73\x65\x71\x5f\x6e\x75\x6d\x20\x3d\ -\x20\x63\x74\x78\x2d\x3e\x6d\x65\x74\x61\x2d\x3e\x73\x65\x71\x5f\x6e\x75\x6d\ -\x3b\0\x09\x69\x66\x20\x28\x73\x65\x71\x5f\x6e\x75\x6d\x20\x3d\x3d\x20\x30\x29\ -\0\x09\x09\x42\x50\x46\x5f\x53\x45\x51\x5f\x50\x52\x49\x4e\x54\x46\x28\x73\x65\ -\x71\x2c\x20\x22\x20\x20\x69\x64\x20\x6e\x61\x6d\x65\x20\x20\x20\x20\x20\x20\ -\x20\x20\x20\x20\x20\x20\x20\x6d\x61\x78\x5f\x65\x6e\x74\x72\x69\x65\x73\x5c\ -\x6e\x22\x29\x3b\0\x62\x70\x66\x5f\x6d\x61\x70\0\x69\x64\0\x6e\x61\x6d\x65\0\ -\x6d\x61\x78\x5f\x65\x6e\x74\x72\x69\x65\x73\0\x5f\x5f\x75\x33\x32\0\x75\x6e\ -\x73\x69\x67\x6e\x65\x64\x20\x69\x6e\x74\0\x63\x68\x61\x72\0\x5f\x5f\x41\x52\ -\x52\x41\x59\x5f\x53\x49\x5a\x45\x5f\x54\x59\x50\x45\x5f\x5f\0\x09\x42\x50\x46\ -\x5f\x53\x45\x51\x5f\x50\x52\x49\x4e\x54\x46\x28\x73\x65\x71\x2c\x20\x22\x25\ -\x34\x75\x20\x25\x2d\x31\x36\x73\x25\x36\x64\x5c\x6e\x22\x2c\x20\x6d\x61\x70\ -\x2d\x3e\x69\x64\x2c\x20\x6d\x61\x70\x2d\x3e\x6e\x61\x6d\x65\x2c\x20\x6d\x61\ -\x70\x2d\x3e\x6d\x61\x78\x5f\x65\x6e\x74\x72\x69\x65\x73\x29\x3b\0\x7d\0\x62\ -\x70\x66\x5f\x69\x74\x65\x72\x5f\x5f\x62\x70\x66\x5f\x70\x72\x6f\x67\0\x70\x72\ -\x6f\x67\0\x64\x75\x6d\x70\x5f\x62\x70\x66\x5f\x70\x72\x6f\x67\0\x69\x74\x65\ -\x72\x2f\x62\x70\x66\x5f\x70\x72\x6f\x67\0\x09\x73\x74\x72\x75\x63\x74\x20\x62\ -\x70\x66\x5f\x70\x72\x6f\x67\x20\x2a\x70\x72\x6f\x67\x20\x3d\x20\x63\x74\x78\ -\x2d\x3e\x70\x72\x6f\x67\x3b\0\x09\x69\x66\x20\x28\x21\x70\x72\x6f\x67\x29\0\ -\x62\x70\x66\x5f\x70\x72\x6f\x67\0\x61\x75\x78\0\x09\x61\x75\x78\x20\x3d\x20\ -\x70\x72\x6f\x67\x2d\x3e\x61\x75\x78\x3b\0\x09\x09\x42\x50\x46\x5f\x53\x45\x51\ -\x5f\x50\x52\x49\x4e\x54\x46\x28\x73\x65\x71\x2c\x20\x22\x20\x20\x69\x64\x20\ -\x6e\x61\x6d\x65\x20\x20\x20\x20\x20\x20\x20\x20\x20\x20\x20\x20\x20\x61\x74\ -\x74\x61\x63\x68\x65\x64\x5c\x6e\x22\x29\x3b\0\x62\x70\x66\x5f\x70\x72\x6f\x67\ -\x5f\x61\x75\x78\0\x61\x74\x74\x61\x63\x68\x5f\x66\x75\x6e\x63\x5f\x6e\x61\x6d\ -\x65\0\x64\x73\x74\x5f\x70\x72\x6f\x67\0\x66\x75\x6e\x63\x5f\x69\x6e\x66\x6f\0\ -\x62\x74\x66\0\x09\x42\x50\x46\x5f\x53\x45\x51\x5f\x50\x52\x49\x4e\x54\x46\x28\ -\x73\x65\x71\x2c\x20\x22\x25\x34\x75\x20\x25\x2d\x31\x36\x73\x20\x25\x73\x20\ -\x25\x73\x5c\x6e\x22\x2c\x20\x61\x75\x78\x2d\x3e\x69\x64\x2c\0\x30\x3a\x34\0\ -\x30\x3a\x35\0\x09\x69\x66\x20\x28\x21\x62\x74\x66\x29\0\x62\x70\x66\x5f\x66\ -\x75\x6e\x63\x5f\x69\x6e\x66\x6f\0\x69\x6e\x73\x6e\x5f\x6f\x66\x66\0\x74\x79\ -\x70\x65\x5f\x69\x64\0\x30\0\x73\x74\x72\x69\x6e\x67\x73\0\x74\x79\x70\x65\x73\ -\0\x68\x64\x72\0\x62\x74\x66\x5f\x68\x65\x61\x64\x65\x72\0\x73\x74\x72\x5f\x6c\ -\x65\x6e\0\x09\x74\x79\x70\x65\x73\x20\x3d\x20\x62\x74\x66\x2d\x3e\x74\x79\x70\ -\x65\x73\x3b\0\x09\x62\x70\x66\x5f\x70\x72\x6f\x62\x65\x5f\x72\x65\x61\x64\x5f\ -\x6b\x65\x72\x6e\x65\x6c\x28\x26\x74\x2c\x20\x73\x69\x7a\x65\x6f\x66\x28\x74\ -\x29\x2c\x20\x74\x79\x70\x65\x73\x20\x2b\x20\x62\x74\x66\x5f\x69\x64\x29\x3b\0\ -\x09\x73\x74\x72\x20\x3d\x20\x62\x74\x66\x2d\x3e\x73\x74\x72\x69\x6e\x67\x73\ -\x3b\0\x62\x74\x66\x5f\x74\x79\x70\x65\0\x6e\x61\x6d\x65\x5f\x6f\x66\x66\0\x09\ -\x6e\x61\x6d\x65\x5f\x6f\x66\x66\x20\x3d\x20\x42\x50\x46\x5f\x43\x4f\x52\x45\ -\x5f\x52\x45\x41\x44\x28\x74\x2c\x20\x6e\x61\x6d\x65\x5f\x6f\x66\x66\x29\x3b\0\ -\x30\x3a\x32\x3a\x30\0\x09\x69\x66\x20\x28\x6e\x61\x6d\x65\x5f\x6f\x66\x66\x20\ -\x3e\x3d\x20\x62\x74\x66\x2d\x3e\x68\x64\x72\x2e\x73\x74\x72\x5f\x6c\x65\x6e\ -\x29\0\x09\x72\x65\x74\x75\x72\x6e\x20\x73\x74\x72\x20\x2b\x20\x6e\x61\x6d\x65\ -\x5f\x6f\x66\x66\x3b\0\x30\x3a\x33\0\x64\x75\x6d\x70\x5f\x62\x70\x66\x5f\x6d\ -\x61\x70\x2e\x5f\x5f\x5f\x66\x6d\x74\0\x64\x75\x6d\x70\x5f\x62\x70\x66\x5f\x6d\ -\x61\x70\x2e\x5f\x5f\x5f\x66\x6d\x74\x2e\x31\0\x64\x75\x6d\x70\x5f\x62\x70\x66\ -\x5f\x70\x72\x6f\x67\x2e\x5f\x5f\x5f\x66\x6d\x74\0\x64\x75\x6d\x70\x5f\x62\x70\ -\x66\x5f\x70\x72\x6f\x67\x2e\x5f\x5f\x5f\x66\x6d\x74\x2e\x32\0\x4c\x49\x43\x45\ -\x4e\x53\x45\0\x2e\x72\x6f\x64\x61\x74\x61\0\x6c\x69\x63\x65\x6e\x73\x65\0\x9f\ -\xeb\x01\0\x20\0\0\0\0\0\0\0\x24\0\0\0\x24\0\0\0\x44\x02\0\0\x68\x02\0\0\xa4\ -\x01\0\0\x08\0\0\0\x31\0\0\0\x01\0\0\0\0\0\0\0\x07\0\0\0\x62\x02\0\0\x01\0\0\0\ -\0\0\0\0\x17\0\0\0\x10\0\0\0\x31\0\0\0\x09\0\0\0\0\0\0\0\x42\0\0\0\x87\0\0\0\ -\x1e\x40\x01\0\x08\0\0\0\x42\0\0\0\x87\0\0\0\x24\x40\x01\0\x10\0\0\0\x42\0\0\0\ -\xfe\0\0\0\x1d\x48\x01\0\x18\0\0\0\x42\0\0\0\x1f\x01\0\0\x06\x50\x01\0\x20\0\0\ -\0\x42\0\0\0\x2e\x01\0\0\x1d\x44\x01\0\x28\0\0\0\x42\0\0\0\x53\x01\0\0\x06\x5c\ -\x01\0\x38\0\0\0\x42\0\0\0\x66\x01\0\0\x03\x60\x01\0\x70\0\0\0\x42\0\0\0\xec\ -\x01\0\0\x02\x68\x01\0\xf0\0\0\0\x42\0\0\0\x3a\x02\0\0\x01\x70\x01\0\x62\x02\0\ -\0\x1a\0\0\0\0\0\0\0\x42\0\0\0\x87\0\0\0\x1e\x84\x01\0\x08\0\0\0\x42\0\0\0\x87\ -\0\0\0\x24\x84\x01\0\x10\0\0\0\x42\0\0\0\x70\x02\0\0\x1f\x8c\x01\0\x18\0\0\0\ -\x42\0\0\0\x94\x02\0\0\x06\x98\x01\0\x20\0\0\0\x42\0\0\0\xad\x02\0\0\x0e\xa4\ -\x01\0\x28\0\0\0\x42\0\0\0\x2e\x01\0\0\x1d\x88\x01\0\x30\0\0\0\x42\0\0\0\x53\ -\x01\0\0\x06\xa8\x01\0\x40\0\0\0\x42\0\0\0\xbf\x02\0\0\x03\xac\x01\0\x80\0\0\0\ -\x42\0\0\0\x2f\x03\0\0\x02\xb4\x01\0\xb8\0\0\0\x42\0\0\0\x6a\x03\0\0\x06\x08\ -\x01\0\xd0\0\0\0\x42\0\0\0\0\0\0\0\0\0\0\0\xd8\0\0\0\x42\0\0\0\xbb\x03\0\0\x0f\ -\x14\x01\0\xe0\0\0\0\x42\0\0\0\xd0\x03\0\0\x2d\x18\x01\0\xf0\0\0\0\x42\0\0\0\ -\x07\x04\0\0\x0d\x10\x01\0\0\x01\0\0\x42\0\0\0\0\0\0\0\0\0\0\0\x08\x01\0\0\x42\ -\0\0\0\xd0\x03\0\0\x02\x18\x01\0\x20\x01\0\0\x42\0\0\0\x2e\x04\0\0\x0d\x1c\x01\ -\0\x38\x01\0\0\x42\0\0\0\0\0\0\0\0\0\0\0\x40\x01\0\0\x42\0\0\0\x2e\x04\0\0\x0d\ -\x1c\x01\0\x58\x01\0\0\x42\0\0\0\x2e\x04\0\0\x0d\x1c\x01\0\x60\x01\0\0\x42\0\0\ -\0\x5c\x04\0\0\x1b\x20\x01\0\x68\x01\0\0\x42\0\0\0\x5c\x04\0\0\x06\x20\x01\0\ -\x70\x01\0\0\x42\0\0\0\x7f\x04\0\0\x0d\x28\x01\0\x78\x01\0\0\x42\0\0\0\0\0\0\0\ -\0\0\0\0\x80\x01\0\0\x42\0\0\0\x2f\x03\0\0\x02\xb4\x01\0\xf8\x01\0\0\x42\0\0\0\ -\x3a\x02\0\0\x01\xc4\x01\0\x10\0\0\0\x31\0\0\0\x07\0\0\0\0\0\0\0\x02\0\0\0\x3e\ -\0\0\0\0\0\0\0\x08\0\0\0\x08\0\0\0\x3e\0\0\0\0\0\0\0\x10\0\0\0\x02\0\0\0\xfa\0\ -\0\0\0\0\0\0\x20\0\0\0\x08\0\0\0\x2a\x01\0\0\0\0\0\0\x70\0\0\0\x0d\0\0\0\x3e\0\ -\0\0\0\0\0\0\x80\0\0\0\x0d\0\0\0\xfa\0\0\0\0\0\0\0\xa0\0\0\0\x0d\0\0\0\x2a\x01\ -\0\0\0\0\0\0\x62\x02\0\0\x12\0\0\0\0\0\0\0\x14\0\0\0\x3e\0\0\0\0\0\0\0\x08\0\0\ -\0\x08\0\0\0\x3e\0\0\0\0\0\0\0\x10\0\0\0\x14\0\0\0\xfa\0\0\0\0\0\0\0\x20\0\0\0\ -\x18\0\0\0\x3e\0\0\0\0\0\0\0\x28\0\0\0\x08\0\0\0\x2a\x01\0\0\0\0\0\0\x80\0\0\0\ -\x1a\0\0\0\x3e\0\0\0\0\0\0\0\x90\0\0\0\x1a\0\0\0\xfa\0\0\0\0\0\0\0\xa8\0\0\0\ -\x1a\0\0\0\x62\x03\0\0\0\0\0\0\xb0\0\0\0\x1a\0\0\0\x66\x03\0\0\0\0\0\0\xc0\0\0\ -\0\x1f\0\0\0\x94\x03\0\0\0\0\0\0\xd8\0\0\0\x20\0\0\0\xfa\0\0\0\0\0\0\0\xf0\0\0\ -\0\x20\0\0\0\x3e\0\0\0\0\0\0\0\x18\x01\0\0\x24\0\0\0\x3e\0\0\0\0\0\0\0\x50\x01\ -\0\0\x1a\0\0\0\xfa\0\0\0\0\0\0\0\x60\x01\0\0\x20\0\0\0\x56\x04\0\0\0\0\0\0\x88\ -\x01\0\0\x1a\0\0\0\x2a\x01\0\0\0\0\0\0\x98\x01\0\0\x1a\0\0\0\x97\x04\0\0\0\0\0\ -\0\xa0\x01\0\0\x18\0\0\0\x3e\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ -\0\0\0\0\0\0\0\x91\0\0\0\x04\0\xf1\xff\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\xe6\0\0\ -\0\0\0\x02\0\x70\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\xd8\0\0\0\0\0\x02\0\xf0\0\0\0\0\ -\0\0\0\0\0\0\0\0\0\0\0\xdf\0\0\0\0\0\x03\0\x78\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ -\xd1\0\0\0\0\0\x03\0\x80\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\0\xca\0\0\0\0\0\x03\0\ -\xf8\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x14\0\0\0\x01\0\x04\0\0\0\0\0\0\0\0\0\x23\ -\0\0\0\0\0\0\0\x04\x01\0\0\x01\0\x04\0\x23\0\0\0\0\0\0\0\x0e\0\0\0\0\0\0\0\x28\ -\0\0\0\x01\0\x04\0\x31\0\0\0\0\0\0\0\x20\0\0\0\0\0\0\0\xed\0\0\0\x01\0\x04\0\ -\x51\0\0\0\0\0\0\0\x11\0\0\0\0\0\0\0\0\0\0\0\x03\0\x02\0\0\0\0\0\0\0\0\0\0\0\0\ -\0\0\0\0\0\0\0\0\0\x03\0\x03\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x03\0\ -\x04\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\xc2\0\0\0\x11\0\x05\0\0\0\0\0\0\0\0\0\ -\x04\0\0\0\0\0\0\0\x3d\0\0\0\x12\0\x02\0\0\0\0\0\0\0\0\0\0\x01\0\0\0\0\0\0\x5b\ -\0\0\0\x12\0\x03\0\0\0\0\0\0\0\0\0\x08\x02\0\0\0\0\0\0\x48\0\0\0\0\0\0\0\x01\0\ -\0\0\x0d\0\0\0\xc8\0\0\0\0\0\0\0\x01\0\0\0\x0d\0\0\0\x50\0\0\0\0\0\0\0\x01\0\0\ -\0\x0d\0\0\0\xd0\x01\0\0\0\0\0\0\x01\0\0\0\x0d\0\0\0\xf0\x03\0\0\0\0\0\0\x0a\0\ -\0\0\x0d\0\0\0\xfc\x03\0\0\0\0\0\0\x0a\0\0\0\x0d\0\0\0\x08\x04\0\0\0\0\0\0\x0a\ -\0\0\0\x0d\0\0\0\x14\x04\0\0\0\0\0\0\x0a\0\0\0\x0d\0\0\0\x2c\x04\0\0\0\0\0\0\0\ -\0\0\0\x0e\0\0\0\x2c\0\0\0\0\0\0\0\0\0\0\0\x0b\0\0\0\x3c\0\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\x50\0\0\0\0\0\0\0\0\0\0\0\x0b\0\0\0\x60\0\0\0\0\0\0\0\0\0\0\0\x0b\0\ -\0\0\x70\0\0\0\0\0\0\0\0\0\0\0\x0b\0\0\0\x80\0\0\0\0\0\0\0\0\0\0\0\x0b\0\0\0\ -\x90\0\0\0\0\0\0\0\0\0\0\0\x0b\0\0\0\xa0\0\0\0\0\0\0\0\0\0\0\0\x0b\0\0\0\xb0\0\ -\0\0\0\0\0\0\0\0\0\0\x0b\0\0\0\xc0\0\0\0\0\0\0\0\0\0\0\0\x0b\0\0\0\xd0\0\0\0\0\ -\0\0\0\0\0\0\0\x0b\0\0\0\xe8\0\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\xf8\0\0\0\0\0\0\0\ -\0\0\0\0\x0c\0\0\0\x08\x01\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\x18\x01\0\0\0\0\0\0\0\ -\0\0\0\x0c\0\0\0\x28\x01\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\x38\x01\0\0\0\0\0\0\0\0\ -\0\0\x0c\0\0\0\x48\x01\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\x58\x01\0\0\0\0\0\0\0\0\0\ -\0\x0c\0\0\0\x68\x01\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\x78\x01\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\x88\x01\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\x98\x01\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\xa8\x01\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\xb8\x01\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\xc8\x01\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\xd8\x01\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\xe8\x01\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\xf8\x01\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\x08\x02\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\x18\x02\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\x28\x02\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\x38\x02\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\x48\x02\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\x58\x02\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\x68\x02\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\x78\x02\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\x94\x02\0\0\0\0\0\0\0\0\0\0\x0b\0\0\0\xa4\x02\0\0\0\0\0\0\0\0\0\0\ -\x0b\0\0\0\xb4\x02\0\0\0\0\0\0\0\0\0\0\x0b\0\0\0\xc4\x02\0\0\0\0\0\0\0\0\0\0\ -\x0b\0\0\0\xd4\x02\0\0\0\0\0\0\0\0\0\0\x0b\0\0\0\xe4\x02\0\0\0\0\0\0\0\0\0\0\ -\x0b\0\0\0\xf4\x02\0\0\0\0\0\0\0\0\0\0\x0b\0\0\0\x0c\x03\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\x1c\x03\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\x2c\x03\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\x3c\x03\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\x4c\x03\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\x5c\x03\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\x6c\x03\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\x7c\x03\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\x8c\x03\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\x9c\x03\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\xac\x03\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\xbc\x03\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\xcc\x03\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\xdc\x03\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\xec\x03\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\xfc\x03\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\x0c\x04\0\0\0\0\0\0\0\0\0\0\ -\x0c\0\0\0\x1c\x04\0\0\0\0\0\0\0\0\0\0\x0c\0\0\0\x4d\x4e\x40\x41\x42\x43\x4c\0\ -\x2e\x74\x65\x78\x74\0\x2e\x72\x65\x6c\x2e\x42\x54\x46\x2e\x65\x78\x74\0\x64\ -\x75\x6d\x70\x5f\x62\x70\x66\x5f\x6d\x61\x70\x2e\x5f\x5f\x5f\x66\x6d\x74\0\x64\ -\x75\x6d\x70\x5f\x62\x70\x66\x5f\x70\x72\x6f\x67\x2e\x5f\x5f\x5f\x66\x6d\x74\0\ -\x64\x75\x6d\x70\x5f\x62\x70\x66\x5f\x6d\x61\x70\0\x2e\x72\x65\x6c\x69\x74\x65\ -\x72\x2f\x62\x70\x66\x5f\x6d\x61\x70\0\x64\x75\x6d\x70\x5f\x62\x70\x66\x5f\x70\ -\x72\x6f\x67\0\x2e\x72\x65\x6c\x69\x74\x65\x72\x2f\x62\x70\x66\x5f\x70\x72\x6f\ -\x67\0\x2e\x6c\x6c\x76\x6d\x5f\x61\x64\x64\x72\x73\x69\x67\0\x6c\x69\x63\x65\ -\x6e\x73\x65\0\x69\x74\x65\x72\x61\x74\x6f\x72\x73\x2e\x62\x70\x66\x2e\x63\0\ -\x2e\x73\x74\x72\x74\x61\x62\0\x2e\x73\x79\x6d\x74\x61\x62\0\x2e\x72\x6f\x64\ -\x61\x74\x61\0\x2e\x72\x65\x6c\x2e\x42\x54\x46\0\x4c\x49\x43\x45\x4e\x53\x45\0\ -\x4c\x42\x42\x31\x5f\x37\0\x4c\x42\x42\x31\x5f\x36\0\x4c\x42\x42\x30\x5f\x34\0\ -\x4c\x42\x42\x31\x5f\x33\0\x4c\x42\x42\x30\x5f\x33\0\x64\x75\x6d\x70\x5f\x62\ -\x70\x66\x5f\x70\x72\x6f\x67\x2e\x5f\x5f\x5f\x66\x6d\x74\x2e\x32\0\x64\x75\x6d\ -\x70\x5f\x62\x70\x66\x5f\x6d\x61\x70\x2e\x5f\x5f\x5f\x66\x6d\x74\x2e\x31\0\0\0\ -\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ -\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x01\0\0\0\x01\0\0\ -\0\x06\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x40\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ -\0\0\0\0\x04\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4e\0\0\0\x01\0\0\0\x06\0\0\0\0\0\0\ -\0\0\0\0\0\0\0\0\0\x40\0\0\0\0\0\0\0\0\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x08\0\0\ -\0\0\0\0\0\0\0\0\0\0\0\0\0\x6d\0\0\0\x01\0\0\0\x06\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ -\0\x40\x01\0\0\0\0\0\0\x08\x02\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x08\0\0\0\0\0\0\0\0\ -\0\0\0\0\0\0\0\xb1\0\0\0\x01\0\0\0\x02\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x48\x03\0\ -\0\0\0\0\0\x62\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ -\x89\0\0\0\x01\0\0\0\x03\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\xaa\x03\0\0\0\0\0\0\x04\ -\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\xbd\0\0\0\x01\ -\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\xae\x03\0\0\0\0\0\0\x3d\x09\0\0\0\0\0\0\ -\0\0\0\0\0\0\0\0\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x0b\0\0\0\x01\0\0\0\0\0\0\0\ -\0\0\0\0\0\0\0\0\0\0\0\0\xeb\x0c\0\0\0\0\0\0\x2c\x04\0\0\0\0\0\0\0\0\0\0\0\0\0\ -\0\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\xa9\0\0\0\x02\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ -\0\0\0\0\0\x18\x11\0\0\0\0\0\0\x98\x01\0\0\0\0\0\0\x0e\0\0\0\x0e\0\0\0\x08\0\0\ -\0\0\0\0\0\x18\0\0\0\0\0\0\0\x4a\0\0\0\x09\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ -\0\xb0\x12\0\0\0\0\0\0\x20\0\0\0\0\0\0\0\x08\0\0\0\x02\0\0\0\x08\0\0\0\0\0\0\0\ -\x10\0\0\0\0\0\0\0\x69\0\0\0\x09\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\xd0\x12\ -\0\0\0\0\0\0\x20\0\0\0\0\0\0\0\x08\0\0\0\x03\0\0\0\x08\0\0\0\0\0\0\0\x10\0\0\0\ -\0\0\0\0\xb9\0\0\0\x09\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\xf0\x12\0\0\0\0\0\ -\0\x50\0\0\0\0\0\0\0\x08\0\0\0\x06\0\0\0\x08\0\0\0\0\0\0\0\x10\0\0\0\0\0\0\0\ -\x07\0\0\0\x09\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x40\x13\0\0\0\0\0\0\xe0\ -\x03\0\0\0\0\0\0\x08\0\0\0\x07\0\0\0\x08\0\0\0\0\0\0\0\x10\0\0\0\0\0\0\0\x7b\0\ -\0\0\x03\x4c\xff\x6f\0\0\0\x80\0\0\0\0\0\0\0\0\0\0\0\0\x20\x17\0\0\0\0\0\0\x07\ -\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\xa1\0\0\0\x03\ -\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x27\x17\0\0\0\0\0\0\x1a\x01\0\0\0\0\0\0\ -\0\0\0\0\0\0\0\0\x01\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"; - - return 0; -err: - bpf_object__destroy_skeleton(s); - return -1; -} - -#endif /* __ITERATORS_BPF_SKEL_H__ */ diff --git a/kernel/bpf/prog_iter.c b/kernel/bpf/prog_iter.c deleted file mode 100644 index 53a73c841c13..000000000000 --- a/kernel/bpf/prog_iter.c +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2020 Facebook */ -#include -#include -#include -#include -#include - -struct bpf_iter_seq_prog_info { - u32 prog_id; -}; - -static void *bpf_prog_seq_start(struct seq_file *seq, loff_t *pos) -{ - struct bpf_iter_seq_prog_info *info = seq->private; - struct bpf_prog *prog; - - prog = bpf_prog_get_curr_or_next(&info->prog_id); - if (!prog) - return NULL; - - if (*pos == 0) - ++*pos; - return prog; -} - -static void *bpf_prog_seq_next(struct seq_file *seq, void *v, loff_t *pos) -{ - struct bpf_iter_seq_prog_info *info = seq->private; - - ++*pos; - ++info->prog_id; - bpf_prog_put((struct bpf_prog *)v); - return bpf_prog_get_curr_or_next(&info->prog_id); -} - -struct bpf_iter__bpf_prog { - __bpf_md_ptr(struct bpf_iter_meta *, meta); - __bpf_md_ptr(struct bpf_prog *, prog); -}; - -DEFINE_BPF_ITER_FUNC(bpf_prog, struct bpf_iter_meta *meta, struct bpf_prog *prog) - -static int __bpf_prog_seq_show(struct seq_file *seq, void *v, bool in_stop) -{ - struct bpf_iter__bpf_prog ctx; - struct bpf_iter_meta meta; - struct bpf_prog *prog; - int ret = 0; - - ctx.meta = &meta; - ctx.prog = v; - meta.seq = seq; - prog = bpf_iter_get_info(&meta, in_stop); - if (prog) - ret = bpf_iter_run_prog(prog, &ctx); - - return ret; -} - -static int bpf_prog_seq_show(struct seq_file *seq, void *v) -{ - return __bpf_prog_seq_show(seq, v, false); -} - -static void bpf_prog_seq_stop(struct seq_file *seq, void *v) -{ - if (!v) - (void)__bpf_prog_seq_show(seq, v, true); - else - bpf_prog_put((struct bpf_prog *)v); -} - -static const struct seq_operations bpf_prog_seq_ops = { - .start = bpf_prog_seq_start, - .next = bpf_prog_seq_next, - .stop = bpf_prog_seq_stop, - .show = bpf_prog_seq_show, -}; - -BTF_ID_LIST(btf_bpf_prog_id) -BTF_ID(struct, bpf_prog) - -static const struct bpf_iter_seq_info bpf_prog_seq_info = { - .seq_ops = &bpf_prog_seq_ops, - .init_seq_private = NULL, - .fini_seq_private = NULL, - .seq_priv_size = sizeof(struct bpf_iter_seq_prog_info), -}; - -static struct bpf_iter_reg bpf_prog_reg_info = { - .target = "bpf_prog", - .ctx_arg_info_size = 1, - .ctx_arg_info = { - { offsetof(struct bpf_iter__bpf_prog, prog), - PTR_TO_BTF_ID_OR_NULL }, - }, - .seq_info = &bpf_prog_seq_info, -}; - -static int __init bpf_prog_iter_init(void) -{ - bpf_prog_reg_info.ctx_arg_info[0].btf_id = *btf_bpf_prog_id; - return bpf_iter_reg_target(&bpf_prog_reg_info); -} - -late_initcall(bpf_prog_iter_init); diff --git a/kernel/bpf/queue_stack_maps.c b/kernel/bpf/queue_stack_maps.c index a047a2053d41..26ba7cb01136 100644 --- a/kernel/bpf/queue_stack_maps.c +++ b/kernel/bpf/queue_stack_maps.c @@ -19,7 +19,7 @@ struct bpf_queue_stack { u32 head, tail; u32 size; /* max_entries + 1 */ - char elements[] __aligned(8); + char elements[0] __aligned(8); }; static struct bpf_queue_stack *bpf_queue_stack(struct bpf_map *map) @@ -45,7 +45,7 @@ static bool queue_stack_map_is_full(struct bpf_queue_stack *qs) /* Called from syscall */ static int queue_stack_map_alloc_check(union bpf_attr *attr) { - if (!bpf_capable()) + if (!capable(CAP_SYS_ADMIN)) return -EPERM; /* check sanity of attributes */ @@ -101,6 +101,13 @@ static void queue_stack_map_free(struct bpf_map *map) { struct bpf_queue_stack *qs = bpf_queue_stack(map); + /* at this point bpf_prog->aux->refcnt == 0 and this map->refcnt == 0, + * so the programs (can be more than one that used this map) were + * disconnected from events. Wait for outstanding critical sections in + * these programs to complete + */ + synchronize_rcu(); + bpf_map_area_free(qs); } @@ -270,9 +277,7 @@ static int queue_stack_map_get_next_key(struct bpf_map *map, void *key, return -EINVAL; } -static int queue_map_btf_id; const struct bpf_map_ops queue_map_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc_check = queue_stack_map_alloc_check, .map_alloc = queue_stack_map_alloc, .map_free = queue_stack_map_free, @@ -283,13 +288,9 @@ const struct bpf_map_ops queue_map_ops = { .map_pop_elem = queue_map_pop_elem, .map_peek_elem = queue_map_peek_elem, .map_get_next_key = queue_stack_map_get_next_key, - .map_btf_name = "bpf_queue_stack", - .map_btf_id = &queue_map_btf_id, }; -static int stack_map_btf_id; const struct bpf_map_ops stack_map_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc_check = queue_stack_map_alloc_check, .map_alloc = queue_stack_map_alloc, .map_free = queue_stack_map_free, @@ -300,6 +301,4 @@ const struct bpf_map_ops stack_map_ops = { .map_pop_elem = stack_map_pop_elem, .map_peek_elem = stack_map_peek_elem, .map_get_next_key = queue_stack_map_get_next_key, - .map_btf_name = "bpf_queue_stack", - .map_btf_id = &stack_map_btf_id, }; diff --git a/kernel/bpf/reuseport_array.c b/kernel/bpf/reuseport_array.c index a55cd542f2ce..50c083ba978c 100644 --- a/kernel/bpf/reuseport_array.c +++ b/kernel/bpf/reuseport_array.c @@ -20,14 +20,11 @@ static struct reuseport_array *reuseport_array(struct bpf_map *map) /* The caller must hold the reuseport_lock */ void bpf_sk_reuseport_detach(struct sock *sk) { - uintptr_t sk_user_data; + struct sock __rcu **socks; write_lock_bh(&sk->sk_callback_lock); - sk_user_data = (uintptr_t)sk->sk_user_data; - if (sk_user_data & SK_USER_DATA_BPF) { - struct sock __rcu **socks; - - socks = (void *)(sk_user_data & SK_USER_DATA_PTRMASK); + socks = sk->sk_user_data; + if (socks) { WRITE_ONCE(sk->sk_user_data, NULL); /* * Do not move this NULL assignment outside of @@ -99,6 +96,8 @@ static void reuseport_array_free(struct bpf_map *map) struct sock *sk; u32 i; + synchronize_rcu(); + /* * ops->map_*_elem() will not be able to access this * array now. Hence, this function only races with @@ -155,7 +154,7 @@ static struct bpf_map *reuseport_array_alloc(union bpf_attr *attr) struct bpf_map_memory mem; u64 array_size; - if (!bpf_capable()) + if (!capable(CAP_SYS_ADMIN)) return ERR_PTR(-EPERM); array_size = sizeof(*array); @@ -191,7 +190,7 @@ int bpf_fd_reuseport_array_lookup_elem(struct bpf_map *map, void *key, rcu_read_lock(); sk = reuseport_array_lookup_elem(map, key); if (sk) { - *(u64 *)value = __sock_gen_cookie(sk); + *(u64 *)value = sock_gen_cookie(sk); err = 0; } else { err = -ENOENT; @@ -253,7 +252,6 @@ int bpf_fd_reuseport_array_update_elem(struct bpf_map *map, void *key, struct sock *free_osk = NULL, *osk, *nsk; struct sock_reuseport *reuse; u32 index = *(u32 *)key; - uintptr_t sk_user_data; struct socket *socket; int err, fd; @@ -307,9 +305,12 @@ int bpf_fd_reuseport_array_update_elem(struct bpf_map *map, void *key, if (err) goto put_file_unlock; - sk_user_data = (uintptr_t)&array->ptrs[index] | SK_USER_DATA_NOCOPY | - SK_USER_DATA_BPF; - WRITE_ONCE(nsk->sk_user_data, (void *)sk_user_data); + /* Ensure reuse->reuseport_id is set */ + err = reuseport_get_id(reuse); + if (err < 0) + goto put_file_unlock; + + WRITE_ONCE(nsk->sk_user_data, &array->ptrs[index]); rcu_assign_pointer(array->ptrs[index], nsk); free_osk = osk; err = 0; @@ -349,15 +350,11 @@ static int reuseport_array_get_next_key(struct bpf_map *map, void *key, return 0; } -static int reuseport_array_map_btf_id; const struct bpf_map_ops reuseport_array_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc_check = reuseport_array_alloc_check, .map_alloc = reuseport_array_alloc, .map_free = reuseport_array_free, .map_lookup_elem = reuseport_array_lookup_elem, .map_get_next_key = reuseport_array_get_next_key, .map_delete_elem = reuseport_array_delete_elem, - .map_btf_name = "reuseport_array", - .map_btf_id = &reuseport_array_map_btf_id, }; diff --git a/kernel/bpf/ringbuf.c b/kernel/bpf/ringbuf.c deleted file mode 100644 index eac0026e2fa6..000000000000 --- a/kernel/bpf/ringbuf.c +++ /dev/null @@ -1,516 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define RINGBUF_CREATE_FLAG_MASK (BPF_F_NUMA_NODE) - -/* non-mmap()'able part of bpf_ringbuf (everything up to consumer page) */ -#define RINGBUF_PGOFF \ - (offsetof(struct bpf_ringbuf, consumer_pos) >> PAGE_SHIFT) -/* consumer page and producer page */ -#define RINGBUF_POS_PAGES 2 - -#define RINGBUF_MAX_RECORD_SZ (UINT_MAX/4) - -/* Maximum size of ring buffer area is limited by 32-bit page offset within - * record header, counted in pages. Reserve 8 bits for extensibility, and take - * into account few extra pages for consumer/producer pages and - * non-mmap()'able parts. This gives 64GB limit, which seems plenty for single - * ring buffer. - */ -#define RINGBUF_MAX_DATA_SZ \ - (((1ULL << 24) - RINGBUF_POS_PAGES - RINGBUF_PGOFF) * PAGE_SIZE) - -struct bpf_ringbuf { - wait_queue_head_t waitq; - struct irq_work work; - u64 mask; - struct page **pages; - int nr_pages; - spinlock_t spinlock ____cacheline_aligned_in_smp; - /* Consumer and producer counters are put into separate pages to allow - * mapping consumer page as r/w, but restrict producer page to r/o. - * This protects producer position from being modified by user-space - * application and ruining in-kernel position tracking. - * Note that the pending counter is placed in the same - * page as the producer, so that it shares the same cache line. - */ - unsigned long consumer_pos __aligned(PAGE_SIZE); - unsigned long producer_pos __aligned(PAGE_SIZE); - unsigned long pending_pos; - char data[] __aligned(PAGE_SIZE); -}; - -struct bpf_ringbuf_map { - struct bpf_map map; - struct bpf_map_memory memory; - struct bpf_ringbuf *rb; -}; - -/* 8-byte ring buffer record header structure */ -struct bpf_ringbuf_hdr { - u32 len; - u32 pg_off; -}; - -static struct bpf_ringbuf *bpf_ringbuf_area_alloc(size_t data_sz, int numa_node) -{ - const gfp_t flags = GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN | - __GFP_ZERO; - int nr_meta_pages = RINGBUF_PGOFF + RINGBUF_POS_PAGES; - int nr_data_pages = data_sz >> PAGE_SHIFT; - int nr_pages = nr_meta_pages + nr_data_pages; - struct page **pages, *page; - struct bpf_ringbuf *rb; - size_t array_size; - int i; - - /* Each data page is mapped twice to allow "virtual" - * continuous read of samples wrapping around the end of ring - * buffer area: - * ------------------------------------------------------ - * | meta pages | real data pages | same data pages | - * ------------------------------------------------------ - * | | 1 2 3 4 5 6 7 8 9 | 1 2 3 4 5 6 7 8 9 | - * ------------------------------------------------------ - * | | TA DA | TA DA | - * ------------------------------------------------------ - * ^^^^^^^ - * | - * Here, no need to worry about special handling of wrapped-around - * data due to double-mapped data pages. This works both in kernel and - * when mmap()'ed in user-space, simplifying both kernel and - * user-space implementations significantly. - */ - array_size = (nr_meta_pages + 2 * nr_data_pages) * sizeof(*pages); - if (array_size > PAGE_SIZE) - pages = vmalloc_node(array_size, numa_node); - else - pages = kmalloc_node(array_size, flags, numa_node); - if (!pages) - return NULL; - - for (i = 0; i < nr_pages; i++) { - page = alloc_pages_node(numa_node, flags, 0); - if (!page) { - nr_pages = i; - goto err_free_pages; - } - pages[i] = page; - if (i >= nr_meta_pages) - pages[nr_data_pages + i] = page; - } - - rb = vmap(pages, nr_meta_pages + 2 * nr_data_pages, - VM_MAP | VM_USERMAP, PAGE_KERNEL); - if (rb) { - kmemleak_not_leak(pages); - rb->pages = pages; - rb->nr_pages = nr_pages; - return rb; - } - -err_free_pages: - for (i = 0; i < nr_pages; i++) - __free_page(pages[i]); - kvfree(pages); - return NULL; -} - -static void bpf_ringbuf_notify(struct irq_work *work) -{ - struct bpf_ringbuf *rb = container_of(work, struct bpf_ringbuf, work); - - wake_up_all(&rb->waitq); -} - -static struct bpf_ringbuf *bpf_ringbuf_alloc(size_t data_sz, int numa_node) -{ - struct bpf_ringbuf *rb; - - rb = bpf_ringbuf_area_alloc(data_sz, numa_node); - if (!rb) - return ERR_PTR(-ENOMEM); - - spin_lock_init(&rb->spinlock); - init_waitqueue_head(&rb->waitq); - init_irq_work(&rb->work, bpf_ringbuf_notify); - - rb->mask = data_sz - 1; - rb->consumer_pos = 0; - rb->producer_pos = 0; - rb->pending_pos = 0; - - return rb; -} - -static struct bpf_map *ringbuf_map_alloc(union bpf_attr *attr) -{ - struct bpf_ringbuf_map *rb_map; - u64 cost; - int err; - - if (attr->map_flags & ~RINGBUF_CREATE_FLAG_MASK) - return ERR_PTR(-EINVAL); - - if (attr->key_size || attr->value_size || - !is_power_of_2(attr->max_entries) || - !PAGE_ALIGNED(attr->max_entries)) - return ERR_PTR(-EINVAL); - -#ifdef CONFIG_64BIT - /* on 32-bit arch, it's impossible to overflow record's hdr->pgoff */ - if (attr->max_entries > RINGBUF_MAX_DATA_SZ) - return ERR_PTR(-E2BIG); -#endif - - rb_map = kzalloc(sizeof(*rb_map), GFP_USER); - if (!rb_map) - return ERR_PTR(-ENOMEM); - - bpf_map_init_from_attr(&rb_map->map, attr); - - cost = sizeof(struct bpf_ringbuf_map) + - sizeof(struct bpf_ringbuf) + - attr->max_entries; - err = bpf_map_charge_init(&rb_map->map.memory, cost); - if (err) - goto err_free_map; - - rb_map->rb = bpf_ringbuf_alloc(attr->max_entries, rb_map->map.numa_node); - if (IS_ERR(rb_map->rb)) { - err = PTR_ERR(rb_map->rb); - goto err_uncharge; - } - - return &rb_map->map; - -err_uncharge: - bpf_map_charge_finish(&rb_map->map.memory); -err_free_map: - kfree(rb_map); - return ERR_PTR(err); -} - -static void bpf_ringbuf_free(struct bpf_ringbuf *rb) -{ - /* copy pages pointer and nr_pages to local variable, as we are going - * to unmap rb itself with vunmap() below - */ - struct page **pages = rb->pages; - int i, nr_pages = rb->nr_pages; - - vunmap(rb); - for (i = 0; i < nr_pages; i++) - __free_page(pages[i]); - kvfree(pages); -} - -static void ringbuf_map_free(struct bpf_map *map) -{ - struct bpf_ringbuf_map *rb_map; - - rb_map = container_of(map, struct bpf_ringbuf_map, map); - bpf_ringbuf_free(rb_map->rb); - kfree(rb_map); -} - -static void *ringbuf_map_lookup_elem(struct bpf_map *map, void *key) -{ - return ERR_PTR(-ENOTSUPP); -} - -static int ringbuf_map_update_elem(struct bpf_map *map, void *key, void *value, - u64 flags) -{ - return -ENOTSUPP; -} - -static int ringbuf_map_delete_elem(struct bpf_map *map, void *key) -{ - return -ENOTSUPP; -} - -static int ringbuf_map_get_next_key(struct bpf_map *map, void *key, - void *next_key) -{ - return -ENOTSUPP; -} - -static int ringbuf_map_mmap(struct bpf_map *map, struct vm_area_struct *vma) -{ - struct bpf_ringbuf_map *rb_map; - - rb_map = container_of(map, struct bpf_ringbuf_map, map); - - if (vma->vm_flags & VM_WRITE) { - /* allow writable mapping for the consumer_pos only */ - if (vma->vm_pgoff != 0 || vma->vm_end - vma->vm_start != PAGE_SIZE) - return -EPERM; - } else { - vma->vm_flags &= ~VM_MAYWRITE; - } - /* remap_vmalloc_range() checks size and offset constraints */ - return remap_vmalloc_range(vma, rb_map->rb, - vma->vm_pgoff + RINGBUF_PGOFF); -} - -static unsigned long ringbuf_avail_data_sz(struct bpf_ringbuf *rb) -{ - unsigned long cons_pos, prod_pos; - - cons_pos = smp_load_acquire(&rb->consumer_pos); - prod_pos = smp_load_acquire(&rb->producer_pos); - return prod_pos - cons_pos; -} - -static __poll_t ringbuf_map_poll(struct bpf_map *map, struct file *filp, - struct poll_table_struct *pts) -{ - struct bpf_ringbuf_map *rb_map; - - rb_map = container_of(map, struct bpf_ringbuf_map, map); - poll_wait(filp, &rb_map->rb->waitq, pts); - - if (ringbuf_avail_data_sz(rb_map->rb)) - return EPOLLIN | EPOLLRDNORM; - return 0; -} - -static int ringbuf_map_btf_id; -const struct bpf_map_ops ringbuf_map_ops = { - .map_meta_equal = bpf_map_meta_equal, - .map_alloc = ringbuf_map_alloc, - .map_free = ringbuf_map_free, - .map_mmap = ringbuf_map_mmap, - .map_poll = ringbuf_map_poll, - .map_lookup_elem = ringbuf_map_lookup_elem, - .map_update_elem = ringbuf_map_update_elem, - .map_delete_elem = ringbuf_map_delete_elem, - .map_get_next_key = ringbuf_map_get_next_key, - .map_btf_name = "bpf_ringbuf_map", - .map_btf_id = &ringbuf_map_btf_id, -}; - -/* Given pointer to ring buffer record metadata and struct bpf_ringbuf itself, - * calculate offset from record metadata to ring buffer in pages, rounded - * down. This page offset is stored as part of record metadata and allows to - * restore struct bpf_ringbuf * from record pointer. This page offset is - * stored at offset 4 of record metadata header. - */ -static size_t bpf_ringbuf_rec_pg_off(struct bpf_ringbuf *rb, - struct bpf_ringbuf_hdr *hdr) -{ - return ((void *)hdr - (void *)rb) >> PAGE_SHIFT; -} - -/* Given pointer to ring buffer record header, restore pointer to struct - * bpf_ringbuf itself by using page offset stored at offset 4 - */ -static struct bpf_ringbuf * -bpf_ringbuf_restore_from_rec(struct bpf_ringbuf_hdr *hdr) -{ - unsigned long addr = (unsigned long)(void *)hdr; - unsigned long off = (unsigned long)hdr->pg_off << PAGE_SHIFT; - - return (void*)((addr & PAGE_MASK) - off); -} - -static void *__bpf_ringbuf_reserve(struct bpf_ringbuf *rb, u64 size) -{ - unsigned long cons_pos, prod_pos, new_prod_pos, pend_pos, flags; - struct bpf_ringbuf_hdr *hdr; - u32 len, pg_off, tmp_size, hdr_len; - - if (unlikely(size > RINGBUF_MAX_RECORD_SZ)) - return NULL; - - len = round_up(size + BPF_RINGBUF_HDR_SZ, 8); - if (len > rb->mask + 1) - return NULL; - - cons_pos = smp_load_acquire(&rb->consumer_pos); - - if (in_nmi()) { - if (!spin_trylock_irqsave(&rb->spinlock, flags)) - return NULL; - } else { - spin_lock_irqsave(&rb->spinlock, flags); - } - - pend_pos = rb->pending_pos; - prod_pos = rb->producer_pos; - new_prod_pos = prod_pos + len; - - while (pend_pos < prod_pos) { - hdr = (void *)rb->data + (pend_pos & rb->mask); - hdr_len = READ_ONCE(hdr->len); - if (hdr_len & BPF_RINGBUF_BUSY_BIT) - break; - tmp_size = hdr_len & ~BPF_RINGBUF_DISCARD_BIT; - tmp_size = round_up(tmp_size + BPF_RINGBUF_HDR_SZ, 8); - pend_pos += tmp_size; - } - rb->pending_pos = pend_pos; - - /* check for out of ringbuf space: - * - by ensuring producer position doesn't advance more than - * (ringbuf_size - 1) ahead - * - by ensuring oldest not yet committed record until newest - * record does not span more than (ringbuf_size - 1) - */ - if (new_prod_pos - cons_pos > rb->mask || - new_prod_pos - pend_pos > rb->mask) { - spin_unlock_irqrestore(&rb->spinlock, flags); - return NULL; - } - - hdr = (void *)rb->data + (prod_pos & rb->mask); - pg_off = bpf_ringbuf_rec_pg_off(rb, hdr); - hdr->len = size | BPF_RINGBUF_BUSY_BIT; - hdr->pg_off = pg_off; - - /* pairs with consumer's smp_load_acquire() */ - smp_store_release(&rb->producer_pos, new_prod_pos); - - spin_unlock_irqrestore(&rb->spinlock, flags); - - return (void *)hdr + BPF_RINGBUF_HDR_SZ; -} - -BPF_CALL_3(bpf_ringbuf_reserve, struct bpf_map *, map, u64, size, u64, flags) -{ - struct bpf_ringbuf_map *rb_map; - - if (unlikely(flags)) - return 0; - - rb_map = container_of(map, struct bpf_ringbuf_map, map); - return (unsigned long)__bpf_ringbuf_reserve(rb_map->rb, size); -} - -const struct bpf_func_proto bpf_ringbuf_reserve_proto = { - .func = bpf_ringbuf_reserve, - .ret_type = RET_PTR_TO_ALLOC_MEM_OR_NULL, - .arg1_type = ARG_CONST_MAP_PTR, - .arg2_type = ARG_CONST_ALLOC_SIZE_OR_ZERO, - .arg3_type = ARG_ANYTHING, -}; - -static void bpf_ringbuf_commit(void *sample, u64 flags, bool discard) -{ - unsigned long rec_pos, cons_pos; - struct bpf_ringbuf_hdr *hdr; - struct bpf_ringbuf *rb; - u32 new_len; - - hdr = sample - BPF_RINGBUF_HDR_SZ; - rb = bpf_ringbuf_restore_from_rec(hdr); - new_len = hdr->len ^ BPF_RINGBUF_BUSY_BIT; - if (discard) - new_len |= BPF_RINGBUF_DISCARD_BIT; - - /* update record header with correct final size prefix */ - xchg(&hdr->len, new_len); - - /* if consumer caught up and is waiting for our record, notify about - * new data availability - */ - rec_pos = (void *)hdr - (void *)rb->data; - cons_pos = smp_load_acquire(&rb->consumer_pos) & rb->mask; - - if (flags & BPF_RB_FORCE_WAKEUP) - irq_work_queue(&rb->work); - else if (cons_pos == rec_pos && !(flags & BPF_RB_NO_WAKEUP)) - irq_work_queue(&rb->work); -} - -BPF_CALL_2(bpf_ringbuf_submit, void *, sample, u64, flags) -{ - bpf_ringbuf_commit(sample, flags, false /* discard */); - return 0; -} - -const struct bpf_func_proto bpf_ringbuf_submit_proto = { - .func = bpf_ringbuf_submit, - .ret_type = RET_VOID, - .arg1_type = ARG_PTR_TO_ALLOC_MEM, - .arg2_type = ARG_ANYTHING, -}; - -BPF_CALL_2(bpf_ringbuf_discard, void *, sample, u64, flags) -{ - bpf_ringbuf_commit(sample, flags, true /* discard */); - return 0; -} - -const struct bpf_func_proto bpf_ringbuf_discard_proto = { - .func = bpf_ringbuf_discard, - .ret_type = RET_VOID, - .arg1_type = ARG_PTR_TO_ALLOC_MEM, - .arg2_type = ARG_ANYTHING, -}; - -BPF_CALL_4(bpf_ringbuf_output, struct bpf_map *, map, void *, data, u64, size, - u64, flags) -{ - struct bpf_ringbuf_map *rb_map; - void *rec; - - if (unlikely(flags & ~(BPF_RB_NO_WAKEUP | BPF_RB_FORCE_WAKEUP))) - return -EINVAL; - - rb_map = container_of(map, struct bpf_ringbuf_map, map); - rec = __bpf_ringbuf_reserve(rb_map->rb, size); - if (!rec) - return -EAGAIN; - - memcpy(rec, data, size); - bpf_ringbuf_commit(rec, flags, false /* discard */); - return 0; -} - -const struct bpf_func_proto bpf_ringbuf_output_proto = { - .func = bpf_ringbuf_output, - .ret_type = RET_INTEGER, - .arg1_type = ARG_CONST_MAP_PTR, - .arg2_type = ARG_PTR_TO_MEM, - .arg3_type = ARG_CONST_SIZE_OR_ZERO, - .arg4_type = ARG_ANYTHING, -}; - -BPF_CALL_2(bpf_ringbuf_query, struct bpf_map *, map, u64, flags) -{ - struct bpf_ringbuf *rb; - - rb = container_of(map, struct bpf_ringbuf_map, map)->rb; - - switch (flags) { - case BPF_RB_AVAIL_DATA: - return ringbuf_avail_data_sz(rb); - case BPF_RB_RING_SIZE: - return rb->mask + 1; - case BPF_RB_CONS_POS: - return smp_load_acquire(&rb->consumer_pos); - case BPF_RB_PROD_POS: - return smp_load_acquire(&rb->producer_pos); - default: - return 0; - } -} - -const struct bpf_func_proto bpf_ringbuf_query_proto = { - .func = bpf_ringbuf_query, - .ret_type = RET_INTEGER, - .arg1_type = ARG_CONST_MAP_PTR, - .arg2_type = ARG_ANYTHING, -}; diff --git a/kernel/bpf/stackmap.c b/kernel/bpf/stackmap.c index 5be1f521317a..bd8516d96745 100644 --- a/kernel/bpf/stackmap.c +++ b/kernel/bpf/stackmap.c @@ -4,13 +4,11 @@ #include #include #include -#include #include #include #include #include #include -#include #include "percpu_freelist.h" #define STACK_CREATE_FLAG_MASK \ @@ -42,9 +40,6 @@ static void do_up_read(struct irq_work *entry) { struct stack_map_irq_work *work; - if (WARN_ON_ONCE(IS_ENABLED(CONFIG_PREEMPT_RT))) - return; - work = container_of(entry, struct stack_map_irq_work, irq_work); up_read_non_owner(work->sem); work->sem = NULL; @@ -96,7 +91,7 @@ static struct bpf_map *stack_map_alloc(union bpf_attr *attr) u64 cost, n_buckets; int err; - if (!bpf_capable()) + if (!capable(CAP_SYS_ADMIN)) return ERR_PTR(-EPERM); if (attr->map_flags & ~STACK_CREATE_FLAG_MASK) @@ -123,8 +118,6 @@ static struct bpf_map *stack_map_alloc(union bpf_attr *attr) return ERR_PTR(-E2BIG); n_buckets = roundup_pow_of_two(attr->max_entries); - if (!n_buckets) - return ERR_PTR(-E2BIG); cost = n_buckets * sizeof(struct stack_map_bucket *) + sizeof(*smap); err = bpf_map_charge_init(&mem, cost + attr->max_entries * @@ -222,13 +215,11 @@ static int stack_map_get_build_id_32(void *page_addr, phdr = (Elf32_Phdr *)(page_addr + sizeof(Elf32_Ehdr)); - for (i = 0; i < ehdr->e_phnum; ++i) { - if (phdr[i].p_type == PT_NOTE && - !stack_map_parse_build_id(page_addr, build_id, - page_addr + phdr[i].p_offset, - phdr[i].p_filesz)) - return 0; - } + for (i = 0; i < ehdr->e_phnum; ++i) + if (phdr[i].p_type == PT_NOTE) + return stack_map_parse_build_id(page_addr, build_id, + page_addr + phdr[i].p_offset, + phdr[i].p_filesz); return -EINVAL; } @@ -247,13 +238,11 @@ static int stack_map_get_build_id_64(void *page_addr, phdr = (Elf64_Phdr *)(page_addr + sizeof(Elf64_Ehdr)); - for (i = 0; i < ehdr->e_phnum; ++i) { - if (phdr[i].p_type == PT_NOTE && - !stack_map_parse_build_id(page_addr, build_id, - page_addr + phdr[i].p_offset, - phdr[i].p_filesz)) - return 0; - } + for (i = 0; i < ehdr->e_phnum; ++i) + if (phdr[i].p_type == PT_NOTE) + return stack_map_parse_build_id(page_addr, build_id, + page_addr + phdr[i].p_offset, + phdr[i].p_filesz); return -EINVAL; } @@ -305,19 +294,10 @@ static void stack_map_get_build_id_offset(struct bpf_stack_build_id *id_offs, struct stack_map_irq_work *work = NULL; if (irqs_disabled()) { - if (!IS_ENABLED(CONFIG_PREEMPT_RT)) { - work = this_cpu_ptr(&up_read_work); - if (atomic_read(&work->irq_work.flags) & IRQ_WORK_BUSY) { - /* cannot queue more up_read, fallback */ - irq_work_busy = true; - } - } else { - /* - * PREEMPT_RT does not allow to trylock mmap sem in - * interrupt disabled context. Force the fallback code. - */ + work = this_cpu_ptr(&up_read_work); + if (work->irq_work.flags & IRQ_WORK_BUSY) + /* cannot queue more up_read, fallback */ irq_work_busy = true; - } } /* @@ -369,61 +349,45 @@ static void stack_map_get_build_id_offset(struct bpf_stack_build_id *id_offs, } } -static struct perf_callchain_entry * -get_callchain_entry_for_task(struct task_struct *task, u32 max_depth) -{ -#ifdef CONFIG_STACKTRACE - struct perf_callchain_entry *entry; - int rctx; - - entry = get_callchain_entry(&rctx); - - if (!entry) - return NULL; - - entry->nr = stack_trace_save_tsk(task, (unsigned long *)entry->ip, - max_depth, 0); - - /* stack_trace_save_tsk() works on unsigned long array, while - * perf_callchain_entry uses u64 array. For 32-bit systems, it is - * necessary to fix this mismatch. - */ - if (__BITS_PER_LONG != 64) { - unsigned long *from = (unsigned long *) entry->ip; - u64 *to = entry->ip; - int i; - - /* copy data from the end to avoid using extra buffer */ - for (i = entry->nr - 1; i >= 0; i--) - to[i] = (u64)(from[i]); - } - - put_callchain_entry(rctx); - - return entry; -#else /* CONFIG_STACKTRACE */ - return NULL; -#endif -} - -static long __bpf_get_stackid(struct bpf_map *map, - struct perf_callchain_entry *trace, u64 flags) +BPF_CALL_3(bpf_get_stackid, struct pt_regs *, regs, struct bpf_map *, map, + u64, flags) { struct bpf_stack_map *smap = container_of(map, struct bpf_stack_map, map); + struct perf_callchain_entry *trace; struct stack_map_bucket *bucket, *new_bucket, *old_bucket; + u32 max_depth = map->value_size / stack_map_data_size(map); + /* stack_map_alloc() checks that max_depth <= sysctl_perf_event_max_stack */ + u32 init_nr = sysctl_perf_event_max_stack - max_depth; u32 skip = flags & BPF_F_SKIP_FIELD_MASK; u32 hash, id, trace_nr, trace_len; bool user = flags & BPF_F_USER_STACK; + bool kernel = !user; u64 *ips; bool hash_matches; - if (trace->nr <= skip) + if (unlikely(flags & ~(BPF_F_SKIP_FIELD_MASK | BPF_F_USER_STACK | + BPF_F_FAST_STACK_CMP | BPF_F_REUSE_STACKID))) + return -EINVAL; + + trace = get_perf_callchain(regs, init_nr, kernel, user, + sysctl_perf_event_max_stack, false, false); + + if (unlikely(!trace)) + /* couldn't fetch the stack trace */ + return -EFAULT; + + /* get_perf_callchain() guarantees that trace->nr >= init_nr + * and trace-nr <= sysctl_perf_event_max_stack, so trace_nr <= max_depth + */ + trace_nr = trace->nr - init_nr; + + if (trace_nr <= skip) /* skipping more than usable stack trace */ return -EFAULT; - trace_nr = trace->nr - skip; + trace_nr -= skip; trace_len = trace_nr * sizeof(u64); - ips = trace->ip + skip; + ips = trace->ip + skip + init_nr; hash = jhash2((u32 *)ips, trace_len / sizeof(u32), 0); id = hash & (smap->n_buckets - 1); bucket = READ_ONCE(smap->buckets[id]); @@ -476,33 +440,6 @@ static long __bpf_get_stackid(struct bpf_map *map, return id; } -BPF_CALL_3(bpf_get_stackid, struct pt_regs *, regs, struct bpf_map *, map, - u64, flags) -{ - u32 max_depth = map->value_size / stack_map_data_size(map); - u32 skip = flags & BPF_F_SKIP_FIELD_MASK; - bool user = flags & BPF_F_USER_STACK; - struct perf_callchain_entry *trace; - bool kernel = !user; - - if (unlikely(flags & ~(BPF_F_SKIP_FIELD_MASK | BPF_F_USER_STACK | - BPF_F_FAST_STACK_CMP | BPF_F_REUSE_STACKID))) - return -EINVAL; - - max_depth += skip; - if (max_depth > sysctl_perf_event_max_stack) - max_depth = sysctl_perf_event_max_stack; - - trace = get_perf_callchain(regs, 0, kernel, user, max_depth, - false, false); - - if (unlikely(!trace)) - /* couldn't fetch the stack trace */ - return -EFAULT; - - return __bpf_get_stackid(map, trace, flags); -} - const struct bpf_func_proto bpf_get_stackid_proto = { .func = bpf_get_stackid, .gpl_only = true, @@ -512,82 +449,11 @@ const struct bpf_func_proto bpf_get_stackid_proto = { .arg3_type = ARG_ANYTHING, }; -static __u64 count_kernel_ip(struct perf_callchain_entry *trace) +BPF_CALL_4(bpf_get_stack, struct pt_regs *, regs, void *, buf, u32, size, + u64, flags) { - __u64 nr_kernel = 0; - - while (nr_kernel < trace->nr) { - if (trace->ip[nr_kernel] == PERF_CONTEXT_USER) - break; - nr_kernel++; - } - return nr_kernel; -} - -BPF_CALL_3(bpf_get_stackid_pe, struct bpf_perf_event_data_kern *, ctx, - struct bpf_map *, map, u64, flags) -{ - struct perf_event *event = ctx->event; - struct perf_callchain_entry *trace; - bool kernel, user; - __u64 nr_kernel; - int ret; - - /* perf_sample_data doesn't have callchain, use bpf_get_stackid */ - if (!(event->attr.sample_type & __PERF_SAMPLE_CALLCHAIN_EARLY)) - return bpf_get_stackid((unsigned long)(ctx->regs), - (unsigned long) map, flags, 0, 0); - - if (unlikely(flags & ~(BPF_F_SKIP_FIELD_MASK | BPF_F_USER_STACK | - BPF_F_FAST_STACK_CMP | BPF_F_REUSE_STACKID))) - return -EINVAL; - - user = flags & BPF_F_USER_STACK; - kernel = !user; - - trace = ctx->data->callchain; - if (unlikely(!trace)) - return -EFAULT; - - nr_kernel = count_kernel_ip(trace); - - if (kernel) { - __u64 nr = trace->nr; - - trace->nr = nr_kernel; - ret = __bpf_get_stackid(map, trace, flags); - - /* restore nr */ - trace->nr = nr; - } else { /* user */ - u64 skip = flags & BPF_F_SKIP_FIELD_MASK; - - skip += nr_kernel; - if (skip > BPF_F_SKIP_FIELD_MASK) - return -EFAULT; - - flags = (flags & ~BPF_F_SKIP_FIELD_MASK) | skip; - ret = __bpf_get_stackid(map, trace, flags); - } - return ret; -} - -const struct bpf_func_proto bpf_get_stackid_proto_pe = { - .func = bpf_get_stackid_pe, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX, - .arg2_type = ARG_CONST_MAP_PTR, - .arg3_type = ARG_ANYTHING, -}; - -static long __bpf_get_stack(struct pt_regs *regs, struct task_struct *task, - struct perf_callchain_entry *trace_in, - void *buf, u32 size, u64 flags) -{ - u32 trace_nr, copy_len, elem_size, num_elem, max_depth; + u32 init_nr, trace_nr, copy_len, elem_size, num_elem; bool user_build_id = flags & BPF_F_USER_BUILD_ID; - bool crosstask = task && task != current; u32 skip = flags & BPF_F_SKIP_FIELD_MASK; bool user = flags & BPF_F_USER_STACK; struct perf_callchain_entry *trace; @@ -606,41 +472,24 @@ static long __bpf_get_stack(struct pt_regs *regs, struct task_struct *task, if (unlikely(size % elem_size)) goto clear; - /* cannot get valid user stack for task without user_mode regs */ - if (task && user && !user_mode(regs)) - goto err_fault; - - /* get_perf_callchain does not support crosstask user stack walking - * but returns an empty stack instead of NULL. - */ - if (crosstask && user) { - err = -EOPNOTSUPP; - goto clear; - } - num_elem = size / elem_size; - max_depth = num_elem + skip; - if (sysctl_perf_event_max_stack < max_depth) - max_depth = sysctl_perf_event_max_stack; - - if (trace_in) - trace = trace_in; - else if (kernel && task) - trace = get_callchain_entry_for_task(task, max_depth); + if (sysctl_perf_event_max_stack < num_elem) + init_nr = 0; else - trace = get_perf_callchain(regs, 0, kernel, user, max_depth, - crosstask, false); + init_nr = sysctl_perf_event_max_stack - num_elem; + trace = get_perf_callchain(regs, init_nr, kernel, user, + sysctl_perf_event_max_stack, false, false); if (unlikely(!trace)) goto err_fault; - if (trace->nr < skip) + trace_nr = trace->nr - init_nr; + if (trace_nr < skip) goto err_fault; - trace_nr = trace->nr - skip; + trace_nr -= skip; trace_nr = (trace_nr <= num_elem) ? trace_nr : num_elem; copy_len = trace_nr * elem_size; - - ips = trace->ip + skip; + ips = trace->ip + skip + init_nr; if (user && user_build_id) stack_map_get_build_id_offset(buf, ips, trace_nr, user); else @@ -657,12 +506,6 @@ clear: return err; } -BPF_CALL_4(bpf_get_stack, struct pt_regs *, regs, void *, buf, u32, size, - u64, flags) -{ - return __bpf_get_stack(regs, NULL, NULL, buf, size, flags); -} - const struct bpf_func_proto bpf_get_stack_proto = { .func = bpf_get_stack, .gpl_only = true, @@ -673,99 +516,6 @@ const struct bpf_func_proto bpf_get_stack_proto = { .arg4_type = ARG_ANYTHING, }; -BPF_CALL_4(bpf_get_task_stack, struct task_struct *, task, void *, buf, - u32, size, u64, flags) -{ - struct pt_regs *regs; - long res = -EINVAL; - - if (!try_get_task_stack(task)) - return -EFAULT; - - regs = task_pt_regs(task); - if (regs) - res = __bpf_get_stack(regs, task, NULL, buf, size, flags); - put_task_stack(task); - - return res; -} - -BTF_ID_LIST_SINGLE(bpf_get_task_stack_btf_ids, struct, task_struct) - -const struct bpf_func_proto bpf_get_task_stack_proto = { - .func = bpf_get_task_stack, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_BTF_ID, - .arg1_btf_id = &bpf_get_task_stack_btf_ids[0], - .arg2_type = ARG_PTR_TO_UNINIT_MEM, - .arg3_type = ARG_CONST_SIZE_OR_ZERO, - .arg4_type = ARG_ANYTHING, -}; - -BPF_CALL_4(bpf_get_stack_pe, struct bpf_perf_event_data_kern *, ctx, - void *, buf, u32, size, u64, flags) -{ - struct pt_regs *regs = (struct pt_regs *)(ctx->regs); - struct perf_event *event = ctx->event; - struct perf_callchain_entry *trace; - bool kernel, user; - int err = -EINVAL; - __u64 nr_kernel; - - if (!(event->attr.sample_type & __PERF_SAMPLE_CALLCHAIN_EARLY)) - return __bpf_get_stack(regs, NULL, NULL, buf, size, flags); - - if (unlikely(flags & ~(BPF_F_SKIP_FIELD_MASK | BPF_F_USER_STACK | - BPF_F_USER_BUILD_ID))) - goto clear; - - user = flags & BPF_F_USER_STACK; - kernel = !user; - - err = -EFAULT; - trace = ctx->data->callchain; - if (unlikely(!trace)) - goto clear; - - nr_kernel = count_kernel_ip(trace); - - if (kernel) { - __u64 nr = trace->nr; - - trace->nr = nr_kernel; - err = __bpf_get_stack(regs, NULL, trace, buf, size, flags); - - /* restore nr */ - trace->nr = nr; - } else { /* user */ - u64 skip = flags & BPF_F_SKIP_FIELD_MASK; - - skip += nr_kernel; - if (skip > BPF_F_SKIP_FIELD_MASK) - goto clear; - - flags = (flags & ~BPF_F_SKIP_FIELD_MASK) | skip; - err = __bpf_get_stack(regs, NULL, trace, buf, size, flags); - } - return err; - -clear: - memset(buf, 0, size); - return err; - -} - -const struct bpf_func_proto bpf_get_stack_proto_pe = { - .func = bpf_get_stack_pe, - .gpl_only = true, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX, - .arg2_type = ARG_PTR_TO_UNINIT_MEM, - .arg3_type = ARG_CONST_SIZE_OR_ZERO, - .arg4_type = ARG_ANYTHING, -}; - /* Called from eBPF program */ static void *stack_map_lookup_elem(struct bpf_map *map, void *key) { @@ -855,15 +605,16 @@ static void stack_map_free(struct bpf_map *map) { struct bpf_stack_map *smap = container_of(map, struct bpf_stack_map, map); + /* wait for bpf programs to complete before freeing stack map */ + synchronize_rcu(); + bpf_map_area_free(smap->elems); pcpu_freelist_destroy(&smap->freelist); bpf_map_area_free(smap); put_callchain_buffers(); } -static int stack_trace_map_btf_id; const struct bpf_map_ops stack_trace_map_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc = stack_map_alloc, .map_free = stack_map_free, .map_get_next_key = stack_map_get_next_key, @@ -871,8 +622,6 @@ const struct bpf_map_ops stack_trace_map_ops = { .map_update_elem = stack_map_update_elem, .map_delete_elem = stack_map_delete_elem, .map_check_btf = map_check_no_btf, - .map_btf_name = "bpf_stack_map", - .map_btf_id = &stack_trace_map_btf_id, }; static int __init stack_map_init(void) diff --git a/kernel/bpf/syscall.c b/kernel/bpf/syscall.c index bf96ac276536..de788761b708 100644 --- a/kernel/bpf/syscall.c +++ b/kernel/bpf/syscall.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -24,20 +23,13 @@ #include #include #include -#include -#include -#include -#include -#include -#include -#define IS_FD_ARRAY(map) ((map)->map_type == BPF_MAP_TYPE_PERF_EVENT_ARRAY || \ - (map)->map_type == BPF_MAP_TYPE_CGROUP_ARRAY || \ - (map)->map_type == BPF_MAP_TYPE_ARRAY_OF_MAPS) -#define IS_FD_PROG_ARRAY(map) ((map)->map_type == BPF_MAP_TYPE_PROG_ARRAY) +#define IS_FD_ARRAY(map) ((map)->map_type == BPF_MAP_TYPE_PROG_ARRAY || \ + (map)->map_type == BPF_MAP_TYPE_PERF_EVENT_ARRAY || \ + (map)->map_type == BPF_MAP_TYPE_CGROUP_ARRAY || \ + (map)->map_type == BPF_MAP_TYPE_ARRAY_OF_MAPS) #define IS_FD_HASH(map) ((map)->map_type == BPF_MAP_TYPE_HASH_OF_MAPS) -#define IS_FD_MAP(map) (IS_FD_ARRAY(map) || IS_FD_PROG_ARRAY(map) || \ - IS_FD_HASH(map)) +#define IS_FD_MAP(map) (IS_FD_ARRAY(map) || IS_FD_HASH(map)) #define BPF_OBJ_FLAG_MASK (BPF_F_RDONLY | BPF_F_WRONLY) @@ -46,21 +38,17 @@ static DEFINE_IDR(prog_idr); static DEFINE_SPINLOCK(prog_idr_lock); static DEFINE_IDR(map_idr); static DEFINE_SPINLOCK(map_idr_lock); -static DEFINE_IDR(link_idr); -static DEFINE_SPINLOCK(link_idr_lock); int sysctl_unprivileged_bpf_disabled __read_mostly = IS_BUILTIN(CONFIG_BPF_UNPRIV_DEFAULT_OFF) ? 2 : 0; static const struct bpf_map_ops * const bpf_map_types[] = { -#define BPF_PROG_TYPE(_id, _name, prog_ctx_type, kern_ctx_type) +#define BPF_PROG_TYPE(_id, _ops) #define BPF_MAP_TYPE(_id, _ops) \ [_id] = &_ops, -#define BPF_LINK_TYPE(_id, _name) #include #undef BPF_PROG_TYPE #undef BPF_MAP_TYPE -#undef BPF_LINK_TYPE }; /* @@ -76,23 +64,35 @@ int bpf_check_uarg_tail_zero(void __user *uaddr, size_t expected_size, size_t actual_size) { - unsigned char __user *addr = uaddr + expected_size; - int res; + unsigned char __user *addr; + unsigned char __user *end; + unsigned char val; + int err; if (unlikely(actual_size > PAGE_SIZE)) /* silly large */ return -E2BIG; + if (unlikely(!access_ok(uaddr, actual_size))) + return -EFAULT; + if (actual_size <= expected_size) return 0; - res = check_zeroed_user(addr, actual_size - expected_size); - if (res < 0) - return res; - return res ? 0 : -E2BIG; + addr = uaddr + expected_size; + end = uaddr + actual_size; + + for (; addr < end; addr++) { + err = get_user(val, addr); + if (err) + return err; + if (val) + return -E2BIG; + } + + return 0; } const struct bpf_map_ops bpf_map_offload_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc = bpf_map_offload_map_alloc, .map_free = bpf_map_offload_map_free, .map_check_btf = map_check_no_btf, @@ -127,162 +127,7 @@ static struct bpf_map *find_and_alloc_map(union bpf_attr *attr) return map; } -static void bpf_map_write_active_inc(struct bpf_map *map) -{ - atomic64_inc(&map->writecnt); -} - -static void bpf_map_write_active_dec(struct bpf_map *map) -{ - atomic64_dec(&map->writecnt); -} - -bool bpf_map_write_active(const struct bpf_map *map) -{ - return atomic64_read(&map->writecnt) != 0; -} - -static u32 bpf_map_value_size(struct bpf_map *map) -{ - if (map->map_type == BPF_MAP_TYPE_PERCPU_HASH || - map->map_type == BPF_MAP_TYPE_LRU_PERCPU_HASH || - map->map_type == BPF_MAP_TYPE_PERCPU_ARRAY || - map->map_type == BPF_MAP_TYPE_PERCPU_CGROUP_STORAGE) - return round_up(map->value_size, 8) * num_possible_cpus(); - else if (IS_FD_MAP(map)) - return sizeof(u32); - else - return map->value_size; -} - -static void maybe_wait_bpf_programs(struct bpf_map *map) -{ - /* Wait for any running BPF programs to complete so that - * userspace, when we return to it, knows that all programs - * that could be running use the new map value. - */ - if (map->map_type == BPF_MAP_TYPE_HASH_OF_MAPS || - map->map_type == BPF_MAP_TYPE_ARRAY_OF_MAPS) - synchronize_rcu(); -} - -static int bpf_map_update_value(struct bpf_map *map, struct fd f, void *key, - void *value, __u64 flags) -{ - int err; - - /* Need to create a kthread, thus must support schedule */ - if (bpf_map_is_dev_bound(map)) { - return bpf_map_offload_update_elem(map, key, value, flags); - } else if (map->map_type == BPF_MAP_TYPE_CPUMAP || - map->map_type == BPF_MAP_TYPE_STRUCT_OPS) { - return map->ops->map_update_elem(map, key, value, flags); - } else if (map->map_type == BPF_MAP_TYPE_SOCKHASH || - map->map_type == BPF_MAP_TYPE_SOCKMAP) { - return sock_map_update_elem_sys(map, key, value, flags); - } else if (IS_FD_PROG_ARRAY(map)) { - return bpf_fd_array_map_update_elem(map, f.file, key, value, - flags); - } - - bpf_disable_instrumentation(); - if (map->map_type == BPF_MAP_TYPE_PERCPU_HASH || - map->map_type == BPF_MAP_TYPE_LRU_PERCPU_HASH) { - err = bpf_percpu_hash_update(map, key, value, flags); - } else if (map->map_type == BPF_MAP_TYPE_PERCPU_ARRAY) { - err = bpf_percpu_array_update(map, key, value, flags); - } else if (map->map_type == BPF_MAP_TYPE_PERCPU_CGROUP_STORAGE) { - err = bpf_percpu_cgroup_storage_update(map, key, value, - flags); - } else if (IS_FD_ARRAY(map)) { - rcu_read_lock(); - err = bpf_fd_array_map_update_elem(map, f.file, key, value, - flags); - rcu_read_unlock(); - } else if (map->map_type == BPF_MAP_TYPE_HASH_OF_MAPS) { - rcu_read_lock(); - err = bpf_fd_htab_map_update_elem(map, f.file, key, value, - flags); - rcu_read_unlock(); - } else if (map->map_type == BPF_MAP_TYPE_REUSEPORT_SOCKARRAY) { - /* rcu_read_lock() is not needed */ - err = bpf_fd_reuseport_array_update_elem(map, key, value, - flags); - } else if (map->map_type == BPF_MAP_TYPE_QUEUE || - map->map_type == BPF_MAP_TYPE_STACK) { - err = map->ops->map_push_elem(map, value, flags); - } else { - rcu_read_lock(); - err = map->ops->map_update_elem(map, key, value, flags); - rcu_read_unlock(); - } - bpf_enable_instrumentation(); - maybe_wait_bpf_programs(map); - - return err; -} - -static int bpf_map_copy_value(struct bpf_map *map, void *key, void *value, - __u64 flags) -{ - void *ptr; - int err; - - if (bpf_map_is_dev_bound(map)) - return bpf_map_offload_lookup_elem(map, key, value); - - bpf_disable_instrumentation(); - if (map->map_type == BPF_MAP_TYPE_PERCPU_HASH || - map->map_type == BPF_MAP_TYPE_LRU_PERCPU_HASH) { - err = bpf_percpu_hash_copy(map, key, value); - } else if (map->map_type == BPF_MAP_TYPE_PERCPU_ARRAY) { - err = bpf_percpu_array_copy(map, key, value); - } else if (map->map_type == BPF_MAP_TYPE_PERCPU_CGROUP_STORAGE) { - err = bpf_percpu_cgroup_storage_copy(map, key, value); - } else if (map->map_type == BPF_MAP_TYPE_STACK_TRACE) { - err = bpf_stackmap_copy(map, key, value); - } else if (IS_FD_ARRAY(map) || IS_FD_PROG_ARRAY(map)) { - err = bpf_fd_array_map_lookup_elem(map, key, value); - } else if (IS_FD_HASH(map)) { - err = bpf_fd_htab_map_lookup_elem(map, key, value); - } else if (map->map_type == BPF_MAP_TYPE_REUSEPORT_SOCKARRAY) { - err = bpf_fd_reuseport_array_lookup_elem(map, key, value); - } else if (map->map_type == BPF_MAP_TYPE_QUEUE || - map->map_type == BPF_MAP_TYPE_STACK) { - err = map->ops->map_peek_elem(map, value); - } else if (map->map_type == BPF_MAP_TYPE_STRUCT_OPS) { - /* struct_ops map requires directly updating "value" */ - err = bpf_struct_ops_map_sys_lookup_elem(map, key, value); - } else { - rcu_read_lock(); - if (map->ops->map_lookup_elem_sys_only) - ptr = map->ops->map_lookup_elem_sys_only(map, key); - else - ptr = map->ops->map_lookup_elem(map, key); - if (IS_ERR(ptr)) { - err = PTR_ERR(ptr); - } else if (!ptr) { - err = -ENOENT; - } else { - err = 0; - if (flags & BPF_F_LOCK) - /* lock 'ptr' and copy everything but lock */ - copy_map_value_locked(map, value, ptr, true); - else - copy_map_value(map, value, ptr); - /* mask lock, since value wasn't zero inited */ - check_and_init_map_lock(map, value); - } - rcu_read_unlock(); - } - - bpf_enable_instrumentation(); - maybe_wait_bpf_programs(map); - - return err; -} - -static void *__bpf_map_area_alloc(u64 size, int numa_node, bool mmapable) +void *bpf_map_area_alloc(u64 size, int numa_node) { /* We really just want to fail instead of triggering OOM killer * under memory pressure, therefore we set __GFP_NORETRY to kmalloc, @@ -300,32 +145,18 @@ static void *__bpf_map_area_alloc(u64 size, int numa_node, bool mmapable) if (size >= SIZE_MAX) return NULL; - if (!mmapable && size <= (PAGE_SIZE << PAGE_ALLOC_COSTLY_ORDER)) { + if (size <= (PAGE_SIZE << PAGE_ALLOC_COSTLY_ORDER)) { area = kmalloc_node(size, GFP_USER | __GFP_NORETRY | flags, numa_node); if (area != NULL) return area; } - if (mmapable) { - BUG_ON(!PAGE_ALIGNED(size)); - return vmalloc_user_node_flags(size, numa_node, GFP_KERNEL | - __GFP_RETRY_MAYFAIL | flags); - } + return __vmalloc_node_flags_caller(size, numa_node, GFP_KERNEL | __GFP_RETRY_MAYFAIL | flags, __builtin_return_address(0)); } -void *bpf_map_area_alloc(u64 size, int numa_node) -{ - return __bpf_map_area_alloc(size, numa_node, false); -} - -void *bpf_map_area_mmapable_alloc(u64 size, int numa_node) -{ - return __bpf_map_area_alloc(size, numa_node, true); -} - void bpf_map_area_free(void *area) { kvfree(area); @@ -483,7 +314,7 @@ static void bpf_map_free_deferred(struct work_struct *work) static void bpf_map_put_uref(struct bpf_map *map) { - if (atomic64_dec_and_test(&map->usercnt)) { + if (atomic_dec_and_test(&map->usercnt)) { if (map->ops->map_release_uref) map->ops->map_release_uref(map); } @@ -494,7 +325,7 @@ static void bpf_map_put_uref(struct bpf_map *map) */ static void __bpf_map_put(struct bpf_map *map, bool do_idr_lock) { - if (atomic64_dec_and_test(&map->refcnt)) { + if (atomic_dec_and_test(&map->refcnt)) { /* bpf_map_free_id() must be called first */ bpf_map_free_id(map, do_idr_lock); btf_put(map->btf); @@ -543,14 +374,13 @@ static void bpf_map_show_fdinfo(struct seq_file *m, struct file *filp) { const struct bpf_map *map = filp->private_data; const struct bpf_array *array; - u32 type = 0, jited = 0; + u32 owner_prog_type = 0; + u32 owner_jited = 0; if (map->map_type == BPF_MAP_TYPE_PROG_ARRAY) { array = container_of(map, struct bpf_array, map); - spin_lock(&array->aux->owner.lock); - type = array->aux->owner.type; - jited = array->aux->owner.jited; - spin_unlock(&array->aux->owner.lock); + owner_prog_type = array->owner_prog_type; + owner_jited = array->owner_jited; } seq_printf(m, @@ -570,9 +400,12 @@ static void bpf_map_show_fdinfo(struct seq_file *m, struct file *filp) map->memory.pages * 1ULL << PAGE_SHIFT, map->id, READ_ONCE(map->frozen)); - if (type) { - seq_printf(m, "owner_prog_type:\t%u\n", type); - seq_printf(m, "owner_jited:\t%u\n", jited); + + if (owner_prog_type) { + seq_printf(m, "owner_prog_type:\t%u\n", + owner_prog_type); + seq_printf(m, "owner_jited:\t%u\n", + owner_jited); } } #endif @@ -595,90 +428,6 @@ static ssize_t bpf_dummy_write(struct file *filp, const char __user *buf, return -EINVAL; } -/* called for any extra memory-mapped regions (except initial) */ -static void bpf_map_mmap_open(struct vm_area_struct *vma) -{ - struct bpf_map *map = vma->vm_file->private_data; - - if (vma->vm_flags & VM_MAYWRITE) - bpf_map_write_active_inc(map); -} - -/* called for all unmapped memory region (including initial) */ -static void bpf_map_mmap_close(struct vm_area_struct *vma) -{ - struct bpf_map *map = vma->vm_file->private_data; - - if (vma->vm_flags & VM_MAYWRITE) - bpf_map_write_active_dec(map); -} - -static const struct vm_operations_struct bpf_map_default_vmops = { - .open = bpf_map_mmap_open, - .close = bpf_map_mmap_close, -}; - -static int bpf_map_mmap(struct file *filp, struct vm_area_struct *vma) -{ - struct bpf_map *map = filp->private_data; - int err = 0; - - if (!map->ops->map_mmap || map_value_has_spin_lock(map)) - return -ENOTSUPP; - - if (!(vma->vm_flags & VM_SHARED)) - return -EINVAL; - - mutex_lock(&map->freeze_mutex); - - if (vma->vm_flags & VM_WRITE) { - if (map->frozen) { - err = -EPERM; - goto out; - } - /* map is meant to be read-only, so do not allow mapping as - * writable, because it's possible to leak a writable page - * reference and allows user-space to still modify it after - * freezing, while verifier will assume contents do not change - */ - if (map->map_flags & BPF_F_RDONLY_PROG) { - err = -EACCES; - goto out; - } - bpf_map_write_active_inc(map); - } -out: - mutex_unlock(&map->freeze_mutex); - if (err) - return err; - - /* set default open/close callbacks */ - vma->vm_ops = &bpf_map_default_vmops; - vma->vm_private_data = map; - vma->vm_flags &= ~VM_MAYEXEC; - if (!(vma->vm_flags & VM_WRITE)) - /* disallow re-mapping with PROT_WRITE */ - vma->vm_flags &= ~VM_MAYWRITE; - - err = map->ops->map_mmap(map, vma); - if (err) { - if (vma->vm_flags & VM_WRITE) - bpf_map_write_active_dec(map); - } - - return err; -} - -static __poll_t bpf_map_poll(struct file *filp, struct poll_table_struct *pts) -{ - struct bpf_map *map = filp->private_data; - - if (map->ops->map_poll) - return map->ops->map_poll(map, filp, pts); - - return EPOLLERR; -} - const struct file_operations bpf_map_fops = { #ifdef CONFIG_PROC_FS .show_fdinfo = bpf_map_show_fdinfo, @@ -686,8 +435,6 @@ const struct file_operations bpf_map_fops = { .release = bpf_map_release, .read = bpf_dummy_read, .write = bpf_dummy_write, - .mmap = bpf_map_mmap, - .poll = bpf_map_poll, }; int bpf_map_new_fd(struct bpf_map *map, int flags) @@ -721,15 +468,14 @@ int bpf_get_file_flag(int flags) offsetof(union bpf_attr, CMD##_LAST_FIELD) - \ sizeof(attr->CMD##_LAST_FIELD)) != NULL -/* dst and src must have at least "size" number of bytes. - * Return strlen on success and < 0 on error. +/* dst and src must have at least BPF_OBJ_NAME_LEN number of bytes. + * Return 0 on success and < 0 on error. */ -int bpf_obj_name_cpy(char *dst, const char *src, unsigned int size) +static int bpf_obj_name_cpy(char *dst, const char *src) { - const char *end = src + size; - const char *orig_src = src; + const char *end = src + BPF_OBJ_NAME_LEN; - memset(dst, 0, size); + memset(dst, 0, BPF_OBJ_NAME_LEN); /* Copy all isalnum(), '_' and '.' chars. */ while (src < end && *src) { if (!isalnum(*src) && @@ -738,11 +484,11 @@ int bpf_obj_name_cpy(char *dst, const char *src, unsigned int size) *dst++ = *src++; } - /* No '\0' found in "size" number of bytes */ + /* No '\0' found in BPF_OBJ_NAME_LEN number of bytes */ if (src == end) return -EINVAL; - return src - orig_src; + return 0; } int map_check_no_btf(const struct bpf_map *map, @@ -783,8 +529,7 @@ static int map_check_btf(struct bpf_map *map, const struct btf *btf, if (map->map_type != BPF_MAP_TYPE_HASH && map->map_type != BPF_MAP_TYPE_ARRAY && map->map_type != BPF_MAP_TYPE_CGROUP_STORAGE && - map->map_type != BPF_MAP_TYPE_SK_STORAGE && - map->map_type != BPF_MAP_TYPE_INODE_STORAGE) + map->map_type != BPF_MAP_TYPE_SK_STORAGE) return -ENOTSUPP; if (map->spin_lock_off + sizeof(struct bpf_spin_lock) > map->value_size) { @@ -801,7 +546,7 @@ static int map_check_btf(struct bpf_map *map, const struct btf *btf, return ret; } -#define BPF_MAP_CREATE_LAST_FIELD btf_vmlinux_value_type_id +#define BPF_MAP_CREATE_LAST_FIELD btf_value_type_id /* called via syscall */ static int map_create(union bpf_attr *attr) { @@ -815,14 +560,6 @@ static int map_create(union bpf_attr *attr) if (err) return -EINVAL; - if (attr->btf_vmlinux_value_type_id) { - if (attr->map_type != BPF_MAP_TYPE_STRUCT_OPS || - attr->btf_key_type_id || attr->btf_value_type_id) - return -EINVAL; - } else if (attr->btf_key_type_id && !attr->btf_value_type_id) { - return -EINVAL; - } - f_flags = bpf_get_file_flag(attr->map_flags); if (f_flags < 0) return f_flags; @@ -837,44 +574,39 @@ static int map_create(union bpf_attr *attr) if (IS_ERR(map)) return PTR_ERR(map); - err = bpf_obj_name_cpy(map->name, attr->map_name, - sizeof(attr->map_name)); - if (err < 0) + err = bpf_obj_name_cpy(map->name, attr->map_name); + if (err) goto free_map; - atomic64_set(&map->refcnt, 1); - atomic64_set(&map->usercnt, 1); - mutex_init(&map->freeze_mutex); + atomic_set(&map->refcnt, 1); + atomic_set(&map->usercnt, 1); - map->spin_lock_off = -EINVAL; - if (attr->btf_key_type_id || attr->btf_value_type_id || - /* Even the map's value is a kernel's struct, - * the bpf_prog.o must have BTF to begin with - * to figure out the corresponding kernel's - * counter part. Thus, attr->btf_fd has - * to be valid also. - */ - attr->btf_vmlinux_value_type_id) { + if (attr->btf_key_type_id || attr->btf_value_type_id) { struct btf *btf; + if (!attr->btf_value_type_id) { + err = -EINVAL; + goto free_map; + } + btf = btf_get_by_fd(attr->btf_fd); if (IS_ERR(btf)) { err = PTR_ERR(btf); goto free_map; } - map->btf = btf; - if (attr->btf_value_type_id) { - err = map_check_btf(map, btf, attr->btf_key_type_id, - attr->btf_value_type_id); - if (err) - goto free_map; + err = map_check_btf(map, btf, attr->btf_key_type_id, + attr->btf_value_type_id); + if (err) { + btf_put(btf); + goto free_map; } + map->btf = btf; map->btf_key_type_id = attr->btf_key_type_id; map->btf_value_type_id = attr->btf_value_type_id; - map->btf_vmlinux_value_type_id = - attr->btf_vmlinux_value_type_id; + } else { + map->spin_lock_off = -EINVAL; } err = security_bpf_map_alloc(map); @@ -924,33 +656,20 @@ struct bpf_map *__bpf_map_get(struct fd f) return f.file->private_data; } -void bpf_map_inc(struct bpf_map *map) +/* prog's and map's refcnt limit */ +#define BPF_MAX_REFCNT 32768 + +struct bpf_map *bpf_map_inc(struct bpf_map *map, bool uref) { - atomic64_inc(&map->refcnt); -} -EXPORT_SYMBOL_GPL(bpf_map_inc); - -void bpf_map_inc_with_uref(struct bpf_map *map) -{ - atomic64_inc(&map->refcnt); - atomic64_inc(&map->usercnt); -} -EXPORT_SYMBOL_GPL(bpf_map_inc_with_uref); - -struct bpf_map *bpf_map_get(u32 ufd) -{ - struct fd f = fdget(ufd); - struct bpf_map *map; - - map = __bpf_map_get(f); - if (IS_ERR(map)) - return map; - - bpf_map_inc(map); - fdput(f); - + if (atomic_inc_return(&map->refcnt) > BPF_MAX_REFCNT) { + atomic_dec(&map->refcnt); + return ERR_PTR(-EBUSY); + } + if (uref) + atomic_inc(&map->usercnt); return map; } +EXPORT_SYMBOL_GPL(bpf_map_inc); struct bpf_map *bpf_map_get_with_uref(u32 ufd) { @@ -961,30 +680,38 @@ struct bpf_map *bpf_map_get_with_uref(u32 ufd) if (IS_ERR(map)) return map; - bpf_map_inc_with_uref(map); + map = bpf_map_inc(map, true); fdput(f); return map; } /* map_idr_lock should have been held */ -static struct bpf_map *__bpf_map_inc_not_zero(struct bpf_map *map, bool uref) +static struct bpf_map *__bpf_map_inc_not_zero(struct bpf_map *map, + bool uref) { int refold; - refold = atomic64_fetch_add_unless(&map->refcnt, 1, 0); + refold = atomic_fetch_add_unless(&map->refcnt, 1, 0); + + if (refold >= BPF_MAX_REFCNT) { + __bpf_map_put(map, false); + return ERR_PTR(-EBUSY); + } + if (!refold) return ERR_PTR(-ENOENT); + if (uref) - atomic64_inc(&map->usercnt); + atomic_inc(&map->usercnt); return map; } -struct bpf_map *bpf_map_inc_not_zero(struct bpf_map *map) +struct bpf_map *bpf_map_inc_not_zero(struct bpf_map *map, bool uref) { spin_lock_bh(&map_idr_lock); - map = __bpf_map_inc_not_zero(map, false); + map = __bpf_map_inc_not_zero(map, uref); spin_unlock_bh(&map_idr_lock); return map; @@ -1016,7 +743,7 @@ static int map_lookup_elem(union bpf_attr *attr) void __user *uvalue = u64_to_user_ptr(attr->value); int ufd = attr->map_fd; struct bpf_map *map; - void *key, *value; + void *key, *value, *ptr; u32 value_size; struct fd f; int err; @@ -1048,14 +775,72 @@ static int map_lookup_elem(union bpf_attr *attr) goto err_put; } - value_size = bpf_map_value_size(map); + if (map->map_type == BPF_MAP_TYPE_PERCPU_HASH || + map->map_type == BPF_MAP_TYPE_LRU_PERCPU_HASH || + map->map_type == BPF_MAP_TYPE_PERCPU_ARRAY || + map->map_type == BPF_MAP_TYPE_PERCPU_CGROUP_STORAGE) + value_size = round_up(map->value_size, 8) * num_possible_cpus(); + else if (IS_FD_MAP(map)) + value_size = sizeof(u32); + else + value_size = map->value_size; err = -ENOMEM; value = kmalloc(value_size, GFP_USER | __GFP_NOWARN); if (!value) goto free_key; - err = bpf_map_copy_value(map, key, value, attr->flags); + if (bpf_map_is_dev_bound(map)) { + err = bpf_map_offload_lookup_elem(map, key, value); + goto done; + } + + preempt_disable(); + this_cpu_inc(bpf_prog_active); + if (map->map_type == BPF_MAP_TYPE_PERCPU_HASH || + map->map_type == BPF_MAP_TYPE_LRU_PERCPU_HASH) { + err = bpf_percpu_hash_copy(map, key, value); + } else if (map->map_type == BPF_MAP_TYPE_PERCPU_ARRAY) { + err = bpf_percpu_array_copy(map, key, value); + } else if (map->map_type == BPF_MAP_TYPE_PERCPU_CGROUP_STORAGE) { + err = bpf_percpu_cgroup_storage_copy(map, key, value); + } else if (map->map_type == BPF_MAP_TYPE_STACK_TRACE) { + err = bpf_stackmap_copy(map, key, value); + } else if (IS_FD_ARRAY(map)) { + err = bpf_fd_array_map_lookup_elem(map, key, value); + } else if (IS_FD_HASH(map)) { + err = bpf_fd_htab_map_lookup_elem(map, key, value); + } else if (map->map_type == BPF_MAP_TYPE_REUSEPORT_SOCKARRAY) { + err = bpf_fd_reuseport_array_lookup_elem(map, key, value); + } else if (map->map_type == BPF_MAP_TYPE_QUEUE || + map->map_type == BPF_MAP_TYPE_STACK) { + err = map->ops->map_peek_elem(map, value); + } else { + rcu_read_lock(); + if (map->ops->map_lookup_elem_sys_only) + ptr = map->ops->map_lookup_elem_sys_only(map, key); + else + ptr = map->ops->map_lookup_elem(map, key); + if (IS_ERR(ptr)) { + err = PTR_ERR(ptr); + } else if (!ptr) { + err = -ENOENT; + } else { + err = 0; + if (attr->flags & BPF_F_LOCK) + /* lock 'ptr' and copy everything but lock */ + copy_map_value_locked(map, value, ptr, true); + else + copy_map_value(map, value, ptr); + /* mask lock, since value wasn't zero inited */ + check_and_init_map_lock(map, value); + } + rcu_read_unlock(); + } + this_cpu_dec(bpf_prog_active); + preempt_enable(); + +done: if (err) goto free_value; @@ -1074,6 +859,16 @@ err_put: return err; } +static void maybe_wait_bpf_programs(struct bpf_map *map) +{ + /* Wait for any running BPF programs to complete so that + * userspace, when we return to it, knows that all programs + * that could be running use the new map value. + */ + if (map->map_type == BPF_MAP_TYPE_HASH_OF_MAPS || + map->map_type == BPF_MAP_TYPE_ARRAY_OF_MAPS) + synchronize_rcu(); +} #define BPF_MAP_UPDATE_ELEM_LAST_FIELD flags @@ -1095,7 +890,6 @@ static int map_update_elem(union bpf_attr *attr) map = __bpf_map_get(f); if (IS_ERR(map)) return PTR_ERR(map); - bpf_map_write_active_inc(map); if (!(map_get_sys_perms(map, f) & FMODE_CAN_WRITE)) { err = -EPERM; goto err_put; @@ -1130,14 +924,61 @@ static int map_update_elem(union bpf_attr *attr) if (copy_from_user(value, uvalue, value_size) != 0) goto free_value; - err = bpf_map_update_value(map, f, key, value, attr->flags); + /* Need to create a kthread, thus must support schedule */ + if (bpf_map_is_dev_bound(map)) { + err = bpf_map_offload_update_elem(map, key, value, attr->flags); + goto out; + } else if (map->map_type == BPF_MAP_TYPE_CPUMAP || + map->map_type == BPF_MAP_TYPE_SOCKHASH || + map->map_type == BPF_MAP_TYPE_SOCKMAP) { + err = map->ops->map_update_elem(map, key, value, attr->flags); + goto out; + } + /* must increment bpf_prog_active to avoid kprobe+bpf triggering from + * inside bpf map update or delete otherwise deadlocks are possible + */ + preempt_disable(); + __this_cpu_inc(bpf_prog_active); + if (map->map_type == BPF_MAP_TYPE_PERCPU_HASH || + map->map_type == BPF_MAP_TYPE_LRU_PERCPU_HASH) { + err = bpf_percpu_hash_update(map, key, value, attr->flags); + } else if (map->map_type == BPF_MAP_TYPE_PERCPU_ARRAY) { + err = bpf_percpu_array_update(map, key, value, attr->flags); + } else if (map->map_type == BPF_MAP_TYPE_PERCPU_CGROUP_STORAGE) { + err = bpf_percpu_cgroup_storage_update(map, key, value, + attr->flags); + } else if (IS_FD_ARRAY(map)) { + rcu_read_lock(); + err = bpf_fd_array_map_update_elem(map, f.file, key, value, + attr->flags); + rcu_read_unlock(); + } else if (map->map_type == BPF_MAP_TYPE_HASH_OF_MAPS) { + rcu_read_lock(); + err = bpf_fd_htab_map_update_elem(map, f.file, key, value, + attr->flags); + rcu_read_unlock(); + } else if (map->map_type == BPF_MAP_TYPE_REUSEPORT_SOCKARRAY) { + /* rcu_read_lock() is not needed */ + err = bpf_fd_reuseport_array_update_elem(map, key, value, + attr->flags); + } else if (map->map_type == BPF_MAP_TYPE_QUEUE || + map->map_type == BPF_MAP_TYPE_STACK) { + err = map->ops->map_push_elem(map, value, attr->flags); + } else { + rcu_read_lock(); + err = map->ops->map_update_elem(map, key, value, attr->flags); + rcu_read_unlock(); + } + __this_cpu_dec(bpf_prog_active); + preempt_enable(); + maybe_wait_bpf_programs(map); +out: free_value: kfree(value); free_key: kfree(key); err_put: - bpf_map_write_active_dec(map); fdput(f); return err; } @@ -1160,7 +1001,6 @@ static int map_delete_elem(union bpf_attr *attr) map = __bpf_map_get(f); if (IS_ERR(map)) return PTR_ERR(map); - bpf_map_write_active_inc(map); if (!(map_get_sys_perms(map, f) & FMODE_CAN_WRITE)) { err = -EPERM; goto err_put; @@ -1175,23 +1015,19 @@ static int map_delete_elem(union bpf_attr *attr) if (bpf_map_is_dev_bound(map)) { err = bpf_map_offload_delete_elem(map, key); goto out; - } else if (IS_FD_PROG_ARRAY(map) || - map->map_type == BPF_MAP_TYPE_STRUCT_OPS) { - /* These maps require sleepable context */ - err = map->ops->map_delete_elem(map, key); - goto out; } - bpf_disable_instrumentation(); + preempt_disable(); + __this_cpu_inc(bpf_prog_active); rcu_read_lock(); err = map->ops->map_delete_elem(map, key); rcu_read_unlock(); - bpf_enable_instrumentation(); + __this_cpu_dec(bpf_prog_active); + preempt_enable(); maybe_wait_bpf_programs(map); out: kfree(key); err_put: - bpf_map_write_active_dec(map); fdput(f); return err; } @@ -1263,220 +1099,6 @@ err_put: return err; } -int generic_map_delete_batch(struct bpf_map *map, - const union bpf_attr *attr, - union bpf_attr __user *uattr) -{ - void __user *keys = u64_to_user_ptr(attr->batch.keys); - u32 cp, max_count; - int err = 0; - void *key; - - if (attr->batch.elem_flags & ~BPF_F_LOCK) - return -EINVAL; - - if ((attr->batch.elem_flags & BPF_F_LOCK) && - !map_value_has_spin_lock(map)) { - return -EINVAL; - } - - max_count = attr->batch.count; - if (!max_count) - return 0; - - if (put_user(0, &uattr->batch.count)) - return -EFAULT; - - key = kmalloc(map->key_size, GFP_USER | __GFP_NOWARN); - if (!key) - return -ENOMEM; - - for (cp = 0; cp < max_count; cp++) { - err = -EFAULT; - if (copy_from_user(key, keys + cp * map->key_size, - map->key_size)) - break; - - if (bpf_map_is_dev_bound(map)) { - err = bpf_map_offload_delete_elem(map, key); - break; - } - - bpf_disable_instrumentation(); - rcu_read_lock(); - err = map->ops->map_delete_elem(map, key); - rcu_read_unlock(); - bpf_enable_instrumentation(); - maybe_wait_bpf_programs(map); - if (err) - break; - cond_resched(); - } - if (copy_to_user(&uattr->batch.count, &cp, sizeof(cp))) - err = -EFAULT; - - kfree(key); - return err; -} - -int generic_map_update_batch(struct bpf_map *map, - const union bpf_attr *attr, - union bpf_attr __user *uattr) -{ - void __user *values = u64_to_user_ptr(attr->batch.values); - void __user *keys = u64_to_user_ptr(attr->batch.keys); - u32 value_size, cp, max_count; - int ufd = attr->batch.map_fd; - void *key, *value; - struct fd f; - int err = 0; - - if (attr->batch.elem_flags & ~BPF_F_LOCK) - return -EINVAL; - - if ((attr->batch.elem_flags & BPF_F_LOCK) && - !map_value_has_spin_lock(map)) { - return -EINVAL; - } - - value_size = bpf_map_value_size(map); - - max_count = attr->batch.count; - if (!max_count) - return 0; - - if (put_user(0, &uattr->batch.count)) - return -EFAULT; - - key = kmalloc(map->key_size, GFP_USER | __GFP_NOWARN); - if (!key) - return -ENOMEM; - - value = kmalloc(value_size, GFP_USER | __GFP_NOWARN); - if (!value) { - kfree(key); - return -ENOMEM; - } - - f = fdget(ufd); /* bpf_map_do_batch() guarantees ufd is valid */ - for (cp = 0; cp < max_count; cp++) { - err = -EFAULT; - if (copy_from_user(key, keys + cp * map->key_size, - map->key_size) || - copy_from_user(value, values + cp * value_size, value_size)) - break; - - err = bpf_map_update_value(map, f, key, value, - attr->batch.elem_flags); - - if (err) - break; - cond_resched(); - } - - if (copy_to_user(&uattr->batch.count, &cp, sizeof(cp))) - err = -EFAULT; - - kfree(value); - kfree(key); - fdput(f); - return err; -} - -int generic_map_lookup_batch(struct bpf_map *map, - const union bpf_attr *attr, - union bpf_attr __user *uattr) -{ - void __user *uobatch = u64_to_user_ptr(attr->batch.out_batch); - void __user *ubatch = u64_to_user_ptr(attr->batch.in_batch); - void __user *values = u64_to_user_ptr(attr->batch.values); - void __user *keys = u64_to_user_ptr(attr->batch.keys); - void *buf, *buf_prevkey, *prev_key, *key, *value; - u32 value_size, cp, max_count; - int err; - - if (attr->batch.elem_flags & ~BPF_F_LOCK) - return -EINVAL; - - if ((attr->batch.elem_flags & BPF_F_LOCK) && - !map_value_has_spin_lock(map)) - return -EINVAL; - - value_size = bpf_map_value_size(map); - - max_count = attr->batch.count; - if (!max_count) - return 0; - - if (put_user(0, &uattr->batch.count)) - return -EFAULT; - - buf_prevkey = kmalloc(map->key_size, GFP_USER | __GFP_NOWARN); - if (!buf_prevkey) - return -ENOMEM; - - buf = kmalloc(map->key_size + value_size, GFP_USER | __GFP_NOWARN); - if (!buf) { - kfree(buf_prevkey); - return -ENOMEM; - } - - err = -EFAULT; - prev_key = NULL; - if (ubatch && copy_from_user(buf_prevkey, ubatch, map->key_size)) - goto free_buf; - key = buf; - value = key + map->key_size; - if (ubatch) - prev_key = buf_prevkey; - - for (cp = 0; cp < max_count;) { - rcu_read_lock(); - err = map->ops->map_get_next_key(map, prev_key, key); - rcu_read_unlock(); - if (err) - break; - err = bpf_map_copy_value(map, key, value, - attr->batch.elem_flags); - - if (err == -ENOENT) - goto next_key; - - if (err) - goto free_buf; - - if (copy_to_user(keys + cp * map->key_size, key, - map->key_size)) { - err = -EFAULT; - goto free_buf; - } - if (copy_to_user(values + cp * value_size, value, value_size)) { - err = -EFAULT; - goto free_buf; - } - - cp++; -next_key: - if (!prev_key) - prev_key = buf_prevkey; - - swap(prev_key, key); - cond_resched(); - } - - if (err == -EFAULT) - goto free_buf; - - if ((copy_to_user(&uattr->batch.count, &cp, sizeof(cp)) || - (cp && copy_to_user(uobatch, prev_key, map->key_size)))) - err = -EFAULT; - -free_buf: - kfree(buf_prevkey); - kfree(buf); - return err; -} - #define BPF_MAP_LOOKUP_AND_DELETE_ELEM_LAST_FIELD value static int map_lookup_and_delete_elem(union bpf_attr *attr) @@ -1497,7 +1119,6 @@ static int map_lookup_and_delete_elem(union bpf_attr *attr) map = __bpf_map_get(f); if (IS_ERR(map)) return PTR_ERR(map); - bpf_map_write_active_inc(map); if (!(map_get_sys_perms(map, f) & FMODE_CAN_READ) || !(map_get_sys_perms(map, f) & FMODE_CAN_WRITE)) { err = -EPERM; @@ -1539,7 +1160,6 @@ free_value: free_key: kfree(key); err_put: - bpf_map_write_active_dec(map); fdput(f); return err; } @@ -1559,42 +1179,28 @@ static int map_freeze(const union bpf_attr *attr) map = __bpf_map_get(f); if (IS_ERR(map)) return PTR_ERR(map); - - if (map->map_type == BPF_MAP_TYPE_STRUCT_OPS) { - fdput(f); - return -ENOTSUPP; - } - - mutex_lock(&map->freeze_mutex); - if (bpf_map_write_active(map)) { - err = -EBUSY; - goto err_put; - } if (READ_ONCE(map->frozen)) { err = -EBUSY; goto err_put; } - if (!bpf_capable()) { + if (!capable(CAP_SYS_ADMIN)) { err = -EPERM; goto err_put; } WRITE_ONCE(map->frozen, true); err_put: - mutex_unlock(&map->freeze_mutex); fdput(f); return err; } static const struct bpf_prog_ops * const bpf_prog_types[] = { -#define BPF_PROG_TYPE(_id, _name, prog_ctx_type, kern_ctx_type) \ +#define BPF_PROG_TYPE(_id, _name) \ [_id] = & _name ## _prog_ops, #define BPF_MAP_TYPE(_id, _ops) -#define BPF_LINK_TYPE(_id, _name) #include #undef BPF_PROG_TYPE #undef BPF_MAP_TYPE -#undef BPF_LINK_TYPE }; static int find_prog_type(enum bpf_prog_type type, struct bpf_prog *prog) @@ -1616,34 +1222,23 @@ static int find_prog_type(enum bpf_prog_type type, struct bpf_prog *prog) return 0; } -enum bpf_audit { - BPF_AUDIT_LOAD, - BPF_AUDIT_UNLOAD, - BPF_AUDIT_MAX, -}; - -static const char * const bpf_audit_str[BPF_AUDIT_MAX] = { - [BPF_AUDIT_LOAD] = "LOAD", - [BPF_AUDIT_UNLOAD] = "UNLOAD", -}; - -static void bpf_audit_prog(const struct bpf_prog *prog, unsigned int op) +/* drop refcnt on maps used by eBPF program and free auxilary data */ +static void free_used_maps(struct bpf_prog_aux *aux) { - struct audit_context *ctx = NULL; - struct audit_buffer *ab; + enum bpf_cgroup_storage_type stype; + int i; - if (WARN_ON_ONCE(op >= BPF_AUDIT_MAX)) - return; - if (audit_enabled == AUDIT_OFF) - return; - if (op == BPF_AUDIT_LOAD) - ctx = audit_context(); - ab = audit_log_start(ctx, GFP_ATOMIC, AUDIT_BPF); - if (unlikely(!ab)) - return; - audit_log_format(ab, "prog-id=%u op=%s", - prog->aux->id, bpf_audit_str[op]); - audit_log_end(ab); + for_each_cgroup_storage_type(stype) { + if (!aux->cgroup_storage[stype]) + continue; + bpf_cgroup_storage_release(aux->prog, + aux->cgroup_storage[stype]); + } + + for (i = 0; i < aux->used_map_cnt; i++) + bpf_map_put(aux->used_maps[i]); + + kfree(aux->used_maps); } int __bpf_prog_charge(struct user_struct *user, u32 pages) @@ -1739,7 +1334,7 @@ static void __bpf_prog_put_rcu(struct rcu_head *rcu) struct bpf_prog_aux *aux = container_of(rcu, struct bpf_prog_aux, rcu); kvfree(aux->func_info); - kfree(aux->func_info_aux); + free_used_maps(aux); bpf_prog_uncharge_memlock(aux->prog); security_bpf_prog_free(aux); bpf_prog_free(aux->prog); @@ -1751,21 +1346,16 @@ static void __bpf_prog_put_noref(struct bpf_prog *prog, bool deferred) btf_put(prog->aux->btf); bpf_prog_free_linfo(prog); - if (deferred) { - if (prog->aux->sleepable) - call_rcu_tasks_trace(&prog->aux->rcu, __bpf_prog_put_rcu); - else - call_rcu(&prog->aux->rcu, __bpf_prog_put_rcu); - } else { + if (deferred) + call_rcu(&prog->aux->rcu, __bpf_prog_put_rcu); + else __bpf_prog_put_rcu(&prog->aux->rcu); - } } static void __bpf_prog_put(struct bpf_prog *prog, bool do_idr_lock) { - if (atomic64_dec_and_test(&prog->aux->refcnt)) { + if (atomic_dec_and_test(&prog->aux->refcnt)) { perf_event_bpf_event(prog, PERF_BPF_EVENT_PROG_UNLOAD, 0); - bpf_audit_prog(prog, BPF_AUDIT_UNLOAD); /* bpf_prog_free_id() must be called first */ bpf_prog_free_id(prog, do_idr_lock); __bpf_prog_put_noref(prog, true); @@ -1870,9 +1460,13 @@ static struct bpf_prog *____bpf_prog_get(struct fd f) return f.file->private_data; } -void bpf_prog_add(struct bpf_prog *prog, int i) +struct bpf_prog *bpf_prog_add(struct bpf_prog *prog, int i) { - atomic64_add(i, &prog->aux->refcnt); + if (atomic_add_return(i, &prog->aux->refcnt) > BPF_MAX_REFCNT) { + atomic_sub(i, &prog->aux->refcnt); + return ERR_PTR(-EBUSY); + } + return prog; } EXPORT_SYMBOL_GPL(bpf_prog_add); @@ -1883,13 +1477,13 @@ void bpf_prog_sub(struct bpf_prog *prog, int i) * path holds a reference to the program, thus atomic_sub() can * be safely used in such cases! */ - WARN_ON(atomic64_sub_return(i, &prog->aux->refcnt) == 0); + WARN_ON(atomic_sub_return(i, &prog->aux->refcnt) == 0); } EXPORT_SYMBOL_GPL(bpf_prog_sub); -void bpf_prog_inc(struct bpf_prog *prog) +struct bpf_prog *bpf_prog_inc(struct bpf_prog *prog) { - atomic64_inc(&prog->aux->refcnt); + return bpf_prog_add(prog, 1); } EXPORT_SYMBOL_GPL(bpf_prog_inc); @@ -1898,7 +1492,12 @@ struct bpf_prog *bpf_prog_inc_not_zero(struct bpf_prog *prog) { int refold; - refold = atomic64_fetch_add_unless(&prog->aux->refcnt, 1, 0); + refold = atomic_fetch_add_unless(&prog->aux->refcnt, 1, 0); + + if (refold >= BPF_MAX_REFCNT) { + __bpf_prog_put(prog, false); + return ERR_PTR(-EBUSY); + } if (!refold) return ERR_PTR(-ENOENT); @@ -1936,7 +1535,7 @@ static struct bpf_prog *__bpf_prog_get(u32 ufd, enum bpf_prog_type *attach_type, goto out; } - bpf_prog_inc(prog); + prog = bpf_prog_inc(prog); out: fdput(f); return prog; @@ -1981,34 +1580,13 @@ static void bpf_prog_load_fixup_attach_type(union bpf_attr *attr) } static int -bpf_prog_load_check_attach(enum bpf_prog_type prog_type, - enum bpf_attach_type expected_attach_type, - u32 btf_id, u32 prog_fd) +bpf_prog_load_check_attach_type(enum bpf_prog_type prog_type, + enum bpf_attach_type expected_attach_type) { - if (btf_id) { - if (btf_id > BTF_MAX_TYPE) - return -EINVAL; - - switch (prog_type) { - case BPF_PROG_TYPE_TRACING: - case BPF_PROG_TYPE_LSM: - case BPF_PROG_TYPE_STRUCT_OPS: - case BPF_PROG_TYPE_EXT: - break; - default: - return -EINVAL; - } - } - - if (prog_fd && prog_type != BPF_PROG_TYPE_TRACING && - prog_type != BPF_PROG_TYPE_EXT) - return -EINVAL; - switch (prog_type) { case BPF_PROG_TYPE_CGROUP_SOCK: switch (expected_attach_type) { case BPF_CGROUP_INET_SOCK_CREATE: - case BPF_CGROUP_INET_SOCK_RELEASE: case BPF_CGROUP_INET4_POST_BIND: case BPF_CGROUP_INET6_POST_BIND: return 0; @@ -2021,10 +1599,6 @@ bpf_prog_load_check_attach(enum bpf_prog_type prog_type, case BPF_CGROUP_INET6_BIND: case BPF_CGROUP_INET4_CONNECT: case BPF_CGROUP_INET6_CONNECT: - case BPF_CGROUP_INET4_GETPEERNAME: - case BPF_CGROUP_INET6_GETPEERNAME: - case BPF_CGROUP_INET4_GETSOCKNAME: - case BPF_CGROUP_INET6_GETSOCKNAME: case BPF_CGROUP_UDP4_SENDMSG: case BPF_CGROUP_UDP6_SENDMSG: case BPF_CGROUP_UDP4_RECVMSG: @@ -2049,70 +1623,13 @@ bpf_prog_load_check_attach(enum bpf_prog_type prog_type, default: return -EINVAL; } - case BPF_PROG_TYPE_SK_LOOKUP: - if (expected_attach_type == BPF_SK_LOOKUP) - return 0; - return -EINVAL; - case BPF_PROG_TYPE_EXT: - if (expected_attach_type) - return -EINVAL; - fallthrough; default: return 0; } } -static bool is_net_admin_prog_type(enum bpf_prog_type prog_type) -{ - switch (prog_type) { - case BPF_PROG_TYPE_SCHED_CLS: - case BPF_PROG_TYPE_SCHED_ACT: - case BPF_PROG_TYPE_XDP: - case BPF_PROG_TYPE_LWT_IN: - case BPF_PROG_TYPE_LWT_OUT: - case BPF_PROG_TYPE_LWT_XMIT: - case BPF_PROG_TYPE_LWT_SEG6LOCAL: - case BPF_PROG_TYPE_SK_SKB: - case BPF_PROG_TYPE_SK_MSG: - case BPF_PROG_TYPE_LIRC_MODE2: - case BPF_PROG_TYPE_FLOW_DISSECTOR: - case BPF_PROG_TYPE_CGROUP_DEVICE: - case BPF_PROG_TYPE_CGROUP_SOCK: - case BPF_PROG_TYPE_CGROUP_SOCK_ADDR: - case BPF_PROG_TYPE_CGROUP_SOCKOPT: - case BPF_PROG_TYPE_CGROUP_SYSCTL: - case BPF_PROG_TYPE_SOCK_OPS: - case BPF_PROG_TYPE_EXT: /* extends any prog */ - return true; - case BPF_PROG_TYPE_CGROUP_SKB: - /* always unpriv */ - case BPF_PROG_TYPE_SK_REUSEPORT: - /* equivalent to SOCKET_FILTER. need CAP_BPF only */ - default: - return false; - } -} - -static bool is_perfmon_prog_type(enum bpf_prog_type prog_type) -{ - switch (prog_type) { - case BPF_PROG_TYPE_KPROBE: - case BPF_PROG_TYPE_TRACEPOINT: - case BPF_PROG_TYPE_PERF_EVENT: - case BPF_PROG_TYPE_RAW_TRACEPOINT: - case BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE: - case BPF_PROG_TYPE_TRACING: - case BPF_PROG_TYPE_LSM: - case BPF_PROG_TYPE_STRUCT_OPS: /* has access to struct sock */ - case BPF_PROG_TYPE_EXT: /* extends any prog */ - return true; - default: - return false; - } -} - /* last field in 'union bpf_attr' used by this command */ -#define BPF_PROG_LOAD_LAST_FIELD attach_prog_fd +#define BPF_PROG_LOAD_LAST_FIELD line_info_cnt static int bpf_prog_load(union bpf_attr *attr, union bpf_attr __user *uattr) { @@ -2128,13 +1645,12 @@ static int bpf_prog_load(union bpf_attr *attr, union bpf_attr __user *uattr) if (attr->prog_flags & ~(BPF_F_STRICT_ALIGNMENT | BPF_F_ANY_ALIGNMENT | BPF_F_TEST_STATE_FREQ | - BPF_F_SLEEPABLE | BPF_F_TEST_RND_HI32)) return -EINVAL; if (!IS_ENABLED(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) && (attr->prog_flags & BPF_F_ANY_ALIGNMENT) && - !bpf_capable()) + !capable(CAP_SYS_ADMIN)) return -EPERM; /* copy eBPF program license from user space */ @@ -2147,22 +1663,15 @@ static int bpf_prog_load(union bpf_attr *attr, union bpf_attr __user *uattr) is_gpl = license_is_gpl_compatible(license); if (attr->insn_cnt == 0 || - attr->insn_cnt > (bpf_capable() ? BPF_COMPLEXITY_LIMIT_INSNS : BPF_MAXINSNS)) + attr->insn_cnt > (capable(CAP_SYS_ADMIN) ? BPF_COMPLEXITY_LIMIT_INSNS : BPF_MAXINSNS)) return -E2BIG; if (type != BPF_PROG_TYPE_SOCKET_FILTER && type != BPF_PROG_TYPE_CGROUP_SKB && - !bpf_capable()) - return -EPERM; - - if (is_net_admin_prog_type(type) && !capable(CAP_NET_ADMIN) && !capable(CAP_SYS_ADMIN)) - return -EPERM; - if (is_perfmon_prog_type(type) && !perfmon_capable()) + !capable(CAP_SYS_ADMIN)) return -EPERM; bpf_prog_load_fixup_attach_type(attr); - if (bpf_prog_load_check_attach(type, attr->expected_attach_type, - attr->attach_btf_id, - attr->attach_prog_fd)) + if (bpf_prog_load_check_attach_type(type, attr->expected_attach_type)) return -EINVAL; /* plain bpf_prog allocation */ @@ -2171,20 +1680,8 @@ static int bpf_prog_load(union bpf_attr *attr, union bpf_attr __user *uattr) return -ENOMEM; prog->expected_attach_type = attr->expected_attach_type; - prog->aux->attach_btf_id = attr->attach_btf_id; - if (attr->attach_prog_fd) { - struct bpf_prog *dst_prog; - - dst_prog = bpf_prog_get(attr->attach_prog_fd); - if (IS_ERR(dst_prog)) { - err = PTR_ERR(dst_prog); - goto free_prog_nouncharge; - } - prog->aux->dst_prog = dst_prog; - } prog->aux->offload_requested = !!attr->prog_ifindex; - prog->aux->sleepable = attr->prog_flags & BPF_F_SLEEPABLE; err = security_bpf_prog_alloc(prog->aux); if (err) @@ -2204,7 +1701,7 @@ static int bpf_prog_load(union bpf_attr *attr, union bpf_attr __user *uattr) prog->orig_prog = NULL; prog->jited = 0; - atomic64_set(&prog->aux->refcnt, 1); + atomic_set(&prog->aux->refcnt, 1); prog->gpl_compatible = is_gpl ? 1 : 0; if (bpf_prog_is_dev_bound(prog->aux)) { @@ -2219,9 +1716,8 @@ static int bpf_prog_load(union bpf_attr *attr, union bpf_attr __user *uattr) goto free_prog; prog->aux->load_time = ktime_get_boottime_ns(); - err = bpf_obj_name_cpy(prog->aux->name, attr->prog_name, - sizeof(attr->prog_name)); - if (err < 0) + err = bpf_obj_name_cpy(prog->aux->name, attr->prog_name); + if (err) goto free_prog; /* run eBPF verifier */ @@ -2253,7 +1749,6 @@ static int bpf_prog_load(union bpf_attr *attr, union bpf_attr __user *uattr) */ bpf_prog_kallsyms_add(prog); perf_event_bpf_event(prog, PERF_BPF_EVENT_PROG_LOAD, 0); - bpf_audit_prog(prog, BPF_AUDIT_LOAD); err = bpf_prog_new_fd(prog); if (err < 0) @@ -2296,615 +1791,87 @@ static int bpf_obj_get(const union bpf_attr *attr) attr->file_flags); } -void bpf_link_init(struct bpf_link *link, enum bpf_link_type type, - const struct bpf_link_ops *ops, struct bpf_prog *prog) -{ - atomic64_set(&link->refcnt, 1); - link->type = type; - link->id = 0; - link->ops = ops; - link->prog = prog; -} +struct bpf_raw_tracepoint { + struct bpf_raw_event_map *btp; + struct bpf_prog *prog; +}; -static void bpf_link_free_id(int id) +static int bpf_raw_tracepoint_release(struct inode *inode, struct file *filp) { - if (!id) - return; + struct bpf_raw_tracepoint *raw_tp = filp->private_data; - spin_lock_bh(&link_idr_lock); - idr_remove(&link_idr, id); - spin_unlock_bh(&link_idr_lock); -} - -/* Clean up bpf_link and corresponding anon_inode file and FD. After - * anon_inode is created, bpf_link can't be just kfree()'d due to deferred - * anon_inode's release() call. This helper marksbpf_link as - * defunct, releases anon_inode file and puts reserved FD. bpf_prog's refcnt - * is not decremented, it's the responsibility of a calling code that failed - * to complete bpf_link initialization. - */ -void bpf_link_cleanup(struct bpf_link_primer *primer) -{ - primer->link->prog = NULL; - bpf_link_free_id(primer->id); - fput(primer->file); - put_unused_fd(primer->fd); -} - -void bpf_link_inc(struct bpf_link *link) -{ - atomic64_inc(&link->refcnt); -} - -/* bpf_link_free is guaranteed to be called from process context */ -static void bpf_link_free(struct bpf_link *link) -{ - bpf_link_free_id(link->id); - if (link->prog) { - /* detach BPF program, clean up used resources */ - link->ops->release(link); - bpf_prog_put(link->prog); + if (raw_tp->prog) { + bpf_probe_unregister(raw_tp->btp, raw_tp->prog); + bpf_prog_put(raw_tp->prog); } - /* free bpf_link and its containing memory */ - link->ops->dealloc(link); -} - -static void bpf_link_put_deferred(struct work_struct *work) -{ - struct bpf_link *link = container_of(work, struct bpf_link, work); - - bpf_link_free(link); -} - -/* bpf_link_put can be called from atomic context, but ensures that resources - * are freed from process context - */ -void bpf_link_put(struct bpf_link *link) -{ - if (!atomic64_dec_and_test(&link->refcnt)) - return; - - if (in_atomic()) { - INIT_WORK(&link->work, bpf_link_put_deferred); - schedule_work(&link->work); - } else { - bpf_link_free(link); - } -} - -static int bpf_link_release(struct inode *inode, struct file *filp) -{ - struct bpf_link *link = filp->private_data; - - bpf_link_put(link); + bpf_put_raw_tracepoint(raw_tp->btp); + kfree(raw_tp); return 0; } -#ifdef CONFIG_PROC_FS -#define BPF_PROG_TYPE(_id, _name, prog_ctx_type, kern_ctx_type) -#define BPF_MAP_TYPE(_id, _ops) -#define BPF_LINK_TYPE(_id, _name) [_id] = #_name, -static const char *bpf_link_type_strs[] = { - [BPF_LINK_TYPE_UNSPEC] = "", -#include -}; -#undef BPF_PROG_TYPE -#undef BPF_MAP_TYPE -#undef BPF_LINK_TYPE - -static void bpf_link_show_fdinfo(struct seq_file *m, struct file *filp) -{ - const struct bpf_link *link = filp->private_data; - const struct bpf_prog *prog = link->prog; - enum bpf_link_type type = link->type; - char prog_tag[sizeof(prog->tag) * 2 + 1] = { }; - - if (type < ARRAY_SIZE(bpf_link_type_strs) && bpf_link_type_strs[type]) { - seq_printf(m, "link_type:\t%s\n", bpf_link_type_strs[type]); - } else { - WARN_ONCE(1, "missing BPF_LINK_TYPE(...) for link type %u\n", type); - seq_printf(m, "link_type:\t<%u>\n", type); - } - seq_printf(m, "link_id:\t%u\n", link->id); - - bin2hex(prog_tag, prog->tag, sizeof(prog->tag)); - seq_printf(m, - "prog_tag:\t%s\n" - "prog_id:\t%u\n", - prog_tag, - prog->aux->id); - if (link->ops->show_fdinfo) - link->ops->show_fdinfo(link, m); -} -#endif - -static const struct file_operations bpf_link_fops = { -#ifdef CONFIG_PROC_FS - .show_fdinfo = bpf_link_show_fdinfo, -#endif - .release = bpf_link_release, +static const struct file_operations bpf_raw_tp_fops = { + .release = bpf_raw_tracepoint_release, .read = bpf_dummy_read, .write = bpf_dummy_write, }; -static int bpf_link_alloc_id(struct bpf_link *link) -{ - int id; - - idr_preload(GFP_KERNEL); - spin_lock_bh(&link_idr_lock); - id = idr_alloc_cyclic(&link_idr, link, 1, INT_MAX, GFP_ATOMIC); - spin_unlock_bh(&link_idr_lock); - idr_preload_end(); - - return id; -} - -/* Prepare bpf_link to be exposed to user-space by allocating anon_inode file, - * reserving unused FD and allocating ID from link_idr. This is to be paired - * with bpf_link_settle() to install FD and ID and expose bpf_link to - * user-space, if bpf_link is successfully attached. If not, bpf_link and - * pre-allocated resources are to be freed with bpf_cleanup() call. All the - * transient state is passed around in struct bpf_link_primer. - * This is preferred way to create and initialize bpf_link, especially when - * there are complicated and expensive operations inbetween creating bpf_link - * itself and attaching it to BPF hook. By using bpf_link_prime() and - * bpf_link_settle() kernel code using bpf_link doesn't have to perform - * expensive (and potentially failing) roll back operations in a rare case - * that file, FD, or ID can't be allocated. - */ -int bpf_link_prime(struct bpf_link *link, struct bpf_link_primer *primer) -{ - struct file *file; - int fd, id; - - fd = get_unused_fd_flags(O_CLOEXEC); - if (fd < 0) - return fd; - - - id = bpf_link_alloc_id(link); - if (id < 0) { - put_unused_fd(fd); - return id; - } - - file = anon_inode_getfile("bpf_link", &bpf_link_fops, link, O_CLOEXEC); - if (IS_ERR(file)) { - bpf_link_free_id(id); - put_unused_fd(fd); - return PTR_ERR(file); - } - - primer->link = link; - primer->file = file; - primer->fd = fd; - primer->id = id; - return 0; -} - -int bpf_link_settle(struct bpf_link_primer *primer) -{ - /* make bpf_link fetchable by ID */ - spin_lock_bh(&link_idr_lock); - primer->link->id = primer->id; - spin_unlock_bh(&link_idr_lock); - /* make bpf_link fetchable by FD */ - fd_install(primer->fd, primer->file); - /* pass through installed FD */ - return primer->fd; -} - -int bpf_link_new_fd(struct bpf_link *link) -{ - return anon_inode_getfd("bpf-link", &bpf_link_fops, link, O_CLOEXEC); -} - -struct bpf_link *bpf_link_get_from_fd(u32 ufd) -{ - struct fd f = fdget(ufd); - struct bpf_link *link; - - if (!f.file) - return ERR_PTR(-EBADF); - if (f.file->f_op != &bpf_link_fops) { - fdput(f); - return ERR_PTR(-EINVAL); - } - - link = f.file->private_data; - bpf_link_inc(link); - fdput(f); - - return link; -} - -struct bpf_tracing_link { - struct bpf_link link; - enum bpf_attach_type attach_type; - struct bpf_trampoline *trampoline; - struct bpf_prog *tgt_prog; -}; - -static void bpf_tracing_link_release(struct bpf_link *link) -{ - struct bpf_tracing_link *tr_link = - container_of(link, struct bpf_tracing_link, link); - - WARN_ON_ONCE(bpf_trampoline_unlink_prog(link->prog, - tr_link->trampoline)); - - bpf_trampoline_put(tr_link->trampoline); - - /* tgt_prog is NULL if target is a kernel function */ - if (tr_link->tgt_prog) - bpf_prog_put(tr_link->tgt_prog); -} - -static void bpf_tracing_link_dealloc(struct bpf_link *link) -{ - struct bpf_tracing_link *tr_link = - container_of(link, struct bpf_tracing_link, link); - - kfree(tr_link); -} - -static void bpf_tracing_link_show_fdinfo(const struct bpf_link *link, - struct seq_file *seq) -{ - struct bpf_tracing_link *tr_link = - container_of(link, struct bpf_tracing_link, link); - - seq_printf(seq, - "attach_type:\t%d\n", - tr_link->attach_type); -} - -static int bpf_tracing_link_fill_link_info(const struct bpf_link *link, - struct bpf_link_info *info) -{ - struct bpf_tracing_link *tr_link = - container_of(link, struct bpf_tracing_link, link); - - info->tracing.attach_type = tr_link->attach_type; - - return 0; -} - -static const struct bpf_link_ops bpf_tracing_link_lops = { - .release = bpf_tracing_link_release, - .dealloc = bpf_tracing_link_dealloc, - .show_fdinfo = bpf_tracing_link_show_fdinfo, - .fill_link_info = bpf_tracing_link_fill_link_info, -}; - -static int bpf_tracing_prog_attach(struct bpf_prog *prog, - int tgt_prog_fd, - u32 btf_id) -{ - struct bpf_link_primer link_primer; - struct bpf_prog *tgt_prog = NULL; - struct bpf_trampoline *tr = NULL; - struct bpf_tracing_link *link; - u64 key = 0; - int err; - - switch (prog->type) { - case BPF_PROG_TYPE_TRACING: - if (prog->expected_attach_type != BPF_TRACE_FENTRY && - prog->expected_attach_type != BPF_TRACE_FEXIT && - prog->expected_attach_type != BPF_MODIFY_RETURN) { - err = -EINVAL; - goto out_put_prog; - } - break; - case BPF_PROG_TYPE_EXT: - if (prog->expected_attach_type != 0) { - err = -EINVAL; - goto out_put_prog; - } - break; - case BPF_PROG_TYPE_LSM: - if (prog->expected_attach_type != BPF_LSM_MAC) { - err = -EINVAL; - goto out_put_prog; - } - break; - default: - err = -EINVAL; - goto out_put_prog; - } - - if (!!tgt_prog_fd != !!btf_id) { - err = -EINVAL; - goto out_put_prog; - } - - if (tgt_prog_fd) { - /* For now we only allow new targets for BPF_PROG_TYPE_EXT */ - if (prog->type != BPF_PROG_TYPE_EXT) { - err = -EINVAL; - goto out_put_prog; - } - - tgt_prog = bpf_prog_get(tgt_prog_fd); - if (IS_ERR(tgt_prog)) { - err = PTR_ERR(tgt_prog); - tgt_prog = NULL; - goto out_put_prog; - } - - key = bpf_trampoline_compute_key(tgt_prog, btf_id); - } - - link = kzalloc(sizeof(*link), GFP_USER); - if (!link) { - err = -ENOMEM; - goto out_put_prog; - } - bpf_link_init(&link->link, BPF_LINK_TYPE_TRACING, - &bpf_tracing_link_lops, prog); - link->attach_type = prog->expected_attach_type; - - mutex_lock(&prog->aux->dst_mutex); - - /* There are a few possible cases here: - * - * - if prog->aux->dst_trampoline is set, the program was just loaded - * and not yet attached to anything, so we can use the values stored - * in prog->aux - * - * - if prog->aux->dst_trampoline is NULL, the program has already been - * attached to a target and its initial target was cleared (below) - * - * - if tgt_prog != NULL, the caller specified tgt_prog_fd + - * target_btf_id using the link_create API. - * - * - if tgt_prog == NULL when this function was called using the old - * raw_tracepoint_open API, and we need a target from prog->aux - * - * The combination of no saved target in prog->aux, and no target - * specified on load is illegal, and we reject that here. - */ - if (!prog->aux->dst_trampoline && !tgt_prog) { - err = -ENOENT; - goto out_unlock; - } - - if (!prog->aux->dst_trampoline || - (key && key != prog->aux->dst_trampoline->key)) { - /* If there is no saved target, or the specified target is - * different from the destination specified at load time, we - * need a new trampoline and a check for compatibility - */ - struct bpf_attach_target_info tgt_info = {}; - - err = bpf_check_attach_target(NULL, prog, tgt_prog, btf_id, - &tgt_info); - if (err) - goto out_unlock; - - tr = bpf_trampoline_get(key, &tgt_info); - if (!tr) { - err = -ENOMEM; - goto out_unlock; - } - } else { - /* The caller didn't specify a target, or the target was the - * same as the destination supplied during program load. This - * means we can reuse the trampoline and reference from program - * load time, and there is no need to allocate a new one. This - * can only happen once for any program, as the saved values in - * prog->aux are cleared below. - */ - tr = prog->aux->dst_trampoline; - tgt_prog = prog->aux->dst_prog; - } - - err = bpf_link_prime(&link->link, &link_primer); - if (err) - goto out_unlock; - - err = bpf_trampoline_link_prog(prog, tr); - if (err) { - bpf_link_cleanup(&link_primer); - link = NULL; - goto out_unlock; - } - - link->tgt_prog = tgt_prog; - link->trampoline = tr; - - /* Always clear the trampoline and target prog from prog->aux to make - * sure the original attach destination is not kept alive after a - * program is (re-)attached to another target. - */ - if (prog->aux->dst_prog && - (tgt_prog_fd || tr != prog->aux->dst_trampoline)) - /* got extra prog ref from syscall, or attaching to different prog */ - bpf_prog_put(prog->aux->dst_prog); - if (prog->aux->dst_trampoline && tr != prog->aux->dst_trampoline) - /* we allocated a new trampoline, so free the old one */ - bpf_trampoline_put(prog->aux->dst_trampoline); - - prog->aux->dst_prog = NULL; - prog->aux->dst_trampoline = NULL; - mutex_unlock(&prog->aux->dst_mutex); - - return bpf_link_settle(&link_primer); -out_unlock: - if (tr && tr != prog->aux->dst_trampoline) - bpf_trampoline_put(tr); - mutex_unlock(&prog->aux->dst_mutex); - kfree(link); -out_put_prog: - if (tgt_prog_fd && tgt_prog) - bpf_prog_put(tgt_prog); - return err; -} - -struct bpf_raw_tp_link { - struct bpf_link link; - struct bpf_raw_event_map *btp; -}; - -static void bpf_raw_tp_link_release(struct bpf_link *link) -{ - struct bpf_raw_tp_link *raw_tp = - container_of(link, struct bpf_raw_tp_link, link); - - bpf_probe_unregister(raw_tp->btp, raw_tp->link.prog); - bpf_put_raw_tracepoint(raw_tp->btp); -} - -static void bpf_raw_tp_link_dealloc(struct bpf_link *link) -{ - struct bpf_raw_tp_link *raw_tp = - container_of(link, struct bpf_raw_tp_link, link); - - kfree(raw_tp); -} - -static void bpf_raw_tp_link_show_fdinfo(const struct bpf_link *link, - struct seq_file *seq) -{ - struct bpf_raw_tp_link *raw_tp_link = - container_of(link, struct bpf_raw_tp_link, link); - - seq_printf(seq, - "tp_name:\t%s\n", - raw_tp_link->btp->tp->name); -} - -static int bpf_raw_tp_link_fill_link_info(const struct bpf_link *link, - struct bpf_link_info *info) -{ - struct bpf_raw_tp_link *raw_tp_link = - container_of(link, struct bpf_raw_tp_link, link); - char __user *ubuf = u64_to_user_ptr(info->raw_tracepoint.tp_name); - const char *tp_name = raw_tp_link->btp->tp->name; - u32 ulen = info->raw_tracepoint.tp_name_len; - size_t tp_len = strlen(tp_name); - - if (!ulen ^ !ubuf) - return -EINVAL; - - info->raw_tracepoint.tp_name_len = tp_len + 1; - - if (!ubuf) - return 0; - - if (ulen >= tp_len + 1) { - if (copy_to_user(ubuf, tp_name, tp_len + 1)) - return -EFAULT; - } else { - char zero = '\0'; - - if (copy_to_user(ubuf, tp_name, ulen - 1)) - return -EFAULT; - if (put_user(zero, ubuf + ulen - 1)) - return -EFAULT; - return -ENOSPC; - } - - return 0; -} - -static const struct bpf_link_ops bpf_raw_tp_link_lops = { - .release = bpf_raw_tp_link_release, - .dealloc = bpf_raw_tp_link_dealloc, - .show_fdinfo = bpf_raw_tp_link_show_fdinfo, - .fill_link_info = bpf_raw_tp_link_fill_link_info, -}; - #define BPF_RAW_TRACEPOINT_OPEN_LAST_FIELD raw_tracepoint.prog_fd static int bpf_raw_tracepoint_open(const union bpf_attr *attr) { - struct bpf_link_primer link_primer; - struct bpf_raw_tp_link *link; + struct bpf_raw_tracepoint *raw_tp; struct bpf_raw_event_map *btp; struct bpf_prog *prog; - const char *tp_name; - char buf[128]; - int err; + char tp_name[128]; + int tp_fd, err; - if (CHECK_ATTR(BPF_RAW_TRACEPOINT_OPEN)) - return -EINVAL; + if (strncpy_from_user(tp_name, u64_to_user_ptr(attr->raw_tracepoint.name), + sizeof(tp_name) - 1) < 0) + return -EFAULT; + tp_name[sizeof(tp_name) - 1] = 0; + + btp = bpf_get_raw_tracepoint(tp_name); + if (!btp) + return -ENOENT; + + raw_tp = kzalloc(sizeof(*raw_tp), GFP_USER); + if (!raw_tp) { + err = -ENOMEM; + goto out_put_btp; + } + raw_tp->btp = btp; prog = bpf_prog_get(attr->raw_tracepoint.prog_fd); - if (IS_ERR(prog)) - return PTR_ERR(prog); - - switch (prog->type) { - case BPF_PROG_TYPE_TRACING: - case BPF_PROG_TYPE_EXT: - case BPF_PROG_TYPE_LSM: - if (attr->raw_tracepoint.name) { - /* The attach point for this category of programs - * should be specified via btf_id during program load. - */ - err = -EINVAL; - goto out_put_prog; - } - if (prog->type == BPF_PROG_TYPE_TRACING && - prog->expected_attach_type == BPF_TRACE_RAW_TP) { - tp_name = prog->aux->attach_func_name; - break; - } - err = bpf_tracing_prog_attach(prog, 0, 0); - if (err >= 0) - return err; - goto out_put_prog; - case BPF_PROG_TYPE_RAW_TRACEPOINT: - case BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE: - if (strncpy_from_user(buf, - u64_to_user_ptr(attr->raw_tracepoint.name), - sizeof(buf) - 1) < 0) { - err = -EFAULT; - goto out_put_prog; - } - buf[sizeof(buf) - 1] = 0; - tp_name = buf; - break; - default: + if (IS_ERR(prog)) { + err = PTR_ERR(prog); + goto out_free_tp; + } + if (prog->type != BPF_PROG_TYPE_RAW_TRACEPOINT && + prog->type != BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE) { err = -EINVAL; goto out_put_prog; } - btp = bpf_get_raw_tracepoint(tp_name); - if (!btp) { - err = -ENOENT; + err = bpf_probe_register(raw_tp->btp, prog); + if (err) + goto out_put_prog; + + raw_tp->prog = prog; + tp_fd = anon_inode_getfd("bpf-raw-tracepoint", &bpf_raw_tp_fops, raw_tp, + O_CLOEXEC); + if (tp_fd < 0) { + bpf_probe_unregister(raw_tp->btp, prog); + err = tp_fd; goto out_put_prog; } + return tp_fd; - link = kzalloc(sizeof(*link), GFP_USER); - if (!link) { - err = -ENOMEM; - goto out_put_btp; - } - bpf_link_init(&link->link, BPF_LINK_TYPE_RAW_TRACEPOINT, - &bpf_raw_tp_link_lops, prog); - link->btp = btp; - - err = bpf_link_prime(&link->link, &link_primer); - if (err) { - kfree(link); - goto out_put_btp; - } - - err = bpf_probe_register(link->btp, prog); - if (err) { - bpf_link_cleanup(&link_primer); - goto out_put_btp; - } - - return bpf_link_settle(&link_primer); - -out_put_btp: - bpf_put_raw_tracepoint(btp); out_put_prog: bpf_prog_put(prog); +out_free_tp: + kfree(raw_tp); +out_put_btp: + bpf_put_raw_tracepoint(btp); return err; } @@ -2915,14 +1882,8 @@ static int bpf_prog_attach_check_attach_type(const struct bpf_prog *prog, case BPF_PROG_TYPE_CGROUP_SOCK: case BPF_PROG_TYPE_CGROUP_SOCK_ADDR: case BPF_PROG_TYPE_CGROUP_SOCKOPT: - case BPF_PROG_TYPE_SK_LOOKUP: return attach_type == prog->expected_attach_type ? 0 : -EINVAL; case BPF_PROG_TYPE_CGROUP_SKB: - if (!capable(CAP_NET_ADMIN)) - /* cg-skb progs can be loaded by unpriv user. - * check permissions at attach time. - */ - return -EPERM; return prog->enforce_expected_attach_type && prog->expected_attach_type != attach_type ? -EINVAL : 0; @@ -2931,64 +1892,10 @@ static int bpf_prog_attach_check_attach_type(const struct bpf_prog *prog, } } -static enum bpf_prog_type -attach_type_to_prog_type(enum bpf_attach_type attach_type) -{ - switch (attach_type) { - case BPF_CGROUP_INET_INGRESS: - case BPF_CGROUP_INET_EGRESS: - return BPF_PROG_TYPE_CGROUP_SKB; - case BPF_CGROUP_INET_SOCK_CREATE: - case BPF_CGROUP_INET_SOCK_RELEASE: - case BPF_CGROUP_INET4_POST_BIND: - case BPF_CGROUP_INET6_POST_BIND: - return BPF_PROG_TYPE_CGROUP_SOCK; - case BPF_CGROUP_INET4_BIND: - case BPF_CGROUP_INET6_BIND: - case BPF_CGROUP_INET4_CONNECT: - case BPF_CGROUP_INET6_CONNECT: - case BPF_CGROUP_INET4_GETPEERNAME: - case BPF_CGROUP_INET6_GETPEERNAME: - case BPF_CGROUP_INET4_GETSOCKNAME: - case BPF_CGROUP_INET6_GETSOCKNAME: - case BPF_CGROUP_UDP4_SENDMSG: - case BPF_CGROUP_UDP6_SENDMSG: - case BPF_CGROUP_UDP4_RECVMSG: - case BPF_CGROUP_UDP6_RECVMSG: - return BPF_PROG_TYPE_CGROUP_SOCK_ADDR; - case BPF_CGROUP_SOCK_OPS: - return BPF_PROG_TYPE_SOCK_OPS; - case BPF_CGROUP_DEVICE: - return BPF_PROG_TYPE_CGROUP_DEVICE; - case BPF_SK_MSG_VERDICT: - return BPF_PROG_TYPE_SK_MSG; - case BPF_SK_SKB_STREAM_PARSER: - case BPF_SK_SKB_STREAM_VERDICT: - return BPF_PROG_TYPE_SK_SKB; - case BPF_LIRC_MODE2: - return BPF_PROG_TYPE_LIRC_MODE2; - case BPF_FLOW_DISSECTOR: - return BPF_PROG_TYPE_FLOW_DISSECTOR; - case BPF_CGROUP_SYSCTL: - return BPF_PROG_TYPE_CGROUP_SYSCTL; - case BPF_CGROUP_GETSOCKOPT: - case BPF_CGROUP_SETSOCKOPT: - return BPF_PROG_TYPE_CGROUP_SOCKOPT; - case BPF_TRACE_ITER: - return BPF_PROG_TYPE_TRACING; - case BPF_SK_LOOKUP: - return BPF_PROG_TYPE_SK_LOOKUP; - case BPF_XDP: - return BPF_PROG_TYPE_XDP; - default: - return BPF_PROG_TYPE_UNSPEC; - } -} - -#define BPF_PROG_ATTACH_LAST_FIELD replace_bpf_fd +#define BPF_PROG_ATTACH_LAST_FIELD attach_flags #define BPF_F_ATTACH_MASK \ - (BPF_F_ALLOW_OVERRIDE | BPF_F_ALLOW_MULTI | BPF_F_REPLACE) + (BPF_F_ALLOW_OVERRIDE | BPF_F_ALLOW_MULTI) static int bpf_prog_attach(const union bpf_attr *attr) { @@ -2996,15 +1903,64 @@ static int bpf_prog_attach(const union bpf_attr *attr) struct bpf_prog *prog; int ret; + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + if (CHECK_ATTR(BPF_PROG_ATTACH)) return -EINVAL; if (attr->attach_flags & ~BPF_F_ATTACH_MASK) return -EINVAL; - ptype = attach_type_to_prog_type(attr->attach_type); - if (ptype == BPF_PROG_TYPE_UNSPEC) + switch (attr->attach_type) { + case BPF_CGROUP_INET_INGRESS: + case BPF_CGROUP_INET_EGRESS: + ptype = BPF_PROG_TYPE_CGROUP_SKB; + break; + case BPF_CGROUP_INET_SOCK_CREATE: + case BPF_CGROUP_INET4_POST_BIND: + case BPF_CGROUP_INET6_POST_BIND: + ptype = BPF_PROG_TYPE_CGROUP_SOCK; + break; + case BPF_CGROUP_INET4_BIND: + case BPF_CGROUP_INET6_BIND: + case BPF_CGROUP_INET4_CONNECT: + case BPF_CGROUP_INET6_CONNECT: + case BPF_CGROUP_UDP4_SENDMSG: + case BPF_CGROUP_UDP6_SENDMSG: + case BPF_CGROUP_UDP4_RECVMSG: + case BPF_CGROUP_UDP6_RECVMSG: + ptype = BPF_PROG_TYPE_CGROUP_SOCK_ADDR; + break; + case BPF_CGROUP_SOCK_OPS: + ptype = BPF_PROG_TYPE_SOCK_OPS; + break; + case BPF_CGROUP_DEVICE: + ptype = BPF_PROG_TYPE_CGROUP_DEVICE; + break; + case BPF_SK_MSG_VERDICT: + ptype = BPF_PROG_TYPE_SK_MSG; + break; + case BPF_SK_SKB_STREAM_PARSER: + case BPF_SK_SKB_STREAM_VERDICT: + ptype = BPF_PROG_TYPE_SK_SKB; + break; + case BPF_LIRC_MODE2: + ptype = BPF_PROG_TYPE_LIRC_MODE2; + break; + case BPF_FLOW_DISSECTOR: + ptype = BPF_PROG_TYPE_FLOW_DISSECTOR; + break; + case BPF_CGROUP_SYSCTL: + ptype = BPF_PROG_TYPE_CGROUP_SYSCTL; + break; + case BPF_CGROUP_GETSOCKOPT: + case BPF_CGROUP_SETSOCKOPT: + ptype = BPF_PROG_TYPE_CGROUP_SOCKOPT; + break; + default: return -EINVAL; + } prog = bpf_prog_get_type(attr->attach_bpf_fd, ptype); if (IS_ERR(prog)) @@ -3024,19 +1980,10 @@ static int bpf_prog_attach(const union bpf_attr *attr) ret = lirc_prog_attach(attr, prog); break; case BPF_PROG_TYPE_FLOW_DISSECTOR: - ret = netns_bpf_prog_attach(attr, prog); - break; - case BPF_PROG_TYPE_CGROUP_DEVICE: - case BPF_PROG_TYPE_CGROUP_SKB: - case BPF_PROG_TYPE_CGROUP_SOCK: - case BPF_PROG_TYPE_CGROUP_SOCK_ADDR: - case BPF_PROG_TYPE_CGROUP_SOCKOPT: - case BPF_PROG_TYPE_CGROUP_SYSCTL: - case BPF_PROG_TYPE_SOCK_OPS: - ret = cgroup_bpf_prog_attach(attr, ptype, prog); + ret = skb_flow_dissector_bpf_prog_attach(attr, prog); break; default: - ret = -EINVAL; + ret = cgroup_bpf_prog_attach(attr, ptype, prog); } if (ret) @@ -3050,30 +1997,59 @@ static int bpf_prog_detach(const union bpf_attr *attr) { enum bpf_prog_type ptype; + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + if (CHECK_ATTR(BPF_PROG_DETACH)) return -EINVAL; - ptype = attach_type_to_prog_type(attr->attach_type); - - switch (ptype) { - case BPF_PROG_TYPE_SK_MSG: - case BPF_PROG_TYPE_SK_SKB: - return sock_map_get_from_fd(attr, NULL); - case BPF_PROG_TYPE_LIRC_MODE2: + switch (attr->attach_type) { + case BPF_CGROUP_INET_INGRESS: + case BPF_CGROUP_INET_EGRESS: + ptype = BPF_PROG_TYPE_CGROUP_SKB; + break; + case BPF_CGROUP_INET_SOCK_CREATE: + case BPF_CGROUP_INET4_POST_BIND: + case BPF_CGROUP_INET6_POST_BIND: + ptype = BPF_PROG_TYPE_CGROUP_SOCK; + break; + case BPF_CGROUP_INET4_BIND: + case BPF_CGROUP_INET6_BIND: + case BPF_CGROUP_INET4_CONNECT: + case BPF_CGROUP_INET6_CONNECT: + case BPF_CGROUP_UDP4_SENDMSG: + case BPF_CGROUP_UDP6_SENDMSG: + case BPF_CGROUP_UDP4_RECVMSG: + case BPF_CGROUP_UDP6_RECVMSG: + ptype = BPF_PROG_TYPE_CGROUP_SOCK_ADDR; + break; + case BPF_CGROUP_SOCK_OPS: + ptype = BPF_PROG_TYPE_SOCK_OPS; + break; + case BPF_CGROUP_DEVICE: + ptype = BPF_PROG_TYPE_CGROUP_DEVICE; + break; + case BPF_SK_MSG_VERDICT: + return sock_map_prog_detach(attr, BPF_PROG_TYPE_SK_MSG); + case BPF_SK_SKB_STREAM_PARSER: + case BPF_SK_SKB_STREAM_VERDICT: + return sock_map_prog_detach(attr, BPF_PROG_TYPE_SK_SKB); + case BPF_LIRC_MODE2: return lirc_prog_detach(attr); - case BPF_PROG_TYPE_FLOW_DISSECTOR: - return netns_bpf_prog_detach(attr, ptype); - case BPF_PROG_TYPE_CGROUP_DEVICE: - case BPF_PROG_TYPE_CGROUP_SKB: - case BPF_PROG_TYPE_CGROUP_SOCK: - case BPF_PROG_TYPE_CGROUP_SOCK_ADDR: - case BPF_PROG_TYPE_CGROUP_SOCKOPT: - case BPF_PROG_TYPE_CGROUP_SYSCTL: - case BPF_PROG_TYPE_SOCK_OPS: - return cgroup_bpf_prog_detach(attr, ptype); + case BPF_FLOW_DISSECTOR: + return skb_flow_dissector_bpf_prog_detach(attr); + case BPF_CGROUP_SYSCTL: + ptype = BPF_PROG_TYPE_CGROUP_SYSCTL; + break; + case BPF_CGROUP_GETSOCKOPT: + case BPF_CGROUP_SETSOCKOPT: + ptype = BPF_PROG_TYPE_CGROUP_SOCKOPT; + break; default: return -EINVAL; } + + return cgroup_bpf_prog_detach(attr, ptype); } #define BPF_PROG_QUERY_LAST_FIELD query.prog_cnt @@ -3092,17 +2068,12 @@ static int bpf_prog_query(const union bpf_attr *attr, case BPF_CGROUP_INET_INGRESS: case BPF_CGROUP_INET_EGRESS: case BPF_CGROUP_INET_SOCK_CREATE: - case BPF_CGROUP_INET_SOCK_RELEASE: case BPF_CGROUP_INET4_BIND: case BPF_CGROUP_INET6_BIND: case BPF_CGROUP_INET4_POST_BIND: case BPF_CGROUP_INET6_POST_BIND: case BPF_CGROUP_INET4_CONNECT: case BPF_CGROUP_INET6_CONNECT: - case BPF_CGROUP_INET4_GETPEERNAME: - case BPF_CGROUP_INET6_GETPEERNAME: - case BPF_CGROUP_INET4_GETSOCKNAME: - case BPF_CGROUP_INET6_GETSOCKNAME: case BPF_CGROUP_UDP4_SENDMSG: case BPF_CGROUP_UDP6_SENDMSG: case BPF_CGROUP_UDP4_RECVMSG: @@ -3112,18 +2083,19 @@ static int bpf_prog_query(const union bpf_attr *attr, case BPF_CGROUP_SYSCTL: case BPF_CGROUP_GETSOCKOPT: case BPF_CGROUP_SETSOCKOPT: - return cgroup_bpf_prog_query(attr, uattr); + break; case BPF_LIRC_MODE2: return lirc_prog_query(attr, uattr); case BPF_FLOW_DISSECTOR: - case BPF_SK_LOOKUP: - return netns_bpf_prog_query(attr, uattr); + return skb_flow_dissector_prog_query(attr, uattr); default: return -EINVAL; } + + return cgroup_bpf_prog_query(attr, uattr); } -#define BPF_PROG_TEST_RUN_LAST_FIELD test.cpu +#define BPF_PROG_TEST_RUN_LAST_FIELD test.ctx_out static int bpf_prog_test_run(const union bpf_attr *attr, union bpf_attr __user *uattr) @@ -3131,6 +2103,8 @@ static int bpf_prog_test_run(const union bpf_attr *attr, struct bpf_prog *prog; int ret = -ENOTSUPP; + if (!capable(CAP_SYS_ADMIN)) + return -EPERM; if (CHECK_ATTR(BPF_PROG_TEST_RUN)) return -EINVAL; @@ -3181,63 +2155,8 @@ static int bpf_obj_get_next_id(const union bpf_attr *attr, return err; } -struct bpf_map *bpf_map_get_curr_or_next(u32 *id) -{ - struct bpf_map *map; - - spin_lock_bh(&map_idr_lock); -again: - map = idr_get_next(&map_idr, id); - if (map) { - map = __bpf_map_inc_not_zero(map, false); - if (IS_ERR(map)) { - (*id)++; - goto again; - } - } - spin_unlock_bh(&map_idr_lock); - - return map; -} - -struct bpf_prog *bpf_prog_get_curr_or_next(u32 *id) -{ - struct bpf_prog *prog; - - spin_lock_bh(&prog_idr_lock); -again: - prog = idr_get_next(&prog_idr, id); - if (prog) { - prog = bpf_prog_inc_not_zero(prog); - if (IS_ERR(prog)) { - (*id)++; - goto again; - } - } - spin_unlock_bh(&prog_idr_lock); - - return prog; -} - #define BPF_PROG_GET_FD_BY_ID_LAST_FIELD prog_id -struct bpf_prog *bpf_prog_by_id(u32 id) -{ - struct bpf_prog *prog; - - if (!id) - return ERR_PTR(-ENOENT); - - spin_lock_bh(&prog_idr_lock); - prog = idr_find(&prog_idr, id); - if (prog) - prog = bpf_prog_inc_not_zero(prog); - else - prog = ERR_PTR(-ENOENT); - spin_unlock_bh(&prog_idr_lock); - return prog; -} - static int bpf_prog_get_fd_by_id(const union bpf_attr *attr) { struct bpf_prog *prog; @@ -3250,7 +2169,14 @@ static int bpf_prog_get_fd_by_id(const union bpf_attr *attr) if (!capable(CAP_SYS_ADMIN)) return -EPERM; - prog = bpf_prog_by_id(id); + spin_lock_bh(&prog_idr_lock); + prog = idr_find(&prog_idr, id); + if (prog) + prog = bpf_prog_inc_not_zero(prog); + else + prog = ERR_PTR(-ENOENT); + spin_unlock_bh(&prog_idr_lock); + if (IS_ERR(prog)) return PTR_ERR(prog); @@ -3306,25 +2232,21 @@ static const struct bpf_map *bpf_map_from_imm(const struct bpf_prog *prog, const struct bpf_map *map; int i; - mutex_lock(&prog->aux->used_maps_mutex); for (i = 0, *off = 0; i < prog->aux->used_map_cnt; i++) { map = prog->aux->used_maps[i]; if (map == (void *)addr) { *type = BPF_PSEUDO_MAP_FD; - goto out; + return map; } if (!map->ops->map_direct_value_meta) continue; if (!map->ops->map_direct_value_meta(map, addr, off)) { *type = BPF_PSEUDO_MAP_VALUE; - goto out; + return map; } } - map = NULL; -out: - mutex_unlock(&prog->aux->used_maps_mutex); - return map; + return NULL; } static struct bpf_insn *bpf_insn_prepare_dump(const struct bpf_prog *prog, @@ -3334,7 +2256,6 @@ static struct bpf_insn *bpf_insn_prepare_dump(const struct bpf_prog *prog, struct bpf_insn *insns; u32 off, type; u64 imm; - u8 code; int i; insns = kmemdup(prog->insnsi, bpf_prog_insn_size(prog), @@ -3343,27 +2264,21 @@ static struct bpf_insn *bpf_insn_prepare_dump(const struct bpf_prog *prog, return insns; for (i = 0; i < prog->len; i++) { - code = insns[i].code; - - if (code == (BPF_JMP | BPF_TAIL_CALL)) { + if (insns[i].code == (BPF_JMP | BPF_TAIL_CALL)) { insns[i].code = BPF_JMP | BPF_CALL; insns[i].imm = BPF_FUNC_tail_call; /* fall-through */ } - if (code == (BPF_JMP | BPF_CALL) || - code == (BPF_JMP | BPF_CALL_ARGS)) { - if (code == (BPF_JMP | BPF_CALL_ARGS)) + if (insns[i].code == (BPF_JMP | BPF_CALL) || + insns[i].code == (BPF_JMP | BPF_CALL_ARGS)) { + if (insns[i].code == (BPF_JMP | BPF_CALL_ARGS)) insns[i].code = BPF_JMP | BPF_CALL; if (!bpf_dump_raw_ok(f_cred)) insns[i].imm = 0; continue; } - if (BPF_CLASS(code) == BPF_LDX && BPF_MODE(code) == BPF_PROBE_MEM) { - insns[i].code = BPF_LDX | BPF_SIZE(code) | BPF_MEM; - continue; - } - if (code != (BPF_LD | BPF_IMM | BPF_DW)) + if (insns[i].code != (BPF_LD | BPF_IMM | BPF_DW)) continue; imm = ((u64)insns[i + 1].imm << 32) | (u32)insns[i].imm; @@ -3442,7 +2357,6 @@ static int bpf_prog_get_info_by_fd(struct file *file, memcpy(info.tag, prog->tag, sizeof(prog->tag)); memcpy(info.name, prog->aux->name, sizeof(prog->aux->name)); - mutex_lock(&prog->aux->used_maps_mutex); ulen = info.nr_map_ids; info.nr_map_ids = prog->aux->used_map_cnt; ulen = min_t(u32, info.nr_map_ids, ulen); @@ -3452,12 +2366,9 @@ static int bpf_prog_get_info_by_fd(struct file *file, for (i = 0; i < ulen; i++) if (put_user(prog->aux->used_maps[i]->id, - &user_map_ids[i])) { - mutex_unlock(&prog->aux->used_maps_mutex); + &user_map_ids[i])) return -EFAULT; - } } - mutex_unlock(&prog->aux->used_maps_mutex); err = set_info_rec_size(&info); if (err) @@ -3467,7 +2378,7 @@ static int bpf_prog_get_info_by_fd(struct file *file, info.run_time_ns = stats.nsecs; info.run_cnt = stats.cnt; - if (!bpf_capable()) { + if (!capable(CAP_SYS_ADMIN)) { info.jited_prog_len = 0; info.xlated_prog_len = 0; info.nr_jited_ksyms = 0; @@ -3720,7 +2631,6 @@ static int bpf_map_get_info_by_fd(struct file *file, info.btf_key_type_id = map->btf_key_type_id; info.btf_value_type_id = map->btf_value_type_id; } - info.btf_vmlinux_value_type_id = map->btf_vmlinux_value_type_id; if (bpf_map_is_dev_bound(map)) { err = bpf_map_offload_info_fill(&info, map); @@ -3751,43 +2661,6 @@ static int bpf_btf_get_info_by_fd(struct file *file, return btf_get_info_by_fd(btf, attr, uattr); } -static int bpf_link_get_info_by_fd(struct file *file, - struct bpf_link *link, - const union bpf_attr *attr, - union bpf_attr __user *uattr) -{ - struct bpf_link_info __user *uinfo = u64_to_user_ptr(attr->info.info); - struct bpf_link_info info; - u32 info_len = attr->info.info_len; - int err; - - err = bpf_check_uarg_tail_zero(uinfo, sizeof(info), info_len); - if (err) - return err; - info_len = min_t(u32, sizeof(info), info_len); - - memset(&info, 0, sizeof(info)); - if (copy_from_user(&info, uinfo, info_len)) - return -EFAULT; - - info.type = link->type; - info.id = link->id; - info.prog_id = link->prog->aux->id; - - if (link->ops->fill_link_info) { - err = link->ops->fill_link_info(link, &info); - if (err) - return err; - } - - if (copy_to_user(uinfo, &info, info_len) || - put_user(info_len, &uattr->info.info_len)) - return -EFAULT; - - return 0; -} - - #define BPF_OBJ_GET_INFO_BY_FD_LAST_FIELD info.info static int bpf_obj_get_info_by_fd(const union bpf_attr *attr, @@ -3812,9 +2685,6 @@ static int bpf_obj_get_info_by_fd(const union bpf_attr *attr, uattr); else if (f.file->f_op == &btf_fops) err = bpf_btf_get_info_by_fd(f.file, f.file->private_data, attr, uattr); - else if (f.file->f_op == &bpf_link_fops) - err = bpf_link_get_info_by_fd(f.file, f.file->private_data, - attr, uattr); else err = -EINVAL; @@ -3829,7 +2699,7 @@ static int bpf_btf_load(const union bpf_attr *attr) if (CHECK_ATTR(BPF_BTF_LOAD)) return -EINVAL; - if (!bpf_capable()) + if (!capable(CAP_SYS_ADMIN)) return -EPERM; return btf_new_fd(attr); @@ -3941,21 +2811,15 @@ static int bpf_task_fd_query(const union bpf_attr *attr, if (err) goto out; - if (file->f_op == &bpf_link_fops) { - struct bpf_link *link = file->private_data; + if (file->f_op == &bpf_raw_tp_fops) { + struct bpf_raw_tracepoint *raw_tp = file->private_data; + struct bpf_raw_event_map *btp = raw_tp->btp; - if (link->ops == &bpf_raw_tp_link_lops) { - struct bpf_raw_tp_link *raw_tp = - container_of(link, struct bpf_raw_tp_link, link); - struct bpf_raw_event_map *btp = raw_tp->btp; - - err = bpf_task_fd_query_copy(attr, uattr, - raw_tp->link.prog->aux->id, - BPF_FD_TYPE_RAW_TRACEPOINT, - btp->tp->name, 0, 0); - goto put_file; - } - goto out_not_supp; + err = bpf_task_fd_query_copy(attr, uattr, + raw_tp->prog->aux->id, + BPF_FD_TYPE_RAW_TRACEPOINT, + btp->tp->name, 0, 0); + goto put_file; } event = perf_get_event(file); @@ -3975,7 +2839,6 @@ static int bpf_task_fd_query(const union bpf_attr *attr, goto put_file; } -out_not_supp: err = -ENOTSUPP; put_file: fput(file); @@ -3983,411 +2846,12 @@ out: return err; } -#define BPF_MAP_BATCH_LAST_FIELD batch.flags - -#define BPF_DO_BATCH(fn) \ - do { \ - if (!fn) { \ - err = -ENOTSUPP; \ - goto err_put; \ - } \ - err = fn(map, attr, uattr); \ - } while (0) - -static int bpf_map_do_batch(const union bpf_attr *attr, - union bpf_attr __user *uattr, - int cmd) -{ - bool has_read = cmd == BPF_MAP_LOOKUP_BATCH || - cmd == BPF_MAP_LOOKUP_AND_DELETE_BATCH; - bool has_write = cmd != BPF_MAP_LOOKUP_BATCH; - struct bpf_map *map; - int err, ufd; - struct fd f; - - if (CHECK_ATTR(BPF_MAP_BATCH)) - return -EINVAL; - - ufd = attr->batch.map_fd; - f = fdget(ufd); - map = __bpf_map_get(f); - if (IS_ERR(map)) - return PTR_ERR(map); - if (has_write) - bpf_map_write_active_inc(map); - if (has_read && !(map_get_sys_perms(map, f) & FMODE_CAN_READ)) { - err = -EPERM; - goto err_put; - } - if (has_write && !(map_get_sys_perms(map, f) & FMODE_CAN_WRITE)) { - err = -EPERM; - goto err_put; - } - - if (cmd == BPF_MAP_LOOKUP_BATCH) - BPF_DO_BATCH(map->ops->map_lookup_batch); - else if (cmd == BPF_MAP_LOOKUP_AND_DELETE_BATCH) - BPF_DO_BATCH(map->ops->map_lookup_and_delete_batch); - else if (cmd == BPF_MAP_UPDATE_BATCH) - BPF_DO_BATCH(map->ops->map_update_batch); - else - BPF_DO_BATCH(map->ops->map_delete_batch); -err_put: - if (has_write) - bpf_map_write_active_dec(map); - fdput(f); - return err; -} - -static int tracing_bpf_link_attach(const union bpf_attr *attr, struct bpf_prog *prog) -{ - if (attr->link_create.attach_type != prog->expected_attach_type) - return -EINVAL; - - if (prog->expected_attach_type == BPF_TRACE_ITER) - return bpf_iter_link_attach(attr, prog); - else if (prog->type == BPF_PROG_TYPE_EXT) - return bpf_tracing_prog_attach(prog, - attr->link_create.target_fd, - attr->link_create.target_btf_id); - return -EINVAL; -} - -#define BPF_LINK_CREATE_LAST_FIELD link_create.iter_info_len -static int link_create(union bpf_attr *attr) -{ - enum bpf_prog_type ptype; - struct bpf_prog *prog; - int ret; - - if (CHECK_ATTR(BPF_LINK_CREATE)) - return -EINVAL; - - prog = bpf_prog_get(attr->link_create.prog_fd); - if (IS_ERR(prog)) - return PTR_ERR(prog); - - ret = bpf_prog_attach_check_attach_type(prog, - attr->link_create.attach_type); - if (ret) - goto out; - - if (prog->type == BPF_PROG_TYPE_EXT) { - ret = tracing_bpf_link_attach(attr, prog); - goto out; - } - - ptype = attach_type_to_prog_type(attr->link_create.attach_type); - if (ptype == BPF_PROG_TYPE_UNSPEC || ptype != prog->type) { - ret = -EINVAL; - goto out; - } - - switch (ptype) { - case BPF_PROG_TYPE_CGROUP_SKB: - case BPF_PROG_TYPE_CGROUP_SOCK: - case BPF_PROG_TYPE_CGROUP_SOCK_ADDR: - case BPF_PROG_TYPE_SOCK_OPS: - case BPF_PROG_TYPE_CGROUP_DEVICE: - case BPF_PROG_TYPE_CGROUP_SYSCTL: - case BPF_PROG_TYPE_CGROUP_SOCKOPT: - ret = cgroup_bpf_link_attach(attr, prog); - break; - case BPF_PROG_TYPE_TRACING: - ret = tracing_bpf_link_attach(attr, prog); - break; - case BPF_PROG_TYPE_FLOW_DISSECTOR: - case BPF_PROG_TYPE_SK_LOOKUP: - ret = netns_bpf_link_create(attr, prog); - break; -#ifdef CONFIG_NET - case BPF_PROG_TYPE_XDP: - ret = bpf_xdp_link_attach(attr, prog); - break; -#endif - default: - ret = -EINVAL; - } - -out: - if (ret < 0) - bpf_prog_put(prog); - return ret; -} - -#define BPF_LINK_UPDATE_LAST_FIELD link_update.old_prog_fd - -static int link_update(union bpf_attr *attr) -{ - struct bpf_prog *old_prog = NULL, *new_prog; - struct bpf_link *link; - u32 flags; - int ret; - - if (CHECK_ATTR(BPF_LINK_UPDATE)) - return -EINVAL; - - flags = attr->link_update.flags; - if (flags & ~BPF_F_REPLACE) - return -EINVAL; - - link = bpf_link_get_from_fd(attr->link_update.link_fd); - if (IS_ERR(link)) - return PTR_ERR(link); - - new_prog = bpf_prog_get(attr->link_update.new_prog_fd); - if (IS_ERR(new_prog)) { - ret = PTR_ERR(new_prog); - goto out_put_link; - } - - if (flags & BPF_F_REPLACE) { - old_prog = bpf_prog_get(attr->link_update.old_prog_fd); - if (IS_ERR(old_prog)) { - ret = PTR_ERR(old_prog); - old_prog = NULL; - goto out_put_progs; - } - } else if (attr->link_update.old_prog_fd) { - ret = -EINVAL; - goto out_put_progs; - } - - if (link->ops->update_prog) - ret = link->ops->update_prog(link, new_prog, old_prog); - else - ret = -EINVAL; - -out_put_progs: - if (old_prog) - bpf_prog_put(old_prog); - if (ret) - bpf_prog_put(new_prog); -out_put_link: - bpf_link_put(link); - return ret; -} - -#define BPF_LINK_DETACH_LAST_FIELD link_detach.link_fd - -static int link_detach(union bpf_attr *attr) -{ - struct bpf_link *link; - int ret; - - if (CHECK_ATTR(BPF_LINK_DETACH)) - return -EINVAL; - - link = bpf_link_get_from_fd(attr->link_detach.link_fd); - if (IS_ERR(link)) - return PTR_ERR(link); - - if (link->ops->detach) - ret = link->ops->detach(link); - else - ret = -EOPNOTSUPP; - - bpf_link_put(link); - return ret; -} - -static struct bpf_link *bpf_link_inc_not_zero(struct bpf_link *link) -{ - return atomic64_fetch_add_unless(&link->refcnt, 1, 0) ? link : ERR_PTR(-ENOENT); -} - -struct bpf_link *bpf_link_by_id(u32 id) -{ - struct bpf_link *link; - - if (!id) - return ERR_PTR(-ENOENT); - - spin_lock_bh(&link_idr_lock); - /* before link is "settled", ID is 0, pretend it doesn't exist yet */ - link = idr_find(&link_idr, id); - if (link) { - if (link->id) - link = bpf_link_inc_not_zero(link); - else - link = ERR_PTR(-EAGAIN); - } else { - link = ERR_PTR(-ENOENT); - } - spin_unlock_bh(&link_idr_lock); - return link; -} - -#define BPF_LINK_GET_FD_BY_ID_LAST_FIELD link_id - -static int bpf_link_get_fd_by_id(const union bpf_attr *attr) -{ - struct bpf_link *link; - u32 id = attr->link_id; - int fd; - - if (CHECK_ATTR(BPF_LINK_GET_FD_BY_ID)) - return -EINVAL; - - if (!capable(CAP_SYS_ADMIN)) - return -EPERM; - - link = bpf_link_by_id(id); - if (IS_ERR(link)) - return PTR_ERR(link); - - fd = bpf_link_new_fd(link); - if (fd < 0) - bpf_link_put(link); - - return fd; -} - -DEFINE_MUTEX(bpf_stats_enabled_mutex); - -static int bpf_stats_release(struct inode *inode, struct file *file) -{ - mutex_lock(&bpf_stats_enabled_mutex); - static_key_slow_dec(&bpf_stats_enabled_key.key); - mutex_unlock(&bpf_stats_enabled_mutex); - return 0; -} - -static const struct file_operations bpf_stats_fops = { - .release = bpf_stats_release, -}; - -static int bpf_enable_runtime_stats(void) -{ - int fd; - - mutex_lock(&bpf_stats_enabled_mutex); - - /* Set a very high limit to avoid overflow */ - if (static_key_count(&bpf_stats_enabled_key.key) > INT_MAX / 2) { - mutex_unlock(&bpf_stats_enabled_mutex); - return -EBUSY; - } - - fd = anon_inode_getfd("bpf-stats", &bpf_stats_fops, NULL, O_CLOEXEC); - if (fd >= 0) - static_key_slow_inc(&bpf_stats_enabled_key.key); - - mutex_unlock(&bpf_stats_enabled_mutex); - return fd; -} - -#define BPF_ENABLE_STATS_LAST_FIELD enable_stats.type - -static int bpf_enable_stats(union bpf_attr *attr) -{ - - if (CHECK_ATTR(BPF_ENABLE_STATS)) - return -EINVAL; - - if (!capable(CAP_SYS_ADMIN)) - return -EPERM; - - switch (attr->enable_stats.type) { - case BPF_STATS_RUN_TIME: - return bpf_enable_runtime_stats(); - default: - break; - } - return -EINVAL; -} - -#define BPF_ITER_CREATE_LAST_FIELD iter_create.flags - -static int bpf_iter_create(union bpf_attr *attr) -{ - struct bpf_link *link; - int err; - - if (CHECK_ATTR(BPF_ITER_CREATE)) - return -EINVAL; - - if (attr->iter_create.flags) - return -EINVAL; - - link = bpf_link_get_from_fd(attr->iter_create.link_fd); - if (IS_ERR(link)) - return PTR_ERR(link); - - err = bpf_iter_new_fd(link); - bpf_link_put(link); - - return err; -} - -#define BPF_PROG_BIND_MAP_LAST_FIELD prog_bind_map.flags - -static int bpf_prog_bind_map(union bpf_attr *attr) -{ - struct bpf_prog *prog; - struct bpf_map *map; - struct bpf_map **used_maps_old, **used_maps_new; - int i, ret = 0; - - if (CHECK_ATTR(BPF_PROG_BIND_MAP)) - return -EINVAL; - - if (attr->prog_bind_map.flags) - return -EINVAL; - - prog = bpf_prog_get(attr->prog_bind_map.prog_fd); - if (IS_ERR(prog)) - return PTR_ERR(prog); - - map = bpf_map_get(attr->prog_bind_map.map_fd); - if (IS_ERR(map)) { - ret = PTR_ERR(map); - goto out_prog_put; - } - - mutex_lock(&prog->aux->used_maps_mutex); - - used_maps_old = prog->aux->used_maps; - - for (i = 0; i < prog->aux->used_map_cnt; i++) - if (used_maps_old[i] == map) { - bpf_map_put(map); - goto out_unlock; - } - - used_maps_new = kmalloc_array(prog->aux->used_map_cnt + 1, - sizeof(used_maps_new[0]), - GFP_KERNEL); - if (!used_maps_new) { - ret = -ENOMEM; - goto out_unlock; - } - - memcpy(used_maps_new, used_maps_old, - sizeof(used_maps_old[0]) * prog->aux->used_map_cnt); - used_maps_new[prog->aux->used_map_cnt] = map; - - prog->aux->used_map_cnt++; - prog->aux->used_maps = used_maps_new; - - kfree(used_maps_old); - -out_unlock: - mutex_unlock(&prog->aux->used_maps_mutex); - - if (ret) - bpf_map_put(map); -out_prog_put: - bpf_prog_put(prog); - return ret; -} - SYSCALL_DEFINE3(bpf, int, cmd, union bpf_attr __user *, uattr, unsigned int, size) { union bpf_attr attr; int err; - if (sysctl_unprivileged_bpf_disabled && !bpf_capable()) + if (sysctl_unprivileged_bpf_disabled && !capable(CAP_SYS_ADMIN)) return -EPERM; err = bpf_check_uarg_tail_zero(uattr, sizeof(attr), size); @@ -4480,44 +2944,6 @@ SYSCALL_DEFINE3(bpf, int, cmd, union bpf_attr __user *, uattr, unsigned int, siz case BPF_MAP_LOOKUP_AND_DELETE_ELEM: err = map_lookup_and_delete_elem(&attr); break; - case BPF_MAP_LOOKUP_BATCH: - err = bpf_map_do_batch(&attr, uattr, BPF_MAP_LOOKUP_BATCH); - break; - case BPF_MAP_LOOKUP_AND_DELETE_BATCH: - err = bpf_map_do_batch(&attr, uattr, - BPF_MAP_LOOKUP_AND_DELETE_BATCH); - break; - case BPF_MAP_UPDATE_BATCH: - err = bpf_map_do_batch(&attr, uattr, BPF_MAP_UPDATE_BATCH); - break; - case BPF_MAP_DELETE_BATCH: - err = bpf_map_do_batch(&attr, uattr, BPF_MAP_DELETE_BATCH); - break; - case BPF_LINK_CREATE: - err = link_create(&attr); - break; - case BPF_LINK_UPDATE: - err = link_update(&attr); - break; - case BPF_LINK_GET_FD_BY_ID: - err = bpf_link_get_fd_by_id(&attr); - break; - case BPF_LINK_GET_NEXT_ID: - err = bpf_obj_get_next_id(&attr, uattr, - &link_idr, &link_idr_lock); - break; - case BPF_ENABLE_STATS: - err = bpf_enable_stats(&attr); - break; - case BPF_ITER_CREATE: - err = bpf_iter_create(&attr); - break; - case BPF_LINK_DETACH: - err = link_detach(&attr); - break; - case BPF_PROG_BIND_MAP: - err = bpf_prog_bind_map(&attr); - break; default: err = -EINVAL; break; diff --git a/kernel/bpf/task_iter.c b/kernel/bpf/task_iter.c deleted file mode 100644 index f3d3a562a802..000000000000 --- a/kernel/bpf/task_iter.c +++ /dev/null @@ -1,361 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2020 Facebook */ - -#include -#include -#include -#include -#include -#include -#include - -struct bpf_iter_seq_task_common { - struct pid_namespace *ns; -}; - -struct bpf_iter_seq_task_info { - /* The first field must be struct bpf_iter_seq_task_common. - * this is assumed by {init, fini}_seq_pidns() callback functions. - */ - struct bpf_iter_seq_task_common common; - u32 tid; -}; - -static struct task_struct *task_seq_get_next(struct pid_namespace *ns, - u32 *tid, - bool skip_if_dup_files) -{ - struct task_struct *task = NULL; - struct pid *pid; - - rcu_read_lock(); -retry: - pid = find_ge_pid(*tid, ns); - if (pid) { - *tid = pid_nr_ns(pid, ns); - task = get_pid_task(pid, PIDTYPE_PID); - if (!task) { - ++*tid; - goto retry; - } else if (skip_if_dup_files && task->tgid != task->pid && - task->files == task->group_leader->files) { - put_task_struct(task); - task = NULL; - ++*tid; - goto retry; - } - } - rcu_read_unlock(); - - return task; -} - -static void *task_seq_start(struct seq_file *seq, loff_t *pos) -{ - struct bpf_iter_seq_task_info *info = seq->private; - struct task_struct *task; - - task = task_seq_get_next(info->common.ns, &info->tid, false); - if (!task) - return NULL; - - if (*pos == 0) - ++*pos; - return task; -} - -static void *task_seq_next(struct seq_file *seq, void *v, loff_t *pos) -{ - struct bpf_iter_seq_task_info *info = seq->private; - struct task_struct *task; - - ++*pos; - ++info->tid; - put_task_struct((struct task_struct *)v); - task = task_seq_get_next(info->common.ns, &info->tid, false); - if (!task) - return NULL; - - return task; -} - -struct bpf_iter__task { - __bpf_md_ptr(struct bpf_iter_meta *, meta); - __bpf_md_ptr(struct task_struct *, task); -}; - -DEFINE_BPF_ITER_FUNC(task, struct bpf_iter_meta *meta, struct task_struct *task) - -static int __task_seq_show(struct seq_file *seq, struct task_struct *task, - bool in_stop) -{ - struct bpf_iter_meta meta; - struct bpf_iter__task ctx; - struct bpf_prog *prog; - - meta.seq = seq; - prog = bpf_iter_get_info(&meta, in_stop); - if (!prog) - return 0; - - meta.seq = seq; - ctx.meta = &meta; - ctx.task = task; - return bpf_iter_run_prog(prog, &ctx); -} - -static int task_seq_show(struct seq_file *seq, void *v) -{ - return __task_seq_show(seq, v, false); -} - -static void task_seq_stop(struct seq_file *seq, void *v) -{ - if (!v) - (void)__task_seq_show(seq, v, true); - else - put_task_struct((struct task_struct *)v); -} - -static const struct seq_operations task_seq_ops = { - .start = task_seq_start, - .next = task_seq_next, - .stop = task_seq_stop, - .show = task_seq_show, -}; - -struct bpf_iter_seq_task_file_info { - /* The first field must be struct bpf_iter_seq_task_common. - * this is assumed by {init, fini}_seq_pidns() callback functions. - */ - struct bpf_iter_seq_task_common common; - struct task_struct *task; - struct files_struct *files; - u32 tid; - u32 fd; -}; - -static struct file * -task_file_seq_get_next(struct bpf_iter_seq_task_file_info *info) -{ - struct pid_namespace *ns = info->common.ns; - u32 curr_tid = info->tid, max_fds; - struct files_struct *curr_files; - struct task_struct *curr_task; - int curr_fd = info->fd; - - /* If this function returns a non-NULL file object, - * it held a reference to the task/files_struct/file. - * Otherwise, it does not hold any reference. - */ -again: - if (info->task) { - curr_task = info->task; - curr_files = info->files; - curr_fd = info->fd; - } else { - curr_task = task_seq_get_next(ns, &curr_tid, true); - if (!curr_task) { - info->task = NULL; - info->files = NULL; - info->tid = curr_tid; - return NULL; - } - - curr_files = get_files_struct(curr_task); - if (!curr_files) { - put_task_struct(curr_task); - curr_tid = curr_tid + 1; - info->fd = 0; - goto again; - } - - info->files = curr_files; - info->task = curr_task; - if (curr_tid == info->tid) { - curr_fd = info->fd; - } else { - info->tid = curr_tid; - curr_fd = 0; - } - } - - rcu_read_lock(); - max_fds = files_fdtable(curr_files)->max_fds; - for (; curr_fd < max_fds; curr_fd++) { - struct file *f; - - f = fcheck_files(curr_files, curr_fd); - if (!f) - continue; - if (!get_file_rcu(f)) - continue; - - /* set info->fd */ - info->fd = curr_fd; - rcu_read_unlock(); - return f; - } - - /* the current task is done, go to the next task */ - rcu_read_unlock(); - put_files_struct(curr_files); - put_task_struct(curr_task); - info->task = NULL; - info->files = NULL; - info->fd = 0; - curr_tid = ++(info->tid); - goto again; -} - -static void *task_file_seq_start(struct seq_file *seq, loff_t *pos) -{ - struct bpf_iter_seq_task_file_info *info = seq->private; - struct file *file; - - info->task = NULL; - info->files = NULL; - file = task_file_seq_get_next(info); - if (file && *pos == 0) - ++*pos; - - return file; -} - -static void *task_file_seq_next(struct seq_file *seq, void *v, loff_t *pos) -{ - struct bpf_iter_seq_task_file_info *info = seq->private; - - ++*pos; - ++info->fd; - fput((struct file *)v); - return task_file_seq_get_next(info); -} - -struct bpf_iter__task_file { - __bpf_md_ptr(struct bpf_iter_meta *, meta); - __bpf_md_ptr(struct task_struct *, task); - u32 fd __aligned(8); - __bpf_md_ptr(struct file *, file); -}; - -DEFINE_BPF_ITER_FUNC(task_file, struct bpf_iter_meta *meta, - struct task_struct *task, u32 fd, - struct file *file) - -static int __task_file_seq_show(struct seq_file *seq, struct file *file, - bool in_stop) -{ - struct bpf_iter_seq_task_file_info *info = seq->private; - struct bpf_iter__task_file ctx; - struct bpf_iter_meta meta; - struct bpf_prog *prog; - - meta.seq = seq; - prog = bpf_iter_get_info(&meta, in_stop); - if (!prog) - return 0; - - ctx.meta = &meta; - ctx.task = info->task; - ctx.fd = info->fd; - ctx.file = file; - return bpf_iter_run_prog(prog, &ctx); -} - -static int task_file_seq_show(struct seq_file *seq, void *v) -{ - return __task_file_seq_show(seq, v, false); -} - -static void task_file_seq_stop(struct seq_file *seq, void *v) -{ - struct bpf_iter_seq_task_file_info *info = seq->private; - - if (!v) { - (void)__task_file_seq_show(seq, v, true); - } else { - fput((struct file *)v); - put_files_struct(info->files); - put_task_struct(info->task); - info->files = NULL; - info->task = NULL; - } -} - -static int init_seq_pidns(void *priv_data, struct bpf_iter_aux_info *aux) -{ - struct bpf_iter_seq_task_common *common = priv_data; - - common->ns = get_pid_ns(task_active_pid_ns(current)); - return 0; -} - -static void fini_seq_pidns(void *priv_data) -{ - struct bpf_iter_seq_task_common *common = priv_data; - - put_pid_ns(common->ns); -} - -static const struct seq_operations task_file_seq_ops = { - .start = task_file_seq_start, - .next = task_file_seq_next, - .stop = task_file_seq_stop, - .show = task_file_seq_show, -}; - -BTF_ID_LIST(btf_task_file_ids) -BTF_ID(struct, task_struct) -BTF_ID(struct, file) - -static const struct bpf_iter_seq_info task_seq_info = { - .seq_ops = &task_seq_ops, - .init_seq_private = init_seq_pidns, - .fini_seq_private = fini_seq_pidns, - .seq_priv_size = sizeof(struct bpf_iter_seq_task_info), -}; - -static struct bpf_iter_reg task_reg_info = { - .target = "task", - .ctx_arg_info_size = 1, - .ctx_arg_info = { - { offsetof(struct bpf_iter__task, task), - PTR_TO_BTF_ID_OR_NULL }, - }, - .seq_info = &task_seq_info, -}; - -static const struct bpf_iter_seq_info task_file_seq_info = { - .seq_ops = &task_file_seq_ops, - .init_seq_private = init_seq_pidns, - .fini_seq_private = fini_seq_pidns, - .seq_priv_size = sizeof(struct bpf_iter_seq_task_file_info), -}; - -static struct bpf_iter_reg task_file_reg_info = { - .target = "task_file", - .ctx_arg_info_size = 2, - .ctx_arg_info = { - { offsetof(struct bpf_iter__task_file, task), - PTR_TO_BTF_ID_OR_NULL }, - { offsetof(struct bpf_iter__task_file, file), - PTR_TO_BTF_ID_OR_NULL }, - }, - .seq_info = &task_file_seq_info, -}; - -static int __init task_iter_init(void) -{ - int ret; - - task_reg_info.ctx_arg_info[0].btf_id = btf_task_file_ids[0]; - ret = bpf_iter_reg_target(&task_reg_info); - if (ret) - return ret; - - task_file_reg_info.ctx_arg_info[0].btf_id = btf_task_file_ids[0]; - task_file_reg_info.ctx_arg_info[1].btf_id = btf_task_file_ids[1]; - return bpf_iter_reg_target(&task_file_reg_info); -} -late_initcall(task_iter_init); diff --git a/kernel/bpf/tnum.c b/kernel/bpf/tnum.c index ceac5281bd31..d4f335a9a899 100644 --- a/kernel/bpf/tnum.c +++ b/kernel/bpf/tnum.c @@ -194,18 +194,3 @@ int tnum_sbin(char *str, size_t size, struct tnum a) str[min(size - 1, (size_t)64)] = 0; return 64; } - -struct tnum tnum_subreg(struct tnum a) -{ - return tnum_cast(a, 4); -} - -struct tnum tnum_clear_subreg(struct tnum a) -{ - return tnum_lshift(tnum_rshift(a, 32), 32); -} - -struct tnum tnum_const_subreg(struct tnum a, u32 value) -{ - return tnum_or(tnum_clear_subreg(a), tnum_const(value)); -} diff --git a/kernel/bpf/trampoline.c b/kernel/bpf/trampoline.c deleted file mode 100644 index 87becf77cc75..000000000000 --- a/kernel/bpf/trampoline.c +++ /dev/null @@ -1,577 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2019 Facebook */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* dummy _ops. The verifier will operate on target program's ops. */ -const struct bpf_verifier_ops bpf_extension_verifier_ops = { -}; -const struct bpf_prog_ops bpf_extension_prog_ops = { -}; - -/* btf_vmlinux has ~22k attachable functions. 1k htab is enough. */ -#define TRAMPOLINE_HASH_BITS 10 -#define TRAMPOLINE_TABLE_SIZE (1 << TRAMPOLINE_HASH_BITS) - -static struct hlist_head trampoline_table[TRAMPOLINE_TABLE_SIZE]; - -/* serializes access to trampoline_table */ -static DEFINE_MUTEX(trampoline_mutex); - -void *bpf_jit_alloc_exec_page(void) -{ - void *image; - - image = bpf_jit_alloc_exec(PAGE_SIZE); - if (!image) - return NULL; - - set_vm_flush_reset_perms(image); - /* Keep image as writeable. The alternative is to keep flipping ro/rw - * everytime new program is attached or detached. - */ - set_memory_x((long)image, 1); - return image; -} - -void bpf_image_ksym_add(void *data, struct bpf_ksym *ksym) -{ - ksym->start = (unsigned long) data; - ksym->end = ksym->start + PAGE_SIZE; - bpf_ksym_add(ksym); - perf_event_ksymbol(PERF_RECORD_KSYMBOL_TYPE_BPF, ksym->start, - PAGE_SIZE, false, ksym->name); -} - -void bpf_image_ksym_del(struct bpf_ksym *ksym) -{ - bpf_ksym_del(ksym); - perf_event_ksymbol(PERF_RECORD_KSYMBOL_TYPE_BPF, ksym->start, - PAGE_SIZE, true, ksym->name); -} - -static struct bpf_trampoline *bpf_trampoline_lookup(u64 key) -{ - struct bpf_trampoline *tr; - struct hlist_head *head; - int i; - - mutex_lock(&trampoline_mutex); - head = &trampoline_table[hash_64(key, TRAMPOLINE_HASH_BITS)]; - hlist_for_each_entry(tr, head, hlist) { - if (tr->key == key) { - refcount_inc(&tr->refcnt); - goto out; - } - } - tr = kzalloc(sizeof(*tr), GFP_KERNEL); - if (!tr) - goto out; - - tr->key = key; - INIT_HLIST_NODE(&tr->hlist); - hlist_add_head(&tr->hlist, head); - refcount_set(&tr->refcnt, 1); - mutex_init(&tr->mutex); - for (i = 0; i < BPF_TRAMP_MAX; i++) - INIT_HLIST_HEAD(&tr->progs_hlist[i]); -out: - mutex_unlock(&trampoline_mutex); - return tr; -} - -static int is_ftrace_location(void *ip) -{ - long addr; - - addr = ftrace_location((long)ip); - if (!addr) - return 0; - if (WARN_ON_ONCE(addr != (long)ip)) - return -EFAULT; - return 1; -} - -static int unregister_fentry(struct bpf_trampoline *tr, void *old_addr) -{ - void *ip = tr->func.addr; - int ret; - - if (tr->func.ftrace_managed) - ret = unregister_ftrace_direct((long)ip, (long)old_addr); - else - ret = bpf_arch_text_poke(ip, BPF_MOD_CALL, old_addr, NULL); - return ret; -} - -static int modify_fentry(struct bpf_trampoline *tr, void *old_addr, void *new_addr) -{ - void *ip = tr->func.addr; - int ret; - - if (tr->func.ftrace_managed) - ret = modify_ftrace_direct((long)ip, (long)old_addr, (long)new_addr); - else - ret = bpf_arch_text_poke(ip, BPF_MOD_CALL, old_addr, new_addr); - return ret; -} - -/* first time registering */ -static int register_fentry(struct bpf_trampoline *tr, void *new_addr) -{ - void *ip = tr->func.addr; - int ret; - - ret = is_ftrace_location(ip); - if (ret < 0) - return ret; - tr->func.ftrace_managed = ret; - - if (tr->func.ftrace_managed) - ret = register_ftrace_direct((long)ip, (long)new_addr); - else - ret = bpf_arch_text_poke(ip, BPF_MOD_CALL, NULL, new_addr); - return ret; -} - -static struct bpf_tramp_progs * -bpf_trampoline_get_progs(const struct bpf_trampoline *tr, int *total) -{ - const struct bpf_prog_aux *aux; - struct bpf_tramp_progs *tprogs; - struct bpf_prog **progs; - int kind; - - *total = 0; - tprogs = kcalloc(BPF_TRAMP_MAX, sizeof(*tprogs), GFP_KERNEL); - if (!tprogs) - return ERR_PTR(-ENOMEM); - - for (kind = 0; kind < BPF_TRAMP_MAX; kind++) { - tprogs[kind].nr_progs = tr->progs_cnt[kind]; - *total += tr->progs_cnt[kind]; - progs = tprogs[kind].progs; - - hlist_for_each_entry(aux, &tr->progs_hlist[kind], tramp_hlist) - *progs++ = aux->prog; - } - return tprogs; -} - -static void __bpf_tramp_image_put_deferred(struct work_struct *work) -{ - struct bpf_tramp_image *im; - - im = container_of(work, struct bpf_tramp_image, work); - bpf_image_ksym_del(&im->ksym); - bpf_jit_free_exec(im->image); - bpf_jit_uncharge_modmem(1); - percpu_ref_exit(&im->pcref); - kfree_rcu(im, rcu); -} - -/* callback, fexit step 3 or fentry step 2 */ -static void __bpf_tramp_image_put_rcu(struct rcu_head *rcu) -{ - struct bpf_tramp_image *im; - - im = container_of(rcu, struct bpf_tramp_image, rcu); - INIT_WORK(&im->work, __bpf_tramp_image_put_deferred); - schedule_work(&im->work); -} - -/* callback, fexit step 2. Called after percpu_ref_kill confirms. */ -static void __bpf_tramp_image_release(struct percpu_ref *pcref) -{ - struct bpf_tramp_image *im; - - im = container_of(pcref, struct bpf_tramp_image, pcref); - call_rcu_tasks(&im->rcu, __bpf_tramp_image_put_rcu); -} - -/* callback, fexit or fentry step 1 */ -static void __bpf_tramp_image_put_rcu_tasks(struct rcu_head *rcu) -{ - struct bpf_tramp_image *im; - - im = container_of(rcu, struct bpf_tramp_image, rcu); - if (im->ip_after_call) - /* the case of fmod_ret/fexit trampoline and CONFIG_PREEMPTION=y */ - percpu_ref_kill(&im->pcref); - else - /* the case of fentry trampoline */ - call_rcu_tasks(&im->rcu, __bpf_tramp_image_put_rcu); -} - -static void bpf_tramp_image_put(struct bpf_tramp_image *im) -{ - /* The trampoline image that calls original function is using: - * rcu_read_lock_trace to protect sleepable bpf progs - * rcu_read_lock to protect normal bpf progs - * percpu_ref to protect trampoline itself - * rcu tasks to protect trampoline asm not covered by percpu_ref - * (which are few asm insns before __bpf_tramp_enter and - * after __bpf_tramp_exit) - * - * The trampoline is unreachable before bpf_tramp_image_put(). - * - * First, patch the trampoline to avoid calling into fexit progs. - * The progs will be freed even if the original function is still - * executing or sleeping. - * In case of CONFIG_PREEMPT=y use call_rcu_tasks() to wait on - * first few asm instructions to execute and call into - * __bpf_tramp_enter->percpu_ref_get. - * Then use percpu_ref_kill to wait for the trampoline and the original - * function to finish. - * Then use call_rcu_tasks() to make sure few asm insns in - * the trampoline epilogue are done as well. - * - * In !PREEMPT case the task that got interrupted in the first asm - * insns won't go through an RCU quiescent state which the - * percpu_ref_kill will be waiting for. Hence the first - * call_rcu_tasks() is not necessary. - */ - if (im->ip_after_call) { - int err = bpf_arch_text_poke(im->ip_after_call, BPF_MOD_JUMP, - NULL, im->ip_epilogue); - WARN_ON(err); - if (IS_ENABLED(CONFIG_PREEMPTION)) - call_rcu_tasks(&im->rcu, __bpf_tramp_image_put_rcu_tasks); - else - percpu_ref_kill(&im->pcref); - return; - } - - /* The trampoline without fexit and fmod_ret progs doesn't call original - * function and doesn't use percpu_ref. - * Use call_rcu_tasks_trace() to wait for sleepable progs to finish. - * Then use call_rcu_tasks() to wait for the rest of trampoline asm - * and normal progs. - */ - call_rcu_tasks_trace(&im->rcu, __bpf_tramp_image_put_rcu_tasks); -} - -static struct bpf_tramp_image *bpf_tramp_image_alloc(u64 key, u32 idx) -{ - struct bpf_tramp_image *im; - struct bpf_ksym *ksym; - void *image; - int err = -ENOMEM; - - im = kzalloc(sizeof(*im), GFP_KERNEL); - if (!im) - goto out; - - err = bpf_jit_charge_modmem(1); - if (err) - goto out_free_im; - - err = -ENOMEM; - im->image = image = bpf_jit_alloc_exec_page(); - if (!image) - goto out_uncharge; - - err = percpu_ref_init(&im->pcref, __bpf_tramp_image_release, 0, GFP_KERNEL); - if (err) - goto out_free_image; - - ksym = &im->ksym; - INIT_LIST_HEAD_RCU(&ksym->lnode); - snprintf(ksym->name, KSYM_NAME_LEN, "bpf_trampoline_%llu_%u", key, idx); - bpf_image_ksym_add(image, ksym); - return im; - -out_free_image: - bpf_jit_free_exec(im->image); -out_uncharge: - bpf_jit_uncharge_modmem(1); -out_free_im: - kfree(im); -out: - return ERR_PTR(err); -} - -static int bpf_trampoline_update(struct bpf_trampoline *tr) -{ - struct bpf_tramp_image *im; - struct bpf_tramp_progs *tprogs; - u32 flags = BPF_TRAMP_F_RESTORE_REGS; - int err, total; - - tprogs = bpf_trampoline_get_progs(tr, &total); - if (IS_ERR(tprogs)) - return PTR_ERR(tprogs); - - if (total == 0) { - err = unregister_fentry(tr, tr->cur_image->image); - bpf_tramp_image_put(tr->cur_image); - tr->cur_image = NULL; - tr->selector = 0; - goto out; - } - - im = bpf_tramp_image_alloc(tr->key, tr->selector); - if (IS_ERR(im)) { - err = PTR_ERR(im); - goto out; - } - - if (tprogs[BPF_TRAMP_FEXIT].nr_progs || - tprogs[BPF_TRAMP_MODIFY_RETURN].nr_progs) - flags = BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_SKIP_FRAME; - - err = arch_prepare_bpf_trampoline(im, im->image, im->image + PAGE_SIZE, - &tr->func.model, flags, tprogs, - tr->func.addr); - if (err < 0) - goto out; - - WARN_ON(tr->cur_image && tr->selector == 0); - WARN_ON(!tr->cur_image && tr->selector); - if (tr->cur_image) - /* progs already running at this address */ - err = modify_fentry(tr, tr->cur_image->image, im->image); - else - /* first time registering */ - err = register_fentry(tr, im->image); - if (err) - goto out; - if (tr->cur_image) - bpf_tramp_image_put(tr->cur_image); - tr->cur_image = im; - tr->selector++; -out: - kfree(tprogs); - return err; -} - -static enum bpf_tramp_prog_type bpf_attach_type_to_tramp(struct bpf_prog *prog) -{ - switch (prog->expected_attach_type) { - case BPF_TRACE_FENTRY: - return BPF_TRAMP_FENTRY; - case BPF_MODIFY_RETURN: - return BPF_TRAMP_MODIFY_RETURN; - case BPF_TRACE_FEXIT: - return BPF_TRAMP_FEXIT; - case BPF_LSM_MAC: - if (!prog->aux->attach_func_proto->type) - /* The function returns void, we cannot modify its - * return value. - */ - return BPF_TRAMP_FEXIT; - else - return BPF_TRAMP_MODIFY_RETURN; - default: - return BPF_TRAMP_REPLACE; - } -} - -int bpf_trampoline_link_prog(struct bpf_prog *prog, struct bpf_trampoline *tr) -{ - enum bpf_tramp_prog_type kind; - int err = 0; - int cnt = 0, i; - - kind = bpf_attach_type_to_tramp(prog); - mutex_lock(&tr->mutex); - if (tr->extension_prog) { - /* cannot attach fentry/fexit if extension prog is attached. - * cannot overwrite extension prog either. - */ - err = -EBUSY; - goto out; - } - - for (i = 0; i < BPF_TRAMP_MAX; i++) - cnt += tr->progs_cnt[i]; - - if (kind == BPF_TRAMP_REPLACE) { - /* Cannot attach extension if fentry/fexit are in use. */ - if (cnt) { - err = -EBUSY; - goto out; - } - tr->extension_prog = prog; - err = bpf_arch_text_poke(tr->func.addr, BPF_MOD_JUMP, NULL, - prog->bpf_func); - goto out; - } - if (cnt >= BPF_MAX_TRAMP_PROGS) { - err = -E2BIG; - goto out; - } - if (!hlist_unhashed(&prog->aux->tramp_hlist)) { - /* prog already linked */ - err = -EBUSY; - goto out; - } - hlist_add_head(&prog->aux->tramp_hlist, &tr->progs_hlist[kind]); - tr->progs_cnt[kind]++; - err = bpf_trampoline_update(tr); - if (err) { - hlist_del(&prog->aux->tramp_hlist); - tr->progs_cnt[kind]--; - } -out: - mutex_unlock(&tr->mutex); - return err; -} - -/* bpf_trampoline_unlink_prog() should never fail. */ -int bpf_trampoline_unlink_prog(struct bpf_prog *prog, struct bpf_trampoline *tr) -{ - enum bpf_tramp_prog_type kind; - int err; - - kind = bpf_attach_type_to_tramp(prog); - mutex_lock(&tr->mutex); - if (kind == BPF_TRAMP_REPLACE) { - WARN_ON_ONCE(!tr->extension_prog); - err = bpf_arch_text_poke(tr->func.addr, BPF_MOD_JUMP, - tr->extension_prog->bpf_func, NULL); - tr->extension_prog = NULL; - goto out; - } - hlist_del(&prog->aux->tramp_hlist); - tr->progs_cnt[kind]--; - err = bpf_trampoline_update(tr); -out: - mutex_unlock(&tr->mutex); - return err; -} - -struct bpf_trampoline *bpf_trampoline_get(u64 key, - struct bpf_attach_target_info *tgt_info) -{ - struct bpf_trampoline *tr; - - tr = bpf_trampoline_lookup(key); - if (!tr) - return NULL; - - mutex_lock(&tr->mutex); - if (tr->func.addr) - goto out; - - memcpy(&tr->func.model, &tgt_info->fmodel, sizeof(tgt_info->fmodel)); - tr->func.addr = (void *)tgt_info->tgt_addr; -out: - mutex_unlock(&tr->mutex); - return tr; -} - -void bpf_trampoline_put(struct bpf_trampoline *tr) -{ - int i; - - if (!tr) - return; - mutex_lock(&trampoline_mutex); - if (!refcount_dec_and_test(&tr->refcnt)) - goto out; - WARN_ON_ONCE(mutex_is_locked(&tr->mutex)); - - for (i = 0; i < BPF_TRAMP_MAX; i++) - if (WARN_ON_ONCE(!hlist_empty(&tr->progs_hlist[i]))) - goto out; - - /* This code will be executed even when the last bpf_tramp_image - * is alive. All progs are detached from the trampoline and the - * trampoline image is patched with jmp into epilogue to skip - * fexit progs. The fentry-only trampoline will be freed via - * multiple rcu callbacks. - */ - hlist_del(&tr->hlist); - kfree(tr); -out: - mutex_unlock(&trampoline_mutex); -} - -/* The logic is similar to BPF_PROG_RUN, but with an explicit - * rcu_read_lock() and migrate_disable() which are required - * for the trampoline. The macro is split into - * call _bpf_prog_enter - * call prog->bpf_func - * call __bpf_prog_exit - */ -u64 notrace __bpf_prog_enter(void) - __acquires(RCU) -{ - u64 start = 0; - - rcu_read_lock(); - migrate_disable(); - if (static_branch_unlikely(&bpf_stats_enabled_key)) - start = sched_clock(); - return start; -} - -void notrace __bpf_prog_exit(struct bpf_prog *prog, u64 start) - __releases(RCU) -{ - struct bpf_prog_stats *stats; - - if (static_branch_unlikely(&bpf_stats_enabled_key) && - /* static_key could be enabled in __bpf_prog_enter - * and disabled in __bpf_prog_exit. - * And vice versa. - * Hence check that 'start' is not zero. - */ - start) { - stats = this_cpu_ptr(prog->aux->stats); - u64_stats_update_begin(&stats->syncp); - stats->cnt++; - stats->nsecs += sched_clock() - start; - u64_stats_update_end(&stats->syncp); - } - migrate_enable(); - rcu_read_unlock(); -} - -void notrace __bpf_prog_enter_sleepable(void) -{ - rcu_read_lock_trace(); - might_fault(); -} - -void notrace __bpf_prog_exit_sleepable(void) -{ - rcu_read_unlock_trace(); -} - -void notrace __bpf_tramp_enter(struct bpf_tramp_image *tr) -{ - percpu_ref_get(&tr->pcref); -} - -void notrace __bpf_tramp_exit(struct bpf_tramp_image *tr) -{ - percpu_ref_put(&tr->pcref); -} - -int __weak -arch_prepare_bpf_trampoline(struct bpf_tramp_image *tr, void *image, void *image_end, - const struct btf_func_model *m, u32 flags, - struct bpf_tramp_progs *tprogs, - void *orig_call) -{ - return -ENOTSUPP; -} - -static int __init init_trampolines(void) -{ - int i; - - for (i = 0; i < TRAMPOLINE_TABLE_SIZE; i++) - INIT_HLIST_HEAD(&trampoline_table[i]); - return 0; -} -late_initcall(init_trampolines); diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c index d467cd22efca..da2f54b02d81 100644 --- a/kernel/bpf/verifier.c +++ b/kernel/bpf/verifier.c @@ -19,21 +19,16 @@ #include #include #include -#include -#include -#include #include "disasm.h" static const struct bpf_verifier_ops * const bpf_verifier_ops[] = { -#define BPF_PROG_TYPE(_id, _name, prog_ctx_type, kern_ctx_type) \ +#define BPF_PROG_TYPE(_id, _name) \ [_id] = & _name ## _verifier_ops, #define BPF_MAP_TYPE(_id, _ops) -#define BPF_LINK_TYPE(_id, _name) #include #undef BPF_PROG_TYPE #undef BPF_MAP_TYPE -#undef BPF_LINK_TYPE }; /* bpf_check() is a static code analyzer that walks eBPF program @@ -171,16 +166,11 @@ struct bpf_verifier_stack_elem { int insn_idx; int prev_insn_idx; struct bpf_verifier_stack_elem *next; - /* length of verifier log at the time this state was pushed on stack */ - u32 log_pos; }; #define BPF_COMPLEXITY_LIMIT_JMP_SEQ 8192 #define BPF_COMPLEXITY_LIMIT_STATES 64 -#define BPF_MAP_KEY_POISON (1ULL << 63) -#define BPF_MAP_KEY_SEEN (1ULL << 62) - #define BPF_MAP_PTR_UNPRIV 1UL #define BPF_MAP_PTR_POISON ((void *)((0xeB9FUL << 1) + \ POISON_POINTER_DELTA)) @@ -188,12 +178,12 @@ struct bpf_verifier_stack_elem { static bool bpf_map_ptr_poisoned(const struct bpf_insn_aux_data *aux) { - return BPF_MAP_PTR(aux->map_ptr_state) == BPF_MAP_PTR_POISON; + return BPF_MAP_PTR(aux->map_state) == BPF_MAP_PTR_POISON; } static bool bpf_map_ptr_unpriv(const struct bpf_insn_aux_data *aux) { - return aux->map_ptr_state & BPF_MAP_PTR_UNPRIV; + return aux->map_state & BPF_MAP_PTR_UNPRIV; } static void bpf_map_ptr_store(struct bpf_insn_aux_data *aux, @@ -201,31 +191,8 @@ static void bpf_map_ptr_store(struct bpf_insn_aux_data *aux, { BUILD_BUG_ON((unsigned long)BPF_MAP_PTR_POISON & BPF_MAP_PTR_UNPRIV); unpriv |= bpf_map_ptr_unpriv(aux); - aux->map_ptr_state = (unsigned long)map | - (unpriv ? BPF_MAP_PTR_UNPRIV : 0UL); -} - -static bool bpf_map_key_poisoned(const struct bpf_insn_aux_data *aux) -{ - return aux->map_key_state & BPF_MAP_KEY_POISON; -} - -static bool bpf_map_key_unseen(const struct bpf_insn_aux_data *aux) -{ - return !(aux->map_key_state & BPF_MAP_KEY_SEEN); -} - -static u64 bpf_map_key_immediate(const struct bpf_insn_aux_data *aux) -{ - return aux->map_key_state & ~(BPF_MAP_KEY_SEEN | BPF_MAP_KEY_POISON); -} - -static void bpf_map_key_store(struct bpf_insn_aux_data *aux, u64 state) -{ - bool poisoned = bpf_map_key_poisoned(aux); - - aux->map_key_state = state | BPF_MAP_KEY_SEEN | - (poisoned ? BPF_MAP_KEY_POISON : 0ULL); + aux->map_state = (unsigned long)map | + (unpriv ? BPF_MAP_PTR_UNPRIV : 0UL); } struct bpf_call_arg_meta { @@ -234,16 +201,11 @@ struct bpf_call_arg_meta { bool pkt_access; int regno; int access_size; - int mem_size; u64 msize_max_value; int ref_obj_id; int func_id; - u32 btf_id; - u32 ret_btf_id; }; -struct btf *btf_vmlinux; - static DEFINE_MUTEX(bpf_verifier_lock); static const struct bpf_line_info * @@ -280,28 +242,12 @@ void bpf_verifier_vlog(struct bpf_verifier_log *log, const char *fmt, n = min(log->len_total - log->len_used - 1, n); log->kbuf[n] = '\0'; - if (log->level == BPF_LOG_KERNEL) { - pr_err("BPF:%s\n", log->kbuf); - return; - } if (!copy_to_user(log->ubuf + log->len_used, log->kbuf, n + 1)) log->len_used += n; else log->ubuf = NULL; } -static void bpf_vlog_reset(struct bpf_verifier_log *log, u32 new_pos) -{ - char zero = 0; - - if (!bpf_verifier_log_needed(log)) - return; - - log->len_used = new_pos; - if (put_user(zero, log->ubuf + new_pos)) - log->ubuf = NULL; -} - /* log_level controls verbosity level of eBPF verifier. * bpf_verifier_log_write() is used to dump the verification trace to the log, * so the user can figure out what's wrong with the program @@ -333,19 +279,6 @@ __printf(2, 3) static void verbose(void *private_data, const char *fmt, ...) va_end(args); } -__printf(2, 3) void bpf_log(struct bpf_verifier_log *log, - const char *fmt, ...) -{ - va_list args; - - if (!bpf_verifier_log_needed(log)) - return; - - va_start(args, fmt); - bpf_verifier_vlog(log, fmt, args); - va_end(args); -} - static const char *ltrim(const char *s) { while (isspace(*s)) @@ -396,24 +329,12 @@ static bool type_is_sk_pointer(enum bpf_reg_type type) type == PTR_TO_XDP_SOCK; } -static bool reg_type_not_null(enum bpf_reg_type type) -{ - return type == PTR_TO_SOCKET || - type == PTR_TO_TCP_SOCK || - type == PTR_TO_MAP_VALUE || - type == PTR_TO_SOCK_COMMON; -} - static bool reg_type_may_be_null(enum bpf_reg_type type) { return type == PTR_TO_MAP_VALUE_OR_NULL || type == PTR_TO_SOCKET_OR_NULL || type == PTR_TO_SOCK_COMMON_OR_NULL || - type == PTR_TO_TCP_SOCK_OR_NULL || - type == PTR_TO_BTF_ID_OR_NULL || - type == PTR_TO_MEM_OR_NULL || - type == PTR_TO_RDONLY_BUF_OR_NULL || - type == PTR_TO_RDWR_BUF_OR_NULL; + type == PTR_TO_TCP_SOCK_OR_NULL; } static bool reg_may_point_to_spin_lock(const struct bpf_reg_state *reg) @@ -427,9 +348,7 @@ static bool reg_type_may_be_refcounted_or_null(enum bpf_reg_type type) return type == PTR_TO_SOCKET || type == PTR_TO_SOCKET_OR_NULL || type == PTR_TO_TCP_SOCK || - type == PTR_TO_TCP_SOCK_OR_NULL || - type == PTR_TO_MEM || - type == PTR_TO_MEM_OR_NULL; + type == PTR_TO_TCP_SOCK_OR_NULL; } static bool arg_type_may_be_refcounted(enum bpf_arg_type type) @@ -437,63 +356,26 @@ static bool arg_type_may_be_refcounted(enum bpf_arg_type type) return type == ARG_PTR_TO_SOCK_COMMON; } -static bool arg_type_may_be_null(enum bpf_arg_type type) -{ - return type == ARG_PTR_TO_MAP_VALUE_OR_NULL || - type == ARG_PTR_TO_MEM_OR_NULL || - type == ARG_PTR_TO_CTX_OR_NULL || - type == ARG_PTR_TO_SOCKET_OR_NULL || - type == ARG_PTR_TO_ALLOC_MEM_OR_NULL; -} - /* Determine whether the function releases some resources allocated by another * function call. The first reference type argument will be assumed to be * released by release_reference(). */ static bool is_release_function(enum bpf_func_id func_id) { - return func_id == BPF_FUNC_sk_release || - func_id == BPF_FUNC_ringbuf_submit || - func_id == BPF_FUNC_ringbuf_discard; + return func_id == BPF_FUNC_sk_release; } -static bool may_be_acquire_function(enum bpf_func_id func_id) +static bool is_acquire_function(enum bpf_func_id func_id) { return func_id == BPF_FUNC_sk_lookup_tcp || func_id == BPF_FUNC_sk_lookup_udp || - func_id == BPF_FUNC_skc_lookup_tcp || - func_id == BPF_FUNC_map_lookup_elem || - func_id == BPF_FUNC_ringbuf_reserve; -} - -static bool is_acquire_function(enum bpf_func_id func_id, - const struct bpf_map *map) -{ - enum bpf_map_type map_type = map ? map->map_type : BPF_MAP_TYPE_UNSPEC; - - if (func_id == BPF_FUNC_sk_lookup_tcp || - func_id == BPF_FUNC_sk_lookup_udp || - func_id == BPF_FUNC_skc_lookup_tcp || - func_id == BPF_FUNC_ringbuf_reserve) - return true; - - if (func_id == BPF_FUNC_map_lookup_elem && - (map_type == BPF_MAP_TYPE_SOCKMAP || - map_type == BPF_MAP_TYPE_SOCKHASH)) - return true; - - return false; + func_id == BPF_FUNC_skc_lookup_tcp; } static bool is_ptr_cast_function(enum bpf_func_id func_id) { return func_id == BPF_FUNC_tcp_sock || - func_id == BPF_FUNC_sk_fullsock || - func_id == BPF_FUNC_skc_to_tcp_sock || - func_id == BPF_FUNC_skc_to_tcp6_sock || - func_id == BPF_FUNC_skc_to_udp6_sock || - func_id == BPF_FUNC_skc_to_tcp_timewait_sock || - func_id == BPF_FUNC_skc_to_tcp_request_sock; + func_id == BPF_FUNC_sk_fullsock; } /* string representation of 'enum bpf_reg_type' */ @@ -517,15 +399,6 @@ static const char * const reg_type_str[] = { [PTR_TO_TCP_SOCK_OR_NULL] = "tcp_sock_or_null", [PTR_TO_TP_BUFFER] = "tp_buffer", [PTR_TO_XDP_SOCK] = "xdp_sock", - [PTR_TO_BTF_ID] = "ptr_", - [PTR_TO_BTF_ID_OR_NULL] = "ptr_or_null_", - [PTR_TO_PERCPU_BTF_ID] = "percpu_ptr_", - [PTR_TO_MEM] = "mem", - [PTR_TO_MEM_OR_NULL] = "mem_or_null", - [PTR_TO_RDONLY_BUF] = "rdonly_buf", - [PTR_TO_RDONLY_BUF_OR_NULL] = "rdonly_buf_or_null", - [PTR_TO_RDWR_BUF] = "rdwr_buf", - [PTR_TO_RDWR_BUF_OR_NULL] = "rdwr_buf_or_null", }; static char slot_type_char[] = { @@ -556,26 +429,6 @@ static struct bpf_func_state *func(struct bpf_verifier_env *env, return cur->frame[reg->frameno]; } -const char *kernel_type_name(u32 id) -{ - return btf_name_by_offset(btf_vmlinux, - btf_type_by_id(btf_vmlinux, id)->name_off); -} - -/* The reg state of a pointer or a bounded scalar was saved when - * it was spilled to the stack. - */ -static bool is_spilled_reg(const struct bpf_stack_state *stack) -{ - return stack->slot_type[BPF_REG_SIZE - 1] == STACK_SPILL; -} - -static void scrub_spilled_slot(u8 *stype) -{ - if (*stype != STACK_INVALID) - *stype = STACK_MISC; -} - static void print_verifier_state(struct bpf_verifier_env *env, const struct bpf_func_state *state) { @@ -600,10 +453,6 @@ static void print_verifier_state(struct bpf_verifier_env *env, /* reg->off should be 0 for SCALAR_VALUE */ verbose(env, "%lld", reg->var_off.value + reg->off); } else { - if (t == PTR_TO_BTF_ID || - t == PTR_TO_BTF_ID_OR_NULL || - t == PTR_TO_PERCPU_BTF_ID) - verbose(env, "%s", kernel_type_name(reg->btf_id)); verbose(env, "(id=%d", reg->id); if (reg_type_may_be_refcounted_or_null(t)) verbose(env, ",ref_obj_id=%d", reg->ref_obj_id); @@ -644,22 +493,6 @@ static void print_verifier_state(struct bpf_verifier_env *env, tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); verbose(env, ",var_off=%s", tn_buf); } - if (reg->s32_min_value != reg->smin_value && - reg->s32_min_value != S32_MIN) - verbose(env, ",s32_min_value=%d", - (int)(reg->s32_min_value)); - if (reg->s32_max_value != reg->smax_value && - reg->s32_max_value != S32_MAX) - verbose(env, ",s32_max_value=%d", - (int)(reg->s32_max_value)); - if (reg->u32_min_value != reg->umin_value && - reg->u32_min_value != U32_MIN) - verbose(env, ",u32_min_value=%d", - (int)(reg->u32_min_value)); - if (reg->u32_max_value != reg->umax_value && - reg->u32_max_value != U32_MAX) - verbose(env, ",u32_max_value=%d", - (int)(reg->u32_max_value)); } verbose(env, ")"); } @@ -680,7 +513,7 @@ static void print_verifier_state(struct bpf_verifier_env *env, continue; verbose(env, " fp%d", (-i - 1) * BPF_REG_SIZE); print_liveness(env, state->stack[i].spilled_ptr.live); - if (is_spilled_reg(&state->stack[i])) { + if (state->stack[i].slot_type[0] == STACK_SPILL) { reg = &state->stack[i].spilled_ptr; t = reg->type; verbose(env, "=%s", reg_type_str[t]); @@ -940,7 +773,7 @@ static void update_branch_counts(struct bpf_verifier_env *env, struct bpf_verifi } static int pop_stack(struct bpf_verifier_env *env, int *prev_insn_idx, - int *insn_idx, bool pop_log) + int *insn_idx) { struct bpf_verifier_state *cur = env->cur_state; struct bpf_verifier_stack_elem *elem, *head = env->head; @@ -954,8 +787,6 @@ static int pop_stack(struct bpf_verifier_env *env, int *prev_insn_idx, if (err) return err; } - if (pop_log) - bpf_vlog_reset(&env->log, head->log_pos); if (insn_idx) *insn_idx = head->insn_idx; if (prev_insn_idx) @@ -983,7 +814,6 @@ static struct bpf_verifier_state *push_stack(struct bpf_verifier_env *env, elem->insn_idx = insn_idx; elem->prev_insn_idx = prev_insn_idx; elem->next = env->head; - elem->log_pos = env->log.len_used; env->head = elem; env->stack_size++; err = copy_verifier_state(&elem->st, cur); @@ -1012,7 +842,7 @@ err: free_verifier_state(env->cur_state, true); env->cur_state = NULL; /* pop all elements and return */ - while (!pop_stack(env, NULL, NULL, false)); + while (!pop_stack(env, NULL, NULL)); return NULL; } @@ -1024,21 +854,6 @@ static const int caller_saved[CALLER_SAVED_REGS] = { static void __mark_reg_not_init(const struct bpf_verifier_env *env, struct bpf_reg_state *reg); -/* This helper doesn't clear reg->id */ -static void ___mark_reg_known(struct bpf_reg_state *reg, u64 imm) -{ - reg->var_off = tnum_const(imm); - reg->smin_value = (s64)imm; - reg->smax_value = (s64)imm; - reg->umin_value = imm; - reg->umax_value = imm; - - reg->s32_min_value = (s32)imm; - reg->s32_max_value = (s32)imm; - reg->u32_min_value = (u32)imm; - reg->u32_max_value = (u32)imm; -} - /* Mark the unknown part of a register (variable offset or scalar value) as * known to have the value @imm. */ @@ -1047,16 +862,11 @@ static void __mark_reg_known(struct bpf_reg_state *reg, u64 imm) /* Clear id, off, and union(map_ptr, range) */ memset(((u8 *)reg) + sizeof(reg->type), 0, offsetof(struct bpf_reg_state, var_off) - sizeof(reg->type)); - ___mark_reg_known(reg, imm); -} - -static void __mark_reg32_known(struct bpf_reg_state *reg, u64 imm) -{ - reg->var_off = tnum_const_subreg(reg->var_off, imm); - reg->s32_min_value = (s32)imm; - reg->s32_max_value = (s32)imm; - reg->u32_min_value = (u32)imm; - reg->u32_max_value = (u32)imm; + reg->var_off = tnum_const(imm); + reg->smin_value = (s64)imm; + reg->smax_value = (s64)imm; + reg->umin_value = imm; + reg->umax_value = imm; } /* Mark the 'variable offset' part of a register as zero. This should be @@ -1111,52 +921,8 @@ static bool reg_is_init_pkt_pointer(const struct bpf_reg_state *reg, tnum_equals_const(reg->var_off, 0); } -/* Reset the min/max bounds of a register */ -static void __mark_reg_unbounded(struct bpf_reg_state *reg) -{ - reg->smin_value = S64_MIN; - reg->smax_value = S64_MAX; - reg->umin_value = 0; - reg->umax_value = U64_MAX; - - reg->s32_min_value = S32_MIN; - reg->s32_max_value = S32_MAX; - reg->u32_min_value = 0; - reg->u32_max_value = U32_MAX; -} - -static void __mark_reg64_unbounded(struct bpf_reg_state *reg) -{ - reg->smin_value = S64_MIN; - reg->smax_value = S64_MAX; - reg->umin_value = 0; - reg->umax_value = U64_MAX; -} - -static void __mark_reg32_unbounded(struct bpf_reg_state *reg) -{ - reg->s32_min_value = S32_MIN; - reg->s32_max_value = S32_MAX; - reg->u32_min_value = 0; - reg->u32_max_value = U32_MAX; -} - -static void __update_reg32_bounds(struct bpf_reg_state *reg) -{ - struct tnum var32_off = tnum_subreg(reg->var_off); - - /* min signed is max(sign bit) | min(other bits) */ - reg->s32_min_value = max_t(s32, reg->s32_min_value, - var32_off.value | (var32_off.mask & S32_MIN)); - /* max signed is min(sign bit) | max(other bits) */ - reg->s32_max_value = min_t(s32, reg->s32_max_value, - var32_off.value | (var32_off.mask & S32_MAX)); - reg->u32_min_value = max_t(u32, reg->u32_min_value, (u32)var32_off.value); - reg->u32_max_value = min(reg->u32_max_value, - (u32)(var32_off.value | var32_off.mask)); -} - -static void __update_reg64_bounds(struct bpf_reg_state *reg) +/* Attempts to improve min/max values based on var_off information */ +static void __update_reg_bounds(struct bpf_reg_state *reg) { /* min signed is max(sign bit) | min(other bits) */ reg->smin_value = max_t(s64, reg->smin_value, @@ -1169,48 +935,8 @@ static void __update_reg64_bounds(struct bpf_reg_state *reg) reg->var_off.value | reg->var_off.mask); } -static void __update_reg_bounds(struct bpf_reg_state *reg) -{ - __update_reg32_bounds(reg); - __update_reg64_bounds(reg); -} - /* Uses signed min/max values to inform unsigned, and vice-versa */ -static void __reg32_deduce_bounds(struct bpf_reg_state *reg) -{ - /* Learn sign from signed bounds. - * If we cannot cross the sign boundary, then signed and unsigned bounds - * are the same, so combine. This works even in the negative case, e.g. - * -3 s<= x s<= -1 implies 0xf...fd u<= x u<= 0xf...ff. - */ - if (reg->s32_min_value >= 0 || reg->s32_max_value < 0) { - reg->s32_min_value = reg->u32_min_value = - max_t(u32, reg->s32_min_value, reg->u32_min_value); - reg->s32_max_value = reg->u32_max_value = - min_t(u32, reg->s32_max_value, reg->u32_max_value); - return; - } - /* Learn sign from unsigned bounds. Signed bounds cross the sign - * boundary, so we must be careful. - */ - if ((s32)reg->u32_max_value >= 0) { - /* Positive. We can't learn anything from the smin, but smax - * is positive, hence safe. - */ - reg->s32_min_value = reg->u32_min_value; - reg->s32_max_value = reg->u32_max_value = - min_t(u32, reg->s32_max_value, reg->u32_max_value); - } else if ((s32)reg->u32_min_value < 0) { - /* Negative. We can't learn anything from the smax, but smin - * is negative, hence safe. - */ - reg->s32_min_value = reg->u32_min_value = - max_t(u32, reg->s32_min_value, reg->u32_min_value); - reg->s32_max_value = reg->u32_max_value; - } -} - -static void __reg64_deduce_bounds(struct bpf_reg_state *reg) +static void __reg_deduce_bounds(struct bpf_reg_state *reg) { /* Learn sign from signed bounds. * If we cannot cross the sign boundary, then signed and unsigned bounds @@ -1244,107 +970,21 @@ static void __reg64_deduce_bounds(struct bpf_reg_state *reg) } } -static void __reg_deduce_bounds(struct bpf_reg_state *reg) -{ - __reg32_deduce_bounds(reg); - __reg64_deduce_bounds(reg); -} - /* Attempts to improve var_off based on unsigned min/max information */ static void __reg_bound_offset(struct bpf_reg_state *reg) { - struct tnum var64_off = tnum_intersect(reg->var_off, - tnum_range(reg->umin_value, - reg->umax_value)); - struct tnum var32_off = tnum_intersect(tnum_subreg(reg->var_off), - tnum_range(reg->u32_min_value, - reg->u32_max_value)); - - reg->var_off = tnum_or(tnum_clear_subreg(var64_off), var32_off); + reg->var_off = tnum_intersect(reg->var_off, + tnum_range(reg->umin_value, + reg->umax_value)); } -static void reg_bounds_sync(struct bpf_reg_state *reg) +/* Reset the min/max bounds of a register */ +static void __mark_reg_unbounded(struct bpf_reg_state *reg) { - /* We might have learned new bounds from the var_off. */ - __update_reg_bounds(reg); - /* We might have learned something about the sign bit. */ - __reg_deduce_bounds(reg); - /* We might have learned some bits from the bounds. */ - __reg_bound_offset(reg); - /* Intersecting with the old var_off might have improved our bounds - * slightly, e.g. if umax was 0x7f...f and var_off was (0; 0xf...fc), - * then new var_off is (0; 0x7f...fc) which improves our umax. - */ - __update_reg_bounds(reg); -} - -static bool __reg32_bound_s64(s32 a) -{ - return a >= 0 && a <= S32_MAX; -} - -static void __reg_assign_32_into_64(struct bpf_reg_state *reg) -{ - reg->umin_value = reg->u32_min_value; - reg->umax_value = reg->u32_max_value; - - /* Attempt to pull 32-bit signed bounds into 64-bit bounds but must - * be positive otherwise set to worse case bounds and refine later - * from tnum. - */ - if (__reg32_bound_s64(reg->s32_min_value) && - __reg32_bound_s64(reg->s32_max_value)) { - reg->smin_value = reg->s32_min_value; - reg->smax_value = reg->s32_max_value; - } else { - reg->smin_value = 0; - reg->smax_value = U32_MAX; - } -} - -static void __reg_combine_32_into_64(struct bpf_reg_state *reg) -{ - /* special case when 64-bit register has upper 32-bit register - * zeroed. Typically happens after zext or <<32, >>32 sequence - * allowing us to use 32-bit bounds directly, - */ - if (tnum_equals_const(tnum_clear_subreg(reg->var_off), 0)) { - __reg_assign_32_into_64(reg); - } else { - /* Otherwise the best we can do is push lower 32bit known and - * unknown bits into register (var_off set from jmp logic) - * then learn as much as possible from the 64-bit tnum - * known and unknown bits. The previous smin/smax bounds are - * invalid here because of jmp32 compare so mark them unknown - * so they do not impact tnum bounds calculation. - */ - __mark_reg64_unbounded(reg); - } - reg_bounds_sync(reg); -} - -static bool __reg64_bound_s32(s64 a) -{ - return a >= S32_MIN && a <= S32_MAX; -} - -static bool __reg64_bound_u32(u64 a) -{ - return a >= U32_MIN && a <= U32_MAX; -} - -static void __reg_combine_64_into_32(struct bpf_reg_state *reg) -{ - __mark_reg32_unbounded(reg); - if (__reg64_bound_s32(reg->smin_value) && __reg64_bound_s32(reg->smax_value)) { - reg->s32_min_value = (s32)reg->smin_value; - reg->s32_max_value = (s32)reg->smax_value; - } - if (__reg64_bound_u32(reg->umin_value) && __reg64_bound_u32(reg->umax_value)) { - reg->u32_min_value = (u32)reg->umin_value; - reg->u32_max_value = (u32)reg->umax_value; - } - reg_bounds_sync(reg); + reg->smin_value = S64_MIN; + reg->smax_value = S64_MAX; + reg->umin_value = 0; + reg->umax_value = U64_MAX; } /* Mark a register as having a completely unknown (scalar) value. */ @@ -1359,7 +999,8 @@ static void __mark_reg_unknown(const struct bpf_verifier_env *env, reg->type = SCALAR_VALUE; reg->var_off = tnum_unknown; reg->frameno = 0; - reg->precise = !env->bpf_capable; + reg->precise = env->subprog_cnt > 1 || !env->allow_ptr_leaks ? + true : false; __mark_reg_unbounded(reg); } @@ -1396,19 +1037,6 @@ static void mark_reg_not_init(struct bpf_verifier_env *env, __mark_reg_not_init(env, regs + regno); } -static void mark_btf_ld_reg(struct bpf_verifier_env *env, - struct bpf_reg_state *regs, u32 regno, - enum bpf_reg_type reg_type, u32 btf_id) -{ - if (reg_type == SCALAR_VALUE) { - mark_reg_unknown(env, regs, regno); - return; - } - mark_reg_known_zero(env, regs, regno); - regs[regno].type = PTR_TO_BTF_ID; - regs[regno].btf_id = btf_id; -} - #define DEF_NOT_SUBREG (0) static void init_reg_state(struct bpf_verifier_env *env, struct bpf_func_state *state) @@ -1427,6 +1055,10 @@ static void init_reg_state(struct bpf_verifier_env *env, regs[BPF_REG_FP].type = PTR_TO_STACK; mark_reg_known_zero(env, regs, BPF_REG_FP); regs[BPF_REG_FP].frameno = state->frameno; + + /* 1st arg to a function */ + regs[BPF_REG_1].type = PTR_TO_CTX; + mark_reg_known_zero(env, regs, BPF_REG_1); } #define BPF_MAIN_FUNC (-1) @@ -1504,9 +1136,8 @@ static int check_subprogs(struct bpf_verifier_env *env) continue; if (insn[i].src_reg != BPF_PSEUDO_CALL) continue; - if (!env->bpf_capable) { - verbose(env, - "function calls to other bpf functions are allowed for CAP_BPF and CAP_SYS_ADMIN\n"); + if (!env->allow_ptr_leaks) { + verbose(env, "function calls to other bpf functions are allowed for root only\n"); return -EPERM; } ret = add_subprog(env, i + insn[i].imm + 1); @@ -1533,9 +1164,6 @@ static int check_subprogs(struct bpf_verifier_env *env) insn[i].imm == BPF_FUNC_tail_call && insn[i].src_reg != BPF_PSEUDO_CALL) subprog[cur_subprog].has_tail_call = true; - if (BPF_CLASS(code) == BPF_LD && - (BPF_MODE(code) == BPF_ABS || BPF_MODE(code) == BPF_IND)) - subprog[cur_subprog].has_ld_abs = true; if (BPF_CLASS(code) != BPF_JMP && BPF_CLASS(code) != BPF_JMP32) goto next; if (BPF_OP(code) == BPF_EXIT || BPF_OP(code) == BPF_CALL) @@ -1796,29 +1424,12 @@ static int push_jmp_history(struct bpf_verifier_env *env, /* Backtrack one insn at a time. If idx is not at the top of recorded * history then previous instruction came from straight line execution. - * Return -ENOENT if we exhausted all instructions within given state. - * - * It's legal to have a bit of a looping with the same starting and ending - * insn index within the same state, e.g.: 3->4->5->3, so just because current - * instruction index is the same as state's first_idx doesn't mean we are - * done. If there is still some jump history left, we should keep going. We - * need to take into account that we might have a jump history between given - * state's parent and itself, due to checkpointing. In this case, we'll have - * history entry recording a jump from last instruction of parent state and - * first instruction of given state. */ static int get_prev_insn_idx(struct bpf_verifier_state *st, int i, u32 *history) { u32 cnt = *history; - if (i == st->first_insn_idx) { - if (cnt == 0) - return -ENOENT; - if (cnt == 1 && st->jmp_history[0].idx == i) - return -ENOENT; - } - if (cnt && st->jmp_history[cnt - 1].idx == i) { i = st->jmp_history[cnt - 1].prev_idx; (*history)--; @@ -1904,6 +1515,8 @@ static int backtrack_insn(struct bpf_verifier_env *env, int idx, */ if (insn->src_reg != BPF_REG_FP) return 0; + if (BPF_SIZE(insn->code) != BPF_DW) + return 0; /* dreg = *(u64 *)[fp - off] was a fill from the stack. * that [fp - off] slot contains scalar that needs to be @@ -1926,6 +1539,8 @@ static int backtrack_insn(struct bpf_verifier_env *env, int idx, /* scalars can only be spilled into stack */ if (insn->dst_reg != BPF_REG_FP) return 0; + if (BPF_SIZE(insn->code) != BPF_DW) + return 0; spi = (-insn->off - 1) / BPF_REG_SIZE; if (spi >= 64) { verbose(env, "BUG spi %d\n", spi); @@ -2045,11 +1660,8 @@ static void mark_all_scalars_precise(struct bpf_verifier_env *env, /* big hammer: mark all scalars precise in this path. * pop_stack may still get !precise scalars. - * We also skip current state and go straight to first parent state, - * because precision markings in current non-checkpointed state are - * not needed. See why in the comment in __mark_chain_precision below. */ - for (st = st->parent; st; st = st->parent) { + for (; st; st = st->parent) for (i = 0; i <= st->curframe; i++) { func = st->frame[i]; for (j = 0; j < BPF_REG_FP; j++) { @@ -2059,7 +1671,7 @@ static void mark_all_scalars_precise(struct bpf_verifier_env *env, reg->precise = true; } for (j = 0; j < func->allocated_stack / BPF_REG_SIZE; j++) { - if (!is_spilled_reg(&func->stack[j])) + if (func->stack[j].slot_type[0] != STACK_SPILL) continue; reg = &func->stack[j].spilled_ptr; if (reg->type != SCALAR_VALUE) @@ -2067,122 +1679,9 @@ static void mark_all_scalars_precise(struct bpf_verifier_env *env, reg->precise = true; } } - } } -static void mark_all_scalars_imprecise(struct bpf_verifier_env *env, struct bpf_verifier_state *st) -{ - struct bpf_func_state *func; - struct bpf_reg_state *reg; - int i, j; - - for (i = 0; i <= st->curframe; i++) { - func = st->frame[i]; - for (j = 0; j < BPF_REG_FP; j++) { - reg = &func->regs[j]; - if (reg->type != SCALAR_VALUE) - continue; - reg->precise = false; - } - for (j = 0; j < func->allocated_stack / BPF_REG_SIZE; j++) { - if (!is_spilled_reg(&func->stack[j])) - continue; - reg = &func->stack[j].spilled_ptr; - if (reg->type != SCALAR_VALUE) - continue; - reg->precise = false; - } - } -} - -/* - * __mark_chain_precision() backtracks BPF program instruction sequence and - * chain of verifier states making sure that register *regno* (if regno >= 0) - * and/or stack slot *spi* (if spi >= 0) are marked as precisely tracked - * SCALARS, as well as any other registers and slots that contribute to - * a tracked state of given registers/stack slots, depending on specific BPF - * assembly instructions (see backtrack_insns() for exact instruction handling - * logic). This backtracking relies on recorded jmp_history and is able to - * traverse entire chain of parent states. This process ends only when all the - * necessary registers/slots and their transitive dependencies are marked as - * precise. - * - * One important and subtle aspect is that precise marks *do not matter* in - * the currently verified state (current state). It is important to understand - * why this is the case. - * - * First, note that current state is the state that is not yet "checkpointed", - * i.e., it is not yet put into env->explored_states, and it has no children - * states as well. It's ephemeral, and can end up either a) being discarded if - * compatible explored state is found at some point or BPF_EXIT instruction is - * reached or b) checkpointed and put into env->explored_states, branching out - * into one or more children states. - * - * In the former case, precise markings in current state are completely - * ignored by state comparison code (see regsafe() for details). Only - * checkpointed ("old") state precise markings are important, and if old - * state's register/slot is precise, regsafe() assumes current state's - * register/slot as precise and checks value ranges exactly and precisely. If - * states turn out to be compatible, current state's necessary precise - * markings and any required parent states' precise markings are enforced - * after the fact with propagate_precision() logic, after the fact. But it's - * important to realize that in this case, even after marking current state - * registers/slots as precise, we immediately discard current state. So what - * actually matters is any of the precise markings propagated into current - * state's parent states, which are always checkpointed (due to b) case above). - * As such, for scenario a) it doesn't matter if current state has precise - * markings set or not. - * - * Now, for the scenario b), checkpointing and forking into child(ren) - * state(s). Note that before current state gets to checkpointing step, any - * processed instruction always assumes precise SCALAR register/slot - * knowledge: if precise value or range is useful to prune jump branch, BPF - * verifier takes this opportunity enthusiastically. Similarly, when - * register's value is used to calculate offset or memory address, exact - * knowledge of SCALAR range is assumed, checked, and enforced. So, similar to - * what we mentioned above about state comparison ignoring precise markings - * during state comparison, BPF verifier ignores and also assumes precise - * markings *at will* during instruction verification process. But as verifier - * assumes precision, it also propagates any precision dependencies across - * parent states, which are not yet finalized, so can be further restricted - * based on new knowledge gained from restrictions enforced by their children - * states. This is so that once those parent states are finalized, i.e., when - * they have no more active children state, state comparison logic in - * is_state_visited() would enforce strict and precise SCALAR ranges, if - * required for correctness. - * - * To build a bit more intuition, note also that once a state is checkpointed, - * the path we took to get to that state is not important. This is crucial - * property for state pruning. When state is checkpointed and finalized at - * some instruction index, it can be correctly and safely used to "short - * circuit" any *compatible* state that reaches exactly the same instruction - * index. I.e., if we jumped to that instruction from a completely different - * code path than original finalized state was derived from, it doesn't - * matter, current state can be discarded because from that instruction - * forward having a compatible state will ensure we will safely reach the - * exit. States describe preconditions for further exploration, but completely - * forget the history of how we got here. - * - * This also means that even if we needed precise SCALAR range to get to - * finalized state, but from that point forward *that same* SCALAR register is - * never used in a precise context (i.e., it's precise value is not needed for - * correctness), it's correct and safe to mark such register as "imprecise" - * (i.e., precise marking set to false). This is what we rely on when we do - * not set precise marking in current state. If no child state requires - * precision for any given SCALAR register, it's safe to dictate that it can - * be imprecise. If any child state does require this register to be precise, - * we'll mark it precise later retroactively during precise markings - * propagation from child state to parent states. - * - * Skipping precise marking setting in current state is a mild version of - * relying on the above observation. But we can utilize this property even - * more aggressively by proactively forgetting any precise marking in the - * current state (which we inherited from the parent state), right before we - * checkpoint it and branch off into new child state. This is done by - * mark_all_scalars_imprecise() to hopefully get more permissive and generic - * finalized states which help in short circuiting more future states. - */ -static int __mark_chain_precision(struct bpf_verifier_env *env, int frame, int regno, +static int __mark_chain_precision(struct bpf_verifier_env *env, int regno, int spi) { struct bpf_verifier_state *st = env->cur_state; @@ -2196,25 +1695,26 @@ static int __mark_chain_precision(struct bpf_verifier_env *env, int frame, int r bool new_marks = false; int i, err; - if (!env->bpf_capable) + if (!env->allow_ptr_leaks) + /* backtracking is root only for now */ return 0; - /* Do sanity checks against current state of register and/or stack - * slot, but don't set precise flag in current state, as precision - * tracking in the current state is unnecessary. - */ - func = st->frame[frame]; + func = st->frame[st->curframe]; if (regno >= 0) { reg = &func->regs[regno]; if (reg->type != SCALAR_VALUE) { WARN_ONCE(1, "backtracing misuse"); return -EFAULT; } - new_marks = true; + if (!reg->precise) + new_marks = true; + else + reg_mask = 0; + reg->precise = true; } while (spi >= 0) { - if (!is_spilled_reg(&func->stack[spi])) { + if (func->stack[spi].slot_type[0] != STACK_SPILL) { stack_mask = 0; break; } @@ -2223,7 +1723,11 @@ static int __mark_chain_precision(struct bpf_verifier_env *env, int frame, int r stack_mask = 0; break; } - new_marks = true; + if (!reg->precise) + new_marks = true; + else + stack_mask = 0; + reg->precise = true; break; } @@ -2231,42 +1735,12 @@ static int __mark_chain_precision(struct bpf_verifier_env *env, int frame, int r return 0; if (!reg_mask && !stack_mask) return 0; - for (;;) { DECLARE_BITMAP(mask, 64); u32 history = st->jmp_history_cnt; if (env->log.level & BPF_LOG_LEVEL) verbose(env, "last_idx %d first_idx %d\n", last_idx, first_idx); - - if (last_idx < 0) { - /* we are at the entry into subprog, which - * is expected for global funcs, but only if - * requested precise registers are R1-R5 - * (which are global func's input arguments) - */ - if (st->curframe == 0 && - st->frame[0]->subprogno > 0 && - st->frame[0]->callsite == BPF_MAIN_FUNC && - stack_mask == 0 && (reg_mask & ~0x3e) == 0) { - bitmap_from_u64(mask, reg_mask); - for_each_set_bit(i, mask, 32) { - reg = &st->frame[0]->regs[i]; - if (reg->type != SCALAR_VALUE) { - reg_mask &= ~(1u << i); - continue; - } - reg->precise = true; - } - return 0; - } - - verbose(env, "BUG backtracing func entry subprog %d reg_mask %x stack_mask %llx\n", - st->frame[0]->subprogno, reg_mask, stack_mask); - WARN_ONCE(1, "verifier backtracking bug"); - return -EFAULT; - } - for (i = last_idx;;) { if (skip_first) { err = 0; @@ -2286,9 +1760,9 @@ static int __mark_chain_precision(struct bpf_verifier_env *env, int frame, int r * Nothing to be tracked further in the parent state. */ return 0; - i = get_prev_insn_idx(st, i, &history); - if (i == -ENOENT) + if (i == first_idx) break; + i = get_prev_insn_idx(st, i, &history); if (i >= env->prog->len) { /* This can happen if backtracking reached insn 0 * and there are still reg_mask or stack_mask @@ -2306,7 +1780,7 @@ static int __mark_chain_precision(struct bpf_verifier_env *env, int frame, int r break; new_marks = false; - func = st->frame[frame]; + func = st->frame[st->curframe]; bitmap_from_u64(mask, reg_mask); for_each_set_bit(i, mask, 32) { reg = &func->regs[i]; @@ -2339,7 +1813,7 @@ static int __mark_chain_precision(struct bpf_verifier_env *env, int frame, int r return 0; } - if (!is_spilled_reg(&func->stack[i])) { + if (func->stack[i].slot_type[0] != STACK_SPILL) { stack_mask &= ~(1ull << i); continue; } @@ -2372,17 +1846,12 @@ static int __mark_chain_precision(struct bpf_verifier_env *env, int frame, int r static int mark_chain_precision(struct bpf_verifier_env *env, int regno) { - return __mark_chain_precision(env, env->cur_state->curframe, regno, -1); + return __mark_chain_precision(env, regno, -1); } -static int mark_chain_precision_frame(struct bpf_verifier_env *env, int frame, int regno) +static int mark_chain_precision_stack(struct bpf_verifier_env *env, int spi) { - return __mark_chain_precision(env, frame, regno, -1); -} - -static int mark_chain_precision_stack_frame(struct bpf_verifier_env *env, int frame, int spi) -{ - return __mark_chain_precision(env, frame, -1, spi); + return __mark_chain_precision(env, -1, spi); } static bool is_spillable_regtype(enum bpf_reg_type type) @@ -2404,15 +1873,6 @@ static bool is_spillable_regtype(enum bpf_reg_type type) case PTR_TO_TCP_SOCK: case PTR_TO_TCP_SOCK_OR_NULL: case PTR_TO_XDP_SOCK: - case PTR_TO_BTF_ID: - case PTR_TO_BTF_ID_OR_NULL: - case PTR_TO_RDONLY_BUF: - case PTR_TO_RDONLY_BUF_OR_NULL: - case PTR_TO_RDWR_BUF: - case PTR_TO_RDWR_BUF_OR_NULL: - case PTR_TO_PERCPU_BTF_ID: - case PTR_TO_MEM: - case PTR_TO_MEM_OR_NULL: return true; default: return false; @@ -2430,20 +1890,6 @@ static bool register_is_const(struct bpf_reg_state *reg) return reg->type == SCALAR_VALUE && tnum_is_const(reg->var_off); } -static bool __is_scalar_unbounded(struct bpf_reg_state *reg) -{ - return tnum_is_unknown(reg->var_off) && - reg->smin_value == S64_MIN && reg->smax_value == S64_MAX && - reg->umin_value == 0 && reg->umax_value == U64_MAX && - reg->s32_min_value == S32_MIN && reg->s32_max_value == S32_MAX && - reg->u32_min_value == 0 && reg->u32_max_value == U32_MAX; -} - -static bool register_is_bounded(struct bpf_reg_state *reg) -{ - return reg->type == SCALAR_VALUE && !__is_scalar_unbounded(reg); -} - static bool __is_pointer_value(bool allow_ptr_leaks, const struct bpf_reg_state *reg) { @@ -2453,54 +1899,29 @@ static bool __is_pointer_value(bool allow_ptr_leaks, return reg->type != SCALAR_VALUE; } -/* Copy src state preserving dst->parent and dst->live fields */ -static void copy_register_state(struct bpf_reg_state *dst, const struct bpf_reg_state *src) -{ - struct bpf_reg_state *parent = dst->parent; - enum bpf_reg_liveness live = dst->live; - - *dst = *src; - dst->parent = parent; - dst->live = live; -} - static void save_register_state(struct bpf_func_state *state, - int spi, struct bpf_reg_state *reg, - int size) + int spi, struct bpf_reg_state *reg) { int i; - copy_register_state(&state->stack[spi].spilled_ptr, reg); - if (size == BPF_REG_SIZE) - state->stack[spi].spilled_ptr.live |= REG_LIVE_WRITTEN; + state->stack[spi].spilled_ptr = *reg; + state->stack[spi].spilled_ptr.live |= REG_LIVE_WRITTEN; - for (i = BPF_REG_SIZE; i > BPF_REG_SIZE - size; i--) - state->stack[spi].slot_type[i - 1] = STACK_SPILL; - - /* size < 8 bytes spill */ - for (; i; i--) - scrub_spilled_slot(&state->stack[spi].slot_type[i - 1]); + for (i = 0; i < BPF_REG_SIZE; i++) + state->stack[spi].slot_type[i] = STACK_SPILL; } -static bool is_bpf_st_mem(struct bpf_insn *insn) -{ - return BPF_CLASS(insn->code) == BPF_ST && BPF_MODE(insn->code) == BPF_MEM; -} - -/* check_stack_{read,write}_fixed_off functions track spill/fill of registers, +/* check_stack_read/write functions track spill/fill of registers, * stack boundary and alignment are checked in check_mem_access() */ -static int check_stack_write_fixed_off(struct bpf_verifier_env *env, - /* stack frame we're writing to */ - struct bpf_func_state *state, - int off, int size, int value_regno, - int insn_idx) +static int check_stack_write(struct bpf_verifier_env *env, + struct bpf_func_state *state, /* func where register points to */ + int off, int size, int value_regno, int insn_idx) { struct bpf_func_state *cur; /* state of the current function */ int i, slot = -off - 1, spi = slot / BPF_REG_SIZE, err; - struct bpf_insn *insn = &env->prog->insnsi[insn_idx]; + u32 dst_reg = env->prog->insnsi[insn_idx].dst_reg; struct bpf_reg_state *reg = NULL; - u32 dst_reg = insn->dst_reg; err = realloc_func_state(state, round_up(slot + 1, BPF_REG_SIZE), state->acquired_refs, true); @@ -2510,7 +1931,7 @@ static int check_stack_write_fixed_off(struct bpf_verifier_env *env, * so it's aligned access and [off, off + size) are within stack limits */ if (!env->allow_ptr_leaks && - is_spilled_reg(&state->stack[spi]) && + state->stack[spi].slot_type[0] == STACK_SPILL && size != BPF_REG_SIZE) { verbose(env, "attempt to corrupt spilled pointer on stack\n"); return -EACCES; @@ -2519,7 +1940,7 @@ static int check_stack_write_fixed_off(struct bpf_verifier_env *env, cur = env->cur_state->frame[env->cur_state->curframe]; if (value_regno >= 0) reg = &cur->regs[value_regno]; - if (!env->bypass_spec_v4) { + if (!env->allow_ptr_leaks) { bool sanitize = reg && is_spillable_regtype(reg->type); for (i = 0; i < size; i++) { @@ -2535,8 +1956,8 @@ static int check_stack_write_fixed_off(struct bpf_verifier_env *env, env->insn_aux_data[insn_idx].sanitize_stack_spill = true; } - if (reg && !(off % BPF_REG_SIZE) && register_is_bounded(reg) && - !register_is_null(reg) && env->bpf_capable) { + if (reg && size == BPF_REG_SIZE && register_is_const(reg) && + !register_is_null(reg) && env->allow_ptr_leaks) { if (dst_reg != BPF_REG_FP) { /* The backtracking logic can only recognize explicit * stack slot address like [fp - 8]. Other spill of @@ -2548,17 +1969,7 @@ static int check_stack_write_fixed_off(struct bpf_verifier_env *env, if (err) return err; } - save_register_state(state, spi, reg, size); - /* Break the relation on a narrowing spill. */ - if (fls64(reg->umax_value) > BITS_PER_BYTE * size) - state->stack[spi].spilled_ptr.id = 0; - } else if (!reg && !(off % BPF_REG_SIZE) && is_bpf_st_mem(insn) && - insn->imm != 0 && env->bpf_capable) { - struct bpf_reg_state fake_reg = {}; - - __mark_reg_known(&fake_reg, insn->imm); - fake_reg.type = SCALAR_VALUE; - save_register_state(state, spi, &fake_reg, size); + save_register_state(state, spi, reg); } else if (reg && is_spillable_regtype(reg->type)) { /* register containing pointer is being spilled into stack */ if (size != BPF_REG_SIZE) { @@ -2570,16 +1981,16 @@ static int check_stack_write_fixed_off(struct bpf_verifier_env *env, verbose(env, "cannot spill pointers to stack into stack frame of the caller\n"); return -EINVAL; } - save_register_state(state, spi, reg, size); + save_register_state(state, spi, reg); } else { u8 type = STACK_MISC; /* regular write of data into stack destroys any spilled ptr */ state->stack[spi].spilled_ptr.type = NOT_INIT; /* Mark slots as STACK_MISC if they belonged to spilled ptr. */ - if (is_spilled_reg(&state->stack[spi])) + if (state->stack[spi].slot_type[0] == STACK_SPILL) for (i = 0; i < BPF_REG_SIZE; i++) - scrub_spilled_slot(&state->stack[spi].slot_type[i]); + state->stack[spi].slot_type[i] = STACK_MISC; /* only mark the slot as written if all 8 bytes were written * otherwise read propagation may incorrectly stop too soon @@ -2593,8 +2004,7 @@ static int check_stack_write_fixed_off(struct bpf_verifier_env *env, state->stack[spi].spilled_ptr.live |= REG_LIVE_WRITTEN; /* when we zero initialize stack slots mark them as such */ - if ((reg && register_is_null(reg)) || - (!reg && is_bpf_st_mem(insn) && insn->imm == 0)) { + if (reg && register_is_null(reg)) { /* backtracking doesn't work for STACK_ZERO yet. */ err = mark_chain_precision(env, value_regno); if (err) @@ -2610,242 +2020,55 @@ static int check_stack_write_fixed_off(struct bpf_verifier_env *env, return 0; } -/* Write the stack: 'stack[ptr_regno + off] = value_regno'. 'ptr_regno' is - * known to contain a variable offset. - * This function checks whether the write is permitted and conservatively - * tracks the effects of the write, considering that each stack slot in the - * dynamic range is potentially written to. - * - * 'off' includes 'regno->off'. - * 'value_regno' can be -1, meaning that an unknown value is being written to - * the stack. - * - * Spilled pointers in range are not marked as written because we don't know - * what's going to be actually written. This means that read propagation for - * future reads cannot be terminated by this write. - * - * For privileged programs, uninitialized stack slots are considered - * initialized by this write (even though we don't know exactly what offsets - * are going to be written to). The idea is that we don't want the verifier to - * reject future reads that access slots written to through variable offsets. - */ -static int check_stack_write_var_off(struct bpf_verifier_env *env, - /* func where register points to */ - struct bpf_func_state *state, - int ptr_regno, int off, int size, - int value_regno, int insn_idx) -{ - struct bpf_func_state *cur; /* state of the current function */ - int min_off, max_off; - int i, err; - struct bpf_reg_state *ptr_reg = NULL, *value_reg = NULL; - bool writing_zero = false; - /* set if the fact that we're writing a zero is used to let any - * stack slots remain STACK_ZERO - */ - bool zero_used = false; - - cur = env->cur_state->frame[env->cur_state->curframe]; - ptr_reg = &cur->regs[ptr_regno]; - min_off = ptr_reg->smin_value + off; - max_off = ptr_reg->smax_value + off + size; - if (value_regno >= 0) - value_reg = &cur->regs[value_regno]; - if (value_reg && register_is_null(value_reg)) - writing_zero = true; - - err = realloc_func_state(state, round_up(-min_off, BPF_REG_SIZE), - state->acquired_refs, true); - if (err) - return err; - - - /* Variable offset writes destroy any spilled pointers in range. */ - for (i = min_off; i < max_off; i++) { - u8 new_type, *stype; - int slot, spi; - - slot = -i - 1; - spi = slot / BPF_REG_SIZE; - stype = &state->stack[spi].slot_type[slot % BPF_REG_SIZE]; - - if (!env->allow_ptr_leaks && *stype != STACK_MISC && *stype != STACK_ZERO) { - /* Reject the write if range we may write to has not - * been initialized beforehand. If we didn't reject - * here, the ptr status would be erased below (even - * though not all slots are actually overwritten), - * possibly opening the door to leaks. - * - * We do however catch STACK_INVALID case below, and - * only allow reading possibly uninitialized memory - * later for CAP_PERFMON, as the write may not happen to - * that slot. - */ - verbose(env, "spilled ptr in range of var-offset stack write; insn %d, ptr off: %d", - insn_idx, i); - return -EINVAL; - } - - /* Erase all spilled pointers. */ - state->stack[spi].spilled_ptr.type = NOT_INIT; - - /* Update the slot type. */ - new_type = STACK_MISC; - if (writing_zero && *stype == STACK_ZERO) { - new_type = STACK_ZERO; - zero_used = true; - } - /* If the slot is STACK_INVALID, we check whether it's OK to - * pretend that it will be initialized by this write. The slot - * might not actually be written to, and so if we mark it as - * initialized future reads might leak uninitialized memory. - * For privileged programs, we will accept such reads to slots - * that may or may not be written because, if we're reject - * them, the error would be too confusing. - */ - if (*stype == STACK_INVALID && !env->allow_uninit_stack) { - verbose(env, "uninit stack in range of var-offset write prohibited for !root; insn %d, off: %d", - insn_idx, i); - return -EINVAL; - } - *stype = new_type; - } - if (zero_used) { - /* backtracking doesn't work for STACK_ZERO yet. */ - err = mark_chain_precision(env, value_regno); - if (err) - return err; - } - return 0; -} - -/* When register 'dst_regno' is assigned some values from stack[min_off, - * max_off), we set the register's type according to the types of the - * respective stack slots. If all the stack values are known to be zeros, then - * so is the destination reg. Otherwise, the register is considered to be - * SCALAR. This function does not deal with register filling; the caller must - * ensure that all spilled registers in the stack range have been marked as - * read. - */ -static void mark_reg_stack_read(struct bpf_verifier_env *env, - /* func where src register points to */ - struct bpf_func_state *ptr_state, - int min_off, int max_off, int dst_regno) -{ - struct bpf_verifier_state *vstate = env->cur_state; - struct bpf_func_state *state = vstate->frame[vstate->curframe]; - int i, slot, spi; - u8 *stype; - int zeros = 0; - - for (i = min_off; i < max_off; i++) { - slot = -i - 1; - spi = slot / BPF_REG_SIZE; - stype = ptr_state->stack[spi].slot_type; - if (stype[slot % BPF_REG_SIZE] != STACK_ZERO) - break; - zeros++; - } - if (zeros == max_off - min_off) { - /* any access_size read into register is zero extended, - * so the whole register == const_zero - */ - __mark_reg_const_zero(&state->regs[dst_regno]); - /* backtracking doesn't support STACK_ZERO yet, - * so mark it precise here, so that later - * backtracking can stop here. - * Backtracking may not need this if this register - * doesn't participate in pointer adjustment. - * Forward propagation of precise flag is not - * necessary either. This mark is only to stop - * backtracking. Any register that contributed - * to const 0 was marked precise before spill. - */ - state->regs[dst_regno].precise = true; - } else { - /* have read misc data from the stack */ - mark_reg_unknown(env, state->regs, dst_regno); - } - state->regs[dst_regno].live |= REG_LIVE_WRITTEN; -} - -/* Read the stack at 'off' and put the results into the register indicated by - * 'dst_regno'. It handles reg filling if the addressed stack slot is a - * spilled reg. - * - * 'dst_regno' can be -1, meaning that the read value is not going to a - * register. - * - * The access is assumed to be within the current stack bounds. - */ -static int check_stack_read_fixed_off(struct bpf_verifier_env *env, - /* func where src register points to */ - struct bpf_func_state *reg_state, - int off, int size, int dst_regno) +static int check_stack_read(struct bpf_verifier_env *env, + struct bpf_func_state *reg_state /* func where register points to */, + int off, int size, int value_regno) { struct bpf_verifier_state *vstate = env->cur_state; struct bpf_func_state *state = vstate->frame[vstate->curframe]; int i, slot = -off - 1, spi = slot / BPF_REG_SIZE; struct bpf_reg_state *reg; - u8 *stype, type; + u8 *stype; + if (reg_state->allocated_stack <= slot) { + verbose(env, "invalid read from stack off %d+0 size %d\n", + off, size); + return -EACCES; + } stype = reg_state->stack[spi].slot_type; reg = ®_state->stack[spi].spilled_ptr; - if (is_spilled_reg(®_state->stack[spi])) { - u8 spill_size = 1; - - for (i = BPF_REG_SIZE - 1; i > 0 && stype[i - 1] == STACK_SPILL; i--) - spill_size++; - - if (size != BPF_REG_SIZE || spill_size != BPF_REG_SIZE) { + if (stype[0] == STACK_SPILL) { + if (size != BPF_REG_SIZE) { if (reg->type != SCALAR_VALUE) { verbose_linfo(env, env->insn_idx, "; "); verbose(env, "invalid size of register fill\n"); return -EACCES; } - - mark_reg_read(env, reg, reg->parent, REG_LIVE_READ64); - if (dst_regno < 0) - return 0; - - if (!(off % BPF_REG_SIZE) && size == spill_size) { - /* The earlier check_reg_arg() has decided the - * subreg_def for this insn. Save it first. - */ - s32 subreg_def = state->regs[dst_regno].subreg_def; - - copy_register_state(&state->regs[dst_regno], reg); - state->regs[dst_regno].subreg_def = subreg_def; - } else { - for (i = 0; i < size; i++) { - type = stype[(slot - i) % BPF_REG_SIZE]; - if (type == STACK_SPILL) - continue; - if (type == STACK_MISC) - continue; - if (type == STACK_INVALID && env->allow_uninit_stack) - continue; - verbose(env, "invalid read from stack off %d+%d size %d\n", - off, i, size); - return -EACCES; - } - mark_reg_unknown(env, state->regs, dst_regno); + if (value_regno >= 0) { + mark_reg_unknown(env, state->regs, value_regno); + state->regs[value_regno].live |= REG_LIVE_WRITTEN; } - state->regs[dst_regno].live |= REG_LIVE_WRITTEN; + mark_reg_read(env, reg, reg->parent, REG_LIVE_READ64); return 0; } + for (i = 1; i < BPF_REG_SIZE; i++) { + if (stype[(slot - i) % BPF_REG_SIZE] != STACK_SPILL) { + verbose(env, "corrupted spill memory\n"); + return -EACCES; + } + } - if (dst_regno >= 0) { + if (value_regno >= 0) { /* restore register state from stack */ - copy_register_state(&state->regs[dst_regno], reg); + state->regs[value_regno] = *reg; /* mark reg as written since spilled pointer state likely * has its liveness marks cleared by is_state_visited() * which resets stack/reg liveness for state transitions */ - state->regs[dst_regno].live |= REG_LIVE_WRITTEN; + state->regs[value_regno].live |= REG_LIVE_WRITTEN; } else if (__is_pointer_value(env->allow_ptr_leaks, reg)) { - /* If dst_regno==-1, the caller is asking us whether + /* If value_regno==-1, the caller is asking us whether * it is acceptable to use this value as a SCALAR_VALUE * (e.g. for XADD). * We must not allow unprivileged callers to do that @@ -2857,163 +2080,70 @@ static int check_stack_read_fixed_off(struct bpf_verifier_env *env, } mark_reg_read(env, reg, reg->parent, REG_LIVE_READ64); } else { + int zeros = 0; + for (i = 0; i < size; i++) { - type = stype[(slot - i) % BPF_REG_SIZE]; - if (type == STACK_MISC) + if (stype[(slot - i) % BPF_REG_SIZE] == STACK_MISC) continue; - if (type == STACK_ZERO) - continue; - if (type == STACK_INVALID && env->allow_uninit_stack) + if (stype[(slot - i) % BPF_REG_SIZE] == STACK_ZERO) { + zeros++; continue; + } verbose(env, "invalid read from stack off %d+%d size %d\n", off, i, size); return -EACCES; } mark_reg_read(env, reg, reg->parent, REG_LIVE_READ64); - if (dst_regno >= 0) - mark_reg_stack_read(env, reg_state, off, off + size, dst_regno); + if (value_regno >= 0) { + if (zeros == size) { + /* any size read into register is zero extended, + * so the whole register == const_zero + */ + __mark_reg_const_zero(&state->regs[value_regno]); + /* backtracking doesn't support STACK_ZERO yet, + * so mark it precise here, so that later + * backtracking can stop here. + * Backtracking may not need this if this register + * doesn't participate in pointer adjustment. + * Forward propagation of precise flag is not + * necessary either. This mark is only to stop + * backtracking. Any register that contributed + * to const 0 was marked precise before spill. + */ + state->regs[value_regno].precise = true; + } else { + /* have read misc data from the stack */ + mark_reg_unknown(env, state->regs, value_regno); + } + state->regs[value_regno].live |= REG_LIVE_WRITTEN; + } } return 0; } -enum stack_access_src { - ACCESS_DIRECT = 1, /* the access is performed by an instruction */ - ACCESS_HELPER = 2, /* the access is performed by a helper */ -}; - -static int check_stack_range_initialized(struct bpf_verifier_env *env, - int regno, int off, int access_size, - bool zero_size_allowed, - enum stack_access_src type, - struct bpf_call_arg_meta *meta); - -static struct bpf_reg_state *reg_state(struct bpf_verifier_env *env, int regno) +static int check_stack_access(struct bpf_verifier_env *env, + const struct bpf_reg_state *reg, + int off, int size) { - return cur_regs(env) + regno; -} - -/* Read the stack at 'ptr_regno + off' and put the result into the register - * 'dst_regno'. - * 'off' includes the pointer register's fixed offset(i.e. 'ptr_regno.off'), - * but not its variable offset. - * 'size' is assumed to be <= reg size and the access is assumed to be aligned. - * - * As opposed to check_stack_read_fixed_off, this function doesn't deal with - * filling registers (i.e. reads of spilled register cannot be detected when - * the offset is not fixed). We conservatively mark 'dst_regno' as containing - * SCALAR_VALUE. That's why we assert that the 'ptr_regno' has a variable - * offset; for a fixed offset check_stack_read_fixed_off should be used - * instead. - */ -static int check_stack_read_var_off(struct bpf_verifier_env *env, - int ptr_regno, int off, int size, int dst_regno) -{ - /* The state of the source register. */ - struct bpf_reg_state *reg = reg_state(env, ptr_regno); - struct bpf_func_state *ptr_state = func(env, reg); - int err; - int min_off, max_off; - - /* Note that we pass a NULL meta, so raw access will not be permitted. + /* Stack accesses must be at a fixed offset, so that we + * can determine what type of data were returned. See + * check_stack_read(). */ - err = check_stack_range_initialized(env, ptr_regno, off, size, - false, ACCESS_DIRECT, NULL); - if (err) - return err; - - min_off = reg->smin_value + off; - max_off = reg->smax_value + off; - mark_reg_stack_read(env, ptr_state, min_off, max_off + size, dst_regno); - return 0; -} - -/* check_stack_read dispatches to check_stack_read_fixed_off or - * check_stack_read_var_off. - * - * The caller must ensure that the offset falls within the allocated stack - * bounds. - * - * 'dst_regno' is a register which will receive the value from the stack. It - * can be -1, meaning that the read value is not going to a register. - */ -static int check_stack_read(struct bpf_verifier_env *env, - int ptr_regno, int off, int size, - int dst_regno) -{ - struct bpf_reg_state *reg = reg_state(env, ptr_regno); - struct bpf_func_state *state = func(env, reg); - int err; - /* Some accesses are only permitted with a static offset. */ - bool var_off = !tnum_is_const(reg->var_off); - - /* The offset is required to be static when reads don't go to a - * register, in order to not leak pointers (see - * check_stack_read_fixed_off). - */ - if (dst_regno < 0 && var_off) { + if (!tnum_is_const(reg->var_off)) { char tn_buf[48]; tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); - verbose(env, "variable offset stack pointer cannot be passed into helper function; var_off=%s off=%d size=%d\n", + verbose(env, "variable stack access var_off=%s off=%d size=%d\n", tn_buf, off, size); return -EACCES; } - /* Variable offset is prohibited for unprivileged mode for simplicity - * since it requires corresponding support in Spectre masking for stack - * ALU. See also retrieve_ptr_limit(). The check in - * check_stack_access_for_ptr_arithmetic() called by - * adjust_ptr_min_max_vals() prevents users from creating stack pointers - * with variable offsets, therefore no check is required here. Further, - * just checking it here would be insufficient as speculative stack - * writes could still lead to unsafe speculative behaviour. - */ - if (!var_off) { - off += reg->var_off.value; - err = check_stack_read_fixed_off(env, state, off, size, - dst_regno); - } else { - /* Variable offset stack reads need more conservative handling - * than fixed offset ones. Note that dst_regno >= 0 on this - * branch. - */ - err = check_stack_read_var_off(env, ptr_regno, off, size, - dst_regno); + + if (off >= 0 || off < -MAX_BPF_STACK) { + verbose(env, "invalid stack off=%d size=%d\n", off, size); + return -EACCES; } - return err; -} - -/* check_stack_write dispatches to check_stack_write_fixed_off or - * check_stack_write_var_off. - * - * 'ptr_regno' is the register used as a pointer into the stack. - * 'off' includes 'ptr_regno->off', but not its variable offset (if any). - * 'value_regno' is the register whose value we're writing to the stack. It can - * be -1, meaning that we're not writing from a register. - * - * The caller must ensure that the offset falls within the maximum stack size. - */ -static int check_stack_write(struct bpf_verifier_env *env, - int ptr_regno, int off, int size, - int value_regno, int insn_idx) -{ - struct bpf_reg_state *reg = reg_state(env, ptr_regno); - struct bpf_func_state *state = func(env, reg); - int err; - - if (tnum_is_const(reg->var_off)) { - off += reg->var_off.value; - err = check_stack_write_fixed_off(env, state, off, size, - value_regno, insn_idx); - } else { - /* Variable offset stack reads need more conservative handling - * than fixed offset ones. - */ - err = check_stack_write_var_off(env, state, - ptr_regno, off, size, - value_regno, insn_idx); - } - return err; + return 0; } static int check_map_access_type(struct bpf_verifier_env *env, u32 regno, @@ -3038,49 +2168,32 @@ static int check_map_access_type(struct bpf_verifier_env *env, u32 regno, return 0; } -/* check read/write into memory region (e.g., map value, ringbuf sample, etc) */ -static int __check_mem_access(struct bpf_verifier_env *env, int regno, - int off, int size, u32 mem_size, - bool zero_size_allowed) +/* check read/write into map element returned by bpf_map_lookup_elem() */ +static int __check_map_access(struct bpf_verifier_env *env, u32 regno, int off, + int size, bool zero_size_allowed) { - bool size_ok = size > 0 || (size == 0 && zero_size_allowed); - struct bpf_reg_state *reg; + struct bpf_reg_state *regs = cur_regs(env); + struct bpf_map *map = regs[regno].map_ptr; - if (off >= 0 && size_ok && (u64)off + size <= mem_size) - return 0; - - reg = &cur_regs(env)[regno]; - switch (reg->type) { - case PTR_TO_MAP_VALUE: + if (off < 0 || size < 0 || (size == 0 && !zero_size_allowed) || + off + size > map->value_size) { verbose(env, "invalid access to map value, value_size=%d off=%d size=%d\n", - mem_size, off, size); - break; - case PTR_TO_PACKET: - case PTR_TO_PACKET_META: - case PTR_TO_PACKET_END: - verbose(env, "invalid access to packet, off=%d size=%d, R%d(id=%d,off=%d,r=%d)\n", - off, size, regno, reg->id, off, mem_size); - break; - case PTR_TO_MEM: - default: - verbose(env, "invalid access to memory, mem_size=%u off=%d size=%d\n", - mem_size, off, size); + map->value_size, off, size); + return -EACCES; } - - return -EACCES; + return 0; } -/* check read/write into a memory region with possible variable offset */ -static int check_mem_region_access(struct bpf_verifier_env *env, u32 regno, - int off, int size, u32 mem_size, - bool zero_size_allowed) +/* check read/write into a map element with possible variable offset */ +static int check_map_access(struct bpf_verifier_env *env, u32 regno, + int off, int size, bool zero_size_allowed) { struct bpf_verifier_state *vstate = env->cur_state; struct bpf_func_state *state = vstate->frame[vstate->curframe]; struct bpf_reg_state *reg = &state->regs[regno]; int err; - /* We may have adjusted the register pointing to memory region, so we + /* We may have adjusted the register to this map value, so we * need to try adding each of min_value and max_value to off * to make sure our theoretical access will be safe. */ @@ -3101,10 +2214,10 @@ static int check_mem_region_access(struct bpf_verifier_env *env, u32 regno, regno); return -EACCES; } - err = __check_mem_access(env, regno, reg->smin_value + off, size, - mem_size, zero_size_allowed); + err = __check_map_access(env, regno, reg->smin_value + off, size, + zero_size_allowed); if (err) { - verbose(env, "R%d min value is outside of the allowed memory range\n", + verbose(env, "R%d min value is outside of the array range\n", regno); return err; } @@ -3114,38 +2227,18 @@ static int check_mem_region_access(struct bpf_verifier_env *env, u32 regno, * If reg->umax_value + off could overflow, treat that as unbounded too. */ if (reg->umax_value >= BPF_MAX_VAR_OFF) { - verbose(env, "R%d unbounded memory access, make sure to bounds check any such access\n", + verbose(env, "R%d unbounded memory access, make sure to bounds check any array access into a map\n", regno); return -EACCES; } - err = __check_mem_access(env, regno, reg->umax_value + off, size, - mem_size, zero_size_allowed); - if (err) { - verbose(env, "R%d max value is outside of the allowed memory range\n", - regno); - return err; - } - - return 0; -} - -/* check read/write into a map element with possible variable offset */ -static int check_map_access(struct bpf_verifier_env *env, u32 regno, - int off, int size, bool zero_size_allowed) -{ - struct bpf_verifier_state *vstate = env->cur_state; - struct bpf_func_state *state = vstate->frame[vstate->curframe]; - struct bpf_reg_state *reg = &state->regs[regno]; - struct bpf_map *map = reg->map_ptr; - int err; - - err = check_mem_region_access(env, regno, off, size, map->value_size, - zero_size_allowed); + err = __check_map_access(env, regno, reg->umax_value + off, size, + zero_size_allowed); if (err) - return err; + verbose(env, "R%d max value is outside of the array range\n", + regno); - if (map_value_has_spin_lock(map)) { - u32 lock = map->spin_lock_off; + if (map_value_has_spin_lock(reg->map_ptr)) { + u32 lock = reg->map_ptr->spin_lock_off; /* if any part of struct bpf_spin_lock can be touched by * load/store reject this program. @@ -3163,18 +2256,11 @@ static int check_map_access(struct bpf_verifier_env *env, u32 regno, #define MAX_PACKET_OFF 0xffff -static enum bpf_prog_type resolve_prog_type(struct bpf_prog *prog) -{ - return prog->aux->dst_prog ? prog->aux->dst_prog->type : prog->type; -} - static bool may_access_direct_pkt_data(struct bpf_verifier_env *env, const struct bpf_call_arg_meta *meta, enum bpf_access_type t) { - enum bpf_prog_type prog_type = resolve_prog_type(env->prog); - - switch (prog_type) { + switch (env->prog->type) { /* Program types only with direct read access go here! */ case BPF_PROG_TYPE_LWT_IN: case BPF_PROG_TYPE_LWT_OUT: @@ -3184,7 +2270,7 @@ static bool may_access_direct_pkt_data(struct bpf_verifier_env *env, case BPF_PROG_TYPE_CGROUP_SKB: if (t == BPF_WRITE) return false; - fallthrough; + /* fallthrough */ /* Program types with direct read + write access go here! */ case BPF_PROG_TYPE_SCHED_CLS: @@ -3210,6 +2296,21 @@ static bool may_access_direct_pkt_data(struct bpf_verifier_env *env, } } +static int __check_packet_access(struct bpf_verifier_env *env, u32 regno, + int off, int size, bool zero_size_allowed) +{ + struct bpf_reg_state *regs = cur_regs(env); + struct bpf_reg_state *reg = ®s[regno]; + + if (off < 0 || size < 0 || (size == 0 && !zero_size_allowed) || + (u64)off + size > reg->range) { + verbose(env, "invalid access to packet, off=%d size=%d, R%d(id=%d,off=%d,r=%d)\n", + off, size, regno, reg->id, reg->off, reg->range); + return -EACCES; + } + return 0; +} + static int check_packet_access(struct bpf_verifier_env *env, u32 regno, int off, int size, bool zero_size_allowed) { @@ -3230,19 +2331,16 @@ static int check_packet_access(struct bpf_verifier_env *env, u32 regno, int off, regno); return -EACCES; } - - err = reg->range < 0 ? -EINVAL : - __check_mem_access(env, regno, off, size, reg->range, - zero_size_allowed); + err = __check_packet_access(env, regno, off, size, zero_size_allowed); if (err) { verbose(env, "R%d offset is outside of the packet\n", regno); return err; } - /* __check_mem_access has made sure "off + size - 1" is within u16. + /* __check_packet_access has made sure "off + size - 1" is within u16. * reg->umax_value can't be bigger than MAX_PACKET_OFF which is 0xffff, * otherwise find_good_pkt_pointers would have refused to set range info - * that __check_mem_access would have rejected this pkt access. + * that __check_packet_access would have rejected this pkt access. * Therefore, "off + reg->umax_value + size - 1" won't overflow u32. */ env->prog->aux->max_pkt_offset = @@ -3254,12 +2352,10 @@ static int check_packet_access(struct bpf_verifier_env *env, u32 regno, int off, /* check access to 'struct bpf_context' fields. Supports fixed offsets only */ static int check_ctx_access(struct bpf_verifier_env *env, int insn_idx, int off, int size, - enum bpf_access_type t, enum bpf_reg_type *reg_type, - u32 *btf_id) + enum bpf_access_type t, enum bpf_reg_type *reg_type) { struct bpf_insn_access_aux info = { .reg_type = *reg_type, - .log = &env->log, }; if (env->ops->is_valid_access && @@ -3273,10 +2369,7 @@ static int check_ctx_access(struct bpf_verifier_env *env, int insn_idx, int off, */ *reg_type = info.reg_type; - if (*reg_type == PTR_TO_BTF_ID || *reg_type == PTR_TO_BTF_ID_OR_NULL) - *btf_id = info.btf_id; - else - env->insn_aux_data[insn_idx].ctx_field_size = info.ctx_field_size; + env->insn_aux_data[insn_idx].ctx_field_size = info.ctx_field_size; /* remember the offset of last byte accessed in ctx */ if (env->prog->aux->max_ctx_offset < off + size) env->prog->aux->max_ctx_offset = off + size; @@ -3344,6 +2437,11 @@ static int check_sock_access(struct bpf_verifier_env *env, int insn_idx, return -EACCES; } +static struct bpf_reg_state *reg_state(struct bpf_verifier_env *env, int regno) +{ + return cur_regs(env) + regno; +} + static bool is_pointer_value(struct bpf_verifier_env *env, int regno) { return __is_pointer_value(env->allow_ptr_leaks, reg_state(env, regno)); @@ -3462,8 +2560,8 @@ static int check_ptr_alignment(struct bpf_verifier_env *env, break; case PTR_TO_STACK: pointer_desc = "stack "; - /* The stack spill tracking logic in check_stack_write_fixed_off() - * and check_stack_read_fixed_off() relies on stack accesses being + /* The stack spill tracking logic in check_stack_write() + * and check_stack_read() relies on stack accesses being * aligned. */ strict = true; @@ -3512,10 +2610,8 @@ static int check_max_stack_depth(struct bpf_verifier_env *env) int depth = 0, frame = 0, idx = 0, i = 0, subprog_end; struct bpf_subprog_info *subprog = env->subprog_info; struct bpf_insn *insn = env->prog->insnsi; - bool tail_call_reachable = false; int ret_insn[MAX_CALL_FRAMES]; int ret_prog[MAX_CALL_FRAMES]; - int j; process_func: /* protect against potential stack overflow that might happen when @@ -3571,10 +2667,6 @@ continue_func: i); return -EFAULT; } - - if (subprog[idx].has_tail_call) - tail_call_reachable = true; - frame++; if (frame >= MAX_CALL_FRAMES) { verbose(env, "the call stack of %d frames is too deep !\n", @@ -3583,17 +2675,6 @@ continue_func: } goto process_func; } - /* if tail call got detected across bpf2bpf calls then mark each of the - * currently present subprog frames as tail call reachable subprogs; - * this info will be utilized by JIT so that we will be preserving the - * tail call counter throughout bpf2bpf calls combined with tailcalls - */ - if (tail_call_reachable) - for (j = 0; j < frame; j++) - subprog[ret_prog[j]].tail_call_reachable = true; - if (subprog[0].tail_call_reachable) - env->prog->aux->tail_call_reachable = true; - /* end of for() loop means the last insn of the 'subprog' * was reached. Doesn't matter whether it was JA or EXIT */ @@ -3622,8 +2703,8 @@ static int get_callee_stack_depth(struct bpf_verifier_env *env, } #endif -int check_ctx_reg(struct bpf_verifier_env *env, - const struct bpf_reg_state *reg, int regno) +static int check_ctx_reg(struct bpf_verifier_env *env, + const struct bpf_reg_state *reg, int regno) { /* Access to ctx or passing it to a helper is only allowed in * its original, unmodified form. @@ -3646,15 +2727,14 @@ int check_ctx_reg(struct bpf_verifier_env *env, return 0; } -static int __check_buffer_access(struct bpf_verifier_env *env, - const char *buf_info, - const struct bpf_reg_state *reg, - int regno, int off, int size) +static int check_tp_buffer_access(struct bpf_verifier_env *env, + const struct bpf_reg_state *reg, + int regno, int off, int size) { if (off < 0) { verbose(env, - "R%d invalid %s buffer access: off=%d, size=%d\n", - regno, buf_info, off, size); + "R%d invalid tracepoint buffer access: off=%d, size=%d", + regno, off, size); return -EACCES; } if (!tnum_is_const(reg->var_off) || reg->var_off.value) { @@ -3662,55 +2742,16 @@ static int __check_buffer_access(struct bpf_verifier_env *env, tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); verbose(env, - "R%d invalid variable buffer offset: off=%d, var_off=%s\n", + "R%d invalid variable buffer offset: off=%d, var_off=%s", regno, off, tn_buf); return -EACCES; } - - return 0; -} - -static int check_tp_buffer_access(struct bpf_verifier_env *env, - const struct bpf_reg_state *reg, - int regno, int off, int size) -{ - int err; - - err = __check_buffer_access(env, "tracepoint", reg, regno, off, size); - if (err) - return err; - if (off + size > env->prog->aux->max_tp_access) env->prog->aux->max_tp_access = off + size; return 0; } -static int check_buffer_access(struct bpf_verifier_env *env, - const struct bpf_reg_state *reg, - int regno, int off, int size, - bool zero_size_allowed, - const char *buf_info, - u32 *max_access) -{ - int err; - - err = __check_buffer_access(env, buf_info, reg, regno, off, size); - if (err) - return err; - - if (off + size > *max_access) - *max_access = off + size; - - return 0; -} - -/* BPF architecture zero extends alu32 ops into 64-bit registesr */ -static void zext_32_to_64(struct bpf_reg_state *reg) -{ - reg->var_off = tnum_subreg(reg->var_off); - __reg_assign_32_into_64(reg); -} /* truncate register to smaller size (in bytes) * must be called with size < BPF_REG_SIZE @@ -3733,34 +2774,11 @@ static void coerce_reg_to_size(struct bpf_reg_state *reg, int size) } reg->smin_value = reg->umin_value; reg->smax_value = reg->umax_value; - - /* If size is smaller than 32bit register the 32bit register - * values are also truncated so we push 64-bit bounds into - * 32-bit bounds. Above were truncated < 32-bits already. - */ - if (size >= 4) - return; - __reg_combine_64_into_32(reg); } static bool bpf_map_is_rdonly(const struct bpf_map *map) { - /* A map is considered read-only if the following condition are true: - * - * 1) BPF program side cannot change any of the map content. The - * BPF_F_RDONLY_PROG flag is throughout the lifetime of a map - * and was set at map creation time. - * 2) The map value(s) have been initialized from user space by a - * loader and then "frozen", such that no new map update/delete - * operations from syscall side are possible for the rest of - * the map's lifetime from that point onwards. - * 3) Any parallel/pending map update/delete operations from syscall - * side have been completed. Only after that point, it's safe to - * assume that map value(s) are immutable. - */ - return (map->map_flags & BPF_F_RDONLY_PROG) && - READ_ONCE(map->frozen) && - !bpf_map_write_active(map); + return (map->map_flags & BPF_F_RDONLY_PROG) && map->frozen; } static int bpf_map_direct_read(struct bpf_map *map, int off, int size, u64 *val) @@ -3793,196 +2811,6 @@ static int bpf_map_direct_read(struct bpf_map *map, int off, int size, u64 *val) return 0; } -static int check_ptr_to_btf_access(struct bpf_verifier_env *env, - struct bpf_reg_state *regs, - int regno, int off, int size, - enum bpf_access_type atype, - int value_regno) -{ - struct bpf_reg_state *reg = regs + regno; - const struct btf_type *t = btf_type_by_id(btf_vmlinux, reg->btf_id); - const char *tname = btf_name_by_offset(btf_vmlinux, t->name_off); - u32 btf_id; - int ret; - - if (off < 0) { - verbose(env, - "R%d is ptr_%s invalid negative access: off=%d\n", - regno, tname, off); - return -EACCES; - } - if (!tnum_is_const(reg->var_off) || reg->var_off.value) { - char tn_buf[48]; - - tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); - verbose(env, - "R%d is ptr_%s invalid variable offset: off=%d, var_off=%s\n", - regno, tname, off, tn_buf); - return -EACCES; - } - - if (env->ops->btf_struct_access) { - ret = env->ops->btf_struct_access(&env->log, t, off, size, - atype, &btf_id); - } else { - if (atype != BPF_READ) { - verbose(env, "only read is supported\n"); - return -EACCES; - } - - ret = btf_struct_access(&env->log, t, off, size, atype, - &btf_id); - } - - if (ret < 0) - return ret; - - if (atype == BPF_READ && value_regno >= 0) - mark_btf_ld_reg(env, regs, value_regno, ret, btf_id); - - return 0; -} - -static int check_ptr_to_map_access(struct bpf_verifier_env *env, - struct bpf_reg_state *regs, - int regno, int off, int size, - enum bpf_access_type atype, - int value_regno) -{ - struct bpf_reg_state *reg = regs + regno; - struct bpf_map *map = reg->map_ptr; - const struct btf_type *t; - const char *tname; - u32 btf_id; - int ret; - - if (!btf_vmlinux) { - verbose(env, "map_ptr access not supported without CONFIG_DEBUG_INFO_BTF\n"); - return -ENOTSUPP; - } - - if (!map->ops->map_btf_id || !*map->ops->map_btf_id) { - verbose(env, "map_ptr access not supported for map type %d\n", - map->map_type); - return -ENOTSUPP; - } - - t = btf_type_by_id(btf_vmlinux, *map->ops->map_btf_id); - tname = btf_name_by_offset(btf_vmlinux, t->name_off); - - if (!env->allow_ptr_to_map_access) { - verbose(env, - "%s access is allowed only to CAP_PERFMON and CAP_SYS_ADMIN\n", - tname); - return -EPERM; - } - - if (off < 0) { - verbose(env, "R%d is %s invalid negative access: off=%d\n", - regno, tname, off); - return -EACCES; - } - - if (atype != BPF_READ) { - verbose(env, "only read from %s is supported\n", tname); - return -EACCES; - } - - ret = btf_struct_access(&env->log, t, off, size, atype, &btf_id); - if (ret < 0) - return ret; - - if (value_regno >= 0) - mark_btf_ld_reg(env, regs, value_regno, ret, btf_id); - - return 0; -} - -/* Check that the stack access at the given offset is within bounds. The - * maximum valid offset is -1. - * - * The minimum valid offset is -MAX_BPF_STACK for writes, and - * -state->allocated_stack for reads. - */ -static int check_stack_slot_within_bounds(int off, - struct bpf_func_state *state, - enum bpf_access_type t) -{ - int min_valid_off; - - if (t == BPF_WRITE) - min_valid_off = -MAX_BPF_STACK; - else - min_valid_off = -state->allocated_stack; - - if (off < min_valid_off || off > -1) - return -EACCES; - return 0; -} - -/* Check that the stack access at 'regno + off' falls within the maximum stack - * bounds. - * - * 'off' includes `regno->offset`, but not its dynamic part (if any). - */ -static int check_stack_access_within_bounds( - struct bpf_verifier_env *env, - int regno, int off, int access_size, - enum stack_access_src src, enum bpf_access_type type) -{ - struct bpf_reg_state *regs = cur_regs(env); - struct bpf_reg_state *reg = regs + regno; - struct bpf_func_state *state = func(env, reg); - int min_off, max_off; - int err; - char *err_extra; - - if (src == ACCESS_HELPER) - /* We don't know if helpers are reading or writing (or both). */ - err_extra = " indirect access to"; - else if (type == BPF_READ) - err_extra = " read from"; - else - err_extra = " write to"; - - if (tnum_is_const(reg->var_off)) { - min_off = reg->var_off.value + off; - max_off = min_off + access_size; - } else { - if (reg->smax_value >= BPF_MAX_VAR_OFF || - reg->smin_value <= -BPF_MAX_VAR_OFF) { - verbose(env, "invalid unbounded variable-offset%s stack R%d\n", - err_extra, regno); - return -EACCES; - } - min_off = reg->smin_value + off; - max_off = reg->smax_value + off + access_size; - } - - err = check_stack_slot_within_bounds(min_off, state, type); - if (!err && max_off > 0) - err = -EINVAL; /* out of stack access into non-negative offsets */ - if (!err && access_size < 0) - /* access_size should not be negative (or overflow an int); others checks - * along the way should have prevented such an access. - */ - err = -EFAULT; /* invalid negative access size; integer overflow? */ - - if (err) { - if (tnum_is_const(reg->var_off)) { - verbose(env, "invalid%s stack R%d off=%d size=%d\n", - err_extra, regno, off, access_size); - } else { - char tn_buf[48]; - - tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); - verbose(env, "invalid variable-offset%s stack R%d var_off=%s size=%d\n", - err_extra, regno, tn_buf, access_size); - } - } - return err; -} - /* check whether memory at (regno + off) is accessible for t = (read | write) * if t==write, value_regno is a register which value is stored into memory * if t==read, value_regno is a register which will receive the value from memory @@ -4041,19 +2869,8 @@ static int check_mem_access(struct bpf_verifier_env *env, int insn_idx, u32 regn mark_reg_unknown(env, regs, value_regno); } } - } else if (reg->type == PTR_TO_MEM) { - if (t == BPF_WRITE && value_regno >= 0 && - is_pointer_value(env, value_regno)) { - verbose(env, "R%d leaks addr into mem\n", value_regno); - return -EACCES; - } - err = check_mem_region_access(env, regno, off, size, - reg->mem_size, false); - if (!err && t == BPF_READ && value_regno >= 0) - mark_reg_unknown(env, regs, value_regno); } else if (reg->type == PTR_TO_CTX) { enum bpf_reg_type reg_type = SCALAR_VALUE; - u32 btf_id = 0; if (t == BPF_WRITE && value_regno >= 0 && is_pointer_value(env, value_regno)) { @@ -4065,9 +2882,7 @@ static int check_mem_access(struct bpf_verifier_env *env, int insn_idx, u32 regn if (err < 0) return err; - err = check_ctx_access(env, insn_idx, off, size, t, ®_type, &btf_id); - if (err) - verbose_linfo(env, insn_idx, "; "); + err = check_ctx_access(env, insn_idx, off, size, t, ®_type); if (!err && t == BPF_READ && value_regno >= 0) { /* ctx access returns either a scalar, or a * PTR_TO_PACKET[_META,_END]. In the latter @@ -4086,16 +2901,13 @@ static int check_mem_access(struct bpf_verifier_env *env, int insn_idx, u32 regn * a sub-register. */ regs[value_regno].subreg_def = DEF_NOT_SUBREG; - if (reg_type == PTR_TO_BTF_ID || - reg_type == PTR_TO_BTF_ID_OR_NULL) - regs[value_regno].btf_id = btf_id; } regs[value_regno].type = reg_type; } } else if (reg->type == PTR_TO_STACK) { - /* Basic bounds checks. */ - err = check_stack_access_within_bounds(env, regno, off, size, ACCESS_DIRECT, t); + off += reg->var_off.value; + err = check_stack_access(env, reg, off, size); if (err) return err; @@ -4104,12 +2916,12 @@ static int check_mem_access(struct bpf_verifier_env *env, int insn_idx, u32 regn if (err) return err; - if (t == BPF_READ) - err = check_stack_read(env, regno, off, size, - value_regno); - else - err = check_stack_write(env, regno, off, size, + if (t == BPF_WRITE) + err = check_stack_write(env, state, off, size, value_regno, insn_idx); + else + err = check_stack_read(env, state, off, size, + value_regno); } else if (reg_is_pkt_pointer(reg)) { if (t == BPF_WRITE && !may_access_direct_pkt_data(env, NULL, t)) { verbose(env, "cannot write into packet\n"); @@ -4148,29 +2960,6 @@ static int check_mem_access(struct bpf_verifier_env *env, int insn_idx, u32 regn err = check_tp_buffer_access(env, reg, regno, off, size); if (!err && t == BPF_READ && value_regno >= 0) mark_reg_unknown(env, regs, value_regno); - } else if (reg->type == PTR_TO_BTF_ID) { - err = check_ptr_to_btf_access(env, regs, regno, off, size, t, - value_regno); - } else if (reg->type == CONST_PTR_TO_MAP) { - err = check_ptr_to_map_access(env, regs, regno, off, size, t, - value_regno); - } else if (reg->type == PTR_TO_RDONLY_BUF) { - if (t == BPF_WRITE) { - verbose(env, "R%d cannot write into %s\n", - regno, reg_type_str[reg->type]); - return -EACCES; - } - err = check_buffer_access(env, reg, regno, off, size, false, - "rdonly", - &env->prog->aux->max_rdonly_access); - if (!err && value_regno >= 0) - mark_reg_unknown(env, regs, value_regno); - } else if (reg->type == PTR_TO_RDWR_BUF) { - err = check_buffer_access(env, reg, regno, off, size, false, - "rdwr", - &env->prog->aux->max_rdwr_access); - if (!err && t == BPF_READ && value_regno >= 0) - mark_reg_unknown(env, regs, value_regno); } else { verbose(env, "R%d invalid mem access '%s'\n", regno, reg_type_str[reg->type]); @@ -4231,65 +3020,73 @@ static int check_xadd(struct bpf_verifier_env *env, int insn_idx, struct bpf_ins BPF_SIZE(insn->code), BPF_WRITE, -1, true); } -/* When register 'regno' is used to read the stack (either directly or through - * a helper function) make sure that it's within stack boundary and, depending - * on the access type, that all elements of the stack are initialized. - * - * 'off' includes 'regno->off', but not its dynamic part (if any). - * - * All registers that have been spilled on the stack in the slots within the - * read offsets are marked as read. +static int __check_stack_boundary(struct bpf_verifier_env *env, u32 regno, + int off, int access_size, + bool zero_size_allowed) +{ + struct bpf_reg_state *reg = reg_state(env, regno); + + if (off >= 0 || off < -MAX_BPF_STACK || off + access_size > 0 || + access_size < 0 || (access_size == 0 && !zero_size_allowed)) { + if (tnum_is_const(reg->var_off)) { + verbose(env, "invalid stack type R%d off=%d access_size=%d\n", + regno, off, access_size); + } else { + char tn_buf[48]; + + tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); + verbose(env, "invalid stack type R%d var_off=%s access_size=%d\n", + regno, tn_buf, access_size); + } + return -EACCES; + } + return 0; +} + +/* when register 'regno' is passed into function that will read 'access_size' + * bytes from that pointer, make sure that it's within stack boundary + * and all elements of stack are initialized. + * Unlike most pointer bounds-checking functions, this one doesn't take an + * 'off' argument, so it has to add in reg->off itself. */ -static int check_stack_range_initialized( - struct bpf_verifier_env *env, int regno, int off, - int access_size, bool zero_size_allowed, - enum stack_access_src type, struct bpf_call_arg_meta *meta) +static int check_stack_boundary(struct bpf_verifier_env *env, int regno, + int access_size, bool zero_size_allowed, + struct bpf_call_arg_meta *meta) { struct bpf_reg_state *reg = reg_state(env, regno); struct bpf_func_state *state = func(env, reg); int err, min_off, max_off, i, j, slot, spi; - char *err_extra = type == ACCESS_HELPER ? " indirect" : ""; - enum bpf_access_type bounds_check_type; - /* Some accesses can write anything into the stack, others are - * read-only. - */ - bool clobber = false; - if (access_size == 0 && !zero_size_allowed) { - verbose(env, "invalid zero-sized read\n"); + if (reg->type != PTR_TO_STACK) { + /* Allow zero-byte read from NULL, regardless of pointer type */ + if (zero_size_allowed && access_size == 0 && + register_is_null(reg)) + return 0; + + verbose(env, "R%d type=%s expected=%s\n", regno, + reg_type_str[reg->type], + reg_type_str[PTR_TO_STACK]); return -EACCES; } - if (type == ACCESS_HELPER) { - /* The bounds checks for writes are more permissive than for - * reads. However, if raw_mode is not set, we'll do extra - * checks below. - */ - bounds_check_type = BPF_WRITE; - clobber = true; - } else { - bounds_check_type = BPF_READ; - } - err = check_stack_access_within_bounds(env, regno, off, access_size, - type, bounds_check_type); - if (err) - return err; - - if (tnum_is_const(reg->var_off)) { - min_off = max_off = reg->var_off.value + off; + min_off = max_off = reg->var_off.value + reg->off; + err = __check_stack_boundary(env, regno, min_off, access_size, + zero_size_allowed); + if (err) + return err; } else { /* Variable offset is prohibited for unprivileged mode for * simplicity since it requires corresponding support in * Spectre masking for stack ALU. * See also retrieve_ptr_limit(). */ - if (!env->bypass_spec_v1) { + if (!env->allow_ptr_leaks) { char tn_buf[48]; tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); - verbose(env, "R%d%s variable offset stack access prohibited for !root, var_off=%s\n", - regno, err_extra, tn_buf); + verbose(env, "R%d indirect variable offset stack access prohibited for !root, var_off=%s\n", + regno, tn_buf); return -EACCES; } /* Only initialized buffer on stack is allowed to be accessed @@ -4301,8 +3098,28 @@ static int check_stack_range_initialized( if (meta && meta->raw_mode) meta = NULL; - min_off = reg->smin_value + off; - max_off = reg->smax_value + off; + if (reg->smax_value >= BPF_MAX_VAR_OFF || + reg->smax_value <= -BPF_MAX_VAR_OFF) { + verbose(env, "R%d unbounded indirect variable offset stack access\n", + regno); + return -EACCES; + } + min_off = reg->smin_value + reg->off; + max_off = reg->smax_value + reg->off; + err = __check_stack_boundary(env, regno, min_off, access_size, + zero_size_allowed); + if (err) { + verbose(env, "R%d min value is outside of stack bound\n", + regno); + return err; + } + err = __check_stack_boundary(env, regno, max_off, access_size, + zero_size_allowed); + if (err) { + verbose(env, "R%d max value is outside of stack bound\n", + regno); + return err; + } } if (meta && meta->raw_mode) { @@ -4321,40 +3138,29 @@ static int check_stack_range_initialized( stype = &state->stack[spi].slot_type[slot % BPF_REG_SIZE]; if (*stype == STACK_MISC) goto mark; - if ((*stype == STACK_ZERO) || - (*stype == STACK_INVALID && env->allow_uninit_stack)) { - if (clobber) { - /* helper can write anything into the stack */ - *stype = STACK_MISC; - } + if (*stype == STACK_ZERO) { + /* helper can write anything into the stack */ + *stype = STACK_MISC; goto mark; } - - if (is_spilled_reg(&state->stack[spi]) && - state->stack[spi].spilled_ptr.type == PTR_TO_BTF_ID) - goto mark; - - if (is_spilled_reg(&state->stack[spi]) && - (state->stack[spi].spilled_ptr.type == SCALAR_VALUE || - env->allow_ptr_leaks)) { - if (clobber) { - __mark_reg_unknown(env, &state->stack[spi].spilled_ptr); - for (j = 0; j < BPF_REG_SIZE; j++) - scrub_spilled_slot(&state->stack[spi].slot_type[j]); - } + if (state->stack[spi].slot_type[0] == STACK_SPILL && + state->stack[spi].spilled_ptr.type == SCALAR_VALUE) { + __mark_reg_unknown(env, &state->stack[spi].spilled_ptr); + for (j = 0; j < BPF_REG_SIZE; j++) + state->stack[spi].slot_type[j] = STACK_MISC; goto mark; } err: if (tnum_is_const(reg->var_off)) { - verbose(env, "invalid%s read from stack R%d off %d+%d size %d\n", - err_extra, regno, min_off, i - min_off, access_size); + verbose(env, "invalid indirect read from stack off %d+%d size %d\n", + min_off, i - min_off, access_size); } else { char tn_buf[48]; tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); - verbose(env, "invalid%s read from stack R%d var_off %s+%d size %d\n", - err_extra, regno, tn_buf, i - min_off, access_size); + verbose(env, "invalid indirect read from stack var_off %s+%d size %d\n", + tn_buf, i - min_off, access_size); } return -EACCES; mark: @@ -4386,37 +3192,9 @@ static int check_helper_mem_access(struct bpf_verifier_env *env, int regno, return -EACCES; return check_map_access(env, regno, reg->off, access_size, zero_size_allowed); - case PTR_TO_MEM: - return check_mem_region_access(env, regno, reg->off, - access_size, reg->mem_size, - zero_size_allowed); - case PTR_TO_RDONLY_BUF: - if (meta && meta->raw_mode) - return -EACCES; - return check_buffer_access(env, reg, regno, reg->off, - access_size, zero_size_allowed, - "rdonly", - &env->prog->aux->max_rdonly_access); - case PTR_TO_RDWR_BUF: - return check_buffer_access(env, reg, regno, reg->off, - access_size, zero_size_allowed, - "rdwr", - &env->prog->aux->max_rdwr_access); - case PTR_TO_STACK: - return check_stack_range_initialized( - env, - regno, reg->off, access_size, - zero_size_allowed, ACCESS_HELPER, meta); - default: /* scalar_value or invalid ptr */ - /* Allow zero-byte read from NULL, regardless of pointer type */ - if (zero_size_allowed && access_size == 0 && - register_is_null(reg)) - return 0; - - verbose(env, "R%d type=%s expected=%s\n", regno, - reg_type_str[reg->type], - reg_type_str[PTR_TO_STACK]); - return -EACCES; + default: /* scalar_value|ptr_to_stack or invalid ptr */ + return check_stack_boundary(env, regno, access_size, + zero_size_allowed, meta); } } @@ -4448,6 +3226,10 @@ static int process_spin_lock(struct bpf_verifier_env *env, int regno, struct bpf_map *map = reg->map_ptr; u64 val = reg->var_off.value; + if (reg->type != PTR_TO_MAP_VALUE) { + verbose(env, "R%d is not a pointer to map_value\n", regno); + return -EINVAL; + } if (!is_const) { verbose(env, "R%d doesn't have constant offset. bpf_spin_lock has to be at the constant offset\n", @@ -4514,11 +3296,6 @@ static bool arg_type_is_mem_size(enum bpf_arg_type type) type == ARG_CONST_SIZE_OR_ZERO; } -static bool arg_type_is_alloc_size(enum bpf_arg_type type) -{ - return type == ARG_CONST_ALLOC_SIZE_OR_ZERO; -} - static bool arg_type_is_int_ptr(enum bpf_arg_type type) { return type == ARG_PTR_TO_INT || @@ -4535,194 +3312,12 @@ static int int_ptr_type_to_size(enum bpf_arg_type type) return -EINVAL; } -static int resolve_map_arg_type(struct bpf_verifier_env *env, - const struct bpf_call_arg_meta *meta, - enum bpf_arg_type *arg_type) -{ - if (!meta->map_ptr) { - /* kernel subsystem misconfigured verifier */ - verbose(env, "invalid map_ptr to access map->type\n"); - return -EACCES; - } - - switch (meta->map_ptr->map_type) { - case BPF_MAP_TYPE_SOCKMAP: - case BPF_MAP_TYPE_SOCKHASH: - if (*arg_type == ARG_PTR_TO_MAP_VALUE) { - *arg_type = ARG_PTR_TO_BTF_ID_SOCK_COMMON; - } else { - verbose(env, "invalid arg_type for sockmap/sockhash\n"); - return -EINVAL; - } - break; - - default: - break; - } - return 0; -} - -struct bpf_reg_types { - const enum bpf_reg_type types[10]; - u32 *btf_id; -}; - -static const struct bpf_reg_types map_key_value_types = { - .types = { - PTR_TO_STACK, - PTR_TO_PACKET, - PTR_TO_PACKET_META, - PTR_TO_MAP_VALUE, - }, -}; - -static const struct bpf_reg_types sock_types = { - .types = { - PTR_TO_SOCK_COMMON, - PTR_TO_SOCKET, - PTR_TO_TCP_SOCK, - PTR_TO_XDP_SOCK, - }, -}; - -#ifdef CONFIG_NET -static const struct bpf_reg_types btf_id_sock_common_types = { - .types = { - PTR_TO_SOCK_COMMON, - PTR_TO_SOCKET, - PTR_TO_TCP_SOCK, - PTR_TO_XDP_SOCK, - PTR_TO_BTF_ID, - }, - .btf_id = &btf_sock_ids[BTF_SOCK_TYPE_SOCK_COMMON], -}; -#endif - -static const struct bpf_reg_types mem_types = { - .types = { - PTR_TO_STACK, - PTR_TO_PACKET, - PTR_TO_PACKET_META, - PTR_TO_MAP_VALUE, - PTR_TO_MEM, - PTR_TO_RDONLY_BUF, - PTR_TO_RDWR_BUF, - }, -}; - -static const struct bpf_reg_types int_ptr_types = { - .types = { - PTR_TO_STACK, - PTR_TO_PACKET, - PTR_TO_PACKET_META, - PTR_TO_MAP_VALUE, - }, -}; - -static const struct bpf_reg_types fullsock_types = { .types = { PTR_TO_SOCKET } }; -static const struct bpf_reg_types scalar_types = { .types = { SCALAR_VALUE } }; -static const struct bpf_reg_types context_types = { .types = { PTR_TO_CTX } }; -static const struct bpf_reg_types alloc_mem_types = { .types = { PTR_TO_MEM } }; -static const struct bpf_reg_types const_map_ptr_types = { .types = { CONST_PTR_TO_MAP } }; -static const struct bpf_reg_types btf_ptr_types = { .types = { PTR_TO_BTF_ID } }; -static const struct bpf_reg_types spin_lock_types = { .types = { PTR_TO_MAP_VALUE } }; -static const struct bpf_reg_types percpu_btf_ptr_types = { .types = { PTR_TO_PERCPU_BTF_ID } }; - -static const struct bpf_reg_types *compatible_reg_types[__BPF_ARG_TYPE_MAX] = { - [ARG_PTR_TO_MAP_KEY] = &map_key_value_types, - [ARG_PTR_TO_MAP_VALUE] = &map_key_value_types, - [ARG_PTR_TO_UNINIT_MAP_VALUE] = &map_key_value_types, - [ARG_PTR_TO_MAP_VALUE_OR_NULL] = &map_key_value_types, - [ARG_CONST_SIZE] = &scalar_types, - [ARG_CONST_SIZE_OR_ZERO] = &scalar_types, - [ARG_CONST_ALLOC_SIZE_OR_ZERO] = &scalar_types, - [ARG_CONST_MAP_PTR] = &const_map_ptr_types, - [ARG_PTR_TO_CTX] = &context_types, - [ARG_PTR_TO_CTX_OR_NULL] = &context_types, - [ARG_PTR_TO_SOCK_COMMON] = &sock_types, -#ifdef CONFIG_NET - [ARG_PTR_TO_BTF_ID_SOCK_COMMON] = &btf_id_sock_common_types, -#endif - [ARG_PTR_TO_SOCKET] = &fullsock_types, - [ARG_PTR_TO_SOCKET_OR_NULL] = &fullsock_types, - [ARG_PTR_TO_BTF_ID] = &btf_ptr_types, - [ARG_PTR_TO_SPIN_LOCK] = &spin_lock_types, - [ARG_PTR_TO_MEM] = &mem_types, - [ARG_PTR_TO_MEM_OR_NULL] = &mem_types, - [ARG_PTR_TO_UNINIT_MEM] = &mem_types, - [ARG_PTR_TO_ALLOC_MEM] = &alloc_mem_types, - [ARG_PTR_TO_ALLOC_MEM_OR_NULL] = &alloc_mem_types, - [ARG_PTR_TO_INT] = &int_ptr_types, - [ARG_PTR_TO_LONG] = &int_ptr_types, - [ARG_PTR_TO_PERCPU_BTF_ID] = &percpu_btf_ptr_types, -}; - -static int check_reg_type(struct bpf_verifier_env *env, u32 regno, +static int check_func_arg(struct bpf_verifier_env *env, u32 regno, enum bpf_arg_type arg_type, - const u32 *arg_btf_id) + struct bpf_call_arg_meta *meta) { struct bpf_reg_state *regs = cur_regs(env), *reg = ®s[regno]; - enum bpf_reg_type expected, type = reg->type; - const struct bpf_reg_types *compatible; - int i, j; - - compatible = compatible_reg_types[arg_type]; - if (!compatible) { - verbose(env, "verifier internal error: unsupported arg type %d\n", arg_type); - return -EFAULT; - } - - for (i = 0; i < ARRAY_SIZE(compatible->types); i++) { - expected = compatible->types[i]; - if (expected == NOT_INIT) - break; - - if (type == expected) - goto found; - } - - verbose(env, "R%d type=%s expected=", regno, reg_type_str[type]); - for (j = 0; j + 1 < i; j++) - verbose(env, "%s, ", reg_type_str[compatible->types[j]]); - verbose(env, "%s\n", reg_type_str[compatible->types[j]]); - return -EACCES; - -found: - if (type == PTR_TO_BTF_ID) { - if (!arg_btf_id) { - if (!compatible->btf_id) { - verbose(env, "verifier internal error: missing arg compatible BTF ID\n"); - return -EFAULT; - } - arg_btf_id = compatible->btf_id; - } - - if (!btf_struct_ids_match(&env->log, reg->off, reg->btf_id, - *arg_btf_id)) { - verbose(env, "R%d is of type %s but %s is expected\n", - regno, kernel_type_name(reg->btf_id), - kernel_type_name(*arg_btf_id)); - return -EACCES; - } - - if (!tnum_is_const(reg->var_off) || reg->var_off.value) { - verbose(env, "R%d is a pointer to in-kernel struct with non-zero offset\n", - regno); - return -EACCES; - } - } - - return 0; -} - -static int check_func_arg(struct bpf_verifier_env *env, u32 arg, - struct bpf_call_arg_meta *meta, - const struct bpf_func_proto *fn) -{ - u32 regno = BPF_REG_1 + arg; - struct bpf_reg_state *regs = cur_regs(env), *reg = ®s[regno]; - enum bpf_arg_type arg_type = fn->arg_type[arg]; - enum bpf_reg_type type = reg->type; + enum bpf_reg_type expected_type, type = reg->type; int err = 0; if (arg_type == ARG_DONTCARE) @@ -4747,39 +3342,86 @@ static int check_func_arg(struct bpf_verifier_env *env, u32 arg, return -EACCES; } - if (arg_type == ARG_PTR_TO_MAP_VALUE || + if (arg_type == ARG_PTR_TO_MAP_KEY || + arg_type == ARG_PTR_TO_MAP_VALUE || arg_type == ARG_PTR_TO_UNINIT_MAP_VALUE || arg_type == ARG_PTR_TO_MAP_VALUE_OR_NULL) { - err = resolve_map_arg_type(env, meta, &arg_type); - if (err) - return err; - } - - if (register_is_null(reg) && arg_type_may_be_null(arg_type)) - /* A NULL register has a SCALAR_VALUE type, so skip - * type checking. - */ - goto skip_type_check; - - err = check_reg_type(env, regno, arg_type, fn->arg_btf_id[arg]); - if (err) - return err; - - if (type == PTR_TO_CTX) { + expected_type = PTR_TO_STACK; + if (register_is_null(reg) && + arg_type == ARG_PTR_TO_MAP_VALUE_OR_NULL) + /* final test in check_stack_boundary() */; + else if (!type_is_pkt_pointer(type) && + type != PTR_TO_MAP_VALUE && + type != expected_type) + goto err_type; + } else if (arg_type == ARG_CONST_SIZE || + arg_type == ARG_CONST_SIZE_OR_ZERO) { + expected_type = SCALAR_VALUE; + if (type != expected_type) + goto err_type; + } else if (arg_type == ARG_CONST_MAP_PTR) { + expected_type = CONST_PTR_TO_MAP; + if (type != expected_type) + goto err_type; + } else if (arg_type == ARG_PTR_TO_CTX) { + expected_type = PTR_TO_CTX; + if (type != expected_type) + goto err_type; err = check_ctx_reg(env, reg, regno); if (err < 0) return err; - } - -skip_type_check: - if (reg->ref_obj_id) { - if (meta->ref_obj_id) { - verbose(env, "verifier internal error: more than one arg with ref_obj_id R%d %u %u\n", - regno, reg->ref_obj_id, - meta->ref_obj_id); + } else if (arg_type == ARG_PTR_TO_SOCK_COMMON) { + expected_type = PTR_TO_SOCK_COMMON; + /* Any sk pointer can be ARG_PTR_TO_SOCK_COMMON */ + if (!type_is_sk_pointer(type)) + goto err_type; + if (reg->ref_obj_id) { + if (meta->ref_obj_id) { + verbose(env, "verifier internal error: more than one arg with ref_obj_id R%d %u %u\n", + regno, reg->ref_obj_id, + meta->ref_obj_id); + return -EFAULT; + } + meta->ref_obj_id = reg->ref_obj_id; + } + } else if (arg_type == ARG_PTR_TO_SOCKET) { + expected_type = PTR_TO_SOCKET; + if (type != expected_type) + goto err_type; + } else if (arg_type == ARG_PTR_TO_SPIN_LOCK) { + if (meta->func_id == BPF_FUNC_spin_lock) { + if (process_spin_lock(env, regno, true)) + return -EACCES; + } else if (meta->func_id == BPF_FUNC_spin_unlock) { + if (process_spin_lock(env, regno, false)) + return -EACCES; + } else { + verbose(env, "verifier internal error\n"); return -EFAULT; } - meta->ref_obj_id = reg->ref_obj_id; + } else if (arg_type_is_mem_ptr(arg_type)) { + expected_type = PTR_TO_STACK; + /* One exception here. In case function allows for NULL to be + * passed in as argument, it's a SCALAR_VALUE type. Final test + * happens during stack boundary checking. + */ + if (register_is_null(reg) && + arg_type == ARG_PTR_TO_MEM_OR_NULL) + /* final test in check_stack_boundary() */; + else if (!type_is_pkt_pointer(type) && + type != PTR_TO_MAP_VALUE && + type != expected_type) + goto err_type; + meta->raw_mode = arg_type == ARG_PTR_TO_UNINIT_MEM; + } else if (arg_type_is_int_ptr(arg_type)) { + expected_type = PTR_TO_STACK; + if (!type_is_pkt_pointer(type) && + type != PTR_TO_MAP_VALUE && + type != expected_type) + goto err_type; + } else { + verbose(env, "unsupported arg_type %d\n", arg_type); + return -EFAULT; } if (arg_type == ARG_CONST_MAP_PTR) { @@ -4818,38 +3460,11 @@ skip_type_check: err = check_helper_mem_access(env, regno, meta->map_ptr->value_size, false, meta); - } else if (arg_type == ARG_PTR_TO_PERCPU_BTF_ID) { - if (!reg->btf_id) { - verbose(env, "Helper has invalid btf_id in R%d\n", regno); - return -EACCES; - } - meta->ret_btf_id = reg->btf_id; - } else if (arg_type == ARG_PTR_TO_SPIN_LOCK) { - if (meta->func_id == BPF_FUNC_spin_lock) { - if (process_spin_lock(env, regno, true)) - return -EACCES; - } else if (meta->func_id == BPF_FUNC_spin_unlock) { - if (process_spin_lock(env, regno, false)) - return -EACCES; - } else { - verbose(env, "verifier internal error\n"); - return -EFAULT; - } - } else if (arg_type_is_mem_ptr(arg_type)) { - /* The access to this pointer is only checked when we hit the - * next is_mem_size argument below. - */ - meta->raw_mode = (arg_type == ARG_PTR_TO_UNINIT_MEM); } else if (arg_type_is_mem_size(arg_type)) { bool zero_size_allowed = (arg_type == ARG_CONST_SIZE_OR_ZERO); - /* This is used to refine r0 return value bounds for helpers - * that enforce this value as an upper bound on return values. - * See do_refine_retval_range() for helpers that can refine - * the return value. C type of helper is u32 so we pull register - * bound from umax_value however, if negative verifier errors - * out. Only upper bounds can be learned because retval is an - * int type and negative retvals are allowed. + /* remember the mem_size which may be used later + * to refine return values. */ meta->msize_max_value = reg->umax_value; @@ -4888,13 +3503,6 @@ skip_type_check: zero_size_allowed, meta); if (!err) err = mark_chain_precision(env, regno); - } else if (arg_type_is_alloc_size(arg_type)) { - if (!tnum_is_const(reg->var_off)) { - verbose(env, "R%d unbounded size, use 'var &= const' or 'if (var < const)'\n", - regno); - return -EACCES; - } - meta->mem_size = reg->var_off.value; } else if (arg_type_is_int_ptr(arg_type)) { int size = int_ptr_type_to_size(arg_type); @@ -4905,49 +3513,10 @@ skip_type_check: } return err; -} - -static bool may_update_sockmap(struct bpf_verifier_env *env, int func_id) -{ - enum bpf_attach_type eatype = env->prog->expected_attach_type; - enum bpf_prog_type type = resolve_prog_type(env->prog); - - if (func_id != BPF_FUNC_map_update_elem && - func_id != BPF_FUNC_map_delete_elem) - return false; - - /* It's not possible to get access to a locked struct sock in these - * contexts, so updating is safe. - */ - switch (type) { - case BPF_PROG_TYPE_TRACING: - if (eatype == BPF_TRACE_ITER) - return true; - break; - case BPF_PROG_TYPE_SOCK_OPS: - /* map_update allowed only via dedicated helpers with event type checks */ - if (func_id == BPF_FUNC_map_delete_elem) - return true; - break; - case BPF_PROG_TYPE_SOCKET_FILTER: - case BPF_PROG_TYPE_SCHED_CLS: - case BPF_PROG_TYPE_SCHED_ACT: - case BPF_PROG_TYPE_XDP: - case BPF_PROG_TYPE_SK_REUSEPORT: - case BPF_PROG_TYPE_FLOW_DISSECTOR: - case BPF_PROG_TYPE_SK_LOOKUP: - return true; - default: - break; - } - - verbose(env, "cannot update sockmap in this context\n"); - return false; -} - -static bool allow_tail_call_in_subprogs(struct bpf_verifier_env *env) -{ - return env->prog->jit_requested && IS_ENABLED(CONFIG_X86_64); +err_type: + verbose(env, "R%d type=%s expected=%s\n", regno, + reg_type_str[type], reg_type_str[expected_type]); + return -EACCES; } static int check_map_func_compatibility(struct bpf_verifier_env *env, @@ -4965,15 +3534,7 @@ static int check_map_func_compatibility(struct bpf_verifier_env *env, case BPF_MAP_TYPE_PERF_EVENT_ARRAY: if (func_id != BPF_FUNC_perf_event_read && func_id != BPF_FUNC_perf_event_output && - func_id != BPF_FUNC_skb_output && - func_id != BPF_FUNC_perf_event_read_value && - func_id != BPF_FUNC_xdp_output) - goto error; - break; - case BPF_MAP_TYPE_RINGBUF: - if (func_id != BPF_FUNC_ringbuf_output && - func_id != BPF_FUNC_ringbuf_reserve && - func_id != BPF_FUNC_ringbuf_query) + func_id != BPF_FUNC_perf_event_read_value) goto error; break; case BPF_MAP_TYPE_STACK_TRACE: @@ -5016,19 +3577,15 @@ static int check_map_func_compatibility(struct bpf_verifier_env *env, case BPF_MAP_TYPE_SOCKMAP: if (func_id != BPF_FUNC_sk_redirect_map && func_id != BPF_FUNC_sock_map_update && - func_id != BPF_FUNC_msg_redirect_map && - func_id != BPF_FUNC_sk_select_reuseport && - func_id != BPF_FUNC_map_lookup_elem && - !may_update_sockmap(env, func_id)) + func_id != BPF_FUNC_map_delete_elem && + func_id != BPF_FUNC_msg_redirect_map) goto error; break; case BPF_MAP_TYPE_SOCKHASH: if (func_id != BPF_FUNC_sk_redirect_hash && func_id != BPF_FUNC_sock_hash_update && - func_id != BPF_FUNC_msg_redirect_hash && - func_id != BPF_FUNC_sk_select_reuseport && - func_id != BPF_FUNC_map_lookup_elem && - !may_update_sockmap(env, func_id)) + func_id != BPF_FUNC_map_delete_elem && + func_id != BPF_FUNC_msg_redirect_hash) goto error; break; case BPF_MAP_TYPE_REUSEPORT_SOCKARRAY: @@ -5047,11 +3604,6 @@ static int check_map_func_compatibility(struct bpf_verifier_env *env, func_id != BPF_FUNC_sk_storage_delete) goto error; break; - case BPF_MAP_TYPE_INODE_STORAGE: - if (func_id != BPF_FUNC_inode_storage_get && - func_id != BPF_FUNC_inode_storage_delete) - goto error; - break; default: break; } @@ -5061,25 +3613,17 @@ static int check_map_func_compatibility(struct bpf_verifier_env *env, case BPF_FUNC_tail_call: if (map->map_type != BPF_MAP_TYPE_PROG_ARRAY) goto error; - if (env->subprog_cnt > 1 && !allow_tail_call_in_subprogs(env)) { - verbose(env, "tail_calls are not allowed in non-JITed programs with bpf-to-bpf calls\n"); + if (env->subprog_cnt > 1) { + verbose(env, "tail_calls are not allowed in programs with bpf-to-bpf calls\n"); return -EINVAL; } break; case BPF_FUNC_perf_event_read: case BPF_FUNC_perf_event_output: case BPF_FUNC_perf_event_read_value: - case BPF_FUNC_skb_output: - case BPF_FUNC_xdp_output: if (map->map_type != BPF_MAP_TYPE_PERF_EVENT_ARRAY) goto error; break; - case BPF_FUNC_ringbuf_output: - case BPF_FUNC_ringbuf_reserve: - case BPF_FUNC_ringbuf_query: - if (map->map_type != BPF_MAP_TYPE_RINGBUF) - goto error; - break; case BPF_FUNC_get_stackid: if (map->map_type != BPF_MAP_TYPE_STACK_TRACE) goto error; @@ -5114,9 +3658,7 @@ static int check_map_func_compatibility(struct bpf_verifier_env *env, goto error; break; case BPF_FUNC_sk_select_reuseport: - if (map->map_type != BPF_MAP_TYPE_REUSEPORT_SOCKARRAY && - map->map_type != BPF_MAP_TYPE_SOCKMAP && - map->map_type != BPF_MAP_TYPE_SOCKHASH) + if (map->map_type != BPF_MAP_TYPE_REUSEPORT_SOCKARRAY) goto error; break; case BPF_FUNC_map_peek_elem: @@ -5131,11 +3673,6 @@ static int check_map_func_compatibility(struct bpf_verifier_env *env, if (map->map_type != BPF_MAP_TYPE_SK_STORAGE) goto error; break; - case BPF_FUNC_inode_storage_get: - case BPF_FUNC_inode_storage_delete: - if (map->map_type != BPF_MAP_TYPE_INODE_STORAGE) - goto error; - break; default: break; } @@ -5214,7 +3751,7 @@ static bool check_refcount_ok(const struct bpf_func_proto *fn, int func_id) /* A reference acquiring function cannot acquire * another refcounted ptr. */ - if (may_be_acquire_function(func_id) && count) + if (is_acquire_function(func_id) && count) return false; /* We only support one arg being unreferenced at the moment, @@ -5223,67 +3760,60 @@ static bool check_refcount_ok(const struct bpf_func_proto *fn, int func_id) return count <= 1; } -static bool check_btf_id_ok(const struct bpf_func_proto *fn) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(fn->arg_type); i++) { - if (fn->arg_type[i] == ARG_PTR_TO_BTF_ID && !fn->arg_btf_id[i]) - return false; - - if (fn->arg_type[i] != ARG_PTR_TO_BTF_ID && fn->arg_btf_id[i]) - return false; - } - - return true; -} - static int check_func_proto(const struct bpf_func_proto *fn, int func_id) { return check_raw_mode_ok(fn) && check_arg_pair_ok(fn) && - check_btf_id_ok(fn) && check_refcount_ok(fn, func_id) ? 0 : -EINVAL; } /* Packet data might have moved, any old PTR_TO_PACKET[_META,_END] * are now invalid, so turn them into unknown SCALAR_VALUE. */ -static void clear_all_pkt_pointers(struct bpf_verifier_env *env) +static void __clear_all_pkt_pointers(struct bpf_verifier_env *env, + struct bpf_func_state *state) { - struct bpf_func_state *state; - struct bpf_reg_state *reg; + struct bpf_reg_state *regs = state->regs, *reg; + int i; - bpf_for_each_reg_in_vstate(env->cur_state, state, reg, ({ + for (i = 0; i < MAX_BPF_REG; i++) + if (reg_is_pkt_pointer_any(®s[i])) + mark_reg_unknown(env, regs, i); + + bpf_for_each_spilled_reg(i, state, reg) { + if (!reg) + continue; if (reg_is_pkt_pointer_any(reg)) __mark_reg_unknown(env, reg); - })); + } } -enum { - AT_PKT_END = -1, - BEYOND_PKT_END = -2, -}; - -static void mark_pkt_end(struct bpf_verifier_state *vstate, int regn, bool range_open) +static void clear_all_pkt_pointers(struct bpf_verifier_env *env) { - struct bpf_func_state *state = vstate->frame[vstate->curframe]; - struct bpf_reg_state *reg = &state->regs[regn]; + struct bpf_verifier_state *vstate = env->cur_state; + int i; - if (reg->type != PTR_TO_PACKET) - /* PTR_TO_PACKET_META is not supported yet */ - return; + for (i = 0; i <= vstate->curframe; i++) + __clear_all_pkt_pointers(env, vstate->frame[i]); +} - /* The 'reg' is pkt > pkt_end or pkt >= pkt_end. - * How far beyond pkt_end it goes is unknown. - * if (!range_open) it's the case of pkt >= pkt_end - * if (range_open) it's the case of pkt > pkt_end - * hence this pointer is at least 1 byte bigger than pkt_end - */ - if (range_open) - reg->range = BEYOND_PKT_END; - else - reg->range = AT_PKT_END; +static void release_reg_references(struct bpf_verifier_env *env, + struct bpf_func_state *state, + int ref_obj_id) +{ + struct bpf_reg_state *regs = state->regs, *reg; + int i; + + for (i = 0; i < MAX_BPF_REG; i++) + if (regs[i].ref_obj_id == ref_obj_id) + mark_reg_unknown(env, regs, i); + + bpf_for_each_spilled_reg(i, state, reg) { + if (!reg) + continue; + if (reg->ref_obj_id == ref_obj_id) + __mark_reg_unknown(env, reg); + } } /* The pointer with the specified id has released its reference to kernel @@ -5292,46 +3822,26 @@ static void mark_pkt_end(struct bpf_verifier_state *vstate, int regn, bool range static int release_reference(struct bpf_verifier_env *env, int ref_obj_id) { - struct bpf_func_state *state; - struct bpf_reg_state *reg; + struct bpf_verifier_state *vstate = env->cur_state; int err; + int i; err = release_reference_state(cur_func(env), ref_obj_id); if (err) return err; - bpf_for_each_reg_in_vstate(env->cur_state, state, reg, ({ - if (reg->ref_obj_id == ref_obj_id) { - if (!env->allow_ptr_leaks) - __mark_reg_not_init(env, reg); - else - __mark_reg_unknown(env, reg); - } - })); + for (i = 0; i <= vstate->curframe; i++) + release_reg_references(env, vstate->frame[i], ref_obj_id); return 0; } -static void clear_caller_saved_regs(struct bpf_verifier_env *env, - struct bpf_reg_state *regs) -{ - int i; - - /* after the call registers r0 - r5 were scratched */ - for (i = 0; i < CALLER_SAVED_REGS; i++) { - mark_reg_not_init(env, regs, caller_saved[i]); - check_reg_arg(env, caller_saved[i], DST_OP_NO_MARK); - } -} - static int check_func_call(struct bpf_verifier_env *env, struct bpf_insn *insn, int *insn_idx) { struct bpf_verifier_state *state = env->cur_state; - struct bpf_func_info_aux *func_info_aux; struct bpf_func_state *caller, *callee; int i, err, subprog, target_insn; - bool is_global = false; if (state->curframe + 1 >= MAX_CALL_FRAMES) { verbose(env, "the call stack of %d frames is too deep\n", @@ -5354,33 +3864,6 @@ static int check_func_call(struct bpf_verifier_env *env, struct bpf_insn *insn, return -EFAULT; } - func_info_aux = env->prog->aux->func_info_aux; - if (func_info_aux) - is_global = func_info_aux[subprog].linkage == BTF_FUNC_GLOBAL; - err = btf_check_func_arg_match(env, subprog, caller->regs); - if (err == -EFAULT) - return err; - if (is_global) { - if (err) { - verbose(env, "Caller passes invalid args into func#%d\n", - subprog); - return err; - } else { - if (env->log.level & BPF_LOG_LEVEL) - verbose(env, - "Func#%d is global and valid. Skipping.\n", - subprog); - clear_caller_saved_regs(env, caller->regs); - - /* All global functions return a 64-bit SCALAR_VALUE */ - mark_reg_unknown(env, caller->regs, BPF_REG_0); - caller->regs[BPF_REG_0].subreg_def = DEF_NOT_SUBREG; - - /* continue with next insn after call */ - return 0; - } - } - callee = kzalloc(sizeof(*callee), GFP_KERNEL); if (!callee) return -ENOMEM; @@ -5407,7 +3890,11 @@ static int check_func_call(struct bpf_verifier_env *env, struct bpf_insn *insn, for (i = BPF_REG_1; i <= BPF_REG_5; i++) callee->regs[i] = caller->regs[i]; - clear_caller_saved_regs(env, caller->regs); + /* after the call registers r0 - r5 were scratched */ + for (i = 0; i < CALLER_SAVED_REGS; i++) { + mark_reg_not_init(env, caller->regs, caller_saved[i]); + check_reg_arg(env, caller_saved[i], DST_OP_NO_MARK); + } /* only increment it after check_reg_arg() finished */ state->curframe++; @@ -5467,24 +3954,44 @@ static int prepare_func_exit(struct bpf_verifier_env *env, int *insn_idx) return 0; } -static void do_refine_retval_range(struct bpf_reg_state *regs, int ret_type, - int func_id, - struct bpf_call_arg_meta *meta) +static int do_refine_retval_range(struct bpf_verifier_env *env, + struct bpf_reg_state *regs, int ret_type, + int func_id, struct bpf_call_arg_meta *meta) { struct bpf_reg_state *ret_reg = ®s[BPF_REG_0]; + struct bpf_reg_state tmp_reg = *ret_reg; + bool ret; if (ret_type != RET_INTEGER || (func_id != BPF_FUNC_get_stack && - func_id != BPF_FUNC_probe_read_str && - func_id != BPF_FUNC_probe_read_kernel_str && - func_id != BPF_FUNC_probe_read_user_str)) - return; + func_id != BPF_FUNC_probe_read_str)) + return 0; + /* Error case where ret is in interval [S32MIN, -1]. */ + ret_reg->smin_value = S32_MIN; + ret_reg->smax_value = -1; + + __reg_deduce_bounds(ret_reg); + __reg_bound_offset(ret_reg); + __update_reg_bounds(ret_reg); + + ret = push_stack(env, env->insn_idx + 1, env->insn_idx, false); + if (!ret) + return -EFAULT; + + *ret_reg = tmp_reg; + + /* Success case where ret is in range [0, msize_max_value]. */ + ret_reg->smin_value = 0; ret_reg->smax_value = meta->msize_max_value; - ret_reg->s32_max_value = meta->msize_max_value; - ret_reg->smin_value = -MAX_ERRNO; - ret_reg->s32_min_value = -MAX_ERRNO; - reg_bounds_sync(ret_reg); + ret_reg->umin_value = ret_reg->smin_value; + ret_reg->umax_value = ret_reg->smax_value; + + __reg_deduce_bounds(ret_reg); + __reg_bound_offset(ret_reg); + __update_reg_bounds(ret_reg); + + return 0; } static int @@ -5521,49 +4028,12 @@ record_func_map(struct bpf_verifier_env *env, struct bpf_call_arg_meta *meta, return -EACCES; } - if (!BPF_MAP_PTR(aux->map_ptr_state)) + if (!BPF_MAP_PTR(aux->map_state)) bpf_map_ptr_store(aux, meta->map_ptr, - !meta->map_ptr->bypass_spec_v1); - else if (BPF_MAP_PTR(aux->map_ptr_state) != meta->map_ptr) + meta->map_ptr->unpriv_array); + else if (BPF_MAP_PTR(aux->map_state) != meta->map_ptr) bpf_map_ptr_store(aux, BPF_MAP_PTR_POISON, - !meta->map_ptr->bypass_spec_v1); - return 0; -} - -static int -record_func_key(struct bpf_verifier_env *env, struct bpf_call_arg_meta *meta, - int func_id, int insn_idx) -{ - struct bpf_insn_aux_data *aux = &env->insn_aux_data[insn_idx]; - struct bpf_reg_state *regs = cur_regs(env), *reg; - struct bpf_map *map = meta->map_ptr; - u64 val, max; - int err; - - if (func_id != BPF_FUNC_tail_call) - return 0; - if (!map || map->map_type != BPF_MAP_TYPE_PROG_ARRAY) { - verbose(env, "kernel subsystem misconfigured verifier\n"); - return -EINVAL; - } - - reg = ®s[BPF_REG_3]; - val = reg->var_off.value; - max = map->max_entries; - - if (!(register_is_const(reg) && val < max)) { - bpf_map_key_store(aux, BPF_MAP_KEY_POISON); - return 0; - } - - err = mark_chain_precision(env, BPF_REG_3); - if (err) - return err; - if (bpf_map_key_unseen(aux)) - bpf_map_key_store(aux, val); - else if (!bpf_map_key_poisoned(aux) && - bpf_map_key_immediate(aux) != val) - bpf_map_key_store(aux, BPF_MAP_KEY_POISON); + meta->map_ptr->unpriv_array); return 0; } @@ -5608,11 +4078,6 @@ static int check_helper_call(struct bpf_verifier_env *env, int func_id, int insn return -EINVAL; } - if (fn->allowed && !fn->allowed(env->prog)) { - verbose(env, "helper call is not allowed in probe\n"); - return -EINVAL; - } - /* With LD_ABS/IND some JITs save/restore skb from r1. */ changes_data = bpf_helper_changes_pkt_data(fn->func); if (changes_data && fn->arg1_type != ARG_PTR_TO_CTX) { @@ -5633,17 +4098,23 @@ static int check_helper_call(struct bpf_verifier_env *env, int func_id, int insn meta.func_id = func_id; /* check args */ - for (i = 0; i < 5; i++) { - err = check_func_arg(env, i, &meta, fn); - if (err) - return err; - } - - err = record_func_map(env, &meta, func_id, insn_idx); + err = check_func_arg(env, BPF_REG_1, fn->arg1_type, &meta); + if (err) + return err; + err = check_func_arg(env, BPF_REG_2, fn->arg2_type, &meta); + if (err) + return err; + err = check_func_arg(env, BPF_REG_3, fn->arg3_type, &meta); + if (err) + return err; + err = check_func_arg(env, BPF_REG_4, fn->arg4_type, &meta); + if (err) + return err; + err = check_func_arg(env, BPF_REG_5, fn->arg5_type, &meta); if (err) return err; - err = record_func_key(env, &meta, func_id, insn_idx); + err = record_func_map(env, &meta, func_id, insn_idx); if (err) return err; @@ -5718,74 +4189,30 @@ static int check_helper_call(struct bpf_verifier_env *env, int func_id, int insn regs[BPF_REG_0].id = ++env->id_gen; } else { regs[BPF_REG_0].type = PTR_TO_MAP_VALUE_OR_NULL; + regs[BPF_REG_0].id = ++env->id_gen; } } else if (fn->ret_type == RET_PTR_TO_SOCKET_OR_NULL) { mark_reg_known_zero(env, regs, BPF_REG_0); regs[BPF_REG_0].type = PTR_TO_SOCKET_OR_NULL; + regs[BPF_REG_0].id = ++env->id_gen; } else if (fn->ret_type == RET_PTR_TO_SOCK_COMMON_OR_NULL) { mark_reg_known_zero(env, regs, BPF_REG_0); regs[BPF_REG_0].type = PTR_TO_SOCK_COMMON_OR_NULL; + regs[BPF_REG_0].id = ++env->id_gen; } else if (fn->ret_type == RET_PTR_TO_TCP_SOCK_OR_NULL) { mark_reg_known_zero(env, regs, BPF_REG_0); regs[BPF_REG_0].type = PTR_TO_TCP_SOCK_OR_NULL; - } else if (fn->ret_type == RET_PTR_TO_ALLOC_MEM_OR_NULL) { - mark_reg_known_zero(env, regs, BPF_REG_0); - regs[BPF_REG_0].type = PTR_TO_MEM_OR_NULL; - regs[BPF_REG_0].mem_size = meta.mem_size; - } else if (fn->ret_type == RET_PTR_TO_MEM_OR_BTF_ID_OR_NULL || - fn->ret_type == RET_PTR_TO_MEM_OR_BTF_ID) { - const struct btf_type *t; - - mark_reg_known_zero(env, regs, BPF_REG_0); - t = btf_type_skip_modifiers(btf_vmlinux, meta.ret_btf_id, NULL); - if (!btf_type_is_struct(t)) { - u32 tsize; - const struct btf_type *ret; - const char *tname; - - /* resolve the type size of ksym. */ - ret = btf_resolve_size(btf_vmlinux, t, &tsize); - if (IS_ERR(ret)) { - tname = btf_name_by_offset(btf_vmlinux, t->name_off); - verbose(env, "unable to resolve the size of type '%s': %ld\n", - tname, PTR_ERR(ret)); - return -EINVAL; - } - regs[BPF_REG_0].type = - fn->ret_type == RET_PTR_TO_MEM_OR_BTF_ID ? - PTR_TO_MEM : PTR_TO_MEM_OR_NULL; - regs[BPF_REG_0].mem_size = tsize; - } else { - regs[BPF_REG_0].type = - fn->ret_type == RET_PTR_TO_MEM_OR_BTF_ID ? - PTR_TO_BTF_ID : PTR_TO_BTF_ID_OR_NULL; - regs[BPF_REG_0].btf_id = meta.ret_btf_id; - } - } else if (fn->ret_type == RET_PTR_TO_BTF_ID_OR_NULL) { - int ret_btf_id; - - mark_reg_known_zero(env, regs, BPF_REG_0); - regs[BPF_REG_0].type = PTR_TO_BTF_ID_OR_NULL; - ret_btf_id = *fn->ret_btf_id; - if (ret_btf_id == 0) { - verbose(env, "invalid return type %d of func %s#%d\n", - fn->ret_type, func_id_name(func_id), func_id); - return -EINVAL; - } - regs[BPF_REG_0].btf_id = ret_btf_id; + regs[BPF_REG_0].id = ++env->id_gen; } else { verbose(env, "unknown return type %d of func %s#%d\n", fn->ret_type, func_id_name(func_id), func_id); return -EINVAL; } - if (reg_type_may_be_null(regs[BPF_REG_0].type)) - regs[BPF_REG_0].id = ++env->id_gen; - if (is_ptr_cast_function(func_id)) { /* For release_reference() */ regs[BPF_REG_0].ref_obj_id = meta.ref_obj_id; - } else if (is_acquire_function(func_id, meta.map_ptr)) { + } else if (is_acquire_function(func_id)) { int id = acquire_reference_state(env, insn_idx); if (id < 0) @@ -5796,15 +4223,15 @@ static int check_helper_call(struct bpf_verifier_env *env, int func_id, int insn regs[BPF_REG_0].ref_obj_id = id; } - do_refine_retval_range(regs, fn->ret_type, func_id, &meta); + err = do_refine_retval_range(env, regs, fn->ret_type, func_id, &meta); + if (err) + return err; err = check_map_func_compatibility(env, meta.map_ptr, func_id); if (err) return err; - if ((func_id == BPF_FUNC_get_stack || - func_id == BPF_FUNC_get_task_stack) && - !env->prog->has_callchain_buf) { + if (func_id == BPF_FUNC_get_stack && !env->prog->has_callchain_buf) { const char *err_str; #ifdef CONFIG_PERF_EVENTS @@ -5822,9 +4249,6 @@ static int check_helper_call(struct bpf_verifier_env *env, int func_id, int insn env->prog->has_callchain_buf = true; } - if (func_id == BPF_FUNC_get_stackid || func_id == BPF_FUNC_get_stack) - env->prog->call_get_stack = true; - if (changes_data) clear_all_pkt_pointers(env); return 0; @@ -5840,16 +4264,6 @@ static bool signed_add_overflows(s64 a, s64 b) return res < a; } -static bool signed_add32_overflows(s32 a, s32 b) -{ - /* Do the add in u32, where overflow is well-defined */ - s32 res = (s32)((u32)a + (u32)b); - - if (b < 0) - return res > a; - return res < a; -} - static bool signed_sub_overflows(s64 a, s64 b) { /* Do the sub in u64, where overflow is well-defined */ @@ -5860,16 +4274,6 @@ static bool signed_sub_overflows(s64 a, s64 b) return res > a; } -static bool signed_sub32_overflows(s32 a, s32 b) -{ - /* Do the sub in u32, where overflow is well-defined */ - s32 res = (s32)((u32)a - (u32)b); - - if (b < 0) - return res < a; - return res > a; -} - static bool check_reg_sane_offset(struct bpf_verifier_env *env, const struct bpf_reg_state *reg, enum bpf_reg_type type) @@ -5952,7 +4356,7 @@ static int retrieve_ptr_limit(const struct bpf_reg_state *ptr_reg, static bool can_skip_alu_sanitation(const struct bpf_verifier_env *env, const struct bpf_insn *insn) { - return env->bypass_spec_v1 || BPF_SRC(insn->code) == BPF_K; + return env->allow_ptr_leaks || BPF_SRC(insn->code) == BPF_K; } static int update_alu_sanitation_state(struct bpf_insn_aux_data *aux, @@ -6101,7 +4505,7 @@ do_sim: */ if (!ptr_is_dst_reg) { tmp = *dst_reg; - copy_register_state(dst_reg, ptr_reg); + *dst_reg = *ptr_reg; } ret = sanitize_speculative_path(env, NULL, env->insn_idx + 1, env->insn_idx); @@ -6162,40 +4566,6 @@ static int sanitize_err(struct bpf_verifier_env *env, return -EACCES; } -/* check that stack access falls within stack limits and that 'reg' doesn't - * have a variable offset. - * - * Variable offset is prohibited for unprivileged mode for simplicity since it - * requires corresponding support in Spectre masking for stack ALU. See also - * retrieve_ptr_limit(). - * - * - * 'off' includes 'reg->off'. - */ -static int check_stack_access_for_ptr_arithmetic( - struct bpf_verifier_env *env, - int regno, - const struct bpf_reg_state *reg, - int off) -{ - if (!tnum_is_const(reg->var_off)) { - char tn_buf[48]; - - tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); - verbose(env, "R%d variable stack access prohibited for !root, var_off=%s off=%d\n", - regno, tn_buf, off); - return -EACCES; - } - - if (off >= 0 || off < -MAX_BPF_STACK) { - verbose(env, "R%d stack pointer arithmetic goes out of range, " - "prohibited for !root; off=%d\n", regno, off); - return -EACCES; - } - - return 0; -} - static int sanitize_check_bounds(struct bpf_verifier_env *env, const struct bpf_insn *insn, const struct bpf_reg_state *dst_reg) @@ -6205,14 +4575,17 @@ static int sanitize_check_bounds(struct bpf_verifier_env *env, /* For unprivileged we require that resulting offset must be in bounds * in order to be able to sanitize access later on. */ - if (env->bypass_spec_v1) + if (env->allow_ptr_leaks) return 0; switch (dst_reg->type) { case PTR_TO_STACK: - if (check_stack_access_for_ptr_arithmetic(env, dst, dst_reg, - dst_reg->off + dst_reg->var_off.value)) + if (check_stack_access(env, dst_reg, dst_reg->off + + dst_reg->var_off.value, 1)) { + verbose(env, "R%d stack pointer arithmetic goes out of range, " + "prohibited for !root\n", dst); return -EACCES; + } break; case PTR_TO_MAP_VALUE: if (check_map_access(env, dst, dst_reg->off, 1, false)) { @@ -6264,11 +4637,6 @@ static int adjust_ptr_min_max_vals(struct bpf_verifier_env *env, if (BPF_CLASS(insn->code) != BPF_ALU64) { /* 32-bit ALU ops on pointers produce (meaningless) scalars */ - if (opcode == BPF_SUB && env->allow_ptr_leaks) { - __mark_reg_unknown(env, dst_reg); - return 0; - } - verbose(env, "R%d 32-bit pointer arithmetic prohibited\n", dst); @@ -6284,19 +4652,19 @@ static int adjust_ptr_min_max_vals(struct bpf_verifier_env *env, /* smin_val represents the known value */ if (known && smin_val == 0 && opcode == BPF_ADD) break; - fallthrough; + /* fall-through */ case PTR_TO_PACKET_END: case PTR_TO_SOCKET: + case PTR_TO_SOCKET_OR_NULL: case PTR_TO_SOCK_COMMON: + case PTR_TO_SOCK_COMMON_OR_NULL: case PTR_TO_TCP_SOCK: + case PTR_TO_TCP_SOCK_OR_NULL: case PTR_TO_XDP_SOCK: -reject: verbose(env, "R%d pointer arithmetic on %s prohibited\n", dst, reg_type_str[ptr_reg->type]); return -EACCES; default: - if (reg_type_may_be_null(ptr_reg->type)) - goto reject; break; } @@ -6310,9 +4678,6 @@ reject: !check_reg_sane_offset(env, ptr_reg, ptr_reg->type)) return -EINVAL; - /* pointer types do not carry 32-bit bounds at the moment. */ - __mark_reg32_unbounded(dst_reg); - if (sanitize_needed(opcode)) { ret = sanitize_ptr_alu(env, insn, ptr_reg, off_reg, dst_reg, &info, false); @@ -6447,7 +4812,11 @@ reject: if (!check_reg_sane_offset(env, dst_reg, ptr_reg->type)) return -EINVAL; - reg_bounds_sync(dst_reg); + + __update_reg_bounds(dst_reg); + __reg_deduce_bounds(dst_reg); + __reg_bound_offset(dst_reg); + if (sanitize_check_bounds(env, insn, dst_reg) < 0) return -EACCES; if (sanitize_needed(opcode)) { @@ -6460,573 +4829,6 @@ reject: return 0; } -static void scalar32_min_max_add(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - s32 smin_val = src_reg->s32_min_value; - s32 smax_val = src_reg->s32_max_value; - u32 umin_val = src_reg->u32_min_value; - u32 umax_val = src_reg->u32_max_value; - - if (signed_add32_overflows(dst_reg->s32_min_value, smin_val) || - signed_add32_overflows(dst_reg->s32_max_value, smax_val)) { - dst_reg->s32_min_value = S32_MIN; - dst_reg->s32_max_value = S32_MAX; - } else { - dst_reg->s32_min_value += smin_val; - dst_reg->s32_max_value += smax_val; - } - if (dst_reg->u32_min_value + umin_val < umin_val || - dst_reg->u32_max_value + umax_val < umax_val) { - dst_reg->u32_min_value = 0; - dst_reg->u32_max_value = U32_MAX; - } else { - dst_reg->u32_min_value += umin_val; - dst_reg->u32_max_value += umax_val; - } -} - -static void scalar_min_max_add(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - s64 smin_val = src_reg->smin_value; - s64 smax_val = src_reg->smax_value; - u64 umin_val = src_reg->umin_value; - u64 umax_val = src_reg->umax_value; - - if (signed_add_overflows(dst_reg->smin_value, smin_val) || - signed_add_overflows(dst_reg->smax_value, smax_val)) { - dst_reg->smin_value = S64_MIN; - dst_reg->smax_value = S64_MAX; - } else { - dst_reg->smin_value += smin_val; - dst_reg->smax_value += smax_val; - } - if (dst_reg->umin_value + umin_val < umin_val || - dst_reg->umax_value + umax_val < umax_val) { - dst_reg->umin_value = 0; - dst_reg->umax_value = U64_MAX; - } else { - dst_reg->umin_value += umin_val; - dst_reg->umax_value += umax_val; - } -} - -static void scalar32_min_max_sub(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - s32 smin_val = src_reg->s32_min_value; - s32 smax_val = src_reg->s32_max_value; - u32 umin_val = src_reg->u32_min_value; - u32 umax_val = src_reg->u32_max_value; - - if (signed_sub32_overflows(dst_reg->s32_min_value, smax_val) || - signed_sub32_overflows(dst_reg->s32_max_value, smin_val)) { - /* Overflow possible, we know nothing */ - dst_reg->s32_min_value = S32_MIN; - dst_reg->s32_max_value = S32_MAX; - } else { - dst_reg->s32_min_value -= smax_val; - dst_reg->s32_max_value -= smin_val; - } - if (dst_reg->u32_min_value < umax_val) { - /* Overflow possible, we know nothing */ - dst_reg->u32_min_value = 0; - dst_reg->u32_max_value = U32_MAX; - } else { - /* Cannot overflow (as long as bounds are consistent) */ - dst_reg->u32_min_value -= umax_val; - dst_reg->u32_max_value -= umin_val; - } -} - -static void scalar_min_max_sub(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - s64 smin_val = src_reg->smin_value; - s64 smax_val = src_reg->smax_value; - u64 umin_val = src_reg->umin_value; - u64 umax_val = src_reg->umax_value; - - if (signed_sub_overflows(dst_reg->smin_value, smax_val) || - signed_sub_overflows(dst_reg->smax_value, smin_val)) { - /* Overflow possible, we know nothing */ - dst_reg->smin_value = S64_MIN; - dst_reg->smax_value = S64_MAX; - } else { - dst_reg->smin_value -= smax_val; - dst_reg->smax_value -= smin_val; - } - if (dst_reg->umin_value < umax_val) { - /* Overflow possible, we know nothing */ - dst_reg->umin_value = 0; - dst_reg->umax_value = U64_MAX; - } else { - /* Cannot overflow (as long as bounds are consistent) */ - dst_reg->umin_value -= umax_val; - dst_reg->umax_value -= umin_val; - } -} - -static void scalar32_min_max_mul(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - s32 smin_val = src_reg->s32_min_value; - u32 umin_val = src_reg->u32_min_value; - u32 umax_val = src_reg->u32_max_value; - - if (smin_val < 0 || dst_reg->s32_min_value < 0) { - /* Ain't nobody got time to multiply that sign */ - __mark_reg32_unbounded(dst_reg); - return; - } - /* Both values are positive, so we can work with unsigned and - * copy the result to signed (unless it exceeds S32_MAX). - */ - if (umax_val > U16_MAX || dst_reg->u32_max_value > U16_MAX) { - /* Potential overflow, we know nothing */ - __mark_reg32_unbounded(dst_reg); - return; - } - dst_reg->u32_min_value *= umin_val; - dst_reg->u32_max_value *= umax_val; - if (dst_reg->u32_max_value > S32_MAX) { - /* Overflow possible, we know nothing */ - dst_reg->s32_min_value = S32_MIN; - dst_reg->s32_max_value = S32_MAX; - } else { - dst_reg->s32_min_value = dst_reg->u32_min_value; - dst_reg->s32_max_value = dst_reg->u32_max_value; - } -} - -static void scalar_min_max_mul(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - s64 smin_val = src_reg->smin_value; - u64 umin_val = src_reg->umin_value; - u64 umax_val = src_reg->umax_value; - - if (smin_val < 0 || dst_reg->smin_value < 0) { - /* Ain't nobody got time to multiply that sign */ - __mark_reg64_unbounded(dst_reg); - return; - } - /* Both values are positive, so we can work with unsigned and - * copy the result to signed (unless it exceeds S64_MAX). - */ - if (umax_val > U32_MAX || dst_reg->umax_value > U32_MAX) { - /* Potential overflow, we know nothing */ - __mark_reg64_unbounded(dst_reg); - return; - } - dst_reg->umin_value *= umin_val; - dst_reg->umax_value *= umax_val; - if (dst_reg->umax_value > S64_MAX) { - /* Overflow possible, we know nothing */ - dst_reg->smin_value = S64_MIN; - dst_reg->smax_value = S64_MAX; - } else { - dst_reg->smin_value = dst_reg->umin_value; - dst_reg->smax_value = dst_reg->umax_value; - } -} - -static void scalar32_min_max_and(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - bool src_known = tnum_subreg_is_const(src_reg->var_off); - bool dst_known = tnum_subreg_is_const(dst_reg->var_off); - struct tnum var32_off = tnum_subreg(dst_reg->var_off); - s32 smin_val = src_reg->s32_min_value; - u32 umax_val = src_reg->u32_max_value; - - if (src_known && dst_known) { - __mark_reg32_known(dst_reg, var32_off.value); - return; - } - - /* We get our minimum from the var_off, since that's inherently - * bitwise. Our maximum is the minimum of the operands' maxima. - */ - dst_reg->u32_min_value = var32_off.value; - dst_reg->u32_max_value = min(dst_reg->u32_max_value, umax_val); - if (dst_reg->s32_min_value < 0 || smin_val < 0) { - /* Lose signed bounds when ANDing negative numbers, - * ain't nobody got time for that. - */ - dst_reg->s32_min_value = S32_MIN; - dst_reg->s32_max_value = S32_MAX; - } else { - /* ANDing two positives gives a positive, so safe to - * cast result into s64. - */ - dst_reg->s32_min_value = dst_reg->u32_min_value; - dst_reg->s32_max_value = dst_reg->u32_max_value; - } -} - -static void scalar_min_max_and(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - bool src_known = tnum_is_const(src_reg->var_off); - bool dst_known = tnum_is_const(dst_reg->var_off); - s64 smin_val = src_reg->smin_value; - u64 umax_val = src_reg->umax_value; - - if (src_known && dst_known) { - __mark_reg_known(dst_reg, dst_reg->var_off.value); - return; - } - - /* We get our minimum from the var_off, since that's inherently - * bitwise. Our maximum is the minimum of the operands' maxima. - */ - dst_reg->umin_value = dst_reg->var_off.value; - dst_reg->umax_value = min(dst_reg->umax_value, umax_val); - if (dst_reg->smin_value < 0 || smin_val < 0) { - /* Lose signed bounds when ANDing negative numbers, - * ain't nobody got time for that. - */ - dst_reg->smin_value = S64_MIN; - dst_reg->smax_value = S64_MAX; - } else { - /* ANDing two positives gives a positive, so safe to - * cast result into s64. - */ - dst_reg->smin_value = dst_reg->umin_value; - dst_reg->smax_value = dst_reg->umax_value; - } - /* We may learn something more from the var_off */ - __update_reg_bounds(dst_reg); -} - -static void scalar32_min_max_or(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - bool src_known = tnum_subreg_is_const(src_reg->var_off); - bool dst_known = tnum_subreg_is_const(dst_reg->var_off); - struct tnum var32_off = tnum_subreg(dst_reg->var_off); - s32 smin_val = src_reg->s32_min_value; - u32 umin_val = src_reg->u32_min_value; - - if (src_known && dst_known) { - __mark_reg32_known(dst_reg, var32_off.value); - return; - } - - /* We get our maximum from the var_off, and our minimum is the - * maximum of the operands' minima - */ - dst_reg->u32_min_value = max(dst_reg->u32_min_value, umin_val); - dst_reg->u32_max_value = var32_off.value | var32_off.mask; - if (dst_reg->s32_min_value < 0 || smin_val < 0) { - /* Lose signed bounds when ORing negative numbers, - * ain't nobody got time for that. - */ - dst_reg->s32_min_value = S32_MIN; - dst_reg->s32_max_value = S32_MAX; - } else { - /* ORing two positives gives a positive, so safe to - * cast result into s64. - */ - dst_reg->s32_min_value = dst_reg->u32_min_value; - dst_reg->s32_max_value = dst_reg->u32_max_value; - } -} - -static void scalar_min_max_or(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - bool src_known = tnum_is_const(src_reg->var_off); - bool dst_known = tnum_is_const(dst_reg->var_off); - s64 smin_val = src_reg->smin_value; - u64 umin_val = src_reg->umin_value; - - if (src_known && dst_known) { - __mark_reg_known(dst_reg, dst_reg->var_off.value); - return; - } - - /* We get our maximum from the var_off, and our minimum is the - * maximum of the operands' minima - */ - dst_reg->umin_value = max(dst_reg->umin_value, umin_val); - dst_reg->umax_value = dst_reg->var_off.value | dst_reg->var_off.mask; - if (dst_reg->smin_value < 0 || smin_val < 0) { - /* Lose signed bounds when ORing negative numbers, - * ain't nobody got time for that. - */ - dst_reg->smin_value = S64_MIN; - dst_reg->smax_value = S64_MAX; - } else { - /* ORing two positives gives a positive, so safe to - * cast result into s64. - */ - dst_reg->smin_value = dst_reg->umin_value; - dst_reg->smax_value = dst_reg->umax_value; - } - /* We may learn something more from the var_off */ - __update_reg_bounds(dst_reg); -} - -static void scalar32_min_max_xor(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - bool src_known = tnum_subreg_is_const(src_reg->var_off); - bool dst_known = tnum_subreg_is_const(dst_reg->var_off); - struct tnum var32_off = tnum_subreg(dst_reg->var_off); - s32 smin_val = src_reg->s32_min_value; - - if (src_known && dst_known) { - __mark_reg32_known(dst_reg, var32_off.value); - return; - } - - /* We get both minimum and maximum from the var32_off. */ - dst_reg->u32_min_value = var32_off.value; - dst_reg->u32_max_value = var32_off.value | var32_off.mask; - - if (dst_reg->s32_min_value >= 0 && smin_val >= 0) { - /* XORing two positive sign numbers gives a positive, - * so safe to cast u32 result into s32. - */ - dst_reg->s32_min_value = dst_reg->u32_min_value; - dst_reg->s32_max_value = dst_reg->u32_max_value; - } else { - dst_reg->s32_min_value = S32_MIN; - dst_reg->s32_max_value = S32_MAX; - } -} - -static void scalar_min_max_xor(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - bool src_known = tnum_is_const(src_reg->var_off); - bool dst_known = tnum_is_const(dst_reg->var_off); - s64 smin_val = src_reg->smin_value; - - if (src_known && dst_known) { - /* dst_reg->var_off.value has been updated earlier */ - __mark_reg_known(dst_reg, dst_reg->var_off.value); - return; - } - - /* We get both minimum and maximum from the var_off. */ - dst_reg->umin_value = dst_reg->var_off.value; - dst_reg->umax_value = dst_reg->var_off.value | dst_reg->var_off.mask; - - if (dst_reg->smin_value >= 0 && smin_val >= 0) { - /* XORing two positive sign numbers gives a positive, - * so safe to cast u64 result into s64. - */ - dst_reg->smin_value = dst_reg->umin_value; - dst_reg->smax_value = dst_reg->umax_value; - } else { - dst_reg->smin_value = S64_MIN; - dst_reg->smax_value = S64_MAX; - } - - __update_reg_bounds(dst_reg); -} - -static void __scalar32_min_max_lsh(struct bpf_reg_state *dst_reg, - u64 umin_val, u64 umax_val) -{ - /* We lose all sign bit information (except what we can pick - * up from var_off) - */ - dst_reg->s32_min_value = S32_MIN; - dst_reg->s32_max_value = S32_MAX; - /* If we might shift our top bit out, then we know nothing */ - if (umax_val > 31 || dst_reg->u32_max_value > 1ULL << (31 - umax_val)) { - dst_reg->u32_min_value = 0; - dst_reg->u32_max_value = U32_MAX; - } else { - dst_reg->u32_min_value <<= umin_val; - dst_reg->u32_max_value <<= umax_val; - } -} - -static void scalar32_min_max_lsh(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - u32 umax_val = src_reg->u32_max_value; - u32 umin_val = src_reg->u32_min_value; - /* u32 alu operation will zext upper bits */ - struct tnum subreg = tnum_subreg(dst_reg->var_off); - - __scalar32_min_max_lsh(dst_reg, umin_val, umax_val); - dst_reg->var_off = tnum_subreg(tnum_lshift(subreg, umin_val)); - /* Not required but being careful mark reg64 bounds as unknown so - * that we are forced to pick them up from tnum and zext later and - * if some path skips this step we are still safe. - */ - __mark_reg64_unbounded(dst_reg); - __update_reg32_bounds(dst_reg); -} - -static void __scalar64_min_max_lsh(struct bpf_reg_state *dst_reg, - u64 umin_val, u64 umax_val) -{ - /* Special case <<32 because it is a common compiler pattern to sign - * extend subreg by doing <<32 s>>32. In this case if 32bit bounds are - * positive we know this shift will also be positive so we can track - * bounds correctly. Otherwise we lose all sign bit information except - * what we can pick up from var_off. Perhaps we can generalize this - * later to shifts of any length. - */ - if (umin_val == 32 && umax_val == 32 && dst_reg->s32_max_value >= 0) - dst_reg->smax_value = (s64)dst_reg->s32_max_value << 32; - else - dst_reg->smax_value = S64_MAX; - - if (umin_val == 32 && umax_val == 32 && dst_reg->s32_min_value >= 0) - dst_reg->smin_value = (s64)dst_reg->s32_min_value << 32; - else - dst_reg->smin_value = S64_MIN; - - /* If we might shift our top bit out, then we know nothing */ - if (dst_reg->umax_value > 1ULL << (63 - umax_val)) { - dst_reg->umin_value = 0; - dst_reg->umax_value = U64_MAX; - } else { - dst_reg->umin_value <<= umin_val; - dst_reg->umax_value <<= umax_val; - } -} - -static void scalar_min_max_lsh(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - u64 umax_val = src_reg->umax_value; - u64 umin_val = src_reg->umin_value; - - /* scalar64 calc uses 32bit unshifted bounds so must be called first */ - __scalar64_min_max_lsh(dst_reg, umin_val, umax_val); - __scalar32_min_max_lsh(dst_reg, umin_val, umax_val); - - dst_reg->var_off = tnum_lshift(dst_reg->var_off, umin_val); - /* We may learn something more from the var_off */ - __update_reg_bounds(dst_reg); -} - -static void scalar32_min_max_rsh(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - struct tnum subreg = tnum_subreg(dst_reg->var_off); - u32 umax_val = src_reg->u32_max_value; - u32 umin_val = src_reg->u32_min_value; - - /* BPF_RSH is an unsigned shift. If the value in dst_reg might - * be negative, then either: - * 1) src_reg might be zero, so the sign bit of the result is - * unknown, so we lose our signed bounds - * 2) it's known negative, thus the unsigned bounds capture the - * signed bounds - * 3) the signed bounds cross zero, so they tell us nothing - * about the result - * If the value in dst_reg is known nonnegative, then again the - * unsigned bounts capture the signed bounds. - * Thus, in all cases it suffices to blow away our signed bounds - * and rely on inferring new ones from the unsigned bounds and - * var_off of the result. - */ - dst_reg->s32_min_value = S32_MIN; - dst_reg->s32_max_value = S32_MAX; - - dst_reg->var_off = tnum_rshift(subreg, umin_val); - dst_reg->u32_min_value >>= umax_val; - dst_reg->u32_max_value >>= umin_val; - - __mark_reg64_unbounded(dst_reg); - __update_reg32_bounds(dst_reg); -} - -static void scalar_min_max_rsh(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - u64 umax_val = src_reg->umax_value; - u64 umin_val = src_reg->umin_value; - - /* BPF_RSH is an unsigned shift. If the value in dst_reg might - * be negative, then either: - * 1) src_reg might be zero, so the sign bit of the result is - * unknown, so we lose our signed bounds - * 2) it's known negative, thus the unsigned bounds capture the - * signed bounds - * 3) the signed bounds cross zero, so they tell us nothing - * about the result - * If the value in dst_reg is known nonnegative, then again the - * unsigned bounts capture the signed bounds. - * Thus, in all cases it suffices to blow away our signed bounds - * and rely on inferring new ones from the unsigned bounds and - * var_off of the result. - */ - dst_reg->smin_value = S64_MIN; - dst_reg->smax_value = S64_MAX; - dst_reg->var_off = tnum_rshift(dst_reg->var_off, umin_val); - dst_reg->umin_value >>= umax_val; - dst_reg->umax_value >>= umin_val; - - /* Its not easy to operate on alu32 bounds here because it depends - * on bits being shifted in. Take easy way out and mark unbounded - * so we can recalculate later from tnum. - */ - __mark_reg32_unbounded(dst_reg); - __update_reg_bounds(dst_reg); -} - -static void scalar32_min_max_arsh(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - u64 umin_val = src_reg->u32_min_value; - - /* Upon reaching here, src_known is true and - * umax_val is equal to umin_val. - */ - dst_reg->s32_min_value = (u32)(((s32)dst_reg->s32_min_value) >> umin_val); - dst_reg->s32_max_value = (u32)(((s32)dst_reg->s32_max_value) >> umin_val); - - dst_reg->var_off = tnum_arshift(tnum_subreg(dst_reg->var_off), umin_val, 32); - - /* blow away the dst_reg umin_value/umax_value and rely on - * dst_reg var_off to refine the result. - */ - dst_reg->u32_min_value = 0; - dst_reg->u32_max_value = U32_MAX; - - __mark_reg64_unbounded(dst_reg); - __update_reg32_bounds(dst_reg); -} - -static void scalar_min_max_arsh(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg) -{ - u64 umin_val = src_reg->umin_value; - - /* Upon reaching here, src_known is true and umax_val is equal - * to umin_val. - */ - dst_reg->smin_value >>= umin_val; - dst_reg->smax_value >>= umin_val; - - dst_reg->var_off = tnum_arshift(dst_reg->var_off, umin_val, 64); - - /* blow away the dst_reg umin_value/umax_value and rely on - * dst_reg var_off to refine the result. - */ - dst_reg->umin_value = 0; - dst_reg->umax_value = U64_MAX; - - /* Its not easy to operate on alu32 bounds here because it depends - * on bits being shifted in from upper 32-bits. Take easy way out - * and mark unbounded so we can recalculate later from tnum. - */ - __mark_reg32_unbounded(dst_reg); - __update_reg_bounds(dst_reg); -} - /* WARNING: This function does calculations on 64-bit values, but the actual * execution may occur on 32-bit values. Therefore, things like bitshifts * need extra checks in the 32-bit case. @@ -7038,47 +4840,35 @@ static int adjust_scalar_min_max_vals(struct bpf_verifier_env *env, { struct bpf_reg_state *regs = cur_regs(env); u8 opcode = BPF_OP(insn->code); - bool src_known; + bool src_known, dst_known; s64 smin_val, smax_val; u64 umin_val, umax_val; - s32 s32_min_val, s32_max_val; - u32 u32_min_val, u32_max_val; u64 insn_bitness = (BPF_CLASS(insn->code) == BPF_ALU64) ? 64 : 32; int ret; - bool alu32 = (BPF_CLASS(insn->code) != BPF_ALU64); + + if (insn_bitness == 32) { + /* Relevant for 32-bit RSH: Information can propagate towards + * LSB, so it isn't sufficient to only truncate the output to + * 32 bits. + */ + coerce_reg_to_size(dst_reg, 4); + coerce_reg_to_size(&src_reg, 4); + } smin_val = src_reg.smin_value; smax_val = src_reg.smax_value; umin_val = src_reg.umin_value; umax_val = src_reg.umax_value; + src_known = tnum_is_const(src_reg.var_off); + dst_known = tnum_is_const(dst_reg->var_off); - s32_min_val = src_reg.s32_min_value; - s32_max_val = src_reg.s32_max_value; - u32_min_val = src_reg.u32_min_value; - u32_max_val = src_reg.u32_max_value; - - if (alu32) { - src_known = tnum_subreg_is_const(src_reg.var_off); - if ((src_known && - (s32_min_val != s32_max_val || u32_min_val != u32_max_val)) || - s32_min_val > s32_max_val || u32_min_val > u32_max_val) { - /* Taint dst register if offset had invalid bounds - * derived from e.g. dead branches. - */ - __mark_reg_unknown(env, dst_reg); - return 0; - } - } else { - src_known = tnum_is_const(src_reg.var_off); - if ((src_known && - (smin_val != smax_val || umin_val != umax_val)) || - smin_val > smax_val || umin_val > umax_val) { - /* Taint dst register if offset had invalid bounds - * derived from e.g. dead branches. - */ - __mark_reg_unknown(env, dst_reg); - return 0; - } + if ((src_known && (smin_val != smax_val || umin_val != umax_val)) || + smin_val > smax_val || umin_val > umax_val) { + /* Taint dst register if offset had invalid bounds derived from + * e.g. dead branches. + */ + __mark_reg_unknown(env, dst_reg); + return 0; } if (!src_known && @@ -7093,50 +4883,132 @@ static int adjust_scalar_min_max_vals(struct bpf_verifier_env *env, return sanitize_err(env, insn, ret, NULL, NULL); } - /* Calculate sign/unsigned bounds and tnum for alu32 and alu64 bit ops. - * There are two classes of instructions: The first class we track both - * alu32 and alu64 sign/unsigned bounds independently this provides the - * greatest amount of precision when alu operations are mixed with jmp32 - * operations. These operations are BPF_ADD, BPF_SUB, BPF_MUL, BPF_ADD, - * and BPF_OR. This is possible because these ops have fairly easy to - * understand and calculate behavior in both 32-bit and 64-bit alu ops. - * See alu32 verifier tests for examples. The second class of - * operations, BPF_LSH, BPF_RSH, and BPF_ARSH, however are not so easy - * with regards to tracking sign/unsigned bounds because the bits may - * cross subreg boundaries in the alu64 case. When this happens we mark - * the reg unbounded in the subreg bound space and use the resulting - * tnum to calculate an approximation of the sign/unsigned bounds. - */ switch (opcode) { case BPF_ADD: - scalar32_min_max_add(dst_reg, &src_reg); - scalar_min_max_add(dst_reg, &src_reg); + if (signed_add_overflows(dst_reg->smin_value, smin_val) || + signed_add_overflows(dst_reg->smax_value, smax_val)) { + dst_reg->smin_value = S64_MIN; + dst_reg->smax_value = S64_MAX; + } else { + dst_reg->smin_value += smin_val; + dst_reg->smax_value += smax_val; + } + if (dst_reg->umin_value + umin_val < umin_val || + dst_reg->umax_value + umax_val < umax_val) { + dst_reg->umin_value = 0; + dst_reg->umax_value = U64_MAX; + } else { + dst_reg->umin_value += umin_val; + dst_reg->umax_value += umax_val; + } dst_reg->var_off = tnum_add(dst_reg->var_off, src_reg.var_off); break; case BPF_SUB: - scalar32_min_max_sub(dst_reg, &src_reg); - scalar_min_max_sub(dst_reg, &src_reg); + if (signed_sub_overflows(dst_reg->smin_value, smax_val) || + signed_sub_overflows(dst_reg->smax_value, smin_val)) { + /* Overflow possible, we know nothing */ + dst_reg->smin_value = S64_MIN; + dst_reg->smax_value = S64_MAX; + } else { + dst_reg->smin_value -= smax_val; + dst_reg->smax_value -= smin_val; + } + if (dst_reg->umin_value < umax_val) { + /* Overflow possible, we know nothing */ + dst_reg->umin_value = 0; + dst_reg->umax_value = U64_MAX; + } else { + /* Cannot overflow (as long as bounds are consistent) */ + dst_reg->umin_value -= umax_val; + dst_reg->umax_value -= umin_val; + } dst_reg->var_off = tnum_sub(dst_reg->var_off, src_reg.var_off); break; case BPF_MUL: dst_reg->var_off = tnum_mul(dst_reg->var_off, src_reg.var_off); - scalar32_min_max_mul(dst_reg, &src_reg); - scalar_min_max_mul(dst_reg, &src_reg); + if (smin_val < 0 || dst_reg->smin_value < 0) { + /* Ain't nobody got time to multiply that sign */ + __mark_reg_unbounded(dst_reg); + __update_reg_bounds(dst_reg); + break; + } + /* Both values are positive, so we can work with unsigned and + * copy the result to signed (unless it exceeds S64_MAX). + */ + if (umax_val > U32_MAX || dst_reg->umax_value > U32_MAX) { + /* Potential overflow, we know nothing */ + __mark_reg_unbounded(dst_reg); + /* (except what we can learn from the var_off) */ + __update_reg_bounds(dst_reg); + break; + } + dst_reg->umin_value *= umin_val; + dst_reg->umax_value *= umax_val; + if (dst_reg->umax_value > S64_MAX) { + /* Overflow possible, we know nothing */ + dst_reg->smin_value = S64_MIN; + dst_reg->smax_value = S64_MAX; + } else { + dst_reg->smin_value = dst_reg->umin_value; + dst_reg->smax_value = dst_reg->umax_value; + } break; case BPF_AND: + if (src_known && dst_known) { + __mark_reg_known(dst_reg, dst_reg->var_off.value & + src_reg.var_off.value); + break; + } + /* We get our minimum from the var_off, since that's inherently + * bitwise. Our maximum is the minimum of the operands' maxima. + */ dst_reg->var_off = tnum_and(dst_reg->var_off, src_reg.var_off); - scalar32_min_max_and(dst_reg, &src_reg); - scalar_min_max_and(dst_reg, &src_reg); + dst_reg->umin_value = dst_reg->var_off.value; + dst_reg->umax_value = min(dst_reg->umax_value, umax_val); + if (dst_reg->smin_value < 0 || smin_val < 0) { + /* Lose signed bounds when ANDing negative numbers, + * ain't nobody got time for that. + */ + dst_reg->smin_value = S64_MIN; + dst_reg->smax_value = S64_MAX; + } else { + /* ANDing two positives gives a positive, so safe to + * cast result into s64. + */ + dst_reg->smin_value = dst_reg->umin_value; + dst_reg->smax_value = dst_reg->umax_value; + } + /* We may learn something more from the var_off */ + __update_reg_bounds(dst_reg); break; case BPF_OR: + if (src_known && dst_known) { + __mark_reg_known(dst_reg, dst_reg->var_off.value | + src_reg.var_off.value); + break; + } + /* We get our maximum from the var_off, and our minimum is the + * maximum of the operands' minima + */ dst_reg->var_off = tnum_or(dst_reg->var_off, src_reg.var_off); - scalar32_min_max_or(dst_reg, &src_reg); - scalar_min_max_or(dst_reg, &src_reg); - break; - case BPF_XOR: - dst_reg->var_off = tnum_xor(dst_reg->var_off, src_reg.var_off); - scalar32_min_max_xor(dst_reg, &src_reg); - scalar_min_max_xor(dst_reg, &src_reg); + dst_reg->umin_value = max(dst_reg->umin_value, umin_val); + dst_reg->umax_value = dst_reg->var_off.value | + dst_reg->var_off.mask; + if (dst_reg->smin_value < 0 || smin_val < 0) { + /* Lose signed bounds when ORing negative numbers, + * ain't nobody got time for that. + */ + dst_reg->smin_value = S64_MIN; + dst_reg->smax_value = S64_MAX; + } else { + /* ORing two positives gives a positive, so safe to + * cast result into s64. + */ + dst_reg->smin_value = dst_reg->umin_value; + dst_reg->smax_value = dst_reg->umax_value; + } + /* We may learn something more from the var_off */ + __update_reg_bounds(dst_reg); break; case BPF_LSH: if (umax_val >= insn_bitness) { @@ -7146,10 +5018,22 @@ static int adjust_scalar_min_max_vals(struct bpf_verifier_env *env, mark_reg_unknown(env, regs, insn->dst_reg); break; } - if (alu32) - scalar32_min_max_lsh(dst_reg, &src_reg); - else - scalar_min_max_lsh(dst_reg, &src_reg); + /* We lose all sign bit information (except what we can pick + * up from var_off) + */ + dst_reg->smin_value = S64_MIN; + dst_reg->smax_value = S64_MAX; + /* If we might shift our top bit out, then we know nothing */ + if (dst_reg->umax_value > 1ULL << (63 - umax_val)) { + dst_reg->umin_value = 0; + dst_reg->umax_value = U64_MAX; + } else { + dst_reg->umin_value <<= umin_val; + dst_reg->umax_value <<= umax_val; + } + dst_reg->var_off = tnum_lshift(dst_reg->var_off, umin_val); + /* We may learn something more from the var_off */ + __update_reg_bounds(dst_reg); break; case BPF_RSH: if (umax_val >= insn_bitness) { @@ -7159,10 +5043,27 @@ static int adjust_scalar_min_max_vals(struct bpf_verifier_env *env, mark_reg_unknown(env, regs, insn->dst_reg); break; } - if (alu32) - scalar32_min_max_rsh(dst_reg, &src_reg); - else - scalar_min_max_rsh(dst_reg, &src_reg); + /* BPF_RSH is an unsigned shift. If the value in dst_reg might + * be negative, then either: + * 1) src_reg might be zero, so the sign bit of the result is + * unknown, so we lose our signed bounds + * 2) it's known negative, thus the unsigned bounds capture the + * signed bounds + * 3) the signed bounds cross zero, so they tell us nothing + * about the result + * If the value in dst_reg is known nonnegative, then again the + * unsigned bounts capture the signed bounds. + * Thus, in all cases it suffices to blow away our signed bounds + * and rely on inferring new ones from the unsigned bounds and + * var_off of the result. + */ + dst_reg->smin_value = S64_MIN; + dst_reg->smax_value = S64_MAX; + dst_reg->var_off = tnum_rshift(dst_reg->var_off, umin_val); + dst_reg->umin_value >>= umax_val; + dst_reg->umax_value >>= umin_val; + /* We may learn something more from the var_off */ + __update_reg_bounds(dst_reg); break; case BPF_ARSH: if (umax_val >= insn_bitness) { @@ -7172,20 +5073,41 @@ static int adjust_scalar_min_max_vals(struct bpf_verifier_env *env, mark_reg_unknown(env, regs, insn->dst_reg); break; } - if (alu32) - scalar32_min_max_arsh(dst_reg, &src_reg); - else - scalar_min_max_arsh(dst_reg, &src_reg); + + /* Upon reaching here, src_known is true and + * umax_val is equal to umin_val. + */ + if (insn_bitness == 32) { + dst_reg->smin_value = (u32)(((s32)dst_reg->smin_value) >> umin_val); + dst_reg->smax_value = (u32)(((s32)dst_reg->smax_value) >> umin_val); + } else { + dst_reg->smin_value >>= umin_val; + dst_reg->smax_value >>= umin_val; + } + + dst_reg->var_off = tnum_arshift(dst_reg->var_off, umin_val, + insn_bitness); + + /* blow away the dst_reg umin_value/umax_value and rely on + * dst_reg var_off to refine the result. + */ + dst_reg->umin_value = 0; + dst_reg->umax_value = U64_MAX; + __update_reg_bounds(dst_reg); break; default: mark_reg_unknown(env, regs, insn->dst_reg); break; } - /* ALU32 ops are zero extended into 64bit register */ - if (alu32) - zext_32_to_64(dst_reg); - reg_bounds_sync(dst_reg); + if (BPF_CLASS(insn->code) != BPF_ALU64) { + /* 32-bit ALU ops are (32,32)->32 */ + coerce_reg_to_size(dst_reg, 4); + } + + __update_reg_bounds(dst_reg); + __reg_deduce_bounds(dst_reg); + __reg_bound_offset(dst_reg); return 0; } @@ -7206,11 +5128,6 @@ static int adjust_reg_min_max_vals(struct bpf_verifier_env *env, src_reg = NULL; if (dst_reg->type != SCALAR_VALUE) ptr_reg = dst_reg; - else - /* Make sure ID is cleared otherwise dst_reg min/max could be - * incorrectly propagated into other registers by find_equal_scalars() - */ - dst_reg->id = 0; if (BPF_SRC(insn->code) == BPF_X) { src_reg = ®s[insn->src_reg]; if (src_reg->type != SCALAR_VALUE) { @@ -7349,13 +5266,7 @@ static int check_alu_op(struct bpf_verifier_env *env, struct bpf_insn *insn) /* case: R1 = R2 * copy register state to dest reg */ - if (src_reg->type == SCALAR_VALUE && !src_reg->id) - /* Assign src and dst registers the same ID - * that will be used by find_equal_scalars() - * to propagate min/max range. - */ - src_reg->id = ++env->id_gen; - copy_register_state(dst_reg, src_reg); + *dst_reg = *src_reg; dst_reg->live |= REG_LIVE_WRITTEN; dst_reg->subreg_def = DEF_NOT_SUBREG; } else { @@ -7366,20 +5277,14 @@ static int check_alu_op(struct bpf_verifier_env *env, struct bpf_insn *insn) insn->src_reg); return -EACCES; } else if (src_reg->type == SCALAR_VALUE) { - copy_register_state(dst_reg, src_reg); - /* Make sure ID is cleared otherwise - * dst_reg min/max could be incorrectly - * propagated into src_reg by find_equal_scalars() - */ - dst_reg->id = 0; + *dst_reg = *src_reg; dst_reg->live |= REG_LIVE_WRITTEN; dst_reg->subreg_def = env->insn_idx + 1; } else { mark_reg_unknown(env, regs, insn->dst_reg); } - zext_32_to_64(dst_reg); - reg_bounds_sync(dst_reg); + coerce_reg_to_size(dst_reg, 4); } } else { /* case: R = imm @@ -7451,14 +5356,35 @@ static int check_alu_op(struct bpf_verifier_env *env, struct bpf_insn *insn) return 0; } +static void __find_good_pkt_pointers(struct bpf_func_state *state, + struct bpf_reg_state *dst_reg, + enum bpf_reg_type type, u16 new_range) +{ + struct bpf_reg_state *reg; + int i; + + for (i = 0; i < MAX_BPF_REG; i++) { + reg = &state->regs[i]; + if (reg->type == type && reg->id == dst_reg->id) + /* keep the maximum range already checked */ + reg->range = max(reg->range, new_range); + } + + bpf_for_each_spilled_reg(i, state, reg) { + if (!reg) + continue; + if (reg->type == type && reg->id == dst_reg->id) + reg->range = max(reg->range, new_range); + } +} + static void find_good_pkt_pointers(struct bpf_verifier_state *vstate, struct bpf_reg_state *dst_reg, enum bpf_reg_type type, bool range_right_open) { - struct bpf_func_state *state; - struct bpf_reg_state *reg; - int new_range; + u16 new_range; + int i; if (dst_reg->off < 0 || (dst_reg->off == 0 && range_right_open)) @@ -7523,91 +5449,61 @@ static void find_good_pkt_pointers(struct bpf_verifier_state *vstate, * the range won't allow anything. * dst_reg->off is known < MAX_PACKET_OFF, therefore it fits in a u16. */ - bpf_for_each_reg_in_vstate(vstate, state, reg, ({ - if (reg->type == type && reg->id == dst_reg->id) - /* keep the maximum range already checked */ - reg->range = max(reg->range, new_range); - })); + for (i = 0; i <= vstate->curframe; i++) + __find_good_pkt_pointers(vstate->frame[i], dst_reg, type, + new_range); } -static int is_branch32_taken(struct bpf_reg_state *reg, u32 val, u8 opcode) +/* compute branch direction of the expression "if (reg opcode val) goto target;" + * and return: + * 1 - branch will be taken and "goto target" will be executed + * 0 - branch will not be taken and fall-through to next insn + * -1 - unknown. Example: "if (reg < 5)" is unknown when register value range [0,10] + */ +static int is_branch_taken(struct bpf_reg_state *reg, u64 val, u8 opcode, + bool is_jmp32) { - struct tnum subreg = tnum_subreg(reg->var_off); - s32 sval = (s32)val; + struct bpf_reg_state reg_lo; + s64 sval; - switch (opcode) { - case BPF_JEQ: - if (tnum_is_const(subreg)) - return !!tnum_equals_const(subreg, val); - break; - case BPF_JNE: - if (tnum_is_const(subreg)) - return !tnum_equals_const(subreg, val); - break; - case BPF_JSET: - if ((~subreg.mask & subreg.value) & val) - return 1; - if (!((subreg.mask | subreg.value) & val)) - return 0; - break; - case BPF_JGT: - if (reg->u32_min_value > val) - return 1; - else if (reg->u32_max_value <= val) - return 0; - break; - case BPF_JSGT: - if (reg->s32_min_value > sval) - return 1; - else if (reg->s32_max_value <= sval) - return 0; - break; - case BPF_JLT: - if (reg->u32_max_value < val) - return 1; - else if (reg->u32_min_value >= val) - return 0; - break; - case BPF_JSLT: - if (reg->s32_max_value < sval) - return 1; - else if (reg->s32_min_value >= sval) - return 0; - break; - case BPF_JGE: - if (reg->u32_min_value >= val) - return 1; - else if (reg->u32_max_value < val) - return 0; - break; - case BPF_JSGE: - if (reg->s32_min_value >= sval) - return 1; - else if (reg->s32_max_value < sval) - return 0; - break; - case BPF_JLE: - if (reg->u32_max_value <= val) - return 1; - else if (reg->u32_min_value > val) - return 0; - break; - case BPF_JSLE: - if (reg->s32_max_value <= sval) - return 1; - else if (reg->s32_min_value > sval) - return 0; - break; + if (__is_pointer_value(false, reg)) + return -1; + + if (is_jmp32) { + reg_lo = *reg; + reg = ®_lo; + /* For JMP32, only low 32 bits are compared, coerce_reg_to_size + * could truncate high bits and update umin/umax according to + * information of low bits. + */ + coerce_reg_to_size(reg, 4); + /* smin/smax need special handling. For example, after coerce, + * if smin_value is 0x00000000ffffffffLL, the value is -1 when + * used as operand to JMP32. It is a negative number from s32's + * point of view, while it is a positive number when seen as + * s64. The smin/smax are kept as s64, therefore, when used with + * JMP32, they need to be transformed into s32, then sign + * extended back to s64. + * + * Also, smin/smax were copied from umin/umax. If umin/umax has + * different sign bit, then min/max relationship doesn't + * maintain after casting into s32, for this case, set smin/smax + * to safest range. + */ + if ((reg->umax_value ^ reg->umin_value) & + (1ULL << 31)) { + reg->smin_value = S32_MIN; + reg->smax_value = S32_MAX; + } + reg->smin_value = (s64)(s32)reg->smin_value; + reg->smax_value = (s64)(s32)reg->smax_value; + + val = (u32)val; + sval = (s64)(s32)val; + } else { + sval = (s64)val; } - return -1; -} - - -static int is_branch64_taken(struct bpf_reg_state *reg, u64 val, u8 opcode) -{ - s64 sval = (s64)val; - switch (opcode) { case BPF_JEQ: if (tnum_is_const(reg->var_off)) @@ -7632,7 +5528,7 @@ static int is_branch64_taken(struct bpf_reg_state *reg, u64 val, u8 opcode) case BPF_JSGT: if (reg->smin_value > sval) return 1; - else if (reg->smax_value <= sval) + else if (reg->smax_value < sval) return 0; break; case BPF_JLT: @@ -7676,100 +5572,91 @@ static int is_branch64_taken(struct bpf_reg_state *reg, u64 val, u8 opcode) return -1; } -/* compute branch direction of the expression "if (reg opcode val) goto target;" - * and return: - * 1 - branch will be taken and "goto target" will be executed - * 0 - branch will not be taken and fall-through to next insn - * -1 - unknown. Example: "if (reg < 5)" is unknown when register value - * range [0,10] +/* Generate min value of the high 32-bit from TNUM info. */ +static u64 gen_hi_min(struct tnum var) +{ + return var.value & ~0xffffffffULL; +} + +/* Generate max value of the high 32-bit from TNUM info. */ +static u64 gen_hi_max(struct tnum var) +{ + return (var.value | var.mask) & ~0xffffffffULL; +} + +/* Return true if VAL is compared with a s64 sign extended from s32, and they + * are with the same signedness. */ -static int is_branch_taken(struct bpf_reg_state *reg, u64 val, u8 opcode, - bool is_jmp32) +static bool cmp_val_with_extended_s64(s64 sval, struct bpf_reg_state *reg) { - if (__is_pointer_value(false, reg)) { - if (!reg_type_not_null(reg->type)) - return -1; + return ((s32)sval >= 0 && + reg->smin_value >= 0 && reg->smax_value <= S32_MAX) || + ((s32)sval < 0 && + reg->smax_value <= 0 && reg->smin_value >= S32_MIN); +} - /* If pointer is valid tests against zero will fail so we can - * use this to direct branch taken. +/* Constrain the possible values of @reg with unsigned upper bound @bound. + * If @is_exclusive, @bound is an exclusive limit, otherwise it is inclusive. + * If @is_jmp32, @bound is a 32-bit value that only constrains the low 32 bits + * of @reg. + */ +static void set_upper_bound(struct bpf_reg_state *reg, u64 bound, bool is_jmp32, + bool is_exclusive) +{ + if (is_exclusive) { + /* There are no values for `reg` that make `reg<0` true. */ + if (bound == 0) + return; + bound--; + } + if (is_jmp32) { + /* Constrain the register's value in the tnum representation. + * For 64-bit comparisons this happens later in + * __reg_bound_offset(), but for 32-bit comparisons, we can be + * more precise than what can be derived from the updated + * numeric bounds. */ - if (val != 0) - return -1; + struct tnum t = tnum_range(0, bound); - switch (opcode) { - case BPF_JEQ: - return 0; - case BPF_JNE: - return 1; - default: - return -1; - } + t.mask |= ~0xffffffffULL; /* upper half is unknown */ + reg->var_off = tnum_intersect(reg->var_off, t); + + /* Compute the 64-bit bound from the 32-bit bound. */ + bound += gen_hi_max(reg->var_off); } - - if (is_jmp32) - return is_branch32_taken(reg, val, opcode); - return is_branch64_taken(reg, val, opcode); + reg->umax_value = min(reg->umax_value, bound); } -static int flip_opcode(u32 opcode) +/* Constrain the possible values of @reg with unsigned lower bound @bound. + * If @is_exclusive, @bound is an exclusive limit, otherwise it is inclusive. + * If @is_jmp32, @bound is a 32-bit value that only constrains the low 32 bits + * of @reg. + */ +static void set_lower_bound(struct bpf_reg_state *reg, u64 bound, bool is_jmp32, + bool is_exclusive) { - /* How can we transform "a b" into "b a"? */ - static const u8 opcode_flip[16] = { - /* these stay the same */ - [BPF_JEQ >> 4] = BPF_JEQ, - [BPF_JNE >> 4] = BPF_JNE, - [BPF_JSET >> 4] = BPF_JSET, - /* these swap "lesser" and "greater" (L and G in the opcodes) */ - [BPF_JGE >> 4] = BPF_JLE, - [BPF_JGT >> 4] = BPF_JLT, - [BPF_JLE >> 4] = BPF_JGE, - [BPF_JLT >> 4] = BPF_JGT, - [BPF_JSGE >> 4] = BPF_JSLE, - [BPF_JSGT >> 4] = BPF_JSLT, - [BPF_JSLE >> 4] = BPF_JSGE, - [BPF_JSLT >> 4] = BPF_JSGT - }; - return opcode_flip[opcode >> 4]; -} - -static int is_pkt_ptr_branch_taken(struct bpf_reg_state *dst_reg, - struct bpf_reg_state *src_reg, - u8 opcode) -{ - struct bpf_reg_state *pkt; - - if (src_reg->type == PTR_TO_PACKET_END) { - pkt = dst_reg; - } else if (dst_reg->type == PTR_TO_PACKET_END) { - pkt = src_reg; - opcode = flip_opcode(opcode); - } else { - return -1; + if (is_exclusive) { + /* There are no values for `reg` that make `reg>MAX` true. */ + if (bound == (is_jmp32 ? U32_MAX : U64_MAX)) + return; + bound++; } + if (is_jmp32) { + /* Constrain the register's value in the tnum representation. + * For 64-bit comparisons this happens later in + * __reg_bound_offset(), but for 32-bit comparisons, we can be + * more precise than what can be derived from the updated + * numeric bounds. + */ + struct tnum t = tnum_range(bound, U32_MAX); - if (pkt->range >= 0) - return -1; + t.mask |= ~0xffffffffULL; /* upper half is unknown */ + reg->var_off = tnum_intersect(reg->var_off, t); - switch (opcode) { - case BPF_JLE: - /* pkt <= pkt_end */ - fallthrough; - case BPF_JGT: - /* pkt > pkt_end */ - if (pkt->range == BEYOND_PKT_END) - /* pkt has at last one extra byte beyond pkt_end */ - return opcode == BPF_JGT; - break; - case BPF_JLT: - /* pkt < pkt_end */ - fallthrough; - case BPF_JGE: - /* pkt >= pkt_end */ - if (pkt->range == BEYOND_PKT_END || pkt->range == AT_PKT_END) - return opcode == BPF_JGE; - break; + /* Compute the 64-bit bound from the 32-bit bound. */ + bound += gen_hi_min(reg->var_off); } - return -1; + reg->umin_value = max(reg->umin_value, bound); } /* Adjusts the register min/max values in the case that the dst_reg is the @@ -7778,16 +5665,10 @@ static int is_pkt_ptr_branch_taken(struct bpf_reg_state *dst_reg, * In JEQ/JNE cases we also adjust the var_off values. */ static void reg_set_min_max(struct bpf_reg_state *true_reg, - struct bpf_reg_state *false_reg, - u64 val, u32 val32, + struct bpf_reg_state *false_reg, u64 val, u8 opcode, bool is_jmp32) { - struct tnum false_32off = tnum_subreg(false_reg->var_off); - struct tnum false_64off = false_reg->var_off; - struct tnum true_32off = tnum_subreg(true_reg->var_off); - struct tnum true_64off = true_reg->var_off; - s64 sval = (s64)val; - s32 sval32 = (s32)val32; + s64 sval; /* If the dst_reg is a pointer, we can't learn anything about its * variable offset from the compare (unless src_reg were a pointer into @@ -7798,156 +5679,189 @@ static void reg_set_min_max(struct bpf_reg_state *true_reg, if (__is_pointer_value(false, false_reg)) return; + val = is_jmp32 ? (u32)val : val; + sval = is_jmp32 ? (s64)(s32)val : (s64)val; + switch (opcode) { - /* JEQ/JNE comparison doesn't change the register equivalence. - * - * r1 = r2; - * if (r1 == 42) goto label; - * ... - * label: // here both r1 and r2 are known to be 42. - * - * Hence when marking register as known preserve it's ID. - */ case BPF_JEQ: - if (is_jmp32) { - __mark_reg32_known(true_reg, val32); - true_32off = tnum_subreg(true_reg->var_off); - } else { - ___mark_reg_known(true_reg, val); - true_64off = true_reg->var_off; - } - break; case BPF_JNE: + { + struct bpf_reg_state *reg = + opcode == BPF_JEQ ? true_reg : false_reg; + + /* For BPF_JEQ, if this is false we know nothing Jon Snow, but + * if it is true we know the value for sure. Likewise for + * BPF_JNE. + */ if (is_jmp32) { - __mark_reg32_known(false_reg, val32); - false_32off = tnum_subreg(false_reg->var_off); + u64 old_v = reg->var_off.value; + u64 hi_mask = ~0xffffffffULL; + + reg->var_off.value = (old_v & hi_mask) | val; + reg->var_off.mask &= hi_mask; } else { - ___mark_reg_known(false_reg, val); - false_64off = false_reg->var_off; + __mark_reg_known(reg, val); } break; + } case BPF_JSET: - if (is_jmp32) { - false_32off = tnum_and(false_32off, tnum_const(~val32)); - if (is_power_of_2(val32)) - true_32off = tnum_or(true_32off, - tnum_const(val32)); - } else { - false_64off = tnum_and(false_64off, tnum_const(~val)); - if (is_power_of_2(val)) - true_64off = tnum_or(true_64off, - tnum_const(val)); - } + false_reg->var_off = tnum_and(false_reg->var_off, + tnum_const(~val)); + if (is_power_of_2(val)) + true_reg->var_off = tnum_or(true_reg->var_off, + tnum_const(val)); break; case BPF_JGE: case BPF_JGT: { - if (is_jmp32) { - u32 false_umax = opcode == BPF_JGT ? val32 : val32 - 1; - u32 true_umin = opcode == BPF_JGT ? val32 + 1 : val32; - - false_reg->u32_max_value = min(false_reg->u32_max_value, - false_umax); - true_reg->u32_min_value = max(true_reg->u32_min_value, - true_umin); - } else { - u64 false_umax = opcode == BPF_JGT ? val : val - 1; - u64 true_umin = opcode == BPF_JGT ? val + 1 : val; - - false_reg->umax_value = min(false_reg->umax_value, false_umax); - true_reg->umin_value = max(true_reg->umin_value, true_umin); - } + set_upper_bound(false_reg, val, is_jmp32, opcode == BPF_JGE); + set_lower_bound(true_reg, val, is_jmp32, opcode == BPF_JGT); break; } case BPF_JSGE: case BPF_JSGT: { - if (is_jmp32) { - s32 false_smax = opcode == BPF_JSGT ? sval32 : sval32 - 1; - s32 true_smin = opcode == BPF_JSGT ? sval32 + 1 : sval32; + s64 false_smax = opcode == BPF_JSGT ? sval : sval - 1; + s64 true_smin = opcode == BPF_JSGT ? sval + 1 : sval; - false_reg->s32_max_value = min(false_reg->s32_max_value, false_smax); - true_reg->s32_min_value = max(true_reg->s32_min_value, true_smin); - } else { - s64 false_smax = opcode == BPF_JSGT ? sval : sval - 1; - s64 true_smin = opcode == BPF_JSGT ? sval + 1 : sval; - - false_reg->smax_value = min(false_reg->smax_value, false_smax); - true_reg->smin_value = max(true_reg->smin_value, true_smin); - } + /* If the full s64 was not sign-extended from s32 then don't + * deduct further info. + */ + if (is_jmp32 && !cmp_val_with_extended_s64(sval, false_reg)) + break; + false_reg->smax_value = min(false_reg->smax_value, false_smax); + true_reg->smin_value = max(true_reg->smin_value, true_smin); break; } case BPF_JLE: case BPF_JLT: { - if (is_jmp32) { - u32 false_umin = opcode == BPF_JLT ? val32 : val32 + 1; - u32 true_umax = opcode == BPF_JLT ? val32 - 1 : val32; - - false_reg->u32_min_value = max(false_reg->u32_min_value, - false_umin); - true_reg->u32_max_value = min(true_reg->u32_max_value, - true_umax); - } else { - u64 false_umin = opcode == BPF_JLT ? val : val + 1; - u64 true_umax = opcode == BPF_JLT ? val - 1 : val; - - false_reg->umin_value = max(false_reg->umin_value, false_umin); - true_reg->umax_value = min(true_reg->umax_value, true_umax); - } + set_lower_bound(false_reg, val, is_jmp32, opcode == BPF_JLE); + set_upper_bound(true_reg, val, is_jmp32, opcode == BPF_JLT); break; } case BPF_JSLE: case BPF_JSLT: { - if (is_jmp32) { - s32 false_smin = opcode == BPF_JSLT ? sval32 : sval32 + 1; - s32 true_smax = opcode == BPF_JSLT ? sval32 - 1 : sval32; + s64 false_smin = opcode == BPF_JSLT ? sval : sval + 1; + s64 true_smax = opcode == BPF_JSLT ? sval - 1 : sval; - false_reg->s32_min_value = max(false_reg->s32_min_value, false_smin); - true_reg->s32_max_value = min(true_reg->s32_max_value, true_smax); - } else { - s64 false_smin = opcode == BPF_JSLT ? sval : sval + 1; - s64 true_smax = opcode == BPF_JSLT ? sval - 1 : sval; - - false_reg->smin_value = max(false_reg->smin_value, false_smin); - true_reg->smax_value = min(true_reg->smax_value, true_smax); - } + if (is_jmp32 && !cmp_val_with_extended_s64(sval, false_reg)) + break; + false_reg->smin_value = max(false_reg->smin_value, false_smin); + true_reg->smax_value = min(true_reg->smax_value, true_smax); break; } default: - return; + break; } - if (is_jmp32) { - false_reg->var_off = tnum_or(tnum_clear_subreg(false_64off), - tnum_subreg(false_32off)); - true_reg->var_off = tnum_or(tnum_clear_subreg(true_64off), - tnum_subreg(true_32off)); - __reg_combine_32_into_64(false_reg); - __reg_combine_32_into_64(true_reg); - } else { - false_reg->var_off = false_64off; - true_reg->var_off = true_64off; - __reg_combine_64_into_32(false_reg); - __reg_combine_64_into_32(true_reg); - } + __reg_deduce_bounds(false_reg); + __reg_deduce_bounds(true_reg); + /* We might have learned some bits from the bounds. */ + __reg_bound_offset(false_reg); + __reg_bound_offset(true_reg); + /* Intersecting with the old var_off might have improved our bounds + * slightly. e.g. if umax was 0x7f...f and var_off was (0; 0xf...fc), + * then new var_off is (0; 0x7f...fc) which improves our umax. + */ + __update_reg_bounds(false_reg); + __update_reg_bounds(true_reg); } /* Same as above, but for the case that dst_reg holds a constant and src_reg is * the variable reg. */ static void reg_set_min_max_inv(struct bpf_reg_state *true_reg, - struct bpf_reg_state *false_reg, - u64 val, u32 val32, + struct bpf_reg_state *false_reg, u64 val, u8 opcode, bool is_jmp32) { - opcode = flip_opcode(opcode); - /* This uses zero as "not present in table"; luckily the zero opcode, - * BPF_JA, can't get here. + s64 sval; + + if (__is_pointer_value(false, false_reg)) + return; + + val = is_jmp32 ? (u32)val : val; + sval = is_jmp32 ? (s64)(s32)val : (s64)val; + + switch (opcode) { + case BPF_JEQ: + case BPF_JNE: + { + struct bpf_reg_state *reg = + opcode == BPF_JEQ ? true_reg : false_reg; + + if (is_jmp32) { + u64 old_v = reg->var_off.value; + u64 hi_mask = ~0xffffffffULL; + + reg->var_off.value = (old_v & hi_mask) | val; + reg->var_off.mask &= hi_mask; + } else { + __mark_reg_known(reg, val); + } + break; + } + case BPF_JSET: + false_reg->var_off = tnum_and(false_reg->var_off, + tnum_const(~val)); + if (is_power_of_2(val)) + true_reg->var_off = tnum_or(true_reg->var_off, + tnum_const(val)); + break; + case BPF_JGE: + case BPF_JGT: + { + set_lower_bound(false_reg, val, is_jmp32, opcode == BPF_JGE); + set_upper_bound(true_reg, val, is_jmp32, opcode == BPF_JGT); + break; + } + case BPF_JSGE: + case BPF_JSGT: + { + s64 false_smin = opcode == BPF_JSGT ? sval : sval + 1; + s64 true_smax = opcode == BPF_JSGT ? sval - 1 : sval; + + if (is_jmp32 && !cmp_val_with_extended_s64(sval, false_reg)) + break; + false_reg->smin_value = max(false_reg->smin_value, false_smin); + true_reg->smax_value = min(true_reg->smax_value, true_smax); + break; + } + case BPF_JLE: + case BPF_JLT: + { + set_upper_bound(false_reg, val, is_jmp32, opcode == BPF_JLE); + set_lower_bound(true_reg, val, is_jmp32, opcode == BPF_JLT); + break; + } + case BPF_JSLE: + case BPF_JSLT: + { + s64 false_smax = opcode == BPF_JSLT ? sval : sval - 1; + s64 true_smin = opcode == BPF_JSLT ? sval + 1 : sval; + + if (is_jmp32 && !cmp_val_with_extended_s64(sval, false_reg)) + break; + false_reg->smax_value = min(false_reg->smax_value, false_smax); + true_reg->smin_value = max(true_reg->smin_value, true_smin); + break; + } + default: + break; + } + + __reg_deduce_bounds(false_reg); + __reg_deduce_bounds(true_reg); + /* We might have learned some bits from the bounds. */ + __reg_bound_offset(false_reg); + __reg_bound_offset(true_reg); + /* Intersecting with the old var_off might have improved our bounds + * slightly. e.g. if umax was 0x7f...f and var_off was (0; 0xf...fc), + * then new var_off is (0; 0x7f...fc) which improves our umax. */ - if (opcode) - reg_set_min_max(true_reg, false_reg, val, val32, opcode, is_jmp32); + __update_reg_bounds(false_reg); + __update_reg_bounds(true_reg); } /* Regs are known to be equal, so intersect their min/max/var_off */ @@ -7964,8 +5878,21 @@ static void __reg_combine_min_max(struct bpf_reg_state *src_reg, dst_reg->smax_value); src_reg->var_off = dst_reg->var_off = tnum_intersect(src_reg->var_off, dst_reg->var_off); - reg_bounds_sync(src_reg); - reg_bounds_sync(dst_reg); + /* We might have learned new bounds from the var_off. */ + __update_reg_bounds(src_reg); + __update_reg_bounds(dst_reg); + /* We might have learned something about the sign bit. */ + __reg_deduce_bounds(src_reg); + __reg_deduce_bounds(dst_reg); + /* We might have learned some bits from the bounds. */ + __reg_bound_offset(src_reg); + __reg_bound_offset(dst_reg); + /* Intersecting with the old var_off might have improved our bounds + * slightly. e.g. if umax was 0x7f...f and var_off was (0; 0xf...fc), + * then new var_off is (0; 0x7f...fc) which improves our umax. + */ + __update_reg_bounds(src_reg); + __update_reg_bounds(dst_reg); } static void reg_combine_min_max(struct bpf_reg_state *true_src, @@ -7988,31 +5915,26 @@ static void mark_ptr_or_null_reg(struct bpf_func_state *state, struct bpf_reg_state *reg, u32 id, bool is_null) { - if (reg_type_may_be_null(reg->type) && reg->id == id && - !WARN_ON_ONCE(!reg->id)) { + if (reg_type_may_be_null(reg->type) && reg->id == id) { + /* Old offset (both fixed and variable parts) should + * have been known-zero, because we don't allow pointer + * arithmetic on pointers that might be NULL. + */ if (WARN_ON_ONCE(reg->smin_value || reg->smax_value || !tnum_equals_const(reg->var_off, 0) || reg->off)) { - /* Old offset (both fixed and variable parts) should - * have been known-zero, because we don't allow pointer - * arithmetic on pointers that might be NULL. If we - * see this happening, don't convert the register. - */ - return; + __mark_reg_known_zero(reg); + reg->off = 0; } if (is_null) { reg->type = SCALAR_VALUE; } else if (reg->type == PTR_TO_MAP_VALUE_OR_NULL) { - const struct bpf_map *map = reg->map_ptr; - - if (map->inner_map_meta) { + if (reg->map_ptr->inner_map_meta) { reg->type = CONST_PTR_TO_MAP; - reg->map_ptr = map->inner_map_meta; - } else if (map->map_type == BPF_MAP_TYPE_XSKMAP) { + reg->map_ptr = reg->map_ptr->inner_map_meta; + } else if (reg->map_ptr->map_type == + BPF_MAP_TYPE_XSKMAP) { reg->type = PTR_TO_XDP_SOCK; - } else if (map->map_type == BPF_MAP_TYPE_SOCKMAP || - map->map_type == BPF_MAP_TYPE_SOCKHASH) { - reg->type = PTR_TO_SOCKET; } else { reg->type = PTR_TO_MAP_VALUE; } @@ -8022,14 +5944,6 @@ static void mark_ptr_or_null_reg(struct bpf_func_state *state, reg->type = PTR_TO_SOCK_COMMON; } else if (reg->type == PTR_TO_TCP_SOCK_OR_NULL) { reg->type = PTR_TO_TCP_SOCK; - } else if (reg->type == PTR_TO_BTF_ID_OR_NULL) { - reg->type = PTR_TO_BTF_ID; - } else if (reg->type == PTR_TO_MEM_OR_NULL) { - reg->type = PTR_TO_MEM; - } else if (reg->type == PTR_TO_RDONLY_BUF_OR_NULL) { - reg->type = PTR_TO_RDONLY_BUF; - } else if (reg->type == PTR_TO_RDWR_BUF_OR_NULL) { - reg->type = PTR_TO_RDWR_BUF; } if (is_null) { /* We don't need id and ref_obj_id from this point @@ -8040,7 +5954,7 @@ static void mark_ptr_or_null_reg(struct bpf_func_state *state, reg->ref_obj_id = 0; } else if (!reg_may_point_to_spin_lock(reg)) { /* For not-NULL ptr, reg->ref_obj_id will be reset - * in release_reference(). + * in release_reg_references(). * * reg->id is still used by spin_lock ptr. Other * than spin_lock ptr type, reg->id can be reset. @@ -8050,6 +5964,22 @@ static void mark_ptr_or_null_reg(struct bpf_func_state *state, } } +static void __mark_ptr_or_null_regs(struct bpf_func_state *state, u32 id, + bool is_null) +{ + struct bpf_reg_state *reg; + int i; + + for (i = 0; i < MAX_BPF_REG; i++) + mark_ptr_or_null_reg(state, &state->regs[i], id, is_null); + + bpf_for_each_spilled_reg(i, state, reg) { + if (!reg) + continue; + mark_ptr_or_null_reg(state, reg, id, is_null); + } +} + /* The logic is similar to find_good_pkt_pointers(), both could eventually * be folded together at some point. */ @@ -8057,9 +5987,10 @@ static void mark_ptr_or_null_regs(struct bpf_verifier_state *vstate, u32 regno, bool is_null) { struct bpf_func_state *state = vstate->frame[vstate->curframe]; - struct bpf_reg_state *regs = state->regs, *reg; + struct bpf_reg_state *regs = state->regs; u32 ref_obj_id = regs[regno].ref_obj_id; u32 id = regs[regno].id; + int i; if (ref_obj_id && ref_obj_id == id && is_null) /* regs[regno] is in the " == NULL" branch. @@ -8068,9 +5999,8 @@ static void mark_ptr_or_null_regs(struct bpf_verifier_state *vstate, u32 regno, */ WARN_ON_ONCE(release_reference_state(state, id)); - bpf_for_each_reg_in_vstate(vstate, state, reg, ({ - mark_ptr_or_null_reg(state, reg, id, is_null); - })); + for (i = 0; i <= vstate->curframe; i++) + __mark_ptr_or_null_regs(vstate->frame[i], id, is_null); } static bool try_match_pkt_pointers(const struct bpf_insn *insn, @@ -8095,7 +6025,6 @@ static bool try_match_pkt_pointers(const struct bpf_insn *insn, /* pkt_data' > pkt_end, pkt_meta' > pkt_data */ find_good_pkt_pointers(this_branch, dst_reg, dst_reg->type, false); - mark_pkt_end(other_branch, insn->dst_reg, true); } else if ((dst_reg->type == PTR_TO_PACKET_END && src_reg->type == PTR_TO_PACKET) || (reg_is_init_pkt_pointer(dst_reg, PTR_TO_PACKET) && @@ -8103,7 +6032,6 @@ static bool try_match_pkt_pointers(const struct bpf_insn *insn, /* pkt_end > pkt_data', pkt_data > pkt_meta' */ find_good_pkt_pointers(other_branch, src_reg, src_reg->type, true); - mark_pkt_end(this_branch, insn->src_reg, false); } else { return false; } @@ -8116,7 +6044,6 @@ static bool try_match_pkt_pointers(const struct bpf_insn *insn, /* pkt_data' < pkt_end, pkt_meta' < pkt_data */ find_good_pkt_pointers(other_branch, dst_reg, dst_reg->type, true); - mark_pkt_end(this_branch, insn->dst_reg, false); } else if ((dst_reg->type == PTR_TO_PACKET_END && src_reg->type == PTR_TO_PACKET) || (reg_is_init_pkt_pointer(dst_reg, PTR_TO_PACKET) && @@ -8124,7 +6051,6 @@ static bool try_match_pkt_pointers(const struct bpf_insn *insn, /* pkt_end < pkt_data', pkt_data > pkt_meta' */ find_good_pkt_pointers(this_branch, src_reg, src_reg->type, false); - mark_pkt_end(other_branch, insn->src_reg, true); } else { return false; } @@ -8137,7 +6063,6 @@ static bool try_match_pkt_pointers(const struct bpf_insn *insn, /* pkt_data' >= pkt_end, pkt_meta' >= pkt_data */ find_good_pkt_pointers(this_branch, dst_reg, dst_reg->type, true); - mark_pkt_end(other_branch, insn->dst_reg, false); } else if ((dst_reg->type == PTR_TO_PACKET_END && src_reg->type == PTR_TO_PACKET) || (reg_is_init_pkt_pointer(dst_reg, PTR_TO_PACKET) && @@ -8145,7 +6070,6 @@ static bool try_match_pkt_pointers(const struct bpf_insn *insn, /* pkt_end >= pkt_data', pkt_data >= pkt_meta' */ find_good_pkt_pointers(other_branch, src_reg, src_reg->type, false); - mark_pkt_end(this_branch, insn->src_reg, true); } else { return false; } @@ -8158,7 +6082,6 @@ static bool try_match_pkt_pointers(const struct bpf_insn *insn, /* pkt_data' <= pkt_end, pkt_meta' <= pkt_data */ find_good_pkt_pointers(other_branch, dst_reg, dst_reg->type, false); - mark_pkt_end(this_branch, insn->dst_reg, true); } else if ((dst_reg->type == PTR_TO_PACKET_END && src_reg->type == PTR_TO_PACKET) || (reg_is_init_pkt_pointer(dst_reg, PTR_TO_PACKET) && @@ -8166,7 +6089,6 @@ static bool try_match_pkt_pointers(const struct bpf_insn *insn, /* pkt_end <= pkt_data', pkt_data <= pkt_meta' */ find_good_pkt_pointers(this_branch, src_reg, src_reg->type, true); - mark_pkt_end(other_branch, insn->src_reg, false); } else { return false; } @@ -8178,21 +6100,6 @@ static bool try_match_pkt_pointers(const struct bpf_insn *insn, return true; } -static void find_equal_scalars(struct bpf_verifier_state *vstate, - struct bpf_reg_state *known_reg) -{ - struct bpf_func_state *state; - struct bpf_reg_state *reg; - - bpf_for_each_reg_in_vstate(vstate, state, reg, ({ - if (reg->type == SCALAR_VALUE && reg->id == known_reg->id) { - s32 saved_subreg_def = reg->subreg_def; - copy_register_state(reg, known_reg); - reg->subreg_def = saved_subreg_def; - } - })); -} - static int check_cond_jmp_op(struct bpf_verifier_env *env, struct bpf_insn *insn, int *insn_idx) { @@ -8243,34 +6150,16 @@ static int check_cond_jmp_op(struct bpf_verifier_env *env, dst_reg = ®s[insn->dst_reg]; is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32; - if (BPF_SRC(insn->code) == BPF_K) { - pred = is_branch_taken(dst_reg, insn->imm, opcode, is_jmp32); - } else if (src_reg->type == SCALAR_VALUE && - is_jmp32 && tnum_is_const(tnum_subreg(src_reg->var_off))) { - pred = is_branch_taken(dst_reg, - tnum_subreg(src_reg->var_off).value, - opcode, - is_jmp32); - } else if (src_reg->type == SCALAR_VALUE && - !is_jmp32 && tnum_is_const(src_reg->var_off)) { - pred = is_branch_taken(dst_reg, - src_reg->var_off.value, - opcode, - is_jmp32); - } else if (reg_is_pkt_pointer_any(dst_reg) && - reg_is_pkt_pointer_any(src_reg) && - !is_jmp32) { - pred = is_pkt_ptr_branch_taken(dst_reg, src_reg, opcode); - } - + if (BPF_SRC(insn->code) == BPF_K) + pred = is_branch_taken(dst_reg, insn->imm, + opcode, is_jmp32); + else if (src_reg->type == SCALAR_VALUE && + tnum_is_const(src_reg->var_off)) + pred = is_branch_taken(dst_reg, src_reg->var_off.value, + opcode, is_jmp32); if (pred >= 0) { - /* If we get here with a dst_reg pointer type it is because - * above is_branch_taken() special cased the 0 comparison. - */ - if (!__is_pointer_value(false, dst_reg)) - err = mark_chain_precision(env, insn->dst_reg); - if (BPF_SRC(insn->code) == BPF_X && !err && - !__is_pointer_value(false, src_reg)) + err = mark_chain_precision(env, insn->dst_reg); + if (BPF_SRC(insn->code) == BPF_X && !err) err = mark_chain_precision(env, insn->src_reg); if (err) return err; @@ -8281,7 +6170,7 @@ static int check_cond_jmp_op(struct bpf_verifier_env *env, * the fall-through branch for simulation under speculative * execution. */ - if (!env->bypass_spec_v1 && + if (!env->allow_ptr_leaks && !sanitize_speculative_path(env, insn, *insn_idx + 1, *insn_idx)) return -EFAULT; @@ -8292,7 +6181,7 @@ static int check_cond_jmp_op(struct bpf_verifier_env *env, * program will go. If needed, push the goto branch for * simulation under speculative execution. */ - if (!env->bypass_spec_v1 && + if (!env->allow_ptr_leaks && !sanitize_speculative_path(env, insn, *insn_idx + insn->off + 1, *insn_idx)) @@ -8315,24 +6204,32 @@ static int check_cond_jmp_op(struct bpf_verifier_env *env, */ if (BPF_SRC(insn->code) == BPF_X) { struct bpf_reg_state *src_reg = ®s[insn->src_reg]; + struct bpf_reg_state lo_reg0 = *dst_reg; + struct bpf_reg_state lo_reg1 = *src_reg; + struct bpf_reg_state *src_lo, *dst_lo; + + dst_lo = &lo_reg0; + src_lo = &lo_reg1; + coerce_reg_to_size(dst_lo, 4); + coerce_reg_to_size(src_lo, 4); if (dst_reg->type == SCALAR_VALUE && src_reg->type == SCALAR_VALUE) { if (tnum_is_const(src_reg->var_off) || - (is_jmp32 && - tnum_is_const(tnum_subreg(src_reg->var_off)))) + (is_jmp32 && tnum_is_const(src_lo->var_off))) reg_set_min_max(&other_branch_regs[insn->dst_reg], dst_reg, - src_reg->var_off.value, - tnum_subreg(src_reg->var_off).value, + is_jmp32 + ? src_lo->var_off.value + : src_reg->var_off.value, opcode, is_jmp32); else if (tnum_is_const(dst_reg->var_off) || - (is_jmp32 && - tnum_is_const(tnum_subreg(dst_reg->var_off)))) + (is_jmp32 && tnum_is_const(dst_lo->var_off))) reg_set_min_max_inv(&other_branch_regs[insn->src_reg], src_reg, - dst_reg->var_off.value, - tnum_subreg(dst_reg->var_off).value, + is_jmp32 + ? dst_lo->var_off.value + : dst_reg->var_off.value, opcode, is_jmp32); else if (!is_jmp32 && (opcode == BPF_JEQ || opcode == BPF_JNE)) @@ -8340,23 +6237,10 @@ static int check_cond_jmp_op(struct bpf_verifier_env *env, reg_combine_min_max(&other_branch_regs[insn->src_reg], &other_branch_regs[insn->dst_reg], src_reg, dst_reg, opcode); - if (src_reg->id && - !WARN_ON_ONCE(src_reg->id != other_branch_regs[insn->src_reg].id)) { - find_equal_scalars(this_branch, src_reg); - find_equal_scalars(other_branch, &other_branch_regs[insn->src_reg]); - } - } } else if (dst_reg->type == SCALAR_VALUE) { reg_set_min_max(&other_branch_regs[insn->dst_reg], - dst_reg, insn->imm, (u32)insn->imm, - opcode, is_jmp32); - } - - if (dst_reg->type == SCALAR_VALUE && dst_reg->id && - !WARN_ON_ONCE(dst_reg->id != other_branch_regs[insn->dst_reg].id)) { - find_equal_scalars(this_branch, dst_reg); - find_equal_scalars(other_branch, &other_branch_regs[insn->dst_reg]); + dst_reg, insn->imm, opcode, is_jmp32); } /* detect if R == 0 where R is returned from bpf_map_lookup_elem(). @@ -8390,7 +6274,6 @@ static int check_ld_imm(struct bpf_verifier_env *env, struct bpf_insn *insn) { struct bpf_insn_aux_data *aux = cur_aux(env); struct bpf_reg_state *regs = cur_regs(env); - struct bpf_reg_state *dst_reg; struct bpf_map *map; int err; @@ -8407,45 +6290,25 @@ static int check_ld_imm(struct bpf_verifier_env *env, struct bpf_insn *insn) if (err) return err; - dst_reg = ®s[insn->dst_reg]; if (insn->src_reg == 0) { u64 imm = ((u64)(insn + 1)->imm << 32) | (u32)insn->imm; - dst_reg->type = SCALAR_VALUE; + regs[insn->dst_reg].type = SCALAR_VALUE; __mark_reg_known(®s[insn->dst_reg], imm); return 0; } - if (insn->src_reg == BPF_PSEUDO_BTF_ID) { - mark_reg_known_zero(env, regs, insn->dst_reg); - - dst_reg->type = aux->btf_var.reg_type; - switch (dst_reg->type) { - case PTR_TO_MEM: - dst_reg->mem_size = aux->btf_var.mem_size; - break; - case PTR_TO_BTF_ID: - case PTR_TO_PERCPU_BTF_ID: - dst_reg->btf_id = aux->btf_var.btf_id; - break; - default: - verbose(env, "bpf verifier is misconfigured\n"); - return -EFAULT; - } - return 0; - } - map = env->used_maps[aux->map_index]; mark_reg_known_zero(env, regs, insn->dst_reg); - dst_reg->map_ptr = map; + regs[insn->dst_reg].map_ptr = map; if (insn->src_reg == BPF_PSEUDO_MAP_VALUE) { - dst_reg->type = PTR_TO_MAP_VALUE; - dst_reg->off = aux->map_off; + regs[insn->dst_reg].type = PTR_TO_MAP_VALUE; + regs[insn->dst_reg].off = aux->map_off; if (map_value_has_spin_lock(map)) - dst_reg->id = ++env->id_gen; + regs[insn->dst_reg].id = ++env->id_gen; } else if (insn->src_reg == BPF_PSEUDO_MAP_FD) { - dst_reg->type = CONST_PTR_TO_MAP; + regs[insn->dst_reg].type = CONST_PTR_TO_MAP; } else { verbose(env, "bpf verifier is misconfigured\n"); return -EINVAL; @@ -8488,7 +6351,7 @@ static int check_ld_abs(struct bpf_verifier_env *env, struct bpf_insn *insn) u8 mode = BPF_MODE(insn->code); int i, err; - if (!may_access_skb(resolve_prog_type(env->prog))) { + if (!may_access_skb(env->prog->type)) { verbose(env, "BPF_LD_[ABS|IND] instructions not allowed for this program type\n"); return -EINVAL; } @@ -8498,6 +6361,18 @@ static int check_ld_abs(struct bpf_verifier_env *env, struct bpf_insn *insn) return -EINVAL; } + if (env->subprog_cnt > 1) { + /* when program has LD_ABS insn JITs and interpreter assume + * that r1 == ctx == skb which is not the case for callees + * that can have arbitrary arguments. It's problematic + * for main prog as well since JITs would need to analyze + * all functions in order to make proper register save/restore + * decisions in the main prog. Hence disallow LD_ABS with calls + */ + verbose(env, "BPF_LD_[ABS|IND] instructions cannot be mixed with bpf-to-bpf calls\n"); + return -EINVAL; + } + if (insn->dst_reg != BPF_REG_0 || insn->off != 0 || BPF_SIZE(insn->code) == BPF_DW || (mode == BPF_ABS && insn->src_reg != BPF_REG_0)) { @@ -8561,53 +6436,13 @@ static int check_ld_abs(struct bpf_verifier_env *env, struct bpf_insn *insn) static int check_return_code(struct bpf_verifier_env *env) { struct tnum enforce_attach_type_range = tnum_unknown; - const struct bpf_prog *prog = env->prog; struct bpf_reg_state *reg; struct tnum range = tnum_range(0, 1); - enum bpf_prog_type prog_type = resolve_prog_type(env->prog); - int err; - const bool is_subprog = env->cur_state->frame[0]->subprogno; - /* LSM and struct_ops func-ptr's return type could be "void" */ - if (!is_subprog && - (prog_type == BPF_PROG_TYPE_STRUCT_OPS || - prog_type == BPF_PROG_TYPE_LSM) && - !prog->aux->attach_func_proto->type) - return 0; - - /* eBPF calling convetion is such that R0 is used - * to return the value from eBPF program. - * Make sure that it's readable at this time - * of bpf_exit, which means that program wrote - * something into it earlier - */ - err = check_reg_arg(env, BPF_REG_0, SRC_OP); - if (err) - return err; - - if (is_pointer_value(env, BPF_REG_0)) { - verbose(env, "R0 leaks addr as return value\n"); - return -EACCES; - } - - reg = cur_regs(env) + BPF_REG_0; - if (is_subprog) { - if (reg->type != SCALAR_VALUE) { - verbose(env, "At subprogram exit the register R0 is not a scalar value (%s)\n", - reg_type_str[reg->type]); - return -EINVAL; - } - return 0; - } - - switch (prog_type) { + switch (env->prog->type) { case BPF_PROG_TYPE_CGROUP_SOCK_ADDR: if (env->prog->expected_attach_type == BPF_CGROUP_UDP4_RECVMSG || - env->prog->expected_attach_type == BPF_CGROUP_UDP6_RECVMSG || - env->prog->expected_attach_type == BPF_CGROUP_INET4_GETPEERNAME || - env->prog->expected_attach_type == BPF_CGROUP_INET6_GETPEERNAME || - env->prog->expected_attach_type == BPF_CGROUP_INET4_GETSOCKNAME || - env->prog->expected_attach_type == BPF_CGROUP_INET6_GETSOCKNAME) + env->prog->expected_attach_type == BPF_CGROUP_UDP6_RECVMSG) range = tnum_range(1, 1); break; case BPF_PROG_TYPE_CGROUP_SKB: @@ -8622,37 +6457,11 @@ static int check_return_code(struct bpf_verifier_env *env) case BPF_PROG_TYPE_CGROUP_SYSCTL: case BPF_PROG_TYPE_CGROUP_SOCKOPT: break; - case BPF_PROG_TYPE_RAW_TRACEPOINT: - if (!env->prog->aux->attach_btf_id) - return 0; - range = tnum_const(0); - break; - case BPF_PROG_TYPE_TRACING: - switch (env->prog->expected_attach_type) { - case BPF_TRACE_FENTRY: - case BPF_TRACE_FEXIT: - range = tnum_const(0); - break; - case BPF_TRACE_RAW_TP: - case BPF_MODIFY_RETURN: - return 0; - case BPF_TRACE_ITER: - break; - default: - return -ENOTSUPP; - } - break; - case BPF_PROG_TYPE_SK_LOOKUP: - range = tnum_range(SK_DROP, SK_PASS); - break; - case BPF_PROG_TYPE_EXT: - /* freplace program can return anything as its return value - * depends on the to-be-replaced kernel func or bpf program. - */ default: return 0; } + reg = cur_regs(env) + BPF_REG_0; if (reg->type != SCALAR_VALUE) { verbose(env, "At program exit the register R0 is not a known value (%s)\n", reg_type_str[reg->type]); @@ -8776,7 +6585,7 @@ static int push_insn(int t, int w, int e, struct bpf_verifier_env *env, insn_stack[env->cfg.cur_stack++] = w; return 1; } else if ((insn_state[w] & 0xF0) == DISCOVERED) { - if (loop_ok && env->bpf_capable) + if (loop_ok && env->allow_ptr_leaks) return 0; verbose_linfo(env, t, "%d: ", t); verbose_linfo(env, w, "%d: ", w); @@ -8919,23 +6728,6 @@ err_free: return ret; } -static int check_abnormal_return(struct bpf_verifier_env *env) -{ - int i; - - for (i = 1; i < env->subprog_cnt; i++) { - if (env->subprog_info[i].has_ld_abs) { - verbose(env, "LD_ABS is not allowed in subprogs without BTF\n"); - return -EINVAL; - } - if (env->subprog_info[i].has_tail_call) { - verbose(env, "tail_call is not allowed in subprogs without BTF\n"); - return -EINVAL; - } - } - return 0; -} - /* The minimum supported BTF func info size */ #define MIN_BPF_FUNCINFO_SIZE 8 #define MAX_FUNCINFO_REC_SIZE 252 @@ -8944,24 +6736,19 @@ static int check_btf_func(struct bpf_verifier_env *env, const union bpf_attr *attr, union bpf_attr __user *uattr) { - const struct btf_type *type, *func_proto, *ret_type; u32 i, nfuncs, urec_size, min_size; u32 krec_size = sizeof(struct bpf_func_info); struct bpf_func_info *krecord; - struct bpf_func_info_aux *info_aux = NULL; + const struct btf_type *type; struct bpf_prog *prog; const struct btf *btf; void __user *urecord; u32 prev_offset = 0; - bool scalar_return; - int ret = -ENOMEM; + int ret = 0; nfuncs = attr->func_info_cnt; - if (!nfuncs) { - if (check_abnormal_return(env)) - return -EINVAL; + if (!nfuncs) return 0; - } if (nfuncs != env->subprog_cnt) { verbose(env, "number of funcs in func_info doesn't match number of subprogs\n"); @@ -8985,9 +6772,6 @@ static int check_btf_func(struct bpf_verifier_env *env, krecord = kvcalloc(nfuncs, krec_size, GFP_KERNEL | __GFP_NOWARN); if (!krecord) return -ENOMEM; - info_aux = kcalloc(nfuncs, sizeof(*info_aux), GFP_KERNEL | __GFP_NOWARN); - if (!info_aux) - goto err_free; for (i = 0; i < nfuncs; i++) { ret = bpf_check_uarg_tail_zero(urecord, krec_size, urec_size); @@ -9009,48 +6793,34 @@ static int check_btf_func(struct bpf_verifier_env *env, } /* check insn_off */ - ret = -EINVAL; if (i == 0) { if (krecord[i].insn_off) { verbose(env, "nonzero insn_off %u for the first func info record", krecord[i].insn_off); + ret = -EINVAL; goto err_free; } } else if (krecord[i].insn_off <= prev_offset) { verbose(env, "same or smaller insn offset (%u) than previous func info record (%u)", krecord[i].insn_off, prev_offset); + ret = -EINVAL; goto err_free; } if (env->subprog_info[i].start != krecord[i].insn_off) { verbose(env, "func_info BTF section doesn't match subprog layout in BPF program\n"); + ret = -EINVAL; goto err_free; } /* check type_id */ type = btf_type_by_id(btf, krecord[i].type_id); - if (!type || !btf_type_is_func(type)) { + if (!type || BTF_INFO_KIND(type->info) != BTF_KIND_FUNC) { verbose(env, "invalid type id %d in func info", krecord[i].type_id); - goto err_free; - } - info_aux[i].linkage = BTF_INFO_VLEN(type->info); - - func_proto = btf_type_by_id(btf, type->type); - if (unlikely(!func_proto || !btf_type_is_func_proto(func_proto))) - /* btf_func_check() already verified it during BTF load */ - goto err_free; - ret_type = btf_type_skip_modifiers(btf, func_proto->type, NULL); - scalar_return = - btf_type_is_small_int(ret_type) || btf_type_is_enum(ret_type); - if (i && !scalar_return && env->subprog_info[i].has_ld_abs) { - verbose(env, "LD_ABS is only allowed in functions that return 'int'.\n"); - goto err_free; - } - if (i && !scalar_return && env->subprog_info[i].has_tail_call) { - verbose(env, "tail_call is only allowed in functions that return 'int'.\n"); + ret = -EINVAL; goto err_free; } @@ -9060,25 +6830,22 @@ static int check_btf_func(struct bpf_verifier_env *env, prog->aux->func_info = krecord; prog->aux->func_info_cnt = nfuncs; - prog->aux->func_info_aux = info_aux; return 0; err_free: kvfree(krecord); - kfree(info_aux); return ret; } static void adjust_btf_func(struct bpf_verifier_env *env) { - struct bpf_prog_aux *aux = env->prog->aux; int i; - if (!aux->func_info) + if (!env->prog->aux->func_info) return; for (i = 0; i < env->subprog_cnt; i++) - aux->func_info[i].insn_off = env->subprog_info[i].start; + env->prog->aux->func_info[i].insn_off = env->subprog_info[i].start; } #define MIN_BPF_LINEINFO_SIZE (offsetof(struct bpf_line_info, line_col) + \ @@ -9216,11 +6983,8 @@ static int check_btf_info(struct bpf_verifier_env *env, struct btf *btf; int err; - if (!attr->func_info_cnt && !attr->line_info_cnt) { - if (check_abnormal_return(env)) - return -EINVAL; + if (!attr->func_info_cnt && !attr->line_info_cnt) return 0; - } btf = btf_get_by_fd(attr->prog_btf_fd); if (IS_ERR(btf)) @@ -9245,11 +7009,7 @@ static bool range_within(struct bpf_reg_state *old, return old->umin_value <= cur->umin_value && old->umax_value >= cur->umax_value && old->smin_value <= cur->smin_value && - old->smax_value >= cur->smax_value && - old->u32_min_value <= cur->u32_min_value && - old->u32_max_value >= cur->u32_max_value && - old->s32_min_value <= cur->s32_min_value && - old->s32_max_value >= cur->s32_max_value; + old->smax_value >= cur->smax_value; } /* If in the old state two registers had the same id, then they need to have @@ -9408,7 +7168,7 @@ static bool regsafe(struct bpf_verifier_env *env, struct bpf_reg_state *rold, if (env->explore_alu_limits) return false; if (rcur->type == SCALAR_VALUE) { - if (!rold->precise) + if (!rold->precise && !rcur->precise) return true; /* new val must satisfy old val knowledge */ return range_within(rold, rcur) && @@ -9517,10 +7277,6 @@ static bool stacksafe(struct bpf_verifier_env *env, struct bpf_func_state *old, if (old->stack[spi].slot_type[i % BPF_REG_SIZE] == STACK_INVALID) continue; - if (env->allow_uninit_stack && - old->stack[spi].slot_type[i % BPF_REG_SIZE] == STACK_MISC) - continue; - /* explored stack has more populated slots than current stack * and these slots were used */ @@ -9537,14 +7293,14 @@ static bool stacksafe(struct bpf_verifier_env *env, struct bpf_func_state *old, if (old->stack[spi].slot_type[i % BPF_REG_SIZE] != cur->stack[spi].slot_type[i % BPF_REG_SIZE]) /* Ex: old explored (safe) state has STACK_SPILL in - * this stack slot, but current has STACK_MISC -> + * this stack slot, but current has has STACK_MISC -> * this verifier states are not equivalent, * return false to continue verification of this path */ return false; - if (i % BPF_REG_SIZE != BPF_REG_SIZE - 1) + if (i % BPF_REG_SIZE) continue; - if (!is_spilled_reg(&old->stack[spi])) + if (old->stack[spi].slot_type[0] != STACK_SPILL) continue; if (!regsafe(env, &old->stack[spi].spilled_ptr, &cur->stack[spi].spilled_ptr, idmap)) @@ -9735,38 +7491,34 @@ static int propagate_precision(struct bpf_verifier_env *env, { struct bpf_reg_state *state_reg; struct bpf_func_state *state; - int i, err = 0, fr; + int i, err = 0; - for (fr = old->curframe; fr >= 0; fr--) { - state = old->frame[fr]; - state_reg = state->regs; - for (i = 0; i < BPF_REG_FP; i++, state_reg++) { - if (state_reg->type != SCALAR_VALUE || - !state_reg->precise || - !(state_reg->live & REG_LIVE_READ)) - continue; - if (env->log.level & BPF_LOG_LEVEL2) - verbose(env, "frame %d: propagating r%d\n", fr, i); - err = mark_chain_precision_frame(env, fr, i); - if (err < 0) - return err; - } + state = old->frame[old->curframe]; + state_reg = state->regs; + for (i = 0; i < BPF_REG_FP; i++, state_reg++) { + if (state_reg->type != SCALAR_VALUE || + !state_reg->precise) + continue; + if (env->log.level & BPF_LOG_LEVEL2) + verbose(env, "propagating r%d\n", i); + err = mark_chain_precision(env, i); + if (err < 0) + return err; + } - for (i = 0; i < state->allocated_stack / BPF_REG_SIZE; i++) { - if (!is_spilled_reg(&state->stack[i])) - continue; - state_reg = &state->stack[i].spilled_ptr; - if (state_reg->type != SCALAR_VALUE || - !state_reg->precise || - !(state_reg->live & REG_LIVE_READ)) - continue; - if (env->log.level & BPF_LOG_LEVEL2) - verbose(env, "frame %d: propagating fp%d\n", - fr, (-i - 1) * BPF_REG_SIZE); - err = mark_chain_precision_stack_frame(env, fr, i); - if (err < 0) - return err; - } + for (i = 0; i < state->allocated_stack / BPF_REG_SIZE; i++) { + if (state->stack[i].slot_type[0] != STACK_SPILL) + continue; + state_reg = &state->stack[i].spilled_ptr; + if (state_reg->type != SCALAR_VALUE || + !state_reg->precise) + continue; + if (env->log.level & BPF_LOG_LEVEL2) + verbose(env, "propagating fp%d\n", + (-i - 1) * BPF_REG_SIZE); + err = mark_chain_precision_stack(env, i); + if (err < 0) + return err; } return 0; } @@ -9922,7 +7674,7 @@ next: if (env->max_states_per_insn < states_cnt) env->max_states_per_insn = states_cnt; - if (!env->bpf_capable && states_cnt > BPF_COMPLEXITY_LIMIT_STATES) + if (!env->allow_ptr_leaks && states_cnt > BPF_COMPLEXITY_LIMIT_STATES) return push_jmp_history(env, cur); if (!add_new_state) @@ -9945,10 +7697,6 @@ next: env->prev_jmps_processed = env->jmps_processed; env->prev_insn_processed = env->insn_processed; - /* forget precise markings we inherited, see __mark_chain_precision */ - if (env->bpf_capable) - mark_all_scalars_imprecise(env, cur); - /* add new state to the head of linked list */ new = &new_sl->state; err = copy_verifier_state(new, cur); @@ -10012,8 +7760,6 @@ static bool reg_type_mismatch_ok(enum bpf_reg_type type) case PTR_TO_TCP_SOCK: case PTR_TO_TCP_SOCK_OR_NULL: case PTR_TO_XDP_SOCK: - case PTR_TO_BTF_ID: - case PTR_TO_BTF_ID_OR_NULL: return false; default: return true; @@ -10040,14 +7786,32 @@ static bool reg_type_mismatch(enum bpf_reg_type src, enum bpf_reg_type prev) static int do_check(struct bpf_verifier_env *env) { - bool pop_log = !(env->log.level & BPF_LOG_LEVEL2); - struct bpf_verifier_state *state = env->cur_state; + struct bpf_verifier_state *state; struct bpf_insn *insns = env->prog->insnsi; struct bpf_reg_state *regs; int insn_cnt = env->prog->len; bool do_print_state = false; int prev_insn_idx = -1; + env->prev_linfo = NULL; + + state = kzalloc(sizeof(struct bpf_verifier_state), GFP_KERNEL); + if (!state) + return -ENOMEM; + state->curframe = 0; + state->speculative = false; + state->branches = 1; + state->frame[0] = kzalloc(sizeof(struct bpf_func_state), GFP_KERNEL); + if (!state->frame[0]) { + kfree(state); + return -ENOMEM; + } + env->cur_state = state; + init_func_state(env, state->frame[0], + BPF_MAIN_FUNC /* callsite */, + 0 /* frameno */, + 0 /* subprogno, zero == main subprog */); + for (;;) { struct bpf_insn *insn; u8 class; @@ -10311,13 +8075,28 @@ static int do_check(struct bpf_verifier_env *env) if (err) return err; + /* eBPF calling convetion is such that R0 is used + * to return the value from eBPF program. + * Make sure that it's readable at this time + * of bpf_exit, which means that program wrote + * something into it earlier + */ + err = check_reg_arg(env, BPF_REG_0, SRC_OP); + if (err) + return err; + + if (is_pointer_value(env, BPF_REG_0)) { + verbose(env, "R0 leaks addr as return value\n"); + return -EACCES; + } + err = check_return_code(env); if (err) return err; process_bpf_exit: update_branch_counts(env, env->cur_state); err = pop_stack(env, &prev_insn_idx, - &env->insn_idx, pop_log); + &env->insn_idx); if (err < 0) { if (err != -ENOENT) return err; @@ -10358,93 +8137,7 @@ process_bpf_exit: env->insn_idx++; } - return 0; -} - -/* replace pseudo btf_id with kernel symbol address */ -static int check_pseudo_btf_id(struct bpf_verifier_env *env, - struct bpf_insn *insn, - struct bpf_insn_aux_data *aux) -{ - const struct btf_var_secinfo *vsi; - const struct btf_type *datasec; - const struct btf_type *t; - const char *sym_name; - bool percpu = false; - u32 type, id = insn->imm; - s32 datasec_id; - u64 addr; - int i; - - if (!btf_vmlinux) { - verbose(env, "kernel is missing BTF, make sure CONFIG_DEBUG_INFO_BTF=y is specified in Kconfig.\n"); - return -EINVAL; - } - - if (insn[1].imm != 0) { - verbose(env, "reserved field (insn[1].imm) is used in pseudo_btf_id ldimm64 insn.\n"); - return -EINVAL; - } - - t = btf_type_by_id(btf_vmlinux, id); - if (!t) { - verbose(env, "ldimm64 insn specifies invalid btf_id %d.\n", id); - return -ENOENT; - } - - if (!btf_type_is_var(t)) { - verbose(env, "pseudo btf_id %d in ldimm64 isn't KIND_VAR.\n", - id); - return -EINVAL; - } - - sym_name = btf_name_by_offset(btf_vmlinux, t->name_off); - addr = kallsyms_lookup_name(sym_name); - if (!addr) { - verbose(env, "ldimm64 failed to find the address for kernel symbol '%s'.\n", - sym_name); - return -ENOENT; - } - - datasec_id = btf_find_by_name_kind(btf_vmlinux, ".data..percpu", - BTF_KIND_DATASEC); - if (datasec_id > 0) { - datasec = btf_type_by_id(btf_vmlinux, datasec_id); - for_each_vsi(i, datasec, vsi) { - if (vsi->type == id) { - percpu = true; - break; - } - } - } - - insn[0].imm = (u32)addr; - insn[1].imm = addr >> 32; - - type = t->type; - t = btf_type_skip_modifiers(btf_vmlinux, type, NULL); - if (percpu) { - aux->btf_var.reg_type = PTR_TO_PERCPU_BTF_ID; - aux->btf_var.btf_id = type; - } else if (!btf_type_is_struct(t)) { - const struct btf_type *ret; - const char *tname; - u32 tsize; - - /* resolve the type size of ksym. */ - ret = btf_resolve_size(btf_vmlinux, t, &tsize); - if (IS_ERR(ret)) { - tname = btf_name_by_offset(btf_vmlinux, t->name_off); - verbose(env, "ldimm64 unable to resolve the size of type '%s': %ld\n", - tname, PTR_ERR(ret)); - return -EINVAL; - } - aux->btf_var.reg_type = PTR_TO_MEM; - aux->btf_var.mem_size = tsize; - } else { - aux->btf_var.reg_type = PTR_TO_BTF_ID; - aux->btf_var.btf_id = type; - } + env->prog->aux->stack_depth = env->subprog_info[0].stack_depth; return 0; } @@ -10469,53 +8162,30 @@ static bool is_tracing_prog_type(enum bpf_prog_type type) } } -static bool is_preallocated_map(struct bpf_map *map) -{ - if (!check_map_prealloc(map)) - return false; - if (map->inner_map_meta && !check_map_prealloc(map->inner_map_meta)) - return false; - return true; -} - static int check_map_prog_compatibility(struct bpf_verifier_env *env, struct bpf_map *map, struct bpf_prog *prog) { - enum bpf_prog_type prog_type = resolve_prog_type(prog); - /* - * Validate that trace type programs use preallocated hash maps. - * - * For programs attached to PERF events this is mandatory as the - * perf NMI can hit any arbitrary code sequence. - * - * All other trace types using preallocated hash maps are unsafe as - * well because tracepoint or kprobes can be inside locked regions - * of the memory allocator or at a place where a recursion into the - * memory allocator would see inconsistent state. - * - * On RT enabled kernels run-time allocation of all trace type - * programs is strictly prohibited due to lock type constraints. On - * !RT kernels it is allowed for backwards compatibility reasons for - * now, but warnings are emitted so developers are made aware of - * the unsafety and can fix their programs before this is enforced. + /* Make sure that BPF_PROG_TYPE_PERF_EVENT programs only use + * preallocated hash maps, since doing memory allocation + * in overflow_handler can crash depending on where nmi got + * triggered. */ - if (is_tracing_prog_type(prog_type) && !is_preallocated_map(map)) { - if (prog_type == BPF_PROG_TYPE_PERF_EVENT) { + if (prog->type == BPF_PROG_TYPE_PERF_EVENT) { + if (!check_map_prealloc(map)) { verbose(env, "perf_event programs can only use preallocated hash map\n"); return -EINVAL; } - if (IS_ENABLED(CONFIG_PREEMPT_RT)) { - verbose(env, "trace type programs can only use preallocated hash map\n"); + if (map->inner_map_meta && + !check_map_prealloc(map->inner_map_meta)) { + verbose(env, "perf_event programs can only use preallocated inner hash map\n"); return -EINVAL; } - WARN_ONCE(1, "trace type BPF program uses run-time allocation\n"); - verbose(env, "trace type programs with run-time allocated hash maps are unsafe. Switch to preallocated hash maps.\n"); } - if ((is_tracing_prog_type(prog_type) || - prog_type == BPF_PROG_TYPE_SOCKET_FILTER) && + if ((is_tracing_prog_type(prog->type) || + prog->type == BPF_PROG_TYPE_SOCKET_FILTER) && map_value_has_spin_lock(map)) { verbose(env, "tracing progs cannot use bpf_spin_lock yet\n"); return -EINVAL; @@ -10527,28 +8197,6 @@ static int check_map_prog_compatibility(struct bpf_verifier_env *env, return -EINVAL; } - if (map->map_type == BPF_MAP_TYPE_STRUCT_OPS) { - verbose(env, "bpf_struct_ops map cannot be used in prog\n"); - return -EINVAL; - } - - if (prog->aux->sleepable) - switch (map->map_type) { - case BPF_MAP_TYPE_HASH: - case BPF_MAP_TYPE_LRU_HASH: - case BPF_MAP_TYPE_ARRAY: - if (!is_preallocated_map(map)) { - verbose(env, - "Sleepable programs can only use preallocated hash maps\n"); - return -EINVAL; - } - break; - default: - verbose(env, - "Sleepable programs can only use array and hash maps\n"); - return -EINVAL; - } - return 0; } @@ -10558,14 +8206,10 @@ static bool bpf_map_is_cgroup_storage(struct bpf_map *map) map->map_type == BPF_MAP_TYPE_PERCPU_CGROUP_STORAGE); } -/* find and rewrite pseudo imm in ld_imm64 instructions: - * - * 1. if it accesses map FD, replace it with actual map pointer. - * 2. if it accesses btf_id of a VAR, replace it with pointer to the var. - * - * NOTE: btf_vmlinux is required for converting pseudo btf_id. +/* look for pseudo eBPF instructions that access map FDs and + * replace them with actual map pointers */ -static int resolve_pseudo_ldimm64(struct bpf_verifier_env *env) +static int replace_map_fd_with_map_ptr(struct bpf_verifier_env *env) { struct bpf_insn *insn = env->prog->insnsi; int insn_cnt = env->prog->len; @@ -10606,14 +8250,6 @@ static int resolve_pseudo_ldimm64(struct bpf_verifier_env *env) /* valid generic load 64-bit imm */ goto next_insn; - if (insn[0].src_reg == BPF_PSEUDO_BTF_ID) { - aux = &env->insn_aux_data[i]; - err = check_pseudo_btf_id(env, insn, aux); - if (err) - return err; - goto next_insn; - } - /* In final convert_pseudo_ld_imm64() step, this is * converted into regular 64-bit imm load insn. */ @@ -10692,13 +8328,17 @@ static int resolve_pseudo_ldimm64(struct bpf_verifier_env *env) * will be used by the valid program until it's unloaded * and all maps are released in free_used_maps() */ - bpf_map_inc(map); + map = bpf_map_inc(map, false); + if (IS_ERR(map)) { + fdput(f); + return PTR_ERR(map); + } aux->map_index = env->used_map_cnt; env->used_maps[env->used_map_cnt++] = map; if (bpf_map_is_cgroup_storage(map) && - bpf_cgroup_storage_assign(env->prog->aux, map)) { + bpf_cgroup_storage_assign(env->prog, map)) { verbose(env, "only one cgroup storage of each type is allowed\n"); fdput(f); return -EBUSY; @@ -10728,8 +8368,18 @@ next_insn: /* drop refcnt of maps used by the rejected program */ static void release_maps(struct bpf_verifier_env *env) { - __bpf_free_used_maps(env->prog->aux, env->used_maps, - env->used_map_cnt); + enum bpf_cgroup_storage_type stype; + int i; + + for_each_cgroup_storage_type(stype) { + if (!env->prog->aux->cgroup_storage[stype]) + continue; + bpf_cgroup_storage_release(env->prog, + env->prog->aux->cgroup_storage[stype]); + } + + for (i = 0; i < env->used_map_cnt; i++) + bpf_map_put(env->used_maps[i]); } /* convert pseudo BPF_LD_IMM64 into generic BPF_LD_IMM64 */ @@ -10754,7 +8404,7 @@ static void adjust_insn_aux_data(struct bpf_verifier_env *env, { struct bpf_insn_aux_data *old_data = env->insn_aux_data; struct bpf_insn *insn = new_prog->insnsi; - u32 old_seen = old_data[off].seen; + bool old_seen = old_data[off].seen; u32 prog_len; int i; @@ -10794,20 +8444,6 @@ static void adjust_subprog_starts(struct bpf_verifier_env *env, u32 off, u32 len } } -static void adjust_poke_descs(struct bpf_prog *prog, u32 off, u32 len) -{ - struct bpf_jit_poke_descriptor *tab = prog->aux->poke_tab; - int i, sz = prog->aux->size_poke_tab; - struct bpf_jit_poke_descriptor *desc; - - for (i = 0; i < sz; i++) { - desc = &tab[i]; - if (desc->insn_idx <= off) - continue; - desc->insn_idx += len - 1; - } -} - static struct bpf_prog *bpf_patch_insn_data(struct bpf_verifier_env *env, u32 off, const struct bpf_insn *patch, u32 len) { @@ -10832,7 +8468,6 @@ static struct bpf_prog *bpf_patch_insn_data(struct bpf_verifier_env *env, u32 of } adjust_insn_aux_data(env, new_data, new_prog, off, len); adjust_subprog_starts(env, off, len); - adjust_poke_descs(new_prog, off, len); return new_prog; } @@ -11275,16 +8910,6 @@ static int convert_ctx_accesses(struct bpf_verifier_env *env) case PTR_TO_XDP_SOCK: convert_ctx_access = bpf_xdp_sock_convert_ctx_access; break; - case PTR_TO_BTF_ID: - if (type == BPF_READ) { - insn->code = BPF_LDX | BPF_PROBE_MEM | - BPF_SIZE((insn)->code); - env->prog->aux->num_exentries++; - } else if (resolve_prog_type(env->prog) != BPF_PROG_TYPE_STRUCT_OPS) { - verbose(env, "Writes through BTF pointers are not allowed\n"); - return -EINVAL; - } - continue; default: continue; } @@ -11369,10 +8994,9 @@ static int jit_subprogs(struct bpf_verifier_env *env) { struct bpf_prog *prog = env->prog, **func, *tmp; int i, j, subprog_start, subprog_end = 0, len, subprog; - struct bpf_map *map_ptr; struct bpf_insn *insn; void *old_bpf_func; - int err, num_exentries; + int err; if (env->subprog_cnt <= 1) return 0; @@ -11433,22 +9057,13 @@ static int jit_subprogs(struct bpf_verifier_env *env) goto out_free; func[i]->is_func = 1; func[i]->aux->func_idx = i; - /* Below members will be freed only at prog->aux */ + /* the btf and func_info will be freed only at prog->aux */ func[i]->aux->btf = prog->aux->btf; func[i]->aux->func_info = prog->aux->func_info; - func[i]->aux->func_info_cnt = prog->aux->func_info_cnt; - func[i]->aux->poke_tab = prog->aux->poke_tab; - func[i]->aux->size_poke_tab = prog->aux->size_poke_tab; - - for (j = 0; j < prog->aux->size_poke_tab; j++) { - struct bpf_jit_poke_descriptor *poke; - - poke = &prog->aux->poke_tab[j]; - if (poke->insn_idx < subprog_end && - poke->insn_idx >= subprog_start) - poke->aux = func[i]->aux; - } + /* Use bpf_prog_F_tag to indicate functions in stack traces. + * Long term would need debug info to populate names + */ func[i]->aux->name[0] = 'F'; func[i]->aux->stack_depth = env->subprog_info[i].stack_depth; func[i]->jit_requested = 1; @@ -11456,15 +9071,6 @@ static int jit_subprogs(struct bpf_verifier_env *env) func[i]->aux->nr_linfo = prog->aux->nr_linfo; func[i]->aux->jited_linfo = prog->aux->jited_linfo; func[i]->aux->linfo_idx = env->subprog_info[i].linfo_idx; - num_exentries = 0; - insn = func[i]->insnsi; - for (j = 0; j < func[i]->len; j++, insn++) { - if (BPF_CLASS(insn->code) == BPF_LDX && - BPF_MODE(insn->code) == BPF_PROBE_MEM) - num_exentries++; - } - func[i]->aux->num_exentries = num_exentries; - func[i]->aux->tail_call_reachable = env->subprog_info[i].tail_call_reachable; func[i] = bpf_int_jit_compile(func[i]); if (!func[i]->jited) { err = -ENOTSUPP; @@ -11472,7 +9078,6 @@ static int jit_subprogs(struct bpf_verifier_env *env) } cond_resched(); } - /* at this point all bpf functions were successfully JITed * now populate all bpf_calls with correct addresses and * run last pass of JIT @@ -11541,24 +9146,9 @@ static int jit_subprogs(struct bpf_verifier_env *env) bpf_prog_free_unused_jited_linfo(prog); return 0; out_free: - /* We failed JIT'ing, so at this point we need to unregister poke - * descriptors from subprogs, so that kernel is not attempting to - * patch it anymore as we're freeing the subprog JIT memory. - */ - for (i = 0; i < prog->aux->size_poke_tab; i++) { - map_ptr = prog->aux->poke_tab[i].tail_call.map; - map_ptr->ops->map_poke_untrack(map_ptr, prog->aux); - } - /* At this point we're guaranteed that poke descriptors are not - * live anymore. We can just unlink its descriptor table as it's - * released with the main prog. - */ - for (i = 0; i < env->subprog_cnt; i++) { - if (!func[i]) - continue; - func[i]->aux->poke_tab = NULL; - bpf_jit_free(func[i]); - } + for (i = 0; i < env->subprog_cnt; i++) + if (func[i]) + bpf_jit_free(func[i]); kfree(func); out_undo_insn: /* cleanup main prog to be interpreted */ @@ -11592,13 +9182,6 @@ static int fixup_call_args(struct bpf_verifier_env *env) return err; } #ifndef CONFIG_BPF_JIT_ALWAYS_ON - if (env->subprog_cnt > 1 && env->prog->aux->tail_call_reachable) { - /* When JIT fails the progs with bpf2bpf calls and tail_calls - * have to be rejected, since interpreter doesn't support them yet. - */ - verbose(env, "tail_calls are not allowed in non-JITed programs with bpf-to-bpf calls\n"); - return -EINVAL; - } for (i = 0; i < prog->len; i++, insn++) { if (insn->code != (BPF_JMP | BPF_CALL) || insn->src_reg != BPF_PSEUDO_CALL) @@ -11621,7 +9204,6 @@ static int fixup_call_args(struct bpf_verifier_env *env) static int fixup_bpf_calls(struct bpf_verifier_env *env) { struct bpf_prog *prog = env->prog; - bool expect_blinding = bpf_jit_blinding_enabled(prog); struct bpf_insn *insn = prog->insnsi; const struct bpf_func_proto *fn; const int insn_cnt = prog->len; @@ -11630,7 +9212,7 @@ static int fixup_bpf_calls(struct bpf_verifier_env *env) struct bpf_insn insn_buf[16]; struct bpf_prog *new_prog; struct bpf_map *map_ptr; - int i, ret, cnt, delta = 0; + int i, cnt, delta = 0; for (i = 0; i < insn_cnt; i++, insn++) { if (insn->code == (BPF_ALU64 | BPF_MOD | BPF_X) || @@ -11763,9 +9345,8 @@ static int fixup_bpf_calls(struct bpf_verifier_env *env) * the program array. */ prog->cb_access = 1; - if (!allow_tail_call_in_subprogs(env)) - prog->aux->stack_depth = MAX_BPF_STACK; - prog->aux->max_pkt_offset = MAX_PACKET_OFF; + env->prog->aux->stack_depth = MAX_BPF_STACK; + env->prog->aux->max_pkt_offset = MAX_PACKET_OFF; /* mark bpf_tail_call as different opcode to avoid * conditional branch in the interpeter for every normal @@ -11776,28 +9357,6 @@ static int fixup_bpf_calls(struct bpf_verifier_env *env) insn->code = BPF_JMP | BPF_TAIL_CALL; aux = &env->insn_aux_data[i + delta]; - if (env->bpf_capable && !expect_blinding && - prog->jit_requested && - !bpf_map_key_poisoned(aux) && - !bpf_map_ptr_poisoned(aux) && - !bpf_map_ptr_unpriv(aux)) { - struct bpf_jit_poke_descriptor desc = { - .reason = BPF_POKE_REASON_TAIL_CALL, - .tail_call.map = BPF_MAP_PTR(aux->map_ptr_state), - .tail_call.key = bpf_map_key_immediate(aux), - .insn_idx = i + delta, - }; - - ret = bpf_jit_add_poke_descriptor(prog, &desc); - if (ret < 0) { - verbose(env, "adding tail call poke descriptor failed\n"); - return ret; - } - - insn->imm = ret + 1; - continue; - } - if (!bpf_map_ptr_unpriv(aux)) continue; @@ -11812,7 +9371,7 @@ static int fixup_bpf_calls(struct bpf_verifier_env *env) return -EINVAL; } - map_ptr = BPF_MAP_PTR(aux->map_ptr_state); + map_ptr = BPF_MAP_PTR(aux->map_state); insn_buf[0] = BPF_JMP_IMM(BPF_JGE, BPF_REG_3, map_ptr->max_entries, 2); insn_buf[1] = BPF_ALU32_IMM(BPF_AND, BPF_REG_3, @@ -11846,14 +9405,12 @@ static int fixup_bpf_calls(struct bpf_verifier_env *env) if (bpf_map_ptr_poisoned(aux)) goto patch_call_imm; - map_ptr = BPF_MAP_PTR(aux->map_ptr_state); + map_ptr = BPF_MAP_PTR(aux->map_state); ops = map_ptr->ops; if (insn->imm == BPF_FUNC_map_lookup_elem && ops->map_gen_lookup) { cnt = ops->map_gen_lookup(map_ptr, insn_buf); - if (cnt == -EOPNOTSUPP) - goto patch_map_ops_generic; - if (cnt <= 0 || cnt >= ARRAY_SIZE(insn_buf)) { + if (cnt == 0 || cnt >= ARRAY_SIZE(insn_buf)) { verbose(env, "bpf verifier is misconfigured\n"); return -EINVAL; } @@ -11883,7 +9440,7 @@ static int fixup_bpf_calls(struct bpf_verifier_env *env) (int (*)(struct bpf_map *map, void *value))NULL)); BUILD_BUG_ON(!__same_type(ops->map_peek_elem, (int (*)(struct bpf_map *map, void *value))NULL)); -patch_map_ops_generic: + switch (insn->imm) { case BPF_FUNC_map_lookup_elem: insn->imm = BPF_CAST_CALL(ops->map_lookup_elem) - @@ -11914,30 +9471,6 @@ patch_map_ops_generic: goto patch_call_imm; } - if (prog->jit_requested && BITS_PER_LONG == 64 && - insn->imm == BPF_FUNC_jiffies64) { - struct bpf_insn ld_jiffies_addr[2] = { - BPF_LD_IMM64(BPF_REG_0, - (unsigned long)&jiffies), - }; - - insn_buf[0] = ld_jiffies_addr[0]; - insn_buf[1] = ld_jiffies_addr[1]; - insn_buf[2] = BPF_LDX_MEM(BPF_DW, BPF_REG_0, - BPF_REG_0, 0); - cnt = 3; - - new_prog = bpf_patch_insn_data(env, i + delta, insn_buf, - cnt); - if (!new_prog) - return -ENOMEM; - - delta += cnt - 1; - env->prog = prog = new_prog; - insn = new_prog->insnsi + i + delta; - continue; - } - patch_call_imm: fn = env->ops->get_func_proto(insn->imm, env->prog); /* all functions that have prototype and verifier allowed @@ -11952,23 +9485,6 @@ patch_call_imm: insn->imm = fn->func - __bpf_call_base; } - /* Since poke tab is now finalized, publish aux to tracker. */ - for (i = 0; i < prog->aux->size_poke_tab; i++) { - map_ptr = prog->aux->poke_tab[i].tail_call.map; - if (!map_ptr->ops->map_poke_track || - !map_ptr->ops->map_poke_untrack || - !map_ptr->ops->map_poke_run) { - verbose(env, "bpf verifier is misconfigured\n"); - return -EINVAL; - } - - ret = map_ptr->ops->map_poke_track(map_ptr, prog->aux); - if (ret < 0) { - verbose(env, "tracking tail call prog failed\n"); - return ret; - } - } - return 0; } @@ -11984,7 +9500,6 @@ static void free_states(struct bpf_verifier_env *env) kfree(sl); sl = sln; } - env->free_list = NULL; if (!env->explored_states) return; @@ -11998,139 +9513,11 @@ static void free_states(struct bpf_verifier_env *env) kfree(sl); sl = sln; } - env->explored_states[i] = NULL; } + + kvfree(env->explored_states); } -static int do_check_common(struct bpf_verifier_env *env, int subprog) -{ - bool pop_log = !(env->log.level & BPF_LOG_LEVEL2); - struct bpf_verifier_state *state; - struct bpf_reg_state *regs; - int ret, i; - - env->prev_linfo = NULL; - env->pass_cnt++; - - state = kzalloc(sizeof(struct bpf_verifier_state), GFP_KERNEL); - if (!state) - return -ENOMEM; - state->curframe = 0; - state->speculative = false; - state->branches = 1; - state->frame[0] = kzalloc(sizeof(struct bpf_func_state), GFP_KERNEL); - if (!state->frame[0]) { - kfree(state); - return -ENOMEM; - } - env->cur_state = state; - init_func_state(env, state->frame[0], - BPF_MAIN_FUNC /* callsite */, - 0 /* frameno */, - subprog); - - state->first_insn_idx = env->subprog_info[subprog].start; - state->last_insn_idx = -1; - - regs = state->frame[state->curframe]->regs; - if (subprog || env->prog->type == BPF_PROG_TYPE_EXT) { - ret = btf_prepare_func_args(env, subprog, regs); - if (ret) - goto out; - for (i = BPF_REG_1; i <= BPF_REG_5; i++) { - if (regs[i].type == PTR_TO_CTX) - mark_reg_known_zero(env, regs, i); - else if (regs[i].type == SCALAR_VALUE) - mark_reg_unknown(env, regs, i); - } - } else { - /* 1st arg to a function */ - regs[BPF_REG_1].type = PTR_TO_CTX; - mark_reg_known_zero(env, regs, BPF_REG_1); - ret = btf_check_func_arg_match(env, subprog, regs); - if (ret == -EFAULT) - /* unlikely verifier bug. abort. - * ret == 0 and ret < 0 are sadly acceptable for - * main() function due to backward compatibility. - * Like socket filter program may be written as: - * int bpf_prog(struct pt_regs *ctx) - * and never dereference that ctx in the program. - * 'struct pt_regs' is a type mismatch for socket - * filter that should be using 'struct __sk_buff'. - */ - goto out; - } - - ret = do_check(env); -out: - /* check for NULL is necessary, since cur_state can be freed inside - * do_check() under memory pressure. - */ - if (env->cur_state) { - free_verifier_state(env->cur_state, true); - env->cur_state = NULL; - } - while (!pop_stack(env, NULL, NULL, false)); - if (!ret && pop_log) - bpf_vlog_reset(&env->log, 0); - free_states(env); - return ret; -} - -/* Verify all global functions in a BPF program one by one based on their BTF. - * All global functions must pass verification. Otherwise the whole program is rejected. - * Consider: - * int bar(int); - * int foo(int f) - * { - * return bar(f); - * } - * int bar(int b) - * { - * ... - * } - * foo() will be verified first for R1=any_scalar_value. During verification it - * will be assumed that bar() already verified successfully and call to bar() - * from foo() will be checked for type match only. Later bar() will be verified - * independently to check that it's safe for R1=any_scalar_value. - */ -static int do_check_subprogs(struct bpf_verifier_env *env) -{ - struct bpf_prog_aux *aux = env->prog->aux; - int i, ret; - - if (!aux->func_info) - return 0; - - for (i = 1; i < env->subprog_cnt; i++) { - if (aux->func_info_aux[i].linkage != BTF_FUNC_GLOBAL) - continue; - env->insn_idx = env->subprog_info[i].start; - WARN_ON_ONCE(env->insn_idx == 0); - ret = do_check_common(env, i); - if (ret) { - return ret; - } else if (env->log.level & BPF_LOG_LEVEL) { - verbose(env, - "Func#%d is safe for any args that match its prototype\n", - i); - } - } - return 0; -} - -static int do_check_main(struct bpf_verifier_env *env) -{ - int ret; - - env->insn_idx = 0; - ret = do_check_common(env, 0); - if (!ret) - env->prog->aux->stack_depth = env->subprog_info[0].stack_depth; - return ret; -} - - static void print_verification_stats(struct bpf_verifier_env *env) { int i; @@ -12155,419 +9542,6 @@ static void print_verification_stats(struct bpf_verifier_env *env) env->peak_states, env->longest_mark_read_walk); } -static int check_struct_ops_btf_id(struct bpf_verifier_env *env) -{ - const struct btf_type *t, *func_proto; - const struct bpf_struct_ops *st_ops; - const struct btf_member *member; - struct bpf_prog *prog = env->prog; - u32 btf_id, member_idx; - const char *mname; - - if (!prog->gpl_compatible) { - verbose(env, "struct ops programs must have a GPL compatible license\n"); - return -EINVAL; - } - - btf_id = prog->aux->attach_btf_id; - st_ops = bpf_struct_ops_find(btf_id); - if (!st_ops) { - verbose(env, "attach_btf_id %u is not a supported struct\n", - btf_id); - return -ENOTSUPP; - } - - t = st_ops->type; - member_idx = prog->expected_attach_type; - if (member_idx >= btf_type_vlen(t)) { - verbose(env, "attach to invalid member idx %u of struct %s\n", - member_idx, st_ops->name); - return -EINVAL; - } - - member = &btf_type_member(t)[member_idx]; - mname = btf_name_by_offset(btf_vmlinux, member->name_off); - func_proto = btf_type_resolve_func_ptr(btf_vmlinux, member->type, - NULL); - if (!func_proto) { - verbose(env, "attach to invalid member %s(@idx %u) of struct %s\n", - mname, member_idx, st_ops->name); - return -EINVAL; - } - - if (st_ops->check_member) { - int err = st_ops->check_member(t, member); - - if (err) { - verbose(env, "attach to unsupported member %s of struct %s\n", - mname, st_ops->name); - return err; - } - } - - prog->aux->attach_func_proto = func_proto; - prog->aux->attach_func_name = mname; - env->ops = st_ops->verifier_ops; - - return 0; -} -#define SECURITY_PREFIX "security_" - -static int check_attach_modify_return(unsigned long addr, const char *func_name) -{ - if (within_error_injection_list(addr) || - !strncmp(SECURITY_PREFIX, func_name, sizeof(SECURITY_PREFIX) - 1)) - return 0; - - return -EINVAL; -} - -/* non exhaustive list of sleepable bpf_lsm_*() functions */ -BTF_SET_START(btf_sleepable_lsm_hooks) -#ifdef CONFIG_BPF_LSM -BTF_ID(func, bpf_lsm_bprm_committed_creds) -#else -BTF_ID_UNUSED -#endif -BTF_SET_END(btf_sleepable_lsm_hooks) - -static int check_sleepable_lsm_hook(u32 btf_id) -{ - return btf_id_set_contains(&btf_sleepable_lsm_hooks, btf_id); -} - -/* list of non-sleepable functions that are otherwise on - * ALLOW_ERROR_INJECTION list - */ -BTF_SET_START(btf_non_sleepable_error_inject) -/* Three functions below can be called from sleepable and non-sleepable context. - * Assume non-sleepable from bpf safety point of view. - */ -BTF_ID(func, __add_to_page_cache_locked) -BTF_ID(func, should_fail_alloc_page) -BTF_ID(func, should_failslab) -BTF_SET_END(btf_non_sleepable_error_inject) - -static int check_non_sleepable_error_inject(u32 btf_id) -{ - return btf_id_set_contains(&btf_non_sleepable_error_inject, btf_id); -} - -int bpf_check_attach_target(struct bpf_verifier_log *log, - const struct bpf_prog *prog, - const struct bpf_prog *tgt_prog, - u32 btf_id, - struct bpf_attach_target_info *tgt_info) -{ - bool prog_extension = prog->type == BPF_PROG_TYPE_EXT; - const char prefix[] = "btf_trace_"; - int ret = 0, subprog = -1, i; - const struct btf_type *t; - bool conservative = true; - const char *tname; - struct btf *btf; - long addr = 0; - - if (!btf_id) { - bpf_log(log, "Tracing programs must provide btf_id\n"); - return -EINVAL; - } - btf = tgt_prog ? tgt_prog->aux->btf : btf_vmlinux; - if (!btf) { - bpf_log(log, - "FENTRY/FEXIT program can only be attached to another program annotated with BTF\n"); - return -EINVAL; - } - t = btf_type_by_id(btf, btf_id); - if (!t) { - bpf_log(log, "attach_btf_id %u is invalid\n", btf_id); - return -EINVAL; - } - tname = btf_name_by_offset(btf, t->name_off); - if (!tname) { - bpf_log(log, "attach_btf_id %u doesn't have a name\n", btf_id); - return -EINVAL; - } - if (tgt_prog) { - struct bpf_prog_aux *aux = tgt_prog->aux; - - for (i = 0; i < aux->func_info_cnt; i++) - if (aux->func_info[i].type_id == btf_id) { - subprog = i; - break; - } - if (subprog == -1) { - bpf_log(log, "Subprog %s doesn't exist\n", tname); - return -EINVAL; - } - conservative = aux->func_info_aux[subprog].unreliable; - if (prog_extension) { - if (conservative) { - bpf_log(log, - "Cannot replace static functions\n"); - return -EINVAL; - } - if (!prog->jit_requested) { - bpf_log(log, - "Extension programs should be JITed\n"); - return -EINVAL; - } - } - if (!tgt_prog->jited) { - bpf_log(log, "Can attach to only JITed progs\n"); - return -EINVAL; - } - if (tgt_prog->type == prog->type) { - /* Cannot fentry/fexit another fentry/fexit program. - * Cannot attach program extension to another extension. - * It's ok to attach fentry/fexit to extension program. - */ - bpf_log(log, "Cannot recursively attach\n"); - return -EINVAL; - } - if (tgt_prog->type == BPF_PROG_TYPE_TRACING && - prog_extension && - (tgt_prog->expected_attach_type == BPF_TRACE_FENTRY || - tgt_prog->expected_attach_type == BPF_TRACE_FEXIT)) { - /* Program extensions can extend all program types - * except fentry/fexit. The reason is the following. - * The fentry/fexit programs are used for performance - * analysis, stats and can be attached to any program - * type except themselves. When extension program is - * replacing XDP function it is necessary to allow - * performance analysis of all functions. Both original - * XDP program and its program extension. Hence - * attaching fentry/fexit to BPF_PROG_TYPE_EXT is - * allowed. If extending of fentry/fexit was allowed it - * would be possible to create long call chain - * fentry->extension->fentry->extension beyond - * reasonable stack size. Hence extending fentry is not - * allowed. - */ - bpf_log(log, "Cannot extend fentry/fexit\n"); - return -EINVAL; - } - } else { - if (prog_extension) { - bpf_log(log, "Cannot replace kernel functions\n"); - return -EINVAL; - } - } - - switch (prog->expected_attach_type) { - case BPF_TRACE_RAW_TP: - if (tgt_prog) { - bpf_log(log, - "Only FENTRY/FEXIT progs are attachable to another BPF prog\n"); - return -EINVAL; - } - if (!btf_type_is_typedef(t)) { - bpf_log(log, "attach_btf_id %u is not a typedef\n", - btf_id); - return -EINVAL; - } - if (strncmp(prefix, tname, sizeof(prefix) - 1)) { - bpf_log(log, "attach_btf_id %u points to wrong type name %s\n", - btf_id, tname); - return -EINVAL; - } - tname += sizeof(prefix) - 1; - t = btf_type_by_id(btf, t->type); - if (!btf_type_is_ptr(t)) - /* should never happen in valid vmlinux build */ - return -EINVAL; - t = btf_type_by_id(btf, t->type); - if (!btf_type_is_func_proto(t)) - /* should never happen in valid vmlinux build */ - return -EINVAL; - - break; - case BPF_TRACE_ITER: - if (!btf_type_is_func(t)) { - bpf_log(log, "attach_btf_id %u is not a function\n", - btf_id); - return -EINVAL; - } - t = btf_type_by_id(btf, t->type); - if (!btf_type_is_func_proto(t)) - return -EINVAL; - ret = btf_distill_func_proto(log, btf, t, tname, &tgt_info->fmodel); - if (ret) - return ret; - break; - default: - if (!prog_extension) - return -EINVAL; - fallthrough; - case BPF_MODIFY_RETURN: - case BPF_LSM_MAC: - case BPF_TRACE_FENTRY: - case BPF_TRACE_FEXIT: - if (!btf_type_is_func(t)) { - bpf_log(log, "attach_btf_id %u is not a function\n", - btf_id); - return -EINVAL; - } - if (prog_extension && - btf_check_type_match(log, prog, btf, t)) - return -EINVAL; - t = btf_type_by_id(btf, t->type); - if (!btf_type_is_func_proto(t)) - return -EINVAL; - - if ((prog->aux->saved_dst_prog_type || prog->aux->saved_dst_attach_type) && - (!tgt_prog || prog->aux->saved_dst_prog_type != tgt_prog->type || - prog->aux->saved_dst_attach_type != tgt_prog->expected_attach_type)) - return -EINVAL; - - if (tgt_prog && conservative) - t = NULL; - - ret = btf_distill_func_proto(log, btf, t, tname, &tgt_info->fmodel); - if (ret < 0) - return ret; - - if (tgt_prog) { - if (subprog == 0) - addr = (long) tgt_prog->bpf_func; - else - addr = (long) tgt_prog->aux->func[subprog]->bpf_func; - } else { - addr = kallsyms_lookup_name(tname); - if (!addr) { - bpf_log(log, - "The address of function %s cannot be found\n", - tname); - return -ENOENT; - } - } - - if (prog->aux->sleepable) { - ret = -EINVAL; - switch (prog->type) { - case BPF_PROG_TYPE_TRACING: - /* fentry/fexit/fmod_ret progs can be sleepable only if they are - * attached to ALLOW_ERROR_INJECTION and are not in denylist. - */ - if (!check_non_sleepable_error_inject(btf_id) && - within_error_injection_list(addr)) - ret = 0; - break; - case BPF_PROG_TYPE_LSM: - /* LSM progs check that they are attached to bpf_lsm_*() funcs. - * Only some of them are sleepable. - */ - if (check_sleepable_lsm_hook(btf_id)) - ret = 0; - break; - default: - break; - } - if (ret) { - bpf_log(log, "%s is not sleepable\n", tname); - return ret; - } - } else if (prog->expected_attach_type == BPF_MODIFY_RETURN) { - if (tgt_prog) { - bpf_log(log, "can't modify return codes of BPF programs\n"); - return -EINVAL; - } - ret = check_attach_modify_return(addr, tname); - if (ret) { - bpf_log(log, "%s() is not modifiable\n", tname); - return ret; - } - } - - break; - } - tgt_info->tgt_addr = addr; - tgt_info->tgt_name = tname; - tgt_info->tgt_type = t; - return 0; -} - -static int check_attach_btf_id(struct bpf_verifier_env *env) -{ - struct bpf_prog *prog = env->prog; - struct bpf_prog *tgt_prog = prog->aux->dst_prog; - struct bpf_attach_target_info tgt_info = {}; - u32 btf_id = prog->aux->attach_btf_id; - struct bpf_trampoline *tr; - int ret; - u64 key; - - if (prog->aux->sleepable && prog->type != BPF_PROG_TYPE_TRACING && - prog->type != BPF_PROG_TYPE_LSM) { - verbose(env, "Only fentry/fexit/fmod_ret and lsm programs can be sleepable\n"); - return -EINVAL; - } - - if (prog->type == BPF_PROG_TYPE_STRUCT_OPS) - return check_struct_ops_btf_id(env); - - if (prog->type != BPF_PROG_TYPE_TRACING && - prog->type != BPF_PROG_TYPE_LSM && - prog->type != BPF_PROG_TYPE_EXT) - return 0; - - ret = bpf_check_attach_target(&env->log, prog, tgt_prog, btf_id, &tgt_info); - if (ret) - return ret; - - if (tgt_prog && prog->type == BPF_PROG_TYPE_EXT) { - /* to make freplace equivalent to their targets, they need to - * inherit env->ops and expected_attach_type for the rest of the - * verification - */ - env->ops = bpf_verifier_ops[tgt_prog->type]; - prog->expected_attach_type = tgt_prog->expected_attach_type; - } - - /* store info about the attachment target that will be used later */ - prog->aux->attach_func_proto = tgt_info.tgt_type; - prog->aux->attach_func_name = tgt_info.tgt_name; - - if (tgt_prog) { - prog->aux->saved_dst_prog_type = tgt_prog->type; - prog->aux->saved_dst_attach_type = tgt_prog->expected_attach_type; - } - - if (prog->expected_attach_type == BPF_TRACE_RAW_TP) { - prog->aux->attach_btf_trace = true; - return 0; - } else if (prog->expected_attach_type == BPF_TRACE_ITER) { - if (!bpf_iter_prog_supported(prog)) - return -EINVAL; - return 0; - } - - if (prog->type == BPF_PROG_TYPE_LSM) { - ret = bpf_lsm_verify_prog(&env->log, prog); - if (ret < 0) - return ret; - } - - key = bpf_trampoline_compute_key(tgt_prog, btf_id); - tr = bpf_trampoline_get(key, &tgt_info); - if (!tr) - return -ENOMEM; - - prog->aux->dst_trampoline = tr; - return 0; -} - -struct btf *bpf_get_btf_vmlinux(void) -{ - if (!btf_vmlinux && IS_ENABLED(CONFIG_DEBUG_INFO_BTF)) { - mutex_lock(&bpf_verifier_lock); - if (!btf_vmlinux) - btf_vmlinux = btf_parse_vmlinux(); - mutex_unlock(&bpf_verifier_lock); - } - return btf_vmlinux; -} - int bpf_check(struct bpf_prog **prog, union bpf_attr *attr, union bpf_attr __user *uattr) { @@ -12599,9 +9573,7 @@ int bpf_check(struct bpf_prog **prog, union bpf_attr *attr, env->insn_aux_data[i].orig_idx = i; env->prog = *prog; env->ops = bpf_verifier_ops[env->prog->type]; - is_priv = bpf_capable(); - - bpf_get_btf_vmlinux(); + is_priv = capable(CAP_SYS_ADMIN); /* grab the mutex to protect few globals used by verifier */ if (!is_priv) @@ -12615,18 +9587,11 @@ int bpf_check(struct bpf_prog **prog, union bpf_attr *attr, log->ubuf = (char __user *) (unsigned long) attr->log_buf; log->len_total = attr->log_size; + ret = -EINVAL; /* log attributes have to be sane */ - if (!bpf_verifier_log_attr_valid(log)) { - ret = -EINVAL; + if (log->len_total < 128 || log->len_total > UINT_MAX >> 2 || + !log->level || !log->ubuf || log->level & ~BPF_LOG_MASK) goto err_unlock; - } - } - - if (IS_ERR(btf_vmlinux)) { - /* Either gcc or pahole or kernel are broken. */ - verbose(env, "in-kernel BTF is malformed\n"); - ret = PTR_ERR(btf_vmlinux); - goto skip_full_check; } env->strict_alignment = !!(attr->prog_flags & BPF_F_STRICT_ALIGNMENT); @@ -12635,16 +9600,21 @@ int bpf_check(struct bpf_prog **prog, union bpf_attr *attr, if (attr->prog_flags & BPF_F_ANY_ALIGNMENT) env->strict_alignment = false; - env->allow_ptr_leaks = bpf_allow_ptr_leaks(); - env->allow_uninit_stack = bpf_allow_uninit_stack(); - env->allow_ptr_to_map_access = bpf_allow_ptr_to_map_access(); - env->bypass_spec_v1 = bpf_bypass_spec_v1(); - env->bypass_spec_v4 = bpf_bypass_spec_v4(); - env->bpf_capable = bpf_capable(); + env->allow_ptr_leaks = is_priv; if (is_priv) env->test_state_freq = attr->prog_flags & BPF_F_TEST_STATE_FREQ; + ret = replace_map_fd_with_map_ptr(env); + if (ret < 0) + goto skip_full_check; + + if (bpf_prog_is_dev_bound(env->prog->aux)) { + ret = bpf_prog_offload_verifier_prep(env->prog); + if (ret) + goto skip_full_check; + } + env->explored_states = kvcalloc(state_htab_size(env), sizeof(struct bpf_verifier_state_list *), GFP_USER); @@ -12660,32 +9630,22 @@ int bpf_check(struct bpf_prog **prog, union bpf_attr *attr, if (ret < 0) goto skip_full_check; - ret = check_attach_btf_id(env); - if (ret) - goto skip_full_check; - - ret = resolve_pseudo_ldimm64(env); - if (ret < 0) - goto skip_full_check; - - if (bpf_prog_is_dev_bound(env->prog->aux)) { - ret = bpf_prog_offload_verifier_prep(env->prog); - if (ret) - goto skip_full_check; - } - ret = check_cfg(env); if (ret < 0) goto skip_full_check; - ret = do_check_subprogs(env); - ret = ret ?: do_check_main(env); + ret = do_check(env); + if (env->cur_state) { + free_verifier_state(env->cur_state, true); + env->cur_state = NULL; + } if (ret == 0 && bpf_prog_is_dev_bound(env->prog->aux)) ret = bpf_prog_offload_finalize(env); skip_full_check: - kvfree(env->explored_states); + while (!pop_stack(env, NULL, NULL)); + free_states(env); if (ret == 0) ret = check_max_stack_depth(env); @@ -12768,13 +9728,6 @@ err_release_maps: * them now. Otherwise free_used_maps() will release them. */ release_maps(env); - - /* extension progs temporarily inherit the attach_type of their targets - for verification purposes, so set it back to zero before returning - */ - if (env->prog->type == BPF_PROG_TYPE_EXT) - env->prog->expected_attach_type = 0; - *prog = env->prog; err_unlock: if (!is_priv) diff --git a/net/xdp/xskmap.c b/kernel/bpf/xskmap.c similarity index 71% rename from net/xdp/xskmap.c rename to kernel/bpf/xskmap.c index 3bf8ac169604..82a1ffe15dfa 100644 --- a/net/xdp/xskmap.c +++ b/kernel/bpf/xskmap.c @@ -9,12 +9,19 @@ #include #include -#include "xsk.h" +struct xsk_map { + struct bpf_map map; + struct xdp_sock **xsk_map; + struct list_head __percpu *flush_list; + spinlock_t lock; /* Synchronize map updates */ +}; int xsk_map_inc(struct xsk_map *map) { - bpf_map_inc(&map->map); - return 0; + struct bpf_map *m = &map->map; + + m = bpf_map_inc(m, false); + return PTR_ERR_OR_ZERO(m); } void xsk_map_put(struct xsk_map *map) @@ -73,10 +80,9 @@ static void xsk_map_sock_delete(struct xdp_sock *xs, static struct bpf_map *xsk_map_alloc(union bpf_attr *attr) { - struct bpf_map_memory mem; - int err, numa_node; struct xsk_map *m; - u64 size; + int cpu, err; + u64 cost; if (!capable(CAP_NET_ADMIN)) return ERR_PTR(-EPERM); @@ -86,24 +92,44 @@ static struct bpf_map *xsk_map_alloc(union bpf_attr *attr) attr->map_flags & ~(BPF_F_NUMA_NODE | BPF_F_RDONLY | BPF_F_WRONLY)) return ERR_PTR(-EINVAL); - numa_node = bpf_map_attr_numa_node(attr); - size = struct_size(m, xsk_map, attr->max_entries); - - err = bpf_map_charge_init(&mem, size); - if (err < 0) - return ERR_PTR(err); - - m = bpf_map_area_alloc(size, numa_node); - if (!m) { - bpf_map_charge_finish(&mem); + m = kzalloc(sizeof(*m), GFP_USER); + if (!m) return ERR_PTR(-ENOMEM); - } bpf_map_init_from_attr(&m->map, attr); - bpf_map_charge_move(&m->map.memory, &mem); spin_lock_init(&m->lock); + cost = (u64)m->map.max_entries * sizeof(struct xdp_sock *); + cost += sizeof(struct list_head) * num_possible_cpus(); + + /* Notice returns -EPERM on if map size is larger than memlock limit */ + err = bpf_map_charge_init(&m->map.memory, cost); + if (err) + goto free_m; + + err = -ENOMEM; + + m->flush_list = alloc_percpu(struct list_head); + if (!m->flush_list) + goto free_charge; + + for_each_possible_cpu(cpu) + INIT_LIST_HEAD(per_cpu_ptr(m->flush_list, cpu)); + + m->xsk_map = bpf_map_area_alloc(m->map.max_entries * + sizeof(struct xdp_sock *), + m->map.numa_node); + if (!m->xsk_map) + goto free_percpu; return &m->map; + +free_percpu: + free_percpu(m->flush_list); +free_charge: + bpf_map_charge_finish(&m->map.memory); +free_m: + kfree(m); + return ERR_PTR(err); } static void xsk_map_free(struct bpf_map *map) @@ -112,7 +138,9 @@ static void xsk_map_free(struct bpf_map *map) bpf_clear_redirect_map(map); synchronize_net(); - bpf_map_area_free(m); + free_percpu(m->flush_list); + bpf_map_area_free(m->xsk_map); + kfree(m); } static int xsk_map_get_next_key(struct bpf_map *map, void *key, void *next_key) @@ -132,20 +160,45 @@ static int xsk_map_get_next_key(struct bpf_map *map, void *key, void *next_key) return 0; } -static int xsk_map_gen_lookup(struct bpf_map *map, struct bpf_insn *insn_buf) +struct xdp_sock *__xsk_map_lookup_elem(struct bpf_map *map, u32 key) { - const int ret = BPF_REG_0, mp = BPF_REG_1, index = BPF_REG_2; - struct bpf_insn *insn = insn_buf; + struct xsk_map *m = container_of(map, struct xsk_map, map); + struct xdp_sock *xs; - *insn++ = BPF_LDX_MEM(BPF_W, ret, index, 0); - *insn++ = BPF_JMP_IMM(BPF_JGE, ret, map->max_entries, 5); - *insn++ = BPF_ALU64_IMM(BPF_LSH, ret, ilog2(sizeof(struct xsk_sock *))); - *insn++ = BPF_ALU64_IMM(BPF_ADD, mp, offsetof(struct xsk_map, xsk_map)); - *insn++ = BPF_ALU64_REG(BPF_ADD, ret, mp); - *insn++ = BPF_LDX_MEM(BPF_SIZEOF(struct xsk_sock *), ret, ret, 0); - *insn++ = BPF_JMP_IMM(BPF_JA, 0, 0, 1); - *insn++ = BPF_MOV64_IMM(ret, 0); - return insn - insn_buf; + if (key >= map->max_entries) + return NULL; + + xs = READ_ONCE(m->xsk_map[key]); + return xs; +} + +int __xsk_map_redirect(struct bpf_map *map, struct xdp_buff *xdp, + struct xdp_sock *xs) +{ + struct xsk_map *m = container_of(map, struct xsk_map, map); + struct list_head *flush_list = this_cpu_ptr(m->flush_list); + int err; + + err = xsk_rcv(xs, xdp); + if (err) + return err; + + if (!xs->flush_node.prev) + list_add(&xs->flush_node, flush_list); + + return 0; +} + +void __xsk_map_flush(struct bpf_map *map) +{ + struct xsk_map *m = container_of(map, struct xsk_map, map); + struct list_head *flush_list = this_cpu_ptr(m->flush_list); + struct xdp_sock *xs, *tmp; + + list_for_each_entry_safe(xs, tmp, flush_list, flush_node) { + xsk_flush(xs); + __list_del_clearprev(&xs->flush_node); + } } static void *xsk_map_lookup_elem(struct bpf_map *map, void *key) @@ -254,25 +307,13 @@ void xsk_map_try_sock_delete(struct xsk_map *map, struct xdp_sock *xs, spin_unlock_bh(&map->lock); } -static bool xsk_map_meta_equal(const struct bpf_map *meta0, - const struct bpf_map *meta1) -{ - return meta0->max_entries == meta1->max_entries && - bpf_map_meta_equal(meta0, meta1); -} - -static int xsk_map_btf_id; const struct bpf_map_ops xsk_map_ops = { - .map_meta_equal = xsk_map_meta_equal, .map_alloc = xsk_map_alloc, .map_free = xsk_map_free, .map_get_next_key = xsk_map_get_next_key, .map_lookup_elem = xsk_map_lookup_elem, - .map_gen_lookup = xsk_map_gen_lookup, .map_lookup_elem_sys_only = xsk_map_lookup_elem_sys_only, .map_update_elem = xsk_map_update_elem, .map_delete_elem = xsk_map_delete_elem, .map_check_btf = map_check_no_btf, - .map_btf_name = "xsk_map", - .map_btf_id = &xsk_map_btf_id, }; diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c index 012deb2fb04a..85b8b0dbd88a 100644 --- a/kernel/cgroup/cgroup.c +++ b/kernel/cgroup/cgroup.c @@ -1356,7 +1356,10 @@ static void cgroup_exit_root_id(struct cgroup_root *root) void cgroup_free_root(struct cgroup_root *root) { - kfree(root); + if (root) { + idr_destroy(&root->cgroup_idr); + kfree(root); + } } static void cgroup_destroy_root(struct cgroup_root *root) @@ -1897,14 +1900,12 @@ int cgroup_show_path(struct seq_file *sf, struct kernfs_node *kf_node, enum cgroup2_param { Opt_nsdelegate, Opt_memory_localevents, - Opt_memory_recursiveprot, nr__cgroup2_params }; static const struct fs_parameter_spec cgroup2_param_specs[] = { fsparam_flag("nsdelegate", Opt_nsdelegate), fsparam_flag("memory_localevents", Opt_memory_localevents), - fsparam_flag("memory_recursiveprot", Opt_memory_recursiveprot), {} }; @@ -1930,9 +1931,6 @@ static int cgroup2_parse_param(struct fs_context *fc, struct fs_parameter *param case Opt_memory_localevents: ctx->flags |= CGRP_ROOT_MEMORY_LOCAL_EVENTS; return 0; - case Opt_memory_recursiveprot: - ctx->flags |= CGRP_ROOT_MEMORY_RECURSIVE_PROT; - return 0; } return -EINVAL; } @@ -1949,11 +1947,6 @@ static void apply_cgroup_root_flags(unsigned int root_flags) cgrp_dfl_root.flags |= CGRP_ROOT_MEMORY_LOCAL_EVENTS; else cgrp_dfl_root.flags &= ~CGRP_ROOT_MEMORY_LOCAL_EVENTS; - - if (root_flags & CGRP_ROOT_MEMORY_RECURSIVE_PROT) - cgrp_dfl_root.flags |= CGRP_ROOT_MEMORY_RECURSIVE_PROT; - else - cgrp_dfl_root.flags &= ~CGRP_ROOT_MEMORY_RECURSIVE_PROT; } } @@ -1963,8 +1956,6 @@ static int cgroup_show_options(struct seq_file *seq, struct kernfs_root *kf_root seq_puts(seq, ",nsdelegate"); if (cgrp_dfl_root.flags & CGRP_ROOT_MEMORY_LOCAL_EVENTS) seq_puts(seq, ",memory_localevents"); - if (cgrp_dfl_root.flags & CGRP_ROOT_MEMORY_RECURSIVE_PROT) - seq_puts(seq, ",memory_recursiveprot"); return 0; } @@ -2069,6 +2060,7 @@ void init_cgroup_root(struct cgroup_fs_context *ctx) atomic_set(&root->nr_cgrps, 1); cgrp->root = root; init_cgroup_housekeeping(cgrp); + idr_init(&root->cgroup_idr); root->flags = ctx->flags; if (ctx->release_agent) @@ -2089,6 +2081,12 @@ int cgroup_setup_root(struct cgroup_root *root, u16 ss_mask) lockdep_assert_held(&cgroup_mutex); + ret = cgroup_idr_alloc(&root->cgroup_idr, root_cgrp, 1, 2, GFP_KERNEL); + if (ret < 0) + goto out; + root_cgrp->id = ret; + root_cgrp->ancestor_ids[0] = ret; + ret = percpu_ref_init(&root_cgrp->self.refcnt, css_release, 0, GFP_KERNEL); if (ret) @@ -2114,16 +2112,13 @@ int cgroup_setup_root(struct cgroup_root *root, u16 ss_mask) root->kf_root = kernfs_create_root(kf_sops, KERNFS_ROOT_CREATE_DEACTIVATED | - KERNFS_ROOT_SUPPORT_EXPORTOP | - KERNFS_ROOT_SUPPORT_USER_XATTR, + KERNFS_ROOT_SUPPORT_EXPORTOP, root_cgrp); if (IS_ERR(root->kf_root)) { ret = PTR_ERR(root->kf_root); goto exit_root_id; } root_cgrp->kn = root->kf_root->kn; - WARN_ON_ONCE(cgroup_ino(root_cgrp) != 1); - root_cgrp->ancestor_ids[0] = cgroup_id(root_cgrp); ret = css_populate_dir(&root_cgrp->self); if (ret) @@ -2133,10 +2128,8 @@ int cgroup_setup_root(struct cgroup_root *root, u16 ss_mask) if (ret) goto destroy_root; - if (root == &cgrp_dfl_root) { - ret = cgroup_bpf_inherit(root_cgrp); - WARN_ON_ONCE(ret); - } + ret = cgroup_bpf_inherit(root_cgrp); + WARN_ON_ONCE(ret); trace_cgroup_setup_root(root); @@ -2163,6 +2156,7 @@ int cgroup_setup_root(struct cgroup_root *root, u16 ss_mask) BUG_ON(!list_empty(&root_cgrp->self.children)); BUG_ON(atomic_read(&root->nr_cgrps) != 1); + kernfs_activate(root_cgrp->kn); ret = 0; goto out; @@ -3764,22 +3758,22 @@ static int cpu_stat_show(struct seq_file *seq, void *v) #ifdef CONFIG_PSI static int cgroup_io_pressure_show(struct seq_file *seq, void *v) { - struct cgroup *cgrp = seq_css(seq)->cgroup; - struct psi_group *psi = cgroup_id(cgrp) == 1 ? &psi_system : &cgrp->psi; + struct cgroup *cgroup = seq_css(seq)->cgroup; + struct psi_group *psi = cgroup->id == 1 ? &psi_system : &cgroup->psi; return psi_show(seq, psi, PSI_IO); } static int cgroup_memory_pressure_show(struct seq_file *seq, void *v) { - struct cgroup *cgrp = seq_css(seq)->cgroup; - struct psi_group *psi = cgroup_id(cgrp) == 1 ? &psi_system : &cgrp->psi; + struct cgroup *cgroup = seq_css(seq)->cgroup; + struct psi_group *psi = cgroup->id == 1 ? &psi_system : &cgroup->psi; return psi_show(seq, psi, PSI_MEM); } static int cgroup_cpu_pressure_show(struct seq_file *seq, void *v) { - struct cgroup *cgrp = seq_css(seq)->cgroup; - struct psi_group *psi = cgroup_id(cgrp) == 1 ? &psi_system : &cgrp->psi; + struct cgroup *cgroup = seq_css(seq)->cgroup; + struct psi_group *psi = cgroup->id == 1 ? &psi_system : &cgroup->psi; return psi_show(seq, psi, PSI_CPU); } @@ -5282,6 +5276,9 @@ static void css_release_work_fn(struct work_struct *work) tcgrp->nr_dying_descendants--; spin_unlock_irq(&css_set_lock); + cgroup_idr_remove(&cgrp->root->cgroup_idr, cgrp->id); + cgrp->id = -1; + /* * There are two control paths which try to determine * cgroup from dentry without going through kernfs - @@ -5446,12 +5443,10 @@ err_free_css: * it isn't associated with its kernfs_node and doesn't have the control * mask applied. */ -static struct cgroup *cgroup_create(struct cgroup *parent, const char *name, - umode_t mode) +static struct cgroup *cgroup_create(struct cgroup *parent) { struct cgroup_root *root = parent->root; struct cgroup *cgrp, *tcgrp; - struct kernfs_node *kn; int level = parent->level + 1; int ret; @@ -5471,13 +5466,15 @@ static struct cgroup *cgroup_create(struct cgroup *parent, const char *name, goto out_cancel_ref; } - /* create the directory */ - kn = kernfs_create_dir(parent->kn, name, mode, cgrp); - if (IS_ERR(kn)) { - ret = PTR_ERR(kn); + /* + * Temporarily set the pointer to NULL, so idr_find() won't return + * a half-baked cgroup. + */ + cgrp->id = cgroup_idr_alloc(&root->cgroup_idr, NULL, 2, 0, GFP_KERNEL); + if (cgrp->id < 0) { + ret = -ENOMEM; goto out_stat_exit; } - cgrp->kn = kn; init_cgroup_housekeeping(cgrp); @@ -5487,13 +5484,11 @@ static struct cgroup *cgroup_create(struct cgroup *parent, const char *name, ret = psi_cgroup_alloc(cgrp); if (ret) - goto out_kernfs_remove; + goto out_idr_free; - if (cgrp->root == &cgrp_dfl_root) { - ret = cgroup_bpf_inherit(cgrp); - if (ret) - goto out_psi_free; - } + ret = cgroup_bpf_inherit(cgrp); + if (ret) + goto out_psi_free; /* * New cgroup inherits effective freeze counter, and @@ -5513,7 +5508,7 @@ static struct cgroup *cgroup_create(struct cgroup *parent, const char *name, spin_lock_irq(&css_set_lock); for (tcgrp = cgrp; tcgrp; tcgrp = cgroup_parent(tcgrp)) { - cgrp->ancestor_ids[tcgrp->level] = cgroup_id(tcgrp); + cgrp->ancestor_ids[tcgrp->level] = tcgrp->id; if (tcgrp != cgrp) { tcgrp->nr_descendants++; @@ -5542,6 +5537,12 @@ static struct cgroup *cgroup_create(struct cgroup *parent, const char *name, atomic_inc(&root->nr_cgrps); cgroup_get_live(parent); + /* + * @cgrp is now fully operational. If something fails after this + * point, it'll be released via the normal destruction path. + */ + cgroup_idr_replace(&root->cgroup_idr, cgrp, cgrp->id); + /* * On the default hierarchy, a child doesn't automatically inherit * subtree_control from the parent. Each is configured manually. @@ -5555,8 +5556,8 @@ static struct cgroup *cgroup_create(struct cgroup *parent, const char *name, out_psi_free: psi_cgroup_free(cgrp); -out_kernfs_remove: - kernfs_remove(cgrp->kn); +out_idr_free: + cgroup_idr_remove(&root->cgroup_idr, cgrp->id); out_stat_exit: if (cgroup_on_dfl(parent)) cgroup_rstat_exit(cgrp); @@ -5593,6 +5594,7 @@ fail: int cgroup_mkdir(struct kernfs_node *parent_kn, const char *name, umode_t mode) { struct cgroup *parent, *cgrp; + struct kernfs_node *kn; int ret; /* do not accept '\n' to prevent making /proc//cgroup unparsable */ @@ -5608,19 +5610,27 @@ int cgroup_mkdir(struct kernfs_node *parent_kn, const char *name, umode_t mode) goto out_unlock; } - cgrp = cgroup_create(parent, name, mode); + cgrp = cgroup_create(parent); if (IS_ERR(cgrp)) { ret = PTR_ERR(cgrp); goto out_unlock; } + /* create the directory */ + kn = kernfs_create_dir(parent->kn, name, mode, cgrp); + if (IS_ERR(kn)) { + ret = PTR_ERR(kn); + goto out_destroy; + } + cgrp->kn = kn; + /* * This extra ref will be put in cgroup_free_fn() and guarantees * that @cgrp->kn is always accessible. */ - kernfs_get(cgrp->kn); + kernfs_get(kn); - ret = cgroup_kn_set_ugid(cgrp->kn); + ret = cgroup_kn_set_ugid(kn); if (ret) goto out_destroy; @@ -5635,7 +5645,7 @@ int cgroup_mkdir(struct kernfs_node *parent_kn, const char *name, umode_t mode) TRACE_CGROUP_PATH(mkdir, cgrp); /* let's create and online css's */ - kernfs_activate(cgrp->kn); + kernfs_activate(kn); ret = 0; goto out_unlock; @@ -5812,8 +5822,7 @@ static int cgroup_destroy_locked(struct cgroup *cgrp) cgroup1_check_for_release(parent); - if (cgrp->root == &cgrp_dfl_root) - cgroup_bpf_offline(cgrp); + cgroup_bpf_offline(cgrp); /* put the base reference */ percpu_ref_kill(&cgrp->self.refcnt); @@ -6066,7 +6075,8 @@ static int __init cgroup_wq_init(void) } core_initcall(cgroup_wq_init); -void cgroup_path_from_kernfs_id(u64 id, char *buf, size_t buflen) +void cgroup_path_from_kernfs_id(const union kernfs_node_id *id, + char *buf, size_t buflen) { struct kernfs_node *kn; @@ -6660,31 +6670,26 @@ void cgroup_sk_free(struct sock_cgroup_data *skcd) #endif /* CONFIG_SOCK_CGROUP_DATA */ #ifdef CONFIG_CGROUP_BPF -int cgroup_bpf_attach(struct cgroup *cgrp, - struct bpf_prog *prog, struct bpf_prog *replace_prog, - struct bpf_cgroup_link *link, - enum bpf_attach_type type, - u32 flags) +int cgroup_bpf_attach(struct cgroup *cgrp, struct bpf_prog *prog, + enum bpf_attach_type type, u32 flags) { int ret; mutex_lock(&cgroup_mutex); - ret = __cgroup_bpf_attach(cgrp, prog, replace_prog, link, type, flags); + ret = __cgroup_bpf_attach(cgrp, prog, type, flags); mutex_unlock(&cgroup_mutex); return ret; } - int cgroup_bpf_detach(struct cgroup *cgrp, struct bpf_prog *prog, - enum bpf_attach_type type) + enum bpf_attach_type type, u32 flags) { int ret; mutex_lock(&cgroup_mutex); - ret = __cgroup_bpf_detach(cgrp, prog, NULL, type); + ret = __cgroup_bpf_detach(cgrp, prog, type); mutex_unlock(&cgroup_mutex); return ret; } - int cgroup_bpf_query(struct cgroup *cgrp, const union bpf_attr *attr, union bpf_attr __user *uattr) { @@ -6745,10 +6750,7 @@ static struct kobj_attribute cgroup_delegate_attr = __ATTR_RO(delegate); static ssize_t features_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) { - return snprintf(buf, PAGE_SIZE, - "nsdelegate\n" - "memory_localevents\n" - "memory_recursiveprot\n"); + return snprintf(buf, PAGE_SIZE, "nsdelegate\nmemory_localevents\n"); } static struct kobj_attribute cgroup_features_attr = __ATTR_RO(features); diff --git a/kernel/debug/debug_core.c b/kernel/debug/debug_core.c index b9d09ebe2038..1ab2e9703486 100644 --- a/kernel/debug/debug_core.c +++ b/kernel/debug/debug_core.c @@ -164,18 +164,18 @@ int __weak kgdb_arch_set_breakpoint(struct kgdb_bkpt *bpt) { int err; - err = copy_from_kernel_nofault(bpt->saved_instr, (char *)bpt->bpt_addr, + err = probe_kernel_read(bpt->saved_instr, (char *)bpt->bpt_addr, BREAK_INSTR_SIZE); if (err) return err; - err = copy_to_kernel_nofault((char *)bpt->bpt_addr, + err = probe_kernel_write((char *)bpt->bpt_addr, arch_kgdb_ops.gdb_bpt_instr, BREAK_INSTR_SIZE); return err; } int __weak kgdb_arch_remove_breakpoint(struct kgdb_bkpt *bpt) { - return copy_to_kernel_nofault((char *)bpt->bpt_addr, + return probe_kernel_write((char *)bpt->bpt_addr, (char *)bpt->saved_instr, BREAK_INSTR_SIZE); } diff --git a/kernel/debug/gdbstub.c b/kernel/debug/gdbstub.c index 61774aec46b4..4b280fc7dd67 100644 --- a/kernel/debug/gdbstub.c +++ b/kernel/debug/gdbstub.c @@ -247,7 +247,7 @@ char *kgdb_mem2hex(char *mem, char *buf, int count) */ tmp = buf + count; - err = copy_from_kernel_nofault(tmp, mem, count); + err = probe_kernel_read(tmp, mem, count); if (err) return NULL; while (count > 0) { @@ -283,7 +283,7 @@ int kgdb_hex2mem(char *buf, char *mem, int count) *tmp_raw |= hex_to_bin(*tmp_hex--) << 4; } - return copy_to_kernel_nofault(mem, tmp_raw, count); + return probe_kernel_write(mem, tmp_raw, count); } /* @@ -335,7 +335,7 @@ static int kgdb_ebin2mem(char *buf, char *mem, int count) size++; } - return copy_to_kernel_nofault(mem, c, size); + return probe_kernel_write(mem, c, size); } #if DBG_MAX_REG_NUM > 0 diff --git a/kernel/debug/kdb/kdb_main.c b/kernel/debug/kdb/kdb_main.c index 3d3d3e651c4a..51cfb8618205 100644 --- a/kernel/debug/kdb/kdb_main.c +++ b/kernel/debug/kdb/kdb_main.c @@ -2380,8 +2380,7 @@ void kdb_ps1(const struct task_struct *p) int cpu; unsigned long tmp; - if (!p || - copy_from_kernel_nofault(&tmp, (char *)p, sizeof(unsigned long))) + if (!p || probe_kernel_read(&tmp, (char *)p, sizeof(unsigned long))) return; cpu = kdb_process_cpu(p); diff --git a/kernel/debug/kdb/kdb_support.c b/kernel/debug/kdb/kdb_support.c index 004c5b6c87f8..b8e6306e7e13 100644 --- a/kernel/debug/kdb/kdb_support.c +++ b/kernel/debug/kdb/kdb_support.c @@ -325,7 +325,7 @@ char *kdb_strdup(const char *str, gfp_t type) */ int kdb_getarea_size(void *res, unsigned long addr, size_t size) { - int ret = copy_from_kernel_nofault((char *)res, (char *)addr, size); + int ret = probe_kernel_read((char *)res, (char *)addr, size); if (ret) { if (!KDB_STATE(SUPPRESS)) { kdb_printf("kdb_getarea: Bad address 0x%lx\n", addr); @@ -350,7 +350,7 @@ int kdb_getarea_size(void *res, unsigned long addr, size_t size) */ int kdb_putarea_size(unsigned long addr, void *res, size_t size) { - int ret = copy_from_kernel_nofault((char *)addr, (char *)res, size); + int ret = probe_kernel_read((char *)addr, (char *)res, size); if (ret) { if (!KDB_STATE(SUPPRESS)) { kdb_printf("kdb_putarea: Bad address 0x%lx\n", addr); @@ -624,8 +624,7 @@ char kdb_task_state_char (const struct task_struct *p) char state; unsigned long tmp; - if (!p || - copy_from_kernel_nofault(&tmp, (char *)p, sizeof(unsigned long))) + if (!p || probe_kernel_read(&tmp, (char *)p, sizeof(unsigned long))) return 'E'; cpu = kdb_process_cpu(p); diff --git a/kernel/events/callchain.c b/kernel/events/callchain.c index 41160f218852..c2b41a263166 100644 --- a/kernel/events/callchain.c +++ b/kernel/events/callchain.c @@ -149,7 +149,7 @@ void put_callchain_buffers(void) } } -struct perf_callchain_entry *get_callchain_entry(int *rctx) +static struct perf_callchain_entry *get_callchain_entry(int *rctx) { int cpu; struct callchain_cpus_entries *entries; @@ -159,10 +159,8 @@ struct perf_callchain_entry *get_callchain_entry(int *rctx) return NULL; entries = rcu_dereference(callchain_cpus_entries); - if (!entries) { - put_recursion_context(this_cpu_ptr(callchain_recursion), *rctx); + if (!entries) return NULL; - } cpu = smp_processor_id(); @@ -170,7 +168,7 @@ struct perf_callchain_entry *get_callchain_entry(int *rctx) (*rctx * perf_callchain_entry__sizeof())); } -void +static void put_callchain_entry(int rctx) { put_recursion_context(this_cpu_ptr(callchain_recursion), rctx); @@ -185,9 +183,12 @@ get_perf_callchain(struct pt_regs *regs, u32 init_nr, bool kernel, bool user, int rctx; entry = get_callchain_entry(&rctx); - if (!entry) + if (rctx == -1) return NULL; + if (!entry) + goto exit_put; + ctx.entry = entry; ctx.max_stack = max_stack; ctx.nr = entry->nr = init_nr; @@ -235,7 +236,7 @@ exit_put: * sysctl_perf_event_max_contexts_per_stack. */ int perf_event_max_stack_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int *value = table->data; int new_value = *value, ret; diff --git a/kernel/events/core.c b/kernel/events/core.c index 2fe7d93277cd..db126bb24ec0 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -461,7 +461,8 @@ static void update_perf_cpu_limits(void) static bool perf_rotate_context(struct perf_cpu_context *cpuctx); int perf_proc_update_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { int ret; int perf_cpu = sysctl_perf_cpu_time_max_percent; @@ -485,7 +486,8 @@ int perf_proc_update_handler(struct ctl_table *table, int write, int sysctl_perf_cpu_time_max_percent __read_mostly = DEFAULT_CPU_TIME_MAX_PERCENT; int perf_cpu_time_max_percent_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos); @@ -7476,7 +7478,7 @@ static void perf_fill_ns_link_info(struct perf_ns_link_info *ns_link_info, { struct path ns_path; struct inode *ns_inode; - int error; + void *error; error = ns_get_path(&ns_path, task, ns_ops); if (!error) { @@ -8227,22 +8229,23 @@ static void perf_event_bpf_emit_ksymbols(struct bpf_prog *prog, enum perf_bpf_event_type type) { bool unregister = type == PERF_BPF_EVENT_PROG_UNLOAD; + char sym[KSYM_NAME_LEN]; int i; if (prog->aux->func_cnt == 0) { + bpf_get_prog_name(prog, sym); perf_event_ksymbol(PERF_RECORD_KSYMBOL_TYPE_BPF, (u64)(unsigned long)prog->bpf_func, - prog->jited_len, unregister, - prog->aux->ksym.name); + prog->jited_len, unregister, sym); } else { for (i = 0; i < prog->aux->func_cnt; i++) { struct bpf_prog *subprog = prog->aux->func[i]; + bpf_get_prog_name(subprog, sym); perf_event_ksymbol( PERF_RECORD_KSYMBOL_TYPE_BPF, (u64)(unsigned long)subprog->bpf_func, - subprog->jited_len, unregister, - prog->aux->ksym.name); + subprog->jited_len, unregister, sym); } } } @@ -9207,24 +9210,6 @@ static int perf_event_set_bpf_handler(struct perf_event *event, u32 prog_fd) if (IS_ERR(prog)) return PTR_ERR(prog); - if (event->attr.precise_ip && - prog->call_get_stack && - (!(event->attr.sample_type & __PERF_SAMPLE_CALLCHAIN_EARLY) || - event->attr.exclude_callchain_kernel || - event->attr.exclude_callchain_user)) { - /* - * On perf_event with precise_ip, calling bpf_get_stack() - * may trigger unwinder warnings and occasional crashes. - * bpf_get_[stack|stackid] works around this issue by using - * callchain attached to perf_sample_data. If the - * perf_event does not full (kernel and user) callchain - * attached to perf_sample_data, do not allow attaching BPF - * program that calls bpf_get_[stack|stackid]. - */ - bpf_prog_put(prog); - return -EPROTO; - } - event->prog = prog; event->orig_overflow_handler = READ_ONCE(event->overflow_handler); WRITE_ONCE(event->overflow_handler, bpf_overflow_handler); @@ -10846,9 +10831,12 @@ perf_event_alloc(struct perf_event_attr *attr, int cpu, context = parent_event->overflow_handler_context; #if defined(CONFIG_BPF_SYSCALL) && defined(CONFIG_EVENT_TRACING) if (overflow_handler == bpf_overflow_handler) { - struct bpf_prog *prog = parent_event->prog; + struct bpf_prog *prog = bpf_prog_inc(parent_event->prog); - bpf_prog_inc(prog); + if (IS_ERR(prog)) { + err = PTR_ERR(prog); + goto err_ns; + } event->prog = prog; event->orig_overflow_handler = parent_event->orig_overflow_handler; diff --git a/kernel/events/uprobes.c b/kernel/events/uprobes.c index 2b809bc849dd..6285674412f2 100644 --- a/kernel/events/uprobes.c +++ b/kernel/events/uprobes.c @@ -2248,13 +2248,6 @@ static void handle_swbp(struct pt_regs *regs) handler_chain(uprobe, regs); - /* - * If user decided to take execution elsewhere, it makes little sense - * to execute the original instruction, so let's skip it. - */ - if (instruction_pointer(regs) != bp_vaddr) - goto out; - if (arch_uprobe_skip_sstep(&uprobe->arch, regs)) goto out; diff --git a/kernel/exit.c b/kernel/exit.c index d5d584cd79ce..4461ba1dd3fc 100644 --- a/kernel/exit.c +++ b/kernel/exit.c @@ -64,7 +64,6 @@ #include #include #include -#include #include #include @@ -274,7 +273,6 @@ repeat: } write_unlock_irq(&tasklist_lock); - seccomp_filter_release(p); release_thread(p); put_task_struct_rcu_user(p); @@ -870,8 +868,7 @@ void __noreturn do_exit(long code) exit_task_namespaces(tsk); exit_task_work(tsk); exit_thread(tsk); - if (group_dead) - exit_umh(tsk); + exit_umh(tsk); sched_autogroup_exit_task(tsk); cgroup_exit(tsk); @@ -1778,30 +1775,6 @@ Efault: } #endif -/** - * thread_group_exited - check that a thread group has exited - * @pid: tgid of thread group to be checked. - * - * Test if the thread group represented by tgid has exited (all - * threads are zombies, dead or completely gone). - * - * Return: true if the thread group has exited. false otherwise. - */ -bool thread_group_exited(struct pid *pid) -{ - struct task_struct *task; - bool exited; - - rcu_read_lock(); - task = pid_task(pid, PIDTYPE_PID); - exited = !task || - (READ_ONCE(task->exit_state) && thread_group_empty(task)); - rcu_read_unlock(); - - return exited; -} -EXPORT_SYMBOL(thread_group_exited); - __weak void abort(void) { BUG(); diff --git a/kernel/extable.c b/kernel/extable.c index b0ea5eb0c3b4..14bda7cab65f 100644 --- a/kernel/extable.c +++ b/kernel/extable.c @@ -57,8 +57,6 @@ const struct exception_table_entry *search_exception_tables(unsigned long addr) e = search_kernel_exception_table(addr); if (!e) e = search_module_extables(addr); - if (!e) - e = search_bpf_extables(addr); return e; } @@ -132,9 +130,8 @@ int kernel_text_address(unsigned long addr) * triggers a stack trace, or a WARN() that happens during * coming back from idle, or cpu on or offlining. * - * is_module_text_address() as well as the kprobe slots, - * is_bpf_text_address() and is_bpf_image_address require - * RCU to be watching. + * is_module_text_address() as well as the kprobe slots + * and is_bpf_text_address() require RCU to be watching. */ no_rcu = !rcu_is_watching(); diff --git a/kernel/fork.c b/kernel/fork.c index 3b98f44b8799..6e799e98a14c 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -474,6 +474,7 @@ void free_task(struct task_struct *tsk) #endif rt_mutex_debug_task_free(tsk); ftrace_graph_exit_task(tsk); + put_seccomp_filter(tsk); arch_release_task_struct(tsk); if (tsk->flags & PF_KTHREAD) free_kthread_struct(tsk); @@ -1476,25 +1477,28 @@ static int copy_fs(unsigned long clone_flags, struct task_struct *tsk) static int copy_files(unsigned long clone_flags, struct task_struct *tsk) { struct files_struct *oldf, *newf; + int error = 0; /* * A background process may not have any files ... */ oldf = current->files; if (!oldf) - return 0; + goto out; if (clone_flags & CLONE_FILES) { atomic_inc(&oldf->count); - return 0; + goto out; } - newf = dup_fd(oldf, NULL); - if (IS_ERR(newf)) - return PTR_ERR(newf); + newf = dup_fd(oldf, &error); + if (!newf) + goto out; tsk->files = newf; - return 0; + error = 0; +out: + return error; } static int copy_io(unsigned long clone_flags, struct task_struct *tsk) @@ -1540,11 +1544,6 @@ static int copy_sighand(unsigned long clone_flags, struct task_struct *tsk) spin_lock_irq(¤t->sighand->siglock); memcpy(sig->action, current->sighand->action, sizeof(sig->action)); spin_unlock_irq(¤t->sighand->siglock); - - /* Reset all signal handler not set to SIG_IGN to SIG_DFL. */ - if (clone_flags & CLONE_CLEAR_SIGHAND) - flush_signal_handlers(tsk, 0); - return 0; } @@ -1703,10 +1702,6 @@ static inline void rcu_copy_process(struct task_struct *p) INIT_LIST_HEAD(&p->rcu_tasks_holdout_list); p->rcu_tasks_idle_cpu = -1; #endif /* #ifdef CONFIG_TASKS_RCU */ -#ifdef CONFIG_TASKS_TRACE_RCU - p->trc_reader_nesting = 0; - INIT_LIST_HEAD(&p->trc_holdout_list); -#endif /* #ifdef CONFIG_TASKS_TRACE_RCU */ } struct pid *pidfd_pid(const struct file *file) @@ -1748,18 +1743,22 @@ static void pidfd_show_fdinfo(struct seq_file *m, struct file *f) */ static __poll_t pidfd_poll(struct file *file, struct poll_table_struct *pts) { + struct task_struct *task; struct pid *pid = file->private_data; __poll_t poll_flags = 0; poll_wait(file, &pid->wait_pidfd, pts); + rcu_read_lock(); + task = pid_task(pid, PIDTYPE_PID); /* * Inform pollers only when the whole thread group exits. * If the thread group leader exits before all other threads in the * group, then poll(2) should block, similar to the wait(2) family. */ - if (thread_group_exited(pid)) + if (!task || (task->exit_state && thread_group_empty(task))) poll_flags = EPOLLIN | EPOLLRDNORM; + rcu_read_unlock(); return poll_flags; } @@ -2166,8 +2165,7 @@ static __latent_entropy struct task_struct *copy_process( stackleak_task_init(p); if (pid != &init_struct_pid) { - pid = alloc_pid(p->nsproxy->pid_ns_for_children, args->set_tid, - args->set_tid_size); + pid = alloc_pid(p->nsproxy->pid_ns_for_children); if (IS_ERR(pid)) { retval = PTR_ERR(pid); goto bad_fork_cleanup_thread; @@ -2665,7 +2663,6 @@ noinline static int copy_clone_args_from_user(struct kernel_clone_args *kargs, { int err; struct clone_args args; - pid_t *kset_tid = kargs->set_tid; if (unlikely(usize > PAGE_SIZE)) return -E2BIG; @@ -2676,15 +2673,6 @@ noinline static int copy_clone_args_from_user(struct kernel_clone_args *kargs, if (err) return err; - if (unlikely(args.set_tid_size > MAX_PID_NS_LEVEL)) - return -EINVAL; - - if (unlikely(!args.set_tid && args.set_tid_size > 0)) - return -EINVAL; - - if (unlikely(args.set_tid && args.set_tid_size == 0)) - return -EINVAL; - /* * Verify that higher 32bits of exit_signal are unset and that * it is a valid signal @@ -2702,16 +2690,8 @@ noinline static int copy_clone_args_from_user(struct kernel_clone_args *kargs, .stack = args.stack, .stack_size = args.stack_size, .tls = args.tls, - .set_tid_size = args.set_tid_size, }; - if (args.set_tid && - copy_from_user(kset_tid, u64_to_user_ptr(args.set_tid), - (kargs->set_tid_size * sizeof(pid_t)))) - return -EFAULT; - - kargs->set_tid = kset_tid; - return 0; } @@ -2745,8 +2725,11 @@ static inline bool clone3_stack_valid(struct kernel_clone_args *kargs) static bool clone3_args_valid(struct kernel_clone_args *kargs) { - /* Verify that no unknown flags are passed along. */ - if (kargs->flags & ~(CLONE_LEGACY_FLAGS | CLONE_CLEAR_SIGHAND)) + /* + * All lower bits of the flag word are taken. + * Verify that no other unknown flags are passed along. + */ + if (kargs->flags & ~CLONE_LEGACY_FLAGS) return false; /* @@ -2756,10 +2739,6 @@ static bool clone3_args_valid(struct kernel_clone_args *kargs) if (kargs->flags & (CLONE_DETACHED | CSIGNAL)) return false; - if ((kargs->flags & (CLONE_SIGHAND | CLONE_CLEAR_SIGHAND)) == - (CLONE_SIGHAND | CLONE_CLEAR_SIGHAND)) - return false; - if ((kargs->flags & (CLONE_THREAD | CLONE_PARENT)) && kargs->exit_signal) return false; @@ -2786,9 +2765,6 @@ SYSCALL_DEFINE2(clone3, struct clone_args __user *, uargs, size_t, size) int err; struct kernel_clone_args kargs; - pid_t set_tid[MAX_PID_NS_LEVEL]; - - kargs.set_tid = set_tid; err = copy_clone_args_from_user(&kargs, uargs, size); if (err) @@ -2947,13 +2923,13 @@ static int unshare_fs(unsigned long unshare_flags, struct fs_struct **new_fsp) static int unshare_fd(unsigned long unshare_flags, struct files_struct **new_fdp) { struct files_struct *fd = current->files; + int error = 0; if ((unshare_flags & CLONE_FILES) && (fd && atomic_read(&fd->count) > 1)) { - fd = dup_fd(fd, NULL); - if (IS_ERR(fd)) - return PTR_ERR(fd); - *new_fdp = fd; + *new_fdp = dup_fd(fd, &error); + if (!*new_fdp) + return error; } return 0; @@ -3113,7 +3089,7 @@ int unshare_files(struct files_struct **displaced) } int sysctl_max_threads(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ctl_table t; int ret; diff --git a/kernel/gcov/gcc_4_7.c b/kernel/gcov/gcc_4_7.c index 85c290f710d6..88e128c1221b 100644 --- a/kernel/gcov/gcc_4_7.c +++ b/kernel/gcov/gcc_4_7.c @@ -19,9 +19,7 @@ #include #include "gcov.h" -#if (__GNUC__ >= 15) -#define GCOV_COUNTERS 10 -#elif (__GNUC__ >= 14) +#if (__GNUC__ >= 14) #define GCOV_COUNTERS 9 #elif (__GNUC__ >= 10) #define GCOV_COUNTERS 8 diff --git a/kernel/groups.c b/kernel/groups.c index 6ee6691f6839..daae2f2dc6d4 100644 --- a/kernel/groups.c +++ b/kernel/groups.c @@ -20,7 +20,7 @@ struct group_info *groups_alloc(int gidsetsize) len = sizeof(struct group_info) + sizeof(kgid_t) * gidsetsize; gi = kmalloc(len, GFP_KERNEL_ACCOUNT|__GFP_NOWARN|__GFP_NORETRY); if (!gi) - gi = __vmalloc(len, GFP_KERNEL_ACCOUNT); + gi = __vmalloc(len, GFP_KERNEL_ACCOUNT, PAGE_KERNEL); if (!gi) return NULL; diff --git a/kernel/hung_task.c b/kernel/hung_task.c index 4f77a49c69cc..313fc190f265 100644 --- a/kernel/hung_task.c +++ b/kernel/hung_task.c @@ -231,7 +231,8 @@ static long hung_timeout_jiffies(unsigned long last_checked, * Process updating of timeout sysctl */ int proc_dohung_task_timeout_secs(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { int ret; diff --git a/kernel/irq_work.c b/kernel/irq_work.c index df0dbf4d859b..d42acaf81886 100644 --- a/kernel/irq_work.c +++ b/kernel/irq_work.c @@ -29,16 +29,16 @@ static DEFINE_PER_CPU(struct llist_head, lazy_list); */ static bool irq_work_claim(struct irq_work *work) { - int flags, oflags, nflags; + unsigned long flags, oflags, nflags; /* * Start with our best wish as a premise but only trust any * flag value after cmpxchg() result. */ - flags = atomic_read(&work->flags) & ~IRQ_WORK_PENDING; + flags = work->flags & ~IRQ_WORK_PENDING; for (;;) { nflags = flags | IRQ_WORK_CLAIMED; - oflags = atomic_cmpxchg(&work->flags, flags, nflags); + oflags = cmpxchg(&work->flags, flags, nflags); if (oflags == flags) break; if (oflags & IRQ_WORK_PENDING) @@ -61,7 +61,7 @@ void __weak arch_irq_work_raise(void) static void __irq_work_queue_local(struct irq_work *work) { /* If the work is "lazy", handle it from next tick if any */ - if (atomic_read(&work->flags) & IRQ_WORK_LAZY) { + if (work->flags & IRQ_WORK_LAZY) { if (llist_add(&work->llnode, this_cpu_ptr(&lazy_list)) && tick_nohz_tick_stopped()) arch_irq_work_raise(); @@ -143,7 +143,7 @@ static void irq_work_run_list(struct llist_head *list) { struct irq_work *work, *tmp; struct llist_node *llnode; - int flags; + unsigned long flags; BUG_ON(!irqs_disabled()); @@ -159,15 +159,15 @@ static void irq_work_run_list(struct llist_head *list) * to claim that work don't rely on us to handle their data * while we are in the middle of the func. */ - flags = atomic_read(&work->flags) & ~IRQ_WORK_PENDING; - atomic_xchg(&work->flags, flags); + flags = work->flags & ~IRQ_WORK_PENDING; + xchg(&work->flags, flags); work->func(work); /* * Clear the BUSY bit and return to the free state if * no-one else claimed it meanwhile. */ - (void)atomic_cmpxchg(&work->flags, flags, flags & ~IRQ_WORK_BUSY); + (void)cmpxchg(&work->flags, flags, flags & ~IRQ_WORK_BUSY); } } @@ -199,7 +199,7 @@ void irq_work_sync(struct irq_work *work) { lockdep_assert_irqs_enabled(); - while (atomic_read(&work->flags) & IRQ_WORK_BUSY) + while (work->flags & IRQ_WORK_BUSY) cpu_relax(); } EXPORT_SYMBOL_GPL(irq_work_sync); diff --git a/kernel/kprobes.c b/kernel/kprobes.c index c928bb963074..063e4ade1680 100644 --- a/kernel/kprobes.c +++ b/kernel/kprobes.c @@ -894,7 +894,7 @@ static void unoptimize_all_kprobes(void) static DEFINE_MUTEX(kprobe_sysctl_mutex); int sysctl_kprobes_optimization; int proc_kprobes_optimization_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, + void __user *buffer, size_t *length, loff_t *ppos) { int ret; diff --git a/kernel/kthread.c b/kernel/kthread.c index d3065a49fca3..4ab1bf86a708 100644 --- a/kernel/kthread.c +++ b/kernel/kthread.c @@ -200,7 +200,7 @@ void *kthread_probe_data(struct task_struct *task) void *data = NULL; if (kthread) - copy_from_kernel_nofault(&data, &kthread->data, sizeof(data)); + probe_kernel_read(&data, &kthread->data, sizeof(data)); return data; } diff --git a/kernel/latencytop.c b/kernel/latencytop.c index c22fc68bdf8a..e3acead004e6 100644 --- a/kernel/latencytop.c +++ b/kernel/latencytop.c @@ -269,8 +269,8 @@ static int __init init_lstats_procfs(void) return 0; } -int sysctl_latencytop(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos) +int sysctl_latencytop(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) { int err; diff --git a/kernel/livepatch/patch.c b/kernel/livepatch/patch.c index b552cf2d85f8..bd43537702bd 100644 --- a/kernel/livepatch/patch.c +++ b/kernel/livepatch/patch.c @@ -196,8 +196,7 @@ static int klp_patch_func(struct klp_func *func) ops->fops.func = klp_ftrace_handler; ops->fops.flags = FTRACE_OPS_FL_SAVE_REGS | FTRACE_OPS_FL_DYNAMIC | - FTRACE_OPS_FL_IPMODIFY | - FTRACE_OPS_FL_PERMANENT; + FTRACE_OPS_FL_IPMODIFY; list_add(&ops->node, &klp_ops); diff --git a/kernel/locking/rtmutex.c b/kernel/locking/rtmutex.c index 7a68ab2c5851..7c727c4944e6 100644 --- a/kernel/locking/rtmutex.c +++ b/kernel/locking/rtmutex.c @@ -1063,26 +1063,20 @@ static void mark_wakeup_next_waiter(struct wake_q_head *wake_q, * * Must be called with lock->wait_lock held and interrupts disabled. I must * have just failed to try_to_take_rt_mutex(). - * - * When invoked from rt_mutex_start_proxy_lock() waiter::task != current ! */ static void remove_waiter(struct rt_mutex *lock, struct rt_mutex_waiter *waiter) { bool is_top_waiter = (waiter == rt_mutex_top_waiter(lock)); struct task_struct *owner = rt_mutex_owner(lock); - struct task_struct *waiter_task = waiter->task; struct rt_mutex *next_lock; lockdep_assert_held(&lock->wait_lock); - if (!waiter_task) /* never enqueued */ - return; - - raw_spin_lock(&waiter_task->pi_lock); + raw_spin_lock(¤t->pi_lock); rt_mutex_dequeue(lock, waiter); - waiter_task->pi_blocked_on = NULL; - raw_spin_unlock(&waiter_task->pi_lock); + current->pi_blocked_on = NULL; + raw_spin_unlock(¤t->pi_lock); /* * Only update priority if the waiter was the highest priority @@ -1118,7 +1112,7 @@ static void remove_waiter(struct rt_mutex *lock, raw_spin_unlock_irq(&lock->wait_lock); rt_mutex_adjust_prio_chain(owner, RT_MUTEX_MIN_CHAINWALK, lock, - next_lock, NULL, waiter_task); + next_lock, NULL, current); raw_spin_lock_irq(&lock->wait_lock); } @@ -1808,7 +1802,7 @@ int rt_mutex_start_proxy_lock(struct rt_mutex *lock, raw_spin_lock_irq(&lock->wait_lock); ret = __rt_mutex_start_proxy_lock(lock, waiter, task); - if (unlikely(ret < 0)) + if (unlikely(ret)) remove_waiter(lock, waiter); raw_spin_unlock_irq(&lock->wait_lock); diff --git a/kernel/module.c b/kernel/module.c index 67ebb48b2ee8..adceceb6c49f 100644 --- a/kernel/module.c +++ b/kernel/module.c @@ -3166,7 +3166,8 @@ static int copy_module_from_user(const void __user *umod, unsigned long len, return err; /* Suck in entire file: we'll want most of it. */ - info->hdr = __vmalloc(info->len, GFP_KERNEL | __GFP_NOWARN); + info->hdr = __vmalloc(info->len, + GFP_KERNEL | __GFP_NOWARN, PAGE_KERNEL); if (!info->hdr) return -ENOMEM; diff --git a/kernel/padata.c b/kernel/padata.c index 409d24228439..47aebcda65d5 100644 --- a/kernel/padata.c +++ b/kernel/padata.c @@ -204,11 +204,7 @@ static struct padata_priv *padata_find_next(struct parallel_data *pd, list_del_init(&padata->list); atomic_dec(&pd->reorder_objects); ++pd->processed; - /* When sequence wraps around, reset to the first CPU. */ - if (unlikely(pd->processed == 0)) - pd->cpu = cpumask_first(pd->cpumask.pcpu); - else - pd->cpu = cpumask_next_wrap(cpu, pd->cpumask.pcpu, -1, false); + pd->cpu = cpumask_next_wrap(cpu, pd->cpumask.pcpu, -1, false); } spin_unlock(&reorder->lock); diff --git a/kernel/pid.c b/kernel/pid.c index b7adaef4889b..d28a7387912f 100644 --- a/kernel/pid.c +++ b/kernel/pid.c @@ -157,8 +157,7 @@ void free_pid(struct pid *pid) call_rcu(&pid->rcu, delayed_put_pid); } -struct pid *alloc_pid(struct pid_namespace *ns, pid_t *set_tid, - size_t set_tid_size) +struct pid *alloc_pid(struct pid_namespace *ns) { struct pid *pid; enum pid_type type; @@ -167,17 +166,6 @@ struct pid *alloc_pid(struct pid_namespace *ns, pid_t *set_tid, struct upid *upid; int retval = -ENOMEM; - /* - * set_tid_size contains the size of the set_tid array. Starting at - * the most nested currently active PID namespace it tells alloc_pid() - * which PID to set for a process in that most nested PID namespace - * up to set_tid_size PID namespaces. It does not have to set the PID - * for a process in all nested PID namespaces but set_tid_size must - * never be greater than the current ns->level + 1. - */ - if (set_tid_size > ns->level + 1) - return ERR_PTR(-EINVAL); - pid = kmem_cache_alloc(ns->pid_cachep, GFP_KERNEL); if (!pid) return ERR_PTR(retval); @@ -186,54 +174,24 @@ struct pid *alloc_pid(struct pid_namespace *ns, pid_t *set_tid, pid->level = ns->level; for (i = ns->level; i >= 0; i--) { - int tid = 0; - - if (set_tid_size) { - tid = set_tid[ns->level - i]; - - retval = -EINVAL; - if (tid < 1 || tid >= pid_max) - goto out_free; - /* - * Also fail if a PID != 1 is requested and - * no PID 1 exists. - */ - if (tid != 1 && !tmp->child_reaper) - goto out_free; - retval = -EPERM; - if (!checkpoint_restore_ns_capable(tmp->user_ns)) - goto out_free; - set_tid_size--; - } + int pid_min = 1; idr_preload(GFP_KERNEL); spin_lock_irq(&pidmap_lock); - if (tid) { - nr = idr_alloc(&tmp->idr, NULL, tid, - tid + 1, GFP_ATOMIC); - /* - * If ENOSPC is returned it means that the PID is - * alreay in use. Return EEXIST in that case. - */ - if (nr == -ENOSPC) - nr = -EEXIST; - } else { - int pid_min = 1; - /* - * init really needs pid 1, but after reaching the - * maximum wrap back to RESERVED_PIDS - */ - if (idr_get_cursor(&tmp->idr) > RESERVED_PIDS) - pid_min = RESERVED_PIDS; + /* + * init really needs pid 1, but after reaching the maximum + * wrap back to RESERVED_PIDS + */ + if (idr_get_cursor(&tmp->idr) > RESERVED_PIDS) + pid_min = RESERVED_PIDS; - /* - * Store a null pointer so find_pid_ns does not find - * a partially initialized PID (see below). - */ - nr = idr_alloc_cyclic(&tmp->idr, NULL, pid_min, - pid_max, GFP_ATOMIC); - } + /* + * Store a null pointer so find_pid_ns does not find + * a partially initialized PID (see below). + */ + nr = idr_alloc_cyclic(&tmp->idr, NULL, pid_min, + pid_max, GFP_ATOMIC); spin_unlock_irq(&pidmap_lock); idr_preload_end(); @@ -450,7 +408,7 @@ pid_t pid_nr_ns(struct pid *pid, struct pid_namespace *ns) struct upid *upid; pid_t nr = 0; - if (pid && ns && ns->level <= pid->level) { + if (pid && ns->level <= pid->level) { upid = &pid->numbers[ns->level]; if (upid->ns == ns) nr = upid->nr; diff --git a/kernel/pid_namespace.c b/kernel/pid_namespace.c index 78b409b88fbd..f26415341c75 100644 --- a/kernel/pid_namespace.c +++ b/kernel/pid_namespace.c @@ -26,6 +26,8 @@ static DEFINE_MUTEX(pid_caches_mutex); static struct kmem_cache *pid_ns_cachep; +/* MAX_PID_NS_LEVEL is needed for limiting size of 'struct pid' */ +#define MAX_PID_NS_LEVEL 32 /* Write once array, filled from the beginning. */ static struct kmem_cache *pid_cache[MAX_PID_NS_LEVEL]; @@ -264,13 +266,13 @@ void zap_pid_ns_processes(struct pid_namespace *pid_ns) #ifdef CONFIG_CHECKPOINT_RESTORE static int pid_ns_ctl_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct pid_namespace *pid_ns = task_active_pid_ns(current); struct ctl_table tmp = *table; int ret, next; - if (write && !checkpoint_restore_ns_capable(pid_ns->user_ns)) + if (write && !ns_capable(pid_ns->user_ns, CAP_SYS_ADMIN)) return -EPERM; /* diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c index bdb38bd29ce8..54de5cc3e4e8 100644 --- a/kernel/printk/printk.c +++ b/kernel/printk/printk.c @@ -177,7 +177,7 @@ __setup("printk.devkmsg=", control_devkmsg); char devkmsg_log_str[DEVKMSG_STR_MAX_SIZE] = "ratelimit"; int devkmsg_sysctl_set_loglvl(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { char old_str[DEVKMSG_STR_MAX_SIZE]; unsigned int old; @@ -3060,7 +3060,7 @@ static void wake_up_klogd_work_func(struct irq_work *irq_work) static DEFINE_PER_CPU(struct irq_work, wake_up_klogd_work) = { .func = wake_up_klogd_work_func, - .flags = ATOMIC_INIT(IRQ_WORK_LAZY), + .flags = IRQ_WORK_LAZY, }; void wake_up_klogd(void) diff --git a/kernel/rcu/Kconfig b/kernel/rcu/Kconfig index 439222236550..7644eda17d62 100644 --- a/kernel/rcu/Kconfig +++ b/kernel/rcu/Kconfig @@ -69,37 +69,13 @@ config TREE_SRCU help This option selects the full-fledged version of SRCU. -config TASKS_RCU_GENERIC - def_bool TASKS_RCU || TASKS_RUDE_RCU || TASKS_TRACE_RCU - select SRCU - help - This option enables generic infrastructure code supporting - task-based RCU implementations. Not for manual selection. - config TASKS_RCU def_bool PREEMPTION + select SRCU help This option enables a task-based RCU implementation that uses only voluntary context switch (not preemption!), idle, and - user-mode execution as quiescent states. Not for manual selection. - -config TASKS_RUDE_RCU - def_bool 0 - help - This option enables a task-based RCU implementation that uses - only context switch (including preemption) and user-mode - execution as quiescent states. It forces IPIs and context - switches on all online CPUs, including idle ones, so use - with caution. - -config TASKS_TRACE_RCU - def_bool 0 - help - This option enables a task-based RCU implementation that uses - explicit rcu_read_lock_trace() read-side markers, and allows - these readers to appear in the idle loop as well as on the CPU - hotplug code paths. It can force IPIs on online CPUs, including - idle ones, so use with caution. + user-mode execution as quiescent states. config RCU_STALL_COMMON def_bool ( TREE_RCU || PREEMPT_RCU ) diff --git a/kernel/rcu/tasks.h b/kernel/rcu/tasks.h deleted file mode 100644 index b537d349fbde..000000000000 --- a/kernel/rcu/tasks.h +++ /dev/null @@ -1,932 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Task-based RCU implementations. - * - * Copyright (C) 2020 Paul E. McKenney - */ - - -//////////////////////////////////////////////////////////////////////// -// -// Generic data structures. - -struct rcu_tasks; -typedef void (*rcu_tasks_gp_func_t)(struct rcu_tasks *rtp); -typedef void (*pregp_func_t)(void); -typedef void (*pertask_func_t)(struct task_struct *t, struct list_head *hop); -typedef void (*postscan_func_t)(void); -typedef void (*holdouts_func_t)(struct list_head *hop, bool ndrpt, bool *frptp); -typedef void (*postgp_func_t)(void); - -/** - * Definition for a Tasks-RCU-like mechanism. - * @cbs_head: Head of callback list. - * @cbs_tail: Tail pointer for callback list. - * @cbs_wq: Wait queue allowning new callback to get kthread's attention. - * @cbs_lock: Lock protecting callback list. - * @kthread_ptr: This flavor's grace-period/callback-invocation kthread. - * @gp_func: This flavor's grace-period-wait function. - * @pregp_func: This flavor's pre-grace-period function (optional). - * @pertask_func: This flavor's per-task scan function (optional). - * @postscan_func: This flavor's post-task scan function (optional). - * @holdout_func: This flavor's holdout-list scan function (optional). - * @postgp_func: This flavor's post-grace-period function (optional). - * @call_func: This flavor's call_rcu()-equivalent function. - * @name: This flavor's textual name. - * @kname: This flavor's kthread name. - */ -struct rcu_tasks { - struct rcu_head *cbs_head; - struct rcu_head **cbs_tail; - struct wait_queue_head cbs_wq; - raw_spinlock_t cbs_lock; - unsigned long gp_start; - struct task_struct *kthread_ptr; - rcu_tasks_gp_func_t gp_func; - pregp_func_t pregp_func; - pertask_func_t pertask_func; - postscan_func_t postscan_func; - holdouts_func_t holdouts_func; - postgp_func_t postgp_func; - call_rcu_func_t call_func; - char *name; - char *kname; -}; - -#define DEFINE_RCU_TASKS(rt_name, gp, call, n) \ -static struct rcu_tasks rt_name = \ -{ \ - .cbs_tail = &rt_name.cbs_head, \ - .cbs_wq = __WAIT_QUEUE_HEAD_INITIALIZER(rt_name.cbs_wq), \ - .cbs_lock = __RAW_SPIN_LOCK_UNLOCKED(rt_name.cbs_lock), \ - .gp_func = gp, \ - .call_func = call, \ - .name = n, \ - .kname = #rt_name, \ -} - -/* Track exiting tasks in order to allow them to be waited for. */ -DEFINE_STATIC_SRCU(tasks_rcu_exit_srcu); - -/* Avoid IPIing CPUs early in the grace period. */ -#define RCU_TASK_IPI_DELAY (IS_ENABLED(CONFIG_TASKS_TRACE_RCU_READ_MB) ? HZ / 2 : 0) -static int rcu_task_ipi_delay __read_mostly = RCU_TASK_IPI_DELAY; -module_param(rcu_task_ipi_delay, int, 0644); - -/* Control stall timeouts. Disable with <= 0, otherwise jiffies till stall. */ -#define RCU_TASK_STALL_TIMEOUT (HZ * 60 * 10) -static int rcu_task_stall_timeout __read_mostly = RCU_TASK_STALL_TIMEOUT; -module_param(rcu_task_stall_timeout, int, 0644); - -//////////////////////////////////////////////////////////////////////// -// -// Generic code. - -// Enqueue a callback for the specified flavor of Tasks RCU. -static void call_rcu_tasks_generic(struct rcu_head *rhp, rcu_callback_t func, - struct rcu_tasks *rtp) -{ - unsigned long flags; - bool needwake; - - rhp->next = NULL; - rhp->func = func; - raw_spin_lock_irqsave(&rtp->cbs_lock, flags); - needwake = !rtp->cbs_head; - WRITE_ONCE(*rtp->cbs_tail, rhp); - rtp->cbs_tail = &rhp->next; - raw_spin_unlock_irqrestore(&rtp->cbs_lock, flags); - /* We can't create the thread unless interrupts are enabled. */ - if (needwake && READ_ONCE(rtp->kthread_ptr)) - wake_up(&rtp->cbs_wq); -} - -// Wait for a grace period for the specified flavor of Tasks RCU. -static void synchronize_rcu_tasks_generic(struct rcu_tasks *rtp) -{ - /* Complain if the scheduler has not started. */ - RCU_LOCKDEP_WARN(rcu_scheduler_active == RCU_SCHEDULER_INACTIVE, - "synchronize_rcu_tasks called too soon"); - - /* Wait for the grace period. */ - wait_rcu_gp(rtp->call_func); -} - -/* RCU-tasks kthread that detects grace periods and invokes callbacks. */ -static int __noreturn rcu_tasks_kthread(void *arg) -{ - unsigned long flags; - struct rcu_head *list; - struct rcu_head *next; - struct rcu_tasks *rtp = arg; - - /* Run on housekeeping CPUs by default. Sysadm can move if desired. */ - housekeeping_affine(current, HK_FLAG_RCU); - WRITE_ONCE(rtp->kthread_ptr, current); // Let GPs start! - - /* - * Each pass through the following loop makes one check for - * newly arrived callbacks, and, if there are some, waits for - * one RCU-tasks grace period and then invokes the callbacks. - * This loop is terminated by the system going down. ;-) - */ - for (;;) { - - /* Pick up any new callbacks. */ - raw_spin_lock_irqsave(&rtp->cbs_lock, flags); - smp_mb__after_unlock_lock(); // Order updates vs. GP. - list = rtp->cbs_head; - rtp->cbs_head = NULL; - rtp->cbs_tail = &rtp->cbs_head; - raw_spin_unlock_irqrestore(&rtp->cbs_lock, flags); - - /* If there were none, wait a bit and start over. */ - if (!list) { - wait_event_interruptible(rtp->cbs_wq, - READ_ONCE(rtp->cbs_head)); - if (!rtp->cbs_head) { - WARN_ON(signal_pending(current)); - schedule_timeout_interruptible(HZ/10); - } - continue; - } - - // Wait for one grace period. - rtp->gp_start = jiffies; - rtp->gp_func(rtp); - - /* Invoke the callbacks. */ - while (list) { - next = list->next; - local_bh_disable(); - list->func(list); - local_bh_enable(); - list = next; - cond_resched(); - } - /* Paranoid sleep to keep this from entering a tight loop */ - schedule_timeout_uninterruptible(HZ/10); - } -} - -/* Spawn RCU-tasks grace-period kthread, e.g., at core_initcall() time. */ -static void __init rcu_spawn_tasks_kthread_generic(struct rcu_tasks *rtp) -{ - struct task_struct *t; - - t = kthread_run(rcu_tasks_kthread, rtp, "%s_kthread", rtp->kname); - if (WARN_ONCE(IS_ERR(t), "%s: Could not start %s grace-period kthread, OOM is now expected behavior\n", __func__, rtp->name)) - return; - smp_mb(); /* Ensure others see full kthread. */ -} - -/* Do the srcu_read_lock() for the above synchronize_srcu(). */ -void exit_tasks_rcu_start(void) __acquires(&tasks_rcu_exit_srcu) -{ - preempt_disable(); - current->rcu_tasks_idx = __srcu_read_lock(&tasks_rcu_exit_srcu); - preempt_enable(); -} - -static void exit_tasks_rcu_finish_trace(struct task_struct *t); - -/* Do the srcu_read_unlock() for the above synchronize_srcu(). */ -void exit_tasks_rcu_finish(void) __releases(&tasks_rcu_exit_srcu) -{ - struct task_struct *t = current; - - preempt_disable(); - __srcu_read_unlock(&tasks_rcu_exit_srcu, t->rcu_tasks_idx); - preempt_enable(); - exit_tasks_rcu_finish_trace(t); -} - -#ifndef CONFIG_TINY_RCU - -/* - * Print any non-default Tasks RCU settings. - */ -static void __init rcu_tasks_bootup_oddness(void) -{ -#if defined(CONFIG_TASKS_RCU) || defined(CONFIG_TASKS_TRACE_RCU) - if (rcu_task_stall_timeout != RCU_TASK_STALL_TIMEOUT) - pr_info("\tTasks-RCU CPU stall warnings timeout set to %d (rcu_task_stall_timeout).\n", rcu_task_stall_timeout); -#endif /* #ifdef CONFIG_TASKS_RCU */ -#ifdef CONFIG_TASKS_RCU - pr_info("\tTrampoline variant of Tasks RCU enabled.\n"); -#endif /* #ifdef CONFIG_TASKS_RCU */ -#ifdef CONFIG_TASKS_RUDE_RCU - pr_info("\tRude variant of Tasks RCU enabled.\n"); -#endif /* #ifdef CONFIG_TASKS_RUDE_RCU */ -#ifdef CONFIG_TASKS_TRACE_RCU - pr_info("\tTracing variant of Tasks RCU enabled.\n"); -#endif /* #ifdef CONFIG_TASKS_TRACE_RCU */ -} - -#endif /* #ifndef CONFIG_TINY_RCU */ - -#ifdef CONFIG_TASKS_RCU - -//////////////////////////////////////////////////////////////////////// -// -// Shared code between task-list-scanning variants of Tasks RCU. - -/* Wait for one RCU-tasks grace period. */ -static void rcu_tasks_wait_gp(struct rcu_tasks *rtp) -{ - struct task_struct *g, *t; - unsigned long lastreport; - LIST_HEAD(holdouts); - int fract; - - rtp->pregp_func(); - - /* - * There were callbacks, so we need to wait for an RCU-tasks - * grace period. Start off by scanning the task list for tasks - * that are not already voluntarily blocked. Mark these tasks - * and make a list of them in holdouts. - */ - rcu_read_lock(); - for_each_process_thread(g, t) - rtp->pertask_func(t, &holdouts); - rcu_read_unlock(); - - rtp->postscan_func(); - - /* - * Each pass through the following loop scans the list of holdout - * tasks, removing any that are no longer holdouts. When the list - * is empty, we are done. - */ - lastreport = jiffies; - - /* Start off with HZ/10 wait and slowly back off to 1 HZ wait. */ - fract = 10; - - for (;;) { - bool firstreport; - bool needreport; - int rtst; - - if (list_empty(&holdouts)) - break; - - /* Slowly back off waiting for holdouts */ - schedule_timeout_interruptible(HZ/fract); - - if (fract > 1) - fract--; - - rtst = READ_ONCE(rcu_task_stall_timeout); - needreport = rtst > 0 && time_after(jiffies, lastreport + rtst); - if (needreport) - lastreport = jiffies; - firstreport = true; - WARN_ON(signal_pending(current)); - rtp->holdouts_func(&holdouts, needreport, &firstreport); - } - - rtp->postgp_func(); -} - -//////////////////////////////////////////////////////////////////////// -// -// Simple variant of RCU whose quiescent states are voluntary context -// switch, cond_resched_rcu_qs(), user-space execution, and idle. -// As such, grace periods can take one good long time. There are no -// read-side primitives similar to rcu_read_lock() and rcu_read_unlock() -// because this implementation is intended to get the system into a safe -// state for some of the manipulations involved in tracing and the like. -// Finally, this implementation does not support high call_rcu_tasks() -// rates from multiple CPUs. If this is required, per-CPU callback lists -// will be needed. - -/* Pre-grace-period preparation. */ -static void rcu_tasks_pregp_step(void) -{ - /* - * Wait for all pre-existing t->on_rq and t->nvcsw transitions - * to complete. Invoking synchronize_rcu() suffices because all - * these transitions occur with interrupts disabled. Without this - * synchronize_rcu(), a read-side critical section that started - * before the grace period might be incorrectly seen as having - * started after the grace period. - * - * This synchronize_rcu() also dispenses with the need for a - * memory barrier on the first store to t->rcu_tasks_holdout, - * as it forces the store to happen after the beginning of the - * grace period. - */ - synchronize_rcu(); -} - -/* Per-task initial processing. */ -static void rcu_tasks_pertask(struct task_struct *t, struct list_head *hop) -{ - if (t != current && READ_ONCE(t->on_rq) && !is_idle_task(t)) { - get_task_struct(t); - t->rcu_tasks_nvcsw = READ_ONCE(t->nvcsw); - WRITE_ONCE(t->rcu_tasks_holdout, true); - list_add(&t->rcu_tasks_holdout_list, hop); - } -} - -/* Processing between scanning taskslist and draining the holdout list. */ -void rcu_tasks_postscan(void) -{ - /* - * Wait for tasks that are in the process of exiting. This - * does only part of the job, ensuring that all tasks that were - * previously exiting reach the point where they have disabled - * preemption, allowing the later synchronize_rcu() to finish - * the job. - */ - synchronize_srcu(&tasks_rcu_exit_srcu); -} - -/* See if tasks are still holding out, complain if so. */ -static void check_holdout_task(struct task_struct *t, - bool needreport, bool *firstreport) -{ - int cpu; - - if (!READ_ONCE(t->rcu_tasks_holdout) || - t->rcu_tasks_nvcsw != READ_ONCE(t->nvcsw) || - !READ_ONCE(t->on_rq) || - (IS_ENABLED(CONFIG_NO_HZ_FULL) && - !is_idle_task(t) && t->rcu_tasks_idle_cpu >= 0)) { - WRITE_ONCE(t->rcu_tasks_holdout, false); - list_del_init(&t->rcu_tasks_holdout_list); - put_task_struct(t); - return; - } - rcu_request_urgent_qs_task(t); - if (!needreport) - return; - if (*firstreport) { - pr_err("INFO: rcu_tasks detected stalls on tasks:\n"); - *firstreport = false; - } - cpu = task_cpu(t); - pr_alert("%p: %c%c nvcsw: %lu/%lu holdout: %d idle_cpu: %d/%d\n", - t, ".I"[is_idle_task(t)], - "N."[cpu < 0 || !tick_nohz_full_cpu(cpu)], - t->rcu_tasks_nvcsw, t->nvcsw, t->rcu_tasks_holdout, - t->rcu_tasks_idle_cpu, cpu); - sched_show_task(t); -} - -/* Scan the holdout lists for tasks no longer holding out. */ -static void check_all_holdout_tasks(struct list_head *hop, - bool needreport, bool *firstreport) -{ - struct task_struct *t, *t1; - - list_for_each_entry_safe(t, t1, hop, rcu_tasks_holdout_list) { - check_holdout_task(t, needreport, firstreport); - cond_resched(); - } -} - -/* Finish off the Tasks-RCU grace period. */ -static void rcu_tasks_postgp(void) -{ - /* - * Because ->on_rq and ->nvcsw are not guaranteed to have a full - * memory barriers prior to them in the schedule() path, memory - * reordering on other CPUs could cause their RCU-tasks read-side - * critical sections to extend past the end of the grace period. - * However, because these ->nvcsw updates are carried out with - * interrupts disabled, we can use synchronize_rcu() to force the - * needed ordering on all such CPUs. - * - * This synchronize_rcu() also confines all ->rcu_tasks_holdout - * accesses to be within the grace period, avoiding the need for - * memory barriers for ->rcu_tasks_holdout accesses. - * - * In addition, this synchronize_rcu() waits for exiting tasks - * to complete their final preempt_disable() region of execution, - * cleaning up after the synchronize_srcu() above. - */ - synchronize_rcu(); -} - -void call_rcu_tasks(struct rcu_head *rhp, rcu_callback_t func); -DEFINE_RCU_TASKS(rcu_tasks, rcu_tasks_wait_gp, call_rcu_tasks, "RCU Tasks"); - -/** - * call_rcu_tasks() - Queue an RCU for invocation task-based grace period - * @rhp: structure to be used for queueing the RCU updates. - * @func: actual callback function to be invoked after the grace period - * - * The callback function will be invoked some time after a full grace - * period elapses, in other words after all currently executing RCU - * read-side critical sections have completed. call_rcu_tasks() assumes - * that the read-side critical sections end at a voluntary context - * switch (not a preemption!), cond_resched_rcu_qs(), entry into idle, - * or transition to usermode execution. As such, there are no read-side - * primitives analogous to rcu_read_lock() and rcu_read_unlock() because - * this primitive is intended to determine that all tasks have passed - * through a safe state, not so much for data-strcuture synchronization. - * - * See the description of call_rcu() for more detailed information on - * memory ordering guarantees. - */ -void call_rcu_tasks(struct rcu_head *rhp, rcu_callback_t func) -{ - call_rcu_tasks_generic(rhp, func, &rcu_tasks); -} -EXPORT_SYMBOL_GPL(call_rcu_tasks); - -/** - * synchronize_rcu_tasks - wait until an rcu-tasks grace period has elapsed. - * - * Control will return to the caller some time after a full rcu-tasks - * grace period has elapsed, in other words after all currently - * executing rcu-tasks read-side critical sections have elapsed. These - * read-side critical sections are delimited by calls to schedule(), - * cond_resched_tasks_rcu_qs(), idle execution, userspace execution, calls - * to synchronize_rcu_tasks(), and (in theory, anyway) cond_resched(). - * - * This is a very specialized primitive, intended only for a few uses in - * tracing and other situations requiring manipulation of function - * preambles and profiling hooks. The synchronize_rcu_tasks() function - * is not (yet) intended for heavy use from multiple CPUs. - * - * See the description of synchronize_rcu() for more detailed information - * on memory ordering guarantees. - */ -void synchronize_rcu_tasks(void) -{ - synchronize_rcu_tasks_generic(&rcu_tasks); -} -EXPORT_SYMBOL_GPL(synchronize_rcu_tasks); - -/** - * rcu_barrier_tasks - Wait for in-flight call_rcu_tasks() callbacks. - * - * Although the current implementation is guaranteed to wait, it is not - * obligated to, for example, if there are no pending callbacks. - */ -void rcu_barrier_tasks(void) -{ - /* There is only one callback queue, so this is easy. ;-) */ - synchronize_rcu_tasks(); -} -EXPORT_SYMBOL_GPL(rcu_barrier_tasks); - -static int __init rcu_spawn_tasks_kthread(void) -{ - rcu_tasks.pregp_func = rcu_tasks_pregp_step; - rcu_tasks.pertask_func = rcu_tasks_pertask; - rcu_tasks.postscan_func = rcu_tasks_postscan; - rcu_tasks.holdouts_func = check_all_holdout_tasks; - rcu_tasks.postgp_func = rcu_tasks_postgp; - rcu_spawn_tasks_kthread_generic(&rcu_tasks); - return 0; -} -core_initcall(rcu_spawn_tasks_kthread); - -#endif /* #ifdef CONFIG_TASKS_RCU */ - -#ifdef CONFIG_TASKS_RUDE_RCU - -//////////////////////////////////////////////////////////////////////// -// -// "Rude" variant of Tasks RCU, inspired by Steve Rostedt's trick of -// passing an empty function to schedule_on_each_cpu(). This approach -// provides an asynchronous call_rcu_tasks_rude() API and batching -// of concurrent calls to the synchronous synchronize_rcu_rude() API. -// This sends IPIs far and wide and induces otherwise unnecessary context -// switches on all online CPUs, whether idle or not. - -// Empty function to allow workqueues to force a context switch. -static void rcu_tasks_be_rude(struct work_struct *work) -{ -} - -// Wait for one rude RCU-tasks grace period. -static void rcu_tasks_rude_wait_gp(struct rcu_tasks *rtp) -{ - schedule_on_each_cpu(rcu_tasks_be_rude); -} - -void call_rcu_tasks_rude(struct rcu_head *rhp, rcu_callback_t func); -DEFINE_RCU_TASKS(rcu_tasks_rude, rcu_tasks_rude_wait_gp, call_rcu_tasks_rude, - "RCU Tasks Rude"); - -/** - * call_rcu_tasks_rude() - Queue a callback rude task-based grace period - * @rhp: structure to be used for queueing the RCU updates. - * @func: actual callback function to be invoked after the grace period - * - * The callback function will be invoked some time after a full grace - * period elapses, in other words after all currently executing RCU - * read-side critical sections have completed. call_rcu_tasks_rude() - * assumes that the read-side critical sections end at context switch, - * cond_resched_rcu_qs(), or transition to usermode execution. As such, - * there are no read-side primitives analogous to rcu_read_lock() and - * rcu_read_unlock() because this primitive is intended to determine - * that all tasks have passed through a safe state, not so much for - * data-strcuture synchronization. - * - * See the description of call_rcu() for more detailed information on - * memory ordering guarantees. - */ -void call_rcu_tasks_rude(struct rcu_head *rhp, rcu_callback_t func) -{ - call_rcu_tasks_generic(rhp, func, &rcu_tasks_rude); -} -EXPORT_SYMBOL_GPL(call_rcu_tasks_rude); - -/** - * synchronize_rcu_tasks_rude - wait for a rude rcu-tasks grace period - * - * Control will return to the caller some time after a rude rcu-tasks - * grace period has elapsed, in other words after all currently - * executing rcu-tasks read-side critical sections have elapsed. These - * read-side critical sections are delimited by calls to schedule(), - * cond_resched_tasks_rcu_qs(), userspace execution, and (in theory, - * anyway) cond_resched(). - * - * This is a very specialized primitive, intended only for a few uses in - * tracing and other situations requiring manipulation of function preambles - * and profiling hooks. The synchronize_rcu_tasks_rude() function is not - * (yet) intended for heavy use from multiple CPUs. - * - * See the description of synchronize_rcu() for more detailed information - * on memory ordering guarantees. - */ -void synchronize_rcu_tasks_rude(void) -{ - synchronize_rcu_tasks_generic(&rcu_tasks_rude); -} -EXPORT_SYMBOL_GPL(synchronize_rcu_tasks_rude); - -/** - * rcu_barrier_tasks_rude - Wait for in-flight call_rcu_tasks_rude() callbacks. - * - * Although the current implementation is guaranteed to wait, it is not - * obligated to, for example, if there are no pending callbacks. - */ -void rcu_barrier_tasks_rude(void) -{ - /* There is only one callback queue, so this is easy. ;-) */ - synchronize_rcu_tasks_rude(); -} -EXPORT_SYMBOL_GPL(rcu_barrier_tasks_rude); - -static int __init rcu_spawn_tasks_rude_kthread(void) -{ - rcu_spawn_tasks_kthread_generic(&rcu_tasks_rude); - return 0; -} -core_initcall(rcu_spawn_tasks_rude_kthread); - -#endif /* #ifdef CONFIG_TASKS_RUDE_RCU */ - -//////////////////////////////////////////////////////////////////////// -// -// Tracing variant of Tasks RCU. This variant is designed to be used -// to protect tracing hooks, including those of BPF. This variant -// therefore: -// -// 1. Has explicit read-side markers to allow finite grace periods -// in the face of in-kernel loops for PREEMPT=n builds. -// -// 2. Protects code in the idle loop, exception entry/exit, and -// CPU-hotplug code paths, similar to the capabilities of SRCU. -// -// 3. Avoids expensive read-side instruction, having overhead similar -// to that of Preemptible RCU. -// -// There are of course downsides. The grace-period code can send IPIs to -// CPUs, even when those CPUs are in the idle loop or in nohz_full userspace. -// It is necessary to scan the full tasklist, much as for Tasks RCU. There -// is a single callback queue guarded by a single lock, again, much as for -// Tasks RCU. If needed, these downsides can be at least partially remedied. -// -// Perhaps most important, this variant of RCU does not affect the vanilla -// flavors, rcu_preempt and rcu_sched. The fact that RCU Tasks Trace -// readers can operate from idle, offline, and exception entry/exit in no -// way allows rcu_preempt and rcu_sched readers to also do so. - -// The lockdep state must be outside of #ifdef to be useful. -#ifdef CONFIG_DEBUG_LOCK_ALLOC -static struct lock_class_key rcu_lock_trace_key; -struct lockdep_map rcu_trace_lock_map = - STATIC_LOCKDEP_MAP_INIT("rcu_read_lock_trace", &rcu_lock_trace_key); -EXPORT_SYMBOL_GPL(rcu_trace_lock_map); -#endif /* #ifdef CONFIG_DEBUG_LOCK_ALLOC */ - -#ifdef CONFIG_TASKS_TRACE_RCU - -atomic_t trc_n_readers_need_end; // Number of waited-for readers. -DECLARE_WAIT_QUEUE_HEAD(trc_wait); // List of holdout tasks. - -// Record outstanding IPIs to each CPU. No point in sending two... -static DEFINE_PER_CPU(bool, trc_ipi_to_cpu); - -void call_rcu_tasks_trace(struct rcu_head *rhp, rcu_callback_t func); -DEFINE_RCU_TASKS(rcu_tasks_trace, rcu_tasks_wait_gp, call_rcu_tasks_trace, - "RCU Tasks Trace"); - -/* If we are the last reader, wake up the grace-period kthread. */ -void rcu_read_unlock_trace_special(struct task_struct *t) -{ - WRITE_ONCE(t->trc_reader_need_end, false); - if (atomic_dec_and_test(&trc_n_readers_need_end)) - wake_up(&trc_wait); -} -EXPORT_SYMBOL_GPL(rcu_read_unlock_trace_special); - -/* Add a task to the holdout list, if it is not already on the list. */ -static void trc_add_holdout(struct task_struct *t, struct list_head *bhp) -{ - if (list_empty(&t->trc_holdout_list)) { - get_task_struct(t); - list_add(&t->trc_holdout_list, bhp); - } -} - -/* Remove a task from the holdout list, if it is in fact present. */ -static void trc_del_holdout(struct task_struct *t) -{ - if (!list_empty(&t->trc_holdout_list)) { - list_del_init(&t->trc_holdout_list); - put_task_struct(t); - } -} - -/* IPI handler to check task state. */ -static void trc_read_check_handler(void *t_in) -{ - struct task_struct *t = current; - struct task_struct *texp = t_in; - - // If the task is no longer running on this CPU, leave. - if (unlikely(texp != t)) { - if (WARN_ON_ONCE(atomic_dec_and_test(&trc_n_readers_need_end))) - wake_up(&trc_wait); - goto reset_ipi; // Already on holdout list, so will check later. - } - - // If the task is not in a read-side critical section, and - // if this is the last reader, awaken the grace-period kthread. - if (likely(!t->trc_reader_nesting)) { - if (WARN_ON_ONCE(atomic_dec_and_test(&trc_n_readers_need_end))) - wake_up(&trc_wait); - // Mark as checked after decrement to avoid false - // positives on the above WARN_ON_ONCE(). - WRITE_ONCE(t->trc_reader_checked, true); - goto reset_ipi; - } - WRITE_ONCE(t->trc_reader_checked, true); - - // Get here if the task is in a read-side critical section. Set - // its state so that it will awaken the grace-period kthread upon - // exit from that critical section. - WARN_ON_ONCE(t->trc_reader_need_end); - WRITE_ONCE(t->trc_reader_need_end, true); - -reset_ipi: - // Allow future IPIs to be sent on CPU and for task. - // Also order this IPI handler against any later manipulations of - // the intended task. - smp_store_release(&per_cpu(trc_ipi_to_cpu, smp_processor_id()), false); // ^^^ - smp_store_release(&texp->trc_ipi_to_cpu, -1); // ^^^ -} - -/* Callback function for scheduler to check locked-down task. */ -static bool trc_inspect_reader(struct task_struct *t, void *arg) -{ - if (task_curr(t)) - return false; // It is running, so decline to inspect it. - - // Mark as checked. Because this is called from the grace-period - // kthread, also remove the task from the holdout list. - t->trc_reader_checked = true; - trc_del_holdout(t); - - // If the task is in a read-side critical section, set up its - // its state so that it will awaken the grace-period kthread upon - // exit from that critical section. - if (unlikely(t->trc_reader_nesting)) { - atomic_inc(&trc_n_readers_need_end); // One more to wait on. - WARN_ON_ONCE(t->trc_reader_need_end); - WRITE_ONCE(t->trc_reader_need_end, true); - } - return true; -} - -/* Attempt to extract the state for the specified task. */ -static void trc_wait_for_one_reader(struct task_struct *t, - struct list_head *bhp) -{ - int cpu; - - // If a previous IPI is still in flight, let it complete. - if (smp_load_acquire(&t->trc_ipi_to_cpu) != -1) // Order IPI - return; - - // The current task had better be in a quiescent state. - if (t == current) { - t->trc_reader_checked = true; - trc_del_holdout(t); - WARN_ON_ONCE(t->trc_reader_nesting); - return; - } - - // Attempt to nail down the task for inspection. - get_task_struct(t); - if (try_invoke_on_locked_down_task(t, trc_inspect_reader, NULL)) { - put_task_struct(t); - return; - } - put_task_struct(t); - - // If currently running, send an IPI, either way, add to list. - trc_add_holdout(t, bhp); - if (task_curr(t) && - time_after(jiffies + 1, rcu_tasks_trace.gp_start + rcu_task_ipi_delay)) { - // The task is currently running, so try IPIing it. - cpu = task_cpu(t); - - // If there is already an IPI outstanding, let it happen. - if (per_cpu(trc_ipi_to_cpu, cpu) || t->trc_ipi_to_cpu >= 0) - return; - - atomic_inc(&trc_n_readers_need_end); - per_cpu(trc_ipi_to_cpu, cpu) = true; - t->trc_ipi_to_cpu = cpu; - if (smp_call_function_single(cpu, - trc_read_check_handler, t, 0)) { - // Just in case there is some other reason for - // failure than the target CPU being offline. - per_cpu(trc_ipi_to_cpu, cpu) = false; - t->trc_ipi_to_cpu = cpu; - if (atomic_dec_and_test(&trc_n_readers_need_end)) { - WARN_ON_ONCE(1); - wake_up(&trc_wait); - } - } - } -} - -/* Initialize for a new RCU-tasks-trace grace period. */ -static void rcu_tasks_trace_pregp_step(void) -{ - int cpu; - - // Wait for CPU-hotplug paths to complete. - cpus_read_lock(); - cpus_read_unlock(); - - // Allow for fast-acting IPIs. - atomic_set(&trc_n_readers_need_end, 1); - - // There shouldn't be any old IPIs, but... - for_each_possible_cpu(cpu) - WARN_ON_ONCE(per_cpu(trc_ipi_to_cpu, cpu)); -} - -/* Do first-round processing for the specified task. */ -static void rcu_tasks_trace_pertask(struct task_struct *t, - struct list_head *hop) -{ - WRITE_ONCE(t->trc_reader_need_end, false); - t->trc_reader_checked = false; - t->trc_ipi_to_cpu = -1; - trc_wait_for_one_reader(t, hop); -} - -/* Do intermediate processing between task and holdout scans. */ -static void rcu_tasks_trace_postscan(void) -{ - // Wait for late-stage exiting tasks to finish exiting. - // These might have passed the call to exit_tasks_rcu_finish(). - synchronize_rcu(); - // Any tasks that exit after this point will set ->trc_reader_checked. -} - -/* Do one scan of the holdout list. */ -static void check_all_holdout_tasks_trace(struct list_head *hop, - bool ndrpt, bool *frptp) -{ - struct task_struct *g, *t; - - list_for_each_entry_safe(t, g, hop, trc_holdout_list) { - // If safe and needed, try to check the current task. - if (READ_ONCE(t->trc_ipi_to_cpu) == -1 && - !READ_ONCE(t->trc_reader_checked)) - trc_wait_for_one_reader(t, hop); - - // If check succeeded, remove this task from the list. - if (READ_ONCE(t->trc_reader_checked)) - trc_del_holdout(t); - } -} - -/* Wait for grace period to complete and provide ordering. */ -static void rcu_tasks_trace_postgp(void) -{ - // Remove the safety count. - smp_mb__before_atomic(); // Order vs. earlier atomics - atomic_dec(&trc_n_readers_need_end); - smp_mb__after_atomic(); // Order vs. later atomics - - // Wait for readers. - wait_event_idle_exclusive(trc_wait, - atomic_read(&trc_n_readers_need_end) == 0); - - smp_mb(); // Caller's code must be ordered after wakeup. -} - -/* Report any needed quiescent state for this exiting task. */ -void exit_tasks_rcu_finish_trace(struct task_struct *t) -{ - WRITE_ONCE(t->trc_reader_checked, true); - WARN_ON_ONCE(t->trc_reader_nesting); - WRITE_ONCE(t->trc_reader_nesting, 0); - if (WARN_ON_ONCE(READ_ONCE(t->trc_reader_need_end))) - rcu_read_unlock_trace_special(t); -} - -/** - * call_rcu_tasks_trace() - Queue a callback trace task-based grace period - * @rhp: structure to be used for queueing the RCU updates. - * @func: actual callback function to be invoked after the grace period - * - * The callback function will be invoked some time after a full grace - * period elapses, in other words after all currently executing RCU - * read-side critical sections have completed. call_rcu_tasks_trace() - * assumes that the read-side critical sections end at context switch, - * cond_resched_rcu_qs(), or transition to usermode execution. As such, - * there are no read-side primitives analogous to rcu_read_lock() and - * rcu_read_unlock() because this primitive is intended to determine - * that all tasks have passed through a safe state, not so much for - * data-strcuture synchronization. - * - * See the description of call_rcu() for more detailed information on - * memory ordering guarantees. - */ -void call_rcu_tasks_trace(struct rcu_head *rhp, rcu_callback_t func) -{ - call_rcu_tasks_generic(rhp, func, &rcu_tasks_trace); -} -EXPORT_SYMBOL_GPL(call_rcu_tasks_trace); - -/** - * synchronize_rcu_tasks_trace - wait for a trace rcu-tasks grace period - * - * Control will return to the caller some time after a trace rcu-tasks - * grace period has elapsed, in other words after all currently - * executing rcu-tasks read-side critical sections have elapsed. These - * read-side critical sections are delimited by calls to schedule(), - * cond_resched_tasks_rcu_qs(), userspace execution, and (in theory, - * anyway) cond_resched(). - * - * This is a very specialized primitive, intended only for a few uses in - * tracing and other situations requiring manipulation of function preambles - * and profiling hooks. The synchronize_rcu_tasks_trace() function is not - * (yet) intended for heavy use from multiple CPUs. - * - * See the description of synchronize_rcu() for more detailed information - * on memory ordering guarantees. - */ -void synchronize_rcu_tasks_trace(void) -{ - RCU_LOCKDEP_WARN(lock_is_held(&rcu_trace_lock_map), "Illegal synchronize_rcu_tasks_trace() in RCU Tasks Trace read-side critical section"); - synchronize_rcu_tasks_generic(&rcu_tasks_trace); -} -EXPORT_SYMBOL_GPL(synchronize_rcu_tasks_trace); - -/** - * rcu_barrier_tasks_trace - Wait for in-flight call_rcu_tasks_trace() callbacks. - * - * Although the current implementation is guaranteed to wait, it is not - * obligated to, for example, if there are no pending callbacks. - */ -void rcu_barrier_tasks_trace(void) -{ - /* There is only one callback queue, so this is easy. ;-) */ - synchronize_rcu_tasks_trace(); -} -EXPORT_SYMBOL_GPL(rcu_barrier_tasks_trace); - -static int __init rcu_spawn_tasks_trace_kthread(void) -{ - rcu_tasks_trace.pregp_func = rcu_tasks_trace_pregp_step; - rcu_tasks_trace.pertask_func = rcu_tasks_trace_pertask; - rcu_tasks_trace.postscan_func = rcu_tasks_trace_postscan; - rcu_tasks_trace.holdouts_func = check_all_holdout_tasks_trace; - rcu_tasks_trace.postgp_func = rcu_tasks_trace_postgp; - rcu_spawn_tasks_kthread_generic(&rcu_tasks_trace); - return 0; -} -core_initcall(rcu_spawn_tasks_trace_kthread); - -#else /* #ifdef CONFIG_TASKS_TRACE_RCU */ -void exit_tasks_rcu_finish_trace(struct task_struct *t) { } -#endif /* #else #ifdef CONFIG_TASKS_TRACE_RCU */ diff --git a/kernel/rcu/update.c b/kernel/rcu/update.c index 542a27f1134a..1861103662db 100644 --- a/kernel/rcu/update.c +++ b/kernel/rcu/update.c @@ -471,6 +471,370 @@ int rcu_cpu_stall_timeout __read_mostly = CONFIG_RCU_CPU_STALL_TIMEOUT; module_param(rcu_cpu_stall_timeout, int, 0644); #endif /* #ifdef CONFIG_RCU_STALL_COMMON */ +#ifdef CONFIG_TASKS_RCU + +/* + * Simple variant of RCU whose quiescent states are voluntary context + * switch, cond_resched_rcu_qs(), user-space execution, and idle. + * As such, grace periods can take one good long time. There are no + * read-side primitives similar to rcu_read_lock() and rcu_read_unlock() + * because this implementation is intended to get the system into a safe + * state for some of the manipulations involved in tracing and the like. + * Finally, this implementation does not support high call_rcu_tasks() + * rates from multiple CPUs. If this is required, per-CPU callback lists + * will be needed. + */ + +/* Global list of callbacks and associated lock. */ +static struct rcu_head *rcu_tasks_cbs_head; +static struct rcu_head **rcu_tasks_cbs_tail = &rcu_tasks_cbs_head; +static DECLARE_WAIT_QUEUE_HEAD(rcu_tasks_cbs_wq); +static DEFINE_RAW_SPINLOCK(rcu_tasks_cbs_lock); + +/* Track exiting tasks in order to allow them to be waited for. */ +DEFINE_STATIC_SRCU(tasks_rcu_exit_srcu); + +/* Control stall timeouts. Disable with <= 0, otherwise jiffies till stall. */ +#define RCU_TASK_STALL_TIMEOUT (HZ * 60 * 10) +static int rcu_task_stall_timeout __read_mostly = RCU_TASK_STALL_TIMEOUT; +module_param(rcu_task_stall_timeout, int, 0644); + +static struct task_struct *rcu_tasks_kthread_ptr; + +/** + * call_rcu_tasks() - Queue an RCU for invocation task-based grace period + * @rhp: structure to be used for queueing the RCU updates. + * @func: actual callback function to be invoked after the grace period + * + * The callback function will be invoked some time after a full grace + * period elapses, in other words after all currently executing RCU + * read-side critical sections have completed. call_rcu_tasks() assumes + * that the read-side critical sections end at a voluntary context + * switch (not a preemption!), cond_resched_rcu_qs(), entry into idle, + * or transition to usermode execution. As such, there are no read-side + * primitives analogous to rcu_read_lock() and rcu_read_unlock() because + * this primitive is intended to determine that all tasks have passed + * through a safe state, not so much for data-strcuture synchronization. + * + * See the description of call_rcu() for more detailed information on + * memory ordering guarantees. + */ +void call_rcu_tasks(struct rcu_head *rhp, rcu_callback_t func) +{ + unsigned long flags; + bool needwake; + + rhp->next = NULL; + rhp->func = func; + raw_spin_lock_irqsave(&rcu_tasks_cbs_lock, flags); + needwake = !rcu_tasks_cbs_head; + *rcu_tasks_cbs_tail = rhp; + rcu_tasks_cbs_tail = &rhp->next; + raw_spin_unlock_irqrestore(&rcu_tasks_cbs_lock, flags); + /* We can't create the thread unless interrupts are enabled. */ + if (needwake && READ_ONCE(rcu_tasks_kthread_ptr)) + wake_up(&rcu_tasks_cbs_wq); +} +EXPORT_SYMBOL_GPL(call_rcu_tasks); + +/** + * synchronize_rcu_tasks - wait until an rcu-tasks grace period has elapsed. + * + * Control will return to the caller some time after a full rcu-tasks + * grace period has elapsed, in other words after all currently + * executing rcu-tasks read-side critical sections have elapsed. These + * read-side critical sections are delimited by calls to schedule(), + * cond_resched_tasks_rcu_qs(), idle execution, userspace execution, calls + * to synchronize_rcu_tasks(), and (in theory, anyway) cond_resched(). + * + * This is a very specialized primitive, intended only for a few uses in + * tracing and other situations requiring manipulation of function + * preambles and profiling hooks. The synchronize_rcu_tasks() function + * is not (yet) intended for heavy use from multiple CPUs. + * + * Note that this guarantee implies further memory-ordering guarantees. + * On systems with more than one CPU, when synchronize_rcu_tasks() returns, + * each CPU is guaranteed to have executed a full memory barrier since the + * end of its last RCU-tasks read-side critical section whose beginning + * preceded the call to synchronize_rcu_tasks(). In addition, each CPU + * having an RCU-tasks read-side critical section that extends beyond + * the return from synchronize_rcu_tasks() is guaranteed to have executed + * a full memory barrier after the beginning of synchronize_rcu_tasks() + * and before the beginning of that RCU-tasks read-side critical section. + * Note that these guarantees include CPUs that are offline, idle, or + * executing in user mode, as well as CPUs that are executing in the kernel. + * + * Furthermore, if CPU A invoked synchronize_rcu_tasks(), which returned + * to its caller on CPU B, then both CPU A and CPU B are guaranteed + * to have executed a full memory barrier during the execution of + * synchronize_rcu_tasks() -- even if CPU A and CPU B are the same CPU + * (but again only if the system has more than one CPU). + */ +void synchronize_rcu_tasks(void) +{ + /* Complain if the scheduler has not started. */ + RCU_LOCKDEP_WARN(rcu_scheduler_active == RCU_SCHEDULER_INACTIVE, + "synchronize_rcu_tasks called too soon"); + + /* Wait for the grace period. */ + wait_rcu_gp(call_rcu_tasks); +} +EXPORT_SYMBOL_GPL(synchronize_rcu_tasks); + +/** + * rcu_barrier_tasks - Wait for in-flight call_rcu_tasks() callbacks. + * + * Although the current implementation is guaranteed to wait, it is not + * obligated to, for example, if there are no pending callbacks. + */ +void rcu_barrier_tasks(void) +{ + /* There is only one callback queue, so this is easy. ;-) */ + synchronize_rcu_tasks(); +} +EXPORT_SYMBOL_GPL(rcu_barrier_tasks); + +/* See if tasks are still holding out, complain if so. */ +static void check_holdout_task(struct task_struct *t, + bool needreport, bool *firstreport) +{ + int cpu; + + if (!READ_ONCE(t->rcu_tasks_holdout) || + t->rcu_tasks_nvcsw != READ_ONCE(t->nvcsw) || + !READ_ONCE(t->on_rq) || + (IS_ENABLED(CONFIG_NO_HZ_FULL) && + !is_idle_task(t) && t->rcu_tasks_idle_cpu >= 0)) { + WRITE_ONCE(t->rcu_tasks_holdout, false); + list_del_init(&t->rcu_tasks_holdout_list); + put_task_struct(t); + return; + } + rcu_request_urgent_qs_task(t); + if (!needreport) + return; + if (*firstreport) { + pr_err("INFO: rcu_tasks detected stalls on tasks:\n"); + *firstreport = false; + } + cpu = task_cpu(t); + pr_alert("%p: %c%c nvcsw: %lu/%lu holdout: %d idle_cpu: %d/%d\n", + t, ".I"[is_idle_task(t)], + "N."[cpu < 0 || !tick_nohz_full_cpu(cpu)], + t->rcu_tasks_nvcsw, t->nvcsw, t->rcu_tasks_holdout, + t->rcu_tasks_idle_cpu, cpu); + sched_show_task(t); +} + +/* RCU-tasks kthread that detects grace periods and invokes callbacks. */ +static int __noreturn rcu_tasks_kthread(void *arg) +{ + unsigned long flags; + struct task_struct *g, *t; + unsigned long lastreport; + struct rcu_head *list; + struct rcu_head *next; + LIST_HEAD(rcu_tasks_holdouts); + int fract; + + /* Run on housekeeping CPUs by default. Sysadm can move if desired. */ + housekeeping_affine(current, HK_FLAG_RCU); + + /* + * Each pass through the following loop makes one check for + * newly arrived callbacks, and, if there are some, waits for + * one RCU-tasks grace period and then invokes the callbacks. + * This loop is terminated by the system going down. ;-) + */ + for (;;) { + + /* Pick up any new callbacks. */ + raw_spin_lock_irqsave(&rcu_tasks_cbs_lock, flags); + list = rcu_tasks_cbs_head; + rcu_tasks_cbs_head = NULL; + rcu_tasks_cbs_tail = &rcu_tasks_cbs_head; + raw_spin_unlock_irqrestore(&rcu_tasks_cbs_lock, flags); + + /* If there were none, wait a bit and start over. */ + if (!list) { + wait_event_interruptible(rcu_tasks_cbs_wq, + rcu_tasks_cbs_head); + if (!rcu_tasks_cbs_head) { + WARN_ON(signal_pending(current)); + schedule_timeout_interruptible(HZ/10); + } + continue; + } + + /* + * Wait for all pre-existing t->on_rq and t->nvcsw + * transitions to complete. Invoking synchronize_rcu() + * suffices because all these transitions occur with + * interrupts disabled. Without this synchronize_rcu(), + * a read-side critical section that started before the + * grace period might be incorrectly seen as having started + * after the grace period. + * + * This synchronize_rcu() also dispenses with the + * need for a memory barrier on the first store to + * ->rcu_tasks_holdout, as it forces the store to happen + * after the beginning of the grace period. + */ + synchronize_rcu(); + + /* + * There were callbacks, so we need to wait for an + * RCU-tasks grace period. Start off by scanning + * the task list for tasks that are not already + * voluntarily blocked. Mark these tasks and make + * a list of them in rcu_tasks_holdouts. + */ + rcu_read_lock(); + for_each_process_thread(g, t) { + if (t != current && READ_ONCE(t->on_rq) && + !is_idle_task(t)) { + get_task_struct(t); + t->rcu_tasks_nvcsw = READ_ONCE(t->nvcsw); + WRITE_ONCE(t->rcu_tasks_holdout, true); + list_add(&t->rcu_tasks_holdout_list, + &rcu_tasks_holdouts); + } + } + rcu_read_unlock(); + + /* + * Wait for tasks that are in the process of exiting. + * This does only part of the job, ensuring that all + * tasks that were previously exiting reach the point + * where they have disabled preemption, allowing the + * later synchronize_rcu() to finish the job. + */ + synchronize_srcu(&tasks_rcu_exit_srcu); + + /* + * Each pass through the following loop scans the list + * of holdout tasks, removing any that are no longer + * holdouts. When the list is empty, we are done. + */ + lastreport = jiffies; + + /* Start off with HZ/10 wait and slowly back off to 1 HZ wait*/ + fract = 10; + + for (;;) { + bool firstreport; + bool needreport; + int rtst; + struct task_struct *t1; + + if (list_empty(&rcu_tasks_holdouts)) + break; + + /* Slowly back off waiting for holdouts */ + schedule_timeout_interruptible(HZ/fract); + + if (fract > 1) + fract--; + + rtst = READ_ONCE(rcu_task_stall_timeout); + needreport = rtst > 0 && + time_after(jiffies, lastreport + rtst); + if (needreport) + lastreport = jiffies; + firstreport = true; + WARN_ON(signal_pending(current)); + list_for_each_entry_safe(t, t1, &rcu_tasks_holdouts, + rcu_tasks_holdout_list) { + check_holdout_task(t, needreport, &firstreport); + cond_resched(); + } + } + + /* + * Because ->on_rq and ->nvcsw are not guaranteed + * to have a full memory barriers prior to them in the + * schedule() path, memory reordering on other CPUs could + * cause their RCU-tasks read-side critical sections to + * extend past the end of the grace period. However, + * because these ->nvcsw updates are carried out with + * interrupts disabled, we can use synchronize_rcu() + * to force the needed ordering on all such CPUs. + * + * This synchronize_rcu() also confines all + * ->rcu_tasks_holdout accesses to be within the grace + * period, avoiding the need for memory barriers for + * ->rcu_tasks_holdout accesses. + * + * In addition, this synchronize_rcu() waits for exiting + * tasks to complete their final preempt_disable() region + * of execution, cleaning up after the synchronize_srcu() + * above. + */ + synchronize_rcu(); + + /* Invoke the callbacks. */ + while (list) { + next = list->next; + local_bh_disable(); + list->func(list); + local_bh_enable(); + list = next; + cond_resched(); + } + /* Paranoid sleep to keep this from entering a tight loop */ + schedule_timeout_uninterruptible(HZ/10); + } +} + +/* Spawn rcu_tasks_kthread() at core_initcall() time. */ +static int __init rcu_spawn_tasks_kthread(void) +{ + struct task_struct *t; + + t = kthread_run(rcu_tasks_kthread, NULL, "rcu_tasks_kthread"); + if (WARN_ONCE(IS_ERR(t), "%s: Could not start Tasks-RCU grace-period kthread, OOM is now expected behavior\n", __func__)) + return 0; + smp_mb(); /* Ensure others see full kthread. */ + WRITE_ONCE(rcu_tasks_kthread_ptr, t); + return 0; +} +core_initcall(rcu_spawn_tasks_kthread); + +/* Do the srcu_read_lock() for the above synchronize_srcu(). */ +void exit_tasks_rcu_start(void) +{ + preempt_disable(); + current->rcu_tasks_idx = __srcu_read_lock(&tasks_rcu_exit_srcu); + preempt_enable(); +} + +/* Do the srcu_read_unlock() for the above synchronize_srcu(). */ +void exit_tasks_rcu_finish(void) +{ + preempt_disable(); + __srcu_read_unlock(&tasks_rcu_exit_srcu, current->rcu_tasks_idx); + preempt_enable(); +} + +#endif /* #ifdef CONFIG_TASKS_RCU */ + +#ifndef CONFIG_TINY_RCU + +/* + * Print any non-default Tasks RCU settings. + */ +static void __init rcu_tasks_bootup_oddness(void) +{ +#ifdef CONFIG_TASKS_RCU + if (rcu_task_stall_timeout != RCU_TASK_STALL_TIMEOUT) + pr_info("\tTasks-RCU CPU stall warnings timeout set to %d (rcu_task_stall_timeout).\n", rcu_task_stall_timeout); + else + pr_info("\tTasks RCU enabled.\n"); +#endif /* #ifdef CONFIG_TASKS_RCU */ +} + +#endif /* #ifndef CONFIG_TINY_RCU */ + #ifdef CONFIG_PROVE_RCU /* @@ -533,12 +897,6 @@ late_initcall(rcu_verify_early_boot_tests); void rcu_early_boot_tests(void) {} #endif /* CONFIG_PROVE_RCU */ -#ifdef CONFIG_TASKS_RCU_GENERIC -#include "tasks.h" -#else /* #ifdef CONFIG_TASKS_RCU_GENERIC */ -static inline void rcu_tasks_bootup_oddness(void) {} -#endif /* #else #ifdef CONFIG_TASKS_RCU_GENERIC */ - #ifndef CONFIG_TINY_RCU /* diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 2edacc65c658..93392dbaedd5 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -1213,7 +1213,8 @@ static void uclamp_update_root_tg(void) { } #endif int sysctl_sched_uclamp_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { bool update_root_tg = false; int old_min, old_max; @@ -2793,8 +2794,6 @@ try_to_wake_up(struct task_struct *p, unsigned int state, int wake_flags, * * Pairs with the LOCK+smp_mb__after_spinlock() on rq->lock in * __schedule(). See the comment for smp_mb__after_spinlock(). - * - * A similar smb_rmb() lives in try_invoke_on_locked_down_task(). */ smp_rmb(); if (p->on_rq && ttwu_remote(p, wake_flags)) @@ -2882,52 +2881,6 @@ out: return success; } -/** - * try_invoke_on_locked_down_task - Invoke a function on task in fixed state - * @p: Process for which the function is to be invoked. - * @func: Function to invoke. - * @arg: Argument to function. - * - * If the specified task can be quickly locked into a definite state - * (either sleeping or on a given runqueue), arrange to keep it in that - * state while invoking @func(@arg). This function can use ->on_rq and - * task_curr() to work out what the state is, if required. Given that - * @func can be invoked with a runqueue lock held, it had better be quite - * lightweight. - * - * Returns: - * @false if the task slipped out from under the locks. - * @true if the task was locked onto a runqueue or is sleeping. - * However, @func can override this by returning @false. - */ -bool try_invoke_on_locked_down_task(struct task_struct *p, bool (*func)(struct task_struct *t, void *arg), void *arg) -{ - bool ret = false; - struct rq_flags rf; - struct rq *rq; - - lockdep_assert_irqs_enabled(); - raw_spin_lock_irq(&p->pi_lock); - if (p->on_rq) { - rq = __task_rq_lock(p, &rf); - if (task_rq(p) == rq) - ret = func(p, arg); - rq_unlock(rq, &rf); - } else { - switch (p->state) { - case TASK_RUNNING: - case TASK_WAKING: - break; - default: - smp_rmb(); // See smp_rmb() comment in try_to_wake_up(). - if (!p->on_rq) - ret = func(p, arg); - } - } - raw_spin_unlock_irq(&p->pi_lock); - return ret; -} - /** * wake_up_process - Wake up a specific process * @p: The process to be woken up. @@ -3021,7 +2974,7 @@ void set_numabalancing_state(bool enabled) #ifdef CONFIG_PROC_SYSCTL int sysctl_numa_balancing(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ctl_table t; int err; @@ -3095,8 +3048,8 @@ static void __init init_schedstats(void) } #ifdef CONFIG_PROC_SYSCTL -int sysctl_schedstats(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos) +int sysctl_schedstats(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ctl_table t; int err; diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 6d4c25094f37..fd8d3a105a4c 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -656,7 +656,8 @@ struct sched_entity *__pick_last_entity(struct cfs_rq *cfs_rq) */ int sched_proc_update_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos); unsigned int factor = get_update_sysctl_factor(); @@ -3713,8 +3714,6 @@ static inline unsigned long cfs_rq_load_avg(struct cfs_rq *cfs_rq) return cfs_rq->avg.load_avg; } -static int sched_balance_newidle(struct rq *this_rq, struct rq_flags *rf); - static inline unsigned long _task_util_est(struct task_struct *p) { struct util_est ue = READ_ONCE(p->se.avg.util_est); @@ -4036,7 +4035,7 @@ attach_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se, int flags static inline void detach_entity_load_avg(struct cfs_rq *cfs_rq, struct sched_entity *se) {} -static inline int sched_balance_newidle(struct rq *rq, struct rq_flags *rf) +static inline int idle_balance(struct rq *rq, struct rq_flags *rf) { return 0; } @@ -7596,7 +7595,7 @@ balance_fair(struct rq *rq, struct task_struct *prev, struct rq_flags *rf) if (rq->nr_running) return 1; - return sched_balance_newidle(rq, rf) != 0; + return newidle_balance(rq, rf) != 0; } #endif /* CONFIG_SMP */ @@ -7884,21 +7883,21 @@ done: __maybe_unused; return p; idle: - if (rf) { - new_tasks = sched_balance_newidle(rq, rf); + if (!rf) + return NULL; - /* - * Because sched_balance_newidle() releases (and re-acquires) - * rq->lock, it is possible for any higher priority task to - * appear. In that case we must re-start the pick_next_entity() - * loop. - */ - if (new_tasks < 0) - return RETRY_TASK; + new_tasks = newidle_balance(rq, rf); - if (new_tasks > 0) - goto again; - } + /* + * Because newidle_balance() releases (and re-acquires) rq->lock, it is + * possible for any higher priority task to appear. In that case we + * must re-start the pick_next_entity() loop. + */ + if (new_tasks < 0) + return RETRY_TASK; + + if (new_tasks > 0) + goto again; /* * rq is about to be idle, check if we need to update the @@ -10572,7 +10571,7 @@ out_one_pinned: ld_moved = 0; /* - * sched_balance_newidle() disregards balance intervals, so we could + * newidle_balance() disregards balance intervals, so we could * repeatedly reach this code, which would lead to balance_interval * skyrocketting in a short amount of time. Skip the balance_interval * increase logic to avoid that. @@ -11509,10 +11508,10 @@ static inline bool silver_has_big_tasks(void) #endif /* - * sched_balance_newidle is called by schedule() if this_cpu is about to become + * idle_balance is called by schedule() if this_cpu is about to become * idle. Attempts to pull tasks from other CPUs. */ -static int sched_balance_newidle(struct rq *this_rq, struct rq_flags *rf) +int newidle_balance(struct rq *this_rq, struct rq_flags *rf) { unsigned long next_balance = jiffies + HZ; int this_cpu = this_rq->cpu; diff --git a/kernel/sched/rt.c b/kernel/sched/rt.c index 2d771222d6ad..47bdbac14259 100644 --- a/kernel/sched/rt.c +++ b/kernel/sched/rt.c @@ -3074,8 +3074,9 @@ static void sched_rt_do_global(void) raw_spin_unlock_irqrestore(&def_rt_bandwidth.rt_runtime_lock, flags); } -int sched_rt_handler(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos) +int sched_rt_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos) { int old_period, old_runtime; static DEFINE_MUTEX(mutex); @@ -3113,8 +3114,9 @@ undo: return ret; } -int sched_rr_handler(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos) +int sched_rr_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos) { int ret; static DEFINE_MUTEX(mutex); diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index 7b6820d7aa9a..b5ac1d91cb45 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -1612,10 +1612,14 @@ static inline void unregister_sched_domain_sysctl(void) } #endif +extern int newidle_balance(struct rq *this_rq, struct rq_flags *rf); + #else static inline void sched_ttwu_pending(void) { } +static inline int newidle_balance(struct rq *this_rq, struct rq_flags *rf) { return 0; } + #endif /* CONFIG_SMP */ #include "stats.h" diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index 1f1115ccd5e7..b86947e46d00 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -209,7 +209,7 @@ bool sched_energy_update; #ifdef CONFIG_PROC_SYSCTL int sched_energy_aware_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int ret, state; diff --git a/kernel/seccomp.c b/kernel/seccomp.c index 1ec9bdc1e208..b2e1981663b8 100644 --- a/kernel/seccomp.c +++ b/kernel/seccomp.c @@ -13,7 +13,6 @@ * Mode 2 allows user-defined system call filters in the form * of Berkeley Packet Filters/Linux Socket Filters. */ -#define pr_fmt(fmt) "seccomp: " fmt #include #include @@ -45,7 +44,6 @@ #include #include #include -#include /* * When SECCOMP_IOCTL_NOTIF_ID_VALID was first introduced, it had the @@ -88,7 +86,6 @@ struct seccomp_knotif { /* The return values, only valid when in SECCOMP_NOTIFY_REPLIED */ int error; long val; - u32 flags; /* Signals when this has entered SECCOMP_NOTIFY_REPLIED */ struct completion ready; @@ -107,68 +104,27 @@ struct seccomp_knotif { * filter->notify_lock. * @next_id: The id of the next request. * @notifications: A list of struct seccomp_knotif elements. + * @wqh: A wait queue for poll. */ struct notification { struct semaphore request; u64 next_id; struct list_head notifications; + wait_queue_head_t wqh; }; -#ifdef SECCOMP_ARCH_NATIVE -/** - * struct action_cache - per-filter cache of seccomp actions per - * arch/syscall pair - * - * @allow_native: A bitmap where each bit represents whether the - * filter will always allow the syscall, for the - * native architecture. - * @allow_compat: A bitmap where each bit represents whether the - * filter will always allow the syscall, for the - * compat architecture. - */ -struct action_cache { - DECLARE_BITMAP(allow_native, SECCOMP_ARCH_NATIVE_NR); -#ifdef SECCOMP_ARCH_COMPAT - DECLARE_BITMAP(allow_compat, SECCOMP_ARCH_COMPAT_NR); -#endif -}; -#else -struct action_cache { }; - -static inline bool seccomp_cache_check_allow(const struct seccomp_filter *sfilter, - const struct seccomp_data *sd) -{ - return false; -} - -static inline void seccomp_cache_prepare(struct seccomp_filter *sfilter) -{ -} -#endif /* SECCOMP_ARCH_NATIVE */ - /** * struct seccomp_filter - container for seccomp BPF programs * - * @refs: Reference count to manage the object lifetime. - * A filter's reference count is incremented for each directly - * attached task, once for the dependent filter, and if - * requested for the user notifier. When @refs reaches zero, - * the filter can be freed. - * @users: A filter's @users count is incremented for each directly - * attached task (filter installation, fork(), thread_sync), - * and once for the dependent filter (tracked in filter->prev). - * When it reaches zero it indicates that no direct or indirect - * users of that filter exist. No new tasks can get associated with - * this filter after reaching 0. The @users count is always smaller - * or equal to @refs. Hence, reaching 0 for @users does not mean - * the filter can be freed. - * @cache: cache of arch/syscall mappings to actions + * @usage: reference count to manage the object lifetime. + * get/put helpers should be used when accessing an instance + * outside of a lifetime-guarded section. In general, this + * is only needed for handling filters shared across tasks. * @log: true if all actions except for SECCOMP_RET_ALLOW should be logged * @prev: points to a previously installed, or inherited, filter * @prog: the BPF program to evaluate * @notif: the struct that holds all notification related information * @notify_lock: A lock for all notification-related accesses. - * @wqh: A wait queue for poll if a notifier is in use. * * seccomp_filter objects are organized in a tree linked via the @prev * pointer. For any task, it appears to be a singly-linked list starting @@ -178,18 +134,15 @@ static inline void seccomp_cache_prepare(struct seccomp_filter *sfilter) * how namespaces work. * * seccomp_filter objects should never be modified after being attached - * to a task_struct (other than @refs). + * to a task_struct (other than @usage). */ struct seccomp_filter { - refcount_t refs; - refcount_t users; + refcount_t usage; bool log; - struct action_cache cache; struct seccomp_filter *prev; struct bpf_prog *prog; struct notification *notif; struct mutex notify_lock; - wait_queue_head_t wqh; }; /* Limit any path through the tree to 256KB worth of instructions. */ @@ -201,10 +154,6 @@ struct seccomp_filter { */ static void populate_seccomp_data(struct seccomp_data *sd) { - /* - * Instead of using current_pt_reg(), we're already doing the work - * to safely fetch "current", so just use "task" everywhere below. - */ struct task_struct *task = current; struct pt_regs *regs = task_pt_regs(task); unsigned long args[6]; @@ -303,52 +252,6 @@ static int seccomp_check_filter(struct sock_filter *filter, unsigned int flen) return 0; } -#ifdef SECCOMP_ARCH_NATIVE -static inline bool seccomp_cache_check_allow_bitmap(const void *bitmap, - size_t bitmap_size, - int syscall_nr) -{ - if (unlikely(syscall_nr < 0 || syscall_nr >= bitmap_size)) - return false; - syscall_nr = array_index_nospec(syscall_nr, bitmap_size); - - return test_bit(syscall_nr, bitmap); -} - -/** - * seccomp_cache_check_allow - lookup seccomp cache - * @sfilter: The seccomp filter - * @sd: The seccomp data to lookup the cache with - * - * Returns true if the seccomp_data is cached and allowed. - */ -static inline bool seccomp_cache_check_allow(const struct seccomp_filter *sfilter, - const struct seccomp_data *sd) -{ - int syscall_nr = sd->nr; - const struct action_cache *cache = &sfilter->cache; - -#ifndef SECCOMP_ARCH_COMPAT - /* A native-only architecture doesn't need to check sd->arch. */ - return seccomp_cache_check_allow_bitmap(cache->allow_native, - SECCOMP_ARCH_NATIVE_NR, - syscall_nr); -#else - if (likely(sd->arch == SECCOMP_ARCH_NATIVE)) - return seccomp_cache_check_allow_bitmap(cache->allow_native, - SECCOMP_ARCH_NATIVE_NR, - syscall_nr); - if (likely(sd->arch == SECCOMP_ARCH_COMPAT)) - return seccomp_cache_check_allow_bitmap(cache->allow_compat, - SECCOMP_ARCH_COMPAT_NR, - syscall_nr); -#endif /* SECCOMP_ARCH_COMPAT */ - - WARN_ON_ONCE(true); - return false; -} -#endif /* SECCOMP_ARCH_NATIVE */ - /** * seccomp_run_filters - evaluates all seccomp filters against @sd * @sd: optional seccomp data to be passed to filters @@ -371,9 +274,6 @@ static u32 seccomp_run_filters(const struct seccomp_data *sd, if (WARN_ON(f == NULL)) return SECCOMP_RET_KILL_PROCESS; - if (seccomp_cache_check_allow(f, sd)) - return SECCOMP_RET_ALLOW; - /* * All filters in the list are evaluated and the lowest BPF return * value always takes priority (ignoring the DATA). @@ -478,59 +378,6 @@ static inline pid_t seccomp_can_sync_threads(void) return 0; } -static inline void seccomp_filter_free(struct seccomp_filter *filter) -{ - if (filter) { - bpf_prog_destroy(filter->prog); - kfree(filter); - } -} - -static void __seccomp_filter_orphan(struct seccomp_filter *orig) -{ - while (orig && refcount_dec_and_test(&orig->users)) { - if (waitqueue_active(&orig->wqh)) - wake_up_poll(&orig->wqh, EPOLLHUP); - orig = orig->prev; - } -} - -static void __put_seccomp_filter(struct seccomp_filter *orig) -{ - /* Clean up single-reference branches iteratively. */ - while (orig && refcount_dec_and_test(&orig->refs)) { - struct seccomp_filter *freeme = orig; - orig = orig->prev; - seccomp_filter_free(freeme); - } -} - -static void __seccomp_filter_release(struct seccomp_filter *orig) -{ - /* Notify about any unused filters in the task's former filter tree. */ - __seccomp_filter_orphan(orig); - /* Finally drop all references to the task's former tree. */ - __put_seccomp_filter(orig); -} - -/** - * seccomp_filter_release - Detach the task from its filter tree, - * drop its reference count, and notify - * about unused filters - * - * This function should only be called when the task is exiting as - * it detaches it from its filter tree. As such, READ_ONCE() and - * barriers are not needed here, as would normally be needed. - */ -void seccomp_filter_release(struct task_struct *tsk) -{ - struct seccomp_filter *orig = tsk->seccomp.filter; - - /* Detach task from its filter tree. */ - tsk->seccomp.filter = NULL; - __seccomp_filter_release(orig); -} - /** * seccomp_sync_threads: sets all threads to use current's filter * @@ -555,19 +402,14 @@ static inline void seccomp_sync_threads(unsigned long flags) /* Get a task reference for the new leaf node. */ get_seccomp_filter(caller); - /* * Drop the task reference to the shared ancestor since * current's path will hold a reference. (This also * allows a put before the assignment.) */ - __seccomp_filter_release(thread->seccomp.filter); - - /* Make our new filter tree visible. */ + put_seccomp_filter(thread); smp_store_release(&thread->seccomp.filter, caller->seccomp.filter); - atomic_set(&thread->seccomp.filter_count, - atomic_read(&caller->seccomp.filter_count)); /* * Don't let an unprivileged task work around @@ -600,12 +442,7 @@ static struct seccomp_filter *seccomp_prepare_filter(struct sock_fprog *fprog) { struct seccomp_filter *sfilter; int ret; - const bool save_orig = -#if defined(CONFIG_CHECKPOINT_RESTORE) || defined(SECCOMP_ARCH_NATIVE) - true; -#else - false; -#endif + const bool save_orig = IS_ENABLED(CONFIG_CHECKPOINT_RESTORE); if (fprog->len == 0 || fprog->len > BPF_MAXINSNS) return ERR_PTR(-EINVAL); @@ -635,9 +472,7 @@ static struct seccomp_filter *seccomp_prepare_filter(struct sock_fprog *fprog) return ERR_PTR(ret); } - refcount_set(&sfilter->refs, 1); - refcount_set(&sfilter->users, 1); - init_waitqueue_head(&sfilter->wqh); + refcount_set(&sfilter->usage, 1); return sfilter; } @@ -670,148 +505,6 @@ out: return filter; } -#ifdef SECCOMP_ARCH_NATIVE -/** - * seccomp_is_const_allow - check if filter is constant allow with given data - * @fprog: The BPF programs - * @sd: The seccomp data to check against, only syscall number and arch - * number are considered constant. - */ -static bool seccomp_is_const_allow(struct sock_fprog_kern *fprog, - struct seccomp_data *sd) -{ - unsigned int reg_value = 0; - unsigned int pc; - bool op_res; - - if (WARN_ON_ONCE(!fprog)) - return false; - - for (pc = 0; pc < fprog->len; pc++) { - struct sock_filter *insn = &fprog->filter[pc]; - u16 code = insn->code; - u32 k = insn->k; - - switch (code) { - case BPF_LD | BPF_W | BPF_ABS: - switch (k) { - case offsetof(struct seccomp_data, nr): - reg_value = sd->nr; - break; - case offsetof(struct seccomp_data, arch): - reg_value = sd->arch; - break; - default: - /* can't optimize (non-constant value load) */ - return false; - } - break; - case BPF_RET | BPF_K: - /* reached return with constant values only, check allow */ - return k == SECCOMP_RET_ALLOW; - case BPF_JMP | BPF_JA: - pc += insn->k; - break; - case BPF_JMP | BPF_JEQ | BPF_K: - case BPF_JMP | BPF_JGE | BPF_K: - case BPF_JMP | BPF_JGT | BPF_K: - case BPF_JMP | BPF_JSET | BPF_K: - switch (BPF_OP(code)) { - case BPF_JEQ: - op_res = reg_value == k; - break; - case BPF_JGE: - op_res = reg_value >= k; - break; - case BPF_JGT: - op_res = reg_value > k; - break; - case BPF_JSET: - op_res = !!(reg_value & k); - break; - default: - /* can't optimize (unknown jump) */ - return false; - } - - pc += op_res ? insn->jt : insn->jf; - break; - case BPF_ALU | BPF_AND | BPF_K: - reg_value &= k; - break; - default: - /* can't optimize (unknown insn) */ - return false; - } - } - - /* ran off the end of the filter?! */ - WARN_ON(1); - return false; -} - -static void seccomp_cache_prepare_bitmap(struct seccomp_filter *sfilter, - void *bitmap, const void *bitmap_prev, - size_t bitmap_size, int arch) -{ - struct sock_fprog_kern *fprog = sfilter->prog->orig_prog; - struct seccomp_data sd; - int nr; - - if (bitmap_prev) { - /* The new filter must be as restrictive as the last. */ - bitmap_copy(bitmap, bitmap_prev, bitmap_size); - } else { - /* Before any filters, all syscalls are always allowed. */ - bitmap_fill(bitmap, bitmap_size); - } - - for (nr = 0; nr < bitmap_size; nr++) { - /* No bitmap change: not a cacheable action. */ - if (!test_bit(nr, bitmap)) - continue; - - sd.nr = nr; - sd.arch = arch; - - /* No bitmap change: continue to always allow. */ - if (seccomp_is_const_allow(fprog, &sd)) - continue; - - /* - * Not a cacheable action: always run filters. - * atomic clear_bit() not needed, filter not visible yet. - */ - __clear_bit(nr, bitmap); - } -} - -/** - * seccomp_cache_prepare - emulate the filter to find cachable syscalls - * @sfilter: The seccomp filter - * - * Returns 0 if successful or -errno if error occurred. - */ -static void seccomp_cache_prepare(struct seccomp_filter *sfilter) -{ - struct action_cache *cache = &sfilter->cache; - const struct action_cache *cache_prev = - sfilter->prev ? &sfilter->prev->cache : NULL; - - seccomp_cache_prepare_bitmap(sfilter, cache->allow_native, - cache_prev ? cache_prev->allow_native : NULL, - SECCOMP_ARCH_NATIVE_NR, - SECCOMP_ARCH_NATIVE); - -#ifdef SECCOMP_ARCH_COMPAT - seccomp_cache_prepare_bitmap(sfilter, cache->allow_compat, - cache_prev ? cache_prev->allow_compat : NULL, - SECCOMP_ARCH_COMPAT_NR, - SECCOMP_ARCH_COMPAT); -#endif /* SECCOMP_ARCH_COMPAT */ -} -#endif /* SECCOMP_ARCH_NATIVE */ - /** * seccomp_attach_filter: validate and attach filter * @flags: flags to change filter behavior @@ -857,9 +550,7 @@ static long seccomp_attach_filter(unsigned int flags, * task reference. */ filter->prev = current->seccomp.filter; - seccomp_cache_prepare(filter); current->seccomp.filter = filter; - atomic_inc(¤t->seccomp.filter_count); /* Now that the new filter is in place, synchronize to all threads. */ if (flags & SECCOMP_FILTER_FLAG_TSYNC) @@ -870,7 +561,7 @@ static long seccomp_attach_filter(unsigned int flags, static void __get_seccomp_filter(struct seccomp_filter *filter) { - refcount_inc(&filter->refs); + refcount_inc(&filter->usage); } /* get_seccomp_filter - increments the reference count of the filter on @tsk */ @@ -880,7 +571,30 @@ void get_seccomp_filter(struct task_struct *tsk) if (!orig) return; __get_seccomp_filter(orig); - refcount_inc(&orig->users); +} + +static inline void seccomp_filter_free(struct seccomp_filter *filter) +{ + if (filter) { + bpf_prog_destroy(filter->prog); + kfree(filter); + } +} + +static void __put_seccomp_filter(struct seccomp_filter *orig) +{ + /* Clean up single-reference branches iteratively. */ + while (orig && refcount_dec_and_test(&orig->usage)) { + struct seccomp_filter *freeme = orig; + orig = orig->prev; + seccomp_filter_free(freeme); + } +} + +/* put_seccomp_filter - decrements the ref count of tsk->seccomp.filter */ +void put_seccomp_filter(struct task_struct *tsk) +{ + __put_seccomp_filter(tsk->seccomp.filter); } static void seccomp_init_siginfo(kernel_siginfo_t *info, int syscall, int reason) @@ -977,20 +691,20 @@ static inline void seccomp_log(unsigned long syscall, long signr, u32 action, */ static const int mode1_syscalls[] = { __NR_seccomp_read, __NR_seccomp_write, __NR_seccomp_exit, __NR_seccomp_sigreturn, - -1, /* negative terminated */ + 0, /* null terminated */ }; static void __secure_computing_strict(int this_syscall) { - const int *allowed_syscalls = mode1_syscalls; + const int *syscall_whitelist = mode1_syscalls; #ifdef CONFIG_COMPAT if (in_compat_syscall()) - allowed_syscalls = get_compat_mode1_syscalls(); + syscall_whitelist = get_compat_mode1_syscalls(); #endif do { - if (*allowed_syscalls == this_syscall) + if (*syscall_whitelist == this_syscall) return; - } while (*++allowed_syscalls != -1); + } while (*++syscall_whitelist); #ifdef SECCOMP_DEBUG dump_stack(); @@ -1029,12 +743,11 @@ static u64 seccomp_next_notify_id(struct seccomp_filter *filter) return filter->notif->next_id++; } -static int seccomp_do_user_notification(int this_syscall, - struct seccomp_filter *match, - const struct seccomp_data *sd) +static void seccomp_do_user_notification(int this_syscall, + struct seccomp_filter *match, + const struct seccomp_data *sd) { int err; - u32 flags = 0; long ret = 0; struct seccomp_knotif n = {}; @@ -1051,7 +764,7 @@ static int seccomp_do_user_notification(int this_syscall, list_add(&n.list, &match->notif->notifications); up(&match->notif->request); - wake_up_poll(&match->wqh, EPOLLIN | EPOLLRDNORM); + wake_up_poll(&match->notif->wqh, EPOLLIN | EPOLLRDNORM); mutex_unlock(&match->notify_lock); /* @@ -1062,7 +775,6 @@ static int seccomp_do_user_notification(int this_syscall, if (err == 0) { ret = n.val; err = n.error; - flags = n.flags; } /* @@ -1079,14 +791,8 @@ static int seccomp_do_user_notification(int this_syscall, list_del(&n.list); out: mutex_unlock(&match->notify_lock); - - /* Userspace requests to continue the syscall. */ - if (flags & SECCOMP_USER_NOTIF_FLAG_CONTINUE) - return 0; - - syscall_set_return_value(current, current_pt_regs(), + syscall_set_return_value(current, task_pt_regs(current), err, ret); - return -1; } static int __seccomp_filter(int this_syscall, const struct seccomp_data *sd, @@ -1117,13 +823,13 @@ static int __seccomp_filter(int this_syscall, const struct seccomp_data *sd, /* Set low-order bits as an errno, capped at MAX_ERRNO. */ if (data > MAX_ERRNO) data = MAX_ERRNO; - syscall_set_return_value(current, current_pt_regs(), + syscall_set_return_value(current, task_pt_regs(current), -data, 0); goto skip; case SECCOMP_RET_TRAP: /* Show the handler the original registers. */ - syscall_rollback(current, current_pt_regs()); + syscall_rollback(current, task_pt_regs(current)); /* Let the filter pass back 16 bits of data. */ seccomp_send_sigsys(this_syscall, data); goto skip; @@ -1136,7 +842,7 @@ static int __seccomp_filter(int this_syscall, const struct seccomp_data *sd, /* ENOSYS these calls if there is no tracer attached. */ if (!ptrace_event_enabled(current, PTRACE_EVENT_SECCOMP)) { syscall_set_return_value(current, - current_pt_regs(), + task_pt_regs(current), -ENOSYS, 0); goto skip; } @@ -1156,7 +862,7 @@ static int __seccomp_filter(int this_syscall, const struct seccomp_data *sd, if (fatal_signal_pending(current)) goto skip; /* Check if the tracer forced the syscall to be skipped. */ - this_syscall = syscall_get_nr(current, current_pt_regs()); + this_syscall = syscall_get_nr(current, task_pt_regs(current)); if (this_syscall < 0) goto skip; @@ -1172,10 +878,8 @@ static int __seccomp_filter(int this_syscall, const struct seccomp_data *sd, return 0; case SECCOMP_RET_USER_NOTIF: - if (seccomp_do_user_notification(this_syscall, match, sd)) - goto skip; - - return 0; + seccomp_do_user_notification(this_syscall, match, sd); + goto skip; case SECCOMP_RET_LOG: seccomp_log(this_syscall, 0, action, true); @@ -1195,20 +899,20 @@ static int __seccomp_filter(int this_syscall, const struct seccomp_data *sd, current->seccomp.mode = SECCOMP_MODE_DEAD; seccomp_log(this_syscall, SIGSYS, action, true); /* Dump core only if this is the last remaining thread. */ - if (action != SECCOMP_RET_KILL_THREAD || + if (action == SECCOMP_RET_KILL_PROCESS || get_nr_threads(current) == 1) { kernel_siginfo_t info; /* Show the original registers in the dump. */ - syscall_rollback(current, current_pt_regs()); + syscall_rollback(current, task_pt_regs(current)); /* Trigger a manual coredump since do_exit skips it. */ seccomp_init_siginfo(&info, this_syscall, data); do_coredump(&info); } - if (action == SECCOMP_RET_KILL_THREAD) - do_exit(SIGSYS); - else + if (action == SECCOMP_RET_KILL_PROCESS) do_group_exit(SIGSYS); + else + do_exit(SIGSYS); } unreachable(); @@ -1237,7 +941,7 @@ int __secure_computing(const struct seccomp_data *sd) return 0; this_syscall = sd ? sd->nr : - syscall_get_nr(current, current_pt_regs()); + syscall_get_nr(current, task_pt_regs(current)); switch (mode) { case SECCOMP_MODE_STRICT: @@ -1291,18 +995,13 @@ out: } #ifdef CONFIG_SECCOMP_FILTER -static void seccomp_notify_free(struct seccomp_filter *filter) -{ - kfree(filter->notif); - filter->notif = NULL; -} - -static void seccomp_notify_detach(struct seccomp_filter *filter) +static int seccomp_notify_release(struct inode *inode, struct file *file) { + struct seccomp_filter *filter = file->private_data; struct seccomp_knotif *knotif; if (!filter) - return; + return 0; mutex_lock(&filter->notify_lock); @@ -1321,36 +1020,13 @@ static void seccomp_notify_detach(struct seccomp_filter *filter) complete(&knotif->ready); } - seccomp_notify_free(filter); + kfree(filter->notif); + filter->notif = NULL; mutex_unlock(&filter->notify_lock); -} - -static int seccomp_notify_release(struct inode *inode, struct file *file) -{ - struct seccomp_filter *filter = file->private_data; - - seccomp_notify_detach(filter); __put_seccomp_filter(filter); return 0; } -/* must be called with notif_lock held */ -static inline struct seccomp_knotif * -find_notification(struct seccomp_filter *filter, u64 id) -{ - struct seccomp_knotif *cur; - - lockdep_assert_held(&filter->notify_lock); - - list_for_each_entry(cur, &filter->notif->notifications, list) { - if (cur->id == id) - return cur; - } - - return NULL; -} - - static long seccomp_notify_recv(struct seccomp_filter *filter, void __user *buf) { @@ -1394,7 +1070,7 @@ static long seccomp_notify_recv(struct seccomp_filter *filter, unotif.data = *(knotif->data); knotif->state = SECCOMP_NOTIFY_SENT; - wake_up_poll(&filter->wqh, EPOLLOUT | EPOLLWRNORM); + wake_up_poll(&filter->notif->wqh, EPOLLOUT | EPOLLWRNORM); ret = 0; out: mutex_unlock(&filter->notify_lock); @@ -1408,8 +1084,15 @@ out: * may have died when we released the lock, so we need to make * sure it's still around. */ + knotif = NULL; mutex_lock(&filter->notify_lock); - knotif = find_notification(filter, unotif.id); + list_for_each_entry(cur, &filter->notif->notifications, list) { + if (cur->id == unotif.id) { + knotif = cur; + break; + } + } + if (knotif) { knotif->state = SECCOMP_NOTIFY_INIT; up(&filter->notif->request); @@ -1424,24 +1107,26 @@ static long seccomp_notify_send(struct seccomp_filter *filter, void __user *buf) { struct seccomp_notif_resp resp = {}; - struct seccomp_knotif *knotif; + struct seccomp_knotif *knotif = NULL, *cur; long ret; if (copy_from_user(&resp, buf, sizeof(resp))) return -EFAULT; - if (resp.flags & ~SECCOMP_USER_NOTIF_FLAG_CONTINUE) - return -EINVAL; - - if ((resp.flags & SECCOMP_USER_NOTIF_FLAG_CONTINUE) && - (resp.error || resp.val)) + if (resp.flags) return -EINVAL; ret = mutex_lock_interruptible(&filter->notify_lock); if (ret < 0) return ret; - knotif = find_notification(filter, resp.id); + list_for_each_entry(cur, &filter->notif->notifications, list) { + if (cur->id == resp.id) { + knotif = cur; + break; + } + } + if (!knotif) { ret = -ENOENT; goto out; @@ -1457,7 +1142,6 @@ static long seccomp_notify_send(struct seccomp_filter *filter, knotif->state = SECCOMP_NOTIFY_REPLIED; knotif->error = resp.error; knotif->val = resp.val; - knotif->flags = resp.flags; complete(&knotif->ready); out: mutex_unlock(&filter->notify_lock); @@ -1467,7 +1151,7 @@ out: static long seccomp_notify_id_valid(struct seccomp_filter *filter, void __user *buf) { - struct seccomp_knotif *knotif; + struct seccomp_knotif *knotif = NULL; u64 id; long ret; @@ -1478,12 +1162,16 @@ static long seccomp_notify_id_valid(struct seccomp_filter *filter, if (ret < 0) return ret; - knotif = find_notification(filter, id); - if (knotif && knotif->state == SECCOMP_NOTIFY_SENT) - ret = 0; - else - ret = -ENOENT; + ret = -ENOENT; + list_for_each_entry(knotif, &filter->notif->notifications, list) { + if (knotif->id == id) { + if (knotif->state == SECCOMP_NOTIFY_SENT) + ret = 0; + goto out; + } + } +out: mutex_unlock(&filter->notify_lock); return ret; } @@ -1514,7 +1202,7 @@ static __poll_t seccomp_notify_poll(struct file *file, __poll_t ret = 0; struct seccomp_knotif *cur; - poll_wait(file, &filter->wqh, poll_tab); + poll_wait(file, &filter->notif->wqh, poll_tab); if (mutex_lock_interruptible(&filter->notify_lock) < 0) return EPOLLERR; @@ -1530,9 +1218,6 @@ static __poll_t seccomp_notify_poll(struct file *file, mutex_unlock(&filter->notify_lock); - if (refcount_read(&filter->users) == 0) - ret |= EPOLLHUP; - return ret; } @@ -1555,6 +1240,7 @@ static struct file *init_listener(struct seccomp_filter *filter) sema_init(&filter->notif->request, 0); filter->notif->next_id = get_random_u64(); INIT_LIST_HEAD(&filter->notif->notifications); + init_waitqueue_head(&filter->notif->wqh); ret = anon_inode_getfile("seccomp notify", &seccomp_notify_ops, filter, O_RDWR); @@ -1566,7 +1252,7 @@ static struct file *init_listener(struct seccomp_filter *filter) out_notif: if (IS_ERR(ret)) - seccomp_notify_free(filter); + kfree(filter->notif); out: return ret; } @@ -1687,7 +1373,6 @@ out_put_fd: listener_f->private_data = NULL; fput(listener_f); put_unused_fd(listener); - seccomp_notify_detach(prepared); } else { fd_install(listener, listener_f); ret = listener; @@ -2035,7 +1720,7 @@ static bool seccomp_actions_logged_from_names(u32 *actions_logged, char *names) return true; } -static int read_actions_logged(struct ctl_table *ro_table, void *buffer, +static int read_actions_logged(struct ctl_table *ro_table, void __user *buffer, size_t *lenp, loff_t *ppos) { char names[sizeof(seccomp_actions_avail)]; @@ -2053,7 +1738,7 @@ static int read_actions_logged(struct ctl_table *ro_table, void *buffer, return proc_dostring(&table, 0, buffer, lenp, ppos); } -static int write_actions_logged(struct ctl_table *ro_table, void *buffer, +static int write_actions_logged(struct ctl_table *ro_table, void __user *buffer, size_t *lenp, loff_t *ppos, u32 *actions_logged) { char names[sizeof(seccomp_actions_avail)]; @@ -2115,7 +1800,7 @@ static void audit_actions_logged(u32 actions_logged, u32 old_actions_logged, } static int seccomp_actions_logged_handler(struct ctl_table *ro_table, int write, - void *buffer, size_t *lenp, + void __user *buffer, size_t *lenp, loff_t *ppos) { int ret; @@ -2161,7 +1846,7 @@ static int __init seccomp_sysctl_init(void) hdr = register_sysctl_paths(seccomp_sysctl_path, seccomp_sysctl_table); if (!hdr) - pr_warn("sysctl registration failed\n"); + pr_warn("seccomp: sysctl registration failed\n"); else kmemleak_not_leak(hdr); diff --git a/kernel/stackleak.c b/kernel/stackleak.c index b54bf2770bce..b193a59fc05b 100644 --- a/kernel/stackleak.c +++ b/kernel/stackleak.c @@ -20,7 +20,7 @@ static DEFINE_STATIC_KEY_FALSE(stack_erasing_bypass); int stack_erasing_sysctl(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int ret = 0; int state = !static_branch_unlikely(&stack_erasing_bypass); diff --git a/kernel/sys.c b/kernel/sys.c index 3ed05f046c92..fa3f48a51aa9 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -2005,15 +2005,12 @@ static int prctl_set_mm_map(int opt, const void __user *addr, unsigned long data if (prctl_map.exe_fd != (u32)-1) { /* - * Check if the current user is checkpoint/restore capable. - * At the time of this writing, it checks for CAP_SYS_ADMIN - * or CAP_CHECKPOINT_RESTORE. - * Note that a user with access to ptrace can masquerade an - * arbitrary program as any executable, even setuid ones. - * This may have implications in the tomoyo subsystem. + * Make sure the caller has the rights to + * change /proc/pid/exe link: only local sys admin should + * be allowed to. */ - if (!checkpoint_restore_ns_capable(current_user_ns())) - return -EPERM; + if (!ns_capable(current_user_ns(), CAP_SYS_ADMIN)) + return -EINVAL; error = prctl_set_mm_exe_file(mm, prctl_map.exe_fd); if (error) diff --git a/kernel/sys_ni.c b/kernel/sys_ni.c index b3ee8641e44a..9925446f9c54 100644 --- a/kernel/sys_ni.c +++ b/kernel/sys_ni.c @@ -68,8 +68,6 @@ COND_SYSCALL(epoll_create1); COND_SYSCALL(epoll_ctl); COND_SYSCALL(epoll_pwait); COND_SYSCALL_COMPAT(epoll_pwait); -COND_SYSCALL(epoll_pwait2); -COND_SYSCALL_COMPAT(epoll_pwait2); /* fs/fcntl.c */ diff --git a/kernel/sysctl.c b/kernel/sysctl.c index 6ec1bb514ecd..6a8fd496fd2f 100644 --- a/kernel/sysctl.c +++ b/kernel/sysctl.c @@ -236,31 +236,31 @@ enum sysctl_writes_mode { static enum sysctl_writes_mode sysctl_writes_strict = SYSCTL_WRITES_STRICT; static int proc_do_cad_pid(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); static int proc_taint(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); #endif #ifdef CONFIG_PRINTK static int proc_dointvec_minmax_sysadmin(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); #endif static int proc_dointvec_minmax_coredump(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); #ifdef CONFIG_COREDUMP static int proc_dostring_coredump(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); #endif static int proc_dopipe_max_size(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, loff_t *ppos); #ifdef CONFIG_MAGIC_SYSRQ /* Note: sysrq code uses its own private copy */ static int __sysrq_enabled = CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE; static int sysrq_sysctl_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, + void __user *buffer, size_t *lenp, loff_t *ppos) { int error; @@ -373,39 +373,6 @@ static int min_extfrag_threshold; static int max_extfrag_threshold = 1000; #endif -#ifdef CONFIG_BPF_SYSCALL -static int bpf_stats_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) -{ - struct static_key *key = (struct static_key *)table->data; - static int saved_val; - int val, ret; - struct ctl_table tmp = { - .data = &val, - .maxlen = sizeof(val), - .mode = table->mode, - .extra1 = SYSCTL_ZERO, - .extra2 = SYSCTL_ONE, - }; - - if (write && !capable(CAP_SYS_ADMIN)) - return -EPERM; - - mutex_lock(&bpf_stats_enabled_mutex); - val = saved_val; - ret = proc_dointvec_minmax(&tmp, write, buffer, lenp, ppos); - if (write && !ret && val != saved_val) { - if (val) - static_key_slow_inc(key); - else - static_key_slow_dec(key); - saved_val = val; - } - mutex_unlock(&bpf_stats_enabled_mutex); - return ret; -} -#endif - static struct ctl_table kern_table[] = { { .procname = "sched_child_runs_first", @@ -1659,7 +1626,7 @@ static struct ctl_table kern_table[] = { .data = &bpf_stats_enabled_key.key, .maxlen = sizeof(bpf_stats_enabled_key), .mode = 0644, - .proc_handler = bpf_stats_handler, + .proc_handler = proc_do_static_key, }, #endif #if defined(CONFIG_TREE_RCU) || defined(CONFIG_PREEMPT_RCU) @@ -2437,10 +2404,12 @@ int __init sysctl_init(void) #ifdef CONFIG_PROC_SYSCTL static int _proc_do_string(char *data, int maxlen, int write, - char *buffer, size_t *lenp, loff_t *ppos) + char __user *buffer, + size_t *lenp, loff_t *ppos) { size_t len; - char c, *p; + char __user *p; + char c; if (!data || !maxlen || !*lenp) { *lenp = 0; @@ -2465,7 +2434,8 @@ static int _proc_do_string(char *data, int maxlen, int write, *ppos += *lenp; p = buffer; while ((p - buffer) < *lenp && len < maxlen - 1) { - c = *(p++); + if (get_user(c, p++)) + return -EFAULT; if (c == 0 || c == '\n') break; data[len++] = c; @@ -2487,9 +2457,11 @@ static int _proc_do_string(char *data, int maxlen, int write, if (len > *lenp) len = *lenp; if (len) - memcpy(buffer, data, len); + if (copy_to_user(buffer, data, len)) + return -EFAULT; if (len < *lenp) { - buffer[len] = '\n'; + if (put_user('\n', buffer + len)) + return -EFAULT; len++; } *lenp = len; @@ -2550,13 +2522,13 @@ static bool proc_first_pos_non_zero_ignore(loff_t *ppos, * Returns 0 on success. */ int proc_dostring(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { if (write) proc_first_pos_non_zero_ignore(ppos, table); - return _proc_do_string(table->data, table->maxlen, write, buffer, lenp, - ppos); + return _proc_do_string((char *)(table->data), table->maxlen, write, + (char __user *)buffer, lenp, ppos); } static void proc_skip_spaces(char **buf, size_t *size) @@ -2687,10 +2659,11 @@ static int proc_get_long(char **buf, size_t *size, * @val: the integer to be converted * @neg: sign of the number, %TRUE for negative * - * In case of success @buf and @size are updated with the amount of bytes - * written. + * In case of success %0 is returned and @buf and @size are updated with + * the amount of bytes written. */ -static void proc_put_long(void **buf, size_t *size, unsigned long val, bool neg) +static int proc_put_long(void __user **buf, size_t *size, unsigned long val, + bool neg) { int len; char tmp[TMPBUFLEN], *p = tmp; @@ -2699,22 +2672,24 @@ static void proc_put_long(void **buf, size_t *size, unsigned long val, bool neg) len = strlen(tmp); if (len > *size) len = *size; - memcpy(*buf, tmp, len); + if (copy_to_user(*buf, tmp, len)) + return -EFAULT; *size -= len; *buf += len; + return 0; } #undef TMPBUFLEN -static void proc_put_char(void **buf, size_t *size, char c) +static int proc_put_char(void __user **buf, size_t *size, char c) { if (*size) { - char **buffer = (char **)buf; - **buffer = c; - - (*size)--; - (*buffer)++; + char __user **buffer = (char __user **)buf; + if (put_user(c, *buffer)) + return -EFAULT; + (*size)--, (*buffer)++; *buf = *buffer; } + return 0; } static int do_proc_dointvec_conv(bool *negp, unsigned long *lvalp, @@ -2762,7 +2737,7 @@ static int do_proc_douintvec_conv(unsigned long *lvalp, static const char proc_wspace_sep[] = { ' ', '\t', '\n' }; static int __do_proc_dointvec(void *tbl_data, struct ctl_table *table, - int write, void *buffer, + int write, void __user *buffer, size_t *lenp, loff_t *ppos, int (*conv)(bool *negp, unsigned long *lvalp, int *valp, int write, void *data), @@ -2770,7 +2745,7 @@ static int __do_proc_dointvec(void *tbl_data, struct ctl_table *table, { int *i, vleft, first = 1, err = 0; size_t left; - char *p; + char *kbuf = NULL, *p; if (!tbl_data || !table->maxlen || !*lenp || (*ppos && !write)) { *lenp = 0; @@ -2790,7 +2765,9 @@ static int __do_proc_dointvec(void *tbl_data, struct ctl_table *table, if (left > PAGE_SIZE - 1) left = PAGE_SIZE - 1; - p = buffer; + p = kbuf = memdup_user_nul(buffer, left); + if (IS_ERR(kbuf)) + return PTR_ERR(kbuf); } for (; left && vleft--; i++, first=0) { @@ -2817,17 +2794,24 @@ static int __do_proc_dointvec(void *tbl_data, struct ctl_table *table, break; } if (!first) - proc_put_char(&buffer, &left, '\t'); - proc_put_long(&buffer, &left, lval, neg); + err = proc_put_char(&buffer, &left, '\t'); + if (err) + break; + err = proc_put_long(&buffer, &left, lval, neg); + if (err) + break; } } if (!write && !first && left && !err) - proc_put_char(&buffer, &left, '\n'); + err = proc_put_char(&buffer, &left, '\n'); if (write && !err && left) proc_skip_spaces(&p, &left); - if (write && first) - return err ? : -EINVAL; + if (write) { + kfree(kbuf); + if (first) + return err ? : -EINVAL; + } *lenp -= left; out: *ppos += *lenp; @@ -2835,7 +2819,7 @@ out: } static int do_proc_dointvec(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos, + void __user *buffer, size_t *lenp, loff_t *ppos, int (*conv)(bool *negp, unsigned long *lvalp, int *valp, int write, void *data), void *data) @@ -2846,7 +2830,7 @@ static int do_proc_dointvec(struct ctl_table *table, int write, static int do_proc_douintvec_w(unsigned int *tbl_data, struct ctl_table *table, - void *buffer, + void __user *buffer, size_t *lenp, loff_t *ppos, int (*conv)(unsigned long *lvalp, unsigned int *valp, @@ -2857,7 +2841,7 @@ static int do_proc_douintvec_w(unsigned int *tbl_data, int err = 0; size_t left; bool neg; - char *p = buffer; + char *kbuf = NULL, *p; left = *lenp; @@ -2867,6 +2851,10 @@ static int do_proc_douintvec_w(unsigned int *tbl_data, if (left > PAGE_SIZE - 1) left = PAGE_SIZE - 1; + p = kbuf = memdup_user_nul(buffer, left); + if (IS_ERR(kbuf)) + return -EINVAL; + proc_skip_spaces(&p, &left); if (!left) { err = -EINVAL; @@ -2890,6 +2878,7 @@ static int do_proc_douintvec_w(unsigned int *tbl_data, proc_skip_spaces(&p, &left); out_free: + kfree(kbuf); if (err) return -EINVAL; @@ -2901,7 +2890,7 @@ bail_early: return err; } -static int do_proc_douintvec_r(unsigned int *tbl_data, void *buffer, +static int do_proc_douintvec_r(unsigned int *tbl_data, void __user *buffer, size_t *lenp, loff_t *ppos, int (*conv)(unsigned long *lvalp, unsigned int *valp, @@ -2919,11 +2908,11 @@ static int do_proc_douintvec_r(unsigned int *tbl_data, void *buffer, goto out; } - proc_put_long(&buffer, &left, lval, false); - if (!left) + err = proc_put_long(&buffer, &left, lval, false); + if (err || !left) goto out; - proc_put_char(&buffer, &left, '\n'); + err = proc_put_char(&buffer, &left, '\n'); out: *lenp -= left; @@ -2933,7 +2922,7 @@ out: } static int __do_proc_douintvec(void *tbl_data, struct ctl_table *table, - int write, void *buffer, + int write, void __user *buffer, size_t *lenp, loff_t *ppos, int (*conv)(unsigned long *lvalp, unsigned int *valp, @@ -2969,7 +2958,7 @@ static int __do_proc_douintvec(void *tbl_data, struct ctl_table *table, } static int do_proc_douintvec(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos, + void __user *buffer, size_t *lenp, loff_t *ppos, int (*conv)(unsigned long *lvalp, unsigned int *valp, int write, void *data), @@ -2992,8 +2981,8 @@ static int do_proc_douintvec(struct ctl_table *table, int write, * * Returns 0 on success. */ -int proc_dointvec(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos) +int proc_dointvec(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) { return do_proc_dointvec(table, write, buffer, lenp, ppos, NULL, NULL); } @@ -3011,8 +3000,8 @@ int proc_dointvec(struct ctl_table *table, int write, void *buffer, * * Returns 0 on success. */ -int proc_douintvec(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos) +int proc_douintvec(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) { return do_proc_douintvec(table, write, buffer, lenp, ppos, do_proc_douintvec_conv, NULL); @@ -3023,7 +3012,7 @@ int proc_douintvec(struct ctl_table *table, int write, void *buffer, * This means we can safely use a temporary. */ static int proc_taint(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ctl_table t; unsigned long tmptaint = get_taint(); @@ -3055,7 +3044,7 @@ static int proc_taint(struct ctl_table *table, int write, #ifdef CONFIG_PRINTK static int proc_dointvec_minmax_sysadmin(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { if (write && !capable(CAP_SYS_ADMIN)) return -EPERM; @@ -3121,7 +3110,7 @@ static int do_proc_dointvec_minmax_conv(bool *negp, unsigned long *lvalp, * Returns 0 on success or -EINVAL on write when the range check fails. */ int proc_dointvec_minmax(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct do_proc_dointvec_minmax_conv_param param = { .min = (int *) table->extra1, @@ -3190,7 +3179,7 @@ static int do_proc_douintvec_minmax_conv(unsigned long *lvalp, * Returns 0 on success or -ERANGE on write when the range check fails. */ int proc_douintvec_minmax(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct do_proc_douintvec_minmax_conv_param param = { .min = (unsigned int *) table->extra1, @@ -3221,7 +3210,7 @@ static int do_proc_dopipe_max_size_conv(unsigned long *lvalp, } static int proc_dopipe_max_size(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return do_proc_douintvec(table, write, buffer, lenp, ppos, do_proc_dopipe_max_size_conv, NULL); @@ -3242,7 +3231,7 @@ static void validate_coredump_safety(void) } static int proc_dointvec_minmax_coredump(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int error = proc_dointvec_minmax(table, write, buffer, lenp, ppos); if (!error) @@ -3252,7 +3241,7 @@ static int proc_dointvec_minmax_coredump(struct ctl_table *table, int write, #ifdef CONFIG_COREDUMP static int proc_dostring_coredump(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int error = proc_dostring(table, write, buffer, lenp, ppos); if (!error) @@ -3261,14 +3250,16 @@ static int proc_dostring_coredump(struct ctl_table *table, int write, } #endif -static int __do_proc_doulongvec_minmax(void *data, struct ctl_table *table, - int write, void *buffer, size_t *lenp, loff_t *ppos, - unsigned long convmul, unsigned long convdiv) +static int __do_proc_doulongvec_minmax(void *data, struct ctl_table *table, int write, + void __user *buffer, + size_t *lenp, loff_t *ppos, + unsigned long convmul, + unsigned long convdiv) { unsigned long *i, *min, *max; int vleft, first = 1, err = 0; size_t left; - char *p; + char *kbuf = NULL, *p; if (!data || !table->maxlen || !*lenp || (*ppos && !write)) { *lenp = 0; @@ -3287,7 +3278,9 @@ static int __do_proc_doulongvec_minmax(void *data, struct ctl_table *table, if (left > PAGE_SIZE - 1) left = PAGE_SIZE - 1; - p = buffer; + p = kbuf = memdup_user_nul(buffer, left); + if (IS_ERR(kbuf)) + return PTR_ERR(kbuf); } for (; left && vleft--; i++, first = 0) { @@ -3315,18 +3308,26 @@ static int __do_proc_doulongvec_minmax(void *data, struct ctl_table *table, *i = val; } else { val = convdiv * (*i) / convmul; - if (!first) - proc_put_char(&buffer, &left, '\t'); - proc_put_long(&buffer, &left, val, false); + if (!first) { + err = proc_put_char(&buffer, &left, '\t'); + if (err) + break; + } + err = proc_put_long(&buffer, &left, val, false); + if (err) + break; } } if (!write && !first && left && !err) - proc_put_char(&buffer, &left, '\n'); + err = proc_put_char(&buffer, &left, '\n'); if (write && !err) proc_skip_spaces(&p, &left); - if (write && first) - return err ? : -EINVAL; + if (write) { + kfree(kbuf); + if (first) + return err ? : -EINVAL; + } *lenp -= left; out: *ppos += *lenp; @@ -3334,8 +3335,10 @@ out: } static int do_proc_doulongvec_minmax(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos, unsigned long convmul, - unsigned long convdiv) + void __user *buffer, + size_t *lenp, loff_t *ppos, + unsigned long convmul, + unsigned long convdiv) { return __do_proc_doulongvec_minmax(table->data, table, write, buffer, lenp, ppos, convmul, convdiv); @@ -3358,7 +3361,7 @@ static int do_proc_doulongvec_minmax(struct ctl_table *table, int write, * Returns 0 on success. */ int proc_doulongvec_minmax(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return do_proc_doulongvec_minmax(table, write, buffer, lenp, ppos, 1l, 1l); } @@ -3381,7 +3384,8 @@ int proc_doulongvec_minmax(struct ctl_table *table, int write, * Returns 0 on success. */ int proc_doulongvec_ms_jiffies_minmax(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { return do_proc_doulongvec_minmax(table, write, buffer, lenp, ppos, HZ, 1000l); @@ -3475,7 +3479,7 @@ static int do_proc_dointvec_ms_jiffies_conv(bool *negp, unsigned long *lvalp, * Returns 0 on success. */ int proc_dointvec_jiffies(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return do_proc_dointvec(table,write,buffer,lenp,ppos, do_proc_dointvec_jiffies_conv,NULL); @@ -3497,7 +3501,7 @@ int proc_dointvec_jiffies(struct ctl_table *table, int write, * Returns 0 on success. */ int proc_dointvec_userhz_jiffies(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return do_proc_dointvec(table,write,buffer,lenp,ppos, do_proc_dointvec_userhz_jiffies_conv,NULL); @@ -3519,15 +3523,15 @@ int proc_dointvec_userhz_jiffies(struct ctl_table *table, int write, * * Returns 0 on success. */ -int proc_dointvec_ms_jiffies(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos) +int proc_dointvec_ms_jiffies(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) { return do_proc_dointvec(table, write, buffer, lenp, ppos, do_proc_dointvec_ms_jiffies_conv, NULL); } -static int proc_do_cad_pid(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos) +static int proc_do_cad_pid(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) { struct pid *new_pid; pid_t tmp; @@ -3566,7 +3570,7 @@ static int proc_do_cad_pid(struct ctl_table *table, int write, void *buffer, * Returns 0 on success. */ int proc_do_large_bitmap(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int err = 0; bool first = 1; @@ -3582,7 +3586,7 @@ int proc_do_large_bitmap(struct ctl_table *table, int write, } if (write) { - char *p = buffer; + char *kbuf, *p; size_t skipped = 0; if (left > PAGE_SIZE - 1) { @@ -3591,9 +3595,15 @@ int proc_do_large_bitmap(struct ctl_table *table, int write, skipped = *lenp - left; } + p = kbuf = memdup_user_nul(buffer, left); + if (IS_ERR(kbuf)) + return PTR_ERR(kbuf); + tmp_bitmap = bitmap_zalloc(bitmap_len, GFP_KERNEL); - if (!tmp_bitmap) + if (!tmp_bitmap) { + kfree(kbuf); return -ENOMEM; + } proc_skip_char(&p, &left, '\n'); while (!err && left) { unsigned long val_a, val_b; @@ -3657,6 +3667,7 @@ int proc_do_large_bitmap(struct ctl_table *table, int write, first = 0; proc_skip_char(&p, &left, '\n'); } + kfree(kbuf); left += skipped; } else { unsigned long bit_a, bit_b = 0; @@ -3668,17 +3679,27 @@ int proc_do_large_bitmap(struct ctl_table *table, int write, bit_b = find_next_zero_bit(bitmap, bitmap_len, bit_a + 1) - 1; - if (!first) - proc_put_char(&buffer, &left, ','); - proc_put_long(&buffer, &left, bit_a, false); + if (!first) { + err = proc_put_char(&buffer, &left, ','); + if (err) + break; + } + err = proc_put_long(&buffer, &left, bit_a, false); + if (err) + break; if (bit_a != bit_b) { - proc_put_char(&buffer, &left, '-'); - proc_put_long(&buffer, &left, bit_b, false); + err = proc_put_char(&buffer, &left, '-'); + if (err) + break; + err = proc_put_long(&buffer, &left, bit_b, false); + if (err) + break; } first = 0; bit_b++; } - proc_put_char(&buffer, &left, '\n'); + if (!err) + err = proc_put_char(&buffer, &left, '\n'); } if (!err) { @@ -3727,7 +3748,7 @@ static int do_proc_douintvec_capacity_conv(bool *negp, unsigned long *lvalp, * Returns 0 on success. */ int proc_douintvec_capacity(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return do_proc_dointvec(table, write, buffer, lenp, ppos, do_proc_douintvec_capacity_conv, NULL); @@ -3751,7 +3772,7 @@ static int do_proc_douintvec_rwin(bool *negp, unsigned long *lvalp, } int proc_douintvec_ravg_window(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return do_proc_dointvec(table, write, buffer, lenp, ppos, do_proc_douintvec_rwin, NULL); @@ -3760,79 +3781,80 @@ int proc_douintvec_ravg_window(struct ctl_table *table, int write, #else /* CONFIG_PROC_SYSCTL */ int proc_dostring(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return -ENOSYS; } int proc_dointvec(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return -ENOSYS; } int proc_douintvec(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return -ENOSYS; } int proc_dointvec_minmax(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return -ENOSYS; } int proc_douintvec_minmax(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return -ENOSYS; } int proc_dointvec_jiffies(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return -ENOSYS; } int proc_dointvec_userhz_jiffies(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return -ENOSYS; } int proc_dointvec_ms_jiffies(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return -ENOSYS; } int proc_doulongvec_minmax(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return -ENOSYS; } int proc_doulongvec_ms_jiffies_minmax(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { - return -ENOSYS; + return -ENOSYS; } int proc_do_large_bitmap(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return -ENOSYS; } int proc_douintvec_ravg_window(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return -ENOSYS; } int proc_douintvec_capacity(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return -ENOSYS; } @@ -3841,7 +3863,8 @@ int proc_douintvec_capacity(struct ctl_table *table, int write, #if defined(CONFIG_SYSCTL) int proc_do_static_key(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { struct static_key *key = (struct static_key *)table->data; static DEFINE_MUTEX(static_key_mutex); diff --git a/kernel/time/timer.c b/kernel/time/timer.c index a76d66d456c2..777858d79484 100644 --- a/kernel/time/timer.c +++ b/kernel/time/timer.c @@ -252,7 +252,8 @@ void timers_update_nohz(void) } int timer_migration_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { int ret; diff --git a/kernel/trace/Kconfig b/kernel/trace/Kconfig index fa347a7ed8d4..57e1baf8053d 100644 --- a/kernel/trace/Kconfig +++ b/kernel/trace/Kconfig @@ -33,9 +33,6 @@ config HAVE_DYNAMIC_FTRACE config HAVE_DYNAMIC_FTRACE_WITH_REGS bool -config HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS - bool - config HAVE_FTRACE_MCOUNT_RECORD bool help @@ -630,11 +627,6 @@ config DYNAMIC_FTRACE_WITH_REGS depends on DYNAMIC_FTRACE depends on HAVE_DYNAMIC_FTRACE_WITH_REGS -config DYNAMIC_FTRACE_WITH_DIRECT_CALLS - def_bool y - depends on DYNAMIC_FTRACE - depends on HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS - config FUNCTION_PROFILER bool "Kernel function profiler" depends on FUNCTION_TRACER diff --git a/kernel/trace/Makefile b/kernel/trace/Makefile index d09dfa4226b8..f9f4512c617d 100644 --- a/kernel/trace/Makefile +++ b/kernel/trace/Makefile @@ -28,8 +28,6 @@ ifdef CONFIG_GCOV_PROFILE_FTRACE GCOV_PROFILE := y endif -CFLAGS_bpf_trace.o := -I$(src) - CFLAGS_trace_benchmark.o := -I$(src) CFLAGS_trace_events_filter.o := -I$(src) @@ -74,7 +72,6 @@ obj-$(CONFIG_EVENT_TRACING) += trace_events_trigger.o obj-$(CONFIG_HIST_TRIGGERS) += trace_events_hist.o obj-$(CONFIG_BPF_EVENTS) += bpf_trace.o obj-$(CONFIG_KPROBE_EVENTS) += trace_kprobe.o -obj-$(CONFIG_TRACEPOINTS) += error_report-traces.o obj-$(CONFIG_TRACEPOINTS) += power-traces.o ifeq ($(CONFIG_PM),y) obj-$(CONFIG_TRACEPOINTS) += rpm-traces.o diff --git a/kernel/trace/blktrace.c b/kernel/trace/blktrace.c index d0fcedac5805..abf5cbbb743b 100644 --- a/kernel/trace/blktrace.c +++ b/kernel/trace/blktrace.c @@ -67,7 +67,8 @@ static void blk_unregister_tracepoints(void); * Send out a notify message. */ static void trace_note(struct blk_trace *bt, pid_t pid, int action, - const void *data, size_t len, u64 cgid) + const void *data, size_t len, + union kernfs_node_id *cgid) { struct blk_io_trace *t; struct ring_buffer_event *event = NULL; @@ -75,7 +76,7 @@ static void trace_note(struct blk_trace *bt, pid_t pid, int action, int pc = 0; int cpu = smp_processor_id(); bool blk_tracer = blk_tracer_enabled; - ssize_t cgid_len = cgid ? sizeof(cgid) : 0; + ssize_t cgid_len = cgid ? sizeof(*cgid) : 0; if (blk_tracer) { buffer = blk_tr->trace_buffer.buffer; @@ -102,8 +103,8 @@ record_it: t->pid = pid; t->cpu = cpu; t->pdu_len = len + cgid_len; - if (cgid_len) - memcpy((void *)t + sizeof(*t), &cgid, cgid_len); + if (cgid) + memcpy((void *)t + sizeof(*t), cgid, cgid_len); memcpy((void *) t + sizeof(*t) + cgid_len, data, len); if (blk_tracer) @@ -124,7 +125,7 @@ static void trace_note_tsk(struct task_struct *tsk) spin_lock_irqsave(&running_trace_lock, flags); list_for_each_entry(bt, &running_trace_list, running_list) { trace_note(bt, tsk->pid, BLK_TN_PROCESS, tsk->comm, - sizeof(tsk->comm), 0); + sizeof(tsk->comm), NULL); } spin_unlock_irqrestore(&running_trace_lock, flags); } @@ -141,7 +142,7 @@ static void trace_note_time(struct blk_trace *bt) words[1] = now.tv_nsec; local_irq_save(flags); - trace_note(bt, 0, BLK_TN_TIMESTAMP, words, sizeof(words), 0); + trace_note(bt, 0, BLK_TN_TIMESTAMP, words, sizeof(words), NULL); local_irq_restore(flags); } @@ -174,9 +175,9 @@ void __trace_note_message(struct blk_trace *bt, struct blkcg *blkcg, blkcg = NULL; #ifdef CONFIG_BLK_CGROUP trace_note(bt, 0, BLK_TN_MESSAGE, buf, n, - blkcg ? cgroup_id(blkcg->css.cgroup) : 1); + blkcg ? cgroup_get_kernfs_id(blkcg->css.cgroup) : NULL); #else - trace_note(bt, 0, BLK_TN_MESSAGE, buf, n, 0); + trace_note(bt, 0, BLK_TN_MESSAGE, buf, n, NULL); #endif local_irq_restore(flags); } @@ -214,7 +215,7 @@ static const u32 ddir_act[2] = { BLK_TC_ACT(BLK_TC_READ), */ static void __blk_add_trace(struct blk_trace *bt, sector_t sector, int bytes, int op, int op_flags, u32 what, int error, int pdu_len, - void *pdu_data, u64 cgid) + void *pdu_data, union kernfs_node_id *cgid) { struct task_struct *tsk = current; struct ring_buffer_event *event = NULL; @@ -225,7 +226,7 @@ static void __blk_add_trace(struct blk_trace *bt, sector_t sector, int bytes, pid_t pid; int cpu, pc = 0; bool blk_tracer = blk_tracer_enabled; - ssize_t cgid_len = cgid ? sizeof(cgid) : 0; + ssize_t cgid_len = cgid ? sizeof(*cgid) : 0; if (unlikely(bt->trace_state != Blktrace_running && !blk_tracer)) return; @@ -296,7 +297,7 @@ record_it: t->pdu_len = pdu_len + cgid_len; if (cgid_len) - memcpy((void *)t + sizeof(*t), &cgid, cgid_len); + memcpy((void *)t + sizeof(*t), cgid, cgid_len); if (pdu_len) memcpy((void *)t + sizeof(*t) + cgid_len, pdu_data, pdu_len); @@ -784,31 +785,33 @@ void blk_trace_shutdown(struct request_queue *q) } #ifdef CONFIG_BLK_CGROUP -static u64 blk_trace_bio_get_cgid(struct request_queue *q, struct bio *bio) +static union kernfs_node_id * +blk_trace_bio_get_cgid(struct request_queue *q, struct bio *bio) { struct blk_trace *bt; /* We don't use the 'bt' value here except as an optimization... */ bt = rcu_dereference_protected(q->blk_trace, 1); if (!bt || !(blk_tracer_flags.val & TRACE_BLK_OPT_CGROUP)) - return 0; + return NULL; if (!bio->bi_blkg) - return 0; - return cgroup_id(bio_blkcg(bio)->css.cgroup); + return NULL; + return cgroup_get_kernfs_id(bio_blkcg(bio)->css.cgroup); } #else -u64 blk_trace_bio_get_cgid(struct request_queue *q, struct bio *bio) +static union kernfs_node_id * +blk_trace_bio_get_cgid(struct request_queue *q, struct bio *bio) { - return 0; + return NULL; } #endif -static u64 +static union kernfs_node_id * blk_trace_request_get_cgid(struct request_queue *q, struct request *rq) { if (!rq->bio) - return 0; + return NULL; /* Use the first bio */ return blk_trace_bio_get_cgid(q, rq->bio); } @@ -830,7 +833,8 @@ blk_trace_request_get_cgid(struct request_queue *q, struct request *rq) * **/ static void blk_add_trace_rq(struct request *rq, int error, - unsigned int nr_bytes, u32 what, u64 cgid) + unsigned int nr_bytes, u32 what, + union kernfs_node_id *cgid) { struct blk_trace *bt; @@ -957,7 +961,7 @@ static void blk_add_trace_getrq(void *ignore, bt = rcu_dereference(q->blk_trace); if (bt) __blk_add_trace(bt, 0, 0, rw, 0, BLK_TA_GETRQ, 0, 0, - NULL, 0); + NULL, NULL); rcu_read_unlock(); } } @@ -976,7 +980,7 @@ static void blk_add_trace_sleeprq(void *ignore, bt = rcu_dereference(q->blk_trace); if (bt) __blk_add_trace(bt, 0, 0, rw, 0, BLK_TA_SLEEPRQ, - 0, 0, NULL, 0); + 0, 0, NULL, NULL); rcu_read_unlock(); } } @@ -988,7 +992,7 @@ static void blk_add_trace_plug(void *ignore, struct request_queue *q) rcu_read_lock(); bt = rcu_dereference(q->blk_trace); if (bt) - __blk_add_trace(bt, 0, 0, 0, 0, BLK_TA_PLUG, 0, 0, NULL, 0); + __blk_add_trace(bt, 0, 0, 0, 0, BLK_TA_PLUG, 0, 0, NULL, NULL); rcu_read_unlock(); } @@ -1008,7 +1012,7 @@ static void blk_add_trace_unplug(void *ignore, struct request_queue *q, else what = BLK_TA_UNPLUG_TIMER; - __blk_add_trace(bt, 0, 0, 0, 0, what, 0, sizeof(rpdu), &rpdu, 0); + __blk_add_trace(bt, 0, 0, 0, 0, what, 0, sizeof(rpdu), &rpdu, NULL); } rcu_read_unlock(); } @@ -1247,17 +1251,19 @@ const struct blk_io_trace *te_blk_io_trace(const struct trace_entry *ent) static inline const void *pdu_start(const struct trace_entry *ent, bool has_cg) { - return (void *)(te_blk_io_trace(ent) + 1) + (has_cg ? sizeof(u64) : 0); + return (void *)(te_blk_io_trace(ent) + 1) + + (has_cg ? sizeof(union kernfs_node_id) : 0); } -static inline u64 t_cgid(const struct trace_entry *ent) +static inline const void *cgid_start(const struct trace_entry *ent) { - return *(u64 *)(te_blk_io_trace(ent) + 1); + return (void *)(te_blk_io_trace(ent) + 1); } static inline int pdu_real_len(const struct trace_entry *ent, bool has_cg) { - return te_blk_io_trace(ent)->pdu_len - (has_cg ? sizeof(u64) : 0); + return te_blk_io_trace(ent)->pdu_len - + (has_cg ? sizeof(union kernfs_node_id) : 0); } static inline u32 t_action(const struct trace_entry *ent) @@ -1319,7 +1325,7 @@ static void blk_log_action(struct trace_iterator *iter, const char *act, fill_rwbs(rwbs, t); if (has_cg) { - u64 id = t_cgid(iter->ent); + const union kernfs_node_id *id = cgid_start(iter->ent); if (blk_tracer_flags.val & TRACE_BLK_OPT_CGNAME) { char blkcg_name_buf[NAME_MAX + 1] = "<...>"; @@ -1331,10 +1337,9 @@ static void blk_log_action(struct trace_iterator *iter, const char *act, blkcg_name_buf, act, rwbs); } else trace_seq_printf(&iter->seq, - "%3d,%-3d %lx,%-x %2s %3s ", + "%3d,%-3d %x,%-x %2s %3s ", MAJOR(t->device), MINOR(t->device), - kernfs_id_ino(id), kernfs_id_gen(id), - act, rwbs); + id->ino, id->generation, act, rwbs); } else trace_seq_printf(&iter->seq, "%3d,%-3d %2s %3s ", MAJOR(t->device), MINOR(t->device), act, rwbs); diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c index a9829e3c4914..01ef204d5a98 100644 --- a/kernel/trace/bpf_trace.c +++ b/kernel/trace/bpf_trace.c @@ -7,27 +7,18 @@ #include #include #include -#include #include #include #include #include -#include #include #include -#include - -#include -#include #include #include "trace_probe.h" #include "trace.h" -#define CREATE_TRACE_POINTS -#include "bpf_trace.h" - #define bpf_event_rcu_dereference(p) \ rcu_dereference_protected(p, lockdep_is_held(&bpf_event_mutex)) @@ -71,10 +62,6 @@ static struct bpf_raw_event_map *bpf_get_raw_tracepoint_module(const char *name) u64 bpf_get_stackid(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5); u64 bpf_get_stack(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5); -static int bpf_btf_printf_prepare(struct btf_ptr *ptr, u32 btf_ptr_size, - u64 flags, const struct btf **btf, - s32 *btf_id); - /** * trace_call_bpf - invoke BPF program * @call: tracepoint event @@ -93,7 +80,10 @@ unsigned int trace_call_bpf(struct trace_event_call *call, void *ctx) { unsigned int ret; - cant_sleep(); + if (in_nmi()) /* not supported yet */ + return 1; + + preempt_disable(); if (unlikely(__this_cpu_inc_return(bpf_prog_active) != 1)) { /* @@ -125,9 +115,11 @@ unsigned int trace_call_bpf(struct trace_event_call *call, void *ctx) out: __this_cpu_dec(bpf_prog_active); + preempt_enable(); return ret; } +EXPORT_SYMBOL_GPL(trace_call_bpf); #ifdef CONFIG_BPF_KPROBE_OVERRIDE BPF_CALL_2(bpf_override_return, struct pt_regs *, regs, unsigned long, rc) @@ -146,25 +138,24 @@ static const struct bpf_func_proto bpf_override_return_proto = { }; #endif -static __always_inline int -bpf_probe_read_user_common(void *dst, u32 size, const void __user *unsafe_ptr) +BPF_CALL_3(bpf_probe_read, void *, dst, u32, size, const void *, unsafe_ptr) { int ret; - ret = copy_from_user_nofault(dst, unsafe_ptr, size); + ret = security_locked_down(LOCKDOWN_BPF_READ); + if (ret < 0) + goto out; + + ret = probe_kernel_read(dst, unsafe_ptr, size); if (unlikely(ret < 0)) +out: memset(dst, 0, size); + return ret; } -BPF_CALL_3(bpf_probe_read_user, void *, dst, u32, size, - const void __user *, unsafe_ptr) -{ - return bpf_probe_read_user_common(dst, size, unsafe_ptr); -} - -const struct bpf_func_proto bpf_probe_read_user_proto = { - .func = bpf_probe_read_user, +static const struct bpf_func_proto bpf_probe_read_proto = { + .func = bpf_probe_read, .gpl_only = true, .ret_type = RET_INTEGER, .arg1_type = ARG_PTR_TO_UNINIT_MEM, @@ -172,156 +163,6 @@ const struct bpf_func_proto bpf_probe_read_user_proto = { .arg3_type = ARG_ANYTHING, }; -static __always_inline int -bpf_probe_read_user_str_common(void *dst, u32 size, - const void __user *unsafe_ptr) -{ - int ret; - - /* - * NB: We rely on strncpy_from_user() not copying junk past the NUL - * terminator into `dst`. - * - * strncpy_from_user() does long-sized strides in the fast path. If the - * strncpy does not mask out the bytes after the NUL in `unsafe_ptr`, - * then there could be junk after the NUL in `dst`. If user takes `dst` - * and keys a hash map with it, then semantically identical strings can - * occupy multiple entries in the map. - */ - ret = strncpy_from_user_nofault(dst, unsafe_ptr, size); - if (unlikely(ret < 0)) - memset(dst, 0, size); - return ret; -} - -BPF_CALL_3(bpf_probe_read_user_str, void *, dst, u32, size, - const void __user *, unsafe_ptr) -{ - return bpf_probe_read_user_str_common(dst, size, unsafe_ptr); -} - -const struct bpf_func_proto bpf_probe_read_user_str_proto = { - .func = bpf_probe_read_user_str, - .gpl_only = true, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_UNINIT_MEM, - .arg2_type = ARG_CONST_SIZE_OR_ZERO, - .arg3_type = ARG_ANYTHING, -}; - -static __always_inline int -bpf_probe_read_kernel_common(void *dst, u32 size, const void *unsafe_ptr) -{ - int ret = security_locked_down(LOCKDOWN_BPF_READ); - - if (unlikely(ret < 0)) - goto fail; - ret = copy_from_kernel_nofault(dst, unsafe_ptr, size); - if (unlikely(ret < 0)) - goto fail; - return ret; -fail: - memset(dst, 0, size); - return ret; -} - -BPF_CALL_3(bpf_probe_read_kernel, void *, dst, u32, size, - const void *, unsafe_ptr) -{ - return bpf_probe_read_kernel_common(dst, size, unsafe_ptr); -} - -const struct bpf_func_proto bpf_probe_read_kernel_proto = { - .func = bpf_probe_read_kernel, - .gpl_only = true, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_UNINIT_MEM, - .arg2_type = ARG_CONST_SIZE_OR_ZERO, - .arg3_type = ARG_ANYTHING, -}; - -static __always_inline int -bpf_probe_read_kernel_str_common(void *dst, u32 size, const void *unsafe_ptr) -{ - int ret = security_locked_down(LOCKDOWN_BPF_READ); - - if (unlikely(ret < 0)) - goto fail; - - /* - * The strncpy_from_kernel_nofault() call will likely not fill the - * entire buffer, but that's okay in this circumstance as we're probing - * arbitrary memory anyway similar to bpf_probe_read_*() and might - * as well probe the stack. Thus, memory is explicitly cleared - * only in error case, so that improper users ignoring return - * code altogether don't copy garbage; otherwise length of string - * is returned that can be used for bpf_perf_event_output() et al. - */ - ret = strncpy_from_kernel_nofault(dst, unsafe_ptr, size); - if (unlikely(ret < 0)) - goto fail; - - return 0; -fail: - memset(dst, 0, size); - return ret; -} - -BPF_CALL_3(bpf_probe_read_kernel_str, void *, dst, u32, size, - const void *, unsafe_ptr) -{ - return bpf_probe_read_kernel_str_common(dst, size, unsafe_ptr); -} - -const struct bpf_func_proto bpf_probe_read_kernel_str_proto = { - .func = bpf_probe_read_kernel_str, - .gpl_only = true, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_UNINIT_MEM, - .arg2_type = ARG_CONST_SIZE_OR_ZERO, - .arg3_type = ARG_ANYTHING, -}; - -#ifdef CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE -BPF_CALL_3(bpf_probe_read_compat, void *, dst, u32, size, - const void *, unsafe_ptr) -{ - if ((unsigned long)unsafe_ptr < TASK_SIZE) { - return bpf_probe_read_user_common(dst, size, - (__force void __user *)unsafe_ptr); - } - return bpf_probe_read_kernel_common(dst, size, unsafe_ptr); -} - -static const struct bpf_func_proto bpf_probe_read_compat_proto = { - .func = bpf_probe_read_compat, - .gpl_only = true, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_UNINIT_MEM, - .arg2_type = ARG_CONST_SIZE_OR_ZERO, - .arg3_type = ARG_ANYTHING, -}; - -BPF_CALL_3(bpf_probe_read_compat_str, void *, dst, u32, size, - const void *, unsafe_ptr) -{ - if ((unsigned long)unsafe_ptr < TASK_SIZE) { - return bpf_probe_read_user_str_common(dst, size, - (__force void __user *)unsafe_ptr); - } - return bpf_probe_read_kernel_str_common(dst, size, unsafe_ptr); -} - -static const struct bpf_func_proto bpf_probe_read_compat_str_proto = { - .func = bpf_probe_read_compat_str, - .gpl_only = true, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_UNINIT_MEM, - .arg2_type = ARG_CONST_SIZE_OR_ZERO, - .arg3_type = ARG_ANYTHING, -}; -#endif /* CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE */ - BPF_CALL_3(bpf_probe_write_user, void __user *, unsafe_ptr, const void *, src, u32, size) { @@ -346,7 +187,7 @@ BPF_CALL_3(bpf_probe_write_user, void __user *, unsafe_ptr, const void *, src, if (unlikely(!nmi_uaccess_okay())) return -EPERM; - return copy_to_user_nofault(unsafe_ptr, src, size); + return probe_user_write(unsafe_ptr, src, size); } static const struct bpf_func_proto bpf_probe_write_user_proto = { @@ -360,75 +201,25 @@ static const struct bpf_func_proto bpf_probe_write_user_proto = { static const struct bpf_func_proto *bpf_get_probe_write_proto(void) { - if (!capable(CAP_SYS_ADMIN)) - return NULL; - pr_warn_ratelimited("%s[%d] is installing a program with bpf_probe_write_user helper that may corrupt user memory!", current->comm, task_pid_nr(current)); return &bpf_probe_write_user_proto; } -static void bpf_trace_copy_string(char *buf, void *unsafe_ptr, char fmt_ptype, - size_t bufsz) -{ - void __user *user_ptr = (__force void __user *)unsafe_ptr; - - buf[0] = 0; - - switch (fmt_ptype) { - case 's': -#ifdef CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE - if ((unsigned long)unsafe_ptr < TASK_SIZE) { - strncpy_from_user_nofault(buf, user_ptr, bufsz); - break; - } - fallthrough; -#endif - case 'k': - strncpy_from_kernel_nofault(buf, unsafe_ptr, bufsz); - break; - case 'u': - strncpy_from_user_nofault(buf, user_ptr, bufsz); - break; - } -} - -static DEFINE_RAW_SPINLOCK(trace_printk_lock); - -#define BPF_TRACE_PRINTK_SIZE 1024 - -static __printf(1, 0) int bpf_do_trace_printk(const char *fmt, ...) -{ - static char buf[BPF_TRACE_PRINTK_SIZE]; - unsigned long flags; - va_list ap; - int ret; - - raw_spin_lock_irqsave(&trace_printk_lock, flags); - va_start(ap, fmt); - ret = vsnprintf(buf, sizeof(buf), fmt, ap); - va_end(ap); - /* vsnprintf() will not append null for zero-length strings */ - if (ret == 0) - buf[0] = '\0'; - trace_bpf_trace_printk(buf); - raw_spin_unlock_irqrestore(&trace_printk_lock, flags); - - return ret; -} - /* * Only limited trace_printk() conversion specifiers allowed: - * %d %i %u %x %ld %li %lu %lx %lld %lli %llu %llx %p %pB %pks %pus %s + * %d %i %u %x %ld %li %lu %lx %lld %lli %llu %llx %p %s */ BPF_CALL_5(bpf_trace_printk, char *, fmt, u32, fmt_size, u64, arg1, u64, arg2, u64, arg3) { - int i, mod[3] = {}, fmt_cnt = 0; - char buf[64], fmt_ptype; - void *unsafe_ptr = NULL; bool str_seen = false; + int mod[3] = {}; + int fmt_cnt = 0; + u64 unsafe_addr; + char buf[64]; + int i; /* * bpf_check()->check_func_arg()->check_stack_boundary() @@ -454,60 +245,40 @@ BPF_CALL_5(bpf_trace_printk, char *, fmt, u32, fmt_size, u64, arg1, if (fmt[i] == 'l') { mod[fmt_cnt]++; i++; - } else if (fmt[i] == 'p') { + } else if (fmt[i] == 'p' || fmt[i] == 's') { mod[fmt_cnt]++; - if ((fmt[i + 1] == 'k' || - fmt[i + 1] == 'u') && - fmt[i + 2] == 's') { - fmt_ptype = fmt[i + 1]; - i += 2; - goto fmt_str; - } - - if (fmt[i + 1] == 'B') { - i++; - goto fmt_next; - } - /* disallow any further format extensions */ if (fmt[i + 1] != 0 && !isspace(fmt[i + 1]) && !ispunct(fmt[i + 1])) return -EINVAL; + fmt_cnt++; + if (fmt[i] == 's') { + if (str_seen) + /* allow only one '%s' per fmt string */ + return -EINVAL; + str_seen = true; - goto fmt_next; - } else if (fmt[i] == 's') { - mod[fmt_cnt]++; - fmt_ptype = fmt[i]; -fmt_str: - if (str_seen) - /* allow only one '%s' per fmt string */ - return -EINVAL; - str_seen = true; - - if (fmt[i + 1] != 0 && - !isspace(fmt[i + 1]) && - !ispunct(fmt[i + 1])) - return -EINVAL; - - switch (fmt_cnt) { - case 0: - unsafe_ptr = (void *)(long)arg1; - arg1 = (long)buf; - break; - case 1: - unsafe_ptr = (void *)(long)arg2; - arg2 = (long)buf; - break; - case 2: - unsafe_ptr = (void *)(long)arg3; - arg3 = (long)buf; - break; + switch (fmt_cnt) { + case 1: + unsafe_addr = arg1; + arg1 = (long) buf; + break; + case 2: + unsafe_addr = arg2; + arg2 = (long) buf; + break; + case 3: + unsafe_addr = arg3; + arg3 = (long) buf; + break; + } + buf[0] = 0; + strncpy_from_unsafe(buf, + (void *) (long) unsafe_addr, + sizeof(buf)); } - - bpf_trace_copy_string(buf, unsafe_ptr, fmt_ptype, - sizeof(buf)); - goto fmt_next; + continue; } if (fmt[i] == 'l') { @@ -518,7 +289,6 @@ fmt_str: if (fmt[i] != 'i' && fmt[i] != 'd' && fmt[i] != 'u' && fmt[i] != 'x') return -EINVAL; -fmt_next: fmt_cnt++; } @@ -527,7 +297,8 @@ fmt_next: */ #define __BPF_TP_EMIT() __BPF_ARG3_TP() #define __BPF_TP(...) \ - bpf_do_trace_printk(fmt, ##__VA_ARGS__) + __trace_printk(0 /* Fake ip */, \ + fmt, ##__VA_ARGS__) #define __BPF_ARG1_TP(...) \ ((mod[0] == 2 || (mod[0] == 1 && __BITS_PER_LONG == 64)) \ @@ -564,254 +335,14 @@ static const struct bpf_func_proto bpf_trace_printk_proto = { const struct bpf_func_proto *bpf_get_trace_printk_proto(void) { /* - * This program might be calling bpf_trace_printk, - * so enable the associated bpf_trace/bpf_trace_printk event. - * Repeat this each time as it is possible a user has - * disabled bpf_trace_printk events. By loading a program - * calling bpf_trace_printk() however the user has expressed - * the intent to see such events. + * this program might be calling bpf_trace_printk, + * so allocate per-cpu printk buffers */ - if (trace_set_clr_event("bpf_trace", "bpf_trace_printk", 1)) - pr_warn_ratelimited("could not enable bpf_trace_printk events"); + trace_printk_init_buffers(); return &bpf_trace_printk_proto; } -#define MAX_SEQ_PRINTF_VARARGS 12 -#define MAX_SEQ_PRINTF_MAX_MEMCPY 6 -#define MAX_SEQ_PRINTF_STR_LEN 128 - -struct bpf_seq_printf_buf { - char buf[MAX_SEQ_PRINTF_MAX_MEMCPY][MAX_SEQ_PRINTF_STR_LEN]; -}; -static DEFINE_PER_CPU(struct bpf_seq_printf_buf, bpf_seq_printf_buf); -static DEFINE_PER_CPU(int, bpf_seq_printf_buf_used); - -BPF_CALL_5(bpf_seq_printf, struct seq_file *, m, char *, fmt, u32, fmt_size, - const void *, data, u32, data_len) -{ - int err = -EINVAL, fmt_cnt = 0, memcpy_cnt = 0; - int i, buf_used, copy_size, num_args; - u64 params[MAX_SEQ_PRINTF_VARARGS]; - struct bpf_seq_printf_buf *bufs; - const u64 *args = data; - - buf_used = this_cpu_inc_return(bpf_seq_printf_buf_used); - if (WARN_ON_ONCE(buf_used > 1)) { - err = -EBUSY; - goto out; - } - - bufs = this_cpu_ptr(&bpf_seq_printf_buf); - - /* - * bpf_check()->check_func_arg()->check_stack_boundary() - * guarantees that fmt points to bpf program stack, - * fmt_size bytes of it were initialized and fmt_size > 0 - */ - if (fmt[--fmt_size] != 0) - goto out; - - if (data_len & 7) - goto out; - - for (i = 0; i < fmt_size; i++) { - if (fmt[i] == '%') { - if (fmt[i + 1] == '%') - i++; - else if (!data || !data_len) - goto out; - } - } - - num_args = data_len / 8; - - /* check format string for allowed specifiers */ - for (i = 0; i < fmt_size; i++) { - /* only printable ascii for now. */ - if ((!isprint(fmt[i]) && !isspace(fmt[i])) || !isascii(fmt[i])) { - err = -EINVAL; - goto out; - } - - if (fmt[i] != '%') - continue; - - if (fmt[i + 1] == '%') { - i++; - continue; - } - - if (fmt_cnt >= MAX_SEQ_PRINTF_VARARGS) { - err = -E2BIG; - goto out; - } - - if (fmt_cnt >= num_args) { - err = -EINVAL; - goto out; - } - - /* fmt[i] != 0 && fmt[last] == 0, so we can access fmt[i + 1] */ - i++; - - /* skip optional "[0 +-][num]" width formating field */ - while (fmt[i] == '0' || fmt[i] == '+' || fmt[i] == '-' || - fmt[i] == ' ') - i++; - if (fmt[i] >= '1' && fmt[i] <= '9') { - i++; - while (fmt[i] >= '0' && fmt[i] <= '9') - i++; - } - - if (fmt[i] == 's') { - void *unsafe_ptr; - - /* try our best to copy */ - if (memcpy_cnt >= MAX_SEQ_PRINTF_MAX_MEMCPY) { - err = -E2BIG; - goto out; - } - - unsafe_ptr = (void *)(long)args[fmt_cnt]; - err = strncpy_from_kernel_nofault(bufs->buf[memcpy_cnt], - unsafe_ptr, MAX_SEQ_PRINTF_STR_LEN); - if (err < 0) - bufs->buf[memcpy_cnt][0] = '\0'; - params[fmt_cnt] = (u64)(long)bufs->buf[memcpy_cnt]; - - fmt_cnt++; - memcpy_cnt++; - continue; - } - - if (fmt[i] == 'p') { - if (fmt[i + 1] == 0 || - fmt[i + 1] == 'K' || - fmt[i + 1] == 'x' || - fmt[i + 1] == 'B') { - /* just kernel pointers */ - params[fmt_cnt] = args[fmt_cnt]; - fmt_cnt++; - continue; - } - - /* only support "%pI4", "%pi4", "%pI6" and "%pi6". */ - if (fmt[i + 1] != 'i' && fmt[i + 1] != 'I') { - err = -EINVAL; - goto out; - } - if (fmt[i + 2] != '4' && fmt[i + 2] != '6') { - err = -EINVAL; - goto out; - } - - if (memcpy_cnt >= MAX_SEQ_PRINTF_MAX_MEMCPY) { - err = -E2BIG; - goto out; - } - - - copy_size = (fmt[i + 2] == '4') ? 4 : 16; - - err = copy_from_kernel_nofault(bufs->buf[memcpy_cnt], - (void *) (long) args[fmt_cnt], - copy_size); - if (err < 0) - memset(bufs->buf[memcpy_cnt], 0, copy_size); - params[fmt_cnt] = (u64)(long)bufs->buf[memcpy_cnt]; - - i += 2; - fmt_cnt++; - memcpy_cnt++; - continue; - } - - if (fmt[i] == 'l') { - i++; - if (fmt[i] == 'l') - i++; - } - - if (fmt[i] != 'i' && fmt[i] != 'd' && - fmt[i] != 'u' && fmt[i] != 'x' && - fmt[i] != 'X') { - err = -EINVAL; - goto out; - } - - params[fmt_cnt] = args[fmt_cnt]; - fmt_cnt++; - } - - /* Maximumly we can have MAX_SEQ_PRINTF_VARARGS parameter, just give - * all of them to seq_printf(). - */ - seq_printf(m, fmt, params[0], params[1], params[2], params[3], - params[4], params[5], params[6], params[7], params[8], - params[9], params[10], params[11]); - - err = seq_has_overflowed(m) ? -EOVERFLOW : 0; -out: - this_cpu_dec(bpf_seq_printf_buf_used); - return err; -} - -BTF_ID_LIST_SINGLE(btf_seq_file_ids, struct, seq_file) - -static const struct bpf_func_proto bpf_seq_printf_proto = { - .func = bpf_seq_printf, - .gpl_only = true, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_BTF_ID, - .arg1_btf_id = &btf_seq_file_ids[0], - .arg2_type = ARG_PTR_TO_MEM, - .arg3_type = ARG_CONST_SIZE, - .arg4_type = ARG_PTR_TO_MEM_OR_NULL, - .arg5_type = ARG_CONST_SIZE_OR_ZERO, -}; - -BPF_CALL_3(bpf_seq_write, struct seq_file *, m, const void *, data, u32, len) -{ - return seq_write(m, data, len) ? -EOVERFLOW : 0; -} - -static const struct bpf_func_proto bpf_seq_write_proto = { - .func = bpf_seq_write, - .gpl_only = true, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_BTF_ID, - .arg1_btf_id = &btf_seq_file_ids[0], - .arg2_type = ARG_PTR_TO_MEM, - .arg3_type = ARG_CONST_SIZE_OR_ZERO, -}; - -BPF_CALL_4(bpf_seq_printf_btf, struct seq_file *, m, struct btf_ptr *, ptr, - u32, btf_ptr_size, u64, flags) -{ - const struct btf *btf; - s32 btf_id; - int ret; - - ret = bpf_btf_printf_prepare(ptr, btf_ptr_size, flags, &btf, &btf_id); - if (ret) - return ret; - - return btf_type_seq_show_flags(btf, btf_id, ptr->ptr, m, flags); -} - -static const struct bpf_func_proto bpf_seq_printf_btf_proto = { - .func = bpf_seq_printf_btf, - .gpl_only = true, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_BTF_ID, - .arg1_btf_id = &btf_seq_file_ids[0], - .arg2_type = ARG_PTR_TO_MEM, - .arg3_type = ARG_CONST_SIZE_OR_ZERO, - .arg4_type = ARG_ANYTHING, -}; - static __always_inline int get_map_perf_counter(struct bpf_map *map, u64 flags, u64 *value, u64 *enabled, u64 *running) @@ -982,6 +513,7 @@ static DEFINE_PER_CPU(struct bpf_trace_sample_data, bpf_misc_sds); u64 bpf_event_output(struct bpf_map *map, u64 flags, void *meta, u64 meta_size, void *ctx, u64 ctx_size, bpf_ctx_copy_t ctx_copy) { + int nest_level = this_cpu_inc_return(bpf_event_output_nest_level); struct perf_raw_frag frag = { .copy = ctx_copy, .size = ctx_size, @@ -998,12 +530,8 @@ u64 bpf_event_output(struct bpf_map *map, u64 flags, void *meta, u64 meta_size, }; struct perf_sample_data *sd; struct pt_regs *regs; - int nest_level; u64 ret; - preempt_disable(); - nest_level = this_cpu_inc_return(bpf_event_output_nest_level); - if (WARN_ON_ONCE(nest_level > ARRAY_SIZE(bpf_misc_sds.sds))) { ret = -EBUSY; goto out; @@ -1018,7 +546,6 @@ u64 bpf_event_output(struct bpf_map *map, u64 flags, void *meta, u64 meta_size, ret = __bpf_perf_event_output(regs, map, flags, sd); out: this_cpu_dec(bpf_event_output_nest_level); - preempt_enable(); return ret; } @@ -1027,7 +554,7 @@ BPF_CALL_0(bpf_get_current_task) return (long) current; } -const struct bpf_func_proto bpf_get_current_task_proto = { +static const struct bpf_func_proto bpf_get_current_task_proto = { .func = bpf_get_current_task, .gpl_only = true, .ret_type = RET_INTEGER, @@ -1056,11 +583,45 @@ static const struct bpf_func_proto bpf_current_task_under_cgroup_proto = { .arg2_type = ARG_ANYTHING, }; +BPF_CALL_3(bpf_probe_read_str, void *, dst, u32, size, + const void *, unsafe_ptr) +{ + int ret; + + ret = security_locked_down(LOCKDOWN_BPF_READ); + if (ret < 0) + goto out; + + /* + * The strncpy_from_unsafe() call will likely not fill the entire + * buffer, but that's okay in this circumstance as we're probing + * arbitrary memory anyway similar to bpf_probe_read() and might + * as well probe the stack. Thus, memory is explicitly cleared + * only in error case, so that improper users ignoring return + * code altogether don't copy garbage; otherwise length of string + * is returned that can be used for bpf_perf_event_output() et al. + */ + ret = strncpy_from_unsafe(dst, unsafe_ptr, size); + if (unlikely(ret < 0)) +out: + memset(dst, 0, size); + + return ret; +} + +static const struct bpf_func_proto bpf_probe_read_str_proto = { + .func = bpf_probe_read_str, + .gpl_only = true, + .ret_type = RET_INTEGER, + .arg1_type = ARG_PTR_TO_UNINIT_MEM, + .arg2_type = ARG_CONST_SIZE_OR_ZERO, + .arg3_type = ARG_ANYTHING, +}; + struct send_signal_irq_work { struct irq_work irq_work; struct task_struct *task; u32 sig; - enum pid_type type; }; static DEFINE_PER_CPU(struct send_signal_irq_work, send_signal_work); @@ -1070,11 +631,10 @@ static void do_bpf_send_signal(struct irq_work *entry) struct send_signal_irq_work *work; work = container_of(entry, struct send_signal_irq_work, irq_work); - group_send_sig_info(work->sig, SEND_SIG_PRIV, work->task, work->type); - put_task_struct(work->task); + group_send_sig_info(work->sig, SEND_SIG_PRIV, work->task, PIDTYPE_TGID); } -static int bpf_send_signal_common(u32 sig, enum pid_type type) +BPF_CALL_1(bpf_send_signal, u32, sig) { struct send_signal_irq_work *work = NULL; @@ -1101,26 +661,20 @@ static int bpf_send_signal_common(u32 sig, enum pid_type type) return -EINVAL; work = this_cpu_ptr(&send_signal_work); - if (atomic_read(&work->irq_work.flags) & IRQ_WORK_BUSY) + if (work->irq_work.flags & IRQ_WORK_BUSY) return -EBUSY; /* Add the current task, which is the target of sending signal, * to the irq_work. The current task may change when queued * irq works get executed. */ - work->task = get_task_struct(current); + work->task = current; work->sig = sig; - work->type = type; irq_work_queue(&work->irq_work); return 0; } - return group_send_sig_info(sig, SEND_SIG_PRIV, current, type); -} - -BPF_CALL_1(bpf_send_signal, u32, sig) -{ - return bpf_send_signal_common(sig, PIDTYPE_TGID); + return group_send_sig_info(sig, SEND_SIG_PRIV, current, PIDTYPE_TGID); } static const struct bpf_func_proto bpf_send_signal_proto = { @@ -1130,142 +684,8 @@ static const struct bpf_func_proto bpf_send_signal_proto = { .arg1_type = ARG_ANYTHING, }; -BPF_CALL_1(bpf_send_signal_thread, u32, sig) -{ - return bpf_send_signal_common(sig, PIDTYPE_PID); -} - -static const struct bpf_func_proto bpf_send_signal_thread_proto = { - .func = bpf_send_signal_thread, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_ANYTHING, -}; - -BPF_CALL_3(bpf_d_path, struct path *, path, char *, buf, u32, sz) -{ - struct path copy; - long len; - char *p; - - if (!sz) - return 0; - - /* - * The path pointer is verified as trusted and safe to use, - * but let's double check it's valid anyway to workaround - * potentially broken verifier. - */ - len = copy_from_kernel_nofault(©, path, sizeof(*path)); - if (len < 0) - return len; - - p = d_path(©, buf, sz); - if (IS_ERR(p)) { - len = PTR_ERR(p); - } else { - len = buf + sz - p; - memmove(buf, p, len); - } - - return len; -} - -BTF_SET_START(btf_allowlist_d_path) -#ifdef CONFIG_SECURITY -BTF_ID(func, security_file_permission) -BTF_ID(func, security_inode_getattr) -BTF_ID(func, security_file_open) -#endif -#ifdef CONFIG_SECURITY_PATH -BTF_ID(func, security_path_truncate) -#endif -BTF_ID(func, vfs_truncate) -BTF_ID(func, vfs_fallocate) -BTF_ID(func, dentry_open) -BTF_ID(func, vfs_getattr) -BTF_ID(func, filp_close) -BTF_SET_END(btf_allowlist_d_path) - -static bool bpf_d_path_allowed(const struct bpf_prog *prog) -{ - return btf_id_set_contains(&btf_allowlist_d_path, prog->aux->attach_btf_id); -} - -BTF_ID_LIST_SINGLE(bpf_d_path_btf_ids, struct, path) - -static const struct bpf_func_proto bpf_d_path_proto = { - .func = bpf_d_path, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_BTF_ID, - .arg1_btf_id = &bpf_d_path_btf_ids[0], - .arg2_type = ARG_PTR_TO_MEM, - .arg3_type = ARG_CONST_SIZE_OR_ZERO, - .allowed = bpf_d_path_allowed, -}; - -#define BTF_F_ALL (BTF_F_COMPACT | BTF_F_NONAME | \ - BTF_F_PTR_RAW | BTF_F_ZERO) - -static int bpf_btf_printf_prepare(struct btf_ptr *ptr, u32 btf_ptr_size, - u64 flags, const struct btf **btf, - s32 *btf_id) -{ - const struct btf_type *t; - - if (unlikely(flags & ~(BTF_F_ALL))) - return -EINVAL; - - if (btf_ptr_size != sizeof(struct btf_ptr)) - return -EINVAL; - - *btf = bpf_get_btf_vmlinux(); - - if (IS_ERR_OR_NULL(*btf)) - return IS_ERR(*btf) ? PTR_ERR(*btf) : -EINVAL; - - if (ptr->type_id > 0) - *btf_id = ptr->type_id; - else - return -EINVAL; - - if (*btf_id > 0) - t = btf_type_by_id(*btf, *btf_id); - if (*btf_id <= 0 || !t) - return -ENOENT; - - return 0; -} - -BPF_CALL_5(bpf_snprintf_btf, char *, str, u32, str_size, struct btf_ptr *, ptr, - u32, btf_ptr_size, u64, flags) -{ - const struct btf *btf; - s32 btf_id; - int ret; - - ret = bpf_btf_printf_prepare(ptr, btf_ptr_size, flags, &btf, &btf_id); - if (ret) - return ret; - - return btf_type_snprintf_show(btf, btf_id, ptr->ptr, str, str_size, - flags); -} - -const struct bpf_func_proto bpf_snprintf_btf_proto = { - .func = bpf_snprintf_btf, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_MEM, - .arg2_type = ARG_CONST_SIZE, - .arg3_type = ARG_PTR_TO_MEM, - .arg4_type = ARG_CONST_SIZE, - .arg5_type = ARG_ANYTHING, -}; - -const struct bpf_func_proto * -bpf_tracing_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) +static const struct bpf_func_proto * +tracing_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { case BPF_FUNC_map_lookup_elem: @@ -1280,6 +700,8 @@ bpf_tracing_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return &bpf_map_pop_elem_proto; case BPF_FUNC_map_peek_elem: return &bpf_map_peek_elem_proto; + case BPF_FUNC_probe_read: + return &bpf_probe_read_proto; case BPF_FUNC_ktime_get_ns: return &bpf_ktime_get_ns_proto; case BPF_FUNC_ktime_get_boot_ns: @@ -1302,61 +724,20 @@ bpf_tracing_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return &bpf_get_numa_node_id_proto; case BPF_FUNC_perf_event_read: return &bpf_perf_event_read_proto; + case BPF_FUNC_probe_write_user: + return bpf_get_probe_write_proto(); case BPF_FUNC_current_task_under_cgroup: return &bpf_current_task_under_cgroup_proto; case BPF_FUNC_get_prandom_u32: return &bpf_get_prandom_u32_proto; - case BPF_FUNC_probe_write_user: - return security_locked_down(LOCKDOWN_BPF_WRITE_USER) < 0 ? - NULL : bpf_get_probe_write_proto(); - case BPF_FUNC_probe_read_user: - return &bpf_probe_read_user_proto; - case BPF_FUNC_probe_read_kernel: - return &bpf_probe_read_kernel_proto; - case BPF_FUNC_probe_read_user_str: - return &bpf_probe_read_user_str_proto; - case BPF_FUNC_probe_read_kernel_str: - return &bpf_probe_read_kernel_str_proto; -#ifdef CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE - case BPF_FUNC_probe_read: - return &bpf_probe_read_compat_proto; case BPF_FUNC_probe_read_str: - return &bpf_probe_read_compat_str_proto; -#endif + return &bpf_probe_read_str_proto; #ifdef CONFIG_CGROUPS case BPF_FUNC_get_current_cgroup_id: return &bpf_get_current_cgroup_id_proto; #endif case BPF_FUNC_send_signal: return &bpf_send_signal_proto; - case BPF_FUNC_send_signal_thread: - return &bpf_send_signal_thread_proto; - case BPF_FUNC_perf_event_read_value: - return &bpf_perf_event_read_value_proto; - case BPF_FUNC_get_ns_current_pid_tgid: - return &bpf_get_ns_current_pid_tgid_proto; - case BPF_FUNC_ringbuf_output: - return &bpf_ringbuf_output_proto; - case BPF_FUNC_ringbuf_reserve: - return &bpf_ringbuf_reserve_proto; - case BPF_FUNC_ringbuf_submit: - return &bpf_ringbuf_submit_proto; - case BPF_FUNC_ringbuf_discard: - return &bpf_ringbuf_discard_proto; - case BPF_FUNC_ringbuf_query: - return &bpf_ringbuf_query_proto; - case BPF_FUNC_jiffies64: - return &bpf_jiffies64_proto; - case BPF_FUNC_get_task_stack: - return &bpf_get_task_stack_proto; - case BPF_FUNC_copy_from_user: - return prog->aux->sleepable ? &bpf_copy_from_user_proto : NULL; - case BPF_FUNC_snprintf_btf: - return &bpf_snprintf_btf_proto; - case BPF_FUNC_per_cpu_ptr: - return &bpf_per_cpu_ptr_proto; - case BPF_FUNC_this_cpu_ptr: - return &bpf_this_cpu_ptr_proto; default: return NULL; } @@ -1372,12 +753,14 @@ kprobe_prog_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return &bpf_get_stackid_proto; case BPF_FUNC_get_stack: return &bpf_get_stack_proto; + case BPF_FUNC_perf_event_read_value: + return &bpf_perf_event_read_value_proto; #ifdef CONFIG_BPF_KPROBE_OVERRIDE case BPF_FUNC_override_return: return &bpf_override_return_proto; #endif default: - return bpf_tracing_func_proto(func_id, prog); + return tracing_func_proto(func_id, prog); } } @@ -1487,7 +870,7 @@ tp_prog_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) case BPF_FUNC_get_stack: return &bpf_get_stack_proto_tp; default: - return bpf_tracing_func_proto(func_id, prog); + return tracing_func_proto(func_id, prog); } } @@ -1540,41 +923,6 @@ static const struct bpf_func_proto bpf_perf_prog_read_value_proto = { .arg3_type = ARG_CONST_SIZE, }; -BPF_CALL_4(bpf_read_branch_records, struct bpf_perf_event_data_kern *, ctx, - void *, buf, u32, size, u64, flags) -{ - static const u32 br_entry_size = sizeof(struct perf_branch_entry); - struct perf_branch_stack *br_stack = ctx->data->br_stack; - u32 to_copy; - - if (unlikely(flags & ~BPF_F_GET_BRANCH_RECORDS_SIZE)) - return -EINVAL; - - if (unlikely(!br_stack)) - return -ENOENT; - - if (flags & BPF_F_GET_BRANCH_RECORDS_SIZE) - return br_stack->nr * br_entry_size; - - if (!buf || (size % br_entry_size != 0)) - return -EINVAL; - - to_copy = min_t(u32, br_stack->nr * br_entry_size, size); - memcpy(buf, br_stack->entries, to_copy); - - return to_copy; -} - -static const struct bpf_func_proto bpf_read_branch_records_proto = { - .func = bpf_read_branch_records, - .gpl_only = true, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX, - .arg2_type = ARG_PTR_TO_MEM_OR_NULL, - .arg3_type = ARG_CONST_SIZE_OR_ZERO, - .arg4_type = ARG_ANYTHING, -}; - static const struct bpf_func_proto * pe_prog_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { @@ -1582,15 +930,13 @@ pe_prog_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) case BPF_FUNC_perf_event_output: return &bpf_perf_event_output_proto_tp; case BPF_FUNC_get_stackid: - return &bpf_get_stackid_proto_pe; + return &bpf_get_stackid_proto_tp; case BPF_FUNC_get_stack: - return &bpf_get_stack_proto_pe; + return &bpf_get_stack_proto_tp; case BPF_FUNC_perf_prog_read_value: return &bpf_perf_prog_read_value_proto; - case BPF_FUNC_read_branch_records: - return &bpf_read_branch_records_proto; default: - return bpf_tracing_func_proto(func_id, prog); + return tracing_func_proto(func_id, prog); } } @@ -1652,9 +998,6 @@ static const struct bpf_func_proto bpf_perf_event_output_proto_raw_tp = { .arg5_type = ARG_CONST_SIZE_OR_ZERO, }; -extern const struct bpf_func_proto bpf_skb_output_proto; -extern const struct bpf_func_proto bpf_xdp_output_proto; - BPF_CALL_3(bpf_get_stackid_raw_tp, struct bpf_raw_tracepoint_args *, args, struct bpf_map *, map, u64, flags) { @@ -1718,46 +1061,7 @@ raw_tp_prog_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) case BPF_FUNC_get_stack: return &bpf_get_stack_proto_raw_tp; default: - return bpf_tracing_func_proto(func_id, prog); - } -} - -const struct bpf_func_proto * -tracing_prog_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) -{ - switch (func_id) { -#ifdef CONFIG_NET - case BPF_FUNC_skb_output: - return &bpf_skb_output_proto; - case BPF_FUNC_xdp_output: - return &bpf_xdp_output_proto; - case BPF_FUNC_skc_to_tcp6_sock: - return &bpf_skc_to_tcp6_sock_proto; - case BPF_FUNC_skc_to_tcp_sock: - return &bpf_skc_to_tcp_sock_proto; - case BPF_FUNC_skc_to_tcp_timewait_sock: - return &bpf_skc_to_tcp_timewait_sock_proto; - case BPF_FUNC_skc_to_tcp_request_sock: - return &bpf_skc_to_tcp_request_sock_proto; - case BPF_FUNC_skc_to_udp6_sock: - return &bpf_skc_to_udp6_sock_proto; -#endif - case BPF_FUNC_seq_printf: - return prog->expected_attach_type == BPF_TRACE_ITER ? - &bpf_seq_printf_proto : - NULL; - case BPF_FUNC_seq_write: - return prog->expected_attach_type == BPF_TRACE_ITER ? - &bpf_seq_write_proto : - NULL; - case BPF_FUNC_seq_printf_btf: - return prog->expected_attach_type == BPF_TRACE_ITER ? - &bpf_seq_printf_btf_proto : - NULL; - case BPF_FUNC_d_path: - return &bpf_d_path_proto; - default: - return raw_tp_prog_func_proto(func_id, prog); + return tracing_func_proto(func_id, prog); } } @@ -1766,7 +1070,8 @@ static bool raw_tp_prog_is_valid_access(int off, int size, const struct bpf_prog *prog, struct bpf_insn_access_aux *info) { - if (off < 0 || off >= sizeof(__u64) * MAX_BPF_FUNC_ARGS) + /* largest tracepoint in the kernel has 12 args */ + if (off < 0 || off >= sizeof(__u64) * 12) return false; if (type != BPF_READ) return false; @@ -1775,45 +1080,12 @@ static bool raw_tp_prog_is_valid_access(int off, int size, return true; } -static bool tracing_prog_is_valid_access(int off, int size, - enum bpf_access_type type, - const struct bpf_prog *prog, - struct bpf_insn_access_aux *info) -{ - if (off < 0 || off >= sizeof(__u64) * MAX_BPF_FUNC_ARGS) - return false; - if (type != BPF_READ) - return false; - if (off % size != 0) - return false; - return btf_ctx_access(off, size, type, prog, info); -} - -int __weak bpf_prog_test_run_tracing(struct bpf_prog *prog, - const union bpf_attr *kattr, - union bpf_attr __user *uattr) -{ - return -ENOTSUPP; -} - const struct bpf_verifier_ops raw_tracepoint_verifier_ops = { .get_func_proto = raw_tp_prog_func_proto, .is_valid_access = raw_tp_prog_is_valid_access, }; const struct bpf_prog_ops raw_tracepoint_prog_ops = { -#ifdef CONFIG_NET - .test_run = bpf_prog_test_run_raw_tp, -#endif -}; - -const struct bpf_verifier_ops tracing_verifier_ops = { - .get_func_proto = tracing_prog_func_proto, - .is_valid_access = tracing_prog_is_valid_access, -}; - -const struct bpf_prog_ops tracing_prog_ops = { - .test_run = bpf_prog_test_run_tracing, }; static bool raw_tp_writable_prog_is_valid_access(int off, int size, @@ -2003,7 +1275,7 @@ int perf_event_query_prog_array(struct perf_event *event, void __user *info) u32 *ids, prog_cnt, ids_len; int ret; - if (!perfmon_capable()) + if (!capable(CAP_SYS_ADMIN)) return -EPERM; if (event->attr.type != PERF_TYPE_TRACEPOINT) return -EINVAL; @@ -2064,9 +1336,10 @@ void bpf_put_raw_tracepoint(struct bpf_raw_event_map *btp) static __always_inline void __bpf_trace_run(struct bpf_prog *prog, u64 *args) { - cant_sleep(); rcu_read_lock(); + preempt_disable(); (void) BPF_PROG_RUN(prog, args); + preempt_enable(); rcu_read_unlock(); } @@ -2210,11 +1483,10 @@ static int bpf_event_notify(struct notifier_block *nb, unsigned long op, { struct bpf_trace_module *btm, *tmp; struct module *mod = module; - int ret = 0; if (mod->num_bpf_raw_events == 0 || (op != MODULE_STATE_COMING && op != MODULE_STATE_GOING)) - goto out; + return 0; mutex_lock(&bpf_module_mutex); @@ -2224,8 +1496,6 @@ static int bpf_event_notify(struct notifier_block *nb, unsigned long op, if (btm) { btm->module = module; list_add(&btm->list, &bpf_trace_modules); - } else { - ret = -ENOMEM; } break; case MODULE_STATE_GOING: @@ -2241,8 +1511,7 @@ static int bpf_event_notify(struct notifier_block *nb, unsigned long op, mutex_unlock(&bpf_module_mutex); -out: - return notifier_from_errno(ret); + return 0; } static struct notifier_block bpf_module_nb = { diff --git a/kernel/trace/bpf_trace.h b/kernel/trace/bpf_trace.h deleted file mode 100644 index 9acbc11ac7bb..000000000000 --- a/kernel/trace/bpf_trace.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#undef TRACE_SYSTEM -#define TRACE_SYSTEM bpf_trace - -#if !defined(_TRACE_BPF_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) - -#define _TRACE_BPF_TRACE_H - -#include - -TRACE_EVENT(bpf_trace_printk, - - TP_PROTO(const char *bpf_string), - - TP_ARGS(bpf_string), - - TP_STRUCT__entry( - __string(bpf_string, bpf_string) - ), - - TP_fast_assign( - __assign_str(bpf_string, bpf_string); - ), - - TP_printk("%s", __get_str(bpf_string)) -); - -#endif /* _TRACE_BPF_TRACE_H */ - -#undef TRACE_INCLUDE_PATH -#define TRACE_INCLUDE_PATH . -#define TRACE_INCLUDE_FILE bpf_trace - -#include diff --git a/kernel/trace/error_report-traces.c b/kernel/trace/error_report-traces.c deleted file mode 100644 index 632c8c7ff079..000000000000 --- a/kernel/trace/error_report-traces.c +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Error reporting trace points. - * - * Copyright (C) 2021, Google LLC. - */ - -#define CREATE_TRACE_POINTS -#include - -EXPORT_TRACEPOINT_SYMBOL_GPL(error_report_end); - diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c index bc95bddfa77d..8cfbf9f01aa5 100644 --- a/kernel/trace/ftrace.c +++ b/kernel/trace/ftrace.c @@ -326,8 +326,6 @@ int __register_ftrace_function(struct ftrace_ops *ops) if (ops->flags & FTRACE_OPS_FL_SAVE_REGS_IF_SUPPORTED) ops->flags |= FTRACE_OPS_FL_SAVE_REGS; #endif - if (!ftrace_enabled && (ops->flags & FTRACE_OPS_FL_PERMANENT)) - return -EBUSY; if (!core_kernel_data((unsigned long)ops)) ops->flags |= FTRACE_OPS_FL_DYNAMIC; @@ -1020,7 +1018,6 @@ static bool update_all_ops; struct ftrace_func_entry { struct hlist_node hlist; unsigned long ip; - unsigned long direct; /* for direct lookup only */ }; struct ftrace_func_probe { @@ -1724,9 +1721,6 @@ static bool __ftrace_hash_rec_update(struct ftrace_ops *ops, if (FTRACE_WARN_ON(ftrace_rec_count(rec) == FTRACE_REF_MAX)) return false; - if (ops->flags & FTRACE_OPS_FL_DIRECT) - rec->flags |= FTRACE_FL_DIRECT; - /* * If there's only a single callback registered to a * function, and the ops has a trampoline registered @@ -1754,15 +1748,6 @@ static bool __ftrace_hash_rec_update(struct ftrace_ops *ops, return false; rec->flags--; - /* - * Only the internal direct_ops should have the - * DIRECT flag set. Thus, if it is removing a - * function, then that function should no longer - * be direct. - */ - if (ops->flags & FTRACE_OPS_FL_DIRECT) - rec->flags &= ~FTRACE_FL_DIRECT; - /* * If the rec had REGS enabled and the ops that is * being removed had REGS set, then see if there is @@ -1975,7 +1960,7 @@ static void print_ip_ins(const char *fmt, const unsigned char *p) char ins[MCOUNT_INSN_SIZE]; int i; - if (copy_from_kernel_nofault(ins, p, MCOUNT_INSN_SIZE)) { + if (probe_kernel_read(ins, p, MCOUNT_INSN_SIZE)) { printk(KERN_CONT "%s[FAULT] %px\n", fmt, p); return; } @@ -2104,34 +2089,15 @@ static int ftrace_check_record(struct dyn_ftrace *rec, bool enable, bool update) * If enabling and the REGS flag does not match the REGS_EN, or * the TRAMP flag doesn't match the TRAMP_EN, then do not ignore * this record. Set flags to fail the compare against ENABLED. - * Same for direct calls. */ if (flag) { - if (!(rec->flags & FTRACE_FL_REGS) != + if (!(rec->flags & FTRACE_FL_REGS) != !(rec->flags & FTRACE_FL_REGS_EN)) flag |= FTRACE_FL_REGS; - if (!(rec->flags & FTRACE_FL_TRAMP) != + if (!(rec->flags & FTRACE_FL_TRAMP) != !(rec->flags & FTRACE_FL_TRAMP_EN)) flag |= FTRACE_FL_TRAMP; - - /* - * Direct calls are special, as count matters. - * We must test the record for direct, if the - * DIRECT and DIRECT_EN do not match, but only - * if the count is 1. That's because, if the - * count is something other than one, we do not - * want the direct enabled (it will be done via the - * direct helper). But if DIRECT_EN is set, and - * the count is not one, we need to clear it. - */ - if (ftrace_rec_count(rec) == 1) { - if (!(rec->flags & FTRACE_FL_DIRECT) != - !(rec->flags & FTRACE_FL_DIRECT_EN)) - flag |= FTRACE_FL_DIRECT; - } else if (rec->flags & FTRACE_FL_DIRECT_EN) { - flag |= FTRACE_FL_DIRECT; - } } /* If the state of this record hasn't changed, then do nothing */ @@ -2156,25 +2122,6 @@ static int ftrace_check_record(struct dyn_ftrace *rec, bool enable, bool update) else rec->flags &= ~FTRACE_FL_TRAMP_EN; } - if (flag & FTRACE_FL_DIRECT) { - /* - * If there's only one user (direct_ops helper) - * then we can call the direct function - * directly (no ftrace trampoline). - */ - if (ftrace_rec_count(rec) == 1) { - if (rec->flags & FTRACE_FL_DIRECT) - rec->flags |= FTRACE_FL_DIRECT_EN; - else - rec->flags &= ~FTRACE_FL_DIRECT_EN; - } else { - /* - * Can only call directly if there's - * only one callback to the function. - */ - rec->flags &= ~FTRACE_FL_DIRECT_EN; - } - } } /* @@ -2204,7 +2151,7 @@ static int ftrace_check_record(struct dyn_ftrace *rec, bool enable, bool update) * and REGS states. The _EN flags must be disabled though. */ rec->flags &= ~(FTRACE_FL_ENABLED | FTRACE_FL_TRAMP_EN | - FTRACE_FL_REGS_EN | FTRACE_FL_DIRECT_EN); + FTRACE_FL_REGS_EN); } ftrace_bug_type = FTRACE_BUG_NOP; @@ -2377,51 +2324,6 @@ ftrace_find_tramp_ops_new(struct dyn_ftrace *rec) return NULL; } -#ifdef CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS -/* Protected by rcu_tasks for reading, and direct_mutex for writing */ -static struct ftrace_hash *direct_functions = EMPTY_HASH; -static DEFINE_MUTEX(direct_mutex); - -/* - * Search the direct_functions hash to see if the given instruction pointer - * has a direct caller attached to it. - */ -static unsigned long find_rec_direct(unsigned long ip) -{ - struct ftrace_func_entry *entry; - - entry = __ftrace_lookup_ip(direct_functions, ip); - if (!entry) - return 0; - - return entry->direct; -} - -static void call_direct_funcs(unsigned long ip, unsigned long pip, - struct ftrace_ops *ops, struct pt_regs *regs) -{ - unsigned long addr; - - addr = find_rec_direct(ip); - if (!addr) - return; - - arch_ftrace_set_direct_caller(regs, addr); -} - -struct ftrace_ops direct_ops = { - .func = call_direct_funcs, - .flags = FTRACE_OPS_FL_IPMODIFY | FTRACE_OPS_FL_RECURSION_SAFE - | FTRACE_OPS_FL_DIRECT | FTRACE_OPS_FL_SAVE_REGS - | FTRACE_OPS_FL_PERMANENT, -}; -#else -static inline unsigned long find_rec_direct(unsigned long ip) -{ - return 0; -} -#endif /* CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS */ - /** * ftrace_get_addr_new - Get the call address to set to * @rec: The ftrace record descriptor @@ -2435,15 +2337,6 @@ static inline unsigned long find_rec_direct(unsigned long ip) unsigned long ftrace_get_addr_new(struct dyn_ftrace *rec) { struct ftrace_ops *ops; - unsigned long addr; - - if ((rec->flags & FTRACE_FL_DIRECT) && - (ftrace_rec_count(rec) == 1)) { - addr = find_rec_direct(rec->ip); - if (addr) - return addr; - WARN_ON_ONCE(1); - } /* Trampolines take precedence over regs */ if (rec->flags & FTRACE_FL_TRAMP) { @@ -2476,15 +2369,6 @@ unsigned long ftrace_get_addr_new(struct dyn_ftrace *rec) unsigned long ftrace_get_addr_curr(struct dyn_ftrace *rec) { struct ftrace_ops *ops; - unsigned long addr; - - /* Direct calls take precedence over trampolines */ - if (rec->flags & FTRACE_FL_DIRECT_EN) { - addr = find_rec_direct(rec->ip); - if (addr) - return addr; - WARN_ON_ONCE(1); - } /* Trampolines take precedence over regs */ if (rec->flags & FTRACE_FL_TRAMP_EN) { @@ -3619,11 +3503,10 @@ static int t_show(struct seq_file *m, void *v) if (iter->flags & FTRACE_ITER_ENABLED) { struct ftrace_ops *ops; - seq_printf(m, " (%ld)%s%s%s", + seq_printf(m, " (%ld)%s%s", ftrace_rec_count(rec), rec->flags & FTRACE_FL_REGS ? " R" : " ", - rec->flags & FTRACE_FL_IPMODIFY ? " I" : " ", - rec->flags & FTRACE_FL_DIRECT ? " D" : " "); + rec->flags & FTRACE_FL_IPMODIFY ? " I" : " "); if (rec->flags & FTRACE_FL_TRAMP_EN) { ops = ftrace_find_tramp_ops_any(rec); if (ops) { @@ -3639,13 +3522,6 @@ static int t_show(struct seq_file *m, void *v) } else { add_trampoline_func(m, NULL, rec); } - if (rec->flags & FTRACE_FL_DIRECT) { - unsigned long direct; - - direct = find_rec_direct(rec->ip); - if (direct) - seq_printf(m, "\n\tdirect-->%pS", (void *)direct); - } } seq_putc(m, '\n'); @@ -4984,221 +4860,6 @@ ftrace_set_addr(struct ftrace_ops *ops, unsigned long ip, int remove, return ftrace_set_hash(ops, NULL, 0, ip, remove, reset, enable); } -#ifdef CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS -/** - * register_ftrace_direct - Call a custom trampoline directly - * @ip: The address of the nop at the beginning of a function - * @addr: The address of the trampoline to call at @ip - * - * This is used to connect a direct call from the nop location (@ip) - * at the start of ftrace traced functions. The location that it calls - * (@addr) must be able to handle a direct call, and save the parameters - * of the function being traced, and restore them (or inject new ones - * if needed), before returning. - * - * Returns: - * 0 on success - * -EBUSY - Another direct function is already attached (there can be only one) - * -ENODEV - @ip does not point to a ftrace nop location (or not supported) - * -ENOMEM - There was an allocation failure. - */ -int register_ftrace_direct(unsigned long ip, unsigned long addr) -{ - struct ftrace_func_entry *entry; - struct ftrace_hash *free_hash = NULL; - struct dyn_ftrace *rec; - int ret = -EBUSY; - - mutex_lock(&direct_mutex); - - /* See if there's a direct function at @ip already */ - if (find_rec_direct(ip)) - goto out_unlock; - - ret = -ENODEV; - rec = lookup_rec(ip, ip); - if (!rec) - goto out_unlock; - - /* - * Check if the rec says it has a direct call but we didn't - * find one earlier? - */ - if (WARN_ON(rec->flags & FTRACE_FL_DIRECT)) - goto out_unlock; - - /* Make sure the ip points to the exact record */ - ip = rec->ip; - - ret = -ENOMEM; - if (ftrace_hash_empty(direct_functions) || - direct_functions->count > 2 * (1 << direct_functions->size_bits)) { - struct ftrace_hash *new_hash; - int size = ftrace_hash_empty(direct_functions) ? 0 : - direct_functions->count + 1; - - if (size < 32) - size = 32; - - new_hash = dup_hash(direct_functions, size); - if (!new_hash) - goto out_unlock; - - free_hash = direct_functions; - direct_functions = new_hash; - } - - entry = kmalloc(sizeof(*entry), GFP_KERNEL); - if (!entry) - goto out_unlock; - - entry->ip = ip; - entry->direct = addr; - __add_hash_entry(direct_functions, entry); - - ret = ftrace_set_filter_ip(&direct_ops, ip, 0, 0); - if (ret) - remove_hash_entry(direct_functions, entry); - - if (!ret && !(direct_ops.flags & FTRACE_OPS_FL_ENABLED)) { - ret = register_ftrace_function(&direct_ops); - if (ret) - ftrace_set_filter_ip(&direct_ops, ip, 1, 0); - } - - if (ret) - kfree(entry); - out_unlock: - mutex_unlock(&direct_mutex); - - if (free_hash) { - synchronize_rcu_tasks(); - free_ftrace_hash(free_hash); - } - - return ret; -} -EXPORT_SYMBOL_GPL(register_ftrace_direct); - -int unregister_ftrace_direct(unsigned long ip, unsigned long addr) -{ - struct ftrace_func_entry *entry; - struct dyn_ftrace *rec; - int ret = -ENODEV; - - mutex_lock(&direct_mutex); - - entry = __ftrace_lookup_ip(direct_functions, ip); - if (!entry) { - /* OK if it is off by a little */ - rec = lookup_rec(ip, ip); - if (!rec || rec->ip == ip) - goto out_unlock; - - entry = __ftrace_lookup_ip(direct_functions, rec->ip); - if (!entry) { - WARN_ON(rec->flags & FTRACE_FL_DIRECT); - goto out_unlock; - } - - WARN_ON(!(rec->flags & FTRACE_FL_DIRECT)); - } - - if (direct_functions->count == 1) - unregister_ftrace_function(&direct_ops); - - ret = ftrace_set_filter_ip(&direct_ops, ip, 1, 0); - - WARN_ON(ret); - - remove_hash_entry(direct_functions, entry); - - out_unlock: - mutex_unlock(&direct_mutex); - - return ret; -} -EXPORT_SYMBOL_GPL(unregister_ftrace_direct); - -static struct ftrace_ops stub_ops = { - .func = ftrace_stub, -}; - -/** - * modify_ftrace_direct - Modify an existing direct call to call something else - * @ip: The instruction pointer to modify - * @old_addr: The address that the current @ip calls directly - * @new_addr: The address that the @ip should call - * - * This modifies a ftrace direct caller at an instruction pointer without - * having to disable it first. The direct call will switch over to the - * @new_addr without missing anything. - * - * Returns: zero on success. Non zero on error, which includes: - * -ENODEV : the @ip given has no direct caller attached - * -EINVAL : the @old_addr does not match the current direct caller - */ -int modify_ftrace_direct(unsigned long ip, - unsigned long old_addr, unsigned long new_addr) -{ - struct ftrace_func_entry *entry; - struct dyn_ftrace *rec; - int ret = -ENODEV; - - mutex_lock(&direct_mutex); - entry = __ftrace_lookup_ip(direct_functions, ip); - if (!entry) { - /* OK if it is off by a little */ - rec = lookup_rec(ip, ip); - if (!rec || rec->ip == ip) - goto out_unlock; - - entry = __ftrace_lookup_ip(direct_functions, rec->ip); - if (!entry) - goto out_unlock; - - ip = rec->ip; - WARN_ON(!(rec->flags & FTRACE_FL_DIRECT)); - } - - ret = -EINVAL; - if (entry->direct != old_addr) - goto out_unlock; - - /* - * By setting a stub function at the same address, we force - * the code to call the iterator and the direct_ops helper. - * This means that @ip does not call the direct call, and - * we can simply modify it. - */ - ret = ftrace_set_filter_ip(&stub_ops, ip, 0, 0); - if (ret) - goto out_unlock; - - ret = register_ftrace_function(&stub_ops); - if (ret) { - ftrace_set_filter_ip(&stub_ops, ip, 1, 0); - goto out_unlock; - } - - entry->direct = new_addr; - - /* - * By removing the stub, we put back the direct call, calling - * the @new_addr. - */ - unregister_ftrace_function(&stub_ops); - ftrace_set_filter_ip(&stub_ops, ip, 1, 0); - - ret = 0; - - out_unlock: - mutex_unlock(&direct_mutex); - return ret; -} -EXPORT_SYMBOL_GPL(modify_ftrace_direct); -#endif /* CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS */ - /** * ftrace_set_filter_ip - set a function to filter on in ftrace by address * @ops - the ops to set the filter with @@ -7198,21 +6859,10 @@ int unregister_ftrace_function(struct ftrace_ops *ops) } EXPORT_SYMBOL_GPL(unregister_ftrace_function); -static bool is_permanent_ops_registered(void) -{ - struct ftrace_ops *op; - - do_for_each_ftrace_op(op, ftrace_ops_list) { - if (op->flags & FTRACE_OPS_FL_PERMANENT) - return true; - } while_for_each_ftrace_op(op); - - return false; -} - int ftrace_enable_sysctl(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { int ret = -ENODEV; @@ -7226,6 +6876,8 @@ ftrace_enable_sysctl(struct ctl_table *table, int write, if (ret || !write || (last_ftrace_enabled == !!ftrace_enabled)) goto out; + last_ftrace_enabled = !!ftrace_enabled; + if (ftrace_enabled) { /* we are starting ftrace again */ @@ -7236,19 +6888,12 @@ ftrace_enable_sysctl(struct ctl_table *table, int write, ftrace_startup_sysctl(); } else { - if (is_permanent_ops_registered()) { - ftrace_enabled = true; - ret = -EBUSY; - goto out; - } - /* stopping ftrace calls (just send to ftrace_stub) */ ftrace_trace_function = ftrace_stub; ftrace_shutdown_sysctl(); } - last_ftrace_enabled = !!ftrace_enabled; out: mutex_unlock(&ftrace_lock); return ret; diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c index 74e161f1c88e..0b19596451c2 100644 --- a/kernel/trace/trace.c +++ b/kernel/trace/trace.c @@ -2613,7 +2613,7 @@ static void output_printk(struct trace_event_buffer *fbuffer) } int tracepoint_printk_sysctl(struct ctl_table *table, int write, - void *buffer, size_t *lenp, + void __user *buffer, size_t *lenp, loff_t *ppos) { int save_tracepoint_printk; @@ -8942,7 +8942,7 @@ static int trace_module_notify(struct notifier_block *self, break; } - return NOTIFY_OK; + return 0; } static struct notifier_block trace_module_nb = { diff --git a/kernel/trace/trace_events.c b/kernel/trace/trace_events.c index c353b25f6d32..275c29ed7f1e 100644 --- a/kernel/trace/trace_events.c +++ b/kernel/trace/trace_events.c @@ -2463,7 +2463,7 @@ static int trace_module_notify(struct notifier_block *self, mutex_unlock(&trace_types_lock); mutex_unlock(&event_mutex); - return NOTIFY_OK; + return 0; } static struct notifier_block trace_module_nb = { diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c index 8db7c46e0971..36c1593624be 100644 --- a/kernel/trace/trace_events_hist.c +++ b/kernel/trace/trace_events_hist.c @@ -3646,16 +3646,14 @@ static struct field_var *create_field_var(struct hist_trigger_data *hist_data, var = create_var(hist_data, file, field_name, val->size, val->type); if (IS_ERR(var)) { hist_err(tr, HIST_ERR_VAR_CREATE_FIND_FAIL, errpos(field_name)); - destroy_hist_field(val, 0); + kfree(val); ret = PTR_ERR(var); goto err; } field_var = kzalloc(sizeof(struct field_var), GFP_KERNEL); if (!field_var) { - destroy_hist_field(val, 0); - kfree_const(var->type); - kfree(var->var.name); + kfree(val); kfree(var); ret = -ENOMEM; goto err; diff --git a/kernel/trace/trace_kprobe.c b/kernel/trace/trace_kprobe.c index b553b499206d..56d22752a52e 100644 --- a/kernel/trace/trace_kprobe.c +++ b/kernel/trace/trace_kprobe.c @@ -1100,6 +1100,21 @@ static const struct file_operations kprobe_profile_ops = { /* Kprobe specific fetch functions */ +/* Return the length of string -- including null terminal byte */ +static nokprobe_inline int +fetch_store_strlen(unsigned long addr) +{ + int ret, len = 0; + u8 c; + + do { + ret = probe_kernel_read(&c, (u8 *)addr + len, 1); + len++; + } while (c && ret == 0 && len < MAX_STRING_SIZE); + + return (ret < 0) ? ret : len; +} + /* Return the length of string -- including null terminal byte */ static nokprobe_inline int fetch_store_strlen_user(unsigned long addr) @@ -1109,24 +1124,31 @@ fetch_store_strlen_user(unsigned long addr) return strnlen_unsafe_user(uaddr, MAX_STRING_SIZE); } -/* Return the length of string -- including null terminal byte */ +/* + * Fetch a null-terminated string. Caller MUST set *(u32 *)buf with max + * length and relative data location. + */ static nokprobe_inline int -fetch_store_strlen(unsigned long addr) +fetch_store_string(unsigned long addr, void *dest, void *base) { - int ret, len = 0; - u8 c; + int maxlen = get_loc_len(*(u32 *)dest); + void *__dest; + long ret; -#ifdef CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE - if (addr < TASK_SIZE) - return fetch_store_strlen_user(addr); -#endif + if (unlikely(!maxlen)) + return -ENOMEM; - do { - ret = copy_from_kernel_nofault(&c, (u8 *)addr + len, 1); - len++; - } while (c && ret == 0 && len < MAX_STRING_SIZE); + __dest = get_loc_data(dest, base); - return (ret < 0) ? ret : len; + /* + * Try to get string again, since the string can be changed while + * probing. + */ + ret = strncpy_from_unsafe(__dest, (void *)addr, maxlen); + if (ret >= 0) + *(u32 *)dest = make_data_loc(ret, __dest - base); + + return ret; } /* @@ -1146,43 +1168,17 @@ fetch_store_string_user(unsigned long addr, void *dest, void *base) __dest = get_loc_data(dest, base); - ret = strncpy_from_user_nofault(__dest, uaddr, maxlen); + ret = strncpy_from_unsafe_user(__dest, uaddr, maxlen); if (ret >= 0) *(u32 *)dest = make_data_loc(ret, __dest - base); return ret; } -/* - * Fetch a null-terminated string. Caller MUST set *(u32 *)buf with max - * length and relative data location. - */ static nokprobe_inline int -fetch_store_string(unsigned long addr, void *dest, void *base) +probe_mem_read(void *dest, void *src, size_t size) { - int maxlen = get_loc_len(*(u32 *)dest); - void *__dest; - long ret; - -#ifdef CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE - if ((unsigned long)addr < TASK_SIZE) - return fetch_store_string_user(addr, dest, base); -#endif - - if (unlikely(!maxlen)) - return -ENOMEM; - - __dest = get_loc_data(dest, base); - - /* - * Try to get string again, since the string can be changed while - * probing. - */ - ret = strncpy_from_kernel_nofault(__dest, (void *)addr, maxlen); - if (ret >= 0) - *(u32 *)dest = make_data_loc(ret, __dest - base); - - return ret; + return probe_kernel_read(dest, src, size); } static nokprobe_inline int @@ -1190,17 +1186,7 @@ probe_mem_read_user(void *dest, void *src, size_t size) { const void __user *uaddr = (__force const void __user *)src; - return copy_from_user_nofault(dest, uaddr, size); -} - -static nokprobe_inline int -probe_mem_read(void *dest, void *src, size_t size) -{ -#ifdef CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE - if ((unsigned long)src < TASK_SIZE) - return probe_mem_read_user(dest, src, size); -#endif - return copy_from_kernel_nofault(dest, src, size); + return probe_user_read(dest, uaddr, size); } /* Note that we don't verify it, since the code does not come from user space */ @@ -1599,15 +1585,14 @@ static int kprobe_register(struct trace_event_call *event, static int kprobe_dispatcher(struct kprobe *kp, struct pt_regs *regs) { struct trace_kprobe *tk = container_of(kp, struct trace_kprobe, rp.kp); - unsigned int flags = trace_probe_load_flag(&tk->tp); int ret = 0; raw_cpu_inc(*tk->nhit); - if (flags & TP_FLAG_TRACE) + if (trace_probe_test_flag(&tk->tp, TP_FLAG_TRACE)) kprobe_trace_func(tk, regs); #ifdef CONFIG_PERF_EVENTS - if (flags & TP_FLAG_PROFILE) + if (trace_probe_test_flag(&tk->tp, TP_FLAG_PROFILE)) ret = kprobe_perf_func(tk, regs); #endif return ret; @@ -1618,15 +1603,13 @@ static int kretprobe_dispatcher(struct kretprobe_instance *ri, struct pt_regs *regs) { struct trace_kprobe *tk = container_of(ri->rp, struct trace_kprobe, rp); - unsigned int flags; raw_cpu_inc(*tk->nhit); - flags = trace_probe_load_flag(&tk->tp); - if (flags & TP_FLAG_TRACE) + if (trace_probe_test_flag(&tk->tp, TP_FLAG_TRACE)) kretprobe_trace_func(tk, ri, regs); #ifdef CONFIG_PERF_EVENTS - if (flags & TP_FLAG_PROFILE) + if (trace_probe_test_flag(&tk->tp, TP_FLAG_PROFILE)) kretprobe_perf_func(tk, ri, regs); #endif return 0; /* We don't tweek kernel, so just return 0 */ diff --git a/kernel/trace/trace_printk.c b/kernel/trace/trace_printk.c index 0bf2a1d21ecd..b8014b361a1a 100644 --- a/kernel/trace/trace_printk.c +++ b/kernel/trace/trace_printk.c @@ -96,7 +96,7 @@ static int module_trace_bprintk_format_notify(struct notifier_block *self, if (val == MODULE_STATE_COMING) hold_module_trace_bprintk_format(start, end); } - return NOTIFY_OK; + return 0; } /* @@ -174,7 +174,7 @@ __init static int module_trace_bprintk_format_notify(struct notifier_block *self, unsigned long val, void *data) { - return NOTIFY_OK; + return 0; } static inline const char ** find_next_mod_format(int start_index, void *v, const char **fmt, loff_t *pos) diff --git a/kernel/trace/trace_probe.h b/kernel/trace/trace_probe.h index 15c9ef34a611..edbb1624061e 100644 --- a/kernel/trace/trace_probe.h +++ b/kernel/trace/trace_probe.h @@ -252,21 +252,16 @@ struct event_file_link { struct list_head list; }; -static inline unsigned int trace_probe_load_flag(struct trace_probe *tp) -{ - return smp_load_acquire(&tp->event->flags); -} - static inline bool trace_probe_test_flag(struct trace_probe *tp, unsigned int flag) { - return !!(trace_probe_load_flag(tp) & flag); + return !!(tp->event->flags & flag); } static inline void trace_probe_set_flag(struct trace_probe *tp, unsigned int flag) { - smp_store_release(&tp->event->flags, tp->event->flags | flag); + tp->event->flags |= flag; } static inline void trace_probe_clear_flag(struct trace_probe *tp, diff --git a/kernel/trace/trace_stack.c b/kernel/trace/trace_stack.c index 98bba4764c52..c557f42a9397 100644 --- a/kernel/trace/trace_stack.c +++ b/kernel/trace/trace_stack.c @@ -515,8 +515,9 @@ static const struct file_operations stack_trace_filter_fops = { #endif /* CONFIG_DYNAMIC_FTRACE */ int -stack_trace_sysctl(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos) +stack_trace_sysctl(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos) { int was_enabled; int ret; diff --git a/kernel/trace/trace_uprobe.c b/kernel/trace/trace_uprobe.c index dcc72df3a2bf..25e86e85bfac 100644 --- a/kernel/trace/trace_uprobe.c +++ b/kernel/trace/trace_uprobe.c @@ -1469,7 +1469,6 @@ static int uprobe_dispatcher(struct uprobe_consumer *con, struct pt_regs *regs) struct uprobe_dispatch_data udd; struct uprobe_cpu_buffer *ucb; int dsize, esize; - unsigned int flags; int ret = 0; @@ -1490,12 +1489,11 @@ static int uprobe_dispatcher(struct uprobe_consumer *con, struct pt_regs *regs) ucb = uprobe_buffer_get(); store_trace_args(ucb->buf, &tu->tp, regs, esize, dsize); - flags = trace_probe_load_flag(&tu->tp); - if (flags & TP_FLAG_TRACE) + if (trace_probe_test_flag(&tu->tp, TP_FLAG_TRACE)) ret |= uprobe_trace_func(tu, regs, ucb, dsize); #ifdef CONFIG_PERF_EVENTS - if (flags & TP_FLAG_PROFILE) + if (trace_probe_test_flag(&tu->tp, TP_FLAG_PROFILE)) ret |= uprobe_perf_func(tu, regs, ucb, dsize); #endif uprobe_buffer_put(ucb); @@ -1509,7 +1507,6 @@ static int uretprobe_dispatcher(struct uprobe_consumer *con, struct uprobe_dispatch_data udd; struct uprobe_cpu_buffer *ucb; int dsize, esize; - unsigned int flags; tu = container_of(con, struct trace_uprobe, consumer); @@ -1527,12 +1524,11 @@ static int uretprobe_dispatcher(struct uprobe_consumer *con, ucb = uprobe_buffer_get(); store_trace_args(ucb->buf, &tu->tp, regs, esize, dsize); - flags = trace_probe_load_flag(&tu->tp); - if (flags & TP_FLAG_TRACE) + if (trace_probe_test_flag(&tu->tp, TP_FLAG_TRACE)) uretprobe_trace_func(tu, func, regs, ucb, dsize); #ifdef CONFIG_PERF_EVENTS - if (flags & TP_FLAG_PROFILE) + if (trace_probe_test_flag(&tu->tp, TP_FLAG_PROFILE)) uretprobe_perf_func(tu, func, regs, ucb, dsize); #endif uprobe_buffer_put(ucb); diff --git a/kernel/tracepoint.c b/kernel/tracepoint.c index fbf6acae1a39..5d87b21ba130 100644 --- a/kernel/tracepoint.c +++ b/kernel/tracepoint.c @@ -596,7 +596,7 @@ static int tracepoint_module_notify(struct notifier_block *self, case MODULE_STATE_UNFORMED: break; } - return notifier_from_errno(ret); + return ret; } static struct notifier_block tracepoint_module_nb = { diff --git a/kernel/umh.c b/kernel/umh.c index df68772ad521..f601857fa9b1 100644 --- a/kernel/umh.c +++ b/kernel/umh.c @@ -27,6 +27,8 @@ #include #include #include +#include +#include #include @@ -37,6 +39,8 @@ static kernel_cap_t usermodehelper_bset = CAP_FULL_SET; static kernel_cap_t usermodehelper_inheritable = CAP_FULL_SET; static DEFINE_SPINLOCK(umh_sysctl_lock); static DECLARE_RWSEM(umhelper_sem); +static LIST_HEAD(umh_list); +static DEFINE_MUTEX(umh_list_lock); static void call_usermodehelper_freeinfo(struct subprocess_info *info) { @@ -107,10 +111,13 @@ static int call_usermodehelper_exec_async(void *data) commit_creds(new); - if (sub_info->file) + sub_info->pid = task_pid_nr(current); + if (sub_info->file) { retval = do_execve_file(sub_info->file, sub_info->argv, sub_info->envp); - else + if (!retval) + current->flags |= PF_UMH; + } else retval = do_execve(getname_kernel(sub_info->path), (const char __user *const __user *)sub_info->argv, (const char __user *const __user *)sub_info->envp); @@ -411,6 +418,140 @@ struct subprocess_info *call_usermodehelper_setup(const char *path, char **argv, } EXPORT_SYMBOL(call_usermodehelper_setup); +struct subprocess_info *call_usermodehelper_setup_file(struct file *file, + int (*init)(struct subprocess_info *info, struct cred *new), + void (*cleanup)(struct subprocess_info *info), void *data) +{ + struct subprocess_info *sub_info; + struct umh_info *info = data; + const char *cmdline = (info->cmdline) ? info->cmdline : "usermodehelper"; + + sub_info = kzalloc(sizeof(struct subprocess_info), GFP_KERNEL); + if (!sub_info) + return NULL; + + sub_info->argv = argv_split(GFP_KERNEL, cmdline, NULL); + if (!sub_info->argv) { + kfree(sub_info); + return NULL; + } + + INIT_WORK(&sub_info->work, call_usermodehelper_exec_work); + sub_info->path = "none"; + sub_info->file = file; + sub_info->init = init; + sub_info->cleanup = cleanup; + sub_info->data = data; + return sub_info; +} + +static int umh_pipe_setup(struct subprocess_info *info, struct cred *new) +{ + struct umh_info *umh_info = info->data; + struct file *from_umh[2]; + struct file *to_umh[2]; + int err; + + /* create pipe to send data to umh */ + err = create_pipe_files(to_umh, 0); + if (err) + return err; + err = replace_fd(0, to_umh[0], 0); + fput(to_umh[0]); + if (err < 0) { + fput(to_umh[1]); + return err; + } + + /* create pipe to receive data from umh */ + err = create_pipe_files(from_umh, 0); + if (err) { + fput(to_umh[1]); + replace_fd(0, NULL, 0); + return err; + } + err = replace_fd(1, from_umh[1], 0); + fput(from_umh[1]); + if (err < 0) { + fput(to_umh[1]); + replace_fd(0, NULL, 0); + fput(from_umh[0]); + return err; + } + + umh_info->pipe_to_umh = to_umh[1]; + umh_info->pipe_from_umh = from_umh[0]; + return 0; +} + +static void umh_clean_and_save_pid(struct subprocess_info *info) +{ + struct umh_info *umh_info = info->data; + + /* cleanup if umh_pipe_setup() was successful but exec failed */ + if (info->pid && info->retval) { + fput(umh_info->pipe_to_umh); + fput(umh_info->pipe_from_umh); + } + + argv_free(info->argv); + umh_info->pid = info->pid; +} + +/** + * fork_usermode_blob - fork a blob of bytes as a usermode process + * @data: a blob of bytes that can be do_execv-ed as a file + * @len: length of the blob + * @info: information about usermode process (shouldn't be NULL) + * + * If info->cmdline is set it will be used as command line for the + * user process, else "usermodehelper" is used. + * + * Returns either negative error or zero which indicates success + * in executing a blob of bytes as a usermode process. In such + * case 'struct umh_info *info' is populated with two pipes + * and a pid of the process. The caller is responsible for health + * check of the user process, killing it via pid, and closing the + * pipes when user process is no longer needed. + */ +int fork_usermode_blob(void *data, size_t len, struct umh_info *info) +{ + struct subprocess_info *sub_info; + struct file *file; + ssize_t written; + loff_t pos = 0; + int err; + + file = shmem_kernel_file_setup("", len, 0); + if (IS_ERR(file)) + return PTR_ERR(file); + + written = kernel_write(file, data, len, &pos); + if (written != len) { + err = written; + if (err >= 0) + err = -ENOMEM; + goto out; + } + + err = -ENOMEM; + sub_info = call_usermodehelper_setup_file(file, umh_pipe_setup, + umh_clean_and_save_pid, info); + if (!sub_info) + goto out; + + err = call_usermodehelper_exec(sub_info, UMH_WAIT_EXEC); + if (!err) { + mutex_lock(&umh_list_lock); + list_add(&info->list, &umh_list); + mutex_unlock(&umh_list_lock); + } +out: + fput(file); + return err; +} +EXPORT_SYMBOL_GPL(fork_usermode_blob); + /** * call_usermodehelper_exec - start a usermode application * @sub_info: information about the subprocessa @@ -513,7 +654,7 @@ int call_usermodehelper(const char *path, char **argv, char **envp, int wait) EXPORT_SYMBOL(call_usermodehelper); static int proc_cap_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ctl_table t; unsigned long cap_array[_KERNEL_CAPABILITY_U32S]; @@ -572,6 +713,26 @@ static int proc_cap_handler(struct ctl_table *table, int write, return 0; } +void __exit_umh(struct task_struct *tsk) +{ + struct umh_info *info; + pid_t pid = tsk->pid; + + mutex_lock(&umh_list_lock); + list_for_each_entry(info, &umh_list, list) { + if (info->pid == pid) { + list_del(&info->list); + mutex_unlock(&umh_list_lock); + goto out; + } + } + mutex_unlock(&umh_list_lock); + return; +out: + if (info->cleanup) + info->cleanup(info); +} + struct ctl_table usermodehelper_table[] = { { .procname = "bset", diff --git a/kernel/usermode_driver.c b/kernel/usermode_driver.c deleted file mode 100644 index 5fdeb7a52004..000000000000 --- a/kernel/usermode_driver.c +++ /dev/null @@ -1,225 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * umd - User mode driver support - */ -#include -#include -#include -#include -#include -#include - -static LIST_HEAD(umh_list); -static DEFINE_MUTEX(umh_list_lock); - -static struct vfsmount *blob_to_mnt(const void *data, size_t len, const char *name) -{ - struct file_system_type *type; - struct vfsmount *mnt; - struct file *file; - ssize_t written; - loff_t pos = 0; - - type = get_fs_type("tmpfs"); - if (!type) - return ERR_PTR(-ENODEV); - - mnt = kern_mount(type); - put_filesystem(type); - if (IS_ERR(mnt)) - return mnt; - - file = file_open_root(mnt->mnt_root, mnt, name, O_CREAT | O_WRONLY, 0700); - if (IS_ERR(file)) { - mntput(mnt); - return ERR_CAST(file); - } - - written = kernel_write(file, data, len, &pos); - if (written != len) { - int err = written; - if (err >= 0) - err = -ENOMEM; - filp_close(file, NULL); - mntput(mnt); - return ERR_PTR(err); - } - - fput(file); - - /* Flush delayed fput so exec can open the file read-only */ - flush_delayed_fput(); - task_work_run(); - return mnt; -} - -/** - * umd_load_blob - Remember a blob of bytes for fork_usermode_driver - * @info: information about usermode driver - * @data: a blob of bytes that can be executed as a file - * @len: The lentgh of the blob - * - */ -int umd_load_blob(struct umd_info *info, const void *data, size_t len) -{ - struct vfsmount *mnt; - - if (WARN_ON_ONCE(info->wd.dentry || info->wd.mnt)) - return -EBUSY; - - mnt = blob_to_mnt(data, len, info->driver_name); - if (IS_ERR(mnt)) - return PTR_ERR(mnt); - - info->wd.mnt = mnt; - info->wd.dentry = mnt->mnt_root; - return 0; -} -EXPORT_SYMBOL_GPL(umd_load_blob); - -/** - * umd_unload_blob - Disassociate @info from a previously loaded blob - * @info: information about usermode driver - * - */ -int umd_unload_blob(struct umd_info *info) -{ - if (WARN_ON_ONCE(!info->wd.mnt || - !info->wd.dentry || - info->wd.mnt->mnt_root != info->wd.dentry)) - return -EINVAL; - - kern_unmount(info->wd.mnt); - info->wd.mnt = NULL; - info->wd.dentry = NULL; - return 0; -} -EXPORT_SYMBOL_GPL(umd_unload_blob); - -static int umd_setup(struct subprocess_info *info, struct cred *new) -{ - struct umd_info *umd_info = info->data; - struct file *from_umh[2]; - struct file *to_umh[2]; - int err; - - /* create pipe to send data to umh */ - err = create_pipe_files(to_umh, 0); - if (err) - return err; - err = replace_fd(0, to_umh[0], 0); - fput(to_umh[0]); - if (err < 0) { - fput(to_umh[1]); - return err; - } - - /* create pipe to receive data from umh */ - err = create_pipe_files(from_umh, 0); - if (err) { - fput(to_umh[1]); - replace_fd(0, NULL, 0); - return err; - } - err = replace_fd(1, from_umh[1], 0); - fput(from_umh[1]); - if (err < 0) { - fput(to_umh[1]); - replace_fd(0, NULL, 0); - fput(from_umh[0]); - return err; - } - - set_fs_pwd(current->fs, &umd_info->wd); - umd_info->pipe_to_umh = to_umh[1]; - umd_info->pipe_from_umh = from_umh[0]; - umd_info->tgid = get_pid(task_tgid(current)); - current->flags |= PF_UMH; - return 0; -} - -static void umd_cleanup(struct subprocess_info *info) -{ - struct umd_info *umd_info = info->data; - - /* cleanup if umh_setup() was successful but exec failed */ - if (info->retval) - umd_cleanup_helper(umd_info); -} - -/** - * umd_cleanup_helper - release the resources which were allocated in umd_setup - * @info: information about usermode driver - */ -void umd_cleanup_helper(struct umd_info *info) -{ - fput(info->pipe_to_umh); - fput(info->pipe_from_umh); - put_pid(info->tgid); - info->tgid = NULL; -} -EXPORT_SYMBOL_GPL(umd_cleanup_helper); - -/** - * fork_usermode_driver - fork a usermode driver - * @info: information about usermode driver (shouldn't be NULL) - * - * Returns either negative error or zero which indicates success in - * executing a usermode driver. In such case 'struct umd_info *info' - * is populated with two pipes and a tgid of the process. The caller is - * responsible for health check of the user process, killing it via - * tgid, and closing the pipes when user process is no longer needed. - */ -int fork_usermode_driver(struct umd_info *info) -{ - struct subprocess_info *sub_info; - char **argv = NULL; - int err; - - if (WARN_ON_ONCE(info->tgid)) - return -EBUSY; - - err = -ENOMEM; - argv = argv_split(GFP_KERNEL, info->driver_name, NULL); - if (!argv) - goto out; - - sub_info = call_usermodehelper_setup(info->driver_name, argv, NULL, - GFP_KERNEL, - umd_setup, umd_cleanup, info); - if (!sub_info) - goto out; - - err = call_usermodehelper_exec(sub_info, UMH_WAIT_EXEC); - if (!err) { - mutex_lock(&umh_list_lock); - list_add(&info->list, &umh_list); - mutex_unlock(&umh_list_lock); - } -out: - if (argv) - argv_free(argv); - return err; -} -EXPORT_SYMBOL_GPL(fork_usermode_driver); - -void __exit_umh(struct task_struct *tsk) -{ - struct umd_info *info; - struct pid *tgid = task_tgid(tsk); - - mutex_lock(&umh_list_lock); - list_for_each_entry(info, &umh_list, list) { - if (info->tgid == tgid) { - list_del(&info->list); - mutex_unlock(&umh_list_lock); - goto out; - } - } - mutex_unlock(&umh_list_lock); - return; -out: - if (info->cleanup) - info->cleanup(info); -} - diff --git a/kernel/utsname_sysctl.c b/kernel/utsname_sysctl.c index 4ca61d49885b..3732c888a949 100644 --- a/kernel/utsname_sysctl.c +++ b/kernel/utsname_sysctl.c @@ -30,7 +30,7 @@ static void *get_uts(struct ctl_table *table) * to observe. Should this be in kernel/sys.c ???? */ static int proc_do_uts_string(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ctl_table uts_table; int r; diff --git a/kernel/watchdog.c b/kernel/watchdog.c index d8c2f023cccf..d6651c10a8bf 100644 --- a/kernel/watchdog.c +++ b/kernel/watchdog.c @@ -719,7 +719,7 @@ static void proc_watchdog_update(void) * proc_soft_watchdog | soft_watchdog_user_enabled | SOFT_WATCHDOG_ENABLED */ static int proc_watchdog_common(int which, struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int err, old, *param = table->data; @@ -746,7 +746,7 @@ static int proc_watchdog_common(int which, struct ctl_table *table, int write, * /proc/sys/kernel/watchdog */ int proc_watchdog(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return proc_watchdog_common(NMI_WATCHDOG_ENABLED|SOFT_WATCHDOG_ENABLED, table, write, buffer, lenp, ppos); @@ -756,7 +756,7 @@ int proc_watchdog(struct ctl_table *table, int write, * /proc/sys/kernel/nmi_watchdog */ int proc_nmi_watchdog(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { if (!nmi_watchdog_available && write) return -ENOTSUPP; @@ -768,7 +768,7 @@ int proc_nmi_watchdog(struct ctl_table *table, int write, * /proc/sys/kernel/soft_watchdog */ int proc_soft_watchdog(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { return proc_watchdog_common(SOFT_WATCHDOG_ENABLED, table, write, buffer, lenp, ppos); @@ -778,7 +778,7 @@ int proc_soft_watchdog(struct ctl_table *table, int write, * /proc/sys/kernel/watchdog_thresh */ int proc_watchdog_thresh(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int err, old; @@ -801,7 +801,7 @@ int proc_watchdog_thresh(struct ctl_table *table, int write, * been brought online, if desired. */ int proc_watchdog_cpumask(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int err; diff --git a/kernel/workqueue.c b/kernel/workqueue.c index 91191464870a..611831132baa 100644 --- a/kernel/workqueue.c +++ b/kernel/workqueue.c @@ -4652,11 +4652,11 @@ void print_worker_info(const char *log_lvl, struct task_struct *task) * Carefully copy the associated workqueue's workfn, name and desc. * Keep the original last '\0' in case the original is garbage. */ - copy_from_kernel_nofault(&fn, &worker->current_func, sizeof(fn)); - copy_from_kernel_nofault(&pwq, &worker->current_pwq, sizeof(pwq)); - copy_from_kernel_nofault(&wq, &pwq->wq, sizeof(wq)); - copy_from_kernel_nofault(name, wq->name, sizeof(name) - 1); - copy_from_kernel_nofault(desc, worker->desc, sizeof(desc) - 1); + probe_kernel_read(&fn, &worker->current_func, sizeof(fn)); + probe_kernel_read(&pwq, &worker->current_pwq, sizeof(pwq)); + probe_kernel_read(&wq, &pwq->wq, sizeof(wq)); + probe_kernel_read(name, wq->name, sizeof(name) - 1); + probe_kernel_read(desc, worker->desc, sizeof(desc) - 1); if (fn || name[0] || desc[0]) { printk("%sWorkqueue: %s %ps", log_lvl, name, fn); diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index f47cbf5660b1..b74832919af2 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -782,7 +782,6 @@ config DEBUG_STACKOVERFLOW If in doubt, say "N". source "lib/Kconfig.kasan" -source "lib/Kconfig.kfence" endmenu # "Memory Debugging" diff --git a/lib/Kconfig.kfence b/lib/Kconfig.kfence deleted file mode 100644 index e641add33947..000000000000 --- a/lib/Kconfig.kfence +++ /dev/null @@ -1,83 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -config HAVE_ARCH_KFENCE - bool - -menuconfig KFENCE - bool "KFENCE: low-overhead sampling-based memory safety error detector" - depends on HAVE_ARCH_KFENCE && (SLAB || SLUB) - select STACKTRACE - select IRQ_WORK - help - KFENCE is a low-overhead sampling-based detector of heap out-of-bounds - access, use-after-free, and invalid-free errors. KFENCE is designed - to have negligible cost to permit enabling it in production - environments. - - See for more details. - - Note that, KFENCE is not a substitute for explicit testing with tools - such as KASAN. KFENCE can detect a subset of bugs that KASAN can - detect, albeit at very different performance profiles. If you can - afford to use KASAN, continue using KASAN, for example in test - environments. If your kernel targets production use, and cannot - enable KASAN due to its cost, consider using KFENCE. - -if KFENCE - -config KFENCE_STATIC_KEYS - bool "Use static keys to set up allocations" - default y - depends on JUMP_LABEL # To ensure performance, require jump labels - help - Use static keys (static branches) to set up KFENCE allocations. Using - static keys is normally recommended, because it avoids a dynamic - branch in the allocator's fast path. However, with very low sample - intervals, or on systems that do not support jump labels, a dynamic - branch may still be an acceptable performance trade-off. - -config KFENCE_SAMPLE_INTERVAL - int "Default sample interval in milliseconds" - default 100 - help - The KFENCE sample interval determines the frequency with which heap - allocations will be guarded by KFENCE. May be overridden via boot - parameter "kfence.sample_interval". - - Set this to 0 to disable KFENCE by default, in which case only - setting "kfence.sample_interval" to a non-zero value enables KFENCE. - -config KFENCE_NUM_OBJECTS - int "Number of guarded objects available" - range 1 65535 - default 255 - help - The number of guarded objects available. For each KFENCE object, 2 - pages are required; with one containing the object and two adjacent - ones used as guard pages. - -config KFENCE_STRESS_TEST_FAULTS - int "Stress testing of fault handling and error reporting" if EXPERT - default 0 - help - The inverse probability with which to randomly protect KFENCE object - pages, resulting in spurious use-after-frees. The main purpose of - this option is to stress test KFENCE with concurrent error reports - and allocations/frees. A value of 0 disables stress testing logic. - - Only for KFENCE testing; set to 0 if you are not a KFENCE developer. - -config KFENCE_KUNIT_TEST - tristate "KFENCE integration test suite" if !KUNIT_ALL_TESTS - default KUNIT_ALL_TESTS - depends on TRACEPOINTS && KUNIT - help - Test suite for KFENCE, testing various error detection scenarios with - various allocation types, and checking that reports are correctly - output to console. - - Say Y here if you want the test to be built into the kernel and run - during boot; say M if you want the test to build as a module; say N - if you are unsure. - -endif # KFENCE diff --git a/lib/genalloc.c b/lib/genalloc.c index 6a88836c1dce..80d10d02cf38 100644 --- a/lib/genalloc.c +++ b/lib/genalloc.c @@ -892,11 +892,8 @@ struct gen_pool *of_gen_pool_get(struct device_node *np, if (!name) name = np_pool->name; } - if (pdev) { + if (pdev) pool = gen_pool_get(&pdev->dev, name); - put_device(&pdev->dev); - } - of_node_put(np_pool); return pool; diff --git a/lib/sha1.c b/lib/sha1.c index b9c0f15860c7..bad46695476b 100644 --- a/lib/sha1.c +++ b/lib/sha1.c @@ -66,24 +66,22 @@ #define T_60_79(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (B^C^D) , 0xca62c1d6, A, B, C, D, E ) /** - * sha1_transform - single block SHA1 transform (deprecated) + * sha_transform - single block SHA1 transform * * @digest: 160 bit digest to update * @data: 512 bits of data to hash * @array: 16 words of workspace (see note) * - * This function executes SHA-1's internal compression function. It updates the - * 160-bit internal state (@digest) with a single 512-bit data block (@data). - * - * Don't use this function. SHA-1 is no longer considered secure. And even if - * you do have to use SHA-1, this isn't the correct way to hash something with - * SHA-1 as this doesn't handle padding and finalization. + * This function generates a SHA1 digest for a single 512-bit block. + * Be warned, it does not handle padding and message digest, do not + * confuse it with the full FIPS 180-1 digest algorithm for variable + * length messages. * * Note: If the hash is security sensitive, the caller should be sure * to clear the workspace. This is left to the caller to avoid * unnecessary clears between chained hashing operations. */ -void sha1_transform(__u32 *digest, const char *data, __u32 *array) +void sha_transform(__u32 *digest, const char *data, __u32 *array) { __u32 A, B, C, D, E; unsigned int i = 0; @@ -120,13 +118,13 @@ void sha1_transform(__u32 *digest, const char *data, __u32 *array) digest[3] += D; digest[4] += E; } -EXPORT_SYMBOL(sha1_transform); +EXPORT_SYMBOL(sha_transform); /** - * sha1_init - initialize the vectors for a SHA1 digest + * sha_init - initialize the vectors for a SHA1 digest * @buf: vector to initialize */ -void sha1_init(__u32 *buf) +void sha_init(__u32 *buf) { buf[0] = 0x67452301; buf[1] = 0xefcdab89; @@ -134,4 +132,4 @@ void sha1_init(__u32 *buf) buf[3] = 0x10325476; buf[4] = 0xc3d2e1f0; } -EXPORT_SYMBOL(sha1_init); +EXPORT_SYMBOL(sha_init); diff --git a/lib/strncpy_from_user.c b/lib/strncpy_from_user.c index e136beefa7ba..706020b06617 100644 --- a/lib/strncpy_from_user.c +++ b/lib/strncpy_from_user.c @@ -34,32 +34,17 @@ static inline long do_strncpy_from_user(char *dst, const char __user *src, goto byte_at_a_time; while (max >= sizeof(unsigned long)) { - unsigned long c, data, mask; + unsigned long c, data; /* Fall back to byte-at-a-time if we get a page fault */ unsafe_get_user(c, (unsigned long __user *)(src+res), byte_at_a_time); - /* - * Note that we mask out the bytes following the NUL. This is - * important to do because string oblivious code may read past - * the NUL. For those routines, we don't want to give them - * potentially random bytes after the NUL in `src`. - * - * One example of such code is BPF map keys. BPF treats map keys - * as an opaque set of bytes. Without the post-NUL mask, any BPF - * maps keyed by strings returned from strncpy_from_user() may - * have multiple entries for semantically identical strings. - */ + *(unsigned long *)(dst+res) = c; if (has_zero(c, &data, &constants)) { data = prep_zero_mask(c, data, &constants); data = create_zero_mask(data); - mask = zero_bytemask(data); - *(unsigned long *)(dst+res) = c & mask; return res + find_zero(data); } - - *(unsigned long *)(dst+res) = c; - res += sizeof(unsigned long); max -= sizeof(unsigned long); } diff --git a/lib/test_bitmap.c b/lib/test_bitmap.c index 1ee9d95898b5..51a98f7ee79e 100644 --- a/lib/test_bitmap.c +++ b/lib/test_bitmap.c @@ -16,7 +16,8 @@ #include "../tools/testing/selftests/kselftest_module.h" -KSTM_MODULE_GLOBALS(); +static unsigned total_tests __initdata; +static unsigned failed_tests __initdata; static char pbl_buffer[PAGE_SIZE] __initdata; diff --git a/lib/test_bpf.c b/lib/test_bpf.c index b6f33d980872..3ae002ced4c7 100644 --- a/lib/test_bpf.c +++ b/lib/test_bpf.c @@ -6660,14 +6660,14 @@ static int __run_one(const struct bpf_prog *fp, const void *data, u64 start, finish; int ret = 0, i; - migrate_disable(); + preempt_disable(); start = ktime_get_ns(); for (i = 0; i < runs; i++) ret = BPF_PROG_RUN(fp, data); finish = ktime_get_ns(); - migrate_enable(); + preempt_enable(); *duration = finish - start; do_div(*duration, runs); diff --git a/lib/test_printf.c b/lib/test_printf.c index 0a3153f162c7..d4b711b53942 100644 --- a/lib/test_printf.c +++ b/lib/test_printf.c @@ -28,13 +28,11 @@ #define PAD_SIZE 16 #define FILL_CHAR '$' -KSTM_MODULE_GLOBALS(); - +static unsigned total_tests __initdata; +static unsigned failed_tests __initdata; static char *test_buffer __initdata; static char *alloced_buffer __initdata; -extern bool no_hash_pointers; - static int __printf(4, 0) __init do_test(int bufsize, const char *expect, int elen, const char *fmt, va_list ap) @@ -301,12 +299,6 @@ plain(void) { int err; - if (no_hash_pointers) { - pr_warn("skipping plain 'p' tests"); - skipped_tests += 2; - return; - } - err = plain_hash(); if (err) { pr_warn("plain 'p' does not appear to be hashed\n"); diff --git a/lib/vsprintf.c b/lib/vsprintf.c index f3d84136199b..b34657d3451b 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -2057,32 +2057,6 @@ static char *kobject_string(char *buf, char *end, void *ptr, return error_string(buf, end, "(%pO?)", spec); } -/* Disable pointer hashing if requested */ -bool no_hash_pointers __ro_after_init; -EXPORT_SYMBOL_GPL(no_hash_pointers); - -static int __init no_hash_pointers_enable(char *str) -{ - no_hash_pointers = true; - - pr_warn("**********************************************************\n"); - pr_warn("** NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE **\n"); - pr_warn("** **\n"); - pr_warn("** This system shows unhashed kernel memory addresses **\n"); - pr_warn("** via the console, logs, and other interfaces. This **\n"); - pr_warn("** might reduce the security of your system. **\n"); - pr_warn("** **\n"); - pr_warn("** If you see this message and you are not debugging **\n"); - pr_warn("** the kernel, report this immediately to your system **\n"); - pr_warn("** administrator! **\n"); - pr_warn("** **\n"); - pr_warn("** NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE **\n"); - pr_warn("**********************************************************\n"); - - return 0; -} -early_param("no_hash_pointers", no_hash_pointers_enable); - /* * Show a '%p' thing. A kernel extension is that the '%p' is followed * by an extra set of alphanumeric characters that are extended format @@ -2188,10 +2162,6 @@ early_param("no_hash_pointers", no_hash_pointers_enable); * c major compatible string * C full compatible string * - 'x' For printing the address. Equivalent to "%lx". - * - '[ku]s' For a BPF/tracing related format specifier, e.g. used out of - * bpf_trace_printk() where [ku] prefix specifies either kernel (k) - * or user (u) memory to probe, and: - * s a string, equivalent to "%s" on direct vsnprintf() use * * ** When making changes please also update: * Documentation/core-api/printk-formats.rst @@ -2272,27 +2242,13 @@ char *pointer(const char *fmt, char *buf, char *end, void *ptr, return kobject_string(buf, end, ptr, spec, fmt); case 'x': return pointer_string(buf, end, ptr, spec); - case 'u': - case 'k': - switch (fmt[1]) { - case 's': - return string(buf, end, ptr, spec); - default: - return error_string(buf, end, "(einval)", spec); - } } if (IS_ENABLED(CONFIG_DEBUG_CONSOLE_UNHASHED_POINTERS)) return pointer_string(buf, end, ptr, spec); - /* - * default is to _not_ leak addresses, so hash before printing, - * unless no_hash_pointers is specified on the command line. - */ - if (unlikely(no_hash_pointers)) - return pointer_string(buf, end, ptr, spec); - else - return ptr_to_id(buf, end, ptr, spec); + /* default is to _not_ leak addresses, hash before printing */ + return ptr_to_id(buf, end, ptr, spec); } /* diff --git a/mm/Makefile b/mm/Makefile index 7d852be8167b..d433568ee189 100644 --- a/mm/Makefile +++ b/mm/Makefile @@ -71,7 +71,6 @@ obj-$(CONFIG_PAGE_POISONING) += page_poison.o obj-$(CONFIG_SLAB) += slab.o obj-$(CONFIG_SLUB) += slub.o obj-$(CONFIG_KASAN) += kasan/ -obj-$(CONFIG_KFENCE) += kfence/ obj-$(CONFIG_FAILSLAB) += failslab.o obj-$(CONFIG_MEMORY_HOTPLUG) += memory_hotplug.o obj-$(CONFIG_MEMTEST) += memtest.o diff --git a/mm/backing-dev.c b/mm/backing-dev.c index 1dcde0685a5f..3954ef0cc770 100644 --- a/mm/backing-dev.c +++ b/mm/backing-dev.c @@ -878,8 +878,6 @@ struct backing_dev_info *bdi_alloc_node(gfp_t gfp_mask, int node_id) kfree(bdi); return NULL; } - bdi->ra_pages = VM_READAHEAD_PAGES; - bdi->io_pages = VM_READAHEAD_PAGES; return bdi; } EXPORT_SYMBOL(bdi_alloc_node); diff --git a/mm/compaction.c b/mm/compaction.c index d83347905d90..a75da20b8d0a 100644 --- a/mm/compaction.c +++ b/mm/compaction.c @@ -2453,7 +2453,7 @@ int sysctl_compact_memory; * /proc/sys/vm/compact_memory */ int sysctl_compaction_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos) + void __user *buffer, size_t *length, loff_t *ppos) { if (write) compact_nodes(); diff --git a/mm/hugetlb.c b/mm/hugetlb.c index b4a9a001ea6e..5fbc62a8c971 100644 --- a/mm/hugetlb.c +++ b/mm/hugetlb.c @@ -3145,7 +3145,7 @@ static int proc_hugetlb_doulongvec_minmax(struct ctl_table *table, int write, static int hugetlb_sysctl_handler_common(bool obey_mempolicy, struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos) + void __user *buffer, size_t *length, loff_t *ppos) { struct hstate *h = &default_hstate; unsigned long tmp = h->max_huge_pages; @@ -3167,7 +3167,7 @@ out: } int hugetlb_sysctl_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos) + void __user *buffer, size_t *length, loff_t *ppos) { return hugetlb_sysctl_handler_common(false, table, write, @@ -3176,7 +3176,7 @@ int hugetlb_sysctl_handler(struct ctl_table *table, int write, #ifdef CONFIG_NUMA int hugetlb_mempolicy_sysctl_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos) + void __user *buffer, size_t *length, loff_t *ppos) { return hugetlb_sysctl_handler_common(true, table, write, buffer, length, ppos); @@ -3184,7 +3184,8 @@ int hugetlb_mempolicy_sysctl_handler(struct ctl_table *table, int write, #endif /* CONFIG_NUMA */ int hugetlb_overcommit_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos) + void __user *buffer, + size_t *length, loff_t *ppos) { struct hstate *h = &default_hstate; unsigned long tmp; @@ -4736,8 +4737,6 @@ unsigned long hugetlb_change_protection(struct vm_area_struct *vma, pages++; } spin_unlock(ptl); - - cond_resched(); } /* * Must flush TLB before releasing i_mmap_rwsem: x86's huge_pmd_unshare diff --git a/mm/kasan/common.c b/mm/kasan/common.c index b71b16da066e..ac9f624158b9 100644 --- a/mm/kasan/common.c +++ b/mm/kasan/common.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -141,10 +140,6 @@ void kasan_poison_shadow(const void *address, size_t size, u8 value) */ address = reset_tag(address); - /* Skip KFENCE memory if called explicitly outside of sl*b. */ - if (is_kfence_address(address)) - return; - shadow_start = kasan_mem_to_shadow(address); shadow_end = kasan_mem_to_shadow(address + size); @@ -162,14 +157,6 @@ void kasan_unpoison_shadow(const void *address, size_t size) */ address = reset_tag(address); - /* - * Skip KFENCE memory if called explicitly outside of sl*b. Also note - * that calls to ksize(), where size is not a multiple of machine-word - * size, would otherwise poison the invalid portion of the word. - */ - if (is_kfence_address(address)) - return; - kasan_poison_shadow(address, size, tag); if (size & KASAN_SHADOW_MASK) { @@ -458,9 +445,6 @@ static bool __kasan_slab_free(struct kmem_cache *cache, void *object, tagged_object = object; object = reset_tag(object); - if (is_kfence_address(object)) - return false; - if (unlikely(nearest_obj(cache, virt_to_head_page(object), object) != object)) { kasan_report_invalid_free(tagged_object, ip); @@ -509,9 +493,6 @@ static void *__kasan_kmalloc(struct kmem_cache *cache, const void *object, if (unlikely(object == NULL)) return NULL; - if (is_kfence_address(kasan_reset_tag(object))) - return (void *)object; - redzone_start = round_up((unsigned long)(object + size), KASAN_SHADOW_SCALE_SIZE); redzone_end = round_up((unsigned long)object + cache->object_size, diff --git a/mm/kasan/report.c b/mm/kasan/report.c index 783301f294de..4d87df96acc1 100644 --- a/mm/kasan/report.c +++ b/mm/kasan/report.c @@ -29,7 +29,6 @@ #include #include #include -#include #include @@ -88,9 +87,8 @@ static void start_report(unsigned long *flags) pr_err("==================================================================\n"); } -static void end_report(unsigned long *flags, unsigned long addr) +static void end_report(unsigned long *flags) { - trace_error_report_end(ERROR_DETECTOR_KASAN, addr); pr_err("==================================================================\n"); add_taint(TAINT_BAD_PAGE, LOCKDEP_NOW_UNRELIABLE); spin_unlock_irqrestore(&report_lock, *flags); @@ -470,7 +468,7 @@ void kasan_report_invalid_free(void *object, unsigned long ip) print_address_description(object, tag); pr_err("\n"); print_shadow_for_address(object); - end_report(&flags, (unsigned long)object); + end_report(&flags); } void __kasan_report(unsigned long addr, size_t size, bool is_write, unsigned long ip) @@ -512,5 +510,5 @@ void __kasan_report(unsigned long addr, size_t size, bool is_write, unsigned lon dump_stack(); } - end_report(&flags, addr); + end_report(&flags); } diff --git a/mm/kfence/Makefile b/mm/kfence/Makefile deleted file mode 100644 index cb2bcf773083..000000000000 --- a/mm/kfence/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 - -obj-$(CONFIG_KFENCE) := core.o report.o - -CFLAGS_kfence_test.o := -fno-omit-frame-pointer -fno-optimize-sibling-calls -obj-$(CONFIG_KFENCE_KUNIT_TEST) += kfence_test.o diff --git a/mm/kfence/core.c b/mm/kfence/core.c deleted file mode 100644 index 566a82c3cb20..000000000000 --- a/mm/kfence/core.c +++ /dev/null @@ -1,889 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * KFENCE guarded object allocator and fault handling. - * - * Copyright (C) 2020, Google LLC. - */ - -#define pr_fmt(fmt) "kfence: " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "kfence.h" - -/* - * Android 4.19 kernel does not support KCSAN, so we have to disable data race - * annotations. - */ -#ifndef data_race -#define data_race(x) (x) -#endif - -/* Disables KFENCE on the first warning assuming an irrecoverable error. */ -#define KFENCE_WARN_ON(cond) \ - ({ \ - const bool __cond = WARN_ON(cond); \ - if (unlikely(__cond)) \ - WRITE_ONCE(kfence_enabled, false); \ - __cond; \ - }) - -/* === Data ================================================================= */ - -static bool kfence_enabled __read_mostly; - -static unsigned long kfence_sample_interval __read_mostly = CONFIG_KFENCE_SAMPLE_INTERVAL; - -#ifdef MODULE_PARAM_PREFIX -#undef MODULE_PARAM_PREFIX -#endif -#define MODULE_PARAM_PREFIX "kfence." - -static int param_set_sample_interval(const char *val, const struct kernel_param *kp) -{ - unsigned long num; - int ret = kstrtoul(val, 0, &num); - - if (ret < 0) - return ret; - - if (!num) /* Using 0 to indicate KFENCE is disabled. */ - WRITE_ONCE(kfence_enabled, false); - else if (!READ_ONCE(kfence_enabled) && system_state != SYSTEM_BOOTING) - return -EINVAL; /* Cannot (re-)enable KFENCE on-the-fly. */ - - *((unsigned long *)kp->arg) = num; - return 0; -} - -static int param_get_sample_interval(char *buffer, const struct kernel_param *kp) -{ - if (!READ_ONCE(kfence_enabled)) - return sprintf(buffer, "0\n"); - - return param_get_ulong(buffer, kp); -} - -static const struct kernel_param_ops sample_interval_param_ops = { - .set = param_set_sample_interval, - .get = param_get_sample_interval, -}; -module_param_cb(sample_interval, &sample_interval_param_ops, &kfence_sample_interval, 0600); - -/* The pool of pages used for guard pages and objects. */ -char *__kfence_pool __ro_after_init; -EXPORT_SYMBOL(__kfence_pool); /* Export for test modules. */ - -/* - * Per-object metadata, with one-to-one mapping of object metadata to - * backing pages (in __kfence_pool). - */ -static_assert(CONFIG_KFENCE_NUM_OBJECTS > 0); -struct kfence_metadata kfence_metadata[CONFIG_KFENCE_NUM_OBJECTS]; - -/* Freelist with available objects. */ -static struct list_head kfence_freelist = LIST_HEAD_INIT(kfence_freelist); -static DEFINE_RAW_SPINLOCK(kfence_freelist_lock); /* Lock protecting freelist. */ - -#ifdef CONFIG_KFENCE_STATIC_KEYS -/* The static key to set up a KFENCE allocation. */ -DEFINE_STATIC_KEY_FALSE(kfence_allocation_key); -#endif - -/* Gates the allocation, ensuring only one succeeds in a given period. */ -atomic_t kfence_allocation_gate = ATOMIC_INIT(1); - -/* Statistics counters for debugfs. */ -enum kfence_counter_id { - KFENCE_COUNTER_ALLOCATED, - KFENCE_COUNTER_ALLOCS, - KFENCE_COUNTER_FREES, - KFENCE_COUNTER_ZOMBIES, - KFENCE_COUNTER_BUGS, - KFENCE_COUNTER_COUNT, -}; -static atomic_long_t counters[KFENCE_COUNTER_COUNT]; -static const char *const counter_names[] = { - [KFENCE_COUNTER_ALLOCATED] = "currently allocated", - [KFENCE_COUNTER_ALLOCS] = "total allocations", - [KFENCE_COUNTER_FREES] = "total frees", - [KFENCE_COUNTER_ZOMBIES] = "zombie allocations", - [KFENCE_COUNTER_BUGS] = "total bugs", -}; -static_assert(ARRAY_SIZE(counter_names) == KFENCE_COUNTER_COUNT); - -/* === Internals ============================================================ */ - -static bool kfence_protect(unsigned long addr) -{ - return !KFENCE_WARN_ON(!kfence_protect_page(ALIGN_DOWN(addr, PAGE_SIZE), true)); -} - -static bool kfence_unprotect(unsigned long addr) -{ - return !KFENCE_WARN_ON(!kfence_protect_page(ALIGN_DOWN(addr, PAGE_SIZE), false)); -} - -static inline struct kfence_metadata *addr_to_metadata(unsigned long addr) -{ - long index; - - /* The checks do not affect performance; only called from slow-paths. */ - - if (!is_kfence_address((void *)addr)) - return NULL; - - /* - * May be an invalid index if called with an address at the edge of - * __kfence_pool, in which case we would report an "invalid access" - * error. - */ - index = (addr - (unsigned long)__kfence_pool) / (PAGE_SIZE * 2) - 1; - if (index < 0 || index >= CONFIG_KFENCE_NUM_OBJECTS) - return NULL; - - return &kfence_metadata[index]; -} - -static inline unsigned long metadata_to_pageaddr(const struct kfence_metadata *meta) -{ - unsigned long offset = (meta - kfence_metadata + 1) * PAGE_SIZE * 2; - unsigned long pageaddr = (unsigned long)&__kfence_pool[offset]; - - /* The checks do not affect performance; only called from slow-paths. */ - - /* Only call with a pointer into kfence_metadata. */ - if (KFENCE_WARN_ON(meta < kfence_metadata || - meta >= kfence_metadata + CONFIG_KFENCE_NUM_OBJECTS)) - return 0; - - /* - * This metadata object only ever maps to 1 page; verify that the stored - * address is in the expected range. - */ - if (KFENCE_WARN_ON(ALIGN_DOWN(meta->addr, PAGE_SIZE) != pageaddr)) - return 0; - - return pageaddr; -} - -/* - * Update the object's metadata state, including updating the alloc/free stacks - * depending on the state transition. - */ -static noinline void metadata_update_state(struct kfence_metadata *meta, - enum kfence_object_state next) -{ - struct kfence_track *track = - next == KFENCE_OBJECT_FREED ? &meta->free_track : &meta->alloc_track; - - lockdep_assert_held(&meta->lock); - - /* - * Skip over 1 (this) functions; noinline ensures we do not accidentally - * skip over the caller by never inlining. - */ - track->num_stack_entries = stack_trace_save(track->stack_entries, KFENCE_STACK_DEPTH, 1); - track->pid = task_pid_nr(current); - - /* - * Pairs with READ_ONCE() in - * kfence_shutdown_cache(), - * kfence_handle_page_fault(). - */ - WRITE_ONCE(meta->state, next); -} - -/* Write canary byte to @addr. */ -static inline bool set_canary_byte(u8 *addr) -{ - *addr = KFENCE_CANARY_PATTERN(addr); - return true; -} - -/* Check canary byte at @addr. */ -static inline bool check_canary_byte(u8 *addr) -{ - if (likely(*addr == KFENCE_CANARY_PATTERN(addr))) - return true; - - atomic_long_inc(&counters[KFENCE_COUNTER_BUGS]); - kfence_report_error((unsigned long)addr, false, NULL, addr_to_metadata((unsigned long)addr), - KFENCE_ERROR_CORRUPTION); - return false; -} - -/* __always_inline this to ensure we won't do an indirect call to fn. */ -static __always_inline void for_each_canary(const struct kfence_metadata *meta, bool (*fn)(u8 *)) -{ - const unsigned long pageaddr = ALIGN_DOWN(meta->addr, PAGE_SIZE); - unsigned long addr; - - lockdep_assert_held(&meta->lock); - - /* - * We'll iterate over each canary byte per-side until fn() returns - * false. However, we'll still iterate over the canary bytes to the - * right of the object even if there was an error in the canary bytes to - * the left of the object. Specifically, if check_canary_byte() - * generates an error, showing both sides might give more clues as to - * what the error is about when displaying which bytes were corrupted. - */ - - /* Apply to left of object. */ - for (addr = pageaddr; addr < meta->addr; addr++) { - if (!fn((u8 *)addr)) - break; - } - - /* Apply to right of object. */ - for (addr = meta->addr + meta->size; addr < pageaddr + PAGE_SIZE; addr++) { - if (!fn((u8 *)addr)) - break; - } -} - -static void *kfence_guarded_alloc(struct kmem_cache *cache, size_t size, gfp_t gfp) -{ - struct kfence_metadata *meta = NULL; - unsigned long flags; - struct page *page; - void *addr; - - /* Try to obtain a free object. */ - raw_spin_lock_irqsave(&kfence_freelist_lock, flags); - if (!list_empty(&kfence_freelist)) { - meta = list_entry(kfence_freelist.next, struct kfence_metadata, list); - list_del_init(&meta->list); - } - raw_spin_unlock_irqrestore(&kfence_freelist_lock, flags); - if (!meta) - return NULL; - - if (unlikely(!raw_spin_trylock_irqsave(&meta->lock, flags))) { - /* - * This is extremely unlikely -- we are reporting on a - * use-after-free, which locked meta->lock, and the reporting - * code via printk calls kmalloc() which ends up in - * kfence_alloc() and tries to grab the same object that we're - * reporting on. While it has never been observed, lockdep does - * report that there is a possibility of deadlock. Fix it by - * using trylock and bailing out gracefully. - */ - raw_spin_lock_irqsave(&kfence_freelist_lock, flags); - /* Put the object back on the freelist. */ - list_add_tail(&meta->list, &kfence_freelist); - raw_spin_unlock_irqrestore(&kfence_freelist_lock, flags); - - return NULL; - } - - meta->addr = metadata_to_pageaddr(meta); - /* Unprotect if we're reusing this page. */ - if (meta->state == KFENCE_OBJECT_FREED) - kfence_unprotect(meta->addr); - - /* - * Note: for allocations made before RNG initialization, will always - * return zero. We still benefit from enabling KFENCE as early as - * possible, even when the RNG is not yet available, as this will allow - * KFENCE to detect bugs due to earlier allocations. The only downside - * is that the out-of-bounds accesses detected are deterministic for - * such allocations. - */ - if (prandom_u32_max(2)) { - /* Allocate on the "right" side, re-calculate address. */ - meta->addr += PAGE_SIZE - size; - meta->addr = ALIGN_DOWN(meta->addr, cache->align); - } - - addr = (void *)meta->addr; - - /* Update remaining metadata. */ - metadata_update_state(meta, KFENCE_OBJECT_ALLOCATED); - /* Pairs with READ_ONCE() in kfence_shutdown_cache(). */ - WRITE_ONCE(meta->cache, cache); - meta->size = size; - for_each_canary(meta, set_canary_byte); - - /* Set required struct page fields. */ - page = virt_to_page(meta->addr); - page->slab_cache = cache; - if (IS_ENABLED(CONFIG_SLUB)) - page->objects = 1; - if (IS_ENABLED(CONFIG_SLAB)) - page->s_mem = addr; - - raw_spin_unlock_irqrestore(&meta->lock, flags); - - /* Memory initialization. */ - - /* - * We check slab_want_init_on_alloc() ourselves, rather than letting - * SL*B do the initialization, as otherwise we might overwrite KFENCE's - * redzone. - */ - if (unlikely(slab_want_init_on_alloc(gfp, cache))) - memzero_explicit(addr, size); - if (cache->ctor) - cache->ctor(addr); - - if (CONFIG_KFENCE_STRESS_TEST_FAULTS && !prandom_u32_max(CONFIG_KFENCE_STRESS_TEST_FAULTS)) - kfence_protect(meta->addr); /* Random "faults" by protecting the object. */ - - atomic_long_inc(&counters[KFENCE_COUNTER_ALLOCATED]); - atomic_long_inc(&counters[KFENCE_COUNTER_ALLOCS]); - - return addr; -} - -static void kfence_guarded_free(void *addr, struct kfence_metadata *meta, bool zombie) -{ - unsigned long flags; - - raw_spin_lock_irqsave(&meta->lock, flags); - - if (meta->state != KFENCE_OBJECT_ALLOCATED || meta->addr != (unsigned long)addr) { - /* Invalid or double-free, bail out. */ - atomic_long_inc(&counters[KFENCE_COUNTER_BUGS]); - kfence_report_error((unsigned long)addr, false, NULL, meta, - KFENCE_ERROR_INVALID_FREE); - raw_spin_unlock_irqrestore(&meta->lock, flags); - return; - } - - if (CONFIG_KFENCE_STRESS_TEST_FAULTS) - kfence_unprotect((unsigned long)addr); /* To check canary bytes. */ - - /* Restore page protection if there was an OOB access. */ - if (meta->unprotected_page) { - memzero_explicit((void *)ALIGN_DOWN(meta->unprotected_page, PAGE_SIZE), PAGE_SIZE); - kfence_protect(meta->unprotected_page); - meta->unprotected_page = 0; - } - - /* Check canary bytes for memory corruption. */ - for_each_canary(meta, check_canary_byte); - - /* - * Clear memory if init-on-free is set. While we protect the page, the - * data is still there, and after a use-after-free is detected, we - * unprotect the page, so the data is still accessible. - */ - if (!zombie && unlikely(slab_want_init_on_free(meta->cache))) - memzero_explicit(addr, meta->size); - - /* Mark the object as freed. */ - metadata_update_state(meta, KFENCE_OBJECT_FREED); - - raw_spin_unlock_irqrestore(&meta->lock, flags); - - /* Protect to detect use-after-frees. */ - kfence_protect((unsigned long)addr); - - if (!zombie) { - /* Add it to the tail of the freelist for reuse. */ - raw_spin_lock_irqsave(&kfence_freelist_lock, flags); - KFENCE_WARN_ON(!list_empty(&meta->list)); - list_add_tail(&meta->list, &kfence_freelist); - raw_spin_unlock_irqrestore(&kfence_freelist_lock, flags); - - atomic_long_dec(&counters[KFENCE_COUNTER_ALLOCATED]); - atomic_long_inc(&counters[KFENCE_COUNTER_FREES]); - } else { - /* See kfence_shutdown_cache(). */ - atomic_long_inc(&counters[KFENCE_COUNTER_ZOMBIES]); - } -} - -static void rcu_guarded_free(struct rcu_head *h) -{ - struct kfence_metadata *meta = container_of(h, struct kfence_metadata, rcu_head); - - kfence_guarded_free((void *)meta->addr, meta, false); -} - -static bool __init kfence_init_pool(void) -{ - unsigned long addr = (unsigned long)__kfence_pool; - struct page *pages; - int i; - - if (!__kfence_pool) - return false; - - if (!arch_kfence_init_pool()) - goto err; - - pages = virt_to_page(addr); - - /* - * Set up object pages: they must have PG_slab set, to avoid freeing - * these as real pages. - * - * We also want to avoid inserting kfence_free() in the kfree() - * fast-path in SLUB, and therefore need to ensure kfree() correctly - * enters __slab_free() slow-path. - */ - for (i = 0; i < KFENCE_POOL_SIZE / PAGE_SIZE; i++) { - if (!i || (i % 2)) - continue; - - /* Verify we do not have a compound head page. */ - if (WARN_ON(compound_head(&pages[i]) != &pages[i])) - goto err; - - __SetPageSlab(&pages[i]); - } - - /* - * Protect the first 2 pages. The first page is mostly unnecessary, and - * merely serves as an extended guard page. However, adding one - * additional page in the beginning gives us an even number of pages, - * which simplifies the mapping of address to metadata index. - */ - for (i = 0; i < 2; i++) { - if (unlikely(!kfence_protect(addr))) - goto err; - - addr += PAGE_SIZE; - } - - for (i = 0; i < CONFIG_KFENCE_NUM_OBJECTS; i++) { - struct kfence_metadata *meta = &kfence_metadata[i]; - - /* Initialize metadata. */ - INIT_LIST_HEAD(&meta->list); - raw_spin_lock_init(&meta->lock); - meta->state = KFENCE_OBJECT_UNUSED; - meta->addr = addr; /* Initialize for validation in metadata_to_pageaddr(). */ - list_add_tail(&meta->list, &kfence_freelist); - - /* Protect the right redzone. */ - if (unlikely(!kfence_protect(addr + PAGE_SIZE))) - goto err; - - addr += 2 * PAGE_SIZE; - } - - /* - * The pool is live and will never be deallocated from this point on. - * Remove the pool object from the kmemleak object tree, as it would - * otherwise overlap with allocations returned by kfence_alloc(), which - * are registered with kmemleak through the slab post-alloc hook. - */ - kmemleak_free(__kfence_pool); - - return true; - -err: - /* - * Only release unprotected pages, and do not try to go back and change - * page attributes due to risk of failing to do so as well. If changing - * page attributes for some pages fails, it is very likely that it also - * fails for the first page, and therefore expect addr==__kfence_pool in - * most failure cases. - */ - memblock_free_late(__pa(addr), KFENCE_POOL_SIZE - (addr - (unsigned long)__kfence_pool)); - __kfence_pool = NULL; - return false; -} - -/* === DebugFS Interface ==================================================== */ - -static int stats_show(struct seq_file *seq, void *v) -{ - int i; - - seq_printf(seq, "enabled: %i\n", READ_ONCE(kfence_enabled)); - for (i = 0; i < KFENCE_COUNTER_COUNT; i++) - seq_printf(seq, "%s: %ld\n", counter_names[i], atomic_long_read(&counters[i])); - - return 0; -} -DEFINE_SHOW_ATTRIBUTE(stats); - -/* - * debugfs seq_file operations for /sys/kernel/debug/kfence/objects. - * start_object() and next_object() return the object index + 1, because NULL is used - * to stop iteration. - */ -static void *start_object(struct seq_file *seq, loff_t *pos) -{ - if (*pos < CONFIG_KFENCE_NUM_OBJECTS) - return (void *)((long)*pos + 1); - return NULL; -} - -static void stop_object(struct seq_file *seq, void *v) -{ -} - -static void *next_object(struct seq_file *seq, void *v, loff_t *pos) -{ - ++*pos; - if (*pos < CONFIG_KFENCE_NUM_OBJECTS) - return (void *)((long)*pos + 1); - return NULL; -} - -static int show_object(struct seq_file *seq, void *v) -{ - struct kfence_metadata *meta = &kfence_metadata[(long)v - 1]; - unsigned long flags; - - raw_spin_lock_irqsave(&meta->lock, flags); - kfence_print_object(seq, meta); - raw_spin_unlock_irqrestore(&meta->lock, flags); - seq_puts(seq, "---------------------------------\n"); - - return 0; -} - -static const struct seq_operations object_seqops = { - .start = start_object, - .next = next_object, - .stop = stop_object, - .show = show_object, -}; - -static int open_objects(struct inode *inode, struct file *file) -{ - return seq_open(file, &object_seqops); -} - -static const struct file_operations objects_fops = { - .open = open_objects, - .read = seq_read, - .llseek = seq_lseek, - .release = seq_release, -}; - -static int __init kfence_debugfs_init(void) -{ - struct dentry *kfence_dir = debugfs_create_dir("kfence", NULL); - - debugfs_create_file("stats", 0444, kfence_dir, NULL, &stats_fops); - debugfs_create_file("objects", 0400, kfence_dir, NULL, &objects_fops); - return 0; -} - -late_initcall(kfence_debugfs_init); - -/* === Allocation Gate Timer ================================================ */ - -#ifdef CONFIG_KFENCE_STATIC_KEYS -/* Wait queue to wake up allocation-gate timer task. */ -static DECLARE_WAIT_QUEUE_HEAD(allocation_wait); - -static void wake_up_kfence_timer(struct irq_work *work) -{ - wake_up(&allocation_wait); -} -static DEFINE_IRQ_WORK(wake_up_kfence_timer_work, wake_up_kfence_timer); -#endif - -/* - * Set up delayed work, which will enable and disable the static key. We need to - * use a work queue (rather than a simple timer), since enabling and disabling a - * static key cannot be done from an interrupt. - * - * Note: Toggling a static branch currently causes IPIs, and here we'll end up - * with a total of 2 IPIs to all CPUs. If this ends up a problem in future (with - * more aggressive sampling intervals), we could get away with a variant that - * avoids IPIs, at the cost of not immediately capturing allocations if the - * instructions remain cached. - */ -static struct delayed_work kfence_timer; -static void toggle_allocation_gate(struct work_struct *work) -{ - if (!READ_ONCE(kfence_enabled)) - return; - - atomic_set(&kfence_allocation_gate, 0); -#ifdef CONFIG_KFENCE_STATIC_KEYS - /* Enable static key, and await allocation to happen. */ - static_branch_enable(&kfence_allocation_key); - - if (sysctl_hung_task_timeout_secs) { - /* - * During low activity with no allocations we might wait a - * while; let's avoid the hung task warning. - */ - wait_event_idle_timeout(allocation_wait, atomic_read(&kfence_allocation_gate), - sysctl_hung_task_timeout_secs * HZ / 2); - } else { - wait_event_idle(allocation_wait, atomic_read(&kfence_allocation_gate)); - } - - /* Disable static key and reset timer. */ - static_branch_disable(&kfence_allocation_key); -#endif - queue_delayed_work(system_unbound_wq, &kfence_timer, - msecs_to_jiffies(kfence_sample_interval)); -} -static DECLARE_DELAYED_WORK(kfence_timer, toggle_allocation_gate); - -/* === Public interface ===================================================== */ - -void __init kfence_alloc_pool(void) -{ - if (!kfence_sample_interval) - return; - - __kfence_pool = memblock_alloc(KFENCE_POOL_SIZE, PAGE_SIZE); - - if (!__kfence_pool) - pr_err("failed to allocate pool\n"); -} - -void __init kfence_init(void) -{ - /* Setting kfence_sample_interval to 0 on boot disables KFENCE. */ - if (!kfence_sample_interval) - return; - - if (!kfence_init_pool()) { - pr_err("%s failed\n", __func__); - return; - } - - WRITE_ONCE(kfence_enabled, true); - queue_delayed_work(system_unbound_wq, &kfence_timer, 0); - pr_info("initialized - using %lu bytes for %d objects at 0x%p-0x%p\n", KFENCE_POOL_SIZE, - CONFIG_KFENCE_NUM_OBJECTS, (void *)__kfence_pool, - (void *)(__kfence_pool + KFENCE_POOL_SIZE)); -} - -void kfence_shutdown_cache(struct kmem_cache *s) -{ - unsigned long flags; - struct kfence_metadata *meta; - int i; - - for (i = 0; i < CONFIG_KFENCE_NUM_OBJECTS; i++) { - bool in_use; - - meta = &kfence_metadata[i]; - - /* - * If we observe some inconsistent cache and state pair where we - * should have returned false here, cache destruction is racing - * with either kmem_cache_alloc() or kmem_cache_free(). Taking - * the lock will not help, as different critical section - * serialization will have the same outcome. - */ - if (READ_ONCE(meta->cache) != s || - READ_ONCE(meta->state) != KFENCE_OBJECT_ALLOCATED) - continue; - - raw_spin_lock_irqsave(&meta->lock, flags); - in_use = meta->cache == s && meta->state == KFENCE_OBJECT_ALLOCATED; - raw_spin_unlock_irqrestore(&meta->lock, flags); - - if (in_use) { - /* - * This cache still has allocations, and we should not - * release them back into the freelist so they can still - * safely be used and retain the kernel's default - * behaviour of keeping the allocations alive (leak the - * cache); however, they effectively become "zombie - * allocations" as the KFENCE objects are the only ones - * still in use and the owning cache is being destroyed. - * - * We mark them freed, so that any subsequent use shows - * more useful error messages that will include stack - * traces of the user of the object, the original - * allocation, and caller to shutdown_cache(). - */ - kfence_guarded_free((void *)meta->addr, meta, /*zombie=*/true); - } - } - - for (i = 0; i < CONFIG_KFENCE_NUM_OBJECTS; i++) { - meta = &kfence_metadata[i]; - - /* See above. */ - if (READ_ONCE(meta->cache) != s || READ_ONCE(meta->state) != KFENCE_OBJECT_FREED) - continue; - - raw_spin_lock_irqsave(&meta->lock, flags); - if (meta->cache == s && meta->state == KFENCE_OBJECT_FREED) - meta->cache = NULL; - raw_spin_unlock_irqrestore(&meta->lock, flags); - } -} - -void *__kfence_alloc(struct kmem_cache *s, size_t size, gfp_t flags) -{ - /* - * Perform size check before switching kfence_allocation_gate, so that - * we don't disable KFENCE without making an allocation. - */ - if (size > PAGE_SIZE) - return NULL; - - /* - * Skip allocations from non-default zones, including DMA. We cannot - * guarantee that pages in the KFENCE pool will have the requested - * properties (e.g. reside in DMAable memory). - */ - if ((flags & GFP_ZONEMASK) || - (s->flags & (SLAB_CACHE_DMA | SLAB_CACHE_DMA32))) - return NULL; - - /* - * allocation_gate only needs to become non-zero, so it doesn't make - * sense to continue writing to it and pay the associated contention - * cost, in case we have a large number of concurrent allocations. - */ - if (atomic_read(&kfence_allocation_gate) || atomic_inc_return(&kfence_allocation_gate) > 1) - return NULL; -#ifdef CONFIG_KFENCE_STATIC_KEYS - /* - * waitqueue_active() is fully ordered after the update of - * kfence_allocation_gate per atomic_inc_return(). - */ - if (waitqueue_active(&allocation_wait)) { - /* - * Calling wake_up() here may deadlock when allocations happen - * from within timer code. Use an irq_work to defer it. - */ - irq_work_queue(&wake_up_kfence_timer_work); - } -#endif - - if (!READ_ONCE(kfence_enabled)) - return NULL; - - return kfence_guarded_alloc(s, size, flags); -} - -size_t kfence_ksize(const void *addr) -{ - const struct kfence_metadata *meta = addr_to_metadata((unsigned long)addr); - - /* - * Read locklessly -- if there is a race with __kfence_alloc(), this is - * either a use-after-free or invalid access. - */ - return meta ? meta->size : 0; -} - -void *kfence_object_start(const void *addr) -{ - const struct kfence_metadata *meta = addr_to_metadata((unsigned long)addr); - - /* - * Read locklessly -- if there is a race with __kfence_alloc(), this is - * either a use-after-free or invalid access. - */ - return meta ? (void *)meta->addr : NULL; -} - -void __kfence_free(void *addr) -{ - struct kfence_metadata *meta = addr_to_metadata((unsigned long)addr); - - /* - * If the objects of the cache are SLAB_TYPESAFE_BY_RCU, defer freeing - * the object, as the object page may be recycled for other-typed - * objects once it has been freed. meta->cache may be NULL if the cache - * was destroyed. - */ - if (unlikely(meta->cache && (meta->cache->flags & SLAB_TYPESAFE_BY_RCU))) - call_rcu(&meta->rcu_head, rcu_guarded_free); - else - kfence_guarded_free(addr, meta, false); -} - -bool kfence_handle_page_fault(unsigned long addr, bool is_write, struct pt_regs *regs) -{ - const int page_index = (addr - (unsigned long)__kfence_pool) / PAGE_SIZE; - struct kfence_metadata *to_report = NULL; - enum kfence_error_type error_type; - unsigned long flags; - - if (!is_kfence_address((void *)addr)) - return false; - - if (!READ_ONCE(kfence_enabled)) /* If disabled at runtime ... */ - return kfence_unprotect(addr); /* ... unprotect and proceed. */ - - atomic_long_inc(&counters[KFENCE_COUNTER_BUGS]); - - if (page_index % 2) { - /* This is a redzone, report a buffer overflow. */ - struct kfence_metadata *meta; - int distance = 0; - - meta = addr_to_metadata(addr - PAGE_SIZE); - if (meta && READ_ONCE(meta->state) == KFENCE_OBJECT_ALLOCATED) { - to_report = meta; - /* Data race ok; distance calculation approximate. */ - distance = addr - data_race(meta->addr + meta->size); - } - - meta = addr_to_metadata(addr + PAGE_SIZE); - if (meta && READ_ONCE(meta->state) == KFENCE_OBJECT_ALLOCATED) { - /* Data race ok; distance calculation approximate. */ - if (!to_report || distance > data_race(meta->addr) - addr) - to_report = meta; - } - - if (!to_report) - goto out; - - raw_spin_lock_irqsave(&to_report->lock, flags); - to_report->unprotected_page = addr; - error_type = KFENCE_ERROR_OOB; - - /* - * If the object was freed before we took the look we can still - * report this as an OOB -- the report will simply show the - * stacktrace of the free as well. - */ - } else { - to_report = addr_to_metadata(addr); - if (!to_report) - goto out; - - raw_spin_lock_irqsave(&to_report->lock, flags); - error_type = KFENCE_ERROR_UAF; - /* - * We may race with __kfence_alloc(), and it is possible that a - * freed object may be reallocated. We simply report this as a - * use-after-free, with the stack trace showing the place where - * the object was re-allocated. - */ - } - -out: - if (to_report) { - kfence_report_error(addr, is_write, regs, to_report, error_type); - raw_spin_unlock_irqrestore(&to_report->lock, flags); - } else { - /* This may be a UAF or OOB access, but we can't be sure. */ - kfence_report_error(addr, is_write, regs, NULL, KFENCE_ERROR_INVALID); - } - - return kfence_unprotect(addr); /* Unprotect and let access proceed. */ -} diff --git a/mm/kfence/kfence.h b/mm/kfence/kfence.h deleted file mode 100644 index 24065321ff8a..000000000000 --- a/mm/kfence/kfence.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Kernel Electric-Fence (KFENCE). For more info please see - * Documentation/dev-tools/kfence.rst. - * - * Copyright (C) 2020, Google LLC. - */ - -#ifndef MM_KFENCE_KFENCE_H -#define MM_KFENCE_KFENCE_H - -#include -#include -#include -#include - -#include "../slab.h" /* for struct kmem_cache */ - -/* - * Get the canary byte pattern for @addr. Use a pattern that varies based on the - * lower 3 bits of the address, to detect memory corruptions with higher - * probability, where similar constants are used. - */ -#define KFENCE_CANARY_PATTERN(addr) ((u8)0xaa ^ (u8)((unsigned long)(addr) & 0x7)) - -/* Maximum stack depth for reports. */ -#define KFENCE_STACK_DEPTH 64 - -/* KFENCE object states. */ -enum kfence_object_state { - KFENCE_OBJECT_UNUSED, /* Object is unused. */ - KFENCE_OBJECT_ALLOCATED, /* Object is currently allocated. */ - KFENCE_OBJECT_FREED, /* Object was allocated, and then freed. */ -}; - -/* Alloc/free tracking information. */ -struct kfence_track { - pid_t pid; - int num_stack_entries; - unsigned long stack_entries[KFENCE_STACK_DEPTH]; -}; - -/* KFENCE metadata per guarded allocation. */ -struct kfence_metadata { - struct list_head list; /* Freelist node; access under kfence_freelist_lock. */ - struct rcu_head rcu_head; /* For delayed freeing. */ - - /* - * Lock protecting below data; to ensure consistency of the below data, - * since the following may execute concurrently: __kfence_alloc(), - * __kfence_free(), kfence_handle_page_fault(). However, note that we - * cannot grab the same metadata off the freelist twice, and multiple - * __kfence_alloc() cannot run concurrently on the same metadata. - */ - raw_spinlock_t lock; - - /* The current state of the object; see above. */ - enum kfence_object_state state; - - /* - * Allocated object address; cannot be calculated from size, because of - * alignment requirements. - * - * Invariant: ALIGN_DOWN(addr, PAGE_SIZE) is constant. - */ - unsigned long addr; - - /* - * The size of the original allocation. - */ - size_t size; - - /* - * The kmem_cache cache of the last allocation; NULL if never allocated - * or the cache has already been destroyed. - */ - struct kmem_cache *cache; - - /* - * In case of an invalid access, the page that was unprotected; we - * optimistically only store one address. - */ - unsigned long unprotected_page; - - /* Allocation and free stack information. */ - struct kfence_track alloc_track; - struct kfence_track free_track; -}; - -extern struct kfence_metadata kfence_metadata[CONFIG_KFENCE_NUM_OBJECTS]; - -/* KFENCE error types for report generation. */ -enum kfence_error_type { - KFENCE_ERROR_OOB, /* Detected a out-of-bounds access. */ - KFENCE_ERROR_UAF, /* Detected a use-after-free access. */ - KFENCE_ERROR_CORRUPTION, /* Detected a memory corruption on free. */ - KFENCE_ERROR_INVALID, /* Invalid access of unknown type. */ - KFENCE_ERROR_INVALID_FREE, /* Invalid free. */ -}; - -void kfence_report_error(unsigned long address, bool is_write, struct pt_regs *regs, - const struct kfence_metadata *meta, enum kfence_error_type type); - -void kfence_print_object(struct seq_file *seq, const struct kfence_metadata *meta); - -#endif /* MM_KFENCE_KFENCE_H */ diff --git a/mm/kfence/kfence_test.c b/mm/kfence/kfence_test.c deleted file mode 100644 index b959548a47ce..000000000000 --- a/mm/kfence/kfence_test.c +++ /dev/null @@ -1,847 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Test cases for KFENCE memory safety error detector. Since the interface with - * which KFENCE's reports are obtained is via the console, this is the output we - * should verify. For each test case checks the presence (or absence) of - * generated reports. Relies on 'console' tracepoint to capture reports as they - * appear in the kernel log. - * - * Copyright (C) 2020, Google LLC. - * Author: Alexander Potapenko - * Marco Elver - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "kfence.h" - -/* Report as observed from console. */ -static struct { - spinlock_t lock; - int nlines; - char lines[2][256]; -} observed = { - .lock = __SPIN_LOCK_UNLOCKED(observed.lock), -}; - -/* Probe for console output: obtains observed lines of interest. */ -static void probe_console(void *ignore, const char *buf, size_t len) -{ - unsigned long flags; - int nlines; - - spin_lock_irqsave(&observed.lock, flags); - nlines = observed.nlines; - - if (strnstr(buf, "BUG: KFENCE: ", len) && strnstr(buf, "test_", len)) { - /* - * KFENCE report and related to the test. - * - * The provided @buf is not NUL-terminated; copy no more than - * @len bytes and let strscpy() add the missing NUL-terminator. - */ - strscpy(observed.lines[0], buf, min(len + 1, sizeof(observed.lines[0]))); - nlines = 1; - } else if (nlines == 1 && (strnstr(buf, "at 0x", len) || strnstr(buf, "of 0x", len))) { - strscpy(observed.lines[nlines++], buf, min(len + 1, sizeof(observed.lines[0]))); - } - - WRITE_ONCE(observed.nlines, nlines); /* Publish new nlines. */ - spin_unlock_irqrestore(&observed.lock, flags); -} - -/* Check if a report related to the test exists. */ -static bool report_available(void) -{ - return READ_ONCE(observed.nlines) == ARRAY_SIZE(observed.lines); -} - -/* Information we expect in a report. */ -struct expect_report { - enum kfence_error_type type; /* The type or error. */ - void *fn; /* Function pointer to expected function where access occurred. */ - char *addr; /* Address at which the bad access occurred. */ - bool is_write; /* Is access a write. */ -}; - -static const char *get_access_type(const struct expect_report *r) -{ - return r->is_write ? "write" : "read"; -} - -/* Check observed report matches information in @r. */ -static bool report_matches(const struct expect_report *r) -{ - bool ret = false; - unsigned long flags; - typeof(observed.lines) expect; - const char *end; - char *cur; - - /* Doubled-checked locking. */ - if (!report_available()) - return false; - - /* Generate expected report contents. */ - - /* Title */ - cur = expect[0]; - end = &expect[0][sizeof(expect[0]) - 1]; - switch (r->type) { - case KFENCE_ERROR_OOB: - cur += scnprintf(cur, end - cur, "BUG: KFENCE: out-of-bounds %s", - get_access_type(r)); - break; - case KFENCE_ERROR_UAF: - cur += scnprintf(cur, end - cur, "BUG: KFENCE: use-after-free %s", - get_access_type(r)); - break; - case KFENCE_ERROR_CORRUPTION: - cur += scnprintf(cur, end - cur, "BUG: KFENCE: memory corruption"); - break; - case KFENCE_ERROR_INVALID: - cur += scnprintf(cur, end - cur, "BUG: KFENCE: invalid %s", - get_access_type(r)); - break; - case KFENCE_ERROR_INVALID_FREE: - cur += scnprintf(cur, end - cur, "BUG: KFENCE: invalid free"); - break; - } - - scnprintf(cur, end - cur, " in %pS", r->fn); - /* The exact offset won't match, remove it; also strip module name. */ - cur = strchr(expect[0], '+'); - if (cur) - *cur = '\0'; - - /* Access information */ - cur = expect[1]; - end = &expect[1][sizeof(expect[1]) - 1]; - - switch (r->type) { - case KFENCE_ERROR_OOB: - cur += scnprintf(cur, end - cur, "Out-of-bounds %s at", get_access_type(r)); - break; - case KFENCE_ERROR_UAF: - cur += scnprintf(cur, end - cur, "Use-after-free %s at", get_access_type(r)); - break; - case KFENCE_ERROR_CORRUPTION: - cur += scnprintf(cur, end - cur, "Corrupted memory at"); - break; - case KFENCE_ERROR_INVALID: - cur += scnprintf(cur, end - cur, "Invalid %s at", get_access_type(r)); - break; - case KFENCE_ERROR_INVALID_FREE: - cur += scnprintf(cur, end - cur, "Invalid free of"); - break; - } - - cur += scnprintf(cur, end - cur, " 0x%p", (void *)r->addr); - - spin_lock_irqsave(&observed.lock, flags); - if (!report_available()) - goto out; /* A new report is being captured. */ - - /* Finally match expected output to what we actually observed. */ - ret = strstr(observed.lines[0], expect[0]) && strstr(observed.lines[1], expect[1]); -out: - spin_unlock_irqrestore(&observed.lock, flags); - return ret; -} - -/* ===== Test cases ===== */ - -#define TEST_PRIV_WANT_MEMCACHE ((void *)1) - -/* Cache used by tests; if NULL, allocate from kmalloc instead. */ -static struct kmem_cache *test_cache; - -static size_t setup_test_cache(struct kunit *test, size_t size, slab_flags_t flags, - void (*ctor)(void *)) -{ - if (test->priv != TEST_PRIV_WANT_MEMCACHE) - return size; - - kunit_info(test, "%s: size=%zu, ctor=%ps\n", __func__, size, ctor); - - /* - * Use SLAB_NOLEAKTRACE to prevent merging with existing caches. Any - * other flag in SLAB_NEVER_MERGE also works. Use SLAB_ACCOUNT to - * allocate via memcg, if enabled. - */ - flags |= SLAB_NOLEAKTRACE | SLAB_ACCOUNT; - test_cache = kmem_cache_create("test", size, 1, flags, ctor); - KUNIT_ASSERT_TRUE_MSG(test, test_cache, "could not create cache"); - - return size; -} - -static void test_cache_destroy(void) -{ - if (!test_cache) - return; - - kmem_cache_destroy(test_cache); - test_cache = NULL; -} - -static inline size_t kmalloc_cache_alignment(size_t size) -{ - return kmalloc_caches[kmalloc_type(GFP_KERNEL)][kmalloc_index(size)]->align; -} - -/* Must always inline to match stack trace against caller. */ -static __always_inline void test_free(void *ptr) -{ - if (test_cache) - kmem_cache_free(test_cache, ptr); - else - kfree(ptr); -} - -/* - * If this should be a KFENCE allocation, and on which side the allocation and - * the closest guard page should be. - */ -enum allocation_policy { - ALLOCATE_ANY, /* KFENCE, any side. */ - ALLOCATE_LEFT, /* KFENCE, left side of page. */ - ALLOCATE_RIGHT, /* KFENCE, right side of page. */ - ALLOCATE_NONE, /* No KFENCE allocation. */ -}; - -/* - * Try to get a guarded allocation from KFENCE. Uses either kmalloc() or the - * current test_cache if set up. - */ -static void *test_alloc(struct kunit *test, size_t size, gfp_t gfp, enum allocation_policy policy) -{ - void *alloc; - unsigned long timeout, resched_after; - const char *policy_name; - - switch (policy) { - case ALLOCATE_ANY: - policy_name = "any"; - break; - case ALLOCATE_LEFT: - policy_name = "left"; - break; - case ALLOCATE_RIGHT: - policy_name = "right"; - break; - case ALLOCATE_NONE: - policy_name = "none"; - break; - } - - kunit_info(test, "%s: size=%zu, gfp=%x, policy=%s, cache=%i\n", __func__, size, gfp, - policy_name, !!test_cache); - - /* - * 100x the sample interval should be more than enough to ensure we get - * a KFENCE allocation eventually. - */ - timeout = jiffies + msecs_to_jiffies(100 * CONFIG_KFENCE_SAMPLE_INTERVAL); - /* - * Especially for non-preemption kernels, ensure the allocation-gate - * timer can catch up: after @resched_after, every failed allocation - * attempt yields, to ensure the allocation-gate timer is scheduled. - */ - resched_after = jiffies + msecs_to_jiffies(CONFIG_KFENCE_SAMPLE_INTERVAL); - do { - if (test_cache) - alloc = kmem_cache_alloc(test_cache, gfp); - else - alloc = kmalloc(size, gfp); - - if (is_kfence_address(alloc)) { - if (policy == ALLOCATE_ANY) - return alloc; - if (policy == ALLOCATE_LEFT && IS_ALIGNED((unsigned long)alloc, PAGE_SIZE)) - return alloc; - if (policy == ALLOCATE_RIGHT && - !IS_ALIGNED((unsigned long)alloc, PAGE_SIZE)) - return alloc; - } else if (policy == ALLOCATE_NONE) - return alloc; - - test_free(alloc); - - if (time_after(jiffies, resched_after)) - cond_resched(); - } while (time_before(jiffies, timeout)); - - KUNIT_ASSERT_TRUE_MSG(test, false, "failed to allocate from KFENCE"); - return NULL; /* Unreachable. */ -} - -static void test_out_of_bounds_read(struct kunit *test) -{ - size_t size = 32; - struct expect_report expect = { - .type = KFENCE_ERROR_OOB, - .fn = test_out_of_bounds_read, - .is_write = false, - }; - char *buf; - - setup_test_cache(test, size, 0, NULL); - - /* - * If we don't have our own cache, adjust based on alignment, so that we - * actually access guard pages on either side. - */ - if (!test_cache) - size = kmalloc_cache_alignment(size); - - /* Test both sides. */ - - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_LEFT); - expect.addr = buf - 1; - READ_ONCE(*expect.addr); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); - test_free(buf); - - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_RIGHT); - expect.addr = buf + size; - READ_ONCE(*expect.addr); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); - test_free(buf); -} - -static void test_out_of_bounds_write(struct kunit *test) -{ - size_t size = 32; - struct expect_report expect = { - .type = KFENCE_ERROR_OOB, - .fn = test_out_of_bounds_write, - .is_write = true, - }; - char *buf; - - setup_test_cache(test, size, 0, NULL); - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_LEFT); - expect.addr = buf - 1; - WRITE_ONCE(*expect.addr, 42); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); - test_free(buf); -} - -static void test_use_after_free_read(struct kunit *test) -{ - const size_t size = 32; - struct expect_report expect = { - .type = KFENCE_ERROR_UAF, - .fn = test_use_after_free_read, - .is_write = false, - }; - - setup_test_cache(test, size, 0, NULL); - expect.addr = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY); - test_free(expect.addr); - READ_ONCE(*expect.addr); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); -} - -static void test_double_free(struct kunit *test) -{ - const size_t size = 32; - struct expect_report expect = { - .type = KFENCE_ERROR_INVALID_FREE, - .fn = test_double_free, - }; - - setup_test_cache(test, size, 0, NULL); - expect.addr = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY); - test_free(expect.addr); - test_free(expect.addr); /* Double-free. */ - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); -} - -static void test_invalid_addr_free(struct kunit *test) -{ - const size_t size = 32; - struct expect_report expect = { - .type = KFENCE_ERROR_INVALID_FREE, - .fn = test_invalid_addr_free, - }; - char *buf; - - setup_test_cache(test, size, 0, NULL); - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY); - expect.addr = buf + 1; /* Free on invalid address. */ - test_free(expect.addr); /* Invalid address free. */ - test_free(buf); /* No error. */ - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); -} - -static void test_corruption(struct kunit *test) -{ - size_t size = 32; - struct expect_report expect = { - .type = KFENCE_ERROR_CORRUPTION, - .fn = test_corruption, - }; - char *buf; - - setup_test_cache(test, size, 0, NULL); - - /* Test both sides. */ - - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_LEFT); - expect.addr = buf + size; - WRITE_ONCE(*expect.addr, 42); - test_free(buf); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); - - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_RIGHT); - expect.addr = buf - 1; - WRITE_ONCE(*expect.addr, 42); - test_free(buf); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); -} - -/* - * KFENCE is unable to detect an OOB if the allocation's alignment requirements - * leave a gap between the object and the guard page. Specifically, an - * allocation of e.g. 73 bytes is aligned on 8 and 128 bytes for SLUB or SLAB - * respectively. Therefore it is impossible for the allocated object to - * contiguously line up with the right guard page. - * - * However, we test that an access to memory beyond the gap results in KFENCE - * detecting an OOB access. - */ -static void test_kmalloc_aligned_oob_read(struct kunit *test) -{ - const size_t size = 73; - const size_t align = kmalloc_cache_alignment(size); - struct expect_report expect = { - .type = KFENCE_ERROR_OOB, - .fn = test_kmalloc_aligned_oob_read, - .is_write = false, - }; - char *buf; - - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_RIGHT); - - /* - * The object is offset to the right, so there won't be an OOB to the - * left of it. - */ - READ_ONCE(*(buf - 1)); - KUNIT_EXPECT_FALSE(test, report_available()); - - /* - * @buf must be aligned on @align, therefore buf + size belongs to the - * same page -> no OOB. - */ - READ_ONCE(*(buf + size)); - KUNIT_EXPECT_FALSE(test, report_available()); - - /* Overflowing by @align bytes will result in an OOB. */ - expect.addr = buf + size + align; - READ_ONCE(*expect.addr); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); - - test_free(buf); -} - -static void test_kmalloc_aligned_oob_write(struct kunit *test) -{ - const size_t size = 73; - struct expect_report expect = { - .type = KFENCE_ERROR_CORRUPTION, - .fn = test_kmalloc_aligned_oob_write, - }; - char *buf; - - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_RIGHT); - /* - * The object is offset to the right, so we won't get a page - * fault immediately after it. - */ - expect.addr = buf + size; - WRITE_ONCE(*expect.addr, READ_ONCE(*expect.addr) + 1); - KUNIT_EXPECT_FALSE(test, report_available()); - test_free(buf); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); -} - -/* Test cache shrinking and destroying with KFENCE. */ -static void test_shrink_memcache(struct kunit *test) -{ - const size_t size = 32; - void *buf; - - setup_test_cache(test, size, 0, NULL); - KUNIT_EXPECT_TRUE(test, test_cache); - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY); - kmem_cache_shrink(test_cache); - test_free(buf); - - KUNIT_EXPECT_FALSE(test, report_available()); -} - -static void ctor_set_x(void *obj) -{ - /* Every object has at least 8 bytes. */ - memset(obj, 'x', 8); -} - -/* Ensure that SL*B does not modify KFENCE objects on bulk free. */ -static void test_free_bulk(struct kunit *test) -{ - int iter; - - for (iter = 0; iter < 5; iter++) { - const size_t size = setup_test_cache(test, 8 + prandom_u32_max(300), 0, - (iter & 1) ? ctor_set_x : NULL); - void *objects[] = { - test_alloc(test, size, GFP_KERNEL, ALLOCATE_RIGHT), - test_alloc(test, size, GFP_KERNEL, ALLOCATE_NONE), - test_alloc(test, size, GFP_KERNEL, ALLOCATE_LEFT), - test_alloc(test, size, GFP_KERNEL, ALLOCATE_NONE), - test_alloc(test, size, GFP_KERNEL, ALLOCATE_NONE), - }; - - kmem_cache_free_bulk(test_cache, ARRAY_SIZE(objects), objects); - KUNIT_ASSERT_FALSE(test, report_available()); - test_cache_destroy(); - } -} - -/* Test init-on-free works. */ -static void test_init_on_free(struct kunit *test) -{ - const size_t size = 32; - struct expect_report expect = { - .type = KFENCE_ERROR_UAF, - .fn = test_init_on_free, - .is_write = false, - }; - int i; - - if (!IS_ENABLED(CONFIG_INIT_ON_FREE_DEFAULT_ON)) - return; - /* Assume it hasn't been disabled on command line. */ - - setup_test_cache(test, size, 0, NULL); - expect.addr = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY); - for (i = 0; i < size; i++) - expect.addr[i] = i + 1; - test_free(expect.addr); - - for (i = 0; i < size; i++) { - /* - * This may fail if the page was recycled by KFENCE and then - * written to again -- this however, is near impossible with a - * default config. - */ - KUNIT_EXPECT_EQ(test, expect.addr[i], (char)0); - - if (!i) /* Only check first access to not fail test if page is ever re-protected. */ - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); - } -} - -/* Ensure that constructors work properly. */ -static void test_memcache_ctor(struct kunit *test) -{ - const size_t size = 32; - char *buf; - int i; - - setup_test_cache(test, size, 0, ctor_set_x); - buf = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY); - - for (i = 0; i < 8; i++) - KUNIT_EXPECT_EQ(test, buf[i], (char)'x'); - - test_free(buf); - - KUNIT_EXPECT_FALSE(test, report_available()); -} - -/* Test that memory is zeroed if requested. */ -static void test_gfpzero(struct kunit *test) -{ - const size_t size = PAGE_SIZE; /* PAGE_SIZE so we can use ALLOCATE_ANY. */ - char *buf1, *buf2; - int i; - - if (CONFIG_KFENCE_SAMPLE_INTERVAL > 100) { - kunit_warn(test, "skipping ... would take too long\n"); - return; - } - - setup_test_cache(test, size, 0, NULL); - buf1 = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY); - for (i = 0; i < size; i++) - buf1[i] = i + 1; - test_free(buf1); - - /* Try to get same address again -- this can take a while. */ - for (i = 0;; i++) { - buf2 = test_alloc(test, size, GFP_KERNEL | __GFP_ZERO, ALLOCATE_ANY); - if (buf1 == buf2) - break; - test_free(buf2); - - if (i == CONFIG_KFENCE_NUM_OBJECTS) { - kunit_warn(test, "giving up ... cannot get same object back\n"); - return; - } - } - - for (i = 0; i < size; i++) - KUNIT_EXPECT_EQ(test, buf2[i], (char)0); - - test_free(buf2); - - KUNIT_EXPECT_FALSE(test, report_available()); -} - -static void test_invalid_access(struct kunit *test) -{ - const struct expect_report expect = { - .type = KFENCE_ERROR_INVALID, - .fn = test_invalid_access, - .addr = &__kfence_pool[10], - .is_write = false, - }; - - READ_ONCE(__kfence_pool[10]); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); -} - -/* Test SLAB_TYPESAFE_BY_RCU works. */ -static void test_memcache_typesafe_by_rcu(struct kunit *test) -{ - const size_t size = 32; - struct expect_report expect = { - .type = KFENCE_ERROR_UAF, - .fn = test_memcache_typesafe_by_rcu, - .is_write = false, - }; - - setup_test_cache(test, size, SLAB_TYPESAFE_BY_RCU, NULL); - KUNIT_EXPECT_TRUE(test, test_cache); /* Want memcache. */ - - expect.addr = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY); - *expect.addr = 42; - - rcu_read_lock(); - test_free(expect.addr); - KUNIT_EXPECT_EQ(test, *expect.addr, (char)42); - /* - * Up to this point, memory should not have been freed yet, and - * therefore there should be no KFENCE report from the above access. - */ - rcu_read_unlock(); - - /* Above access to @expect.addr should not have generated a report! */ - KUNIT_EXPECT_FALSE(test, report_available()); - - /* Only after rcu_barrier() is the memory guaranteed to be freed. */ - rcu_barrier(); - - /* Expect use-after-free. */ - KUNIT_EXPECT_EQ(test, *expect.addr, (char)42); - KUNIT_EXPECT_TRUE(test, report_matches(&expect)); -} - -/* Test krealloc(). */ -static void test_krealloc(struct kunit *test) -{ - const size_t size = 32; - const struct expect_report expect = { - .type = KFENCE_ERROR_UAF, - .fn = test_krealloc, - .addr = test_alloc(test, size, GFP_KERNEL, ALLOCATE_ANY), - .is_write = false, - }; - char *buf = expect.addr; - int i; - - KUNIT_EXPECT_FALSE(test, test_cache); - KUNIT_EXPECT_EQ(test, ksize(buf), size); /* Precise size match after KFENCE alloc. */ - for (i = 0; i < size; i++) - buf[i] = i + 1; - - /* Check that we successfully change the size. */ - buf = krealloc(buf, size * 3, GFP_KERNEL); /* Grow. */ - /* Note: Might no longer be a KFENCE alloc. */ - KUNIT_EXPECT_GE(test, ksize(buf), size * 3); - for (i = 0; i < size; i++) - KUNIT_EXPECT_EQ(test, buf[i], (char)(i + 1)); - for (; i < size * 3; i++) /* Fill to extra bytes. */ - buf[i] = i + 1; - - buf = krealloc(buf, size * 2, GFP_KERNEL); /* Shrink. */ - KUNIT_EXPECT_GE(test, ksize(buf), size * 2); - for (i = 0; i < size * 2; i++) - KUNIT_EXPECT_EQ(test, buf[i], (char)(i + 1)); - - buf = krealloc(buf, 0, GFP_KERNEL); /* Free. */ - KUNIT_EXPECT_EQ(test, (unsigned long)buf, (unsigned long)ZERO_SIZE_PTR); - KUNIT_ASSERT_FALSE(test, report_available()); /* No reports yet! */ - - READ_ONCE(*expect.addr); /* Ensure krealloc() actually freed earlier KFENCE object. */ - KUNIT_ASSERT_TRUE(test, report_matches(&expect)); -} - -/* Test that some objects from a bulk allocation belong to KFENCE pool. */ -static void test_memcache_alloc_bulk(struct kunit *test) -{ - const size_t size = 32; - bool pass = false; - unsigned long timeout; - - setup_test_cache(test, size, 0, NULL); - KUNIT_EXPECT_TRUE(test, test_cache); /* Want memcache. */ - /* - * 100x the sample interval should be more than enough to ensure we get - * a KFENCE allocation eventually. - */ - timeout = jiffies + msecs_to_jiffies(100 * CONFIG_KFENCE_SAMPLE_INTERVAL); - do { - void *objects[100]; - int i, num = kmem_cache_alloc_bulk(test_cache, GFP_ATOMIC, ARRAY_SIZE(objects), - objects); - if (!num) - continue; - for (i = 0; i < ARRAY_SIZE(objects); i++) { - if (is_kfence_address(objects[i])) { - pass = true; - break; - } - } - kmem_cache_free_bulk(test_cache, num, objects); - /* - * kmem_cache_alloc_bulk() disables interrupts, and calling it - * in a tight loop may not give KFENCE a chance to switch the - * static branch. Call cond_resched() to let KFENCE chime in. - */ - cond_resched(); - } while (!pass && time_before(jiffies, timeout)); - - KUNIT_EXPECT_TRUE(test, pass); - KUNIT_EXPECT_FALSE(test, report_available()); -} - -/* - * KUnit does not provide a way to provide arguments to tests, and we encode - * additional info in the name. Set up 2 tests per test case, one using the - * default allocator, and another using a custom memcache (suffix '-memcache'). - */ -#define KFENCE_KUNIT_CASE(test_name) \ - { .run_case = test_name, .name = #test_name }, \ - { .run_case = test_name, .name = #test_name "-memcache" } - -static struct kunit_case kfence_test_cases[] = { - KFENCE_KUNIT_CASE(test_out_of_bounds_read), - KFENCE_KUNIT_CASE(test_out_of_bounds_write), - KFENCE_KUNIT_CASE(test_use_after_free_read), - KFENCE_KUNIT_CASE(test_double_free), - KFENCE_KUNIT_CASE(test_invalid_addr_free), - KFENCE_KUNIT_CASE(test_corruption), - KFENCE_KUNIT_CASE(test_free_bulk), - KFENCE_KUNIT_CASE(test_init_on_free), - KUNIT_CASE(test_kmalloc_aligned_oob_read), - KUNIT_CASE(test_kmalloc_aligned_oob_write), - KUNIT_CASE(test_shrink_memcache), - KUNIT_CASE(test_memcache_ctor), - KUNIT_CASE(test_invalid_access), - KUNIT_CASE(test_gfpzero), - KUNIT_CASE(test_memcache_typesafe_by_rcu), - KUNIT_CASE(test_krealloc), - KUNIT_CASE(test_memcache_alloc_bulk), - {}, -}; - -/* ===== End test cases ===== */ - -static int test_init(struct kunit *test) -{ - unsigned long flags; - int i; - - spin_lock_irqsave(&observed.lock, flags); - for (i = 0; i < ARRAY_SIZE(observed.lines); i++) - observed.lines[i][0] = '\0'; - observed.nlines = 0; - spin_unlock_irqrestore(&observed.lock, flags); - - /* Any test with 'memcache' in its name will want a memcache. */ - if (strstr(test->name, "memcache")) - test->priv = TEST_PRIV_WANT_MEMCACHE; - else - test->priv = NULL; - - return 0; -} - -static void test_exit(struct kunit *test) -{ - test_cache_destroy(); -} - -static struct kunit_suite kfence_test_suite = { - .name = "kfence", - .test_cases = kfence_test_cases, - .init = test_init, - .exit = test_exit, -}; -static struct kunit_suite *kfence_test_suites[] = { &kfence_test_suite, NULL }; - -static void register_tracepoints(struct tracepoint *tp, void *ignore) -{ - check_trace_callback_type_console(probe_console); - if (!strcmp(tp->name, "console")) - WARN_ON(tracepoint_probe_register(tp, probe_console, NULL)); -} - -static void unregister_tracepoints(struct tracepoint *tp, void *ignore) -{ - if (!strcmp(tp->name, "console")) - tracepoint_probe_unregister(tp, probe_console, NULL); -} - -/* - * We only want to do tracepoints setup and teardown once, therefore we have to - * customize the init and exit functions and cannot rely on kunit_test_suite(). - */ -static int __init kfence_test_init(void) -{ - /* - * Because we want to be able to build the test as a module, we need to - * iterate through all known tracepoints, since the static registration - * won't work here. - */ - for_each_kernel_tracepoint(register_tracepoints, NULL); - return __kunit_test_suites_init(kfence_test_suites); -} - -static void kfence_test_exit(void) -{ - __kunit_test_suites_exit(kfence_test_suites); - for_each_kernel_tracepoint(unregister_tracepoints, NULL); - tracepoint_synchronize_unregister(); -} - -late_initcall(kfence_test_init); -module_exit(kfence_test_exit); - -MODULE_LICENSE("GPL v2"); -MODULE_AUTHOR("Alexander Potapenko , Marco Elver "); diff --git a/mm/kfence/report.c b/mm/kfence/report.c deleted file mode 100644 index e3f71451ad9e..000000000000 --- a/mm/kfence/report.c +++ /dev/null @@ -1,268 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * KFENCE reporting. - * - * Copyright (C) 2020, Google LLC. - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "kfence.h" - -/* May be overridden by . */ -#ifndef ARCH_FUNC_PREFIX -#define ARCH_FUNC_PREFIX "" -#endif - -extern bool no_hash_pointers; - -/* Helper function to either print to a seq_file or to console. */ -__printf(2, 3) -static void seq_con_printf(struct seq_file *seq, const char *fmt, ...) -{ - va_list args; - - va_start(args, fmt); - if (seq) - seq_vprintf(seq, fmt, args); - else - vprintk(fmt, args); - va_end(args); -} - -/* - * Get the number of stack entries to skip to get out of MM internals. @type is - * optional, and if set to NULL, assumes an allocation or free stack. - */ -static int get_stack_skipnr(const unsigned long stack_entries[], int num_entries, - const enum kfence_error_type *type) -{ - char buf[64]; - int skipnr, fallback = 0; - - if (type) { - /* Depending on error type, find different stack entries. */ - switch (*type) { - case KFENCE_ERROR_UAF: - case KFENCE_ERROR_OOB: - case KFENCE_ERROR_INVALID: - /* - * kfence_handle_page_fault() may be called with pt_regs - * set to NULL; in that case we'll simply show the full - * stack trace. - */ - return 0; - case KFENCE_ERROR_CORRUPTION: - case KFENCE_ERROR_INVALID_FREE: - break; - } - } - - for (skipnr = 0; skipnr < num_entries; skipnr++) { - int len = scnprintf(buf, sizeof(buf), "%ps", (void *)stack_entries[skipnr]); - - if (str_has_prefix(buf, ARCH_FUNC_PREFIX "kfence_") || - str_has_prefix(buf, ARCH_FUNC_PREFIX "__kfence_") || - !strncmp(buf, ARCH_FUNC_PREFIX "__slab_free", len)) { - /* - * In case of tail calls from any of the below - * to any of the above. - */ - fallback = skipnr + 1; - } - - /* Also the *_bulk() variants by only checking prefixes. */ - if (str_has_prefix(buf, ARCH_FUNC_PREFIX "kfree") || - str_has_prefix(buf, ARCH_FUNC_PREFIX "kmem_cache_free") || - str_has_prefix(buf, ARCH_FUNC_PREFIX "__kmalloc") || - str_has_prefix(buf, ARCH_FUNC_PREFIX "kmem_cache_alloc")) - goto found; - } - if (fallback < num_entries) - return fallback; -found: - skipnr++; - return skipnr < num_entries ? skipnr : 0; -} - -static void kfence_print_stack(struct seq_file *seq, const struct kfence_metadata *meta, - bool show_alloc) -{ - const struct kfence_track *track = show_alloc ? &meta->alloc_track : &meta->free_track; - - if (track->num_stack_entries) { - /* Skip allocation/free internals stack. */ - int i = get_stack_skipnr(track->stack_entries, track->num_stack_entries, NULL); - - /* stack_trace_seq_print() does not exist; open code our own. */ - for (; i < track->num_stack_entries; i++) - seq_con_printf(seq, " %pS\n", (void *)track->stack_entries[i]); - } else { - seq_con_printf(seq, " no %s stack\n", show_alloc ? "allocation" : "deallocation"); - } -} - -void kfence_print_object(struct seq_file *seq, const struct kfence_metadata *meta) -{ - const int size = abs(meta->size); - const unsigned long start = meta->addr; - const struct kmem_cache *const cache = meta->cache; - - lockdep_assert_held(&meta->lock); - - if (meta->state == KFENCE_OBJECT_UNUSED) { - seq_con_printf(seq, "kfence-#%td unused\n", meta - kfence_metadata); - return; - } - - seq_con_printf(seq, - "kfence-#%td [0x%p-0x%p" - ", size=%d, cache=%s] allocated by task %d:\n", - meta - kfence_metadata, (void *)start, (void *)(start + size - 1), size, - (cache && cache->name) ? cache->name : "", meta->alloc_track.pid); - kfence_print_stack(seq, meta, true); - - if (meta->state == KFENCE_OBJECT_FREED) { - seq_con_printf(seq, "\nfreed by task %d:\n", meta->free_track.pid); - kfence_print_stack(seq, meta, false); - } -} - -/* - * Show bytes at @addr that are different from the expected canary values, up to - * @max_bytes. - */ -static void print_diff_canary(unsigned long address, size_t bytes_to_show, - const struct kfence_metadata *meta) -{ - const unsigned long show_until_addr = address + bytes_to_show; - const u8 *cur, *end; - - /* Do not show contents of object nor read into following guard page. */ - end = (const u8 *)(address < meta->addr ? min(show_until_addr, meta->addr) - : min(show_until_addr, PAGE_ALIGN(address))); - - pr_cont("["); - for (cur = (const u8 *)address; cur < end; cur++) { - if (*cur == KFENCE_CANARY_PATTERN(cur)) - pr_cont(" ."); - else if (no_hash_pointers) - pr_cont(" 0x%02x", *cur); - else /* Do not leak kernel memory in non-debug builds. */ - pr_cont(" !"); - } - pr_cont(" ]"); -} - -static const char *get_access_type(bool is_write) -{ - return is_write ? "write" : "read"; -} - -void kfence_report_error(unsigned long address, bool is_write, struct pt_regs *regs, - const struct kfence_metadata *meta, enum kfence_error_type type) -{ - unsigned long stack_entries[KFENCE_STACK_DEPTH] = { 0 }; - const ptrdiff_t object_index = meta ? meta - kfence_metadata : -1; - int num_stack_entries; - int skipnr = 0; - - if (regs) { - num_stack_entries = stack_trace_save_regs(regs, stack_entries, KFENCE_STACK_DEPTH, 0); - } else { - num_stack_entries = stack_trace_save(stack_entries, KFENCE_STACK_DEPTH, 1); - skipnr = get_stack_skipnr(stack_entries, num_stack_entries, &type); - } - - /* Require non-NULL meta, except if KFENCE_ERROR_INVALID. */ - if (WARN_ON(type != KFENCE_ERROR_INVALID && !meta)) - return; - - if (meta) - lockdep_assert_held(&meta->lock); - /* - * Because we may generate reports in printk-unfriendly parts of the - * kernel, such as scheduler code, the use of printk() could deadlock. - * Until such time that all printing code here is safe in all parts of - * the kernel, accept the risk, and just get our message out (given the - * system might already behave unpredictably due to the memory error). - * As such, also disable lockdep to hide warnings, and avoid disabling - * lockdep for the rest of the kernel. - */ - lockdep_off(); - - pr_err("==================================================================\n"); - /* Print report header. */ - switch (type) { - case KFENCE_ERROR_OOB: { - const bool left_of_object = address < meta->addr; - - pr_err("BUG: KFENCE: out-of-bounds %s in %pS\n\n", get_access_type(is_write), - (void *)stack_entries[skipnr]); - pr_err("Out-of-bounds %s at 0x%p (%luB %s of kfence-#%td):\n", - get_access_type(is_write), (void *)address, - left_of_object ? meta->addr - address : address - meta->addr, - left_of_object ? "left" : "right", object_index); - break; - } - case KFENCE_ERROR_UAF: - pr_err("BUG: KFENCE: use-after-free %s in %pS\n\n", get_access_type(is_write), - (void *)stack_entries[skipnr]); - pr_err("Use-after-free %s at 0x%p (in kfence-#%td):\n", - get_access_type(is_write), (void *)address, object_index); - break; - case KFENCE_ERROR_CORRUPTION: - pr_err("BUG: KFENCE: memory corruption in %pS\n\n", (void *)stack_entries[skipnr]); - pr_err("Corrupted memory at 0x%p ", (void *)address); - print_diff_canary(address, 16, meta); - pr_cont(" (in kfence-#%td):\n", object_index); - break; - case KFENCE_ERROR_INVALID: - pr_err("BUG: KFENCE: invalid %s in %pS\n\n", get_access_type(is_write), - (void *)stack_entries[skipnr]); - pr_err("Invalid %s at 0x%p:\n", get_access_type(is_write), - (void *)address); - break; - case KFENCE_ERROR_INVALID_FREE: - pr_err("BUG: KFENCE: invalid free in %pS\n\n", (void *)stack_entries[skipnr]); - pr_err("Invalid free of 0x%p (in kfence-#%td):\n", (void *)address, - object_index); - break; - } - - /* Print stack trace and object info. */ - stack_trace_print(stack_entries + skipnr, num_stack_entries - skipnr, 0); - - if (meta) { - pr_err("\n"); - kfence_print_object(NULL, meta); - } - - /* Print report footer. */ - pr_err("\n"); - if (no_hash_pointers && regs) - show_regs(regs); - else - dump_stack_print_info(KERN_ERR); - trace_error_report_end(ERROR_DETECTOR_KFENCE, address); - pr_err("==================================================================\n"); - - lockdep_on(); - - if (panic_on_warn) - panic("panic_on_warn set ...\n"); - - /* We encountered a memory unsafety error, taint the kernel! */ - add_taint(TAINT_BAD_PAGE, LOCKDEP_STILL_OK); -} diff --git a/mm/kmemleak.c b/mm/kmemleak.c index dce9e2a42549..a7fc6b23c37e 100644 --- a/mm/kmemleak.c +++ b/mm/kmemleak.c @@ -97,7 +97,6 @@ #include #include -#include #include #include @@ -593,7 +592,7 @@ static struct kmemleak_object *create_object(unsigned long ptr, size_t size, atomic_set(&object->use_count, 1); object->flags = OBJECT_ALLOCATED; object->pointer = ptr; - object->size = kfence_ksize((void *)ptr) ?: size; + object->size = size; object->excess_ref = 0; object->min_count = min_count; object->count = 0; /* white color initially */ diff --git a/mm/maccess.c b/mm/maccess.c index d3edb61528c3..2d3c3d01064c 100644 --- a/mm/maccess.c +++ b/mm/maccess.c @@ -6,125 +6,63 @@ #include #include -bool __weak copy_from_kernel_nofault_allowed(const void *unsafe_src, - size_t size) +static __always_inline long +probe_read_common(void *dst, const void __user *src, size_t size) { - return true; -} - -#ifdef HAVE_GET_KERNEL_NOFAULT - -#define copy_from_kernel_nofault_loop(dst, src, len, type, err_label) \ - while (len >= sizeof(type)) { \ - __get_kernel_nofault(dst, src, type, err_label); \ - dst += sizeof(type); \ - src += sizeof(type); \ - len -= sizeof(type); \ - } - -long copy_from_kernel_nofault(void *dst, const void *src, size_t size) -{ - if (!copy_from_kernel_nofault_allowed(src, size)) - return -ERANGE; + long ret; pagefault_disable(); - copy_from_kernel_nofault_loop(dst, src, size, u64, Efault); - copy_from_kernel_nofault_loop(dst, src, size, u32, Efault); - copy_from_kernel_nofault_loop(dst, src, size, u16, Efault); - copy_from_kernel_nofault_loop(dst, src, size, u8, Efault); + ret = __copy_from_user_inatomic(dst, src, size); pagefault_enable(); - return 0; -Efault: - pagefault_enable(); - return -EFAULT; -} -EXPORT_SYMBOL_GPL(copy_from_kernel_nofault); -#define copy_to_kernel_nofault_loop(dst, src, len, type, err_label) \ - while (len >= sizeof(type)) { \ - __put_kernel_nofault(dst, src, type, err_label); \ - dst += sizeof(type); \ - src += sizeof(type); \ - len -= sizeof(type); \ - } - -long copy_to_kernel_nofault(void *dst, const void *src, size_t size) -{ - pagefault_disable(); - copy_to_kernel_nofault_loop(dst, src, size, u64, Efault); - copy_to_kernel_nofault_loop(dst, src, size, u32, Efault); - copy_to_kernel_nofault_loop(dst, src, size, u16, Efault); - copy_to_kernel_nofault_loop(dst, src, size, u8, Efault); - pagefault_enable(); - return 0; -Efault: - pagefault_enable(); - return -EFAULT; + return ret ? -EFAULT : 0; } -long strncpy_from_kernel_nofault(char *dst, const void *unsafe_addr, long count) +static __always_inline long +probe_write_common(void __user *dst, const void *src, size_t size) { - const void *src = unsafe_addr; - - if (unlikely(count <= 0)) - return 0; - if (!copy_from_kernel_nofault_allowed(unsafe_addr, count)) - return -ERANGE; + long ret; pagefault_disable(); - do { - __get_kernel_nofault(dst, src, u8, Efault); - dst++; - src++; - } while (dst[-1] && src - unsafe_addr < count); + ret = __copy_to_user_inatomic(dst, src, size); pagefault_enable(); - dst[-1] = '\0'; - return src - unsafe_addr; -Efault: - pagefault_enable(); - dst[-1] = '\0'; - return -EFAULT; + return ret ? -EFAULT : 0; } -#else /* HAVE_GET_KERNEL_NOFAULT */ + /** - * copy_from_kernel_nofault(): safely attempt to read from kernel-space + * probe_kernel_read(): safely attempt to read from a kernel-space location * @dst: pointer to the buffer that shall take the data * @src: address to read from * @size: size of the data chunk * - * Safely read from kernel address @src to the buffer at @dst. If a kernel - * fault happens, handle that and return -EFAULT. If @src is not a valid kernel - * address, return -ERANGE. + * Safely read from address @src to the buffer at @dst. If a kernel fault + * happens, handle that and return -EFAULT. * * We ensure that the copy_from_user is executed in atomic context so that * do_page_fault() doesn't attempt to take mmap_sem. This makes - * copy_from_kernel_nofault() suitable for use within regions where the caller + * probe_kernel_read() suitable for use within regions where the caller * already holds mmap_sem, or other locks which nest inside mmap_sem. */ -long copy_from_kernel_nofault(void *dst, const void *src, size_t size) + +long __weak probe_kernel_read(void *dst, const void *src, size_t size) + __attribute__((alias("__probe_kernel_read"))); + +long __probe_kernel_read(void *dst, const void *src, size_t size) { long ret; mm_segment_t old_fs = get_fs(); - if (!copy_from_kernel_nofault_allowed(src, size)) - return -ERANGE; - set_fs(KERNEL_DS); - pagefault_disable(); - ret = __copy_from_user_inatomic(dst, (__force const void __user *)src, - size); - pagefault_enable(); + ret = probe_read_common(dst, (__force const void __user *)src, size); set_fs(old_fs); - if (ret) - return -EFAULT; - return 0; + return ret; } -EXPORT_SYMBOL_GPL(copy_from_kernel_nofault); +EXPORT_SYMBOL_GPL(probe_kernel_read); /** - * copy_from_user_nofault(): safely attempt to read from a user-space location + * probe_user_read(): safely attempt to read from a user-space location * @dst: pointer to the buffer that shall take the data * @src: address to read from. This must be a user address. * @size: size of the data chunk @@ -132,24 +70,23 @@ EXPORT_SYMBOL_GPL(copy_from_kernel_nofault); * Safely read from user address @src to the buffer at @dst. If a kernel fault * happens, handle that and return -EFAULT. */ -long copy_from_user_nofault(void *dst, const void __user *src, size_t size) + +long __weak probe_user_read(void *dst, const void __user *src, size_t size) + __attribute__((alias("__probe_user_read"))); + +long __probe_user_read(void *dst, const void __user *src, size_t size) { long ret = -EFAULT; mm_segment_t old_fs = get_fs(); set_fs(USER_DS); - if (access_ok(src, size)) { - pagefault_disable(); - ret = __copy_from_user_inatomic(dst, src, size); - pagefault_enable(); - } + if (access_ok(src, size)) + ret = probe_read_common(dst, src, size); set_fs(old_fs); - if (ret) - return -EFAULT; - return 0; + return ret; } -EXPORT_SYMBOL_GPL(copy_from_user_nofault); +EXPORT_SYMBOL_GPL(probe_user_read); /** * probe_kernel_write(): safely attempt to write to a location @@ -160,24 +97,25 @@ EXPORT_SYMBOL_GPL(copy_from_user_nofault); * Safely write to address @dst from the buffer at @src. If a kernel fault * happens, handle that and return -EFAULT. */ -long copy_to_kernel_nofault(void *dst, const void *src, size_t size) + +long __weak probe_kernel_write(void *dst, const void *src, size_t size) + __attribute__((alias("__probe_kernel_write"))); + +long __probe_kernel_write(void *dst, const void *src, size_t size) { long ret; mm_segment_t old_fs = get_fs(); set_fs(KERNEL_DS); - pagefault_disable(); - ret = __copy_to_user_inatomic((__force void __user *)dst, src, size); - pagefault_enable(); + ret = probe_write_common((__force void __user *)dst, src, size); set_fs(old_fs); - if (ret) - return -EFAULT; - return 0; + return ret; } +EXPORT_SYMBOL_GPL(probe_kernel_write); /** - * copy_to_user_nofault(): safely attempt to write to a user-space location + * probe_user_write(): safely attempt to write to a user-space location * @dst: address to write to * @src: pointer to the data that shall be written * @size: size of the data chunk @@ -185,28 +123,26 @@ long copy_to_kernel_nofault(void *dst, const void *src, size_t size) * Safely write to address @dst from the buffer at @src. If a kernel fault * happens, handle that and return -EFAULT. */ -long copy_to_user_nofault(void __user *dst, const void *src, size_t size) + +long __weak probe_user_write(void __user *dst, const void *src, size_t size) + __attribute__((alias("__probe_user_write"))); + +long __probe_user_write(void __user *dst, const void *src, size_t size) { long ret = -EFAULT; mm_segment_t old_fs = get_fs(); set_fs(USER_DS); - if (access_ok(dst, size)) { - pagefault_disable(); - ret = __copy_to_user_inatomic(dst, src, size); - pagefault_enable(); - } + if (access_ok(dst, size)) + ret = probe_write_common(dst, src, size); set_fs(old_fs); - if (ret) - return -EFAULT; - return 0; + return ret; } -EXPORT_SYMBOL_GPL(copy_to_user_nofault); +EXPORT_SYMBOL_GPL(probe_user_write); /** - * strncpy_from_kernel_nofault: - Copy a NUL terminated string from unsafe - * address. + * strncpy_from_unsafe: - Copy a NUL terminated string from unsafe address. * @dst: Destination address, in kernel space. This buffer must be at * least @count bytes long. * @unsafe_addr: Unsafe address. @@ -216,14 +152,13 @@ EXPORT_SYMBOL_GPL(copy_to_user_nofault); * * On success, returns the length of the string INCLUDING the trailing NUL. * - * If access fails, returns -EFAULT (some data may have been copied and the - * trailing NUL added). If @unsafe_addr is not a valid kernel address, return - * -ERANGE. + * If access fails, returns -EFAULT (some data may have been copied + * and the trailing NUL added). * * If @count is smaller than the length of the string, copies @count-1 bytes, * sets the last byte of @dst buffer to NUL and returns @count. */ -long strncpy_from_kernel_nofault(char *dst, const void *unsafe_addr, long count) +long strncpy_from_unsafe(char *dst, const void *unsafe_addr, long count) { mm_segment_t old_fs = get_fs(); const void *src = unsafe_addr; @@ -231,8 +166,6 @@ long strncpy_from_kernel_nofault(char *dst, const void *unsafe_addr, long count) if (unlikely(count <= 0)) return 0; - if (!copy_from_kernel_nofault_allowed(unsafe_addr, count)) - return -ERANGE; set_fs(KERNEL_DS); pagefault_disable(); @@ -247,10 +180,9 @@ long strncpy_from_kernel_nofault(char *dst, const void *unsafe_addr, long count) return ret ? -EFAULT : src - unsafe_addr; } -#endif /* HAVE_GET_KERNEL_NOFAULT */ /** - * strncpy_from_user_nofault: - Copy a NUL terminated string from unsafe user + * strncpy_from_unsafe_user: - Copy a NUL terminated string from unsafe user * address. * @dst: Destination address, in kernel space. This buffer must be at * least @count bytes long. @@ -267,7 +199,7 @@ long strncpy_from_kernel_nofault(char *dst, const void *unsafe_addr, long count) * If @count is smaller than the length of the string, copies @count-1 bytes, * sets the last byte of @dst buffer to NUL and returns @count. */ -long strncpy_from_user_nofault(char *dst, const void __user *unsafe_addr, +long strncpy_from_unsafe_user(char *dst, const void __user *unsafe_addr, long count) { mm_segment_t old_fs = get_fs(); diff --git a/mm/memcontrol.c b/mm/memcontrol.c index 0a2f67c468a0..2da22ba7efe4 100644 --- a/mm/memcontrol.c +++ b/mm/memcontrol.c @@ -6405,117 +6405,6 @@ struct cgroup_subsys memory_cgrp_subsys = { .early_init = 0, }; -/* - * This function calculates an individual cgroup's effective - * protection which is derived from its own memory.min/low, its - * parent's and siblings' settings, as well as the actual memory - * distribution in the tree. - * - * The following rules apply to the effective protection values: - * - * 1. At the first level of reclaim, effective protection is equal to - * the declared protection in memory.min and memory.low. - * - * 2. To enable safe delegation of the protection configuration, at - * subsequent levels the effective protection is capped to the - * parent's effective protection. - * - * 3. To make complex and dynamic subtrees easier to configure, the - * user is allowed to overcommit the declared protection at a given - * level. If that is the case, the parent's effective protection is - * distributed to the children in proportion to how much protection - * they have declared and how much of it they are utilizing. - * - * This makes distribution proportional, but also work-conserving: - * if one cgroup claims much more protection than it uses memory, - * the unused remainder is available to its siblings. - * - * 4. Conversely, when the declared protection is undercommitted at a - * given level, the distribution of the larger parental protection - * budget is NOT proportional. A cgroup's protection from a sibling - * is capped to its own memory.min/low setting. - * - * 5. However, to allow protecting recursive subtrees from each other - * without having to declare each individual cgroup's fixed share - * of the ancestor's claim to protection, any unutilized - - * "floating" - protection from up the tree is distributed in - * proportion to each cgroup's *usage*. This makes the protection - * neutral wrt sibling cgroups and lets them compete freely over - * the shared parental protection budget, but it protects the - * subtree as a whole from neighboring subtrees. - * - * Note that 4. and 5. are not in conflict: 4. is about protecting - * against immediate siblings whereas 5. is about protecting against - * neighboring subtrees. - */ -static unsigned long effective_protection(unsigned long usage, - unsigned long parent_usage, - unsigned long setting, - unsigned long parent_effective, - unsigned long siblings_protected) -{ - unsigned long protected; - unsigned long ep; - - protected = min(usage, setting); - /* - * If all cgroups at this level combined claim and use more - * protection then what the parent affords them, distribute - * shares in proportion to utilization. - * - * We are using actual utilization rather than the statically - * claimed protection in order to be work-conserving: claimed - * but unused protection is available to siblings that would - * otherwise get a smaller chunk than what they claimed. - */ - if (siblings_protected > parent_effective) - return protected * parent_effective / siblings_protected; - - /* - * Ok, utilized protection of all children is within what the - * parent affords them, so we know whatever this child claims - * and utilizes is effectively protected. - * - * If there is unprotected usage beyond this value, reclaim - * will apply pressure in proportion to that amount. - * - * If there is unutilized protection, the cgroup will be fully - * shielded from reclaim, but we do return a smaller value for - * protection than what the group could enjoy in theory. This - * is okay. With the overcommit distribution above, effective - * protection is always dependent on how memory is actually - * consumed among the siblings anyway. - */ - ep = protected; - - /* - * If the children aren't claiming (all of) the protection - * afforded to them by the parent, distribute the remainder in - * proportion to the (unprotected) memory of each cgroup. That - * way, cgroups that aren't explicitly prioritized wrt each - * other compete freely over the allowance, but they are - * collectively protected from neighboring trees. - * - * We're using unprotected memory for the weight so that if - * some cgroups DO claim explicit protection, we don't protect - * the same bytes twice. - */ - if (!(cgrp_dfl_root.flags & CGRP_ROOT_MEMORY_RECURSIVE_PROT)) - return ep; - - if (parent_effective > siblings_protected && usage > protected) { - unsigned long unclaimed; - - unclaimed = parent_effective - siblings_protected; - unclaimed *= usage - protected; - unclaimed /= parent_usage - siblings_protected; - - ep += unclaimed; - } - - return ep; -} - /** * mem_cgroup_protected - check if memory consumption is in the normal range * @root: the top ancestor of the sub-tree being checked @@ -6529,12 +6418,70 @@ static unsigned long effective_protection(unsigned long usage, * MEMCG_PROT_LOW: cgroup memory is protected as long there is * an unprotected supply of reclaimable memory from other cgroups. * MEMCG_PROT_MIN: cgroup memory is protected + * + * @root is exclusive; it is never protected when looked at directly + * + * To provide a proper hierarchical behavior, effective memory.min/low values + * are used. Below is the description of how effective memory.low is calculated. + * Effective memory.min values is calculated in the same way. + * + * Effective memory.low is always equal or less than the original memory.low. + * If there is no memory.low overcommittment (which is always true for + * top-level memory cgroups), these two values are equal. + * Otherwise, it's a part of parent's effective memory.low, + * calculated as a cgroup's memory.low usage divided by sum of sibling's + * memory.low usages, where memory.low usage is the size of actually + * protected memory. + * + * low_usage + * elow = min( memory.low, parent->elow * ------------------ ), + * siblings_low_usage + * + * | memory.current, if memory.current < memory.low + * low_usage = | + * | 0, otherwise. + * + * + * Such definition of the effective memory.low provides the expected + * hierarchical behavior: parent's memory.low value is limiting + * children, unprotected memory is reclaimed first and cgroups, + * which are not using their guarantee do not affect actual memory + * distribution. + * + * For example, if there are memcgs A, A/B, A/C, A/D and A/E: + * + * A A/memory.low = 2G, A/memory.current = 6G + * //\\ + * BC DE B/memory.low = 3G B/memory.current = 2G + * C/memory.low = 1G C/memory.current = 2G + * D/memory.low = 0 D/memory.current = 2G + * E/memory.low = 10G E/memory.current = 0 + * + * and the memory pressure is applied, the following memory distribution + * is expected (approximately): + * + * A/memory.current = 2G + * + * B/memory.current = 1.3G + * C/memory.current = 0.6G + * D/memory.current = 0 + * E/memory.current = 0 + * + * These calculations require constant tracking of the actual low usages + * (see propagate_protected_usage()), as well as recursive calculation of + * effective memory.low values. But as we do call mem_cgroup_protected() + * path for each memory cgroup top-down from the reclaim, + * it's possible to optimize this part, and save calculated elow + * for next usage. This part is intentionally racy, but it's ok, + * as memory.low is a best-effort mechanism. */ enum mem_cgroup_protection mem_cgroup_protected(struct mem_cgroup *root, struct mem_cgroup *memcg) { - unsigned long usage, parent_usage; struct mem_cgroup *parent; + unsigned long emin, parent_emin; + unsigned long elow, parent_elow; + unsigned long usage; if (mem_cgroup_disabled()) return MEMCG_PROT_NONE; @@ -6556,31 +6503,52 @@ enum mem_cgroup_protection mem_cgroup_protected(struct mem_cgroup *root, if (!usage) return MEMCG_PROT_NONE; + emin = memcg->memory.min; + elow = memcg->memory.low; + parent = parent_mem_cgroup(memcg); /* No parent means a non-hierarchical mode on v1 memcg */ if (!parent) return MEMCG_PROT_NONE; - if (parent == root) { - memcg->memory.emin = memcg->memory.min; - memcg->memory.elow = memcg->memory.low; - goto out; + if (parent == root) + goto exit; + + parent_emin = READ_ONCE(parent->memory.emin); + emin = min(emin, parent_emin); + if (emin && parent_emin) { + unsigned long min_usage, siblings_min_usage; + + min_usage = min(usage, memcg->memory.min); + siblings_min_usage = atomic_long_read( + &parent->memory.children_min_usage); + + if (min_usage && siblings_min_usage) + emin = min(emin, parent_emin * min_usage / + siblings_min_usage); } - parent_usage = page_counter_read(&parent->memory); + parent_elow = READ_ONCE(parent->memory.elow); + elow = min(elow, parent_elow); + if (elow && parent_elow) { + unsigned long low_usage, siblings_low_usage; - memcg->memory.emin = effective_protection(usage, parent_usage, - memcg->memory.min, READ_ONCE(parent->memory.emin), - atomic_long_read(&parent->memory.children_min_usage)); + low_usage = min(usage, memcg->memory.low); + siblings_low_usage = atomic_long_read( + &parent->memory.children_low_usage); - memcg->memory.elow = effective_protection(usage, parent_usage, - memcg->memory.low, READ_ONCE(parent->memory.elow), - atomic_long_read(&parent->memory.children_low_usage)); + if (low_usage && siblings_low_usage) + elow = min(elow, parent_elow * low_usage / + siblings_low_usage); + } -out: - if (usage <= memcg->memory.emin) +exit: + memcg->memory.emin = emin; + memcg->memory.elow = elow; + + if (usage <= emin) return MEMCG_PROT_MIN; - else if (usage <= memcg->memory.elow) + else if (usage <= elow) return MEMCG_PROT_LOW; else return MEMCG_PROT_NONE; diff --git a/mm/memory.c b/mm/memory.c index a6346468cf38..41572f4ccf48 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -2539,7 +2539,6 @@ static vm_fault_t wp_page_copy(struct vm_fault *vmf) } flush_cache_page(vma, vmf->address, pte_pfn(vmf->orig_pte)); entry = mk_pte(new_page, vma->vm_page_prot); - entry = pte_sw_mkyoung(entry); entry = maybe_mkwrite(pte_mkdirty(entry), vma); /* * Clear the pte entry and flush it first, before updating the @@ -3224,7 +3223,6 @@ static vm_fault_t do_anonymous_page(struct vm_fault *vmf) __SetPageUptodate(page); entry = mk_pte(page, vma->vm_page_prot); - entry = pte_sw_mkyoung(entry); if (vma->vm_flags & VM_WRITE) entry = pte_mkwrite(pte_mkdirty(entry)); @@ -3513,7 +3511,6 @@ vm_fault_t alloc_set_pte(struct vm_fault *vmf, struct mem_cgroup *memcg, flush_icache_page(vma, page); entry = mk_pte(page, vma->vm_page_prot); - entry = pte_sw_mkyoung(entry); if (write) entry = maybe_mkwrite(pte_mkdirty(entry), vma); diff --git a/mm/nommu.c b/mm/nommu.c index f5776ff7b0b7..3b67bd20c2af 100644 --- a/mm/nommu.c +++ b/mm/nommu.c @@ -140,7 +140,7 @@ void vfree(const void *addr) } EXPORT_SYMBOL(vfree); -void *__vmalloc(unsigned long size, gfp_t gfp_mask) +void *__vmalloc(unsigned long size, gfp_t gfp_mask, pgprot_t prot) { /* * You can't specify __GFP_HIGHMEM with kmalloc() since kmalloc() @@ -152,14 +152,14 @@ EXPORT_SYMBOL(__vmalloc); void *__vmalloc_node_flags(unsigned long size, int node, gfp_t flags) { - return __vmalloc(size, flags); + return __vmalloc(size, flags, PAGE_KERNEL); } void *vmalloc_user(unsigned long size) { void *ret; - ret = __vmalloc(size, GFP_KERNEL | __GFP_ZERO); + ret = __vmalloc(size, GFP_KERNEL | __GFP_ZERO, PAGE_KERNEL); if (ret) { struct vm_area_struct *vma; @@ -219,7 +219,7 @@ long vwrite(char *buf, char *addr, unsigned long count) */ void *vmalloc(unsigned long size) { - return __vmalloc(size, GFP_KERNEL | __GFP_HIGHMEM); + return __vmalloc(size, GFP_KERNEL | __GFP_HIGHMEM, PAGE_KERNEL); } EXPORT_SYMBOL(vmalloc); @@ -237,7 +237,8 @@ EXPORT_SYMBOL(vmalloc); */ void *vzalloc(unsigned long size) { - return __vmalloc(size, GFP_KERNEL | __GFP_HIGHMEM | __GFP_ZERO); + return __vmalloc(size, GFP_KERNEL | __GFP_HIGHMEM | __GFP_ZERO, + PAGE_KERNEL); } EXPORT_SYMBOL(vzalloc); @@ -290,7 +291,7 @@ EXPORT_SYMBOL(vzalloc_node); void *vmalloc_exec(unsigned long size) { - return __vmalloc(size, GFP_KERNEL | __GFP_HIGHMEM); + return __vmalloc(size, GFP_KERNEL | __GFP_HIGHMEM, PAGE_KERNEL_EXEC); } /** @@ -302,7 +303,7 @@ void *vmalloc_exec(unsigned long size) */ void *vmalloc_32(unsigned long size) { - return __vmalloc(size, GFP_KERNEL); + return __vmalloc(size, GFP_KERNEL, PAGE_KERNEL); } EXPORT_SYMBOL(vmalloc_32); diff --git a/mm/page-writeback.c b/mm/page-writeback.c index de9031d394ab..ad68a2d0119b 100644 --- a/mm/page-writeback.c +++ b/mm/page-writeback.c @@ -523,7 +523,8 @@ bool node_dirty_ok(struct pglist_data *pgdat) } int dirty_background_ratio_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { int ret; @@ -534,7 +535,8 @@ int dirty_background_ratio_handler(struct ctl_table *table, int write, } int dirty_background_bytes_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { int ret; unsigned long old_bytes = dirty_background_bytes; @@ -551,8 +553,9 @@ int dirty_background_bytes_handler(struct ctl_table *table, int write, return ret; } -int dirty_ratio_handler(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos) +int dirty_ratio_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos) { int old_ratio = vm_dirty_ratio; int ret; @@ -566,7 +569,8 @@ int dirty_ratio_handler(struct ctl_table *table, int write, void *buffer, } int dirty_bytes_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { unsigned long old_bytes = vm_dirty_bytes; int ret; @@ -1990,7 +1994,7 @@ bool wb_over_bg_thresh(struct bdi_writeback *wb) * sysctl handler for /proc/sys/vm/dirty_writeback_centisecs */ int dirty_writeback_centisecs_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos) + void __user *buffer, size_t *length, loff_t *ppos) { unsigned int old_interval = dirty_writeback_interval; int ret; diff --git a/mm/page_alloc.c b/mm/page_alloc.c index 2b4a3d33d48b..7d1fc0d92666 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -5730,11 +5730,21 @@ char numa_zonelist_order[] = "Node"; * sysctl handler for numa_zonelist_order */ int numa_zonelist_order_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos) + void __user *buffer, size_t *length, + loff_t *ppos) { - if (write) - return __parse_numa_zonelist_order(buffer); - return proc_dostring(table, write, buffer, length, ppos); + char *str; + int ret; + + if (!write) + return proc_dostring(table, write, buffer, length, ppos); + str = memdup_user_nul(buffer, 16); + if (IS_ERR(str)) + return PTR_ERR(str); + + ret = __parse_numa_zonelist_order(str); + kfree(str); + return ret; } @@ -8145,7 +8155,7 @@ postcore_initcall(init_per_zone_wmark_min) * or extra_free_kbytes changes. */ int min_free_kbytes_sysctl_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos) + void __user *buffer, size_t *length, loff_t *ppos) { int rc; @@ -8189,7 +8199,7 @@ int kswapd_threads_sysctl_handler(struct ctl_table *table, int write, } #endif int watermark_scale_factor_sysctl_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos) + void __user *buffer, size_t *length, loff_t *ppos) { int rc; @@ -8219,7 +8229,7 @@ static void setup_min_unmapped_ratio(void) int sysctl_min_unmapped_ratio_sysctl_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos) + void __user *buffer, size_t *length, loff_t *ppos) { int rc; @@ -8246,7 +8256,7 @@ static void setup_min_slab_ratio(void) } int sysctl_min_slab_ratio_sysctl_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos) + void __user *buffer, size_t *length, loff_t *ppos) { int rc; @@ -8270,7 +8280,7 @@ int sysctl_min_slab_ratio_sysctl_handler(struct ctl_table *table, int write, * if in function of the boot time zone sizes. */ int lowmem_reserve_ratio_sysctl_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos) + void __user *buffer, size_t *length, loff_t *ppos) { proc_dointvec_minmax(table, write, buffer, length, ppos); setup_per_zone_lowmem_reserve(); @@ -8283,7 +8293,7 @@ int lowmem_reserve_ratio_sysctl_handler(struct ctl_table *table, int write, * pagelist can have before it gets flushed back to buddy allocator. */ int percpu_pagelist_fraction_sysctl_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos) + void __user *buffer, size_t *length, loff_t *ppos) { struct zone *zone; int old_percpu_pagelist_fraction; @@ -8432,7 +8442,7 @@ void *__init alloc_large_system_hash(const char *tablename, table = memblock_alloc_raw(size, SMP_CACHE_BYTES); } else if (get_order(size) >= MAX_ORDER || hashdist) { - table = __vmalloc(size, gfp_flags); + table = __vmalloc(size, gfp_flags, PAGE_KERNEL); virt = true; } else { /* @@ -8449,7 +8459,7 @@ void *__init alloc_large_system_hash(const char *tablename, panic("Failed to allocate %s hash table\n", tablename); pr_info("%s hash table entries: %ld (order: %d, %lu bytes, %s)\n", - tablename, 1UL << log2qty, get_order(size), size, + tablename, 1UL << log2qty, ilog2(size) - PAGE_SHIFT, size, virt ? "vmalloc" : "linear"); if (_hash_shift) diff --git a/mm/percpu.c b/mm/percpu.c index 1e31e6bc6ba5..2e4b286c88c8 100644 --- a/mm/percpu.c +++ b/mm/percpu.c @@ -508,7 +508,7 @@ static void *pcpu_mem_zalloc(size_t size, gfp_t gfp) if (size <= PAGE_SIZE) return kzalloc(size, gfp); else - return __vmalloc(size, gfp | __GFP_ZERO); + return __vmalloc(size, gfp | __GFP_ZERO, PAGE_KERNEL); } /** diff --git a/mm/rodata_test.c b/mm/rodata_test.c index 2a99df7beeb3..5e313fa93276 100644 --- a/mm/rodata_test.c +++ b/mm/rodata_test.c @@ -25,7 +25,7 @@ void rodata_test(void) } /* test 2: write to the variable; this should fault */ - if (!copy_to_kernel_nofault((void *)&rodata_test_data, + if (!probe_kernel_write((void *)&rodata_test_data, (void *)&zero, sizeof(zero))) { pr_err("test data was not read only\n"); return; diff --git a/mm/shmem.c b/mm/shmem.c index edaa65d0aacb..f7c04a91687b 100644 --- a/mm/shmem.c +++ b/mm/shmem.c @@ -3203,7 +3203,7 @@ static int shmem_xattr_handler_set(const struct xattr_handler *handler, struct shmem_inode_info *info = SHMEM_I(inode); name = xattr_full_name(handler, name); - return simple_xattr_set(&info->xattrs, name, value, size, flags, NULL); + return simple_xattr_set(&info->xattrs, name, value, size, flags); } static const struct xattr_handler shmem_security_xattr_handler = { diff --git a/mm/slab.c b/mm/slab.c index a9a5fb49373d..1a75a1204ff4 100644 --- a/mm/slab.c +++ b/mm/slab.c @@ -100,7 +100,6 @@ #include #include #include -#include #include #include #include @@ -3220,28 +3219,18 @@ must_grow: } static __always_inline void * -slab_alloc_node(struct kmem_cache *cachep, gfp_t flags, int nodeid, size_t orig_size, +slab_alloc_node(struct kmem_cache *cachep, gfp_t flags, int nodeid, unsigned long caller) { unsigned long save_flags; void *ptr; int slab_node = numa_mem_id(); - struct kmem_cache *orig_cachep = cachep; flags &= gfp_allowed_mask; cachep = slab_pre_alloc_hook(cachep, flags); if (unlikely(!cachep)) return NULL; - /* - * 5.4 note: passing in original cachep to avoid problems with memcg - * accounting. Making KFENCE properly work with memcgs on older kernels - * is not worth the effort. - */ - ptr = kfence_alloc(orig_cachep, orig_size, flags); - if (unlikely(ptr)) - goto out_hooks; - cache_alloc_debugcheck_before(cachep, flags); local_irq_save(save_flags); @@ -3274,7 +3263,6 @@ slab_alloc_node(struct kmem_cache *cachep, gfp_t flags, int nodeid, size_t orig_ if (unlikely(slab_want_init_on_alloc(flags, cachep)) && ptr) memset(ptr, 0, cachep->object_size); -out_hooks: slab_post_alloc_hook(cachep, flags, 1, &ptr); return ptr; } @@ -3312,26 +3300,16 @@ __do_cache_alloc(struct kmem_cache *cachep, gfp_t flags) #endif /* CONFIG_NUMA */ static __always_inline void * -slab_alloc(struct kmem_cache *cachep, gfp_t flags, size_t orig_size, unsigned long caller) +slab_alloc(struct kmem_cache *cachep, gfp_t flags, unsigned long caller) { unsigned long save_flags; void *objp; - struct kmem_cache *orig_cachep = cachep; flags &= gfp_allowed_mask; cachep = slab_pre_alloc_hook(cachep, flags); if (unlikely(!cachep)) return NULL; - /* - * 5.4 note: passing in original cachep to avoid problems with memcg - * accounting. Making KFENCE properly work with memcgs on older kernels - * is not worth the effort. - */ - objp = kfence_alloc(orig_cachep, orig_size, flags); - if (unlikely(objp)) - goto out; - cache_alloc_debugcheck_before(cachep, flags); local_irq_save(save_flags); objp = __do_cache_alloc(cachep, flags); @@ -3342,7 +3320,6 @@ slab_alloc(struct kmem_cache *cachep, gfp_t flags, size_t orig_size, unsigned lo if (unlikely(slab_want_init_on_alloc(flags, cachep)) && objp) memset(objp, 0, cachep->object_size); -out: slab_post_alloc_hook(cachep, flags, 1, &objp); return objp; } @@ -3448,15 +3425,6 @@ free_done: static __always_inline void __cache_free(struct kmem_cache *cachep, void *objp, unsigned long caller) { - if (is_kfence_address(objp)) { - kmemleak_free_recursive(objp, cachep->flags); - __kfence_free(objp); - return; - } - - if (unlikely(slab_want_init_on_free(cachep))) - memset(objp, 0, cachep->object_size); - /* Put the object into the quarantine, don't touch it for now. */ if (kasan_slab_free(cachep, objp, _RET_IP_)) return; @@ -3470,6 +3438,8 @@ void ___cache_free(struct kmem_cache *cachep, void *objp, struct array_cache *ac = cpu_cache_get(cachep); check_irq_off(); + if (unlikely(slab_want_init_on_free(cachep))) + memset(objp, 0, cachep->object_size); kmemleak_free_recursive(objp, cachep->flags); objp = cache_free_debugcheck(cachep, objp, caller); @@ -3514,7 +3484,7 @@ void ___cache_free(struct kmem_cache *cachep, void *objp, */ void *kmem_cache_alloc(struct kmem_cache *cachep, gfp_t flags) { - void *ret = slab_alloc(cachep, flags, cachep->object_size, _RET_IP_); + void *ret = slab_alloc(cachep, flags, _RET_IP_); trace_kmem_cache_alloc(_RET_IP_, ret, cachep->object_size, cachep->size, flags); @@ -3537,7 +3507,6 @@ int kmem_cache_alloc_bulk(struct kmem_cache *s, gfp_t flags, size_t size, void **p) { size_t i; - struct kmem_cache *root_s = s; s = slab_pre_alloc_hook(s, flags); if (!s) @@ -3547,13 +3516,7 @@ int kmem_cache_alloc_bulk(struct kmem_cache *s, gfp_t flags, size_t size, local_irq_disable(); for (i = 0; i < size; i++) { - /* - * 5.4 note: passing in original cachep to avoid problems with - * memcg accounting. Making KFENCE properly work with memcgs on - * older kernels is not worth the effort. - */ - void *objp = kfence_alloc(root_s, s->object_size, flags) ?: - __do_cache_alloc(s, flags); + void *objp = __do_cache_alloc(s, flags); if (unlikely(!objp)) goto error; @@ -3586,7 +3549,7 @@ kmem_cache_alloc_trace(struct kmem_cache *cachep, gfp_t flags, size_t size) { void *ret; - ret = slab_alloc(cachep, flags, size, _RET_IP_); + ret = slab_alloc(cachep, flags, _RET_IP_); ret = kasan_kmalloc(cachep, ret, size, flags); trace_kmalloc(_RET_IP_, ret, @@ -3612,7 +3575,7 @@ EXPORT_SYMBOL(kmem_cache_alloc_trace); */ void *kmem_cache_alloc_node(struct kmem_cache *cachep, gfp_t flags, int nodeid) { - void *ret = slab_alloc_node(cachep, flags, nodeid, cachep->object_size, _RET_IP_); + void *ret = slab_alloc_node(cachep, flags, nodeid, _RET_IP_); trace_kmem_cache_alloc_node(_RET_IP_, ret, cachep->object_size, cachep->size, @@ -3630,7 +3593,7 @@ void *kmem_cache_alloc_node_trace(struct kmem_cache *cachep, { void *ret; - ret = slab_alloc_node(cachep, flags, nodeid, size, _RET_IP_); + ret = slab_alloc_node(cachep, flags, nodeid, _RET_IP_); ret = kasan_kmalloc(cachep, ret, size, flags); trace_kmalloc_node(_RET_IP_, ret, @@ -3691,7 +3654,7 @@ static __always_inline void *__do_kmalloc(size_t size, gfp_t flags, cachep = kmalloc_slab(size, flags); if (unlikely(ZERO_OR_NULL_PTR(cachep))) return cachep; - ret = slab_alloc(cachep, flags, size, caller); + ret = slab_alloc(cachep, flags, caller); ret = kasan_kmalloc(cachep, ret, size, flags); trace_kmalloc(caller, ret, @@ -4240,10 +4203,7 @@ void __check_heap_object(const void *ptr, unsigned long n, struct page *page, BUG_ON(objnr >= cachep->num); /* Find offset within object. */ - if (is_kfence_address(ptr)) - offset = ptr - kfence_object_start(ptr); - else - offset = ptr - index_to_obj(cachep, page, objnr) - obj_offset(cachep); + offset = ptr - index_to_obj(cachep, page, objnr) - obj_offset(cachep); /* Allow address range falling entirely within usercopy region. */ if (offset >= cachep->useroffset && diff --git a/mm/slab_common.c b/mm/slab_common.c index f024c2067aa0..ca398f6bfa48 100644 --- a/mm/slab_common.c +++ b/mm/slab_common.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -594,7 +593,6 @@ static void slab_caches_to_rcu_destroy_workfn(struct work_struct *work) rcu_barrier(); list_for_each_entry_safe(s, s2, &to_destroy, list) { - kfence_shutdown_cache(s); #ifdef SLAB_SUPPORTS_SYSFS sysfs_slab_release(s); #else @@ -621,7 +619,6 @@ static int shutdown_cache(struct kmem_cache *s) list_add_tail(&s->list, &slab_caches_to_rcu_destroy); schedule_work(&slab_caches_to_rcu_destroy_work); } else { - kfence_shutdown_cache(s); #ifdef SLAB_SUPPORTS_SYSFS sysfs_slab_unlink(s); sysfs_slab_release(s); @@ -1873,7 +1870,7 @@ size_t ksize(const void *objp) if (unlikely(objp == ZERO_SIZE_PTR) || !__kasan_check_read(objp, 1)) return 0; - size = kfence_ksize(objp) ?: __ksize(objp); + size = __ksize(objp); /* * We assume that ksize callers could use whole allocated area, * so we need to unpoison this area. diff --git a/mm/slub.c b/mm/slub.c index 638736789987..8d8d0f67c795 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -304,7 +303,7 @@ static inline void *get_freepointer_safe(struct kmem_cache *s, void *object) return get_freepointer(s, object); freepointer_addr = (unsigned long)object + s->offset; - copy_from_kernel_nofault(&p, (void **)freepointer_addr, sizeof(p)); + probe_kernel_read(&p, (void **)freepointer_addr, sizeof(p)); return freelist_ptr(s, p, freepointer_addr); } @@ -1487,11 +1486,6 @@ static inline bool slab_free_freelist_hook(struct kmem_cache *s, void *old_tail = *tail ? *tail : *head; int rsize; - if (is_kfence_address(next)) { - slab_free_hook(s, next); - return true; - } - /* Head and tail of the reconstructed freelist */ *head = NULL; *tail = NULL; @@ -2776,27 +2770,16 @@ static __always_inline void maybe_wipe_obj_freeptr(struct kmem_cache *s, * Otherwise we can simply pick the next object from the lockless free list. */ static __always_inline void *slab_alloc_node(struct kmem_cache *s, - gfp_t gfpflags, int node, unsigned long addr, size_t orig_size) + gfp_t gfpflags, int node, unsigned long addr) { void *object; struct kmem_cache_cpu *c; struct page *page; unsigned long tid; - struct kmem_cache *root_s = s; s = slab_pre_alloc_hook(s, gfpflags); if (!s) return NULL; - - /* - * 5.4 note: passing in original cachep to avoid problems with memcg - * accounting. Making KFENCE properly work with memcgs on older kernels - * is not worth the effort. - */ - object = kfence_alloc(root_s, orig_size, gfpflags); - if (unlikely(object)) - goto out; - redo: /* * Must read kmem_cache cpu data via this cpu ptr. Preemption is @@ -2870,21 +2853,20 @@ redo: if (unlikely(slab_want_init_on_alloc(gfpflags, s)) && object) memset(object, 0, s->object_size); -out: slab_post_alloc_hook(s, gfpflags, 1, &object); return object; } static __always_inline void *slab_alloc(struct kmem_cache *s, - gfp_t gfpflags, unsigned long addr, size_t orig_size) + gfp_t gfpflags, unsigned long addr) { - return slab_alloc_node(s, gfpflags, NUMA_NO_NODE, addr, orig_size); + return slab_alloc_node(s, gfpflags, NUMA_NO_NODE, addr); } void *kmem_cache_alloc(struct kmem_cache *s, gfp_t gfpflags) { - void *ret = slab_alloc(s, gfpflags, _RET_IP_, s->object_size); + void *ret = slab_alloc(s, gfpflags, _RET_IP_); trace_kmem_cache_alloc(_RET_IP_, ret, s->object_size, s->size, gfpflags); @@ -2896,7 +2878,7 @@ EXPORT_SYMBOL(kmem_cache_alloc); #ifdef CONFIG_TRACING void *kmem_cache_alloc_trace(struct kmem_cache *s, gfp_t gfpflags, size_t size) { - void *ret = slab_alloc(s, gfpflags, _RET_IP_, size); + void *ret = slab_alloc(s, gfpflags, _RET_IP_); trace_kmalloc(_RET_IP_, ret, size, s->size, gfpflags); ret = kasan_kmalloc(s, ret, size, gfpflags); return ret; @@ -2907,7 +2889,7 @@ EXPORT_SYMBOL(kmem_cache_alloc_trace); #ifdef CONFIG_NUMA void *kmem_cache_alloc_node(struct kmem_cache *s, gfp_t gfpflags, int node) { - void *ret = slab_alloc_node(s, gfpflags, node, _RET_IP_, s->object_size); + void *ret = slab_alloc_node(s, gfpflags, node, _RET_IP_); trace_kmem_cache_alloc_node(_RET_IP_, ret, s->object_size, s->size, gfpflags, node); @@ -2921,7 +2903,7 @@ void *kmem_cache_alloc_node_trace(struct kmem_cache *s, gfp_t gfpflags, int node, size_t size) { - void *ret = slab_alloc_node(s, gfpflags, node, _RET_IP_, size); + void *ret = slab_alloc_node(s, gfpflags, node, _RET_IP_); trace_kmalloc_node(_RET_IP_, ret, size, s->size, gfpflags, node); @@ -2955,9 +2937,6 @@ static void __slab_free(struct kmem_cache *s, struct page *page, stat(s, FREE_SLOWPATH); - if (kfence_free(head)) - return; - if (kmem_cache_debug(s) && !free_debug_processing(s, page, head, tail, cnt, addr)) return; @@ -3199,13 +3178,6 @@ int build_detached_freelist(struct kmem_cache *s, size_t size, df->s = cache_from_obj(s, object); /* Support for memcg */ } - if (is_kfence_address(object)) { - slab_free_hook(df->s, object); - __kfence_free(object); - p[size] = NULL; /* mark object processed */ - return size; - } - /* Start new detached freelist */ df->page = page; set_freepointer(df->s, object, NULL); @@ -3265,7 +3237,6 @@ int kmem_cache_alloc_bulk(struct kmem_cache *s, gfp_t flags, size_t size, { struct kmem_cache_cpu *c; int i; - struct kmem_cache *root_s = s; /* memcg and kmem_cache debug support */ s = slab_pre_alloc_hook(s, flags); @@ -3280,19 +3251,8 @@ int kmem_cache_alloc_bulk(struct kmem_cache *s, gfp_t flags, size_t size, c = this_cpu_ptr(s->cpu_slab); for (i = 0; i < size; i++) { - /* - * 5.4 note: passing in original cachep to avoid problems with memcg - * accounting. Making KFENCE properly work with memcgs on older kernels - * is not worth the effort. - */ - void *object = kfence_alloc(root_s, s->object_size, flags); + void *object = c->freelist; - if (unlikely(object)) { - p[i] = object; - continue; - } - - object = c->freelist; if (unlikely(!object)) { /* * We may have removed an object from c->freelist using @@ -3951,7 +3911,7 @@ void *__kmalloc(size_t size, gfp_t flags) if (unlikely(ZERO_OR_NULL_PTR(s))) return s; - ret = slab_alloc(s, flags, _RET_IP_, size); + ret = slab_alloc(s, flags, _RET_IP_); trace_kmalloc(_RET_IP_, ret, size, s->size, flags); @@ -3999,7 +3959,7 @@ void *__kmalloc_node(size_t size, gfp_t flags, int node) if (unlikely(ZERO_OR_NULL_PTR(s))) return s; - ret = slab_alloc_node(s, flags, node, _RET_IP_, size); + ret = slab_alloc_node(s, flags, node, _RET_IP_); trace_kmalloc_node(_RET_IP_, ret, size, s->size, flags, node); @@ -4025,7 +3985,6 @@ void __check_heap_object(const void *ptr, unsigned long n, struct page *page, struct kmem_cache *s; unsigned int offset; size_t object_size; - bool is_kfence = is_kfence_address(ptr); ptr = kasan_reset_tag(ptr); @@ -4038,13 +3997,10 @@ void __check_heap_object(const void *ptr, unsigned long n, struct page *page, to_user, 0, n); /* Find offset within object. */ - if (is_kfence) - offset = ptr - kfence_object_start(ptr); - else - offset = (ptr - page_address(page)) % s->size; + offset = (ptr - page_address(page)) % s->size; /* Adjust for redzone and reject if within the redzone. */ - if (!is_kfence && kmem_cache_debug(s) && s->flags & SLAB_RED_ZONE) { + if (kmem_cache_debug(s) && s->flags & SLAB_RED_ZONE) { if (offset < s->red_left_pad) usercopy_abort("SLUB object in left red zone", s->name, to_user, offset, n); @@ -4491,7 +4447,7 @@ void *__kmalloc_track_caller(size_t size, gfp_t gfpflags, unsigned long caller) if (unlikely(ZERO_OR_NULL_PTR(s))) return s; - ret = slab_alloc(s, gfpflags, caller, size); + ret = slab_alloc(s, gfpflags, caller); /* Honor the call site pointer we received. */ trace_kmalloc(caller, ret, size, s->size, gfpflags); @@ -4522,7 +4478,7 @@ void *__kmalloc_node_track_caller(size_t size, gfp_t gfpflags, if (unlikely(ZERO_OR_NULL_PTR(s))) return s; - ret = slab_alloc_node(s, gfpflags, node, caller, size); + ret = slab_alloc_node(s, gfpflags, node, caller); /* Honor the call site pointer we received. */ trace_kmalloc_node(caller, ret, size, s->size, gfpflags, node); diff --git a/mm/util.c b/mm/util.c index cd6aa1118a6b..289e38a06a51 100644 --- a/mm/util.c +++ b/mm/util.c @@ -757,8 +757,9 @@ int sysctl_max_map_count __read_mostly = DEFAULT_MAX_MAP_COUNT; unsigned long sysctl_user_reserve_kbytes __read_mostly = 1UL << 17; /* 128MB */ unsigned long sysctl_admin_reserve_kbytes __read_mostly = 1UL << 13; /* 8MB */ -int overcommit_ratio_handler(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos) +int overcommit_ratio_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos) { int ret; @@ -768,8 +769,9 @@ int overcommit_ratio_handler(struct ctl_table *table, int write, void *buffer, return ret; } -int overcommit_kbytes_handler(struct ctl_table *table, int write, void *buffer, - size_t *lenp, loff_t *ppos) +int overcommit_kbytes_handler(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos) { int ret; diff --git a/mm/vmalloc.c b/mm/vmalloc.c index faa12b2d121c..d89ffa44516a 100644 --- a/mm/vmalloc.c +++ b/mm/vmalloc.c @@ -2643,9 +2643,9 @@ static void *__vmalloc_node(unsigned long size, unsigned long align, #endif } -void *__vmalloc(unsigned long size, gfp_t gfp_mask) +void *__vmalloc(unsigned long size, gfp_t gfp_mask, pgprot_t prot) { - return __vmalloc_node(size, 1, gfp_mask, PAGE_KERNEL, NUMA_NO_NODE, + return __vmalloc_node(size, 1, gfp_mask, prot, NUMA_NO_NODE, __builtin_return_address(0)); } EXPORT_SYMBOL(__vmalloc); @@ -2762,26 +2762,6 @@ void *vzalloc_node(unsigned long size, int node) } EXPORT_SYMBOL(vzalloc_node); -/** - * vmalloc_user_node_flags - allocate memory for userspace on a specific node - * @size: allocation size - * @node: numa node - * @flags: flags for the page level allocator - * - * The resulting memory area is zeroed so it can be mapped to userspace - * without leaking data. - * - * Return: pointer to the allocated memory or %NULL on error - */ -void *vmalloc_user_node_flags(unsigned long size, int node, gfp_t flags) -{ - return __vmalloc_node_range(size, SHMLBA, VMALLOC_START, VMALLOC_END, - flags | __GFP_ZERO, PAGE_KERNEL, - VM_USERMAP, node, - __builtin_return_address(0)); -} -EXPORT_SYMBOL(vmalloc_user_node_flags); - /** * vmalloc_exec - allocate virtually contiguous, executable memory * @size: allocation size diff --git a/mm/vmstat.c b/mm/vmstat.c index 4a7366dcfd3b..10d281bfd71b 100644 --- a/mm/vmstat.c +++ b/mm/vmstat.c @@ -76,7 +76,7 @@ static void invalid_numa_statistics(void) static DEFINE_MUTEX(vm_numa_stat_lock); int sysctl_vm_numa_stat_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, loff_t *ppos) + void __user *buffer, size_t *length, loff_t *ppos) { int ret, oldval; @@ -1761,7 +1761,7 @@ static void refresh_vm_stats(struct work_struct *work) } int vmstat_refresh(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { long val; int err; diff --git a/net/8021q/vlan.c b/net/8021q/vlan.c index c6d5cf810523..14244445f944 100644 --- a/net/8021q/vlan.c +++ b/net/8021q/vlan.c @@ -187,8 +187,6 @@ int register_vlan_dev(struct net_device *dev, struct netlink_ext_ack *extack) vlan_group_set_device(grp, vlan->vlan_proto, vlan_id, dev); grp->nr_vlan_devs++; - netdev_update_features(dev); - return 0; out_unregister_netdev: diff --git a/net/9p/trans_fd.c b/net/9p/trans_fd.c index 3a56a888f939..872568cca926 100644 --- a/net/9p/trans_fd.c +++ b/net/9p/trans_fd.c @@ -711,10 +711,10 @@ static int p9_fd_cancelled(struct p9_client *client, struct p9_req_t *req) p9_debug(P9_DEBUG_TRANS, "client %p req %p\n", client, req); spin_lock(&client->lock); - /* Ignore cancelled request if status changed since the request was - * processed in p9_client_flush() - */ - if (req->status != REQ_STATUS_SENT) { + /* Ignore cancelled request if message has been received + * before lock. + */ + if (req->status == REQ_STATUS_RCVD) { spin_unlock(&client->lock); return 0; } diff --git a/net/Kconfig b/net/Kconfig index deca236df35f..7bab19b67941 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -258,7 +258,7 @@ config XPS default y config HWBM - bool + bool config CGROUP_NET_PRIO bool "Network priority cgroup" @@ -309,8 +309,12 @@ config BPF_STREAM_PARSER select STREAM_PARSER select NET_SOCK_MSG ---help--- - Enabling this allows a stream parser to be used with - BPF_MAP_TYPE_SOCKMAP. + Enabling this allows a stream parser to be used with + BPF_MAP_TYPE_SOCKMAP. + + BPF_MAP_TYPE_SOCKMAP provides a map type to use with network sockets. + It can be used to enforce socket policy, implement socket redirects, + etc. config NET_FLOW_LIMIT bool @@ -345,12 +349,12 @@ config NET_DROP_MONITOR tristate "Network packet drop alerting service" depends on INET && TRACEPOINTS ---help--- - This feature provides an alerting service to userspace in the - event that packets are discarded in the network stack. Alerts - are broadcast via netlink socket to any listening user space - process. If you don't need network drop alerts, or if you are ok - just checking the various proc files and other utilities for - drop statistics, say N here. + This feature provides an alerting service to userspace in the + event that packets are discarded in the network stack. Alerts + are broadcast via netlink socket to any listening user space + process. If you don't need network drop alerts, or if you are ok + just checking the various proc files and other utilities for + drop statistics, say N here. endmenu @@ -430,7 +434,7 @@ config NET_DEVLINK imply NET_DROP_MONITOR config PAGE_POOL - bool + bool config FAILOVER tristate "Generic failover module" diff --git a/net/ax25/af_ax25.c b/net/ax25/af_ax25.c index 302696254ae6..aff991ca0e4a 100644 --- a/net/ax25/af_ax25.c +++ b/net/ax25/af_ax25.c @@ -831,7 +831,7 @@ static int ax25_create(struct net *net, struct socket *sock, int protocol, struct sock *sk; ax25_cb *ax25; - if (protocol < 0 || protocol > U8_MAX) + if (protocol < 0 || protocol > SK_PROTOCOL_MAX) return -EINVAL; if (!net_eq(net, &init_net)) diff --git a/net/bluetooth/6lowpan.c b/net/bluetooth/6lowpan.c index c7cdb5c1273a..12052b766441 100644 --- a/net/bluetooth/6lowpan.c +++ b/net/bluetooth/6lowpan.c @@ -52,11 +52,6 @@ static bool enable_6lowpan; static struct l2cap_chan *listen_chan; static DEFINE_MUTEX(set_lock); -enum { - LOWPAN_PEER_CLOSING, - LOWPAN_PEER_MAXBITS -}; - struct lowpan_peer { struct list_head list; struct rcu_head rcu; @@ -65,8 +60,6 @@ struct lowpan_peer { /* peer addresses in various formats */ unsigned char lladdr[ETH_ALEN]; struct in6_addr peer_addr; - - DECLARE_BITMAP(flags, LOWPAN_PEER_MAXBITS); }; struct lowpan_btle_dev { @@ -324,7 +317,6 @@ static int recv_pkt(struct sk_buff *skb, struct net_device *dev, local_skb->pkt_type = PACKET_HOST; local_skb->dev = dev; - skb_reset_mac_header(local_skb); skb_set_transport_header(local_skb, sizeof(struct ipv6hdr)); if (give_skb_to_upper(local_skb, dev) != NET_RX_SUCCESS) { @@ -993,11 +985,10 @@ static struct l2cap_chan *bt_6lowpan_listen(void) } static int get_l2cap_conn(char *buf, bdaddr_t *addr, u8 *addr_type, - struct l2cap_conn **conn, bool disconnect) + struct l2cap_conn **conn) { struct hci_conn *hcon; struct hci_dev *hdev; - int le_addr_type; int n; n = sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx %hhu", @@ -1008,32 +999,13 @@ static int get_l2cap_conn(char *buf, bdaddr_t *addr, u8 *addr_type, if (n < 7) return -EINVAL; - if (disconnect) { - /* The "disconnect" debugfs command has used different address - * type constants than "connect" since 2015. Let's retain that - * for now even though it's obviously buggy... - */ - *addr_type += 1; - } - - switch (*addr_type) { - case BDADDR_LE_PUBLIC: - le_addr_type = ADDR_LE_DEV_PUBLIC; - break; - case BDADDR_LE_RANDOM: - le_addr_type = ADDR_LE_DEV_RANDOM; - break; - default: - return -EINVAL; - } - /* The LE_PUBLIC address type is ignored because of BDADDR_ANY */ hdev = hci_get_route(addr, BDADDR_ANY, BDADDR_LE_PUBLIC); if (!hdev) return -ENOENT; hci_dev_lock(hdev); - hcon = hci_conn_hash_lookup_le(hdev, addr, le_addr_type); + hcon = hci_conn_hash_lookup_le(hdev, addr, *addr_type); hci_dev_unlock(hdev); hci_dev_put(hdev); @@ -1050,52 +1022,41 @@ static int get_l2cap_conn(char *buf, bdaddr_t *addr, u8 *addr_type, static void disconnect_all_peers(void) { struct lowpan_btle_dev *entry; - struct lowpan_peer *peer; - int nchans; + struct lowpan_peer *peer, *tmp_peer, *new_peer; + struct list_head peers; - /* l2cap_chan_close() cannot be called from RCU, and lock ordering - * chan->lock > devices_lock prevents taking write side lock, so copy - * then close. + INIT_LIST_HEAD(&peers); + + /* We make a separate list of peers as the close_cb() will + * modify the device peers list so it is better not to mess + * with the same list at the same time. */ rcu_read_lock(); - list_for_each_entry_rcu(entry, &bt_6lowpan_devices, list) - list_for_each_entry_rcu(peer, &entry->peers, list) - clear_bit(LOWPAN_PEER_CLOSING, peer->flags); + + list_for_each_entry_rcu(entry, &bt_6lowpan_devices, list) { + list_for_each_entry_rcu(peer, &entry->peers, list) { + new_peer = kmalloc(sizeof(*new_peer), GFP_ATOMIC); + if (!new_peer) + break; + + new_peer->chan = peer->chan; + INIT_LIST_HEAD(&new_peer->list); + + list_add(&new_peer->list, &peers); + } + } + rcu_read_unlock(); - do { - struct l2cap_chan *chans[32]; - int i; + spin_lock(&devices_lock); + list_for_each_entry_safe(peer, tmp_peer, &peers, list) { + l2cap_chan_close(peer->chan, ENOENT); - nchans = 0; - - spin_lock(&devices_lock); - - list_for_each_entry_rcu(entry, &bt_6lowpan_devices, list) { - list_for_each_entry_rcu(peer, &entry->peers, list) { - if (test_and_set_bit(LOWPAN_PEER_CLOSING, - peer->flags)) - continue; - - l2cap_chan_hold(peer->chan); - chans[nchans++] = peer->chan; - - if (nchans >= ARRAY_SIZE(chans)) - goto done; - } - } - -done: - spin_unlock(&devices_lock); - - for (i = 0; i < nchans; ++i) { - l2cap_chan_lock(chans[i]); - l2cap_chan_close(chans[i], ENOENT); - l2cap_chan_unlock(chans[i]); - l2cap_chan_put(chans[i]); - } - } while (nchans); + list_del_rcu(&peer->list); + kfree_rcu(peer, rcu); + } + spin_unlock(&devices_lock); } struct set_enable { @@ -1171,7 +1132,7 @@ static ssize_t lowpan_control_write(struct file *fp, buf[buf_size] = '\0'; if (memcmp(buf, "connect ", 8) == 0) { - ret = get_l2cap_conn(&buf[8], &addr, &addr_type, &conn, false); + ret = get_l2cap_conn(&buf[8], &addr, &addr_type, &conn); if (ret == -EINVAL) return ret; @@ -1208,7 +1169,7 @@ static ssize_t lowpan_control_write(struct file *fp, } if (memcmp(buf, "disconnect ", 11) == 0) { - ret = get_l2cap_conn(&buf[11], &addr, &addr_type, &conn, true); + ret = get_l2cap_conn(&buf[11], &addr, &addr_type, &conn); if (ret < 0) return ret; diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c index 4c82770173aa..1272ad73e401 100644 --- a/net/bluetooth/l2cap_core.c +++ b/net/bluetooth/l2cap_core.c @@ -517,7 +517,6 @@ void l2cap_chan_hold(struct l2cap_chan *c) kref_get(&c->kref); } -EXPORT_SYMBOL_GPL(l2cap_chan_hold); struct l2cap_chan *l2cap_chan_hold_unless_zero(struct l2cap_chan *c) { diff --git a/net/bluetooth/sco.c b/net/bluetooth/sco.c index dc99b5d985fd..4c81883ba25e 100644 --- a/net/bluetooth/sco.c +++ b/net/bluetooth/sco.c @@ -399,13 +399,6 @@ static void sco_sock_kill(struct sock *sk) BT_DBG("sk %p state %d", sk, sk->sk_state); - /* Sock is dead, so set conn->sk to NULL to avoid possible UAF */ - if (sco_pi(sk)->conn) { - sco_conn_lock(sco_pi(sk)->conn); - sco_pi(sk)->conn->sk = NULL; - sco_conn_unlock(sco_pi(sk)->conn); - } - /* Kill poor orphan */ bt_sock_unlink(&sco_sk_list, sk); sock_set_flag(sk, SOCK_DEAD); diff --git a/net/bpf/test_run.c b/net/bpf/test_run.c index f60109cff3a8..591d146a5308 100644 --- a/net/bpf/test_run.c +++ b/net/bpf/test_run.c @@ -10,84 +10,18 @@ #include #include #include -#include -#include #define CREATE_TRACE_POINTS #include -struct bpf_test_timer { - enum { NO_PREEMPT, NO_MIGRATE } mode; - u32 i; - u64 time_start, time_spent; -}; - -static void bpf_test_timer_enter(struct bpf_test_timer *t) - __acquires(rcu) -{ - rcu_read_lock(); - if (t->mode == NO_PREEMPT) - preempt_disable(); - else - migrate_disable(); - - t->time_start = ktime_get_ns(); -} - -static void bpf_test_timer_leave(struct bpf_test_timer *t) - __releases(rcu) -{ - t->time_start = 0; - - if (t->mode == NO_PREEMPT) - preempt_enable(); - else - migrate_enable(); - rcu_read_unlock(); -} - -static bool bpf_test_timer_continue(struct bpf_test_timer *t, u32 repeat, int *err, u32 *duration) - __must_hold(rcu) -{ - t->i++; - if (t->i >= repeat) { - /* We're done. */ - t->time_spent += ktime_get_ns() - t->time_start; - do_div(t->time_spent, t->i); - *duration = t->time_spent > U32_MAX ? U32_MAX : (u32)t->time_spent; - *err = 0; - goto reset; - } - - if (signal_pending(current)) { - /* During iteration: we've been cancelled, abort. */ - *err = -EINTR; - goto reset; - } - - if (need_resched()) { - /* During iteration: we need to reschedule between runs. */ - t->time_spent += ktime_get_ns() - t->time_start; - bpf_test_timer_leave(t); - cond_resched(); - bpf_test_timer_enter(t); - } - - /* Do another round. */ - return true; - -reset: - t->i = 0; - return false; -} - static int bpf_test_run(struct bpf_prog *prog, void *ctx, u32 repeat, - u32 *retval, u32 *time, bool xdp) + u32 *retval, u32 *time) { struct bpf_cgroup_storage *storage[MAX_BPF_CGROUP_STORAGE_TYPE] = { NULL }; - struct bpf_test_timer t = { NO_MIGRATE }; enum bpf_cgroup_storage_type stype; - int ret; + u64 time_start, time_spent = 0; + int ret = 0; + u32 i; for_each_cgroup_storage_type(stype) { storage[stype] = bpf_cgroup_storage_alloc(prog, stype); @@ -102,21 +36,36 @@ static int bpf_test_run(struct bpf_prog *prog, void *ctx, u32 repeat, if (!repeat) repeat = 1; - bpf_test_timer_enter(&t); - do { - ret = bpf_cgroup_storage_set(storage); - if (ret) + rcu_read_lock(); + preempt_disable(); + time_start = ktime_get_ns(); + for (i = 0; i < repeat; i++) { + bpf_cgroup_storage_set(storage); + *retval = BPF_PROG_RUN(prog, ctx); + + if (signal_pending(current)) { + ret = -EINTR; break; + } - if (xdp) - *retval = bpf_prog_run_xdp(prog, ctx); - else - *retval = BPF_PROG_RUN(prog, ctx); + if (need_resched()) { + time_spent += ktime_get_ns() - time_start; + preempt_enable(); + rcu_read_unlock(); - bpf_cgroup_storage_unset(); + cond_resched(); - } while (bpf_test_timer_continue(&t, repeat, &ret, time)); - bpf_test_timer_leave(&t); + rcu_read_lock(); + preempt_disable(); + time_start = ktime_get_ns(); + } + } + time_spent += ktime_get_ns() - time_start; + preempt_enable(); + rcu_read_unlock(); + + do_div(time_spent, repeat); + *time = time_spent > U32_MAX ? U32_MAX : (u32)time_spent; for_each_cgroup_storage_type(stype) bpf_cgroup_storage_free(storage[stype]); @@ -156,215 +105,27 @@ out: return err; } -/* Integer types of various sizes and pointer combinations cover variety of - * architecture dependent calling conventions. 7+ can be supported in the - * future. - */ -__diag_push(); -__diag_ignore(GCC, 8, "-Wmissing-prototypes", - "Global functions as their definitions will be in vmlinux BTF"); -int noinline bpf_fentry_test1(int a) -{ - return a + 1; -} - -int noinline bpf_fentry_test2(int a, u64 b) -{ - return a + b; -} - -int noinline bpf_fentry_test3(char a, int b, u64 c) -{ - return a + b + c; -} - -int noinline bpf_fentry_test4(void *a, char b, int c, u64 d) -{ - return (long)a + b + c + d; -} - -int noinline bpf_fentry_test5(u64 a, void *b, short c, int d, u64 e) -{ - return a + (long)b + c + d + e; -} - -int noinline bpf_fentry_test6(u64 a, void *b, short c, int d, void *e, u64 f) -{ - return a + (long)b + c + d + (long)e + f; -} - -struct bpf_fentry_test_t { - struct bpf_fentry_test_t *a; -}; - -int noinline bpf_fentry_test7(struct bpf_fentry_test_t *arg) -{ - return (long)arg; -} - -int noinline bpf_fentry_test8(struct bpf_fentry_test_t *arg) -{ - return (long)arg->a; -} - -int noinline bpf_modify_return_test(int a, int *b) -{ - *b += 1; - return a + *b; -} -__diag_pop(); - -ALLOW_ERROR_INJECTION(bpf_modify_return_test, ERRNO); - static void *bpf_test_init(const union bpf_attr *kattr, u32 size, u32 headroom, u32 tailroom) { void __user *data_in = u64_to_user_ptr(kattr->test.data_in); - u32 user_size = kattr->test.data_size_in; void *data; if (size < ETH_HLEN || size > PAGE_SIZE - headroom - tailroom) return ERR_PTR(-EINVAL); - if (user_size > size) - return ERR_PTR(-EMSGSIZE); - size = SKB_DATA_ALIGN(size); data = kzalloc(size + headroom + tailroom, GFP_USER); if (!data) return ERR_PTR(-ENOMEM); - if (copy_from_user(data + headroom, data_in, user_size)) { + if (copy_from_user(data + headroom, data_in, size)) { kfree(data); return ERR_PTR(-EFAULT); } - return data; } -int bpf_prog_test_run_tracing(struct bpf_prog *prog, - const union bpf_attr *kattr, - union bpf_attr __user *uattr) -{ - struct bpf_fentry_test_t arg = {}; - u16 side_effect = 0, ret = 0; - int b = 2, err = -EFAULT; - u32 retval = 0; - - if (kattr->test.flags || kattr->test.cpu) - return -EINVAL; - - switch (prog->expected_attach_type) { - case BPF_TRACE_FENTRY: - case BPF_TRACE_FEXIT: - if (bpf_fentry_test1(1) != 2 || - bpf_fentry_test2(2, 3) != 5 || - bpf_fentry_test3(4, 5, 6) != 15 || - bpf_fentry_test4((void *)7, 8, 9, 10) != 34 || - bpf_fentry_test5(11, (void *)12, 13, 14, 15) != 65 || - bpf_fentry_test6(16, (void *)17, 18, 19, (void *)20, 21) != 111 || - bpf_fentry_test7((struct bpf_fentry_test_t *)0) != 0 || - bpf_fentry_test8(&arg) != 0) - goto out; - break; - case BPF_MODIFY_RETURN: - ret = bpf_modify_return_test(1, &b); - if (b != 2) - side_effect = 1; - break; - default: - goto out; - } - - retval = ((u32)side_effect << 16) | ret; - if (copy_to_user(&uattr->test.retval, &retval, sizeof(retval))) - goto out; - - err = 0; -out: - trace_bpf_test_finish(&err); - return err; -} - -struct bpf_raw_tp_test_run_info { - struct bpf_prog *prog; - void *ctx; - u32 retval; -}; - -static void -__bpf_prog_test_run_raw_tp(void *data) -{ - struct bpf_raw_tp_test_run_info *info = data; - - rcu_read_lock(); - info->retval = BPF_PROG_RUN(info->prog, info->ctx); - rcu_read_unlock(); -} - -int bpf_prog_test_run_raw_tp(struct bpf_prog *prog, - const union bpf_attr *kattr, - union bpf_attr __user *uattr) -{ - void __user *ctx_in = u64_to_user_ptr(kattr->test.ctx_in); - __u32 ctx_size_in = kattr->test.ctx_size_in; - struct bpf_raw_tp_test_run_info info; - int cpu = kattr->test.cpu, err = 0; - int current_cpu; - - /* doesn't support data_in/out, ctx_out, duration, or repeat */ - if (kattr->test.data_in || kattr->test.data_out || - kattr->test.ctx_out || kattr->test.duration || - kattr->test.repeat) - return -EINVAL; - - if (ctx_size_in < prog->aux->max_ctx_offset || - ctx_size_in > MAX_BPF_FUNC_ARGS * sizeof(u64)) - return -EINVAL; - - if ((kattr->test.flags & BPF_F_TEST_RUN_ON_CPU) == 0 && cpu != 0) - return -EINVAL; - - if (ctx_size_in) { - info.ctx = kzalloc(ctx_size_in, GFP_USER); - if (!info.ctx) - return -ENOMEM; - if (copy_from_user(info.ctx, ctx_in, ctx_size_in)) { - err = -EFAULT; - goto out; - } - } else { - info.ctx = NULL; - } - - info.prog = prog; - - current_cpu = get_cpu(); - if ((kattr->test.flags & BPF_F_TEST_RUN_ON_CPU) == 0 || - cpu == current_cpu) { - __bpf_prog_test_run_raw_tp(&info); - } else if (cpu >= nr_cpu_ids || !cpu_online(cpu)) { - /* smp_call_function_single() also checks cpu_online() - * after csd_lock(). However, since cpu is from user - * space, let's do an extra quick check to filter out - * invalid value before smp_call_function_single(). - */ - err = -ENXIO; - } else { - err = smp_call_function_single(cpu, __bpf_prog_test_run_raw_tp, - &info, 1); - } - put_cpu(); - - if (!err && - copy_to_user(&uattr->test.retval, &info.retval, sizeof(u32))) - err = -EFAULT; - -out: - kfree(info.ctx); - return err; -} - static void *bpf_ctx_init(const union bpf_attr *kattr, u32 max_size) { void __user *data_in = u64_to_user_ptr(kattr->test.ctx_in); @@ -444,66 +205,26 @@ static int convert___skb_to_skb(struct sk_buff *skb, struct __sk_buff *__skb) return 0; /* make sure the fields we don't use are zeroed */ - if (!range_is_zero(__skb, 0, offsetof(struct __sk_buff, mark))) - return -EINVAL; - - /* mark is allowed */ - - if (!range_is_zero(__skb, offsetofend(struct __sk_buff, mark), - offsetof(struct __sk_buff, priority))) + if (!range_is_zero(__skb, 0, offsetof(struct __sk_buff, priority))) return -EINVAL; /* priority is allowed */ - if (!range_is_zero(__skb, offsetofend(struct __sk_buff, priority), - offsetof(struct __sk_buff, ifindex))) - return -EINVAL; - - /* ifindex is allowed */ - - if (!range_is_zero(__skb, offsetofend(struct __sk_buff, ifindex), + if (!range_is_zero(__skb, offsetof(struct __sk_buff, priority) + + FIELD_SIZEOF(struct __sk_buff, priority), offsetof(struct __sk_buff, cb))) return -EINVAL; /* cb is allowed */ - if (!range_is_zero(__skb, offsetofend(struct __sk_buff, cb), - offsetof(struct __sk_buff, tstamp))) - return -EINVAL; - - /* tstamp is allowed */ - /* wire_len is allowed */ - /* gso_segs is allowed */ - - if (!range_is_zero(__skb, offsetofend(struct __sk_buff, gso_segs), - offsetof(struct __sk_buff, gso_size))) - return -EINVAL; - - /* gso_size is allowed */ - - if (!range_is_zero(__skb, offsetofend(struct __sk_buff, gso_size), + if (!range_is_zero(__skb, offsetof(struct __sk_buff, cb) + + FIELD_SIZEOF(struct __sk_buff, cb), sizeof(struct __sk_buff))) return -EINVAL; - skb->mark = __skb->mark; skb->priority = __skb->priority; - skb->tstamp = __skb->tstamp; memcpy(&cb->data, __skb->cb, QDISC_CB_PRIV_LEN); - if (__skb->wire_len == 0) { - cb->pkt_len = skb->len; - } else { - if (__skb->wire_len < skb->len || - __skb->wire_len > GSO_MAX_SIZE) - return -EINVAL; - cb->pkt_len = __skb->wire_len; - } - - if (__skb->gso_segs > GSO_MAX_SEGS) - return -EINVAL; - skb_shinfo(skb)->gso_segs = __skb->gso_segs; - skb_shinfo(skb)->gso_size = __skb->gso_size; - return 0; } @@ -514,27 +235,14 @@ static void convert_skb_to___skb(struct sk_buff *skb, struct __sk_buff *__skb) if (!__skb) return; - __skb->mark = skb->mark; __skb->priority = skb->priority; - __skb->ifindex = skb->dev->ifindex; - __skb->tstamp = skb->tstamp; memcpy(__skb->cb, &cb->data, QDISC_CB_PRIV_LEN); - __skb->wire_len = cb->pkt_len; - __skb->gso_segs = skb_shinfo(skb)->gso_segs; } -static struct proto bpf_dummy_proto = { - .name = "bpf_dummy", - .owner = THIS_MODULE, - .obj_size = sizeof(struct sock), -}; - int bpf_prog_test_run_skb(struct bpf_prog *prog, const union bpf_attr *kattr, union bpf_attr __user *uattr) { bool is_l2 = false, is_direct_pkt_access = false; - struct net *net = current->nsproxy->net_ns; - struct net_device *dev = net->loopback_dev; u32 size = kattr->test.data_size_in; u32 repeat = kattr->test.repeat; struct __sk_buff *ctx = NULL; @@ -545,9 +253,6 @@ int bpf_prog_test_run_skb(struct bpf_prog *prog, const union bpf_attr *kattr, void *data; int ret; - if (kattr->test.flags || kattr->test.cpu) - return -EINVAL; - data = bpf_test_init(kattr, size, NET_SKB_PAD + NET_IP_ALIGN, SKB_DATA_ALIGN(sizeof(struct skb_shared_info))); if (IS_ERR(data)) @@ -573,56 +278,29 @@ int bpf_prog_test_run_skb(struct bpf_prog *prog, const union bpf_attr *kattr, break; } - sk = sk_alloc(net, AF_UNSPEC, GFP_USER, &bpf_dummy_proto, 1); + sk = kzalloc(sizeof(struct sock), GFP_USER); if (!sk) { kfree(data); kfree(ctx); return -ENOMEM; } + sock_net_set(sk, current->nsproxy->net_ns); sock_init_data(NULL, sk); skb = build_skb(data, 0); if (!skb) { kfree(data); kfree(ctx); - sk_free(sk); + kfree(sk); return -ENOMEM; } skb->sk = sk; skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); __skb_put(skb, size); - if (ctx && ctx->ifindex > 1) { - dev = dev_get_by_index(net, ctx->ifindex); - if (!dev) { - ret = -ENODEV; - goto out; - } - } - skb->protocol = eth_type_trans(skb, dev); + skb->protocol = eth_type_trans(skb, current->nsproxy->net_ns->loopback_dev); skb_reset_network_header(skb); - switch (skb->protocol) { - case htons(ETH_P_IP): - sk->sk_family = AF_INET; - if (sizeof(struct iphdr) <= skb_headlen(skb)) { - sk->sk_rcv_saddr = ip_hdr(skb)->saddr; - sk->sk_daddr = ip_hdr(skb)->daddr; - } - break; -#if IS_ENABLED(CONFIG_IPV6) - case htons(ETH_P_IPV6): - sk->sk_family = AF_INET6; - if (sizeof(struct ipv6hdr) <= skb_headlen(skb)) { - sk->sk_v6_rcv_saddr = ipv6_hdr(skb)->saddr; - sk->sk_v6_daddr = ipv6_hdr(skb)->daddr; - } - break; -#endif - default: - break; - } - if (is_l2) __skb_push(skb, hh_len); if (is_direct_pkt_access) @@ -630,7 +308,7 @@ int bpf_prog_test_run_skb(struct bpf_prog *prog, const union bpf_attr *kattr, ret = convert___skb_to_skb(skb, ctx); if (ret) goto out; - ret = bpf_test_run(prog, skb, repeat, &retval, &duration, false); + ret = bpf_test_run(prog, skb, repeat, &retval, &duration); if (ret) goto out; if (!is_l2) { @@ -655,10 +333,9 @@ int bpf_prog_test_run_skb(struct bpf_prog *prog, const union bpf_attr *kattr, ret = bpf_ctx_finish(kattr, uattr, ctx, sizeof(struct __sk_buff)); out: - if (dev && dev != net->loopback_dev) - dev_put(dev); kfree_skb(skb); - sk_free(sk); + bpf_sk_storage_free(sk); + kfree(sk); kfree(ctx); return ret; } @@ -666,47 +343,37 @@ out: int bpf_prog_test_run_xdp(struct bpf_prog *prog, const union bpf_attr *kattr, union bpf_attr __user *uattr) { - u32 tailroom = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); - u32 headroom = XDP_PACKET_HEADROOM; u32 size = kattr->test.data_size_in; u32 repeat = kattr->test.repeat; struct netdev_rx_queue *rxqueue; struct xdp_buff xdp = {}; u32 retval, duration; - u32 max_data_sz; void *data; int ret; - if (prog->expected_attach_type == BPF_XDP_DEVMAP || - prog->expected_attach_type == BPF_XDP_CPUMAP) - return -EINVAL; if (kattr->test.ctx_in || kattr->test.ctx_out) return -EINVAL; - /* XDP have extra tailroom as (most) drivers use full page */ - max_data_sz = 4096 - headroom - tailroom; - - data = bpf_test_init(kattr, max_data_sz, headroom, tailroom); + data = bpf_test_init(kattr, size, XDP_PACKET_HEADROOM + NET_IP_ALIGN, 0); if (IS_ERR(data)) return PTR_ERR(data); xdp.data_hard_start = data; - xdp.data = data + headroom; + xdp.data = data + XDP_PACKET_HEADROOM + NET_IP_ALIGN; xdp.data_meta = xdp.data; xdp.data_end = xdp.data + size; - xdp.frame_sz = headroom + max_data_sz + tailroom; rxqueue = __netif_get_rx_queue(current->nsproxy->net_ns->loopback_dev, 0); xdp.rxq = &rxqueue->xdp_rxq; - bpf_prog_change_xdp(NULL, prog); - ret = bpf_test_run(prog, &xdp, repeat, &retval, &duration, true); + + ret = bpf_test_run(prog, &xdp, repeat, &retval, &duration); if (ret) goto out; - if (xdp.data != data + headroom || xdp.data_end != xdp.data + size) + if (xdp.data != data + XDP_PACKET_HEADROOM + NET_IP_ALIGN || + xdp.data_end != xdp.data + size) size = xdp.data_end - xdp.data; ret = bpf_test_finish(kattr, uattr, xdp.data, size, retval, duration); out: - bpf_prog_change_xdp(prog, NULL); kfree(data); return ret; } @@ -719,7 +386,8 @@ static int verify_user_bpf_flow_keys(struct bpf_flow_keys *ctx) /* flags is allowed */ - if (!range_is_zero(ctx, offsetofend(struct bpf_flow_keys, flags), + if (!range_is_zero(ctx, offsetof(struct bpf_flow_keys, flags) + + FIELD_SIZEOF(struct bpf_flow_keys, flags), sizeof(struct bpf_flow_keys))) return -EINVAL; @@ -730,24 +398,22 @@ int bpf_prog_test_run_flow_dissector(struct bpf_prog *prog, const union bpf_attr *kattr, union bpf_attr __user *uattr) { - struct bpf_test_timer t = { NO_PREEMPT }; u32 size = kattr->test.data_size_in; struct bpf_flow_dissector ctx = {}; u32 repeat = kattr->test.repeat; struct bpf_flow_keys *user_ctx; struct bpf_flow_keys flow_keys; + u64 time_start, time_spent = 0; const struct ethhdr *eth; unsigned int flags = 0; u32 retval, duration; void *data; int ret; + u32 i; if (prog->type != BPF_PROG_TYPE_FLOW_DISSECTOR) return -EINVAL; - if (kattr->test.flags || kattr->test.cpu) - return -EINVAL; - if (size < ETH_HLEN) return -EINVAL; @@ -776,15 +442,39 @@ int bpf_prog_test_run_flow_dissector(struct bpf_prog *prog, ctx.data = data; ctx.data_end = (__u8 *)data + size; - bpf_test_timer_enter(&t); - do { + rcu_read_lock(); + preempt_disable(); + time_start = ktime_get_ns(); + for (i = 0; i < repeat; i++) { retval = bpf_flow_dissect(prog, &ctx, eth->h_proto, ETH_HLEN, size, flags); - } while (bpf_test_timer_continue(&t, repeat, &ret, &duration)); - bpf_test_timer_leave(&t); - if (ret < 0) - goto out; + if (signal_pending(current)) { + preempt_enable(); + rcu_read_unlock(); + + ret = -EINTR; + goto out; + } + + if (need_resched()) { + time_spent += ktime_get_ns() - time_start; + preempt_enable(); + rcu_read_unlock(); + + cond_resched(); + + rcu_read_lock(); + preempt_disable(); + time_start = ktime_get_ns(); + } + } + time_spent += ktime_get_ns() - time_start; + preempt_enable(); + rcu_read_unlock(); + + do_div(time_spent, repeat); + duration = time_spent > U32_MAX ? U32_MAX : (u32)time_spent; ret = bpf_test_finish(kattr, uattr, &flow_keys, sizeof(flow_keys), retval, duration); diff --git a/net/bpfilter/Kconfig b/net/bpfilter/Kconfig index 8ad0233ce497..045144d4a42c 100644 --- a/net/bpfilter/Kconfig +++ b/net/bpfilter/Kconfig @@ -2,7 +2,6 @@ menuconfig BPFILTER bool "BPF based packet filtering framework (BPFILTER)" depends on NET && BPF && INET - select USERMODE_DRIVER help This builds experimental bpfilter framework that is aiming to provide netfilter compatible functionality via BPF @@ -10,14 +9,8 @@ menuconfig BPFILTER if BPFILTER config BPFILTER_UMH tristate "bpfilter kernel module with user mode helper" - depends on CC_CAN_LINK - depends on m || CC_CAN_LINK_STATIC + depends on CC_CAN_LINK_STATIC default m help This builds bpfilter kernel module with embedded user mode helper - - Note: To compile this as built-in, your toolchain must support - building static binaries, since rootfs isn't mounted at the time - when __init functions are called and do_execv won't be able to find - the elf interpreter. endif diff --git a/net/bpfilter/Makefile b/net/bpfilter/Makefile index cdac82b8c53a..05930c2fafd5 100644 --- a/net/bpfilter/Makefile +++ b/net/bpfilter/Makefile @@ -3,15 +3,17 @@ # Makefile for the Linux BPFILTER layer. # -userprogs := bpfilter_umh +hostprogs-y := bpfilter_umh bpfilter_umh-objs := main.o -userccflags += -I $(srctree)/tools/include/ -I $(srctree)/tools/include/uapi +KBUILD_HOSTCFLAGS += -I $(srctree)/tools/include/ -I $(srctree)/tools/include/uapi \ + $(filter -m32 -m64, $(KBUILD_CFLAGS)) +HOSTCC := $(CC) ifeq ($(CONFIG_BPFILTER_UMH), y) -# builtin bpfilter_umh should be linked with -static +# builtin bpfilter_umh should be compiled with -static # since rootfs isn't mounted at the time of __init # function is called and do_execv won't find elf interpreter -userldflags += -static +KBUILD_HOSTLDFLAGS += -static $(filter -m32 -m64, $(KBUILD_CFLAGS)) endif $(obj)/bpfilter_umh_blob.o: $(obj)/bpfilter_umh diff --git a/net/bpfilter/bpfilter_kern.c b/net/bpfilter/bpfilter_kern.c index 51a941b56ec3..c0f0990f30b6 100644 --- a/net/bpfilter/bpfilter_kern.c +++ b/net/bpfilter/bpfilter_kern.c @@ -15,13 +15,15 @@ extern char bpfilter_umh_end; static void shutdown_umh(void) { - struct umd_info *info = &bpfilter_ops.info; - struct pid *tgid = info->tgid; + struct task_struct *tsk; - if (tgid) { - kill_pid(tgid, SIGKILL, 1); - wait_event(tgid->wait_pidfd, thread_group_exited(tgid)); - bpfilter_umh_cleanup(info); + if (bpfilter_ops.stop) + return; + + tsk = get_pid_task(find_vpid(bpfilter_ops.info.pid), PIDTYPE_PID); + if (tsk) { + send_sig(SIGKILL, tsk, 1); + put_task_struct(tsk); } } @@ -31,65 +33,60 @@ static void __stop_umh(void) shutdown_umh(); } -static int bpfilter_send_req(struct mbox_request *req) +static int __bpfilter_process_sockopt(struct sock *sk, int optname, + char __user *optval, + unsigned int optlen, bool is_set) { + struct mbox_request req; struct mbox_reply reply; - loff_t pos = 0; + loff_t pos; ssize_t n; + int ret = -EFAULT; - if (!bpfilter_ops.info.tgid) - return -EFAULT; - pos = 0; - n = kernel_write(bpfilter_ops.info.pipe_to_umh, req, sizeof(*req), + req.is_set = is_set; + req.pid = current->pid; + req.cmd = optname; + req.addr = (long __force __user)optval; + req.len = optlen; + if (!bpfilter_ops.info.pid) + goto out; + n = __kernel_write(bpfilter_ops.info.pipe_to_umh, &req, sizeof(req), &pos); - if (n != sizeof(*req)) { + if (n != sizeof(req)) { pr_err("write fail %zd\n", n); - goto stop; + __stop_umh(); + ret = -EFAULT; + goto out; } pos = 0; n = kernel_read(bpfilter_ops.info.pipe_from_umh, &reply, sizeof(reply), &pos); if (n != sizeof(reply)) { pr_err("read fail %zd\n", n); - goto stop; + __stop_umh(); + ret = -EFAULT; + goto out; } - return reply.status; -stop: - __stop_umh(); - return -EFAULT; -} - -static int bpfilter_process_sockopt(struct sock *sk, int optname, - sockptr_t optval, unsigned int optlen, - bool is_set) -{ - struct mbox_request req = { - .is_set = is_set, - .pid = current->pid, - .cmd = optname, - .addr = (uintptr_t)optval.user, - .len = optlen, - }; - if (uaccess_kernel() || sockptr_is_kernel(optval)) { - pr_err("kernel access not supported\n"); - return -EFAULT; - } - return bpfilter_send_req(&req); + ret = reply.status; +out: + return ret; } static int start_umh(void) { - struct mbox_request req = { .pid = current->pid }; int err; /* fork usermode process */ - err = fork_usermode_driver(&bpfilter_ops.info); + err = fork_usermode_blob(&bpfilter_umh_start, + &bpfilter_umh_end - &bpfilter_umh_start, + &bpfilter_ops.info); if (err) return err; - pr_info("Loaded bpfilter_umh pid %d\n", pid_nr(bpfilter_ops.info.tgid)); + bpfilter_ops.stop = false; + pr_info("Loaded bpfilter_umh pid %d\n", bpfilter_ops.info.pid); /* health check that usermode process started correctly */ - if (bpfilter_send_req(&req) != 0) { + if (__bpfilter_process_sockopt(NULL, 0, NULL, 0, 0) != 0) { shutdown_umh(); return -EFAULT; } @@ -101,21 +98,18 @@ static int __init load_umh(void) { int err; - err = umd_load_blob(&bpfilter_ops.info, - &bpfilter_umh_start, - &bpfilter_umh_end - &bpfilter_umh_start); - if (err) - return err; - mutex_lock(&bpfilter_ops.lock); + if (!bpfilter_ops.stop) { + err = -EFAULT; + goto out; + } err = start_umh(); if (!err && IS_ENABLED(CONFIG_INET)) { - bpfilter_ops.sockopt = &bpfilter_process_sockopt; + bpfilter_ops.sockopt = &__bpfilter_process_sockopt; bpfilter_ops.start = &start_umh; } +out: mutex_unlock(&bpfilter_ops.lock); - if (err) - umd_unload_blob(&bpfilter_ops.info); return err; } @@ -128,8 +122,6 @@ static void __exit fini_umh(void) bpfilter_ops.sockopt = NULL; } mutex_unlock(&bpfilter_ops.lock); - - umd_unload_blob(&bpfilter_ops.info); } module_init(load_umh); module_exit(fini_umh); diff --git a/net/bpfilter/bpfilter_umh_blob.S b/net/bpfilter/bpfilter_umh_blob.S index 40311d10d2f2..9ea6100dca87 100644 --- a/net/bpfilter/bpfilter_umh_blob.S +++ b/net/bpfilter/bpfilter_umh_blob.S @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ - .section .init.rodata, "a" + .section .rodata, "a" .global bpfilter_umh_start bpfilter_umh_start: .incbin "net/bpfilter/bpfilter_umh" diff --git a/net/bridge/br_device.c b/net/bridge/br_device.c index ec4dee64357b..00438505c175 100644 --- a/net/bridge/br_device.c +++ b/net/bridge/br_device.c @@ -34,10 +34,6 @@ netdev_tx_t br_dev_xmit(struct sk_buff *skb, struct net_device *dev) const struct nf_br_ops *nf_ops; const unsigned char *dest; u16 vid = 0; -#ifdef CONFIG_HYFI_BRIDGE_HOOKS - struct net_bridge_port *pdst; - br_get_dst_hook_t *get_dst_hook; -#endif if (unlikely(!pskb_may_pull(skb, ETH_HLEN))) { kfree_skb(skb); @@ -86,10 +82,6 @@ netdev_tx_t br_dev_xmit(struct sk_buff *skb, struct net_device *dev) br_do_suppress_nd(skb, br, vid, NULL, msg); } -#ifdef CONFIG_HYFI_BRIDGE_HOOKS - get_dst_hook = rcu_dereference(br_get_dst_hook); -#endif - dest = eth_hdr(skb)->h_dest; if (is_broadcast_ether_addr(dest)) { br_flood(br, skb, BR_PKT_BROADCAST, false, true); @@ -115,24 +107,11 @@ netdev_tx_t br_dev_xmit(struct sk_buff *skb, struct net_device *dev) br_multicast_flood(mdst, skb, false, true); else br_flood(br, skb, BR_PKT_MULTICAST, false, true); + } else if ((dst = br_fdb_find_rcu(br, dest, vid)) != NULL) { + br_forward(dst->dst, skb, false, true); } else { -#ifdef CONFIG_HYFI_BRIDGE_HOOKS - pdst = __br_get(get_dst_hook, NULL, NULL, &skb); - if (pdst) { - if (!skb) - goto out; - br_forward(pdst, skb, false, true); - } else -#endif - { - dst = br_fdb_find_rcu(br, dest, vid); - if (dst) - br_forward(dst->dst, skb, false, true); - else - br_flood(br, skb, BR_PKT_UNICAST, false, true); - } + br_flood(br, skb, BR_PKT_UNICAST, false, true); } - out: rcu_read_unlock(); return NETDEV_TX_OK; diff --git a/net/bridge/br_forward.c b/net/bridge/br_forward.c index 0e268272a66f..bcb820391f30 100644 --- a/net/bridge/br_forward.c +++ b/net/bridge/br_forward.c @@ -142,8 +142,7 @@ void br_forward(const struct net_bridge_port *to, goto out; /* redirect to backup link if the destination port is down */ - if (rcu_access_pointer(to->backup_port) && - (!netif_carrier_ok(to->dev) || !netif_running(to->dev))) { + if (rcu_access_pointer(to->backup_port) && !netif_carrier_ok(to->dev)) { struct net_bridge_port *backup_port; backup_port = rcu_dereference(to->backup_port); diff --git a/net/bridge/br_if.c b/net/bridge/br_if.c index a5565b7dfb06..ea0ddd513cc1 100644 --- a/net/bridge/br_if.c +++ b/net/bridge/br_if.c @@ -695,7 +695,6 @@ int br_add_if(struct net_bridge *br, struct net_device *dev, br_set_gso_limits(br); kobject_uevent(&p->kobj, KOBJ_ADD); - call_netdevice_notifiers(NETDEV_BR_JOIN, dev); return 0; @@ -733,8 +732,6 @@ int br_del_if(struct net_bridge *br, struct net_device *dev) if (!p || p->br != br) return -EINVAL; - call_netdevice_notifiers(NETDEV_BR_LEAVE, dev); - /* Since more than one interface can be attached to a bridge, * there still maybe an alternate path for netconsole to use; * therefore there is no reason for a NETDEV_RELEASE event. diff --git a/net/bridge/br_input.c b/net/bridge/br_input.c index 02dbaf13f591..ace461e94830 100644 --- a/net/bridge/br_input.c +++ b/net/bridge/br_input.c @@ -33,11 +33,6 @@ br_netif_receive_skb(struct net *net, struct sock *sk, struct sk_buff *skb) /* Hook for external Multicast handler */ br_multicast_handle_hook_t __rcu *br_multicast_handle_hook __read_mostly; EXPORT_SYMBOL(br_multicast_handle_hook); - -/* Hook for external forwarding logic */ -br_get_dst_hook_t __rcu *br_get_dst_hook __read_mostly; -EXPORT_SYMBOL_GPL(br_get_dst_hook); - #endif int br_pass_frame_up(struct sk_buff *skb) @@ -99,8 +94,6 @@ int br_handle_frame_finish(struct net *net, struct sock *sk, struct sk_buff *skb struct net_bridge *br; #ifdef CONFIG_HYFI_BRIDGE_HOOKS br_multicast_handle_hook_t *multicast_handle_hook; - struct net_bridge_port *pdst = NULL; - br_get_dst_hook_t *get_dst_hook = rcu_dereference(br_get_dst_hook); #endif u16 vid = 0; @@ -175,17 +168,7 @@ int br_handle_frame_finish(struct net *net, struct sock *sk, struct sk_buff *skb } break; case BR_PKT_UNICAST: -#ifdef CONFIG_HYFI_BRIDGE_HOOKS - pdst = __br_get(get_dst_hook, NULL, p, &skb); - if (pdst) { - if (!skb) - goto out; - } else -#endif - { - dst = br_fdb_find_rcu(br, eth_hdr(skb)->h_dest, vid); - } - break; + dst = br_fdb_find_rcu(br, eth_hdr(skb)->h_dest, vid); default: break; } diff --git a/net/bridge/br_netfilter_hooks.c b/net/bridge/br_netfilter_hooks.c index 4f867aca6300..a16559140541 100644 --- a/net/bridge/br_netfilter_hooks.c +++ b/net/bridge/br_netfilter_hooks.c @@ -1057,7 +1057,7 @@ int br_nf_hook_thresh(unsigned int hook, struct net *net, #ifdef CONFIG_SYSCTL static int brnf_sysctl_call_tables(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int ret; diff --git a/net/bridge/br_private.h b/net/bridge/br_private.h index 023ecc1f4494..c7130fff57a0 100644 --- a/net/bridge/br_private.h +++ b/net/bridge/br_private.h @@ -195,9 +195,6 @@ struct net_bridge_fdb_entry { struct net_bridge_fdb_key key; struct hlist_node fdb_node; - unsigned char is_local:1, - is_static:1; - unsigned long flags; unsigned char offloaded:1; diff --git a/net/bridge/netfilter/ebtables.c b/net/bridge/netfilter/ebtables.c index 5b843f84a4ef..f6853fc0fcc0 100644 --- a/net/bridge/netfilter/ebtables.c +++ b/net/bridge/netfilter/ebtables.c @@ -1096,14 +1096,16 @@ static int do_replace(struct net *net, const void __user *user, tmp.name[sizeof(tmp.name) - 1] = 0; countersize = COUNTER_OFFSET(tmp.nentries) * nr_cpu_ids; - newinfo = __vmalloc(sizeof(*newinfo) + countersize, GFP_KERNEL_ACCOUNT); + newinfo = __vmalloc(sizeof(*newinfo) + countersize, GFP_KERNEL_ACCOUNT, + PAGE_KERNEL); if (!newinfo) return -ENOMEM; if (countersize) memset(newinfo->counters, 0, countersize); - newinfo->entries = __vmalloc(tmp.entries_size, GFP_KERNEL_ACCOUNT); + newinfo->entries = __vmalloc(tmp.entries_size, GFP_KERNEL_ACCOUNT, + PAGE_KERNEL); if (!newinfo->entries) { ret = -ENOMEM; goto free_newinfo; diff --git a/net/compat.c b/net/compat.c index e7a873422ec3..f5b88166c44a 100644 --- a/net/compat.c +++ b/net/compat.c @@ -318,6 +318,49 @@ void scm_detach_fds_compat(struct msghdr *kmsg, struct scm_cookie *scm) __scm_destroy(scm); } +/* allocate a 64-bit sock_fprog on the user stack for duration of syscall. */ +struct sock_fprog __user *get_compat_bpf_fprog(char __user *optval) +{ + struct compat_sock_fprog __user *fprog32 = (struct compat_sock_fprog __user *)optval; + struct sock_fprog __user *kfprog = compat_alloc_user_space(sizeof(struct sock_fprog)); + struct compat_sock_fprog f32; + struct sock_fprog f; + + if (copy_from_user(&f32, fprog32, sizeof(*fprog32))) + return NULL; + memset(&f, 0, sizeof(f)); + f.len = f32.len; + f.filter = compat_ptr(f32.filter); + if (copy_to_user(kfprog, &f, sizeof(struct sock_fprog))) + return NULL; + + return kfprog; +} +EXPORT_SYMBOL_GPL(get_compat_bpf_fprog); + +static int do_set_attach_filter(struct socket *sock, int level, int optname, + char __user *optval, unsigned int optlen) +{ + struct sock_fprog __user *kfprog; + + kfprog = get_compat_bpf_fprog(optval); + if (!kfprog) + return -EFAULT; + + return sock_setsockopt(sock, level, optname, (char __user *)kfprog, + sizeof(struct sock_fprog)); +} + +static int compat_sock_setsockopt(struct socket *sock, int level, int optname, + char __user *optval, unsigned int optlen) +{ + if (optname == SO_ATTACH_FILTER || + optname == SO_ATTACH_REUSEPORT_CBPF) + return do_set_attach_filter(sock, level, optname, + optval, optlen); + return sock_setsockopt(sock, level, optname, optval, optlen); +} + static int __compat_sys_setsockopt(int fd, int level, int optname, char __user *optval, unsigned int optlen) { @@ -336,7 +379,7 @@ static int __compat_sys_setsockopt(int fd, int level, int optname, } if (level == SOL_SOCKET) - err = sock_setsockopt(sock, level, + err = compat_sock_setsockopt(sock, level, optname, optval, optlen); else if (sock->ops->compat_setsockopt) err = sock->ops->compat_setsockopt(sock, level, diff --git a/net/core/Makefile b/net/core/Makefile index 26ef2eb6b1e6..a104dc8faafc 100644 --- a/net/core/Makefile +++ b/net/core/Makefile @@ -16,6 +16,7 @@ obj-y += dev.o ethtool.o dev_addr_lists.o dst.o netevent.o \ obj-y += net-sysfs.o obj-$(CONFIG_PAGE_POOL) += page_pool.o obj-$(CONFIG_PROC_FS) += net-procfs.o +obj-$(CONFIG_NET_SOCK_MSG) += skmsg.o obj-$(CONFIG_NET_PKTGEN) += pktgen.o obj-$(CONFIG_NETPOLL) += netpoll.o obj-$(CONFIG_FIB_RULES) += fib_rules.o @@ -27,13 +28,10 @@ obj-$(CONFIG_CGROUP_NET_PRIO) += netprio_cgroup.o obj-$(CONFIG_CGROUP_NET_CLASSID) += netclassid_cgroup.o obj-$(CONFIG_LWTUNNEL) += lwtunnel.o obj-$(CONFIG_LWTUNNEL_BPF) += lwt_bpf.o +obj-$(CONFIG_BPF_STREAM_PARSER) += sock_map.o obj-$(CONFIG_DST_CACHE) += dst_cache.o obj-$(CONFIG_HWBM) += hwbm.o obj-$(CONFIG_NET_DEVLINK) += devlink.o obj-$(CONFIG_GRO_CELLS) += gro_cells.o obj-$(CONFIG_FAILOVER) += failover.o -ifeq ($(CONFIG_INET),y) -obj-$(CONFIG_NET_SOCK_MSG) += skmsg.o -obj-$(CONFIG_BPF_SYSCALL) += sock_map.o -endif obj-$(CONFIG_BPF_SYSCALL) += bpf_sk_storage.o diff --git a/net/core/bpf_sk_storage.c b/net/core/bpf_sk_storage.c index 9af6af56fa5c..0147b26f585a 100644 --- a/net/core/bpf_sk_storage.c +++ b/net/core/bpf_sk_storage.c @@ -6,15 +6,95 @@ #include #include #include -#include -#include #include #include -#include #include -#include -DEFINE_BPF_STORAGE_CACHE(sk_cache); +static atomic_t cache_idx; + +#define SK_STORAGE_CREATE_FLAG_MASK \ + (BPF_F_NO_PREALLOC | BPF_F_CLONE) + +struct bucket { + struct hlist_head list; + raw_spinlock_t lock; +}; + +/* Thp map is not the primary owner of a bpf_sk_storage_elem. + * Instead, the sk->sk_bpf_storage is. + * + * The map (bpf_sk_storage_map) is for two purposes + * 1. Define the size of the "sk local storage". It is + * the map's value_size. + * + * 2. Maintain a list to keep track of all elems such + * that they can be cleaned up during the map destruction. + * + * When a bpf local storage is being looked up for a + * particular sk, the "bpf_map" pointer is actually used + * as the "key" to search in the list of elem in + * sk->sk_bpf_storage. + * + * Hence, consider sk->sk_bpf_storage is the mini-map + * with the "bpf_map" pointer as the searching key. + */ +struct bpf_sk_storage_map { + struct bpf_map map; + /* Lookup elem does not require accessing the map. + * + * Updating/Deleting requires a bucket lock to + * link/unlink the elem from the map. Having + * multiple buckets to improve contention. + */ + struct bucket *buckets; + u32 bucket_log; + u16 elem_size; + u16 cache_idx; +}; + +struct bpf_sk_storage_data { + /* smap is used as the searching key when looking up + * from sk->sk_bpf_storage. + * + * Put it in the same cacheline as the data to minimize + * the number of cachelines access during the cache hit case. + */ + struct bpf_sk_storage_map __rcu *smap; + u8 data[0] __aligned(8); +}; + +/* Linked to bpf_sk_storage and bpf_sk_storage_map */ +struct bpf_sk_storage_elem { + struct hlist_node map_node; /* Linked to bpf_sk_storage_map */ + struct hlist_node snode; /* Linked to bpf_sk_storage */ + struct bpf_sk_storage __rcu *sk_storage; + struct rcu_head rcu; + /* 8 bytes hole */ + /* The data is stored in aother cacheline to minimize + * the number of cachelines access during a cache hit. + */ + struct bpf_sk_storage_data sdata ____cacheline_aligned; +}; + +#define SELEM(_SDATA) container_of((_SDATA), struct bpf_sk_storage_elem, sdata) +#define SDATA(_SELEM) (&(_SELEM)->sdata) +#define BPF_SK_STORAGE_CACHE_SIZE 16 + +struct bpf_sk_storage { + struct bpf_sk_storage_data __rcu *cache[BPF_SK_STORAGE_CACHE_SIZE]; + struct hlist_head list; /* List of bpf_sk_storage_elem */ + struct sock *sk; /* The sk that owns the the above "list" of + * bpf_sk_storage_elem. + */ + struct rcu_head rcu; + raw_spinlock_t lock; /* Protect adding/removing from the "list" */ +}; + +static struct bucket *select_bucket(struct bpf_sk_storage_map *smap, + struct bpf_sk_storage_elem *selem) +{ + return &smap->buckets[hash_ptr(selem, smap->bucket_log)]; +} static int omem_charge(struct sock *sk, unsigned int size) { @@ -28,29 +108,405 @@ static int omem_charge(struct sock *sk, unsigned int size) return -ENOMEM; } -static struct bpf_local_storage_data * +static bool selem_linked_to_sk(const struct bpf_sk_storage_elem *selem) +{ + return !hlist_unhashed(&selem->snode); +} + +static bool selem_linked_to_map(const struct bpf_sk_storage_elem *selem) +{ + return !hlist_unhashed(&selem->map_node); +} + +static struct bpf_sk_storage_elem *selem_alloc(struct bpf_sk_storage_map *smap, + struct sock *sk, void *value, + bool charge_omem) +{ + struct bpf_sk_storage_elem *selem; + + if (charge_omem && omem_charge(sk, smap->elem_size)) + return NULL; + + selem = kzalloc(smap->elem_size, GFP_ATOMIC | __GFP_NOWARN); + if (selem) { + if (value) + memcpy(SDATA(selem)->data, value, smap->map.value_size); + return selem; + } + + if (charge_omem) + atomic_sub(smap->elem_size, &sk->sk_omem_alloc); + + return NULL; +} + +/* sk_storage->lock must be held and selem->sk_storage == sk_storage. + * The caller must ensure selem->smap is still valid to be + * dereferenced for its smap->elem_size and smap->cache_idx. + */ +static bool __selem_unlink_sk(struct bpf_sk_storage *sk_storage, + struct bpf_sk_storage_elem *selem, + bool uncharge_omem) +{ + struct bpf_sk_storage_map *smap; + bool free_sk_storage; + struct sock *sk; + + smap = rcu_dereference(SDATA(selem)->smap); + sk = sk_storage->sk; + + /* All uncharging on sk->sk_omem_alloc must be done first. + * sk may be freed once the last selem is unlinked from sk_storage. + */ + if (uncharge_omem) + atomic_sub(smap->elem_size, &sk->sk_omem_alloc); + + free_sk_storage = hlist_is_singular_node(&selem->snode, + &sk_storage->list); + if (free_sk_storage) { + atomic_sub(sizeof(struct bpf_sk_storage), &sk->sk_omem_alloc); + sk_storage->sk = NULL; + /* After this RCU_INIT, sk may be freed and cannot be used */ + RCU_INIT_POINTER(sk->sk_bpf_storage, NULL); + + /* sk_storage is not freed now. sk_storage->lock is + * still held and raw_spin_unlock_bh(&sk_storage->lock) + * will be done by the caller. + * + * Although the unlock will be done under + * rcu_read_lock(), it is more intutivie to + * read if kfree_rcu(sk_storage, rcu) is done + * after the raw_spin_unlock_bh(&sk_storage->lock). + * + * Hence, a "bool free_sk_storage" is returned + * to the caller which then calls the kfree_rcu() + * after unlock. + */ + } + hlist_del_init_rcu(&selem->snode); + if (rcu_access_pointer(sk_storage->cache[smap->cache_idx]) == + SDATA(selem)) + RCU_INIT_POINTER(sk_storage->cache[smap->cache_idx], NULL); + + kfree_rcu(selem, rcu); + + return free_sk_storage; +} + +static void selem_unlink_sk(struct bpf_sk_storage_elem *selem) +{ + struct bpf_sk_storage *sk_storage; + bool free_sk_storage = false; + + if (unlikely(!selem_linked_to_sk(selem))) + /* selem has already been unlinked from sk */ + return; + + sk_storage = rcu_dereference(selem->sk_storage); + raw_spin_lock_bh(&sk_storage->lock); + if (likely(selem_linked_to_sk(selem))) + free_sk_storage = __selem_unlink_sk(sk_storage, selem, true); + raw_spin_unlock_bh(&sk_storage->lock); + + if (free_sk_storage) + kfree_rcu(sk_storage, rcu); +} + +static void __selem_link_sk(struct bpf_sk_storage *sk_storage, + struct bpf_sk_storage_elem *selem) +{ + RCU_INIT_POINTER(selem->sk_storage, sk_storage); + hlist_add_head(&selem->snode, &sk_storage->list); +} + +static void selem_unlink_map(struct bpf_sk_storage_elem *selem) +{ + struct bpf_sk_storage_map *smap; + struct bucket *b; + + if (unlikely(!selem_linked_to_map(selem))) + /* selem has already be unlinked from smap */ + return; + + smap = rcu_dereference(SDATA(selem)->smap); + b = select_bucket(smap, selem); + raw_spin_lock_bh(&b->lock); + if (likely(selem_linked_to_map(selem))) + hlist_del_init_rcu(&selem->map_node); + raw_spin_unlock_bh(&b->lock); +} + +static void selem_link_map(struct bpf_sk_storage_map *smap, + struct bpf_sk_storage_elem *selem) +{ + struct bucket *b = select_bucket(smap, selem); + + raw_spin_lock_bh(&b->lock); + RCU_INIT_POINTER(SDATA(selem)->smap, smap); + hlist_add_head_rcu(&selem->map_node, &b->list); + raw_spin_unlock_bh(&b->lock); +} + +static void selem_unlink(struct bpf_sk_storage_elem *selem) +{ + /* Always unlink from map before unlinking from sk_storage + * because selem will be freed after successfully unlinked from + * the sk_storage. + */ + selem_unlink_map(selem); + selem_unlink_sk(selem); +} + +static struct bpf_sk_storage_data * +__sk_storage_lookup(struct bpf_sk_storage *sk_storage, + struct bpf_sk_storage_map *smap, + bool cacheit_lockit) +{ + struct bpf_sk_storage_data *sdata; + struct bpf_sk_storage_elem *selem; + + /* Fast path (cache hit) */ + sdata = rcu_dereference(sk_storage->cache[smap->cache_idx]); + if (sdata && rcu_access_pointer(sdata->smap) == smap) + return sdata; + + /* Slow path (cache miss) */ + hlist_for_each_entry_rcu(selem, &sk_storage->list, snode) + if (rcu_access_pointer(SDATA(selem)->smap) == smap) + break; + + if (!selem) + return NULL; + + sdata = SDATA(selem); + if (cacheit_lockit) { + /* spinlock is needed to avoid racing with the + * parallel delete. Otherwise, publishing an already + * deleted sdata to the cache will become a use-after-free + * problem in the next __sk_storage_lookup(). + */ + raw_spin_lock_bh(&sk_storage->lock); + if (selem_linked_to_sk(selem)) + rcu_assign_pointer(sk_storage->cache[smap->cache_idx], + sdata); + raw_spin_unlock_bh(&sk_storage->lock); + } + + return sdata; +} + +static struct bpf_sk_storage_data * sk_storage_lookup(struct sock *sk, struct bpf_map *map, bool cacheit_lockit) { - struct bpf_local_storage *sk_storage; - struct bpf_local_storage_map *smap; + struct bpf_sk_storage *sk_storage; + struct bpf_sk_storage_map *smap; sk_storage = rcu_dereference(sk->sk_bpf_storage); if (!sk_storage) return NULL; - smap = (struct bpf_local_storage_map *)map; - return bpf_local_storage_lookup(sk_storage, smap, cacheit_lockit); + smap = (struct bpf_sk_storage_map *)map; + return __sk_storage_lookup(sk_storage, smap, cacheit_lockit); +} + +static int check_flags(const struct bpf_sk_storage_data *old_sdata, + u64 map_flags) +{ + if (old_sdata && (map_flags & ~BPF_F_LOCK) == BPF_NOEXIST) + /* elem already exists */ + return -EEXIST; + + if (!old_sdata && (map_flags & ~BPF_F_LOCK) == BPF_EXIST) + /* elem doesn't exist, cannot update it */ + return -ENOENT; + + return 0; +} + +static int sk_storage_alloc(struct sock *sk, + struct bpf_sk_storage_map *smap, + struct bpf_sk_storage_elem *first_selem) +{ + struct bpf_sk_storage *prev_sk_storage, *sk_storage; + int err; + + err = omem_charge(sk, sizeof(*sk_storage)); + if (err) + return err; + + sk_storage = kzalloc(sizeof(*sk_storage), GFP_ATOMIC | __GFP_NOWARN); + if (!sk_storage) { + err = -ENOMEM; + goto uncharge; + } + INIT_HLIST_HEAD(&sk_storage->list); + raw_spin_lock_init(&sk_storage->lock); + sk_storage->sk = sk; + + __selem_link_sk(sk_storage, first_selem); + selem_link_map(smap, first_selem); + /* Publish sk_storage to sk. sk->sk_lock cannot be acquired. + * Hence, atomic ops is used to set sk->sk_bpf_storage + * from NULL to the newly allocated sk_storage ptr. + * + * From now on, the sk->sk_bpf_storage pointer is protected + * by the sk_storage->lock. Hence, when freeing + * the sk->sk_bpf_storage, the sk_storage->lock must + * be held before setting sk->sk_bpf_storage to NULL. + */ + prev_sk_storage = cmpxchg((struct bpf_sk_storage **)&sk->sk_bpf_storage, + NULL, sk_storage); + if (unlikely(prev_sk_storage)) { + selem_unlink_map(first_selem); + err = -EAGAIN; + goto uncharge; + + /* Note that even first_selem was linked to smap's + * bucket->list, first_selem can be freed immediately + * (instead of kfree_rcu) because + * bpf_sk_storage_map_free() does a + * synchronize_rcu() before walking the bucket->list. + * Hence, no one is accessing selem from the + * bucket->list under rcu_read_lock(). + */ + } + + return 0; + +uncharge: + kfree(sk_storage); + atomic_sub(sizeof(*sk_storage), &sk->sk_omem_alloc); + return err; +} + +/* sk cannot be going away because it is linking new elem + * to sk->sk_bpf_storage. (i.e. sk->sk_refcnt cannot be 0). + * Otherwise, it will become a leak (and other memory issues + * during map destruction). + */ +static struct bpf_sk_storage_data *sk_storage_update(struct sock *sk, + struct bpf_map *map, + void *value, + u64 map_flags) +{ + struct bpf_sk_storage_data *old_sdata = NULL; + struct bpf_sk_storage_elem *selem; + struct bpf_sk_storage *sk_storage; + struct bpf_sk_storage_map *smap; + int err; + + /* BPF_EXIST and BPF_NOEXIST cannot be both set */ + if (unlikely((map_flags & ~BPF_F_LOCK) > BPF_EXIST) || + /* BPF_F_LOCK can only be used in a value with spin_lock */ + unlikely((map_flags & BPF_F_LOCK) && !map_value_has_spin_lock(map))) + return ERR_PTR(-EINVAL); + + smap = (struct bpf_sk_storage_map *)map; + sk_storage = rcu_dereference(sk->sk_bpf_storage); + if (!sk_storage || hlist_empty(&sk_storage->list)) { + /* Very first elem for this sk */ + err = check_flags(NULL, map_flags); + if (err) + return ERR_PTR(err); + + selem = selem_alloc(smap, sk, value, true); + if (!selem) + return ERR_PTR(-ENOMEM); + + err = sk_storage_alloc(sk, smap, selem); + if (err) { + kfree(selem); + atomic_sub(smap->elem_size, &sk->sk_omem_alloc); + return ERR_PTR(err); + } + + return SDATA(selem); + } + + if ((map_flags & BPF_F_LOCK) && !(map_flags & BPF_NOEXIST)) { + /* Hoping to find an old_sdata to do inline update + * such that it can avoid taking the sk_storage->lock + * and changing the lists. + */ + old_sdata = __sk_storage_lookup(sk_storage, smap, false); + err = check_flags(old_sdata, map_flags); + if (err) + return ERR_PTR(err); + if (old_sdata && selem_linked_to_sk(SELEM(old_sdata))) { + copy_map_value_locked(map, old_sdata->data, + value, false); + return old_sdata; + } + } + + raw_spin_lock_bh(&sk_storage->lock); + + /* Recheck sk_storage->list under sk_storage->lock */ + if (unlikely(hlist_empty(&sk_storage->list))) { + /* A parallel del is happening and sk_storage is going + * away. It has just been checked before, so very + * unlikely. Return instead of retry to keep things + * simple. + */ + err = -EAGAIN; + goto unlock_err; + } + + old_sdata = __sk_storage_lookup(sk_storage, smap, false); + err = check_flags(old_sdata, map_flags); + if (err) + goto unlock_err; + + if (old_sdata && (map_flags & BPF_F_LOCK)) { + copy_map_value_locked(map, old_sdata->data, value, false); + selem = SELEM(old_sdata); + goto unlock; + } + + /* sk_storage->lock is held. Hence, we are sure + * we can unlink and uncharge the old_sdata successfully + * later. Hence, instead of charging the new selem now + * and then uncharge the old selem later (which may cause + * a potential but unnecessary charge failure), avoid taking + * a charge at all here (the "!old_sdata" check) and the + * old_sdata will not be uncharged later during __selem_unlink_sk(). + */ + selem = selem_alloc(smap, sk, value, !old_sdata); + if (!selem) { + err = -ENOMEM; + goto unlock_err; + } + + /* First, link the new selem to the map */ + selem_link_map(smap, selem); + + /* Second, link (and publish) the new selem to sk_storage */ + __selem_link_sk(sk_storage, selem); + + /* Third, remove old selem, SELEM(old_sdata) */ + if (old_sdata) { + selem_unlink_map(SELEM(old_sdata)); + __selem_unlink_sk(sk_storage, SELEM(old_sdata), false); + } + +unlock: + raw_spin_unlock_bh(&sk_storage->lock); + return SDATA(selem); + +unlock_err: + raw_spin_unlock_bh(&sk_storage->lock); + return ERR_PTR(err); } static int sk_storage_delete(struct sock *sk, struct bpf_map *map) { - struct bpf_local_storage_data *sdata; + struct bpf_sk_storage_data *sdata; sdata = sk_storage_lookup(sk, map, false); if (!sdata) return -ENOENT; - bpf_selem_unlink(SELEM(sdata)); + selem_unlink(SELEM(sdata)); return 0; } @@ -58,8 +514,8 @@ static int sk_storage_delete(struct sock *sk, struct bpf_map *map) /* Called by __sk_destruct() & bpf_sk_storage_clone() */ void bpf_sk_storage_free(struct sock *sk) { - struct bpf_local_storage_elem *selem; - struct bpf_local_storage *sk_storage; + struct bpf_sk_storage_elem *selem; + struct bpf_sk_storage *sk_storage; bool free_sk_storage = false; struct hlist_node *n; @@ -75,7 +531,7 @@ void bpf_sk_storage_free(struct sock *sk) * Thus, no elem can be added-to or deleted-from the * sk_storage->list by the bpf_prog or by the bpf-map's syscall. * - * It is racing with bpf_local_storage_map_free() alone + * It is racing with bpf_sk_storage_map_free() alone * when unlinking elem from the sk_storage->list and * the map's bucket->list. */ @@ -84,9 +540,8 @@ void bpf_sk_storage_free(struct sock *sk) /* Always unlink from map before unlinking from * sk_storage. */ - bpf_selem_unlink_map(selem); - free_sk_storage = bpf_selem_unlink_storage_nolock(sk_storage, - selem, true); + selem_unlink_map(selem); + free_sk_storage = __selem_unlink_sk(sk_storage, selem, true); } raw_spin_unlock_bh(&sk_storage->lock); rcu_read_unlock(); @@ -95,24 +550,128 @@ void bpf_sk_storage_free(struct sock *sk) kfree_rcu(sk_storage, rcu); } -static void sk_storage_map_free(struct bpf_map *map) +static void bpf_sk_storage_map_free(struct bpf_map *map) { - struct bpf_local_storage_map *smap; + struct bpf_sk_storage_elem *selem; + struct bpf_sk_storage_map *smap; + struct bucket *b; + unsigned int i; - smap = (struct bpf_local_storage_map *)map; - bpf_local_storage_cache_idx_free(&sk_cache, smap->cache_idx); - bpf_local_storage_map_free(smap); + smap = (struct bpf_sk_storage_map *)map; + + /* Note that this map might be concurrently cloned from + * bpf_sk_storage_clone. Wait for any existing bpf_sk_storage_clone + * RCU read section to finish before proceeding. New RCU + * read sections should be prevented via bpf_map_inc_not_zero. + */ + synchronize_rcu(); + + /* bpf prog and the userspace can no longer access this map + * now. No new selem (of this map) can be added + * to the sk->sk_bpf_storage or to the map bucket's list. + * + * The elem of this map can be cleaned up here + * or + * by bpf_sk_storage_free() during __sk_destruct(). + */ + for (i = 0; i < (1U << smap->bucket_log); i++) { + b = &smap->buckets[i]; + + rcu_read_lock(); + /* No one is adding to b->list now */ + while ((selem = hlist_entry_safe(rcu_dereference_raw(hlist_first_rcu(&b->list)), + struct bpf_sk_storage_elem, + map_node))) { + selem_unlink(selem); + cond_resched_rcu(); + } + rcu_read_unlock(); + } + + /* bpf_sk_storage_free() may still need to access the map. + * e.g. bpf_sk_storage_free() has unlinked selem from the map + * which then made the above while((selem = ...)) loop + * exited immediately. + * + * However, the bpf_sk_storage_free() still needs to access + * the smap->elem_size to do the uncharging in + * __selem_unlink_sk(). + * + * Hence, wait another rcu grace period for the + * bpf_sk_storage_free() to finish. + */ + synchronize_rcu(); + + kvfree(smap->buckets); + kfree(map); } -static struct bpf_map *sk_storage_map_alloc(union bpf_attr *attr) +static int bpf_sk_storage_map_alloc_check(union bpf_attr *attr) { - struct bpf_local_storage_map *smap; + if (attr->map_flags & ~SK_STORAGE_CREATE_FLAG_MASK || + !(attr->map_flags & BPF_F_NO_PREALLOC) || + attr->max_entries || + attr->key_size != sizeof(int) || !attr->value_size || + /* Enforce BTF for userspace sk dumping */ + !attr->btf_key_type_id || !attr->btf_value_type_id) + return -EINVAL; - smap = bpf_local_storage_map_alloc(attr); - if (IS_ERR(smap)) - return ERR_CAST(smap); + if (!capable(CAP_SYS_ADMIN)) + return -EPERM; + + if (attr->value_size >= KMALLOC_MAX_SIZE - + MAX_BPF_STACK - sizeof(struct bpf_sk_storage_elem) || + /* U16_MAX is much more than enough for sk local storage + * considering a tcp_sock is ~2k. + */ + attr->value_size > U16_MAX - sizeof(struct bpf_sk_storage_elem)) + return -E2BIG; + + return 0; +} + +static struct bpf_map *bpf_sk_storage_map_alloc(union bpf_attr *attr) +{ + struct bpf_sk_storage_map *smap; + unsigned int i; + u32 nbuckets; + u64 cost; + int ret; + + smap = kzalloc(sizeof(*smap), GFP_USER | __GFP_NOWARN); + if (!smap) + return ERR_PTR(-ENOMEM); + bpf_map_init_from_attr(&smap->map, attr); + + nbuckets = roundup_pow_of_two(num_possible_cpus()); + /* Use at least 2 buckets, select_bucket() is undefined behavior with 1 bucket */ + nbuckets = max_t(u32, 2, nbuckets); + smap->bucket_log = ilog2(nbuckets); + cost = sizeof(*smap->buckets) * nbuckets + sizeof(*smap); + + ret = bpf_map_charge_init(&smap->map.memory, cost); + if (ret < 0) { + kfree(smap); + return ERR_PTR(ret); + } + + smap->buckets = kvcalloc(sizeof(*smap->buckets), nbuckets, + GFP_USER | __GFP_NOWARN); + if (!smap->buckets) { + bpf_map_charge_finish(&smap->map.memory); + kfree(smap); + return ERR_PTR(-ENOMEM); + } + + for (i = 0; i < nbuckets; i++) { + INIT_HLIST_HEAD(&smap->buckets[i].list); + raw_spin_lock_init(&smap->buckets[i].lock); + } + + smap->elem_size = sizeof(struct bpf_sk_storage_elem) + attr->value_size; + smap->cache_idx = (unsigned int)atomic_inc_return(&cache_idx) % + BPF_SK_STORAGE_CACHE_SIZE; - smap->cache_idx = bpf_local_storage_cache_idx_get(&sk_cache); return &smap->map; } @@ -122,9 +681,26 @@ static int notsupp_get_next_key(struct bpf_map *map, void *key, return -ENOTSUPP; } +static int bpf_sk_storage_map_check_btf(const struct bpf_map *map, + const struct btf *btf, + const struct btf_type *key_type, + const struct btf_type *value_type) +{ + u32 int_data; + + if (BTF_INFO_KIND(key_type->info) != BTF_KIND_INT) + return -EINVAL; + + int_data = *(u32 *)(key_type + 1); + if (BTF_INT_BITS(int_data) != 32 || BTF_INT_OFFSET(int_data)) + return -EINVAL; + + return 0; +} + static void *bpf_fd_sk_storage_lookup_elem(struct bpf_map *map, void *key) { - struct bpf_local_storage_data *sdata; + struct bpf_sk_storage_data *sdata; struct socket *sock; int fd, err; @@ -142,16 +718,14 @@ static void *bpf_fd_sk_storage_lookup_elem(struct bpf_map *map, void *key) static int bpf_fd_sk_storage_update_elem(struct bpf_map *map, void *key, void *value, u64 map_flags) { - struct bpf_local_storage_data *sdata; + struct bpf_sk_storage_data *sdata; struct socket *sock; int fd, err; fd = *(int *)key; sock = sockfd_lookup(fd, &err); if (sock) { - sdata = bpf_local_storage_update( - sock->sk, (struct bpf_local_storage_map *)map, value, - map_flags); + sdata = sk_storage_update(sock->sk, map, value, map_flags); sockfd_put(sock); return PTR_ERR_OR_ZERO(sdata); } @@ -175,14 +749,14 @@ static int bpf_fd_sk_storage_delete_elem(struct bpf_map *map, void *key) return err; } -static struct bpf_local_storage_elem * +static struct bpf_sk_storage_elem * bpf_sk_storage_clone_elem(struct sock *newsk, - struct bpf_local_storage_map *smap, - struct bpf_local_storage_elem *selem) + struct bpf_sk_storage_map *smap, + struct bpf_sk_storage_elem *selem) { - struct bpf_local_storage_elem *copy_selem; + struct bpf_sk_storage_elem *copy_selem; - copy_selem = bpf_selem_alloc(smap, newsk, NULL, true); + copy_selem = selem_alloc(smap, newsk, NULL, true); if (!copy_selem) return NULL; @@ -198,9 +772,9 @@ bpf_sk_storage_clone_elem(struct sock *newsk, int bpf_sk_storage_clone(const struct sock *sk, struct sock *newsk) { - struct bpf_local_storage *new_sk_storage = NULL; - struct bpf_local_storage *sk_storage; - struct bpf_local_storage_elem *selem; + struct bpf_sk_storage *new_sk_storage = NULL; + struct bpf_sk_storage *sk_storage; + struct bpf_sk_storage_elem *selem; int ret = 0; RCU_INIT_POINTER(newsk->sk_bpf_storage, NULL); @@ -212,8 +786,8 @@ int bpf_sk_storage_clone(const struct sock *sk, struct sock *newsk) goto out; hlist_for_each_entry_rcu(selem, &sk_storage->list, snode) { - struct bpf_local_storage_elem *copy_selem; - struct bpf_local_storage_map *smap; + struct bpf_sk_storage_elem *copy_selem; + struct bpf_sk_storage_map *smap; struct bpf_map *map; smap = rcu_dereference(SDATA(selem)->smap); @@ -221,11 +795,11 @@ int bpf_sk_storage_clone(const struct sock *sk, struct sock *newsk) continue; /* Note that for lockless listeners adding new element - * here can race with cleanup in bpf_local_storage_map_free. + * here can race with cleanup in bpf_sk_storage_map_free. * Try to grab map refcnt to make sure that it's still * alive and prevent concurrent removal. */ - map = bpf_map_inc_not_zero(&smap->map); + map = bpf_map_inc_not_zero(&smap->map, false); if (IS_ERR(map)) continue; @@ -237,10 +811,10 @@ int bpf_sk_storage_clone(const struct sock *sk, struct sock *newsk) } if (new_sk_storage) { - bpf_selem_link_map(smap, copy_selem); - bpf_selem_link_storage_nolock(new_sk_storage, copy_selem); + selem_link_map(smap, copy_selem); + __selem_link_sk(new_sk_storage, copy_selem); } else { - ret = bpf_local_storage_alloc(newsk, smap, copy_selem); + ret = sk_storage_alloc(newsk, smap, copy_selem); if (ret) { kfree(copy_selem); atomic_sub(smap->elem_size, @@ -249,8 +823,7 @@ int bpf_sk_storage_clone(const struct sock *sk, struct sock *newsk) goto out; } - new_sk_storage = - rcu_dereference(copy_selem->local_storage); + new_sk_storage = rcu_dereference(copy_selem->sk_storage); } bpf_map_put(map); } @@ -268,9 +841,9 @@ out: BPF_CALL_4(bpf_sk_storage_get, struct bpf_map *, map, struct sock *, sk, void *, value, u64, flags) { - struct bpf_local_storage_data *sdata; + struct bpf_sk_storage_data *sdata; - if (!sk || !sk_fullsock(sk) || flags > BPF_SK_STORAGE_GET_F_CREATE) + if (flags > BPF_SK_STORAGE_GET_F_CREATE) return (unsigned long)NULL; sdata = sk_storage_lookup(sk, map, true); @@ -284,9 +857,7 @@ BPF_CALL_4(bpf_sk_storage_get, struct bpf_map *, map, struct sock *, sk, * destruction). */ refcount_inc_not_zero(&sk->sk_refcnt)) { - sdata = bpf_local_storage_update( - sk, (struct bpf_local_storage_map *)map, value, - BPF_NOEXIST); + sdata = sk_storage_update(sk, map, value, BPF_NOEXIST); /* sk must be a fullsock (guaranteed by verifier), * so sock_gen_put() is unnecessary. */ @@ -300,9 +871,6 @@ BPF_CALL_4(bpf_sk_storage_get, struct bpf_map *, map, struct sock *, sk, BPF_CALL_2(bpf_sk_storage_delete, struct bpf_map *, map, struct sock *, sk) { - if (!sk || !sk_fullsock(sk)) - return -EINVAL; - if (refcount_inc_not_zero(&sk->sk_refcnt)) { int err; @@ -314,44 +882,15 @@ BPF_CALL_2(bpf_sk_storage_delete, struct bpf_map *, map, struct sock *, sk) return -ENOENT; } -static int sk_storage_charge(struct bpf_local_storage_map *smap, - void *owner, u32 size) -{ - return omem_charge(owner, size); -} - -static void sk_storage_uncharge(struct bpf_local_storage_map *smap, - void *owner, u32 size) -{ - struct sock *sk = owner; - - atomic_sub(size, &sk->sk_omem_alloc); -} - -static struct bpf_local_storage __rcu ** -sk_storage_ptr(void *owner) -{ - struct sock *sk = owner; - - return &sk->sk_bpf_storage; -} - -static int sk_storage_map_btf_id; const struct bpf_map_ops sk_storage_map_ops = { - .map_meta_equal = bpf_map_meta_equal, - .map_alloc_check = bpf_local_storage_map_alloc_check, - .map_alloc = sk_storage_map_alloc, - .map_free = sk_storage_map_free, + .map_alloc_check = bpf_sk_storage_map_alloc_check, + .map_alloc = bpf_sk_storage_map_alloc, + .map_free = bpf_sk_storage_map_free, .map_get_next_key = notsupp_get_next_key, .map_lookup_elem = bpf_fd_sk_storage_lookup_elem, .map_update_elem = bpf_fd_sk_storage_update_elem, .map_delete_elem = bpf_fd_sk_storage_delete_elem, - .map_check_btf = bpf_local_storage_map_check_btf, - .map_btf_name = "bpf_local_storage_map", - .map_btf_id = &sk_storage_map_btf_id, - .map_local_storage_charge = sk_storage_charge, - .map_local_storage_uncharge = sk_storage_uncharge, - .map_owner_storage_ptr = sk_storage_ptr, + .map_check_btf = bpf_sk_storage_map_check_btf, }; const struct bpf_func_proto bpf_sk_storage_get_proto = { @@ -359,17 +898,7 @@ const struct bpf_func_proto bpf_sk_storage_get_proto = { .gpl_only = false, .ret_type = RET_PTR_TO_MAP_VALUE_OR_NULL, .arg1_type = ARG_CONST_MAP_PTR, - .arg2_type = ARG_PTR_TO_BTF_ID_SOCK_COMMON, - .arg3_type = ARG_PTR_TO_MAP_VALUE_OR_NULL, - .arg4_type = ARG_ANYTHING, -}; - -const struct bpf_func_proto bpf_sk_storage_get_cg_sock_proto = { - .func = bpf_sk_storage_get, - .gpl_only = false, - .ret_type = RET_PTR_TO_MAP_VALUE_OR_NULL, - .arg1_type = ARG_CONST_MAP_PTR, - .arg2_type = ARG_PTR_TO_CTX, /* context is 'struct sock' */ + .arg2_type = ARG_PTR_TO_SOCKET, .arg3_type = ARG_PTR_TO_MAP_VALUE_OR_NULL, .arg4_type = ARG_ANYTHING, }; @@ -379,500 +908,5 @@ const struct bpf_func_proto bpf_sk_storage_delete_proto = { .gpl_only = false, .ret_type = RET_INTEGER, .arg1_type = ARG_CONST_MAP_PTR, - .arg2_type = ARG_PTR_TO_BTF_ID_SOCK_COMMON, + .arg2_type = ARG_PTR_TO_SOCKET, }; - -struct bpf_sk_storage_diag { - u32 nr_maps; - struct bpf_map *maps[]; -}; - -/* The reply will be like: - * INET_DIAG_BPF_SK_STORAGES (nla_nest) - * SK_DIAG_BPF_STORAGE (nla_nest) - * SK_DIAG_BPF_STORAGE_MAP_ID (nla_put_u32) - * SK_DIAG_BPF_STORAGE_MAP_VALUE (nla_reserve_64bit) - * SK_DIAG_BPF_STORAGE (nla_nest) - * SK_DIAG_BPF_STORAGE_MAP_ID (nla_put_u32) - * SK_DIAG_BPF_STORAGE_MAP_VALUE (nla_reserve_64bit) - * .... - */ -static int nla_value_size(u32 value_size) -{ - /* SK_DIAG_BPF_STORAGE (nla_nest) - * SK_DIAG_BPF_STORAGE_MAP_ID (nla_put_u32) - * SK_DIAG_BPF_STORAGE_MAP_VALUE (nla_reserve_64bit) - */ - return nla_total_size(0) + nla_total_size(sizeof(u32)) + - nla_total_size_64bit(value_size); -} - -void bpf_sk_storage_diag_free(struct bpf_sk_storage_diag *diag) -{ - u32 i; - - if (!diag) - return; - - for (i = 0; i < diag->nr_maps; i++) - bpf_map_put(diag->maps[i]); - - kfree(diag); -} -EXPORT_SYMBOL_GPL(bpf_sk_storage_diag_free); - -static bool diag_check_dup(const struct bpf_sk_storage_diag *diag, - const struct bpf_map *map) -{ - u32 i; - - for (i = 0; i < diag->nr_maps; i++) { - if (diag->maps[i] == map) - return true; - } - - return false; -} - -struct bpf_sk_storage_diag * -bpf_sk_storage_diag_alloc(const struct nlattr *nla_stgs) -{ - struct bpf_sk_storage_diag *diag; - struct nlattr *nla; - u32 nr_maps = 0; - int rem, err; - - /* bpf_local_storage_map is currently limited to CAP_SYS_ADMIN as - * the map_alloc_check() side also does. - */ - if (!bpf_capable()) - return ERR_PTR(-EPERM); - - nla_for_each_nested(nla, nla_stgs, rem) { - if (nla_type(nla) == SK_DIAG_BPF_STORAGE_REQ_MAP_FD) - nr_maps++; - } - - diag = kzalloc(sizeof(*diag) + sizeof(diag->maps[0]) * nr_maps, - GFP_KERNEL); - if (!diag) - return ERR_PTR(-ENOMEM); - - nla_for_each_nested(nla, nla_stgs, rem) { - struct bpf_map *map; - int map_fd; - - if (nla_type(nla) != SK_DIAG_BPF_STORAGE_REQ_MAP_FD) - continue; - - map_fd = nla_get_u32(nla); - map = bpf_map_get(map_fd); - if (IS_ERR(map)) { - err = PTR_ERR(map); - goto err_free; - } - if (map->map_type != BPF_MAP_TYPE_SK_STORAGE) { - bpf_map_put(map); - err = -EINVAL; - goto err_free; - } - if (diag_check_dup(diag, map)) { - bpf_map_put(map); - err = -EEXIST; - goto err_free; - } - diag->maps[diag->nr_maps++] = map; - } - - return diag; - -err_free: - bpf_sk_storage_diag_free(diag); - return ERR_PTR(err); -} -EXPORT_SYMBOL_GPL(bpf_sk_storage_diag_alloc); - -static int diag_get(struct bpf_local_storage_data *sdata, struct sk_buff *skb) -{ - struct nlattr *nla_stg, *nla_value; - struct bpf_local_storage_map *smap; - - /* It cannot exceed max nlattr's payload */ - BUILD_BUG_ON(U16_MAX - NLA_HDRLEN < BPF_LOCAL_STORAGE_MAX_VALUE_SIZE); - - nla_stg = nla_nest_start(skb, SK_DIAG_BPF_STORAGE); - if (!nla_stg) - return -EMSGSIZE; - - smap = rcu_dereference(sdata->smap); - if (nla_put_u32(skb, SK_DIAG_BPF_STORAGE_MAP_ID, smap->map.id)) - goto errout; - - nla_value = nla_reserve_64bit(skb, SK_DIAG_BPF_STORAGE_MAP_VALUE, - smap->map.value_size, - SK_DIAG_BPF_STORAGE_PAD); - if (!nla_value) - goto errout; - - if (map_value_has_spin_lock(&smap->map)) - copy_map_value_locked(&smap->map, nla_data(nla_value), - sdata->data, true); - else - copy_map_value(&smap->map, nla_data(nla_value), sdata->data); - - nla_nest_end(skb, nla_stg); - return 0; - -errout: - nla_nest_cancel(skb, nla_stg); - return -EMSGSIZE; -} - -static int bpf_sk_storage_diag_put_all(struct sock *sk, struct sk_buff *skb, - int stg_array_type, - unsigned int *res_diag_size) -{ - /* stg_array_type (e.g. INET_DIAG_BPF_SK_STORAGES) */ - unsigned int diag_size = nla_total_size(0); - struct bpf_local_storage *sk_storage; - struct bpf_local_storage_elem *selem; - struct bpf_local_storage_map *smap; - struct nlattr *nla_stgs; - unsigned int saved_len; - int err = 0; - - rcu_read_lock(); - - sk_storage = rcu_dereference(sk->sk_bpf_storage); - if (!sk_storage || hlist_empty(&sk_storage->list)) { - rcu_read_unlock(); - return 0; - } - - nla_stgs = nla_nest_start(skb, stg_array_type); - if (!nla_stgs) - /* Continue to learn diag_size */ - err = -EMSGSIZE; - - saved_len = skb->len; - hlist_for_each_entry_rcu(selem, &sk_storage->list, snode) { - smap = rcu_dereference(SDATA(selem)->smap); - diag_size += nla_value_size(smap->map.value_size); - - if (nla_stgs && diag_get(SDATA(selem), skb)) - /* Continue to learn diag_size */ - err = -EMSGSIZE; - } - - rcu_read_unlock(); - - if (nla_stgs) { - if (saved_len == skb->len) - nla_nest_cancel(skb, nla_stgs); - else - nla_nest_end(skb, nla_stgs); - } - - if (diag_size == nla_total_size(0)) { - *res_diag_size = 0; - return 0; - } - - *res_diag_size = diag_size; - return err; -} - -int bpf_sk_storage_diag_put(struct bpf_sk_storage_diag *diag, - struct sock *sk, struct sk_buff *skb, - int stg_array_type, - unsigned int *res_diag_size) -{ - /* stg_array_type (e.g. INET_DIAG_BPF_SK_STORAGES) */ - unsigned int diag_size = nla_total_size(0); - struct bpf_local_storage *sk_storage; - struct bpf_local_storage_data *sdata; - struct nlattr *nla_stgs; - unsigned int saved_len; - int err = 0; - u32 i; - - *res_diag_size = 0; - - /* No map has been specified. Dump all. */ - if (!diag->nr_maps) - return bpf_sk_storage_diag_put_all(sk, skb, stg_array_type, - res_diag_size); - - rcu_read_lock(); - sk_storage = rcu_dereference(sk->sk_bpf_storage); - if (!sk_storage || hlist_empty(&sk_storage->list)) { - rcu_read_unlock(); - return 0; - } - - nla_stgs = nla_nest_start(skb, stg_array_type); - if (!nla_stgs) - /* Continue to learn diag_size */ - err = -EMSGSIZE; - - saved_len = skb->len; - for (i = 0; i < diag->nr_maps; i++) { - sdata = bpf_local_storage_lookup(sk_storage, - (struct bpf_local_storage_map *)diag->maps[i], - false); - - if (!sdata) - continue; - - diag_size += nla_value_size(diag->maps[i]->value_size); - - if (nla_stgs && diag_get(sdata, skb)) - /* Continue to learn diag_size */ - err = -EMSGSIZE; - } - rcu_read_unlock(); - - if (nla_stgs) { - if (saved_len == skb->len) - nla_nest_cancel(skb, nla_stgs); - else - nla_nest_end(skb, nla_stgs); - } - - if (diag_size == nla_total_size(0)) { - *res_diag_size = 0; - return 0; - } - - *res_diag_size = diag_size; - return err; -} -EXPORT_SYMBOL_GPL(bpf_sk_storage_diag_put); - -struct bpf_iter_seq_sk_storage_map_info { - struct bpf_map *map; - unsigned int bucket_id; - unsigned skip_elems; -}; - -static struct bpf_local_storage_elem * -bpf_sk_storage_map_seq_find_next(struct bpf_iter_seq_sk_storage_map_info *info, - struct bpf_local_storage_elem *prev_selem) -{ - struct bpf_local_storage *sk_storage; - struct bpf_local_storage_elem *selem; - u32 skip_elems = info->skip_elems; - struct bpf_local_storage_map *smap; - u32 bucket_id = info->bucket_id; - u32 i, count, n_buckets; - struct bpf_local_storage_map_bucket *b; - - smap = (struct bpf_local_storage_map *)info->map; - n_buckets = 1U << smap->bucket_log; - if (bucket_id >= n_buckets) - return NULL; - - /* try to find next selem in the same bucket */ - selem = prev_selem; - count = 0; - while (selem) { - selem = hlist_entry_safe(selem->map_node.next, - struct bpf_local_storage_elem, map_node); - if (!selem) { - /* not found, unlock and go to the next bucket */ - b = &smap->buckets[bucket_id++]; - raw_spin_unlock_bh(&b->lock); - skip_elems = 0; - break; - } - sk_storage = rcu_dereference_raw(selem->local_storage); - if (sk_storage) { - info->skip_elems = skip_elems + count; - return selem; - } - count++; - } - - for (i = bucket_id; i < (1U << smap->bucket_log); i++) { - b = &smap->buckets[i]; - raw_spin_lock_bh(&b->lock); - count = 0; - hlist_for_each_entry(selem, &b->list, map_node) { - sk_storage = rcu_dereference_raw(selem->local_storage); - if (sk_storage && count >= skip_elems) { - info->bucket_id = i; - info->skip_elems = count; - return selem; - } - count++; - } - raw_spin_unlock_bh(&b->lock); - skip_elems = 0; - } - - info->bucket_id = i; - info->skip_elems = 0; - return NULL; -} - -static void *bpf_sk_storage_map_seq_start(struct seq_file *seq, loff_t *pos) -{ - struct bpf_local_storage_elem *selem; - - selem = bpf_sk_storage_map_seq_find_next(seq->private, NULL); - if (!selem) - return NULL; - - if (*pos == 0) - ++*pos; - return selem; -} - -static void *bpf_sk_storage_map_seq_next(struct seq_file *seq, void *v, - loff_t *pos) -{ - struct bpf_iter_seq_sk_storage_map_info *info = seq->private; - - ++*pos; - ++info->skip_elems; - return bpf_sk_storage_map_seq_find_next(seq->private, v); -} - -struct bpf_iter__bpf_sk_storage_map { - __bpf_md_ptr(struct bpf_iter_meta *, meta); - __bpf_md_ptr(struct bpf_map *, map); - __bpf_md_ptr(struct sock *, sk); - __bpf_md_ptr(void *, value); -}; - -DEFINE_BPF_ITER_FUNC(bpf_sk_storage_map, struct bpf_iter_meta *meta, - struct bpf_map *map, struct sock *sk, - void *value) - -static int __bpf_sk_storage_map_seq_show(struct seq_file *seq, - struct bpf_local_storage_elem *selem) -{ - struct bpf_iter_seq_sk_storage_map_info *info = seq->private; - struct bpf_iter__bpf_sk_storage_map ctx = {}; - struct bpf_local_storage *sk_storage; - struct bpf_iter_meta meta; - struct bpf_prog *prog; - int ret = 0; - - meta.seq = seq; - prog = bpf_iter_get_info(&meta, selem == NULL); - if (prog) { - ctx.meta = &meta; - ctx.map = info->map; - if (selem) { - sk_storage = rcu_dereference_raw(selem->local_storage); - ctx.sk = sk_storage->owner; - ctx.value = SDATA(selem)->data; - } - ret = bpf_iter_run_prog(prog, &ctx); - } - - return ret; -} - -static int bpf_sk_storage_map_seq_show(struct seq_file *seq, void *v) -{ - return __bpf_sk_storage_map_seq_show(seq, v); -} - -static void bpf_sk_storage_map_seq_stop(struct seq_file *seq, void *v) -{ - struct bpf_iter_seq_sk_storage_map_info *info = seq->private; - struct bpf_local_storage_map *smap; - struct bpf_local_storage_map_bucket *b; - - if (!v) { - (void)__bpf_sk_storage_map_seq_show(seq, v); - } else { - smap = (struct bpf_local_storage_map *)info->map; - b = &smap->buckets[info->bucket_id]; - raw_spin_unlock_bh(&b->lock); - } -} - -static int bpf_iter_init_sk_storage_map(void *priv_data, - struct bpf_iter_aux_info *aux) -{ - struct bpf_iter_seq_sk_storage_map_info *seq_info = priv_data; - - seq_info->map = aux->map; - return 0; -} - -static int bpf_iter_attach_map(struct bpf_prog *prog, - union bpf_iter_link_info *linfo, - struct bpf_iter_aux_info *aux) -{ - struct bpf_map *map; - int err = -EINVAL; - - if (!linfo->map.map_fd) - return -EBADF; - - map = bpf_map_get_with_uref(linfo->map.map_fd); - if (IS_ERR(map)) - return PTR_ERR(map); - - if (map->map_type != BPF_MAP_TYPE_SK_STORAGE) - goto put_map; - - if (prog->aux->max_rdonly_access > map->value_size) { - err = -EACCES; - goto put_map; - } - - aux->map = map; - return 0; - -put_map: - bpf_map_put_with_uref(map); - return err; -} - -static void bpf_iter_detach_map(struct bpf_iter_aux_info *aux) -{ - bpf_map_put_with_uref(aux->map); -} - -static const struct seq_operations bpf_sk_storage_map_seq_ops = { - .start = bpf_sk_storage_map_seq_start, - .next = bpf_sk_storage_map_seq_next, - .stop = bpf_sk_storage_map_seq_stop, - .show = bpf_sk_storage_map_seq_show, -}; - -static const struct bpf_iter_seq_info iter_seq_info = { - .seq_ops = &bpf_sk_storage_map_seq_ops, - .init_seq_private = bpf_iter_init_sk_storage_map, - .fini_seq_private = NULL, - .seq_priv_size = sizeof(struct bpf_iter_seq_sk_storage_map_info), -}; - -static struct bpf_iter_reg bpf_sk_storage_map_reg_info = { - .target = "bpf_sk_storage_map", - .attach_target = bpf_iter_attach_map, - .detach_target = bpf_iter_detach_map, - .show_fdinfo = bpf_iter_map_show_fdinfo, - .fill_link_info = bpf_iter_map_fill_link_info, - .ctx_arg_info_size = 2, - .ctx_arg_info = { - { offsetof(struct bpf_iter__bpf_sk_storage_map, sk), - PTR_TO_BTF_ID_OR_NULL }, - { offsetof(struct bpf_iter__bpf_sk_storage_map, value), - PTR_TO_RDWR_BUF_OR_NULL }, - }, - .seq_info = &iter_seq_info, -}; - -static int __init bpf_sk_storage_map_iter_init(void) -{ - bpf_sk_storage_map_reg_info.ctx_arg_info[0].btf_id = - btf_sock_ids[BTF_SOCK_TYPE_SOCK]; - return bpf_iter_reg_target(&bpf_sk_storage_map_reg_info); -} -late_initcall(bpf_sk_storage_map_iter_init); diff --git a/net/core/dev.c b/net/core/dev.c index 9b8bd2d89595..aad29ac5ac15 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -1521,7 +1521,7 @@ const char *netdev_cmd_to_name(enum netdev_cmd cmd) N(UDP_TUNNEL_DROP_INFO) N(CHANGE_TX_QUEUE_LEN) N(CVLAN_FILTER_PUSH_INFO) N(CVLAN_FILTER_DROP_INFO) N(SVLAN_FILTER_PUSH_INFO) N(SVLAN_FILTER_DROP_INFO) - N(PRE_CHANGEADDR) N(BR_JOIN) N(BR_LEAVE) + N(PRE_CHANGEADDR) } #undef N return "UNKNOWN_NETDEV_EVENT"; @@ -1538,62 +1538,6 @@ static int call_netdevice_notifier(struct notifier_block *nb, unsigned long val, return nb->notifier_call(nb, val, &info); } -static int call_netdevice_register_notifiers(struct notifier_block *nb, - struct net_device *dev) -{ - int err; - - err = call_netdevice_notifier(nb, NETDEV_REGISTER, dev); - err = notifier_to_errno(err); - if (err) - return err; - - if (!(dev->flags & IFF_UP)) - return 0; - - call_netdevice_notifier(nb, NETDEV_UP, dev); - return 0; -} - -static void call_netdevice_unregister_notifiers(struct notifier_block *nb, - struct net_device *dev) -{ - if (dev->flags & IFF_UP) { - call_netdevice_notifier(nb, NETDEV_GOING_DOWN, - dev); - call_netdevice_notifier(nb, NETDEV_DOWN, dev); - } - call_netdevice_notifier(nb, NETDEV_UNREGISTER, dev); -} - -static int call_netdevice_register_net_notifiers(struct notifier_block *nb, - struct net *net) -{ - struct net_device *dev; - int err; - - for_each_netdev(net, dev) { - err = call_netdevice_register_notifiers(nb, dev); - if (err) - goto rollback; - } - return 0; - -rollback: - for_each_netdev_continue_reverse(net, dev) - call_netdevice_unregister_notifiers(nb, dev); - return err; -} - -static void call_netdevice_unregister_net_notifiers(struct notifier_block *nb, - struct net *net) -{ - struct net_device *dev; - - for_each_netdev(net, dev) - call_netdevice_unregister_notifiers(nb, dev); -} - static int dev_boot_phase = 1; /** @@ -1612,6 +1556,8 @@ static int dev_boot_phase = 1; int register_netdevice_notifier(struct notifier_block *nb) { + struct net_device *dev; + struct net_device *last; struct net *net; int err; @@ -1624,9 +1570,17 @@ int register_netdevice_notifier(struct notifier_block *nb) if (dev_boot_phase) goto unlock; for_each_net(net) { - err = call_netdevice_register_net_notifiers(nb, net); - if (err) - goto rollback; + for_each_netdev(net, dev) { + err = call_netdevice_notifier(nb, NETDEV_REGISTER, dev); + err = notifier_to_errno(err); + if (err) + goto rollback; + + if (!(dev->flags & IFF_UP)) + continue; + + call_netdevice_notifier(nb, NETDEV_UP, dev); + } } unlock: @@ -1635,9 +1589,22 @@ unlock: return err; rollback: - for_each_net_continue_reverse(net) - call_netdevice_unregister_net_notifiers(nb, net); + last = dev; + for_each_net(net) { + for_each_netdev(net, dev) { + if (dev == last) + goto outroll; + if (dev->flags & IFF_UP) { + call_netdevice_notifier(nb, NETDEV_GOING_DOWN, + dev); + call_netdevice_notifier(nb, NETDEV_DOWN, dev); + } + call_netdevice_notifier(nb, NETDEV_UNREGISTER, dev); + } + } + +outroll: raw_notifier_chain_unregister(&netdev_chain, nb); goto unlock; } @@ -1687,138 +1654,6 @@ unlock: } EXPORT_SYMBOL(unregister_netdevice_notifier); -static int __register_netdevice_notifier_net(struct net *net, - struct notifier_block *nb, - bool ignore_call_fail) -{ - int err; - - err = raw_notifier_chain_register(&net->netdev_chain, nb); - if (err) - return err; - if (dev_boot_phase) - return 0; - - err = call_netdevice_register_net_notifiers(nb, net); - if (err && !ignore_call_fail) - goto chain_unregister; - - return 0; - -chain_unregister: - raw_notifier_chain_unregister(&net->netdev_chain, nb); - return err; -} - -static int __unregister_netdevice_notifier_net(struct net *net, - struct notifier_block *nb) -{ - int err; - - err = raw_notifier_chain_unregister(&net->netdev_chain, nb); - if (err) - return err; - - call_netdevice_unregister_net_notifiers(nb, net); - return 0; -} - -/** - * register_netdevice_notifier_net - register a per-netns network notifier block - * @net: network namespace - * @nb: notifier - * - * Register a notifier to be called when network device events occur. - * The notifier passed is linked into the kernel structures and must - * not be reused until it has been unregistered. A negative errno code - * is returned on a failure. - * - * When registered all registration and up events are replayed - * to the new notifier to allow device to have a race free - * view of the network device list. - */ - -int register_netdevice_notifier_net(struct net *net, struct notifier_block *nb) -{ - int err; - - rtnl_lock(); - err = __register_netdevice_notifier_net(net, nb, false); - rtnl_unlock(); - return err; -} -EXPORT_SYMBOL(register_netdevice_notifier_net); - -/** - * unregister_netdevice_notifier_net - unregister a per-netns - * network notifier block - * @net: network namespace - * @nb: notifier - * - * Unregister a notifier previously registered by - * register_netdevice_notifier(). The notifier is unlinked into the - * kernel structures and may then be reused. A negative errno code - * is returned on a failure. - * - * After unregistering unregister and down device events are synthesized - * for all devices on the device list to the removed notifier to remove - * the need for special case cleanup code. - */ - -int unregister_netdevice_notifier_net(struct net *net, - struct notifier_block *nb) -{ - int err; - - rtnl_lock(); - err = __unregister_netdevice_notifier_net(net, nb); - rtnl_unlock(); - return err; -} -EXPORT_SYMBOL(unregister_netdevice_notifier_net); - -int register_netdevice_notifier_dev_net(struct net_device *dev, - struct notifier_block *nb, - struct netdev_net_notifier *nn) -{ - int err; - - rtnl_lock(); - err = __register_netdevice_notifier_net(dev_net(dev), nb, false); - if (!err) { - nn->nb = nb; - list_add(&nn->list, &dev->net_notifier_list); - } - rtnl_unlock(); - return err; -} -EXPORT_SYMBOL(register_netdevice_notifier_dev_net); - -int unregister_netdevice_notifier_dev_net(struct net_device *dev, - struct notifier_block *nb, - struct netdev_net_notifier *nn) -{ - int err; - - rtnl_lock(); - list_del(&nn->list); - err = __unregister_netdevice_notifier_net(dev_net(dev), nb); - rtnl_unlock(); - return err; -} -EXPORT_SYMBOL(unregister_netdevice_notifier_dev_net); - -static void move_netdevice_notifiers_dev_net(struct net_device *dev, - struct net *net) -{ - struct netdev_net_notifier *nn; - - list_for_each_entry(nn, &dev->net_notifier_list, list) { - __unregister_netdevice_notifier_net(dev_net(dev), nn->nb); - __register_netdevice_notifier_net(net, nn->nb, true); - } -} - /** * call_netdevice_notifiers_info - call all network notifier blocks * @val: value passed unmodified to notifier function @@ -1831,18 +1666,7 @@ static void move_netdevice_notifiers_dev_net(struct net_device *dev, static int call_netdevice_notifiers_info(unsigned long val, struct netdev_notifier_info *info) { - struct net *net = dev_net(info->dev); - int ret; - ASSERT_RTNL(); - - /* Run per-netns notifier block chain first, then run the global one. - * Hopefully, one day, the global one is going to be removed after - * all notifier block registrators get converted to be per-netns. - */ - ret = raw_notifier_call_chain(&net->netdev_chain, val, info); - if (ret & NOTIFY_STOP_MASK) - return ret; return raw_notifier_call_chain(&netdev_chain, val, info); } @@ -4589,6 +4413,7 @@ void generic_xdp_tx(struct sk_buff *skb, struct bpf_prog *xdp_prog) kfree_skb(skb); } } +EXPORT_SYMBOL_GPL(generic_xdp_tx); static DEFINE_STATIC_KEY_FALSE(generic_xdp_needed_key); @@ -4794,7 +4619,7 @@ EXPORT_SYMBOL_GPL(br_fdb_test_addr_hook); static inline struct sk_buff * sch_handle_ingress(struct sk_buff *skb, struct packet_type **pt_prev, int *ret, - struct net_device *orig_dev, bool *another) + struct net_device *orig_dev) { #ifdef CONFIG_NET_CLS_ACT struct mini_Qdisc *miniq = rcu_dereference_bh(skb->dev->miniq_ingress); @@ -4837,11 +4662,7 @@ sch_handle_ingress(struct sk_buff *skb, struct packet_type **pt_prev, int *ret, * redirecting to another netdev */ __skb_push(skb, skb->mac_len); - if (skb_do_redirect(skb) == -EAGAIN) { - __skb_pull(skb, skb->mac_len); - *another = true; - break; - } + skb_do_redirect(skb); return NULL; case TC_ACT_CONSUMED: return NULL; @@ -5063,12 +4884,7 @@ another_round: skip_taps: #ifdef CONFIG_NET_INGRESS if (static_branch_unlikely(&ingress_needed_key)) { - bool another = false; - - skb = sch_handle_ingress(skb, &pt_prev, &ret, orig_dev, - &another); - if (another) - goto another_round; + skb = sch_handle_ingress(skb, &pt_prev, &ret, orig_dev); if (!skb) goto out; @@ -5381,25 +5197,6 @@ static int generic_xdp_install(struct net_device *dev, struct netdev_bpf *xdp) struct bpf_prog *new = xdp->prog; int ret = 0; - if (new) { - u32 i; - - mutex_lock(&new->aux->used_maps_mutex); - - /* generic XDP does not work with DEVMAPs that can - * have a bpf_prog installed on an entry - */ - for (i = 0; i < new->aux->used_map_cnt; i++) { - if (dev_map_can_have_prog(new->aux->used_maps[i]) || - cpu_map_prog_allowed(new->aux->used_maps[i])) { - mutex_unlock(&new->aux->used_maps_mutex); - return -EINVAL; - } - } - - mutex_unlock(&new->aux->used_maps_mutex); - } - switch (xdp->command) { case XDP_SETUP_PROG: rcu_assign_pointer(dev->xdp_prog, new); @@ -8684,419 +8481,67 @@ int dev_change_proto_down_generic(struct net_device *dev, bool proto_down) } EXPORT_SYMBOL(dev_change_proto_down_generic); -struct bpf_xdp_link { - struct bpf_link link; - struct net_device *dev; /* protected by rtnl_lock, no refcnt held */ - int flags; -}; - -static enum bpf_xdp_mode dev_xdp_mode(u32 flags) -{ - if (flags & XDP_FLAGS_HW_MODE) - return XDP_MODE_HW; - if (flags & XDP_FLAGS_DRV_MODE) - return XDP_MODE_DRV; - return XDP_MODE_SKB; -} - -static bpf_op_t dev_xdp_bpf_op(struct net_device *dev, enum bpf_xdp_mode mode) -{ - switch (mode) { - case XDP_MODE_SKB: - return generic_xdp_install; - case XDP_MODE_DRV: - case XDP_MODE_HW: - return dev->netdev_ops->ndo_bpf; - default: - return NULL; - }; -} - -static struct bpf_xdp_link *dev_xdp_link(struct net_device *dev, - enum bpf_xdp_mode mode) -{ - return dev->xdp_state[mode].link; -} - -static struct bpf_prog *dev_xdp_prog(struct net_device *dev, - enum bpf_xdp_mode mode) -{ - struct bpf_xdp_link *link = dev_xdp_link(dev, mode); - - if (link) - return link->link.prog; - return dev->xdp_state[mode].prog; -} - -u32 dev_xdp_prog_id(struct net_device *dev, enum bpf_xdp_mode mode) -{ - struct bpf_prog *prog = dev_xdp_prog(dev, mode); - - return prog ? prog->aux->id : 0; -} - -static void dev_xdp_set_link(struct net_device *dev, enum bpf_xdp_mode mode, - struct bpf_xdp_link *link) -{ - dev->xdp_state[mode].link = link; - dev->xdp_state[mode].prog = NULL; -} - -static void dev_xdp_set_prog(struct net_device *dev, enum bpf_xdp_mode mode, - struct bpf_prog *prog) -{ - dev->xdp_state[mode].link = NULL; - dev->xdp_state[mode].prog = prog; -} - -static int dev_xdp_install(struct net_device *dev, enum bpf_xdp_mode mode, - bpf_op_t bpf_op, struct netlink_ext_ack *extack, - u32 flags, struct bpf_prog *prog) +u32 __dev_xdp_query(struct net_device *dev, bpf_op_t bpf_op, + enum bpf_netdev_command cmd) { struct netdev_bpf xdp; - int err; + + if (!bpf_op) + return 0; memset(&xdp, 0, sizeof(xdp)); - xdp.command = mode == XDP_MODE_HW ? XDP_SETUP_PROG_HW : XDP_SETUP_PROG; + xdp.command = cmd; + + /* Query must always succeed. */ + WARN_ON(bpf_op(dev, &xdp) < 0 && cmd == XDP_QUERY_PROG); + + return xdp.prog_id; +} + +static int dev_xdp_install(struct net_device *dev, bpf_op_t bpf_op, + struct netlink_ext_ack *extack, u32 flags, + struct bpf_prog *prog) +{ + struct netdev_bpf xdp; + + memset(&xdp, 0, sizeof(xdp)); + if (flags & XDP_FLAGS_HW_MODE) + xdp.command = XDP_SETUP_PROG_HW; + else + xdp.command = XDP_SETUP_PROG; xdp.extack = extack; xdp.flags = flags; xdp.prog = prog; - /* Drivers assume refcnt is already incremented (i.e, prog pointer is - * "moved" into driver), so they don't increment it on their own, but - * they do decrement refcnt when program is detached or replaced. - * Given net_device also owns link/prog, we need to bump refcnt here - * to prevent drivers from underflowing it. - */ - if (prog) - bpf_prog_inc(prog); - err = bpf_op(dev, &xdp); - if (err) { - if (prog) - bpf_prog_put(prog); - return err; - } - - if (mode != XDP_MODE_HW) - bpf_prog_change_xdp(dev_xdp_prog(dev, mode), prog); - - return 0; + return bpf_op(dev, &xdp); } static void dev_xdp_uninstall(struct net_device *dev) { - struct bpf_xdp_link *link; - struct bpf_prog *prog; - enum bpf_xdp_mode mode; - bpf_op_t bpf_op; + struct netdev_bpf xdp; + bpf_op_t ndo_bpf; - ASSERT_RTNL(); + /* Remove generic XDP */ + WARN_ON(dev_xdp_install(dev, generic_xdp_install, NULL, 0, NULL)); - for (mode = XDP_MODE_SKB; mode < __MAX_XDP_MODE; mode++) { - prog = dev_xdp_prog(dev, mode); - if (!prog) - continue; + /* Remove from the driver */ + ndo_bpf = dev->netdev_ops->ndo_bpf; + if (!ndo_bpf) + return; - bpf_op = dev_xdp_bpf_op(dev, mode); - if (!bpf_op) - continue; + memset(&xdp, 0, sizeof(xdp)); + xdp.command = XDP_QUERY_PROG; + WARN_ON(ndo_bpf(dev, &xdp)); + if (xdp.prog_id) + WARN_ON(dev_xdp_install(dev, ndo_bpf, NULL, xdp.prog_flags, + NULL)); - WARN_ON(dev_xdp_install(dev, mode, bpf_op, NULL, 0, NULL)); - - /* auto-detach link from net device */ - link = dev_xdp_link(dev, mode); - if (link) - link->dev = NULL; - else - bpf_prog_put(prog); - - dev_xdp_set_link(dev, mode, NULL); - } -} - -static int dev_xdp_attach(struct net_device *dev, struct netlink_ext_ack *extack, - struct bpf_xdp_link *link, struct bpf_prog *new_prog, - struct bpf_prog *old_prog, u32 flags) -{ - struct bpf_prog *cur_prog; - enum bpf_xdp_mode mode; - bpf_op_t bpf_op; - int err; - - ASSERT_RTNL(); - - /* either link or prog attachment, never both */ - if (link && (new_prog || old_prog)) - return -EINVAL; - /* link supports only XDP mode flags */ - if (link && (flags & ~XDP_FLAGS_MODES)) { - NL_SET_ERR_MSG(extack, "Invalid XDP flags for BPF link attachment"); - return -EINVAL; - } - /* just one XDP mode bit should be set, zero defaults to SKB mode */ - if (hweight32(flags & XDP_FLAGS_MODES) > 1) { - NL_SET_ERR_MSG(extack, "Only one XDP mode flag can be set"); - return -EINVAL; - } - /* old_prog != NULL implies XDP_FLAGS_REPLACE is set */ - if (old_prog && !(flags & XDP_FLAGS_REPLACE)) { - NL_SET_ERR_MSG(extack, "XDP_FLAGS_REPLACE is not specified"); - return -EINVAL; - } - - mode = dev_xdp_mode(flags); - /* can't replace attached link */ - if (dev_xdp_link(dev, mode)) { - NL_SET_ERR_MSG(extack, "Can't replace active BPF XDP link"); - return -EBUSY; - } - - cur_prog = dev_xdp_prog(dev, mode); - /* can't replace attached prog with link */ - if (link && cur_prog) { - NL_SET_ERR_MSG(extack, "Can't replace active XDP program with BPF link"); - return -EBUSY; - } - if ((flags & XDP_FLAGS_REPLACE) && cur_prog != old_prog) { - NL_SET_ERR_MSG(extack, "Active program does not match expected"); - return -EEXIST; - } - if ((flags & XDP_FLAGS_UPDATE_IF_NOEXIST) && cur_prog) { - NL_SET_ERR_MSG(extack, "XDP program already attached"); - return -EBUSY; - } - - /* put effective new program into new_prog */ - if (link) - new_prog = link->link.prog; - - if (new_prog) { - bool offload = mode == XDP_MODE_HW; - enum bpf_xdp_mode other_mode = mode == XDP_MODE_SKB - ? XDP_MODE_DRV : XDP_MODE_SKB; - - if (!offload && dev_xdp_prog(dev, other_mode)) { - NL_SET_ERR_MSG(extack, "Native and generic XDP can't be active at the same time"); - return -EEXIST; - } - if (!offload && bpf_prog_is_dev_bound(new_prog->aux)) { - NL_SET_ERR_MSG(extack, "Using device-bound program without HW_MODE flag is not supported"); - return -EINVAL; - } - if (new_prog->expected_attach_type == BPF_XDP_DEVMAP) { - NL_SET_ERR_MSG(extack, "BPF_XDP_DEVMAP programs can not be attached to a device"); - return -EINVAL; - } - if (new_prog->expected_attach_type == BPF_XDP_CPUMAP) { - NL_SET_ERR_MSG(extack, "BPF_XDP_CPUMAP programs can not be attached to a device"); - return -EINVAL; - } - } - - /* don't call drivers if the effective program didn't change */ - if (new_prog != cur_prog) { - bpf_op = dev_xdp_bpf_op(dev, mode); - if (!bpf_op) { - NL_SET_ERR_MSG(extack, "Underlying driver does not support XDP in native mode"); - return -EOPNOTSUPP; - } - - err = dev_xdp_install(dev, mode, bpf_op, extack, flags, new_prog); - if (err) - return err; - } - - if (link) - dev_xdp_set_link(dev, mode, link); - else - dev_xdp_set_prog(dev, mode, new_prog); - if (cur_prog) - bpf_prog_put(cur_prog); - - return 0; -} - -static int dev_xdp_attach_link(struct net_device *dev, - struct netlink_ext_ack *extack, - struct bpf_xdp_link *link) -{ - return dev_xdp_attach(dev, extack, link, NULL, NULL, link->flags); -} - -static int dev_xdp_detach_link(struct net_device *dev, - struct netlink_ext_ack *extack, - struct bpf_xdp_link *link) -{ - enum bpf_xdp_mode mode; - bpf_op_t bpf_op; - - ASSERT_RTNL(); - - mode = dev_xdp_mode(link->flags); - if (dev_xdp_link(dev, mode) != link) - return -EINVAL; - - bpf_op = dev_xdp_bpf_op(dev, mode); - WARN_ON(dev_xdp_install(dev, mode, bpf_op, NULL, 0, NULL)); - dev_xdp_set_link(dev, mode, NULL); - return 0; -} - -static void bpf_xdp_link_release(struct bpf_link *link) -{ - struct bpf_xdp_link *xdp_link = container_of(link, struct bpf_xdp_link, link); - - rtnl_lock(); - - /* if racing with net_device's tear down, xdp_link->dev might be - * already NULL, in which case link was already auto-detached - */ - if (xdp_link->dev) { - WARN_ON(dev_xdp_detach_link(xdp_link->dev, NULL, xdp_link)); - xdp_link->dev = NULL; - } - - rtnl_unlock(); -} - -static int bpf_xdp_link_detach(struct bpf_link *link) -{ - bpf_xdp_link_release(link); - return 0; -} - -static void bpf_xdp_link_dealloc(struct bpf_link *link) -{ - struct bpf_xdp_link *xdp_link = container_of(link, struct bpf_xdp_link, link); - - kfree(xdp_link); -} - -static void bpf_xdp_link_show_fdinfo(const struct bpf_link *link, - struct seq_file *seq) -{ - struct bpf_xdp_link *xdp_link = container_of(link, struct bpf_xdp_link, link); - u32 ifindex = 0; - - rtnl_lock(); - if (xdp_link->dev) - ifindex = xdp_link->dev->ifindex; - rtnl_unlock(); - - seq_printf(seq, "ifindex:\t%u\n", ifindex); -} - -static int bpf_xdp_link_fill_link_info(const struct bpf_link *link, - struct bpf_link_info *info) -{ - struct bpf_xdp_link *xdp_link = container_of(link, struct bpf_xdp_link, link); - u32 ifindex = 0; - - rtnl_lock(); - if (xdp_link->dev) - ifindex = xdp_link->dev->ifindex; - rtnl_unlock(); - - info->xdp.ifindex = ifindex; - return 0; -} - -static int bpf_xdp_link_update(struct bpf_link *link, struct bpf_prog *new_prog, - struct bpf_prog *old_prog) -{ - struct bpf_xdp_link *xdp_link = container_of(link, struct bpf_xdp_link, link); - enum bpf_xdp_mode mode; - bpf_op_t bpf_op; - int err = 0; - - rtnl_lock(); - - /* link might have been auto-released already, so fail */ - if (!xdp_link->dev) { - err = -ENOLINK; - goto out_unlock; - } - - if (old_prog && link->prog != old_prog) { - err = -EPERM; - goto out_unlock; - } - old_prog = link->prog; - if (old_prog == new_prog) { - /* no-op, don't disturb drivers */ - bpf_prog_put(new_prog); - goto out_unlock; - } - - mode = dev_xdp_mode(xdp_link->flags); - bpf_op = dev_xdp_bpf_op(xdp_link->dev, mode); - err = dev_xdp_install(xdp_link->dev, mode, bpf_op, NULL, - xdp_link->flags, new_prog); - if (err) - goto out_unlock; - - old_prog = xchg(&link->prog, new_prog); - bpf_prog_put(old_prog); - -out_unlock: - rtnl_unlock(); - return err; -} - -static const struct bpf_link_ops bpf_xdp_link_lops = { - .release = bpf_xdp_link_release, - .dealloc = bpf_xdp_link_dealloc, - .detach = bpf_xdp_link_detach, - .show_fdinfo = bpf_xdp_link_show_fdinfo, - .fill_link_info = bpf_xdp_link_fill_link_info, - .update_prog = bpf_xdp_link_update, -}; - -int bpf_xdp_link_attach(const union bpf_attr *attr, struct bpf_prog *prog) -{ - struct net *net = current->nsproxy->net_ns; - struct bpf_link_primer link_primer; - struct bpf_xdp_link *link; - struct net_device *dev; - int err, fd; - - dev = dev_get_by_index(net, attr->link_create.target_ifindex); - if (!dev) - return -EINVAL; - - link = kzalloc(sizeof(*link), GFP_USER); - if (!link) { - err = -ENOMEM; - goto out_put_dev; - } - - bpf_link_init(&link->link, BPF_LINK_TYPE_XDP, &bpf_xdp_link_lops, prog); - link->dev = dev; - link->flags = attr->link_create.flags; - - err = bpf_link_prime(&link->link, &link_primer); - if (err) { - kfree(link); - goto out_put_dev; - } - - rtnl_lock(); - err = dev_xdp_attach_link(dev, NULL, link); - rtnl_unlock(); - - if (err) { - bpf_link_cleanup(&link_primer); - goto out_put_dev; - } - - fd = bpf_link_settle(&link_primer); - /* link itself doesn't hold dev's refcnt to not complicate shutdown */ - dev_put(dev); - return fd; - -out_put_dev: - dev_put(dev); - return err; + /* Remove HW offload */ + memset(&xdp, 0, sizeof(xdp)); + xdp.command = XDP_QUERY_PROG_HW; + if (!ndo_bpf(dev, &xdp) && xdp.prog_id) + WARN_ON(dev_xdp_install(dev, ndo_bpf, NULL, xdp.prog_flags, + NULL)); } /** @@ -9104,44 +8549,74 @@ out_put_dev: * @dev: device * @extack: netlink extended ack * @fd: new program fd or negative value to clear - * @expected_fd: old program fd that userspace expects to replace or clear * @flags: xdp-related flags * * Set or clear a bpf program for a device */ int dev_change_xdp_fd(struct net_device *dev, struct netlink_ext_ack *extack, - int fd, int expected_fd, u32 flags) + int fd, u32 flags) { - enum bpf_xdp_mode mode = dev_xdp_mode(flags); - struct bpf_prog *new_prog = NULL, *old_prog = NULL; + const struct net_device_ops *ops = dev->netdev_ops; + enum bpf_netdev_command query; + struct bpf_prog *prog = NULL; + bpf_op_t bpf_op, bpf_chk; + bool offload; int err; ASSERT_RTNL(); + offload = flags & XDP_FLAGS_HW_MODE; + query = offload ? XDP_QUERY_PROG_HW : XDP_QUERY_PROG; + + bpf_op = bpf_chk = ops->ndo_bpf; + if (!bpf_op && (flags & (XDP_FLAGS_DRV_MODE | XDP_FLAGS_HW_MODE))) { + NL_SET_ERR_MSG(extack, "underlying driver does not support XDP in native mode"); + return -EOPNOTSUPP; + } + if (!bpf_op || (flags & XDP_FLAGS_SKB_MODE)) + bpf_op = generic_xdp_install; + if (bpf_op == bpf_chk) + bpf_chk = generic_xdp_install; + if (fd >= 0) { - new_prog = bpf_prog_get_type_dev(fd, BPF_PROG_TYPE_XDP, - mode != XDP_MODE_SKB); - if (IS_ERR(new_prog)) - return PTR_ERR(new_prog); - } + u32 prog_id; - if (expected_fd >= 0) { - old_prog = bpf_prog_get_type_dev(expected_fd, BPF_PROG_TYPE_XDP, - mode != XDP_MODE_SKB); - if (IS_ERR(old_prog)) { - err = PTR_ERR(old_prog); - old_prog = NULL; - goto err_out; + if (!offload && __dev_xdp_query(dev, bpf_chk, XDP_QUERY_PROG)) { + NL_SET_ERR_MSG(extack, "native and generic XDP can't be active at the same time"); + return -EEXIST; } + + prog_id = __dev_xdp_query(dev, bpf_op, query); + if ((flags & XDP_FLAGS_UPDATE_IF_NOEXIST) && prog_id) { + NL_SET_ERR_MSG(extack, "XDP program already attached"); + return -EBUSY; + } + + prog = bpf_prog_get_type_dev(fd, BPF_PROG_TYPE_XDP, + bpf_op == ops->ndo_bpf); + if (IS_ERR(prog)) + return PTR_ERR(prog); + + if (!offload && bpf_prog_is_dev_bound(prog->aux)) { + NL_SET_ERR_MSG(extack, "using device-bound program without HW_MODE flag is not supported"); + bpf_prog_put(prog); + return -EINVAL; + } + + /* prog->aux->id may be 0 for orphaned device-bound progs */ + if (prog->aux->id && prog->aux->id == prog_id) { + bpf_prog_put(prog); + return 0; + } + } else { + if (!__dev_xdp_query(dev, bpf_op, query)) + return 0; } - err = dev_xdp_attach(dev, extack, NULL, new_prog, old_prog, flags); + err = dev_xdp_install(dev, bpf_op, extack, flags, prog); + if (err < 0 && prog) + bpf_prog_put(prog); -err_out: - if (err && new_prog) - bpf_prog_put(new_prog); - if (old_prog) - bpf_prog_put(old_prog); return err; } @@ -10239,7 +9714,6 @@ struct net_device *alloc_netdev_mqs(int sizeof_priv, const char *name, INIT_LIST_HEAD(&dev->adj_list.lower); INIT_LIST_HEAD(&dev->ptype_all); INIT_LIST_HEAD(&dev->ptype_specific); - INIT_LIST_HEAD(&dev->net_notifier_list); #ifdef CONFIG_NET_SCHED hash_init(dev->qdisc_hash); #endif @@ -10310,8 +9784,6 @@ void free_netdev(struct net_device *dev) free_percpu(dev->pcpu_refcnt); dev->pcpu_refcnt = NULL; - free_percpu(dev->xdp_bulkq); - dev->xdp_bulkq = NULL; netdev_unregister_lockdep_key(dev); @@ -10503,9 +9975,6 @@ int dev_change_net_namespace(struct net_device *dev, struct net *net, const char kobject_uevent(&dev->dev.kobj, KOBJ_REMOVE); netdev_adjacent_del_links(dev); - /* Move per-net netdevice notifiers that are following the netdevice */ - move_netdevice_notifiers_dev_net(dev, net); - /* Actually switch the network namespace */ dev_net_set(dev, net); dev->ifindex = new_ifindex; @@ -10661,8 +10130,6 @@ static int __net_init netdev_init(struct net *net) if (net->dev_index_head == NULL) goto err_idx; - RAW_INIT_NOTIFIER_HEAD(&net->netdev_chain); - return 0; err_idx: diff --git a/net/core/devlink.c b/net/core/devlink.c index 77770ef6c6ee..5bd6330ab427 100644 --- a/net/core/devlink.c +++ b/net/core/devlink.c @@ -4127,7 +4127,7 @@ struct devlink_fmsg_item { int attrtype; u8 nla_type; u16 len; - int value[]; + int value[0]; }; struct devlink_fmsg { diff --git a/net/core/drop_monitor.c b/net/core/drop_monitor.c index 3edde3bf2f80..1c6237a88acc 100644 --- a/net/core/drop_monitor.c +++ b/net/core/drop_monitor.c @@ -67,7 +67,7 @@ struct net_dm_hw_entry { struct net_dm_hw_entries { u32 num_entries; - struct net_dm_hw_entry entries[]; + struct net_dm_hw_entry entries[0]; }; struct per_cpu_dm_data { diff --git a/net/core/filter.c b/net/core/filter.c index 5c88141ac58d..71666495df04 100644 --- a/net/core/filter.c +++ b/net/core/filter.c @@ -47,7 +47,6 @@ #include #include #include -#include #include #include #include @@ -74,38 +73,6 @@ #include #include #include -#include -#include -#include - -/* Keep the struct bpf_fib_lookup small so that it fits into a cacheline */ -static_assert(sizeof(struct bpf_fib_lookup) == 64, "struct bpf_fib_lookup size check"); - -static const struct bpf_func_proto * -bpf_sk_base_func_proto(enum bpf_func_id func_id); - -int copy_bpf_fprog_from_user(struct sock_fprog *dst, sockptr_t src, int len) -{ - if (in_compat_syscall()) { - struct compat_sock_fprog f32; - - if (len != sizeof(f32)) - return -EINVAL; - if (copy_from_sockptr(&f32, src, sizeof(f32))) - return -EFAULT; - memset(dst, 0, sizeof(*dst)); - dst->len = f32.len; - dst->filter = compat_ptr(f32.filter); - } else { - if (len != sizeof(*dst)) - return -EINVAL; - if (copy_from_sockptr(dst, src, sizeof(*dst))) - return -EFAULT; - } - - return 0; -} -EXPORT_SYMBOL_GPL(copy_bpf_fprog_from_user); /** * sk_filter_trim_cap - run a packet through a socket filter @@ -297,6 +264,17 @@ BPF_CALL_2(bpf_skb_load_helper_32_no_cache, const struct sk_buff *, skb, offset); } +BPF_CALL_0(bpf_get_raw_cpu_id) +{ + return raw_smp_processor_id(); +} + +static const struct bpf_func_proto bpf_get_raw_smp_processor_id_proto = { + .func = bpf_get_raw_cpu_id, + .gpl_only = false, + .ret_type = RET_INTEGER, +}; + static u32 convert_skb_access(int skb_field, int dst_reg, int src_reg, struct bpf_insn *insn_buf) { @@ -1505,7 +1483,7 @@ struct bpf_prog *__get_filter(struct sock_fprog *fprog, struct sock *sk) if (copy_from_user(prog->insns, fprog->filter, fsize)) { __bpf_prog_free(prog); - return ERR_PTR(-EFAULT); + return ERR_PTR(-EINVAL); } prog->len = fprog->len; @@ -1952,11 +1930,10 @@ BPF_CALL_5(bpf_l4_csum_replace, struct sk_buff *, skb, u32, offset, bool is_pseudo = flags & BPF_F_PSEUDO_HDR; bool is_mmzero = flags & BPF_F_MARK_MANGLED_0; bool do_mforce = flags & BPF_F_MARK_ENFORCE; - bool is_ipv6 = flags & BPF_F_IPV6; __sum16 *ptr; if (unlikely(flags & ~(BPF_F_MARK_MANGLED_0 | BPF_F_MARK_ENFORCE | - BPF_F_PSEUDO_HDR | BPF_F_HDR_FIELD_MASK | BPF_F_IPV6))) + BPF_F_PSEUDO_HDR | BPF_F_HDR_FIELD_MASK))) return -EINVAL; if (unlikely(offset > 0xffff || offset & 1)) return -EFAULT; @@ -1972,7 +1949,7 @@ BPF_CALL_5(bpf_l4_csum_replace, struct sk_buff *, skb, u32, offset, if (unlikely(from != 0)) return -EINVAL; - inet_proto_csum_replace_by_diff(ptr, skb, to, is_pseudo, is_ipv6); + inet_proto_csum_replace_by_diff(ptr, skb, to, is_pseudo); break; case 2: inet_proto_csum_replace2(ptr, skb, from, to, is_pseudo); @@ -2059,40 +2036,6 @@ static const struct bpf_func_proto bpf_csum_update_proto = { .arg2_type = ARG_ANYTHING, }; -BPF_CALL_2(bpf_csum_level, struct sk_buff *, skb, u64, level) -{ - /* The interface is to be used in combination with bpf_skb_adjust_room() - * for encap/decap of packet headers when BPF_F_ADJ_ROOM_NO_CSUM_RESET - * is passed as flags, for example. - */ - switch (level) { - case BPF_CSUM_LEVEL_INC: - __skb_incr_checksum_unnecessary(skb); - break; - case BPF_CSUM_LEVEL_DEC: - __skb_decr_checksum_unnecessary(skb); - break; - case BPF_CSUM_LEVEL_RESET: - __skb_reset_checksum_unnecessary(skb); - break; - case BPF_CSUM_LEVEL_QUERY: - return skb->ip_summed == CHECKSUM_UNNECESSARY ? - skb->csum_level : -EACCES; - default: - return -EINVAL; - } - - return 0; -} - -static const struct bpf_func_proto bpf_csum_level_proto = { - .func = bpf_csum_level, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX, - .arg2_type = ARG_ANYTHING, -}; - static inline int __bpf_rx_skb(struct net_device *dev, struct sk_buff *skb) { return dev_forward_skb(dev, skb); @@ -2185,266 +2128,13 @@ static int __bpf_redirect(struct sk_buff *skb, struct net_device *dev, return __bpf_redirect_no_mac(skb, dev, flags); } -#if IS_ENABLED(CONFIG_IPV6) -static int bpf_out_neigh_v6(struct net *net, struct sk_buff *skb, - struct net_device *dev, struct bpf_nh_params *nh) -{ - u32 hh_len = LL_RESERVED_SPACE(dev); - const struct in6_addr *nexthop; - struct dst_entry *dst = NULL; - struct neighbour *neigh; - - if (dev_xmit_recursion()) { - net_crit_ratelimited("bpf: recursion limit reached on datapath, buggy bpf program?\n"); - goto out_drop; - } - - skb->dev = dev; - skb->tstamp = 0; - - if (unlikely(skb_headroom(skb) < hh_len && dev->header_ops)) { - struct sk_buff *skb2; - - skb2 = skb_realloc_headroom(skb, hh_len); - if (unlikely(!skb2)) { - kfree_skb(skb); - return -ENOMEM; - } - if (skb->sk) - skb_set_owner_w(skb2, skb->sk); - consume_skb(skb); - skb = skb2; - } - - rcu_read_lock_bh(); - if (!nh) { - dst = skb_dst(skb); - nexthop = rt6_nexthop(container_of(dst, struct rt6_info, dst), - &ipv6_hdr(skb)->daddr); - } else { - nexthop = &nh->ipv6_nh; - } - neigh = ip_neigh_gw6(dev, nexthop); - if (likely(!IS_ERR(neigh))) { - int ret; - - sock_confirm_neigh(skb, neigh); - dev_xmit_recursion_inc(); - ret = neigh_output(neigh, skb, false); - dev_xmit_recursion_dec(); - rcu_read_unlock_bh(); - return ret; - } - rcu_read_unlock_bh(); - if (dst) - IP6_INC_STATS(dev_net(dst->dev), - ip6_dst_idev(dst), IPSTATS_MIB_OUTNOROUTES); -out_drop: - kfree_skb(skb); - return -ENETDOWN; -} - -static int __bpf_redirect_neigh_v6(struct sk_buff *skb, struct net_device *dev, - struct bpf_nh_params *nh) -{ - const struct ipv6hdr *ip6h = ipv6_hdr(skb); - struct net *net = dev_net(dev); - int err, ret = NET_XMIT_DROP; - - if (!nh) { - struct dst_entry *dst; - struct flowi6 fl6 = { - .flowi6_flags = FLOWI_FLAG_ANYSRC, - .flowi6_mark = skb->mark, - .flowlabel = ip6_flowinfo(ip6h), - .flowi6_oif = dev->ifindex, - .flowi6_proto = ip6h->nexthdr, - .daddr = ip6h->daddr, - .saddr = ip6h->saddr, - }; - - dst = ipv6_stub->ipv6_dst_lookup_flow(net, NULL, &fl6, NULL); - if (IS_ERR(dst)) - goto out_drop; - - skb_dst_set(skb, dst); - } else if (nh->nh_family != AF_INET6) { - goto out_drop; - } - - err = bpf_out_neigh_v6(net, skb, dev, nh); - if (unlikely(net_xmit_eval(err))) - dev->stats.tx_errors++; - else - ret = NET_XMIT_SUCCESS; - goto out_xmit; -out_drop: - dev->stats.tx_errors++; - kfree_skb(skb); -out_xmit: - return ret; -} -#else -static int __bpf_redirect_neigh_v6(struct sk_buff *skb, struct net_device *dev, - struct bpf_nh_params *nh) -{ - kfree_skb(skb); - return NET_XMIT_DROP; -} -#endif /* CONFIG_IPV6 */ - -#if IS_ENABLED(CONFIG_INET) -static int bpf_out_neigh_v4(struct net *net, struct sk_buff *skb, - struct net_device *dev, struct bpf_nh_params *nh) -{ - u32 hh_len = LL_RESERVED_SPACE(dev); - struct neighbour *neigh; - bool is_v6gw = false; - - if (dev_xmit_recursion()) { - net_crit_ratelimited("bpf: recursion limit reached on datapath, buggy bpf program?\n"); - goto out_drop; - } - - skb->dev = dev; - skb->tstamp = 0; - - if (unlikely(skb_headroom(skb) < hh_len && dev->header_ops)) { - struct sk_buff *skb2; - - skb2 = skb_realloc_headroom(skb, hh_len); - if (unlikely(!skb2)) { - kfree_skb(skb); - return -ENOMEM; - } - if (skb->sk) - skb_set_owner_w(skb2, skb->sk); - consume_skb(skb); - skb = skb2; - } - - rcu_read_lock_bh(); - if (!nh) { - struct dst_entry *dst = skb_dst(skb); - struct rtable *rt = container_of(dst, struct rtable, dst); - - neigh = ip_neigh_for_gw(rt, skb, &is_v6gw); - } else if (nh->nh_family == AF_INET6) { - neigh = ip_neigh_gw6(dev, &nh->ipv6_nh); - is_v6gw = true; - } else if (nh->nh_family == AF_INET) { - neigh = ip_neigh_gw4(dev, nh->ipv4_nh); - } else { - rcu_read_unlock_bh(); - goto out_drop; - } - - if (likely(!IS_ERR(neigh))) { - int ret; - - sock_confirm_neigh(skb, neigh); - dev_xmit_recursion_inc(); - ret = neigh_output(neigh, skb, is_v6gw); - dev_xmit_recursion_dec(); - rcu_read_unlock_bh(); - return ret; - } - rcu_read_unlock_bh(); -out_drop: - kfree_skb(skb); - return -ENETDOWN; -} - -static int __bpf_redirect_neigh_v4(struct sk_buff *skb, struct net_device *dev, - struct bpf_nh_params *nh) -{ - const struct iphdr *ip4h = ip_hdr(skb); - struct net *net = dev_net(dev); - int err, ret = NET_XMIT_DROP; - - if (!nh) { - struct flowi4 fl4 = { - .flowi4_flags = FLOWI_FLAG_ANYSRC, - .flowi4_mark = skb->mark, - .flowi4_tos = RT_TOS(ip4h->tos), - .flowi4_oif = dev->ifindex, - .flowi4_proto = ip4h->protocol, - .daddr = ip4h->daddr, - .saddr = ip4h->saddr, - }; - struct rtable *rt; - - rt = ip_route_output_flow(net, &fl4, NULL); - if (IS_ERR(rt)) - goto out_drop; - if (rt->rt_type != RTN_UNICAST && rt->rt_type != RTN_LOCAL) { - ip_rt_put(rt); - goto out_drop; - } - - skb_dst_set(skb, &rt->dst); - } - - err = bpf_out_neigh_v4(net, skb, dev, nh); - if (unlikely(net_xmit_eval(err))) - dev->stats.tx_errors++; - else - ret = NET_XMIT_SUCCESS; - goto out_xmit; -out_drop: - dev->stats.tx_errors++; - kfree_skb(skb); -out_xmit: - return ret; -} -#else -static int __bpf_redirect_neigh_v4(struct sk_buff *skb, struct net_device *dev, - struct bpf_nh_params *nh) -{ - kfree_skb(skb); - return NET_XMIT_DROP; -} -#endif /* CONFIG_INET */ - -static int __bpf_redirect_neigh(struct sk_buff *skb, struct net_device *dev, - struct bpf_nh_params *nh) -{ - struct ethhdr *ethh = eth_hdr(skb); - - if (unlikely(skb->mac_header >= skb->network_header)) - goto out; - bpf_push_mac_rcsum(skb); - if (is_multicast_ether_addr(ethh->h_dest)) - goto out; - - skb_pull(skb, sizeof(*ethh)); - skb_unset_mac_header(skb); - skb_reset_network_header(skb); - - if (skb->protocol == htons(ETH_P_IP)) - return __bpf_redirect_neigh_v4(skb, dev, nh); - else if (skb->protocol == htons(ETH_P_IPV6)) - return __bpf_redirect_neigh_v6(skb, dev, nh); -out: - kfree_skb(skb); - return -ENOTSUPP; -} - -/* Internal, non-exposed redirect flags. */ -enum { - BPF_F_NEIGH = (1ULL << 1), - BPF_F_PEER = (1ULL << 2), - BPF_F_NEXTHOP = (1ULL << 3), -#define BPF_F_REDIRECT_INTERNAL (BPF_F_NEIGH | BPF_F_PEER | BPF_F_NEXTHOP) -}; - BPF_CALL_3(bpf_clone_redirect, struct sk_buff *, skb, u32, ifindex, u64, flags) { struct net_device *dev; struct sk_buff *clone; int ret; - if (unlikely(flags & (~(BPF_F_INGRESS) | BPF_F_REDIRECT_INTERNAL))) + if (unlikely(flags & ~(BPF_F_INGRESS))) return -EINVAL; dev = dev_get_by_index_rcu(dev_net(skb->dev), ifindex); @@ -2481,46 +2171,11 @@ static const struct bpf_func_proto bpf_clone_redirect_proto = { DEFINE_PER_CPU(struct bpf_redirect_info, bpf_redirect_info); EXPORT_PER_CPU_SYMBOL_GPL(bpf_redirect_info); -int skb_do_redirect(struct sk_buff *skb) -{ - struct bpf_redirect_info *ri = this_cpu_ptr(&bpf_redirect_info); - struct net *net = dev_net(skb->dev); - struct net_device *dev; - u32 flags = ri->flags; - - dev = dev_get_by_index_rcu(net, ri->tgt_index); - ri->tgt_index = 0; - ri->flags = 0; - if (unlikely(!dev)) - goto out_drop; - if (flags & BPF_F_PEER) { - const struct net_device_ops *ops = dev->netdev_ops; - - if (unlikely(!ops->ndo_get_peer_dev || - !skb_at_tc_ingress(skb))) - goto out_drop; - dev = ops->ndo_get_peer_dev(dev); - if (unlikely(!dev || - !is_skb_forwardable(dev, skb) || - net_eq(net, dev_net(dev)))) - goto out_drop; - skb->dev = dev; - return -EAGAIN; - } - return flags & BPF_F_NEIGH ? - __bpf_redirect_neigh(skb, dev, flags & BPF_F_NEXTHOP ? - &ri->nh : NULL) : - __bpf_redirect(skb, dev, flags); -out_drop: - kfree_skb(skb); - return -EINVAL; -} - BPF_CALL_2(bpf_redirect, u32, ifindex, u64, flags) { struct bpf_redirect_info *ri = this_cpu_ptr(&bpf_redirect_info); - if (unlikely(flags & (~(BPF_F_INGRESS) | BPF_F_REDIRECT_INTERNAL))) + if (unlikely(flags & ~(BPF_F_INGRESS))) return TC_ACT_SHOT; ri->flags = flags; @@ -2529,6 +2184,21 @@ BPF_CALL_2(bpf_redirect, u32, ifindex, u64, flags) return TC_ACT_REDIRECT; } +int skb_do_redirect(struct sk_buff *skb) +{ + struct bpf_redirect_info *ri = this_cpu_ptr(&bpf_redirect_info); + struct net_device *dev; + + dev = dev_get_by_index_rcu(dev_net(skb->dev), ri->tgt_index); + ri->tgt_index = 0; + if (unlikely(!dev)) { + kfree_skb(skb); + return -EINVAL; + } + + return __bpf_redirect(skb, dev, ri->flags); +} + static const struct bpf_func_proto bpf_redirect_proto = { .func = bpf_redirect, .gpl_only = false, @@ -2537,55 +2207,6 @@ static const struct bpf_func_proto bpf_redirect_proto = { .arg2_type = ARG_ANYTHING, }; -BPF_CALL_2(bpf_redirect_peer, u32, ifindex, u64, flags) -{ - struct bpf_redirect_info *ri = this_cpu_ptr(&bpf_redirect_info); - - if (unlikely(flags)) - return TC_ACT_SHOT; - - ri->flags = BPF_F_PEER; - ri->tgt_index = ifindex; - - return TC_ACT_REDIRECT; -} - -static const struct bpf_func_proto bpf_redirect_peer_proto = { - .func = bpf_redirect_peer, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_ANYTHING, - .arg2_type = ARG_ANYTHING, -}; - -BPF_CALL_4(bpf_redirect_neigh, u32, ifindex, struct bpf_redir_neigh *, params, - int, plen, u64, flags) -{ - struct bpf_redirect_info *ri = this_cpu_ptr(&bpf_redirect_info); - - if (unlikely((plen && plen < sizeof(*params)) || flags)) - return TC_ACT_SHOT; - - ri->flags = BPF_F_NEIGH | (plen ? BPF_F_NEXTHOP : 0); - ri->tgt_index = ifindex; - - BUILD_BUG_ON(sizeof(struct bpf_redir_neigh) != sizeof(struct bpf_nh_params)); - if (plen) - memcpy(&ri->nh, params, sizeof(ri->nh)); - - return TC_ACT_REDIRECT; -} - -static const struct bpf_func_proto bpf_redirect_neigh_proto = { - .func = bpf_redirect_neigh, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_ANYTHING, - .arg2_type = ARG_PTR_TO_MEM_OR_NULL, - .arg3_type = ARG_CONST_SIZE_OR_ZERO, - .arg4_type = ARG_ANYTHING, -}; - BPF_CALL_2(bpf_msg_apply_bytes, struct sk_msg *, msg, u32, bytes) { msg->apply_bytes = bytes; @@ -2658,7 +2279,7 @@ BPF_CALL_4(bpf_msg_pull_data, struct sk_msg *, msg, u32, start, * account for the headroom. */ bytes_sg_total = start - offset + bytes; - if (!test_bit(i, &msg->sg.copy) && bytes_sg_total <= len) + if (!msg->sg.copy[i] && bytes_sg_total <= len) goto out; /* At this point we need to linearize multiple scatterlist @@ -2766,9 +2387,6 @@ BPF_CALL_4(bpf_msg_push_data, struct sk_msg *, msg, u32, start, if (unlikely(flags)) return -EINVAL; - if (unlikely(len == 0)) - return 0; - /* First find the starting scatterlist element */ i = msg->sg.start; do { @@ -2881,7 +2499,7 @@ place_new: /* Place newly allocated data buffer */ sk_mem_charge(msg->sk, len); msg->sg.size += len; - __clear_bit(new, &msg->sg.copy); + msg->sg.copy[new] = false; sg_set_page(&msg->sg.data[new], page, len + copy, 0); if (rsge.length) { get_page(sg_page(&rsge)); @@ -3076,36 +2694,6 @@ static const struct bpf_func_proto bpf_msg_pop_data_proto = { .arg4_type = ARG_ANYTHING, }; -#ifdef CONFIG_CGROUP_NET_CLASSID -BPF_CALL_0(bpf_get_cgroup_classid_curr) -{ - return __task_get_classid(current); -} - -static const struct bpf_func_proto bpf_get_cgroup_classid_curr_proto = { - .func = bpf_get_cgroup_classid_curr, - .gpl_only = false, - .ret_type = RET_INTEGER, -}; - -BPF_CALL_1(bpf_skb_cgroup_classid, const struct sk_buff *, skb) -{ - struct sock *sk = skb_to_full_sk(skb); - - if (!sk || !sk_fullsock(sk)) - return 0; - - return sock_cgroup_classid(&sk->sk_cgrp_data); -} - -static const struct bpf_func_proto bpf_skb_cgroup_classid_proto = { - .func = bpf_skb_cgroup_classid, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX, -}; -#endif - BPF_CALL_1(bpf_get_cgroup_classid, const struct sk_buff *, skb) { return task_get_classid(skb); @@ -3304,6 +2892,9 @@ static int bpf_skb_proto_4_to_6(struct sk_buff *skb) u32 off = skb_mac_header_len(skb); int ret; + if (skb_is_gso(skb) && !skb_is_gso_tcp(skb)) + return -ENOTSUPP; + ret = skb_cow(skb, len_diff); if (unlikely(ret < 0)) return ret; @@ -3315,11 +2906,17 @@ static int bpf_skb_proto_4_to_6(struct sk_buff *skb) if (skb_is_gso(skb)) { struct skb_shared_info *shinfo = skb_shinfo(skb); - /* SKB_GSO_TCPV4 needs to be changed into SKB_GSO_TCPV6. */ + /* SKB_GSO_TCPV4 needs to be changed into + * SKB_GSO_TCPV6. + */ if (shinfo->gso_type & SKB_GSO_TCPV4) { shinfo->gso_type &= ~SKB_GSO_TCPV4; shinfo->gso_type |= SKB_GSO_TCPV6; } + + /* Header must be checked, and gso_segs recomputed. */ + shinfo->gso_type |= SKB_GSO_DODGY; + shinfo->gso_segs = 0; } skb->protocol = htons(ETH_P_IPV6); @@ -3334,6 +2931,9 @@ static int bpf_skb_proto_6_to_4(struct sk_buff *skb) u32 off = skb_mac_header_len(skb); int ret; + if (skb_is_gso(skb) && !skb_is_gso_tcp(skb)) + return -ENOTSUPP; + ret = skb_unclone(skb, GFP_ATOMIC); if (unlikely(ret < 0)) return ret; @@ -3345,11 +2945,17 @@ static int bpf_skb_proto_6_to_4(struct sk_buff *skb) if (skb_is_gso(skb)) { struct skb_shared_info *shinfo = skb_shinfo(skb); - /* SKB_GSO_TCPV6 needs to be changed into SKB_GSO_TCPV4. */ + /* SKB_GSO_TCPV6 needs to be changed into + * SKB_GSO_TCPV4. + */ if (shinfo->gso_type & SKB_GSO_TCPV6) { shinfo->gso_type &= ~SKB_GSO_TCPV6; shinfo->gso_type |= SKB_GSO_TCPV4; } + + /* Header must be checked, and gso_segs recomputed. */ + shinfo->gso_type |= SKB_GSO_DODGY; + shinfo->gso_segs = 0; } skb->protocol = htons(ETH_P_IP); @@ -3563,8 +3169,7 @@ static int bpf_skb_net_shrink(struct sk_buff *skb, u32 off, u32 len_diff, { int ret; - if (unlikely(flags & ~(BPF_F_ADJ_ROOM_FIXED_GSO | - BPF_F_ADJ_ROOM_NO_CSUM_RESET))) + if (flags & ~BPF_F_ADJ_ROOM_FIXED_GSO) return -EINVAL; if (skb_is_gso(skb) && !skb_is_gso_tcp(skb)) { @@ -3599,48 +3204,6 @@ static int bpf_skb_net_shrink(struct sk_buff *skb, u32 off, u32 len_diff, #define BPF_SKB_MAX_LEN SKB_MAX_ALLOC -BPF_CALL_4(sk_skb_adjust_room, struct sk_buff *, skb, s32, len_diff, - u32, mode, u64, flags) -{ - u32 len_diff_abs = abs(len_diff); - bool shrink = len_diff < 0; - int ret = 0; - - if (unlikely(flags || mode)) - return -EINVAL; - if (unlikely(len_diff_abs > 0xfffU)) - return -EFAULT; - - if (!shrink) { - ret = skb_cow(skb, len_diff); - if (unlikely(ret < 0)) - return ret; - __skb_push(skb, len_diff_abs); - memset(skb->data, 0, len_diff_abs); - } else { - if (unlikely(!pskb_may_pull(skb, len_diff_abs))) - return -ENOMEM; - __skb_pull(skb, len_diff_abs); - } - bpf_compute_data_end_sk_skb(skb); - if (tls_sw_has_ctx_rx(skb->sk)) { - struct strp_msg *rxm = strp_msg(skb); - - rxm->full_len += len_diff; - } - return ret; -} - -static const struct bpf_func_proto sk_skb_adjust_room_proto = { - .func = sk_skb_adjust_room, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX, - .arg2_type = ARG_ANYTHING, - .arg3_type = ARG_ANYTHING, - .arg4_type = ARG_ANYTHING, -}; - BPF_CALL_4(bpf_skb_adjust_room, struct sk_buff *, skb, s32, len_diff, u32, mode, u64, flags) { @@ -3652,8 +3215,7 @@ BPF_CALL_4(bpf_skb_adjust_room, struct sk_buff *, skb, s32, len_diff, u32 off; int ret; - if (unlikely(flags & ~(BPF_F_ADJ_ROOM_MASK | - BPF_F_ADJ_ROOM_NO_CSUM_RESET))) + if (unlikely(flags & ~BPF_F_ADJ_ROOM_MASK)) return -EINVAL; if (unlikely(len_diff_abs > 0xfffU)) return -EFAULT; @@ -3681,8 +3243,6 @@ BPF_CALL_4(bpf_skb_adjust_room, struct sk_buff *, skb, s32, len_diff, ret = shrink ? bpf_skb_net_shrink(skb, off, len_diff_abs, flags) : bpf_skb_net_grow(skb, off, len_diff_abs, flags); - if (!ret && !(flags & BPF_F_ADJ_ROOM_NO_CSUM_RESET)) - __skb_reset_checksum_unnecessary(skb); bpf_compute_data_pointers(skb); return ret; @@ -3913,26 +3473,15 @@ static const struct bpf_func_proto bpf_xdp_adjust_head_proto = { BPF_CALL_2(bpf_xdp_adjust_tail, struct xdp_buff *, xdp, int, offset) { - void *data_hard_end = xdp_data_hard_end(xdp); /* use xdp->frame_sz */ void *data_end = xdp->data_end + offset; - /* Notice that xdp_data_hard_end have reserved some tailroom */ - if (unlikely(data_end > data_hard_end)) + /* only shrinking is allowed for now. */ + if (unlikely(offset >= 0)) return -EINVAL; - /* ALL drivers MUST init xdp->frame_sz, chicken check below */ - if (unlikely(xdp->frame_sz > PAGE_SIZE)) { - WARN_ONCE(1, "Too BIG xdp->frame_sz = %d\n", xdp->frame_sz); - return -EINVAL; - } - if (unlikely(data_end < xdp->data + ETH_HLEN)) return -EINVAL; - /* Clear memory area on grow, can contain uninit kernel memory */ - if (offset > 0) - memset(xdp->data_end, 0, offset); - xdp->data_end = data_end; return 0; @@ -3974,30 +3523,119 @@ static const struct bpf_func_proto bpf_xdp_adjust_meta_proto = { .arg2_type = ARG_ANYTHING, }; -static int __bpf_tx_xdp_map(struct net_device *dev_rx, void *fwd, - struct bpf_map *map, struct xdp_buff *xdp) +static int __bpf_tx_xdp(struct net_device *dev, + struct bpf_map *map, + struct xdp_buff *xdp, + u32 index) { + struct xdp_frame *xdpf; + int err, sent; + + if (!dev->netdev_ops->ndo_xdp_xmit) { + return -EOPNOTSUPP; + } + + err = xdp_ok_fwd_dev(dev, xdp->data_end - xdp->data); + if (unlikely(err)) + return err; + + xdpf = convert_to_xdp_frame(xdp); + if (unlikely(!xdpf)) + return -EOVERFLOW; + + sent = dev->netdev_ops->ndo_xdp_xmit(dev, 1, &xdpf, XDP_XMIT_FLUSH); + if (sent <= 0) + return sent; + return 0; +} + +static noinline int +xdp_do_redirect_slow(struct net_device *dev, struct xdp_buff *xdp, + struct bpf_prog *xdp_prog, struct bpf_redirect_info *ri) +{ + struct net_device *fwd; + u32 index = ri->tgt_index; + int err; + + fwd = dev_get_by_index_rcu(dev_net(dev), index); + ri->tgt_index = 0; + if (unlikely(!fwd)) { + err = -EINVAL; + goto err; + } + + err = __bpf_tx_xdp(fwd, NULL, xdp, 0); + if (unlikely(err)) + goto err; + + _trace_xdp_redirect(dev, xdp_prog, index); + return 0; +err: + _trace_xdp_redirect_err(dev, xdp_prog, index, err); + return err; +} + +static int __bpf_tx_xdp_map(struct net_device *dev_rx, void *fwd, + struct bpf_map *map, + struct xdp_buff *xdp, + u32 index) +{ + int err; + switch (map->map_type) { case BPF_MAP_TYPE_DEVMAP: - case BPF_MAP_TYPE_DEVMAP_HASH: - return dev_map_enqueue(fwd, xdp, dev_rx); - case BPF_MAP_TYPE_CPUMAP: - return cpu_map_enqueue(fwd, xdp, dev_rx); - case BPF_MAP_TYPE_XSKMAP: - return __xsk_map_redirect(fwd, xdp); + case BPF_MAP_TYPE_DEVMAP_HASH: { + struct bpf_dtab_netdev *dst = fwd; + + err = dev_map_enqueue(dst, xdp, dev_rx); + if (unlikely(err)) + return err; + break; + } + case BPF_MAP_TYPE_CPUMAP: { + struct bpf_cpu_map_entry *rcpu = fwd; + + err = cpu_map_enqueue(rcpu, xdp, dev_rx); + if (unlikely(err)) + return err; + break; + } + case BPF_MAP_TYPE_XSKMAP: { + struct xdp_sock *xs = fwd; + + err = __xsk_map_redirect(map, xdp, xs); + return err; + } default: return -EBADRQC; } return 0; } -void xdp_do_flush(void) +void xdp_do_flush_map(void) { - __dev_flush(); - __cpu_map_flush(); - __xsk_map_flush(); + struct bpf_redirect_info *ri = this_cpu_ptr(&bpf_redirect_info); + struct bpf_map *map = ri->map_to_flush; + + ri->map_to_flush = NULL; + if (map) { + switch (map->map_type) { + case BPF_MAP_TYPE_DEVMAP: + case BPF_MAP_TYPE_DEVMAP_HASH: + __dev_map_flush(map); + break; + case BPF_MAP_TYPE_CPUMAP: + __cpu_map_flush(map); + break; + case BPF_MAP_TYPE_XSKMAP: + __xsk_map_flush(map); + break; + default: + break; + } + } } -EXPORT_SYMBOL_GPL(xdp_do_flush); +EXPORT_SYMBOL_GPL(xdp_do_flush_map); static inline void *__xdp_map_lookup_elem(struct bpf_map *map, u32 index) { @@ -4032,11 +3670,10 @@ void bpf_clear_redirect_map(struct bpf_map *map) } } -int xdp_do_redirect(struct net_device *dev, struct xdp_buff *xdp, - struct bpf_prog *xdp_prog) +static int xdp_do_redirect_map(struct net_device *dev, struct xdp_buff *xdp, + struct bpf_prog *xdp_prog, struct bpf_map *map, + struct bpf_redirect_info *ri) { - struct bpf_redirect_info *ri = this_cpu_ptr(&bpf_redirect_info); - struct bpf_map *map = READ_ONCE(ri->map); u32 index = ri->tgt_index; void *fwd = ri->tgt_value; int err; @@ -4045,27 +3682,32 @@ int xdp_do_redirect(struct net_device *dev, struct xdp_buff *xdp, ri->tgt_value = NULL; WRITE_ONCE(ri->map, NULL); - if (unlikely(!map)) { - fwd = dev_get_by_index_rcu(dev_net(dev), index); - if (unlikely(!fwd)) { - err = -EINVAL; - goto err; - } - - err = dev_xdp_enqueue(fwd, xdp, dev); - } else { - err = __bpf_tx_xdp_map(dev, fwd, map, xdp); - } + if (ri->map_to_flush && unlikely(ri->map_to_flush != map)) + xdp_do_flush_map(); + err = __bpf_tx_xdp_map(dev, fwd, map, xdp, index); if (unlikely(err)) goto err; + ri->map_to_flush = map; _trace_xdp_redirect_map(dev, xdp_prog, fwd, map, index); return 0; err: _trace_xdp_redirect_map_err(dev, xdp_prog, fwd, map, index, err); return err; } + +int xdp_do_redirect(struct net_device *dev, struct xdp_buff *xdp, + struct bpf_prog *xdp_prog) +{ + struct bpf_redirect_info *ri = this_cpu_ptr(&bpf_redirect_info); + struct bpf_map *map = READ_ONCE(ri->map); + + if (likely(map)) + return xdp_do_redirect_map(dev, xdp, xdp_prog, map, ri); + + return xdp_do_redirect_slow(dev, xdp, xdp_prog, ri); +} EXPORT_SYMBOL_GPL(xdp_do_redirect); static int xdp_do_generic_redirect_map(struct net_device *dev, @@ -4141,6 +3783,7 @@ err: _trace_xdp_redirect_err(dev, xdp_prog, index, err); return err; } +EXPORT_SYMBOL_GPL(xdp_do_generic_redirect); BPF_CALL_2(bpf_xdp_redirect, u32, ifindex, u64, flags) { @@ -4221,7 +3864,7 @@ BPF_CALL_5(bpf_skb_event_output, struct sk_buff *, skb, struct bpf_map *, map, if (unlikely(flags & ~(BPF_F_CTXLEN_MASK | BPF_F_INDEX_MASK))) return -EINVAL; - if (unlikely(!skb || skb_size > skb->len)) + if (unlikely(skb_size > skb->len)) return -EFAULT; return bpf_event_output(map, flags, meta, meta_size, skb, skb_size, @@ -4239,20 +3882,6 @@ static const struct bpf_func_proto bpf_skb_event_output_proto = { .arg5_type = ARG_CONST_SIZE_OR_ZERO, }; -BTF_ID_LIST_SINGLE(bpf_skb_output_btf_ids, struct, sk_buff) - -const struct bpf_func_proto bpf_skb_output_proto = { - .func = bpf_skb_event_output, - .gpl_only = true, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_BTF_ID, - .arg1_btf_id = &bpf_skb_output_btf_ids[0], - .arg2_type = ARG_CONST_MAP_PTR, - .arg3_type = ARG_ANYTHING, - .arg4_type = ARG_PTR_TO_MEM, - .arg5_type = ARG_CONST_SIZE_OR_ZERO, -}; - static unsigned short bpf_tunnel_key_af(u64 flags) { return flags & BPF_F_TUNINFO_IPV6 ? AF_INET6 : AF_INET; @@ -4517,21 +4146,16 @@ static const struct bpf_func_proto bpf_skb_under_cgroup_proto = { }; #ifdef CONFIG_SOCK_CGROUP_DATA -static inline u64 __bpf_sk_cgroup_id(struct sock *sk) +BPF_CALL_1(bpf_skb_cgroup_id, const struct sk_buff *, skb) { + struct sock *sk = skb_to_full_sk(skb); struct cgroup *cgrp; - sk = sk_to_full_sk(sk); if (!sk || !sk_fullsock(sk)) return 0; cgrp = sock_cgroup_ptr(&sk->sk_cgrp_data); - return cgroup_id(cgrp); -} - -BPF_CALL_1(bpf_skb_cgroup_id, const struct sk_buff *, skb) -{ - return __bpf_sk_cgroup_id(skb->sk); + return cgrp->kn->id.id; } static const struct bpf_func_proto bpf_skb_cgroup_id_proto = { @@ -4541,13 +4165,13 @@ static const struct bpf_func_proto bpf_skb_cgroup_id_proto = { .arg1_type = ARG_PTR_TO_CTX, }; -static inline u64 __bpf_sk_ancestor_cgroup_id(struct sock *sk, - int ancestor_level) +BPF_CALL_2(bpf_skb_ancestor_cgroup_id, const struct sk_buff *, skb, int, + ancestor_level) { + struct sock *sk = skb_to_full_sk(skb); struct cgroup *ancestor; struct cgroup *cgrp; - sk = sk_to_full_sk(sk); if (!sk || !sk_fullsock(sk)) return 0; @@ -4556,13 +4180,7 @@ static inline u64 __bpf_sk_ancestor_cgroup_id(struct sock *sk, if (!ancestor) return 0; - return cgroup_id(ancestor); -} - -BPF_CALL_2(bpf_skb_ancestor_cgroup_id, const struct sk_buff *, skb, int, - ancestor_level) -{ - return __bpf_sk_ancestor_cgroup_id(skb->sk, ancestor_level); + return ancestor->kn->id.id; } static const struct bpf_func_proto bpf_skb_ancestor_cgroup_id_proto = { @@ -4572,31 +4190,6 @@ static const struct bpf_func_proto bpf_skb_ancestor_cgroup_id_proto = { .arg1_type = ARG_PTR_TO_CTX, .arg2_type = ARG_ANYTHING, }; - -BPF_CALL_1(bpf_sk_cgroup_id, struct sock *, sk) -{ - return __bpf_sk_cgroup_id(sk); -} - -static const struct bpf_func_proto bpf_sk_cgroup_id_proto = { - .func = bpf_sk_cgroup_id, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_BTF_ID_SOCK_COMMON, -}; - -BPF_CALL_2(bpf_sk_ancestor_cgroup_id, struct sock *, sk, int, ancestor_level) -{ - return __bpf_sk_ancestor_cgroup_id(sk, ancestor_level); -} - -static const struct bpf_func_proto bpf_sk_ancestor_cgroup_id_proto = { - .func = bpf_sk_ancestor_cgroup_id, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_BTF_ID_SOCK_COMMON, - .arg2_type = ARG_ANYTHING, -}; #endif static unsigned long bpf_xdp_copy(void *dst_buff, const void *src_buff, @@ -4613,8 +4206,7 @@ BPF_CALL_5(bpf_xdp_event_output, struct xdp_buff *, xdp, struct bpf_map *, map, if (unlikely(flags & ~(BPF_F_CTXLEN_MASK | BPF_F_INDEX_MASK))) return -EINVAL; - if (unlikely(!xdp || - xdp_size > (unsigned long)(xdp->data_end - xdp->data))) + if (unlikely(xdp_size > (unsigned long)(xdp->data_end - xdp->data))) return -EFAULT; return bpf_event_output(map, flags, meta, meta_size, xdp->data, @@ -4632,23 +4224,9 @@ static const struct bpf_func_proto bpf_xdp_event_output_proto = { .arg5_type = ARG_CONST_SIZE_OR_ZERO, }; -BTF_ID_LIST_SINGLE(bpf_xdp_output_btf_ids, struct, xdp_buff) - -const struct bpf_func_proto bpf_xdp_output_proto = { - .func = bpf_xdp_event_output, - .gpl_only = true, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_BTF_ID, - .arg1_btf_id = &bpf_xdp_output_btf_ids[0], - .arg2_type = ARG_CONST_MAP_PTR, - .arg3_type = ARG_ANYTHING, - .arg4_type = ARG_PTR_TO_MEM, - .arg5_type = ARG_CONST_SIZE_OR_ZERO, -}; - BPF_CALL_1(bpf_get_socket_cookie, struct sk_buff *, skb) { - return skb->sk ? __sock_gen_cookie(skb->sk) : 0; + return skb->sk ? sock_gen_cookie(skb->sk) : 0; } static const struct bpf_func_proto bpf_get_socket_cookie_proto = { @@ -4660,7 +4238,7 @@ static const struct bpf_func_proto bpf_get_socket_cookie_proto = { BPF_CALL_1(bpf_get_socket_cookie_sock_addr, struct bpf_sock_addr_kern *, ctx) { - return __sock_gen_cookie(ctx->sk); + return sock_gen_cookie(ctx->sk); } static const struct bpf_func_proto bpf_get_socket_cookie_sock_addr_proto = { @@ -4670,21 +4248,9 @@ static const struct bpf_func_proto bpf_get_socket_cookie_sock_addr_proto = { .arg1_type = ARG_PTR_TO_CTX, }; -BPF_CALL_1(bpf_get_socket_cookie_sock, struct sock *, ctx) -{ - return __sock_gen_cookie(ctx); -} - -static const struct bpf_func_proto bpf_get_socket_cookie_sock_proto = { - .func = bpf_get_socket_cookie_sock, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX, -}; - BPF_CALL_1(bpf_get_socket_cookie_sock_ops, struct bpf_sock_ops_kern *, ctx) { - return __sock_gen_cookie(ctx->sk); + return sock_gen_cookie(ctx->sk); } static const struct bpf_func_proto bpf_get_socket_cookie_sock_ops_proto = { @@ -4694,37 +4260,6 @@ static const struct bpf_func_proto bpf_get_socket_cookie_sock_ops_proto = { .arg1_type = ARG_PTR_TO_CTX, }; -static u64 __bpf_get_netns_cookie(struct sock *sk) -{ - const struct net *net = sk ? sock_net(sk) : &init_net; - - return atomic64_read(&net->net_cookie); -} - -BPF_CALL_1(bpf_get_netns_cookie_sock, struct sock *, ctx) -{ - return __bpf_get_netns_cookie(ctx); -} - -static const struct bpf_func_proto bpf_get_netns_cookie_sock_proto = { - .func = bpf_get_netns_cookie_sock, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX_OR_NULL, -}; - -BPF_CALL_1(bpf_get_netns_cookie_sock_addr, struct bpf_sock_addr_kern *, ctx) -{ - return __bpf_get_netns_cookie(ctx ? ctx->sk : NULL); -} - -static const struct bpf_func_proto bpf_get_netns_cookie_sock_addr_proto = { - .func = bpf_get_netns_cookie_sock_addr, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX_OR_NULL, -}; - BPF_CALL_1(bpf_get_socket_uid, struct sk_buff *, skb) { struct sock *sk = sk_to_full_sk(skb->sk); @@ -4743,25 +4278,40 @@ static const struct bpf_func_proto bpf_get_socket_uid_proto = { .arg1_type = ARG_PTR_TO_CTX, }; -static int _bpf_setsockopt(struct sock *sk, int level, int optname, - char *optval, int optlen) +BPF_CALL_5(bpf_sockopt_event_output, struct bpf_sock_ops_kern *, bpf_sock, + struct bpf_map *, map, u64, flags, void *, data, u64, size) { - char devname[IFNAMSIZ]; - int val, valbool; - struct net *net; - int ifindex; + if (unlikely(flags & ~(BPF_F_INDEX_MASK))) + return -EINVAL; + + return bpf_event_output(map, flags, data, size, NULL, 0, NULL); +} + +static const struct bpf_func_proto bpf_sockopt_event_output_proto = { + .func = bpf_sockopt_event_output, + .gpl_only = true, + .ret_type = RET_INTEGER, + .arg1_type = ARG_PTR_TO_CTX, + .arg2_type = ARG_CONST_MAP_PTR, + .arg3_type = ARG_ANYTHING, + .arg4_type = ARG_PTR_TO_MEM, + .arg5_type = ARG_CONST_SIZE_OR_ZERO, +}; + +BPF_CALL_5(bpf_setsockopt, struct bpf_sock_ops_kern *, bpf_sock, + int, level, int, optname, char *, optval, int, optlen) +{ + struct sock *sk = bpf_sock->sk; int ret = 0; + int val; if (!sk_fullsock(sk)) return -EINVAL; - sock_owned_by_me(sk); - if (level == SOL_SOCKET) { - if (optlen != sizeof(int) && optname != SO_BINDTODEVICE) + if (optlen != sizeof(int)) return -EINVAL; val = *((int *)optval); - valbool = val ? 1 : 0; /* Only some socketops are supported */ switch (optname) { @@ -4803,31 +4353,6 @@ static int _bpf_setsockopt(struct sock *sk, int level, int optname, sk_dst_reset(sk); } break; - case SO_BINDTODEVICE: - optlen = min_t(long, optlen, IFNAMSIZ - 1); - strncpy(devname, optval, optlen); - devname[optlen] = 0; - - ifindex = 0; - if (devname[0] != '\0') { - struct net_device *dev; - - ret = -ENODEV; - - net = sock_net(sk); - dev = dev_get_by_name(net, devname); - if (!dev) - break; - ifindex = dev->ifindex; - dev_put(dev); - } - ret = sock_bindtoindex(sk, ifindex, false); - break; - case SO_KEEPALIVE: - if (sk->sk_prot->keepalive) - sk->sk_prot->keepalive(sk, valbool); - sock_valbool_flag(sk, SOCK_KEEPOPEN, valbool); - break; default: ret = -EINVAL; } @@ -4880,15 +4405,15 @@ static int _bpf_setsockopt(struct sock *sk, int level, int optname, sk->sk_prot->setsockopt == tcp_setsockopt) { if (optname == TCP_CONGESTION) { char name[TCP_CA_NAME_MAX]; + bool reinit = bpf_sock->op > BPF_SOCK_OPS_NEEDS_ECN; strncpy(name, optval, min_t(long, optlen, TCP_CA_NAME_MAX-1)); name[TCP_CA_NAME_MAX-1] = 0; - ret = tcp_set_congestion_control(sk, name, false, true); + ret = tcp_set_congestion_control(sk, name, false, + reinit, true); } else { - struct inet_connection_sock *icsk = inet_csk(sk); struct tcp_sock *tp = tcp_sk(sk); - unsigned long timeout; if (optlen != sizeof(int)) return -EINVAL; @@ -4910,57 +4435,12 @@ static int _bpf_setsockopt(struct sock *sk, int level, int optname, tp->snd_ssthresh = val; } break; - case TCP_BPF_DELACK_MAX: - timeout = usecs_to_jiffies(val); - if (timeout > TCP_DELACK_MAX || - timeout < TCP_TIMEOUT_MIN) - return -EINVAL; - inet_csk(sk)->icsk_delack_max = timeout; - break; - case TCP_BPF_RTO_MIN: - timeout = usecs_to_jiffies(val); - if (timeout > TCP_RTO_MIN || - timeout < TCP_TIMEOUT_MIN) - return -EINVAL; - inet_csk(sk)->icsk_rto_min = timeout; - break; case TCP_SAVE_SYN: if (val < 0 || val > 1) ret = -EINVAL; else tp->save_syn = val; break; - case TCP_KEEPIDLE: - ret = tcp_sock_set_keepidle_locked(sk, val); - break; - case TCP_KEEPINTVL: - if (val < 1 || val > MAX_TCP_KEEPINTVL) - ret = -EINVAL; - else - tp->keepalive_intvl = val * HZ; - break; - case TCP_KEEPCNT: - if (val < 1 || val > MAX_TCP_KEEPCNT) - ret = -EINVAL; - else - tp->keepalive_probes = val; - break; - case TCP_SYNCNT: - if (val < 1 || val > MAX_TCP_SYNCNT) - ret = -EINVAL; - else - icsk->icsk_syn_retries = val; - break; - case TCP_USER_TIMEOUT: - if (val < 0) - ret = -EINVAL; - else - icsk->icsk_user_timeout = val; - break; - case TCP_NOTSENT_LOWAT: - tp->notsent_lowat = val; - sk->sk_write_space(sk); - break; default: ret = -EINVAL; } @@ -4972,14 +4452,24 @@ static int _bpf_setsockopt(struct sock *sk, int level, int optname, return ret; } -static int _bpf_getsockopt(struct sock *sk, int level, int optname, - char *optval, int optlen) +static const struct bpf_func_proto bpf_setsockopt_proto = { + .func = bpf_setsockopt, + .gpl_only = false, + .ret_type = RET_INTEGER, + .arg1_type = ARG_PTR_TO_CTX, + .arg2_type = ARG_ANYTHING, + .arg3_type = ARG_ANYTHING, + .arg4_type = ARG_PTR_TO_MEM, + .arg5_type = ARG_CONST_SIZE, +}; + +BPF_CALL_5(bpf_getsockopt, struct bpf_sock_ops_kern *, bpf_sock, + int, level, int, optname, char *, optval, int, optlen) { + struct sock *sk = bpf_sock->sk; + if (!sk_fullsock(sk)) goto err_clear; - - sock_owned_by_me(sk); - #ifdef CONFIG_INET if (level == SOL_TCP && sk->sk_prot->getsockopt == tcp_getsockopt) { struct inet_connection_sock *icsk; @@ -4998,9 +4488,9 @@ static int _bpf_getsockopt(struct sock *sk, int level, int optname, tp = tcp_sk(sk); if (optlen <= 0 || !tp->saved_syn || - optlen > tcp_saved_syn_len(tp->saved_syn)) + optlen > tp->saved_syn[0]) goto err_clear; - memcpy(optval, tp->saved_syn->data, optlen); + memcpy(optval, tp->saved_syn + 1, optlen); break; default: goto err_clear; @@ -5045,155 +4535,8 @@ err_clear: return -EINVAL; } -BPF_CALL_5(bpf_sock_addr_setsockopt, struct bpf_sock_addr_kern *, ctx, - int, level, int, optname, char *, optval, int, optlen) -{ - return _bpf_setsockopt(ctx->sk, level, optname, optval, optlen); -} - -static const struct bpf_func_proto bpf_sock_addr_setsockopt_proto = { - .func = bpf_sock_addr_setsockopt, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX, - .arg2_type = ARG_ANYTHING, - .arg3_type = ARG_ANYTHING, - .arg4_type = ARG_PTR_TO_MEM, - .arg5_type = ARG_CONST_SIZE, -}; - -BPF_CALL_5(bpf_sock_addr_getsockopt, struct bpf_sock_addr_kern *, ctx, - int, level, int, optname, char *, optval, int, optlen) -{ - return _bpf_getsockopt(ctx->sk, level, optname, optval, optlen); -} - -static const struct bpf_func_proto bpf_sock_addr_getsockopt_proto = { - .func = bpf_sock_addr_getsockopt, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX, - .arg2_type = ARG_ANYTHING, - .arg3_type = ARG_ANYTHING, - .arg4_type = ARG_PTR_TO_UNINIT_MEM, - .arg5_type = ARG_CONST_SIZE, -}; - -BPF_CALL_5(bpf_sock_ops_setsockopt, struct bpf_sock_ops_kern *, bpf_sock, - int, level, int, optname, char *, optval, int, optlen) -{ - return _bpf_setsockopt(bpf_sock->sk, level, optname, optval, optlen); -} - -static const struct bpf_func_proto bpf_sock_ops_setsockopt_proto = { - .func = bpf_sock_ops_setsockopt, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX, - .arg2_type = ARG_ANYTHING, - .arg3_type = ARG_ANYTHING, - .arg4_type = ARG_PTR_TO_MEM, - .arg5_type = ARG_CONST_SIZE, -}; - -static int bpf_sock_ops_get_syn(struct bpf_sock_ops_kern *bpf_sock, - int optname, const u8 **start) -{ - struct sk_buff *syn_skb = bpf_sock->syn_skb; - const u8 *hdr_start; - int ret; - - if (syn_skb) { - /* sk is a request_sock here */ - - if (optname == TCP_BPF_SYN) { - hdr_start = syn_skb->data; - ret = tcp_hdrlen(syn_skb); - } else if (optname == TCP_BPF_SYN_IP) { - hdr_start = skb_network_header(syn_skb); - ret = skb_network_header_len(syn_skb) + - tcp_hdrlen(syn_skb); - } else { - /* optname == TCP_BPF_SYN_MAC */ - hdr_start = skb_mac_header(syn_skb); - ret = skb_mac_header_len(syn_skb) + - skb_network_header_len(syn_skb) + - tcp_hdrlen(syn_skb); - } - } else { - struct sock *sk = bpf_sock->sk; - struct saved_syn *saved_syn; - - if (sk->sk_state == TCP_NEW_SYN_RECV) - /* synack retransmit. bpf_sock->syn_skb will - * not be available. It has to resort to - * saved_syn (if it is saved). - */ - saved_syn = inet_reqsk(sk)->saved_syn; - else - saved_syn = tcp_sk(sk)->saved_syn; - - if (!saved_syn) - return -ENOENT; - - if (optname == TCP_BPF_SYN) { - hdr_start = saved_syn->data + - saved_syn->mac_hdrlen + - saved_syn->network_hdrlen; - ret = saved_syn->tcp_hdrlen; - } else if (optname == TCP_BPF_SYN_IP) { - hdr_start = saved_syn->data + - saved_syn->mac_hdrlen; - ret = saved_syn->network_hdrlen + - saved_syn->tcp_hdrlen; - } else { - /* optname == TCP_BPF_SYN_MAC */ - - /* TCP_SAVE_SYN may not have saved the mac hdr */ - if (!saved_syn->mac_hdrlen) - return -ENOENT; - - hdr_start = saved_syn->data; - ret = saved_syn->mac_hdrlen + - saved_syn->network_hdrlen + - saved_syn->tcp_hdrlen; - } - } - - *start = hdr_start; - return ret; -} - -BPF_CALL_5(bpf_sock_ops_getsockopt, struct bpf_sock_ops_kern *, bpf_sock, - int, level, int, optname, char *, optval, int, optlen) -{ - if (IS_ENABLED(CONFIG_INET) && level == SOL_TCP && - optname >= TCP_BPF_SYN && optname <= TCP_BPF_SYN_MAC) { - int ret, copy_len = 0; - const u8 *start; - - ret = bpf_sock_ops_get_syn(bpf_sock, optname, &start); - if (ret > 0) { - copy_len = ret; - if (optlen < copy_len) { - copy_len = optlen; - ret = -ENOSPC; - } - - memcpy(optval, start, copy_len); - } - - /* Zero out unused buffer at the end */ - memset(optval + copy_len, 0, optlen - copy_len); - - return ret; - } - - return _bpf_getsockopt(bpf_sock->sk, level, optname, optval, optlen); -} - -static const struct bpf_func_proto bpf_sock_ops_getsockopt_proto = { - .func = bpf_sock_ops_getsockopt, +static const struct bpf_func_proto bpf_getsockopt_proto = { + .func = bpf_getsockopt, .gpl_only = false, .ret_type = RET_INTEGER, .arg1_type = ARG_PTR_TO_CTX, @@ -5233,28 +4576,30 @@ BPF_CALL_3(bpf_bind, struct bpf_sock_addr_kern *, ctx, struct sockaddr *, addr, { #ifdef CONFIG_INET struct sock *sk = ctx->sk; - u32 flags = BIND_FROM_BPF; int err; + /* Binding to port can be expensive so it's prohibited in the helper. + * Only binding to IP is supported. + */ err = -EINVAL; if (addr_len < offsetofend(struct sockaddr, sa_family)) return err; if (addr->sa_family == AF_INET) { if (addr_len < sizeof(struct sockaddr_in)) return err; - if (((struct sockaddr_in *)addr)->sin_port == htons(0)) - flags |= BIND_FORCE_ADDRESS_NO_PORT; - return __inet_bind(sk, addr, addr_len, flags); + if (((struct sockaddr_in *)addr)->sin_port != htons(0)) + return err; + return __inet_bind(sk, addr, addr_len, true, false); #if IS_ENABLED(CONFIG_IPV6) } else if (addr->sa_family == AF_INET6) { if (addr_len < SIN6_LEN_RFC2133) return err; - if (((struct sockaddr_in6 *)addr)->sin6_port == htons(0)) - flags |= BIND_FORCE_ADDRESS_NO_PORT; + if (((struct sockaddr_in6 *)addr)->sin6_port != htons(0)) + return err; /* ipv6_bpf_stub cannot be NULL, since it's called from * bpf_cgroup_inet6_connect hook and ipv6 is already loaded */ - return ipv6_bpf_stub->inet6_bind(sk, addr, addr_len, flags); + return ipv6_bpf_stub->inet6_bind(sk, addr, addr_len, true, false); #endif /* CONFIG_IPV6 */ } #endif /* CONFIG_INET */ @@ -5654,7 +4999,7 @@ static int bpf_push_seg6_encap(struct sk_buff *skb, u32 type, void *hdr, u32 len int err; struct ipv6_sr_hdr *srh = (struct ipv6_sr_hdr *)hdr; - if (!seg6_validate_srh(srh, len, false)) + if (!seg6_validate_srh(srh, len)) return -EINVAL; switch (type) { @@ -5987,11 +5332,12 @@ static struct sock *sk_lookup(struct net *net, struct bpf_sock_tuple *tuple, static struct sock * __bpf_skc_lookup(struct sk_buff *skb, struct bpf_sock_tuple *tuple, u32 len, struct net *caller_net, u32 ifindex, u8 proto, u64 netns_id, - u64 flags, int sdif) + u64 flags) { struct sock *sk = NULL; u8 family = AF_UNSPEC; struct net *net; + int sdif; if (len == sizeof(tuple->ipv4)) family = AF_INET; @@ -6004,12 +5350,10 @@ __bpf_skc_lookup(struct sk_buff *skb, struct bpf_sock_tuple *tuple, u32 len, !((s32)netns_id < 0 || netns_id <= S32_MAX))) goto out; - if (sdif < 0) { - if (family == AF_INET) - sdif = inet_sdif(skb); - else - sdif = inet6_sdif(skb); - } + if (family == AF_INET) + sdif = inet_sdif(skb); + else + sdif = inet6_sdif(skb); if ((s32)netns_id < 0) { net = caller_net; @@ -6029,11 +5373,10 @@ out: static struct sock * __bpf_sk_lookup(struct sk_buff *skb, struct bpf_sock_tuple *tuple, u32 len, struct net *caller_net, u32 ifindex, u8 proto, u64 netns_id, - u64 flags, int sdif) + u64 flags) { struct sock *sk = __bpf_skc_lookup(skb, tuple, len, caller_net, - ifindex, proto, netns_id, flags, - sdif); + ifindex, proto, netns_id, flags); if (sk) { struct sock *sk2 = sk_to_full_sk(sk); @@ -6073,7 +5416,7 @@ bpf_skc_lookup(struct sk_buff *skb, struct bpf_sock_tuple *tuple, u32 len, } return __bpf_skc_lookup(skb, tuple, len, caller_net, ifindex, proto, - netns_id, flags, -1); + netns_id, flags); } static struct sock * @@ -6164,7 +5507,8 @@ static const struct bpf_func_proto bpf_sk_lookup_udp_proto = { BPF_CALL_1(bpf_sk_release, struct sock *, sk) { - if (sk && sk_is_refcounted(sk)) + /* Only full sockets have sk->sk_flags. */ + if (!sk_fullsock(sk) || !sock_flag(sk, SOCK_RCU_FREE)) sock_gen_put(sk); return 0; } @@ -6173,19 +5517,18 @@ static const struct bpf_func_proto bpf_sk_release_proto = { .func = bpf_sk_release, .gpl_only = false, .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_BTF_ID_SOCK_COMMON, + .arg1_type = ARG_PTR_TO_SOCK_COMMON, }; BPF_CALL_5(bpf_xdp_sk_lookup_udp, struct xdp_buff *, ctx, struct bpf_sock_tuple *, tuple, u32, len, u32, netns_id, u64, flags) { - struct net_device *dev = ctx->rxq->dev; - int ifindex = dev->ifindex, sdif = dev_sdif(dev); - struct net *caller_net = dev_net(dev); + struct net *caller_net = dev_net(ctx->rxq->dev); + int ifindex = ctx->rxq->dev->ifindex; return (unsigned long)__bpf_sk_lookup(NULL, tuple, len, caller_net, ifindex, IPPROTO_UDP, netns_id, - flags, sdif); + flags); } static const struct bpf_func_proto bpf_xdp_sk_lookup_udp_proto = { @@ -6203,13 +5546,12 @@ static const struct bpf_func_proto bpf_xdp_sk_lookup_udp_proto = { BPF_CALL_5(bpf_xdp_skc_lookup_tcp, struct xdp_buff *, ctx, struct bpf_sock_tuple *, tuple, u32, len, u32, netns_id, u64, flags) { - struct net_device *dev = ctx->rxq->dev; - int ifindex = dev->ifindex, sdif = dev_sdif(dev); - struct net *caller_net = dev_net(dev); + struct net *caller_net = dev_net(ctx->rxq->dev); + int ifindex = ctx->rxq->dev->ifindex; return (unsigned long)__bpf_skc_lookup(NULL, tuple, len, caller_net, ifindex, IPPROTO_TCP, netns_id, - flags, sdif); + flags); } static const struct bpf_func_proto bpf_xdp_skc_lookup_tcp_proto = { @@ -6227,13 +5569,12 @@ static const struct bpf_func_proto bpf_xdp_skc_lookup_tcp_proto = { BPF_CALL_5(bpf_xdp_sk_lookup_tcp, struct xdp_buff *, ctx, struct bpf_sock_tuple *, tuple, u32, len, u32, netns_id, u64, flags) { - struct net_device *dev = ctx->rxq->dev; - int ifindex = dev->ifindex, sdif = dev_sdif(dev); - struct net *caller_net = dev_net(dev); + struct net *caller_net = dev_net(ctx->rxq->dev); + int ifindex = ctx->rxq->dev->ifindex; return (unsigned long)__bpf_sk_lookup(NULL, tuple, len, caller_net, ifindex, IPPROTO_TCP, netns_id, - flags, sdif); + flags); } static const struct bpf_func_proto bpf_xdp_sk_lookup_tcp_proto = { @@ -6253,8 +5594,7 @@ BPF_CALL_5(bpf_sock_addr_skc_lookup_tcp, struct bpf_sock_addr_kern *, ctx, { return (unsigned long)__bpf_skc_lookup(NULL, tuple, len, sock_net(ctx->sk), 0, - IPPROTO_TCP, netns_id, flags, - -1); + IPPROTO_TCP, netns_id, flags); } static const struct bpf_func_proto bpf_sock_addr_skc_lookup_tcp_proto = { @@ -6273,7 +5613,7 @@ BPF_CALL_5(bpf_sock_addr_sk_lookup_tcp, struct bpf_sock_addr_kern *, ctx, { return (unsigned long)__bpf_sk_lookup(NULL, tuple, len, sock_net(ctx->sk), 0, IPPROTO_TCP, - netns_id, flags, -1); + netns_id, flags); } static const struct bpf_func_proto bpf_sock_addr_sk_lookup_tcp_proto = { @@ -6292,7 +5632,7 @@ BPF_CALL_5(bpf_sock_addr_sk_lookup_udp, struct bpf_sock_addr_kern *, ctx, { return (unsigned long)__bpf_sk_lookup(NULL, tuple, len, sock_net(ctx->sk), 0, IPPROTO_UDP, - netns_id, flags, -1); + netns_id, flags); } static const struct bpf_func_proto bpf_sock_addr_sk_lookup_udp_proto = { @@ -6559,7 +5899,7 @@ BPF_CALL_5(bpf_tcp_check_syncookie, struct sock *, sk, void *, iph, u32, iph_len u32 cookie; int ret; - if (unlikely(!sk || th_len < sizeof(*th))) + if (unlikely(th_len < sizeof(*th))) return -EINVAL; /* sk_listener() allows TCP_NEW_SYN_RECV, which makes no sense here. */ @@ -6621,7 +5961,7 @@ static const struct bpf_func_proto bpf_tcp_check_syncookie_proto = { .gpl_only = true, .pkt_access = true, .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_BTF_ID_SOCK_COMMON, + .arg1_type = ARG_PTR_TO_SOCK_COMMON, .arg2_type = ARG_PTR_TO_MEM, .arg3_type = ARG_CONST_SIZE, .arg4_type = ARG_PTR_TO_MEM, @@ -6635,7 +5975,7 @@ BPF_CALL_5(bpf_tcp_gen_syncookie, struct sock *, sk, void *, iph, u32, iph_len, u32 cookie; u16 mss; - if (unlikely(!sk || th_len < sizeof(*th) || th_len != th->doff * 4)) + if (unlikely(th_len < sizeof(*th) || th_len != th->doff * 4)) return -EINVAL; if (sk->sk_protocol != IPPROTO_TCP || sk->sk_state != TCP_LISTEN) @@ -6690,271 +6030,13 @@ static const struct bpf_func_proto bpf_tcp_gen_syncookie_proto = { .gpl_only = true, /* __cookie_v*_init_sequence() is GPL */ .pkt_access = true, .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_BTF_ID_SOCK_COMMON, + .arg1_type = ARG_PTR_TO_SOCK_COMMON, .arg2_type = ARG_PTR_TO_MEM, .arg3_type = ARG_CONST_SIZE, .arg4_type = ARG_PTR_TO_MEM, .arg5_type = ARG_CONST_SIZE, }; -BPF_CALL_3(bpf_sk_assign, struct sk_buff *, skb, struct sock *, sk, u64, flags) -{ - if (!sk || flags != 0) - return -EINVAL; - if (!skb_at_tc_ingress(skb)) - return -EOPNOTSUPP; - if (unlikely(dev_net(skb->dev) != sock_net(sk))) - return -ENETUNREACH; - if (unlikely(sk_fullsock(sk) && sk->sk_reuseport)) - return -ESOCKTNOSUPPORT; - if (sk_unhashed(sk)) - return -EOPNOTSUPP; - if (sk_is_refcounted(sk) && - unlikely(!refcount_inc_not_zero(&sk->sk_refcnt))) - return -ENOENT; - - skb_orphan(skb); - skb->sk = sk; - skb->destructor = sock_pfree; - - return 0; -} - -static const struct bpf_func_proto bpf_sk_assign_proto = { - .func = bpf_sk_assign, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX, - .arg2_type = ARG_PTR_TO_BTF_ID_SOCK_COMMON, - .arg3_type = ARG_ANYTHING, -}; - -static const u8 *bpf_search_tcp_opt(const u8 *op, const u8 *opend, - u8 search_kind, const u8 *magic, - u8 magic_len, bool *eol) -{ - u8 kind, kind_len; - - *eol = false; - - while (op < opend) { - kind = op[0]; - - if (kind == TCPOPT_EOL) { - *eol = true; - return ERR_PTR(-ENOMSG); - } else if (kind == TCPOPT_NOP) { - op++; - continue; - } - - if (opend - op < 2 || opend - op < op[1] || op[1] < 2) - /* Something is wrong in the received header. - * Follow the TCP stack's tcp_parse_options() - * and just bail here. - */ - return ERR_PTR(-EFAULT); - - kind_len = op[1]; - if (search_kind == kind) { - if (!magic_len) - return op; - - if (magic_len > kind_len - 2) - return ERR_PTR(-ENOMSG); - - if (!memcmp(&op[2], magic, magic_len)) - return op; - } - - op += kind_len; - } - - return ERR_PTR(-ENOMSG); -} - -BPF_CALL_4(bpf_sock_ops_load_hdr_opt, struct bpf_sock_ops_kern *, bpf_sock, - void *, search_res, u32, len, u64, flags) -{ - bool eol, load_syn = flags & BPF_LOAD_HDR_OPT_TCP_SYN; - const u8 *op, *opend, *magic, *search = search_res; - u8 search_kind, search_len, copy_len, magic_len; - int ret; - - /* 2 byte is the minimal option len except TCPOPT_NOP and - * TCPOPT_EOL which are useless for the bpf prog to learn - * and this helper disallow loading them also. - */ - if (len < 2 || flags & ~BPF_LOAD_HDR_OPT_TCP_SYN) - return -EINVAL; - - search_kind = search[0]; - search_len = search[1]; - - if (search_len > len || search_kind == TCPOPT_NOP || - search_kind == TCPOPT_EOL) - return -EINVAL; - - if (search_kind == TCPOPT_EXP || search_kind == 253) { - /* 16 or 32 bit magic. +2 for kind and kind length */ - if (search_len != 4 && search_len != 6) - return -EINVAL; - magic = &search[2]; - magic_len = search_len - 2; - } else { - if (search_len) - return -EINVAL; - magic = NULL; - magic_len = 0; - } - - if (load_syn) { - ret = bpf_sock_ops_get_syn(bpf_sock, TCP_BPF_SYN, &op); - if (ret < 0) - return ret; - - opend = op + ret; - op += sizeof(struct tcphdr); - } else { - if (!bpf_sock->skb || - bpf_sock->op == BPF_SOCK_OPS_HDR_OPT_LEN_CB) - /* This bpf_sock->op cannot call this helper */ - return -EPERM; - - opend = bpf_sock->skb_data_end; - op = bpf_sock->skb->data + sizeof(struct tcphdr); - } - - op = bpf_search_tcp_opt(op, opend, search_kind, magic, magic_len, - &eol); - if (IS_ERR(op)) - return PTR_ERR(op); - - copy_len = op[1]; - ret = copy_len; - if (copy_len > len) { - ret = -ENOSPC; - copy_len = len; - } - - memcpy(search_res, op, copy_len); - return ret; -} - -static const struct bpf_func_proto bpf_sock_ops_load_hdr_opt_proto = { - .func = bpf_sock_ops_load_hdr_opt, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX, - .arg2_type = ARG_PTR_TO_MEM, - .arg3_type = ARG_CONST_SIZE, - .arg4_type = ARG_ANYTHING, -}; - -BPF_CALL_4(bpf_sock_ops_store_hdr_opt, struct bpf_sock_ops_kern *, bpf_sock, - const void *, from, u32, len, u64, flags) -{ - u8 new_kind, new_kind_len, magic_len = 0, *opend; - const u8 *op, *new_op, *magic = NULL; - struct sk_buff *skb; - bool eol; - - if (bpf_sock->op != BPF_SOCK_OPS_WRITE_HDR_OPT_CB) - return -EPERM; - - if (len < 2 || flags) - return -EINVAL; - - new_op = from; - new_kind = new_op[0]; - new_kind_len = new_op[1]; - - if (new_kind_len > len || new_kind == TCPOPT_NOP || - new_kind == TCPOPT_EOL) - return -EINVAL; - - if (new_kind_len > bpf_sock->remaining_opt_len) - return -ENOSPC; - - /* 253 is another experimental kind */ - if (new_kind == TCPOPT_EXP || new_kind == 253) { - if (new_kind_len < 4) - return -EINVAL; - /* Match for the 2 byte magic also. - * RFC 6994: the magic could be 2 or 4 bytes. - * Hence, matching by 2 byte only is on the - * conservative side but it is the right - * thing to do for the 'search-for-duplication' - * purpose. - */ - magic = &new_op[2]; - magic_len = 2; - } - - /* Check for duplication */ - skb = bpf_sock->skb; - op = skb->data + sizeof(struct tcphdr); - opend = bpf_sock->skb_data_end; - - op = bpf_search_tcp_opt(op, opend, new_kind, magic, magic_len, - &eol); - if (!IS_ERR(op)) - return -EEXIST; - - if (PTR_ERR(op) != -ENOMSG) - return PTR_ERR(op); - - if (eol) - /* The option has been ended. Treat it as no more - * header option can be written. - */ - return -ENOSPC; - - /* No duplication found. Store the header option. */ - memcpy(opend, from, new_kind_len); - - bpf_sock->remaining_opt_len -= new_kind_len; - bpf_sock->skb_data_end += new_kind_len; - - return 0; -} - -static const struct bpf_func_proto bpf_sock_ops_store_hdr_opt_proto = { - .func = bpf_sock_ops_store_hdr_opt, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX, - .arg2_type = ARG_PTR_TO_MEM, - .arg3_type = ARG_CONST_SIZE, - .arg4_type = ARG_ANYTHING, -}; - -BPF_CALL_3(bpf_sock_ops_reserve_hdr_opt, struct bpf_sock_ops_kern *, bpf_sock, - u32, len, u64, flags) -{ - if (bpf_sock->op != BPF_SOCK_OPS_HDR_OPT_LEN_CB) - return -EPERM; - - if (flags || len < 2) - return -EINVAL; - - if (len > bpf_sock->remaining_opt_len) - return -ENOSPC; - - bpf_sock->remaining_opt_len -= len; - - return 0; -} - -static const struct bpf_func_proto bpf_sock_ops_reserve_hdr_opt_proto = { - .func = bpf_sock_ops_reserve_hdr_opt, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX, - .arg2_type = ARG_ANYTHING, - .arg3_type = ARG_ANYTHING, -}; - #endif /* CONFIG_INET */ bool bpf_helper_changes_pkt_data(void *func) @@ -6968,7 +6050,6 @@ bool bpf_helper_changes_pkt_data(void *func) func == bpf_skb_change_tail || func == sk_skb_change_tail || func == bpf_skb_adjust_room || - func == sk_skb_adjust_room || func == bpf_skb_pull_data || func == sk_skb_pull_data || func == bpf_clone_redirect || @@ -6984,9 +6065,6 @@ bool bpf_helper_changes_pkt_data(void *func) func == bpf_lwt_seg6_store_bytes || func == bpf_lwt_seg6_adjust_srh || func == bpf_lwt_seg6_action || -#endif -#ifdef CONFIG_INET - func == bpf_sock_ops_store_hdr_opt || #endif func == bpf_lwt_in_push_encap || func == bpf_lwt_xmit_push_encap) @@ -6995,8 +6073,52 @@ bool bpf_helper_changes_pkt_data(void *func) return false; } -const struct bpf_func_proto bpf_event_output_data_proto __weak; -const struct bpf_func_proto bpf_sk_storage_get_cg_sock_proto __weak; +static const struct bpf_func_proto * +bpf_base_func_proto(enum bpf_func_id func_id) +{ + switch (func_id) { + case BPF_FUNC_map_lookup_elem: + return &bpf_map_lookup_elem_proto; + case BPF_FUNC_map_update_elem: + return &bpf_map_update_elem_proto; + case BPF_FUNC_map_delete_elem: + return &bpf_map_delete_elem_proto; + case BPF_FUNC_map_push_elem: + return &bpf_map_push_elem_proto; + case BPF_FUNC_map_pop_elem: + return &bpf_map_pop_elem_proto; + case BPF_FUNC_map_peek_elem: + return &bpf_map_peek_elem_proto; + case BPF_FUNC_get_prandom_u32: + return &bpf_get_prandom_u32_proto; + case BPF_FUNC_get_smp_processor_id: + return &bpf_get_raw_smp_processor_id_proto; + case BPF_FUNC_get_numa_node_id: + return &bpf_get_numa_node_id_proto; + case BPF_FUNC_tail_call: + return &bpf_tail_call_proto; + case BPF_FUNC_ktime_get_ns: + return &bpf_ktime_get_ns_proto; + case BPF_FUNC_ktime_get_boot_ns: + return &bpf_ktime_get_boot_ns_proto; + default: + break; + } + + if (!capable(CAP_SYS_ADMIN)) + return NULL; + + switch (func_id) { + case BPF_FUNC_spin_lock: + return &bpf_spin_lock_proto; + case BPF_FUNC_spin_unlock: + return &bpf_spin_unlock_proto; + case BPF_FUNC_trace_printk: + return bpf_get_trace_printk_proto(); + default: + return NULL; + } +} static const struct bpf_func_proto * sock_filter_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) @@ -7009,28 +6131,6 @@ sock_filter_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return &bpf_get_current_uid_gid_proto; case BPF_FUNC_get_local_storage: return &bpf_get_local_storage_proto; - case BPF_FUNC_get_socket_cookie: - return &bpf_get_socket_cookie_sock_proto; - case BPF_FUNC_get_netns_cookie: - return &bpf_get_netns_cookie_sock_proto; - case BPF_FUNC_perf_event_output: - return &bpf_event_output_data_proto; - case BPF_FUNC_get_current_pid_tgid: - return &bpf_get_current_pid_tgid_proto; - case BPF_FUNC_get_current_comm: - return &bpf_get_current_comm_proto; -#ifdef CONFIG_CGROUPS - case BPF_FUNC_get_current_cgroup_id: - return &bpf_get_current_cgroup_id_proto; - case BPF_FUNC_get_current_ancestor_cgroup_id: - return &bpf_get_current_ancestor_cgroup_id_proto; -#endif -#ifdef CONFIG_CGROUP_NET_CLASSID - case BPF_FUNC_get_cgroup_classid: - return &bpf_get_cgroup_classid_curr_proto; -#endif - case BPF_FUNC_sk_storage_get: - return &bpf_sk_storage_get_cg_sock_proto; default: return bpf_base_func_proto(func_id); } @@ -7055,26 +6155,8 @@ sock_addr_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) } case BPF_FUNC_get_socket_cookie: return &bpf_get_socket_cookie_sock_addr_proto; - case BPF_FUNC_get_netns_cookie: - return &bpf_get_netns_cookie_sock_addr_proto; case BPF_FUNC_get_local_storage: return &bpf_get_local_storage_proto; - case BPF_FUNC_perf_event_output: - return &bpf_event_output_data_proto; - case BPF_FUNC_get_current_pid_tgid: - return &bpf_get_current_pid_tgid_proto; - case BPF_FUNC_get_current_comm: - return &bpf_get_current_comm_proto; -#ifdef CONFIG_CGROUPS - case BPF_FUNC_get_current_cgroup_id: - return &bpf_get_current_cgroup_id_proto; - case BPF_FUNC_get_current_ancestor_cgroup_id: - return &bpf_get_current_ancestor_cgroup_id_proto; -#endif -#ifdef CONFIG_CGROUP_NET_CLASSID - case BPF_FUNC_get_cgroup_classid: - return &bpf_get_cgroup_classid_curr_proto; -#endif #ifdef CONFIG_INET case BPF_FUNC_sk_lookup_tcp: return &bpf_sock_addr_sk_lookup_tcp_proto; @@ -7089,24 +6171,8 @@ sock_addr_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return &bpf_sk_storage_get_proto; case BPF_FUNC_sk_storage_delete: return &bpf_sk_storage_delete_proto; - case BPF_FUNC_setsockopt: - switch (prog->expected_attach_type) { - case BPF_CGROUP_INET4_CONNECT: - case BPF_CGROUP_INET6_CONNECT: - return &bpf_sock_addr_setsockopt_proto; - default: - return NULL; - } - case BPF_FUNC_getsockopt: - switch (prog->expected_attach_type) { - case BPF_CGROUP_INET4_CONNECT: - case BPF_CGROUP_INET6_CONNECT: - return &bpf_sock_addr_getsockopt_proto; - default: - return NULL; - } default: - return bpf_sk_base_func_proto(func_id); + return bpf_base_func_proto(func_id); } } @@ -7125,7 +6191,7 @@ sk_filter_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) case BPF_FUNC_perf_event_output: return &bpf_skb_event_output_proto; default: - return bpf_sk_base_func_proto(func_id); + return bpf_base_func_proto(func_id); } } @@ -7149,22 +6215,8 @@ cg_skb_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) #ifdef CONFIG_SOCK_CGROUP_DATA case BPF_FUNC_skb_cgroup_id: return &bpf_skb_cgroup_id_proto; - case BPF_FUNC_skb_ancestor_cgroup_id: - return &bpf_skb_ancestor_cgroup_id_proto; - case BPF_FUNC_sk_cgroup_id: - return &bpf_sk_cgroup_id_proto; - case BPF_FUNC_sk_ancestor_cgroup_id: - return &bpf_sk_ancestor_cgroup_id_proto; #endif #ifdef CONFIG_INET - case BPF_FUNC_sk_lookup_tcp: - return &bpf_sk_lookup_tcp_proto; - case BPF_FUNC_sk_lookup_udp: - return &bpf_sk_lookup_udp_proto; - case BPF_FUNC_sk_release: - return &bpf_sk_release_proto; - case BPF_FUNC_skc_lookup_tcp: - return &bpf_skc_lookup_tcp_proto; case BPF_FUNC_tcp_sock: return &bpf_tcp_sock_proto; case BPF_FUNC_get_listener_sock: @@ -7193,8 +6245,6 @@ tc_cls_act_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return &bpf_csum_diff_proto; case BPF_FUNC_csum_update: return &bpf_csum_update_proto; - case BPF_FUNC_csum_level: - return &bpf_csum_level_proto; case BPF_FUNC_l3_csum_replace: return &bpf_l3_csum_replace_proto; case BPF_FUNC_l4_csum_replace: @@ -7227,10 +6277,6 @@ tc_cls_act_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return bpf_get_skb_set_tunnel_proto(func_id); case BPF_FUNC_redirect: return &bpf_redirect_proto; - case BPF_FUNC_redirect_neigh: - return &bpf_redirect_neigh_proto; - case BPF_FUNC_redirect_peer: - return &bpf_redirect_peer_proto; case BPF_FUNC_get_route_realm: return &bpf_get_route_realm_proto; case BPF_FUNC_get_hash_recalc: @@ -7261,10 +6307,6 @@ tc_cls_act_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) case BPF_FUNC_skb_get_xfrm_state: return &bpf_skb_get_xfrm_state_proto; #endif -#ifdef CONFIG_CGROUP_NET_CLASSID - case BPF_FUNC_skb_cgroup_classid: - return &bpf_skb_cgroup_classid_proto; -#endif #ifdef CONFIG_SOCK_CGROUP_DATA case BPF_FUNC_skb_cgroup_id: return &bpf_skb_cgroup_id_proto; @@ -7290,11 +6332,9 @@ tc_cls_act_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return &bpf_skb_ecn_set_ce_proto; case BPF_FUNC_tcp_gen_syncookie: return &bpf_tcp_gen_syncookie_proto; - case BPF_FUNC_sk_assign: - return &bpf_sk_assign_proto; #endif default: - return bpf_sk_base_func_proto(func_id); + return bpf_base_func_proto(func_id); } } @@ -7335,7 +6375,7 @@ xdp_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return &bpf_tcp_gen_syncookie_proto; #endif default: - return bpf_sk_base_func_proto(func_id); + return bpf_base_func_proto(func_id); } } @@ -7347,9 +6387,9 @@ sock_ops_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) { switch (func_id) { case BPF_FUNC_setsockopt: - return &bpf_sock_ops_setsockopt_proto; + return &bpf_setsockopt_proto; case BPF_FUNC_getsockopt: - return &bpf_sock_ops_getsockopt_proto; + return &bpf_getsockopt_proto; case BPF_FUNC_sock_ops_cb_flags_set: return &bpf_sock_ops_cb_flags_set_proto; case BPF_FUNC_sock_map_update: @@ -7361,23 +6401,17 @@ sock_ops_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) case BPF_FUNC_get_local_storage: return &bpf_get_local_storage_proto; case BPF_FUNC_perf_event_output: - return &bpf_event_output_data_proto; + return &bpf_sockopt_event_output_proto; case BPF_FUNC_sk_storage_get: return &bpf_sk_storage_get_proto; case BPF_FUNC_sk_storage_delete: return &bpf_sk_storage_delete_proto; #ifdef CONFIG_INET - case BPF_FUNC_load_hdr_opt: - return &bpf_sock_ops_load_hdr_opt_proto; - case BPF_FUNC_store_hdr_opt: - return &bpf_sock_ops_store_hdr_opt_proto; - case BPF_FUNC_reserve_hdr_opt: - return &bpf_sock_ops_reserve_hdr_opt_proto; case BPF_FUNC_tcp_sock: return &bpf_tcp_sock_proto; #endif /* CONFIG_INET */ default: - return bpf_sk_base_func_proto(func_id); + return bpf_base_func_proto(func_id); } } @@ -7402,28 +6436,8 @@ sk_msg_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return &bpf_msg_push_data_proto; case BPF_FUNC_msg_pop_data: return &bpf_msg_pop_data_proto; - case BPF_FUNC_perf_event_output: - return &bpf_event_output_data_proto; - case BPF_FUNC_get_current_uid_gid: - return &bpf_get_current_uid_gid_proto; - case BPF_FUNC_get_current_pid_tgid: - return &bpf_get_current_pid_tgid_proto; - case BPF_FUNC_sk_storage_get: - return &bpf_sk_storage_get_proto; - case BPF_FUNC_sk_storage_delete: - return &bpf_sk_storage_delete_proto; -#ifdef CONFIG_CGROUPS - case BPF_FUNC_get_current_cgroup_id: - return &bpf_get_current_cgroup_id_proto; - case BPF_FUNC_get_current_ancestor_cgroup_id: - return &bpf_get_current_ancestor_cgroup_id_proto; -#endif -#ifdef CONFIG_CGROUP_NET_CLASSID - case BPF_FUNC_get_cgroup_classid: - return &bpf_get_cgroup_classid_curr_proto; -#endif default: - return bpf_sk_base_func_proto(func_id); + return bpf_base_func_proto(func_id); } } @@ -7444,8 +6458,6 @@ sk_skb_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return &sk_skb_change_tail_proto; case BPF_FUNC_skb_change_head: return &sk_skb_change_head_proto; - case BPF_FUNC_skb_adjust_room: - return &sk_skb_adjust_room_proto; case BPF_FUNC_get_socket_cookie: return &bpf_get_socket_cookie_proto; case BPF_FUNC_get_socket_uid: @@ -7467,7 +6479,7 @@ sk_skb_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return &bpf_skc_lookup_tcp_proto; #endif default: - return bpf_sk_base_func_proto(func_id); + return bpf_base_func_proto(func_id); } } @@ -7478,7 +6490,7 @@ flow_dissector_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) case BPF_FUNC_skb_load_bytes: return &bpf_flow_dissector_load_bytes_proto; default: - return bpf_sk_base_func_proto(func_id); + return bpf_base_func_proto(func_id); } } @@ -7505,7 +6517,7 @@ lwt_out_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) case BPF_FUNC_skb_under_cgroup: return &bpf_skb_under_cgroup_proto; default: - return bpf_sk_base_func_proto(func_id); + return bpf_base_func_proto(func_id); } } @@ -7544,8 +6556,6 @@ lwt_xmit_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return &bpf_skb_store_bytes_proto; case BPF_FUNC_csum_update: return &bpf_csum_update_proto; - case BPF_FUNC_csum_level: - return &bpf_csum_level_proto; case BPF_FUNC_l3_csum_replace: return &bpf_l3_csum_replace_proto; case BPF_FUNC_l4_csum_replace: @@ -7670,7 +6680,7 @@ static bool cg_skb_is_valid_access(int off, int size, return false; case bpf_ctx_range(struct __sk_buff, data): case bpf_ctx_range(struct __sk_buff, data_end): - if (!bpf_capable()) + if (!capable(CAP_SYS_ADMIN)) return false; break; } @@ -7682,7 +6692,7 @@ static bool cg_skb_is_valid_access(int off, int size, case bpf_ctx_range_till(struct __sk_buff, cb[0], cb[4]): break; case bpf_ctx_range(struct __sk_buff, tstamp): - if (!bpf_capable()) + if (!capable(CAP_SYS_ADMIN)) return false; break; default: @@ -7750,7 +6760,6 @@ static bool __sock_filter_check_attach_type(int off, case offsetof(struct bpf_sock, priority): switch (attach_type) { case BPF_CGROUP_INET_SOCK_CREATE: - case BPF_CGROUP_INET_SOCK_RELEASE: goto full_access; default: return false; @@ -7813,7 +6822,6 @@ bool bpf_sock_is_valid_access(int off, int size, enum bpf_access_type type, case offsetof(struct bpf_sock, type): case offsetof(struct bpf_sock, protocol): case offsetof(struct bpf_sock, src_port): - case offsetof(struct bpf_sock, rx_queue_mapping): case bpf_ctx_range(struct bpf_sock, src_ip4): case bpf_ctx_range_till(struct bpf_sock, src_ip6[0], src_ip6[3]): case bpf_ctx_range(struct bpf_sock, dst_ip4): @@ -7987,13 +6995,6 @@ static bool xdp_is_valid_access(int off, int size, const struct bpf_prog *prog, struct bpf_insn_access_aux *info) { - if (prog->expected_attach_type != BPF_XDP_DEVMAP) { - switch (off) { - case offsetof(struct xdp_md, egress_ifindex): - return false; - } - } - if (type == BPF_WRITE) { if (bpf_prog_is_dev_bound(prog->aux)) { switch (off) { @@ -8049,8 +7050,6 @@ static bool sock_addr_is_valid_access(int off, int size, switch (prog->expected_attach_type) { case BPF_CGROUP_INET4_BIND: case BPF_CGROUP_INET4_CONNECT: - case BPF_CGROUP_INET4_GETPEERNAME: - case BPF_CGROUP_INET4_GETSOCKNAME: case BPF_CGROUP_UDP4_SENDMSG: case BPF_CGROUP_UDP4_RECVMSG: break; @@ -8062,8 +7061,6 @@ static bool sock_addr_is_valid_access(int off, int size, switch (prog->expected_attach_type) { case BPF_CGROUP_INET6_BIND: case BPF_CGROUP_INET6_CONNECT: - case BPF_CGROUP_INET6_GETPEERNAME: - case BPF_CGROUP_INET6_GETSOCKNAME: case BPF_CGROUP_UDP6_SENDMSG: case BPF_CGROUP_UDP6_RECVMSG: break; @@ -8096,7 +7093,6 @@ static bool sock_addr_is_valid_access(int off, int size, case bpf_ctx_range(struct bpf_sock_addr, msg_src_ip4): case bpf_ctx_range_till(struct bpf_sock_addr, msg_src_ip6[0], msg_src_ip6[3]): - case bpf_ctx_range(struct bpf_sock_addr, user_port): if (type == BPF_READ) { bpf_ctx_record_field_size(info, size_default); @@ -8127,6 +7123,10 @@ static bool sock_addr_is_valid_access(int off, int size, return false; } break; + case bpf_ctx_range(struct bpf_sock_addr, user_port): + if (size != size_default) + return false; + break; case offsetof(struct bpf_sock_addr, sk): if (type != BPF_READ) return false; @@ -8134,17 +7134,13 @@ static bool sock_addr_is_valid_access(int off, int size, return false; info->reg_type = PTR_TO_SOCKET; break; - case bpf_ctx_range(struct bpf_sock_addr, user_family): - case bpf_ctx_range(struct bpf_sock_addr, family): - case bpf_ctx_range(struct bpf_sock_addr, type): - case bpf_ctx_range(struct bpf_sock_addr, protocol): - if (type != BPF_READ) - return false; - if (size != size_default) - return false; - break; default: - return false; + if (type == BPF_READ) { + if (size != size_default) + return false; + } else { + return false; + } } return true; @@ -8186,20 +7182,6 @@ static bool sock_ops_is_valid_access(int off, int size, return false; info->reg_type = PTR_TO_SOCKET_OR_NULL; break; - case offsetof(struct bpf_sock_ops, skb_data): - if (size != sizeof(__u64)) - return false; - info->reg_type = PTR_TO_PACKET; - break; - case offsetof(struct bpf_sock_ops, skb_data_end): - if (size != sizeof(__u64)) - return false; - info->reg_type = PTR_TO_PACKET_END; - break; - case offsetof(struct bpf_sock_ops, skb_tcp_flags): - bpf_ctx_record_field_size(info, size_default); - return bpf_ctx_narrow_access_ok(off, size, - size_default); default: if (size != size_default) return false; @@ -8275,11 +7257,6 @@ static bool sk_msg_is_valid_access(int off, int size, if (size != sizeof(__u64)) return false; break; - case offsetof(struct sk_msg_md, sk): - if (size != sizeof(__u64)) - return false; - info->reg_type = PTR_TO_SOCKET; - break; case bpf_ctx_range(struct sk_msg_md, family): case bpf_ctx_range(struct sk_msg_md, remote_ip4): case bpf_ctx_range(struct sk_msg_md, local_ip4): @@ -8799,21 +7776,21 @@ u32 bpf_sock_convert_ctx_access(enum bpf_access_type type, break; case offsetof(struct bpf_sock, type): - *insn++ = BPF_LDX_MEM( - BPF_FIELD_SIZEOF(struct sock, sk_type), - si->dst_reg, si->src_reg, - bpf_target_off(struct sock, sk_type, - sizeof_field(struct sock, sk_type), - target_size)); + BUILD_BUG_ON(HWEIGHT32(SK_FL_TYPE_MASK) != BITS_PER_BYTE * 2); + *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg, si->src_reg, + offsetof(struct sock, __sk_flags_offset)); + *insn++ = BPF_ALU32_IMM(BPF_AND, si->dst_reg, SK_FL_TYPE_MASK); + *insn++ = BPF_ALU32_IMM(BPF_RSH, si->dst_reg, SK_FL_TYPE_SHIFT); + *target_size = 2; break; case offsetof(struct bpf_sock, protocol): - *insn++ = BPF_LDX_MEM( - BPF_FIELD_SIZEOF(struct sock, sk_protocol), - si->dst_reg, si->src_reg, - bpf_target_off(struct sock, sk_protocol, - sizeof_field(struct sock, sk_protocol), - target_size)); + BUILD_BUG_ON(HWEIGHT32(SK_FL_PROTO_MASK) != BITS_PER_BYTE); + *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg, si->src_reg, + offsetof(struct sock, __sk_flags_offset)); + *insn++ = BPF_ALU32_IMM(BPF_AND, si->dst_reg, SK_FL_PROTO_MASK); + *insn++ = BPF_ALU32_IMM(BPF_RSH, si->dst_reg, SK_FL_PROTO_SHIFT); + *target_size = 1; break; case offsetof(struct bpf_sock, src_ip4): @@ -8898,23 +7875,6 @@ u32 bpf_sock_convert_ctx_access(enum bpf_access_type type, skc_state), target_size)); break; - case offsetof(struct bpf_sock, rx_queue_mapping): -#ifdef CONFIG_XPS - *insn++ = BPF_LDX_MEM( - BPF_FIELD_SIZEOF(struct sock, sk_rx_queue_mapping), - si->dst_reg, si->src_reg, - bpf_target_off(struct sock, sk_rx_queue_mapping, - sizeof_field(struct sock, - sk_rx_queue_mapping), - target_size)); - *insn++ = BPF_JMP_IMM(BPF_JNE, si->dst_reg, NO_QUEUE_MAPPING, - 1); - *insn++ = BPF_MOV64_IMM(si->dst_reg, -1); -#else - *insn++ = BPF_MOV64_IMM(si->dst_reg, -1); - *target_size = 2; -#endif - break; } return insn - insn_buf; @@ -8985,16 +7945,6 @@ static u32 xdp_convert_ctx_access(enum bpf_access_type type, offsetof(struct xdp_rxq_info, queue_index)); break; - case offsetof(struct xdp_md, egress_ifindex): - *insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct xdp_buff, txq), - si->dst_reg, si->src_reg, - offsetof(struct xdp_buff, txq)); - *insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct xdp_txq_info, dev), - si->dst_reg, si->dst_reg, - offsetof(struct xdp_txq_info, dev)); - *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg, si->dst_reg, - offsetof(struct net_device, ifindex)); - break; } return insn - insn_buf; @@ -9075,8 +8025,8 @@ static u32 sock_addr_convert_ctx_access(enum bpf_access_type type, struct bpf_insn *insn_buf, struct bpf_prog *prog, u32 *target_size) { - int off, port_size = sizeof_field(struct sockaddr_in6, sin6_port); struct bpf_insn *insn = insn_buf; + int off; switch (si->off) { case offsetof(struct bpf_sock_addr, user_family): @@ -9111,11 +8061,9 @@ static u32 sock_addr_convert_ctx_access(enum bpf_access_type type, offsetof(struct sockaddr_in6, sin6_port)); BUILD_BUG_ON(FIELD_SIZEOF(struct sockaddr_in, sin_port) != FIELD_SIZEOF(struct sockaddr_in6, sin6_port)); - /* Account for sin6_port being smaller than user_port. */ - port_size = min(port_size, BPF_LDST_BYTES(si)); - SOCK_ADDR_LOAD_OR_STORE_NESTED_FIELD_SIZE_OFF( - struct bpf_sock_addr_kern, struct sockaddr_in6, uaddr, - sin6_port, bytes_to_bpf_size(port_size), 0, tmp_reg); + SOCK_ADDR_LOAD_OR_STORE_NESTED_FIELD(struct bpf_sock_addr_kern, + struct sockaddr_in6, uaddr, + sin6_port, tmp_reg); break; case offsetof(struct bpf_sock_addr, family): @@ -9124,13 +8072,20 @@ static u32 sock_addr_convert_ctx_access(enum bpf_access_type type, break; case offsetof(struct bpf_sock_addr, type): - SOCK_ADDR_LOAD_NESTED_FIELD(struct bpf_sock_addr_kern, - struct sock, sk, sk_type); + SOCK_ADDR_LOAD_NESTED_FIELD_SIZE_OFF( + struct bpf_sock_addr_kern, struct sock, sk, + __sk_flags_offset, BPF_W, 0); + *insn++ = BPF_ALU32_IMM(BPF_AND, si->dst_reg, SK_FL_TYPE_MASK); + *insn++ = BPF_ALU32_IMM(BPF_RSH, si->dst_reg, SK_FL_TYPE_SHIFT); break; case offsetof(struct bpf_sock_addr, protocol): - SOCK_ADDR_LOAD_NESTED_FIELD(struct bpf_sock_addr_kern, - struct sock, sk, sk_protocol); + SOCK_ADDR_LOAD_NESTED_FIELD_SIZE_OFF( + struct bpf_sock_addr_kern, struct sock, sk, + __sk_flags_offset, BPF_W, 0); + *insn++ = BPF_ALU32_IMM(BPF_AND, si->dst_reg, SK_FL_PROTO_MASK); + *insn++ = BPF_ALU32_IMM(BPF_RSH, si->dst_reg, + SK_FL_PROTO_SHIFT); break; case offsetof(struct bpf_sock_addr, msg_src_ip4): @@ -9171,31 +8126,15 @@ static u32 sock_ops_convert_ctx_access(enum bpf_access_type type, /* Helper macro for adding read access to tcp_sock or sock fields. */ #define SOCK_OPS_GET_FIELD(BPF_FIELD, OBJ_FIELD, OBJ) \ do { \ - int fullsock_reg = si->dst_reg, reg = BPF_REG_9, jmp = 2; \ BUILD_BUG_ON(FIELD_SIZEOF(OBJ, OBJ_FIELD) > \ FIELD_SIZEOF(struct bpf_sock_ops, BPF_FIELD)); \ - if (si->dst_reg == reg || si->src_reg == reg) \ - reg--; \ - if (si->dst_reg == reg || si->src_reg == reg) \ - reg--; \ - if (si->dst_reg == si->src_reg) { \ - *insn++ = BPF_STX_MEM(BPF_DW, si->src_reg, reg, \ - offsetof(struct bpf_sock_ops_kern, \ - temp)); \ - fullsock_reg = reg; \ - jmp += 2; \ - } \ *insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF( \ struct bpf_sock_ops_kern, \ is_fullsock), \ - fullsock_reg, si->src_reg, \ + si->dst_reg, si->src_reg, \ offsetof(struct bpf_sock_ops_kern, \ is_fullsock)); \ - *insn++ = BPF_JMP_IMM(BPF_JEQ, fullsock_reg, 0, jmp); \ - if (si->dst_reg == si->src_reg) \ - *insn++ = BPF_LDX_MEM(BPF_DW, reg, si->src_reg, \ - offsetof(struct bpf_sock_ops_kern, \ - temp)); \ + *insn++ = BPF_JMP_IMM(BPF_JEQ, si->dst_reg, 0, 2); \ *insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF( \ struct bpf_sock_ops_kern, sk),\ si->dst_reg, si->src_reg, \ @@ -9204,12 +8143,6 @@ static u32 sock_ops_convert_ctx_access(enum bpf_access_type type, OBJ_FIELD), \ si->dst_reg, si->dst_reg, \ offsetof(OBJ, OBJ_FIELD)); \ - if (si->dst_reg == si->src_reg) { \ - *insn++ = BPF_JMP_A(1); \ - *insn++ = BPF_LDX_MEM(BPF_DW, reg, si->src_reg, \ - offsetof(struct bpf_sock_ops_kern, \ - temp)); \ - } \ } while (0) #define SOCK_OPS_GET_SK() \ @@ -9304,22 +8237,17 @@ static u32 sock_ops_convert_ctx_access(enum bpf_access_type type, return insn - insn_buf; switch (si->off) { - case offsetof(struct bpf_sock_ops, op): - *insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct bpf_sock_ops_kern, - op), - si->dst_reg, si->src_reg, - offsetof(struct bpf_sock_ops_kern, op)); - break; - - case offsetof(struct bpf_sock_ops, replylong[0]) ... + case offsetof(struct bpf_sock_ops, op) ... offsetof(struct bpf_sock_ops, replylong[3]): + BUILD_BUG_ON(FIELD_SIZEOF(struct bpf_sock_ops, op) != + FIELD_SIZEOF(struct bpf_sock_ops_kern, op)); BUILD_BUG_ON(FIELD_SIZEOF(struct bpf_sock_ops, reply) != FIELD_SIZEOF(struct bpf_sock_ops_kern, reply)); BUILD_BUG_ON(FIELD_SIZEOF(struct bpf_sock_ops, replylong) != FIELD_SIZEOF(struct bpf_sock_ops_kern, replylong)); off = si->off; - off -= offsetof(struct bpf_sock_ops, replylong[0]); - off += offsetof(struct bpf_sock_ops_kern, replylong[0]); + off -= offsetof(struct bpf_sock_ops, op); + off += offsetof(struct bpf_sock_ops_kern, op); if (type == BPF_WRITE) *insn++ = BPF_STX_MEM(BPF_W, si->dst_reg, si->src_reg, off); @@ -9540,49 +8468,6 @@ static u32 sock_ops_convert_ctx_access(enum bpf_access_type type, case offsetof(struct bpf_sock_ops, sk): SOCK_OPS_GET_SK(); break; - case offsetof(struct bpf_sock_ops, skb_data_end): - *insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct bpf_sock_ops_kern, - skb_data_end), - si->dst_reg, si->src_reg, - offsetof(struct bpf_sock_ops_kern, - skb_data_end)); - break; - case offsetof(struct bpf_sock_ops, skb_data): - *insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct bpf_sock_ops_kern, - skb), - si->dst_reg, si->src_reg, - offsetof(struct bpf_sock_ops_kern, - skb)); - *insn++ = BPF_JMP_IMM(BPF_JEQ, si->dst_reg, 0, 1); - *insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct sk_buff, data), - si->dst_reg, si->dst_reg, - offsetof(struct sk_buff, data)); - break; - case offsetof(struct bpf_sock_ops, skb_len): - *insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct bpf_sock_ops_kern, - skb), - si->dst_reg, si->src_reg, - offsetof(struct bpf_sock_ops_kern, - skb)); - *insn++ = BPF_JMP_IMM(BPF_JEQ, si->dst_reg, 0, 1); - *insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct sk_buff, len), - si->dst_reg, si->dst_reg, - offsetof(struct sk_buff, len)); - break; - case offsetof(struct bpf_sock_ops, skb_tcp_flags): - off = offsetof(struct sk_buff, cb); - off += offsetof(struct tcp_skb_cb, tcp_flags); - *target_size = sizeof_field(struct tcp_skb_cb, tcp_flags); - *insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct bpf_sock_ops_kern, - skb), - si->dst_reg, si->src_reg, - offsetof(struct bpf_sock_ops_kern, - skb)); - *insn++ = BPF_JMP_IMM(BPF_JEQ, si->dst_reg, 0, 1); - *insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct tcp_skb_cb, - tcp_flags), - si->dst_reg, si->dst_reg, off); - break; } return insn - insn_buf; } @@ -9764,12 +8649,6 @@ static u32 sk_msg_convert_ctx_access(enum bpf_access_type type, si->dst_reg, si->src_reg, offsetof(struct sk_msg_sg, size)); break; - - case offsetof(struct sk_msg_md, sk): - *insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct sk_msg, sk), - si->dst_reg, si->src_reg, - offsetof(struct sk_msg, sk)); - break; } return insn - insn_buf; @@ -9937,7 +8816,8 @@ int sk_detach_filter(struct sock *sk) } EXPORT_SYMBOL_GPL(sk_detach_filter); -int sk_get_filter(struct sock *sk, sockptr_t optval, unsigned int len) +int sk_get_filter(struct sock *sk, struct sock_filter __user *ubuf, + unsigned int len) { struct sock_fprog_kern *fprog; struct sk_filter *filter; @@ -9968,7 +8848,7 @@ int sk_get_filter(struct sock *sk, sockptr_t optval, unsigned int len) goto out; ret = -EFAULT; - if (copy_to_sockptr(optval, fprog->filter, bpf_classic_proglen(fprog))) + if (copy_to_user(ubuf, fprog->filter, bpf_classic_proglen(fprog))) goto out; /* Instead of bytes, the API requests to return the number @@ -9981,6 +8861,16 @@ out: } #ifdef CONFIG_INET +struct sk_reuseport_kern { + struct sk_buff *skb; + struct sock *sk; + struct sock *selected_sk; + void *data_end; + u32 hash; + u32 reuseport_id; + bool bind_inany; +}; + static void bpf_init_reuseport_kern(struct sk_reuseport_kern *reuse_kern, struct sock_reuseport *reuse, struct sock *sk, struct sk_buff *skb, @@ -10014,51 +8904,46 @@ struct sock *bpf_run_sk_reuseport(struct sock_reuseport *reuse, struct sock *sk, BPF_CALL_4(sk_select_reuseport, struct sk_reuseport_kern *, reuse_kern, struct bpf_map *, map, void *, key, u32, flags) { - bool is_sockarray = map->map_type == BPF_MAP_TYPE_REUSEPORT_SOCKARRAY; struct sock_reuseport *reuse; struct sock *selected_sk; - int err; selected_sk = map->ops->map_lookup_elem(map, key); if (!selected_sk) return -ENOENT; reuse = rcu_dereference(selected_sk->sk_reuseport_cb); - if (!reuse) { - /* reuseport_array has only sk with non NULL sk_reuseport_cb. - * The only (!reuse) case here is - the sk has already been - * unhashed (e.g. by close()), so treat it as -ENOENT. - * - * Other maps (e.g. sock_map) do not provide this guarantee and - * the sk may never be in the reuseport group to begin with. + if (!reuse) + /* selected_sk is unhashed (e.g. by close()) after the + * above map_lookup_elem(). Treat selected_sk has already + * been removed from the map. */ - err = is_sockarray ? -ENOENT : -EINVAL; - goto error; - } + return -ENOENT; if (unlikely(reuse->reuseport_id != reuse_kern->reuseport_id)) { - struct sock *sk = reuse_kern->sk; + struct sock *sk; - if (sk->sk_protocol != selected_sk->sk_protocol) { - err = -EPROTOTYPE; - } else if (sk->sk_family != selected_sk->sk_family) { - err = -EAFNOSUPPORT; - } else { - /* Catch all. Likely bound to a different sockaddr. */ - err = -EBADFD; - } - goto error; + if (unlikely(!reuse_kern->reuseport_id)) + /* There is a small race between adding the + * sk to the map and setting the + * reuse_kern->reuseport_id. + * Treat it as the sk has not been added to + * the bpf map yet. + */ + return -ENOENT; + + sk = reuse_kern->sk; + if (sk->sk_protocol != selected_sk->sk_protocol) + return -EPROTOTYPE; + else if (sk->sk_family != selected_sk->sk_family) + return -EAFNOSUPPORT; + + /* Catch all. Likely bound to a different sockaddr. */ + return -EBADFD; } reuse_kern->selected_sk = selected_sk; return 0; -error: - /* Lookup in sock_map can return TCP ESTABLISHED sockets. */ - if (sk_is_refcounted(selected_sk)) - sock_put(selected_sk); - - return err; } static const struct bpf_func_proto sk_select_reuseport_proto = { @@ -10151,7 +9036,7 @@ sk_reuseport_is_valid_access(int off, int size, case bpf_ctx_range(struct sk_reuseport_md, eth_protocol): if (size < FIELD_SIZEOF(struct sk_buff, protocol)) return false; - fallthrough; + /* fall through */ case bpf_ctx_range(struct sk_reuseport_md, ip_protocol): case bpf_ctx_range(struct sk_reuseport_md, bind_inany): case bpf_ctx_range(struct sk_reuseport_md, len): @@ -10177,11 +9062,11 @@ sk_reuseport_is_valid_access(int off, int size, skb, \ SKB_FIELD) -#define SK_REUSEPORT_LOAD_SK_FIELD(SK_FIELD) \ - SOCK_ADDR_LOAD_NESTED_FIELD(struct sk_reuseport_kern, \ - struct sock, \ - sk, \ - SK_FIELD) +#define SK_REUSEPORT_LOAD_SK_FIELD_SIZE_OFF(SK_FIELD, BPF_SIZE, EXTRA_OFF) \ + SOCK_ADDR_LOAD_NESTED_FIELD_SIZE_OFF(struct sk_reuseport_kern, \ + struct sock, \ + sk, \ + SK_FIELD, BPF_SIZE, EXTRA_OFF) static u32 sk_reuseport_convert_ctx_access(enum bpf_access_type type, const struct bpf_insn *si, @@ -10205,7 +9090,16 @@ static u32 sk_reuseport_convert_ctx_access(enum bpf_access_type type, break; case offsetof(struct sk_reuseport_md, ip_protocol): - SK_REUSEPORT_LOAD_SK_FIELD(sk_protocol); + BUILD_BUG_ON(HWEIGHT32(SK_FL_PROTO_MASK) != BITS_PER_BYTE); + SK_REUSEPORT_LOAD_SK_FIELD_SIZE_OFF(__sk_flags_offset, + BPF_W, 0); + *insn++ = BPF_ALU32_IMM(BPF_AND, si->dst_reg, SK_FL_PROTO_MASK); + *insn++ = BPF_ALU32_IMM(BPF_RSH, si->dst_reg, + SK_FL_PROTO_SHIFT); + /* SK_FL_PROTO_MASK and SK_FL_PROTO_SHIFT are endian + * aware. No further narrowing or masking is needed. + */ + *target_size = 1; break; case offsetof(struct sk_reuseport_md, data_end): @@ -10232,344 +9126,4 @@ const struct bpf_verifier_ops sk_reuseport_verifier_ops = { const struct bpf_prog_ops sk_reuseport_prog_ops = { }; - -DEFINE_STATIC_KEY_FALSE(bpf_sk_lookup_enabled); -EXPORT_SYMBOL(bpf_sk_lookup_enabled); - -BPF_CALL_3(bpf_sk_lookup_assign, struct bpf_sk_lookup_kern *, ctx, - struct sock *, sk, u64, flags) -{ - if (unlikely(flags & ~(BPF_SK_LOOKUP_F_REPLACE | - BPF_SK_LOOKUP_F_NO_REUSEPORT))) - return -EINVAL; - if (unlikely(sk && sk_is_refcounted(sk))) - return -ESOCKTNOSUPPORT; /* reject non-RCU freed sockets */ - if (unlikely(sk && sk->sk_state == TCP_ESTABLISHED)) - return -ESOCKTNOSUPPORT; /* reject connected sockets */ - - /* Check if socket is suitable for packet L3/L4 protocol */ - if (sk && sk->sk_protocol != ctx->protocol) - return -EPROTOTYPE; - if (sk && sk->sk_family != ctx->family && - (sk->sk_family == AF_INET || ipv6_only_sock(sk))) - return -EAFNOSUPPORT; - - if (ctx->selected_sk && !(flags & BPF_SK_LOOKUP_F_REPLACE)) - return -EEXIST; - - /* Select socket as lookup result */ - ctx->selected_sk = sk; - ctx->no_reuseport = flags & BPF_SK_LOOKUP_F_NO_REUSEPORT; - return 0; -} - -static const struct bpf_func_proto bpf_sk_lookup_assign_proto = { - .func = bpf_sk_lookup_assign, - .gpl_only = false, - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_CTX, - .arg2_type = ARG_PTR_TO_SOCKET_OR_NULL, - .arg3_type = ARG_ANYTHING, -}; - -static const struct bpf_func_proto * -sk_lookup_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) -{ - switch (func_id) { - case BPF_FUNC_perf_event_output: - return &bpf_event_output_data_proto; - case BPF_FUNC_sk_assign: - return &bpf_sk_lookup_assign_proto; - case BPF_FUNC_sk_release: - return &bpf_sk_release_proto; - default: - return bpf_sk_base_func_proto(func_id); - } -} - -static bool sk_lookup_is_valid_access(int off, int size, - enum bpf_access_type type, - const struct bpf_prog *prog, - struct bpf_insn_access_aux *info) -{ - if (off < 0 || off >= sizeof(struct bpf_sk_lookup)) - return false; - if (off % size != 0) - return false; - if (type != BPF_READ) - return false; - - switch (off) { - case offsetof(struct bpf_sk_lookup, sk): - info->reg_type = PTR_TO_SOCKET_OR_NULL; - return size == sizeof(__u64); - - case bpf_ctx_range(struct bpf_sk_lookup, family): - case bpf_ctx_range(struct bpf_sk_lookup, protocol): - case bpf_ctx_range(struct bpf_sk_lookup, remote_ip4): - case bpf_ctx_range(struct bpf_sk_lookup, local_ip4): - case bpf_ctx_range_till(struct bpf_sk_lookup, remote_ip6[0], remote_ip6[3]): - case bpf_ctx_range_till(struct bpf_sk_lookup, local_ip6[0], local_ip6[3]): - case bpf_ctx_range(struct bpf_sk_lookup, remote_port): - case bpf_ctx_range(struct bpf_sk_lookup, local_port): - bpf_ctx_record_field_size(info, sizeof(__u32)); - return bpf_ctx_narrow_access_ok(off, size, sizeof(__u32)); - - default: - return false; - } -} - -static u32 sk_lookup_convert_ctx_access(enum bpf_access_type type, - const struct bpf_insn *si, - struct bpf_insn *insn_buf, - struct bpf_prog *prog, - u32 *target_size) -{ - struct bpf_insn *insn = insn_buf; - - switch (si->off) { - case offsetof(struct bpf_sk_lookup, sk): - *insn++ = BPF_LDX_MEM(BPF_SIZEOF(void *), si->dst_reg, si->src_reg, - offsetof(struct bpf_sk_lookup_kern, selected_sk)); - break; - - case offsetof(struct bpf_sk_lookup, family): - *insn++ = BPF_LDX_MEM(BPF_H, si->dst_reg, si->src_reg, - bpf_target_off(struct bpf_sk_lookup_kern, - family, 2, target_size)); - break; - - case offsetof(struct bpf_sk_lookup, protocol): - *insn++ = BPF_LDX_MEM(BPF_H, si->dst_reg, si->src_reg, - bpf_target_off(struct bpf_sk_lookup_kern, - protocol, 2, target_size)); - break; - - case offsetof(struct bpf_sk_lookup, remote_ip4): - *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg, si->src_reg, - bpf_target_off(struct bpf_sk_lookup_kern, - v4.saddr, 4, target_size)); - break; - - case offsetof(struct bpf_sk_lookup, local_ip4): - *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg, si->src_reg, - bpf_target_off(struct bpf_sk_lookup_kern, - v4.daddr, 4, target_size)); - break; - - case bpf_ctx_range_till(struct bpf_sk_lookup, - remote_ip6[0], remote_ip6[3]): { -#if IS_ENABLED(CONFIG_IPV6) - int off = si->off; - - off -= offsetof(struct bpf_sk_lookup, remote_ip6[0]); - off += bpf_target_off(struct in6_addr, s6_addr32[0], 4, target_size); - *insn++ = BPF_LDX_MEM(BPF_SIZEOF(void *), si->dst_reg, si->src_reg, - offsetof(struct bpf_sk_lookup_kern, v6.saddr)); - *insn++ = BPF_JMP_IMM(BPF_JEQ, si->dst_reg, 0, 1); - *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg, si->dst_reg, off); -#else - *insn++ = BPF_MOV32_IMM(si->dst_reg, 0); -#endif - break; - } - case bpf_ctx_range_till(struct bpf_sk_lookup, - local_ip6[0], local_ip6[3]): { -#if IS_ENABLED(CONFIG_IPV6) - int off = si->off; - - off -= offsetof(struct bpf_sk_lookup, local_ip6[0]); - off += bpf_target_off(struct in6_addr, s6_addr32[0], 4, target_size); - *insn++ = BPF_LDX_MEM(BPF_SIZEOF(void *), si->dst_reg, si->src_reg, - offsetof(struct bpf_sk_lookup_kern, v6.daddr)); - *insn++ = BPF_JMP_IMM(BPF_JEQ, si->dst_reg, 0, 1); - *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg, si->dst_reg, off); -#else - *insn++ = BPF_MOV32_IMM(si->dst_reg, 0); -#endif - break; - } - case offsetof(struct bpf_sk_lookup, remote_port): - *insn++ = BPF_LDX_MEM(BPF_H, si->dst_reg, si->src_reg, - bpf_target_off(struct bpf_sk_lookup_kern, - sport, 2, target_size)); - break; - - case offsetof(struct bpf_sk_lookup, local_port): - *insn++ = BPF_LDX_MEM(BPF_H, si->dst_reg, si->src_reg, - bpf_target_off(struct bpf_sk_lookup_kern, - dport, 2, target_size)); - break; - } - - return insn - insn_buf; -} - -const struct bpf_prog_ops sk_lookup_prog_ops = { -}; - -const struct bpf_verifier_ops sk_lookup_verifier_ops = { - .get_func_proto = sk_lookup_func_proto, - .is_valid_access = sk_lookup_is_valid_access, - .convert_ctx_access = sk_lookup_convert_ctx_access, -}; - #endif /* CONFIG_INET */ - -DEFINE_BPF_DISPATCHER(xdp) - -void bpf_prog_change_xdp(struct bpf_prog *prev_prog, struct bpf_prog *prog) -{ - bpf_dispatcher_change_prog(BPF_DISPATCHER_PTR(xdp), prev_prog, prog); -} - -#ifdef CONFIG_DEBUG_INFO_BTF -BTF_ID_LIST_GLOBAL(btf_sock_ids) -#define BTF_SOCK_TYPE(name, type) BTF_ID(struct, type) -BTF_SOCK_TYPE_xxx -#undef BTF_SOCK_TYPE -#else -u32 btf_sock_ids[MAX_BTF_SOCK_TYPE]; -#endif - -BPF_CALL_1(bpf_skc_to_tcp6_sock, struct sock *, sk) -{ - /* tcp6_sock type is not generated in dwarf and hence btf, - * trigger an explicit type generation here. - */ - BTF_TYPE_EMIT(struct tcp6_sock); - if (sk && sk_fullsock(sk) && sk->sk_protocol == IPPROTO_TCP && - sk->sk_family == AF_INET6) - return (unsigned long)sk; - - return (unsigned long)NULL; -} - -const struct bpf_func_proto bpf_skc_to_tcp6_sock_proto = { - .func = bpf_skc_to_tcp6_sock, - .gpl_only = false, - .ret_type = RET_PTR_TO_BTF_ID_OR_NULL, - .arg1_type = ARG_PTR_TO_BTF_ID_SOCK_COMMON, - .ret_btf_id = &btf_sock_ids[BTF_SOCK_TYPE_TCP6], -}; - -BPF_CALL_1(bpf_skc_to_tcp_sock, struct sock *, sk) -{ - if (sk && sk_fullsock(sk) && sk->sk_protocol == IPPROTO_TCP) - return (unsigned long)sk; - - return (unsigned long)NULL; -} - -const struct bpf_func_proto bpf_skc_to_tcp_sock_proto = { - .func = bpf_skc_to_tcp_sock, - .gpl_only = false, - .ret_type = RET_PTR_TO_BTF_ID_OR_NULL, - .arg1_type = ARG_PTR_TO_BTF_ID_SOCK_COMMON, - .ret_btf_id = &btf_sock_ids[BTF_SOCK_TYPE_TCP], -}; - -BPF_CALL_1(bpf_skc_to_tcp_timewait_sock, struct sock *, sk) -{ - /* BTF types for tcp_timewait_sock and inet_timewait_sock are not - * generated if CONFIG_INET=n. Trigger an explicit generation here. - */ - BTF_TYPE_EMIT(struct inet_timewait_sock); - BTF_TYPE_EMIT(struct tcp_timewait_sock); - -#ifdef CONFIG_INET - if (sk && sk->sk_prot == &tcp_prot && sk->sk_state == TCP_TIME_WAIT) - return (unsigned long)sk; -#endif - -#if IS_BUILTIN(CONFIG_IPV6) - if (sk && sk->sk_prot == &tcpv6_prot && sk->sk_state == TCP_TIME_WAIT) - return (unsigned long)sk; -#endif - - return (unsigned long)NULL; -} - -const struct bpf_func_proto bpf_skc_to_tcp_timewait_sock_proto = { - .func = bpf_skc_to_tcp_timewait_sock, - .gpl_only = false, - .ret_type = RET_PTR_TO_BTF_ID_OR_NULL, - .arg1_type = ARG_PTR_TO_BTF_ID_SOCK_COMMON, - .ret_btf_id = &btf_sock_ids[BTF_SOCK_TYPE_TCP_TW], -}; - -BPF_CALL_1(bpf_skc_to_tcp_request_sock, struct sock *, sk) -{ -#ifdef CONFIG_INET - if (sk && sk->sk_prot == &tcp_prot && sk->sk_state == TCP_NEW_SYN_RECV) - return (unsigned long)sk; -#endif - -#if IS_BUILTIN(CONFIG_IPV6) - if (sk && sk->sk_prot == &tcpv6_prot && sk->sk_state == TCP_NEW_SYN_RECV) - return (unsigned long)sk; -#endif - - return (unsigned long)NULL; -} - -const struct bpf_func_proto bpf_skc_to_tcp_request_sock_proto = { - .func = bpf_skc_to_tcp_request_sock, - .gpl_only = false, - .ret_type = RET_PTR_TO_BTF_ID_OR_NULL, - .arg1_type = ARG_PTR_TO_BTF_ID_SOCK_COMMON, - .ret_btf_id = &btf_sock_ids[BTF_SOCK_TYPE_TCP_REQ], -}; - -BPF_CALL_1(bpf_skc_to_udp6_sock, struct sock *, sk) -{ - /* udp6_sock type is not generated in dwarf and hence btf, - * trigger an explicit type generation here. - */ - BTF_TYPE_EMIT(struct udp6_sock); - if (sk && sk_fullsock(sk) && sk->sk_protocol == IPPROTO_UDP && - sk->sk_type == SOCK_DGRAM && sk->sk_family == AF_INET6) - return (unsigned long)sk; - - return (unsigned long)NULL; -} - -const struct bpf_func_proto bpf_skc_to_udp6_sock_proto = { - .func = bpf_skc_to_udp6_sock, - .gpl_only = false, - .ret_type = RET_PTR_TO_BTF_ID_OR_NULL, - .arg1_type = ARG_PTR_TO_BTF_ID_SOCK_COMMON, - .ret_btf_id = &btf_sock_ids[BTF_SOCK_TYPE_UDP6], -}; - -static const struct bpf_func_proto * -bpf_sk_base_func_proto(enum bpf_func_id func_id) -{ - const struct bpf_func_proto *func; - - switch (func_id) { - case BPF_FUNC_skc_to_tcp6_sock: - func = &bpf_skc_to_tcp6_sock_proto; - break; - case BPF_FUNC_skc_to_tcp_sock: - func = &bpf_skc_to_tcp_sock_proto; - break; - case BPF_FUNC_skc_to_tcp_timewait_sock: - func = &bpf_skc_to_tcp_timewait_sock_proto; - break; - case BPF_FUNC_skc_to_tcp_request_sock: - func = &bpf_skc_to_tcp_request_sock_proto; - break; - case BPF_FUNC_skc_to_udp6_sock: - func = &bpf_skc_to_udp6_sock_proto; - break; - default: - return bpf_base_func_proto(func_id); - } - - if (!perfmon_capable()) - return NULL; - - return func; -} diff --git a/net/core/flow_dissector.c b/net/core/flow_dissector.c index b47f8a3f279c..96d2635aaae0 100644 --- a/net/core/flow_dissector.c +++ b/net/core/flow_dissector.c @@ -31,7 +31,8 @@ #include #include #endif -#include + +static DEFINE_MUTEX(flow_dissector_mutex); static void dissector_set_key(struct flow_dissector *flow_dissector, enum flow_dissector_key_id key_id) @@ -69,37 +70,120 @@ void skb_flow_dissector_init(struct flow_dissector *flow_dissector, } EXPORT_SYMBOL(skb_flow_dissector_init); -#ifdef CONFIG_BPF_SYSCALL -int flow_dissector_bpf_prog_attach_check(struct net *net, - struct bpf_prog *prog) +int skb_flow_dissector_prog_query(const union bpf_attr *attr, + union bpf_attr __user *uattr) { - enum netns_bpf_attach_type type = NETNS_BPF_FLOW_DISSECTOR; + __u32 __user *prog_ids = u64_to_user_ptr(attr->query.prog_ids); + u32 prog_id, prog_cnt = 0, flags = 0; + struct bpf_prog *attached; + struct net *net; - if (net == &init_net) { - /* BPF flow dissector in the root namespace overrides - * any per-net-namespace one. When attaching to root, - * make sure we don't have any BPF program attached - * to the non-root namespaces. - */ - struct net *ns; + if (attr->query.query_flags) + return -EINVAL; - for_each_net(ns) { - if (ns == &init_net) - continue; - if (rcu_access_pointer(ns->bpf.run_array[type])) - return -EEXIST; - } - } else { - /* Make sure root flow dissector is not attached - * when attaching to the non-root namespace. - */ - if (rcu_access_pointer(init_net.bpf.run_array[type])) - return -EEXIST; + net = get_net_ns_by_fd(attr->query.target_fd); + if (IS_ERR(net)) + return PTR_ERR(net); + + rcu_read_lock(); + attached = rcu_dereference(net->flow_dissector_prog); + if (attached) { + prog_cnt = 1; + prog_id = attached->aux->id; } + rcu_read_unlock(); + + put_net(net); + + if (copy_to_user(&uattr->query.attach_flags, &flags, sizeof(flags))) + return -EFAULT; + if (copy_to_user(&uattr->query.prog_cnt, &prog_cnt, sizeof(prog_cnt))) + return -EFAULT; + + if (!attr->query.prog_cnt || !prog_ids || !prog_cnt) + return 0; + + if (copy_to_user(prog_ids, &prog_id, sizeof(u32))) + return -EFAULT; return 0; } -#endif /* CONFIG_BPF_SYSCALL */ + +int skb_flow_dissector_bpf_prog_attach(const union bpf_attr *attr, + struct bpf_prog *prog) +{ + struct bpf_prog *attached; + struct net *net; + + net = current->nsproxy->net_ns; + mutex_lock(&flow_dissector_mutex); + attached = rcu_dereference_protected(net->flow_dissector_prog, + lockdep_is_held(&flow_dissector_mutex)); + if (attached) { + /* Only one BPF program can be attached at a time */ + mutex_unlock(&flow_dissector_mutex); + return -EEXIST; + } + rcu_assign_pointer(net->flow_dissector_prog, prog); + mutex_unlock(&flow_dissector_mutex); + return 0; +} + +static int flow_dissector_bpf_prog_detach(struct net *net) +{ + struct bpf_prog *attached; + + mutex_lock(&flow_dissector_mutex); + attached = rcu_dereference_protected(net->flow_dissector_prog, + lockdep_is_held(&flow_dissector_mutex)); + if (!attached) { + mutex_unlock(&flow_dissector_mutex); + return -ENOENT; + } + RCU_INIT_POINTER(net->flow_dissector_prog, NULL); + bpf_prog_put(attached); + mutex_unlock(&flow_dissector_mutex); + return 0; +} +/** + * skb_flow_get_be16 - extract be16 entity + * @skb: sk_buff to extract from + * @poff: offset to extract at + * @data: raw buffer pointer to the packet + * @hlen: packet header length + * + * The function will try to retrieve a be32 entity at + * offset poff + */ +static __be16 skb_flow_get_be16(const struct sk_buff *skb, int poff, + void *data, int hlen) +{ + __be16 *u, _u; + + u = __skb_header_pointer(skb, poff, sizeof(_u), data, hlen, &_u); + if (u) + return *u; + + return 0; +} + +int skb_flow_dissector_bpf_prog_detach(const union bpf_attr *attr) +{ + return flow_dissector_bpf_prog_detach(current->nsproxy->net_ns); +} + +static void __net_exit flow_dissector_pernet_pre_exit(struct net *net) +{ + /* We're not racing with attach/detach because there are no + * references to netns left when pre_exit gets called. + */ + if (rcu_access_pointer(net->flow_dissector_prog)) + flow_dissector_bpf_prog_detach(net); +} + +static struct pernet_operations flow_dissector_pernet_ops __net_initdata = { + .pre_exit = flow_dissector_pernet_pre_exit, +}; /** * __skb_flow_get_ports - extract the upper layer ports and return them @@ -135,72 +219,6 @@ __be32 __skb_flow_get_ports(const struct sk_buff *skb, int thoff, u8 ip_proto, } EXPORT_SYMBOL(__skb_flow_get_ports); -static bool icmp_has_id(u8 type) -{ - switch (type) { - case ICMP_ECHO: - case ICMP_ECHOREPLY: - case ICMP_TIMESTAMP: - case ICMP_TIMESTAMPREPLY: - case ICMPV6_ECHO_REQUEST: - case ICMPV6_ECHO_REPLY: - return true; - } - - return false; -} - -/** - * skb_flow_get_icmp_tci - extract ICMP(6) Type, Code and Identifier fields - * @skb: sk_buff to extract from - * @key_icmp: struct flow_dissector_key_icmp to fill - * @data: raw buffer pointer to the packet - * @toff: offset to extract at - * @hlen: packet header length - */ -void skb_flow_get_icmp_tci(const struct sk_buff *skb, - struct flow_dissector_key_icmp *key_icmp, - void *data, int thoff, int hlen) -{ - struct icmphdr *ih, _ih; - - ih = __skb_header_pointer(skb, thoff, sizeof(_ih), data, hlen, &_ih); - if (!ih) - return; - - key_icmp->type = ih->type; - key_icmp->code = ih->code; - - /* As we use 0 to signal that the Id field is not present, - * avoid confusion with packets without such field - */ - if (icmp_has_id(ih->type)) - key_icmp->id = ih->un.echo.id ? : 1; - else - key_icmp->id = 0; -} -EXPORT_SYMBOL(skb_flow_get_icmp_tci); - -/* If FLOW_DISSECTOR_KEY_ICMP is set, dissect an ICMP packet - * using skb_flow_get_icmp_tci(). - */ -static void __skb_flow_dissect_icmp(const struct sk_buff *skb, - struct flow_dissector *flow_dissector, - void *target_container, - void *data, int thoff, int hlen) -{ - struct flow_dissector_key_icmp *key_icmp; - - if (!dissector_uses_key(flow_dissector, FLOW_DISSECTOR_KEY_ICMP)) - return; - - key_icmp = skb_flow_dissector_target(flow_dissector, - FLOW_DISSECTOR_KEY_ICMP, - target_container); - - skb_flow_get_icmp_tci(skb, key_icmp, data, thoff, hlen); -} - void skb_flow_dissect_meta(const struct sk_buff *skb, struct flow_dissector *flow_dissector, void *target_container) @@ -893,8 +911,10 @@ bool __skb_flow_dissect(const struct net *net, struct flow_dissector_key_control *key_control; struct flow_dissector_key_basic *key_basic; struct flow_dissector_key_addrs *key_addrs; + struct flow_dissector_key_icmp *key_icmp; struct flow_dissector_key_tags *key_tags; struct flow_dissector_key_vlan *key_vlan; + struct bpf_prog *attached = NULL; enum flow_dissect_ret fdret; enum flow_dissector_key_id dissector_vlan = FLOW_DISSECTOR_KEY_MAX; int num_hdrs = 0; @@ -948,15 +968,10 @@ bool __skb_flow_dissect(const struct net *net, WARN_ON_ONCE(!net); if (net) { - enum netns_bpf_attach_type type = NETNS_BPF_FLOW_DISSECTOR; - struct bpf_prog_array *run_array; - rcu_read_lock(); - run_array = rcu_dereference(init_net.bpf.run_array[type]); - if (!run_array) - run_array = rcu_dereference(net->bpf.run_array[type]); + attached = rcu_dereference(net->flow_dissector_prog); - if (run_array) { + if (attached) { struct bpf_flow_keys flow_keys; struct bpf_flow_dissector ctx = { .flow_keys = &flow_keys, @@ -964,7 +979,6 @@ bool __skb_flow_dissect(const struct net *net, .data_end = data + hlen, }; __be16 n_proto = proto; - struct bpf_prog *prog; if (skb) { ctx.skb = skb; @@ -975,8 +989,7 @@ bool __skb_flow_dissect(const struct net *net, n_proto = skb->protocol; } - prog = READ_ONCE(run_array->items[0].prog); - ret = bpf_flow_dissect(prog, &ctx, n_proto, nhoff, + ret = bpf_flow_dissect(attached, &ctx, n_proto, nhoff, hlen, flags); __skb_flow_bpf_to_target(&flow_keys, flow_dissector, target_container); @@ -1346,12 +1359,6 @@ ip_proto_again: data, nhoff, hlen); break; - case IPPROTO_ICMP: - case IPPROTO_ICMPV6: - __skb_flow_dissect_icmp(skb, flow_dissector, target_container, - data, nhoff, hlen); - break; - default: break; } @@ -1360,6 +1367,14 @@ ip_proto_again: __skb_flow_dissect_ports(skb, flow_dissector, target_container, data, nhoff, ip_proto, hlen); + if (dissector_uses_key(flow_dissector, + FLOW_DISSECTOR_KEY_ICMP)) { + key_icmp = skb_flow_dissector_target(flow_dissector, + FLOW_DISSECTOR_KEY_ICMP, + target_container); + key_icmp->icmp = skb_flow_get_be16(skb, nhoff, data, hlen); + } + /* Process result of IP proto processing */ switch (fdret) { case FLOW_DISSECT_RET_PROTO_AGAIN: @@ -1409,10 +1424,8 @@ static const void *flow_keys_hash_start(const struct flow_keys *flow) static inline size_t flow_keys_hash_length(const struct flow_keys *flow) { size_t diff = FLOW_KEYS_HASH_OFFSET + sizeof(flow->addrs); - /* flow.addrs MUST be the last member in struct flow_keys because - * different L3 protocols have different address length - */ - BUILD_BUG_ON((sizeof(*flow) - FLOW_KEYS_HASH_OFFSET) % sizeof(u32)); + BUILD_BUG_ON(offsetof(typeof(*flow), addrs) != + sizeof(*flow) - sizeof(flow->addrs)); switch (flow->control.addr_type) { case FLOW_DISSECTOR_KEY_IPV4_ADDRS: @@ -1458,9 +1471,6 @@ __be32 flow_get_u32_dst(const struct flow_keys *flow) } EXPORT_SYMBOL(flow_get_u32_dst); -/* Sort the source and destination IP (and the ports if the IP are the same), - * to have consistent hash within the two directions - */ static inline void __flow_hash_consistentify(struct flow_keys *keys) { int addr_diff, i; @@ -1780,6 +1790,7 @@ static int __init init_default_flow_dissectors(void) skb_flow_dissector_init(&flow_keys_basic_dissector, flow_keys_basic_dissector_keys, ARRAY_SIZE(flow_keys_basic_dissector_keys)); - return 0; + + return register_pernet_subsys(&flow_dissector_pernet_ops); } core_initcall(init_default_flow_dissectors); diff --git a/net/core/lwt_bpf.c b/net/core/lwt_bpf.c index f91d3f53f218..017ed82611a8 100644 --- a/net/core/lwt_bpf.c +++ b/net/core/lwt_bpf.c @@ -39,10 +39,10 @@ static int run_lwt_bpf(struct sk_buff *skb, struct bpf_lwt_prog *lwt, { int ret; - /* Migration disable and BH disable are needed to protect per-cpu + /* Preempt disable and BH disable are needed to protect per-cpu * redirect_info between BPF prog and skb_do_redirect(). */ - migrate_disable(); + preempt_disable(); local_bh_disable(); bpf_compute_data_pointers(skb); ret = bpf_prog_run_save_cb(lwt->prog, skb); @@ -77,7 +77,7 @@ static int run_lwt_bpf(struct sk_buff *skb, struct bpf_lwt_prog *lwt, } local_bh_enable(); - migrate_enable(); + preempt_enable(); return ret; } diff --git a/net/core/neighbour.c b/net/core/neighbour.c index cdc23a9fea3c..d15f813e3672 100644 --- a/net/core/neighbour.c +++ b/net/core/neighbour.c @@ -3419,7 +3419,7 @@ EXPORT_SYMBOL(neigh_app_ns); static int unres_qlen_max = INT_MAX / SKB_TRUESIZE(ETH_FRAME_LEN); static int proc_unres_qlen(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int size, ret; struct ctl_table tmp = *ctl; @@ -3483,8 +3483,8 @@ static void neigh_proc_update(struct ctl_table *ctl, int write) } static int neigh_proc_dointvec_zero_intmax(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, - loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { struct ctl_table tmp = *ctl; int ret; @@ -3497,8 +3497,8 @@ static int neigh_proc_dointvec_zero_intmax(struct ctl_table *ctl, int write, return ret; } -int neigh_proc_dointvec(struct ctl_table *ctl, int write, void *buffer, - size_t *lenp, loff_t *ppos) +int neigh_proc_dointvec(struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) { int ret = proc_dointvec(ctl, write, buffer, lenp, ppos); @@ -3507,7 +3507,8 @@ int neigh_proc_dointvec(struct ctl_table *ctl, int write, void *buffer, } EXPORT_SYMBOL(neigh_proc_dointvec); -int neigh_proc_dointvec_jiffies(struct ctl_table *ctl, int write, void *buffer, +int neigh_proc_dointvec_jiffies(struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) { int ret = proc_dointvec_jiffies(ctl, write, buffer, lenp, ppos); @@ -3518,8 +3519,8 @@ int neigh_proc_dointvec_jiffies(struct ctl_table *ctl, int write, void *buffer, EXPORT_SYMBOL(neigh_proc_dointvec_jiffies); static int neigh_proc_dointvec_userhz_jiffies(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, - loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { int ret = proc_dointvec_userhz_jiffies(ctl, write, buffer, lenp, ppos); @@ -3528,7 +3529,8 @@ static int neigh_proc_dointvec_userhz_jiffies(struct ctl_table *ctl, int write, } int neigh_proc_dointvec_ms_jiffies(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { int ret = proc_dointvec_ms_jiffies(ctl, write, buffer, lenp, ppos); @@ -3538,8 +3540,8 @@ int neigh_proc_dointvec_ms_jiffies(struct ctl_table *ctl, int write, EXPORT_SYMBOL(neigh_proc_dointvec_ms_jiffies); static int neigh_proc_dointvec_unres_qlen(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, - loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { int ret = proc_unres_qlen(ctl, write, buffer, lenp, ppos); @@ -3548,8 +3550,8 @@ static int neigh_proc_dointvec_unres_qlen(struct ctl_table *ctl, int write, } static int neigh_proc_base_reachable_time(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, - loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { struct neigh_parms *p = ctl->extra2; int ret; diff --git a/net/core/net_namespace.c b/net/core/net_namespace.c index 1f7e48138860..c94179d30d42 100644 --- a/net/core/net_namespace.c +++ b/net/core/net_namespace.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include @@ -70,8 +69,6 @@ EXPORT_SYMBOL_GPL(pernet_ops_rwsem); static unsigned int max_gen_ptrs = INITIAL_NET_GEN_PTRS; -DEFINE_COOKIE(net_cookie); - static struct net_generic *net_alloc_generic(void) { unsigned int gen_ptrs = READ_ONCE(max_gen_ptrs); @@ -341,9 +338,6 @@ static __net_init int setup_net(struct net *net, struct user_namespace *user_ns) refcount_set(&net->count, 1); refcount_set(&net->passive, 1); get_random_bytes(&net->hash_mix, sizeof(u32)); - preempt_disable(); - atomic64_set(&net->net_cookie, gen_cookie_next(&net_cookie)); - preempt_enable(); net->dev_base_seq = 1; net->user_ns = user_ns; idr_init(&net->netns_ids); diff --git a/net/core/netpoll.c b/net/core/netpoll.c index f537bc05c8c3..09ae2fc41fa9 100644 --- a/net/core/netpoll.c +++ b/net/core/netpoll.c @@ -858,10 +858,6 @@ void __netpoll_cleanup(struct netpoll *np) synchronize_srcu(&netpoll_srcu); - /* At this point, there is a single npinfo instance per netdevice, and - * its refcnt tracks how many netpoll structures are linked to it. We - * only perform npinfo cleanup when the refcnt decrements to zero. - */ if (refcount_dec_and_test(&npinfo->refcnt)) { const struct net_device_ops *ops; @@ -871,7 +867,8 @@ void __netpoll_cleanup(struct netpoll *np) RCU_INIT_POINTER(np->dev->npinfo, NULL); call_rcu(&npinfo->rcu, rcu_cleanup_netpoll_info); - } + } else + RCU_INIT_POINTER(np->dev->npinfo, NULL); } EXPORT_SYMBOL_GPL(__netpoll_cleanup); diff --git a/net/core/page_pool.c b/net/core/page_pool.c index ec44d0f4086b..10a8ab47e9a7 100644 --- a/net/core/page_pool.c +++ b/net/core/page_pool.c @@ -33,7 +33,11 @@ static int page_pool_init(struct page_pool *pool, return -EINVAL; if (pool->p.pool_size) - ring_qsize = min(pool->p.pool_size, 16384); + ring_qsize = pool->p.pool_size; + + /* Sanity limit mem that can be pinned down */ + if (ring_qsize > 32768) + return -E2BIG; /* DMA direction is either DMA_FROM_DEVICE or DMA_BIDIRECTIONAL. * DMA_BIDIRECTIONAL is for allowing page used for DMA sending, diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c index 1d642045878b..2b7ad5cf8fbf 100644 --- a/net/core/rtnetlink.c +++ b/net/core/rtnetlink.c @@ -1384,12 +1384,13 @@ static u32 rtnl_xdp_prog_skb(struct net_device *dev) static u32 rtnl_xdp_prog_drv(struct net_device *dev) { - return dev_xdp_prog_id(dev, XDP_MODE_DRV); + return __dev_xdp_query(dev, dev->netdev_ops->ndo_bpf, XDP_QUERY_PROG); } static u32 rtnl_xdp_prog_hw(struct net_device *dev) { - return dev_xdp_prog_id(dev, XDP_MODE_HW); + return __dev_xdp_query(dev, dev->netdev_ops->ndo_bpf, + XDP_QUERY_PROG_HW); } static int rtnl_xdp_report_one(struct sk_buff *skb, struct net_device *dev, @@ -1802,9 +1803,7 @@ static const struct nla_policy ifla_port_policy[IFLA_PORT_MAX+1] = { }; static const struct nla_policy ifla_xdp_policy[IFLA_XDP_MAX + 1] = { - [IFLA_XDP_UNSPEC] = { .strict_start_type = IFLA_XDP_EXPECTED_FD }, [IFLA_XDP_FD] = { .type = NLA_S32 }, - [IFLA_XDP_EXPECTED_FD] = { .type = NLA_S32 }, [IFLA_XDP_ATTACHED] = { .type = NLA_U8 }, [IFLA_XDP_FLAGS] = { .type = NLA_U32 }, [IFLA_XDP_PROG_ID] = { .type = NLA_U32 }, @@ -2746,20 +2745,8 @@ static int do_setlink(const struct sk_buff *skb, } if (xdp[IFLA_XDP_FD]) { - int expected_fd = -1; - - if (xdp_flags & XDP_FLAGS_REPLACE) { - if (!xdp[IFLA_XDP_EXPECTED_FD]) { - err = -EINVAL; - goto errout; - } - expected_fd = - nla_get_s32(xdp[IFLA_XDP_EXPECTED_FD]); - } - err = dev_change_xdp_fd(dev, extack, nla_get_s32(xdp[IFLA_XDP_FD]), - expected_fd, xdp_flags); if (err) goto errout; diff --git a/net/core/skbuff.c b/net/core/skbuff.c index 15e7a2a27989..0b21a9902e29 100644 --- a/net/core/skbuff.c +++ b/net/core/skbuff.c @@ -1605,7 +1605,6 @@ struct sk_buff *__pskb_copy_fclone(struct sk_buff *skb, int headroom, skb_frag_ref(skb, i); } skb_shinfo(n)->nr_frags = i; - skb_shinfo(n)->tx_flags |= skb_shinfo(skb)->tx_flags & SKBTX_SHARED_FRAG; } if (skb_has_frag_list(skb)) { @@ -3360,7 +3359,19 @@ EXPORT_SYMBOL(skb_split); */ static int skb_prepare_for_shift(struct sk_buff *skb) { - return skb_unclone_keeptruesize(skb, GFP_ATOMIC); + int ret = 0; + + if (skb_cloned(skb)) { + /* Save and restore truesize: pskb_expand_head() may reallocate + * memory where ksize(kmalloc(S)) != ksize(kmalloc(S)), but we + * cannot change truesize at this point. + */ + unsigned int save_truesize = skb->truesize; + + ret = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); + skb->truesize = save_truesize; + } + return ret; } /** @@ -3490,8 +3501,6 @@ onlymerged: tgt->ip_summed = CHECKSUM_PARTIAL; skb->ip_summed = CHECKSUM_PARTIAL; - skb_shinfo(tgt)->tx_flags |= skb_shinfo(skb)->tx_flags & SKBTX_SHARED_FRAG; - /* Yak, is it really working this way? Some helper please? */ skb->len -= shiftlen; skb->data_len -= shiftlen; @@ -3835,8 +3844,6 @@ int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb) p->truesize += skb->truesize; p->len += skb->len; - skb_shinfo(p)->tx_flags |= skb_shinfo(skb)->tx_flags & SKBTX_SHARED_FRAG; - NAPI_GRO_CB(skb)->same_flow = 1; return 0; @@ -4066,8 +4073,7 @@ normal: skb_copy_from_linear_data_offset(head_skb, offset, skb_put(nskb, hsize), hsize); - skb_shinfo(nskb)->tx_flags |= (skb_shinfo(head_skb)->tx_flags | - skb_shinfo(frag_skb)->tx_flags) & + skb_shinfo(nskb)->tx_flags |= skb_shinfo(head_skb)->tx_flags & SKBTX_SHARED_FRAG; if (skb_zerocopy_clone(nskb, frag_skb, GFP_ATOMIC)) @@ -4084,9 +4090,6 @@ normal: nfrags = skb_shinfo(list_skb)->nr_frags; frag = skb_shinfo(list_skb)->frags; frag_skb = list_skb; - - skb_shinfo(nskb)->tx_flags |= skb_shinfo(frag_skb)->tx_flags & SKBTX_SHARED_FRAG; - if (!skb_headlen(list_skb)) { BUG_ON(!nfrags); } else { @@ -4303,12 +4306,10 @@ done: p->data_len += len; p->truesize += delta_truesize; p->len += len; - skb_shinfo(p)->tx_flags |= skb_shinfo(skb)->tx_flags & SKBTX_SHARED_FRAG; if (lp != p) { lp->data_len += len; lp->truesize += delta_truesize; lp->len += len; - skb_shinfo(lp)->tx_flags |= skbinfo->tx_flags & SKBTX_SHARED_FRAG; } NAPI_GRO_CB(skb)->same_flow = 1; return 0; @@ -5306,8 +5307,6 @@ bool skb_try_coalesce(struct sk_buff *to, struct sk_buff *from, from_shinfo->frags, from_shinfo->nr_frags * sizeof(skb_frag_t)); to_shinfo->nr_frags += from_shinfo->nr_frags; - if (from_shinfo->nr_frags) - to_shinfo->tx_flags |= from_shinfo->tx_flags & SKBTX_SHARED_FRAG; if (!skb_cloned(from)) from_shinfo->nr_frags = 0; @@ -6036,8 +6035,6 @@ static int pskb_carve_inside_header(struct sk_buff *skb, const u32 off, kfree(data); return -ENOMEM; } - if (skb_zcopy(skb)) - refcount_inc(&skb_uarg(skb)->refcnt); for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) skb_frag_ref(skb, i); if (skb_has_frag_list(skb)) @@ -6191,8 +6188,6 @@ static int pskb_carve_inside_nonlinear(struct sk_buff *skb, const u32 off, kfree(data); return -ENOMEM; } - if (skb_zcopy(skb)) - refcount_inc(&skb_uarg(skb)->refcnt); skb_release_data(skb); skb->head = data; diff --git a/net/core/skmsg.c b/net/core/skmsg.c index e1477e062ca7..dfc2e4d6a7a0 100644 --- a/net/core/skmsg.c +++ b/net/core/skmsg.c @@ -549,35 +549,14 @@ end: struct sk_psock *sk_psock_init(struct sock *sk, int node) { - struct sk_psock *psock; - struct proto *prot; + struct sk_psock *psock = kzalloc_node(sizeof(*psock), + GFP_ATOMIC | __GFP_NOWARN, + node); + if (!psock) + return NULL; - write_lock_bh(&sk->sk_callback_lock); - - if (inet_csk_has_ulp(sk)) { - psock = ERR_PTR(-EINVAL); - goto out; - } - - if (sk->sk_user_data) { - psock = ERR_PTR(-EBUSY); - goto out; - } - - psock = kzalloc_node(sizeof(*psock), GFP_ATOMIC | __GFP_NOWARN, node); - if (!psock) { - psock = ERR_PTR(-ENOMEM); - goto out; - } - - prot = READ_ONCE(sk->sk_prot); psock->sk = sk; - psock->eval = __SK_NONE; - psock->sk_proto = prot; - psock->saved_destroy = prot->destroy; - psock->saved_unhash = prot->unhash; - psock->saved_close = prot->close; - psock->saved_write_space = sk->sk_write_space; + psock->eval = __SK_NONE; INIT_LIST_HEAD(&psock->link); spin_lock_init(&psock->link_lock); @@ -589,11 +568,9 @@ struct sk_psock *sk_psock_init(struct sock *sk, int node) sk_psock_set_state(psock, SK_PSOCK_TX_ENABLED); refcount_set(&psock->refcnt, 1); - rcu_assign_sk_user_data_nocopy(sk, psock); + rcu_assign_sk_user_data(sk, psock); sock_hold(sk); -out: - write_unlock_bh(&sk->sk_callback_lock); return psock; } EXPORT_SYMBOL_GPL(sk_psock_init); @@ -638,15 +615,15 @@ static void sk_psock_link_destroy(struct sk_psock *psock) } } -static void sk_psock_done_strp(struct sk_psock *psock); - static void sk_psock_destroy_deferred(struct work_struct *gc) { struct sk_psock *psock = container_of(gc, struct sk_psock, gc); /* No sk_callback_lock since already detached. */ - sk_psock_done_strp(psock); + /* Parser has been stopped */ + if (psock->progs.skb_parser) + strp_done(&psock->parser.strp); cancel_work_sync(&psock->work); @@ -681,8 +658,6 @@ void sk_psock_drop(struct sock *sk, struct sk_psock *psock) rcu_assign_sk_user_data(sk, NULL); if (psock->progs.skb_parser) sk_psock_stop_strp(sk, psock); - else if (psock->progs.skb_verdict) - sk_psock_stop_verdict(sk, psock); write_unlock_bh(&sk->sk_callback_lock); sk_psock_clear_state(psock, SK_PSOCK_TX_ENABLED); @@ -759,6 +734,14 @@ static int sk_psock_bpf_run(struct sk_psock *psock, struct bpf_prog *prog, return ret; } +static struct sk_psock *sk_psock_from_strp(struct strparser *strp) +{ + struct sk_psock_parser *parser; + + parser = container_of(strp, struct sk_psock_parser, strp); + return container_of(parser, struct sk_psock, parser); +} + static void sk_psock_skb_redirect(struct sk_buff *skb) { struct sk_psock *psock_other; @@ -865,24 +848,6 @@ out_free: } } -static void sk_psock_write_space(struct sock *sk) -{ - struct sk_psock *psock; - void (*write_space)(struct sock *sk) = NULL; - - rcu_read_lock(); - psock = sk_psock(sk); - if (likely(psock)) { - if (sk_psock_test_state(psock, SK_PSOCK_TX_ENABLED)) - schedule_work(&psock->work); - write_space = psock->saved_write_space; - } - rcu_read_unlock(); - if (write_space) - write_space(sk); -} - -#if IS_ENABLED(CONFIG_BPF_STREAM_PARSER) static void sk_psock_strp_read(struct strparser *strp, struct sk_buff *skb) { struct sk_psock *psock; @@ -914,14 +879,6 @@ static int sk_psock_strp_read_done(struct strparser *strp, int err) return err; } -static struct sk_psock *sk_psock_from_strp(struct strparser *strp) -{ - struct sk_psock_parser *parser; - - parser = container_of(strp, struct sk_psock_parser, strp); - return container_of(parser, struct sk_psock, parser); -} - static int sk_psock_strp_parse(struct strparser *strp, struct sk_buff *skb) { struct sk_psock *psock = sk_psock_from_strp(strp); @@ -955,6 +912,23 @@ static void sk_psock_strp_data_ready(struct sock *sk) rcu_read_unlock(); } +static void sk_psock_write_space(struct sock *sk) +{ + struct sk_psock *psock; + void (*write_space)(struct sock *sk) = NULL; + + rcu_read_lock(); + psock = sk_psock(sk); + if (likely(psock)) { + if (sk_psock_test_state(psock, SK_PSOCK_TX_ENABLED)) + schedule_work(&psock->work); + write_space = psock->saved_write_space; + } + rcu_read_unlock(); + if (write_space) + write_space(sk); +} + int sk_psock_init_strp(struct sock *sk, struct sk_psock *psock) { static const struct strp_callbacks cb = { @@ -992,91 +966,3 @@ void sk_psock_stop_strp(struct sock *sk, struct sk_psock *psock) strp_stop(&parser->strp); parser->enabled = false; } - -static void sk_psock_done_strp(struct sk_psock *psock) -{ - /* Parser has been stopped */ - if (psock->progs.skb_parser) - strp_done(&psock->parser.strp); -} -#else -static void sk_psock_done_strp(struct sk_psock *psock) -{ -} -#endif /* CONFIG_BPF_STREAM_PARSER */ - -static int sk_psock_verdict_recv(read_descriptor_t *desc, struct sk_buff *skb, - unsigned int offset, size_t orig_len) -{ - struct sock *sk = (struct sock *)desc->arg.data; - struct sk_psock *psock; - struct bpf_prog *prog; - int ret = __SK_DROP; - int len = skb->len; - - /* clone here so sk_eat_skb() in tcp_read_sock does not drop our data */ - skb = skb_clone(skb, GFP_ATOMIC); - if (!skb) { - desc->error = -ENOMEM; - return 0; - } - - rcu_read_lock(); - psock = sk_psock(sk); - if (unlikely(!psock)) { - len = 0; - kfree_skb(skb); - goto out; - } - skb_set_owner_r(skb, sk); - prog = READ_ONCE(psock->progs.skb_verdict); - if (likely(prog)) { - tcp_skb_bpf_redirect_clear(skb); - ret = sk_psock_bpf_run(psock, prog, skb); - ret = sk_psock_map_verd(ret, tcp_skb_bpf_redirect_fetch(skb)); - } - sk_psock_verdict_apply(psock, skb, ret); -out: - rcu_read_unlock(); - return len; -} - -static void sk_psock_verdict_data_ready(struct sock *sk) -{ - struct socket *sock = sk->sk_socket; - read_descriptor_t desc; - - if (unlikely(!sock || !sock->ops || !sock->ops->read_sock)) - return; - - desc.arg.data = sk; - desc.error = 0; - desc.count = 1; - - sock->ops->read_sock(sk, &desc, sk_psock_verdict_recv); -} - -void sk_psock_start_verdict(struct sock *sk, struct sk_psock *psock) -{ - struct sk_psock_parser *parser = &psock->parser; - - if (parser->enabled) - return; - - parser->saved_data_ready = sk->sk_data_ready; - sk->sk_data_ready = sk_psock_verdict_data_ready; - sk->sk_write_space = sk_psock_write_space; - parser->enabled = true; -} - -void sk_psock_stop_verdict(struct sock *sk, struct sk_psock *psock) -{ - struct sk_psock_parser *parser = &psock->parser; - - if (!parser->enabled) - return; - - sk->sk_data_ready = parser->saved_data_ready; - parser->saved_data_ready = NULL; - parser->enabled = false; -} diff --git a/net/core/sock.c b/net/core/sock.c index 1c9d99fe59cb..461e23c56a98 100644 --- a/net/core/sock.c +++ b/net/core/sock.c @@ -570,7 +570,7 @@ struct dst_entry *sk_dst_check(struct sock *sk, u32 cookie) } EXPORT_SYMBOL(sk_dst_check); -static int sock_bindtoindex_locked(struct sock *sk, int ifindex) +static int sock_setbindtodevice_locked(struct sock *sk, int ifindex) { int ret = -ENOPROTOOPT; #ifdef CONFIG_NETDEVICES @@ -578,7 +578,7 @@ static int sock_bindtoindex_locked(struct sock *sk, int ifindex) /* Sorry... */ ret = -EPERM; - if (sk->sk_bound_dev_if && !ns_capable(net->user_ns, CAP_NET_RAW)) + if (!ns_capable(net->user_ns, CAP_NET_RAW)) goto out; ret = -EINVAL; @@ -598,20 +598,6 @@ out: return ret; } -int sock_bindtoindex(struct sock *sk, int ifindex, bool lock_sk) -{ - int ret; - - if (lock_sk) - lock_sock(sk); - ret = sock_bindtoindex_locked(sk, ifindex); - if (lock_sk) - release_sock(sk); - - return ret; -} -EXPORT_SYMBOL(sock_bindtoindex); - static int sock_setbindtodevice(struct sock *sk, char __user *optval, int optlen) { @@ -652,15 +638,18 @@ static int sock_setbindtodevice(struct sock *sk, char __user *optval, goto out; } - return sock_bindtoindex(sk, index, true); + lock_sock(sk); + ret = sock_setbindtodevice_locked(sk, index); + release_sock(sk); + out: #endif return ret; } -static int sock_getbindtodevice(struct sock *sk, sockptr_t optval, - sockptr_t optlen, int len) +static int sock_getbindtodevice(struct sock *sk, char __user *optval, + int __user *optlen, int len) { int ret = -ENOPROTOOPT; #ifdef CONFIG_NETDEVICES @@ -683,12 +672,12 @@ static int sock_getbindtodevice(struct sock *sk, sockptr_t optval, len = strlen(devname) + 1; ret = -EFAULT; - if (copy_to_sockptr(optval, devname, len)) + if (copy_to_user(optval, devname, len)) goto out; zero: ret = -EFAULT; - if (copy_to_sockptr(optlen, &len, sizeof(int))) + if (put_user(len, optlen)) goto out; ret = 0; @@ -699,6 +688,14 @@ out: return ret; } +static inline void sock_valbool_flag(struct sock *sk, int bit, int valbool) +{ + if (valbool) + sock_set_flag(sk, bit); + else + sock_reset_flag(sk, bit); +} + bool sk_mc_loop(struct sock *sk) { if (dev_recursion_level()) @@ -989,15 +986,19 @@ set_rcvbuf: ret = sock_set_timeout(&sk->sk_sndtimeo, optval, optlen, optname == SO_SNDTIMEO_OLD); break; - case SO_ATTACH_FILTER: { - struct sock_fprog fprog; + case SO_ATTACH_FILTER: + ret = -EINVAL; + if (optlen == sizeof(struct sock_fprog)) { + struct sock_fprog fprog; + + ret = -EFAULT; + if (copy_from_user(&fprog, optval, sizeof(fprog))) + break; - ret = copy_bpf_fprog_from_user(&fprog, USER_SOCKPTR(optval), - optlen); - if (!ret) ret = sk_attach_filter(&fprog, sk); + } break; - } + case SO_ATTACH_BPF: ret = -EINVAL; if (optlen == sizeof(u32)) { @@ -1011,15 +1012,19 @@ set_rcvbuf: } break; - case SO_ATTACH_REUSEPORT_CBPF: { - struct sock_fprog fprog; + case SO_ATTACH_REUSEPORT_CBPF: + ret = -EINVAL; + if (optlen == sizeof(struct sock_fprog)) { + struct sock_fprog fprog; + + ret = -EFAULT; + if (copy_from_user(&fprog, optval, sizeof(fprog))) + break; - ret = copy_bpf_fprog_from_user(&fprog, USER_SOCKPTR(optval), - optlen); - if (!ret) ret = sk_reuseport_attach_filter(&fprog, sk); + } break; - } + case SO_ATTACH_REUSEPORT_EBPF: ret = -EINVAL; if (optlen == sizeof(u32)) { @@ -1167,7 +1172,7 @@ set_rcvbuf: break; case SO_BINDTOIFINDEX: - ret = sock_bindtoindex_locked(sk, val); + ret = sock_setbindtodevice_locked(sk, val); break; default: @@ -1203,25 +1208,22 @@ static void cred_to_ucred(struct pid *pid, const struct cred *cred, } } -static int groups_to_user(sockptr_t dst, const struct group_info *src) +static int groups_to_user(gid_t __user *dst, const struct group_info *src) { struct user_namespace *user_ns = current_user_ns(); int i; - for (i = 0; i < src->ngroups; i++) { - gid_t gid = from_kgid_munged(user_ns, src->gid[i]); - - if (copy_to_sockptr_offset(dst, i * sizeof(gid), &gid, sizeof(gid))) + for (i = 0; i < src->ngroups; i++) + if (put_user(from_kgid_munged(user_ns, src->gid[i]), dst + i)) return -EFAULT; - } return 0; } -static int sk_getsockopt(struct sock *sk, int level, int optname, - sockptr_t optval, sockptr_t optlen) +int sock_getsockopt(struct socket *sock, int level, int optname, + char __user *optval, int __user *optlen) { - struct socket *sock = sk->sk_socket; + struct sock *sk = sock->sk; union { int val; @@ -1237,7 +1239,7 @@ static int sk_getsockopt(struct sock *sk, int level, int optname, int lv = sizeof(int); int len; - if (copy_from_sockptr(&len, optlen, sizeof(int))) + if (get_user(len, optlen)) return -EFAULT; if (len < 0) return -EINVAL; @@ -1371,7 +1373,7 @@ static int sk_getsockopt(struct sock *sk, int level, int optname, cred_to_ucred(sk->sk_peer_pid, sk->sk_peer_cred, &peercred); spin_unlock(&sk->sk_peer_lock); - if (copy_to_sockptr(optval, &peercred, len)) + if (copy_to_user(optval, &peercred, len)) return -EFAULT; goto lenout; } @@ -1389,11 +1391,11 @@ static int sk_getsockopt(struct sock *sk, int level, int optname, if (len < n * sizeof(gid_t)) { len = n * sizeof(gid_t); put_cred(cred); - return copy_to_sockptr(optlen, &len, sizeof(int)) ? -EFAULT : -ERANGE; + return put_user(len, optlen) ? -EFAULT : -ERANGE; } len = n * sizeof(gid_t); - ret = groups_to_user(optval, cred->group_info); + ret = groups_to_user((gid_t __user *)optval, cred->group_info); put_cred(cred); if (ret) return ret; @@ -1409,7 +1411,7 @@ static int sk_getsockopt(struct sock *sk, int level, int optname, return -ENOTCONN; if (lv < len) return -EINVAL; - if (copy_to_sockptr(optval, address, len)) + if (copy_to_user(optval, address, len)) return -EFAULT; goto lenout; } @@ -1426,7 +1428,7 @@ static int sk_getsockopt(struct sock *sk, int level, int optname, break; case SO_PEERSEC: - return security_socket_getpeersec_stream(sock, optval.user, optlen.user, len); + return security_socket_getpeersec_stream(sock, optval, optlen, len); case SO_MARK: v.val = sk->sk_mark; @@ -1454,7 +1456,7 @@ static int sk_getsockopt(struct sock *sk, int level, int optname, return sock_getbindtodevice(sk, optval, optlen, len); case SO_GET_FILTER: - len = sk_get_filter(sk, optval, len); + len = sk_get_filter(sk, (struct sock_filter __user *)optval, len); if (len < 0) return len; @@ -1501,7 +1503,7 @@ static int sk_getsockopt(struct sock *sk, int level, int optname, sk_get_meminfo(sk, meminfo); len = min_t(unsigned int, len, sizeof(meminfo)); - if (copy_to_sockptr(optval, &meminfo, len)) + if (copy_to_user(optval, &meminfo, len)) return -EFAULT; goto lenout; @@ -1542,13 +1544,6 @@ static int sk_getsockopt(struct sock *sk, int level, int optname, v.val = sk->sk_bound_dev_if; break; - case SO_NETNS_COOKIE: - lv = sizeof(u64); - if (len != lv) - return -EINVAL; - v.val64 = atomic64_read(&sock_net(sk)->net_cookie); - break; - default: /* We implement the SO_SNDLOWAT etc to not be settable * (1003.1g 7). @@ -1558,22 +1553,14 @@ static int sk_getsockopt(struct sock *sk, int level, int optname, if (len > lv) len = lv; - if (copy_to_sockptr(optval, &v, len)) + if (copy_to_user(optval, &v, len)) return -EFAULT; lenout: - if (copy_to_sockptr(optlen, &len, sizeof(int))) + if (put_user(len, optlen)) return -EFAULT; return 0; } -int sock_getsockopt(struct socket *sock, int level, int optname, - char __user *optval, int __user *optlen) -{ - return sk_getsockopt(sock->sk, level, optname, - USER_SOCKPTR(optval), - USER_SOCKPTR(optlen)); -} - /* * Initialize an sk_lock. * @@ -1606,14 +1593,13 @@ static inline void sock_lock_init(struct sock *sk) */ static void sock_copy(struct sock *nsk, const struct sock *osk) { - const struct proto *prot = READ_ONCE(osk->sk_prot); #ifdef CONFIG_SECURITY_NETWORK void *sptr = nsk->sk_security; #endif memcpy(nsk, osk, offsetof(struct sock, sk_dontcopy_begin)); memcpy(&nsk->sk_dontcopy_end, &osk->sk_dontcopy_end, - prot->obj_size - offsetof(struct sock, sk_dontcopy_end)); + osk->sk_prot->obj_size - offsetof(struct sock, sk_dontcopy_end)); #ifdef CONFIG_SECURITY_NETWORK nsk->sk_security = sptr; @@ -1835,17 +1821,16 @@ static void sk_init_common(struct sock *sk) */ struct sock *sk_clone_lock(const struct sock *sk, const gfp_t priority) { - struct proto *prot = READ_ONCE(sk->sk_prot); struct sock *newsk; bool is_charged = true; - newsk = sk_prot_alloc(prot, priority, sk->sk_family); + newsk = sk_prot_alloc(sk->sk_prot, priority, sk->sk_family); if (newsk != NULL) { struct sk_filter *filter; sock_copy(newsk, sk); - newsk->sk_prot_creator = prot; + newsk->sk_prot_creator = sk->sk_prot; /* SANITY */ if (likely(newsk->sk_net_refcnt)) @@ -1910,12 +1895,6 @@ struct sock *sk_clone_lock(const struct sock *sk, const gfp_t priority) goto out; } - /* Clear sk_user_data if parent had the pointer tagged - * as not suitable for copying when cloning. - */ - if (sk_user_data_is_nocopy(newsk)) - RCU_INIT_POINTER(newsk->sk_user_data, NULL); - newsk->sk_err = 0; newsk->sk_err_soft = 0; newsk->sk_priority = 0; @@ -2108,18 +2087,6 @@ void sock_efree(struct sk_buff *skb) } EXPORT_SYMBOL(sock_efree); -/* Buffer destructor for prefetch/receive path where reference count may - * not be held, e.g. for listen sockets. - */ -#ifdef CONFIG_INET -void sock_pfree(struct sk_buff *skb) -{ - if (sk_is_refcounted(skb->sk)) - sock_gen_put(skb->sk); -} -EXPORT_SYMBOL(sock_pfree); -#endif /* CONFIG_INET */ - kuid_t sock_i_uid(struct sock *sk) { kuid_t uid; @@ -2493,27 +2460,23 @@ void __release_sock(struct sock *sk) __acquires(&sk->sk_lock.slock) { struct sk_buff *skb, *next; - int nb = 0; while ((skb = sk->sk_backlog.head) != NULL) { sk->sk_backlog.head = sk->sk_backlog.tail = NULL; spin_unlock_bh(&sk->sk_lock.slock); - while (1) { + do { next = skb->next; prefetch(next); WARN_ON_ONCE(skb_dst_is_noref(skb)); skb_mark_not_on_list(skb); sk_backlog_rcv(sk, skb); - skb = next; - if (!skb) - break; + cond_resched(); - if (!(++nb & 15)) - cond_resched(); - } + skb = next; + } while (skb != NULL); spin_lock_bh(&sk->sk_lock.slock); } @@ -2631,7 +2594,8 @@ suppress_allocation: return 1; } - trace_sock_exceed_buf_limit(sk, prot, allocated, kind); + if (kind == SK_MEM_SEND || (kind == SK_MEM_RECV && charged)) + trace_sock_exceed_buf_limit(sk, prot, allocated, kind); sk_memory_allocated_sub(sk, amt); diff --git a/net/core/sock_diag.c b/net/core/sock_diag.c index bce65b519ee8..315a5200d170 100644 --- a/net/core/sock_diag.c +++ b/net/core/sock_diag.c @@ -11,7 +11,7 @@ #include #include #include -#include + #include #include @@ -19,17 +19,16 @@ static const struct sock_diag_handler *sock_diag_handlers[AF_MAX]; static int (*inet_rcv_compat)(struct sk_buff *skb, struct nlmsghdr *nlh); static DEFINE_MUTEX(sock_diag_table_mutex); static struct workqueue_struct *broadcast_wq; +static atomic64_t cookie_gen; -DEFINE_COOKIE(sock_cookie); - -u64 __sock_gen_cookie(struct sock *sk) +u64 sock_gen_cookie(struct sock *sk) { while (1) { u64 res = atomic64_read(&sk->sk_cookie); if (res) return res; - res = gen_cookie_next(&sock_cookie); + res = atomic64_inc_return(&cookie_gen); atomic64_cmpxchg(&sk->sk_cookie, 0, res); } } diff --git a/net/core/sock_map.c b/net/core/sock_map.c index 001d7a3b6ead..3397cdd9c96d 100644 --- a/net/core/sock_map.c +++ b/net/core/sock_map.c @@ -10,8 +10,6 @@ #include #include #include -#include -#include struct bpf_stab { struct bpf_map map; @@ -33,8 +31,7 @@ static struct bpf_map *sock_map_alloc(union bpf_attr *attr) return ERR_PTR(-EPERM); if (attr->max_entries == 0 || attr->key_size != 4 || - (attr->value_size != sizeof(u32) && - attr->value_size != sizeof(u64)) || + attr->value_size != 4 || attr->map_flags & ~SOCK_CREATE_FLAG_MASK) return ERR_PTR(-EINVAL); @@ -142,8 +139,8 @@ static void sock_map_add_link(struct sk_psock *psock, static void sock_map_del_link(struct sock *sk, struct sk_psock *psock, void *link_raw) { - bool strp_stop = false, verdict_stop = false; struct sk_psock_link *link, *tmp; + bool strp_stop = false; spin_lock_bh(&psock->link_lock); list_for_each_entry_safe(link, tmp, &psock->link, list) { @@ -153,20 +150,15 @@ static void sock_map_del_link(struct sock *sk, map); if (psock->parser.enabled && stab->progs.skb_parser) strp_stop = true; - if (psock->parser.enabled && stab->progs.skb_verdict) - verdict_stop = true; list_del(&link->list); sk_psock_free_link(link); break; } } spin_unlock_bh(&psock->link_lock); - if (strp_stop || verdict_stop) { + if (strp_stop) { write_lock_bh(&sk->sk_callback_lock); - if (strp_stop) - sk_psock_stop_strp(sk, psock); - else - sk_psock_stop_verdict(sk, psock); + sk_psock_stop_strp(sk, psock); write_unlock_bh(&sk->sk_callback_lock); } } @@ -181,56 +173,12 @@ static void sock_map_unref(struct sock *sk, void *link_raw) } } -static int sock_map_init_proto(struct sock *sk, struct sk_psock *psock) -{ - struct proto *prot; - - switch (sk->sk_type) { - case SOCK_STREAM: - prot = tcp_bpf_get_proto(sk, psock); - break; - - case SOCK_DGRAM: - prot = udp_bpf_get_proto(sk, psock); - break; - - default: - return -EINVAL; - } - - if (IS_ERR(prot)) - return PTR_ERR(prot); - - sk_psock_update_proto(sk, psock, prot); - return 0; -} - -static struct sk_psock *sock_map_psock_get_checked(struct sock *sk) -{ - struct sk_psock *psock; - - rcu_read_lock(); - psock = sk_psock(sk); - if (psock) { - if (sk->sk_prot->close != sock_map_close) { - psock = ERR_PTR(-EBUSY); - goto out; - } - - if (!refcount_inc_not_zero(&psock->refcnt)) - psock = ERR_PTR(-EBUSY); - } -out: - rcu_read_unlock(); - return psock; -} - static int sock_map_link(struct bpf_map *map, struct sk_psock_progs *progs, struct sock *sk) { struct bpf_prog *msg_parser, *skb_parser, *skb_verdict; + bool skb_progs, sk_psock_is_new = false; struct sk_psock *psock; - bool skb_progs; int ret; skb_verdict = READ_ONCE(progs->skb_verdict); @@ -256,7 +204,7 @@ static int sock_map_link(struct bpf_map *map, struct sk_psock_progs *progs, } } - psock = sock_map_psock_get_checked(sk); + psock = sk_psock_get_checked(sk); if (IS_ERR(psock)) { ret = PTR_ERR(psock); goto out_progs; @@ -271,35 +219,36 @@ static int sock_map_link(struct bpf_map *map, struct sk_psock_progs *progs, } } else { psock = sk_psock_init(sk, map->numa_node); - if (IS_ERR(psock)) { - ret = PTR_ERR(psock); + if (!psock) { + ret = -ENOMEM; goto out_progs; } + sk_psock_is_new = true; } if (msg_parser) psock_set_prog(&psock->progs.msg_parser, msg_parser); - - ret = sock_map_init_proto(sk, psock); - if (ret < 0) - goto out_drop; + if (sk_psock_is_new) { + ret = tcp_bpf_init(sk); + if (ret < 0) + goto out_drop; + } else { + tcp_bpf_reinit(sk); + } write_lock_bh(&sk->sk_callback_lock); if (skb_progs && !psock->parser.enabled) { ret = sk_psock_init_strp(sk, psock); - if (ret) - goto out_unlock_drop; + if (ret) { + write_unlock_bh(&sk->sk_callback_lock); + goto out_drop; + } psock_set_prog(&psock->progs.skb_verdict, skb_verdict); psock_set_prog(&psock->progs.skb_parser, skb_parser); sk_psock_start_strp(sk, psock); - } else if (!skb_parser && skb_verdict && !psock->parser.enabled) { - psock_set_prog(&psock->progs.skb_verdict, skb_verdict); - sk_psock_start_verdict(sk,psock); } write_unlock_bh(&sk->sk_callback_lock); return 0; -out_unlock_drop: - write_unlock_bh(&sk->sk_callback_lock); out_drop: sk_psock_put(sk, psock); out_progs: @@ -313,27 +262,6 @@ out: return ret; } -static int sock_map_link_no_progs(struct bpf_map *map, struct sock *sk) -{ - struct sk_psock *psock; - int ret; - - psock = sock_map_psock_get_checked(sk); - if (IS_ERR(psock)) - return PTR_ERR(psock); - - if (!psock) { - psock = sk_psock_init(sk, map->numa_node); - if (IS_ERR(psock)) - return PTR_ERR(psock); - } - - ret = sock_map_init_proto(sk, psock); - if (ret < 0) - sk_psock_put(sk, psock); - return ret; -} - static void sock_map_free(struct bpf_map *map) { struct bpf_stab *stab = container_of(map, struct bpf_stab, map); @@ -385,29 +313,7 @@ static struct sock *__sock_map_lookup_elem(struct bpf_map *map, u32 key) static void *sock_map_lookup(struct bpf_map *map, void *key) { - struct sock *sk; - - sk = __sock_map_lookup_elem(map, *(u32 *)key); - if (!sk || !sk_fullsock(sk)) - return NULL; - if (sk_is_refcounted(sk) && !refcount_inc_not_zero(&sk->sk_refcnt)) - return NULL; - return sk; -} - -static void *sock_map_lookup_sys(struct bpf_map *map, void *key) -{ - struct sock *sk; - - if (map->value_size != sizeof(u64)) - return ERR_PTR(-ENOSPC); - - sk = __sock_map_lookup_elem(map, *(u32 *)key); - if (!sk) - return ERR_PTR(-ENOENT); - - __sock_gen_cookie(sk); - return &sk->sk_cookie; + return ERR_PTR(-EOPNOTSUPP); } static int __sock_map_delete(struct bpf_stab *stab, struct sock *sk_test, @@ -469,11 +375,6 @@ static int sock_map_get_next_key(struct bpf_map *map, void *key, void *next) return 0; } -static bool sock_map_redirect_allowed(const struct sock *sk) -{ - return sk->sk_state != TCP_LISTEN; -} - static int sock_map_update_common(struct bpf_map *map, u32 idx, struct sock *sk, u64 flags) { @@ -496,14 +397,7 @@ static int sock_map_update_common(struct bpf_map *map, u32 idx, if (!link) return -ENOMEM; - /* Only sockets we can redirect into/from in BPF need to hold - * refs to parser/verdict progs and have their sk_data_ready - * and sk_write_space callbacks overridden. - */ - if (sock_map_redirect_allowed(sk)) - ret = sock_map_link(map, &stab->progs, sk); - else - ret = sock_map_link_no_progs(map, sk); + ret = sock_map_link(map, &stab->progs, sk); if (ret < 0) goto out_free; @@ -538,54 +432,23 @@ out_free: static bool sock_map_op_okay(const struct bpf_sock_ops_kern *ops) { return ops->op == BPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB || - ops->op == BPF_SOCK_OPS_ACTIVE_ESTABLISHED_CB || - ops->op == BPF_SOCK_OPS_TCP_LISTEN_CB; + ops->op == BPF_SOCK_OPS_ACTIVE_ESTABLISHED_CB; } -static bool sk_is_tcp(const struct sock *sk) +static bool sock_map_sk_is_suitable(const struct sock *sk) { return sk->sk_type == SOCK_STREAM && sk->sk_protocol == IPPROTO_TCP; } -static bool sk_is_udp(const struct sock *sk) -{ - return sk->sk_type == SOCK_DGRAM && - sk->sk_protocol == IPPROTO_UDP; -} - -static bool sock_map_sk_is_suitable(const struct sock *sk) -{ - return sk_is_tcp(sk) || sk_is_udp(sk); -} - -static bool sock_map_sk_state_allowed(const struct sock *sk) -{ - if (sk_is_tcp(sk)) - return (1 << sk->sk_state) & (TCPF_ESTABLISHED | TCPF_LISTEN); - else if (sk_is_udp(sk)) - return sk_hashed(sk); - - return false; -} - -static int sock_hash_update_common(struct bpf_map *map, void *key, - struct sock *sk, u64 flags); - -int sock_map_update_elem_sys(struct bpf_map *map, void *key, void *value, - u64 flags) +static int sock_map_update_elem(struct bpf_map *map, void *key, + void *value, u64 flags) { + u32 ufd = *(u32 *)value; + u32 idx = *(u32 *)key; struct socket *sock; struct sock *sk; int ret; - u64 ufd; - - if (map->value_size == sizeof(u64)) - ufd = *(u64 *)value; - else - ufd = *(u32 *)value; - if (ufd > S32_MAX) - return -EINVAL; sock = sockfd_lookup(ufd, &ret); if (!sock) @@ -601,43 +464,16 @@ int sock_map_update_elem_sys(struct bpf_map *map, void *key, void *value, } sock_map_sk_acquire(sk); - if (!sock_map_sk_state_allowed(sk)) + if (sk->sk_state != TCP_ESTABLISHED) ret = -EOPNOTSUPP; - else if (map->map_type == BPF_MAP_TYPE_SOCKMAP) - ret = sock_map_update_common(map, *(u32 *)key, sk, flags); else - ret = sock_hash_update_common(map, key, sk, flags); + ret = sock_map_update_common(map, idx, sk, flags); sock_map_sk_release(sk); out: fput(sock->file); return ret; } -static int sock_map_update_elem(struct bpf_map *map, void *key, - void *value, u64 flags) -{ - struct sock *sk = (struct sock *)value; - int ret; - - if (unlikely(!sk || !sk_fullsock(sk))) - return -EINVAL; - - if (!sock_map_sk_is_suitable(sk)) - return -EOPNOTSUPP; - - local_bh_disable(); - bh_lock_sock(sk); - if (!sock_map_sk_state_allowed(sk)) - ret = -EOPNOTSUPP; - else if (map->map_type == BPF_MAP_TYPE_SOCKMAP) - ret = sock_map_update_common(map, *(u32 *)key, sk, flags); - else - ret = sock_hash_update_common(map, key, sk, flags); - bh_unlock_sock(sk); - local_bh_enable(); - return ret; -} - BPF_CALL_4(bpf_sock_map_update, struct bpf_sock_ops_kern *, sops, struct bpf_map *, map, void *, key, u64, flags) { @@ -665,17 +501,13 @@ BPF_CALL_4(bpf_sk_redirect_map, struct sk_buff *, skb, struct bpf_map *, map, u32, key, u64, flags) { struct tcp_skb_cb *tcb = TCP_SKB_CB(skb); - struct sock *sk; if (unlikely(flags & ~(BPF_F_INGRESS))) return SK_DROP; - - sk = __sock_map_lookup_elem(map, key); - if (unlikely(!sk || !sock_map_redirect_allowed(sk))) - return SK_DROP; - tcb->bpf.flags = flags; - tcb->bpf.sk_redir = sk; + tcb->bpf.sk_redir = __sock_map_lookup_elem(map, key); + if (!tcb->bpf.sk_redir) + return SK_DROP; return SK_PASS; } @@ -692,17 +524,12 @@ const struct bpf_func_proto bpf_sk_redirect_map_proto = { BPF_CALL_4(bpf_msg_redirect_map, struct sk_msg *, msg, struct bpf_map *, map, u32, key, u64, flags) { - struct sock *sk; - if (unlikely(flags & ~(BPF_F_INGRESS))) return SK_DROP; - - sk = __sock_map_lookup_elem(map, key); - if (unlikely(!sk || !sock_map_redirect_allowed(sk))) - return SK_DROP; - msg->flags = flags; - msg->sk_redir = sk; + msg->sk_redir = __sock_map_lookup_elem(map, key); + if (!msg->sk_redir) + return SK_DROP; return SK_PASS; } @@ -716,20 +543,15 @@ const struct bpf_func_proto bpf_msg_redirect_map_proto = { .arg4_type = ARG_ANYTHING, }; -static int sock_map_btf_id; const struct bpf_map_ops sock_map_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc = sock_map_alloc, .map_free = sock_map_free, .map_get_next_key = sock_map_get_next_key, - .map_lookup_elem_sys_only = sock_map_lookup_sys, .map_update_elem = sock_map_update_elem, .map_delete_elem = sock_map_delete_elem, .map_lookup_elem = sock_map_lookup, .map_release_uref = sock_map_release_progs, .map_check_btf = map_check_no_btf, - .map_btf_name = "bpf_stab", - .map_btf_id = &sock_map_btf_id, }; struct bpf_htab_elem { @@ -902,14 +724,7 @@ static int sock_hash_update_common(struct bpf_map *map, void *key, if (!link) return -ENOMEM; - /* Only sockets we can redirect into/from in BPF need to hold - * refs to parser/verdict progs and have their sk_data_ready - * and sk_write_space callbacks overridden. - */ - if (sock_map_redirect_allowed(sk)) - ret = sock_map_link(map, &htab->progs, sk); - else - ret = sock_map_link_no_progs(map, sk); + ret = sock_map_link(map, &htab->progs, sk); if (ret < 0) goto out_free; @@ -955,6 +770,38 @@ out_free: return ret; } +static int sock_hash_update_elem(struct bpf_map *map, void *key, + void *value, u64 flags) +{ + u32 ufd = *(u32 *)value; + struct socket *sock; + struct sock *sk; + int ret; + + sock = sockfd_lookup(ufd, &ret); + if (!sock) + return ret; + sk = sock->sk; + if (!sk) { + ret = -EINVAL; + goto out; + } + if (!sock_map_sk_is_suitable(sk)) { + ret = -EOPNOTSUPP; + goto out; + } + + sock_map_sk_acquire(sk); + if (sk->sk_state != TCP_ESTABLISHED) + ret = -EOPNOTSUPP; + else + ret = sock_hash_update_common(map, key, sk, flags); + sock_map_sk_release(sk); +out: + fput(sock->file); + return ret; +} + static int sock_hash_get_next_key(struct bpf_map *map, void *key, void *key_next) { @@ -1005,8 +852,7 @@ static struct bpf_map *sock_hash_alloc(union bpf_attr *attr) return ERR_PTR(-EPERM); if (attr->max_entries == 0 || attr->key_size == 0 || - (attr->value_size != sizeof(u32) && - attr->value_size != sizeof(u64)) || + attr->value_size != 4 || attr->map_flags & ~SOCK_CREATE_FLAG_MASK) return ERR_PTR(-EINVAL); if (attr->key_size > MAX_BPF_STACK) @@ -1113,33 +959,6 @@ static void sock_hash_free(struct bpf_map *map) kfree(htab); } -static void *sock_hash_lookup_sys(struct bpf_map *map, void *key) -{ - struct sock *sk; - - if (map->value_size != sizeof(u64)) - return ERR_PTR(-ENOSPC); - - sk = __sock_hash_lookup_elem(map, key); - if (!sk) - return ERR_PTR(-ENOENT); - - __sock_gen_cookie(sk); - return &sk->sk_cookie; -} - -static void *sock_hash_lookup(struct bpf_map *map, void *key) -{ - struct sock *sk; - - sk = __sock_hash_lookup_elem(map, key); - if (!sk || !sk_fullsock(sk)) - return NULL; - if (sk_is_refcounted(sk) && !refcount_inc_not_zero(&sk->sk_refcnt)) - return NULL; - return sk; -} - static void sock_hash_release_progs(struct bpf_map *map) { psock_progs_drop(&container_of(map, struct bpf_htab, map)->progs); @@ -1171,17 +990,13 @@ BPF_CALL_4(bpf_sk_redirect_hash, struct sk_buff *, skb, struct bpf_map *, map, void *, key, u64, flags) { struct tcp_skb_cb *tcb = TCP_SKB_CB(skb); - struct sock *sk; if (unlikely(flags & ~(BPF_F_INGRESS))) return SK_DROP; - - sk = __sock_hash_lookup_elem(map, key); - if (unlikely(!sk || !sock_map_redirect_allowed(sk))) - return SK_DROP; - tcb->bpf.flags = flags; - tcb->bpf.sk_redir = sk; + tcb->bpf.sk_redir = __sock_hash_lookup_elem(map, key); + if (!tcb->bpf.sk_redir) + return SK_DROP; return SK_PASS; } @@ -1198,17 +1013,12 @@ const struct bpf_func_proto bpf_sk_redirect_hash_proto = { BPF_CALL_4(bpf_msg_redirect_hash, struct sk_msg *, msg, struct bpf_map *, map, void *, key, u64, flags) { - struct sock *sk; - if (unlikely(flags & ~(BPF_F_INGRESS))) return SK_DROP; - - sk = __sock_hash_lookup_elem(map, key); - if (unlikely(!sk || !sock_map_redirect_allowed(sk))) - return SK_DROP; - msg->flags = flags; - msg->sk_redir = sk; + msg->sk_redir = __sock_hash_lookup_elem(map, key); + if (!msg->sk_redir) + return SK_DROP; return SK_PASS; } @@ -1222,20 +1032,15 @@ const struct bpf_func_proto bpf_msg_redirect_hash_proto = { .arg4_type = ARG_ANYTHING, }; -static int sock_hash_map_btf_id; const struct bpf_map_ops sock_hash_ops = { - .map_meta_equal = bpf_map_meta_equal, .map_alloc = sock_hash_alloc, .map_free = sock_hash_free, .map_get_next_key = sock_hash_get_next_key, - .map_update_elem = sock_map_update_elem, + .map_update_elem = sock_hash_update_elem, .map_delete_elem = sock_hash_delete_elem, - .map_lookup_elem = sock_hash_lookup, - .map_lookup_elem_sys_only = sock_hash_lookup_sys, + .map_lookup_elem = sock_map_lookup, .map_release_uref = sock_hash_release_progs, .map_check_btf = map_check_no_btf, - .map_btf_name = "bpf_shtab", - .map_btf_id = &sock_hash_map_btf_id, }; static struct sk_psock_progs *sock_map_progs(struct bpf_map *map) @@ -1265,11 +1070,9 @@ int sock_map_prog_update(struct bpf_map *map, struct bpf_prog *prog, case BPF_SK_MSG_VERDICT: pprog = &progs->msg_parser; break; -#if IS_ENABLED(CONFIG_BPF_STREAM_PARSER) case BPF_SK_SKB_STREAM_PARSER: pprog = &progs->skb_parser; break; -#endif case BPF_SK_SKB_STREAM_VERDICT: pprog = &progs->skb_verdict; break; @@ -1284,7 +1087,7 @@ int sock_map_prog_update(struct bpf_map *map, struct bpf_prog *prog, return 0; } -static void sock_map_unlink(struct sock *sk, struct sk_psock_link *link) +void sk_psock_unlink(struct sock *sk, struct sk_psock_link *link) { switch (link->map->map_type) { case BPF_MAP_TYPE_SOCKMAP: @@ -1297,76 +1100,3 @@ static void sock_map_unlink(struct sock *sk, struct sk_psock_link *link) break; } } - -static void sock_map_remove_links(struct sock *sk, struct sk_psock *psock) -{ - struct sk_psock_link *link; - - while ((link = sk_psock_link_pop(psock))) { - sock_map_unlink(sk, link); - sk_psock_free_link(link); - } -} - -void sock_map_unhash(struct sock *sk) -{ - void (*saved_unhash)(struct sock *sk); - struct sk_psock *psock; - - rcu_read_lock(); - psock = sk_psock(sk); - if (unlikely(!psock)) { - rcu_read_unlock(); - if (sk->sk_prot->unhash) - sk->sk_prot->unhash(sk); - return; - } - - saved_unhash = psock->saved_unhash; - sock_map_remove_links(sk, psock); - rcu_read_unlock(); - saved_unhash(sk); -} - -void sock_map_destroy(struct sock *sk) -{ - void (*saved_destroy)(struct sock *sk); - struct sk_psock *psock; - - rcu_read_lock(); - psock = sk_psock_get(sk); - if (unlikely(!psock)) { - rcu_read_unlock(); - if (sk->sk_prot->destroy) - sk->sk_prot->destroy(sk); - return; - } - - saved_destroy = psock->saved_destroy; - sock_map_remove_links(sk, psock); - rcu_read_unlock(); - sk_psock_put(sk, psock); - saved_destroy(sk); -} -EXPORT_SYMBOL_GPL(sock_map_destroy); - -void sock_map_close(struct sock *sk, long timeout) -{ - void (*saved_close)(struct sock *sk, long timeout); - struct sk_psock *psock; - - lock_sock(sk); - rcu_read_lock(); - psock = sk_psock(sk); - if (unlikely(!psock)) { - rcu_read_unlock(); - release_sock(sk); - return sk->sk_prot->close(sk, timeout); - } - - saved_close = psock->saved_close; - sock_map_remove_links(sk, psock); - rcu_read_unlock(); - release_sock(sk); - saved_close(sk, timeout); -} diff --git a/net/core/sock_reuseport.c b/net/core/sock_reuseport.c index 7227c7a35314..273c921751e4 100644 --- a/net/core/sock_reuseport.c +++ b/net/core/sock_reuseport.c @@ -16,8 +16,27 @@ DEFINE_SPINLOCK(reuseport_lock); +#define REUSEPORT_MIN_ID 1 static DEFINE_IDA(reuseport_ida); +int reuseport_get_id(struct sock_reuseport *reuse) +{ + int id; + + if (reuse->reuseport_id) + return reuse->reuseport_id; + + id = ida_simple_get(&reuseport_ida, REUSEPORT_MIN_ID, 0, + /* Called under reuseport_lock */ + GFP_ATOMIC); + if (id < 0) + return id; + + reuse->reuseport_id = id; + + return reuse->reuseport_id; +} + static struct sock_reuseport *__reuseport_alloc(unsigned int max_socks) { unsigned int size = sizeof(struct sock_reuseport) + @@ -36,7 +55,6 @@ static struct sock_reuseport *__reuseport_alloc(unsigned int max_socks) int reuseport_alloc(struct sock *sk, bool bind_inany) { struct sock_reuseport *reuse; - int id, ret = 0; /* bh lock used since this function call may precede hlist lock in * soft irq of receive path or setsockopt from process context @@ -60,18 +78,10 @@ int reuseport_alloc(struct sock *sk, bool bind_inany) reuse = __reuseport_alloc(INIT_SOCKS); if (!reuse) { - ret = -ENOMEM; - goto out; + spin_unlock_bh(&reuseport_lock); + return -ENOMEM; } - id = ida_alloc(&reuseport_ida, GFP_ATOMIC); - if (id < 0) { - kfree(reuse); - ret = id; - goto out; - } - - reuse->reuseport_id = id; reuse->socks[0] = sk; reuse->num_socks = 1; reuse->bind_inany = bind_inany; @@ -80,7 +90,7 @@ int reuseport_alloc(struct sock *sk, bool bind_inany) out: spin_unlock_bh(&reuseport_lock); - return ret; + return 0; } EXPORT_SYMBOL(reuseport_alloc); @@ -126,7 +136,8 @@ static void reuseport_free_rcu(struct rcu_head *head) reuse = container_of(head, struct sock_reuseport, rcu); sk_reuseport_prog_free(rcu_dereference_protected(reuse->prog, 1)); - ida_free(&reuseport_ida, reuse->reuseport_id); + if (reuse->reuseport_id) + ida_simple_remove(&reuseport_ida, reuse->reuseport_id); kfree(reuse); } @@ -190,15 +201,12 @@ void reuseport_detach_sock(struct sock *sk) reuse = rcu_dereference_protected(sk->sk_reuseport_cb, lockdep_is_held(&reuseport_lock)); - /* Notify the bpf side. The sk may be added to a sockarray - * map. If so, sockarray logic will remove it from the map. - * - * Other bpf map types that work with reuseport, like sockmap, - * don't need an explicit callback from here. They override sk - * unhash/close ops to remove the sk from the map before we - * get to this point. + /* At least one of the sk in this reuseport group is added to + * a bpf map. Notify the bpf side. The bpf map logic will + * remove the sk if it is indeed added to a bpf map. */ - bpf_sk_reuseport_detach(sk); + if (reuse->reuseport_id) + bpf_sk_reuseport_detach(sk); rcu_assign_pointer(sk->sk_reuseport_cb, NULL); diff --git a/net/core/sysctl_net_core.c b/net/core/sysctl_net_core.c index f18d8a2e4468..b3b39b0e0745 100644 --- a/net/core/sysctl_net_core.c +++ b/net/core/sysctl_net_core.c @@ -45,7 +45,7 @@ EXPORT_SYMBOL(sysctl_devconf_inherit_init_net); #ifdef CONFIG_RPS static int rps_sock_flow_sysctl(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { unsigned int orig_size, size; int ret, i; @@ -115,7 +115,8 @@ static int rps_sock_flow_sysctl(struct ctl_table *table, int write, static DEFINE_MUTEX(flow_limit_update_mutex); static int flow_limit_cpu_sysctl(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { struct sd_flow_limit *cur; struct softnet_data *sd; @@ -126,7 +127,7 @@ static int flow_limit_cpu_sysctl(struct ctl_table *table, int write, return -ENOMEM; if (write) { - ret = cpumask_parse(buffer, mask); + ret = cpumask_parse_user(buffer, *lenp, mask); if (ret) goto done; @@ -179,7 +180,10 @@ write_unlock: } if (len < *lenp) kbuf[len++] = '\n'; - memcpy(buffer, kbuf, len); + if (copy_to_user(buffer, kbuf, len)) { + ret = -EFAULT; + goto done; + } *lenp = len; *ppos += len; } @@ -190,7 +194,8 @@ done: } static int flow_limit_table_len_sysctl(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { unsigned int old, *ptr; int ret; @@ -212,7 +217,7 @@ static int flow_limit_table_len_sysctl(struct ctl_table *table, int write, #ifdef CONFIG_NET_SCHED static int set_default_qdisc(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { char id[IFNAMSIZ]; struct ctl_table tbl = { @@ -231,7 +236,7 @@ static int set_default_qdisc(struct ctl_table *table, int write, #endif static int proc_do_dev_weight(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { static DEFINE_MUTEX(dev_weight_mutex); int ret, weight; @@ -249,7 +254,7 @@ static int proc_do_dev_weight(struct ctl_table *table, int write, } static int proc_do_rss_key(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ctl_table fake_table; char buf[NETDEV_RSS_KEY_LEN * 3]; @@ -262,7 +267,7 @@ static int proc_do_rss_key(struct ctl_table *table, int write, #ifdef CONFIG_BPF_JIT static int proc_dointvec_minmax_bpf_enable(struct ctl_table *table, int write, - void *buffer, size_t *lenp, + void __user *buffer, size_t *lenp, loff_t *ppos) { int ret, jit_enable = *(int *)table->data; @@ -289,7 +294,8 @@ static int proc_dointvec_minmax_bpf_enable(struct ctl_table *table, int write, # ifdef CONFIG_HAVE_EBPF_JIT static int proc_dointvec_minmax_bpf_restricted(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { if (!capable(CAP_SYS_ADMIN)) return -EPERM; @@ -300,7 +306,8 @@ proc_dointvec_minmax_bpf_restricted(struct ctl_table *table, int write, static int proc_dolongvec_minmax_bpf_restricted(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { if (!capable(CAP_SYS_ADMIN)) return -EPERM; diff --git a/net/core/utils.c b/net/core/utils.c index d010fcf1dc08..1f31a39236d5 100644 --- a/net/core/utils.c +++ b/net/core/utils.c @@ -473,11 +473,11 @@ void inet_proto_csum_replace16(__sum16 *sum, struct sk_buff *skb, EXPORT_SYMBOL(inet_proto_csum_replace16); void inet_proto_csum_replace_by_diff(__sum16 *sum, struct sk_buff *skb, - __wsum diff, bool pseudohdr, bool ipv6) + __wsum diff, bool pseudohdr) { if (skb->ip_summed != CHECKSUM_PARTIAL) { *sum = csum_fold(csum_add(diff, ~csum_unfold(*sum))); - if (skb->ip_summed == CHECKSUM_COMPLETE && pseudohdr && !ipv6) + if (skb->ip_summed == CHECKSUM_COMPLETE && pseudohdr) skb->csum = ~csum_add(diff, ~skb->csum); } else if (pseudohdr) { *sum = ~csum_fold(csum_add(diff, csum_unfold(*sum))); diff --git a/net/core/xdp.c b/net/core/xdp.c index 32c9915956ee..b3f463c6543f 100644 --- a/net/core/xdp.c +++ b/net/core/xdp.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include @@ -502,10 +501,3 @@ struct xdp_frame *xdp_convert_zc_to_xdp_frame(struct xdp_buff *xdp) return xdpf; } EXPORT_SYMBOL_GPL(xdp_convert_zc_to_xdp_frame); - -/* Used by XDP_WARN macro, to avoid inlining WARN() in fast-path */ -void xdp_warn(const char *msg, const char *func, const int line) -{ - WARN(1, "XDP_WARN: %s(line:%d): %s\n", func, line, msg); -}; -EXPORT_SYMBOL_GPL(xdp_warn); diff --git a/net/ipv4/Kconfig b/net/ipv4/Kconfig index a8acc22d3571..f5af8c6b2f87 100644 --- a/net/ipv4/Kconfig +++ b/net/ipv4/Kconfig @@ -180,8 +180,8 @@ config NET_IPIP config NET_IPGRE_DEMUX tristate "IP: GRE demultiplexer" help - This is helper module to demultiplex GRE packets on GRE version field criteria. - Required by ip_gre and pptp modules. + This is helper module to demultiplex GRE packets on GRE version field criteria. + Required by ip_gre and pptp modules. config NET_IP_TUNNEL tristate @@ -470,185 +470,185 @@ config TCP_CONG_BIC tristate "Binary Increase Congestion (BIC) control" default m ---help--- - BIC-TCP is a sender-side only change that ensures a linear RTT - fairness under large windows while offering both scalability and - bounded TCP-friendliness. The protocol combines two schemes - called additive increase and binary search increase. When the - congestion window is large, additive increase with a large - increment ensures linear RTT fairness as well as good - scalability. Under small congestion windows, binary search - increase provides TCP friendliness. - See http://www.csc.ncsu.edu/faculty/rhee/export/bitcp/ + BIC-TCP is a sender-side only change that ensures a linear RTT + fairness under large windows while offering both scalability and + bounded TCP-friendliness. The protocol combines two schemes + called additive increase and binary search increase. When the + congestion window is large, additive increase with a large + increment ensures linear RTT fairness as well as good + scalability. Under small congestion windows, binary search + increase provides TCP friendliness. + See http://www.csc.ncsu.edu/faculty/rhee/export/bitcp/ config TCP_CONG_CUBIC tristate "CUBIC TCP" default y ---help--- - This is version 2.0 of BIC-TCP which uses a cubic growth function - among other techniques. - See http://www.csc.ncsu.edu/faculty/rhee/export/bitcp/cubic-paper.pdf + This is version 2.0 of BIC-TCP which uses a cubic growth function + among other techniques. + See http://www.csc.ncsu.edu/faculty/rhee/export/bitcp/cubic-paper.pdf config TCP_CONG_WESTWOOD tristate "TCP Westwood+" default m ---help--- - TCP Westwood+ is a sender-side only modification of the TCP Reno - protocol stack that optimizes the performance of TCP congestion - control. It is based on end-to-end bandwidth estimation to set - congestion window and slow start threshold after a congestion - episode. Using this estimation, TCP Westwood+ adaptively sets a - slow start threshold and a congestion window which takes into - account the bandwidth used at the time congestion is experienced. - TCP Westwood+ significantly increases fairness wrt TCP Reno in - wired networks and throughput over wireless links. + TCP Westwood+ is a sender-side only modification of the TCP Reno + protocol stack that optimizes the performance of TCP congestion + control. It is based on end-to-end bandwidth estimation to set + congestion window and slow start threshold after a congestion + episode. Using this estimation, TCP Westwood+ adaptively sets a + slow start threshold and a congestion window which takes into + account the bandwidth used at the time congestion is experienced. + TCP Westwood+ significantly increases fairness wrt TCP Reno in + wired networks and throughput over wireless links. config TCP_CONG_HTCP tristate "H-TCP" default m ---help--- - H-TCP is a send-side only modifications of the TCP Reno - protocol stack that optimizes the performance of TCP - congestion control for high speed network links. It uses a - modeswitch to change the alpha and beta parameters of TCP Reno - based on network conditions and in a way so as to be fair with - other Reno and H-TCP flows. + H-TCP is a send-side only modifications of the TCP Reno + protocol stack that optimizes the performance of TCP + congestion control for high speed network links. It uses a + modeswitch to change the alpha and beta parameters of TCP Reno + based on network conditions and in a way so as to be fair with + other Reno and H-TCP flows. config TCP_CONG_HSTCP tristate "High Speed TCP" default n ---help--- - Sally Floyd's High Speed TCP (RFC 3649) congestion control. - A modification to TCP's congestion control mechanism for use - with large congestion windows. A table indicates how much to - increase the congestion window by when an ACK is received. - For more detail see http://www.icir.org/floyd/hstcp.html + Sally Floyd's High Speed TCP (RFC 3649) congestion control. + A modification to TCP's congestion control mechanism for use + with large congestion windows. A table indicates how much to + increase the congestion window by when an ACK is received. + For more detail see http://www.icir.org/floyd/hstcp.html config TCP_CONG_HYBLA tristate "TCP-Hybla congestion control algorithm" default n ---help--- - TCP-Hybla is a sender-side only change that eliminates penalization of - long-RTT, large-bandwidth connections, like when satellite legs are - involved, especially when sharing a common bottleneck with normal - terrestrial connections. + TCP-Hybla is a sender-side only change that eliminates penalization of + long-RTT, large-bandwidth connections, like when satellite legs are + involved, especially when sharing a common bottleneck with normal + terrestrial connections. config TCP_CONG_VEGAS tristate "TCP Vegas" default n ---help--- - TCP Vegas is a sender-side only change to TCP that anticipates - the onset of congestion by estimating the bandwidth. TCP Vegas - adjusts the sending rate by modifying the congestion - window. TCP Vegas should provide less packet loss, but it is - not as aggressive as TCP Reno. + TCP Vegas is a sender-side only change to TCP that anticipates + the onset of congestion by estimating the bandwidth. TCP Vegas + adjusts the sending rate by modifying the congestion + window. TCP Vegas should provide less packet loss, but it is + not as aggressive as TCP Reno. config TCP_CONG_NV - tristate "TCP NV" - default n - ---help--- - TCP NV is a follow up to TCP Vegas. It has been modified to deal with - 10G networks, measurement noise introduced by LRO, GRO and interrupt - coalescence. In addition, it will decrease its cwnd multiplicatively - instead of linearly. + tristate "TCP NV" + default n + ---help--- + TCP NV is a follow up to TCP Vegas. It has been modified to deal with + 10G networks, measurement noise introduced by LRO, GRO and interrupt + coalescence. In addition, it will decrease its cwnd multiplicatively + instead of linearly. - Note that in general congestion avoidance (cwnd decreased when # packets - queued grows) cannot coexist with congestion control (cwnd decreased only - when there is packet loss) due to fairness issues. One scenario when they - can coexist safely is when the CA flows have RTTs << CC flows RTTs. + Note that in general congestion avoidance (cwnd decreased when # packets + queued grows) cannot coexist with congestion control (cwnd decreased only + when there is packet loss) due to fairness issues. One scenario when they + can coexist safely is when the CA flows have RTTs << CC flows RTTs. - For further details see http://www.brakmo.org/networking/tcp-nv/ + For further details see http://www.brakmo.org/networking/tcp-nv/ config TCP_CONG_SCALABLE tristate "Scalable TCP" default n ---help--- - Scalable TCP is a sender-side only change to TCP which uses a - MIMD congestion control algorithm which has some nice scaling - properties, though is known to have fairness issues. - See http://www.deneholme.net/tom/scalable/ + Scalable TCP is a sender-side only change to TCP which uses a + MIMD congestion control algorithm which has some nice scaling + properties, though is known to have fairness issues. + See http://www.deneholme.net/tom/scalable/ config TCP_CONG_LP tristate "TCP Low Priority" default n ---help--- - TCP Low Priority (TCP-LP), a distributed algorithm whose goal is - to utilize only the excess network bandwidth as compared to the - ``fair share`` of bandwidth as targeted by TCP. - See http://www-ece.rice.edu/networks/TCP-LP/ + TCP Low Priority (TCP-LP), a distributed algorithm whose goal is + to utilize only the excess network bandwidth as compared to the + ``fair share`` of bandwidth as targeted by TCP. + See http://www-ece.rice.edu/networks/TCP-LP/ config TCP_CONG_VENO tristate "TCP Veno" default n ---help--- - TCP Veno is a sender-side only enhancement of TCP to obtain better - throughput over wireless networks. TCP Veno makes use of state - distinguishing to circumvent the difficult judgment of the packet loss - type. TCP Veno cuts down less congestion window in response to random - loss packets. - See + TCP Veno is a sender-side only enhancement of TCP to obtain better + throughput over wireless networks. TCP Veno makes use of state + distinguishing to circumvent the difficult judgment of the packet loss + type. TCP Veno cuts down less congestion window in response to random + loss packets. + See config TCP_CONG_YEAH tristate "YeAH TCP" select TCP_CONG_VEGAS default n ---help--- - YeAH-TCP is a sender-side high-speed enabled TCP congestion control - algorithm, which uses a mixed loss/delay approach to compute the - congestion window. It's design goals target high efficiency, - internal, RTT and Reno fairness, resilience to link loss while - keeping network elements load as low as possible. + YeAH-TCP is a sender-side high-speed enabled TCP congestion control + algorithm, which uses a mixed loss/delay approach to compute the + congestion window. It's design goals target high efficiency, + internal, RTT and Reno fairness, resilience to link loss while + keeping network elements load as low as possible. - For further details look here: - http://wil.cs.caltech.edu/pfldnet2007/paper/YeAH_TCP.pdf + For further details look here: + http://wil.cs.caltech.edu/pfldnet2007/paper/YeAH_TCP.pdf config TCP_CONG_ILLINOIS tristate "TCP Illinois" default n ---help--- - TCP-Illinois is a sender-side modification of TCP Reno for - high speed long delay links. It uses round-trip-time to - adjust the alpha and beta parameters to achieve a higher average - throughput and maintain fairness. + TCP-Illinois is a sender-side modification of TCP Reno for + high speed long delay links. It uses round-trip-time to + adjust the alpha and beta parameters to achieve a higher average + throughput and maintain fairness. - For further details see: - http://www.ews.uiuc.edu/~shaoliu/tcpillinois/index.html + For further details see: + http://www.ews.uiuc.edu/~shaoliu/tcpillinois/index.html config TCP_CONG_DCTCP tristate "DataCenter TCP (DCTCP)" default n ---help--- - DCTCP leverages Explicit Congestion Notification (ECN) in the network to - provide multi-bit feedback to the end hosts. It is designed to provide: + DCTCP leverages Explicit Congestion Notification (ECN) in the network to + provide multi-bit feedback to the end hosts. It is designed to provide: - - High burst tolerance (incast due to partition/aggregate), - - Low latency (short flows, queries), - - High throughput (continuous data updates, large file transfers) with - commodity, shallow-buffered switches. + - High burst tolerance (incast due to partition/aggregate), + - Low latency (short flows, queries), + - High throughput (continuous data updates, large file transfers) with + commodity, shallow-buffered switches. - All switches in the data center network running DCTCP must support - ECN marking and be configured for marking when reaching defined switch - buffer thresholds. The default ECN marking threshold heuristic for - DCTCP on switches is 20 packets (30KB) at 1Gbps, and 65 packets - (~100KB) at 10Gbps, but might need further careful tweaking. + All switches in the data center network running DCTCP must support + ECN marking and be configured for marking when reaching defined switch + buffer thresholds. The default ECN marking threshold heuristic for + DCTCP on switches is 20 packets (30KB) at 1Gbps, and 65 packets + (~100KB) at 10Gbps, but might need further careful tweaking. - For further details see: - http://simula.stanford.edu/~alizade/Site/DCTCP_files/dctcp-final.pdf + For further details see: + http://simula.stanford.edu/~alizade/Site/DCTCP_files/dctcp-final.pdf config TCP_CONG_CDG tristate "CAIA Delay-Gradient (CDG)" default n ---help--- - CAIA Delay-Gradient (CDG) is a TCP congestion control that modifies - the TCP sender in order to: + CAIA Delay-Gradient (CDG) is a TCP congestion control that modifies + the TCP sender in order to: o Use the delay gradient as a congestion signal. o Back off with an average probability that is independent of the RTT. o Coexist with flows that use loss-based congestion control. o Tolerate packet loss unrelated to congestion. - For further details see: - D.A. Hayes and G. Armitage. "Revisiting TCP congestion control using - delay gradients." In Networking 2011. Preprint: http://goo.gl/No3vdg + For further details see: + D.A. Hayes and G. Armitage. "Revisiting TCP congestion control using + delay gradients." In Networking 2011. Preprint: http://goo.gl/No3vdg config TCP_CONG_BBR tristate "BBR TCP" diff --git a/net/ipv4/Makefile b/net/ipv4/Makefile index bbdd9c44f14e..d57ecfaf89d4 100644 --- a/net/ipv4/Makefile +++ b/net/ipv4/Makefile @@ -14,7 +14,7 @@ obj-y := route.o inetpeer.o protocol.o \ udp_offload.o arp.o icmp.o devinet.o af_inet.o igmp.o \ fib_frontend.o fib_semantics.o fib_trie.o fib_notifier.o \ inet_fragment.o ping.o ip_tunnel_core.o gre_offload.o \ - metrics.o netlink.o nexthop.o udp_tunnel_stub.o + metrics.o netlink.o nexthop.o obj-$(CONFIG_BPFILTER) += bpfilter/ @@ -29,7 +29,6 @@ gre-y := gre_demux.o obj-$(CONFIG_NET_FOU) += fou.o obj-$(CONFIG_NET_IPGRE_DEMUX) += gre.o obj-$(CONFIG_NET_IPGRE) += ip_gre.o -udp_tunnel-y := udp_tunnel_core.o udp_tunnel_nic.o obj-$(CONFIG_NET_UDP_TUNNEL) += udp_tunnel.o obj-$(CONFIG_NET_IPVTI) += ip_vti.o obj-$(CONFIG_SYN_COOKIES) += syncookies.o @@ -62,12 +61,7 @@ obj-$(CONFIG_TCP_CONG_LP) += tcp_lp.o obj-$(CONFIG_TCP_CONG_YEAH) += tcp_yeah.o obj-$(CONFIG_TCP_CONG_ILLINOIS) += tcp_illinois.o obj-$(CONFIG_NET_SOCK_MSG) += tcp_bpf.o -obj-$(CONFIG_BPF_SYSCALL) += udp_bpf.o obj-$(CONFIG_NETLABEL) += cipso_ipv4.o obj-$(CONFIG_XFRM) += xfrm4_policy.o xfrm4_state.o xfrm4_input.o \ xfrm4_output.o xfrm4_protocol.o - -ifeq ($(CONFIG_BPF_JIT),y) -obj-$(CONFIG_BPF_SYSCALL) += bpf_tcp_ca.o -endif diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c index 6867cb572844..0d7f53a410e5 100644 --- a/net/ipv4/af_inet.c +++ b/net/ipv4/af_inet.c @@ -408,9 +408,6 @@ int inet_release(struct socket *sock) if (sk) { long timeout; - if (!sk->sk_kern_sock) - BPF_CGROUP_RUN_PROG_INET_SOCK_RELEASE(sk); - /* Applications forget to leave groups before exiting */ ip_mc_drop_socket(sk); @@ -451,12 +448,12 @@ int inet_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len) if (err) return err; - return __inet_bind(sk, uaddr, addr_len, BIND_WITH_LOCK); + return __inet_bind(sk, uaddr, addr_len, false, true); } EXPORT_SYMBOL(inet_bind); int __inet_bind(struct sock *sk, struct sockaddr *uaddr, int addr_len, - u32 flags) + bool force_bind_address_no_port, bool with_lock) { struct sockaddr_in *addr = (struct sockaddr_in *)uaddr; struct inet_sock *inet = inet_sk(sk); @@ -511,7 +508,7 @@ int __inet_bind(struct sock *sk, struct sockaddr *uaddr, int addr_len, * would be illegal to use them (multicast/broadcast) in * which case the sending device address is used. */ - if (flags & BIND_WITH_LOCK) + if (with_lock) lock_sock(sk); /* Check these errors (active socket, double bind). */ @@ -525,18 +522,16 @@ int __inet_bind(struct sock *sk, struct sockaddr *uaddr, int addr_len, /* Make sure we are allowed to bind here. */ if (snum || !(inet->bind_address_no_port || - (flags & BIND_FORCE_ADDRESS_NO_PORT))) { + force_bind_address_no_port)) { if (sk->sk_prot->get_port(sk, snum)) { inet->inet_saddr = inet->inet_rcv_saddr = 0; err = -EADDRINUSE; goto out_release_sock; } - if (!(flags & BIND_FROM_BPF)) { - err = BPF_CGROUP_RUN_PROG_INET4_POST_BIND(sk); - if (err) { - inet->inet_saddr = inet->inet_rcv_saddr = 0; - goto out_release_sock; - } + err = BPF_CGROUP_RUN_PROG_INET4_POST_BIND(sk); + if (err) { + inet->inet_saddr = inet->inet_rcv_saddr = 0; + goto out_release_sock; } } @@ -550,7 +545,7 @@ int __inet_bind(struct sock *sk, struct sockaddr *uaddr, int addr_len, sk_dst_reset(sk); err = 0; out_release_sock: - if (flags & BIND_WITH_LOCK) + if (with_lock) release_sock(sk); out: return err; @@ -768,11 +763,12 @@ do_err: } EXPORT_SYMBOL(inet_accept); + /* * This does both peername and sockname. */ int inet_getname(struct socket *sock, struct sockaddr *uaddr, - int peer) + int peer) { struct sock *sk = sock->sk; struct inet_sock *inet = inet_sk(sk); @@ -793,11 +789,6 @@ int inet_getname(struct socket *sock, struct sockaddr *uaddr, sin->sin_port = inet->inet_sport; sin->sin_addr.s_addr = addr; } - if (cgroup_bpf_enabled) - BPF_CGROUP_RUN_SA_PROG_LOCK(sk, (struct sockaddr *)sin, - peer ? BPF_CGROUP_INET4_GETPEERNAME : - BPF_CGROUP_INET4_GETSOCKNAME, - NULL); memset(sin->sin_zero, 0, sizeof(sin->sin_zero)); return sizeof(*sin); } diff --git a/net/ipv4/bpf_tcp_ca.c b/net/ipv4/bpf_tcp_ca.c deleted file mode 100644 index 618954f82764..000000000000 --- a/net/ipv4/bpf_tcp_ca.c +++ /dev/null @@ -1,254 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2019 Facebook */ - -#include -#include -#include -#include -#include -#include -#include - -static u32 optional_ops[] = { - offsetof(struct tcp_congestion_ops, init), - offsetof(struct tcp_congestion_ops, release), - offsetof(struct tcp_congestion_ops, set_state), - offsetof(struct tcp_congestion_ops, cwnd_event), - offsetof(struct tcp_congestion_ops, in_ack_event), - offsetof(struct tcp_congestion_ops, pkts_acked), - offsetof(struct tcp_congestion_ops, min_tso_segs), - offsetof(struct tcp_congestion_ops, sndbuf_expand), - offsetof(struct tcp_congestion_ops, cong_control), -}; - -static u32 unsupported_ops[] = { - offsetof(struct tcp_congestion_ops, get_info), -}; - -static const struct btf_type *tcp_sock_type; -static u32 tcp_sock_id, sock_id; - -static int bpf_tcp_ca_init(struct btf *btf) -{ - s32 type_id; - - type_id = btf_find_by_name_kind(btf, "sock", BTF_KIND_STRUCT); - if (type_id < 0) - return -EINVAL; - sock_id = type_id; - - type_id = btf_find_by_name_kind(btf, "tcp_sock", BTF_KIND_STRUCT); - if (type_id < 0) - return -EINVAL; - tcp_sock_id = type_id; - tcp_sock_type = btf_type_by_id(btf, tcp_sock_id); - - return 0; -} - -static bool is_optional(u32 member_offset) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(optional_ops); i++) { - if (member_offset == optional_ops[i]) - return true; - } - - return false; -} - -static bool is_unsupported(u32 member_offset) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(unsupported_ops); i++) { - if (member_offset == unsupported_ops[i]) - return true; - } - - return false; -} - -extern struct btf *btf_vmlinux; - -static bool bpf_tcp_ca_is_valid_access(int off, int size, - enum bpf_access_type type, - const struct bpf_prog *prog, - struct bpf_insn_access_aux *info) -{ - if (off < 0 || off >= sizeof(__u64) * MAX_BPF_FUNC_ARGS) - return false; - if (type != BPF_READ) - return false; - if (off % size != 0) - return false; - - if (!btf_ctx_access(off, size, type, prog, info)) - return false; - - if (info->reg_type == PTR_TO_BTF_ID && info->btf_id == sock_id) - /* promote it to tcp_sock */ - info->btf_id = tcp_sock_id; - - return true; -} - -static int bpf_tcp_ca_btf_struct_access(struct bpf_verifier_log *log, - const struct btf_type *t, int off, - int size, enum bpf_access_type atype, - u32 *next_btf_id) -{ - size_t end; - - if (atype == BPF_READ) - return btf_struct_access(log, t, off, size, atype, next_btf_id); - - if (t != tcp_sock_type) { - bpf_log(log, "only read is supported\n"); - return -EACCES; - } - - switch (off) { - case bpf_ctx_range(struct inet_connection_sock, icsk_ca_priv): - end = offsetofend(struct inet_connection_sock, icsk_ca_priv); - break; - case offsetof(struct inet_connection_sock, icsk_ack.pending): - end = offsetofend(struct inet_connection_sock, - icsk_ack.pending); - break; - case offsetof(struct tcp_sock, snd_cwnd): - end = offsetofend(struct tcp_sock, snd_cwnd); - break; - case offsetof(struct tcp_sock, snd_cwnd_cnt): - end = offsetofend(struct tcp_sock, snd_cwnd_cnt); - break; - case offsetof(struct tcp_sock, snd_ssthresh): - end = offsetofend(struct tcp_sock, snd_ssthresh); - break; - case offsetof(struct tcp_sock, ecn_flags): - end = offsetofend(struct tcp_sock, ecn_flags); - break; - default: - bpf_log(log, "no write support to tcp_sock at off %d\n", off); - return -EACCES; - } - - if (off + size > end) { - bpf_log(log, - "write access at off %d with size %d beyond the member of tcp_sock ended at %zu\n", - off, size, end); - return -EACCES; - } - - return NOT_INIT; -} - -BPF_CALL_2(bpf_tcp_send_ack, struct tcp_sock *, tp, u32, rcv_nxt) -{ - /* bpf_tcp_ca prog cannot have NULL tp */ - __tcp_send_ack((struct sock *)tp, rcv_nxt); - return 0; -} - -static const struct bpf_func_proto bpf_tcp_send_ack_proto = { - .func = bpf_tcp_send_ack, - .gpl_only = false, - /* In case we want to report error later */ - .ret_type = RET_INTEGER, - .arg1_type = ARG_PTR_TO_BTF_ID, - .arg1_btf_id = &tcp_sock_id, - .arg2_type = ARG_ANYTHING, -}; - -static const struct bpf_func_proto * -bpf_tcp_ca_get_func_proto(enum bpf_func_id func_id, - const struct bpf_prog *prog) -{ - switch (func_id) { - case BPF_FUNC_tcp_send_ack: - return &bpf_tcp_send_ack_proto; - case BPF_FUNC_sk_storage_get: - return &bpf_sk_storage_get_proto; - case BPF_FUNC_sk_storage_delete: - return &bpf_sk_storage_delete_proto; - default: - return bpf_base_func_proto(func_id); - } -} - -static const struct bpf_verifier_ops bpf_tcp_ca_verifier_ops = { - .get_func_proto = bpf_tcp_ca_get_func_proto, - .is_valid_access = bpf_tcp_ca_is_valid_access, - .btf_struct_access = bpf_tcp_ca_btf_struct_access, -}; - -static int bpf_tcp_ca_init_member(const struct btf_type *t, - const struct btf_member *member, - void *kdata, const void *udata) -{ - const struct tcp_congestion_ops *utcp_ca; - struct tcp_congestion_ops *tcp_ca; - int prog_fd; - u32 moff; - - utcp_ca = (const struct tcp_congestion_ops *)udata; - tcp_ca = (struct tcp_congestion_ops *)kdata; - - moff = btf_member_bit_offset(t, member) / 8; - switch (moff) { - case offsetof(struct tcp_congestion_ops, flags): - if (utcp_ca->flags & ~TCP_CONG_MASK) - return -EINVAL; - tcp_ca->flags = utcp_ca->flags; - return 1; - case offsetof(struct tcp_congestion_ops, name): - if (bpf_obj_name_cpy(tcp_ca->name, utcp_ca->name, - sizeof(tcp_ca->name)) <= 0) - return -EINVAL; - if (tcp_ca_find(utcp_ca->name)) - return -EEXIST; - return 1; - } - - if (!btf_type_resolve_func_ptr(btf_vmlinux, member->type, NULL)) - return 0; - - /* Ensure bpf_prog is provided for compulsory func ptr */ - prog_fd = (int)(*(unsigned long *)(udata + moff)); - if (!prog_fd && !is_optional(moff) && !is_unsupported(moff)) - return -EINVAL; - - return 0; -} - -static int bpf_tcp_ca_check_member(const struct btf_type *t, - const struct btf_member *member) -{ - if (is_unsupported(btf_member_bit_offset(t, member) / 8)) - return -ENOTSUPP; - return 0; -} - -static int bpf_tcp_ca_reg(void *kdata) -{ - return tcp_register_congestion_control(kdata); -} - -static void bpf_tcp_ca_unreg(void *kdata) -{ - tcp_unregister_congestion_control(kdata); -} - -/* Avoid sparse warning. It is only used in bpf_struct_ops.c. */ -extern struct bpf_struct_ops bpf_tcp_congestion_ops; - -struct bpf_struct_ops bpf_tcp_congestion_ops = { - .verifier_ops = &bpf_tcp_ca_verifier_ops, - .reg = bpf_tcp_ca_reg, - .unreg = bpf_tcp_ca_unreg, - .check_member = bpf_tcp_ca_check_member, - .init_member = bpf_tcp_ca_init_member, - .init = bpf_tcp_ca_init, - .name = "tcp_congestion_ops", -}; diff --git a/net/ipv4/bpfilter/sockopt.c b/net/ipv4/bpfilter/sockopt.c index 1b34cb9a7708..0480918bfc7c 100644 --- a/net/ipv4/bpfilter/sockopt.c +++ b/net/ipv4/bpfilter/sockopt.c @@ -12,16 +12,18 @@ struct bpfilter_umh_ops bpfilter_ops; EXPORT_SYMBOL_GPL(bpfilter_ops); -void bpfilter_umh_cleanup(struct umd_info *info) +static void bpfilter_umh_cleanup(struct umh_info *info) { + mutex_lock(&bpfilter_ops.lock); + bpfilter_ops.stop = true; fput(info->pipe_to_umh); fput(info->pipe_from_umh); - put_pid(info->tgid); - info->tgid = NULL; + info->pid = 0; + mutex_unlock(&bpfilter_ops.lock); } -EXPORT_SYMBOL_GPL(bpfilter_umh_cleanup); -static int bpfilter_mbox_request(struct sock *sk, int optname, sockptr_t optval, +static int bpfilter_mbox_request(struct sock *sk, int optname, + char __user *optval, unsigned int optlen, bool is_set) { int err; @@ -36,11 +38,7 @@ static int bpfilter_mbox_request(struct sock *sk, int optname, sockptr_t optval, goto out; } } - if (bpfilter_ops.info.tgid && - thread_group_exited(bpfilter_ops.info.tgid)) - bpfilter_umh_cleanup(&bpfilter_ops.info); - - if (!bpfilter_ops.info.tgid) { + if (bpfilter_ops.stop) { err = bpfilter_ops.start(); if (err) goto out; @@ -51,7 +49,7 @@ out: return err; } -int bpfilter_ip_set_sockopt(struct sock *sk, int optname, sockptr_t optval, +int bpfilter_ip_set_sockopt(struct sock *sk, int optname, char __user *optval, unsigned int optlen) { return bpfilter_mbox_request(sk, optname, optval, optlen, true); @@ -65,15 +63,15 @@ int bpfilter_ip_get_sockopt(struct sock *sk, int optname, char __user *optval, if (get_user(len, optlen)) return -EFAULT; - return bpfilter_mbox_request(sk, optname, USER_SOCKPTR(optval), len, - false); + return bpfilter_mbox_request(sk, optname, optval, len, false); } static int __init bpfilter_sockopt_init(void) { mutex_init(&bpfilter_ops.lock); - bpfilter_ops.info.tgid = NULL; - bpfilter_ops.info.driver_name = "bpfilter_umh"; + bpfilter_ops.stop = true; + bpfilter_ops.info.cmdline = "bpfilter_umh"; + bpfilter_ops.info.cleanup = &bpfilter_umh_cleanup; return 0; } diff --git a/net/ipv4/devinet.c b/net/ipv4/devinet.c index 80f59c9174f7..b4fb75be24d9 100644 --- a/net/ipv4/devinet.c +++ b/net/ipv4/devinet.c @@ -2393,7 +2393,8 @@ static int devinet_conf_ifindex(struct net *net, struct ipv4_devconf *cnf) } static int devinet_conf_proc(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { int old_value = *(int *)ctl->data; int ret = proc_dointvec(ctl, write, buffer, lenp, ppos); @@ -2445,7 +2446,8 @@ static int devinet_conf_proc(struct ctl_table *ctl, int write, } static int devinet_sysctl_forward(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { int *valp = ctl->data; int val = *valp; @@ -2488,7 +2490,8 @@ static int devinet_sysctl_forward(struct ctl_table *ctl, int write, } static int ipv4_doint_and_flush(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { int *valp = ctl->data; int val = *valp; diff --git a/net/ipv4/inet_hashtables.c b/net/ipv4/inet_hashtables.c index ee7aec46adb4..cd2cbf5c52a3 100644 --- a/net/ipv4/inet_hashtables.c +++ b/net/ipv4/inet_hashtables.c @@ -252,22 +252,6 @@ static inline int compute_score(struct sock *sk, struct net *net, return score; } -struct sock *inet_lookup_reuseport(struct net *net, struct sock *sk, - struct sk_buff *skb, int doff, - __be32 saddr, __be16 sport, - __be32 daddr, unsigned short hnum) -{ - struct sock *reuse_sk = NULL; - u32 phash; - - if (sk->sk_reuseport) { - phash = inet_ehashfn(net, daddr, hnum, saddr, sport); - reuse_sk = reuseport_select_sock(sk, phash, skb, doff); - } - return reuse_sk; -} -EXPORT_SYMBOL_GPL(inet_lookup_reuseport); - /* * Here are some nice properties to exploit here. The BSD API * does not allow a listening sock to specify the remote port nor the @@ -287,17 +271,21 @@ static struct sock *inet_lhash2_lookup(struct net *net, struct inet_connection_sock *icsk; struct sock *sk, *result = NULL; int score, hiscore = 0; + u32 phash = 0; inet_lhash2_for_each_icsk_rcu(icsk, &ilb2->head) { sk = (struct sock *)icsk; score = compute_score(sk, net, hnum, daddr, dif, sdif, exact_dif); if (score > hiscore) { - result = inet_lookup_reuseport(net, sk, skb, doff, - saddr, sport, daddr, hnum); - if (result) - return result; - + if (sk->sk_reuseport) { + phash = inet_ehashfn(net, daddr, hnum, + saddr, sport); + result = reuseport_select_sock(sk, phash, + skb, doff); + if (result) + return result; + } result = sk; hiscore = score; } @@ -306,29 +294,6 @@ static struct sock *inet_lhash2_lookup(struct net *net, return result; } -static inline struct sock *inet_lookup_run_bpf(struct net *net, - struct inet_hashinfo *hashinfo, - struct sk_buff *skb, int doff, - __be32 saddr, __be16 sport, - __be32 daddr, u16 hnum) -{ - struct sock *sk, *reuse_sk; - bool no_reuseport; - - if (hashinfo != &tcp_hashinfo) - return NULL; /* only TCP is supported */ - - no_reuseport = bpf_sk_lookup_run_v4(net, IPPROTO_TCP, - saddr, sport, daddr, hnum, &sk); - if (no_reuseport || IS_ERR_OR_NULL(sk)) - return sk; - - reuse_sk = inet_lookup_reuseport(net, sk, skb, doff, saddr, sport, daddr, hnum); - if (reuse_sk) - sk = reuse_sk; - return sk; -} - struct sock *__inet_lookup_listener(struct net *net, struct inet_hashinfo *hashinfo, struct sk_buff *skb, int doff, @@ -340,14 +305,6 @@ struct sock *__inet_lookup_listener(struct net *net, struct sock *result = NULL; unsigned int hash2; - /* Lookup redirect from BPF */ - if (static_branch_unlikely(&bpf_sk_lookup_enabled)) { - result = inet_lookup_run_bpf(net, hashinfo, skb, doff, - saddr, sport, daddr, hnum); - if (result) - goto done; - } - hash2 = ipv4_portaddr_hash(net, daddr, hnum); ilb2 = inet_lhash2_bucket(hashinfo, hash2); diff --git a/net/ipv4/ip_gre.c b/net/ipv4/ip_gre.c index a324980bade6..09e9e46259f7 100644 --- a/net/ipv4/ip_gre.c +++ b/net/ipv4/ip_gre.c @@ -782,37 +782,45 @@ static void ipgre_link_update(struct net_device *dev, bool set_mtu) } } -static int ipgre_tunnel_ctl(struct net_device *dev, struct ip_tunnel_parm *p, - int cmd) +static int ipgre_tunnel_ioctl(struct net_device *dev, + struct ifreq *ifr, int cmd) { + struct ip_tunnel_parm p; int err; + if (copy_from_user(&p, ifr->ifr_ifru.ifru_data, sizeof(p))) + return -EFAULT; + if (cmd == SIOCADDTUNNEL || cmd == SIOCCHGTUNNEL) { - if (p->iph.version != 4 || p->iph.protocol != IPPROTO_GRE || - p->iph.ihl != 5 || (p->iph.frag_off & htons(~IP_DF)) || - ((p->i_flags | p->o_flags) & (GRE_VERSION | GRE_ROUTING))) + if (p.iph.version != 4 || p.iph.protocol != IPPROTO_GRE || + p.iph.ihl != 5 || (p.iph.frag_off & htons(~IP_DF)) || + ((p.i_flags | p.o_flags) & (GRE_VERSION | GRE_ROUTING))) return -EINVAL; } - p->i_flags = gre_flags_to_tnl_flags(p->i_flags); - p->o_flags = gre_flags_to_tnl_flags(p->o_flags); + p.i_flags = gre_flags_to_tnl_flags(p.i_flags); + p.o_flags = gre_flags_to_tnl_flags(p.o_flags); - err = ip_tunnel_ctl(dev, p, cmd); + err = ip_tunnel_ioctl(dev, &p, cmd); if (err) return err; if (cmd == SIOCCHGTUNNEL) { struct ip_tunnel *t = netdev_priv(dev); - t->parms.i_flags = p->i_flags; - t->parms.o_flags = p->o_flags; + t->parms.i_flags = p.i_flags; + t->parms.o_flags = p.o_flags; if (strcmp(dev->rtnl_link_ops->kind, "erspan")) ipgre_link_update(dev, true); } - p->i_flags = gre_tnl_flags_to_gre_flags(p->i_flags); - p->o_flags = gre_tnl_flags_to_gre_flags(p->o_flags); + p.i_flags = gre_tnl_flags_to_gre_flags(p.i_flags); + p.o_flags = gre_tnl_flags_to_gre_flags(p.o_flags); + + if (copy_to_user(ifr->ifr_ifru.ifru_data, &p, sizeof(p))) + return -EFAULT; + return 0; } @@ -930,11 +938,10 @@ static const struct net_device_ops ipgre_netdev_ops = { .ndo_stop = ipgre_close, #endif .ndo_start_xmit = ipgre_xmit, - .ndo_do_ioctl = ip_tunnel_ioctl, + .ndo_do_ioctl = ipgre_tunnel_ioctl, .ndo_change_mtu = ip_tunnel_change_mtu, .ndo_get_stats64 = ip_tunnel_get_stats64, .ndo_get_iflink = ip_tunnel_get_iflink, - .ndo_tunnel_ctl = ipgre_tunnel_ctl, }; #define GRE_FEATURES (NETIF_F_SG | \ diff --git a/net/ipv4/ip_input.c b/net/ipv4/ip_input.c index 001a35dbc3d8..1464e2738211 100644 --- a/net/ipv4/ip_input.c +++ b/net/ipv4/ip_input.c @@ -501,8 +501,7 @@ static struct sk_buff *ip_rcv_core(struct sk_buff *skb, struct net *net) IPCB(skb)->iif = skb->skb_iif; /* Must drop socket now because of tproxy. */ - if (!skb_sk_is_prefetched(skb)) - skb_orphan(skb); + skb_orphan(skb); return skb; diff --git a/net/ipv4/ip_sockglue.c b/net/ipv4/ip_sockglue.c index 650ccd695fbf..0c528f642eb8 100644 --- a/net/ipv4/ip_sockglue.c +++ b/net/ipv4/ip_sockglue.c @@ -1256,8 +1256,7 @@ int ip_setsockopt(struct sock *sk, int level, #if IS_ENABLED(CONFIG_BPFILTER_UMH) if (optname >= BPFILTER_IPT_SO_SET_REPLACE && optname < BPFILTER_IPT_SET_MAX) - err = bpfilter_ip_set_sockopt(sk, optname, USER_SOCKPTR(optval), - optlen); + err = bpfilter_ip_set_sockopt(sk, optname, optval, optlen); #endif #ifdef CONFIG_NETFILTER /* we need to exclude all possible ENOPROTOOPTs except default case */ diff --git a/net/ipv4/ip_tunnel.c b/net/ipv4/ip_tunnel.c index b9899fc92c75..ba1decf81fe3 100644 --- a/net/ipv4/ip_tunnel.c +++ b/net/ipv4/ip_tunnel.c @@ -547,6 +547,20 @@ static int tnl_update_pmtu(struct net_device *dev, struct sk_buff *skb, return 0; } +static void ip_tunnel_adj_headroom(struct net_device *dev, unsigned int headroom) +{ + /* we must cap headroom to some upperlimit, else pskb_expand_head + * will overflow header offsets in skb_headers_offset_update(). + */ + static const unsigned int max_allowed = 512; + + if (headroom > max_allowed) + headroom = max_allowed; + + if (headroom > READ_ONCE(dev->needed_headroom)) + WRITE_ONCE(dev->needed_headroom, headroom); +} + void ip_md_tunnel_xmit(struct sk_buff *skb, struct net_device *dev, u8 proto, int tunnel_hlen) { @@ -863,7 +877,7 @@ static void ip_tunnel_update(struct ip_tunnel_net *itn, netdev_state_change(dev); } -int ip_tunnel_ctl(struct net_device *dev, struct ip_tunnel_parm *p, int cmd) +int ip_tunnel_ioctl(struct net_device *dev, struct ip_tunnel_parm *p, int cmd) { int err = 0; struct ip_tunnel *t = netdev_priv(dev); @@ -963,20 +977,6 @@ int ip_tunnel_ctl(struct net_device *dev, struct ip_tunnel_parm *p, int cmd) done: return err; } -EXPORT_SYMBOL_GPL(ip_tunnel_ctl); - -int ip_tunnel_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -{ - struct ip_tunnel_parm p; - int err; - - if (copy_from_user(&p, ifr->ifr_ifru.ifru_data, sizeof(p))) - return -EFAULT; - err = dev->netdev_ops->ndo_tunnel_ctl(dev, &p, cmd); - if (!err && copy_to_user(ifr->ifr_ifru.ifru_data, &p, sizeof(p))) - return -EFAULT; - return err; -} EXPORT_SYMBOL_GPL(ip_tunnel_ioctl); int __ip_tunnel_change_mtu(struct net_device *dev, int new_mtu, bool strict) diff --git a/net/ipv4/ip_vti.c b/net/ipv4/ip_vti.c index 29016c40556f..275f2ecf0ba6 100644 --- a/net/ipv4/ip_vti.c +++ b/net/ipv4/ip_vti.c @@ -399,31 +399,38 @@ static int vti4_err(struct sk_buff *skb, u32 info) } static int -vti_tunnel_ctl(struct net_device *dev, struct ip_tunnel_parm *p, int cmd) +vti_tunnel_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) { int err = 0; + struct ip_tunnel_parm p; + + if (copy_from_user(&p, ifr->ifr_ifru.ifru_data, sizeof(p))) + return -EFAULT; if (cmd == SIOCADDTUNNEL || cmd == SIOCCHGTUNNEL) { - if (p->iph.version != 4 || p->iph.protocol != IPPROTO_IPIP || - p->iph.ihl != 5) + if (p.iph.version != 4 || p.iph.protocol != IPPROTO_IPIP || + p.iph.ihl != 5) return -EINVAL; } - if (!(p->i_flags & GRE_KEY)) - p->i_key = 0; - if (!(p->o_flags & GRE_KEY)) - p->o_key = 0; + if (!(p.i_flags & GRE_KEY)) + p.i_key = 0; + if (!(p.o_flags & GRE_KEY)) + p.o_key = 0; - p->i_flags = VTI_ISVTI; + p.i_flags = VTI_ISVTI; - err = ip_tunnel_ctl(dev, p, cmd); + err = ip_tunnel_ioctl(dev, &p, cmd); if (err) return err; if (cmd != SIOCDELTUNNEL) { - p->i_flags |= GRE_KEY; - p->o_flags |= GRE_KEY; + p.i_flags |= GRE_KEY; + p.o_flags |= GRE_KEY; } + + if (copy_to_user(ifr->ifr_ifru.ifru_data, &p, sizeof(p))) + return -EFAULT; return 0; } @@ -431,11 +438,10 @@ static const struct net_device_ops vti_netdev_ops = { .ndo_init = vti_tunnel_init, .ndo_uninit = ip_tunnel_uninit, .ndo_start_xmit = vti_tunnel_xmit, - .ndo_do_ioctl = ip_tunnel_ioctl, + .ndo_do_ioctl = vti_tunnel_ioctl, .ndo_change_mtu = ip_tunnel_change_mtu, .ndo_get_stats64 = ip_tunnel_get_stats64, .ndo_get_iflink = ip_tunnel_get_iflink, - .ndo_tunnel_ctl = vti_tunnel_ctl, }; static void vti_tunnel_setup(struct net_device *dev) diff --git a/net/ipv4/ipip.c b/net/ipv4/ipip.c index 40fea52c8277..678575adaf3b 100644 --- a/net/ipv4/ipip.c +++ b/net/ipv4/ipip.c @@ -327,29 +327,41 @@ static bool ipip_tunnel_ioctl_verify_protocol(u8 ipproto) } static int -ipip_tunnel_ctl(struct net_device *dev, struct ip_tunnel_parm *p, int cmd) +ipip_tunnel_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) { + int err = 0; + struct ip_tunnel_parm p; + + if (copy_from_user(&p, ifr->ifr_ifru.ifru_data, sizeof(p))) + return -EFAULT; + if (cmd == SIOCADDTUNNEL || cmd == SIOCCHGTUNNEL) { - if (p->iph.version != 4 || - !ipip_tunnel_ioctl_verify_protocol(p->iph.protocol) || - p->iph.ihl != 5 || (p->iph.frag_off & htons(~IP_DF))) + if (p.iph.version != 4 || + !ipip_tunnel_ioctl_verify_protocol(p.iph.protocol) || + p.iph.ihl != 5 || (p.iph.frag_off&htons(~IP_DF))) return -EINVAL; } - p->i_key = p->o_key = 0; - p->i_flags = p->o_flags = 0; - return ip_tunnel_ctl(dev, p, cmd); + p.i_key = p.o_key = 0; + p.i_flags = p.o_flags = 0; + err = ip_tunnel_ioctl(dev, &p, cmd); + if (err) + return err; + + if (copy_to_user(ifr->ifr_ifru.ifru_data, &p, sizeof(p))) + return -EFAULT; + + return 0; } static const struct net_device_ops ipip_netdev_ops = { .ndo_init = ipip_tunnel_init, .ndo_uninit = ip_tunnel_uninit, .ndo_start_xmit = ipip_tunnel_xmit, - .ndo_do_ioctl = ip_tunnel_ioctl, + .ndo_do_ioctl = ipip_tunnel_ioctl, .ndo_change_mtu = ip_tunnel_change_mtu, .ndo_get_stats64 = ip_tunnel_get_stats64, .ndo_get_iflink = ip_tunnel_get_iflink, - .ndo_tunnel_ctl = ipip_tunnel_ctl, }; #define IPIP_FEATURES (NETIF_F_SG | \ diff --git a/net/ipv4/netfilter/ipt_NATTYPE.c b/net/ipv4/netfilter/ipt_NATTYPE.c index 484c0c111e4a..fae7cad3f89f 100644 --- a/net/ipv4/netfilter/ipt_NATTYPE.c +++ b/net/ipv4/netfilter/ipt_NATTYPE.c @@ -53,8 +53,8 @@ static void nattype_nte_debug_print(const struct ipt_nattype *nte, &nte->range.min_addr.ip, ntohs(nte->range.min_proto.all), ntohs(nte->nat_port), &nte->dest_addr, ntohs(nte->dest_port)); - DEBUGP("Timeout[%lx], Expires[%lx], Current[%lx]\n", nte->timeout_value, - nte->timeout.expires, jiffies); + DEBUGP("Timeout[%lx], Expires[%lx]\n", nte->timeout_value, + nte->timeout.expires); } /* netfilter NATTYPE nattype_free() @@ -80,9 +80,8 @@ bool nattype_refresh_timer_impl(unsigned long nat_type, spin_unlock_bh(&nattype_lock); return false; } - DEBUGP("%s: timeout_value=%lx, jiffies=%lx", __func__, timeout_value, jiffies); if (del_timer(&nte->timeout)) { - nte->timeout.expires = timeout_value + jiffies - nfct_time_stamp; + nte->timeout.expires = timeout_value; add_timer(&nte->timeout); spin_unlock_bh(&nattype_lock); nattype_nte_debug_print(nte, "refresh"); @@ -294,7 +293,7 @@ static unsigned int nattype_nat(struct sk_buff *skb, * found the entry. */ if (!nattype_refresh_timer((unsigned long)nte, - nfct_time_stamp + nte->timeout_value)) + jiffies + nte->timeout_value)) break; /* netfilter @@ -327,7 +326,6 @@ static unsigned int nattype_forward(struct sk_buff *skb, const struct ipt_nattype_info *info = par->targinfo; u16 nat_port; enum ip_conntrack_dir dir; - unsigned long timeout_value; if (xt_hooknum(par) != NF_INET_POST_ROUTING) return XT_CONTINUE; @@ -360,7 +358,7 @@ static unsigned int nattype_forward(struct sk_buff *skb, * found the entry. */ if (!nattype_refresh_timer((unsigned long)nte, - ct->timeout)) + ct->timeout)) break; /* netfilter NATTYPE @@ -433,8 +431,7 @@ static unsigned int nattype_forward(struct sk_buff *skb, * entry as this one is timed out and will be removed * from the list shortly. */ - timeout_value = nfct_time_stamp + nte2->timeout_value; - if (!nattype_refresh_timer((unsigned long)nte2, timeout_value)) + if (!nattype_refresh_timer((unsigned long)nte2, jiffies + nte2->timeout_value)) break; /* netfilter NATTYPE diff --git a/net/ipv4/nexthop.c b/net/ipv4/nexthop.c index 73bcb2732153..28f31c07f06b 100644 --- a/net/ipv4/nexthop.c +++ b/net/ipv4/nexthop.c @@ -760,12 +760,6 @@ static void remove_nexthop_from_groups(struct net *net, struct nexthop *nh, { struct nh_grp_entry *nhge, *tmp; - /* If there is nothing to do, let's avoid the costly call to - * synchronize_net() - */ - if (list_empty(&nh->grp_list)) - return; - list_for_each_entry_safe(nhge, tmp, &nh->grp_list, nh_list) remove_nh_grp_entry(net, nhge, nlinfo); diff --git a/net/ipv4/route.c b/net/ipv4/route.c index c56db00c6096..ffdaece8d156 100644 --- a/net/ipv4/route.c +++ b/net/ipv4/route.c @@ -637,11 +637,6 @@ static void fnhe_remove_oldest(struct fnhe_hash_bucket *hash) oldest_p = fnhe_p; } } - - /* Clear oldest->fnhe_daddr to prevent this fnhe from being - * rebound with new dsts in rt_bind_exception(). - */ - oldest->fnhe_daddr = 0; fnhe_flush_routes(oldest); *oldest_p = oldest->fnhe_next; kfree_rcu(oldest, rcu); @@ -3267,7 +3262,8 @@ static int ip_rt_gc_elasticity __read_mostly = 8; static int ip_min_valid_pmtu __read_mostly = IPV4_MIN_MTU; static int ipv4_sysctl_rtcache_flush(struct ctl_table *__ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { struct net *net = (struct net *)__ctl->extra1; diff --git a/net/ipv4/sysctl_net_ipv4.c b/net/ipv4/sysctl_net_ipv4.c index 7af47031cc2d..092a18299c66 100644 --- a/net/ipv4/sysctl_net_ipv4.c +++ b/net/ipv4/sysctl_net_ipv4.c @@ -75,7 +75,8 @@ static void set_local_port_range(struct net *net, int range[2]) /* Validate changes from /proc interface. */ static int ipv4_local_port_range(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { struct net *net = container_of(table->data, struct net, ipv4.ip_local_ports.range); @@ -110,7 +111,7 @@ static int ipv4_local_port_range(struct ctl_table *table, int write, /* Validate changes from /proc interface. */ static int ipv4_privileged_ports(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct net *net = container_of(table->data, struct net, ipv4.sysctl_ip_prot_sock); @@ -171,7 +172,8 @@ static void set_ping_group_range(struct ctl_table *table, kgid_t low, kgid_t hig /* Validate changes from /proc interface. */ static int ipv4_ping_group_range(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { struct user_namespace *user_ns = current_user_ns(); int ret; @@ -206,7 +208,8 @@ static int ipv4_ping_group_range(struct ctl_table *table, int write, } static int ipv4_fwd_update_priority(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { struct net *net; int ret; @@ -222,7 +225,7 @@ static int ipv4_fwd_update_priority(struct ctl_table *table, int write, } static int proc_tcp_congestion_control(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct net *net = container_of(ctl->data, struct net, ipv4.tcp_congestion_control); @@ -242,8 +245,9 @@ static int proc_tcp_congestion_control(struct ctl_table *ctl, int write, } static int proc_tcp_available_congestion_control(struct ctl_table *ctl, - int write, void *buffer, - size_t *lenp, loff_t *ppos) + int write, + void __user *buffer, size_t *lenp, + loff_t *ppos) { struct ctl_table tbl = { .maxlen = TCP_CA_BUF_MAX, }; int ret; @@ -258,8 +262,9 @@ static int proc_tcp_available_congestion_control(struct ctl_table *ctl, } static int proc_allowed_congestion_control(struct ctl_table *ctl, - int write, void *buffer, - size_t *lenp, loff_t *ppos) + int write, + void __user *buffer, size_t *lenp, + loff_t *ppos) { struct ctl_table tbl = { .maxlen = TCP_CA_BUF_MAX }; int ret; @@ -295,7 +300,8 @@ static int sscanf_key(char *buf, __le32 *key) } static int proc_tcp_fastopen_key(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { struct net *net = container_of(table->data, struct net, ipv4.sysctl_tcp_fastopen); @@ -362,7 +368,8 @@ bad_key: } static int proc_tfo_blackhole_detect_timeout(struct ctl_table *table, - int write, void *buffer, + int write, + void __user *buffer, size_t *lenp, loff_t *ppos) { struct net *net = container_of(table->data, struct net, @@ -377,7 +384,8 @@ static int proc_tfo_blackhole_detect_timeout(struct ctl_table *table, } static int proc_tcp_available_ulp(struct ctl_table *ctl, - int write, void *buffer, size_t *lenp, + int write, + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ctl_table tbl = { .maxlen = TCP_ULP_BUF_MAX, }; @@ -395,7 +403,7 @@ static int proc_tcp_available_ulp(struct ctl_table *ctl, #ifdef CONFIG_IP_ROUTE_MULTIPATH static int proc_fib_multipath_hash_policy(struct ctl_table *table, int write, - void *buffer, size_t *lenp, + void __user *buffer, size_t *lenp, loff_t *ppos) { struct net *net = container_of(table->data, struct net, diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index e3a92c76776d..1f8afb922614 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -422,8 +422,6 @@ void tcp_init_sock(struct sock *sk) INIT_LIST_HEAD(&tp->tsorted_sent_queue); icsk->icsk_rto = TCP_TIMEOUT_INIT; - icsk->icsk_rto_min = TCP_RTO_MIN; - icsk->icsk_delack_max = TCP_DELACK_MAX; tp->mdev_us = jiffies_to_usecs(TCP_TIMEOUT_INIT); minmax_reset(&tp->rtt_min, tcp_jiffies32, ~0U); @@ -2369,8 +2367,8 @@ bool tcp_check_oom(struct sock *sk, int shift) void __tcp_close(struct sock *sk, long timeout) { - bool data_was_unread = false; struct sk_buff *skb; + int data_was_unread = 0; int state; WRITE_ONCE(sk->sk_shutdown, SHUTDOWN_MASK); @@ -2389,12 +2387,11 @@ void __tcp_close(struct sock *sk, long timeout) * reader process may not have drained the data yet! */ while ((skb = __skb_dequeue(&sk->sk_receive_queue)) != NULL) { - u32 end_seq = TCP_SKB_CB(skb)->end_seq; + u32 len = TCP_SKB_CB(skb)->end_seq - TCP_SKB_CB(skb)->seq; if (TCP_SKB_CB(skb)->tcp_flags & TCPHDR_FIN) - end_seq--; - if (after(end_seq, tcp_sk(sk)->copied_seq)) - data_was_unread = true; + len--; + data_was_unread += len; __kfree_skb(skb); } @@ -2658,8 +2655,6 @@ int tcp_disconnect(struct sock *sk, int flags) icsk->icsk_probes_out = 0; icsk->icsk_probes_tstamp = 0; icsk->icsk_rto = TCP_TIMEOUT_INIT; - icsk->icsk_rto_min = TCP_RTO_MIN; - icsk->icsk_delack_max = TCP_DELACK_MAX; tp->snd_ssthresh = TCP_INFINITE_SSTHRESH; tp->snd_cwnd = TCP_INIT_CWND; tp->snd_cwnd_cnt = 0; @@ -2841,39 +2836,6 @@ static void tcp_enable_tx_delay(void) } } -int tcp_sock_set_keepidle_locked(struct sock *sk, int val) -{ - struct tcp_sock *tp = tcp_sk(sk); - - if (val < 1 || val > MAX_TCP_KEEPIDLE) - return -EINVAL; - - tp->keepalive_time = val * HZ; - if (sock_flag(sk, SOCK_KEEPOPEN) && - !((1 << sk->sk_state) & (TCPF_CLOSE | TCPF_LISTEN))) { - u32 elapsed = keepalive_time_elapsed(tp); - - if (tp->keepalive_time > elapsed) - elapsed = tp->keepalive_time - elapsed; - else - elapsed = 0; - inet_csk_reset_keepalive_timer(sk, elapsed); - } - - return 0; -} - -int tcp_sock_set_keepidle(struct sock *sk, int val) -{ - int err; - - lock_sock(sk); - err = tcp_sock_set_keepidle_locked(sk, val); - release_sock(sk); - return err; -} -EXPORT_SYMBOL(tcp_sock_set_keepidle); - /* * Socket option code for TCP. */ @@ -2901,7 +2863,7 @@ static int do_tcp_setsockopt(struct sock *sk, int level, name[val] = 0; lock_sock(sk); - err = tcp_set_congestion_control(sk, name, true, + err = tcp_set_congestion_control(sk, name, true, true, ns_capable(sock_net(sk)->user_ns, CAP_NET_ADMIN)); release_sock(sk); @@ -3081,7 +3043,21 @@ static int do_tcp_setsockopt(struct sock *sk, int level, break; case TCP_KEEPIDLE: - err = tcp_sock_set_keepidle_locked(sk, val); + if (val < 1 || val > MAX_TCP_KEEPIDLE) + err = -EINVAL; + else { + tp->keepalive_time = val * HZ; + if (sock_flag(sk, SOCK_KEEPOPEN) && + !((1 << sk->sk_state) & + (TCPF_CLOSE | TCPF_LISTEN))) { + u32 elapsed = keepalive_time_elapsed(tp); + if (tp->keepalive_time > elapsed) + elapsed = tp->keepalive_time - elapsed; + else + elapsed = 0; + inet_csk_reset_keepalive_timer(sk, elapsed); + } + } break; case TCP_KEEPINTVL: if (val < 1 || val > MAX_TCP_KEEPINTVL) @@ -3103,8 +3079,7 @@ static int do_tcp_setsockopt(struct sock *sk, int level, break; case TCP_SAVE_SYN: - /* 0: disable, 1: enable, 2: start from ether_header */ - if (val < 0 || val > 2) + if (val < 0 || val > 1) err = -EINVAL; else tp->save_syn = val; @@ -3704,21 +3679,20 @@ static int do_tcp_getsockopt(struct sock *sk, int level, lock_sock(sk); if (tp->saved_syn) { - if (len < tcp_saved_syn_len(tp->saved_syn)) { - if (put_user(tcp_saved_syn_len(tp->saved_syn), - optlen)) { + if (len < tp->saved_syn[0]) { + if (put_user(tp->saved_syn[0], optlen)) { release_sock(sk); return -EFAULT; } release_sock(sk); return -EINVAL; } - len = tcp_saved_syn_len(tp->saved_syn); + len = tp->saved_syn[0]; if (put_user(len, optlen)) { release_sock(sk); return -EFAULT; } - if (copy_to_user(optval, tp->saved_syn->data, len)) { + if (copy_to_user(optval, tp->saved_syn + 1, len)) { release_sock(sk); return -EFAULT; } diff --git a/net/ipv4/tcp_bpf.c b/net/ipv4/tcp_bpf.c index e5a72106d292..df0b9edd4e87 100644 --- a/net/ipv4/tcp_bpf.c +++ b/net/ipv4/tcp_bpf.c @@ -10,6 +10,38 @@ #include #include +static bool tcp_bpf_stream_read(const struct sock *sk) +{ + struct sk_psock *psock; + bool empty = true; + + rcu_read_lock(); + psock = sk_psock(sk); + if (likely(psock)) + empty = list_empty(&psock->ingress_msg); + rcu_read_unlock(); + return !empty; +} + +static int tcp_bpf_wait_data(struct sock *sk, struct sk_psock *psock, + int flags, long timeo, int *err) +{ + DEFINE_WAIT_FUNC(wait, woken_wake_function); + int ret = 0; + + if (!timeo) + return ret; + + add_wait_queue(sk_sleep(sk), &wait); + sk_set_bit(SOCKWQ_ASYNC_WAITDATA, sk); + ret = sk_wait_event(sk, &timeo, + !list_empty(&psock->ingress_msg) || + !skb_queue_empty(&sk->sk_receive_queue), &wait); + sk_clear_bit(SOCKWQ_ASYNC_WAITDATA, sk); + remove_wait_queue(sk_sleep(sk), &wait); + return ret; +} + int __tcp_bpf_recvmsg(struct sock *sk, struct sk_psock *psock, struct msghdr *msg, int len, int flags) { @@ -90,6 +122,52 @@ int __tcp_bpf_recvmsg(struct sock *sk, struct sk_psock *psock, } EXPORT_SYMBOL_GPL(__tcp_bpf_recvmsg); +int tcp_bpf_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, + int nonblock, int flags, int *addr_len) +{ + struct sk_psock *psock; + int copied, ret; + + if (unlikely(flags & MSG_ERRQUEUE)) + return inet_recv_error(sk, msg, len, addr_len); + + psock = sk_psock_get(sk); + if (unlikely(!psock)) + return tcp_recvmsg(sk, msg, len, nonblock, flags, addr_len); + if (!skb_queue_empty(&sk->sk_receive_queue) && + sk_psock_queue_empty(psock)) { + sk_psock_put(sk, psock); + return tcp_recvmsg(sk, msg, len, nonblock, flags, addr_len); + } + lock_sock(sk); +msg_bytes_ready: + copied = __tcp_bpf_recvmsg(sk, psock, msg, len, flags); + if (!copied) { + int data, err = 0; + long timeo; + + timeo = sock_rcvtimeo(sk, nonblock); + data = tcp_bpf_wait_data(sk, psock, flags, timeo, &err); + if (data) { + if (!sk_psock_queue_empty(psock)) + goto msg_bytes_ready; + release_sock(sk); + sk_psock_put(sk, psock); + return tcp_recvmsg(sk, msg, len, nonblock, flags, addr_len); + } + if (err) { + ret = err; + goto out; + } + copied = -EAGAIN; + } + ret = copied; +out: + release_sock(sk); + sk_psock_put(sk, psock); + return ret; +} + static int bpf_tcp_ingress(struct sock *sk, struct sk_psock *psock, struct sk_msg *msg, u32 apply_bytes, int flags) { @@ -231,85 +309,6 @@ int tcp_bpf_sendmsg_redir(struct sock *sk, struct sk_msg *msg, } EXPORT_SYMBOL_GPL(tcp_bpf_sendmsg_redir); -#ifdef CONFIG_BPF_SYSCALL -static bool tcp_bpf_stream_read(const struct sock *sk) -{ - struct sk_psock *psock; - bool empty = true; - - rcu_read_lock(); - psock = sk_psock(sk); - if (likely(psock)) - empty = list_empty(&psock->ingress_msg); - rcu_read_unlock(); - return !empty; -} - -static int tcp_bpf_wait_data(struct sock *sk, struct sk_psock *psock, - int flags, long timeo, int *err) -{ - DEFINE_WAIT_FUNC(wait, woken_wake_function); - int ret = 0; - - if (!timeo) - return ret; - - add_wait_queue(sk_sleep(sk), &wait); - sk_set_bit(SOCKWQ_ASYNC_WAITDATA, sk); - ret = sk_wait_event(sk, &timeo, - !list_empty(&psock->ingress_msg) || - !skb_queue_empty(&sk->sk_receive_queue), &wait); - sk_clear_bit(SOCKWQ_ASYNC_WAITDATA, sk); - remove_wait_queue(sk_sleep(sk), &wait); - return ret; -} - -static int tcp_bpf_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, - int nonblock, int flags, int *addr_len) -{ - struct sk_psock *psock; - int copied, ret; - - if (unlikely(flags & MSG_ERRQUEUE)) - return inet_recv_error(sk, msg, len, addr_len); - - psock = sk_psock_get(sk); - if (unlikely(!psock)) - return tcp_recvmsg(sk, msg, len, nonblock, flags, addr_len); - if (!skb_queue_empty(&sk->sk_receive_queue) && - sk_psock_queue_empty(psock)) { - sk_psock_put(sk, psock); - return tcp_recvmsg(sk, msg, len, nonblock, flags, addr_len); - } - lock_sock(sk); -msg_bytes_ready: - copied = __tcp_bpf_recvmsg(sk, psock, msg, len, flags); - if (!copied) { - int data, err = 0; - long timeo; - - timeo = sock_rcvtimeo(sk, nonblock); - data = tcp_bpf_wait_data(sk, psock, flags, timeo, &err); - if (data) { - if (!sk_psock_queue_empty(psock)) - goto msg_bytes_ready; - release_sock(sk); - sk_psock_put(sk, psock); - return tcp_recvmsg(sk, msg, len, nonblock, flags, addr_len); - } - if (err) { - ret = err; - goto out; - } - copied = -EAGAIN; - } - ret = copied; -out: - release_sock(sk); - sk_psock_put(sk, psock); - return ret; -} - static int tcp_bpf_send_verdict(struct sock *sk, struct sk_psock *psock, struct sk_msg *msg, int *copied, int flags) { @@ -558,6 +557,57 @@ out_err: return copied ? copied : err; } +static void tcp_bpf_remove(struct sock *sk, struct sk_psock *psock) +{ + struct sk_psock_link *link; + + while ((link = sk_psock_link_pop(psock))) { + sk_psock_unlink(sk, link); + sk_psock_free_link(link); + } +} + +static void tcp_bpf_unhash(struct sock *sk) +{ + void (*saved_unhash)(struct sock *sk); + struct sk_psock *psock; + + rcu_read_lock(); + psock = sk_psock(sk); + if (unlikely(!psock)) { + rcu_read_unlock(); + if (sk->sk_prot->unhash) + sk->sk_prot->unhash(sk); + return; + } + + saved_unhash = psock->saved_unhash; + tcp_bpf_remove(sk, psock); + rcu_read_unlock(); + saved_unhash(sk); +} + +static void tcp_bpf_close(struct sock *sk, long timeout) +{ + void (*saved_close)(struct sock *sk, long timeout); + struct sk_psock *psock; + + lock_sock(sk); + rcu_read_lock(); + psock = sk_psock(sk); + if (unlikely(!psock)) { + rcu_read_unlock(); + release_sock(sk); + return sk->sk_prot->close(sk, timeout); + } + + saved_close = psock->saved_close; + tcp_bpf_remove(sk, psock); + rcu_read_unlock(); + release_sock(sk); + saved_close(sk, timeout); +} + enum { TCP_BPF_IPV4, TCP_BPF_IPV6, @@ -578,9 +628,8 @@ static void tcp_bpf_rebuild_protos(struct proto prot[TCP_BPF_NUM_CFGS], struct proto *base) { prot[TCP_BPF_BASE] = *base; - prot[TCP_BPF_BASE].unhash = sock_map_unhash; - prot[TCP_BPF_BASE].destroy = sock_map_destroy; - prot[TCP_BPF_BASE].close = sock_map_close; + prot[TCP_BPF_BASE].unhash = tcp_bpf_unhash; + prot[TCP_BPF_BASE].close = tcp_bpf_close; prot[TCP_BPF_BASE].recvmsg = tcp_bpf_recvmsg; prot[TCP_BPF_BASE].stream_memory_read = tcp_bpf_stream_read; @@ -589,9 +638,10 @@ static void tcp_bpf_rebuild_protos(struct proto prot[TCP_BPF_NUM_CFGS], prot[TCP_BPF_TX].sendpage = tcp_bpf_sendpage; } -static void tcp_bpf_check_v6_needs_rebuild(struct proto *ops) +static void tcp_bpf_check_v6_needs_rebuild(struct sock *sk, struct proto *ops) { - if (unlikely(ops != smp_load_acquire(&tcpv6_prot_saved))) { + if (sk->sk_family == AF_INET6 && + unlikely(ops != smp_load_acquire(&tcpv6_prot_saved))) { spin_lock_bh(&tcpv6_prot_lock); if (likely(ops != tcpv6_prot_saved)) { tcp_bpf_rebuild_protos(tcp_bpf_prots[TCP_BPF_IPV6], ops); @@ -608,6 +658,26 @@ static int __init tcp_bpf_v4_build_proto(void) } late_initcall(tcp_bpf_v4_build_proto); +static void tcp_bpf_update_sk_prot(struct sock *sk, struct sk_psock *psock) +{ + int family = sk->sk_family == AF_INET6 ? TCP_BPF_IPV6 : TCP_BPF_IPV4; + int config = psock->progs.msg_parser ? TCP_BPF_TX : TCP_BPF_BASE; + + sk_psock_update_proto(sk, psock, &tcp_bpf_prots[family][config]); +} + +static void tcp_bpf_reinit_sk_prot(struct sock *sk, struct sk_psock *psock) +{ + int family = sk->sk_family == AF_INET6 ? TCP_BPF_IPV6 : TCP_BPF_IPV4; + int config = psock->progs.msg_parser ? TCP_BPF_TX : TCP_BPF_BASE; + + /* Reinit occurs when program types change e.g. TCP_BPF_TX is removed + * or added requiring sk_prot hook updates. We keep original saved + * hooks in this case. + */ + sk->sk_prot = &tcp_bpf_prots[family][config]; +} + static int tcp_bpf_assert_proto_ops(struct proto *ops) { /* In order to avoid retpoline, we make assumptions when we call @@ -619,32 +689,34 @@ static int tcp_bpf_assert_proto_ops(struct proto *ops) ops->sendpage == tcp_sendpage ? 0 : -ENOTSUPP; } -struct proto *tcp_bpf_get_proto(struct sock *sk, struct sk_psock *psock) +void tcp_bpf_reinit(struct sock *sk) { - int family = sk->sk_family == AF_INET6 ? TCP_BPF_IPV6 : TCP_BPF_IPV4; - int config = psock->progs.msg_parser ? TCP_BPF_TX : TCP_BPF_BASE; + struct sk_psock *psock; - if (sk->sk_family == AF_INET6) { - if (tcp_bpf_assert_proto_ops(psock->sk_proto)) - return ERR_PTR(-EINVAL); + sock_owned_by_me(sk); - tcp_bpf_check_v6_needs_rebuild(psock->sk_proto); + rcu_read_lock(); + psock = sk_psock(sk); + tcp_bpf_reinit_sk_prot(sk, psock); + rcu_read_unlock(); +} + +int tcp_bpf_init(struct sock *sk) +{ + struct proto *ops = READ_ONCE(sk->sk_prot); + struct sk_psock *psock; + + sock_owned_by_me(sk); + + rcu_read_lock(); + psock = sk_psock(sk); + if (unlikely(!psock || psock->sk_proto || + tcp_bpf_assert_proto_ops(ops))) { + rcu_read_unlock(); + return -EINVAL; } - - return &tcp_bpf_prots[family][config]; + tcp_bpf_check_v6_needs_rebuild(sk, ops); + tcp_bpf_update_sk_prot(sk, psock); + rcu_read_unlock(); + return 0; } - -/* If a child got cloned from a listening socket that had tcp_bpf - * protocol callbacks installed, we need to restore the callbacks to - * the default ones because the child does not inherit the psock state - * that tcp_bpf callbacks expect. - */ -void tcp_bpf_clone(const struct sock *sk, struct sock *newsk) -{ - int family = sk->sk_family == AF_INET6 ? TCP_BPF_IPV6 : TCP_BPF_IPV4; - struct proto *prot = newsk->sk_prot; - - if (prot == &tcp_bpf_prots[family][TCP_BPF_BASE]) - newsk->sk_prot = sk->sk_prot_creator; -} -#endif /* CONFIG_BPF_SYSCALL */ diff --git a/net/ipv4/tcp_cong.c b/net/ipv4/tcp_cong.c index 02a5b8212893..6d5600889dcf 100644 --- a/net/ipv4/tcp_cong.c +++ b/net/ipv4/tcp_cong.c @@ -21,7 +21,7 @@ static DEFINE_SPINLOCK(tcp_cong_list_lock); static LIST_HEAD(tcp_cong_list); /* Simple linear search, don't expect many entries! */ -struct tcp_congestion_ops *tcp_ca_find(const char *name) +static struct tcp_congestion_ops *tcp_ca_find(const char *name) { struct tcp_congestion_ops *e; @@ -162,7 +162,7 @@ void tcp_assign_congestion_control(struct sock *sk) rcu_read_lock(); ca = rcu_dereference(net->ipv4.tcp_congestion_control); - if (unlikely(!bpf_try_module_get(ca, ca->owner))) + if (unlikely(!try_module_get(ca->owner))) ca = &tcp_reno; icsk->icsk_ca_ops = ca; rcu_read_unlock(); @@ -213,7 +213,7 @@ void tcp_cleanup_congestion_control(struct sock *sk) if (icsk->icsk_ca_ops->release) icsk->icsk_ca_ops->release(sk); - bpf_module_put(icsk->icsk_ca_ops, icsk->icsk_ca_ops->owner); + module_put(icsk->icsk_ca_ops->owner); } /* Used by sysctl to change default congestion control */ @@ -227,7 +227,7 @@ int tcp_set_default_congestion_control(struct net *net, const char *name) ca = tcp_ca_find_autoload(net, name); if (!ca) { ret = -ENOENT; - } else if (!bpf_try_module_get(ca, ca->owner)) { + } else if (!try_module_get(ca->owner)) { ret = -EBUSY; } else if (!net_eq(net, &init_net) && !(ca->flags & TCP_CONG_NON_RESTRICTED)) { @@ -236,7 +236,7 @@ int tcp_set_default_congestion_control(struct net *net, const char *name) } else { prev = xchg(&net->ipv4.tcp_congestion_control, ca); if (prev) - bpf_module_put(prev, prev->owner); + module_put(prev->owner); ca->flags |= TCP_CONG_NON_RESTRICTED; ret = 0; @@ -343,7 +343,7 @@ out: * already initialized. */ int tcp_set_congestion_control(struct sock *sk, const char *name, bool load, - bool cap_net_admin) + bool reinit, bool cap_net_admin) { struct inet_connection_sock *icsk = inet_csk(sk); const struct tcp_congestion_ops *ca; @@ -367,14 +367,21 @@ int tcp_set_congestion_control(struct sock *sk, const char *name, bool load, if (!ca) { err = -ENOENT; } else if (!load) { - if (bpf_try_module_get(ca, ca->owner)) { - tcp_reinit_congestion_control(sk, ca); + const struct tcp_congestion_ops *old_ca = icsk->icsk_ca_ops; + + if (try_module_get(ca->owner)) { + if (reinit) { + tcp_reinit_congestion_control(sk, ca); + } else { + icsk->icsk_ca_ops = ca; + module_put(old_ca->owner); + } } else { err = -EBUSY; } } else if (!((ca->flags & TCP_CONG_NON_RESTRICTED) || cap_net_admin)) { err = -EPERM; - } else if (!bpf_try_module_get(ca, ca->owner)) { + } else if (!try_module_get(ca->owner)) { err = -EBUSY; } else { tcp_reinit_congestion_control(sk, ca); diff --git a/net/ipv4/tcp_fastopen.c b/net/ipv4/tcp_fastopen.c index 47b3c6c539b8..38752bdedee3 100644 --- a/net/ipv4/tcp_fastopen.c +++ b/net/ipv4/tcp_fastopen.c @@ -295,7 +295,7 @@ static struct sock *tcp_fastopen_create_child(struct sock *sk, refcount_set(&req->rsk_refcnt, 2); /* Now finish processing the fastopen child socket. */ - tcp_init_transfer(child, BPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB, skb); + tcp_init_transfer(child, BPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB); tp->rcv_nxt = TCP_SKB_CB(skb)->seq + 1; diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c index c3041cdf6d7b..3b3cd32728e2 100644 --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c @@ -138,69 +138,6 @@ void clean_acked_data_flush(void) EXPORT_SYMBOL_GPL(clean_acked_data_flush); #endif -#ifdef CONFIG_CGROUP_BPF -static void bpf_skops_parse_hdr(struct sock *sk, struct sk_buff *skb) -{ - bool unknown_opt = tcp_sk(sk)->rx_opt.saw_unknown && - BPF_SOCK_OPS_TEST_FLAG(tcp_sk(sk), - BPF_SOCK_OPS_PARSE_UNKNOWN_HDR_OPT_CB_FLAG); - bool parse_all_opt = BPF_SOCK_OPS_TEST_FLAG(tcp_sk(sk), - BPF_SOCK_OPS_PARSE_ALL_HDR_OPT_CB_FLAG); - struct bpf_sock_ops_kern sock_ops; - - if (likely(!unknown_opt && !parse_all_opt)) - return; - - /* The skb will be handled in the - * bpf_skops_established() or - * bpf_skops_write_hdr_opt(). - */ - switch (sk->sk_state) { - case TCP_SYN_RECV: - case TCP_SYN_SENT: - case TCP_LISTEN: - return; - } - - sock_owned_by_me(sk); - - memset(&sock_ops, 0, offsetof(struct bpf_sock_ops_kern, temp)); - sock_ops.op = BPF_SOCK_OPS_PARSE_HDR_OPT_CB; - sock_ops.is_fullsock = 1; - sock_ops.sk = sk; - bpf_skops_init_skb(&sock_ops, skb, tcp_hdrlen(skb)); - - BPF_CGROUP_RUN_PROG_SOCK_OPS(&sock_ops); -} - -static void bpf_skops_established(struct sock *sk, int bpf_op, - struct sk_buff *skb) -{ - struct bpf_sock_ops_kern sock_ops; - - sock_owned_by_me(sk); - - memset(&sock_ops, 0, offsetof(struct bpf_sock_ops_kern, temp)); - sock_ops.op = bpf_op; - sock_ops.is_fullsock = 1; - sock_ops.sk = sk; - /* sk with TCP_REPAIR_ON does not have skb in tcp_finish_connect */ - if (skb) - bpf_skops_init_skb(&sock_ops, skb, tcp_hdrlen(skb)); - - BPF_CGROUP_RUN_PROG_SOCK_OPS(&sock_ops); -} -#else -static void bpf_skops_parse_hdr(struct sock *sk, struct sk_buff *skb) -{ -} - -static void bpf_skops_established(struct sock *sk, int bpf_op, - struct sk_buff *skb) -{ -} -#endif - static void tcp_gro_dev_warn(struct sock *sk, const struct sk_buff *skb, unsigned int len) { @@ -3935,7 +3872,7 @@ static void tcp_parse_fastopen_option(int len, const unsigned char *cookie, foc->exp = exp_opt; } -static bool smc_parse_options(const struct tcphdr *th, +static void smc_parse_options(const struct tcphdr *th, struct tcp_options_received *opt_rx, const unsigned char *ptr, int opsize) @@ -3944,13 +3881,10 @@ static bool smc_parse_options(const struct tcphdr *th, if (static_branch_unlikely(&tcp_have_smc)) { if (th->syn && !(opsize & 1) && opsize >= TCPOLEN_EXP_SMC_BASE && - get_unaligned_be32(ptr) == TCPOPT_SMC_MAGIC) { + get_unaligned_be32(ptr) == TCPOPT_SMC_MAGIC) opt_rx->smc_ok = 1; - return true; - } } #endif - return false; } /* Try to parse the MSS option from the TCP header. Return 0 on failure, clamped @@ -4011,7 +3945,6 @@ void tcp_parse_options(const struct net *net, ptr = (const unsigned char *)(th + 1); opt_rx->saw_tstamp = 0; - opt_rx->saw_unknown = 0; while (length > 0) { int opcode = *ptr++; @@ -4102,21 +4035,15 @@ void tcp_parse_options(const struct net *net, */ if (opsize >= TCPOLEN_EXP_FASTOPEN_BASE && get_unaligned_be16(ptr) == - TCPOPT_FASTOPEN_MAGIC) { + TCPOPT_FASTOPEN_MAGIC) tcp_parse_fastopen_option(opsize - TCPOLEN_EXP_FASTOPEN_BASE, ptr + 2, th->syn, foc, true); - break; - } - - if (smc_parse_options(th, opt_rx, ptr, opsize)) - break; - - opt_rx->saw_unknown = 1; + else + smc_parse_options(th, opt_rx, ptr, + opsize); break; - default: - opt_rx->saw_unknown = 1; } ptr += opsize-2; length -= opsize; @@ -5711,8 +5638,6 @@ syn_challenge: goto discard; } - bpf_skops_parse_hdr(sk, skb); - return true; discard: @@ -5923,7 +5848,7 @@ discard: } EXPORT_SYMBOL(tcp_rcv_established); -void tcp_init_transfer(struct sock *sk, int bpf_op, struct sk_buff *skb) +void tcp_init_transfer(struct sock *sk, int bpf_op) { struct inet_connection_sock *icsk = inet_csk(sk); struct tcp_sock *tp = tcp_sk(sk); @@ -5944,7 +5869,7 @@ void tcp_init_transfer(struct sock *sk, int bpf_op, struct sk_buff *skb) tp->snd_cwnd = tcp_init_cwnd(tp, __sk_dst_get(sk)); tp->snd_cwnd_stamp = tcp_jiffies32; - bpf_skops_established(sk, bpf_op, skb); + tcp_call_bpf(sk, bpf_op, 0, NULL); tcp_init_congestion_control(sk); tcp_init_buffer_space(sk); } @@ -5963,7 +5888,7 @@ void tcp_finish_connect(struct sock *sk, struct sk_buff *skb) sk_mark_napi_id(sk, skb); } - tcp_init_transfer(sk, BPF_SOCK_OPS_ACTIVE_ESTABLISHED_CB, skb); + tcp_init_transfer(sk, BPF_SOCK_OPS_ACTIVE_ESTABLISHED_CB); /* Prevent spurious tcp_cwnd_restart() on first data * packet. @@ -6433,8 +6358,7 @@ int tcp_rcv_state_process(struct sock *sk, struct sk_buff *skb) } else { tcp_try_undo_spurious_syn(sk); tp->retrans_stamp = 0; - tcp_init_transfer(sk, BPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB, - skb); + tcp_init_transfer(sk, BPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB); WRITE_ONCE(tp->copied_seq, tp->rcv_nxt); } smp_mb(); @@ -6722,27 +6646,13 @@ static void tcp_reqsk_record_syn(const struct sock *sk, { if (tcp_sk(sk)->save_syn) { u32 len = skb_network_header_len(skb) + tcp_hdrlen(skb); - struct saved_syn *saved_syn; - u32 mac_hdrlen; - void *base; + u32 *copy; - if (tcp_sk(sk)->save_syn == 2) { /* Save full header. */ - base = skb_mac_header(skb); - mac_hdrlen = skb_mac_header_len(skb); - len += mac_hdrlen; - } else { - base = skb_network_header(skb); - mac_hdrlen = 0; - } - - saved_syn = kmalloc(struct_size(saved_syn, data, len), - GFP_ATOMIC); - if (saved_syn) { - saved_syn->mac_hdrlen = mac_hdrlen; - saved_syn->network_hdrlen = skb_network_header_len(skb); - saved_syn->tcp_hdrlen = tcp_hdrlen(skb); - memcpy(saved_syn->data, base, len); - req->saved_syn = saved_syn; + copy = kmalloc(len + sizeof(u32), GFP_ATOMIC); + if (copy) { + copy[0] = len; + memcpy(©[1], skb_network_header(skb), len); + req->saved_syn = copy; } } } @@ -6890,9 +6800,10 @@ int tcp_conn_request(struct request_sock_ops *rsk_ops, } if (fastopen_sk) { af_ops->send_synack(fastopen_sk, dst, &fl, req, - &foc, TCP_SYNACK_FASTOPEN, skb); + &foc, TCP_SYNACK_FASTOPEN); /* Add the child socket directly into the accept queue */ if (!inet_csk_reqsk_queue_add(sk, req, fastopen_sk)) { + reqsk_fastopen_remove(fastopen_sk, req, false); bh_unlock_sock(fastopen_sk); sock_put(fastopen_sk); goto drop_and_free; @@ -6907,8 +6818,7 @@ int tcp_conn_request(struct request_sock_ops *rsk_ops, tcp_timeout_init((struct sock *)req)); af_ops->send_synack(sk, dst, &fl, req, &foc, !want_cookie ? TCP_SYNACK_NORMAL : - TCP_SYNACK_COOKIE, - skb); + TCP_SYNACK_COOKIE); if (want_cookie) { reqsk_free(req); return 0; diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c index 5cec3c90617c..3f90609f4282 100644 --- a/net/ipv4/tcp_ipv4.c +++ b/net/ipv4/tcp_ipv4.c @@ -76,7 +76,6 @@ #include #include #include -#include #include #include @@ -951,8 +950,7 @@ static int tcp_v4_send_synack(const struct sock *sk, struct dst_entry *dst, struct flowi *fl, struct request_sock *req, struct tcp_fastopen_cookie *foc, - enum tcp_synack_type synack_type, - struct sk_buff *syn_skb) + enum tcp_synack_type synack_type) { const struct inet_request_sock *ireq = inet_rsk(req); struct flowi4 fl4; @@ -963,7 +961,7 @@ static int tcp_v4_send_synack(const struct sock *sk, struct dst_entry *dst, if (!dst && (dst = inet_csk_route_req(sk, &fl4, req)) == NULL) return -1; - skb = tcp_make_synack(sk, dst, req, foc, synack_type, syn_skb); + skb = tcp_make_synack(sk, dst, req, foc, synack_type); if (skb) { __tcp_v4_send_check(skb, ireq->ir_loc_addr, ireq->ir_rmt_addr); @@ -2192,18 +2190,13 @@ EXPORT_SYMBOL(tcp_v4_destroy_sock); */ static void *listening_get_next(struct seq_file *seq, void *cur) { - struct tcp_seq_afinfo *afinfo; + struct tcp_seq_afinfo *afinfo = PDE_DATA(file_inode(seq->file)); struct tcp_iter_state *st = seq->private; struct net *net = seq_file_net(seq); struct inet_listen_hashbucket *ilb; struct hlist_nulls_node *node; struct sock *sk = cur; - if (st->bpf_seq_afinfo) - afinfo = st->bpf_seq_afinfo; - else - afinfo = PDE_DATA(file_inode(seq->file)); - if (!sk) { get_head: ilb = &tcp_hashinfo.listening_hash[st->bucket]; @@ -2221,8 +2214,7 @@ get_sk: sk_nulls_for_each_from(sk, node) { if (!net_eq(sock_net(sk), net)) continue; - if (afinfo->family == AF_UNSPEC || - sk->sk_family == afinfo->family) + if (sk->sk_family == afinfo->family) return sk; } spin_unlock(&ilb->lock); @@ -2259,16 +2251,11 @@ static inline bool empty_bucket(const struct tcp_iter_state *st) */ static void *established_get_first(struct seq_file *seq) { - struct tcp_seq_afinfo *afinfo; + struct tcp_seq_afinfo *afinfo = PDE_DATA(file_inode(seq->file)); struct tcp_iter_state *st = seq->private; struct net *net = seq_file_net(seq); void *rc = NULL; - if (st->bpf_seq_afinfo) - afinfo = st->bpf_seq_afinfo; - else - afinfo = PDE_DATA(file_inode(seq->file)); - st->offset = 0; for (; st->bucket <= tcp_hashinfo.ehash_mask; ++st->bucket) { struct sock *sk; @@ -2281,8 +2268,7 @@ static void *established_get_first(struct seq_file *seq) spin_lock_bh(lock); sk_nulls_for_each(sk, node, &tcp_hashinfo.ehash[st->bucket].chain) { - if ((afinfo->family != AF_UNSPEC && - sk->sk_family != afinfo->family) || + if (sk->sk_family != afinfo->family || !net_eq(sock_net(sk), net)) { continue; } @@ -2297,25 +2283,19 @@ out: static void *established_get_next(struct seq_file *seq, void *cur) { - struct tcp_seq_afinfo *afinfo; + struct tcp_seq_afinfo *afinfo = PDE_DATA(file_inode(seq->file)); struct sock *sk = cur; struct hlist_nulls_node *node; struct tcp_iter_state *st = seq->private; struct net *net = seq_file_net(seq); - if (st->bpf_seq_afinfo) - afinfo = st->bpf_seq_afinfo; - else - afinfo = PDE_DATA(file_inode(seq->file)); - ++st->num; ++st->offset; sk = sk_nulls_next(sk); sk_nulls_for_each_from(sk, node) { - if ((afinfo->family == AF_UNSPEC || - sk->sk_family == afinfo->family) && + if (sk->sk_family == afinfo->family && net_eq(sock_net(sk), net)) return sk; } @@ -2599,74 +2579,6 @@ out: return 0; } -#ifdef CONFIG_BPF_SYSCALL -struct bpf_iter__tcp { - __bpf_md_ptr(struct bpf_iter_meta *, meta); - __bpf_md_ptr(struct sock_common *, sk_common); - uid_t uid __aligned(8); -}; - -static int tcp_prog_seq_show(struct bpf_prog *prog, struct bpf_iter_meta *meta, - struct sock_common *sk_common, uid_t uid) -{ - struct bpf_iter__tcp ctx; - - meta->seq_num--; /* skip SEQ_START_TOKEN */ - ctx.meta = meta; - ctx.sk_common = sk_common; - ctx.uid = uid; - return bpf_iter_run_prog(prog, &ctx); -} - -static int bpf_iter_tcp_seq_show(struct seq_file *seq, void *v) -{ - struct bpf_iter_meta meta; - struct bpf_prog *prog; - struct sock *sk = v; - uid_t uid; - - if (v == SEQ_START_TOKEN) - return 0; - - if (sk->sk_state == TCP_TIME_WAIT) { - uid = 0; - } else if (sk->sk_state == TCP_NEW_SYN_RECV) { - const struct request_sock *req = v; - - uid = from_kuid_munged(seq_user_ns(seq), - sock_i_uid(req->rsk_listener)); - } else { - uid = from_kuid_munged(seq_user_ns(seq), sock_i_uid(sk)); - } - - meta.seq = seq; - prog = bpf_iter_get_info(&meta, false); - return tcp_prog_seq_show(prog, &meta, v, uid); -} - -static void bpf_iter_tcp_seq_stop(struct seq_file *seq, void *v) -{ - struct bpf_iter_meta meta; - struct bpf_prog *prog; - - if (!v) { - meta.seq = seq; - prog = bpf_iter_get_info(&meta, true); - if (prog) - (void)tcp_prog_seq_show(prog, &meta, v, 0); - } - - tcp_seq_stop(seq, v); -} - -static const struct seq_operations bpf_iter_tcp_seq_ops = { - .show = bpf_iter_tcp_seq_show, - .start = tcp_seq_start, - .next = tcp_seq_next, - .stop = bpf_iter_tcp_seq_stop, -}; -#endif - static const struct seq_operations tcp4_seq_ops = { .show = tcp4_seq_show, .start = tcp_seq_start, @@ -2760,8 +2672,7 @@ static void __net_exit tcp_sk_exit(struct net *net) int cpu; if (net->ipv4.tcp_congestion_control) - bpf_module_put(net->ipv4.tcp_congestion_control, - net->ipv4.tcp_congestion_control->owner); + module_put(net->ipv4.tcp_congestion_control->owner); for_each_possible_cpu(cpu) inet_ctl_sock_destroy(*per_cpu_ptr(net->ipv4.tcp_sk, cpu)); @@ -2867,8 +2778,7 @@ static int __net_init tcp_sk_init(struct net *net) /* Reno is always built in */ if (!net_eq(net, &init_net) && - bpf_try_module_get(init_net.ipv4.tcp_congestion_control, - init_net.ipv4.tcp_congestion_control->owner)) + try_module_get(init_net.ipv4.tcp_congestion_control->owner)) net->ipv4.tcp_congestion_control = init_net.ipv4.tcp_congestion_control; else net->ipv4.tcp_congestion_control = &tcp_reno; @@ -2896,68 +2806,8 @@ static struct pernet_operations __net_initdata tcp_sk_ops = { .exit_batch = tcp_sk_exit_batch, }; -#if defined(CONFIG_BPF_SYSCALL) && defined(CONFIG_PROC_FS) -DEFINE_BPF_ITER_FUNC(tcp, struct bpf_iter_meta *meta, - struct sock_common *sk_common, uid_t uid) - -static int bpf_iter_init_tcp(void *priv_data, struct bpf_iter_aux_info *aux) -{ - struct tcp_iter_state *st = priv_data; - struct tcp_seq_afinfo *afinfo; - int ret; - - afinfo = kmalloc(sizeof(*afinfo), GFP_USER | __GFP_NOWARN); - if (!afinfo) - return -ENOMEM; - - afinfo->family = AF_UNSPEC; - st->bpf_seq_afinfo = afinfo; - ret = bpf_iter_init_seq_net(priv_data, aux); - if (ret) - kfree(afinfo); - return ret; -} - -static void bpf_iter_fini_tcp(void *priv_data) -{ - struct tcp_iter_state *st = priv_data; - - kfree(st->bpf_seq_afinfo); - bpf_iter_fini_seq_net(priv_data); -} - -static const struct bpf_iter_seq_info tcp_seq_info = { - .seq_ops = &bpf_iter_tcp_seq_ops, - .init_seq_private = bpf_iter_init_tcp, - .fini_seq_private = bpf_iter_fini_tcp, - .seq_priv_size = sizeof(struct tcp_iter_state), -}; - -static struct bpf_iter_reg tcp_reg_info = { - .target = "tcp", - .ctx_arg_info_size = 1, - .ctx_arg_info = { - { offsetof(struct bpf_iter__tcp, sk_common), - PTR_TO_BTF_ID_OR_NULL }, - }, - .seq_info = &tcp_seq_info, -}; - -static void __init bpf_iter_register(void) -{ - tcp_reg_info.ctx_arg_info[0].btf_id = btf_sock_ids[BTF_SOCK_TYPE_SOCK_COMMON]; - if (bpf_iter_reg_target(&tcp_reg_info)) - pr_warn("Warning: could not register bpf iterator tcp\n"); -} - -#endif - void __init tcp_v4_init(void) { if (register_pernet_subsys(&tcp_sk_ops)) panic("Failed to create the TCP control socket.\n"); - -#if defined(CONFIG_BPF_SYSCALL) && defined(CONFIG_PROC_FS) - bpf_iter_register(); -#endif } diff --git a/net/ipv4/tcp_minisocks.c b/net/ipv4/tcp_minisocks.c index 8f4963f8b0e0..e5dc08579cf5 100644 --- a/net/ipv4/tcp_minisocks.c +++ b/net/ipv4/tcp_minisocks.c @@ -414,7 +414,7 @@ void tcp_ca_openreq_child(struct sock *sk, const struct dst_entry *dst) rcu_read_lock(); ca = tcp_ca_find_key(ca_key); - if (likely(ca && bpf_try_module_get(ca, ca->owner))) { + if (likely(ca && try_module_get(ca->owner))) { icsk->icsk_ca_dst_locked = tcp_ca_dst_locked(dst); icsk->icsk_ca_ops = ca; ca_got_dst = true; @@ -425,7 +425,7 @@ void tcp_ca_openreq_child(struct sock *sk, const struct dst_entry *dst) /* If no valid choice made yet, assign current system default ca. */ if (!ca_got_dst && (!icsk->icsk_ca_setsockopt || - !bpf_try_module_get(icsk->icsk_ca_ops, icsk->icsk_ca_ops->owner))) + !try_module_get(icsk->icsk_ca_ops->owner))) tcp_assign_congestion_control(sk); tcp_set_ca_state(sk, TCP_CA_Open); @@ -548,9 +548,6 @@ struct sock *tcp_create_openreq_child(const struct sock *sk, newtp->fastopen_req = NULL; RCU_INIT_POINTER(newtp->fastopen_rsk, NULL); - bpf_skops_init_child(sk, newsk); - tcp_bpf_clone(sk, newsk); - __TCP_INC_STATS(sock_net(sk), TCP_MIB_PASSIVEOPENS); return newsk; diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c index 9a6e8eb85bdb..51e6ae466562 100644 --- a/net/ipv4/tcp_output.c +++ b/net/ipv4/tcp_output.c @@ -436,151 +436,11 @@ struct tcp_out_options { u8 ws; /* window scale, 0 to disable */ u8 num_sack_blocks; /* number of SACK blocks to include */ u8 hash_size; /* bytes in hash_location */ - u8 bpf_opt_len; /* length of BPF hdr option */ __u8 *hash_location; /* temporary pointer, overloaded */ __u32 tsval, tsecr; /* need to include OPTION_TS */ struct tcp_fastopen_cookie *fastopen_cookie; /* Fast open cookie */ }; -#ifdef CONFIG_CGROUP_BPF -static int bpf_skops_write_hdr_opt_arg0(struct sk_buff *skb, - enum tcp_synack_type synack_type) -{ - if (unlikely(!skb)) - return BPF_WRITE_HDR_TCP_CURRENT_MSS; - - if (unlikely(synack_type == TCP_SYNACK_COOKIE)) - return BPF_WRITE_HDR_TCP_SYNACK_COOKIE; - - return 0; -} - -/* req, syn_skb and synack_type are used when writing synack */ -static void bpf_skops_hdr_opt_len(struct sock *sk, struct sk_buff *skb, - struct request_sock *req, - struct sk_buff *syn_skb, - enum tcp_synack_type synack_type, - struct tcp_out_options *opts, - unsigned int *remaining) -{ - struct bpf_sock_ops_kern sock_ops; - int err; - - if (likely(!BPF_SOCK_OPS_TEST_FLAG(tcp_sk(sk), - BPF_SOCK_OPS_WRITE_HDR_OPT_CB_FLAG)) || - !*remaining) - return; - - /* *remaining has already been aligned to 4 bytes, so *remaining >= 4 */ - - /* init sock_ops */ - memset(&sock_ops, 0, offsetof(struct bpf_sock_ops_kern, temp)); - - sock_ops.op = BPF_SOCK_OPS_HDR_OPT_LEN_CB; - - if (req) { - /* The listen "sk" cannot be passed here because - * it is not locked. It would not make too much - * sense to do bpf_setsockopt(listen_sk) based - * on individual connection request also. - * - * Thus, "req" is passed here and the cgroup-bpf-progs - * of the listen "sk" will be run. - * - * "req" is also used here for fastopen even the "sk" here is - * a fullsock "child" sk. It is to keep the behavior - * consistent between fastopen and non-fastopen on - * the bpf programming side. - */ - sock_ops.sk = (struct sock *)req; - sock_ops.syn_skb = syn_skb; - } else { - sock_owned_by_me(sk); - - sock_ops.is_fullsock = 1; - sock_ops.sk = sk; - } - - sock_ops.args[0] = bpf_skops_write_hdr_opt_arg0(skb, synack_type); - sock_ops.remaining_opt_len = *remaining; - /* tcp_current_mss() does not pass a skb */ - if (skb) - bpf_skops_init_skb(&sock_ops, skb, 0); - - err = BPF_CGROUP_RUN_PROG_SOCK_OPS_SK(&sock_ops, sk); - - if (err || sock_ops.remaining_opt_len == *remaining) - return; - - opts->bpf_opt_len = *remaining - sock_ops.remaining_opt_len; - /* round up to 4 bytes */ - opts->bpf_opt_len = (opts->bpf_opt_len + 3) & ~3; - - *remaining -= opts->bpf_opt_len; -} - -static void bpf_skops_write_hdr_opt(struct sock *sk, struct sk_buff *skb, - struct request_sock *req, - struct sk_buff *syn_skb, - enum tcp_synack_type synack_type, - struct tcp_out_options *opts) -{ - u8 first_opt_off, nr_written, max_opt_len = opts->bpf_opt_len; - struct bpf_sock_ops_kern sock_ops; - int err; - - if (likely(!max_opt_len)) - return; - - memset(&sock_ops, 0, offsetof(struct bpf_sock_ops_kern, temp)); - - sock_ops.op = BPF_SOCK_OPS_WRITE_HDR_OPT_CB; - - if (req) { - sock_ops.sk = (struct sock *)req; - sock_ops.syn_skb = syn_skb; - } else { - sock_owned_by_me(sk); - - sock_ops.is_fullsock = 1; - sock_ops.sk = sk; - } - - sock_ops.args[0] = bpf_skops_write_hdr_opt_arg0(skb, synack_type); - sock_ops.remaining_opt_len = max_opt_len; - first_opt_off = tcp_hdrlen(skb) - max_opt_len; - bpf_skops_init_skb(&sock_ops, skb, first_opt_off); - - err = BPF_CGROUP_RUN_PROG_SOCK_OPS_SK(&sock_ops, sk); - - if (err) - nr_written = 0; - else - nr_written = max_opt_len - sock_ops.remaining_opt_len; - - if (nr_written < max_opt_len) - memset(skb->data + first_opt_off + nr_written, TCPOPT_NOP, - max_opt_len - nr_written); -} -#else -static void bpf_skops_hdr_opt_len(struct sock *sk, struct sk_buff *skb, - struct request_sock *req, - struct sk_buff *syn_skb, - enum tcp_synack_type synack_type, - struct tcp_out_options *opts, - unsigned int *remaining) -{ -} - -static void bpf_skops_write_hdr_opt(struct sock *sk, struct sk_buff *skb, - struct request_sock *req, - struct sk_buff *syn_skb, - enum tcp_synack_type synack_type, - struct tcp_out_options *opts) -{ -} -#endif - /* Write previously computed TCP options to the packet. * * Beware: Something in the Internet is very sensitive to the ordering of @@ -793,8 +653,6 @@ static unsigned int tcp_syn_options(struct sock *sk, struct sk_buff *skb, smc_set_option(tp, opts, &remaining); - bpf_skops_hdr_opt_len(sk, skb, NULL, NULL, 0, opts, &remaining); - return MAX_TCP_OPTION_SPACE - remaining; } @@ -805,8 +663,7 @@ static unsigned int tcp_synack_options(const struct sock *sk, struct tcp_out_options *opts, const struct tcp_md5sig_key *md5, struct tcp_fastopen_cookie *foc, - enum tcp_synack_type synack_type, - struct sk_buff *syn_skb) + enum tcp_synack_type synack_type) { struct inet_request_sock *ireq = inet_rsk(req); unsigned int remaining = MAX_TCP_OPTION_SPACE; @@ -861,9 +718,6 @@ static unsigned int tcp_synack_options(const struct sock *sk, smc_set_option_cond(tcp_sk(sk), ireq, opts, &remaining); - bpf_skops_hdr_opt_len((struct sock *)sk, skb, req, syn_skb, - synack_type, opts, &remaining); - return MAX_TCP_OPTION_SPACE - remaining; } @@ -911,15 +765,6 @@ static unsigned int tcp_established_options(struct sock *sk, struct sk_buff *skb opts->num_sack_blocks * TCPOLEN_SACK_PERBLOCK; } - if (unlikely(BPF_SOCK_OPS_TEST_FLAG(tp, - BPF_SOCK_OPS_WRITE_HDR_OPT_CB_FLAG))) { - unsigned int remaining = MAX_TCP_OPTION_SPACE - size; - - bpf_skops_hdr_opt_len(sk, skb, NULL, NULL, 0, opts, &remaining); - - size = MAX_TCP_OPTION_SPACE - remaining; - } - return size; } @@ -1305,9 +1150,6 @@ static int __tcp_transmit_skb(struct sock *sk, struct sk_buff *skb, icsk->icsk_af_ops->send_check(sk, skb); - /* BPF prog is the last one writing header option */ - bpf_skops_write_hdr_opt(sk, skb, NULL, NULL, 0, &opts); - if (likely(tcb->tcp_flags & TCPHDR_ACK)) tcp_event_ack_sent(sk, rcv_nxt); @@ -1492,7 +1334,7 @@ int tcp_fragment(struct sock *sk, enum tcp_queue tcp_queue, return -ENOMEM; } - if (skb_unclone_keeptruesize(skb, gfp)) + if (skb_unclone(skb, gfp)) return -ENOMEM; /* Get a new skb... force flag on. */ @@ -1601,7 +1443,7 @@ int tcp_trim_head(struct sock *sk, struct sk_buff *skb, u32 len) { u32 delta_truesize; - if (skb_unclone_keeptruesize(skb, GFP_ATOMIC)) + if (skb_unclone(skb, GFP_ATOMIC)) return -ENOMEM; delta_truesize = __pskb_trim_head(skb, len); @@ -2110,8 +1952,7 @@ static bool tcp_tso_should_defer(struct sock *sk, struct sk_buff *skb, u32 max_segs) { const struct inet_connection_sock *icsk = inet_csk(sk); - u32 send_win, cong_win, limit, in_flight, threshold; - u64 srtt_in_ns, expected_ack, how_far_is_the_ack; + u32 send_win, cong_win, limit, in_flight; struct tcp_sock *tp = tcp_sk(sk); struct sk_buff *head; int win_divisor; @@ -2173,19 +2014,9 @@ static bool tcp_tso_should_defer(struct sock *sk, struct sk_buff *skb, head = tcp_rtx_queue_head(sk); if (!head) goto send_now; - - srtt_in_ns = (u64)(NSEC_PER_USEC >> 3) * tp->srtt_us; - /* When is the ACK expected ? */ - expected_ack = head->tstamp + srtt_in_ns; - /* How far from now is the ACK expected ? */ - how_far_is_the_ack = expected_ack - tp->tcp_clock_cache; - - /* If next ACK is likely to come too late, - * ie in more than min(1ms, half srtt), do not defer. - */ - threshold = min_t(u64, srtt_in_ns >> 1, NSEC_PER_MSEC); - - if ((s64)(how_far_is_the_ack - threshold) > 0) + delta = tp->tcp_clock_cache - head->tstamp; + /* If next ACK is likely to come too late (half srtt), do not defer */ + if ((s64)(delta - (u64)NSEC_PER_USEC * (tp->srtt_us >> 4)) < 0) goto send_now; /* Ok, it looks like it is advisable to defer. @@ -3160,7 +2991,7 @@ start: cur_mss, GFP_ATOMIC)) return -ENOMEM; /* We'll try again later. */ } else { - if (skb_unclone_keeptruesize(skb, GFP_ATOMIC)) + if (skb_unclone(skb, GFP_ATOMIC)) return -ENOMEM; diff = tcp_skb_pcount(skb); @@ -3473,19 +3304,18 @@ int tcp_send_synack(struct sock *sk) } /** - * tcp_make_synack - Allocate one skb and build a SYNACK packet. - * @sk: listener socket - * @dst: dst entry attached to the SYNACK. It is consumed and caller - * should not use it again. - * @req: request_sock pointer - * @foc: cookie for tcp fast open - * @syn_skb: SYN packet just received. It could be NULL for rtx case. + * tcp_make_synack - Prepare a SYN-ACK. + * sk: listener socket + * dst: dst entry attached to the SYNACK + * req: request_sock pointer + * + * Allocate one skb and build a SYNACK packet. + * @dst is consumed : Caller should not use it again. */ struct sk_buff *tcp_make_synack(const struct sock *sk, struct dst_entry *dst, struct request_sock *req, struct tcp_fastopen_cookie *foc, - enum tcp_synack_type synack_type, - struct sk_buff *syn_skb) + enum tcp_synack_type synack_type) { struct inet_request_sock *ireq = inet_rsk(req); const struct tcp_sock *tp = tcp_sk(sk); @@ -3544,11 +3374,8 @@ struct sk_buff *tcp_make_synack(const struct sock *sk, struct dst_entry *dst, md5 = tcp_rsk(req)->af_specific->req_md5_lookup(sk, req_to_sk(req)); #endif skb_set_hash(skb, tcp_rsk(req)->txhash, PKT_HASH_TYPE_L4); - /* bpf program will be interested in the tcp_flags */ - TCP_SKB_CB(skb)->tcp_flags = TCPHDR_SYN | TCPHDR_ACK; tcp_header_size = tcp_synack_options(sk, req, mss, skb, &opts, md5, - foc, synack_type, - syn_skb) + sizeof(*th); + foc, synack_type) + sizeof(*th); skb_push(skb, tcp_header_size); skb_reset_transport_header(skb); @@ -3580,9 +3407,6 @@ struct sk_buff *tcp_make_synack(const struct sock *sk, struct dst_entry *dst, rcu_read_unlock(); #endif - bpf_skops_write_hdr_opt((struct sock *)sk, skb, req, syn_skb, - synack_type, &opts); - skb->skb_mstamp_ns = now; tcp_add_tx_delay(skb, tp); @@ -3601,8 +3425,8 @@ static void tcp_ca_dst_init(struct sock *sk, const struct dst_entry *dst) rcu_read_lock(); ca = tcp_ca_find_key(ca_key); - if (likely(ca && bpf_try_module_get(ca, ca->owner))) { - bpf_module_put(icsk->icsk_ca_ops, icsk->icsk_ca_ops->owner); + if (likely(ca && try_module_get(ca->owner))) { + module_put(icsk->icsk_ca_ops->owner); icsk->icsk_ca_dst_locked = tcp_ca_dst_locked(dst); icsk->icsk_ca_ops = ca; } @@ -3886,8 +3710,6 @@ void tcp_send_delayed_ack(struct sock *sk) ato = min(ato, max_ato); } - ato = min_t(u32, ato, inet_csk(sk)->icsk_delack_max); - /* Stay within the limit we were given */ timeout = jiffies + ato; @@ -4084,8 +3906,7 @@ int tcp_rtx_synack(const struct sock *sk, struct request_sock *req) int res; tcp_rsk(req)->txhash = net_tx_rndhash(); - res = af_ops->send_synack(sk, NULL, &fl, req, NULL, TCP_SYNACK_NORMAL, - NULL); + res = af_ops->send_synack(sk, NULL, &fl, req, NULL, TCP_SYNACK_NORMAL); if (!res) { TCP_INC_STATS(sock_net(sk), TCP_MIB_RETRANSSEGS); NET_INC_STATS(sock_net(sk), LINUX_MIB_TCPSYNRETRANS); diff --git a/net/ipv4/tcp_timer.c b/net/ipv4/tcp_timer.c index 2e1e1908097e..3b7f98ef34a4 100644 --- a/net/ipv4/tcp_timer.c +++ b/net/ipv4/tcp_timer.c @@ -47,7 +47,7 @@ static void set_tcp_default(void) /*sysctl handler for tcp_ack realted master control */ int tcp_proc_delayed_ack_control(struct ctl_table *table, int write, - void *buffer, size_t *length, + void __user *buffer, size_t *length, loff_t *ppos) { int ret = proc_dointvec_minmax(table, write, buffer, length, ppos); @@ -61,7 +61,7 @@ int tcp_proc_delayed_ack_control(struct ctl_table *table, int write, /*sysctl handler for tcp_ack realted master control */ int tcp_use_userconfig_sysctl_handler(struct ctl_table *table, int write, - void *buffer, size_t *length, + void __user *buffer, size_t *length, loff_t *ppos) { int ret = proc_dointvec_minmax(table, write, buffer, length, ppos); diff --git a/net/ipv4/tcp_ulp.c b/net/ipv4/tcp_ulp.c index b44f85ac37d9..9168645b760e 100644 --- a/net/ipv4/tcp_ulp.c +++ b/net/ipv4/tcp_ulp.c @@ -103,8 +103,7 @@ void tcp_update_ulp(struct sock *sk, struct proto *proto, if (!icsk->icsk_ulp_ops) { sk->sk_write_space = write_space; - /* Pairs with lockless read in sk_clone_lock() */ - WRITE_ONCE(sk->sk_prot, proto); + sk->sk_prot = proto; return; } diff --git a/net/ipv4/udp.c b/net/ipv4/udp.c index 738944de51f6..6a4ebedb8c17 100644 --- a/net/ipv4/udp.c +++ b/net/ipv4/udp.c @@ -106,7 +106,6 @@ #include #include #include -#include #include #include #include "udp_impl.h" @@ -409,25 +408,6 @@ static u32 udp_ehashfn(const struct net *net, const __be32 laddr, udp_ehash_secret + net_hash_mix(net)); } -static struct sock *lookup_reuseport(struct net *net, struct sock *sk, - struct sk_buff *skb, - __be32 saddr, __be16 sport, - __be32 daddr, unsigned short hnum) -{ - struct sock *reuse_sk = NULL; - u32 hash; - - if (sk->sk_reuseport && sk->sk_state != TCP_ESTABLISHED) { - hash = udp_ehashfn(net, daddr, hnum, saddr, sport); - reuse_sk = reuseport_select_sock(sk, hash, skb, - sizeof(struct udphdr)); - /* Fall back to scoring if group has connections */ - if (reuseport_has_conns(sk, false)) - return NULL; - } - return reuse_sk; -} - /* called with rcu_read_lock() */ static struct sock *udp4_lib_lookup2(struct net *net, __be32 saddr, __be16 sport, @@ -436,8 +416,9 @@ static struct sock *udp4_lib_lookup2(struct net *net, struct udp_hslot *hslot2, struct sk_buff *skb) { - struct sock *sk, *result; + struct sock *sk, *result, *reuseport_result; int score, badness; + u32 hash = 0; result = NULL; badness = 0; @@ -445,41 +426,25 @@ static struct sock *udp4_lib_lookup2(struct net *net, score = compute_score(sk, net, saddr, sport, daddr, hnum, dif, sdif); if (score > badness) { - result = lookup_reuseport(net, sk, skb, - saddr, sport, daddr, hnum); - if (result) - return result; + reuseport_result = NULL; + if (sk->sk_reuseport && + sk->sk_state != TCP_ESTABLISHED) { + hash = udp_ehashfn(net, daddr, hnum, + saddr, sport); + reuseport_result = reuseport_select_sock(sk, hash, skb, + sizeof(struct udphdr)); + if (reuseport_result && !reuseport_has_conns(sk, false)) + return reuseport_result; + } + + result = reuseport_result ? : sk; badness = score; - result = sk; } } return result; } -static inline struct sock *udp4_lookup_run_bpf(struct net *net, - struct udp_table *udptable, - struct sk_buff *skb, - __be32 saddr, __be16 sport, - __be32 daddr, u16 hnum) -{ - struct sock *sk, *reuse_sk; - bool no_reuseport; - - if (udptable != &udp_table) - return NULL; /* only UDP is supported */ - - no_reuseport = bpf_sk_lookup_run_v4(net, IPPROTO_UDP, - saddr, sport, daddr, hnum, &sk); - if (no_reuseport || IS_ERR_OR_NULL(sk)) - return sk; - - reuse_sk = lookup_reuseport(net, sk, skb, saddr, sport, daddr, hnum); - if (reuse_sk) - sk = reuse_sk; - return sk; -} - /* UDP is nearly always wildcards out the wazoo, it makes no sense to try * harder than this. -DaveM */ @@ -487,45 +452,27 @@ struct sock *__udp4_lib_lookup(struct net *net, __be32 saddr, __be16 sport, __be32 daddr, __be16 dport, int dif, int sdif, struct udp_table *udptable, struct sk_buff *skb) { + struct sock *result; unsigned short hnum = ntohs(dport); unsigned int hash2, slot2; struct udp_hslot *hslot2; - struct sock *result, *sk; hash2 = ipv4_portaddr_hash(net, daddr, hnum); slot2 = hash2 & udptable->mask; hslot2 = &udptable->hash2[slot2]; - /* Lookup connected or non-wildcard socket */ result = udp4_lib_lookup2(net, saddr, sport, daddr, hnum, dif, sdif, hslot2, skb); - if (!IS_ERR_OR_NULL(result) && result->sk_state == TCP_ESTABLISHED) - goto done; + if (!result) { + hash2 = ipv4_portaddr_hash(net, htonl(INADDR_ANY), hnum); + slot2 = hash2 & udptable->mask; + hslot2 = &udptable->hash2[slot2]; - /* Lookup redirect from BPF */ - if (static_branch_unlikely(&bpf_sk_lookup_enabled)) { - sk = udp4_lookup_run_bpf(net, udptable, skb, - saddr, sport, daddr, hnum); - if (sk) { - result = sk; - goto done; - } + result = udp4_lib_lookup2(net, saddr, sport, + htonl(INADDR_ANY), hnum, dif, sdif, + hslot2, skb); } - - /* Got non-wildcard socket or error on first lookup */ - if (result) - goto done; - - /* Lookup wildcard sockets */ - hash2 = ipv4_portaddr_hash(net, htonl(INADDR_ANY), hnum); - slot2 = hash2 & udptable->mask; - hslot2 = &udptable->hash2[slot2]; - - result = udp4_lib_lookup2(net, saddr, sport, - htonl(INADDR_ANY), hnum, dif, sdif, - hslot2, skb); -done: if (IS_ERR(result)) return NULL; return result; @@ -1431,12 +1378,12 @@ static bool udp_skb_has_head_state(struct sk_buff *skb) } /* fully reclaim rmem/fwd memory allocated for skb */ -static void udp_rmem_release(struct sock *sk, unsigned int size, - int partial, bool rx_queue_lock_held) +static void udp_rmem_release(struct sock *sk, int size, int partial, + bool rx_queue_lock_held) { struct udp_sock *up = udp_sk(sk); struct sk_buff_head *sk_queue; - unsigned int amt; + int amt; if (likely(partial)) { up->forward_deficit += size; @@ -1456,8 +1403,10 @@ static void udp_rmem_release(struct sock *sk, unsigned int size, if (!rx_queue_lock_held) spin_lock(&sk_queue->lock); - amt = (size + sk->sk_forward_alloc - partial) & ~(PAGE_SIZE - 1); - sk->sk_forward_alloc += size - amt; + + sk->sk_forward_alloc += size; + amt = (sk->sk_forward_alloc - partial) & ~(SK_MEM_QUANTUM - 1); + sk->sk_forward_alloc -= amt; if (amt) __sk_mem_reduce_allocated(sk, amt >> SK_MEM_QUANTUM_SHIFT); @@ -1641,7 +1590,7 @@ EXPORT_SYMBOL_GPL(skb_consume_udp); static struct sk_buff *__first_packet_length(struct sock *sk, struct sk_buff_head *rcvq, - unsigned int *total) + int *total) { struct sk_buff *skb; @@ -1674,8 +1623,8 @@ static int first_packet_length(struct sock *sk) { struct sk_buff_head *rcvq = &udp_sk(sk)->reader_queue; struct sk_buff_head *sk_queue = &sk->sk_receive_queue; - unsigned int total = 0; struct sk_buff *skb; + int total = 0; int res; spin_lock_bh(&rcvq->lock); @@ -2360,7 +2309,6 @@ int __udp4_lib_rcv(struct sk_buff *skb, struct udp_table *udptable, struct rtable *rt = skb_rtable(skb); __be32 saddr, daddr; struct net *net = dev_net(skb->dev); - bool refcounted; /* * Validate the packet. @@ -2386,7 +2334,7 @@ int __udp4_lib_rcv(struct sk_buff *skb, struct udp_table *udptable, if (udp4_csum_init(skb, uh, proto)) goto csum_error; - sk = skb_steal_sock(skb, &refcounted); + sk = skb_steal_sock(skb); if (sk) { struct dst_entry *dst = skb_dst(skb); int ret; @@ -2395,8 +2343,7 @@ int __udp4_lib_rcv(struct sk_buff *skb, struct udp_table *udptable, udp_sk_rx_dst_set(sk, dst); ret = udp_unicast_rcv_skb(sk, skb, uh); - if (refcounted) - sock_put(sk); + sock_put(sk); return ret; } @@ -2605,7 +2552,7 @@ void udp_destroy_sock(struct sock *sk) * Socket option code for UDP */ int udp_lib_setsockopt(struct sock *sk, int level, int optname, - sockptr_t optval, unsigned int optlen, + char __user *optval, unsigned int optlen, int (*push_pending_frames)(struct sock *)) { struct udp_sock *up = udp_sk(sk); @@ -2616,7 +2563,7 @@ int udp_lib_setsockopt(struct sock *sk, int level, int optname, if (optlen < sizeof(int)) return -EINVAL; - if (copy_from_sockptr(&val, optval, sizeof(val))) + if (get_user(val, (int __user *)optval)) return -EFAULT; valbool = val ? 1 : 0; @@ -2720,8 +2667,7 @@ int udp_setsockopt(struct sock *sk, int level, int optname, char __user *optval, unsigned int optlen) { if (level == SOL_UDP || level == SOL_UDPLITE) - return udp_lib_setsockopt(sk, level, optname, - USER_SOCKPTR(optval), optlen, + return udp_lib_setsockopt(sk, level, optname, optval, optlen, udp_push_pending_frames); return ip_setsockopt(sk, level, optname, optval, optlen); } @@ -2731,7 +2677,7 @@ int compat_udp_setsockopt(struct sock *sk, int level, int optname, char __user *optval, unsigned int optlen) { if (level == SOL_UDP || level == SOL_UDPLITE) - return udp_lib_setsockopt(sk, level, optname, USER_SOCKPTR(optval), optlen, + return udp_lib_setsockopt(sk, level, optname, optval, optlen, udp_push_pending_frames); return compat_ip_setsockopt(sk, level, optname, optval, optlen); } @@ -2907,15 +2853,10 @@ EXPORT_SYMBOL(udp_prot); static struct sock *udp_get_first(struct seq_file *seq, int start) { struct sock *sk; - struct udp_seq_afinfo *afinfo; + struct udp_seq_afinfo *afinfo = PDE_DATA(file_inode(seq->file)); struct udp_iter_state *state = seq->private; struct net *net = seq_file_net(seq); - if (state->bpf_seq_afinfo) - afinfo = state->bpf_seq_afinfo; - else - afinfo = PDE_DATA(file_inode(seq->file)); - for (state->bucket = start; state->bucket <= afinfo->udp_table->mask; ++state->bucket) { struct udp_hslot *hslot = &afinfo->udp_table->hash[state->bucket]; @@ -2927,8 +2868,7 @@ static struct sock *udp_get_first(struct seq_file *seq, int start) sk_for_each(sk, &hslot->head) { if (!net_eq(sock_net(sk), net)) continue; - if (afinfo->family == AF_UNSPEC || - sk->sk_family == afinfo->family) + if (sk->sk_family == afinfo->family) goto found; } spin_unlock_bh(&hslot->lock); @@ -2940,20 +2880,13 @@ found: static struct sock *udp_get_next(struct seq_file *seq, struct sock *sk) { - struct udp_seq_afinfo *afinfo; + struct udp_seq_afinfo *afinfo = PDE_DATA(file_inode(seq->file)); struct udp_iter_state *state = seq->private; struct net *net = seq_file_net(seq); - if (state->bpf_seq_afinfo) - afinfo = state->bpf_seq_afinfo; - else - afinfo = PDE_DATA(file_inode(seq->file)); - do { sk = sk_next(sk); - } while (sk && (!net_eq(sock_net(sk), net) || - (afinfo->family != AF_UNSPEC && - sk->sk_family != afinfo->family))); + } while (sk && (!net_eq(sock_net(sk), net) || sk->sk_family != afinfo->family)); if (!sk) { if (state->bucket <= afinfo->udp_table->mask) @@ -2998,14 +2931,9 @@ EXPORT_SYMBOL(udp_seq_next); void udp_seq_stop(struct seq_file *seq, void *v) { - struct udp_seq_afinfo *afinfo; + struct udp_seq_afinfo *afinfo = PDE_DATA(file_inode(seq->file)); struct udp_iter_state *state = seq->private; - if (state->bpf_seq_afinfo) - afinfo = state->bpf_seq_afinfo; - else - afinfo = PDE_DATA(file_inode(seq->file)); - if (state->bucket <= afinfo->udp_table->mask) spin_unlock_bh(&afinfo->udp_table->hash[state->bucket].lock); } @@ -3053,67 +2981,6 @@ int udp4_seq_show(struct seq_file *seq, void *v) return 0; } -#ifdef CONFIG_BPF_SYSCALL -struct bpf_iter__udp { - __bpf_md_ptr(struct bpf_iter_meta *, meta); - __bpf_md_ptr(struct udp_sock *, udp_sk); - uid_t uid __aligned(8); - int bucket __aligned(8); -}; - -static int udp_prog_seq_show(struct bpf_prog *prog, struct bpf_iter_meta *meta, - struct udp_sock *udp_sk, uid_t uid, int bucket) -{ - struct bpf_iter__udp ctx; - - meta->seq_num--; /* skip SEQ_START_TOKEN */ - ctx.meta = meta; - ctx.udp_sk = udp_sk; - ctx.uid = uid; - ctx.bucket = bucket; - return bpf_iter_run_prog(prog, &ctx); -} - -static int bpf_iter_udp_seq_show(struct seq_file *seq, void *v) -{ - struct udp_iter_state *state = seq->private; - struct bpf_iter_meta meta; - struct bpf_prog *prog; - struct sock *sk = v; - uid_t uid; - - if (v == SEQ_START_TOKEN) - return 0; - - uid = from_kuid_munged(seq_user_ns(seq), sock_i_uid(sk)); - meta.seq = seq; - prog = bpf_iter_get_info(&meta, false); - return udp_prog_seq_show(prog, &meta, v, uid, state->bucket); -} - -static void bpf_iter_udp_seq_stop(struct seq_file *seq, void *v) -{ - struct bpf_iter_meta meta; - struct bpf_prog *prog; - - if (!v) { - meta.seq = seq; - prog = bpf_iter_get_info(&meta, true); - if (prog) - (void)udp_prog_seq_show(prog, &meta, v, 0, 0); - } - - udp_seq_stop(seq, v); -} - -static const struct seq_operations bpf_iter_udp_seq_ops = { - .start = udp_seq_start, - .next = udp_seq_next, - .stop = bpf_iter_udp_seq_stop, - .show = bpf_iter_udp_seq_show, -}; -#endif - const struct seq_operations udp_seq_ops = { .start = udp_seq_start, .next = udp_seq_next, @@ -3231,62 +3098,6 @@ static struct pernet_operations __net_initdata udp_sysctl_ops = { .init = udp_sysctl_init, }; -#if defined(CONFIG_BPF_SYSCALL) && defined(CONFIG_PROC_FS) -DEFINE_BPF_ITER_FUNC(udp, struct bpf_iter_meta *meta, - struct udp_sock *udp_sk, uid_t uid, int bucket) - -static int bpf_iter_init_udp(void *priv_data, struct bpf_iter_aux_info *aux) -{ - struct udp_iter_state *st = priv_data; - struct udp_seq_afinfo *afinfo; - int ret; - - afinfo = kmalloc(sizeof(*afinfo), GFP_USER | __GFP_NOWARN); - if (!afinfo) - return -ENOMEM; - - afinfo->family = AF_UNSPEC; - afinfo->udp_table = &udp_table; - st->bpf_seq_afinfo = afinfo; - ret = bpf_iter_init_seq_net(priv_data, aux); - if (ret) - kfree(afinfo); - return ret; -} - -static void bpf_iter_fini_udp(void *priv_data) -{ - struct udp_iter_state *st = priv_data; - - kfree(st->bpf_seq_afinfo); - bpf_iter_fini_seq_net(priv_data); -} - -static const struct bpf_iter_seq_info udp_seq_info = { - .seq_ops = &bpf_iter_udp_seq_ops, - .init_seq_private = bpf_iter_init_udp, - .fini_seq_private = bpf_iter_fini_udp, - .seq_priv_size = sizeof(struct udp_iter_state), -}; - -static struct bpf_iter_reg udp_reg_info = { - .target = "udp", - .ctx_arg_info_size = 1, - .ctx_arg_info = { - { offsetof(struct bpf_iter__udp, udp_sk), - PTR_TO_BTF_ID_OR_NULL }, - }, - .seq_info = &udp_seq_info, -}; - -static void __init bpf_iter_register(void) -{ - udp_reg_info.ctx_arg_info[0].btf_id = btf_sock_ids[BTF_SOCK_TYPE_UDP]; - if (bpf_iter_reg_target(&udp_reg_info)) - pr_warn("Warning: could not register bpf iterator udp\n"); -} -#endif - void __init udp_init(void) { unsigned long limit; @@ -3312,8 +3123,4 @@ void __init udp_init(void) if (register_pernet_subsys(&udp_sysctl_ops)) panic("UDP: failed to init sysctl parameters.\n"); - -#if defined(CONFIG_BPF_SYSCALL) && defined(CONFIG_PROC_FS) - bpf_iter_register(); -#endif } diff --git a/net/ipv4/udp_bpf.c b/net/ipv4/udp_bpf.c deleted file mode 100644 index 7a94791efc1a..000000000000 --- a/net/ipv4/udp_bpf.c +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2020 Cloudflare Ltd https://cloudflare.com */ - -#include -#include -#include - -enum { - UDP_BPF_IPV4, - UDP_BPF_IPV6, - UDP_BPF_NUM_PROTS, -}; - -static struct proto *udpv6_prot_saved __read_mostly; -static DEFINE_SPINLOCK(udpv6_prot_lock); -static struct proto udp_bpf_prots[UDP_BPF_NUM_PROTS]; - -static void udp_bpf_rebuild_protos(struct proto *prot, const struct proto *base) -{ - *prot = *base; - prot->unhash = sock_map_unhash; - prot->close = sock_map_close; -} - -static void udp_bpf_check_v6_needs_rebuild(struct proto *ops) -{ - if (unlikely(ops != smp_load_acquire(&udpv6_prot_saved))) { - spin_lock_bh(&udpv6_prot_lock); - if (likely(ops != udpv6_prot_saved)) { - udp_bpf_rebuild_protos(&udp_bpf_prots[UDP_BPF_IPV6], ops); - smp_store_release(&udpv6_prot_saved, ops); - } - spin_unlock_bh(&udpv6_prot_lock); - } -} - -static int __init udp_bpf_v4_build_proto(void) -{ - udp_bpf_rebuild_protos(&udp_bpf_prots[UDP_BPF_IPV4], &udp_prot); - return 0; -} -core_initcall(udp_bpf_v4_build_proto); - -struct proto *udp_bpf_get_proto(struct sock *sk, struct sk_psock *psock) -{ - int family = sk->sk_family == AF_INET ? UDP_BPF_IPV4 : UDP_BPF_IPV6; - - if (sk->sk_family == AF_INET6) - udp_bpf_check_v6_needs_rebuild(psock->sk_proto); - - return &udp_bpf_prots[family]; -} diff --git a/net/ipv4/udp_tunnel_core.c b/net/ipv4/udp_tunnel.c similarity index 97% rename from net/ipv4/udp_tunnel_core.c rename to net/ipv4/udp_tunnel.c index d70f683d3c49..bbe4eca42d36 100644 --- a/net/ipv4/udp_tunnel_core.c +++ b/net/ipv4/udp_tunnel.c @@ -22,7 +22,9 @@ int udp_sock_create4(struct net *net, struct udp_port_cfg *cfg, goto error; if (cfg->bind_ifindex) { - err = sock_bindtoindex(sock->sk, cfg->bind_ifindex, true); + err = kernel_setsockopt(sock, SOL_SOCKET, SO_BINDTOIFINDEX, + (void *)&cfg->bind_ifindex, + sizeof(cfg->bind_ifindex)); if (err < 0) goto error; } diff --git a/net/ipv4/udp_tunnel_nic.c b/net/ipv4/udp_tunnel_nic.c deleted file mode 100644 index 056cfe0b770e..000000000000 --- a/net/ipv4/udp_tunnel_nic.c +++ /dev/null @@ -1,821 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// Copyright (c) 2020 Facebook Inc. - -#include -#include -#include -#include -#include - -enum udp_tunnel_nic_table_entry_flags { - UDP_TUNNEL_NIC_ENTRY_ADD = BIT(0), - UDP_TUNNEL_NIC_ENTRY_DEL = BIT(1), - UDP_TUNNEL_NIC_ENTRY_OP_FAIL = BIT(2), - UDP_TUNNEL_NIC_ENTRY_FROZEN = BIT(3), -}; - -struct udp_tunnel_nic_table_entry { - __be16 port; - u8 type; - u8 use_cnt; - u8 flags; - u8 hw_priv; -}; - -/** - * struct udp_tunnel_nic - UDP tunnel port offload state - * @work: async work for talking to hardware from process context - * @dev: netdev pointer - * @need_sync: at least one port start changed - * @need_replay: space was freed, we need a replay of all ports - * @work_pending: @work is currently scheduled - * @n_tables: number of tables under @entries - * @missed: bitmap of tables which overflown - * @entries: table of tables of ports currently offloaded - */ -struct udp_tunnel_nic { - struct work_struct work; - - struct net_device *dev; - - u8 need_sync:1; - u8 need_replay:1; - u8 work_pending:1; - - unsigned int n_tables; - unsigned long missed; - struct udp_tunnel_nic_table_entry **entries; -}; - -/* We ensure all work structs are done using driver state, but not the code. - * We need a workqueue we can flush before module gets removed. - */ -static struct workqueue_struct *udp_tunnel_nic_workqueue; - -static const char *udp_tunnel_nic_tunnel_type_name(unsigned int type) -{ - switch (type) { - case UDP_TUNNEL_TYPE_VXLAN: - return "vxlan"; - case UDP_TUNNEL_TYPE_GENEVE: - return "geneve"; - case UDP_TUNNEL_TYPE_VXLAN_GPE: - return "vxlan-gpe"; - default: - return "unknown"; - } -} - -static bool -udp_tunnel_nic_entry_is_free(struct udp_tunnel_nic_table_entry *entry) -{ - return entry->use_cnt == 0 && !entry->flags; -} - -static bool -udp_tunnel_nic_entry_is_frozen(struct udp_tunnel_nic_table_entry *entry) -{ - return entry->flags & UDP_TUNNEL_NIC_ENTRY_FROZEN; -} - -static void -udp_tunnel_nic_entry_freeze_used(struct udp_tunnel_nic_table_entry *entry) -{ - if (!udp_tunnel_nic_entry_is_free(entry)) - entry->flags |= UDP_TUNNEL_NIC_ENTRY_FROZEN; -} - -static void -udp_tunnel_nic_entry_unfreeze(struct udp_tunnel_nic_table_entry *entry) -{ - entry->flags &= ~UDP_TUNNEL_NIC_ENTRY_FROZEN; -} - -static bool -udp_tunnel_nic_entry_is_queued(struct udp_tunnel_nic_table_entry *entry) -{ - return entry->flags & (UDP_TUNNEL_NIC_ENTRY_ADD | - UDP_TUNNEL_NIC_ENTRY_DEL); -} - -static void -udp_tunnel_nic_entry_queue(struct udp_tunnel_nic *utn, - struct udp_tunnel_nic_table_entry *entry, - unsigned int flag) -{ - entry->flags |= flag; - utn->need_sync = 1; -} - -static void -udp_tunnel_nic_ti_from_entry(struct udp_tunnel_nic_table_entry *entry, - struct udp_tunnel_info *ti) -{ - memset(ti, 0, sizeof(*ti)); - ti->port = entry->port; - ti->type = entry->type; - ti->hw_priv = entry->hw_priv; -} - -static bool -udp_tunnel_nic_is_empty(struct net_device *dev, struct udp_tunnel_nic *utn) -{ - const struct udp_tunnel_nic_info *info = dev->udp_tunnel_nic_info; - unsigned int i, j; - - for (i = 0; i < utn->n_tables; i++) - for (j = 0; j < info->tables[i].n_entries; j++) - if (!udp_tunnel_nic_entry_is_free(&utn->entries[i][j])) - return false; - return true; -} - -static bool -udp_tunnel_nic_should_replay(struct net_device *dev, struct udp_tunnel_nic *utn) -{ - const struct udp_tunnel_nic_table_info *table; - unsigned int i, j; - - if (!utn->missed) - return false; - - for (i = 0; i < utn->n_tables; i++) { - table = &dev->udp_tunnel_nic_info->tables[i]; - if (!test_bit(i, &utn->missed)) - continue; - - for (j = 0; j < table->n_entries; j++) - if (udp_tunnel_nic_entry_is_free(&utn->entries[i][j])) - return true; - } - - return false; -} - -static void -__udp_tunnel_nic_get_port(struct net_device *dev, unsigned int table, - unsigned int idx, struct udp_tunnel_info *ti) -{ - struct udp_tunnel_nic_table_entry *entry; - struct udp_tunnel_nic *utn; - - utn = dev->udp_tunnel_nic; - entry = &utn->entries[table][idx]; - - if (entry->use_cnt) - udp_tunnel_nic_ti_from_entry(entry, ti); -} - -static void -__udp_tunnel_nic_set_port_priv(struct net_device *dev, unsigned int table, - unsigned int idx, u8 priv) -{ - dev->udp_tunnel_nic->entries[table][idx].hw_priv = priv; -} - -static void -udp_tunnel_nic_entry_update_done(struct udp_tunnel_nic_table_entry *entry, - int err) -{ - bool dodgy = entry->flags & UDP_TUNNEL_NIC_ENTRY_OP_FAIL; - - WARN_ON_ONCE(entry->flags & UDP_TUNNEL_NIC_ENTRY_ADD && - entry->flags & UDP_TUNNEL_NIC_ENTRY_DEL); - - if (entry->flags & UDP_TUNNEL_NIC_ENTRY_ADD && - (!err || (err == -EEXIST && dodgy))) - entry->flags &= ~UDP_TUNNEL_NIC_ENTRY_ADD; - - if (entry->flags & UDP_TUNNEL_NIC_ENTRY_DEL && - (!err || (err == -ENOENT && dodgy))) - entry->flags &= ~UDP_TUNNEL_NIC_ENTRY_DEL; - - if (!err) - entry->flags &= ~UDP_TUNNEL_NIC_ENTRY_OP_FAIL; - else - entry->flags |= UDP_TUNNEL_NIC_ENTRY_OP_FAIL; -} - -static void -udp_tunnel_nic_device_sync_one(struct net_device *dev, - struct udp_tunnel_nic *utn, - unsigned int table, unsigned int idx) -{ - struct udp_tunnel_nic_table_entry *entry; - struct udp_tunnel_info ti; - int err; - - entry = &utn->entries[table][idx]; - if (!udp_tunnel_nic_entry_is_queued(entry)) - return; - - udp_tunnel_nic_ti_from_entry(entry, &ti); - if (entry->flags & UDP_TUNNEL_NIC_ENTRY_ADD) - err = dev->udp_tunnel_nic_info->set_port(dev, table, idx, &ti); - else - err = dev->udp_tunnel_nic_info->unset_port(dev, table, idx, - &ti); - udp_tunnel_nic_entry_update_done(entry, err); - - if (err) - netdev_warn(dev, - "UDP tunnel port sync failed port %d type %s: %d\n", - be16_to_cpu(entry->port), - udp_tunnel_nic_tunnel_type_name(entry->type), - err); -} - -static void -udp_tunnel_nic_device_sync_by_port(struct net_device *dev, - struct udp_tunnel_nic *utn) -{ - const struct udp_tunnel_nic_info *info = dev->udp_tunnel_nic_info; - unsigned int i, j; - - for (i = 0; i < utn->n_tables; i++) - for (j = 0; j < info->tables[i].n_entries; j++) - udp_tunnel_nic_device_sync_one(dev, utn, i, j); -} - -static void -udp_tunnel_nic_device_sync_by_table(struct net_device *dev, - struct udp_tunnel_nic *utn) -{ - const struct udp_tunnel_nic_info *info = dev->udp_tunnel_nic_info; - unsigned int i, j; - int err; - - for (i = 0; i < utn->n_tables; i++) { - /* Find something that needs sync in this table */ - for (j = 0; j < info->tables[i].n_entries; j++) - if (udp_tunnel_nic_entry_is_queued(&utn->entries[i][j])) - break; - if (j == info->tables[i].n_entries) - continue; - - err = info->sync_table(dev, i); - if (err) - netdev_warn(dev, "UDP tunnel port sync failed for table %d: %d\n", - i, err); - - for (j = 0; j < info->tables[i].n_entries; j++) { - struct udp_tunnel_nic_table_entry *entry; - - entry = &utn->entries[i][j]; - if (udp_tunnel_nic_entry_is_queued(entry)) - udp_tunnel_nic_entry_update_done(entry, err); - } - } -} - -static void -__udp_tunnel_nic_device_sync(struct net_device *dev, struct udp_tunnel_nic *utn) -{ - if (!utn->need_sync) - return; - - if (dev->udp_tunnel_nic_info->sync_table) - udp_tunnel_nic_device_sync_by_table(dev, utn); - else - udp_tunnel_nic_device_sync_by_port(dev, utn); - - utn->need_sync = 0; - /* Can't replay directly here, in case we come from the tunnel driver's - * notification - trying to replay may deadlock inside tunnel driver. - */ - utn->need_replay = udp_tunnel_nic_should_replay(dev, utn); -} - -static void -udp_tunnel_nic_device_sync(struct net_device *dev, struct udp_tunnel_nic *utn) -{ - const struct udp_tunnel_nic_info *info = dev->udp_tunnel_nic_info; - bool may_sleep; - - if (!utn->need_sync) - return; - - /* Drivers which sleep in the callback need to update from - * the workqueue, if we come from the tunnel driver's notification. - */ - may_sleep = info->flags & UDP_TUNNEL_NIC_INFO_MAY_SLEEP; - if (!may_sleep) - __udp_tunnel_nic_device_sync(dev, utn); - if (may_sleep || utn->need_replay) { - queue_work(udp_tunnel_nic_workqueue, &utn->work); - utn->work_pending = 1; - } -} - -static bool -udp_tunnel_nic_table_is_capable(const struct udp_tunnel_nic_table_info *table, - struct udp_tunnel_info *ti) -{ - return table->tunnel_types & ti->type; -} - -static bool -udp_tunnel_nic_is_capable(struct net_device *dev, struct udp_tunnel_nic *utn, - struct udp_tunnel_info *ti) -{ - const struct udp_tunnel_nic_info *info = dev->udp_tunnel_nic_info; - unsigned int i; - - /* Special case IPv4-only NICs */ - if (info->flags & UDP_TUNNEL_NIC_INFO_IPV4_ONLY && - ti->sa_family != AF_INET) - return false; - - for (i = 0; i < utn->n_tables; i++) - if (udp_tunnel_nic_table_is_capable(&info->tables[i], ti)) - return true; - return false; -} - -static int -udp_tunnel_nic_has_collision(struct net_device *dev, struct udp_tunnel_nic *utn, - struct udp_tunnel_info *ti) -{ - const struct udp_tunnel_nic_info *info = dev->udp_tunnel_nic_info; - struct udp_tunnel_nic_table_entry *entry; - unsigned int i, j; - - for (i = 0; i < utn->n_tables; i++) - for (j = 0; j < info->tables[i].n_entries; j++) { - entry = &utn->entries[i][j]; - - if (!udp_tunnel_nic_entry_is_free(entry) && - entry->port == ti->port && - entry->type != ti->type) { - __set_bit(i, &utn->missed); - return true; - } - } - return false; -} - -static void -udp_tunnel_nic_entry_adj(struct udp_tunnel_nic *utn, - unsigned int table, unsigned int idx, int use_cnt_adj) -{ - struct udp_tunnel_nic_table_entry *entry = &utn->entries[table][idx]; - bool dodgy = entry->flags & UDP_TUNNEL_NIC_ENTRY_OP_FAIL; - unsigned int from, to; - - /* If not going from used to unused or vice versa - all done. - * For dodgy entries make sure we try to sync again (queue the entry). - */ - entry->use_cnt += use_cnt_adj; - if (!dodgy && !entry->use_cnt == !(entry->use_cnt - use_cnt_adj)) - return; - - /* Cancel the op before it was sent to the device, if possible, - * otherwise we'd need to take special care to issue commands - * in the same order the ports arrived. - */ - if (use_cnt_adj < 0) { - from = UDP_TUNNEL_NIC_ENTRY_ADD; - to = UDP_TUNNEL_NIC_ENTRY_DEL; - } else { - from = UDP_TUNNEL_NIC_ENTRY_DEL; - to = UDP_TUNNEL_NIC_ENTRY_ADD; - } - - if (entry->flags & from) { - entry->flags &= ~from; - if (!dodgy) - return; - } - - udp_tunnel_nic_entry_queue(utn, entry, to); -} - -static bool -udp_tunnel_nic_entry_try_adj(struct udp_tunnel_nic *utn, - unsigned int table, unsigned int idx, - struct udp_tunnel_info *ti, int use_cnt_adj) -{ - struct udp_tunnel_nic_table_entry *entry = &utn->entries[table][idx]; - - if (udp_tunnel_nic_entry_is_free(entry) || - entry->port != ti->port || - entry->type != ti->type) - return false; - - if (udp_tunnel_nic_entry_is_frozen(entry)) - return true; - - udp_tunnel_nic_entry_adj(utn, table, idx, use_cnt_adj); - return true; -} - -/* Try to find existing matching entry and adjust its use count, instead of - * adding a new one. Returns true if entry was found. In case of delete the - * entry may have gotten removed in the process, in which case it will be - * queued for removal. - */ -static bool -udp_tunnel_nic_try_existing(struct net_device *dev, struct udp_tunnel_nic *utn, - struct udp_tunnel_info *ti, int use_cnt_adj) -{ - const struct udp_tunnel_nic_table_info *table; - unsigned int i, j; - - for (i = 0; i < utn->n_tables; i++) { - table = &dev->udp_tunnel_nic_info->tables[i]; - if (!udp_tunnel_nic_table_is_capable(table, ti)) - continue; - - for (j = 0; j < table->n_entries; j++) - if (udp_tunnel_nic_entry_try_adj(utn, i, j, ti, - use_cnt_adj)) - return true; - } - - return false; -} - -static bool -udp_tunnel_nic_add_existing(struct net_device *dev, struct udp_tunnel_nic *utn, - struct udp_tunnel_info *ti) -{ - return udp_tunnel_nic_try_existing(dev, utn, ti, +1); -} - -static bool -udp_tunnel_nic_del_existing(struct net_device *dev, struct udp_tunnel_nic *utn, - struct udp_tunnel_info *ti) -{ - return udp_tunnel_nic_try_existing(dev, utn, ti, -1); -} - -static bool -udp_tunnel_nic_add_new(struct net_device *dev, struct udp_tunnel_nic *utn, - struct udp_tunnel_info *ti) -{ - const struct udp_tunnel_nic_table_info *table; - unsigned int i, j; - - for (i = 0; i < utn->n_tables; i++) { - table = &dev->udp_tunnel_nic_info->tables[i]; - if (!udp_tunnel_nic_table_is_capable(table, ti)) - continue; - - for (j = 0; j < table->n_entries; j++) { - struct udp_tunnel_nic_table_entry *entry; - - entry = &utn->entries[i][j]; - if (!udp_tunnel_nic_entry_is_free(entry)) - continue; - - entry->port = ti->port; - entry->type = ti->type; - entry->use_cnt = 1; - udp_tunnel_nic_entry_queue(utn, entry, - UDP_TUNNEL_NIC_ENTRY_ADD); - return true; - } - - /* The different table may still fit this port in, but there - * are no devices currently which have multiple tables accepting - * the same tunnel type, and false positives are okay. - */ - __set_bit(i, &utn->missed); - } - - return false; -} - -static void -__udp_tunnel_nic_add_port(struct net_device *dev, struct udp_tunnel_info *ti) -{ - const struct udp_tunnel_nic_info *info = dev->udp_tunnel_nic_info; - struct udp_tunnel_nic *utn; - - utn = dev->udp_tunnel_nic; - if (!utn) - return; - if (!netif_running(dev) && info->flags & UDP_TUNNEL_NIC_INFO_OPEN_ONLY) - return; - - if (!udp_tunnel_nic_is_capable(dev, utn, ti)) - return; - - /* It may happen that a tunnel of one type is removed and different - * tunnel type tries to reuse its port before the device was informed. - * Rely on utn->missed to re-add this port later. - */ - if (udp_tunnel_nic_has_collision(dev, utn, ti)) - return; - - if (!udp_tunnel_nic_add_existing(dev, utn, ti)) - udp_tunnel_nic_add_new(dev, utn, ti); - - udp_tunnel_nic_device_sync(dev, utn); -} - -static void -__udp_tunnel_nic_del_port(struct net_device *dev, struct udp_tunnel_info *ti) -{ - struct udp_tunnel_nic *utn; - - utn = dev->udp_tunnel_nic; - if (!utn) - return; - - if (!udp_tunnel_nic_is_capable(dev, utn, ti)) - return; - - udp_tunnel_nic_del_existing(dev, utn, ti); - - udp_tunnel_nic_device_sync(dev, utn); -} - -static void __udp_tunnel_nic_reset_ntf(struct net_device *dev) -{ - const struct udp_tunnel_nic_info *info = dev->udp_tunnel_nic_info; - struct udp_tunnel_nic *utn; - unsigned int i, j; - - ASSERT_RTNL(); - - utn = dev->udp_tunnel_nic; - if (!utn) - return; - - utn->need_sync = false; - for (i = 0; i < utn->n_tables; i++) - for (j = 0; j < info->tables[i].n_entries; j++) { - struct udp_tunnel_nic_table_entry *entry; - - entry = &utn->entries[i][j]; - - entry->flags &= ~(UDP_TUNNEL_NIC_ENTRY_DEL | - UDP_TUNNEL_NIC_ENTRY_OP_FAIL); - /* We don't release rtnl across ops */ - WARN_ON(entry->flags & UDP_TUNNEL_NIC_ENTRY_FROZEN); - if (!entry->use_cnt) - continue; - - udp_tunnel_nic_entry_queue(utn, entry, - UDP_TUNNEL_NIC_ENTRY_ADD); - } - - __udp_tunnel_nic_device_sync(dev, utn); -} - -static const struct udp_tunnel_nic_ops __udp_tunnel_nic_ops = { - .get_port = __udp_tunnel_nic_get_port, - .set_port_priv = __udp_tunnel_nic_set_port_priv, - .add_port = __udp_tunnel_nic_add_port, - .del_port = __udp_tunnel_nic_del_port, - .reset_ntf = __udp_tunnel_nic_reset_ntf, -}; - -static void -udp_tunnel_nic_flush(struct net_device *dev, struct udp_tunnel_nic *utn) -{ - const struct udp_tunnel_nic_info *info = dev->udp_tunnel_nic_info; - unsigned int i, j; - - for (i = 0; i < utn->n_tables; i++) - for (j = 0; j < info->tables[i].n_entries; j++) { - int adj_cnt = -utn->entries[i][j].use_cnt; - - if (adj_cnt) - udp_tunnel_nic_entry_adj(utn, i, j, adj_cnt); - } - - __udp_tunnel_nic_device_sync(dev, utn); - - for (i = 0; i < utn->n_tables; i++) - memset(utn->entries[i], 0, array_size(info->tables[i].n_entries, - sizeof(**utn->entries))); - WARN_ON(utn->need_sync); - utn->need_replay = 0; -} - -static void -udp_tunnel_nic_replay(struct net_device *dev, struct udp_tunnel_nic *utn) -{ - const struct udp_tunnel_nic_info *info = dev->udp_tunnel_nic_info; - unsigned int i, j; - - /* Freeze all the ports we are already tracking so that the replay - * does not double up the refcount. - */ - for (i = 0; i < utn->n_tables; i++) - for (j = 0; j < info->tables[i].n_entries; j++) - udp_tunnel_nic_entry_freeze_used(&utn->entries[i][j]); - utn->missed = 0; - utn->need_replay = 0; - - udp_tunnel_get_rx_info(dev); - - for (i = 0; i < utn->n_tables; i++) - for (j = 0; j < info->tables[i].n_entries; j++) - udp_tunnel_nic_entry_unfreeze(&utn->entries[i][j]); -} - -static void udp_tunnel_nic_device_sync_work(struct work_struct *work) -{ - struct udp_tunnel_nic *utn = - container_of(work, struct udp_tunnel_nic, work); - - rtnl_lock(); - utn->work_pending = 0; - __udp_tunnel_nic_device_sync(utn->dev, utn); - - if (utn->need_replay) - udp_tunnel_nic_replay(utn->dev, utn); - rtnl_unlock(); -} - -static struct udp_tunnel_nic * -udp_tunnel_nic_alloc(const struct udp_tunnel_nic_info *info, - unsigned int n_tables) -{ - struct udp_tunnel_nic *utn; - unsigned int i; - - utn = kzalloc(sizeof(*utn), GFP_KERNEL); - if (!utn) - return NULL; - utn->n_tables = n_tables; - INIT_WORK(&utn->work, udp_tunnel_nic_device_sync_work); - - utn->entries = kmalloc_array(n_tables, sizeof(void *), GFP_KERNEL); - if (!utn->entries) - goto err_free_utn; - - for (i = 0; i < n_tables; i++) { - utn->entries[i] = kcalloc(info->tables[i].n_entries, - sizeof(*utn->entries[i]), GFP_KERNEL); - if (!utn->entries[i]) - goto err_free_prev_entries; - } - - return utn; - -err_free_prev_entries: - while (i--) - kfree(utn->entries[i]); - kfree(utn->entries); -err_free_utn: - kfree(utn); - return NULL; -} - -static int udp_tunnel_nic_register(struct net_device *dev) -{ - const struct udp_tunnel_nic_info *info = dev->udp_tunnel_nic_info; - struct udp_tunnel_nic *utn; - unsigned int n_tables, i; - - BUILD_BUG_ON(sizeof(utn->missed) * BITS_PER_BYTE < - UDP_TUNNEL_NIC_MAX_TABLES); - - if (WARN_ON(!info->set_port != !info->unset_port) || - WARN_ON(!info->set_port == !info->sync_table) || - WARN_ON(!info->tables[0].n_entries)) - return -EINVAL; - - n_tables = 1; - for (i = 1; i < UDP_TUNNEL_NIC_MAX_TABLES; i++) { - if (!info->tables[i].n_entries) - continue; - - n_tables++; - if (WARN_ON(!info->tables[i - 1].n_entries)) - return -EINVAL; - } - - utn = udp_tunnel_nic_alloc(info, n_tables); - if (!utn) - return -ENOMEM; - - utn->dev = dev; - dev_hold(dev); - dev->udp_tunnel_nic = utn; - - if (!(info->flags & UDP_TUNNEL_NIC_INFO_OPEN_ONLY)) - udp_tunnel_get_rx_info(dev); - - return 0; -} - -static void -udp_tunnel_nic_unregister(struct net_device *dev, struct udp_tunnel_nic *utn) -{ - unsigned int i; - - /* Flush before we check work, so we don't waste time adding entries - * from the work which we will boot immediately. - */ - udp_tunnel_nic_flush(dev, utn); - - /* Wait for the work to be done using the state, netdev core will - * retry unregister until we give up our reference on this device. - */ - if (utn->work_pending) - return; - - for (i = 0; i < utn->n_tables; i++) - kfree(utn->entries[i]); - kfree(utn->entries); - kfree(utn); - dev->udp_tunnel_nic = NULL; - dev_put(dev); -} - -static int -udp_tunnel_nic_netdevice_event(struct notifier_block *unused, - unsigned long event, void *ptr) -{ - struct net_device *dev = netdev_notifier_info_to_dev(ptr); - const struct udp_tunnel_nic_info *info; - struct udp_tunnel_nic *utn; - - info = dev->udp_tunnel_nic_info; - if (!info) - return NOTIFY_DONE; - - if (event == NETDEV_REGISTER) { - int err; - - err = udp_tunnel_nic_register(dev); - if (err) - netdev_WARN(dev, "failed to register for UDP tunnel offloads: %d", err); - return notifier_from_errno(err); - } - /* All other events will need the udp_tunnel_nic state */ - utn = dev->udp_tunnel_nic; - if (!utn) - return NOTIFY_DONE; - - if (event == NETDEV_UNREGISTER) { - udp_tunnel_nic_unregister(dev, utn); - return NOTIFY_OK; - } - - /* All other events only matter if NIC has to be programmed open */ - if (!(info->flags & UDP_TUNNEL_NIC_INFO_OPEN_ONLY)) - return NOTIFY_DONE; - - if (event == NETDEV_UP) { - WARN_ON(!udp_tunnel_nic_is_empty(dev, utn)); - udp_tunnel_get_rx_info(dev); - return NOTIFY_OK; - } - if (event == NETDEV_GOING_DOWN) { - udp_tunnel_nic_flush(dev, utn); - return NOTIFY_OK; - } - - return NOTIFY_DONE; -} - -static struct notifier_block udp_tunnel_nic_notifier_block __read_mostly = { - .notifier_call = udp_tunnel_nic_netdevice_event, -}; - -static int __init udp_tunnel_nic_init_module(void) -{ - int err; - - udp_tunnel_nic_workqueue = alloc_workqueue("udp_tunnel_nic", 0, 0); - if (!udp_tunnel_nic_workqueue) - return -ENOMEM; - - rtnl_lock(); - udp_tunnel_nic_ops = &__udp_tunnel_nic_ops; - rtnl_unlock(); - - err = register_netdevice_notifier(&udp_tunnel_nic_notifier_block); - if (err) - goto err_unset_ops; - - return 0; - -err_unset_ops: - rtnl_lock(); - udp_tunnel_nic_ops = NULL; - rtnl_unlock(); - destroy_workqueue(udp_tunnel_nic_workqueue); - return err; -} -late_initcall(udp_tunnel_nic_init_module); - -static void __exit udp_tunnel_nic_cleanup_module(void) -{ - unregister_netdevice_notifier(&udp_tunnel_nic_notifier_block); - - rtnl_lock(); - udp_tunnel_nic_ops = NULL; - rtnl_unlock(); - - destroy_workqueue(udp_tunnel_nic_workqueue); -} -module_exit(udp_tunnel_nic_cleanup_module); - -MODULE_LICENSE("GPL"); diff --git a/net/ipv4/udp_tunnel_stub.c b/net/ipv4/udp_tunnel_stub.c deleted file mode 100644 index c4b2888f5fef..000000000000 --- a/net/ipv4/udp_tunnel_stub.c +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// Copyright (c) 2020 Facebook Inc. - -#include - -const struct udp_tunnel_nic_ops *udp_tunnel_nic_ops; -EXPORT_SYMBOL_GPL(udp_tunnel_nic_ops); diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c index 318d0111455d..804362353e85 100644 --- a/net/ipv6/addrconf.c +++ b/net/ipv6/addrconf.c @@ -208,7 +208,6 @@ static struct ipv6_devconf ipv6_devconf __read_mostly = { .accept_ra_defrtr = 1, .accept_ra_from_local = 0, .accept_ra_min_hop_limit= 1, - .accept_ra_min_lft = 0, .accept_ra_pinfo = 1, #ifdef CONFIG_IPV6_ROUTER_PREF .accept_ra_rtr_pref = 1, @@ -264,7 +263,6 @@ static struct ipv6_devconf ipv6_devconf_dflt __read_mostly = { .accept_ra_defrtr = 1, .accept_ra_from_local = 0, .accept_ra_min_hop_limit= 1, - .accept_ra_min_lft = 0, .accept_ra_pinfo = 1, #ifdef CONFIG_IPV6_ROUTER_PREF .accept_ra_rtr_pref = 1, @@ -2751,9 +2749,6 @@ void addrconf_prefix_rcv(struct net_device *dev, u8 *opt, int len, bool sllao) return; } - if (valid_lft != 0 && valid_lft < in6_dev->cnf.accept_ra_min_lft) - goto put; - /* * Two things going on here: * 1) Add routes for on-link prefixes @@ -3280,11 +3275,11 @@ static int ipv6_generate_stable_address(struct in6_addr *address, const struct inet6_dev *idev) { static DEFINE_SPINLOCK(lock); - static __u32 digest[SHA1_DIGEST_WORDS]; - static __u32 workspace[SHA1_WORKSPACE_WORDS]; + static __u32 digest[SHA_DIGEST_WORDS]; + static __u32 workspace[SHA_WORKSPACE_WORDS]; static union { - char __data[SHA1_BLOCK_SIZE]; + char __data[SHA_MESSAGE_BYTES]; struct { struct in6_addr secret; __be32 prefix[2]; @@ -3309,7 +3304,7 @@ static int ipv6_generate_stable_address(struct in6_addr *address, retry: spin_lock_bh(&lock); - sha1_init(digest); + sha_init(digest); memset(&data, 0, sizeof(data)); memset(workspace, 0, sizeof(workspace)); memcpy(data.hwaddr, idev->dev->perm_addr, idev->dev->addr_len); @@ -3318,7 +3313,7 @@ retry: data.secret = secret; data.dad_count = dad_count; - sha1_transform(digest, data.__data, workspace); + sha_transform(digest, data.__data, workspace); temp = *address; temp.s6_addr32[2] = (__force __be32)digest[0]; @@ -5552,7 +5547,6 @@ static inline void ipv6_store_devconf(struct ipv6_devconf *cnf, array[DEVCONF_ADDR_GEN_MODE] = cnf->addr_gen_mode; array[DEVCONF_DISABLE_POLICY] = cnf->disable_policy; array[DEVCONF_NDISC_TCLASS] = cnf->ndisc_tclass; - array[DEVCONF_ACCEPT_RA_MIN_LFT] = cnf->accept_ra_min_lft; } static inline size_t inet6_ifla6_size(void) @@ -6143,8 +6137,9 @@ static void ipv6_ifa_notify(int event, struct inet6_ifaddr *ifp) #ifdef CONFIG_SYSCTL -static int addrconf_sysctl_forward(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) +static +int addrconf_sysctl_forward(struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) { int *valp = ctl->data; int val = *valp; @@ -6168,8 +6163,9 @@ static int addrconf_sysctl_forward(struct ctl_table *ctl, int write, return ret; } -static int addrconf_sysctl_mtu(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) +static +int addrconf_sysctl_mtu(struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) { struct inet6_dev *idev = ctl->extra1; int min_mtu = IPV6_MIN_MTU; @@ -6239,8 +6235,9 @@ static int addrconf_disable_ipv6(struct ctl_table *table, int *p, int newf) return 0; } -static int addrconf_sysctl_disable(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) +static +int addrconf_sysctl_disable(struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) { int *valp = ctl->data; int val = *valp; @@ -6264,8 +6261,9 @@ static int addrconf_sysctl_disable(struct ctl_table *ctl, int write, return ret; } -static int addrconf_sysctl_proxy_ndp(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) +static +int addrconf_sysctl_proxy_ndp(struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) { int *valp = ctl->data; int ret; @@ -6306,7 +6304,7 @@ static int addrconf_sysctl_proxy_ndp(struct ctl_table *ctl, int write, } static int addrconf_sysctl_addr_gen_mode(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, + void __user *buffer, size_t *lenp, loff_t *ppos) { int ret = 0; @@ -6368,7 +6366,7 @@ out: } static int addrconf_sysctl_stable_secret(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, + void __user *buffer, size_t *lenp, loff_t *ppos) { int err; @@ -6435,7 +6433,8 @@ out: static int addrconf_sysctl_ignore_routes_with_linkdown(struct ctl_table *ctl, - int write, void *buffer, + int write, + void __user *buffer, size_t *lenp, loff_t *ppos) { @@ -6535,8 +6534,10 @@ int addrconf_disable_policy(struct ctl_table *ctl, int *valp, int val) return 0; } -static int addrconf_sysctl_disable_policy(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) +static +int addrconf_sysctl_disable_policy(struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos) { int *valp = ctl->data; int val = *valp; @@ -6720,13 +6721,6 @@ static const struct ctl_table addrconf_sysctl[] = { .mode = 0644, .proc_handler = proc_dointvec, }, - { - .procname = "accept_ra_min_lft", - .data = &ipv6_devconf.accept_ra_min_lft, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec, - }, { .procname = "accept_ra_pinfo", .data = &ipv6_devconf.accept_ra_pinfo, diff --git a/net/ipv6/af_inet6.c b/net/ipv6/af_inet6.c index 11dd9ec4fa14..d3312a054800 100644 --- a/net/ipv6/af_inet6.c +++ b/net/ipv6/af_inet6.c @@ -277,7 +277,7 @@ out_sk_release: } static int __inet6_bind(struct sock *sk, struct sockaddr *uaddr, int addr_len, - u32 flags) + bool force_bind_address_no_port, bool with_lock) { struct sockaddr_in6 *addr = (struct sockaddr_in6 *)uaddr; struct inet_sock *inet = inet_sk(sk); @@ -303,7 +303,7 @@ static int __inet6_bind(struct sock *sk, struct sockaddr *uaddr, int addr_len, !ns_capable(net->user_ns, CAP_NET_BIND_SERVICE)) return -EACCES; - if (flags & BIND_WITH_LOCK) + if (with_lock) lock_sock(sk); /* Check these errors (active socket, double bind). */ @@ -406,20 +406,18 @@ static int __inet6_bind(struct sock *sk, struct sockaddr *uaddr, int addr_len, /* Make sure we are allowed to bind here. */ if (snum || !(inet->bind_address_no_port || - (flags & BIND_FORCE_ADDRESS_NO_PORT))) { + force_bind_address_no_port)) { if (sk->sk_prot->get_port(sk, snum)) { sk->sk_ipv6only = saved_ipv6only; inet_reset_saddr(sk); err = -EADDRINUSE; goto out; } - if (!(flags & BIND_FROM_BPF)) { - err = BPF_CGROUP_RUN_PROG_INET6_POST_BIND(sk); - if (err) { - sk->sk_ipv6only = saved_ipv6only; - inet_reset_saddr(sk); - goto out; - } + err = BPF_CGROUP_RUN_PROG_INET6_POST_BIND(sk); + if (err) { + sk->sk_ipv6only = saved_ipv6only; + inet_reset_saddr(sk); + goto out; } } @@ -431,7 +429,7 @@ static int __inet6_bind(struct sock *sk, struct sockaddr *uaddr, int addr_len, inet->inet_dport = 0; inet->inet_daddr = 0; out: - if (flags & BIND_WITH_LOCK) + if (with_lock) release_sock(sk); return err; out_unlock: @@ -462,7 +460,7 @@ int inet6_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len) if (err) return err; - return __inet6_bind(sk, uaddr, addr_len, BIND_WITH_LOCK); + return __inet6_bind(sk, uaddr, addr_len, false, true); } EXPORT_SYMBOL(inet6_bind); @@ -519,8 +517,9 @@ EXPORT_SYMBOL_GPL(inet6_cleanup_sock); /* * This does both peername and sockname. */ + int inet6_getname(struct socket *sock, struct sockaddr *uaddr, - int peer) + int peer) { struct sockaddr_in6 *sin = (struct sockaddr_in6 *)uaddr; struct sock *sk = sock->sk; @@ -545,13 +544,9 @@ int inet6_getname(struct socket *sock, struct sockaddr *uaddr, sin->sin6_addr = np->saddr; else sin->sin6_addr = sk->sk_v6_rcv_saddr; + sin->sin6_port = inet->inet_sport; } - if (cgroup_bpf_enabled) - BPF_CGROUP_RUN_SA_PROG_LOCK(sk, (struct sockaddr *)sin, - peer ? BPF_CGROUP_INET6_GETPEERNAME : - BPF_CGROUP_INET6_GETSOCKNAME, - NULL); sin->sin6_scope_id = ipv6_iface_scope_id(&sin->sin6_addr, sk->sk_bound_dev_if); return sizeof(*sin); diff --git a/net/ipv6/ah6.c b/net/ipv6/ah6.c index 240f46c7ce1e..1c5ecd07a43e 100644 --- a/net/ipv6/ah6.c +++ b/net/ipv6/ah6.c @@ -46,34 +46,6 @@ struct ah_skb_cb { #define AH_SKB_CB(__skb) ((struct ah_skb_cb *)&((__skb)->cb[0])) -/* Helper to save IPv6 addresses and extension headers to temporary storage */ -static inline void ah6_save_hdrs(struct tmp_ext *iph_ext, - struct ipv6hdr *top_iph, int extlen) -{ - if (!extlen) - return; - -#if IS_ENABLED(CONFIG_IPV6_MIP6) - iph_ext->saddr = top_iph->saddr; -#endif - iph_ext->daddr = top_iph->daddr; - memcpy(&iph_ext->hdrs, top_iph + 1, extlen - sizeof(*iph_ext)); -} - -/* Helper to restore IPv6 addresses and extension headers from temporary storage */ -static inline void ah6_restore_hdrs(struct ipv6hdr *top_iph, - struct tmp_ext *iph_ext, int extlen) -{ - if (!extlen) - return; - -#if IS_ENABLED(CONFIG_IPV6_MIP6) - top_iph->saddr = iph_ext->saddr; -#endif - top_iph->daddr = iph_ext->daddr; - memcpy(top_iph + 1, &iph_ext->hdrs, extlen - sizeof(*iph_ext)); -} - static void *ah_alloc_tmp(struct crypto_ahash *ahash, int nfrags, unsigned int size) { @@ -335,7 +307,13 @@ static void ah6_output_done(struct crypto_async_request *base, int err) memcpy(ah->auth_data, icv, ahp->icv_trunc_len); memcpy(top_iph, iph_base, IPV6HDR_BASELEN); - ah6_restore_hdrs(top_iph, iph_ext, extlen); + if (extlen) { +#if IS_ENABLED(CONFIG_IPV6_MIP6) + memcpy(&top_iph->saddr, iph_ext, extlen); +#else + memcpy(&top_iph->daddr, iph_ext, extlen); +#endif + } kfree(AH_SKB_CB(skb)->tmp); xfrm_output_resume(skb, err); @@ -406,8 +384,12 @@ static int ah6_output(struct xfrm_state *x, struct sk_buff *skb) */ memcpy(iph_base, top_iph, IPV6HDR_BASELEN); - ah6_save_hdrs(iph_ext, top_iph, extlen); if (extlen) { +#if IS_ENABLED(CONFIG_IPV6_MIP6) + memcpy(iph_ext, &top_iph->saddr, extlen); +#else + memcpy(iph_ext, &top_iph->daddr, extlen); +#endif err = ipv6_clear_mutable_options(top_iph, extlen - sizeof(*iph_ext) + sizeof(*top_iph), @@ -458,7 +440,13 @@ static int ah6_output(struct xfrm_state *x, struct sk_buff *skb) memcpy(ah->auth_data, icv, ahp->icv_trunc_len); memcpy(top_iph, iph_base, IPV6HDR_BASELEN); - ah6_restore_hdrs(top_iph, iph_ext, extlen); + if (extlen) { +#if IS_ENABLED(CONFIG_IPV6_MIP6) + memcpy(&top_iph->saddr, iph_ext, extlen); +#else + memcpy(&top_iph->daddr, iph_ext, extlen); +#endif + } out_free: kfree(iph_base); diff --git a/net/ipv6/icmp.c b/net/ipv6/icmp.c index 012cadd47f43..169467b5c98a 100644 --- a/net/ipv6/icmp.c +++ b/net/ipv6/icmp.c @@ -639,9 +639,6 @@ int ip6_err_gen_icmpv6_unreach(struct sk_buff *skb, int nhs, int type, if (!skb2) return 1; - /* Remove debris left by IPv4 stack. */ - memset(IP6CB(skb2), 0, sizeof(*IP6CB(skb2))); - skb_dst_drop(skb2); skb_pull(skb2, nhs); skb_reset_network_header(skb2); diff --git a/net/ipv6/ila/ila_common.c b/net/ipv6/ila/ila_common.c index b8d43ed4689d..95e9146918cc 100644 --- a/net/ipv6/ila/ila_common.c +++ b/net/ipv6/ila/ila_common.c @@ -86,7 +86,7 @@ static void ila_csum_adjust_transport(struct sk_buff *skb, diff = get_csum_diff(ip6h, p); inet_proto_csum_replace_by_diff(&th->check, skb, - diff, true, true); + diff, true); } break; case NEXTHDR_UDP: @@ -97,7 +97,7 @@ static void ila_csum_adjust_transport(struct sk_buff *skb, if (uh->check || skb->ip_summed == CHECKSUM_PARTIAL) { diff = get_csum_diff(ip6h, p); inet_proto_csum_replace_by_diff(&uh->check, skb, - diff, true, true); + diff, true); if (!uh->check) uh->check = CSUM_MANGLED_0; } @@ -111,7 +111,7 @@ static void ila_csum_adjust_transport(struct sk_buff *skb, diff = get_csum_diff(ip6h, p); inet_proto_csum_replace_by_diff(&ih->icmp6_cksum, skb, - diff, true, true); + diff, true); } break; } diff --git a/net/ipv6/inet6_hashtables.c b/net/ipv6/inet6_hashtables.c index 964eef05fe32..528c78bc920e 100644 --- a/net/ipv6/inet6_hashtables.c +++ b/net/ipv6/inet6_hashtables.c @@ -21,8 +21,6 @@ #include #include -extern struct inet_hashinfo tcp_hashinfo; - u32 inet6_ehashfn(const struct net *net, const struct in6_addr *laddr, const u16 lport, const struct in6_addr *faddr, const __be16 fport) @@ -113,24 +111,6 @@ static inline int compute_score(struct sock *sk, struct net *net, return score; } -struct sock *inet6_lookup_reuseport(struct net *net, struct sock *sk, - struct sk_buff *skb, int doff, - const struct in6_addr *saddr, - __be16 sport, - const struct in6_addr *daddr, - unsigned short hnum) -{ - struct sock *reuse_sk = NULL; - u32 phash; - - if (sk->sk_reuseport) { - phash = inet6_ehashfn(net, daddr, hnum, saddr, sport); - reuse_sk = reuseport_select_sock(sk, phash, skb, doff); - } - return reuse_sk; -} -EXPORT_SYMBOL_GPL(inet6_lookup_reuseport); - /* called with rcu_read_lock() */ static struct sock *inet6_lhash2_lookup(struct net *net, struct inet_listen_hashbucket *ilb2, @@ -143,17 +123,21 @@ static struct sock *inet6_lhash2_lookup(struct net *net, struct inet_connection_sock *icsk; struct sock *sk, *result = NULL; int score, hiscore = 0; + u32 phash = 0; inet_lhash2_for_each_icsk_rcu(icsk, &ilb2->head) { sk = (struct sock *)icsk; score = compute_score(sk, net, hnum, daddr, dif, sdif, exact_dif); if (score > hiscore) { - result = inet6_lookup_reuseport(net, sk, skb, doff, - saddr, sport, daddr, hnum); - if (result) - return result; - + if (sk->sk_reuseport) { + phash = inet6_ehashfn(net, daddr, hnum, + saddr, sport); + result = reuseport_select_sock(sk, phash, + skb, doff); + if (result) + return result; + } result = sk; hiscore = score; } @@ -162,31 +146,6 @@ static struct sock *inet6_lhash2_lookup(struct net *net, return result; } -static inline struct sock *inet6_lookup_run_bpf(struct net *net, - struct inet_hashinfo *hashinfo, - struct sk_buff *skb, int doff, - const struct in6_addr *saddr, - const __be16 sport, - const struct in6_addr *daddr, - const u16 hnum) -{ - struct sock *sk, *reuse_sk; - bool no_reuseport; - - if (hashinfo != &tcp_hashinfo) - return NULL; /* only TCP is supported */ - - no_reuseport = bpf_sk_lookup_run_v6(net, IPPROTO_TCP, - saddr, sport, daddr, hnum, &sk); - if (no_reuseport || IS_ERR_OR_NULL(sk)) - return sk; - - reuse_sk = inet6_lookup_reuseport(net, sk, skb, doff, saddr, sport, daddr, hnum); - if (reuse_sk) - sk = reuse_sk; - return sk; -} - struct sock *inet6_lookup_listener(struct net *net, struct inet_hashinfo *hashinfo, struct sk_buff *skb, int doff, @@ -198,14 +157,6 @@ struct sock *inet6_lookup_listener(struct net *net, struct sock *result = NULL; unsigned int hash2; - /* Lookup redirect from BPF */ - if (static_branch_unlikely(&bpf_sk_lookup_enabled)) { - result = inet6_lookup_run_bpf(net, hashinfo, skb, doff, - saddr, sport, daddr, hnum); - if (result) - goto done; - } - hash2 = ipv6_portaddr_hash(net, daddr, hnum); ilb2 = inet_lhash2_bucket(hashinfo, hash2); diff --git a/net/ipv6/ip6_fib.c b/net/ipv6/ip6_fib.c index 17bf27ee8349..ef1df9d662d6 100644 --- a/net/ipv6/ip6_fib.c +++ b/net/ipv6/ip6_fib.c @@ -2376,7 +2376,7 @@ void fib6_gc_cleanup(void) } #ifdef CONFIG_PROC_FS -static int ipv6_route_native_seq_show(struct seq_file *seq, void *v) +static int ipv6_route_seq_show(struct seq_file *seq, void *v) { struct fib6_info *rt = v; struct ipv6_route_iter *iter = seq->private; @@ -2538,7 +2538,7 @@ static bool ipv6_route_iter_active(struct ipv6_route_iter *iter) return w->node && !(w->state == FWS_U && w->node == w->root); } -static void ipv6_route_native_seq_stop(struct seq_file *seq, void *v) +static void ipv6_route_seq_stop(struct seq_file *seq, void *v) __releases(RCU_BH) { struct net *net = seq_file_net(seq); @@ -2550,62 +2550,6 @@ static void ipv6_route_native_seq_stop(struct seq_file *seq, void *v) rcu_read_unlock_bh(); } -#if IS_BUILTIN(CONFIG_IPV6) && defined(CONFIG_BPF_SYSCALL) -static int ipv6_route_prog_seq_show(struct bpf_prog *prog, - struct bpf_iter_meta *meta, - void *v) -{ - struct bpf_iter__ipv6_route ctx; - - ctx.meta = meta; - ctx.rt = v; - return bpf_iter_run_prog(prog, &ctx); -} - -static int ipv6_route_seq_show(struct seq_file *seq, void *v) -{ - struct ipv6_route_iter *iter = seq->private; - struct bpf_iter_meta meta; - struct bpf_prog *prog; - int ret; - - meta.seq = seq; - prog = bpf_iter_get_info(&meta, false); - if (!prog) - return ipv6_route_native_seq_show(seq, v); - - ret = ipv6_route_prog_seq_show(prog, &meta, v); - iter->w.leaf = NULL; - - return ret; -} - -static void ipv6_route_seq_stop(struct seq_file *seq, void *v) -{ - struct bpf_iter_meta meta; - struct bpf_prog *prog; - - if (!v) { - meta.seq = seq; - prog = bpf_iter_get_info(&meta, true); - if (prog) - (void)ipv6_route_prog_seq_show(prog, &meta, v); - } - - ipv6_route_native_seq_stop(seq, v); -} -#else -static int ipv6_route_seq_show(struct seq_file *seq, void *v) -{ - return ipv6_route_native_seq_show(seq, v); -} - -static void ipv6_route_seq_stop(struct seq_file *seq, void *v) -{ - ipv6_route_native_seq_stop(seq, v); -} -#endif - const struct seq_operations ipv6_route_seq_ops = { .start = ipv6_route_seq_start, .next = ipv6_route_seq_next, diff --git a/net/ipv6/ip6_input.c b/net/ipv6/ip6_input.c index 4d857d44060d..ebf90bce063a 100644 --- a/net/ipv6/ip6_input.c +++ b/net/ipv6/ip6_input.c @@ -257,8 +257,7 @@ static struct sk_buff *ip6_rcv_core(struct sk_buff *skb, struct net_device *dev, rcu_read_unlock(); /* Must drop socket now because of tproxy. */ - if (!skb_sk_is_prefetched(skb)) - skb_orphan(skb); + skb_orphan(skb); return skb; err: diff --git a/net/ipv6/ip6_tunnel.c b/net/ipv6/ip6_tunnel.c index 604a6c018b2b..5319093d9aa6 100644 --- a/net/ipv6/ip6_tunnel.c +++ b/net/ipv6/ip6_tunnel.c @@ -601,16 +601,11 @@ ip4ip6_err(struct sk_buff *skb, struct inet6_skb_parm *opt, if (!skb2) return 0; - /* Remove debris left by IPv6 stack. */ - memset(IPCB(skb2), 0, sizeof(*IPCB(skb2))); - skb_dst_drop(skb2); skb_pull(skb2, offset); skb_reset_network_header(skb2); eiph = ip_hdr(skb2); - if (eiph->version != 4 || eiph->ihl < 5) - goto out; /* Try to guess incoming interface */ rt = ip_route_output_ports(dev_net(skb->dev), &fl4, NULL, eiph->saddr, @@ -1206,7 +1201,8 @@ route_lookup: */ max_headroom = LL_RESERVED_SPACE(dst->dev) + sizeof(struct ipv6hdr) + dst->header_len + t->hlen; - ip_tunnel_adj_headroom(dev, max_headroom); + if (max_headroom > READ_ONCE(dev->needed_headroom)) + WRITE_ONCE(dev->needed_headroom, max_headroom); err = ip6_tnl_encap(skb, t, &proto, fl6); if (err) diff --git a/net/ipv6/ip6_udp_tunnel.c b/net/ipv6/ip6_udp_tunnel.c index d056412a396a..58956a6b66a2 100644 --- a/net/ipv6/ip6_udp_tunnel.c +++ b/net/ipv6/ip6_udp_tunnel.c @@ -33,7 +33,9 @@ int udp_sock_create6(struct net *net, struct udp_port_cfg *cfg, goto error; } if (cfg->bind_ifindex) { - err = sock_bindtoindex(sock->sk, cfg->bind_ifindex, true); + err = kernel_setsockopt(sock, SOL_SOCKET, SO_BINDTOIFINDEX, + (void *)&cfg->bind_ifindex, + sizeof(cfg->bind_ifindex)); if (err < 0) goto error; } diff --git a/net/ipv6/ipv6_sockglue.c b/net/ipv6/ipv6_sockglue.c index 10f0df90a106..1ceb6de0152f 100644 --- a/net/ipv6/ipv6_sockglue.c +++ b/net/ipv6/ipv6_sockglue.c @@ -464,7 +464,7 @@ static int do_ipv6_setsockopt(struct sock *sk, int level, int optname, struct ipv6_sr_hdr *srh = (struct ipv6_sr_hdr *) opt->srcrt; - if (!seg6_validate_srh(srh, optlen, false)) + if (!seg6_validate_srh(srh, optlen)) goto sticky_done; break; } diff --git a/net/ipv6/ndisc.c b/net/ipv6/ndisc.c index 653e5bc7f047..c7e034b22d12 100644 --- a/net/ipv6/ndisc.c +++ b/net/ipv6/ndisc.c @@ -1271,14 +1271,6 @@ static void ndisc_router_discovery(struct sk_buff *skb) goto skip_defrtr; } - lifetime = ntohs(ra_msg->icmph.icmp6_rt_lifetime); - if (lifetime != 0 && lifetime < in6_dev->cnf.accept_ra_min_lft) { - ND_PRINTK(2, info, - "RA: router lifetime (%ds) is too short: %s\n", - lifetime, skb->dev->name); - goto skip_defrtr; - } - /* Do not accept RA with source-addr found on local machine unless * accept_ra_from_local is set to true. */ @@ -1291,6 +1283,8 @@ static void ndisc_router_discovery(struct sk_buff *skb) goto skip_defrtr; } + lifetime = ntohs(ra_msg->icmph.icmp6_rt_lifetime); + #ifdef CONFIG_IPV6_ROUTER_PREF pref = ra_msg->icmph.icmp6_router_pref; /* 10b is handled as if it were 00b (medium) */ @@ -1461,9 +1455,6 @@ skip_linkparms: if (ri->prefix_len == 0 && !in6_dev->cnf.accept_ra_defrtr) continue; - if (ri->lifetime != 0 && - ntohl(ri->lifetime) < in6_dev->cnf.accept_ra_min_lft) - continue; if (ri->prefix_len < in6_dev->cnf.accept_ra_rt_info_min_plen) continue; if (ri->prefix_len > in6_dev->cnf.accept_ra_rt_info_max_plen) @@ -1849,8 +1840,7 @@ static void ndisc_warn_deprecated_sysctl(struct ctl_table *ctl, } } -int ndisc_ifinfo_sysctl_change(struct ctl_table *ctl, int write, void *buffer, - size_t *lenp, loff_t *ppos) +int ndisc_ifinfo_sysctl_change(struct ctl_table *ctl, int write, void __user *buffer, size_t *lenp, loff_t *ppos) { struct net_device *dev = ctl->extra1; struct inet6_dev *idev; diff --git a/net/ipv6/netfilter/Kconfig b/net/ipv6/netfilter/Kconfig index 2e45c75da225..69443e9a3aa5 100644 --- a/net/ipv6/netfilter/Kconfig +++ b/net/ipv6/netfilter/Kconfig @@ -128,9 +128,9 @@ config IP6_NF_MATCH_HL depends on NETFILTER_ADVANCED select NETFILTER_XT_MATCH_HL ---help--- - This is a backwards-compat option for the user's convenience - (e.g. when running oldconfig). It selects - CONFIG_NETFILTER_XT_MATCH_HL. + This is a backwards-compat option for the user's convenience + (e.g. when running oldconfig). It selects + CONFIG_NETFILTER_XT_MATCH_HL. config IP6_NF_MATCH_IPV6HEADER tristate '"ipv6header" IPv6 Extension Headers Match' @@ -184,9 +184,9 @@ config IP6_NF_TARGET_HL depends on NETFILTER_ADVANCED && IP6_NF_MANGLE select NETFILTER_XT_TARGET_HL ---help--- - This is a backwards-compatible option for the user's convenience - (e.g. when running oldconfig). It selects - CONFIG_NETFILTER_XT_TARGET_HL. + This is a backwards-compatible option for the user's convenience + (e.g. when running oldconfig). It selects + CONFIG_NETFILTER_XT_TARGET_HL. config IP6_NF_FILTER tristate "Packet filtering" diff --git a/net/ipv6/raw.c b/net/ipv6/raw.c index 90d828c98b73..731485b18de3 100644 --- a/net/ipv6/raw.c +++ b/net/ipv6/raw.c @@ -474,7 +474,7 @@ static int rawv6_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, if (flags & MSG_ERRQUEUE) return ipv6_recv_error(sk, msg, len, addr_len); - if (np->rxopt.bits.rxpmtu && READ_ONCE(np->rxpmtu)) + if (np->rxpmtu && np->rxopt.bits.rxpmtu) return ipv6_recv_rxpmtu(sk, msg, len, addr_len); skb = skb_recv_datagram(sk, flags, noblock, &err); diff --git a/net/ipv6/route.c b/net/ipv6/route.c index 9036440a7a2d..13359f2dc3cf 100644 --- a/net/ipv6/route.c +++ b/net/ipv6/route.c @@ -62,7 +62,6 @@ #include #include #include -#include #ifdef CONFIG_SYSCTL #include @@ -6104,8 +6103,9 @@ static int rt6_stats_seq_show(struct seq_file *seq, void *v) #ifdef CONFIG_SYSCTL -static int ipv6_sysctl_rtcache_flush(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) +static +int ipv6_sysctl_rtcache_flush(struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) { struct net *net; int delay; @@ -6408,43 +6408,6 @@ void __init ip6_route_init_special_entries(void) #endif } -#if IS_BUILTIN(CONFIG_IPV6) -#if defined(CONFIG_BPF_SYSCALL) && defined(CONFIG_PROC_FS) -DEFINE_BPF_ITER_FUNC(ipv6_route, struct bpf_iter_meta *meta, struct fib6_info *rt) - -BTF_ID_LIST(btf_fib6_info_id) -BTF_ID(struct, fib6_info) - -static const struct bpf_iter_seq_info ipv6_route_seq_info = { - .seq_ops = &ipv6_route_seq_ops, - .init_seq_private = bpf_iter_init_seq_net, - .fini_seq_private = bpf_iter_fini_seq_net, - .seq_priv_size = sizeof(struct ipv6_route_iter), -}; - -static struct bpf_iter_reg ipv6_route_reg_info = { - .target = "ipv6_route", - .ctx_arg_info_size = 1, - .ctx_arg_info = { - { offsetof(struct bpf_iter__ipv6_route, rt), - PTR_TO_BTF_ID_OR_NULL }, - }, - .seq_info = &ipv6_route_seq_info, -}; - -static int __init bpf_iter_register(void) -{ - ipv6_route_reg_info.ctx_arg_info[0].btf_id = *btf_fib6_info_id; - return bpf_iter_reg_target(&ipv6_route_reg_info); -} - -static void bpf_iter_unregister(void) -{ - bpf_iter_unreg_target(&ipv6_route_reg_info); -} -#endif -#endif - int __init ip6_route_init(void) { int ret; @@ -6507,14 +6470,6 @@ int __init ip6_route_init(void) if (ret) goto out_register_late_subsys; -#if IS_BUILTIN(CONFIG_IPV6) -#if defined(CONFIG_BPF_SYSCALL) && defined(CONFIG_PROC_FS) - ret = bpf_iter_register(); - if (ret) - goto out_register_late_subsys; -#endif -#endif - for_each_possible_cpu(cpu) { struct uncached_list *ul = per_cpu_ptr(&rt6_uncached_list, cpu); @@ -6547,11 +6502,6 @@ out_kmem_cache: void ip6_route_cleanup(void) { -#if IS_BUILTIN(CONFIG_IPV6) -#if defined(CONFIG_BPF_SYSCALL) && defined(CONFIG_PROC_FS) - bpf_iter_unregister(); -#endif -#endif unregister_netdevice_notifier(&ip6_route_dev_notifier); unregister_pernet_subsys(&ip6_route_net_late_ops); fib6_rules_cleanup(); diff --git a/net/ipv6/seg6.c b/net/ipv6/seg6.c index 166bd2f06ce6..896281692543 100644 --- a/net/ipv6/seg6.c +++ b/net/ipv6/seg6.c @@ -25,11 +25,10 @@ #include #endif -bool seg6_validate_srh(struct ipv6_sr_hdr *srh, int len, bool reduced) +bool seg6_validate_srh(struct ipv6_sr_hdr *srh, int len) { - unsigned int tlv_offset; - int max_last_entry; int trailing; + unsigned int tlv_offset; if (srh->type != IPV6_SRCRT_TYPE_4) return false; @@ -37,17 +36,8 @@ bool seg6_validate_srh(struct ipv6_sr_hdr *srh, int len, bool reduced) if (((srh->hdrlen + 1) << 3) != len) return false; - if (!reduced && srh->segments_left > srh->first_segment) { + if (srh->segments_left > srh->first_segment) return false; - } else { - max_last_entry = (srh->hdrlen / 2) - 1; - - if (srh->first_segment > max_last_entry) - return false; - - if (srh->segments_left > srh->first_segment + 1) - return false; - } tlv_offset = sizeof(*srh) + ((srh->first_segment + 1) << 4); diff --git a/net/ipv6/seg6_iptunnel.c b/net/ipv6/seg6_iptunnel.c index 0a4175f18b5b..185b9db0b575 100644 --- a/net/ipv6/seg6_iptunnel.c +++ b/net/ipv6/seg6_iptunnel.c @@ -435,7 +435,7 @@ static int seg6_build_state(struct nlattr *nla, } /* verify that SRH is consistent */ - if (!seg6_validate_srh(tuninfo->srh, tuninfo_len - sizeof(*tuninfo), false)) + if (!seg6_validate_srh(tuninfo->srh, tuninfo_len - sizeof(*tuninfo))) return -EINVAL; newts = lwtunnel_state_alloc(tuninfo_len + sizeof(*slwt)); diff --git a/net/ipv6/seg6_local.c b/net/ipv6/seg6_local.c index 2f8deabf7c17..ef5b5cee2201 100644 --- a/net/ipv6/seg6_local.c +++ b/net/ipv6/seg6_local.c @@ -87,7 +87,7 @@ static struct ipv6_sr_hdr *get_srh(struct sk_buff *skb) */ srh = (struct ipv6_sr_hdr *)(skb->data + srhoff); - if (!seg6_validate_srh(srh, len, true)) + if (!seg6_validate_srh(srh, len)) return NULL; return srh; @@ -479,7 +479,7 @@ bool seg6_bpf_has_valid_srh(struct sk_buff *skb) return false; srh->hdrlen = (u8)(srh_state->hdrlen >> 3); - if (!seg6_validate_srh(srh, (srh->hdrlen + 1) << 3, true)) + if (!seg6_validate_srh(srh, (srh->hdrlen + 1) << 3)) return false; srh_state->valid = true; @@ -654,7 +654,7 @@ static int parse_nla_srh(struct nlattr **attrs, struct seg6_local_lwt *slwt) if (len < sizeof(*srh) + sizeof(struct in6_addr)) return -EINVAL; - if (!seg6_validate_srh(srh, len, false)) + if (!seg6_validate_srh(srh, len)) return -EINVAL; slwt->srh = kmemdup(srh, len, GFP_KERNEL); diff --git a/net/ipv6/sysctl_net_ipv6.c b/net/ipv6/sysctl_net_ipv6.c index 951f231f9fce..73842054bfe6 100644 --- a/net/ipv6/sysctl_net_ipv6.c +++ b/net/ipv6/sysctl_net_ipv6.c @@ -27,7 +27,8 @@ static int auto_flowlabels_min; static int auto_flowlabels_max = IP6_AUTO_FLOW_LABEL_MAX; static int proc_rt6_multipath_hash_policy(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { struct net *net; int ret; diff --git a/net/ipv6/tcp_ipv6.c b/net/ipv6/tcp_ipv6.c index b217a87d840c..971109454890 100644 --- a/net/ipv6/tcp_ipv6.c +++ b/net/ipv6/tcp_ipv6.c @@ -505,8 +505,7 @@ static int tcp_v6_send_synack(const struct sock *sk, struct dst_entry *dst, struct flowi *fl, struct request_sock *req, struct tcp_fastopen_cookie *foc, - enum tcp_synack_type synack_type, - struct sk_buff *syn_skb) + enum tcp_synack_type synack_type) { struct inet_request_sock *ireq = inet_rsk(req); struct ipv6_pinfo *np = tcp_inet6_sk(sk); @@ -520,7 +519,7 @@ static int tcp_v6_send_synack(const struct sock *sk, struct dst_entry *dst, IPPROTO_TCP)) == NULL) goto done; - skb = tcp_make_synack(sk, dst, req, foc, synack_type, syn_skb); + skb = tcp_make_synack(sk, dst, req, foc, synack_type); if (skb) { __tcp_v6_send_check(skb, &ireq->ir_v6_loc_addr, diff --git a/net/ipv6/udp.c b/net/ipv6/udp.c index bf9153beec8e..e7c43c69687b 100644 --- a/net/ipv6/udp.c +++ b/net/ipv6/udp.c @@ -162,7 +162,7 @@ static struct sock *udp6_lib_lookup2(struct net *net, int dif, int sdif, struct udp_hslot *hslot2, struct sk_buff *skb) { - struct sock *sk, *result; + struct sock *sk, *result, *reuseport_result; int score, badness; u32 hash = 0; @@ -172,17 +172,20 @@ static struct sock *udp6_lib_lookup2(struct net *net, score = compute_score(sk, net, saddr, sport, daddr, hnum, dif, sdif); if (score > badness) { + reuseport_result = NULL; + if (sk->sk_reuseport && sk->sk_state != TCP_ESTABLISHED) { hash = udp6_ehashfn(net, daddr, hnum, saddr, sport); - result = reuseport_select_sock(sk, hash, skb, - sizeof(struct udphdr)); - if (result && !reuseport_has_conns(sk, false)) - return result; + reuseport_result = reuseport_select_sock(sk, hash, skb, + sizeof(struct udphdr)); + if (reuseport_result && !reuseport_has_conns(sk, false)) + return reuseport_result; } - result = sk; + + result = reuseport_result ? : sk; badness = score; } } @@ -294,7 +297,7 @@ int udpv6_recvmsg(struct sock *sk, struct msghdr *msg, size_t len, if (flags & MSG_ERRQUEUE) return ipv6_recv_error(sk, msg, len, addr_len); - if (np->rxopt.bits.rxpmtu && READ_ONCE(np->rxpmtu)) + if (np->rxpmtu && np->rxopt.bits.rxpmtu) return ipv6_recv_rxpmtu(sk, msg, len, addr_len); try_again: @@ -858,7 +861,6 @@ int __udp6_lib_rcv(struct sk_buff *skb, struct udp_table *udptable, struct net *net = dev_net(skb->dev); struct udphdr *uh; struct sock *sk; - bool refcounted; u32 ulen = 0; if (!pskb_may_pull(skb, sizeof(struct udphdr))) @@ -895,7 +897,7 @@ int __udp6_lib_rcv(struct sk_buff *skb, struct udp_table *udptable, goto csum_error; /* Check if the socket is already available, e.g. due to early demux */ - sk = skb_steal_sock(skb, &refcounted); + sk = skb_steal_sock(skb); if (sk) { struct dst_entry *dst = skb_dst(skb); int ret; @@ -904,14 +906,12 @@ int __udp6_lib_rcv(struct sk_buff *skb, struct udp_table *udptable, udp6_sk_rx_dst_set(sk, dst); if (!uh->check && !udp_sk(sk)->no_check6_rx) { - if (refcounted) - sock_put(sk); + sock_put(sk); goto report_csum_error; } ret = udp6_unicast_rcv_skb(sk, skb, uh); - if (refcounted) - sock_put(sk); + sock_put(sk); return ret; } @@ -1583,8 +1583,7 @@ int udpv6_setsockopt(struct sock *sk, int level, int optname, char __user *optval, unsigned int optlen) { if (level == SOL_UDP || level == SOL_UDPLITE) - return udp_lib_setsockopt(sk, level, optname, - USER_SOCKPTR(optval), optlen, + return udp_lib_setsockopt(sk, level, optname, optval, optlen, udp_v6_push_pending_frames); return ipv6_setsockopt(sk, level, optname, optval, optlen); } @@ -1594,7 +1593,7 @@ int compat_udpv6_setsockopt(struct sock *sk, int level, int optname, char __user *optval, unsigned int optlen) { if (level == SOL_UDP || level == SOL_UDPLITE) - return udp_lib_setsockopt(sk, level, optname, USER_SOCKPTR(optval), optlen, + return udp_lib_setsockopt(sk, level, optname, optval, optlen, udp_v6_push_pending_frames); return compat_ipv6_setsockopt(sk, level, optname, optval, optlen); } diff --git a/net/mac80211/rx.c b/net/mac80211/rx.c index f62bc2705fb1..727aa7f644ff 100644 --- a/net/mac80211/rx.c +++ b/net/mac80211/rx.c @@ -4669,14 +4669,10 @@ void ieee80211_rx_napi(struct ieee80211_hw *hw, struct ieee80211_sta *pubsta, if (WARN_ON(!local->started)) goto drop; - if (likely(!(status->flag & RX_FLAG_FAILED_PLCP_CRC) && - !(status->flag & RX_FLAG_NO_PSDU && - status->zero_length_psdu_type == - IEEE80211_RADIOTAP_ZERO_LEN_PSDU_NOT_CAPTURED))) { + if (likely(!(status->flag & RX_FLAG_FAILED_PLCP_CRC))) { /* - * Validate the rate, unless there was a PLCP error which may - * have an invalid rate or the PSDU was not capture and may be - * missing rate information. + * Validate the rate, unless a PLCP error means that + * we probably can't have a valid rate here anyway. */ switch (status->encoding) { diff --git a/net/mpls/af_mpls.c b/net/mpls/af_mpls.c index 11c26f09db64..bac87a6b7e5b 100644 --- a/net/mpls/af_mpls.c +++ b/net/mpls/af_mpls.c @@ -1362,7 +1362,8 @@ done: (&((struct mpls_dev *)0)->field) static int mpls_conf_proc(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { int oval = *(int *)ctl->data; int ret = proc_dointvec(ctl, write, buffer, lenp, ppos); @@ -2633,7 +2634,7 @@ nolabels: } static int mpls_platform_labels(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct net *net = table->data; int platform_labels = net->mpls.platform_labels; diff --git a/net/netfilter/ipset/ip_set_hash_gen.h b/net/netfilter/ipset/ip_set_hash_gen.h index 9143bc5dae00..516e5adfd0d1 100644 --- a/net/netfilter/ipset/ip_set_hash_gen.h +++ b/net/netfilter/ipset/ip_set_hash_gen.h @@ -87,7 +87,7 @@ struct hbucket { : jhash_size((htable_bits) - HTABLE_REGION_BITS)) #define ahash_sizeof_regions(htable_bits) \ (ahash_numof_locks(htable_bits) * sizeof(struct ip_set_region)) -#define ahash_region(n) \ +#define ahash_region(n, htable_bits) \ ((n) / jhash_size(HTABLE_REGION_BITS)) #define ahash_bucket_start(h, htable_bits) \ ((htable_bits) < HTABLE_REGION_BITS ? 0 \ @@ -716,7 +716,7 @@ retry: #endif key = HKEY(data, h->initval, htable_bits); m = __ipset_dereference(hbucket(t, key)); - nr = ahash_region(key); + nr = ahash_region(key, htable_bits); if (!m) { m = kzalloc(sizeof(*m) + AHASH_INIT_SIZE * dsize, @@ -866,7 +866,7 @@ mtype_add(struct ip_set *set, void *value, const struct ip_set_ext *ext, rcu_read_lock_bh(); t = rcu_dereference_bh(h->table); key = HKEY(value, h->initval, t->htable_bits); - r = ahash_region(key); + r = ahash_region(key, t->htable_bits); atomic_inc(&t->uref); elements = t->hregion[r].elements; maxelem = t->maxelem; @@ -1059,7 +1059,7 @@ mtype_del(struct ip_set *set, void *value, const struct ip_set_ext *ext, rcu_read_lock_bh(); t = rcu_dereference_bh(h->table); key = HKEY(value, h->initval, t->htable_bits); - r = ahash_region(key); + r = ahash_region(key, t->htable_bits); atomic_inc(&t->uref); rcu_read_unlock_bh(); diff --git a/net/netfilter/ipvs/ip_vs_ctl.c b/net/netfilter/ipvs/ip_vs_ctl.c index e301ebe88731..dcce6aaac970 100644 --- a/net/netfilter/ipvs/ip_vs_ctl.c +++ b/net/netfilter/ipvs/ip_vs_ctl.c @@ -1730,7 +1730,7 @@ static int three = 3; static int proc_do_defense_mode(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct netns_ipvs *ipvs = table->extra2; int *valp = table->data; @@ -1757,7 +1757,7 @@ proc_do_defense_mode(struct ctl_table *table, int write, static int proc_do_sync_threshold(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct netns_ipvs *ipvs = table->extra2; int *valp = table->data; @@ -1785,7 +1785,7 @@ proc_do_sync_threshold(struct ctl_table *table, int write, static int proc_do_sync_ports(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int *valp = table->data; int val = *valp; diff --git a/net/netfilter/ipvs/ip_vs_ftp.c b/net/netfilter/ipvs/ip_vs_ftp.c index 67d0d4f1f0db..cf925906f59b 100644 --- a/net/netfilter/ipvs/ip_vs_ftp.c +++ b/net/netfilter/ipvs/ip_vs_ftp.c @@ -53,7 +53,6 @@ enum { IP_VS_FTP_EPSV, }; -static bool exiting_module; /* * List of ports (up to IP_VS_APP_MAX_PORTS) to be handled by helper * First port is set to the default port. @@ -608,7 +607,7 @@ static void __ip_vs_ftp_exit(struct net *net) { struct netns_ipvs *ipvs = net_ipvs(net); - if (!ipvs || !exiting_module) + if (!ipvs) return; unregister_ip_vs_app(ipvs, &ip_vs_ftp); @@ -630,7 +629,6 @@ static int __init ip_vs_ftp_init(void) */ static void __exit ip_vs_ftp_exit(void) { - exiting_module = true; unregister_pernet_subsys(&ip_vs_ftp_ops); /* rcu_barrier() is called by netns */ } diff --git a/net/netfilter/nf_conntrack_core.c b/net/netfilter/nf_conntrack_core.c index effa09102d3c..e999b6d8da11 100644 --- a/net/netfilter/nf_conntrack_core.c +++ b/net/netfilter/nf_conntrack_core.c @@ -1853,12 +1853,8 @@ void __nf_ct_refresh_acct(struct nf_conn *ct, /* Refresh the NAT type entry. */ #if defined(CONFIG_IP_NF_TARGET_NATTYPE_MODULE) nattype_ref_timer = rcu_dereference(nattype_refresh_timer); - if (nattype_ref_timer) { - if (nf_ct_is_confirmed(ct)) - nattype_ref_timer(ct->nattype_entry, ct->timeout); - else - nattype_ref_timer(ct->nattype_entry, extra_jiffies + nfct_time_stamp); - } + if (nattype_ref_timer) + nattype_ref_timer(ct->nattype_entry, ct->timeout); #endif acct: diff --git a/net/netfilter/nf_conntrack_standalone.c b/net/netfilter/nf_conntrack_standalone.c index 78681e7c7bcb..18949d043c5d 100644 --- a/net/netfilter/nf_conntrack_standalone.c +++ b/net/netfilter/nf_conntrack_standalone.c @@ -518,7 +518,7 @@ static unsigned int nf_conntrack_htable_size_user __read_mostly; static int nf_conntrack_hash_sysctl(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int ret; diff --git a/net/netfilter/nf_log.c b/net/netfilter/nf_log.c index 28c6cb5cff0e..e25dbeb220b4 100644 --- a/net/netfilter/nf_log.c +++ b/net/netfilter/nf_log.c @@ -415,7 +415,7 @@ static struct ctl_table nf_log_sysctl_ftable[] = { }; static int nf_log_proc_dostring(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { const struct nf_logger *logger; char buf[NFLOGGER_NAME_LEN]; diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c index b7a759a8f13e..3259fb5b58dd 100644 --- a/net/netlink/af_netlink.c +++ b/net/netlink/af_netlink.c @@ -60,7 +60,6 @@ #include #include #include -#include #include #include @@ -2614,7 +2613,7 @@ static void *netlink_seq_next(struct seq_file *seq, void *v, loff_t *pos) return __netlink_seq_next(seq); } -static void netlink_native_seq_stop(struct seq_file *seq, void *v) +static void netlink_seq_stop(struct seq_file *seq, void *v) { struct nl_seq_iter *iter = seq->private; @@ -2625,7 +2624,7 @@ static void netlink_native_seq_stop(struct seq_file *seq, void *v) } -static int netlink_native_seq_show(struct seq_file *seq, void *v) +static int netlink_seq_show(struct seq_file *seq, void *v) { if (v == SEQ_START_TOKEN) { seq_puts(seq, @@ -2652,68 +2651,6 @@ static int netlink_native_seq_show(struct seq_file *seq, void *v) return 0; } -#ifdef CONFIG_BPF_SYSCALL -struct bpf_iter__netlink { - __bpf_md_ptr(struct bpf_iter_meta *, meta); - __bpf_md_ptr(struct netlink_sock *, sk); -}; - -DEFINE_BPF_ITER_FUNC(netlink, struct bpf_iter_meta *meta, struct netlink_sock *sk) - -static int netlink_prog_seq_show(struct bpf_prog *prog, - struct bpf_iter_meta *meta, - void *v) -{ - struct bpf_iter__netlink ctx; - - meta->seq_num--; /* skip SEQ_START_TOKEN */ - ctx.meta = meta; - ctx.sk = nlk_sk((struct sock *)v); - return bpf_iter_run_prog(prog, &ctx); -} - -static int netlink_seq_show(struct seq_file *seq, void *v) -{ - struct bpf_iter_meta meta; - struct bpf_prog *prog; - - meta.seq = seq; - prog = bpf_iter_get_info(&meta, false); - if (!prog) - return netlink_native_seq_show(seq, v); - - if (v != SEQ_START_TOKEN) - return netlink_prog_seq_show(prog, &meta, v); - - return 0; -} - -static void netlink_seq_stop(struct seq_file *seq, void *v) -{ - struct bpf_iter_meta meta; - struct bpf_prog *prog; - - if (!v) { - meta.seq = seq; - prog = bpf_iter_get_info(&meta, true); - if (prog) - (void)netlink_prog_seq_show(prog, &meta, v); - } - - netlink_native_seq_stop(seq, v); -} -#else -static int netlink_seq_show(struct seq_file *seq, void *v) -{ - return netlink_native_seq_show(seq, v); -} - -static void netlink_seq_stop(struct seq_file *seq, void *v) -{ - netlink_native_seq_stop(seq, v); -} -#endif - static const struct seq_operations netlink_seq_ops = { .start = netlink_seq_start, .next = netlink_seq_next, @@ -2820,34 +2757,6 @@ static const struct rhashtable_params netlink_rhashtable_params = { .automatic_shrinking = true, }; -#if defined(CONFIG_BPF_SYSCALL) && defined(CONFIG_PROC_FS) -BTF_ID_LIST(btf_netlink_sock_id) -BTF_ID(struct, netlink_sock) - -static const struct bpf_iter_seq_info netlink_seq_info = { - .seq_ops = &netlink_seq_ops, - .init_seq_private = bpf_iter_init_seq_net, - .fini_seq_private = bpf_iter_fini_seq_net, - .seq_priv_size = sizeof(struct nl_seq_iter), -}; - -static struct bpf_iter_reg netlink_reg_info = { - .target = "netlink", - .ctx_arg_info_size = 1, - .ctx_arg_info = { - { offsetof(struct bpf_iter__netlink, sk), - PTR_TO_BTF_ID_OR_NULL }, - }, - .seq_info = &netlink_seq_info, -}; - -static int __init bpf_iter_register(void) -{ - netlink_reg_info.ctx_arg_info[0].btf_id = *btf_netlink_sock_id; - return bpf_iter_reg_target(&netlink_reg_info); -} -#endif - static int __init netlink_proto_init(void) { int i; @@ -2856,11 +2765,6 @@ static int __init netlink_proto_init(void) if (err != 0) goto out; -#if defined(CONFIG_BPF_SYSCALL) && defined(CONFIG_PROC_FS) - err = bpf_iter_register(); - if (err) - goto out; -#endif BUILD_BUG_ON(sizeof(struct netlink_skb_parms) > FIELD_SIZEOF(struct sk_buff, cb)); nl_table = kcalloc(MAX_LINKS, sizeof(*nl_table), GFP_KERNEL); diff --git a/net/nfc/hci/Kconfig b/net/nfc/hci/Kconfig index 4822d6f46947..97bd3a2c5c98 100644 --- a/net/nfc/hci/Kconfig +++ b/net/nfc/hci/Kconfig @@ -1,12 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only config NFC_HCI - depends on NFC - tristate "NFC HCI implementation" - default n - help - Say Y here if you want to build support for a kernel NFC HCI - implementation. This is mostly needed for devices that only process - HCI frames, like for example the NXP pn544. + depends on NFC + tristate "NFC HCI implementation" + default n + help + Say Y here if you want to build support for a kernel NFC HCI + implementation. This is mostly needed for devices that only process + HCI frames, like for example the NXP pn544. config NFC_SHDLC depends on NFC_HCI diff --git a/net/nfc/llcp_core.c b/net/nfc/llcp_core.c index cd481490bcfe..da3cb0d29b97 100644 --- a/net/nfc/llcp_core.c +++ b/net/nfc/llcp_core.c @@ -1096,7 +1096,6 @@ static void nfc_llcp_recv_hdlc(struct nfc_llcp_local *local, if (sk->sk_state == LLCP_CLOSED) { release_sock(sk); nfc_llcp_sock_put(llcp_sock); - return; } /* Pass the payload upstream */ @@ -1188,7 +1187,6 @@ static void nfc_llcp_recv_disc(struct nfc_llcp_local *local, if (sk->sk_state == LLCP_CLOSED) { release_sock(sk); nfc_llcp_sock_put(llcp_sock); - return; } if (sk->sk_state == LLCP_CONNECTED) { diff --git a/net/openvswitch/actions.c b/net/openvswitch/actions.c index b1a3581ce206..5af7fe6312cf 100644 --- a/net/openvswitch/actions.c +++ b/net/openvswitch/actions.c @@ -599,6 +599,69 @@ static int set_ipv6(struct sk_buff *skb, struct sw_flow_key *flow_key, return 0; } +static int set_nsh(struct sk_buff *skb, struct sw_flow_key *flow_key, + const struct nlattr *a) +{ + struct nshhdr *nh; + size_t length; + int err; + u8 flags; + u8 ttl; + int i; + + struct ovs_key_nsh key; + struct ovs_key_nsh mask; + + err = nsh_key_from_nlattr(a, &key, &mask); + if (err) + return err; + + /* Make sure the NSH base header is there */ + if (!pskb_may_pull(skb, skb_network_offset(skb) + NSH_BASE_HDR_LEN)) + return -ENOMEM; + + nh = nsh_hdr(skb); + length = nsh_hdr_len(nh); + + /* Make sure the whole NSH header is there */ + err = skb_ensure_writable(skb, skb_network_offset(skb) + + length); + if (unlikely(err)) + return err; + + nh = nsh_hdr(skb); + skb_postpull_rcsum(skb, nh, length); + flags = nsh_get_flags(nh); + flags = OVS_MASKED(flags, key.base.flags, mask.base.flags); + flow_key->nsh.base.flags = flags; + ttl = nsh_get_ttl(nh); + ttl = OVS_MASKED(ttl, key.base.ttl, mask.base.ttl); + flow_key->nsh.base.ttl = ttl; + nsh_set_flags_and_ttl(nh, flags, ttl); + nh->path_hdr = OVS_MASKED(nh->path_hdr, key.base.path_hdr, + mask.base.path_hdr); + flow_key->nsh.base.path_hdr = nh->path_hdr; + switch (nh->mdtype) { + case NSH_M_TYPE1: + for (i = 0; i < NSH_MD1_CONTEXT_SIZE; i++) { + nh->md1.context[i] = + OVS_MASKED(nh->md1.context[i], key.context[i], + mask.context[i]); + } + memcpy(flow_key->nsh.context, nh->md1.context, + sizeof(nh->md1.context)); + break; + case NSH_M_TYPE2: + memset(flow_key->nsh.context, 0, + sizeof(flow_key->nsh.context)); + break; + default: + return -EINVAL; + } + skb_postpush_rcsum(skb, nh, length); + return 0; +} + /* Must follow skb_ensure_writable() since that can move the skb data. */ static void set_tp_port(struct sk_buff *skb, __be16 *port, __be16 new_port, __sum16 *check) @@ -1059,6 +1122,10 @@ static int execute_masked_set_action(struct sk_buff *skb, get_mask(a, struct ovs_key_ethernet *)); break; + case OVS_KEY_ATTR_NSH: + err = set_nsh(skb, flow_key, a); + break; + case OVS_KEY_ATTR_IPV4: err = set_ipv4(skb, flow_key, nla_data(a), get_mask(a, struct ovs_key_ipv4 *)); @@ -1095,7 +1162,6 @@ static int execute_masked_set_action(struct sk_buff *skb, case OVS_KEY_ATTR_CT_LABELS: case OVS_KEY_ATTR_CT_ORIG_TUPLE_IPV4: case OVS_KEY_ATTR_CT_ORIG_TUPLE_IPV6: - case OVS_KEY_ATTR_NSH: err = -EINVAL; break; } diff --git a/net/openvswitch/flow_netlink.c b/net/openvswitch/flow_netlink.c index a378b06db24f..4ad4c89886ee 100644 --- a/net/openvswitch/flow_netlink.c +++ b/net/openvswitch/flow_netlink.c @@ -1277,11 +1277,6 @@ static int metadata_from_nlattrs(struct net *net, struct sw_flow_match *match, return 0; } -/* - * Constructs NSH header 'nh' from attributes of OVS_ACTION_ATTR_PUSH_NSH, - * where 'nh' points to a memory block of 'size' bytes. It's assumed that - * attributes were previously validated with validate_push_nsh(). - */ int nsh_hdr_from_nlattr(const struct nlattr *attr, struct nshhdr *nh, size_t size) { @@ -1291,6 +1286,8 @@ int nsh_hdr_from_nlattr(const struct nlattr *attr, u8 ttl = 0; int mdlen = 0; + /* validate_nsh has check this, so we needn't do duplicate check here + */ if (size < NSH_BASE_HDR_LEN) return -ENOBUFS; @@ -1334,6 +1331,46 @@ int nsh_hdr_from_nlattr(const struct nlattr *attr, return 0; } +int nsh_key_from_nlattr(const struct nlattr *attr, + struct ovs_key_nsh *nsh, struct ovs_key_nsh *nsh_mask) +{ + struct nlattr *a; + int rem; + + /* validate_nsh has check this, so we needn't do duplicate check here + */ + nla_for_each_nested(a, attr, rem) { + int type = nla_type(a); + + switch (type) { + case OVS_NSH_KEY_ATTR_BASE: { + const struct ovs_nsh_key_base *base = nla_data(a); + const struct ovs_nsh_key_base *base_mask = base + 1; + + nsh->base = *base; + nsh_mask->base = *base_mask; + break; + } + case OVS_NSH_KEY_ATTR_MD1: { + const struct ovs_nsh_key_md1 *md1 = nla_data(a); + const struct ovs_nsh_key_md1 *md1_mask = md1 + 1; + + memcpy(nsh->context, md1->context, sizeof(*md1)); + memcpy(nsh_mask->context, md1_mask->context, + sizeof(*md1_mask)); + break; + } + case OVS_NSH_KEY_ATTR_MD2: + /* Not supported yet */ + return -ENOTSUPP; + default: + return -EINVAL; + } + } + + return 0; +} + static int nsh_key_put_from_nlattr(const struct nlattr *attr, struct sw_flow_match *match, bool is_mask, bool is_push_nsh, bool log) @@ -2667,13 +2704,17 @@ static int validate_and_copy_set_tun(const struct nlattr *attr, return err; } -static bool validate_push_nsh(const struct nlattr *attr, bool log) +static bool validate_nsh(const struct nlattr *attr, bool is_mask, + bool is_push_nsh, bool log) { struct sw_flow_match match; struct sw_flow_key key; + int ret = 0; ovs_match_init(&match, &key, true, NULL); - return !nsh_key_put_from_nlattr(attr, &match, false, true, log); + ret = nsh_key_put_from_nlattr(attr, &match, is_mask, + is_push_nsh, log); + return !ret; } /* Return false if there are any non-masked bits set. @@ -2819,6 +2860,13 @@ static int validate_set(const struct nlattr *a, break; + case OVS_KEY_ATTR_NSH: + if (eth_type != htons(ETH_P_NSH)) + return -EINVAL; + if (!validate_nsh(nla_data(a), masked, false, log)) + return -EINVAL; + break; + default: return -EINVAL; } @@ -3171,7 +3219,7 @@ static int __ovs_nla_copy_actions(struct net *net, const struct nlattr *attr, return -EINVAL; } mac_proto = MAC_PROTO_NONE; - if (!validate_push_nsh(nla_data(a), log)) + if (!validate_nsh(nla_data(a), false, true, true)) return -EINVAL; break; diff --git a/net/openvswitch/flow_netlink.h b/net/openvswitch/flow_netlink.h index ff8cdecbe346..fe7f77fc5f18 100644 --- a/net/openvswitch/flow_netlink.h +++ b/net/openvswitch/flow_netlink.h @@ -65,6 +65,8 @@ int ovs_nla_put_actions(const struct nlattr *attr, void ovs_nla_free_flow_actions(struct sw_flow_actions *); void ovs_nla_free_flow_actions_rcu(struct sw_flow_actions *); +int nsh_key_from_nlattr(const struct nlattr *attr, struct ovs_key_nsh *nsh, + struct ovs_key_nsh *nsh_mask); int nsh_hdr_from_nlattr(const struct nlattr *attr, struct nshhdr *nh, size_t size); diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c index 9c6cc1cf547c..34ab7ea7ebcf 100644 --- a/net/packet/af_packet.c +++ b/net/packet/af_packet.c @@ -1589,7 +1589,7 @@ static void __fanout_set_data_bpf(struct packet_fanout *f, struct bpf_prog *new) } } -static int fanout_set_data_cbpf(struct packet_sock *po, sockptr_t data, +static int fanout_set_data_cbpf(struct packet_sock *po, char __user *data, unsigned int len) { struct bpf_prog *new; @@ -1598,10 +1598,10 @@ static int fanout_set_data_cbpf(struct packet_sock *po, sockptr_t data, if (sock_flag(&po->sk, SOCK_FILTER_LOCKED)) return -EPERM; - - ret = copy_bpf_fprog_from_user(&fprog, data, len); - if (ret) - return ret; + if (len != sizeof(fprog)) + return -EINVAL; + if (copy_from_user(&fprog, data, len)) + return -EFAULT; ret = bpf_prog_create_from_user(&new, &fprog, NULL, false); if (ret) @@ -1637,7 +1637,7 @@ static int fanout_set_data(struct packet_sock *po, char __user *data, { switch (po->fanout->type) { case PACKET_FANOUT_CBPF: - return fanout_set_data_cbpf(po, USER_SOCKPTR(data), len); + return fanout_set_data_cbpf(po, data, len); case PACKET_FANOUT_EBPF: return fanout_set_data_ebpf(po, data, len); default: @@ -3117,7 +3117,6 @@ static int packet_release(struct socket *sock) spin_lock(&po->bind_lock); unregister_prot_hook(sk, false); - WRITE_ONCE(po->num, 0); packet_cached_dev_reset(po); if (po->prot_hook.dev) { @@ -4148,6 +4147,28 @@ static int packet_getsockopt(struct socket *sock, int level, int optname, return 0; } + +#ifdef CONFIG_COMPAT +static int compat_packet_setsockopt(struct socket *sock, int level, int optname, + char __user *optval, unsigned int optlen) +{ + struct packet_sock *po = pkt_sk(sock->sk); + + if (level != SOL_PACKET) + return -ENOPROTOOPT; + + if (optname == PACKET_FANOUT_DATA && + po->fanout && po->fanout->type == PACKET_FANOUT_CBPF) { + optval = (char __user *)get_compat_bpf_fprog(optval); + if (!optval) + return -EFAULT; + optlen = sizeof(struct sock_fprog); + } + + return packet_setsockopt(sock, level, optname, optval, optlen); +} +#endif + static int packet_notifier(struct notifier_block *this, unsigned long msg, void *ptr) { @@ -4636,6 +4657,9 @@ static const struct proto_ops packet_ops = { .shutdown = sock_no_shutdown, .setsockopt = packet_setsockopt, .getsockopt = packet_getsockopt, +#ifdef CONFIG_COMPAT + .compat_setsockopt = compat_packet_setsockopt, +#endif .sendmsg = packet_sendmsg, .recvmsg = packet_recvmsg, .mmap = packet_mmap, diff --git a/net/phonet/sysctl.c b/net/phonet/sysctl.c index 0d0bf41381c2..251e750fd9aa 100644 --- a/net/phonet/sysctl.c +++ b/net/phonet/sysctl.c @@ -49,7 +49,8 @@ void phonet_get_local_port_range(int *min, int *max) } static int proc_local_port_range(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, + size_t *lenp, loff_t *ppos) { int ret; int range[2] = {local_port_range[0], local_port_range[1]}; diff --git a/net/rds/rds.h b/net/rds/rds.h index a8ad1e4185eb..2ac5b5e55901 100644 --- a/net/rds/rds.h +++ b/net/rds/rds.h @@ -94,7 +94,7 @@ enum { /* Max number of multipaths per RDS connection. Must be a power of 2 */ #define RDS_MPATH_WORKERS 8 -#define RDS_MPATH_HASH(rs, n) (jhash_1word(ntohs((rs)->rs_bound_port), \ +#define RDS_MPATH_HASH(rs, n) (jhash_1word((rs)->rs_bound_port, \ (rs)->rs_hash_initval) & ((n) - 1)) #define IS_CANONICAL(laddr, faddr) (htonl(laddr) < htonl(faddr)) diff --git a/net/rds/tcp.c b/net/rds/tcp.c index 81c442267317..bfb8d4d6a994 100644 --- a/net/rds/tcp.c +++ b/net/rds/tcp.c @@ -62,7 +62,8 @@ static atomic_t rds_tcp_unloading = ATOMIC_INIT(0); static struct kmem_cache *rds_tcp_conn_slab; static int rds_tcp_skbuf_handler(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *fpos); + void __user *buffer, size_t *lenp, + loff_t *fpos); static int rds_tcp_min_sndbuf = SOCK_MIN_SNDBUF; static int rds_tcp_min_rcvbuf = SOCK_MIN_RCVBUF; @@ -675,7 +676,8 @@ static void rds_tcp_sysctl_reset(struct net *net) } static int rds_tcp_skbuf_handler(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *fpos) + void __user *buffer, size_t *lenp, + loff_t *fpos) { struct net *net = current->nsproxy->net_ns; int err; diff --git a/net/rds/tcp_listen.c b/net/rds/tcp_listen.c index fe0af46ba5a5..dfeceed3b533 100644 --- a/net/rds/tcp_listen.c +++ b/net/rds/tcp_listen.c @@ -56,7 +56,10 @@ int rds_tcp_keepalive(struct socket *sock) if (ret < 0) goto bail; - tcp_sock_set_keepidle(sock->sk, keepidle); + ret = kernel_setsockopt(sock, IPPROTO_TCP, TCP_KEEPIDLE, + (char *)&keepidle, sizeof(keepidle)); + if (ret < 0) + goto bail; /* KEEPINTVL is the interval between successive probes. We follow * the model in xs_tcp_finish_connecting() and re-use keepidle. diff --git a/net/rfkill/core.c b/net/rfkill/core.c index 97101c55763d..5bba7c36ac74 100644 --- a/net/rfkill/core.c +++ b/net/rfkill/core.c @@ -1317,7 +1317,7 @@ static const struct file_operations rfkill_fops = { .release = rfkill_fop_release, #ifdef CONFIG_RFKILL_INPUT .unlocked_ioctl = rfkill_fop_ioctl, - .compat_ioctl = compat_ptr_ioctl, + .compat_ioctl = rfkill_fop_ioctl, #endif .llseek = no_llseek, }; diff --git a/net/sched/act_bpf.c b/net/sched/act_bpf.c index 0b015ce802a4..b7d83d01841b 100644 --- a/net/sched/act_bpf.c +++ b/net/sched/act_bpf.c @@ -12,7 +12,6 @@ #include #include -#include #include #include @@ -54,8 +53,6 @@ static int tcf_bpf_act(struct sk_buff *skb, const struct tc_action *act, bpf_compute_data_pointers(skb); filter_res = BPF_PROG_RUN(filter, skb); } - if (skb_sk_is_prefetched(skb) && filter_res != TC_ACT_OK) - skb_orphan(skb); rcu_read_unlock(); /* A BPF program may overwrite the default action opcode. diff --git a/net/sched/act_ife.c b/net/sched/act_ife.c index 8f82842ad8cb..488d10476e85 100644 --- a/net/sched/act_ife.c +++ b/net/sched/act_ife.c @@ -642,15 +642,13 @@ static int tcf_ife_dump(struct sk_buff *skb, struct tc_action *a, int bind, unsigned char *b = skb_tail_pointer(skb); struct tcf_ife_info *ife = to_ife(a); struct tcf_ife_params *p; - struct tc_ife opt; + struct tc_ife opt = { + .index = ife->tcf_index, + .refcnt = refcount_read(&ife->tcf_refcnt) - ref, + .bindcnt = atomic_read(&ife->tcf_bindcnt) - bind, + }; struct tcf_t t; - memset(&opt, 0, sizeof(opt)); - - opt.index = ife->tcf_index, - opt.refcnt = refcount_read(&ife->tcf_refcnt) - ref, - opt.bindcnt = atomic_read(&ife->tcf_bindcnt) - bind, - spin_lock_bh(&ife->tcf_lock); opt.action = ife->tcf_action; p = rcu_dereference_protected(ife->params, diff --git a/net/sched/sch_api.c b/net/sched/sch_api.c index 84914b2308df..7c91f29f69c1 100644 --- a/net/sched/sch_api.c +++ b/net/sched/sch_api.c @@ -592,6 +592,16 @@ out: qdisc_skb_cb(skb)->pkt_len = pkt_len; } +void qdisc_warn_nonwc(const char *txt, struct Qdisc *qdisc) +{ + if (!(qdisc->flags & TCQ_F_WARN_NONWC)) { + pr_warn("%s: %s qdisc %X: is non-work-conserving?\n", + txt, qdisc->ops->id, qdisc->handle >> 16); + qdisc->flags |= TCQ_F_WARN_NONWC; + } +} +EXPORT_SYMBOL(qdisc_warn_nonwc); + static enum hrtimer_restart qdisc_watchdog(struct hrtimer *timer) { struct qdisc_watchdog *wd = container_of(timer, struct qdisc_watchdog, diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c index f2fa398f863f..c91ca4222d83 100644 --- a/net/sched/sch_generic.c +++ b/net/sched/sch_generic.c @@ -172,10 +172,9 @@ static inline void dev_requeue_skb(struct sk_buff *skb, struct Qdisc *q) static void try_bulk_dequeue_skb(struct Qdisc *q, struct sk_buff *skb, const struct netdev_queue *txq, - int *packets, int budget) + int *packets) { int bytelimit = qdisc_avail_bulklimit(txq) - skb->len; - int cnt = 0; while (bytelimit > 0) { struct sk_buff *nskb = q->dequeue(q); @@ -186,10 +185,8 @@ static void try_bulk_dequeue_skb(struct Qdisc *q, bytelimit -= nskb->len; /* covers GSO len */ skb->next = nskb; skb = nskb; - if (++cnt >= budget) - break; + (*packets)++; /* GSO counts as one pkt */ } - (*packets) += cnt; skb_mark_not_on_list(skb); } @@ -223,7 +220,7 @@ static void try_bulk_dequeue_skb_slow(struct Qdisc *q, * A requeued skb (via q->gso_skb) can also be a SKB list. */ static struct sk_buff *dequeue_skb(struct Qdisc *q, bool *validate, - int *packets, int budget) + int *packets) { const struct netdev_queue *txq = q->dev_queue; struct sk_buff *skb = NULL; @@ -290,7 +287,7 @@ validate: if (skb) { bulk: if (qdisc_may_bulk(q)) - try_bulk_dequeue_skb(q, skb, txq, packets, budget); + try_bulk_dequeue_skb(q, skb, txq, packets); else try_bulk_dequeue_skb_slow(q, skb, packets); } @@ -382,7 +379,7 @@ bool sch_direct_xmit(struct sk_buff *skb, struct Qdisc *q, * >0 - queue is not empty. * */ -static inline bool qdisc_restart(struct Qdisc *q, int *packets, int budget) +static inline bool qdisc_restart(struct Qdisc *q, int *packets) { spinlock_t *root_lock = NULL; struct netdev_queue *txq; @@ -391,7 +388,7 @@ static inline bool qdisc_restart(struct Qdisc *q, int *packets, int budget) bool validate; /* Dequeue packet */ - skb = dequeue_skb(q, &validate, packets, budget); + skb = dequeue_skb(q, &validate, packets); if (unlikely(!skb)) return false; @@ -409,9 +406,14 @@ void __qdisc_run(struct Qdisc *q) int quota = READ_ONCE(dev_tx_weight); int packets; - while (qdisc_restart(q, &packets, quota)) { + while (qdisc_restart(q, &packets)) { + /* + * Ordered by possible occurrence: Postpone processing if + * 1. we've exceeded packet quota + * 2. another process needs the CPU; + */ quota -= packets; - if (quota <= 0) { + if (quota <= 0 || need_resched()) { __netif_schedule(q); break; } diff --git a/net/sched/sch_hfsc.c b/net/sched/sch_hfsc.c index d4d2f2f83241..5cb789c7c82d 100644 --- a/net/sched/sch_hfsc.c +++ b/net/sched/sch_hfsc.c @@ -836,6 +836,22 @@ update_vf(struct hfsc_class *cl, unsigned int len, u64 cur_time) } } +static unsigned int +qdisc_peek_len(struct Qdisc *sch) +{ + struct sk_buff *skb; + unsigned int len; + + skb = sch->ops->peek(sch); + if (unlikely(skb == NULL)) { + qdisc_warn_nonwc("qdisc_peek_len", sch); + return 0; + } + len = qdisc_pkt_len(skb); + + return len; +} + static void hfsc_adjust_levels(struct hfsc_class *cl) { diff --git a/net/sched/sch_qfq.c b/net/sched/sch_qfq.c index 1c0ac9372af9..511f344dbb77 100644 --- a/net/sched/sch_qfq.c +++ b/net/sched/sch_qfq.c @@ -1003,7 +1003,7 @@ static struct sk_buff *agg_dequeue(struct qfq_aggregate *agg, if (cl->qdisc->q.qlen == 0) /* no more packets, remove from list */ list_del_init(&cl->alist); - else if (cl->deficit < qdisc_peek_len(cl->qdisc)) { + else if (cl->deficit < qdisc_pkt_len(cl->qdisc->ops->peek(cl->qdisc))) { cl->deficit += agg->lmax; list_move_tail(&cl->alist, &agg->active); } diff --git a/net/sctp/associola.c b/net/sctp/associola.c index 253ab788cffc..bc9a62744fec 100644 --- a/net/sctp/associola.c +++ b/net/sctp/associola.c @@ -579,6 +579,7 @@ struct sctp_transport *sctp_assoc_add_peer(struct sctp_association *asoc, const gfp_t gfp, const int peer_state) { + struct net *net = sock_net(asoc->base.sk); struct sctp_transport *peer; struct sctp_sock *sp; unsigned short port; @@ -608,7 +609,7 @@ struct sctp_transport *sctp_assoc_add_peer(struct sctp_association *asoc, return peer; } - peer = sctp_transport_new(asoc->base.net, addr, gfp); + peer = sctp_transport_new(net, addr, gfp); if (!peer) return NULL; @@ -977,7 +978,7 @@ static void sctp_assoc_bh_rcv(struct work_struct *work) struct sctp_association *asoc = container_of(work, struct sctp_association, base.inqueue.immediate); - struct net *net = asoc->base.net; + struct net *net = sock_net(asoc->base.sk); union sctp_subtype subtype; struct sctp_endpoint *ep; struct sctp_chunk *chunk; @@ -1444,8 +1445,7 @@ void sctp_assoc_sync_pmtu(struct sctp_association *asoc) /* Should we send a SACK to update our peer? */ static inline bool sctp_peer_needs_update(struct sctp_association *asoc) { - struct net *net = asoc->base.net; - + struct net *net = sock_net(asoc->base.sk); switch (asoc->state) { case SCTP_STATE_ESTABLISHED: case SCTP_STATE_SHUTDOWN_PENDING: @@ -1582,7 +1582,7 @@ int sctp_assoc_set_bind_addr_from_ep(struct sctp_association *asoc, if (asoc->peer.ipv6_address) flags |= SCTP_ADDR6_PEERSUPP; - return sctp_bind_addr_copy(asoc->base.net, + return sctp_bind_addr_copy(sock_net(asoc->base.sk), &asoc->base.bind_addr, &asoc->ep->base.bind_addr, scope, gfp, flags); diff --git a/net/sctp/chunk.c b/net/sctp/chunk.c index 064675bc7b54..cc0405c79dfc 100644 --- a/net/sctp/chunk.c +++ b/net/sctp/chunk.c @@ -227,7 +227,7 @@ struct sctp_datamsg *sctp_datamsg_from_user(struct sctp_association *asoc, if (msg_len >= first_len) { msg->can_delay = 0; if (msg_len > first_len) - SCTP_INC_STATS(asoc->base.net, + SCTP_INC_STATS(sock_net(asoc->base.sk), SCTP_MIB_FRAGUSRMSGS); } else { /* Which may be the only one... */ diff --git a/net/sctp/diag.c b/net/sctp/diag.c index 641e52b9099d..2fcfb8cc8bd1 100644 --- a/net/sctp/diag.c +++ b/net/sctp/diag.c @@ -73,26 +73,19 @@ static int inet_diag_msg_sctpladdrs_fill(struct sk_buff *skb, struct nlattr *attr; void *info = NULL; - rcu_read_lock(); list_for_each_entry_rcu(laddr, address_list, list) addrcnt++; - rcu_read_unlock(); attr = nla_reserve(skb, INET_DIAG_LOCALS, addrlen * addrcnt); if (!attr) return -EMSGSIZE; info = nla_data(attr); - rcu_read_lock(); list_for_each_entry_rcu(laddr, address_list, list) { memcpy(info, &laddr->a, sizeof(laddr->a)); memset(info + sizeof(laddr->a), 0, addrlen - sizeof(laddr->a)); info += addrlen; - - if (!--addrcnt) - break; } - rcu_read_unlock(); return 0; } diff --git a/net/sctp/endpointola.c b/net/sctp/endpointola.c index 208b121d5a78..665a22d5c725 100644 --- a/net/sctp/endpointola.c +++ b/net/sctp/endpointola.c @@ -251,7 +251,7 @@ struct sctp_endpoint *sctp_endpoint_is_match(struct sctp_endpoint *ep, struct sctp_endpoint *retval = NULL; if ((htons(ep->base.bind_addr.port) == laddr->v4.sin_port) && - net_eq(ep->base.net, net)) { + net_eq(sock_net(ep->base.sk), net)) { if (sctp_bind_addr_match(&ep->base.bind_addr, laddr, sctp_sk(ep->base.sk))) retval = ep; @@ -299,8 +299,8 @@ bool sctp_endpoint_is_peeled_off(struct sctp_endpoint *ep, const union sctp_addr *paddr) { struct sctp_sockaddr_entry *addr; - struct net *net = ep->base.net; struct sctp_bind_addr *bp; + struct net *net = sock_net(ep->base.sk); bp = &ep->base.bind_addr; /* This function is called with the socket lock held, @@ -391,7 +391,7 @@ normal: if (asoc && sctp_chunk_is_data(chunk)) asoc->peer.last_data_from = chunk->transport; else { - SCTP_INC_STATS(ep->base.net, SCTP_MIB_INCTRLCHUNKS); + SCTP_INC_STATS(sock_net(ep->base.sk), SCTP_MIB_INCTRLCHUNKS); if (asoc) asoc->stats.ictrlchunks++; } diff --git a/net/sctp/input.c b/net/sctp/input.c index 28e0e110804a..9013257cf3df 100644 --- a/net/sctp/input.c +++ b/net/sctp/input.c @@ -935,7 +935,7 @@ int sctp_hash_transport(struct sctp_transport *t) if (t->asoc->temp) return 0; - arg.net = t->asoc->base.net; + arg.net = sock_net(t->asoc->base.sk); arg.paddr = &t->ipaddr; arg.lport = htons(t->asoc->base.bind_addr.port); @@ -1002,11 +1002,12 @@ struct sctp_transport *sctp_epaddr_lookup_transport( const struct sctp_endpoint *ep, const union sctp_addr *paddr) { + struct net *net = sock_net(ep->base.sk); struct rhlist_head *tmp, *list; struct sctp_transport *t; struct sctp_hash_cmp_arg arg = { .paddr = paddr, - .net = ep->base.net, + .net = net, .lport = htons(ep->base.bind_addr.port), }; diff --git a/net/sctp/inqueue.c b/net/sctp/inqueue.c index 6a434d441dc7..7182c5a450fb 100644 --- a/net/sctp/inqueue.c +++ b/net/sctp/inqueue.c @@ -163,14 +163,13 @@ next_chunk: chunk->head_skb = chunk->skb; /* skbs with "cover letter" */ - if (chunk->head_skb && chunk->skb->data_len == chunk->skb->len) { - if (WARN_ON(!skb_shinfo(chunk->skb)->frag_list)) { - __SCTP_INC_STATS(dev_net(chunk->skb->dev), - SCTP_MIB_IN_PKT_DISCARDS); - sctp_chunk_free(chunk); - goto next_chunk; - } + if (chunk->head_skb && chunk->skb->data_len == chunk->skb->len) chunk->skb = skb_shinfo(chunk->skb)->frag_list; + + if (WARN_ON(!chunk->skb)) { + __SCTP_INC_STATS(dev_net(chunk->skb->dev), SCTP_MIB_IN_PKT_DISCARDS); + sctp_chunk_free(chunk); + goto next_chunk; } } diff --git a/net/sctp/output.c b/net/sctp/output.c index 1441eaf460bb..dbda7e7927fd 100644 --- a/net/sctp/output.c +++ b/net/sctp/output.c @@ -282,7 +282,7 @@ static enum sctp_xmit sctp_packet_bundle_sack(struct sctp_packet *pkt, sctp_chunk_free(sack); goto out; } - SCTP_INC_STATS(asoc->base.net, + SCTP_INC_STATS(sock_net(asoc->base.sk), SCTP_MIB_OUTCTRLCHUNKS); asoc->stats.octrlchunks++; asoc->peer.sack_needed = 0; diff --git a/net/sctp/outqueue.c b/net/sctp/outqueue.c index 6b0b3bad4daa..adceb226ffab 100644 --- a/net/sctp/outqueue.c +++ b/net/sctp/outqueue.c @@ -280,7 +280,7 @@ void sctp_outq_free(struct sctp_outq *q) /* Put a new chunk in an sctp_outq. */ void sctp_outq_tail(struct sctp_outq *q, struct sctp_chunk *chunk, gfp_t gfp) { - struct net *net = q->asoc->base.net; + struct net *net = sock_net(q->asoc->base.sk); pr_debug("%s: outq:%p, chunk:%p[%s]\n", __func__, q, chunk, chunk && chunk->chunk_hdr ? @@ -534,7 +534,7 @@ void sctp_retransmit_mark(struct sctp_outq *q, void sctp_retransmit(struct sctp_outq *q, struct sctp_transport *transport, enum sctp_retransmit_reason reason) { - struct net *net = q->asoc->base.net; + struct net *net = sock_net(q->asoc->base.sk); switch (reason) { case SCTP_RTXR_T3_RTX: @@ -1890,6 +1890,6 @@ void sctp_generate_fwdtsn(struct sctp_outq *q, __u32 ctsn) if (ftsn_chunk) { list_add_tail(&ftsn_chunk->list, &q->control_chunk_list); - SCTP_INC_STATS(asoc->base.net, SCTP_MIB_OUTCTRLCHUNKS); + SCTP_INC_STATS(sock_net(asoc->base.sk), SCTP_MIB_OUTCTRLCHUNKS); } } diff --git a/net/sctp/sm_make_chunk.c b/net/sctp/sm_make_chunk.c index d3cc5a59b0fe..4eebe708c8e4 100644 --- a/net/sctp/sm_make_chunk.c +++ b/net/sctp/sm_make_chunk.c @@ -31,7 +31,6 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include -#include #include #include #include @@ -1759,7 +1758,7 @@ struct sctp_association *sctp_unpack_cookie( } } - if (crypto_memneq(digest, cookie->signature, SCTP_SIGNATURE_SIZE)) { + if (memcmp(digest, cookie->signature, SCTP_SIGNATURE_SIZE)) { *error = -SCTP_IERROR_BAD_SIG; goto fail; } @@ -2319,6 +2318,7 @@ int sctp_process_init(struct sctp_association *asoc, struct sctp_chunk *chunk, const union sctp_addr *peer_addr, struct sctp_init_chunk *peer_init, gfp_t gfp) { + struct net *net = sock_net(asoc->base.sk); struct sctp_transport *transport; struct list_head *pos, *temp; union sctp_params param; @@ -2376,8 +2376,8 @@ int sctp_process_init(struct sctp_association *asoc, struct sctp_chunk *chunk, * also give us an option to silently ignore the packet, which * is what we'll do here. */ - if (!asoc->base.net->sctp.addip_noauth && - (asoc->peer.asconf_capable && !asoc->peer.auth_capable)) { + if (!net->sctp.addip_noauth && + (asoc->peer.asconf_capable && !asoc->peer.auth_capable)) { asoc->peer.addip_disabled_mask |= (SCTP_PARAM_ADD_IP | SCTP_PARAM_DEL_IP | SCTP_PARAM_SET_PRIMARY); @@ -2504,9 +2504,9 @@ static int sctp_process_param(struct sctp_association *asoc, const union sctp_addr *peer_addr, gfp_t gfp) { + struct net *net = sock_net(asoc->base.sk); struct sctp_endpoint *ep = asoc->ep; union sctp_addr_param *addr_param; - struct net *net = asoc->base.net; struct sctp_transport *t; enum sctp_scope scope; union sctp_addr addr; diff --git a/net/sctp/sm_sideeffect.c b/net/sctp/sm_sideeffect.c index 3ecd246feb76..c964e7ca6f7e 100644 --- a/net/sctp/sm_sideeffect.c +++ b/net/sctp/sm_sideeffect.c @@ -520,6 +520,8 @@ static void sctp_do_8_2_transport_strike(struct sctp_cmd_seq *commands, struct sctp_transport *transport, int is_hb) { + struct net *net = sock_net(asoc->base.sk); + /* The check for association's overall error counter exceeding the * threshold is done in the state function. */ @@ -546,10 +548,10 @@ static void sctp_do_8_2_transport_strike(struct sctp_cmd_seq *commands, * is SCTP_ACTIVE, then mark this transport as Partially Failed, * see SCTP Quick Failover Draft, section 5.1 */ - if (asoc->base.net->sctp.pf_enable && - transport->state == SCTP_ACTIVE && - transport->error_count < transport->pathmaxrxt && - transport->error_count > transport->pf_retrans) { + if (net->sctp.pf_enable && + (transport->state == SCTP_ACTIVE) && + (transport->error_count < transport->pathmaxrxt) && + (transport->error_count > transport->pf_retrans)) { sctp_assoc_control_transport(asoc, transport, SCTP_TRANSPORT_PF, @@ -795,8 +797,10 @@ static int sctp_cmd_process_sack(struct sctp_cmd_seq *cmds, int err = 0; if (sctp_outq_sack(&asoc->outqueue, chunk)) { + struct net *net = sock_net(asoc->base.sk); + /* There are no more TSNs awaiting SACK. */ - err = sctp_do_sm(asoc->base.net, SCTP_EVENT_T_OTHER, + err = sctp_do_sm(net, SCTP_EVENT_T_OTHER, SCTP_ST_OTHER(SCTP_EVENT_NO_PENDING_TSN), asoc->state, asoc->ep, asoc, NULL, GFP_ATOMIC); @@ -829,7 +833,7 @@ static void sctp_cmd_assoc_update(struct sctp_cmd_seq *cmds, struct sctp_association *asoc, struct sctp_association *new) { - struct net *net = asoc->base.net; + struct net *net = sock_net(asoc->base.sk); struct sctp_chunk *abort; if (!sctp_assoc_update(asoc, new)) diff --git a/net/sctp/sm_statefuns.c b/net/sctp/sm_statefuns.c index 7808dd812a72..6b613569372a 100644 --- a/net/sctp/sm_statefuns.c +++ b/net/sctp/sm_statefuns.c @@ -30,7 +30,6 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt -#include #include #include #include @@ -874,8 +873,7 @@ enum sctp_disposition sctp_sf_do_5_1D_ce(struct net *net, return SCTP_DISPOSITION_CONSUME; nomem_authev: - if (ai_ev) - sctp_ulpevent_free(ai_ev); + sctp_ulpevent_free(ai_ev); nomem_aiev: sctp_ulpevent_free(ev); nomem_ev: @@ -1342,7 +1340,7 @@ static int sctp_sf_check_restart_addrs(const struct sctp_association *new_asoc, struct sctp_chunk *init, struct sctp_cmd_seq *commands) { - struct net *net = new_asoc->base.net; + struct net *net = sock_net(new_asoc->base.sk); struct sctp_transport *new_addr; int ret = 1; @@ -4304,7 +4302,7 @@ static enum sctp_ierror sctp_sf_authenticate( sh_key, GFP_ATOMIC); /* Discard the packet if the digests do not match */ - if (crypto_memneq(save_digest, digest, sig_len)) { + if (memcmp(save_digest, digest, sig_len)) { kfree(save_digest); return SCTP_IERROR_BAD_SIG; } diff --git a/net/sctp/socket.c b/net/sctp/socket.c index 50b6b6ee734b..18c3c00debdf 100644 --- a/net/sctp/socket.c +++ b/net/sctp/socket.c @@ -469,7 +469,8 @@ static int sctp_do_bind(struct sock *sk, union sctp_addr *addr, int len) static int sctp_send_asconf(struct sctp_association *asoc, struct sctp_chunk *chunk) { - int retval = 0; + struct net *net = sock_net(asoc->base.sk); + int retval = 0; /* If there is an outstanding ASCONF chunk, queue it for later * transmission. @@ -481,7 +482,7 @@ static int sctp_send_asconf(struct sctp_association *asoc, /* Hold the chunk until an ASCONF_ACK is received. */ sctp_chunk_hold(chunk); - retval = sctp_primitive_ASCONF(asoc->base.net, asoc, chunk); + retval = sctp_primitive_ASCONF(net, asoc, chunk); if (retval) sctp_chunk_free(chunk); else @@ -1338,7 +1339,7 @@ static int __sctp_setsockopt_connectx(struct sock *sk, kaddrs = memdup_user(addrs, addrs_size); if (IS_ERR(kaddrs)) - return PTR_ERR(kaddrs); + return PTR_ERR(kaddrs) == -EFAULT ? -EINVAL : PTR_ERR(kaddrs); /* Allow security module to validate connectx addresses. */ err = security_sctp_bind_connect(sk, SCTP_SOCKOPT_CONNECTX, @@ -2466,8 +2467,9 @@ static int sctp_apply_peer_addr_params(struct sctp_paddrparams *params, int error; if (params->spp_flags & SPP_HB_DEMAND && trans) { - error = sctp_primitive_REQUESTHEARTBEAT(trans->asoc->base.net, - trans->asoc, trans); + struct net *net = sock_net(trans->asoc->base.sk); + + error = sctp_primitive_REQUESTHEARTBEAT(net, trans->asoc, trans); if (error) return error; } @@ -5337,7 +5339,7 @@ struct sctp_transport *sctp_transport_get_next(struct net *net, if (!sctp_transport_hold(t)) continue; - if (net_eq(t->asoc->base.net, net) && + if (net_eq(sock_net(t->asoc->base.sk), net) && t->asoc->peer.primary_path == t) break; diff --git a/net/sctp/stream.c b/net/sctp/stream.c index 0527728aee98..08cd06078fab 100644 --- a/net/sctp/stream.c +++ b/net/sctp/stream.c @@ -229,9 +229,10 @@ void sctp_stream_update(struct sctp_stream *stream, struct sctp_stream *new) static int sctp_send_reconf(struct sctp_association *asoc, struct sctp_chunk *chunk) { + struct net *net = sock_net(asoc->base.sk); int retval = 0; - retval = sctp_primitive_RECONF(asoc->base.net, asoc, chunk); + retval = sctp_primitive_RECONF(net, asoc, chunk); if (retval) sctp_chunk_free(chunk); diff --git a/net/sctp/stream_interleave.c b/net/sctp/stream_interleave.c index e3aad75cb11d..c982f99099de 100644 --- a/net/sctp/stream_interleave.c +++ b/net/sctp/stream_interleave.c @@ -241,8 +241,9 @@ out: if (!first_frag) return NULL; - retval = sctp_make_reassembled_event(ulpq->asoc->base.net, &ulpq->reasm, - first_frag, last_frag); + retval = sctp_make_reassembled_event(sock_net(ulpq->asoc->base.sk), + &ulpq->reasm, first_frag, + last_frag); if (retval) { sin->fsn = next_fsn; if (is_last) { @@ -325,7 +326,7 @@ static struct sctp_ulpevent *sctp_intl_retrieve_reassembled( pd_point = sctp_sk(asoc->base.sk)->pd_point; if (pd_point && pd_point <= pd_len) { - retval = sctp_make_reassembled_event(asoc->base.net, + retval = sctp_make_reassembled_event(sock_net(asoc->base.sk), &ulpq->reasm, pd_first, pd_last); if (retval) { @@ -336,7 +337,8 @@ static struct sctp_ulpevent *sctp_intl_retrieve_reassembled( goto out; found: - retval = sctp_make_reassembled_event(asoc->base.net, &ulpq->reasm, + retval = sctp_make_reassembled_event(sock_net(asoc->base.sk), + &ulpq->reasm, first_frag, pos); if (retval) retval->msg_flags |= MSG_EOR; @@ -628,7 +630,7 @@ out: if (!first_frag) return NULL; - retval = sctp_make_reassembled_event(ulpq->asoc->base.net, + retval = sctp_make_reassembled_event(sock_net(ulpq->asoc->base.sk), &ulpq->reasm_uo, first_frag, last_frag); if (retval) { @@ -714,7 +716,7 @@ static struct sctp_ulpevent *sctp_intl_retrieve_reassembled_uo( pd_point = sctp_sk(asoc->base.sk)->pd_point; if (pd_point && pd_point <= pd_len) { - retval = sctp_make_reassembled_event(asoc->base.net, + retval = sctp_make_reassembled_event(sock_net(asoc->base.sk), &ulpq->reasm_uo, pd_first, pd_last); if (retval) { @@ -725,7 +727,8 @@ static struct sctp_ulpevent *sctp_intl_retrieve_reassembled_uo( goto out; found: - retval = sctp_make_reassembled_event(asoc->base.net, &ulpq->reasm_uo, + retval = sctp_make_reassembled_event(sock_net(asoc->base.sk), + &ulpq->reasm_uo, first_frag, pos); if (retval) retval->msg_flags |= MSG_EOR; @@ -811,7 +814,7 @@ static struct sctp_ulpevent *sctp_intl_retrieve_first_uo(struct sctp_ulpq *ulpq) return NULL; out: - retval = sctp_make_reassembled_event(ulpq->asoc->base.net, + retval = sctp_make_reassembled_event(sock_net(ulpq->asoc->base.sk), &ulpq->reasm_uo, first_frag, last_frag); if (retval) { @@ -918,7 +921,7 @@ static struct sctp_ulpevent *sctp_intl_retrieve_first(struct sctp_ulpq *ulpq) return NULL; out: - retval = sctp_make_reassembled_event(ulpq->asoc->base.net, + retval = sctp_make_reassembled_event(sock_net(ulpq->asoc->base.sk), &ulpq->reasm, first_frag, last_frag); if (retval) { @@ -1156,7 +1159,7 @@ static void sctp_generate_iftsn(struct sctp_outq *q, __u32 ctsn) if (ftsn_chunk) { list_add_tail(&ftsn_chunk->list, &q->control_chunk_list); - SCTP_INC_STATS(asoc->base.net, SCTP_MIB_OUTCTRLCHUNKS); + SCTP_INC_STATS(sock_net(asoc->base.sk), SCTP_MIB_OUTCTRLCHUNKS); } } diff --git a/net/sctp/sysctl.c b/net/sctp/sysctl.c index 7e2f626fd73f..f6fe63f60acd 100644 --- a/net/sctp/sysctl.c +++ b/net/sctp/sysctl.c @@ -41,15 +41,20 @@ static unsigned long max_autoclose_max = ? UINT_MAX : MAX_SCHEDULE_TIMEOUT / HZ; static int proc_sctp_do_hmac_alg(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, + loff_t *ppos); static int proc_sctp_do_rto_min(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos); -static int proc_sctp_do_rto_max(struct ctl_table *ctl, int write, void *buffer, - size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, + loff_t *ppos); +static int proc_sctp_do_rto_max(struct ctl_table *ctl, int write, + void __user *buffer, size_t *lenp, + loff_t *ppos); static int proc_sctp_do_alpha_beta(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, + loff_t *ppos); static int proc_sctp_do_auth(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos); + void __user *buffer, size_t *lenp, + loff_t *ppos); static struct ctl_table sctp_table[] = { { @@ -318,7 +323,8 @@ static struct ctl_table sctp_net_table[] = { }; static int proc_sctp_do_hmac_alg(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { struct net *net = container_of(ctl->data, struct net, sctp.sctp_hmac_alg); @@ -364,7 +370,8 @@ static int proc_sctp_do_hmac_alg(struct ctl_table *ctl, int write, } static int proc_sctp_do_rto_min(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { struct net *net = container_of(ctl->data, struct net, sctp.rto_min); unsigned int min = *(unsigned int *) ctl->extra1; @@ -392,7 +399,8 @@ static int proc_sctp_do_rto_min(struct ctl_table *ctl, int write, } static int proc_sctp_do_rto_max(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { struct net *net = container_of(ctl->data, struct net, sctp.rto_max); unsigned int min = *(unsigned int *) ctl->extra1; @@ -420,7 +428,8 @@ static int proc_sctp_do_rto_max(struct ctl_table *ctl, int write, } static int proc_sctp_do_alpha_beta(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { if (write) pr_warn_once("Changing rto_alpha or rto_beta may lead to " @@ -430,7 +439,8 @@ static int proc_sctp_do_alpha_beta(struct ctl_table *ctl, int write, } static int proc_sctp_do_auth(struct ctl_table *ctl, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { struct net *net = container_of(ctl->data, struct net, sctp.auth_enable); struct ctl_table tbl; diff --git a/net/sctp/transport.c b/net/sctp/transport.c index 992104107978..80251c8d2225 100644 --- a/net/sctp/transport.c +++ b/net/sctp/transport.c @@ -336,8 +336,7 @@ void sctp_transport_update_rto(struct sctp_transport *tp, __u32 rtt) pr_debug("%s: rto_pending not set on transport %p!\n", __func__, tp); if (tp->rttvar || tp->srtt) { - struct net *net = tp->asoc->base.net; - unsigned int rto_beta, rto_alpha; + struct net *net = sock_net(tp->asoc->base.sk); /* 6.3.1 C3) When a new RTT measurement R' is made, set * RTTVAR <- (1 - RTO.Beta) * RTTVAR + RTO.Beta * |SRTT - R'| * SRTT <- (1 - RTO.Alpha) * SRTT + RTO.Alpha * R' @@ -349,14 +348,10 @@ void sctp_transport_update_rto(struct sctp_transport *tp, __u32 rtt) * For example, assuming the default value of RTO.Alpha of * 1/8, rto_alpha would be expressed as 3. */ - rto_beta = READ_ONCE(net->sctp.rto_beta); - if (rto_beta < 32) - tp->rttvar = tp->rttvar - (tp->rttvar >> rto_beta) - + (((__u32)abs((__s64)tp->srtt - (__s64)rtt)) >> rto_beta); - rto_alpha = READ_ONCE(net->sctp.rto_alpha); - if (rto_alpha < 32) - tp->srtt = tp->srtt - (tp->srtt >> rto_alpha) - + (rtt >> rto_alpha); + tp->rttvar = tp->rttvar - (tp->rttvar >> net->sctp.rto_beta) + + (((__u32)abs((__s64)tp->srtt - (__s64)rtt)) >> net->sctp.rto_beta); + tp->srtt = tp->srtt - (tp->srtt >> net->sctp.rto_alpha) + + (rtt >> net->sctp.rto_alpha); } else { /* 6.3.1 C2) When the first RTT measurement R is made, set * SRTT <- R, RTTVAR <- R/2. diff --git a/net/sctp/ulpqueue.c b/net/sctp/ulpqueue.c index 1c6c640607c5..b6536b7f14c0 100644 --- a/net/sctp/ulpqueue.c +++ b/net/sctp/ulpqueue.c @@ -486,9 +486,10 @@ static struct sctp_ulpevent *sctp_ulpq_retrieve_reassembled(struct sctp_ulpq *ul cevent = sctp_skb2event(pd_first); pd_point = sctp_sk(asoc->base.sk)->pd_point; if (pd_point && pd_point <= pd_len) { - retval = sctp_make_reassembled_event(asoc->base.net, + retval = sctp_make_reassembled_event(sock_net(asoc->base.sk), &ulpq->reasm, - pd_first, pd_last); + pd_first, + pd_last); if (retval) sctp_ulpq_set_pd(ulpq); } @@ -496,7 +497,7 @@ static struct sctp_ulpevent *sctp_ulpq_retrieve_reassembled(struct sctp_ulpq *ul done: return retval; found: - retval = sctp_make_reassembled_event(ulpq->asoc->base.net, + retval = sctp_make_reassembled_event(sock_net(ulpq->asoc->base.sk), &ulpq->reasm, first_frag, pos); if (retval) retval->msg_flags |= MSG_EOR; @@ -562,8 +563,8 @@ static struct sctp_ulpevent *sctp_ulpq_retrieve_partial(struct sctp_ulpq *ulpq) * further. */ done: - retval = sctp_make_reassembled_event(ulpq->asoc->base.net, &ulpq->reasm, - first_frag, last_frag); + retval = sctp_make_reassembled_event(sock_net(ulpq->asoc->base.sk), + &ulpq->reasm, first_frag, last_frag); if (retval && is_last) retval->msg_flags |= MSG_EOR; @@ -663,8 +664,8 @@ static struct sctp_ulpevent *sctp_ulpq_retrieve_first(struct sctp_ulpq *ulpq) * further. */ done: - retval = sctp_make_reassembled_event(ulpq->asoc->base.net, &ulpq->reasm, - first_frag, last_frag); + retval = sctp_make_reassembled_event(sock_net(ulpq->asoc->base.sk), + &ulpq->reasm, first_frag, last_frag); return retval; } diff --git a/net/strparser/strparser.c b/net/strparser/strparser.c index 8f0c91561518..cd9954c4ad80 100644 --- a/net/strparser/strparser.c +++ b/net/strparser/strparser.c @@ -238,7 +238,7 @@ static int __strp_recv(read_descriptor_t *desc, struct sk_buff *orig_skb, strp_parser_err(strp, -EMSGSIZE, desc); break; } else if (len <= (ssize_t)head->len - - (ssize_t)skb->len - stm->strp.offset) { + skb->len - stm->strp.offset) { /* Length must be into new skb (and also * greater than zero) */ diff --git a/net/sunrpc/sysctl.c b/net/sunrpc/sysctl.c index 999eee1ed61c..d75f17b56f0e 100644 --- a/net/sunrpc/sysctl.c +++ b/net/sunrpc/sysctl.c @@ -60,7 +60,7 @@ rpc_unregister_sysctl(void) } static int proc_do_xprt(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { char tmpbuf[256]; size_t len; @@ -70,15 +70,15 @@ static int proc_do_xprt(struct ctl_table *table, int write, return 0; } len = svc_print_xprts(tmpbuf, sizeof(tmpbuf)); - return memory_read_from_buffer(buffer, *lenp, ppos, tmpbuf, len); + return simple_read_from_buffer(buffer, *lenp, ppos, tmpbuf, len); } static int -proc_dodebug(struct ctl_table *table, int write, void *buffer, size_t *lenp, - loff_t *ppos) +proc_dodebug(struct ctl_table *table, int write, + void __user *buffer, size_t *lenp, loff_t *ppos) { - char tmpbuf[20], *s = NULL; - char *p; + char tmpbuf[20], c, *s = NULL; + char __user *p; unsigned int value; size_t left, len; @@ -90,17 +90,18 @@ proc_dodebug(struct ctl_table *table, int write, void *buffer, size_t *lenp, left = *lenp; if (write) { + if (!access_ok(buffer, left)) + return -EFAULT; p = buffer; - while (left && isspace(*p)) { - left--; - p++; - } + while (left && __get_user(c, p) >= 0 && isspace(c)) + left--, p++; if (!left) goto done; if (left > sizeof(tmpbuf) - 1) return -EINVAL; - memcpy(tmpbuf, p, left); + if (copy_from_user(tmpbuf, p, left)) + return -EFAULT; tmpbuf[left] = '\0'; value = simple_strtol(tmpbuf, &s, 0); @@ -120,9 +121,11 @@ proc_dodebug(struct ctl_table *table, int write, void *buffer, size_t *lenp, len = sprintf(tmpbuf, "0x%04x", *(unsigned int *) table->data); if (len > left) len = left; - memcpy(buffer, tmpbuf, len); + if (copy_to_user(buffer, tmpbuf, len)) + return -EFAULT; if ((left -= len) > 0) { - *((char *)buffer + len) = '\n'; + if (put_user('\n', (char __user *)buffer + len)) + return -EFAULT; left--; } } diff --git a/net/sunrpc/xprtrdma/svc_rdma.c b/net/sunrpc/xprtrdma/svc_rdma.c index 526da5d4710b..97bca509a391 100644 --- a/net/sunrpc/xprtrdma/svc_rdma.c +++ b/net/sunrpc/xprtrdma/svc_rdma.c @@ -80,7 +80,8 @@ atomic_t rdma_stat_sq_prod; * current value. */ static int read_reset_stat(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, + loff_t *ppos) { atomic_t *stat = (atomic_t *)table->data; @@ -102,8 +103,8 @@ static int read_reset_stat(struct ctl_table *table, int write, len -= *ppos; if (len > *lenp) len = *lenp; - if (len) - memcpy(buffer, str_buf, len); + if (len && copy_to_user(buffer, str_buf, len)) + return -EFAULT; *lenp = len; *ppos += len; } diff --git a/net/sunrpc/xprtsock.c b/net/sunrpc/xprtsock.c index 7f2fbaf04e07..15a75e86c894 100644 --- a/net/sunrpc/xprtsock.c +++ b/net/sunrpc/xprtsock.c @@ -2256,7 +2256,8 @@ static void xs_tcp_set_socket_timeouts(struct rpc_xprt *xprt, /* TCP Keepalive options */ kernel_setsockopt(sock, SOL_SOCKET, SO_KEEPALIVE, (char *)&opt_on, sizeof(opt_on)); - tcp_sock_set_keepidle(sock->sk, keepidle); + kernel_setsockopt(sock, SOL_TCP, TCP_KEEPIDLE, + (char *)&keepidle, sizeof(keepidle)); kernel_setsockopt(sock, SOL_TCP, TCP_KEEPINTVL, (char *)&keepidle, sizeof(keepidle)); kernel_setsockopt(sock, SOL_TCP, TCP_KEEPCNT, diff --git a/net/tipc/core.c b/net/tipc/core.c index cce4cde3f5f1..58ee5ee70781 100644 --- a/net/tipc/core.c +++ b/net/tipc/core.c @@ -59,7 +59,7 @@ static int __net_init tipc_init_net(struct net *net) tn->trial_addr = 0; tn->addr_trial_end = 0; tn->capabilities = TIPC_NODE_CAPABILITIES; - INIT_WORK(&tn->work, tipc_net_finalize_work); + INIT_WORK(&tn->final_work.work, tipc_net_finalize_work); memset(tn->node_id, 0, sizeof(tn->node_id)); memset(tn->node_id_string, 0, sizeof(tn->node_id_string)); tn->mon_threshold = TIPC_DEF_MON_THRESHOLD; @@ -101,7 +101,7 @@ static void __net_exit tipc_exit_net(struct net *net) tipc_detach_loopback(net); /* Make sure the tipc_net_finalize_work() finished */ - cancel_work_sync(&tn->work); + cancel_work_sync(&tn->final_work.work); tipc_net_stop(net); tipc_bcast_stop(net); diff --git a/net/tipc/core.h b/net/tipc/core.h index 32c5945c8933..59f97ef12e60 100644 --- a/net/tipc/core.h +++ b/net/tipc/core.h @@ -87,6 +87,12 @@ extern unsigned int tipc_net_id __read_mostly; extern int sysctl_tipc_rmem[3] __read_mostly; extern int sysctl_tipc_named_timeout __read_mostly; +struct tipc_net_work { + struct work_struct work; + struct net *net; + u32 addr; +}; + struct tipc_net { u8 node_id[NODE_ID_LEN]; u32 node_addr; @@ -137,7 +143,7 @@ struct tipc_net { struct packet_type loopback_pt; /* Work item for net finalize */ - struct work_struct work; + struct tipc_net_work final_work; /* The numbers of work queues in schedule */ atomic_t wq_count; }; diff --git a/net/tipc/discover.c b/net/tipc/discover.c index a6aa9ecc4a0b..9c64567f8a74 100644 --- a/net/tipc/discover.c +++ b/net/tipc/discover.c @@ -167,7 +167,7 @@ static bool tipc_disc_addr_trial_msg(struct tipc_discoverer *d, /* Apply trial address if we just left trial period */ if (!trial && !self) { - schedule_work(&tn->work); + tipc_sched_net_finalize(net, tn->trial_addr); msg_set_prevnode(buf_msg(d->skb), tn->trial_addr); msg_set_type(buf_msg(d->skb), DSC_REQ_MSG); } @@ -310,7 +310,7 @@ static void tipc_disc_timeout(struct timer_list *t) if (!time_before(jiffies, tn->addr_trial_end) && !tipc_own_addr(net)) { mod_timer(&d->timer, jiffies + TIPC_DISC_INIT); spin_unlock_bh(&d->lock); - schedule_work(&tn->work); + tipc_sched_net_finalize(net, tn->trial_addr); return; } diff --git a/net/tipc/link.c b/net/tipc/link.c index 38da4ec34c51..893c205ea403 100644 --- a/net/tipc/link.c +++ b/net/tipc/link.c @@ -332,11 +332,6 @@ char tipc_link_plane(struct tipc_link *l) return l->net_plane; } -struct net *tipc_link_net(struct tipc_link *l) -{ - return l->net; -} - void tipc_link_update_caps(struct tipc_link *l, u16 capabilities) { l->peer_caps = capabilities; diff --git a/net/tipc/link.h b/net/tipc/link.h index 5ac43acce958..adcad65e761c 100644 --- a/net/tipc/link.h +++ b/net/tipc/link.h @@ -151,5 +151,4 @@ int tipc_link_bc_sync_rcv(struct tipc_link *l, struct tipc_msg *hdr, int tipc_link_bc_nack_rcv(struct tipc_link *l, struct sk_buff *skb, struct sk_buff_head *xmitq); bool tipc_link_too_silent(struct tipc_link *l); -struct net *tipc_link_net(struct tipc_link *l); #endif diff --git a/net/tipc/msg.c b/net/tipc/msg.c index 5ba2c8ec8e11..ff167decbef1 100644 --- a/net/tipc/msg.c +++ b/net/tipc/msg.c @@ -175,20 +175,8 @@ int tipc_buf_append(struct sk_buff **headbuf, struct sk_buff **buf) if (fragid == LAST_FRAGMENT) { TIPC_SKB_CB(head)->validated = false; - - /* If the reassembled skb has been freed in - * tipc_msg_validate() because of an invalid truesize, - * then head will point to a newly allocated reassembled - * skb, while *headbuf points to freed reassembled skb. - * In such cases, correct *headbuf for freeing the newly - * allocated reassembled skb later. - */ - if (unlikely(!tipc_msg_validate(&head))) { - if (head != *headbuf) - *headbuf = head; + if (unlikely(!tipc_msg_validate(&head))) goto err; - } - *buf = head; TIPC_SKB_CB(head)->tail = NULL; *headbuf = NULL; diff --git a/net/tipc/net.c b/net/tipc/net.c index 81c0b123875a..2498ce8b83c1 100644 --- a/net/tipc/net.c +++ b/net/tipc/net.c @@ -41,7 +41,6 @@ #include "socket.h" #include "node.h" #include "bcast.h" -#include "link.h" #include "netlink.h" #include "monitor.h" @@ -139,11 +138,19 @@ static void tipc_net_finalize(struct net *net, u32 addr) void tipc_net_finalize_work(struct work_struct *work) { - struct tipc_net *tn = container_of(work, struct tipc_net, work); + struct tipc_net_work *fwork; - rtnl_lock(); - tipc_net_finalize(tipc_link_net(tn->bcl), tn->trial_addr); - rtnl_unlock(); + fwork = container_of(work, struct tipc_net_work, work); + tipc_net_finalize(fwork->net, fwork->addr); +} + +void tipc_sched_net_finalize(struct net *net, u32 addr) +{ + struct tipc_net *tn = tipc_net(net); + + tn->final_work.net = net; + tn->final_work.addr = addr; + schedule_work(&tn->final_work.work); } void tipc_net_stop(struct net *net) diff --git a/net/tls/tls_main.c b/net/tls/tls_main.c index f8da20f369f1..cb51a2f46b11 100644 --- a/net/tls/tls_main.c +++ b/net/tls/tls_main.c @@ -181,9 +181,12 @@ int tls_proccess_cmsg(struct sock *sk, struct msghdr *msg, if (msg->msg_flags & MSG_MORE) return -EINVAL; - *record_type = *(unsigned char *)CMSG_DATA(cmsg); - rc = tls_handle_open_record(sk, msg->msg_flags); + if (rc) + return rc; + + *record_type = *(unsigned char *)CMSG_DATA(cmsg); + rc = 0; break; default: return -EINVAL; @@ -806,8 +809,7 @@ static void tls_update(struct sock *sk, struct proto *p, ctx->sk_write_space = write_space; ctx->sk_proto = p; } else { - /* Pairs with lockless read in sk_clone_lock(). */ - WRITE_ONCE(sk->sk_prot, p); + sk->sk_prot = p; sk->sk_write_space = write_space; } } diff --git a/net/tls/tls_sw.c b/net/tls/tls_sw.c index b175f0595a47..8dabbbf52168 100644 --- a/net/tls/tls_sw.c +++ b/net/tls/tls_sw.c @@ -1052,13 +1052,6 @@ alloc_encrypted: else if (ret != -EAGAIN) goto send_end; } - - /* Transmit if any encryptions have completed */ - if (test_and_clear_bit(BIT_TX_SCHEDULED, &ctx->tx_bitmask)) { - cancel_delayed_work(&ctx->tx_work.work); - tls_tx_records(sk, msg->msg_flags); - } - continue; rollback_iter: copied -= try_to_copy; @@ -1113,12 +1106,6 @@ fallback_to_reg_send: goto send_end; } } - - /* Transmit if any encryptions have completed */ - if (test_and_clear_bit(BIT_TX_SCHEDULED, &ctx->tx_bitmask)) { - cancel_delayed_work(&ctx->tx_work.work); - tls_tx_records(sk, msg->msg_flags); - } } continue; diff --git a/net/vmw_vsock/af_vsock.c b/net/vmw_vsock/af_vsock.c index 2202a8ba2dfd..831ca8da8481 100644 --- a/net/vmw_vsock/af_vsock.c +++ b/net/vmw_vsock/af_vsock.c @@ -1235,40 +1235,18 @@ static int vsock_stream_connect(struct socket *sock, struct sockaddr *addr, timeout = schedule_timeout(timeout); lock_sock(sk); - /* Connection established. Whatever happens to socket once we - * release it, that's not connect()'s concern. No need to go - * into signal and timeout handling. Call it a day. - * - * Note that allowing to "reset" an already established socket - * here is racy and insecure. - */ - if (sk->sk_state == TCP_ESTABLISHED) - break; - - /* If connection was _not_ established and a signal/timeout came - * to be, we want the socket's state reset. User space may want - * to retry. - * - * sk_state != TCP_ESTABLISHED implies that socket is not on - * vsock_connected_table. We keep the binding and the transport - * assigned. - */ - if (signal_pending(current) || timeout == 0) { - err = timeout == 0 ? -ETIMEDOUT : sock_intr_errno(timeout); - - /* Listener might have already responded with - * VIRTIO_VSOCK_OP_RESPONSE. Its handling expects our - * sk_state == TCP_SYN_SENT, which hereby we break. - * In such case VIRTIO_VSOCK_OP_RST will follow. - */ + if (signal_pending(current)) { + err = sock_intr_errno(timeout); + sk->sk_state = sk->sk_state == TCP_ESTABLISHED ? TCP_CLOSING : TCP_CLOSE; + sock->state = SS_UNCONNECTED; + vsock_transport_cancel_pkt(vsk); + vsock_remove_connected(vsk); + goto out_wait; + } else if ((sk->sk_state != TCP_ESTABLISHED) && (timeout == 0)) { + err = -ETIMEDOUT; sk->sk_state = TCP_CLOSE; sock->state = SS_UNCONNECTED; - - /* Try to cancel VIRTIO_VSOCK_OP_REQUEST skb sent out by - * transport->connect(). - */ vsock_transport_cancel_pkt(vsk); - goto out_wait; } diff --git a/net/xdp/Makefile b/net/xdp/Makefile index 90b5460d6166..71e2bdafb2ce 100644 --- a/net/xdp/Makefile +++ b/net/xdp/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_XDP_SOCKETS) += xsk.o xdp_umem.o xsk_queue.o xskmap.o +obj-$(CONFIG_XDP_SOCKETS) += xsk.o xdp_umem.o xsk_queue.o obj-$(CONFIG_XDP_SOCKETS_DIAG) += xsk_diag.o diff --git a/net/xdp/xsk.c b/net/xdp/xsk.c index 900c9622009a..2ffcda7b1678 100644 --- a/net/xdp/xsk.c +++ b/net/xdp/xsk.c @@ -31,8 +31,6 @@ #define TX_BATCH_SIZE 16 -static DEFINE_PER_CPU(struct list_head, xskmap_flush_list); - bool xsk_is_setup_for_bpf_map(struct xdp_sock *xs) { return READ_ONCE(xs->rx) && READ_ONCE(xs->umem) && @@ -199,7 +197,7 @@ static bool xsk_is_bound(struct xdp_sock *xs) return false; } -static int xsk_rcv(struct xdp_sock *xs, struct xdp_buff *xdp) +int xsk_rcv(struct xdp_sock *xs, struct xdp_buff *xdp) { u32 len; @@ -215,7 +213,7 @@ static int xsk_rcv(struct xdp_sock *xs, struct xdp_buff *xdp) __xsk_rcv_zc(xs, xdp, len) : __xsk_rcv(xs, xdp, len); } -static void xsk_flush(struct xdp_sock *xs) +void xsk_flush(struct xdp_sock *xs) { xskq_produce_flush_desc(xs->rx); xs->sk.sk_data_ready(&xs->sk); @@ -267,32 +265,6 @@ out_unlock: return err; } -int __xsk_map_redirect(struct xdp_sock *xs, struct xdp_buff *xdp) -{ - struct list_head *flush_list = this_cpu_ptr(&xskmap_flush_list); - int err; - - err = xsk_rcv(xs, xdp); - if (err) - return err; - - if (!xs->flush_node.prev) - list_add(&xs->flush_node, flush_list); - - return 0; -} - -void __xsk_map_flush(void) -{ - struct list_head *flush_list = this_cpu_ptr(&xskmap_flush_list); - struct xdp_sock *xs, *tmp; - - list_for_each_entry_safe(xs, tmp, flush_list, flush_node) { - xsk_flush(xs); - __list_del_clearprev(&xs->flush_node); - } -} - void xsk_umem_complete_tx(struct xdp_umem *umem, u32 nb_entries) { xskq_produce_flush_addr_n(umem->cq, nb_entries); @@ -1190,7 +1162,7 @@ static struct pernet_operations xsk_net_ops = { static int __init xsk_init(void) { - int err, cpu; + int err; err = proto_register(&xsk_proto, 0 /* no slab */); if (err) @@ -1208,8 +1180,6 @@ static int __init xsk_init(void) if (err) goto out_pernet; - for_each_possible_cpu(cpu) - INIT_LIST_HEAD(&per_cpu(xskmap_flush_list, cpu)); return 0; out_pernet: diff --git a/net/xdp/xsk.h b/net/xdp/xsk.h index d6a0979050e6..4cfd106bdb53 100644 --- a/net/xdp/xsk.h +++ b/net/xdp/xsk.h @@ -17,25 +17,9 @@ struct xdp_mmap_offsets_v1 { struct xdp_ring_offset_v1 cr; }; -/* Nodes are linked in the struct xdp_sock map_list field, and used to - * track which maps a certain socket reside in. - */ - -struct xsk_map_node { - struct list_head node; - struct xsk_map *map; - struct xdp_sock **map_entry; -}; - static inline struct xdp_sock *xdp_sk(struct sock *sk) { return (struct xdp_sock *)sk; } -bool xsk_is_setup_for_bpf_map(struct xdp_sock *xs); -void xsk_map_try_sock_delete(struct xsk_map *map, struct xdp_sock *xs, - struct xdp_sock **map_entry); -int xsk_map_inc(struct xsk_map *map); -void xsk_map_put(struct xsk_map *map); - #endif /* XSK_H_ */ diff --git a/net/xfrm/Kconfig b/net/xfrm/Kconfig index 86656a3dc24f..e5815cb2c297 100644 --- a/net/xfrm/Kconfig +++ b/net/xfrm/Kconfig @@ -3,13 +3,13 @@ # XFRM configuration # config XFRM - bool - depends on INET - select GRO_CELLS - select SKB_EXTENSIONS + bool + depends on INET + select GRO_CELLS + select SKB_EXTENSIONS config XFRM_OFFLOAD - bool + bool config XFRM_ALGO tristate diff --git a/samples/bpf/xdp_monitor_kern.c b/samples/bpf/xdp_monitor_kern.c index 39458a44472e..ad10fe700d7d 100644 --- a/samples/bpf/xdp_monitor_kern.c +++ b/samples/bpf/xdp_monitor_kern.c @@ -222,12 +222,14 @@ struct bpf_map_def SEC("maps") devmap_xmit_cnt = { */ struct devmap_xmit_ctx { u64 __pad; // First 8 bytes are not accessible by bpf code - int from_ifindex; // offset:8; size:4; signed:1; + int map_id; // offset:8; size:4; signed:1; u32 act; // offset:12; size:4; signed:0; - int to_ifindex; // offset:16; size:4; signed:1; + u32 map_index; // offset:16; size:4; signed:0; int drops; // offset:20; size:4; signed:1; int sent; // offset:24; size:4; signed:1; - int err; // offset:28; size:4; signed:1; + int from_ifindex; // offset:28; size:4; signed:1; + int to_ifindex; // offset:32; size:4; signed:1; + int err; // offset:36; size:4; signed:1; }; SEC("tracepoint/xdp/xdp_devmap_xmit") diff --git a/scripts/Kconfig.include b/scripts/Kconfig.include index 363c354e9562..496d11c92c97 100644 --- a/scripts/Kconfig.include +++ b/scripts/Kconfig.include @@ -51,9 +51,3 @@ gcc-version := $(shell,$(srctree)/scripts/gcc-version.sh $(CC)) cc-option-bit = $(if-success,$(CC) -Werror $(1) -E -x c /dev/null -o /dev/null,$(1)) m32-flag := $(cc-option-bit,-m32) m64-flag := $(cc-option-bit,-m64) - -# Get the assembler name, version, and error out if it is not supported. -as-info := $(shell,$(srctree)/scripts/as-version.sh $(CC) $(CLANG_FLAGS)) -$(error-if,$(success,test -z "$(as-info)"),Sorry$(comma) this assembler is not supported.) -as-name := $(shell,set -- $(as-info) && echo $1) -as-version := $(shell,set -- $(as-info) && echo $2) diff --git a/scripts/as-version.sh b/scripts/as-version.sh deleted file mode 100755 index 532270bd4b7e..000000000000 --- a/scripts/as-version.sh +++ /dev/null @@ -1,69 +0,0 @@ -#!/bin/sh -# SPDX-License-Identifier: GPL-2.0-only -# -# Print the assembler name and its version in a 5 or 6-digit form. -# Also, perform the minimum version check. -# (If it is the integrated assembler, return 0 as the version, and -# skip the version check.) - -set -e - -# Convert the version string x.y.z to a canonical 5 or 6-digit form. -get_canonical_version() -{ - IFS=. - set -- $1 - - # If the 2nd or 3rd field is missing, fill it with a zero. - # - # The 4th field, if present, is ignored. - # This occurs in development snapshots as in 2.35.1.20201116 - echo $((10000 * $1 + 100 * ${2:-0} + ${3:-0})) -} - -# Clang fails to handle -Wa,--version unless -fno-integrated-as is given. -# We check -fintegrated-as, expecting it is explicitly passed in for the -# integrated assembler case. -check_integrated_as() -{ - while [ $# -gt 0 ]; do - if [ "$1" = -fintegrated-as ]; then - # For the integrated assembler, we do not check the - # version here. It is the same as the clang version, and - # it has been already checked by scripts/cc-version.sh. - echo LLVM 0 - exit 0 - fi - shift - done -} - -check_integrated_as "$@" - -orig_args="$@" - -# Get the first line of the --version output. -IFS=' -' -set -- $(LC_ALL=C "$@" -Wa,--version -c -x assembler /dev/null -o /dev/null 2>/dev/null) - -# Split the line on spaces. -IFS=' ' -set -- $1 - -if [ "$1" = GNU -a "$2" = assembler ]; then - shift $(($# - 1)) - version=$1 - name=GNU -else - echo "$orig_args: unknown assembler invoked" >&2 - exit 1 -fi - -# Some distributions append a package release number, as in 2.34-4.fc32 -# Trim the hyphen and any characters that follow. -version=${version%-*} - -cversion=$(get_canonical_version $version) - -echo $name $cversion diff --git a/scripts/bpf_helpers_doc.py b/scripts/bpf_helpers_doc.py index eddd676f4cae..030a843a4794 100755 --- a/scripts/bpf_helpers_doc.py +++ b/scripts/bpf_helpers_doc.py @@ -320,11 +320,6 @@ may be interested in: of eBPF maps are used with a given helper function. * *kernel/bpf/* directory contains other files in which additional helpers are defined (for cgroups, sockmaps, etc.). -* The bpftool utility can be used to probe the availability of helper functions - on the system (as well as supported program and map types, and a number of - other parameters). To do so, run **bpftool feature probe** (see - **bpftool-feature**\ (8) for details). Add the **unprivileged** keyword to - list features available to unprivileged users. Compatibility between helper functions and program types can generally be found in the files where helper functions are defined. Look for the **struct @@ -345,7 +340,6 @@ SEE ALSO ======== **bpf**\ (2), -**bpftool**\ (8), **cgroups**\ (7), **ip**\ (8), **perf_event_open**\ (2), @@ -406,7 +400,6 @@ class PrinterHelpers(Printer): type_fwds = [ 'struct bpf_fib_lookup', - 'struct bpf_sk_lookup', 'struct bpf_perf_event_data', 'struct bpf_perf_event_value', 'struct bpf_sock', @@ -422,19 +415,10 @@ class PrinterHelpers(Printer): 'struct sk_reuseport_md', 'struct sockaddr', 'struct tcphdr', - 'struct seq_file', - 'struct tcp6_sock', - 'struct tcp_sock', - 'struct tcp_timewait_sock', - 'struct tcp_request_sock', - 'struct udp6_sock', - 'struct task_struct', 'struct __sk_buff', 'struct sk_msg_md', 'struct xdp_md', - 'struct path', - 'struct btf_ptr', ] known_types = { '...', @@ -453,9 +437,6 @@ class PrinterHelpers(Printer): 'struct bpf_fib_lookup', 'struct bpf_perf_event_data', 'struct bpf_perf_event_value', - 'struct bpf_pidns_info', - 'struct bpf_redir_neigh', - 'struct bpf_sk_lookup', 'struct bpf_sock', 'struct bpf_sock_addr', 'struct bpf_sock_ops', @@ -469,15 +450,6 @@ class PrinterHelpers(Printer): 'struct sk_reuseport_md', 'struct sockaddr', 'struct tcphdr', - 'struct seq_file', - 'struct tcp6_sock', - 'struct tcp_sock', - 'struct tcp_timewait_sock', - 'struct tcp_request_sock', - 'struct udp6_sock', - 'struct task_struct', - 'struct path', - 'struct btf_ptr', } mapped_types = { 'u8': '__u8', @@ -495,11 +467,6 @@ class PrinterHelpers(Printer): 'struct sk_msg_buff': 'struct sk_msg_md', 'struct xdp_buff': 'struct xdp_md', } - # Helpers overloaded for different context types. - overloaded_helpers = [ - 'bpf_get_socket_cookie', - 'bpf_sk_assign', - ] def print_header(self): header = '''\ @@ -556,7 +523,7 @@ class PrinterHelpers(Printer): for i, a in enumerate(proto['args']): t = a['type'] n = a['name'] - if proto['name'] in self.overloaded_helpers and i == 0: + if proto['name'] == 'bpf_get_socket_cookie' and i == 0: t = 'void' n = 'ctx' one_arg = '{}{}'.format(comma, self.map_type(t)) diff --git a/scripts/dummy-tools/gcc b/scripts/dummy-tools/gcc deleted file mode 100755 index 9f5e943e7491..000000000000 --- a/scripts/dummy-tools/gcc +++ /dev/null @@ -1,98 +0,0 @@ -#!/bin/sh -# SPDX-License-Identifier: GPL-2.0-only -# -# Staring v4.18, Kconfig evaluates compiler capabilities, and hides CONFIG -# options your compiler does not support. This works well if you configure and -# build the kernel on the same host machine. -# -# It is inconvenient if you prepare the .config that is carried to a different -# build environment (typically this happens when you package the kernel for -# distros) because using a different compiler potentially produces different -# CONFIG options than the real build environment. So, you probably want to make -# as many options visible as possible. In other words, you need to create a -# super-set of CONFIG options that cover any build environment. If some of the -# CONFIG options turned out to be unsupported on the build machine, they are -# automatically disabled by the nature of Kconfig. -# -# However, it is not feasible to get a full-featured compiler for every arch. -# Hence these dummy toolchains to make all compiler tests pass. -# -# Usage: -# -# From the top directory of the source tree, run -# -# $ make CROSS_COMPILE=scripts/dummy-tools/ oldconfig -# -# Most of compiler features are tested by cc-option, which simply checks the -# exit code of $(CC). This script does nothing and just exits with 0 in most -# cases. So, $(cc-option, ...) is evaluated as 'y'. -# -# This scripts caters to more checks; handle --version and pre-process __GNUC__ -# etc. to pretend to be GCC, and also do right things to satisfy some scripts. - -# Check if the first parameter appears in the rest. Succeeds if found. -# This helper is useful if a particular option was passed to this script. -# Typically used like this: -# arg_contain "$@" -arg_contain () -{ - search="$1" - shift - - while [ $# -gt 0 ] - do - if [ "$search" = "$1" ]; then - return 0 - fi - shift - done - - return 1 -} - -# To set CONFIG_CC_IS_GCC=y -if arg_contain --version "$@"; then - echo "gcc (scripts/dummy-tools/gcc)" - exit 0 -fi - -if arg_contain -E "$@"; then - # For scripts/gcc-version.sh; This emulates GCC 20.0.0 - if arg_contain - "$@"; then - sed 's/^__GNUC__$/20/; s/^__GNUC_MINOR__$/0/; s/^__GNUC_PATCHLEVEL__$/0/' - exit 0 - else - echo "no input files" >&2 - exit 1 - fi -fi - -# To set CONFIG_AS_IS_GNU -if arg_contain -Wa,--version "$@"; then - echo "GNU assembler (scripts/dummy-tools) 2.50" - exit 0 -fi - -if arg_contain -S "$@"; then - # For scripts/gcc-x86-*-has-stack-protector.sh - if arg_contain -fstack-protector "$@"; then - echo "%gs" - exit 0 - fi -fi - -# To set GCC_PLUGINS -if arg_contain -print-file-name=plugin "$@"; then - plugin_dir=$(mktemp -d) - - mkdir -p $plugin_dir/include - touch $plugin_dir/include/plugin-version.h - - echo $plugin_dir - exit 0 -fi - -# inverted return value -if arg_contain -D__SIZEOF_INT128__=0 "$@"; then - exit 1 -fi diff --git a/scripts/dummy-tools/ld b/scripts/dummy-tools/ld deleted file mode 100755 index f68233050405..000000000000 --- a/scripts/dummy-tools/ld +++ /dev/null @@ -1,30 +0,0 @@ -#!/bin/sh -# SPDX-License-Identifier: GPL-2.0-only - -# Dummy script that always succeeds. - -# Check if the first parameter appears in the rest. Succeeds if found. -# This helper is useful if a particular option was passed to this script. -# Typically used like this: -# arg_contain "$@" -arg_contain () -{ - search="$1" - shift - - while [ $# -gt 0 ] - do - if [ "$search" = "$1" ]; then - return 0 - fi - shift - done - - return 1 -} - -if arg_contain --version "$@" || arg_contain -v "$@"; then - progname=$(basename $0) - echo "GNU $progname (scripts/dummy-tools/$progname) 2.50" - exit 0 -fi diff --git a/scripts/dummy-tools/nm b/scripts/dummy-tools/nm deleted file mode 120000 index c0648b38dd42..000000000000 --- a/scripts/dummy-tools/nm +++ /dev/null @@ -1 +0,0 @@ -ld \ No newline at end of file diff --git a/scripts/dummy-tools/objcopy b/scripts/dummy-tools/objcopy deleted file mode 120000 index c0648b38dd42..000000000000 --- a/scripts/dummy-tools/objcopy +++ /dev/null @@ -1 +0,0 @@ -ld \ No newline at end of file diff --git a/scripts/headers_install.sh b/scripts/headers_install.sh index da1d8fe8380a..be8626cdcd12 100755 --- a/scripts/headers_install.sh +++ b/scripts/headers_install.sh @@ -97,7 +97,6 @@ include/uapi/linux/eventpoll.h:CONFIG_PM_SLEEP include/uapi/linux/hw_breakpoint.h:CONFIG_HAVE_MIXED_BREAKPOINTS_REGS include/uapi/linux/pktcdvd.h:CONFIG_CDROM_PKTCDVD_WCACHE include/uapi/linux/raw.h:CONFIG_MAX_RAW_DEVS -techpack/camera/include/uapi/camera/media/cam_ope.h:CONFIG_SPECTRA_CAMERA_LEGACY " for c in $configs diff --git a/scripts/kconfig/mconf.c b/scripts/kconfig/mconf.c index fe57b4071e91..49c26ea9dd98 100644 --- a/scripts/kconfig/mconf.c +++ b/scripts/kconfig/mconf.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -1008,8 +1007,6 @@ int main(int ac, char **av) signal(SIGINT, sig_handler); - setlocale(LC_ALL, ""); - if (ac > 1 && strcmp(av[1], "-s") == 0) { silent = 1; /* Silence conf_read() until the real callback is set up */ diff --git a/scripts/kconfig/nconf.c b/scripts/kconfig/nconf.c index 7c126569e6cb..af56d27693d0 100644 --- a/scripts/kconfig/nconf.c +++ b/scripts/kconfig/nconf.c @@ -7,7 +7,6 @@ #ifndef _GNU_SOURCE #define _GNU_SOURCE #endif -#include #include #include @@ -1479,8 +1478,6 @@ int main(int ac, char **av) int lines, columns; char *mode; - setlocale(LC_ALL, ""); - if (ac > 1 && strcmp(av[1], "-s") == 0) { /* Silence conf_read() until the real callback is set up */ conf_set_message_callback(NULL); diff --git a/scripts/link-vmlinux.sh b/scripts/link-vmlinux.sh index c56226e21ddd..ab262fdd24f5 100755 --- a/scripts/link-vmlinux.sh +++ b/scripts/link-vmlinux.sh @@ -440,12 +440,6 @@ fi vmlinux_link vmlinux "${kallsymso}" ${btf_vmlinux_bin_o} -# fill in BTF IDs -if [ -n "${CONFIG_DEBUG_INFO_BTF}" ]; then -info BTFIDS vmlinux -${RESOLVE_BTFIDS} vmlinux -fi - if [ -n "${CONFIG_BUILDTIME_EXTABLE_SORT}" ]; then info SORTEX vmlinux sortextable vmlinux diff --git a/scripts/tools-support-relr.sh b/scripts/tools-support-relr.sh index 4c121946e517..cb55878bd5b8 100755 --- a/scripts/tools-support-relr.sh +++ b/scripts/tools-support-relr.sh @@ -7,12 +7,8 @@ trap "rm -f $tmp_file.o $tmp_file $tmp_file.bin" EXIT cat << "END" | $CC -c -x c - -o $tmp_file.o >/dev/null 2>&1 void *p = &p; END - -# ld.lld before 15 did not support -z pack-relative-relocs. -if ! $LD $tmp_file.o -shared -Bsymbolic --pack-dyn-relocs=relr -o $tmp_file 2>/dev/null; then - $LD $tmp_file.o -shared -Bsymbolic -z pack-relative-relocs -o $tmp_file 2>&1 | - grep -q pack-relative-relocs && exit 1 -fi +$LD $tmp_file.o -shared -Bsymbolic --pack-dyn-relocs=relr \ + --use-android-relr-tags -o $tmp_file # Despite printing an error message, GNU nm still exits with exit code 0 if it # sees a relr section. So we need to check that nothing is printed to stderr. diff --git a/security/Kconfig b/security/Kconfig index 809f242ae505..b3dff990c326 100644 --- a/security/Kconfig +++ b/security/Kconfig @@ -312,11 +312,11 @@ endchoice config LSM string "Ordered list of enabled LSMs" - default "lockdown,yama,loadpin,safesetid,integrity,smack,selinux,tomoyo,apparmor,bpf" if DEFAULT_SECURITY_SMACK - default "lockdown,yama,loadpin,safesetid,integrity,apparmor,selinux,smack,tomoyo,bpf" if DEFAULT_SECURITY_APPARMOR - default "lockdown,yama,loadpin,safesetid,integrity,tomoyo,bpf" if DEFAULT_SECURITY_TOMOYO - default "lockdown,yama,loadpin,safesetid,integrity,bpf" if DEFAULT_SECURITY_DAC - default "lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor,bpf" + default "lockdown,yama,loadpin,safesetid,integrity,smack,selinux,tomoyo,apparmor" if DEFAULT_SECURITY_SMACK + default "lockdown,yama,loadpin,safesetid,integrity,apparmor,selinux,smack,tomoyo" if DEFAULT_SECURITY_APPARMOR + default "lockdown,yama,loadpin,safesetid,integrity,tomoyo" if DEFAULT_SECURITY_TOMOYO + default "lockdown,yama,loadpin,safesetid,integrity" if DEFAULT_SECURITY_DAC + default "lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" help A comma-separated list of LSMs, in initialization order. Any LSMs left off this list will be ignored. This can be diff --git a/security/Makefile b/security/Makefile index eb00547cc109..be1dd9d2cb2f 100644 --- a/security/Makefile +++ b/security/Makefile @@ -12,7 +12,6 @@ subdir-$(CONFIG_SECURITY_YAMA) += yama subdir-$(CONFIG_SECURITY_LOADPIN) += loadpin subdir-$(CONFIG_SECURITY_SAFESETID) += safesetid subdir-$(CONFIG_SECURITY_LOCKDOWN_LSM) += lockdown -subdir-$(CONFIG_BPF_LSM) += bpf # always enable default capabilities obj-y += commoncap.o @@ -31,7 +30,6 @@ obj-$(CONFIG_SECURITY_LOADPIN) += loadpin/ obj-$(CONFIG_SECURITY_SAFESETID) += safesetid/ obj-$(CONFIG_SECURITY_LOCKDOWN_LSM) += lockdown/ obj-$(CONFIG_CGROUP_DEVICE) += device_cgroup.o -obj-$(CONFIG_BPF_LSM) += bpf/ # Object integrity file lists subdir-$(CONFIG_INTEGRITY) += integrity diff --git a/security/apparmor/lsm.c b/security/apparmor/lsm.c index e88f68b60948..4c69259b62f1 100644 --- a/security/apparmor/lsm.c +++ b/security/apparmor/lsm.c @@ -1583,7 +1583,7 @@ static int __init alloc_buffers(void) #ifdef CONFIG_SYSCTL static int apparmor_dointvec(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { if (!policy_admin_capable(NULL)) return -EPERM; diff --git a/security/bpf/Makefile b/security/bpf/Makefile deleted file mode 100644 index c7a89a962084..000000000000 --- a/security/bpf/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (C) 2020 Google LLC. - -obj-$(CONFIG_BPF_LSM) := hooks.o diff --git a/security/bpf/hooks.c b/security/bpf/hooks.c deleted file mode 100644 index 788667d582ae..000000000000 --- a/security/bpf/hooks.c +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* - * Copyright (C) 2020 Google LLC. - */ -#include -#include - -static struct security_hook_list bpf_lsm_hooks[] __lsm_ro_after_init = { - #define LSM_HOOK(RET, DEFAULT, NAME, ...) \ - LSM_HOOK_INIT(NAME, bpf_lsm_##NAME), - #include - #undef LSM_HOOK - LSM_HOOK_INIT(inode_free_security, bpf_inode_storage_free), -}; - -static int __init bpf_lsm_init(void) -{ - security_add_hooks(bpf_lsm_hooks, ARRAY_SIZE(bpf_lsm_hooks), "bpf"); - pr_info("LSM support for eBPF active\n"); - return 0; -} - -struct lsm_blob_sizes bpf_lsm_blob_sizes __lsm_ro_after_init = { - .lbs_inode = sizeof(struct bpf_storage_blob), -}; - -DEFINE_LSM(bpf) = { - .name = "bpf", - .init = bpf_lsm_init, - .blobs = &bpf_lsm_blob_sizes -}; diff --git a/security/keys/trusted.c b/security/keys/trusted.c index 3ee9749c14fb..92a14ab82f72 100644 --- a/security/keys/trusted.c +++ b/security/keys/trusted.c @@ -9,7 +9,6 @@ */ #include -#include #include #include #include @@ -249,7 +248,7 @@ int TSS_checkhmac1(unsigned char *buffer, if (ret < 0) goto out; - if (crypto_memneq(testhmac, authdata, SHA1_DIGEST_SIZE)) + if (memcmp(testhmac, authdata, SHA1_DIGEST_SIZE)) ret = -EINVAL; out: kzfree(sdesc); @@ -342,7 +341,7 @@ static int TSS_checkhmac2(unsigned char *buffer, TPM_NONCE_SIZE, ononce, 1, continueflag1, 0, 0); if (ret < 0) goto out; - if (crypto_memneq(testhmac1, authdata1, SHA1_DIGEST_SIZE)) { + if (memcmp(testhmac1, authdata1, SHA1_DIGEST_SIZE)) { ret = -EINVAL; goto out; } @@ -351,7 +350,7 @@ static int TSS_checkhmac2(unsigned char *buffer, TPM_NONCE_SIZE, ononce, 1, continueflag2, 0, 0); if (ret < 0) goto out; - if (crypto_memneq(testhmac2, authdata2, SHA1_DIGEST_SIZE)) + if (memcmp(testhmac2, authdata2, SHA1_DIGEST_SIZE)) ret = -EINVAL; out: kzfree(sdesc); diff --git a/security/lockdown/lockdown.c b/security/lockdown/lockdown.c index 81dad4f40141..655a6edb5d7f 100644 --- a/security/lockdown/lockdown.c +++ b/security/lockdown/lockdown.c @@ -33,7 +33,6 @@ static const char *const lockdown_reasons[LOCKDOWN_CONFIDENTIALITY_MAX+1] = { [LOCKDOWN_MMIOTRACE] = "unsafe mmio", [LOCKDOWN_DEBUGFS] = "debugfs access", [LOCKDOWN_XMON_WR] = "xmon write access", - [LOCKDOWN_BPF_WRITE_USER] = "use of bpf to write user RAM", [LOCKDOWN_DBG_WRITE_KERNEL] = "use of kgdb/kdb to write kernel RAM", [LOCKDOWN_INTEGRITY_MAX] = "integrity", [LOCKDOWN_KCORE] = "/proc/kcore access", diff --git a/security/min_addr.c b/security/min_addr.c index 88c9a6a21f47..94d2b0cf0e7b 100644 --- a/security/min_addr.c +++ b/security/min_addr.c @@ -30,7 +30,7 @@ static void update_mmap_min_addr(void) * calls update_mmap_min_addr() so non MAP_FIXED hints get rounded properly */ int mmap_min_addr_handler(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { int ret; diff --git a/security/security.c b/security/security.c index 4b1672f2b259..fa2982105e4c 100644 --- a/security/security.c +++ b/security/security.c @@ -636,25 +636,6 @@ static void __init lsm_early_task(struct task_struct *task) panic("%s: Early task alloc failed.\n", __func__); } -/* - * The default value of the LSM hook is defined in linux/lsm_hook_defs.h and - * can be accessed with: - * - * LSM_RET_DEFAULT() - * - * The macros below define static constants for the default value of each - * LSM hook. - */ -#define LSM_RET_DEFAULT(NAME) (NAME##_default) -#define DECLARE_LSM_RET_DEFAULT_void(DEFAULT, NAME) -#define DECLARE_LSM_RET_DEFAULT_int(DEFAULT, NAME) \ - static const int LSM_RET_DEFAULT(NAME) = (DEFAULT); -#define LSM_HOOK(RET, DEFAULT, NAME, ...) \ - DECLARE_LSM_RET_DEFAULT_##RET(DEFAULT, NAME) - -#include -#undef LSM_HOOK - /* * Hook list operation macros. * @@ -1346,16 +1327,16 @@ int security_inode_getsecurity(struct inode *inode, const char *name, void **buf int rc; if (unlikely(IS_PRIVATE(inode))) - return LSM_RET_DEFAULT(inode_getsecurity); + return -EOPNOTSUPP; /* * Only one module will provide an attribute with a given name. */ hlist_for_each_entry(hp, &security_hook_heads.inode_getsecurity, list) { rc = hp->hook.inode_getsecurity(inode, name, buffer, alloc); - if (rc != LSM_RET_DEFAULT(inode_getsecurity)) + if (rc != -EOPNOTSUPP) return rc; } - return LSM_RET_DEFAULT(inode_getsecurity); + return -EOPNOTSUPP; } int security_inode_setsecurity(struct inode *inode, const char *name, const void *value, size_t size, int flags) @@ -1364,17 +1345,17 @@ int security_inode_setsecurity(struct inode *inode, const char *name, const void int rc; if (unlikely(IS_PRIVATE(inode))) - return LSM_RET_DEFAULT(inode_setsecurity); + return -EOPNOTSUPP; /* * Only one module will provide an attribute with a given name. */ hlist_for_each_entry(hp, &security_hook_heads.inode_setsecurity, list) { rc = hp->hook.inode_setsecurity(inode, name, value, size, flags); - if (rc != LSM_RET_DEFAULT(inode_setsecurity)) + if (rc != -EOPNOTSUPP) return rc; } - return LSM_RET_DEFAULT(inode_setsecurity); + return -EOPNOTSUPP; } int security_inode_listsecurity(struct inode *inode, char *buffer, size_t buffer_size) @@ -1766,12 +1747,12 @@ int security_task_prctl(int option, unsigned long arg2, unsigned long arg3, unsigned long arg4, unsigned long arg5) { int thisrc; - int rc = LSM_RET_DEFAULT(task_prctl); + int rc = -ENOSYS; struct security_hook_list *hp; hlist_for_each_entry(hp, &security_hook_heads.task_prctl, list) { thisrc = hp->hook.task_prctl(option, arg2, arg3, arg4, arg5); - if (thisrc != LSM_RET_DEFAULT(task_prctl)) { + if (thisrc != -ENOSYS) { rc = thisrc; if (thisrc != 0) break; @@ -1943,7 +1924,7 @@ int security_getprocattr(struct task_struct *p, const char *lsm, char *name, continue; return hp->hook.getprocattr(p, name, value); } - return LSM_RET_DEFAULT(getprocattr); + return -EINVAL; } int security_setprocattr(const char *lsm, const char *name, void *value, @@ -1956,7 +1937,7 @@ int security_setprocattr(const char *lsm, const char *name, void *value, continue; return hp->hook.setprocattr(name, value, size); } - return LSM_RET_DEFAULT(setprocattr); + return -EINVAL; } int security_netlink_send(struct sock *sk, struct sk_buff *skb) @@ -2341,7 +2322,7 @@ int security_xfrm_state_pol_flow_match(struct xfrm_state *x, const struct flowi *fl) { struct security_hook_list *hp; - int rc = LSM_RET_DEFAULT(xfrm_state_pol_flow_match); + int rc = 1; /* * Since this function is expected to return 0 or 1, the judgment diff --git a/security/selinux/Kconfig b/security/selinux/Kconfig index 4d7d36fde8e8..c9e576c430c2 100644 --- a/security/selinux/Kconfig +++ b/security/selinux/Kconfig @@ -42,9 +42,6 @@ config SECURITY_SELINUX_DISABLE using the selinux=0 boot parameter instead of enabling this option. - WARNING: this option is deprecated and will be removed in a future - kernel release. - If you are unsure how to answer this question, answer N. config SECURITY_SELINUX_DEVELOP @@ -58,8 +55,7 @@ config SECURITY_SELINUX_DEVELOP kernel will start in permissive mode (log everything, deny nothing) unless you specify enforcing=1 on the kernel command line. You can interactively toggle the kernel between enforcing mode and - permissive mode (if permitted by the policy) via - /sys/fs/selinux/enforce. + permissive mode (if permitted by the policy) via /selinux/enforce. config SECURITY_SELINUX_AVC_STATS bool "NSA SELinux AVC Statistics" @@ -67,7 +63,7 @@ config SECURITY_SELINUX_AVC_STATS default y help This option collects access vector cache statistics to - /sys/fs/selinux/avc/cache_stats, which may be monitored via + /selinux/avc/cache_stats, which may be monitored via tools such as avcstat. config SECURITY_SELINUX_CHECKREQPROT_VALUE @@ -86,7 +82,7 @@ config SECURITY_SELINUX_CHECKREQPROT_VALUE default to checking the protection requested by the application. The checkreqprot flag may be changed from the default via the 'checkreqprot=' boot parameter. It may also be changed at runtime - via /sys/fs/selinux/checkreqprot if authorized by policy. + via /selinux/checkreqprot if authorized by policy. If you are unsure how to answer this question, answer 0. diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c index 40bf624d0cb1..abe652fc6eba 100644 --- a/security/selinux/hooks.c +++ b/security/selinux/hooks.c @@ -113,7 +113,7 @@ struct selinux_state selinux_state; static atomic_t selinux_secmark_refcount = ATOMIC_INIT(0); #ifdef CONFIG_SECURITY_SELINUX_DEVELOP -static int selinux_enforcing_boot __initdata; +static int selinux_enforcing_boot; static int __init enforcing_setup(char *str) { @@ -127,13 +127,13 @@ __setup("enforcing=", enforcing_setup); #define selinux_enforcing_boot 1 #endif -int selinux_enabled_boot __initdata = 1; +int selinux_enabled __lsm_ro_after_init = 1; #ifdef CONFIG_SECURITY_SELINUX_BOOTPARAM static int __init selinux_enabled_setup(char *str) { unsigned long enabled; if (!kstrtoul(str, 0, &enabled)) - selinux_enabled_boot = enabled ? 1 : 0; + selinux_enabled = enabled ? 1 : 0; return 1; } __setup("selinux=", selinux_enabled_setup); @@ -276,7 +276,7 @@ static int __inode_security_revalidate(struct inode *inode, might_sleep_if(may_sleep); - if (selinux_initialized(&selinux_state) && + if (selinux_state.initialized && isec->initialized != LABEL_INITIALIZED) { if (!may_sleep) return -ECHILD; @@ -664,7 +664,7 @@ static int selinux_set_mnt_opts(struct super_block *sb, mutex_lock(&sbsec->lock); - if (!selinux_initialized(&selinux_state)) { + if (!selinux_state.initialized) { if (!opts) { /* Defer initialization until selinux_complete_init, after the initial policy is loaded and the security @@ -935,7 +935,7 @@ static int selinux_sb_clone_mnt_opts(const struct super_block *oldsb, * if the parent was able to be mounted it clearly had no special lsm * mount options. thus we can safely deal with this superblock later */ - if (!selinux_initialized(&selinux_state)) + if (!selinux_state.initialized) return 0; /* @@ -1118,7 +1118,7 @@ static int selinux_sb_show_options(struct seq_file *m, struct super_block *sb) if (!(sbsec->flags & SE_SBINITIALIZED)) return 0; - if (!selinux_initialized(&selinux_state)) + if (!selinux_state.initialized) return 0; if (sbsec->flags & FSCONTEXT_MNT) { @@ -1858,8 +1858,8 @@ static int may_create(struct inode *dir, if (rc) return rc; - rc = selinux_determine_inode_label(tsec, dir, &dentry->d_name, tclass, - &newsid); + rc = selinux_determine_inode_label(selinux_cred(current_cred()), dir, + &dentry->d_name, tclass, &newsid); if (rc) return rc; @@ -2936,7 +2936,8 @@ static int selinux_inode_init_security(struct inode *inode, struct inode *dir, newsid = tsec->create_sid; - rc = selinux_determine_inode_label(tsec, dir, qstr, + rc = selinux_determine_inode_label(selinux_cred(current_cred()), + dir, qstr, inode_mode_to_security_class(inode->i_mode), &newsid); if (rc) @@ -2950,8 +2951,7 @@ static int selinux_inode_init_security(struct inode *inode, struct inode *dir, isec->initialized = LABEL_INITIALIZED; } - if (!selinux_initialized(&selinux_state) || - !(sbsec->flags & SBLABEL_MNT)) + if (!selinux_state.initialized || !(sbsec->flags & SBLABEL_MNT)) return -EOPNOTSUPP; if (name) @@ -2978,7 +2978,7 @@ static int selinux_inode_init_security_anon(struct inode *inode, struct inode_security_struct *isec; int rc; - if (unlikely(!selinux_initialized(&selinux_state))) + if (unlikely(!selinux_state.initialized)) return 0; isec = selinux_inode(inode); @@ -3230,7 +3230,7 @@ static int selinux_inode_setxattr(struct dentry *dentry, const char *name, return dentry_has_perm(current_cred(), dentry, FILE__SETATTR); } - if (!selinux_initialized(&selinux_state)) + if (!selinux_state.initialized) return (inode_owner_or_capable(inode) ? 0 : -EPERM); sbsec = inode->i_sb->s_security; @@ -3316,7 +3316,7 @@ static void selinux_inode_post_setxattr(struct dentry *dentry, const char *name, return; } - if (!selinux_initialized(&selinux_state)) { + if (!selinux_state.initialized) { /* If we haven't even been initialized, then we can't validate * against a policy, so leave the label as invalid. It may * resolve to a valid label on the next revalidation try if @@ -3496,10 +3496,6 @@ static int selinux_inode_setsecurity(struct inode *inode, const char *name, static int selinux_inode_listsecurity(struct inode *inode, char *buffer, size_t buffer_size) { const int len = sizeof(XATTR_NAME_SELINUX); - - if (!selinux_initialized(&selinux_state)) - return 0; - if (buffer && len <= buffer_size) memcpy(buffer, XATTR_NAME_SELINUX, len); return len; @@ -3764,7 +3760,7 @@ static int selinux_file_ioctl_compat(struct file *file, unsigned int cmd, return selinux_file_ioctl(file, cmd, arg); } -static int default_noexec __ro_after_init; +static int default_noexec; static int file_map_prot_check(struct file *file, unsigned long prot, int shared) { @@ -5643,6 +5639,64 @@ static int selinux_tun_dev_open(void *security) return 0; } +static int selinux_nlmsg_perm(struct sock *sk, struct sk_buff *skb) +{ + int rc = 0; + unsigned int msg_len; + unsigned int data_len = skb->len; + unsigned char *data = skb->data; + struct nlmsghdr *nlh; + struct sk_security_struct *sksec = sk->sk_security; + u16 sclass = sksec->sclass; + u32 perm; + + while (data_len >= nlmsg_total_size(0)) { + nlh = (struct nlmsghdr *)data; + + /* NOTE: the nlmsg_len field isn't reliably set by some netlink + * users which means we can't reject skb's with bogus + * length fields; our solution is to follow what + * netlink_rcv_skb() does and simply skip processing at + * messages with length fields that are clearly junk + */ + if (nlh->nlmsg_len < NLMSG_HDRLEN || nlh->nlmsg_len > data_len) + return 0; + + rc = selinux_nlmsg_lookup(sclass, nlh->nlmsg_type, &perm); + if (rc == 0) { + rc = sock_has_perm(sk, perm); + if (rc) + return rc; + } else if (rc == -EINVAL) { + /* -EINVAL is a missing msg/perm mapping */ + pr_warn_ratelimited("SELinux: unrecognized netlink" + " message: protocol=%hu nlmsg_type=%hu sclass=%s" + " pid=%d comm=%s\n", + sk->sk_protocol, nlh->nlmsg_type, + secclass_map[sclass - 1].name, + task_pid_nr(current), current->comm); + if (enforcing_enabled(&selinux_state) && + !security_get_allow_unknown(&selinux_state)) + return rc; + rc = 0; + } else if (rc == -ENOENT) { + /* -ENOENT is a missing socket/class mapping, ignore */ + rc = 0; + } else { + return rc; + } + + /* move to the next message after applying netlink padding */ + msg_len = NLMSG_ALIGN(nlh->nlmsg_len); + if (msg_len >= data_len) + return 0; + data_len -= msg_len; + data += msg_len; + } + + return rc; +} + #ifdef CONFIG_NETFILTER static unsigned int selinux_ip_forward(struct sk_buff *skb, @@ -5971,60 +6025,7 @@ static unsigned int selinux_ipv6_postroute(void *priv, static int selinux_netlink_send(struct sock *sk, struct sk_buff *skb) { - int rc = 0; - unsigned int msg_len; - unsigned int data_len = skb->len; - unsigned char *data = skb->data; - struct nlmsghdr *nlh; - struct sk_security_struct *sksec = sk->sk_security; - u16 sclass = sksec->sclass; - u32 perm; - - while (data_len >= nlmsg_total_size(0)) { - nlh = (struct nlmsghdr *)data; - - /* NOTE: the nlmsg_len field isn't reliably set by some netlink - * users which means we can't reject skb's with bogus - * length fields; our solution is to follow what - * netlink_rcv_skb() does and simply skip processing at - * messages with length fields that are clearly junk - */ - if (nlh->nlmsg_len < NLMSG_HDRLEN || nlh->nlmsg_len > data_len) - return 0; - - rc = selinux_nlmsg_lookup(sclass, nlh->nlmsg_type, &perm); - if (rc == 0) { - rc = sock_has_perm(sk, perm); - if (rc) - return rc; - } else if (rc == -EINVAL) { - /* -EINVAL is a missing msg/perm mapping */ - pr_warn_ratelimited("SELinux: unrecognized netlink" - " message: protocol=%hu nlmsg_type=%hu sclass=%s" - " pid=%d comm=%s\n", - sk->sk_protocol, nlh->nlmsg_type, - secclass_map[sclass - 1].name, - task_pid_nr(current), current->comm); - if (enforcing_enabled(&selinux_state) && - !security_get_allow_unknown(&selinux_state)) - return rc; - rc = 0; - } else if (rc == -ENOENT) { - /* -ENOENT is a missing socket/class mapping, ignore */ - rc = 0; - } else { - return rc; - } - - /* move to the next message after applying netlink padding */ - msg_len = NLMSG_ALIGN(nlh->nlmsg_len); - if (msg_len >= data_len) - return 0; - data_len -= msg_len; - data += msg_len; - } - - return rc; + return selinux_nlmsg_perm(sk, skb); } static void ipc_init_security(struct ipc_security_struct *isec, u16 sclass) @@ -7007,21 +7008,6 @@ static int selinux_perf_event_write(struct perf_event *event) } #endif -/* - * IMPORTANT NOTE: When adding new hooks, please be careful to keep this order: - * 1. any hooks that don't belong to (2.) or (3.) below, - * 2. hooks that both access structures allocated by other hooks, and allocate - * structures that can be later accessed by other hooks (mostly "cloning" - * hooks), - * 3. hooks that only allocate structures that can be later accessed by other - * hooks ("allocating" hooks). - * - * Please follow block comment delimiters in the list to keep this order. - * - * This ordering is needed for SELinux runtime disable to work at least somewhat - * safely. Breaking the ordering rules above might lead to NULL pointer derefs - * when disabling SELinux at runtime. - */ static struct security_hook_list selinux_hooks[] __lsm_ro_after_init = { LSM_HOOK_INIT(binder_set_context_mgr, selinux_binder_set_context_mgr), LSM_HOOK_INIT(binder_transaction, selinux_binder_transaction), @@ -7044,7 +7030,12 @@ static struct security_hook_list selinux_hooks[] __lsm_ro_after_init = { LSM_HOOK_INIT(bprm_committing_creds, selinux_bprm_committing_creds), LSM_HOOK_INIT(bprm_committed_creds, selinux_bprm_committed_creds), + LSM_HOOK_INIT(fs_context_dup, selinux_fs_context_dup), + LSM_HOOK_INIT(fs_context_parse_param, selinux_fs_context_parse_param), + + LSM_HOOK_INIT(sb_alloc_security, selinux_sb_alloc_security), LSM_HOOK_INIT(sb_free_security, selinux_sb_free_security), + LSM_HOOK_INIT(sb_eat_lsm_opts, selinux_sb_eat_lsm_opts), LSM_HOOK_INIT(sb_free_mnt_opts, selinux_free_mnt_opts), LSM_HOOK_INIT(sb_remount, selinux_sb_remount), LSM_HOOK_INIT(sb_kern_mount, selinux_sb_kern_mount), @@ -7054,12 +7045,14 @@ static struct security_hook_list selinux_hooks[] __lsm_ro_after_init = { LSM_HOOK_INIT(sb_umount, selinux_umount), LSM_HOOK_INIT(sb_set_mnt_opts, selinux_set_mnt_opts), LSM_HOOK_INIT(sb_clone_mnt_opts, selinux_sb_clone_mnt_opts), + LSM_HOOK_INIT(sb_add_mnt_opt, selinux_add_mnt_opt), LSM_HOOK_INIT(move_mount, selinux_move_mount), LSM_HOOK_INIT(dentry_init_security, selinux_dentry_init_security), LSM_HOOK_INIT(dentry_create_files_as, selinux_dentry_create_files_as), + LSM_HOOK_INIT(inode_alloc_security, selinux_inode_alloc_security), LSM_HOOK_INIT(inode_free_security, selinux_inode_free_security), LSM_HOOK_INIT(inode_init_security, selinux_inode_init_security), LSM_HOOK_INIT(inode_init_security_anon, selinux_inode_init_security_anon), @@ -7133,15 +7126,21 @@ static struct security_hook_list selinux_hooks[] __lsm_ro_after_init = { LSM_HOOK_INIT(ipc_permission, selinux_ipc_permission), LSM_HOOK_INIT(ipc_getsecid, selinux_ipc_getsecid), + LSM_HOOK_INIT(msg_msg_alloc_security, selinux_msg_msg_alloc_security), + + LSM_HOOK_INIT(msg_queue_alloc_security, + selinux_msg_queue_alloc_security), LSM_HOOK_INIT(msg_queue_associate, selinux_msg_queue_associate), LSM_HOOK_INIT(msg_queue_msgctl, selinux_msg_queue_msgctl), LSM_HOOK_INIT(msg_queue_msgsnd, selinux_msg_queue_msgsnd), LSM_HOOK_INIT(msg_queue_msgrcv, selinux_msg_queue_msgrcv), + LSM_HOOK_INIT(shm_alloc_security, selinux_shm_alloc_security), LSM_HOOK_INIT(shm_associate, selinux_shm_associate), LSM_HOOK_INIT(shm_shmctl, selinux_shm_shmctl), LSM_HOOK_INIT(shm_shmat, selinux_shm_shmat), + LSM_HOOK_INIT(sem_alloc_security, selinux_sem_alloc_security), LSM_HOOK_INIT(sem_associate, selinux_sem_associate), LSM_HOOK_INIT(sem_semctl, selinux_sem_semctl), LSM_HOOK_INIT(sem_semop, selinux_sem_semop), @@ -7152,11 +7151,13 @@ static struct security_hook_list selinux_hooks[] __lsm_ro_after_init = { LSM_HOOK_INIT(setprocattr, selinux_setprocattr), LSM_HOOK_INIT(ismaclabel, selinux_ismaclabel), + LSM_HOOK_INIT(secid_to_secctx, selinux_secid_to_secctx), LSM_HOOK_INIT(secctx_to_secid, selinux_secctx_to_secid), LSM_HOOK_INIT(release_secctx, selinux_release_secctx), LSM_HOOK_INIT(inode_invalidate_secctx, selinux_inode_invalidate_secctx), LSM_HOOK_INIT(inode_notifysecctx, selinux_inode_notifysecctx), LSM_HOOK_INIT(inode_setsecctx, selinux_inode_setsecctx), + LSM_HOOK_INIT(inode_getsecctx, selinux_inode_getsecctx), LSM_HOOK_INIT(unix_stream_connect, selinux_socket_unix_stream_connect), LSM_HOOK_INIT(unix_may_send, selinux_socket_unix_may_send), @@ -7179,6 +7180,7 @@ static struct security_hook_list selinux_hooks[] __lsm_ro_after_init = { LSM_HOOK_INIT(socket_getpeersec_stream, selinux_socket_getpeersec_stream), LSM_HOOK_INIT(socket_getpeersec_dgram, selinux_socket_getpeersec_dgram), + LSM_HOOK_INIT(sk_alloc_security, selinux_sk_alloc_security), LSM_HOOK_INIT(sk_free_security, selinux_sk_free_security), LSM_HOOK_INIT(sk_clone_security, selinux_sk_clone_security), LSM_HOOK_INIT(sk_getsecid, selinux_sk_getsecid), @@ -7193,6 +7195,7 @@ static struct security_hook_list selinux_hooks[] __lsm_ro_after_init = { LSM_HOOK_INIT(secmark_refcount_inc, selinux_secmark_refcount_inc), LSM_HOOK_INIT(secmark_refcount_dec, selinux_secmark_refcount_dec), LSM_HOOK_INIT(req_classify_flow, selinux_req_classify_flow), + LSM_HOOK_INIT(tun_dev_alloc_security, selinux_tun_dev_alloc_security), LSM_HOOK_INIT(tun_dev_free_security, selinux_tun_dev_free_security), LSM_HOOK_INIT(tun_dev_create, selinux_tun_dev_create), LSM_HOOK_INIT(tun_dev_attach_queue, selinux_tun_dev_attach_queue), @@ -7202,11 +7205,17 @@ static struct security_hook_list selinux_hooks[] __lsm_ro_after_init = { LSM_HOOK_INIT(ib_pkey_access, selinux_ib_pkey_access), LSM_HOOK_INIT(ib_endport_manage_subnet, selinux_ib_endport_manage_subnet), + LSM_HOOK_INIT(ib_alloc_security, selinux_ib_alloc_security), LSM_HOOK_INIT(ib_free_security, selinux_ib_free_security), #endif #ifdef CONFIG_SECURITY_NETWORK_XFRM + LSM_HOOK_INIT(xfrm_policy_alloc_security, selinux_xfrm_policy_alloc), + LSM_HOOK_INIT(xfrm_policy_clone_security, selinux_xfrm_policy_clone), LSM_HOOK_INIT(xfrm_policy_free_security, selinux_xfrm_policy_free), LSM_HOOK_INIT(xfrm_policy_delete_security, selinux_xfrm_policy_delete), + LSM_HOOK_INIT(xfrm_state_alloc, selinux_xfrm_state_alloc), + LSM_HOOK_INIT(xfrm_state_alloc_acquire, + selinux_xfrm_state_alloc_acquire), LSM_HOOK_INIT(xfrm_state_free_security, selinux_xfrm_state_free), LSM_HOOK_INIT(xfrm_state_delete_security, selinux_xfrm_state_delete), LSM_HOOK_INIT(xfrm_policy_lookup, selinux_xfrm_policy_lookup), @@ -7216,12 +7225,14 @@ static struct security_hook_list selinux_hooks[] __lsm_ro_after_init = { #endif #ifdef CONFIG_KEYS + LSM_HOOK_INIT(key_alloc, selinux_key_alloc), LSM_HOOK_INIT(key_free, selinux_key_free), LSM_HOOK_INIT(key_permission, selinux_key_permission), LSM_HOOK_INIT(key_getsecurity, selinux_key_getsecurity), #endif #ifdef CONFIG_AUDIT + LSM_HOOK_INIT(audit_rule_init, selinux_audit_rule_init), LSM_HOOK_INIT(audit_rule_known, selinux_audit_rule_known), LSM_HOOK_INIT(audit_rule_match, selinux_audit_rule_match), LSM_HOOK_INIT(audit_rule_free, selinux_audit_rule_free), @@ -7231,64 +7242,19 @@ static struct security_hook_list selinux_hooks[] __lsm_ro_after_init = { LSM_HOOK_INIT(bpf, selinux_bpf), LSM_HOOK_INIT(bpf_map, selinux_bpf_map), LSM_HOOK_INIT(bpf_prog, selinux_bpf_prog), + LSM_HOOK_INIT(bpf_map_alloc_security, selinux_bpf_map_alloc), + LSM_HOOK_INIT(bpf_prog_alloc_security, selinux_bpf_prog_alloc), LSM_HOOK_INIT(bpf_map_free_security, selinux_bpf_map_free), LSM_HOOK_INIT(bpf_prog_free_security, selinux_bpf_prog_free), #endif #ifdef CONFIG_PERF_EVENTS LSM_HOOK_INIT(perf_event_open, selinux_perf_event_open), + LSM_HOOK_INIT(perf_event_alloc, selinux_perf_event_alloc), LSM_HOOK_INIT(perf_event_free, selinux_perf_event_free), LSM_HOOK_INIT(perf_event_read, selinux_perf_event_read), LSM_HOOK_INIT(perf_event_write, selinux_perf_event_write), #endif - - /* - * PUT "CLONING" (ACCESSING + ALLOCATING) HOOKS HERE - */ - LSM_HOOK_INIT(fs_context_dup, selinux_fs_context_dup), - LSM_HOOK_INIT(fs_context_parse_param, selinux_fs_context_parse_param), - LSM_HOOK_INIT(sb_eat_lsm_opts, selinux_sb_eat_lsm_opts), - LSM_HOOK_INIT(sb_add_mnt_opt, selinux_add_mnt_opt), -#ifdef CONFIG_SECURITY_NETWORK_XFRM - LSM_HOOK_INIT(xfrm_policy_clone_security, selinux_xfrm_policy_clone), -#endif - - /* - * PUT "ALLOCATING" HOOKS HERE - */ - LSM_HOOK_INIT(msg_msg_alloc_security, selinux_msg_msg_alloc_security), - LSM_HOOK_INIT(msg_queue_alloc_security, - selinux_msg_queue_alloc_security), - LSM_HOOK_INIT(shm_alloc_security, selinux_shm_alloc_security), - LSM_HOOK_INIT(sb_alloc_security, selinux_sb_alloc_security), - LSM_HOOK_INIT(inode_alloc_security, selinux_inode_alloc_security), - LSM_HOOK_INIT(sem_alloc_security, selinux_sem_alloc_security), - LSM_HOOK_INIT(secid_to_secctx, selinux_secid_to_secctx), - LSM_HOOK_INIT(inode_getsecctx, selinux_inode_getsecctx), - LSM_HOOK_INIT(sk_alloc_security, selinux_sk_alloc_security), - LSM_HOOK_INIT(tun_dev_alloc_security, selinux_tun_dev_alloc_security), -#ifdef CONFIG_SECURITY_INFINIBAND - LSM_HOOK_INIT(ib_alloc_security, selinux_ib_alloc_security), -#endif -#ifdef CONFIG_SECURITY_NETWORK_XFRM - LSM_HOOK_INIT(xfrm_policy_alloc_security, selinux_xfrm_policy_alloc), - LSM_HOOK_INIT(xfrm_state_alloc, selinux_xfrm_state_alloc), - LSM_HOOK_INIT(xfrm_state_alloc_acquire, - selinux_xfrm_state_alloc_acquire), -#endif -#ifdef CONFIG_KEYS - LSM_HOOK_INIT(key_alloc, selinux_key_alloc), -#endif -#ifdef CONFIG_AUDIT - LSM_HOOK_INIT(audit_rule_init, selinux_audit_rule_init), -#endif -#ifdef CONFIG_BPF_SYSCALL - LSM_HOOK_INIT(bpf_map_alloc_security, selinux_bpf_map_alloc), - LSM_HOOK_INIT(bpf_prog_alloc_security, selinux_bpf_prog_alloc), -#endif -#ifdef CONFIG_PERF_EVENTS - LSM_HOOK_INIT(perf_event_alloc, selinux_perf_event_alloc), -#endif }; static __init int selinux_init(void) @@ -7351,7 +7317,7 @@ void selinux_complete_init(void) DEFINE_LSM(selinux) = { .name = "selinux", .flags = LSM_FLAG_LEGACY_MAJOR | LSM_FLAG_EXCLUSIVE, - .enabled = &selinux_enabled_boot, + .enabled = &selinux_enabled, .blobs = &selinux_blob_sizes, .init = selinux_init, }; @@ -7420,7 +7386,7 @@ static int __init selinux_nf_ip_init(void) { int err; - if (!selinux_enabled_boot) + if (!selinux_enabled) return 0; pr_debug("SELinux: Registering netfilter hooks\n"); @@ -7453,32 +7419,30 @@ static void selinux_nf_ip_exit(void) #ifdef CONFIG_SECURITY_SELINUX_DISABLE int selinux_disable(struct selinux_state *state) { - if (selinux_initialized(state)) { + if (state->initialized) { /* Not permitted after initial policy load. */ return -EINVAL; } - if (selinux_disabled(state)) { + if (state->disabled) { /* Only do this once. */ return -EINVAL; } - selinux_mark_disabled(state); + state->disabled = 1; pr_info("SELinux: Disabled at runtime.\n"); - /* - * Unregister netfilter hooks. - * Must be done before security_delete_hooks() to avoid breaking - * runtime disable. - */ - selinux_nf_ip_exit(); + selinux_enabled = 0; security_delete_hooks(selinux_hooks, ARRAY_SIZE(selinux_hooks)); /* Try to destroy the avc node cache */ avc_disable(); + /* Unregister netfilter hooks. */ + selinux_nf_ip_exit(); + /* Unregister selinuxfs. */ exit_sel_fs(); diff --git a/security/selinux/ibpkey.c b/security/selinux/ibpkey.c index 3a63a989e55e..5887bff50560 100644 --- a/security/selinux/ibpkey.c +++ b/security/selinux/ibpkey.c @@ -224,7 +224,7 @@ static __init int sel_ib_pkey_init(void) { int iter; - if (!selinux_enabled_boot) + if (!selinux_enabled) return 0; for (iter = 0; iter < SEL_PKEY_HASH_SIZE; iter++) { diff --git a/security/selinux/include/classmap.h b/security/selinux/include/classmap.h index d77f52b70671..542cbfc35787 100644 --- a/security/selinux/include/classmap.h +++ b/security/selinux/include/classmap.h @@ -27,10 +27,9 @@ "audit_control", "setfcap" #define COMMON_CAP2_PERMS "mac_override", "mac_admin", "syslog", \ - "wake_alarm", "block_suspend", "audit_read", "perfmon", "bpf", \ - "checkpoint_restore" + "wake_alarm", "block_suspend", "audit_read" -#if CAP_LAST_CAP > CAP_CHECKPOINT_RESTORE +#if CAP_LAST_CAP > CAP_AUDIT_READ #error New capability defined, please update COMMON_CAP2_PERMS. #endif @@ -248,7 +247,7 @@ struct security_class_mapping secclass_map[] = { { "xdp_socket", { COMMON_SOCK_PERMS, NULL } }, { "perf_event", - {"open", "cpu", "kernel", "tracepoint", "read", "write", NULL } }, + { "open", "cpu", "kernel", "tracepoint", "read", "write", NULL } }, { "anon_inode", { COMMON_FILE_PERMS, NULL } }, { NULL } diff --git a/security/selinux/include/objsec.h b/security/selinux/include/objsec.h index 330b7b6d44e0..a4a86cbcfb0a 100644 --- a/security/selinux/include/objsec.h +++ b/security/selinux/include/objsec.h @@ -35,7 +35,7 @@ struct task_security_struct { u32 create_sid; /* fscreate SID */ u32 keycreate_sid; /* keycreate SID */ u32 sockcreate_sid; /* fscreate SID */ -} __randomize_layout; +}; enum label_initialized { LABEL_INVALID, /* invalid or not initialized */ diff --git a/security/selinux/include/security.h b/security/selinux/include/security.h index 44806eaa28ba..6f5abff4109b 100644 --- a/security/selinux/include/security.h +++ b/security/selinux/include/security.h @@ -68,7 +68,7 @@ struct netlbl_lsm_secattr; -extern int selinux_enabled_boot; +extern int selinux_enabled; /* Policy capabilities */ enum { @@ -98,9 +98,7 @@ struct selinux_avc; struct selinux_ss; struct selinux_state { -#ifdef CONFIG_SECURITY_SELINUX_DISABLE bool disabled; -#endif #ifdef CONFIG_SECURITY_SELINUX_DEVELOP bool enforcing; #endif @@ -112,34 +110,22 @@ struct selinux_state { struct selinux_avc *avc; struct selinux_ss *ss; -} __randomize_layout; +}; void selinux_ss_init(struct selinux_ss **ss); void selinux_avc_init(struct selinux_avc **avc); extern struct selinux_state selinux_state; -static inline bool selinux_initialized(const struct selinux_state *state) -{ - /* do a synchronized load to avoid race conditions */ - return smp_load_acquire(&state->initialized); -} - -static inline void selinux_mark_initialized(struct selinux_state *state) -{ - /* do a synchronized write to avoid race conditions */ - smp_store_release(&state->initialized, true); -} - #ifdef CONFIG_SECURITY_SELINUX_DEVELOP static inline bool enforcing_enabled(struct selinux_state *state) { - return READ_ONCE(state->enforcing); + return state->enforcing; } static inline void enforcing_set(struct selinux_state *state, bool value) { - WRITE_ONCE(state->enforcing, value); + state->enforcing = value; } #else static inline bool enforcing_enabled(struct selinux_state *state) @@ -152,23 +138,6 @@ static inline void enforcing_set(struct selinux_state *state, bool value) } #endif -#ifdef CONFIG_SECURITY_SELINUX_DISABLE -static inline bool selinux_disabled(struct selinux_state *state) -{ - return READ_ONCE(state->disabled); -} - -static inline void selinux_mark_disabled(struct selinux_state *state) -{ - WRITE_ONCE(state->disabled, true); -} -#else -static inline bool selinux_disabled(struct selinux_state *state) -{ - return false; -} -#endif - static inline bool selinux_policycap_netpeer(void) { struct selinux_state *state = &selinux_state; diff --git a/security/selinux/netif.c b/security/selinux/netif.c index 15b8c1bcd7d0..e40fecd73752 100644 --- a/security/selinux/netif.c +++ b/security/selinux/netif.c @@ -266,7 +266,7 @@ static __init int sel_netif_init(void) { int i; - if (!selinux_enabled_boot) + if (!selinux_enabled) return 0; for (i = 0; i < SEL_NETIF_HASH_SIZE; i++) diff --git a/security/selinux/netnode.c b/security/selinux/netnode.c index dff587d1e164..9ab84efa46c7 100644 --- a/security/selinux/netnode.c +++ b/security/selinux/netnode.c @@ -291,7 +291,7 @@ static __init int sel_netnode_init(void) { int iter; - if (!selinux_enabled_boot) + if (!selinux_enabled) return 0; for (iter = 0; iter < SEL_NETNODE_HASH_SIZE; iter++) { diff --git a/security/selinux/netport.c b/security/selinux/netport.c index de727f7489b7..3f8b2c0458c8 100644 --- a/security/selinux/netport.c +++ b/security/selinux/netport.c @@ -225,7 +225,7 @@ static __init int sel_netport_init(void) { int iter; - if (!selinux_enabled_boot) + if (!selinux_enabled) return 0; for (iter = 0; iter < SEL_NETPORT_HASH_SIZE; iter++) { diff --git a/security/selinux/selinuxfs.c b/security/selinux/selinuxfs.c index ee2bcca11100..769e5bbdc815 100644 --- a/security/selinux/selinuxfs.c +++ b/security/selinux/selinuxfs.c @@ -168,10 +168,11 @@ static ssize_t sel_write_enforce(struct file *file, const char __user *buf, goto out; audit_log(audit_context(), GFP_KERNEL, AUDIT_MAC_STATUS, "enforcing=%d old_enforcing=%d auid=%u ses=%u" - " enabled=1 old-enabled=1 lsm=selinux res=1", + " enabled=%d old-enabled=%d lsm=selinux res=1", new_value, old_value, from_kuid(&init_user_ns, audit_get_loginuid(current)), - audit_get_sessionid(current)); + audit_get_sessionid(current), + selinux_enabled, selinux_enabled); enforcing_set(state, new_value); if (new_value) avc_ss_reset(state->avc, 0); @@ -281,13 +282,6 @@ static ssize_t sel_write_disable(struct file *file, const char __user *buf, int new_value; int enforcing; - /* NOTE: we are now officially considering runtime disable as - * deprecated, and using it will become increasingly painful - * (e.g. sleeping/blocking) as we progress through future - * kernel releases until eventually it is removed - */ - pr_err("SELinux: Runtime disable is deprecated, use selinux=0 on the kernel cmdline.\n"); - if (count >= PAGE_SIZE) return -ENOMEM; @@ -310,10 +304,10 @@ static ssize_t sel_write_disable(struct file *file, const char __user *buf, goto out; audit_log(audit_context(), GFP_KERNEL, AUDIT_MAC_STATUS, "enforcing=%d old_enforcing=%d auid=%u ses=%u" - " enabled=0 old-enabled=1 lsm=selinux res=1", + " enabled=%d old-enabled=%d lsm=selinux res=1", enforcing, enforcing, from_kuid(&init_user_ns, audit_get_loginuid(current)), - audit_get_sessionid(current)); + audit_get_sessionid(current), 0, 1); } length = count; @@ -1743,7 +1737,7 @@ static ssize_t sel_read_class(struct file *file, char __user *buf, { unsigned long ino = file_inode(file)->i_ino; char res[TMPBUFLEN]; - ssize_t len = scnprintf(res, sizeof(res), "%d", sel_ino_to_class(ino)); + ssize_t len = snprintf(res, sizeof(res), "%d", sel_ino_to_class(ino)); return simple_read_from_buffer(buf, count, ppos, res, len); } @@ -1757,7 +1751,7 @@ static ssize_t sel_read_perm(struct file *file, char __user *buf, { unsigned long ino = file_inode(file)->i_ino; char res[TMPBUFLEN]; - ssize_t len = scnprintf(res, sizeof(res), "%d", sel_ino_to_perm(ino)); + ssize_t len = snprintf(res, sizeof(res), "%d", sel_ino_to_perm(ino)); return simple_read_from_buffer(buf, count, ppos, res, len); } @@ -2121,7 +2115,7 @@ static int __init init_sel_fs(void) sizeof(NULL_FILE_NAME)-1); int err; - if (!selinux_enabled_boot) + if (!selinux_enabled) return 0; err = sysfs_create_mount_point(fs_kobj, "selinux"); diff --git a/security/selinux/ss/policydb.c b/security/selinux/ss/policydb.c index 58872a2365fc..b2393555d471 100644 --- a/security/selinux/ss/policydb.c +++ b/security/selinux/ss/policydb.c @@ -2663,7 +2663,7 @@ static int role_trans_write(struct policydb *p, void *fp) { struct role_trans *r = p->role_tr; struct role_trans *tr; - __le32 buf[3]; + u32 buf[3]; size_t nel; int rc; @@ -2695,7 +2695,7 @@ static int role_trans_write(struct policydb *p, void *fp) static int role_allow_write(struct role_allow *r, void *fp) { struct role_allow *ra; - __le32 buf[2]; + u32 buf[2]; size_t nel; int rc; diff --git a/security/selinux/ss/policydb.h b/security/selinux/ss/policydb.h index 372e9827338a..34f4c24aa374 100644 --- a/security/selinux/ss/policydb.h +++ b/security/selinux/ss/policydb.h @@ -308,7 +308,7 @@ struct policydb { u16 process_class; u32 process_trans_perms; -} __randomize_layout; +}; extern void policydb_destroy(struct policydb *p); extern int policydb_load_isids(struct policydb *p, struct sidtab *s); diff --git a/security/selinux/ss/services.c b/security/selinux/ss/services.c index 2d41602b60d8..a413c3b7bcc9 100644 --- a/security/selinux/ss/services.c +++ b/security/selinux/ss/services.c @@ -760,7 +760,7 @@ static int security_compute_validatetrans(struct selinux_state *state, int rc = 0; - if (!selinux_initialized(state)) + if (!state->initialized) return 0; read_lock(&state->ss->policy_rwlock); @@ -860,7 +860,7 @@ int security_bounded_transition(struct selinux_state *state, int index; int rc; - if (!selinux_initialized(state)) + if (!state->initialized) return 0; read_lock(&state->ss->policy_rwlock); @@ -1023,7 +1023,7 @@ void security_compute_xperms_decision(struct selinux_state *state, memset(xpermd->dontaudit->p, 0, sizeof(xpermd->dontaudit->p)); read_lock(&state->ss->policy_rwlock); - if (!selinux_initialized(state)) + if (!state->initialized) goto allow; policydb = &state->ss->policydb; @@ -1108,7 +1108,7 @@ void security_compute_av(struct selinux_state *state, read_lock(&state->ss->policy_rwlock); avd_init(state, avd); xperms->len = 0; - if (!selinux_initialized(state)) + if (!state->initialized) goto allow; policydb = &state->ss->policydb; @@ -1162,7 +1162,7 @@ void security_compute_av_user(struct selinux_state *state, read_lock(&state->ss->policy_rwlock); avd_init(state, avd); - if (!selinux_initialized(state)) + if (!state->initialized) goto allow; policydb = &state->ss->policydb; @@ -1265,7 +1265,7 @@ int security_sidtab_hash_stats(struct selinux_state *state, char *page) { int rc; - if (!selinux_initialized(state)) { + if (!state->initialized) { pr_err("SELinux: %s: called before initial load_policy\n", __func__); return -EINVAL; @@ -1299,7 +1299,7 @@ static int security_sid_to_context_core(struct selinux_state *state, *scontext = NULL; *scontext_len = 0; - if (!selinux_initialized(state)) { + if (!state->initialized) { if (sid <= SECINITSID_NUM) { char *scontextp; @@ -1526,7 +1526,7 @@ static int security_context_to_sid_core(struct selinux_state *state, if (!scontext2) return -ENOMEM; - if (!selinux_initialized(state)) { + if (!state->initialized) { int i; for (i = 1; i < SECINITSID_NUM; i++) { @@ -1711,7 +1711,7 @@ static int security_compute_sid(struct selinux_state *state, int rc = 0; bool sock; - if (!selinux_initialized(state)) { + if (!state->initialized) { switch (orig_tclass) { case SECCLASS_PROCESS: /* kernel value */ *out_sid = ssid; @@ -2176,7 +2176,7 @@ int security_load_policy(struct selinux_state *state, void *data, size_t len) goto out; } - if (!selinux_initialized(state)) { + if (!state->initialized) { rc = policydb_read(policydb, fp); if (rc) { kfree(newsidtab); @@ -2201,7 +2201,7 @@ int security_load_policy(struct selinux_state *state, void *data, size_t len) state->ss->sidtab = newsidtab; security_load_policycaps(state); - selinux_mark_initialized(state); + state->initialized = 1; seqno = ++state->ss->latest_granting; selinux_complete_init(); avc_ss_reset(state->avc, seqno); @@ -2657,7 +2657,7 @@ int security_get_user_sids(struct selinux_state *state, *sids = NULL; *nel = 0; - if (!selinux_initialized(state)) + if (!state->initialized) goto out; read_lock(&state->ss->policy_rwlock); @@ -2885,7 +2885,7 @@ int security_get_bools(struct selinux_state *state, struct policydb *policydb; int i, rc; - if (!selinux_initialized(state)) { + if (!state->initialized) { *len = 0; *names = NULL; *values = NULL; @@ -3064,7 +3064,7 @@ int security_sid_mls_copy(struct selinux_state *state, int rc; rc = 0; - if (!selinux_initialized(state) || !policydb->mls_enabled) { + if (!state->initialized || !policydb->mls_enabled) { *new_sid = sid; goto out; } @@ -3231,7 +3231,7 @@ int security_get_classes(struct selinux_state *state, struct policydb *policydb = &state->ss->policydb; int rc; - if (!selinux_initialized(state)) { + if (!state->initialized) { *nclasses = 0; *classes = NULL; return 0; @@ -3380,7 +3380,7 @@ int selinux_audit_rule_init(u32 field, u32 op, char *rulestr, void **vrule) *rule = NULL; - if (!selinux_initialized(state)) + if (!state->initialized) return -EOPNOTSUPP; switch (field) { @@ -3679,7 +3679,7 @@ int security_netlbl_secattr_to_sid(struct selinux_state *state, struct context *ctx; struct context ctx_new; - if (!selinux_initialized(state)) { + if (!state->initialized) { *sid = SECSID_NULL; return 0; } @@ -3746,7 +3746,7 @@ int security_netlbl_sid_to_secattr(struct selinux_state *state, int rc; struct context *ctx; - if (!selinux_initialized(state)) + if (!state->initialized) return 0; read_lock(&state->ss->policy_rwlock); @@ -3785,7 +3785,7 @@ int security_read_policy(struct selinux_state *state, int rc; struct policy_file fp; - if (!selinux_initialized(state)) + if (!state->initialized) return -EINVAL; *len = security_policydb_len(state); diff --git a/security/selinux/ss/services.h b/security/selinux/ss/services.h index c5896f39e8f6..fc40640a9725 100644 --- a/security/selinux/ss/services.h +++ b/security/selinux/ss/services.h @@ -31,7 +31,7 @@ struct selinux_ss { struct selinux_map map; struct page *status_page; struct mutex status_lock; -} __randomize_layout; +}; void services_compute_xperms_drivers(struct extended_perms *xperms, struct avtab_node *node); diff --git a/security/yama/yama_lsm.c b/security/yama/yama_lsm.c index 536c99646f6a..94dc346370b1 100644 --- a/security/yama/yama_lsm.c +++ b/security/yama/yama_lsm.c @@ -430,7 +430,7 @@ static struct security_hook_list yama_hooks[] __lsm_ro_after_init = { #ifdef CONFIG_SYSCTL static int yama_dointvec_minmax(struct ctl_table *table, int write, - void *buffer, size_t *lenp, loff_t *ppos) + void __user *buffer, size_t *lenp, loff_t *ppos) { struct ctl_table table_copy; diff --git a/sound/core/pcm_memory.c b/sound/core/pcm_memory.c index 349766699113..9aea1d6fb054 100644 --- a/sound/core/pcm_memory.c +++ b/sound/core/pcm_memory.c @@ -370,7 +370,7 @@ int _snd_pcm_lib_alloc_vmalloc_buffer(struct snd_pcm_substream *substream, return 0; /* already large enough */ vfree(runtime->dma_area); } - runtime->dma_area = __vmalloc(size, gfp_flags); + runtime->dma_area = __vmalloc(size, gfp_flags, PAGE_KERNEL); if (!runtime->dma_area) return -ENOMEM; runtime->dma_bytes = size; diff --git a/sound/firewire/amdtp-stream.h b/sound/firewire/amdtp-stream.h index f1933f7b9f1b..bbbca964b9b4 100644 --- a/sound/firewire/amdtp-stream.h +++ b/sound/firewire/amdtp-stream.h @@ -32,7 +32,7 @@ * allows 5 times as large as IEC 61883-6 defines. * @CIP_HEADER_WITHOUT_EOH: Only for in-stream. CIP Header doesn't include * valid EOH. - * @CIP_NO_HEADER: a lack of headers in packets + * @CIP_NO_HEADERS: a lack of headers in packets * @CIP_UNALIGHED_DBC: Only for in-stream. The value of dbc is not alighed to * the value of current SYT_INTERVAL; e.g. initial value is not zero. */ diff --git a/sound/pci/lx6464es/lx_core.c b/sound/pci/lx6464es/lx_core.c index 6cf7572779d4..00975e86473c 100644 --- a/sound/pci/lx6464es/lx_core.c +++ b/sound/pci/lx6464es/lx_core.c @@ -316,7 +316,7 @@ polling_successful: /* low-level dsp access */ int lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version) { - int ret; + u16 ret; mutex_lock(&chip->msg_lock); @@ -330,10 +330,10 @@ int lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version) int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq) { + u16 ret = 0; u32 freq_raw = 0; u32 freq = 0; u32 frequency = 0; - int ret; mutex_lock(&chip->msg_lock); diff --git a/sound/soc/codecs/cs4271.c b/sound/soc/codecs/cs4271.c index 1df484ff34a0..04b86a51e055 100644 --- a/sound/soc/codecs/cs4271.c +++ b/sound/soc/codecs/cs4271.c @@ -594,17 +594,17 @@ static int cs4271_component_probe(struct snd_soc_component *component) ret = regcache_sync(cs4271->regmap); if (ret < 0) - goto err_disable_regulator; + return ret; ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, CS4271_MODE2_PDN | CS4271_MODE2_CPEN, CS4271_MODE2_PDN | CS4271_MODE2_CPEN); if (ret < 0) - goto err_disable_regulator; + return ret; ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, CS4271_MODE2_PDN, 0); if (ret < 0) - goto err_disable_regulator; + return ret; /* Power-up sequence requires 85 uS */ udelay(85); @@ -614,10 +614,6 @@ static int cs4271_component_probe(struct snd_soc_component *component) CS4271_MODE2_MUTECAEQUB); return 0; - -err_disable_regulator: - regulator_bulk_disable(ARRAY_SIZE(cs4271->supplies), cs4271->supplies); - return ret; } static void cs4271_component_remove(struct snd_soc_component *component) diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c index 7955ba75255f..ce9f99dd3e87 100644 --- a/sound/soc/codecs/max98090.c +++ b/sound/soc/codecs/max98090.c @@ -1231,11 +1231,9 @@ static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = { SND_SOC_DAPM_INPUT("DMIC4"), SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE, - M98090_DIGMIC3_SHIFT, 0, max98090_shdn_event, - SND_SOC_DAPM_POST_PMU), + M98090_DIGMIC3_SHIFT, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE, - M98090_DIGMIC4_SHIFT, 0, max98090_shdn_event, - SND_SOC_DAPM_POST_PMU), + M98090_DIGMIC4_SHIFT, 0, NULL, 0), }; static const struct snd_soc_dapm_route max98090_dapm_routes[] = { diff --git a/sound/soc/intel/boards/bytcht_es8316.c b/sound/soc/intel/boards/bytcht_es8316.c index 006e489e7e89..57d6d0b48068 100644 --- a/sound/soc/intel/boards/bytcht_es8316.c +++ b/sound/soc/intel/boards/bytcht_es8316.c @@ -46,8 +46,7 @@ enum { BYT_CHT_ES8316_INTMIC_IN2_MAP, }; -#define BYT_CHT_ES8316_MAP_MASK GENMASK(3, 0) -#define BYT_CHT_ES8316_MAP(quirk) ((quirk) & BYT_CHT_ES8316_MAP_MASK) +#define BYT_CHT_ES8316_MAP(quirk) ((quirk) & GENMASK(3, 0)) #define BYT_CHT_ES8316_SSP0 BIT(16) #define BYT_CHT_ES8316_MONO_SPEAKER BIT(17) #define BYT_CHT_ES8316_JD_INVERTED BIT(18) @@ -60,23 +59,10 @@ MODULE_PARM_DESC(quirk, "Board-specific quirk override"); static void log_quirks(struct device *dev) { - int map; - - map = BYT_CHT_ES8316_MAP(quirk); - switch (map) { - case BYT_CHT_ES8316_INTMIC_IN1_MAP: + if (BYT_CHT_ES8316_MAP(quirk) == BYT_CHT_ES8316_INTMIC_IN1_MAP) dev_info(dev, "quirk IN1_MAP enabled"); - break; - case BYT_CHT_ES8316_INTMIC_IN2_MAP: + if (BYT_CHT_ES8316_MAP(quirk) == BYT_CHT_ES8316_INTMIC_IN2_MAP) dev_info(dev, "quirk IN2_MAP enabled"); - break; - default: - dev_warn_once(dev, "quirk sets invalid input map: 0x%x, default to INTMIC_IN1_MAP\n", map); - quirk &= ~BYT_CHT_ES8316_MAP_MASK; - quirk |= BYT_CHT_ES8316_INTMIC_IN1_MAP; - break; - } - if (quirk & BYT_CHT_ES8316_SSP0) dev_info(dev, "quirk SSP0 enabled"); if (quirk & BYT_CHT_ES8316_MONO_SPEAKER) diff --git a/sound/soc/intel/boards/bytcr_rt5640.c b/sound/soc/intel/boards/bytcr_rt5640.c index 88e84415d5a4..5a8e86ba2900 100644 --- a/sound/soc/intel/boards/bytcr_rt5640.c +++ b/sound/soc/intel/boards/bytcr_rt5640.c @@ -60,8 +60,7 @@ enum { BYT_RT5640_OVCD_SF_1P5 = (RT5640_OVCD_SF_1P5 << 13), }; -#define BYT_RT5640_MAP_MASK GENMASK(3, 0) -#define BYT_RT5640_MAP(quirk) ((quirk) & BYT_RT5640_MAP_MASK) +#define BYT_RT5640_MAP(quirk) ((quirk) & GENMASK(3, 0)) #define BYT_RT5640_JDSRC(quirk) (((quirk) & GENMASK(7, 4)) >> 4) #define BYT_RT5640_OVCD_TH(quirk) (((quirk) & GENMASK(12, 8)) >> 8) #define BYT_RT5640_OVCD_SF(quirk) (((quirk) & GENMASK(14, 13)) >> 13) @@ -119,9 +118,7 @@ static void log_quirks(struct device *dev) dev_info(dev, "quirk IN3_MAP enabled\n"); break; default: - dev_warn_once(dev, "quirk sets invalid input map: 0x%x, default to DMIC1_MAP\n", map); - byt_rt5640_quirk &= ~BYT_RT5640_MAP_MASK; - byt_rt5640_quirk |= BYT_RT5640_DMIC1_MAP; + dev_err(dev, "quirk map 0x%x is not supported, microphone input will not work\n", map); break; } if (BYT_RT5640_JDSRC(byt_rt5640_quirk)) { diff --git a/sound/soc/intel/boards/bytcr_rt5651.c b/sound/soc/intel/boards/bytcr_rt5651.c index 6a5098efdaf2..0c1c8628b991 100644 --- a/sound/soc/intel/boards/bytcr_rt5651.c +++ b/sound/soc/intel/boards/bytcr_rt5651.c @@ -58,8 +58,7 @@ enum { BYT_RT5651_OVCD_SF_1P5 = (RT5651_OVCD_SF_1P5 << 13), }; -#define BYT_RT5651_MAP_MASK GENMASK(3, 0) -#define BYT_RT5651_MAP(quirk) ((quirk) & BYT_RT5651_MAP_MASK) +#define BYT_RT5651_MAP(quirk) ((quirk) & GENMASK(3, 0)) #define BYT_RT5651_JDSRC(quirk) (((quirk) & GENMASK(7, 4)) >> 4) #define BYT_RT5651_OVCD_TH(quirk) (((quirk) & GENMASK(12, 8)) >> 8) #define BYT_RT5651_OVCD_SF(quirk) (((quirk) & GENMASK(14, 13)) >> 13) @@ -100,29 +99,14 @@ MODULE_PARM_DESC(quirk, "Board-specific quirk override"); static void log_quirks(struct device *dev) { - int map; - - map = BYT_RT5651_MAP(byt_rt5651_quirk); - switch (map) { - case BYT_RT5651_DMIC_MAP: + if (BYT_RT5651_MAP(byt_rt5651_quirk) == BYT_RT5651_DMIC_MAP) dev_info(dev, "quirk DMIC_MAP enabled"); - break; - case BYT_RT5651_IN1_MAP: + if (BYT_RT5651_MAP(byt_rt5651_quirk) == BYT_RT5651_IN1_MAP) dev_info(dev, "quirk IN1_MAP enabled"); - break; - case BYT_RT5651_IN2_MAP: + if (BYT_RT5651_MAP(byt_rt5651_quirk) == BYT_RT5651_IN2_MAP) dev_info(dev, "quirk IN2_MAP enabled"); - break; - case BYT_RT5651_IN1_IN2_MAP: + if (BYT_RT5651_MAP(byt_rt5651_quirk) == BYT_RT5651_IN1_IN2_MAP) dev_info(dev, "quirk IN1_IN2_MAP enabled"); - break; - default: - dev_warn_once(dev, "quirk sets invalid input map: 0x%x, default to DMIC_MAP\n", map); - byt_rt5651_quirk &= ~BYT_RT5651_MAP_MASK; - byt_rt5651_quirk |= BYT_RT5651_DMIC_MAP; - break; - } - if (BYT_RT5651_JDSRC(byt_rt5651_quirk)) { dev_info(dev, "quirk realtek,jack-detect-source %ld\n", BYT_RT5651_JDSRC(byt_rt5651_quirk)); diff --git a/sound/soc/qcom/qdsp6/q6asm.c b/sound/soc/qcom/qdsp6/q6asm.c index c80f488e5719..835ac98a789c 100644 --- a/sound/soc/qcom/qdsp6/q6asm.c +++ b/sound/soc/qcom/qdsp6/q6asm.c @@ -299,9 +299,9 @@ static void q6asm_audio_client_free_buf(struct audio_client *ac, spin_lock_irqsave(&ac->lock, flags); port->num_periods = 0; - spin_unlock_irqrestore(&ac->lock, flags); kfree(port->buf); port->buf = NULL; + spin_unlock_irqrestore(&ac->lock, flags); } /** diff --git a/sound/usb/mixer.c b/sound/usb/mixer.c index d6dfa2b40067..1374a4e093b3 100644 --- a/sound/usb/mixer.c +++ b/sound/usb/mixer.c @@ -914,7 +914,7 @@ static int parse_term_uac2_clock_source(struct mixer_build *state, { struct uac_clock_source_descriptor *d = p1; - term->type = UAC2_CLOCK_SOURCE << 16; /* virtual type */ + term->type = UAC3_CLOCK_SOURCE << 16; /* virtual type */ term->id = id; term->name = d->iClockSource; return 0; @@ -1181,13 +1181,6 @@ static void volume_control_quirks(struct usb_mixer_elem_info *cval, cval->res = 1; } break; - case USB_ID(0x3302, 0x12db): /* MOONDROP Quark2 */ - if (!strcmp(kctl->id.name, "PCM Playback Volume")) { - usb_audio_info(chip, - "set volume quirk for MOONDROP Quark2\n"); - cval->min = -14208; /* Mute under it */ - } - break; } } @@ -2967,8 +2960,6 @@ static int snd_usb_mixer_controls_badd(struct usb_mixer_interface *mixer, int i; assoc = usb_ifnum_to_if(dev, ctrlif)->intf_assoc; - if (!assoc) - return -EINVAL; /* Detect BADD capture/playback channels from AS EP descriptors */ for (i = 0; i < assoc->bInterfaceCount; i++) { diff --git a/techpack/audio/asoc/codecs/wcd938x/wcd938x.c b/techpack/audio/asoc/codecs/wcd938x/wcd938x.c index d124b31b8e9c..5f33ec26f4b8 100644 --- a/techpack/audio/asoc/codecs/wcd938x/wcd938x.c +++ b/techpack/audio/asoc/codecs/wcd938x/wcd938x.c @@ -3381,35 +3381,35 @@ static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = { SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, ADC4, 0, adc4_switch, ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC0, + SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1, 0, dmic1_switch, ARRAY_SIZE(dmic1_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC1, + SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2, 0, dmic2_switch, ARRAY_SIZE(dmic2_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC2, + SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3, 0, dmic3_switch, ARRAY_SIZE(dmic3_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC3, + SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4, 0, dmic4_switch, ARRAY_SIZE(dmic4_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC4, + SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5, 0, dmic5_switch, ARRAY_SIZE(dmic5_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC5, + SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6, 0, dmic6_switch, ARRAY_SIZE(dmic6_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC6, + SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC7, 0, dmic7_switch, ARRAY_SIZE(dmic7_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC7, + SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC8, 0, dmic8_switch, ARRAY_SIZE(dmic8_switch), wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), diff --git a/techpack/audio/asoc/codecs/wcd_cpe_services.c b/techpack/audio/asoc/codecs/wcd_cpe_services.c index fb6e1de56a21..96e2bb1945a4 100644 --- a/techpack/audio/asoc/codecs/wcd_cpe_services.c +++ b/techpack/audio/asoc/codecs/wcd_cpe_services.c @@ -987,7 +987,7 @@ static enum cpe_svc_result broadcast_boot_event( static enum cpe_process_result cpe_boot_initialize(struct cpe_info *t_info, enum cpe_svc_result *cpe_rc) { - enum cpe_process_result rc = CPE_PROC_FAILED; + enum cpe_process_result rc = CPE_SVC_FAILED; struct cpe_svc_notification payload; struct cmi_core_svc_event_system_boot *p = NULL; @@ -1991,7 +1991,7 @@ enum cmi_api_result cmi_send_msg(void *message) GFP_ATOMIC); if (!msg) { CPE_SVC_REL_LOCK(&cpe_d.cpe_api_mutex, "cpe_api"); - return CMI_API_NO_MEMORY; + return CPE_SVC_NO_MEMORY; } if (CMI_HDR_GET_OBM_FLAG(hdr) == CMI_OBM_FLAG_OUT_BAND) @@ -2006,7 +2006,7 @@ enum cmi_api_result cmi_send_msg(void *message) if (!msg->payload) { kfree(msg); CPE_SVC_REL_LOCK(&cpe_d.cpe_api_mutex, "cpe_api"); - return CMI_API_NO_MEMORY; + return CPE_SVC_NO_MEMORY; } msg->address = 0; diff --git a/techpack/audio/asoc/lahaina-port-config.h b/techpack/audio/asoc/lahaina-port-config.h index 12f89b0620b5..62cdd512be20 100644 --- a/techpack/audio/asoc/lahaina-port-config.h +++ b/techpack/audio/asoc/lahaina-port-config.h @@ -75,8 +75,8 @@ static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = { /* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */ static struct port_params tx_frame_params_shima[SWR_MSTR_PORT_LEN] = { {3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX1 */ - {7, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */ - {7, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX3 */ + {7, 5, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */ + {7, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */ }; /* 4.8 MHz clock */ diff --git a/techpack/audio/asoc/msm-audio-effects-q6-v2.c b/techpack/audio/asoc/msm-audio-effects-q6-v2.c index 4a7b4b32654e..cb795f5bef45 100644 --- a/techpack/audio/asoc/msm-audio-effects-q6-v2.c +++ b/techpack/audio/asoc/msm-audio-effects-q6-v2.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2013-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -1092,7 +1091,7 @@ int msm_audio_effects_popless_eq_handler(struct audio_client *ac, u32 packed_data_size = 0; u8 *eq_config_data = NULL; u32 *updt_config_data = NULL; - int config_param_length, prev_config_param_length = 0; + int config_param_length; pr_debug("%s\n", __func__); if (!ac || (devices == -EINVAL) || (num_commands == -EINVAL)) { @@ -1212,12 +1211,7 @@ int msm_audio_effects_popless_eq_handler(struct audio_client *ac, if (!eq_config_data) eq_config_data = kzalloc(config_param_length, GFP_KERNEL); - else if (config_param_length != prev_config_param_length) { - if (eq_config_data) - kfree(eq_config_data); - eq_config_data = kzalloc(config_param_length, - GFP_KERNEL); - } else + else memset(eq_config_data, 0, config_param_length); if (!eq_config_data) { pr_err("%s, EQ_CONFIG:memory alloc failed\n", @@ -1244,7 +1238,6 @@ int msm_audio_effects_popless_eq_handler(struct audio_client *ac, *updt_config_data++ = eq->per_band_cfg[idx].band_idx; } - prev_config_param_length = config_param_length; break; case EQ_BAND_INDEX: if (length != 1 || index_offset != 0) { @@ -1327,8 +1320,7 @@ int msm_audio_effects_popless_eq_handler(struct audio_client *ac, pr_debug("%s: did not send pp params\n", __func__); invalid_config: kfree(params); - if (eq_config_data) - kfree(eq_config_data); + kfree(eq_config_data); return rc; } EXPORT_SYMBOL(msm_audio_effects_popless_eq_handler); diff --git a/techpack/audio/asoc/msm-compress-q6-v2.c b/techpack/audio/asoc/msm-compress-q6-v2.c index df48c414b05b..14f549310547 100644 --- a/techpack/audio/asoc/msm-compress-q6-v2.c +++ b/techpack/audio/asoc/msm-compress-q6-v2.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.​ */ @@ -4220,7 +4219,6 @@ static int msm_compr_adsp_stream_cmd_put(struct snd_kcontrol *kcontrol, return -EINVAL; } - mutex_lock(&pdata->lock); cstream = pdata->cstream[fe_id]; if (cstream == NULL) { pr_err("%s cstream is null\n", __func__); @@ -4233,6 +4231,7 @@ static int msm_compr_adsp_stream_cmd_put(struct snd_kcontrol *kcontrol, return -EINVAL; } + mutex_lock(&pdata->lock); if (prtd->audio_client == NULL) { pr_err("%s: audio_client is null\n", __func__); ret = -EINVAL; diff --git a/techpack/audio/asoc/msm-lsm-client.c b/techpack/audio/asoc/msm-lsm-client.c index 7d69b97ca7c6..bd9b73571263 100644 --- a/techpack/audio/asoc/msm-lsm-client.c +++ b/techpack/audio/asoc/msm-lsm-client.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -42,11 +42,6 @@ #define LSM_IS_LAST_STAGE(client, stage_idx) \ (client->num_stages == (stage_idx + 1)) -struct lsm_char_dev { - /* Protects access to LSM client sessions and shared resources */ - struct mutex lock; -}; - static struct snd_pcm_hardware msm_pcm_hardware_capture = { .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_BLOCK_TRANSFER | @@ -688,47 +683,15 @@ static int msm_lsm_set_conf(struct snd_pcm_substream *substream, struct lsm_params_info_v2 *p_info) { struct snd_pcm_runtime *runtime = substream->runtime; - struct lsm_priv *prtd = NULL; + struct lsm_priv *prtd = runtime->private_data; struct snd_soc_pcm_runtime *rtd = substream->private_data; int rc = 0; - struct lsm_char_dev *lsm_dev; - struct snd_soc_component *component = NULL; - - if (!rtd) { - pr_err("%s substream runtime or private_data not found\n", - __func__); - return -EINVAL; - } - component = snd_soc_rtdcom_lookup(rtd, DRV_NAME); - if (!component || !component->dev) { - pr_err("%s: invalid component\n", __func__); - return -EINVAL; - } - lsm_dev = (struct lsm_char_dev *) dev_get_drvdata(component->dev); - if (!lsm_dev) { - pr_err("%s: platform data is NULL\n", __func__); - return -EINVAL; - } - - mutex_lock(&lsm_dev->lock); - if (!runtime) { - pr_err("%s: Invalid runtime", __func__); - mutex_unlock(&lsm_dev->lock); - return -EINVAL; - } - prtd = runtime->private_data; - if (!prtd || !prtd->lsm_client) { - pr_err("%s: No LSM session active\n", __func__); - mutex_unlock(&lsm_dev->lock); - return -EINVAL; - } if (p_info->param_type == LSM_MULTI_SND_MODEL_CONFIDENCE_LEVELS) { if (p_info->param_size > MAX_KEYWORDS_SUPPORTED) { dev_err(rtd->dev, "%s: invalid number of snd_model keywords %d, the max is %d\n", __func__, p_info->param_size, MAX_KEYWORDS_SUPPORTED); - mutex_unlock(&lsm_dev->lock); return -EINVAL; } @@ -739,7 +702,6 @@ static int msm_lsm_set_conf(struct snd_pcm_substream *substream, dev_err(rtd->dev, "%s: get_conf_levels failed for snd_model %d, err = %d\n", __func__, p_info->model_id, rc); - mutex_unlock(&lsm_dev->lock); return rc; } @@ -760,7 +722,6 @@ static int msm_lsm_set_conf(struct snd_pcm_substream *substream, dev_err(rtd->dev, "%s: invalid confidence levels %d\n", __func__, p_info->param_size); - mutex_unlock(&lsm_dev->lock); return -EINVAL; } @@ -772,7 +733,6 @@ static int msm_lsm_set_conf(struct snd_pcm_substream *substream, dev_err(rtd->dev, "%s: get_conf_levels failed, err = %d\n", __func__, rc); - mutex_unlock(&lsm_dev->lock); return rc; } @@ -789,7 +749,6 @@ static int msm_lsm_set_conf(struct snd_pcm_substream *substream, prtd->lsm_client->confidence_levels = NULL; } } - mutex_unlock(&lsm_dev->lock); return rc; } @@ -1030,63 +989,23 @@ static int msm_lsm_check_and_set_lab_controls(struct snd_pcm_substream *substrea u32 enable, struct lsm_params_info_v2 *p_info) { struct snd_pcm_runtime *runtime = substream->runtime; - struct lsm_priv *prtd = NULL; + struct lsm_priv *prtd = runtime->private_data; struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct lsm_hw_params *out_hw_params = NULL; - struct snd_soc_component *component = NULL; - struct lsm_char_dev *lsm_dev = NULL; + struct lsm_hw_params *out_hw_params = &prtd->lsm_client->out_hw_params; u8 *chmap = NULL; u32 ch_idx; int rc = 0, stage_idx = p_info->stage_idx; - if (!rtd) { - pr_err("%s substream runtime or private_data not found\n", - __func__); - return -EINVAL; - } - component = snd_soc_rtdcom_lookup(rtd, DRV_NAME); - if (!component || !component->dev) { - pr_err("%s: invalid component\n", __func__); - return -EINVAL; - } - lsm_dev = (struct lsm_char_dev *) dev_get_drvdata(component->dev); - if (!lsm_dev) { - pr_err("%s: platform data is NULL\n", __func__); - return -EINVAL; - } - - mutex_lock(&lsm_dev->lock); - if (!runtime) { - pr_err("%s: Invalid runtime", __func__); - mutex_unlock(&lsm_dev->lock); - return -EINVAL; - } - prtd = runtime->private_data; - if (!prtd || !prtd->lsm_client) { - pr_err("%s: No LSM session active\n", __func__); - mutex_unlock(&lsm_dev->lock); - return -EINVAL; - } - out_hw_params = &prtd->lsm_client->out_hw_params; - if (!out_hw_params) { - pr_err("%s: Invalid hw params\n", __func__); - mutex_unlock(&lsm_dev->lock); - return -EINVAL; - } - if (prtd->lsm_client->stage_cfg[stage_idx].lab_enable == enable) { dev_dbg(rtd->dev, "%s: Lab for session %d, stage %d already %s\n", __func__, prtd->lsm_client->session, stage_idx, enable ? "enabled" : "disabled"); - mutex_unlock(&lsm_dev->lock); return rc; } chmap = kzalloc(out_hw_params->num_chs, GFP_KERNEL); - if (!chmap) { - mutex_unlock(&lsm_dev->lock); + if (!chmap) return -ENOMEM; - } rc = q6lsm_lab_control(prtd->lsm_client, enable, p_info); if (rc) { @@ -1127,7 +1046,6 @@ static int msm_lsm_check_and_set_lab_controls(struct snd_pcm_substream *substrea fail: kfree(chmap); - mutex_unlock(&lsm_dev->lock); return rc; } @@ -3188,11 +3106,9 @@ static int msm_lsm_close(struct snd_pcm_substream *substream) { unsigned long flags; struct snd_pcm_runtime *runtime = substream->runtime; - struct lsm_priv *prtd = NULL; + struct lsm_priv *prtd = runtime->private_data; struct snd_soc_pcm_runtime *rtd; struct msm_pcm_stream_app_type_cfg cfg_data = {0}; - struct lsm_char_dev *lsm_dev; - struct snd_soc_component *component = NULL; int ret = 0; int be_id = 0; int fe_id = 0; @@ -3201,29 +3117,12 @@ static int msm_lsm_close(struct snd_pcm_substream *substream) pr_err("%s: Invalid private_data", __func__); return -EINVAL; } - if (!component || !component->dev) { - pr_err("%s: Invalid component\n", __func__); + if (!prtd || !prtd->lsm_client) { + pr_err("%s: No LSM session active\n", __func__); return -EINVAL; } rtd = substream->private_data; - lsm_dev = (struct lsm_char_dev *) dev_get_drvdata(component->dev); - if (!lsm_dev) { - pr_err("%s: platform data is NULL\n", __func__); - return -EINVAL; - } - mutex_lock(&lsm_dev->lock); - if (!runtime) { - pr_err("%s: Invalid runtime", __func__); - mutex_unlock(&lsm_dev->lock); - return -EINVAL; - } - prtd = runtime->private_data; - if (!prtd || !prtd->lsm_client) { - pr_err("%s: No LSM session active\n", __func__); - mutex_unlock(&lsm_dev->lock); - return -EINVAL; - } dev_dbg(rtd->dev, "%s\n", __func__); if (prtd->lsm_client->started) { if (prtd->lsm_client->lab_enable) { @@ -3333,7 +3232,6 @@ static int msm_lsm_close(struct snd_pcm_substream *substream) mutex_destroy(&prtd->lsm_api_lock); kfree(prtd); runtime->private_data = NULL; - mutex_unlock(&lsm_dev->lock); return 0; } @@ -3342,36 +3240,21 @@ static int msm_lsm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_pcm_runtime *runtime = substream->runtime; - struct lsm_priv *prtd = NULL; + struct lsm_priv *prtd = runtime->private_data; struct lsm_hw_params *out_hw_params = NULL; struct lsm_hw_params *in_hw_params = NULL; struct snd_soc_pcm_runtime *rtd; - struct lsm_char_dev *lsm_dev = NULL; - struct snd_soc_component *component = NULL; if (!substream->private_data) { pr_err("%s: Invalid private_data", __func__); return -EINVAL; } rtd = substream->private_data; - component = snd_soc_rtdcom_lookup(rtd, DRV_NAME); - if (!component || !component->dev) { - pr_err("%s: Invalid component\n", __func__); - return -EINVAL; - } - lsm_dev = (struct lsm_char_dev *) dev_get_drvdata(component->dev); - if (!lsm_dev) { - pr_err("%s: platform data is NULL\n", __func__); - return -EINVAL; - } - mutex_lock(&lsm_dev->lock); - prtd = runtime->private_data; if (!prtd || !params) { dev_err(rtd->dev, "%s: invalid params prtd %pK params %pK", __func__, prtd, params); - mutex_unlock(&lsm_dev->lock); return -EINVAL; } in_hw_params = &prtd->lsm_client->in_hw_params; @@ -3386,7 +3269,6 @@ static int msm_lsm_hw_params(struct snd_pcm_substream *substream, "%s: Invalid Params sample rate %d period count %d\n", __func__, out_hw_params->sample_rate, out_hw_params->period_count); - mutex_unlock(&lsm_dev->lock); return -EINVAL; } @@ -3397,7 +3279,6 @@ static int msm_lsm_hw_params(struct snd_pcm_substream *substream, } else { dev_err(rtd->dev, "%s: Invalid Format 0x%x\n", __func__, params_format(params)); - mutex_unlock(&lsm_dev->lock); return -EINVAL; } @@ -3418,7 +3299,6 @@ static int msm_lsm_hw_params(struct snd_pcm_substream *substream, */ memcpy(in_hw_params, out_hw_params, sizeof(struct lsm_hw_params)); - mutex_unlock(&lsm_dev->lock); return 0; } @@ -3749,14 +3629,6 @@ static struct snd_soc_component_driver msm_soc_component = { static int msm_lsm_probe(struct platform_device *pdev) { - struct lsm_char_dev *lsm_dev; - - lsm_dev = devm_kzalloc(&pdev->dev, sizeof(*lsm_dev), GFP_KERNEL); - if (!lsm_dev) - return -ENOMEM; - - mutex_init(&lsm_dev->lock); - dev_set_drvdata(&pdev->dev, lsm_dev); return snd_soc_register_component(&pdev->dev, &msm_soc_component, NULL, 0); @@ -3764,10 +3636,6 @@ static int msm_lsm_probe(struct platform_device *pdev) static int msm_lsm_remove(struct platform_device *pdev) { - struct lsm_char_dev *lsm_dev; - lsm_dev = dev_get_drvdata(&pdev->dev); - mutex_destroy(&lsm_dev->lock); - snd_soc_unregister_component(&pdev->dev); return 0; diff --git a/techpack/audio/asoc/msm-pcm-routing-v2.c b/techpack/audio/asoc/msm-pcm-routing-v2.c index 09b6ed61dd61..c3b5f480993f 100644 --- a/techpack/audio/asoc/msm-pcm-routing-v2.c +++ b/techpack/audio/asoc/msm-pcm-routing-v2.c @@ -26945,10 +26945,6 @@ static const struct snd_kcontrol_new mmul17_mixer_controls[] = { MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, @@ -41421,7 +41417,6 @@ static const struct snd_soc_dapm_route intercon_mi2s[] = { {"MultiMedia29 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, {"MultiMedia30 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, {"MultiMedia8 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"MultiMedia17 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, {"MultiMedia18 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, {"MultiMedia19 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, {"MultiMedia28 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, diff --git a/techpack/audio/asoc/msm_dailink.h b/techpack/audio/asoc/msm_dailink.h index ef588206d321..c7353b9ae05d 100644 --- a/techpack/audio/asoc/msm_dailink.h +++ b/techpack/audio/asoc/msm_dailink.h @@ -957,8 +957,7 @@ SND_SOC_DAILINK_DEFS(quat_mi2s_tx, SND_SOC_DAILINK_DEFS(quin_mi2s_rx, DAILINK_COMP_ARRAY(COMP_CPU("msm-dai-q6-mi2s.8")), - DAILINK_COMP_ARRAY(COMP_CODEC("msm-stub-codec.1", "msm-stub-rx"), - COMP_CODEC("acm8625s_codec", "acm8625s-hifi")), + DAILINK_COMP_ARRAY(COMP_CODEC("msm-stub-codec.1", "msm-stub-rx")), DAILINK_COMP_ARRAY(COMP_PLATFORM("msm-pcm-routing"))); SND_SOC_DAILINK_DEFS(quin_mi2s_tx, diff --git a/techpack/audio/dsp/q6adm.c b/techpack/audio/dsp/q6adm.c index 15a1d7830ebd..cd876fde3f37 100644 --- a/techpack/audio/dsp/q6adm.c +++ b/techpack/audio/dsp/q6adm.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -3911,14 +3911,10 @@ void adm_copp_mfc_cfg(int port_id, int copp_idx, int dst_sample_rate) pr_err("%s: unable to get channal map\n", __func__); goto fail_cmd; } - if (mfc_cfg.num_channels <= AUDPROC_MFC_OUT_CHANNELS_MAX) { - for (i = 0; i < mfc_cfg.num_channels; i++) - mfc_cfg.channel_type[i] = + + for (i = 0; i < mfc_cfg.num_channels; i++) + mfc_cfg.channel_type[i] = (uint16_t) open.dev_channel_mapping[i]; - } else { - pr_err("%s: size of num_channels is greater than channel type \n", __func__); - goto fail_cmd; - } atomic_set(&this_adm.copp.stat[port_idx][copp_idx], -1); diff --git a/techpack/camera/Makefile b/techpack/camera/Makefile index 81116b28ebb3..2568ff61c873 100644 --- a/techpack/camera/Makefile +++ b/techpack/camera/Makefile @@ -94,11 +94,6 @@ endif endif -ifeq ($(CONFIG_IBIZA_DTB), y) -LINUXINCLUDE += \ - -include $(srctree)/techpack/camera/config/legacycameraconf.h -endif - ifneq (,$(filter $(CONFIG_SPECTRA_CAMERA), y m)) # Use USERINCLUDE when you must reference the UAPI directories only. USERINCLUDE += \ diff --git a/techpack/camera/config/legacycameraconf.h b/techpack/camera/config/legacycameraconf.h deleted file mode 100644 index 6a17cb1ff12f..000000000000 --- a/techpack/camera/config/legacycameraconf.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. - */ - -#define CONFIG_SPECTRA_CAMERA_LEGACY 1 diff --git a/techpack/camera/drivers/cam_core/cam_node.c b/techpack/camera/drivers/cam_core/cam_node.c index f9fa98fe6c5c..d27bcdd6bf0d 100644 --- a/techpack/camera/drivers/cam_core/cam_node.c +++ b/techpack/camera/drivers/cam_core/cam_node.c @@ -812,7 +812,6 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) } case CAM_ACQUIRE_HW: { uint32_t api_version; - uint32_t struct_version; void *acquire_ptr = NULL; size_t acquire_size; @@ -847,16 +846,6 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) } if (api_version == 1) { - struct_version = - ((struct cam_acquire_hw_cmd_v1 *)acquire_ptr)->struct_version; - if (struct_version != api_version) { - CAM_ERR(CAM_CORE, - "Unmatched struct api version %u and struct version %u", - api_version, struct_version); - rc = -EINVAL; - goto acquire_kfree; - } - rc = __cam_node_handle_acquire_hw_v1(node, acquire_ptr); if (rc) { CAM_ERR(CAM_CORE, @@ -864,16 +853,6 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) goto acquire_kfree; } } else if (api_version == 2) { - struct_version = - ((struct cam_acquire_hw_cmd_v2 *)acquire_ptr)->struct_version; - if (struct_version != api_version) { - CAM_ERR(CAM_CORE, - "Unmatched struct api version %u and struct version %u", - api_version, struct_version); - rc = -EINVAL; - goto acquire_kfree; - } - rc = __cam_node_handle_acquire_hw_v2(node, acquire_ptr); if (rc) { CAM_ERR(CAM_CORE, diff --git a/techpack/camera/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/techpack/camera/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 900aeb051db1..137f126caedf 100644 --- a/techpack/camera/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/techpack/camera/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2022, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include diff --git a/techpack/camera/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c b/techpack/camera/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c index bda409c6453c..6d325961680c 100644 --- a/techpack/camera/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c +++ b/techpack/camera/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c @@ -574,10 +574,8 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, /* Loop through multiple command buffers */ for (i = 0; i < csl_packet->num_cmd_buf; i++) { rc = cam_packet_util_validate_cmd_desc(&cmd_desc[i]); - if (rc) { - cam_mem_put_cpu_buf(config.packet_handle); + if (rc) return rc; - } total_cmd_buf_in_bytes = cmd_desc[i].length; if (!total_cmd_buf_in_bytes) diff --git a/techpack/camera/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/techpack/camera/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index 6e10d319a224..534a05cb82f0 100644 --- a/techpack/camera/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/techpack/camera/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -383,7 +383,6 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, CAM_ERR(CAM_CSIPHY, "Inval cam_packet strut size: %zu, len_of_buff: %zu", sizeof(struct cam_packet), len); - cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle); rc = -EINVAL; return rc; } @@ -395,7 +394,6 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, if (cam_packet_util_validate_packet(csl_packet, remain_len)) { CAM_ERR(CAM_CSIPHY, "Invalid packet params"); - cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle); rc = -EINVAL; return rc; } @@ -406,7 +404,6 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, csl_packet->cmd_buf_offset / 4); else { CAM_ERR(CAM_CSIPHY, "num_cmd_buffers = %d", csl_packet->num_cmd_buf); - cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle); rc = -EINVAL; return rc; } @@ -414,7 +411,6 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, rc = cam_packet_util_validate_cmd_desc(cmd_desc); if (rc) { CAM_ERR(CAM_CSIPHY, "Invalid cmd desc ret: %d", rc); - cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle); return rc; } @@ -423,7 +419,6 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, if (rc < 0) { CAM_ERR(CAM_CSIPHY, "Failed to get cmd buf Mem address : %d", rc); - cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle); return rc; } @@ -431,8 +426,6 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, (cmd_desc->offset > (len - sizeof(struct cam_csiphy_info)))) { CAM_ERR(CAM_CSIPHY, "Not enough buffer provided for cam_cisphy_info"); - cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle); - cam_mem_put_cpu_buf(cmd_desc->mem_handle); rc = -EINVAL; return rc; } @@ -444,7 +437,6 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, index = cam_csiphy_get_instance_offset(csiphy_dev, cfg_dev->dev_handle); if (index < 0 || index >= csiphy_dev->session_max_device_support) { CAM_ERR(CAM_CSIPHY, "index in invalid: %d", index); - cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle); cam_mem_put_cpu_buf(cmd_desc->mem_handle); return -EINVAL; } @@ -455,7 +447,6 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, CAM_ERR(CAM_CSIPHY, "Wrong configuration lane_cnt: %u", cam_cmd_csiphy_info->lane_cnt); - cam_mem_put_cpu_buf((int32_t)cfg_dev->packet_handle); cam_mem_put_cpu_buf(cmd_desc->mem_handle); return rc; } diff --git a/techpack/camera/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c b/techpack/camera/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c index 5635e053f40c..9eca22741e75 100644 --- a/techpack/camera/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/techpack/camera/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -633,10 +633,8 @@ int32_t cam_handle_mem_ptr(uint64_t handle, struct cam_sensor_ctrl_t *s_ctrl) for (i = 0; i < pkt->num_cmd_buf; i++) { rc = cam_packet_util_validate_cmd_desc(&cmd_desc[i]); - if (rc) { - cam_mem_put_cpu_buf(handle); + if (rc) return rc; - } if (!(cmd_desc[i].length)) continue; diff --git a/techpack/camera/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c b/techpack/camera/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c index 4e9fabc0d822..325e52e6a5a2 100644 --- a/techpack/camera/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c +++ b/techpack/camera/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c @@ -316,12 +316,12 @@ static int32_t cam_sensor_get_io_buffer( (uint8_t *)buf_addr + io_cfg->offsets[0]; i2c_settings->read_buff_len = buf_size - io_cfg->offsets[0]; - cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); } else { CAM_ERR(CAM_SENSOR, "Invalid direction: %d", io_cfg->direction); rc = -EINVAL; } + cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); return rc; } diff --git a/techpack/camera/include/uapi/camera/media/cam_ope.h b/techpack/camera/include/uapi/camera/media/cam_ope.h index ee6c3423860f..b6a9a41d8dfe 100644 --- a/techpack/camera/include/uapi/camera/media/cam_ope.h +++ b/techpack/camera/include/uapi/camera/media/cam_ope.h @@ -73,11 +73,7 @@ #define OPE_MAX_IO_BUFS (OPE_OUT_RES_MAX + OPE_IN_RES_MAX) #define OPE_MAX_PASS 1 #define OPE_MAX_PLANES 2 -#ifdef CONFIG_SPECTRA_CAMERA_LEGACY -#define OPE_MAX_STRIPES 48 -#else #define OPE_MAX_STRIPES 64 -#endif #define OPE_MAX_BATCH_SIZE 16 /** diff --git a/techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c b/techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c index 28285a6eed57..a3f090def566 100644 --- a/techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c +++ b/techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c @@ -710,10 +710,7 @@ static int __ipa3_del_hdr_proc_ctx(u32 proc_ctx_hdl, return 0; } - if (entry->hdr && entry == entry->hdr->proc_ctx) - entry->hdr->proc_ctx = NULL; - - if (entry->hdr && release_hdr) + if (release_hdr) __ipa3_del_hdr(entry->hdr->id, false); /* move the offset entry to appropriate free list */ @@ -777,19 +774,17 @@ int __ipa3_del_hdr(u32 hdr_hdl, bool by_user) return 0; } - if (entry->proc_ctx && entry == entry->proc_ctx->hdr) - entry->proc_ctx->hdr = NULL; - if (entry->is_hdr_proc_ctx || entry->proc_ctx) { dma_unmap_single(ipa3_ctx->pdev, entry->phys_base, entry->hdr_len, DMA_TO_DEVICE); __ipa3_del_hdr_proc_ctx(entry->proc_ctx->id, false, false); + } else { + /* move the offset entry to appropriate free list */ + list_move(&entry->offset_entry->link, + &htbl->head_free_offset_list[entry->offset_entry->bin]); } - /* move the offset entry to appropriate free list */ - list_move(&entry->offset_entry->link, - &htbl->head_free_offset_list[entry->offset_entry->bin]); list_del(&entry->link); htbl->hdr_cnt--; entry->cookie = 0; diff --git a/techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_pm.c b/techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_pm.c index 0db725a54626..c2232d59b691 100644 --- a/techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_pm.c +++ b/techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/ipa_pm.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -771,9 +770,9 @@ int ipa_pm_register(struct ipa_pm_register_params *params, u32 *hdl) client->skip_clk_vote = params->skip_clk_vote; client->wlock = wakeup_source_register(NULL, client->name); if (!client->wlock) { + ipa_pm_deregister(*hdl); IPA_PM_ERR("IPA wakeup source register failed %s\n", client->name); - ipa_pm_deregister(*hdl); return -ENOMEM; } diff --git a/techpack/datarmnet-ext/shs/rmnet_shs_config.c b/techpack/datarmnet-ext/shs/rmnet_shs_config.c index a7988474c084..56115cc8d2a9 100644 --- a/techpack/datarmnet-ext/shs/rmnet_shs_config.c +++ b/techpack/datarmnet-ext/shs/rmnet_shs_config.c @@ -61,14 +61,14 @@ DATARMNET5fc54f7a13 __read_mostly={.notifier_call=DATARMNETe9173bbe0e,.priority= "\x49\x32\x36\x33\x33\x36\x37\x39\x61\x65\x36\x34\x37\x61\x30\x36\x36\x62\x32\x38\x36\x32\x66\x39\x31\x33\x30\x31\x31\x64\x33\x33\x65\x33\x38\x32\x36\x63\x61\x32\x35" , "\x49\x36\x36\x39\x35\x65\x39\x38\x30\x63\x35\x65\x37\x62\x62\x32\x39\x33\x36\x35\x63\x34\x37\x65\x31\x35\x33\x36\x64\x63\x31\x34\x65\x66\x61\x31\x63\x30\x30\x34\x33" -};static int DATARMNET2cb9ae589c;static int __init DATARMNET163e93649e(void){pr_info( +};static int DATARMNET2cb9ae589c;int __init DATARMNET163e93649e(void){pr_info( "\x25\x73\x28\x29\x3a\x20\x53\x74\x61\x72\x74\x69\x6e\x67\x20\x72\x6d\x6e\x65\x74\x20\x53\x48\x53\x20\x6d\x6f\x64\x75\x6c\x65\x20\x25\x73\x20" "\n" ,__func__,DATARMNETbc8418e817[(0xd2d+202-0xdf7)]);trace_rmnet_shs_high( DATARMNET1790979ccf,DATARMNET72cb00fdc0,(0x16e8+787-0xc0c),(0x16e8+787-0xc0c), (0x16e8+787-0xc0c),(0x16e8+787-0xc0c),NULL,NULL);if(DATARMNET0dbc627e8f()){ rm_err("\x25\x73", "\x53\x48\x53\x5f\x47\x4e\x4c\x3a\x20\x46\x61\x69\x6c\x65\x64\x20\x74\x6f\x20\x69\x6e\x69\x74\x20\x67\x65\x6e\x65\x72\x69\x63\x20\x6e\x65\x74\x6c\x69\x6e\x6b" -);}return register_netdevice_notifier(&DATARMNET5fc54f7a13);}static void __exit +);}return register_netdevice_notifier(&DATARMNET5fc54f7a13);}void __exit DATARMNETf3298dab6f(void){trace_rmnet_shs_high(DATARMNET1790979ccf, DATARMNET89958f9b63,(0x16e8+787-0xc0c),(0x16e8+787-0xc0c),(0x16e8+787-0xc0c), (0x16e8+787-0xc0c),NULL,NULL);unregister_netdevice_notifier(&DATARMNET5fc54f7a13 diff --git a/techpack/datarmnet-ext/shs/rmnet_shs_config.h b/techpack/datarmnet-ext/shs/rmnet_shs_config.h index 52a342bd3157..ac99913202f5 100644 --- a/techpack/datarmnet-ext/shs/rmnet_shs_config.h +++ b/techpack/datarmnet-ext/shs/rmnet_shs_config.h @@ -20,6 +20,7 @@ #define DATARMNET8120d41372 (0xd1f+216-0xdf5) #define DATARMNET47c2367f93 (0xd18+223-0xdf4) extern struct DATARMNETa6b20d7e8b DATARMNETecc0627c70;extern int -rmnet_is_real_dev_registered(const struct net_device*real_dev); +rmnet_is_real_dev_registered(const struct net_device*real_dev);int __init +DATARMNET163e93649e(void);void __exit DATARMNETf3298dab6f(void); #endif diff --git a/techpack/display/config/lahainadisp.conf b/techpack/display/config/lahainadisp.conf index 953a3ef338f8..d413be39445f 100644 --- a/techpack/display/config/lahainadisp.conf +++ b/techpack/display/config/lahainadisp.conf @@ -4,7 +4,7 @@ export CONFIG_DRM_MSM_DP=y export CONFIG_DRM_MSM_DP_MST=y export CONFIG_SYNC_FILE=y export CONFIG_DRM_MSM_DSI=y -export CONFIG_DSI_PARSER=n +export CONFIG_DSI_PARSER=y export CONFIG_DRM_SDE_WB=y export CONFIG_DRM_MSM_REGISTER_LOGGING=y export CONFIG_QCOM_MDSS_PLL=y diff --git a/techpack/display/config/lahainadispconf.h b/techpack/display/config/lahainadispconf.h index 3a0210956e2a..e72e0a43f1ab 100644 --- a/techpack/display/config/lahainadispconf.h +++ b/techpack/display/config/lahainadispconf.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2020, The Linux Foundation. All rights reserved. */ #define CONFIG_DRM_MSM 1 @@ -10,6 +9,7 @@ #define CONFIG_DRM_MSM_SDE 1 #define CONFIG_SYNC_FILE 1 #define CONFIG_DRM_MSM_DSI 1 +#define CONFIG_DSI_PARSER 1 #define CONFIG_DRM_SDE_WB 1 #define CONFIG_DRM_MSM_REGISTER_LOGGING 1 #define CONFIG_DRM_SDE_EVTLOG_DEBUG 1 diff --git a/techpack/display/msm/dp/dp_display.c b/techpack/display/msm/dp/dp_display.c index 0e7760d242d2..ddafc11d5921 100644 --- a/techpack/display/msm/dp/dp_display.c +++ b/techpack/display/msm/dp/dp_display.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ @@ -1184,7 +1184,6 @@ error_ctrl: static int dp_display_panel_ready(struct dp_display_private *dp) { int rc = 0; - bool skip_op = is_skip_required(&dp->dp_display); if (dp->dp_display.is_edp) { rc = dp->power->edp_panel_set_gpio(dp->power, DP_GPIO_EDP_VCC_EN, true); @@ -1202,9 +1201,9 @@ static int dp_display_panel_ready(struct dp_display_private *dp) } return -ETIMEDOUT; } - - dp->panel->init(dp->panel, skip_op); } + if (!dp->dp_display.cont_splash_enabled) + dp->panel->init(dp->panel); return 0; } @@ -1248,7 +1247,6 @@ static int dp_display_host_ready(struct dp_display_private *dp) dp->ctrl->abort(dp->ctrl, false); dp->aux->init(dp->aux, dp->parser->aux_cfg, skip_op); - dp_display_state_add(DP_STATE_READY); /* log this as it results from user action of cable connection */ DP_INFO("[OK]\n"); @@ -3920,7 +3918,6 @@ static int dp_display_get_display_type(struct dp_display *dp_display, const char **display_type) { struct dp_display_private *dp; - struct device_node *of_node; if (!dp_display || !display_type) { pr_err("invalid input\n"); @@ -3930,11 +3927,7 @@ static int dp_display_get_display_type(struct dp_display *dp_display, dp = container_of(dp_display, struct dp_display_private, dp_display); if (dp->parser) *display_type = dp->parser->display_type; - else { - of_node = dp->pdev->dev.of_node; - *display_type = of_get_property(of_node, "qcom,display-type", - NULL); - } + return 0; } diff --git a/techpack/display/msm/dp/dp_drm.c b/techpack/display/msm/dp/dp_drm.c index ad90da674401..6af98873cb38 100644 --- a/techpack/display/msm/dp/dp_drm.c +++ b/techpack/display/msm/dp/dp_drm.c @@ -471,7 +471,6 @@ int dp_connector_get_info(struct drm_connector *connector, { struct dp_display *display = data; const char *display_type = NULL; - u32 conn_disp_type = SDE_CONNECTOR_PRIMARY; if (!info || !display || !display->drm_dev) { DP_ERR("invalid params\n"); @@ -481,11 +480,11 @@ int dp_connector_get_info(struct drm_connector *connector, info->intf_type = DRM_MODE_CONNECTOR_DisplayPort; display->get_display_type(display, &display_type); - if (display_type) { + if (display_type){ if (!strcmp(display_type, "primary")) - conn_disp_type = SDE_CONNECTOR_PRIMARY; + info->display_type = SDE_CONNECTOR_PRIMARY; else if (!strcmp(display_type, "secondary")) - conn_disp_type = SDE_CONNECTOR_SECONDARY; + info->display_type = SDE_CONNECTOR_SECONDARY; } info->num_of_h_tiles = 1; @@ -496,8 +495,7 @@ int dp_connector_get_info(struct drm_connector *connector, if (display && display->is_edp) { info->intf_type = DRM_MODE_CONNECTOR_eDP; - info->display_type = conn_disp_type; - if (display->ext_hpd_en) + if(display->ext_hpd_en) info->capabilities |= MSM_DISPLAY_CAP_HOT_PLUG; else info->is_connected = true; diff --git a/techpack/display/msm/dp/dp_panel.c b/techpack/display/msm/dp/dp_panel.c index a9f65f1aba8c..8fc1b13c3e32 100644 --- a/techpack/display/msm/dp/dp_panel.c +++ b/techpack/display/msm/dp/dp_panel.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ @@ -2381,7 +2381,7 @@ error: return rc; } -static int dp_panel_init_panel_info(struct dp_panel *dp_panel, bool skip_op) +static int dp_panel_init_panel_info(struct dp_panel *dp_panel) { int rc = 0; struct dp_panel_private *panel; @@ -2393,9 +2393,6 @@ static int dp_panel_init_panel_info(struct dp_panel *dp_panel, bool skip_op) goto end; } - if (skip_op) - goto end; - panel = container_of(dp_panel, struct dp_panel_private, dp_panel); pinfo = &dp_panel->pinfo; diff --git a/techpack/display/msm/dp/dp_panel.h b/techpack/display/msm/dp/dp_panel.h index 206b62dc32c7..3abb41297584 100644 --- a/techpack/display/msm/dp/dp_panel.h +++ b/techpack/display/msm/dp/dp_panel.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. */ @@ -162,7 +162,7 @@ struct dp_panel { s64 fec_overhead_fp; - int (*init)(struct dp_panel *dp_panel, bool skip_op); + int (*init)(struct dp_panel *dp_panel); int (*deinit)(struct dp_panel *dp_panel, u32 flags); int (*hw_cfg)(struct dp_panel *dp_panel, bool enable); int (*read_sink_caps)(struct dp_panel *dp_panel, diff --git a/techpack/display/msm/dp/dp_parser.c b/techpack/display/msm/dp/dp_parser.c index 0a138bbe4a1d..ea5546ea476c 100644 --- a/techpack/display/msm/dp/dp_parser.c +++ b/techpack/display/msm/dp/dp_parser.c @@ -178,10 +178,13 @@ static int dp_parser_misc(struct dp_parser *parser) &parser->pixel_base_off[i]); } - parser->display_type = of_get_property(of_node, "qcom,display-type", - NULL); - if (!parser->display_type) - parser->display_type = "unknown"; + parser->display_type = of_get_property(of_node, "qcom,display-type", NULL); + if (!parser->display_type) { + if (parser->is_edp) + parser->display_type = "primary"; + else + parser->display_type = "secondary"; + } parser->panel_notifier_support = of_property_read_bool(of_node, "qcom,panel-notifier-support"); diff --git a/techpack/display/msm/dsi/dsi_ctrl.c b/techpack/display/msm/dsi/dsi_ctrl.c index 988b3e60a462..278e3dcbe921 100644 --- a/techpack/display/msm/dsi/dsi_ctrl.c +++ b/techpack/display/msm/dsi/dsi_ctrl.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -229,10 +229,10 @@ static ssize_t debugfs_line_count_read(struct file *file, dsi_ctrl->cmd_trigger_frame); len += scnprintf((buf + len), max_len - len, "Command successful at line: %04x\n", - atomic_read(&dsi_ctrl->cmd_success_line)); + dsi_ctrl->cmd_success_line); len += scnprintf((buf + len), max_len - len, "Command successful at frame: %04x\n", - atomic_read(&dsi_ctrl->cmd_success_frame)); + dsi_ctrl->cmd_success_frame); mutex_unlock(&dsi_ctrl->ctrl_lock); @@ -2891,13 +2891,12 @@ static irqreturn_t dsi_ctrl_isr(int irq, void *ptr) if (dsi_ctrl->enable_cmd_dma_stats) { u32 reg = dsi_ctrl->hw.ops.log_line_count(&dsi_ctrl->hw, dsi_ctrl->cmd_mode); - atomic_set(&dsi_ctrl->cmd_success_line, (reg & 0xFFFF)); - atomic_set(&dsi_ctrl->cmd_success_frame, ((reg >> 16) & 0xFFFF)); + dsi_ctrl->cmd_success_line = (reg & 0xFFFF); + dsi_ctrl->cmd_success_frame = ((reg >> 16) & 0xFFFF); SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_CASE1, dsi_ctrl->cmd_success_line, dsi_ctrl->cmd_success_frame); } - atomic_set(&dsi_ctrl->dma_irq_trig, 1); dsi_ctrl_disable_status_interrupt(dsi_ctrl, DSI_SINT_CMD_MODE_DMA_DONE); diff --git a/techpack/display/msm/dsi/dsi_ctrl.h b/techpack/display/msm/dsi/dsi_ctrl.h index 944debaa28a4..a3290750520b 100644 --- a/techpack/display/msm/dsi/dsi_ctrl.h +++ b/techpack/display/msm/dsi/dsi_ctrl.h @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. */ @@ -310,8 +309,8 @@ struct dsi_ctrl { bool cmd_mode; u32 cmd_trigger_line; u32 cmd_trigger_frame; - atomic_t cmd_success_line; - atomic_t cmd_success_frame; + u32 cmd_success_line; + u32 cmd_success_frame; }; /** diff --git a/techpack/display/msm/dsi/dsi_display.c b/techpack/display/msm/dsi/dsi_display.c index 51c6376b6a17..506d24720a29 100644 --- a/techpack/display/msm/dsi/dsi_display.c +++ b/techpack/display/msm/dsi/dsi_display.c @@ -6488,25 +6488,15 @@ static int dsi_display_init(struct dsi_display *display) if (rc) { DSI_ERR("[%s] failed to enable vregs, rc=%d\n", display->panel->name, rc); - goto vreg_fail; + return rc; } } rc = component_add(&pdev->dev, &dsi_display_comp_ops); - if (rc) { + if (rc) DSI_ERR("component add failed, rc=%d\n", rc); - goto comp_add_fail; - } DSI_DEBUG("component add success: %s\n", display->name); - return rc; - -comp_add_fail: - if (display->panel) - dsi_pwr_enable_regulator(&display->panel->power_info, false); -vreg_fail: - _dsi_display_dev_deinit(display); - end: return rc; } @@ -7836,10 +7826,8 @@ exit: rc = 0; error: - if (rc) { + if (rc) kfree(display->modes); - display->modes = NULL; - } mutex_unlock(&display->display_lock); return rc; diff --git a/techpack/display/msm/msm_cooling_device.c b/techpack/display/msm/msm_cooling_device.c index 73ce8f200737..c2cc26e75311 100644 --- a/techpack/display/msm/msm_cooling_device.c +++ b/techpack/display/msm/msm_cooling_device.c @@ -1,17 +1,19 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. */ #include #include #include "msm_cooling_device.h" +#define BRIGHTNESS_CDEV_MAX 255 + static int sde_cdev_get_max_brightness(struct thermal_cooling_device *cdev, unsigned long *state) { struct sde_cdev *disp_cdev = (struct sde_cdev *)cdev->devdata; - *state = disp_cdev->bd->props.max_brightness; + *state = disp_cdev->bd->props.max_brightness / disp_cdev->cdev_sf; return 0; } @@ -21,7 +23,8 @@ static int sde_cdev_get_cur_brightness(struct thermal_cooling_device *cdev, { struct sde_cdev *disp_cdev = (struct sde_cdev *)cdev->devdata; - *state = disp_cdev->bd->props.max_brightness - disp_cdev->thermal_state; + *state = ((disp_cdev->bd->props.max_brightness - + disp_cdev->thermal_state) / disp_cdev->cdev_sf); return 0; } @@ -32,10 +35,11 @@ static int sde_cdev_set_cur_brightness(struct thermal_cooling_device *cdev, struct sde_cdev *disp_cdev = (struct sde_cdev *)cdev->devdata; unsigned long brightness_lvl = 0; - if (state > disp_cdev->bd->props.max_brightness) + if (state > disp_cdev->bd->props.max_brightness / disp_cdev->cdev_sf) return -EINVAL; - brightness_lvl = disp_cdev->bd->props.max_brightness - state; + brightness_lvl = disp_cdev->bd->props.max_brightness - + (state * disp_cdev->cdev_sf); if (brightness_lvl == disp_cdev->thermal_state) return 0; disp_cdev->thermal_state = brightness_lvl; @@ -67,6 +71,13 @@ struct sde_cdev *backlight_cdev_register(struct device *dev, return ERR_PTR(-ENOMEM); disp_cdev->thermal_state = 0; disp_cdev->bd = bd; + + if (bd->props.max_brightness > BRIGHTNESS_CDEV_MAX) + disp_cdev->cdev_sf = (bd->props.max_brightness / + BRIGHTNESS_CDEV_MAX); + else + disp_cdev->cdev_sf = 1; + disp_cdev->cdev = thermal_of_cooling_device_register(dev->of_node, (char *)dev_name(&bd->dev), disp_cdev, &sde_cdev_ops); diff --git a/techpack/display/msm/msm_cooling_device.h b/techpack/display/msm/msm_cooling_device.h index b95bf45c3449..5533aabac892 100644 --- a/techpack/display/msm/msm_cooling_device.h +++ b/techpack/display/msm/msm_cooling_device.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. */ #ifndef __SDE_THERMAL_CORE_H__ @@ -16,6 +16,7 @@ struct sde_cdev { struct thermal_cooling_device *cdev; struct backlight_device *bd; unsigned long thermal_state; + unsigned int cdev_sf; }; #ifdef CONFIG_THERMAL_OF diff --git a/techpack/display/msm/msm_smmu.c b/techpack/display/msm/msm_smmu.c index af9ba0ba87f5..53f5f926560a 100644 --- a/techpack/display/msm/msm_smmu.c +++ b/techpack/display/msm/msm_smmu.c @@ -1,5 +1,4 @@ /* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark @@ -212,10 +211,6 @@ static void msm_smmu_destroy(struct msm_mmu *mmu) { struct msm_smmu *smmu = to_msm_smmu(mmu); struct platform_device *pdev = to_platform_device(smmu->client_dev); - struct iommu_domain *domain = iommu_get_domain_for_dev(smmu->client_dev); - - if (domain) - iommu_set_fault_handler(domain, NULL, NULL); if (smmu->client_dev) platform_device_unregister(pdev); diff --git a/techpack/display/msm/sde/sde_crtc.h b/techpack/display/msm/sde/sde_crtc.h index 3a9e4b68eb0b..75fb998ed06d 100644 --- a/techpack/display/msm/sde/sde_crtc.h +++ b/techpack/display/msm/sde/sde_crtc.h @@ -519,8 +519,7 @@ static inline int sde_crtc_get_mixer_width(struct sde_crtc *sde_crtc, if (cstate->num_ds_enabled) mixer_width = cstate->ds_cfg[0].lm_width; else - mixer_width = sde_crtc->num_mixers ? - mode->hdisplay / sde_crtc->num_mixers : mode->hdisplay; + mixer_width = mode->hdisplay / sde_crtc->num_mixers; return mixer_width; } diff --git a/techpack/display/msm/sde/sde_kms.c b/techpack/display/msm/sde/sde_kms.c index ab090babd5e7..63e33a7481d5 100644 --- a/techpack/display/msm/sde/sde_kms.c +++ b/techpack/display/msm/sde/sde_kms.c @@ -1,5 +1,5 @@ /* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark @@ -1264,6 +1264,16 @@ static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms, SDE_EVT32(DRMID(crtc), crtc->state->active, sde_kms->splash_data.num_splash_displays); + /*remove all votes if eDP displays are done with splash*/ + if (dp_display_get_num_of_boot_displays()) { + for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) + sde_power_data_bus_set_quota(phandle, i, + SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA, + phandle->ib_quota[i]); + pm_runtime_put_sync(sde_kms->dev->dev); + sde_kms->splash_data.num_splash_displays--; + } + for (i = 0; i < MAX_DSI_DISPLAYS; i++) { splash_display = &sde_kms->splash_data.splash_display[i]; if (splash_display->encoder && @@ -3395,7 +3405,7 @@ static int sde_kms_cont_splash_config(struct msm_kms *kms, struct msm_display_info info; struct drm_encoder *encoder = NULL; struct drm_crtc *crtc = NULL; - int i, rc = 0, splash_index = 0; + int i, rc = 0; struct drm_display_mode *drm_mode = NULL; struct drm_device *dev; struct msm_drm_private *priv; @@ -3433,7 +3443,7 @@ static int sde_kms_cont_splash_config(struct msm_kms *kms, DRM_INFO("cont_splash enabled in %d of %d display(s)\n", sde_kms->splash_data.num_splash_displays, - sde_kms->dsi_display_count + sde_kms->dp_display_count); + sde_kms->dsi_display_count); /* dsi */ for (i = 0; i < sde_kms->dsi_display_count; ++i) { @@ -3499,20 +3509,11 @@ static int sde_kms_cont_splash_config(struct msm_kms *kms, mutex_unlock(&dev->mode_config.mutex); return -EINVAL; } + mutex_unlock(&dev->mode_config.mutex); crtc->state->encoder_mask = (1 << drm_encoder_index(encoder)); - /* get supported modes in case of external bridge panels*/ - if (!dsi_display->panel->num_timing_nodes) { - connector->funcs->fill_modes(connector, - dev->mode_config.max_width, - dev->mode_config.max_height); - drm_mode = list_first_entry(&connector->modes, - struct drm_display_mode, head); - } - else - drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, state); - mutex_unlock(&dev->mode_config.mutex); + drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, state); if (!drm_mode) { SDE_ERROR("drm_mode not found; handoff_type:%d\n", sde_kms->splash_data.type); @@ -3569,19 +3570,6 @@ static int sde_kms_cont_splash_config(struct msm_kms *kms, break; } - splash_display = &sde_kms->splash_data.splash_display[splash_index]; - if (splash_display->cont_splash_enabled) { - priv = sde_kms->dev->dev_private; - encoder->crtc = priv->crtcs[splash_index]; - splash_display->encoder = encoder; - - SDE_DEBUG("dp-display:%d splash_index:%d crtc id[%d]:%d enc id[%d]:%d\n", - i, splash_index, encoder->crtc->index, encoder->crtc->base.id, - encoder->index, encoder->base.id); - - splash_index++; - } - mutex_lock(&dev->mode_config.mutex); drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { diff --git a/techpack/display/msm/sde/sde_rm.c b/techpack/display/msm/sde/sde_rm.c index 0922d7818db0..4367cf9d2055 100644 --- a/techpack/display/msm/sde/sde_rm.c +++ b/techpack/display/msm/sde/sde_rm.c @@ -987,7 +987,7 @@ static bool _sde_rm_check_lm_and_get_connected_blks( u32 conn_lm_mask) { const struct sde_lm_cfg *lm_cfg = to_sde_hw_mixer(lm->hw)->cap; - const struct sde_pingpong_cfg *pp_cfg = NULL; + const struct sde_pingpong_cfg *pp_cfg; bool ret, is_conn_primary, is_conn_secondary; u32 lm_primary_pref, lm_secondary_pref, cwb_pref; diff --git a/techpack/display/msm/sde/sde_wb.c b/techpack/display/msm/sde/sde_wb.c index d6648ad7e2fc..dcb308fabf84 100644 --- a/techpack/display/msm/sde/sde_wb.c +++ b/techpack/display/msm/sde/sde_wb.c @@ -204,8 +204,6 @@ int sde_wb_connector_set_modes(struct sde_wb_device *wb_dev, memset(&dispmode, 0, sizeof(dispmode)); ret = drm_mode_convert_umode(wb_dev->drm_dev, &dispmode, &modeinfo[i]); - /* null terminate the string */ - modeinfo[i].name[DRM_DISPLAY_MODE_LEN - 1] = '\0'; if (ret) { SDE_ERROR( "failed to convert mode %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x status:%d rc:%d\n", diff --git a/techpack/display/rotator/sde_rotator_r3.c b/techpack/display/rotator/sde_rotator_r3.c index f36c0ce6ce7c..b1e2f15a4b84 100644 --- a/techpack/display/rotator/sde_rotator_r3.c +++ b/techpack/display/rotator/sde_rotator_r3.c @@ -1419,14 +1419,14 @@ static void sde_hw_rotator_vbif_rt_setting(void) for (j = 0; j < MAX_XIN; j++) { reg_high = ((mdata->vbif_xin_id[j] & 0x8) >> 3) * 4 + (i * 8); - reg_shift = (mdata->vbif_xin_id[j] & 0x7) * 4; + reg_shift = mdata->vbif_xin_id[j] * 4; reg_val = SDE_VBIF_READ(mdata, MMSS_VBIF_NRT_VBIF_QOS_RP_REMAP_000 + reg_high); reg_val_lvl = SDE_VBIF_READ(mdata, MMSS_VBIF_NRT_VBIF_QOS_LVL_REMAP_000 + reg_high); - mask = 0x7 << reg_shift; + mask = 0x7 << (mdata->vbif_xin_id[j] * 4); vbif_qos = mdata->vbif_nrt_qos[i]; diff --git a/techpack/video/msm/vidc/msm_venc.c b/techpack/video/msm/vidc/msm_venc.c index f95639e02465..25a282e5aa4a 100644 --- a/techpack/video/msm/vidc/msm_venc.c +++ b/techpack/video/msm/vidc/msm_venc.c @@ -3710,9 +3710,6 @@ int msm_venc_enable_hybrid_hp(struct msm_vidc_inst *inst) if (ctrl->val) return 0; - if (msm_vidc_get_fps(inst) <= 60) - return 0; - ctrl = get_ctrl(inst, V4L2_CID_MPEG_VIDC_VIDEO_HEVC_MAX_HIER_CODING_LAYER); layer = get_ctrl(inst, V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_LAYER); diff --git a/techpack/video/msm/vidc/msm_vidc.c b/techpack/video/msm/vidc/msm_vidc.c index db0f6529abb8..d848eb08976b 100644 --- a/techpack/video/msm/vidc/msm_vidc.c +++ b/techpack/video/msm/vidc/msm_vidc.c @@ -1482,6 +1482,7 @@ static void close_helper(struct kref *kref) { struct msm_vidc_inst *inst = container_of(kref, struct msm_vidc_inst, kref); + msm_vidc_destroy(inst); } @@ -1496,19 +1497,19 @@ void *msm_vidc_open(int core_id, int session_type) session_type >= MSM_VIDC_MAX_DEVICES) { d_vpr_e("Invalid input, core_id = %d, session = %d\n", core_id, session_type); - return NULL; + goto err_invalid_core; } core = get_vidc_core(core_id); if (!core) { d_vpr_e("Failed to find core for core_id = %d\n", core_id); - return NULL; + goto err_invalid_core; } inst = kzalloc(sizeof(*inst), GFP_KERNEL); if (!inst) { d_vpr_e("Failed to allocate memory\n"); rc = -ENOMEM; - return NULL; + goto err_invalid_core; } mutex_lock(&core->lock); rc = get_sid(&inst->sid, session_type); @@ -1608,15 +1609,14 @@ void *msm_vidc_open(int core_id, int session_type) s_vpr_e(inst->sid, "Failed to move video instance to init state\n"); kref_put(&inst->kref, close_helper); - return NULL; + inst = NULL; + goto err_invalid_core; } if (msm_comm_check_for_inst_overload(core)) { s_vpr_e(inst->sid, "Instance count reached Max limit, rejecting session"); - msm_comm_kill_session(inst); - kref_put(&inst->kref, close_helper); - return NULL; + goto fail_init; } msm_comm_scale_clocks_and_bus(inst, 1); @@ -1625,6 +1625,14 @@ void *msm_vidc_open(int core_id, int session_type) msm_vidc_debugfs_init_inst(inst, core->debugfs_root); return inst; +fail_init: + mutex_lock(&core->lock); + list_del(&inst->list); + mutex_unlock(&core->lock); + + v4l2_fh_del(&inst->event_handler); + v4l2_fh_exit(&inst->event_handler); + vb2_queue_release(&inst->bufq[INPUT_PORT].vb2_bufq); fail_bufq_output: vb2_queue_release(&inst->bufq[OUTPUT_PORT].vb2_bufq); fail_bufq_capture: @@ -1652,6 +1660,7 @@ err_invalid_sid: put_sid(inst->sid); kfree(inst); inst = NULL; +err_invalid_core: return inst; } EXPORT_SYMBOL(msm_vidc_open); diff --git a/techpack/video/msm/vidc/msm_vidc_common.c b/techpack/video/msm/vidc/msm_vidc_common.c index de7670f265cb..f38687d5e943 100644 --- a/techpack/video/msm/vidc/msm_vidc_common.c +++ b/techpack/video/msm/vidc/msm_vidc_common.c @@ -2728,7 +2728,7 @@ exit: put_inst(inst); } -void handle_cmd_response(u32 cmd, void *data) +void handle_cmd_response(enum hal_command_response cmd, void *data) { switch (cmd) { case HAL_SYS_INIT_DONE: diff --git a/techpack/video/msm/vidc/msm_vidc_internal.h b/techpack/video/msm/vidc/msm_vidc_internal.h index a74630199b45..0f1614a613d3 100644 --- a/techpack/video/msm/vidc/msm_vidc_internal.h +++ b/techpack/video/msm/vidc/msm_vidc_internal.h @@ -623,7 +623,7 @@ struct msm_vidc_ctrl { const char * const *qmenu; }; -void handle_cmd_response(u32 cmd, void *data); +void handle_cmd_response(enum hal_command_response cmd, void *data); int msm_vidc_trigger_ssr(struct msm_vidc_core *core, u64 trigger_ssr_val); int msm_vidc_noc_error_info(struct msm_vidc_core *core); diff --git a/techpack/video/msm/vidc/vidc_hfi_api.h b/techpack/video/msm/vidc/vidc_hfi_api.h index 17b28bcb0b3a..069185c1b0d8 100644 --- a/techpack/video/msm/vidc/vidc_hfi_api.h +++ b/techpack/video/msm/vidc/vidc_hfi_api.h @@ -678,8 +678,10 @@ struct hfi_device { enum hal_default_properties (*get_default_properties)(void *dev); }; -typedef void (*hfi_cmd_response_callback) (u32 cmd, void *data); -typedef void (*msm_vidc_callback) (u32 response, void *callback); +typedef void (*hfi_cmd_response_callback) (enum hal_command_response cmd, + void *data); +typedef void (*msm_vidc_callback) (enum hal_command_response response, + void *callback); struct hfi_device *vidc_hfi_initialize(enum msm_vidc_hfi_type hfi_type, u32 device_id, struct msm_vidc_platform_resources *res, diff --git a/tools/bpf/bpftool/Documentation/bpftool-btf.rst b/tools/bpf/bpftool/Documentation/bpftool-btf.rst index ce3a724f50c1..39615f8e145b 100644 --- a/tools/bpf/bpftool/Documentation/bpftool-btf.rst +++ b/tools/bpf/bpftool/Documentation/bpftool-btf.rst @@ -230,14 +230,9 @@ SEE ALSO **bpf**\ (2), **bpf-helpers**\ (7), **bpftool**\ (8), - **bpftool-btf**\ (8), + **bpftool-map**\ (8), + **bpftool-prog**\ (8), **bpftool-cgroup**\ (8), **bpftool-feature**\ (8), - **bpftool-gen**\ (8), - **bpftool-iter**\ (8), - **bpftool-link**\ (8), - **bpftool-map**\ (8), **bpftool-net**\ (8), - **bpftool-perf**\ (8), - **bpftool-prog**\ (8), - **bpftool-struct_ops**\ (8) + **bpftool-perf**\ (8) diff --git a/tools/bpf/bpftool/Documentation/bpftool-cgroup.rst b/tools/bpf/bpftool/Documentation/bpftool-cgroup.rst index e4d9da654e84..06a28b07787d 100644 --- a/tools/bpf/bpftool/Documentation/bpftool-cgroup.rst +++ b/tools/bpf/bpftool/Documentation/bpftool-cgroup.rst @@ -20,7 +20,7 @@ SYNOPSIS CGROUP COMMANDS =============== -| **bpftool** **cgroup** { **show** | **list** } *CGROUP* [**effective**] +| **bpftool** **cgroup { show | list }** *CGROUP* [**effective**] | **bpftool** **cgroup tree** [*CGROUP_ROOT*] [**effective**] | **bpftool** **cgroup attach** *CGROUP* *ATTACH_TYPE* *PROG* [*ATTACH_FLAGS*] | **bpftool** **cgroup detach** *CGROUP* *ATTACH_TYPE* *PROG* @@ -160,13 +160,9 @@ SEE ALSO **bpf**\ (2), **bpf-helpers**\ (7), **bpftool**\ (8), - **bpftool-btf**\ (8), - **bpftool-feature**\ (8), - **bpftool-gen**\ (8), - **bpftool-iter**\ (8), - **bpftool-link**\ (8), + **bpftool-prog**\ (8), **bpftool-map**\ (8), + **bpftool-feature**\ (8), **bpftool-net**\ (8), **bpftool-perf**\ (8), - **bpftool-prog**\ (8), - **bpftool-struct_ops**\ (8) + **bpftool-btf**\ (8) diff --git a/tools/bpf/bpftool/Documentation/bpftool-feature.rst b/tools/bpf/bpftool/Documentation/bpftool-feature.rst index 4cebebb2e75f..4d08f35034a2 100644 --- a/tools/bpf/bpftool/Documentation/bpftool-feature.rst +++ b/tools/bpf/bpftool/Documentation/bpftool-feature.rst @@ -28,7 +28,7 @@ DESCRIPTION =========== **bpftool feature probe** [**kernel**] [**macros** [**prefix** *PREFIX*]] Probe the running kernel and dump a number of eBPF-related - parameters, such as availability of the **bpf**\ () system call, + parameters, such as availability of the **bpf()** system call, JIT status, eBPF program types availability, eBPF helper functions availability, and more. @@ -82,13 +82,9 @@ SEE ALSO **bpf**\ (2), **bpf-helpers**\ (7), **bpftool**\ (8), - **bpftool-btf**\ (8), - **bpftool-cgroup**\ (8), - **bpftool-gen**\ (8), - **bpftool-iter**\ (8), - **bpftool-link**\ (8), + **bpftool-prog**\ (8), **bpftool-map**\ (8), + **bpftool-cgroup**\ (8), **bpftool-net**\ (8), **bpftool-perf**\ (8), - **bpftool-prog**\ (8), - **bpftool-struct_ops**\ (8) + **bpftool-btf**\ (8) diff --git a/tools/bpf/bpftool/Documentation/bpftool-gen.rst b/tools/bpf/bpftool/Documentation/bpftool-gen.rst deleted file mode 100644 index 64fac6bee0fe..000000000000 --- a/tools/bpf/bpftool/Documentation/bpftool-gen.rst +++ /dev/null @@ -1,307 +0,0 @@ -================ -bpftool-gen -================ -------------------------------------------------------------------------------- -tool for BPF code-generation -------------------------------------------------------------------------------- - -:Manual section: 8 - -SYNOPSIS -======== - - **bpftool** [*OPTIONS*] **gen** *COMMAND* - - *OPTIONS* := { { **-j** | **--json** } [{ **-p** | **--pretty** }] } - - *COMMAND* := { **skeleton** | **help** } - -GEN COMMANDS -============= - -| **bpftool** **gen skeleton** *FILE* -| **bpftool** **gen help** - -DESCRIPTION -=========== - **bpftool gen skeleton** *FILE* - Generate BPF skeleton C header file for a given *FILE*. - - BPF skeleton is an alternative interface to existing libbpf - APIs for working with BPF objects. Skeleton code is intended - to significantly shorten and simplify code to load and work - with BPF programs from userspace side. Generated code is - tailored to specific input BPF object *FILE*, reflecting its - structure by listing out available maps, program, variables, - etc. Skeleton eliminates the need to lookup mentioned - components by name. Instead, if skeleton instantiation - succeeds, they are populated in skeleton structure as valid - libbpf types (e.g., **struct bpf_map** pointer) and can be - passed to existing generic libbpf APIs. - - In addition to simple and reliable access to maps and - programs, skeleton provides a storage for BPF links (**struct - bpf_link**) for each BPF program within BPF object. When - requested, supported BPF programs will be automatically - attached and resulting BPF links stored for further use by - user in pre-allocated fields in skeleton struct. For BPF - programs that can't be automatically attached by libbpf, - user can attach them manually, but store resulting BPF link - in per-program link field. All such set up links will be - automatically destroyed on BPF skeleton destruction. This - eliminates the need for users to manage links manually and - rely on libbpf support to detach programs and free up - resources. - - Another facility provided by BPF skeleton is an interface to - global variables of all supported kinds: mutable, read-only, - as well as extern ones. This interface allows to pre-setup - initial values of variables before BPF object is loaded and - verified by kernel. For non-read-only variables, the same - interface can be used to fetch values of global variables on - userspace side, even if they are modified by BPF code. - - During skeleton generation, contents of source BPF object - *FILE* is embedded within generated code and is thus not - necessary to keep around. This ensures skeleton and BPF - object file are matching 1-to-1 and always stay in sync. - Generated code is dual-licensed under LGPL-2.1 and - BSD-2-Clause licenses. - - It is a design goal and guarantee that skeleton interfaces - are interoperable with generic libbpf APIs. User should - always be able to use skeleton API to create and load BPF - object, and later use libbpf APIs to keep working with - specific maps, programs, etc. - - As part of skeleton, few custom functions are generated. - Each of them is prefixed with object name, derived from - object file name. I.e., if BPF object file name is - **example.o**, BPF object name will be **example**. The - following custom functions are provided in such case: - - - **example__open** and **example__open_opts**. - These functions are used to instantiate skeleton. It - corresponds to libbpf's **bpf_object__open**\ () API. - **_opts** variants accepts extra **bpf_object_open_opts** - options. - - - **example__load**. - This function creates maps, loads and verifies BPF - programs, initializes global data maps. It corresponds to - libppf's **bpf_object__load**\ () API. - - - **example__open_and_load** combines **example__open** and - **example__load** invocations in one commonly used - operation. - - - **example__attach** and **example__detach** - This pair of functions allow to attach and detach, - correspondingly, already loaded BPF object. Only BPF - programs of types supported by libbpf for auto-attachment - will be auto-attached and their corresponding BPF links - instantiated. For other BPF programs, user can manually - create a BPF link and assign it to corresponding fields in - skeleton struct. **example__detach** will detach both - links created automatically, as well as those populated by - user manually. - - - **example__destroy** - Detach and unload BPF programs, free up all the resources - used by skeleton and BPF object. - - If BPF object has global variables, corresponding structs - with memory layout corresponding to global data data section - layout will be created. Currently supported ones are: .data, - .bss, .rodata, and .extern structs/data sections. These - data sections/structs can be used to set up initial values of - variables, if set before **example__load**. Afterwards, if - target kernel supports memory-mapped BPF arrays, same - structs can be used to fetch and update (non-read-only) - data from userspace, with same simplicity as for BPF side. - - **bpftool gen help** - Print short help message. - -OPTIONS -======= - -h, --help - Print short generic help message (similar to **bpftool help**). - - -V, --version - Print version number (similar to **bpftool version**). - - -j, --json - Generate JSON output. For commands that cannot produce JSON, - this option has no effect. - - -p, --pretty - Generate human-readable JSON output. Implies **-j**. - - -d, --debug - Print all logs available from libbpf, including debug-level - information. - -EXAMPLES -======== -**$ cat example.c** -:: - - #include - #include - #include - #include "bpf_helpers.h" - - const volatile int param1 = 42; - bool global_flag = true; - struct { int x; } data = {}; - - struct { - __uint(type, BPF_MAP_TYPE_HASH); - __uint(max_entries, 128); - __type(key, int); - __type(value, long); - } my_map SEC(".maps"); - - SEC("raw_tp/sys_enter") - int handle_sys_enter(struct pt_regs *ctx) - { - static long my_static_var; - if (global_flag) - my_static_var++; - else - data.x += param1; - return 0; - } - - SEC("raw_tp/sys_exit") - int handle_sys_exit(struct pt_regs *ctx) - { - int zero = 0; - bpf_map_lookup_elem(&my_map, &zero); - return 0; - } - -This is example BPF application with two BPF programs and a mix of BPF maps -and global variables. - -**$ bpftool gen skeleton example.o** -:: - - /* SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) */ - - /* THIS FILE IS AUTOGENERATED! */ - #ifndef __EXAMPLE_SKEL_H__ - #define __EXAMPLE_SKEL_H__ - - #include - #include - - struct example { - struct bpf_object_skeleton *skeleton; - struct bpf_object *obj; - struct { - struct bpf_map *rodata; - struct bpf_map *data; - struct bpf_map *bss; - struct bpf_map *my_map; - } maps; - struct { - struct bpf_program *handle_sys_enter; - struct bpf_program *handle_sys_exit; - } progs; - struct { - struct bpf_link *handle_sys_enter; - struct bpf_link *handle_sys_exit; - } links; - struct example__bss { - struct { - int x; - } data; - } *bss; - struct example__data { - _Bool global_flag; - long int handle_sys_enter_my_static_var; - } *data; - struct example__rodata { - int param1; - } *rodata; - }; - - static void example__destroy(struct example *obj); - static inline struct example *example__open_opts( - const struct bpf_object_open_opts *opts); - static inline struct example *example__open(); - static inline int example__load(struct example *obj); - static inline struct example *example__open_and_load(); - static inline int example__attach(struct example *obj); - static inline void example__detach(struct example *obj); - - #endif /* __EXAMPLE_SKEL_H__ */ - -**$ cat example_user.c** -:: - - #include "example.skel.h" - - int main() - { - struct example *skel; - int err = 0; - - skel = example__open(); - if (!skel) - goto cleanup; - - skel->rodata->param1 = 128; - - err = example__load(skel); - if (err) - goto cleanup; - - err = example__attach(skel); - if (err) - goto cleanup; - - /* all libbpf APIs are usable */ - printf("my_map name: %s\n", bpf_map__name(skel->maps.my_map)); - printf("sys_enter prog FD: %d\n", - bpf_program__fd(skel->progs.handle_sys_enter)); - - /* detach and re-attach sys_exit program */ - bpf_link__destroy(skel->links.handle_sys_exit); - skel->links.handle_sys_exit = - bpf_program__attach(skel->progs.handle_sys_exit); - - printf("my_static_var: %ld\n", - skel->bss->handle_sys_enter_my_static_var); - - cleanup: - example__destroy(skel); - return err; - } - -**# ./example_user** -:: - - my_map name: my_map - sys_enter prog FD: 8 - my_static_var: 7 - -This is a stripped-out version of skeleton generated for above example code. - -SEE ALSO -======== - **bpf**\ (2), - **bpf-helpers**\ (7), - **bpftool**\ (8), - **bpftool-btf**\ (8), - **bpftool-cgroup**\ (8), - **bpftool-feature**\ (8), - **bpftool-iter**\ (8), - **bpftool-link**\ (8), - **bpftool-map**\ (8), - **bpftool-net**\ (8), - **bpftool-perf**\ (8), - **bpftool-prog**\ (8), - **bpftool-struct_ops**\ (8) diff --git a/tools/bpf/bpftool/Documentation/bpftool-map.rst b/tools/bpf/bpftool/Documentation/bpftool-map.rst index 3bf86b5c9f5b..1c0f7146aab0 100644 --- a/tools/bpf/bpftool/Documentation/bpftool-map.rst +++ b/tools/bpf/bpftool/Documentation/bpftool-map.rst @@ -21,7 +21,7 @@ SYNOPSIS MAP COMMANDS ============= -| **bpftool** **map** { **show** | **list** } [*MAP*] +| **bpftool** **map { show | list }** [*MAP*] | **bpftool** **map create** *FILE* **type** *TYPE* **key** *KEY_SIZE* **value** *VALUE_SIZE* \ | **entries** *MAX_ENTRIES* **name** *NAME* [**flags** *FLAGS*] [**dev** *NAME*] | **bpftool** **map dump** *MAP* @@ -49,7 +49,7 @@ MAP COMMANDS | | **lru_percpu_hash** | **lpm_trie** | **array_of_maps** | **hash_of_maps** | | **devmap** | **devmap_hash** | **sockmap** | **cpumap** | **xskmap** | **sockhash** | | **cgroup_storage** | **reuseport_sockarray** | **percpu_cgroup_storage** -| | **queue** | **stack** | **sk_storage** | **struct_ops** | **ringbuf** | **inode_storage** } +| | **queue** | **stack** } DESCRIPTION =========== @@ -65,13 +65,6 @@ DESCRIPTION Create a new map with given parameters and pin it to *bpffs* as *FILE*. - *FLAGS* should be an integer which is the combination of - desired flags, e.g. 1024 for **BPF_F_MMAPABLE** (see bpf.h - UAPI header for existing flags). - - Keyword **dev** expects a network interface name, and is used - to request hardware offload for the map. - **bpftool map dump** *MAP* Dump all entries in a given *MAP*. @@ -83,7 +76,7 @@ DESCRIPTION exists; **noexist** update only if entry doesn't exist. If the **hex** keyword is provided in front of the bytes - sequence, the bytes are parsed as hexadecimal values, even if + sequence, the bytes are parsed as hexadeximal values, even if no "0x" prefix is added. If the keyword is not provided, then the bytes are parsed as decimal values, unless a "0x" prefix (for hexadecimal) or a "0" prefix (for octal) is provided. @@ -105,10 +98,10 @@ DESCRIPTION extensions of *bpffs*. **bpftool** **map event_pipe** *MAP* [**cpu** *N* **index** *M*] - Read events from a **BPF_MAP_TYPE_PERF_EVENT_ARRAY** map. + Read events from a BPF_MAP_TYPE_PERF_EVENT_ARRAY map. Install perf rings into a perf event array map and dump - output of any **bpf_perf_event_output**\ () call in the kernel. + output of any bpf_perf_event_output() call in the kernel. By default read the number of CPUs on the system and install perf ring for each CPU in the corresponding index in the array. @@ -121,24 +114,24 @@ DESCRIPTION receiving events if it installed its rings earlier. **bpftool map peek** *MAP* - Peek next value in the queue or stack. + Peek next **value** in the queue or stack. **bpftool map push** *MAP* **value** *VALUE* - Push *VALUE* onto the stack. + Push **value** onto the stack. **bpftool map pop** *MAP* - Pop and print value from the stack. + Pop and print **value** from the stack. **bpftool map enqueue** *MAP* **value** *VALUE* - Enqueue *VALUE* into the queue. + Enqueue **value** into the queue. **bpftool map dequeue** *MAP* - Dequeue and print value from the queue. + Dequeue and print **value** from the queue. **bpftool map freeze** *MAP* Freeze the map as read-only from user space. Entries from a frozen map can not longer be updated or deleted with the - **bpf**\ () system call. This operation is not reversible, + **bpf\ ()** system call. This operation is not reversible, and the map remains immutable from user space until its destruction. However, read and write permissions for BPF programs to the map remain unchanged. @@ -274,13 +267,9 @@ SEE ALSO **bpf**\ (2), **bpf-helpers**\ (7), **bpftool**\ (8), - **bpftool-btf**\ (8), + **bpftool-prog**\ (8), **bpftool-cgroup**\ (8), **bpftool-feature**\ (8), - **bpftool-gen**\ (8), - **bpftool-iter**\ (8), - **bpftool-link**\ (8), **bpftool-net**\ (8), **bpftool-perf**\ (8), - **bpftool-prog**\ (8), - **bpftool-struct_ops**\ (8) + **bpftool-btf**\ (8) diff --git a/tools/bpf/bpftool/Documentation/bpftool-net.rst b/tools/bpf/bpftool/Documentation/bpftool-net.rst index aa7450736179..8651b00b81ea 100644 --- a/tools/bpf/bpftool/Documentation/bpftool-net.rst +++ b/tools/bpf/bpftool/Documentation/bpftool-net.rst @@ -20,7 +20,7 @@ SYNOPSIS NET COMMANDS ============ -| **bpftool** **net** { **show** | **list** } [ **dev** *NAME* ] +| **bpftool** **net { show | list }** [ **dev** *NAME* ] | **bpftool** **net attach** *ATTACH_TYPE* *PROG* **dev** *NAME* [ **overwrite** ] | **bpftool** **net detach** *ATTACH_TYPE* **dev** *NAME* | **bpftool** **net help** @@ -194,13 +194,9 @@ SEE ALSO **bpf**\ (2), **bpf-helpers**\ (7), **bpftool**\ (8), - **bpftool-btf**\ (8), + **bpftool-prog**\ (8), + **bpftool-map**\ (8), **bpftool-cgroup**\ (8), **bpftool-feature**\ (8), - **bpftool-gen**\ (8), - **bpftool-iter**\ (8), - **bpftool-link**\ (8), - **bpftool-map**\ (8), **bpftool-perf**\ (8), - **bpftool-prog**\ (8), - **bpftool-struct_ops**\ (8) + **bpftool-btf**\ (8) diff --git a/tools/bpf/bpftool/Documentation/bpftool-perf.rst b/tools/bpf/bpftool/Documentation/bpftool-perf.rst index 9c592b7c6775..e252bd0bc434 100644 --- a/tools/bpf/bpftool/Documentation/bpftool-perf.rst +++ b/tools/bpf/bpftool/Documentation/bpftool-perf.rst @@ -20,7 +20,7 @@ SYNOPSIS PERF COMMANDS ============= -| **bpftool** **perf** { **show** | **list** } +| **bpftool** **perf { show | list }** | **bpftool** **perf help** DESCRIPTION @@ -85,13 +85,9 @@ SEE ALSO **bpf**\ (2), **bpf-helpers**\ (7), **bpftool**\ (8), - **bpftool-btf**\ (8), + **bpftool-prog**\ (8), + **bpftool-map**\ (8), **bpftool-cgroup**\ (8), **bpftool-feature**\ (8), - **bpftool-gen**\ (8), - **bpftool-iter**\ (8), - **bpftool-link**\ (8), - **bpftool-map**\ (8), **bpftool-net**\ (8), - **bpftool-prog**\ (8), - **bpftool-struct_ops**\ (8) + **bpftool-btf**\ (8) diff --git a/tools/bpf/bpftool/Documentation/bpftool-prog.rst b/tools/bpf/bpftool/Documentation/bpftool-prog.rst index fc008f3c8ec2..7a374b3c851d 100644 --- a/tools/bpf/bpftool/Documentation/bpftool-prog.rst +++ b/tools/bpf/bpftool/Documentation/bpftool-prog.rst @@ -21,16 +21,15 @@ SYNOPSIS PROG COMMANDS ============= -| **bpftool** **prog** { **show** | **list** } [*PROG*] +| **bpftool** **prog { show | list }** [*PROG*] | **bpftool** **prog dump xlated** *PROG* [{**file** *FILE* | **opcodes** | **visual** | **linum**}] | **bpftool** **prog dump jited** *PROG* [{**file** *FILE* | **opcodes** | **linum**}] | **bpftool** **prog pin** *PROG* *FILE* -| **bpftool** **prog** { **load** | **loadall** } *OBJ* *PATH* [**type** *TYPE*] [**map** {**idx** *IDX* | **name** *NAME*} *MAP*] [**dev** *NAME*] [**pinmaps** *MAP_DIR*] +| **bpftool** **prog { load | loadall }** *OBJ* *PATH* [**type** *TYPE*] [**map** {**idx** *IDX* | **name** *NAME*} *MAP*] [**dev** *NAME*] [**pinmaps** *MAP_DIR*] | **bpftool** **prog attach** *PROG* *ATTACH_TYPE* [*MAP*] | **bpftool** **prog detach** *PROG* *ATTACH_TYPE* [*MAP*] | **bpftool** **prog tracelog** | **bpftool** **prog run** *PROG* **data_in** *FILE* [**data_out** *FILE* [**data_size_out** *L*]] [**ctx_in** *FILE* [**ctx_out** *FILE* [**ctx_size_out** *M*]]] [**repeat** *N*] -| **bpftool** **prog profile** *PROG* [**duration** *DURATION*] *METRICs* | **bpftool** **prog help** | | *MAP* := { **id** *MAP_ID* | **pinned** *FILE* } @@ -48,9 +47,6 @@ PROG COMMANDS | *ATTACH_TYPE* := { | **msg_verdict** | **stream_verdict** | **stream_parser** | **flow_dissector** | } -| *METRICs* := { -| **cycles** | **instructions** | **l1d_loads** | **llc_misses** -| } DESCRIPTION @@ -146,7 +142,7 @@ DESCRIPTION **bpftool prog tracelog** Dump the trace pipe of the system to the console (stdout). Hit to stop printing. BPF programs can write to this - trace pipe at runtime with the **bpf_trace_printk**\ () helper. + trace pipe at runtime with the **bpf_trace_printk()** helper. This should be used only for debugging purposes. For streaming data from BPF programs to user space, one can use perf events (see also **bpftool-map**\ (8)). @@ -184,12 +180,6 @@ DESCRIPTION not all of them can take the **ctx_in**/**ctx_out** arguments. bpftool does not perform checks on program types. - **bpftool prog profile** *PROG* [**duration** *DURATION*] *METRICs* - Profile *METRICs* for bpf program *PROG* for *DURATION* - seconds or until user hits . *DURATION* is optional. - If *DURATION* is not specified, the profiling will run up to - **UINT_MAX** seconds. - **bpftool prog help** Print short help message. @@ -258,7 +248,7 @@ EXAMPLES | | **# bpftool prog dump xlated id 10 file /tmp/t** -| **$ ls -l /tmp/t** +| **# ls -l /tmp/t** :: @@ -312,28 +302,14 @@ EXAMPLES **# rm /sys/fs/bpf/xdp1** -| -| **# bpftool prog profile id 337 duration 10 cycles instructions llc_misses** - -:: - - 51397 run_cnt - 40176203 cycles (83.05%) - 42518139 instructions # 1.06 insns per cycle (83.39%) - 123 llc_misses # 2.89 LLC misses per million insns (83.15%) - SEE ALSO ======== **bpf**\ (2), **bpf-helpers**\ (7), **bpftool**\ (8), - **bpftool-btf**\ (8), + **bpftool-map**\ (8), **bpftool-cgroup**\ (8), **bpftool-feature**\ (8), - **bpftool-gen**\ (8), - **bpftool-iter**\ (8), - **bpftool-link**\ (8), - **bpftool-map**\ (8), **bpftool-net**\ (8), **bpftool-perf**\ (8), - **bpftool-struct_ops**\ (8) + **bpftool-btf**\ (8) diff --git a/tools/bpf/bpftool/Documentation/bpftool.rst b/tools/bpf/bpftool/Documentation/bpftool.rst index 420d4d5df8b6..6a9c52ef84a9 100644 --- a/tools/bpf/bpftool/Documentation/bpftool.rst +++ b/tools/bpf/bpftool/Documentation/bpftool.rst @@ -75,14 +75,10 @@ SEE ALSO ======== **bpf**\ (2), **bpf-helpers**\ (7), - **bpftool-btf**\ (8), + **bpftool-prog**\ (8), + **bpftool-map**\ (8), **bpftool-cgroup**\ (8), **bpftool-feature**\ (8), - **bpftool-gen**\ (8), - **bpftool-iter**\ (8), - **bpftool-link**\ (8), - **bpftool-map**\ (8), **bpftool-net**\ (8), **bpftool-perf**\ (8), - **bpftool-prog**\ (8), - **bpftool-struct_ops**\ (8) + **bpftool-btf**\ (8) diff --git a/tools/bpf/bpftool/bash-completion/bpftool b/tools/bpf/bpftool/bash-completion/bpftool index 44f2cdb6b0b9..70493a6da206 100644 --- a/tools/bpf/bpftool/bash-completion/bpftool +++ b/tools/bpf/bpftool/bash-completion/bpftool @@ -491,8 +491,7 @@ _bpftool() lru_percpu_hash lpm_trie array_of_maps \ hash_of_maps devmap devmap_hash sockmap cpumap \ xskmap sockhash cgroup_storage reuseport_sockarray \ - percpu_cgroup_storage queue stack sk_storage \ - struct_ops inode_storage' -- \ + percpu_cgroup_storage queue stack' -- \ "$cur" ) ) return 0 ;; diff --git a/tools/bpf/bpftool/map.c b/tools/bpf/bpftool/map.c index 70185ea108a9..de61d73b9030 100644 --- a/tools/bpf/bpftool/map.c +++ b/tools/bpf/bpftool/map.c @@ -48,9 +48,6 @@ const char * const map_type_name[] = { [BPF_MAP_TYPE_QUEUE] = "queue", [BPF_MAP_TYPE_STACK] = "stack", [BPF_MAP_TYPE_SK_STORAGE] = "sk_storage", - [BPF_MAP_TYPE_STRUCT_OPS] = "struct_ops", - [BPF_MAP_TYPE_RINGBUF] = "ringbuf", - [BPF_MAP_TYPE_INODE_STORAGE] = "inode_storage", }; const size_t map_type_name_size = ARRAY_SIZE(map_type_name); @@ -1330,8 +1327,7 @@ static int do_help(int argc, char **argv) " percpu_array | stack_trace | cgroup_array | lru_hash |\n" " lru_percpu_hash | lpm_trie | array_of_maps | hash_of_maps |\n" " devmap | devmap_hash | sockmap | cpumap | xskmap | sockhash |\n" - " cgroup_storage | reuseport_sockarray | percpu_cgroup_storage |\n" - " queue | stack | sk_storage | struct_ops | ringbuf | inode_storage }\n" + " cgroup_storage | reuseport_sockarray | percpu_cgroup_storage }\n" " " HELP_SPEC_OPTIONS "\n" "", bin_name, argv[-2], bin_name, argv[-2], bin_name, argv[-2], diff --git a/tools/build/feature/Makefile b/tools/build/feature/Makefile index f5b7b1489e1f..8104e505efde 100644 --- a/tools/build/feature/Makefile +++ b/tools/build/feature/Makefile @@ -258,10 +258,10 @@ $(OUTPUT)test-sync-compare-and-swap.bin: $(BUILD) $(OUTPUT)test-compile-32.bin: - $(CC) -m32 -Wall -Werror -o $@ test-compile.c + $(CC) -m32 -o $@ test-compile.c $(OUTPUT)test-compile-x32.bin: - $(CC) -mx32 -Wall -Werror -o $@ test-compile.c + $(CC) -mx32 -o $@ test-compile.c $(OUTPUT)test-zlib.bin: $(BUILD) -lz diff --git a/tools/include/uapi/linux/bpf.h b/tools/include/uapi/linux/bpf.h index b4a1cbd06fcc..53a3b7e737b3 100644 --- a/tools/include/uapi/linux/bpf.h +++ b/tools/include/uapi/linux/bpf.h @@ -73,7 +73,7 @@ struct bpf_insn { /* Key of an a BPF_MAP_TYPE_LPM_TRIE entry */ struct bpf_lpm_trie_key { __u32 prefixlen; /* up to 32 for AF_INET, 128 for AF_INET6 */ - __u8 data[]; /* Arbitrary size */ + __u8 data[0]; /* Arbitrary size */ }; struct bpf_cgroup_storage_key { @@ -107,16 +107,6 @@ enum bpf_cmd { BPF_MAP_LOOKUP_AND_DELETE_ELEM, BPF_MAP_FREEZE, BPF_BTF_GET_NEXT_ID, - BPF_MAP_LOOKUP_BATCH, - BPF_MAP_LOOKUP_AND_DELETE_BATCH, - BPF_MAP_UPDATE_BATCH, - BPF_MAP_DELETE_BATCH, - BPF_LINK_CREATE, - BPF_LINK_GET_FD_BY_ID, - BPF_LINK_GET_NEXT_ID, - BPF_ENABLE_STATS, - BPF_ITER_CREATE, - BPF_PROG_BIND_MAP, }; enum bpf_map_type { @@ -146,9 +136,6 @@ enum bpf_map_type { BPF_MAP_TYPE_STACK, BPF_MAP_TYPE_SK_STORAGE, BPF_MAP_TYPE_DEVMAP_HASH, - BPF_MAP_TYPE_STRUCT_OPS, - BPF_MAP_TYPE_RINGBUF, - BPF_MAP_TYPE_INODE_STORAGE, }; /* Note that tracing related programs such as @@ -186,9 +173,6 @@ enum bpf_prog_type { BPF_PROG_TYPE_CGROUP_SYSCTL, BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE, BPF_PROG_TYPE_CGROUP_SOCKOPT, - BPF_PROG_TYPE_STRUCT_OPS, - BPF_PROG_TYPE_LSM, - BPF_PROG_TYPE_SK_LOOKUP, }; enum bpf_attach_type { @@ -215,43 +199,11 @@ enum bpf_attach_type { BPF_CGROUP_UDP6_RECVMSG, BPF_CGROUP_GETSOCKOPT, BPF_CGROUP_SETSOCKOPT, - BPF_TRACE_RAW_TP, - BPF_TRACE_FENTRY, - BPF_TRACE_FEXIT, - BPF_MODIFY_RETURN, - BPF_LSM_MAC, - BPF_TRACE_ITER, - BPF_CGROUP_INET4_GETPEERNAME, - BPF_CGROUP_INET6_GETPEERNAME, - BPF_CGROUP_INET4_GETSOCKNAME, - BPF_CGROUP_INET6_GETSOCKNAME, - BPF_XDP_DEVMAP, - BPF_CGROUP_INET_SOCK_RELEASE, - BPF_XDP_CPUMAP, - BPF_SK_LOOKUP, __MAX_BPF_ATTACH_TYPE }; #define MAX_BPF_ATTACH_TYPE __MAX_BPF_ATTACH_TYPE -enum bpf_link_type { - BPF_LINK_TYPE_UNSPEC = 0, - BPF_LINK_TYPE_RAW_TRACEPOINT = 1, - BPF_LINK_TYPE_TRACING = 2, - BPF_LINK_TYPE_CGROUP = 3, - BPF_LINK_TYPE_ITER = 4, - BPF_LINK_TYPE_NETNS = 5, - - MAX_BPF_LINK_TYPE, -}; - -enum bpf_iter_link_info { - BPF_ITER_LINK_UNSPEC = 0, - BPF_ITER_LINK_MAP_FD = 1, - - MAX_BPF_ITER_LINK_INFO, -}; - /* cgroup-bpf attach flags used in BPF_PROG_ATTACH command * * NONE(default): No further bpf programs allowed in the subtree. @@ -275,11 +227,6 @@ enum bpf_iter_link_info { * When children program makes decision (like picking TCP CA or sock bind) * parent program has a chance to override it. * - * With BPF_F_ALLOW_MULTI a new program is added to the end of the list of - * programs for a cgroup. Though it's possible to replace an old program at - * any position by also specifying BPF_F_REPLACE flag and position itself in - * replace_bpf_fd attribute. Old program at this position will be released. - * * A cgroup with MULTI or OVERRIDE flag allows any attach flags in sub-cgroups. * A cgroup with NONE doesn't allow any programs in sub-cgroups. * Ex1: @@ -298,7 +245,6 @@ enum bpf_iter_link_info { */ #define BPF_F_ALLOW_OVERRIDE (1U << 0) #define BPF_F_ALLOW_MULTI (1U << 1) -#define BPF_F_REPLACE (1U << 2) /* If BPF_F_STRICT_ALIGNMENT is used in BPF_PROG_LOAD command, the * verifier will perform strict alignment checking as if the kernel @@ -342,45 +288,19 @@ enum bpf_iter_link_info { /* The verifier internal test flag. Behavior is undefined */ #define BPF_F_TEST_STATE_FREQ (1U << 3) -/* If BPF_F_SLEEPABLE is used in BPF_PROG_LOAD command, the verifier will - * restrict map and helper usage for such programs. Sleepable BPF programs can - * only be attached to hooks where kernel execution context allows sleeping. - * Such programs are allowed to use helpers that may sleep like - * bpf_copy_from_user(). - */ -#define BPF_F_SLEEPABLE (1U << 4) - /* When BPF ldimm64's insn[0].src_reg != 0 then this can have - * the following extensions: + * two extensions: * - * insn[0].src_reg: BPF_PSEUDO_MAP_FD - * insn[0].imm: map fd - * insn[1].imm: 0 - * insn[0].off: 0 - * insn[1].off: 0 - * ldimm64 rewrite: address of map - * verifier type: CONST_PTR_TO_MAP + * insn[0].src_reg: BPF_PSEUDO_MAP_FD BPF_PSEUDO_MAP_VALUE + * insn[0].imm: map fd map fd + * insn[1].imm: 0 offset into value + * insn[0].off: 0 0 + * insn[1].off: 0 0 + * ldimm64 rewrite: address of map address of map[0]+offset + * verifier type: CONST_PTR_TO_MAP PTR_TO_MAP_VALUE */ #define BPF_PSEUDO_MAP_FD 1 -/* insn[0].src_reg: BPF_PSEUDO_MAP_VALUE - * insn[0].imm: map fd - * insn[1].imm: offset into value - * insn[0].off: 0 - * insn[1].off: 0 - * ldimm64 rewrite: address of map[0]+offset - * verifier type: PTR_TO_MAP_VALUE - */ #define BPF_PSEUDO_MAP_VALUE 2 -/* insn[0].src_reg: BPF_PSEUDO_BTF_ID - * insn[0].imm: kernel btd id of VAR - * insn[1].imm: 0 - * insn[0].off: 0 - * insn[1].off: 0 - * ldimm64 rewrite: address of the kernel variable - * verifier type: PTR_TO_BTF_ID or PTR_TO_MEM, depending on whether the var - * is struct/union. - */ -#define BPF_PSEUDO_BTF_ID 3 /* when bpf_call->src_reg == BPF_PSEUDO_CALL, bpf_call->imm == pc-relative * offset to another bpf function @@ -388,72 +308,45 @@ enum bpf_iter_link_info { #define BPF_PSEUDO_CALL 1 /* flags for BPF_MAP_UPDATE_ELEM command */ -enum { - BPF_ANY = 0, /* create new element or update existing */ - BPF_NOEXIST = 1, /* create new element if it didn't exist */ - BPF_EXIST = 2, /* update existing element */ - BPF_F_LOCK = 4, /* spin_lock-ed map_lookup/map_update */ -}; +#define BPF_ANY 0 /* create new element or update existing */ +#define BPF_NOEXIST 1 /* create new element if it didn't exist */ +#define BPF_EXIST 2 /* update existing element */ +#define BPF_F_LOCK 4 /* spin_lock-ed map_lookup/map_update */ /* flags for BPF_MAP_CREATE command */ -enum { - BPF_F_NO_PREALLOC = (1U << 0), +#define BPF_F_NO_PREALLOC (1U << 0) /* Instead of having one common LRU list in the * BPF_MAP_TYPE_LRU_[PERCPU_]HASH map, use a percpu LRU list * which can scale and perform better. * Note, the LRU nodes (including free nodes) cannot be moved * across different LRU lists. */ - BPF_F_NO_COMMON_LRU = (1U << 1), +#define BPF_F_NO_COMMON_LRU (1U << 1) /* Specify numa node during map creation */ - BPF_F_NUMA_NODE = (1U << 2), +#define BPF_F_NUMA_NODE (1U << 2) + +#define BPF_OBJ_NAME_LEN 16U /* Flags for accessing BPF object from syscall side. */ - BPF_F_RDONLY = (1U << 3), - BPF_F_WRONLY = (1U << 4), +#define BPF_F_RDONLY (1U << 3) +#define BPF_F_WRONLY (1U << 4) /* Flag for stack_map, store build_id+offset instead of pointer */ - BPF_F_STACK_BUILD_ID = (1U << 5), +#define BPF_F_STACK_BUILD_ID (1U << 5) /* Zero-initialize hash function seed. This should only be used for testing. */ - BPF_F_ZERO_SEED = (1U << 6), +#define BPF_F_ZERO_SEED (1U << 6) /* Flags for accessing BPF object from program side. */ - BPF_F_RDONLY_PROG = (1U << 7), - BPF_F_WRONLY_PROG = (1U << 8), +#define BPF_F_RDONLY_PROG (1U << 7) +#define BPF_F_WRONLY_PROG (1U << 8) /* Clone map from listener for newly accepted socket */ - BPF_F_CLONE = (1U << 9), +#define BPF_F_CLONE (1U << 9) -/* Enable memory-mapping BPF map */ - BPF_F_MMAPABLE = (1U << 10), - -/* Share perf_event among processes */ - BPF_F_PRESERVE_ELEMS = (1U << 11), - -/* Create a map that is suitable to be an inner map with dynamic max entries */ - BPF_F_INNER_MAP = (1U << 12), -}; - -/* Flags for BPF_PROG_QUERY. */ - -/* Query effective (directly attached + inherited from ancestor cgroups) - * programs that will be executed for events within a cgroup. - * attach_flags with this flag are returned only for directly attached programs. - */ +/* flags for BPF_PROG_QUERY */ #define BPF_F_QUERY_EFFECTIVE (1U << 0) -/* Flags for BPF_PROG_TEST_RUN */ - -/* If set, run the test on the cpu specified by bpf_attr.test.cpu */ -#define BPF_F_TEST_RUN_ON_CPU (1U << 0) - -/* type for BPF_ENABLE_STATS */ -enum bpf_stats_type { - /* enabled run_time_ns and run_cnt */ - BPF_STATS_RUN_TIME = 0, -}; - enum bpf_stack_build_id_status { /* user space need an empty entry to identify end of a trace */ BPF_STACK_BUILD_ID_EMPTY = 0, @@ -473,8 +366,6 @@ struct bpf_stack_build_id { }; }; -#define BPF_OBJ_NAME_LEN 16U - union bpf_attr { struct { /* anonymous struct used by BPF_MAP_CREATE command */ __u32 map_type; /* one of enum bpf_map_type */ @@ -493,10 +384,6 @@ union bpf_attr { __u32 btf_fd; /* fd pointing to a BTF type data */ __u32 btf_key_type_id; /* BTF type_id of the key */ __u32 btf_value_type_id; /* BTF type_id of the value */ - __u32 btf_vmlinux_value_type_id;/* BTF type_id of a kernel- - * struct stored as the - * map value - */ }; struct { /* anonymous struct used by BPF_MAP_*_ELEM commands */ @@ -509,23 +396,6 @@ union bpf_attr { __u64 flags; }; - struct { /* struct used by BPF_MAP_*_BATCH commands */ - __aligned_u64 in_batch; /* start batch, - * NULL to start from beginning - */ - __aligned_u64 out_batch; /* output: next start batch */ - __aligned_u64 keys; - __aligned_u64 values; - __u32 count; /* input/output: - * input: # of key/value - * elements - * output: # of filled elements - */ - __u32 map_fd; - __u64 elem_flags; - __u64 flags; - } batch; - struct { /* anonymous struct used by BPF_PROG_LOAD command */ __u32 prog_type; /* one of enum bpf_prog_type */ __u32 insn_cnt; @@ -550,7 +420,6 @@ union bpf_attr { __u32 line_info_rec_size; /* userspace bpf_line_info size */ __aligned_u64 line_info; /* line info */ __u32 line_info_cnt; /* number of bpf_line_info records */ - __u32 attach_btf_id; /* in-kernel BTF type id to attach to */ }; struct { /* anonymous struct used by BPF_OBJ_* commands */ @@ -564,10 +433,6 @@ union bpf_attr { __u32 attach_bpf_fd; /* eBPF program to attach */ __u32 attach_type; __u32 attach_flags; - __u32 replace_bpf_fd; /* previously attached eBPF - * program to replace if - * BPF_F_REPLACE is used - */ }; struct { /* anonymous struct used by BPF_PROG_TEST_RUN command */ @@ -589,8 +454,6 @@ union bpf_attr { */ __aligned_u64 ctx_in; __aligned_u64 ctx_out; - __u32 flags; - __u32 cpu; } test; struct { /* anonymous struct used by BPF_*_GET_*_ID */ @@ -599,7 +462,6 @@ union bpf_attr { __u32 prog_id; __u32 map_id; __u32 btf_id; - __u32 link_id; }; __u32 next_id; __u32 open_flags; @@ -620,7 +482,7 @@ union bpf_attr { __u32 prog_cnt; } query; - struct { /* anonymous struct used by BPF_RAW_TRACEPOINT_OPEN command */ + struct { __u64 name; __u32 prog_fd; } raw_tracepoint; @@ -648,36 +510,6 @@ union bpf_attr { __u64 probe_offset; /* output: probe_offset */ __u64 probe_addr; /* output: probe_addr */ } task_fd_query; - - struct { /* struct used by BPF_LINK_CREATE command */ - __u32 prog_fd; /* eBPF program to attach */ - __u32 target_fd; /* object to attach to */ - __u32 attach_type; /* attach type */ - __u32 flags; /* extra flags */ - union { - __u32 target_btf_id; /* btf_id of target to attach to */ - struct { - __aligned_u64 iter_info; /* extra bpf_iter_link_info */ - __u32 iter_info_len; /* iter_info length */ - }; - }; - } link_create; - - struct { /* struct used by BPF_ENABLE_STATS command */ - __u32 type; - } enable_stats; - - struct { /* struct used by BPF_ITER_CREATE command */ - __u32 link_fd; - __u32 flags; - } iter_create; - - struct { /* struct used by BPF_PROG_BIND_MAP command */ - __u32 prog_fd; - __u32 map_fd; - __u32 flags; /* extra flags */ - } prog_bind_map; - } __attribute__((aligned(8))); /* The description below is an attempt at providing documentation to eBPF @@ -704,7 +536,7 @@ union bpf_attr { * Map value associated to *key*, or **NULL** if no entry was * found. * - * long bpf_map_update_elem(struct bpf_map *map, const void *key, const void *value, u64 flags) + * int bpf_map_update_elem(struct bpf_map *map, const void *key, const void *value, u64 flags) * Description * Add or update the value of the entry associated to *key* in * *map* with *value*. *flags* is one of: @@ -722,19 +554,16 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_map_delete_elem(struct bpf_map *map, const void *key) + * int bpf_map_delete_elem(struct bpf_map *map, const void *key) * Description * Delete entry with *key* from *map*. * Return * 0 on success, or a negative error in case of failure. * - * long bpf_probe_read(void *dst, u32 size, const void *unsafe_ptr) + * int bpf_probe_read(void *dst, u32 size, const void *src) * Description * For tracing programs, safely attempt to read *size* bytes from - * kernel space address *unsafe_ptr* and store the data in *dst*. - * - * Generally, use bpf_probe_read_user() or bpf_probe_read_kernel() - * instead. + * address *src* and store the data in *dst*. * Return * 0 on success, or a negative error in case of failure. * @@ -746,7 +575,7 @@ union bpf_attr { * Return * Current *ktime*. * - * long bpf_trace_printk(const char *fmt, u32 fmt_size, ...) + * int bpf_trace_printk(const char *fmt, u32 fmt_size, ...) * Description * This helper is a "printk()-like" facility for debugging. It * prints a message defined by format *fmt* (of size *fmt_size*) @@ -796,7 +625,7 @@ union bpf_attr { * * Also, note that **bpf_trace_printk**\ () is slow, and should * only be used for debugging purposes. For this reason, a notice - * block (spanning several lines) is printed to kernel logs and + * bloc (spanning several lines) is printed to kernel logs and * states that the helper should not be used "for production use" * the first time this helper is used (or more precisely, when * **trace_printk**\ () buffers are allocated). For passing values @@ -826,7 +655,7 @@ union bpf_attr { * Return * The SMP id of the processor running the program. * - * long bpf_skb_store_bytes(struct sk_buff *skb, u32 offset, const void *from, u32 len, u64 flags) + * int bpf_skb_store_bytes(struct sk_buff *skb, u32 offset, const void *from, u32 len, u64 flags) * Description * Store *len* bytes from address *from* into the packet * associated to *skb*, at *offset*. *flags* are a combination of @@ -843,7 +672,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_l3_csum_replace(struct sk_buff *skb, u32 offset, u64 from, u64 to, u64 size) + * int bpf_l3_csum_replace(struct sk_buff *skb, u32 offset, u64 from, u64 to, u64 size) * Description * Recompute the layer 3 (e.g. IP) checksum for the packet * associated to *skb*. Computation is incremental, so the helper @@ -868,7 +697,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_l4_csum_replace(struct sk_buff *skb, u32 offset, u64 from, u64 to, u64 flags) + * int bpf_l4_csum_replace(struct sk_buff *skb, u32 offset, u64 from, u64 to, u64 flags) * Description * Recompute the layer 4 (e.g. TCP, UDP or ICMP) checksum for the * packet associated to *skb*. Computation is incremental, so the @@ -886,7 +715,6 @@ union bpf_attr { * for updates resulting in a null checksum the value is set to * **CSUM_MANGLED_0** instead. Flag **BPF_F_PSEUDO_HDR** indicates * the checksum is to be computed against a pseudo-header. - * Flag **BPF_F_IPV6** should be set for IPv6 packets. * * This helper works in combination with **bpf_csum_diff**\ (), * which does not update the checksum in-place, but offers more @@ -901,7 +729,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_tail_call(void *ctx, struct bpf_map *prog_array_map, u32 index) + * int bpf_tail_call(void *ctx, struct bpf_map *prog_array_map, u32 index) * Description * This special helper is used to trigger a "tail call", or in * other words, to jump into another eBPF program. The same stack @@ -932,7 +760,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_clone_redirect(struct sk_buff *skb, u32 ifindex, u64 flags) + * int bpf_clone_redirect(struct sk_buff *skb, u32 ifindex, u64 flags) * Description * Clone and redirect the packet associated to *skb* to another * net device of index *ifindex*. Both ingress and egress @@ -970,7 +798,7 @@ union bpf_attr { * A 64-bit integer containing the current GID and UID, and * created as such: *current_gid* **<< 32 \|** *current_uid*. * - * long bpf_get_current_comm(void *buf, u32 size_of_buf) + * int bpf_get_current_comm(char *buf, u32 size_of_buf) * Description * Copy the **comm** attribute of the current task into *buf* of * *size_of_buf*. The **comm** attribute contains the name of @@ -1007,7 +835,7 @@ union bpf_attr { * Return * The classid, or 0 for the default unconfigured classid. * - * long bpf_skb_vlan_push(struct sk_buff *skb, __be16 vlan_proto, u16 vlan_tci) + * int bpf_skb_vlan_push(struct sk_buff *skb, __be16 vlan_proto, u16 vlan_tci) * Description * Push a *vlan_tci* (VLAN tag control information) of protocol * *vlan_proto* to the packet associated to *skb*, then update @@ -1023,7 +851,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_vlan_pop(struct sk_buff *skb) + * int bpf_skb_vlan_pop(struct sk_buff *skb) * Description * Pop a VLAN header from the packet associated to *skb*. * @@ -1035,7 +863,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_get_tunnel_key(struct sk_buff *skb, struct bpf_tunnel_key *key, u32 size, u64 flags) + * int bpf_skb_get_tunnel_key(struct sk_buff *skb, struct bpf_tunnel_key *key, u32 size, u64 flags) * Description * Get tunnel metadata. This helper takes a pointer *key* to an * empty **struct bpf_tunnel_key** of **size**, that will be @@ -1065,14 +893,14 @@ union bpf_attr { * * int ret; * struct bpf_tunnel_key key = {}; - * + * * ret = bpf_skb_get_tunnel_key(skb, &key, sizeof(key), 0); * if (ret < 0) * return TC_ACT_SHOT; // drop packet - * + * * if (key.remote_ipv4 != 0x0a000001) * return TC_ACT_SHOT; // drop packet - * + * * return TC_ACT_OK; // accept packet * * This interface can also be used with all encapsulation devices @@ -1086,7 +914,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_set_tunnel_key(struct sk_buff *skb, struct bpf_tunnel_key *key, u32 size, u64 flags) + * int bpf_skb_set_tunnel_key(struct sk_buff *skb, struct bpf_tunnel_key *key, u32 size, u64 flags) * Description * Populate tunnel metadata for packet associated to *skb.* The * tunnel metadata is set to the contents of *key*, of *size*. The @@ -1152,7 +980,7 @@ union bpf_attr { * The value of the perf event counter read from the map, or a * negative error code in case of failure. * - * long bpf_redirect(u32 ifindex, u64 flags) + * int bpf_redirect(u32 ifindex, u64 flags) * Description * Redirect the packet to another net device of index *ifindex*. * This helper is somewhat similar to **bpf_clone_redirect**\ @@ -1166,9 +994,9 @@ union bpf_attr { * supports redirection to the egress interface, and accepts no * flag at all. * - * The same effect can also be attained with the more generic - * **bpf_redirect_map**\ (), which uses a BPF map to store the - * redirect target instead of providing it directly to the helper. + * The same effect can be attained with the more generic + * **bpf_redirect_map**\ (), which requires specific maps to be + * used but offers better performance. * Return * For XDP, the helper returns **XDP_REDIRECT** on success or * **XDP_ABORTED** on error. For other program types, the values @@ -1179,7 +1007,7 @@ union bpf_attr { * Description * Retrieve the realm or the route, that is to say the * **tclassid** field of the destination for the *skb*. The - * identifier retrieved is a user-provided tag, similar to the + * indentifier retrieved is a user-provided tag, similar to the * one used with the net_cls cgroup (see description for * **bpf_get_cgroup_classid**\ () helper), but here this tag is * held by a route (a destination entry), not by a task. @@ -1199,7 +1027,7 @@ union bpf_attr { * The realm of the route for the packet associated to *skb*, or 0 * if none was found. * - * long bpf_perf_event_output(void *ctx, struct bpf_map *map, u64 flags, void *data, u64 size) + * int bpf_perf_event_output(struct pt_regs *ctx, struct bpf_map *map, u64 flags, void *data, u64 size) * Description * Write raw *data* blob into a special BPF perf event held by * *map* of type **BPF_MAP_TYPE_PERF_EVENT_ARRAY**. This perf @@ -1244,7 +1072,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_load_bytes(const void *skb, u32 offset, void *to, u32 len) + * int bpf_skb_load_bytes(const struct sk_buff *skb, u32 offset, void *to, u32 len) * Description * This helper was provided as an easy way to load data from a * packet. It can be used to load *len* bytes from *offset* from @@ -1261,7 +1089,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_get_stackid(void *ctx, struct bpf_map *map, u64 flags) + * int bpf_get_stackid(struct pt_regs *ctx, struct bpf_map *map, u64 flags) * Description * Walk a user or a kernel stack and return its id. To achieve * this, the helper needs *ctx*, which is a pointer to the context @@ -1330,7 +1158,7 @@ union bpf_attr { * The checksum result, or a negative error code in case of * failure. * - * long bpf_skb_get_tunnel_opt(struct sk_buff *skb, void *opt, u32 size) + * int bpf_skb_get_tunnel_opt(struct sk_buff *skb, u8 *opt, u32 size) * Description * Retrieve tunnel options metadata for the packet associated to * *skb*, and store the raw tunnel option data to the buffer *opt* @@ -1348,7 +1176,7 @@ union bpf_attr { * Return * The size of the option data retrieved. * - * long bpf_skb_set_tunnel_opt(struct sk_buff *skb, void *opt, u32 size) + * int bpf_skb_set_tunnel_opt(struct sk_buff *skb, u8 *opt, u32 size) * Description * Set tunnel options metadata for the packet associated to *skb* * to the option data contained in the raw buffer *opt* of *size*. @@ -1358,7 +1186,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_change_proto(struct sk_buff *skb, __be16 proto, u64 flags) + * int bpf_skb_change_proto(struct sk_buff *skb, __be16 proto, u64 flags) * Description * Change the protocol of the *skb* to *proto*. Currently * supported are transition from IPv4 to IPv6, and from IPv6 to @@ -1385,7 +1213,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_change_type(struct sk_buff *skb, u32 type) + * int bpf_skb_change_type(struct sk_buff *skb, u32 type) * Description * Change the packet type for the packet associated to *skb*. This * comes down to setting *skb*\ **->pkt_type** to *type*, except @@ -1412,7 +1240,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_under_cgroup(struct sk_buff *skb, struct bpf_map *map, u32 index) + * int bpf_skb_under_cgroup(struct sk_buff *skb, struct bpf_map *map, u32 index) * Description * Check whether *skb* is a descendant of the cgroup2 held by * *map* of type **BPF_MAP_TYPE_CGROUP_ARRAY**, at *index*. @@ -1443,7 +1271,7 @@ union bpf_attr { * Return * A pointer to the current task struct. * - * long bpf_probe_write_user(void *dst, const void *src, u32 len) + * int bpf_probe_write_user(void *dst, const void *src, u32 len) * Description * Attempt in a safe way to write *len* bytes from the buffer * *src* to *dst* in memory. It only works for threads that are in @@ -1462,7 +1290,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_current_task_under_cgroup(struct bpf_map *map, u32 index) + * int bpf_current_task_under_cgroup(struct bpf_map *map, u32 index) * Description * Check whether the probe is being run is the context of a given * subset of the cgroup2 hierarchy. The cgroup2 to test is held by @@ -1474,7 +1302,7 @@ union bpf_attr { * * 0, if current task does not belong to the cgroup2. * * A negative error code, if an error occurred. * - * long bpf_skb_change_tail(struct sk_buff *skb, u32 len, u64 flags) + * int bpf_skb_change_tail(struct sk_buff *skb, u32 len, u64 flags) * Description * Resize (trim or grow) the packet associated to *skb* to the * new *len*. The *flags* are reserved for future usage, and must @@ -1498,7 +1326,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_pull_data(struct sk_buff *skb, u32 len) + * int bpf_skb_pull_data(struct sk_buff *skb, u32 len) * Description * Pull in non-linear data in case the *skb* is non-linear and not * all of *len* are part of the linear section. Make *len* bytes @@ -1554,7 +1382,7 @@ union bpf_attr { * recalculation the next time the kernel tries to access this * hash or when the **bpf_get_hash_recalc**\ () helper is called. * - * long bpf_get_numa_node_id(void) + * int bpf_get_numa_node_id(void) * Description * Return the id of the current NUMA node. The primary use case * for this helper is the selection of sockets for the local NUMA @@ -1565,7 +1393,7 @@ union bpf_attr { * Return * The id of current NUMA node. * - * long bpf_skb_change_head(struct sk_buff *skb, u32 len, u64 flags) + * int bpf_skb_change_head(struct sk_buff *skb, u32 len, u64 flags) * Description * Grows headroom of packet associated to *skb* and adjusts the * offset of the MAC header accordingly, adding *len* bytes of @@ -1586,7 +1414,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_xdp_adjust_head(struct xdp_buff *xdp_md, int delta) + * int bpf_xdp_adjust_head(struct xdp_buff *xdp_md, int delta) * Description * Adjust (move) *xdp_md*\ **->data** by *delta* bytes. Note that * it is possible to use a negative value for *delta*. This helper @@ -1601,14 +1429,45 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_probe_read_str(void *dst, u32 size, const void *unsafe_ptr) + * int bpf_probe_read_str(void *dst, int size, const void *unsafe_ptr) * Description - * Copy a NUL terminated string from an unsafe kernel address - * *unsafe_ptr* to *dst*. See bpf_probe_read_kernel_str() for - * more details. + * Copy a NUL terminated string from an unsafe address + * *unsafe_ptr* to *dst*. The *size* should include the + * terminating NUL byte. In case the string length is smaller than + * *size*, the target is not padded with further NUL bytes. If the + * string length is larger than *size*, just *size*-1 bytes are + * copied and the last byte is set to NUL. * - * Generally, use bpf_probe_read_user_str() or bpf_probe_read_kernel_str() - * instead. + * On success, the length of the copied string is returned. This + * makes this helper useful in tracing programs for reading + * strings, and more importantly to get its length at runtime. See + * the following snippet: + * + * :: + * + * SEC("kprobe/sys_open") + * void bpf_sys_open(struct pt_regs *ctx) + * { + * char buf[PATHLEN]; // PATHLEN is defined to 256 + * int res = bpf_probe_read_str(buf, sizeof(buf), + * ctx->di); + * + * // Consume buf, for example push it to + * // userspace via bpf_perf_event_output(); we + * // can use res (the string length) as event + * // size, after checking its boundaries. + * } + * + * In comparison, using **bpf_probe_read()** helper here instead + * to read the string would require to estimate the length at + * compile time, and would often result in copying more memory + * than necessary. + * + * Another useful use case is when parsing individual process + * arguments or individual environment variables navigating + * *current*\ **->mm->arg_start** and *current*\ + * **->mm->env_start**: using this helper and the return value, + * one can quickly iterate at the right offset of the memory area. * Return * On success, the strictly positive length of the string, * including the trailing NUL character. On error, a negative @@ -1649,14 +1508,14 @@ union bpf_attr { * is returned (note that **overflowuid** might also be the actual * UID value for the socket). * - * long bpf_set_hash(struct sk_buff *skb, u32 hash) + * u32 bpf_set_hash(struct sk_buff *skb, u32 hash) * Description * Set the full hash for *skb* (set the field *skb*\ **->hash**) * to value *hash*. * Return * 0 * - * long bpf_setsockopt(void *bpf_socket, int level, int optname, void *optval, int optlen) + * int bpf_setsockopt(struct bpf_sock_ops *bpf_socket, int level, int optname, char *optval, int optlen) * Description * Emulate a call to **setsockopt()** on the socket associated to * *bpf_socket*, which must be a full socket. The *level* at @@ -1664,40 +1523,25 @@ union bpf_attr { * must be specified, see **setsockopt(2)** for more information. * The option value of length *optlen* is pointed by *optval*. * - * *bpf_socket* should be one of the following: - * * **struct bpf_sock_ops** for **BPF_PROG_TYPE_SOCK_OPS**. - * * **struct bpf_sock_addr** for **BPF_CGROUP_INET4_CONNECT** - * and **BPF_CGROUP_INET6_CONNECT**. - * * This helper actually implements a subset of **setsockopt()**. * It supports the following *level*\ s: * * * **SOL_SOCKET**, which supports the following *optname*\ s: * **SO_RCVBUF**, **SO_SNDBUF**, **SO_MAX_PACING_RATE**, - * **SO_PRIORITY**, **SO_RCVLOWAT**, **SO_MARK**, - * **SO_BINDTODEVICE**, **SO_KEEPALIVE**. + * **SO_PRIORITY**, **SO_RCVLOWAT**, **SO_MARK**. * * **IPPROTO_TCP**, which supports the following *optname*\ s: * **TCP_CONGESTION**, **TCP_BPF_IW**, - * **TCP_BPF_SNDCWND_CLAMP**, **TCP_SAVE_SYN**, - * **TCP_KEEPIDLE**, **TCP_KEEPINTVL**, **TCP_KEEPCNT**, - * **TCP_SYNCNT**, **TCP_USER_TIMEOUT**, **TCP_NOTSENT_LOWAT**. + * **TCP_BPF_SNDCWND_CLAMP**. * * **IPPROTO_IP**, which supports *optname* **IP_TOS**. * * **IPPROTO_IPV6**, which supports *optname* **IPV6_TCLASS**. * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_adjust_room(struct sk_buff *skb, s32 len_diff, u32 mode, u64 flags) + * int bpf_skb_adjust_room(struct sk_buff *skb, s32 len_diff, u32 mode, u64 flags) * Description * Grow or shrink the room for data in the packet associated to * *skb* by *len_diff*, and according to the selected *mode*. * - * By default, the helper will reset any offloaded checksum - * indicator of the skb to CHECKSUM_NONE. This can be avoided - * by the following flag: - * - * * **BPF_F_ADJ_ROOM_NO_CSUM_RESET**: Do not reset offloaded - * checksum data of the skb to CHECKSUM_NONE. - * * There are two supported modes at this time: * * * **BPF_ADJ_ROOM_MAC**: Adjust room at the mac layer @@ -1732,7 +1576,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_redirect_map(struct bpf_map *map, u32 key, u64 flags) + * int bpf_redirect_map(struct bpf_map *map, u32 key, u64 flags) * Description * Redirect the packet to the endpoint referenced by *map* at * index *key*. Depending on its type, this *map* can contain @@ -1747,13 +1591,15 @@ union bpf_attr { * the caller. Any higher bits in the *flags* argument must be * unset. * - * See also bpf_redirect(), which only supports redirecting to an - * ifindex, but doesn't require a map to do so. + * When used to redirect packets to net devices, this helper + * provides a high performance increase over **bpf_redirect**\ (). + * This is due to various implementation details of the underlying + * mechanisms, one of which is the fact that **bpf_redirect_map**\ + * () tries to send packet as a "bulk" to the device. * Return - * **XDP_REDIRECT** on success, or the value of the two lower bits - * of the *flags* argument on error. + * **XDP_REDIRECT** on success, or **XDP_ABORTED** on error. * - * long bpf_sk_redirect_map(struct sk_buff *skb, struct bpf_map *map, u32 key, u64 flags) + * int bpf_sk_redirect_map(struct bpf_map *map, u32 key, u64 flags) * Description * Redirect the packet to the socket referenced by *map* (of type * **BPF_MAP_TYPE_SOCKMAP**) at index *key*. Both ingress and @@ -1764,7 +1610,7 @@ union bpf_attr { * Return * **SK_PASS** on success, or **SK_DROP** on error. * - * long bpf_sock_map_update(struct bpf_sock_ops *skops, struct bpf_map *map, void *key, u64 flags) + * int bpf_sock_map_update(struct bpf_sock_ops *skops, struct bpf_map *map, void *key, u64 flags) * Description * Add an entry to, or update a *map* referencing sockets. The * *skops* is used as a new value for the entry associated to @@ -1783,7 +1629,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_xdp_adjust_meta(struct xdp_buff *xdp_md, int delta) + * int bpf_xdp_adjust_meta(struct xdp_buff *xdp_md, int delta) * Description * Adjust the address pointed by *xdp_md*\ **->data_meta** by * *delta* (which can be positive or negative). Note that this @@ -1812,7 +1658,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_perf_event_read_value(struct bpf_map *map, u64 flags, struct bpf_perf_event_value *buf, u32 buf_size) + * int bpf_perf_event_read_value(struct bpf_map *map, u64 flags, struct bpf_perf_event_value *buf, u32 buf_size) * Description * Read the value of a perf event counter, and store it into *buf* * of size *buf_size*. This helper relies on a *map* of type @@ -1862,7 +1708,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_perf_prog_read_value(struct bpf_perf_event_data *ctx, struct bpf_perf_event_value *buf, u32 buf_size) + * int bpf_perf_prog_read_value(struct bpf_perf_event_data *ctx, struct bpf_perf_event_value *buf, u32 buf_size) * Description * For en eBPF program attached to a perf event, retrieve the * value of the event counter associated to *ctx* and store it in @@ -1873,7 +1719,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_getsockopt(void *bpf_socket, int level, int optname, void *optval, int optlen) + * int bpf_getsockopt(struct bpf_sock_ops *bpf_socket, int level, int optname, char *optval, int optlen) * Description * Emulate a call to **getsockopt()** on the socket associated to * *bpf_socket*, which must be a full socket. The *level* at @@ -1882,11 +1728,6 @@ union bpf_attr { * The retrieved value is stored in the structure pointed by * *opval* and of length *optlen*. * - * *bpf_socket* should be one of the following: - * * **struct bpf_sock_ops** for **BPF_PROG_TYPE_SOCK_OPS**. - * * **struct bpf_sock_addr** for **BPF_CGROUP_INET4_CONNECT** - * and **BPF_CGROUP_INET6_CONNECT**. - * * This helper actually implements a subset of **getsockopt()**. * It supports the following *level*\ s: * @@ -1897,7 +1738,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_override_return(struct pt_regs *regs, u64 rc) + * int bpf_override_return(struct pt_regs *regs, u64 rc) * Description * Used for error injection, this helper uses kprobes to override * the return value of the probed function, and to set it to *rc*. @@ -1922,7 +1763,7 @@ union bpf_attr { * Return * 0 * - * long bpf_sock_ops_cb_flags_set(struct bpf_sock_ops *bpf_sock, int argval) + * int bpf_sock_ops_cb_flags_set(struct bpf_sock_ops *bpf_sock, int argval) * Description * Attempt to set the value of the **bpf_sock_ops_cb_flags** field * for the full TCP socket associated to *bpf_sock_ops* to @@ -1966,7 +1807,7 @@ union bpf_attr { * be set is returned (which comes down to 0 if all bits were set * as required). * - * long bpf_msg_redirect_map(struct sk_msg_buff *msg, struct bpf_map *map, u32 key, u64 flags) + * int bpf_msg_redirect_map(struct sk_msg_buff *msg, struct bpf_map *map, u32 key, u64 flags) * Description * This helper is used in programs implementing policies at the * socket level. If the message *msg* is allowed to pass (i.e. if @@ -1980,7 +1821,7 @@ union bpf_attr { * Return * **SK_PASS** on success, or **SK_DROP** on error. * - * long bpf_msg_apply_bytes(struct sk_msg_buff *msg, u32 bytes) + * int bpf_msg_apply_bytes(struct sk_msg_buff *msg, u32 bytes) * Description * For socket policies, apply the verdict of the eBPF program to * the next *bytes* (number of bytes) of message *msg*. @@ -2014,7 +1855,7 @@ union bpf_attr { * Return * 0 * - * long bpf_msg_cork_bytes(struct sk_msg_buff *msg, u32 bytes) + * int bpf_msg_cork_bytes(struct sk_msg_buff *msg, u32 bytes) * Description * For socket policies, prevent the execution of the verdict eBPF * program for message *msg* until *bytes* (byte number) have been @@ -2032,7 +1873,7 @@ union bpf_attr { * Return * 0 * - * long bpf_msg_pull_data(struct sk_msg_buff *msg, u32 start, u32 end, u64 flags) + * int bpf_msg_pull_data(struct sk_msg_buff *msg, u32 start, u32 end, u64 flags) * Description * For socket policies, pull in non-linear data from user space * for *msg* and set pointers *msg*\ **->data** and *msg*\ @@ -2063,7 +1904,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_bind(struct bpf_sock_addr *ctx, struct sockaddr *addr, int addr_len) + * int bpf_bind(struct bpf_sock_addr *ctx, struct sockaddr *addr, int addr_len) * Description * Bind the socket associated to *ctx* to the address pointed by * *addr*, of length *addr_len*. This allows for making outgoing @@ -2073,15 +1914,14 @@ union bpf_attr { * * This helper works for IPv4 and IPv6, TCP and UDP sockets. The * domain (*addr*\ **->sa_family**) must be **AF_INET** (or - * **AF_INET6**). It's advised to pass zero port (**sin_port** - * or **sin6_port**) which triggers IP_BIND_ADDRESS_NO_PORT-like - * behavior and lets the kernel efficiently pick up an unused - * port as long as 4-tuple is unique. Passing non-zero port might - * lead to degraded performance. + * **AF_INET6**). Looking for a free port to bind to can be + * expensive, therefore binding to port is not permitted by the + * helper: *addr*\ **->sin_port** (or **sin6_port**, respectively) + * must be set to zero. * Return * 0 on success, or a negative error in case of failure. * - * long bpf_xdp_adjust_tail(struct xdp_buff *xdp_md, int delta) + * int bpf_xdp_adjust_tail(struct xdp_buff *xdp_md, int delta) * Description * Adjust (move) *xdp_md*\ **->data_end** by *delta* bytes. It is * only possible to shrink the packet as of this writing, @@ -2095,7 +1935,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_skb_get_xfrm_state(struct sk_buff *skb, u32 index, struct bpf_xfrm_state *xfrm_state, u32 size, u64 flags) + * int bpf_skb_get_xfrm_state(struct sk_buff *skb, u32 index, struct bpf_xfrm_state *xfrm_state, u32 size, u64 flags) * Description * Retrieve the XFRM state (IP transform framework, see also * **ip-xfrm(8)**) at *index* in XFRM "security path" for *skb*. @@ -2111,7 +1951,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_get_stack(void *ctx, void *buf, u32 size, u64 flags) + * int bpf_get_stack(struct pt_regs *regs, void *buf, u32 size, u64 flags) * Description * Return a user or a kernel stack in bpf program provided buffer. * To achieve this, the helper needs *ctx*, which is a pointer @@ -2144,7 +1984,7 @@ union bpf_attr { * A non-negative value equal to or less than *size* on success, * or a negative error in case of failure. * - * long bpf_skb_load_bytes_relative(const void *skb, u32 offset, void *to, u32 len, u32 start_header) + * int bpf_skb_load_bytes_relative(const struct sk_buff *skb, u32 offset, void *to, u32 len, u32 start_header) * Description * This helper is similar to **bpf_skb_load_bytes**\ () in that * it provides an easy way to load *len* bytes from *offset* @@ -2166,7 +2006,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_fib_lookup(void *ctx, struct bpf_fib_lookup *params, int plen, u32 flags) + * int bpf_fib_lookup(void *ctx, struct bpf_fib_lookup *params, int plen, u32 flags) * Description * Do FIB lookup in kernel tables using parameters in *params*. * If lookup is successful and result shows packet is to be @@ -2197,7 +2037,7 @@ union bpf_attr { * * > 0 one of **BPF_FIB_LKUP_RET_** codes explaining why the * packet is not forwarded or needs assist from full stack * - * long bpf_sock_hash_update(struct bpf_sock_ops *skops, struct bpf_map *map, void *key, u64 flags) + * int bpf_sock_hash_update(struct bpf_sock_ops_kern *skops, struct bpf_map *map, void *key, u64 flags) * Description * Add an entry to, or update a sockhash *map* referencing sockets. * The *skops* is used as a new value for the entry associated to @@ -2216,7 +2056,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_msg_redirect_hash(struct sk_msg_buff *msg, struct bpf_map *map, void *key, u64 flags) + * int bpf_msg_redirect_hash(struct sk_msg_buff *msg, struct bpf_map *map, void *key, u64 flags) * Description * This helper is used in programs implementing policies at the * socket level. If the message *msg* is allowed to pass (i.e. if @@ -2230,11 +2070,11 @@ union bpf_attr { * Return * **SK_PASS** on success, or **SK_DROP** on error. * - * long bpf_sk_redirect_hash(struct sk_buff *skb, struct bpf_map *map, void *key, u64 flags) + * int bpf_sk_redirect_hash(struct sk_buff *skb, struct bpf_map *map, void *key, u64 flags) * Description * This helper is used in programs implementing policies at the * skb socket level. If the sk_buff *skb* is allowed to pass (i.e. - * if the verdict eBPF program returns **SK_PASS**), redirect it + * if the verdeict eBPF program returns **SK_PASS**), redirect it * to the socket referenced by *map* (of type * **BPF_MAP_TYPE_SOCKHASH**) using hash *key*. Both ingress and * egress interfaces can be used for redirection. The @@ -2244,7 +2084,7 @@ union bpf_attr { * Return * **SK_PASS** on success, or **SK_DROP** on error. * - * long bpf_lwt_push_encap(struct sk_buff *skb, u32 type, void *hdr, u32 len) + * int bpf_lwt_push_encap(struct sk_buff *skb, u32 type, void *hdr, u32 len) * Description * Encapsulate the packet associated to *skb* within a Layer 3 * protocol header. This header is provided in the buffer at @@ -2281,7 +2121,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_lwt_seg6_store_bytes(struct sk_buff *skb, u32 offset, const void *from, u32 len) + * int bpf_lwt_seg6_store_bytes(struct sk_buff *skb, u32 offset, const void *from, u32 len) * Description * Store *len* bytes from address *from* into the packet * associated to *skb*, at *offset*. Only the flags, tag and TLVs @@ -2296,7 +2136,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_lwt_seg6_adjust_srh(struct sk_buff *skb, u32 offset, s32 delta) + * int bpf_lwt_seg6_adjust_srh(struct sk_buff *skb, u32 offset, s32 delta) * Description * Adjust the size allocated to TLVs in the outermost IPv6 * Segment Routing Header contained in the packet associated to @@ -2312,7 +2152,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_lwt_seg6_action(struct sk_buff *skb, u32 action, void *param, u32 param_len) + * int bpf_lwt_seg6_action(struct sk_buff *skb, u32 action, void *param, u32 param_len) * Description * Apply an IPv6 Segment Routing action of type *action* to the * packet associated to *skb*. Each action takes a parameter @@ -2341,7 +2181,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_rc_repeat(void *ctx) + * int bpf_rc_repeat(void *ctx) * Description * This helper is used in programs implementing IR decoding, to * report a successfully decoded repeat key message. This delays @@ -2360,7 +2200,7 @@ union bpf_attr { * Return * 0 * - * long bpf_rc_keydown(void *ctx, u32 protocol, u64 scancode, u32 toggle) + * int bpf_rc_keydown(void *ctx, u32 protocol, u64 scancode, u32 toggle) * Description * This helper is used in programs implementing IR decoding, to * report a successfully decoded key press with *scancode*, @@ -2425,7 +2265,7 @@ union bpf_attr { * Return * A pointer to the local storage area. * - * long bpf_sk_select_reuseport(struct sk_reuseport_md *reuse, struct bpf_map *map, void *key, u64 flags) + * int bpf_sk_select_reuseport(struct sk_reuseport_md *reuse, struct bpf_map *map, void *key, u64 flags) * Description * Select a **SO_REUSEPORT** socket from a * **BPF_MAP_TYPE_REUSEPORT_SOCKARRAY** *map*. @@ -2470,7 +2310,7 @@ union bpf_attr { * Look for an IPv6 socket. * * If the *netns* is a negative signed 32-bit integer, then the - * socket lookup table in the netns associated with the *ctx* + * socket lookup table in the netns associated with the *ctx* will * will be used. For the TC hooks, this is the netns of the device * in the skb. For socket hooks, this is the netns of the socket. * If *netns* is any other signed 32-bit value greater than or @@ -2507,7 +2347,7 @@ union bpf_attr { * Look for an IPv6 socket. * * If the *netns* is a negative signed 32-bit integer, then the - * socket lookup table in the netns associated with the *ctx* + * socket lookup table in the netns associated with the *ctx* will * will be used. For the TC hooks, this is the netns of the device * in the skb. For socket hooks, this is the netns of the socket. * If *netns* is any other signed 32-bit value greater than or @@ -2526,7 +2366,7 @@ union bpf_attr { * result is from *reuse*\ **->socks**\ [] using the hash of the * tuple. * - * long bpf_sk_release(void *sock) + * int bpf_sk_release(struct bpf_sock *sock) * Description * Release the reference held by *sock*. *sock* must be a * non-**NULL** pointer that was returned from @@ -2534,7 +2374,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_map_push_elem(struct bpf_map *map, const void *value, u64 flags) + * int bpf_map_push_elem(struct bpf_map *map, const void *value, u64 flags) * Description * Push an element *value* in *map*. *flags* is one of: * @@ -2544,19 +2384,19 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_map_pop_elem(struct bpf_map *map, void *value) + * int bpf_map_pop_elem(struct bpf_map *map, void *value) * Description * Pop an element from *map*. * Return * 0 on success, or a negative error in case of failure. * - * long bpf_map_peek_elem(struct bpf_map *map, void *value) + * int bpf_map_peek_elem(struct bpf_map *map, void *value) * Description * Get an element from *map* without removing it. * Return * 0 on success, or a negative error in case of failure. * - * long bpf_msg_push_data(struct sk_msg_buff *msg, u32 start, u32 len, u64 flags) + * int bpf_msg_push_data(struct sk_buff *skb, u32 start, u32 len, u64 flags) * Description * For socket policies, insert *len* bytes into *msg* at offset * *start*. @@ -2572,9 +2412,9 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_msg_pop_data(struct sk_msg_buff *msg, u32 start, u32 len, u64 flags) + * int bpf_msg_pop_data(struct sk_msg_buff *msg, u32 start, u32 pop, u64 flags) * Description - * Will remove *len* bytes from a *msg* starting at byte *start*. + * Will remove *pop* bytes from a *msg* starting at byte *start*. * This may result in **ENOMEM** errors under certain situations if * an allocation and copy are required due to a full ring buffer. * However, the helper will try to avoid doing the allocation @@ -2584,7 +2424,7 @@ union bpf_attr { * Return * 0 on success, or a negative error in case of failure. * - * long bpf_rc_pointer_rel(void *ctx, s32 rel_x, s32 rel_y) + * int bpf_rc_pointer_rel(void *ctx, s32 rel_x, s32 rel_y) * Description * This helper is used in programs implementing IR decoding, to * report a successfully decoded pointer movement. @@ -2598,7 +2438,7 @@ union bpf_attr { * Return * 0 * - * long bpf_spin_lock(struct bpf_spin_lock *lock) + * int bpf_spin_lock(struct bpf_spin_lock *lock) * Description * Acquire a spinlock represented by the pointer *lock*, which is * stored as part of a value of a map. Taking the lock allows to @@ -2646,7 +2486,7 @@ union bpf_attr { * Return * 0 * - * long bpf_spin_unlock(struct bpf_spin_lock *lock) + * int bpf_spin_unlock(struct bpf_spin_lock *lock) * Description * Release the *lock* previously locked by a call to * **bpf_spin_lock**\ (\ *lock*\ ). @@ -2669,7 +2509,7 @@ union bpf_attr { * A **struct bpf_tcp_sock** pointer on success, or **NULL** in * case of failure. * - * long bpf_skb_ecn_set_ce(struct sk_buff *skb) + * int bpf_skb_ecn_set_ce(struct sk_buf *skb) * Description * Set ECN (Explicit Congestion Notification) field of IP header * to **CE** (Congestion Encountered) if current value is **ECT** @@ -2706,7 +2546,7 @@ union bpf_attr { * result is from *reuse*\ **->socks**\ [] using the hash of the * tuple. * - * long bpf_tcp_check_syncookie(void *sk, void *iph, u32 iph_len, struct tcphdr *th, u32 th_len) + * int bpf_tcp_check_syncookie(struct bpf_sock *sk, void *iph, u32 iph_len, struct tcphdr *th, u32 th_len) * Description * Check whether *iph* and *th* contain a valid SYN cookie ACK for * the listening socket in *sk*. @@ -2722,7 +2562,7 @@ union bpf_attr { * 0 if *iph* and *th* are a valid SYN cookie ACK, or a negative * error otherwise. * - * long bpf_sysctl_get_name(struct bpf_sysctl *ctx, char *buf, size_t buf_len, u64 flags) + * int bpf_sysctl_get_name(struct bpf_sysctl *ctx, char *buf, size_t buf_len, u64 flags) * Description * Get name of sysctl in /proc/sys/ and copy it into provided by * program buffer *buf* of size *buf_len*. @@ -2738,7 +2578,7 @@ union bpf_attr { * **-E2BIG** if the buffer wasn't big enough (*buf* will contain * truncated name in this case). * - * long bpf_sysctl_get_current_value(struct bpf_sysctl *ctx, char *buf, size_t buf_len) + * int bpf_sysctl_get_current_value(struct bpf_sysctl *ctx, char *buf, size_t buf_len) * Description * Get current value of sysctl as it is presented in /proc/sys * (incl. newline, etc), and copy it as a string into provided @@ -2757,7 +2597,7 @@ union bpf_attr { * **-EINVAL** if current value was unavailable, e.g. because * sysctl is uninitialized and read returns -EIO for it. * - * long bpf_sysctl_get_new_value(struct bpf_sysctl *ctx, char *buf, size_t buf_len) + * int bpf_sysctl_get_new_value(struct bpf_sysctl *ctx, char *buf, size_t buf_len) * Description * Get new value being written by user space to sysctl (before * the actual write happens) and copy it as a string into @@ -2774,7 +2614,7 @@ union bpf_attr { * * **-EINVAL** if sysctl is being read. * - * long bpf_sysctl_set_new_value(struct bpf_sysctl *ctx, const char *buf, size_t buf_len) + * int bpf_sysctl_set_new_value(struct bpf_sysctl *ctx, const char *buf, size_t buf_len) * Description * Override new value being written by user space to sysctl with * value provided by program in buffer *buf* of size *buf_len*. @@ -2791,7 +2631,7 @@ union bpf_attr { * * **-EINVAL** if sysctl is being read. * - * long bpf_strtol(const char *buf, size_t buf_len, u64 flags, long *res) + * int bpf_strtol(const char *buf, size_t buf_len, u64 flags, long *res) * Description * Convert the initial part of the string from buffer *buf* of * size *buf_len* to a long integer according to the given base @@ -2815,7 +2655,7 @@ union bpf_attr { * * **-ERANGE** if resulting value was out of range. * - * long bpf_strtoul(const char *buf, size_t buf_len, u64 flags, unsigned long *res) + * int bpf_strtoul(const char *buf, size_t buf_len, u64 flags, unsigned long *res) * Description * Convert the initial part of the string from buffer *buf* of * size *buf_len* to an unsigned long integer according to the @@ -2838,7 +2678,7 @@ union bpf_attr { * * **-ERANGE** if resulting value was out of range. * - * void *bpf_sk_storage_get(struct bpf_map *map, void *sk, void *value, u64 flags) + * void *bpf_sk_storage_get(struct bpf_map *map, struct bpf_sock *sk, void *value, u64 flags) * Description * Get a bpf-local-storage from a *sk*. * @@ -2854,9 +2694,6 @@ union bpf_attr { * "type". The bpf-local-storage "type" (i.e. the *map*) is * searched against all bpf-local-storages residing at *sk*. * - * *sk* is a kernel **struct sock** pointer for LSM program. - * *sk* is a **struct bpf_sock** pointer for other program types. - * * An optional *flags* (**BPF_SK_STORAGE_GET_F_CREATE**) can be * used such that a new bpf-local-storage will be * created if one does not exist. *value* can be used @@ -2869,19 +2706,17 @@ union bpf_attr { * **NULL** if not found or there was an error in adding * a new bpf-local-storage. * - * long bpf_sk_storage_delete(struct bpf_map *map, void *sk) + * int bpf_sk_storage_delete(struct bpf_map *map, struct bpf_sock *sk) * Description * Delete a bpf-local-storage from a *sk*. * Return * 0 on success. * * **-ENOENT** if the bpf-local-storage cannot be found. - * **-EINVAL** if sk is not a fullsock (e.g. a request_sock). * - * long bpf_send_signal(u32 sig) + * int bpf_send_signal(u32 sig) * Description - * Send signal *sig* to the process of the current task. - * The signal may be delivered to any of this process's threads. + * Send signal *sig* to the current task. * Return * 0 on success or successfully queued. * @@ -2893,7 +2728,7 @@ union bpf_attr { * * **-EAGAIN** if bpf program can try again. * - * s64 bpf_tcp_gen_syncookie(void *sk, void *iph, u32 iph_len, struct tcphdr *th, u32 th_len) + * s64 bpf_tcp_gen_syncookie(struct bpf_sock *sk, void *iph, u32 iph_len, struct tcphdr *th, u32 th_len) * Description * Try to issue a SYN cookie for the packet with corresponding * IP/TCP headers, *iph* and *th*, on the listening socket in *sk*. @@ -2927,794 +2762,6 @@ union bpf_attr { * See: clock_gettime(CLOCK_BOOTTIME) * Return * Current *ktime*. - * - * long bpf_skb_output(void *ctx, struct bpf_map *map, u64 flags, void *data, u64 size) - * Description - * Write raw *data* blob into a special BPF perf event held by - * *map* of type **BPF_MAP_TYPE_PERF_EVENT_ARRAY**. This perf - * event must have the following attributes: **PERF_SAMPLE_RAW** - * as **sample_type**, **PERF_TYPE_SOFTWARE** as **type**, and - * **PERF_COUNT_SW_BPF_OUTPUT** as **config**. - * - * The *flags* are used to indicate the index in *map* for which - * the value must be put, masked with **BPF_F_INDEX_MASK**. - * Alternatively, *flags* can be set to **BPF_F_CURRENT_CPU** - * to indicate that the index of the current CPU core should be - * used. - * - * The value to write, of *size*, is passed through eBPF stack and - * pointed by *data*. - * - * *ctx* is a pointer to in-kernel struct sk_buff. - * - * This helper is similar to **bpf_perf_event_output**\ () but - * restricted to raw_tracepoint bpf programs. - * Return - * 0 on success, or a negative error in case of failure. - * - * long bpf_probe_read_user(void *dst, u32 size, const void *unsafe_ptr) - * Description - * Safely attempt to read *size* bytes from user space address - * *unsafe_ptr* and store the data in *dst*. - * Return - * 0 on success, or a negative error in case of failure. - * - * long bpf_probe_read_kernel(void *dst, u32 size, const void *unsafe_ptr) - * Description - * Safely attempt to read *size* bytes from kernel space address - * *unsafe_ptr* and store the data in *dst*. - * Return - * 0 on success, or a negative error in case of failure. - * - * long bpf_probe_read_user_str(void *dst, u32 size, const void *unsafe_ptr) - * Description - * Copy a NUL terminated string from an unsafe user address - * *unsafe_ptr* to *dst*. The *size* should include the - * terminating NUL byte. In case the string length is smaller than - * *size*, the target is not padded with further NUL bytes. If the - * string length is larger than *size*, just *size*-1 bytes are - * copied and the last byte is set to NUL. - * - * On success, the length of the copied string is returned. This - * makes this helper useful in tracing programs for reading - * strings, and more importantly to get its length at runtime. See - * the following snippet: - * - * :: - * - * SEC("kprobe/sys_open") - * void bpf_sys_open(struct pt_regs *ctx) - * { - * char buf[PATHLEN]; // PATHLEN is defined to 256 - * int res = bpf_probe_read_user_str(buf, sizeof(buf), - * ctx->di); - * - * // Consume buf, for example push it to - * // userspace via bpf_perf_event_output(); we - * // can use res (the string length) as event - * // size, after checking its boundaries. - * } - * - * In comparison, using **bpf_probe_read_user()** helper here - * instead to read the string would require to estimate the length - * at compile time, and would often result in copying more memory - * than necessary. - * - * Another useful use case is when parsing individual process - * arguments or individual environment variables navigating - * *current*\ **->mm->arg_start** and *current*\ - * **->mm->env_start**: using this helper and the return value, - * one can quickly iterate at the right offset of the memory area. - * Return - * On success, the strictly positive length of the string, - * including the trailing NUL character. On error, a negative - * value. - * - * long bpf_probe_read_kernel_str(void *dst, u32 size, const void *unsafe_ptr) - * Description - * Copy a NUL terminated string from an unsafe kernel address *unsafe_ptr* - * to *dst*. Same semantics as with bpf_probe_read_user_str() apply. - * Return - * On success, the strictly positive length of the string, including - * the trailing NUL character. On error, a negative value. - * - * long bpf_tcp_send_ack(void *tp, u32 rcv_nxt) - * Description - * Send out a tcp-ack. *tp* is the in-kernel struct tcp_sock. - * *rcv_nxt* is the ack_seq to be sent out. - * Return - * 0 on success, or a negative error in case of failure. - * - * long bpf_send_signal_thread(u32 sig) - * Description - * Send signal *sig* to the thread corresponding to the current task. - * Return - * 0 on success or successfully queued. - * - * **-EBUSY** if work queue under nmi is full. - * - * **-EINVAL** if *sig* is invalid. - * - * **-EPERM** if no permission to send the *sig*. - * - * **-EAGAIN** if bpf program can try again. - * - * long bpf_read_branch_records(struct bpf_perf_event_data *ctx, void *buf, u32 size, u64 flags) - * Description - * For an eBPF program attached to a perf event, retrieve the - * branch records (struct perf_branch_entry) associated to *ctx* - * and store it in the buffer pointed by *buf* up to size - * *size* bytes. - * Return - * On success, number of bytes written to *buf*. On error, a - * negative value. - * - * The *flags* can be set to **BPF_F_GET_BRANCH_RECORDS_SIZE** to - * instead return the number of bytes required to store all the - * branch entries. If this flag is set, *buf* may be NULL. - * - * **-EINVAL** if arguments invalid or **size** not a multiple - * of sizeof(struct perf_branch_entry). - * - * **-ENOENT** if architecture does not support branch records. - * - * long bpf_get_ns_current_pid_tgid(u64 dev, u64 ino, struct bpf_pidns_info *nsdata, u32 size) - * Description - * Returns 0 on success, values for *pid* and *tgid* as seen from the current - * *namespace* will be returned in *nsdata*. - * - * On failure, the returned value is one of the following: - * - * **-EINVAL** if dev and inum supplied don't match dev_t and inode number - * with nsfs of current task, or if dev conversion to dev_t lost high bits. - * - * **-ENOENT** if pidns does not exists for the current task. - * - * long bpf_xdp_output(void *ctx, struct bpf_map *map, u64 flags, void *data, u64 size) - * Description - * Write raw *data* blob into a special BPF perf event held by - * *map* of type **BPF_MAP_TYPE_PERF_EVENT_ARRAY**. This perf - * event must have the following attributes: **PERF_SAMPLE_RAW** - * as **sample_type**, **PERF_TYPE_SOFTWARE** as **type**, and - * **PERF_COUNT_SW_BPF_OUTPUT** as **config**. - * - * The *flags* are used to indicate the index in *map* for which - * the value must be put, masked with **BPF_F_INDEX_MASK**. - * Alternatively, *flags* can be set to **BPF_F_CURRENT_CPU** - * to indicate that the index of the current CPU core should be - * used. - * - * The value to write, of *size*, is passed through eBPF stack and - * pointed by *data*. - * - * *ctx* is a pointer to in-kernel struct xdp_buff. - * - * This helper is similar to **bpf_perf_eventoutput**\ () but - * restricted to raw_tracepoint bpf programs. - * Return - * 0 on success, or a negative error in case of failure. - * - * u64 bpf_get_netns_cookie(void *ctx) - * Description - * Retrieve the cookie (generated by the kernel) of the network - * namespace the input *ctx* is associated with. The network - * namespace cookie remains stable for its lifetime and provides - * a global identifier that can be assumed unique. If *ctx* is - * NULL, then the helper returns the cookie for the initial - * network namespace. The cookie itself is very similar to that - * of bpf_get_socket_cookie() helper, but for network namespaces - * instead of sockets. - * Return - * A 8-byte long opaque number. - * - * u64 bpf_get_current_ancestor_cgroup_id(int ancestor_level) - * Description - * Return id of cgroup v2 that is ancestor of the cgroup associated - * with the current task at the *ancestor_level*. The root cgroup - * is at *ancestor_level* zero and each step down the hierarchy - * increments the level. If *ancestor_level* == level of cgroup - * associated with the current task, then return value will be the - * same as that of **bpf_get_current_cgroup_id**\ (). - * - * The helper is useful to implement policies based on cgroups - * that are upper in hierarchy than immediate cgroup associated - * with the current task. - * - * The format of returned id and helper limitations are same as in - * **bpf_get_current_cgroup_id**\ (). - * Return - * The id is returned or 0 in case the id could not be retrieved. - * - * long bpf_sk_assign(struct sk_buff *skb, void *sk, u64 flags) - * Description - * Helper is overloaded depending on BPF program type. This - * description applies to **BPF_PROG_TYPE_SCHED_CLS** and - * **BPF_PROG_TYPE_SCHED_ACT** programs. - * - * Assign the *sk* to the *skb*. When combined with appropriate - * routing configuration to receive the packet towards the socket, - * will cause *skb* to be delivered to the specified socket. - * Subsequent redirection of *skb* via **bpf_redirect**\ (), - * **bpf_clone_redirect**\ () or other methods outside of BPF may - * interfere with successful delivery to the socket. - * - * This operation is only valid from TC ingress path. - * - * The *flags* argument must be zero. - * Return - * 0 on success, or a negative errno in case of failure. - * - * * **-EINVAL** Unsupported flags specified. - * * **-ENOENT** Socket is unavailable for assignment. - * * **-ENETUNREACH** Socket is unreachable (wrong netns). - * * **-EOPNOTSUPP** Unsupported operation, for example a - * call from outside of TC ingress. - * * **-ESOCKTNOSUPPORT** Socket type not supported (reuseport). - * - * long bpf_sk_assign(struct bpf_sk_lookup *ctx, struct bpf_sock *sk, u64 flags) - * Description - * Helper is overloaded depending on BPF program type. This - * description applies to **BPF_PROG_TYPE_SK_LOOKUP** programs. - * - * Select the *sk* as a result of a socket lookup. - * - * For the operation to succeed passed socket must be compatible - * with the packet description provided by the *ctx* object. - * - * L4 protocol (**IPPROTO_TCP** or **IPPROTO_UDP**) must - * be an exact match. While IP family (**AF_INET** or - * **AF_INET6**) must be compatible, that is IPv6 sockets - * that are not v6-only can be selected for IPv4 packets. - * - * Only TCP listeners and UDP unconnected sockets can be - * selected. *sk* can also be NULL to reset any previous - * selection. - * - * *flags* argument can combination of following values: - * - * * **BPF_SK_LOOKUP_F_REPLACE** to override the previous - * socket selection, potentially done by a BPF program - * that ran before us. - * - * * **BPF_SK_LOOKUP_F_NO_REUSEPORT** to skip - * load-balancing within reuseport group for the socket - * being selected. - * - * On success *ctx->sk* will point to the selected socket. - * - * Return - * 0 on success, or a negative errno in case of failure. - * - * * **-EAFNOSUPPORT** if socket family (*sk->family*) is - * not compatible with packet family (*ctx->family*). - * - * * **-EEXIST** if socket has been already selected, - * potentially by another program, and - * **BPF_SK_LOOKUP_F_REPLACE** flag was not specified. - * - * * **-EINVAL** if unsupported flags were specified. - * - * * **-EPROTOTYPE** if socket L4 protocol - * (*sk->protocol*) doesn't match packet protocol - * (*ctx->protocol*). - * - * * **-ESOCKTNOSUPPORT** if socket is not in allowed - * state (TCP listening or UDP unconnected). - * - * u64 bpf_ktime_get_boot_ns(void) - * Description - * Return the time elapsed since system boot, in nanoseconds. - * Does include the time the system was suspended. - * See: clock_gettime(CLOCK_BOOTTIME) - * Return - * Current *ktime*. - * - * long bpf_seq_printf(struct seq_file *m, const char *fmt, u32 fmt_size, const void *data, u32 data_len) - * Description - * seq_printf uses seq_file seq_printf() to print out the format string. - * The *m* represents the seq_file. The *fmt* and *fmt_size* are for - * the format string itself. The *data* and *data_len* are format string - * arguments. The *data* are a u64 array and corresponding format string - * values are stored in the array. For strings and pointers where pointees - * are accessed, only the pointer values are stored in the *data* array. - * The *data_len* is the *data* size in term of bytes. - * - * Formats **%s**, **%p{i,I}{4,6}** requires to read kernel memory. - * Reading kernel memory may fail due to either invalid address or - * valid address but requiring a major memory fault. If reading kernel memory - * fails, the string for **%s** will be an empty string, and the ip - * address for **%p{i,I}{4,6}** will be 0. Not returning error to - * bpf program is consistent with what bpf_trace_printk() does for now. - * Return - * 0 on success, or a negative errno in case of failure. - * - * * **-EBUSY** Percpu memory copy buffer is busy, can try again - * by returning 1 from bpf program. - * * **-EINVAL** Invalid arguments, or invalid/unsupported formats. - * * **-E2BIG** Too many format specifiers. - * * **-EOVERFLOW** Overflow happens, the same object will be tried again. - * - * long bpf_seq_write(struct seq_file *m, const void *data, u32 len) - * Description - * seq_write uses seq_file seq_write() to write the data. - * The *m* represents the seq_file. The *data* and *len* represent the - * data to write in bytes. - * Return - * 0 on success, or a negative errno in case of failure. - * - * * **-EOVERFLOW** Overflow happens, the same object will be tried again. - * - * u64 bpf_sk_cgroup_id(void *sk) - * Description - * Return the cgroup v2 id of the socket *sk*. - * - * *sk* must be a non-**NULL** pointer to a socket, e.g. one - * returned from **bpf_sk_lookup_xxx**\ (), - * **bpf_sk_fullsock**\ (), etc. The format of returned id is - * same as in **bpf_skb_cgroup_id**\ (). - * - * This helper is available only if the kernel was compiled with - * the **CONFIG_SOCK_CGROUP_DATA** configuration option. - * Return - * The id is returned or 0 in case the id could not be retrieved. - * - * u64 bpf_sk_ancestor_cgroup_id(void *sk, int ancestor_level) - * Description - * Return id of cgroup v2 that is ancestor of cgroup associated - * with the *sk* at the *ancestor_level*. The root cgroup is at - * *ancestor_level* zero and each step down the hierarchy - * increments the level. If *ancestor_level* == level of cgroup - * associated with *sk*, then return value will be same as that - * of **bpf_sk_cgroup_id**\ (). - * - * The helper is useful to implement policies based on cgroups - * that are upper in hierarchy than immediate cgroup associated - * with *sk*. - * - * The format of returned id and helper limitations are same as in - * **bpf_sk_cgroup_id**\ (). - * Return - * The id is returned or 0 in case the id could not be retrieved. - * - * long bpf_ringbuf_output(void *ringbuf, void *data, u64 size, u64 flags) - * Description - * Copy *size* bytes from *data* into a ring buffer *ringbuf*. - * If **BPF_RB_NO_WAKEUP** is specified in *flags*, no notification - * of new data availability is sent. - * If **BPF_RB_FORCE_WAKEUP** is specified in *flags*, notification - * of new data availability is sent unconditionally. - * Return - * 0 on success, or a negative error in case of failure. - * - * void *bpf_ringbuf_reserve(void *ringbuf, u64 size, u64 flags) - * Description - * Reserve *size* bytes of payload in a ring buffer *ringbuf*. - * Return - * Valid pointer with *size* bytes of memory available; NULL, - * otherwise. - * - * void bpf_ringbuf_submit(void *data, u64 flags) - * Description - * Submit reserved ring buffer sample, pointed to by *data*. - * If **BPF_RB_NO_WAKEUP** is specified in *flags*, no notification - * of new data availability is sent. - * If **BPF_RB_FORCE_WAKEUP** is specified in *flags*, notification - * of new data availability is sent unconditionally. - * Return - * Nothing. Always succeeds. - * - * void bpf_ringbuf_discard(void *data, u64 flags) - * Description - * Discard reserved ring buffer sample, pointed to by *data*. - * If **BPF_RB_NO_WAKEUP** is specified in *flags*, no notification - * of new data availability is sent. - * If **BPF_RB_FORCE_WAKEUP** is specified in *flags*, notification - * of new data availability is sent unconditionally. - * Return - * Nothing. Always succeeds. - * - * u64 bpf_ringbuf_query(void *ringbuf, u64 flags) - * Description - * Query various characteristics of provided ring buffer. What - * exactly is queries is determined by *flags*: - * - * * **BPF_RB_AVAIL_DATA**: Amount of data not yet consumed. - * * **BPF_RB_RING_SIZE**: The size of ring buffer. - * * **BPF_RB_CONS_POS**: Consumer position (can wrap around). - * * **BPF_RB_PROD_POS**: Producer(s) position (can wrap around). - * - * Data returned is just a momentary snapshot of actual values - * and could be inaccurate, so this facility should be used to - * power heuristics and for reporting, not to make 100% correct - * calculation. - * Return - * Requested value, or 0, if *flags* are not recognized. - * - * long bpf_csum_level(struct sk_buff *skb, u64 level) - * Description - * Change the skbs checksum level by one layer up or down, or - * reset it entirely to none in order to have the stack perform - * checksum validation. The level is applicable to the following - * protocols: TCP, UDP, GRE, SCTP, FCOE. For example, a decap of - * | ETH | IP | UDP | GUE | IP | TCP | into | ETH | IP | TCP | - * through **bpf_skb_adjust_room**\ () helper with passing in - * **BPF_F_ADJ_ROOM_NO_CSUM_RESET** flag would require one call - * to **bpf_csum_level**\ () with **BPF_CSUM_LEVEL_DEC** since - * the UDP header is removed. Similarly, an encap of the latter - * into the former could be accompanied by a helper call to - * **bpf_csum_level**\ () with **BPF_CSUM_LEVEL_INC** if the - * skb is still intended to be processed in higher layers of the - * stack instead of just egressing at tc. - * - * There are three supported level settings at this time: - * - * * **BPF_CSUM_LEVEL_INC**: Increases skb->csum_level for skbs - * with CHECKSUM_UNNECESSARY. - * * **BPF_CSUM_LEVEL_DEC**: Decreases skb->csum_level for skbs - * with CHECKSUM_UNNECESSARY. - * * **BPF_CSUM_LEVEL_RESET**: Resets skb->csum_level to 0 and - * sets CHECKSUM_NONE to force checksum validation by the stack. - * * **BPF_CSUM_LEVEL_QUERY**: No-op, returns the current - * skb->csum_level. - * Return - * 0 on success, or a negative error in case of failure. In the - * case of **BPF_CSUM_LEVEL_QUERY**, the current skb->csum_level - * is returned or the error code -EACCES in case the skb is not - * subject to CHECKSUM_UNNECESSARY. - * - * struct tcp6_sock *bpf_skc_to_tcp6_sock(void *sk) - * Description - * Dynamically cast a *sk* pointer to a *tcp6_sock* pointer. - * Return - * *sk* if casting is valid, or NULL otherwise. - * - * struct tcp_sock *bpf_skc_to_tcp_sock(void *sk) - * Description - * Dynamically cast a *sk* pointer to a *tcp_sock* pointer. - * Return - * *sk* if casting is valid, or NULL otherwise. - * - * struct tcp_timewait_sock *bpf_skc_to_tcp_timewait_sock(void *sk) - * Description - * Dynamically cast a *sk* pointer to a *tcp_timewait_sock* pointer. - * Return - * *sk* if casting is valid, or NULL otherwise. - * - * struct tcp_request_sock *bpf_skc_to_tcp_request_sock(void *sk) - * Description - * Dynamically cast a *sk* pointer to a *tcp_request_sock* pointer. - * Return - * *sk* if casting is valid, or NULL otherwise. - * - * struct udp6_sock *bpf_skc_to_udp6_sock(void *sk) - * Description - * Dynamically cast a *sk* pointer to a *udp6_sock* pointer. - * Return - * *sk* if casting is valid, or NULL otherwise. - * - * long bpf_get_task_stack(struct task_struct *task, void *buf, u32 size, u64 flags) - * Description - * Return a user or a kernel stack in bpf program provided buffer. - * Note: the user stack will only be populated if the *task* is - * the current task; all other tasks will return -EOPNOTSUPP. - * To achieve this, the helper needs *task*, which is a valid - * pointer to struct task_struct. To store the stacktrace, the - * bpf program provides *buf* with a nonnegative *size*. - * - * The last argument, *flags*, holds the number of stack frames to - * skip (from 0 to 255), masked with - * **BPF_F_SKIP_FIELD_MASK**. The next bits can be used to set - * the following flags: - * - * **BPF_F_USER_STACK** - * Collect a user space stack instead of a kernel stack. - * The *task* must be the current task. - * **BPF_F_USER_BUILD_ID** - * Collect buildid+offset instead of ips for user stack, - * only valid if **BPF_F_USER_STACK** is also specified. - * - * **bpf_get_task_stack**\ () can collect up to - * **PERF_MAX_STACK_DEPTH** both kernel and user frames, subject - * to sufficient large buffer size. Note that - * this limit can be controlled with the **sysctl** program, and - * that it should be manually increased in order to profile long - * user stacks (such as stacks for Java programs). To do so, use: - * - * :: - * - * # sysctl kernel.perf_event_max_stack= - * Return - * A non-negative value equal to or less than *size* on success, - * or a negative error in case of failure. - * - * long bpf_load_hdr_opt(struct bpf_sock_ops *skops, void *searchby_res, u32 len, u64 flags) - * Description - * Load header option. Support reading a particular TCP header - * option for bpf program (BPF_PROG_TYPE_SOCK_OPS). - * - * If *flags* is 0, it will search the option from the - * sock_ops->skb_data. The comment in "struct bpf_sock_ops" - * has details on what skb_data contains under different - * sock_ops->op. - * - * The first byte of the *searchby_res* specifies the - * kind that it wants to search. - * - * If the searching kind is an experimental kind - * (i.e. 253 or 254 according to RFC6994). It also - * needs to specify the "magic" which is either - * 2 bytes or 4 bytes. It then also needs to - * specify the size of the magic by using - * the 2nd byte which is "kind-length" of a TCP - * header option and the "kind-length" also - * includes the first 2 bytes "kind" and "kind-length" - * itself as a normal TCP header option also does. - * - * For example, to search experimental kind 254 with - * 2 byte magic 0xeB9F, the searchby_res should be - * [ 254, 4, 0xeB, 0x9F, 0, 0, .... 0 ]. - * - * To search for the standard window scale option (3), - * the searchby_res should be [ 3, 0, 0, .... 0 ]. - * Note, kind-length must be 0 for regular option. - * - * Searching for No-Op (0) and End-of-Option-List (1) are - * not supported. - * - * *len* must be at least 2 bytes which is the minimal size - * of a header option. - * - * Supported flags: - * * **BPF_LOAD_HDR_OPT_TCP_SYN** to search from the - * saved_syn packet or the just-received syn packet. - * - * Return - * >0 when found, the header option is copied to *searchby_res*. - * The return value is the total length copied. - * - * **-EINVAL** If param is invalid - * - * **-ENOMSG** The option is not found - * - * **-ENOENT** No syn packet available when - * **BPF_LOAD_HDR_OPT_TCP_SYN** is used - * - * **-ENOSPC** Not enough space. Only *len* number of - * bytes are copied. - * - * **-EFAULT** Cannot parse the header options in the packet - * - * **-EPERM** This helper cannot be used under the - * current sock_ops->op. - * - * long bpf_store_hdr_opt(struct bpf_sock_ops *skops, const void *from, u32 len, u64 flags) - * Description - * Store header option. The data will be copied - * from buffer *from* with length *len* to the TCP header. - * - * The buffer *from* should have the whole option that - * includes the kind, kind-length, and the actual - * option data. The *len* must be at least kind-length - * long. The kind-length does not have to be 4 byte - * aligned. The kernel will take care of the padding - * and setting the 4 bytes aligned value to th->doff. - * - * This helper will check for duplicated option - * by searching the same option in the outgoing skb. - * - * This helper can only be called during - * BPF_SOCK_OPS_WRITE_HDR_OPT_CB. - * - * Return - * 0 on success, or negative error in case of failure: - * - * **-EINVAL** If param is invalid - * - * **-ENOSPC** Not enough space in the header. - * Nothing has been written - * - * **-EEXIST** The option has already existed - * - * **-EFAULT** Cannot parse the existing header options - * - * **-EPERM** This helper cannot be used under the - * current sock_ops->op. - * - * long bpf_reserve_hdr_opt(struct bpf_sock_ops *skops, u32 len, u64 flags) - * Description - * Reserve *len* bytes for the bpf header option. The - * space will be used by bpf_store_hdr_opt() later in - * BPF_SOCK_OPS_WRITE_HDR_OPT_CB. - * - * If bpf_reserve_hdr_opt() is called multiple times, - * the total number of bytes will be reserved. - * - * This helper can only be called during - * BPF_SOCK_OPS_HDR_OPT_LEN_CB. - * - * Return - * 0 on success, or negative error in case of failure: - * - * **-EINVAL** if param is invalid - * - * **-ENOSPC** Not enough space in the header. - * - * **-EPERM** This helper cannot be used under the - * current sock_ops->op. - * - * void *bpf_inode_storage_get(struct bpf_map *map, void *inode, void *value, u64 flags) - * Description - * Get a bpf_local_storage from an *inode*. - * - * Logically, it could be thought of as getting the value from - * a *map* with *inode* as the **key**. From this - * perspective, the usage is not much different from - * **bpf_map_lookup_elem**\ (*map*, **&**\ *inode*) except this - * helper enforces the key must be an inode and the map must also - * be a **BPF_MAP_TYPE_INODE_STORAGE**. - * - * Underneath, the value is stored locally at *inode* instead of - * the *map*. The *map* is used as the bpf-local-storage - * "type". The bpf-local-storage "type" (i.e. the *map*) is - * searched against all bpf_local_storage residing at *inode*. - * - * An optional *flags* (**BPF_LOCAL_STORAGE_GET_F_CREATE**) can be - * used such that a new bpf_local_storage will be - * created if one does not exist. *value* can be used - * together with **BPF_LOCAL_STORAGE_GET_F_CREATE** to specify - * the initial value of a bpf_local_storage. If *value* is - * **NULL**, the new bpf_local_storage will be zero initialized. - * Return - * A bpf_local_storage pointer is returned on success. - * - * **NULL** if not found or there was an error in adding - * a new bpf_local_storage. - * - * int bpf_inode_storage_delete(struct bpf_map *map, void *inode) - * Description - * Delete a bpf_local_storage from an *inode*. - * Return - * 0 on success. - * - * **-ENOENT** if the bpf_local_storage cannot be found. - * - * long bpf_d_path(struct path *path, char *buf, u32 sz) - * Description - * Return full path for given 'struct path' object, which - * needs to be the kernel BTF 'path' object. The path is - * returned in the provided buffer 'buf' of size 'sz' and - * is zero terminated. - * - * Return - * On success, the strictly positive length of the string, - * including the trailing NUL character. On error, a negative - * value. - * - * long bpf_copy_from_user(void *dst, u32 size, const void *user_ptr) - * Description - * Read *size* bytes from user space address *user_ptr* and store - * the data in *dst*. This is a wrapper of copy_from_user(). - * Return - * 0 on success, or a negative error in case of failure. - * - * long bpf_snprintf_btf(char *str, u32 str_size, struct btf_ptr *ptr, u32 btf_ptr_size, u64 flags) - * Description - * Use BTF to store a string representation of *ptr*->ptr in *str*, - * using *ptr*->type_id. This value should specify the type - * that *ptr*->ptr points to. LLVM __builtin_btf_type_id(type, 1) - * can be used to look up vmlinux BTF type ids. Traversing the - * data structure using BTF, the type information and values are - * stored in the first *str_size* - 1 bytes of *str*. Safe copy of - * the pointer data is carried out to avoid kernel crashes during - * operation. Smaller types can use string space on the stack; - * larger programs can use map data to store the string - * representation. - * - * The string can be subsequently shared with userspace via - * bpf_perf_event_output() or ring buffer interfaces. - * bpf_trace_printk() is to be avoided as it places too small - * a limit on string size to be useful. - * - * *flags* is a combination of - * - * **BTF_F_COMPACT** - * no formatting around type information - * **BTF_F_NONAME** - * no struct/union member names/types - * **BTF_F_PTR_RAW** - * show raw (unobfuscated) pointer values; - * equivalent to printk specifier %px. - * **BTF_F_ZERO** - * show zero-valued struct/union members; they - * are not displayed by default - * - * Return - * The number of bytes that were written (or would have been - * written if output had to be truncated due to string size), - * or a negative error in cases of failure. - * - * long bpf_seq_printf_btf(struct seq_file *m, struct btf_ptr *ptr, u32 ptr_size, u64 flags) - * Description - * Use BTF to write to seq_write a string representation of - * *ptr*->ptr, using *ptr*->type_id as per bpf_snprintf_btf(). - * *flags* are identical to those used for bpf_snprintf_btf. - * Return - * 0 on success or a negative error in case of failure. - * - * u64 bpf_skb_cgroup_classid(struct sk_buff *skb) - * Description - * See **bpf_get_cgroup_classid**\ () for the main description. - * This helper differs from **bpf_get_cgroup_classid**\ () in that - * the cgroup v1 net_cls class is retrieved only from the *skb*'s - * associated socket instead of the current process. - * Return - * The id is returned or 0 in case the id could not be retrieved. - * - * long bpf_redirect_neigh(u32 ifindex, struct bpf_redir_neigh *params, int plen, u64 flags) - * Description - * Redirect the packet to another net device of index *ifindex* - * and fill in L2 addresses from neighboring subsystem. This helper - * is somewhat similar to **bpf_redirect**\ (), except that it - * populates L2 addresses as well, meaning, internally, the helper - * relies on the neighbor lookup for the L2 address of the nexthop. - * - * The helper will perform a FIB lookup based on the skb's - * networking header to get the address of the next hop, unless - * this is supplied by the caller in the *params* argument. The - * *plen* argument indicates the len of *params* and should be set - * to 0 if *params* is NULL. - * - * The *flags* argument is reserved and must be 0. The helper is - * currently only supported for tc BPF program types, and enabled - * for IPv4 and IPv6 protocols. - * Return - * The helper returns **TC_ACT_REDIRECT** on success or - * **TC_ACT_SHOT** on error. - * - * void *bpf_per_cpu_ptr(const void *percpu_ptr, u32 cpu) - * Description - * Take a pointer to a percpu ksym, *percpu_ptr*, and return a - * pointer to the percpu kernel variable on *cpu*. A ksym is an - * extern variable decorated with '__ksym'. For ksym, there is a - * global var (either static or global) defined of the same name - * in the kernel. The ksym is percpu if the global var is percpu. - * The returned pointer points to the global percpu var on *cpu*. - * - * bpf_per_cpu_ptr() has the same semantic as per_cpu_ptr() in the - * kernel, except that bpf_per_cpu_ptr() may return NULL. This - * happens if *cpu* is larger than nr_cpu_ids. The caller of - * bpf_per_cpu_ptr() must check the returned value. - * Return - * A pointer pointing to the kernel percpu variable on *cpu*, or - * NULL, if *cpu* is invalid. - * - * void *bpf_this_cpu_ptr(const void *percpu_ptr) - * Description - * Take a pointer to a percpu ksym, *percpu_ptr*, and return a - * pointer to the percpu kernel variable on this cpu. See the - * description of 'ksym' in **bpf_per_cpu_ptr**\ (). - * - * bpf_this_cpu_ptr() has the same semantic as this_cpu_ptr() in - * the kernel. Different from **bpf_per_cpu_ptr**\ (), it would - * never return NULL. - * Return - * A pointer pointing to the kernel percpu variable on this cpu. - * - * long bpf_redirect_peer(u32 ifindex, u64 flags) - * Description - * Redirect the packet to another net device of index *ifindex*. - * This helper is somewhat similar to **bpf_redirect**\ (), except - * that the redirection happens to the *ifindex*' peer device and - * the netns switch takes place from ingress to ingress without - * going through the CPU's backlog queue. - * - * The *flags* argument is reserved and must be 0. The helper is - * currently only supported for tc BPF program types at the ingress - * hook and for veth device types. The peer device must reside in a - * different network namespace. - * Return - * The helper returns **TC_ACT_REDIRECT** on success or - * **TC_ACT_SHOT** on error. */ #define __BPF_FUNC_MAPPER(FN) \ FN(unspec), \ @@ -3842,38 +2889,7 @@ union bpf_attr { FN(get_netns_cookie), \ FN(get_current_ancestor_cgroup_id), \ FN(sk_assign), \ - FN(ktime_get_boot_ns), \ - FN(seq_printf), \ - FN(seq_write), \ - FN(sk_cgroup_id), \ - FN(sk_ancestor_cgroup_id), \ - FN(ringbuf_output), \ - FN(ringbuf_reserve), \ - FN(ringbuf_submit), \ - FN(ringbuf_discard), \ - FN(ringbuf_query), \ - FN(csum_level), \ - FN(skc_to_tcp6_sock), \ - FN(skc_to_tcp_sock), \ - FN(skc_to_tcp_timewait_sock), \ - FN(skc_to_tcp_request_sock), \ - FN(skc_to_udp6_sock), \ - FN(get_task_stack), \ - FN(load_hdr_opt), \ - FN(store_hdr_opt), \ - FN(reserve_hdr_opt), \ - FN(inode_storage_get), \ - FN(inode_storage_delete), \ - FN(d_path), \ - FN(copy_from_user), \ - FN(snprintf_btf), \ - FN(seq_printf_btf), \ - FN(skb_cgroup_classid), \ - FN(redirect_neigh), \ - FN(per_cpu_ptr), \ - FN(this_cpu_ptr), \ - FN(redirect_peer), \ - /* */ + FN(ktime_get_boot_ns), /* integer value in 'imm' field of BPF_CALL instruction selects which helper * function eBPF program intends to call @@ -3888,143 +2904,69 @@ enum bpf_func_id { /* All flags used by eBPF helper functions, placed here. */ /* BPF_FUNC_skb_store_bytes flags. */ -enum { - BPF_F_RECOMPUTE_CSUM = (1ULL << 0), - BPF_F_INVALIDATE_HASH = (1ULL << 1), -}; +#define BPF_F_RECOMPUTE_CSUM (1ULL << 0) +#define BPF_F_INVALIDATE_HASH (1ULL << 1) /* BPF_FUNC_l3_csum_replace and BPF_FUNC_l4_csum_replace flags. * First 4 bits are for passing the header field size. */ -enum { - BPF_F_HDR_FIELD_MASK = 0xfULL, -}; +#define BPF_F_HDR_FIELD_MASK 0xfULL /* BPF_FUNC_l4_csum_replace flags. */ -enum { - BPF_F_PSEUDO_HDR = (1ULL << 4), - BPF_F_MARK_MANGLED_0 = (1ULL << 5), - BPF_F_MARK_ENFORCE = (1ULL << 6), - BPF_F_IPV6 = (1ULL << 7), -}; +#define BPF_F_PSEUDO_HDR (1ULL << 4) +#define BPF_F_MARK_MANGLED_0 (1ULL << 5) +#define BPF_F_MARK_ENFORCE (1ULL << 6) /* BPF_FUNC_clone_redirect and BPF_FUNC_redirect flags. */ -enum { - BPF_F_INGRESS = (1ULL << 0), -}; +#define BPF_F_INGRESS (1ULL << 0) /* BPF_FUNC_skb_set_tunnel_key and BPF_FUNC_skb_get_tunnel_key flags. */ -enum { - BPF_F_TUNINFO_IPV6 = (1ULL << 0), -}; +#define BPF_F_TUNINFO_IPV6 (1ULL << 0) /* flags for both BPF_FUNC_get_stackid and BPF_FUNC_get_stack. */ -enum { - BPF_F_SKIP_FIELD_MASK = 0xffULL, - BPF_F_USER_STACK = (1ULL << 8), +#define BPF_F_SKIP_FIELD_MASK 0xffULL +#define BPF_F_USER_STACK (1ULL << 8) /* flags used by BPF_FUNC_get_stackid only. */ - BPF_F_FAST_STACK_CMP = (1ULL << 9), - BPF_F_REUSE_STACKID = (1ULL << 10), +#define BPF_F_FAST_STACK_CMP (1ULL << 9) +#define BPF_F_REUSE_STACKID (1ULL << 10) /* flags used by BPF_FUNC_get_stack only. */ - BPF_F_USER_BUILD_ID = (1ULL << 11), -}; +#define BPF_F_USER_BUILD_ID (1ULL << 11) /* BPF_FUNC_skb_set_tunnel_key flags. */ -enum { - BPF_F_ZERO_CSUM_TX = (1ULL << 1), - BPF_F_DONT_FRAGMENT = (1ULL << 2), - BPF_F_SEQ_NUMBER = (1ULL << 3), -}; +#define BPF_F_ZERO_CSUM_TX (1ULL << 1) +#define BPF_F_DONT_FRAGMENT (1ULL << 2) +#define BPF_F_SEQ_NUMBER (1ULL << 3) /* BPF_FUNC_perf_event_output, BPF_FUNC_perf_event_read and * BPF_FUNC_perf_event_read_value flags. */ -enum { - BPF_F_INDEX_MASK = 0xffffffffULL, - BPF_F_CURRENT_CPU = BPF_F_INDEX_MASK, +#define BPF_F_INDEX_MASK 0xffffffffULL +#define BPF_F_CURRENT_CPU BPF_F_INDEX_MASK /* BPF_FUNC_perf_event_output for sk_buff input context. */ - BPF_F_CTXLEN_MASK = (0xfffffULL << 32), -}; +#define BPF_F_CTXLEN_MASK (0xfffffULL << 32) /* Current network namespace */ -enum { - BPF_F_CURRENT_NETNS = (-1L), -}; - -/* BPF_FUNC_csum_level level values. */ -enum { - BPF_CSUM_LEVEL_QUERY, - BPF_CSUM_LEVEL_INC, - BPF_CSUM_LEVEL_DEC, - BPF_CSUM_LEVEL_RESET, -}; +#define BPF_F_CURRENT_NETNS (-1L) /* BPF_FUNC_skb_adjust_room flags. */ -enum { - BPF_F_ADJ_ROOM_FIXED_GSO = (1ULL << 0), - BPF_F_ADJ_ROOM_ENCAP_L3_IPV4 = (1ULL << 1), - BPF_F_ADJ_ROOM_ENCAP_L3_IPV6 = (1ULL << 2), - BPF_F_ADJ_ROOM_ENCAP_L4_GRE = (1ULL << 3), - BPF_F_ADJ_ROOM_ENCAP_L4_UDP = (1ULL << 4), - BPF_F_ADJ_ROOM_NO_CSUM_RESET = (1ULL << 5), -}; +#define BPF_F_ADJ_ROOM_FIXED_GSO (1ULL << 0) -enum { - BPF_ADJ_ROOM_ENCAP_L2_MASK = 0xff, - BPF_ADJ_ROOM_ENCAP_L2_SHIFT = 56, -}; +#define BPF_ADJ_ROOM_ENCAP_L2_MASK 0xff +#define BPF_ADJ_ROOM_ENCAP_L2_SHIFT 56 +#define BPF_F_ADJ_ROOM_ENCAP_L3_IPV4 (1ULL << 1) +#define BPF_F_ADJ_ROOM_ENCAP_L3_IPV6 (1ULL << 2) +#define BPF_F_ADJ_ROOM_ENCAP_L4_GRE (1ULL << 3) +#define BPF_F_ADJ_ROOM_ENCAP_L4_UDP (1ULL << 4) #define BPF_F_ADJ_ROOM_ENCAP_L2(len) (((__u64)len & \ BPF_ADJ_ROOM_ENCAP_L2_MASK) \ << BPF_ADJ_ROOM_ENCAP_L2_SHIFT) /* BPF_FUNC_sysctl_get_name flags. */ -enum { - BPF_F_SYSCTL_BASE_NAME = (1ULL << 0), -}; +#define BPF_F_SYSCTL_BASE_NAME (1ULL << 0) -/* BPF_FUNC__storage_get flags */ -enum { - BPF_LOCAL_STORAGE_GET_F_CREATE = (1ULL << 0), - /* BPF_SK_STORAGE_GET_F_CREATE is only kept for backward compatibility - * and BPF_LOCAL_STORAGE_GET_F_CREATE must be used instead. - */ - BPF_SK_STORAGE_GET_F_CREATE = BPF_LOCAL_STORAGE_GET_F_CREATE, -}; - -/* BPF_FUNC_read_branch_records flags. */ -enum { - BPF_F_GET_BRANCH_RECORDS_SIZE = (1ULL << 0), -}; - -/* BPF_FUNC_bpf_ringbuf_commit, BPF_FUNC_bpf_ringbuf_discard, and - * BPF_FUNC_bpf_ringbuf_output flags. - */ -enum { - BPF_RB_NO_WAKEUP = (1ULL << 0), - BPF_RB_FORCE_WAKEUP = (1ULL << 1), -}; - -/* BPF_FUNC_bpf_ringbuf_query flags */ -enum { - BPF_RB_AVAIL_DATA = 0, - BPF_RB_RING_SIZE = 1, - BPF_RB_CONS_POS = 2, - BPF_RB_PROD_POS = 3, -}; - -/* BPF ring buffer constants */ -enum { - BPF_RINGBUF_BUSY_BIT = (1U << 31), - BPF_RINGBUF_DISCARD_BIT = (1U << 30), - BPF_RINGBUF_HDR_SZ = 8, -}; - -/* BPF_FUNC_sk_assign flags in bpf_sk_lookup context. */ -enum { - BPF_SK_LOOKUP_F_REPLACE = (1ULL << 0), - BPF_SK_LOOKUP_F_NO_REUSEPORT = (1ULL << 1), -}; +/* BPF_FUNC_sk_storage_get flags */ +#define BPF_SK_STORAGE_GET_F_CREATE (1ULL << 0) /* Mode for BPF_FUNC_skb_adjust_room helper. */ enum bpf_adj_room_mode { @@ -4251,34 +3193,6 @@ struct xdp_md { /* Below access go through struct xdp_rxq_info */ __u32 ingress_ifindex; /* rxq->dev->ifindex */ __u32 rx_queue_index; /* rxq->queue_index */ - - __u32 egress_ifindex; /* txq->dev->ifindex */ -}; - -/* DEVMAP map-value layout - * - * The struct data-layout of map-value is a configuration interface. - * New members can only be added to the end of this structure. - */ -struct bpf_devmap_val { - __u32 ifindex; /* device index */ - union { - int fd; /* prog fd on map write */ - __u32 id; /* prog id on map read */ - } bpf_prog; -}; - -/* CPUMAP map-value layout - * - * The struct data-layout of map-value is a configuration interface. - * New members can only be added to the end of this structure. - */ -struct bpf_cpumap_val { - __u32 qsize; /* queue size to remote target CPU */ - union { - int fd; /* prog fd on map write */ - __u32 id; /* prog id on map read */ - } bpf_prog; }; enum sk_action { @@ -4301,8 +3215,6 @@ struct sk_msg_md { __u32 remote_port; /* Stored in network byte order */ __u32 local_port; /* stored in host byte order */ __u32 size; /* Total size of sk_msg */ - - __bpf_md_ptr(struct bpf_sock *, sk); /* current socket */ }; struct sk_reuseport_md { @@ -4379,7 +3291,7 @@ struct bpf_map_info { __u32 map_flags; char name[BPF_OBJ_NAME_LEN]; __u32 ifindex; - __u32 btf_vmlinux_value_type_id; + __u32 :32; __u64 netns_dev; __u64 netns_ino; __u32 btf_id; @@ -4393,41 +3305,9 @@ struct bpf_btf_info { __u32 id; } __attribute__((aligned(8))); -struct bpf_link_info { - __u32 type; - __u32 id; - __u32 prog_id; - union { - struct { - __aligned_u64 tp_name; /* in/out: tp_name buffer ptr */ - __u32 tp_name_len; /* in/out: tp_name buffer len */ - } raw_tracepoint; - struct { - __u32 attach_type; - } tracing; - struct { - __u64 cgroup_id; - __u32 attach_type; - } cgroup; - struct { - __aligned_u64 target_name; /* in/out: target_name buffer ptr */ - __u32 target_name_len; /* in/out: target_name buffer len */ - union { - struct { - __u32 map_id; - } map; - }; - } iter; - struct { - __u32 netns_ino; - __u32 attach_type; - } netns; - }; -} __attribute__((aligned(8))); - /* User bpf_sock_addr struct to access socket fields and sockaddr struct passed * by user and intended to be used by socket (e.g. to bind to, depends on - * attach type). + * attach attach type). */ struct bpf_sock_addr { __u32 user_family; /* Allows 4-byte read, but no write. */ @@ -4437,7 +3317,7 @@ struct bpf_sock_addr { __u32 user_ip6[4]; /* Allows 1,2,4,8-byte read and 4,8-byte write. * Stored in network byte order. */ - __u32 user_port; /* Allows 1,2,4-byte read and 4-byte write. + __u32 user_port; /* Allows 4-byte read and write. * Stored in network byte order */ __u32 family; /* Allows 4-byte read, but no write */ @@ -4502,90 +3382,16 @@ struct bpf_sock_ops { __u64 bytes_received; __u64 bytes_acked; __bpf_md_ptr(struct bpf_sock *, sk); - /* [skb_data, skb_data_end) covers the whole TCP header. - * - * BPF_SOCK_OPS_PARSE_HDR_OPT_CB: The packet received - * BPF_SOCK_OPS_HDR_OPT_LEN_CB: Not useful because the - * header has not been written. - * BPF_SOCK_OPS_WRITE_HDR_OPT_CB: The header and options have - * been written so far. - * BPF_SOCK_OPS_ACTIVE_ESTABLISHED_CB: The SYNACK that concludes - * the 3WHS. - * BPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB: The ACK that concludes - * the 3WHS. - * - * bpf_load_hdr_opt() can also be used to read a particular option. - */ - __bpf_md_ptr(void *, skb_data); - __bpf_md_ptr(void *, skb_data_end); - __u32 skb_len; /* The total length of a packet. - * It includes the header, options, - * and payload. - */ - __u32 skb_tcp_flags; /* tcp_flags of the header. It provides - * an easy way to check for tcp_flags - * without parsing skb_data. - * - * In particular, the skb_tcp_flags - * will still be available in - * BPF_SOCK_OPS_HDR_OPT_LEN even though - * the outgoing header has not - * been written yet. - */ }; /* Definitions for bpf_sock_ops_cb_flags */ -enum { - BPF_SOCK_OPS_RTO_CB_FLAG = (1<<0), - BPF_SOCK_OPS_RETRANS_CB_FLAG = (1<<1), - BPF_SOCK_OPS_STATE_CB_FLAG = (1<<2), - BPF_SOCK_OPS_RTT_CB_FLAG = (1<<3), - /* Call bpf for all received TCP headers. The bpf prog will be - * called under sock_ops->op == BPF_SOCK_OPS_PARSE_HDR_OPT_CB - * - * Please refer to the comment in BPF_SOCK_OPS_PARSE_HDR_OPT_CB - * for the header option related helpers that will be useful - * to the bpf programs. - * - * It could be used at the client/active side (i.e. connect() side) - * when the server told it that the server was in syncookie - * mode and required the active side to resend the bpf-written - * options. The active side can keep writing the bpf-options until - * it received a valid packet from the server side to confirm - * the earlier packet (and options) has been received. The later - * example patch is using it like this at the active side when the - * server is in syncookie mode. - * - * The bpf prog will usually turn this off in the common cases. - */ - BPF_SOCK_OPS_PARSE_ALL_HDR_OPT_CB_FLAG = (1<<4), - /* Call bpf when kernel has received a header option that - * the kernel cannot handle. The bpf prog will be called under - * sock_ops->op == BPF_SOCK_OPS_PARSE_HDR_OPT_CB. - * - * Please refer to the comment in BPF_SOCK_OPS_PARSE_HDR_OPT_CB - * for the header option related helpers that will be useful - * to the bpf programs. - */ - BPF_SOCK_OPS_PARSE_UNKNOWN_HDR_OPT_CB_FLAG = (1<<5), - /* Call bpf when the kernel is writing header options for the - * outgoing packet. The bpf prog will first be called - * to reserve space in a skb under - * sock_ops->op == BPF_SOCK_OPS_HDR_OPT_LEN_CB. Then - * the bpf prog will be called to write the header option(s) - * under sock_ops->op == BPF_SOCK_OPS_WRITE_HDR_OPT_CB. - * - * Please refer to the comment in BPF_SOCK_OPS_HDR_OPT_LEN_CB - * and BPF_SOCK_OPS_WRITE_HDR_OPT_CB for the header option - * related helpers that will be useful to the bpf programs. - * - * The kernel gets its chance to reserve space and write - * options first before the BPF program does. - */ - BPF_SOCK_OPS_WRITE_HDR_OPT_CB_FLAG = (1<<6), -/* Mask of all currently supported cb flags */ - BPF_SOCK_OPS_ALL_CB_FLAGS = 0x7F, -}; +#define BPF_SOCK_OPS_RTO_CB_FLAG (1<<0) +#define BPF_SOCK_OPS_RETRANS_CB_FLAG (1<<1) +#define BPF_SOCK_OPS_STATE_CB_FLAG (1<<2) +#define BPF_SOCK_OPS_RTT_CB_FLAG (1<<3) +#define BPF_SOCK_OPS_ALL_CB_FLAGS 0xF /* Mask of all currently + * supported cb flags + */ /* List of known BPF sock_ops operators. * New entries can only be added at the end @@ -4640,63 +3446,6 @@ enum { */ BPF_SOCK_OPS_RTT_CB, /* Called on every RTT. */ - BPF_SOCK_OPS_PARSE_HDR_OPT_CB, /* Parse the header option. - * It will be called to handle - * the packets received at - * an already established - * connection. - * - * sock_ops->skb_data: - * Referring to the received skb. - * It covers the TCP header only. - * - * bpf_load_hdr_opt() can also - * be used to search for a - * particular option. - */ - BPF_SOCK_OPS_HDR_OPT_LEN_CB, /* Reserve space for writing the - * header option later in - * BPF_SOCK_OPS_WRITE_HDR_OPT_CB. - * Arg1: bool want_cookie. (in - * writing SYNACK only) - * - * sock_ops->skb_data: - * Not available because no header has - * been written yet. - * - * sock_ops->skb_tcp_flags: - * The tcp_flags of the - * outgoing skb. (e.g. SYN, ACK, FIN). - * - * bpf_reserve_hdr_opt() should - * be used to reserve space. - */ - BPF_SOCK_OPS_WRITE_HDR_OPT_CB, /* Write the header options - * Arg1: bool want_cookie. (in - * writing SYNACK only) - * - * sock_ops->skb_data: - * Referring to the outgoing skb. - * It covers the TCP header - * that has already been written - * by the kernel and the - * earlier bpf-progs. - * - * sock_ops->skb_tcp_flags: - * The tcp_flags of the outgoing - * skb. (e.g. SYN, ACK, FIN). - * - * bpf_store_hdr_opt() should - * be used to write the - * option. - * - * bpf_load_hdr_opt() can also - * be used to search for a - * particular option that - * has already been written - * by the kernel or the - * earlier bpf-progs. - */ }; /* List of TCP states. There is a build check in net/ipv4/tcp.c to detect @@ -4721,67 +3470,8 @@ enum { BPF_TCP_MAX_STATES /* Leave at the end! */ }; -enum { - TCP_BPF_IW = 1001, /* Set TCP initial congestion window */ - TCP_BPF_SNDCWND_CLAMP = 1002, /* Set sndcwnd_clamp */ - TCP_BPF_DELACK_MAX = 1003, /* Max delay ack in usecs */ - TCP_BPF_RTO_MIN = 1004, /* Min delay ack in usecs */ - /* Copy the SYN pkt to optval - * - * BPF_PROG_TYPE_SOCK_OPS only. It is similar to the - * bpf_getsockopt(TCP_SAVED_SYN) but it does not limit - * to only getting from the saved_syn. It can either get the - * syn packet from: - * - * 1. the just-received SYN packet (only available when writing the - * SYNACK). It will be useful when it is not necessary to - * save the SYN packet for latter use. It is also the only way - * to get the SYN during syncookie mode because the syn - * packet cannot be saved during syncookie. - * - * OR - * - * 2. the earlier saved syn which was done by - * bpf_setsockopt(TCP_SAVE_SYN). - * - * The bpf_getsockopt(TCP_BPF_SYN*) option will hide where the - * SYN packet is obtained. - * - * If the bpf-prog does not need the IP[46] header, the - * bpf-prog can avoid parsing the IP header by using - * TCP_BPF_SYN. Otherwise, the bpf-prog can get both - * IP[46] and TCP header by using TCP_BPF_SYN_IP. - * - * >0: Total number of bytes copied - * -ENOSPC: Not enough space in optval. Only optlen number of - * bytes is copied. - * -ENOENT: The SYN skb is not available now and the earlier SYN pkt - * is not saved by setsockopt(TCP_SAVE_SYN). - */ - TCP_BPF_SYN = 1005, /* Copy the TCP header */ - TCP_BPF_SYN_IP = 1006, /* Copy the IP[46] and TCP header */ - TCP_BPF_SYN_MAC = 1007, /* Copy the MAC, IP[46], and TCP header */ -}; - -enum { - BPF_LOAD_HDR_OPT_TCP_SYN = (1ULL << 0), -}; - -/* args[0] value during BPF_SOCK_OPS_HDR_OPT_LEN_CB and - * BPF_SOCK_OPS_WRITE_HDR_OPT_CB. - */ -enum { - BPF_WRITE_HDR_TCP_CURRENT_MSS = 1, /* Kernel is finding the - * total option spaces - * required for an established - * sk in order to calculate the - * MSS. No skb is actually - * sent. - */ - BPF_WRITE_HDR_TCP_SYNACK_COOKIE = 2, /* Kernel is in syncookie mode - * when sending a SYN. - */ -}; +#define TCP_BPF_IW 1001 /* Set TCP initial congestion window */ +#define TCP_BPF_SNDCWND_CLAMP 1002 /* Set sndcwnd_clamp */ struct bpf_perf_event_value { __u64 counter; @@ -4789,16 +3479,12 @@ struct bpf_perf_event_value { __u64 running; }; -enum { - BPF_DEVCG_ACC_MKNOD = (1ULL << 0), - BPF_DEVCG_ACC_READ = (1ULL << 1), - BPF_DEVCG_ACC_WRITE = (1ULL << 2), -}; +#define BPF_DEVCG_ACC_MKNOD (1ULL << 0) +#define BPF_DEVCG_ACC_READ (1ULL << 1) +#define BPF_DEVCG_ACC_WRITE (1ULL << 2) -enum { - BPF_DEVCG_DEV_BLOCK = (1ULL << 0), - BPF_DEVCG_DEV_CHAR = (1ULL << 1), -}; +#define BPF_DEVCG_DEV_BLOCK (1ULL << 0) +#define BPF_DEVCG_DEV_CHAR (1ULL << 1) struct bpf_cgroup_dev_ctx { /* access_type encoded as (BPF_DEVCG_ACC_* << 16) | BPF_DEVCG_DEV_* */ @@ -4814,10 +3500,8 @@ struct bpf_raw_tracepoint_args { /* DIRECT: Skip the FIB rules and go to FIB table associated with device * OUTPUT: Do lookup from egress perspective; default is ingress */ -enum { - BPF_FIB_LOOKUP_DIRECT = (1U << 0), - BPF_FIB_LOOKUP_OUTPUT = (1U << 1), -}; +#define BPF_FIB_LOOKUP_DIRECT (1U << 0) +#define BPF_FIB_LOOKUP_OUTPUT (1U << 1) enum { BPF_FIB_LKUP_RET_SUCCESS, /* lookup successful */ @@ -4880,16 +3564,6 @@ struct bpf_fib_lookup { __u8 dmac[6]; /* ETH_ALEN */ }; -struct bpf_redir_neigh { - /* network family for lookup (AF_INET, AF_INET6) */ - __u32 nh_family; - /* network address of nexthop; skips fib lookup to find gateway */ - union { - __be32 ipv4_nh; - __u32 ipv6_nh[4]; /* in6_addr; network order */ - }; -}; - enum bpf_task_fd_type { BPF_FD_TYPE_RAW_TRACEPOINT, /* tp name */ BPF_FD_TYPE_TRACEPOINT, /* tp name */ @@ -4899,11 +3573,9 @@ enum bpf_task_fd_type { BPF_FD_TYPE_URETPROBE, /* filename + offset */ }; -enum { - BPF_FLOW_DISSECTOR_F_PARSE_1ST_FRAG = (1U << 0), - BPF_FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL = (1U << 1), - BPF_FLOW_DISSECTOR_F_STOP_AT_ENCAP = (1U << 2), -}; +#define BPF_FLOW_DISSECTOR_F_PARSE_1ST_FRAG (1U << 0) +#define BPF_FLOW_DISSECTOR_F_STOP_AT_FLOW_LABEL (1U << 1) +#define BPF_FLOW_DISSECTOR_F_STOP_AT_ENCAP (1U << 2) struct bpf_flow_keys { __u16 nhoff; @@ -4969,53 +3641,4 @@ struct bpf_sockopt { __s32 retval; }; -struct bpf_pidns_info { - __u32 pid; - __u32 tgid; -}; - -/* User accessible data for SK_LOOKUP programs. Add new fields at the end. */ -struct bpf_sk_lookup { - __bpf_md_ptr(struct bpf_sock *, sk); /* Selected socket */ - - __u32 family; /* Protocol family (AF_INET, AF_INET6) */ - __u32 protocol; /* IP protocol (IPPROTO_TCP, IPPROTO_UDP) */ - __u32 remote_ip4; /* Network byte order */ - __u32 remote_ip6[4]; /* Network byte order */ - __u32 remote_port; /* Network byte order */ - __u32 local_ip4; /* Network byte order */ - __u32 local_ip6[4]; /* Network byte order */ - __u32 local_port; /* Host byte order */ -}; - -/* - * struct btf_ptr is used for typed pointer representation; the - * type id is used to render the pointer data as the appropriate type - * via the bpf_snprintf_btf() helper described above. A flags field - - * potentially to specify additional details about the BTF pointer - * (rather than its mode of display) - is included for future use. - * Display flags - BTF_F_* - are passed to bpf_snprintf_btf separately. - */ -struct btf_ptr { - void *ptr; - __u32 type_id; - __u32 flags; /* BTF ptr flags; unused at present. */ -}; - -/* - * Flags to control bpf_snprintf_btf() behaviour. - * - BTF_F_COMPACT: no formatting around type information - * - BTF_F_NONAME: no struct/union member names/types - * - BTF_F_PTR_RAW: show raw (unobfuscated) pointer values; - * equivalent to %px. - * - BTF_F_ZERO: show zero-valued struct/union members; they - * are not displayed by default - */ -enum { - BTF_F_COMPACT = (1ULL << 0), - BTF_F_NONAME = (1ULL << 1), - BTF_F_PTR_RAW = (1ULL << 2), - BTF_F_ZERO = (1ULL << 3), -}; - #endif /* _UAPI__LINUX_BPF_H__ */ diff --git a/tools/lib/bpf/.gitignore b/tools/lib/bpf/.gitignore index 12382b0c71c7..d9e9dec04605 100644 --- a/tools/lib/bpf/.gitignore +++ b/tools/lib/bpf/.gitignore @@ -3,6 +3,3 @@ libbpf.pc FEATURE-DUMP.libbpf test_libbpf libbpf.so.* -TAGS -tags -cscope.* diff --git a/tools/lib/bpf/Makefile b/tools/lib/bpf/Makefile index 1b5cc1eafd22..9758bfa59232 100644 --- a/tools/lib/bpf/Makefile +++ b/tools/lib/bpf/Makefile @@ -1,9 +1,6 @@ # SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) # Most of this file is copied from tools/lib/traceevent/Makefile -RM ?= rm -srctree = $(abs_srctree) - LIBBPF_VERSION := $(shell \ grep -oE '^LIBBPF_([0-9.]+)' libbpf.map | \ sort -rV | head -n1 | cut -d'_' -f2) @@ -146,8 +143,6 @@ LIB_TARGET := $(addprefix $(OUTPUT),$(LIB_TARGET)) LIB_FILE := $(addprefix $(OUTPUT),$(LIB_FILE)) PC_FILE := $(addprefix $(OUTPUT),$(PC_FILE)) -TAGS_PROG := $(if $(shell which etags 2>/dev/null),etags,ctags) - GLOBAL_SYM_COUNT = $(shell readelf -s --wide $(BPF_IN_SHARED) | \ cut -d "@" -f1 | sed 's/_v[0-9]_[0-9]_[0-9].*//' | \ sed 's/\[.*\]//' | \ @@ -201,7 +196,7 @@ $(OUTPUT)libbpf.so.$(LIBBPF_VERSION): $(BPF_IN_SHARED) @ln -sf $(@F) $(OUTPUT)libbpf.so.$(LIBBPF_MAJOR_VERSION) $(OUTPUT)libbpf.a: $(BPF_IN_STATIC) - $(QUIET_LINK)$(RM) -f $@; $(AR) rcs $@ $^ + $(QUIET_LINK)$(RM) $@; $(AR) rcs $@ $^ $(OUTPUT)test_libbpf: test_libbpf.cpp $(OUTPUT)libbpf.a $(QUIET_LINK)$(CXX) $(INCLUDES) $^ -lelf -o $@ @@ -282,7 +277,7 @@ clean: -PHONY += force elfdep bpfdep cscope tags +PHONY += force elfdep bpfdep force: elfdep: @@ -291,14 +286,6 @@ elfdep: bpfdep: @if [ "$(feature-bpf)" != "1" ]; then echo "BPF API too old"; exit 1 ; fi -cscope: - ls *.c *.h > cscope.files - cscope -b -q -I $(srctree)/include -f cscope.out - -tags: - $(RM) -f TAGS tags - ls *.c *.h | xargs $(TAGS_PROG) -a - # Declare the contents of the .PHONY variable as phony. We keep that # information in a variable so we can use it in if_changed and friends. .PHONY: $(PHONY) diff --git a/tools/lib/bpf/libbpf.c b/tools/lib/bpf/libbpf.c index 92fbb3ccd02c..98e34c517267 100644 --- a/tools/lib/bpf/libbpf.c +++ b/tools/lib/bpf/libbpf.c @@ -4511,10 +4511,6 @@ static const struct { BPF_APROG_SEC("cgroup_skb/egress", BPF_PROG_TYPE_CGROUP_SKB, BPF_CGROUP_INET_EGRESS), BPF_APROG_COMPAT("cgroup/skb", BPF_PROG_TYPE_CGROUP_SKB), - BPF_EAPROG_SEC("cgroup/sock_create", BPF_PROG_TYPE_CGROUP_SOCK, - BPF_CGROUP_INET_SOCK_CREATE), - BPF_EAPROG_SEC("cgroup/sock_release", BPF_PROG_TYPE_CGROUP_SOCK, - BPF_CGROUP_INET_SOCK_RELEASE), BPF_APROG_SEC("cgroup/sock", BPF_PROG_TYPE_CGROUP_SOCK, BPF_CGROUP_INET_SOCK_CREATE), BPF_EAPROG_SEC("cgroup/post_bind4", BPF_PROG_TYPE_CGROUP_SOCK, @@ -5597,7 +5593,7 @@ error: struct perf_sample_raw { struct perf_event_header header; uint32_t size; - char data[]; + char data[0]; }; struct perf_sample_lost { diff --git a/tools/lib/bpf/libbpf_internal.h b/tools/lib/bpf/libbpf_internal.h index 0dd705a1cb12..92940ae26ada 100644 --- a/tools/lib/bpf/libbpf_internal.h +++ b/tools/lib/bpf/libbpf_internal.h @@ -104,7 +104,7 @@ struct btf_ext_info_sec { __u32 sec_name_off; __u32 num_info; /* Followed by num_info * record_size number of bytes */ - __u8 data[]; + __u8 data[0]; }; /* The minimum bpf_func_info checked by the loader */ diff --git a/tools/lib/bpf/libbpf_probes.c b/tools/lib/bpf/libbpf_probes.c index 789894540f35..4b0b0364f5fc 100644 --- a/tools/lib/bpf/libbpf_probes.c +++ b/tools/lib/bpf/libbpf_probes.c @@ -102,7 +102,6 @@ probe_load(enum bpf_prog_type prog_type, const struct bpf_insn *insns, case BPF_PROG_TYPE_FLOW_DISSECTOR: case BPF_PROG_TYPE_CGROUP_SYSCTL: case BPF_PROG_TYPE_CGROUP_SOCKOPT: - case BPF_PROG_TYPE_LSM: default: break; } @@ -164,7 +163,7 @@ int libbpf__load_raw_btf(const char *raw_types, size_t types_len, return btf_fd; } -static int load_local_storage_btf(void) +static int load_sk_storage_btf(void) { const char strs[] = "\0bpf_spin_lock\0val\0cnt\0l"; /* struct bpf_spin_lock { @@ -223,13 +222,12 @@ bool bpf_probe_map_type(enum bpf_map_type map_type, __u32 ifindex) key_size = 0; break; case BPF_MAP_TYPE_SK_STORAGE: - case BPF_MAP_TYPE_INODE_STORAGE: btf_key_type_id = 1; btf_value_type_id = 3; value_size = 8; max_entries = 0; map_flags = BPF_F_NO_PREALLOC; - btf_fd = load_local_storage_btf(); + btf_fd = load_sk_storage_btf(); if (btf_fd < 0) return false; break; diff --git a/tools/lib/subcmd/help.c b/tools/lib/subcmd/help.c index 10f134c64ada..4260c8b4257b 100644 --- a/tools/lib/subcmd/help.c +++ b/tools/lib/subcmd/help.c @@ -72,9 +72,6 @@ void exclude_cmds(struct cmdnames *cmds, struct cmdnames *excludes) size_t ci, cj, ei; int cmp; - if (!excludes->cnt) - return; - ci = cj = ei = 0; while (ci < cmds->cnt && ei < excludes->cnt) { cmp = strcmp(cmds->names[ci]->name, excludes->names[ei]->name); diff --git a/tools/perf/util/lzma.c b/tools/perf/util/lzma.c index aa9a0ebc1f93..51424cdc3b68 100644 --- a/tools/perf/util/lzma.c +++ b/tools/perf/util/lzma.c @@ -115,7 +115,7 @@ bool lzma_is_compressed(const char *input) ssize_t rc; if (fd < 0) - return false; + return -1; rc = read(fd, buf, sizeof(buf)); close(fd); diff --git a/tools/perf/util/session.c b/tools/perf/util/session.c index cd60a878752f..01e15b445cb5 100644 --- a/tools/perf/util/session.c +++ b/tools/perf/util/session.c @@ -1504,7 +1504,7 @@ static s64 perf_session__process_user_event(struct perf_session *session, struct perf_tool *tool = session->tool; struct perf_sample sample = { .time = 0, }; int fd = perf_data__fd(session->data); - s64 err; + int err; if (event->header.type != PERF_RECORD_COMPRESSED || tool->compressed == perf_session__process_compressed_event_stub) diff --git a/tools/perf/util/zlib.c b/tools/perf/util/zlib.c index 1f7c06523059..78d2297c1b67 100644 --- a/tools/perf/util/zlib.c +++ b/tools/perf/util/zlib.c @@ -88,7 +88,7 @@ bool gzip_is_compressed(const char *input) ssize_t rc; if (fd < 0) - return false; + return -1; rc = read(fd, buf, sizeof(buf)); close(fd); diff --git a/tools/power/cpupower/lib/cpuidle.c b/tools/power/cpupower/lib/cpuidle.c index c15d0de12357..479c5971aa6d 100644 --- a/tools/power/cpupower/lib/cpuidle.c +++ b/tools/power/cpupower/lib/cpuidle.c @@ -231,7 +231,6 @@ int cpuidle_state_disable(unsigned int cpu, { char value[SYSFS_PATH_MAX]; int bytes_written; - int len; if (cpuidle_state_count(cpu) <= idlestate) return -1; @@ -240,10 +239,10 @@ int cpuidle_state_disable(unsigned int cpu, idlestate_value_files[IDLESTATE_DISABLE])) return -2; - len = snprintf(value, SYSFS_PATH_MAX, "%u", disable); + snprintf(value, SYSFS_PATH_MAX, "%u", disable); bytes_written = cpuidle_state_write_file(cpu, idlestate, "disable", - value, len); + value, sizeof(disable)); if (bytes_written) return 0; return -3; diff --git a/tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c b/tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c index c878e2e1cabe..165eb4da8a64 100644 --- a/tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c +++ b/tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c @@ -62,7 +62,6 @@ unsigned char turbo_update_value; unsigned char update_hwp_epp; unsigned char update_hwp_min; unsigned char update_hwp_max; -unsigned char hwp_limits_done_via_sysfs; unsigned char update_hwp_desired; unsigned char update_hwp_window; unsigned char update_hwp_use_pkg; @@ -810,10 +809,8 @@ int ratio_2_sysfs_khz(int ratio) } /* * If HWP is enabled and cpufreq sysfs attribtes are present, - * then update via sysfs. The intel_pstate driver may modify (clip) - * this request, say, when HWP_CAP is outside of PLATFORM_INFO limits, - * and the driver-chosen value takes precidence. - * + * then update sysfs, so that it will not become + * stale when we write to MSRs. * (intel_pstate's max_perf_pct and min_perf_pct will follow cpufreq, * so we don't have to touch that.) */ @@ -868,8 +865,6 @@ int update_sysfs(int cpu) if (update_hwp_max) update_cpufreq_scaling_freq(1, cpu, req_update.hwp_max); - hwp_limits_done_via_sysfs = 1; - return 0; } @@ -948,10 +943,10 @@ int update_hwp_request(int cpu) if (debug) print_hwp_request(cpu, &req, "old: "); - if (update_hwp_min && !hwp_limits_done_via_sysfs) + if (update_hwp_min) req.hwp_min = req_update.hwp_min; - if (update_hwp_max && !hwp_limits_done_via_sysfs) + if (update_hwp_max) req.hwp_max = req_update.hwp_max; if (update_hwp_desired) @@ -1029,18 +1024,13 @@ int update_hwp_request_pkg(int pkg) int enable_hwp_on_cpu(int cpu) { - unsigned long long old_msr, new_msr; + unsigned long long msr; - get_msr(cpu, MSR_PM_ENABLE, &old_msr); - - if (old_msr & 1) - return 0; /* already enabled */ - - new_msr = old_msr | 1; - put_msr(cpu, MSR_PM_ENABLE, new_msr); + get_msr(cpu, MSR_PM_ENABLE, &msr); + put_msr(cpu, MSR_PM_ENABLE, 1); if (verbose) - printf("cpu%d: MSR_PM_ENABLE old: %llX new: %llX\n", cpu, old_msr, new_msr); + printf("cpu%d: MSR_PM_ENABLE old: %d new: %d\n", cpu, (unsigned int) msr, 1); return 0; } diff --git a/tools/testing/selftests/Makefile b/tools/testing/selftests/Makefile index 7b4106268541..40ee6f57af78 100644 --- a/tools/testing/selftests/Makefile +++ b/tools/testing/selftests/Makefile @@ -4,7 +4,6 @@ TARGETS += bpf TARGETS += breakpoints TARGETS += capabilities TARGETS += cgroup -TARGETS += clone3 TARGETS += cpufreq TARGETS += cpu-hotplug TARGETS += drivers/dma-buf @@ -238,7 +237,7 @@ else endif clean: - @for TARGET in $(TARGETS) $(INSTALL_DEP_TARGETS); do \ + @for TARGET in $(TARGETS); do \ BUILD_TARGET=$$BUILD/$$TARGET; \ $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET clean;\ done; diff --git a/tools/testing/selftests/bpf/config b/tools/testing/selftests/bpf/config index 3edaf28eafb1..b9601f13cf03 100644 --- a/tools/testing/selftests/bpf/config +++ b/tools/testing/selftests/bpf/config @@ -36,6 +36,3 @@ CONFIG_MPLS_ROUTING=m CONFIG_MPLS_IPTUNNEL=m CONFIG_IPV6_SIT=m CONFIG_BPF_JIT=y -CONFIG_BPF_LSM=y -CONFIG_SECURITY=y -CONFIG_TCP_CONG_DCTCP=y diff --git a/tools/testing/selftests/bpf/prog_tests/connect_force_port.c b/tools/testing/selftests/bpf/prog_tests/connect_force_port.c deleted file mode 100644 index 47fbb20cb6a6..000000000000 --- a/tools/testing/selftests/bpf/prog_tests/connect_force_port.c +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include -#include "cgroup_helpers.h" -#include "network_helpers.h" - -static int verify_port(int family, int fd, int expected) -{ - struct sockaddr_storage addr; - socklen_t len = sizeof(addr); - __u16 port; - - if (getsockname(fd, (struct sockaddr *)&addr, &len)) { - log_err("Failed to get server addr"); - return -1; - } - - if (family == AF_INET) - port = ((struct sockaddr_in *)&addr)->sin_port; - else - port = ((struct sockaddr_in6 *)&addr)->sin6_port; - - if (ntohs(port) != expected) { - log_err("Unexpected port %d, expected %d", ntohs(port), - expected); - return -1; - } - - return 0; -} - -static int run_test(int cgroup_fd, int server_fd, int family, int type) -{ - struct bpf_prog_load_attr attr = { - .prog_type = BPF_PROG_TYPE_CGROUP_SOCK_ADDR, - }; - struct bpf_object *obj; - int expected_port; - int prog_fd; - int err; - int fd; - - if (family == AF_INET) { - attr.file = "./connect_force_port4.o"; - attr.expected_attach_type = BPF_CGROUP_INET4_CONNECT; - expected_port = 22222; - } else { - attr.file = "./connect_force_port6.o"; - attr.expected_attach_type = BPF_CGROUP_INET6_CONNECT; - expected_port = 22223; - } - - err = bpf_prog_load_xattr(&attr, &obj, &prog_fd); - if (err) { - log_err("Failed to load BPF object"); - return -1; - } - - err = bpf_prog_attach(prog_fd, cgroup_fd, attr.expected_attach_type, - 0); - if (err) { - log_err("Failed to attach BPF program"); - goto close_bpf_object; - } - - fd = connect_to_fd(family, type, server_fd); - if (fd < 0) { - err = -1; - goto close_bpf_object; - } - - err = verify_port(family, fd, expected_port); - - close(fd); - -close_bpf_object: - bpf_object__close(obj); - return err; -} - -void test_connect_force_port(void) -{ - int server_fd, cgroup_fd; - - cgroup_fd = test__join_cgroup("/connect_force_port"); - if (CHECK_FAIL(cgroup_fd < 0)) - return; - - server_fd = start_server(AF_INET, SOCK_STREAM); - if (CHECK_FAIL(server_fd < 0)) - goto close_cgroup_fd; - CHECK_FAIL(run_test(cgroup_fd, server_fd, AF_INET, SOCK_STREAM)); - close(server_fd); - - server_fd = start_server(AF_INET6, SOCK_STREAM); - if (CHECK_FAIL(server_fd < 0)) - goto close_cgroup_fd; - CHECK_FAIL(run_test(cgroup_fd, server_fd, AF_INET6, SOCK_STREAM)); - close(server_fd); - - server_fd = start_server(AF_INET, SOCK_DGRAM); - if (CHECK_FAIL(server_fd < 0)) - goto close_cgroup_fd; - CHECK_FAIL(run_test(cgroup_fd, server_fd, AF_INET, SOCK_DGRAM)); - close(server_fd); - - server_fd = start_server(AF_INET6, SOCK_DGRAM); - if (CHECK_FAIL(server_fd < 0)) - goto close_cgroup_fd; - CHECK_FAIL(run_test(cgroup_fd, server_fd, AF_INET6, SOCK_DGRAM)); - close(server_fd); - -close_cgroup_fd: - close(cgroup_fd); -} diff --git a/tools/testing/selftests/bpf/prog_tests/d_path.c b/tools/testing/selftests/bpf/prog_tests/d_path.c deleted file mode 100644 index 0a577a248d34..000000000000 --- a/tools/testing/selftests/bpf/prog_tests/d_path.c +++ /dev/null @@ -1,157 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#define _GNU_SOURCE -#include -#include -#include -#include - -#define MAX_PATH_LEN 128 -#define MAX_FILES 7 - -#include "test_d_path.skel.h" - -static int duration; - -static struct { - __u32 cnt; - char paths[MAX_FILES][MAX_PATH_LEN]; -} src; - -static int set_pathname(int fd, pid_t pid) -{ - char buf[MAX_PATH_LEN]; - - snprintf(buf, MAX_PATH_LEN, "/proc/%d/fd/%d", pid, fd); - return readlink(buf, src.paths[src.cnt++], MAX_PATH_LEN); -} - -static int trigger_fstat_events(pid_t pid) -{ - int sockfd = -1, procfd = -1, devfd = -1; - int localfd = -1, indicatorfd = -1; - int pipefd[2] = { -1, -1 }; - struct stat fileStat; - int ret = -1; - - /* unmountable pseudo-filesystems */ - if (CHECK(pipe(pipefd) < 0, "trigger", "pipe failed\n")) - return ret; - /* unmountable pseudo-filesystems */ - sockfd = socket(AF_INET, SOCK_STREAM, 0); - if (CHECK(sockfd < 0, "trigger", "socket failed\n")) - goto out_close; - /* mountable pseudo-filesystems */ - procfd = open("/proc/self/comm", O_RDONLY); - if (CHECK(procfd < 0, "trigger", "open /proc/self/comm failed\n")) - goto out_close; - devfd = open("/dev/urandom", O_RDONLY); - if (CHECK(devfd < 0, "trigger", "open /dev/urandom failed\n")) - goto out_close; - localfd = open("/tmp/d_path_loadgen.txt", O_CREAT | O_RDONLY, 0644); - if (CHECK(localfd < 0, "trigger", "open /tmp/d_path_loadgen.txt failed\n")) - goto out_close; - /* bpf_d_path will return path with (deleted) */ - remove("/tmp/d_path_loadgen.txt"); - indicatorfd = open("/tmp/", O_PATH); - if (CHECK(indicatorfd < 0, "trigger", "open /tmp/ failed\n")) - goto out_close; - - ret = set_pathname(pipefd[0], pid); - if (CHECK(ret < 0, "trigger", "set_pathname failed for pipe[0]\n")) - goto out_close; - ret = set_pathname(pipefd[1], pid); - if (CHECK(ret < 0, "trigger", "set_pathname failed for pipe[1]\n")) - goto out_close; - ret = set_pathname(sockfd, pid); - if (CHECK(ret < 0, "trigger", "set_pathname failed for socket\n")) - goto out_close; - ret = set_pathname(procfd, pid); - if (CHECK(ret < 0, "trigger", "set_pathname failed for proc\n")) - goto out_close; - ret = set_pathname(devfd, pid); - if (CHECK(ret < 0, "trigger", "set_pathname failed for dev\n")) - goto out_close; - ret = set_pathname(localfd, pid); - if (CHECK(ret < 0, "trigger", "set_pathname failed for file\n")) - goto out_close; - ret = set_pathname(indicatorfd, pid); - if (CHECK(ret < 0, "trigger", "set_pathname failed for dir\n")) - goto out_close; - - /* triggers vfs_getattr */ - fstat(pipefd[0], &fileStat); - fstat(pipefd[1], &fileStat); - fstat(sockfd, &fileStat); - fstat(procfd, &fileStat); - fstat(devfd, &fileStat); - fstat(localfd, &fileStat); - fstat(indicatorfd, &fileStat); - -out_close: - /* triggers filp_close */ - close(pipefd[0]); - close(pipefd[1]); - close(sockfd); - close(procfd); - close(devfd); - close(localfd); - close(indicatorfd); - return ret; -} - -void test_d_path(void) -{ - struct test_d_path__bss *bss; - struct test_d_path *skel; - int err; - - skel = test_d_path__open_and_load(); - if (CHECK(!skel, "setup", "d_path skeleton failed\n")) - goto cleanup; - - err = test_d_path__attach(skel); - if (CHECK(err, "setup", "attach failed: %d\n", err)) - goto cleanup; - - bss = skel->bss; - bss->my_pid = getpid(); - - err = trigger_fstat_events(bss->my_pid); - if (err < 0) - goto cleanup; - - if (CHECK(!bss->called_stat, - "stat", - "trampoline for security_inode_getattr was not called\n")) - goto cleanup; - - if (CHECK(!bss->called_close, - "close", - "trampoline for filp_close was not called\n")) - goto cleanup; - - for (int i = 0; i < MAX_FILES; i++) { - CHECK(strncmp(src.paths[i], bss->paths_stat[i], MAX_PATH_LEN), - "check", - "failed to get stat path[%d]: %s vs %s\n", - i, src.paths[i], bss->paths_stat[i]); - CHECK(strncmp(src.paths[i], bss->paths_close[i], MAX_PATH_LEN), - "check", - "failed to get close path[%d]: %s vs %s\n", - i, src.paths[i], bss->paths_close[i]); - /* The d_path helper returns size plus NUL char, hence + 1 */ - CHECK(bss->rets_stat[i] != strlen(bss->paths_stat[i]) + 1, - "check", - "failed to match stat return [%d]: %d vs %zd [%s]\n", - i, bss->rets_stat[i], strlen(bss->paths_stat[i]) + 1, - bss->paths_stat[i]); - CHECK(bss->rets_close[i] != strlen(bss->paths_stat[i]) + 1, - "check", - "failed to match stat return [%d]: %d vs %zd [%s]\n", - i, bss->rets_close[i], strlen(bss->paths_close[i]) + 1, - bss->paths_stat[i]); - } - -cleanup: - test_d_path__destroy(skel); -} diff --git a/tools/testing/selftests/bpf/prog_tests/map_init.c b/tools/testing/selftests/bpf/prog_tests/map_init.c deleted file mode 100644 index 14a31109dd0e..000000000000 --- a/tools/testing/selftests/bpf/prog_tests/map_init.c +++ /dev/null @@ -1,214 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2020 Tessares SA */ - -#include -#include "test_map_init.skel.h" - -#define TEST_VALUE 0x1234 -#define FILL_VALUE 0xdeadbeef - -static int nr_cpus; -static int duration; - -typedef unsigned long long map_key_t; -typedef unsigned long long map_value_t; -typedef struct { - map_value_t v; /* padding */ -} __bpf_percpu_val_align pcpu_map_value_t; - - -static int map_populate(int map_fd, int num) -{ - pcpu_map_value_t value[nr_cpus]; - int i, err; - map_key_t key; - - for (i = 0; i < nr_cpus; i++) - bpf_percpu(value, i) = FILL_VALUE; - - for (key = 1; key <= num; key++) { - err = bpf_map_update_elem(map_fd, &key, value, BPF_NOEXIST); - if (!ASSERT_OK(err, "bpf_map_update_elem")) - return -1; - } - - return 0; -} - -static struct test_map_init *setup(enum bpf_map_type map_type, int map_sz, - int *map_fd, int populate) -{ - struct test_map_init *skel; - int err; - - skel = test_map_init__open(); - if (!ASSERT_OK_PTR(skel, "skel_open")) - return NULL; - - err = bpf_map__set_type(skel->maps.hashmap1, map_type); - if (!ASSERT_OK(err, "bpf_map__set_type")) - goto error; - - err = bpf_map__set_max_entries(skel->maps.hashmap1, map_sz); - if (!ASSERT_OK(err, "bpf_map__set_max_entries")) - goto error; - - err = test_map_init__load(skel); - if (!ASSERT_OK(err, "skel_load")) - goto error; - - *map_fd = bpf_map__fd(skel->maps.hashmap1); - if (CHECK(*map_fd < 0, "bpf_map__fd", "failed\n")) - goto error; - - err = map_populate(*map_fd, populate); - if (!ASSERT_OK(err, "map_populate")) - goto error_map; - - return skel; - -error_map: - close(*map_fd); -error: - test_map_init__destroy(skel); - return NULL; -} - -/* executes bpf program that updates map with key, value */ -static int prog_run_insert_elem(struct test_map_init *skel, map_key_t key, - map_value_t value) -{ - struct test_map_init__bss *bss; - - bss = skel->bss; - - bss->inKey = key; - bss->inValue = value; - bss->inPid = getpid(); - - if (!ASSERT_OK(test_map_init__attach(skel), "skel_attach")) - return -1; - - /* Let tracepoint trigger */ - syscall(__NR_getpgid); - - test_map_init__detach(skel); - - return 0; -} - -static int check_values_one_cpu(pcpu_map_value_t *value, map_value_t expected) -{ - int i, nzCnt = 0; - map_value_t val; - - for (i = 0; i < nr_cpus; i++) { - val = bpf_percpu(value, i); - if (val) { - if (CHECK(val != expected, "map value", - "unexpected for cpu %d: 0x%llx\n", i, val)) - return -1; - nzCnt++; - } - } - - if (CHECK(nzCnt != 1, "map value", "set for %d CPUs instead of 1!\n", - nzCnt)) - return -1; - - return 0; -} - -/* Add key=1 elem with values set for all CPUs - * Delete elem key=1 - * Run bpf prog that inserts new key=1 elem with value=0x1234 - * (bpf prog can only set value for current CPU) - * Lookup Key=1 and check value is as expected for all CPUs: - * value set by bpf prog for one CPU, 0 for all others - */ -static void test_pcpu_map_init(void) -{ - pcpu_map_value_t value[nr_cpus]; - struct test_map_init *skel; - int map_fd, err; - map_key_t key; - - /* max 1 elem in map so insertion is forced to reuse freed entry */ - skel = setup(BPF_MAP_TYPE_PERCPU_HASH, 1, &map_fd, 1); - if (!ASSERT_OK_PTR(skel, "prog_setup")) - return; - - /* delete element so the entry can be re-used*/ - key = 1; - err = bpf_map_delete_elem(map_fd, &key); - if (!ASSERT_OK(err, "bpf_map_delete_elem")) - goto cleanup; - - /* run bpf prog that inserts new elem, re-using the slot just freed */ - err = prog_run_insert_elem(skel, key, TEST_VALUE); - if (!ASSERT_OK(err, "prog_run_insert_elem")) - goto cleanup; - - /* check that key=1 was re-created by bpf prog */ - err = bpf_map_lookup_elem(map_fd, &key, value); - if (!ASSERT_OK(err, "bpf_map_lookup_elem")) - goto cleanup; - - /* and has expected values */ - check_values_one_cpu(value, TEST_VALUE); - -cleanup: - test_map_init__destroy(skel); -} - -/* Add key=1 and key=2 elems with values set for all CPUs - * Run bpf prog that inserts new key=3 elem - * (only for current cpu; other cpus should have initial value = 0) - * Lookup Key=1 and check value is as expected for all CPUs - */ -static void test_pcpu_lru_map_init(void) -{ - pcpu_map_value_t value[nr_cpus]; - struct test_map_init *skel; - int map_fd, err; - map_key_t key; - - /* Set up LRU map with 2 elements, values filled for all CPUs. - * With these 2 elements, the LRU map is full - */ - skel = setup(BPF_MAP_TYPE_LRU_PERCPU_HASH, 2, &map_fd, 2); - if (!ASSERT_OK_PTR(skel, "prog_setup")) - return; - - /* run bpf prog that inserts new key=3 element, re-using LRU slot */ - key = 3; - err = prog_run_insert_elem(skel, key, TEST_VALUE); - if (!ASSERT_OK(err, "prog_run_insert_elem")) - goto cleanup; - - /* check that key=3 replaced one of earlier elements */ - err = bpf_map_lookup_elem(map_fd, &key, value); - if (!ASSERT_OK(err, "bpf_map_lookup_elem")) - goto cleanup; - - /* and has expected values */ - check_values_one_cpu(value, TEST_VALUE); - -cleanup: - test_map_init__destroy(skel); -} - -void test_map_init(void) -{ - nr_cpus = bpf_num_possible_cpus(); - if (nr_cpus <= 1) { - printf("%s:SKIP: >1 cpu needed for this test\n", __func__); - test__skip(); - return; - } - - if (test__start_subtest("pcpu_map_init")) - test_pcpu_map_init(); - if (test__start_subtest("pcpu_lru_map_init")) - test_pcpu_lru_map_init(); -} diff --git a/tools/testing/selftests/bpf/prog_tests/map_ptr.c b/tools/testing/selftests/bpf/prog_tests/map_ptr.c deleted file mode 100644 index c230a573c373..000000000000 --- a/tools/testing/selftests/bpf/prog_tests/map_ptr.c +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2020 Facebook - -#include -#include - -#include "map_ptr_kern.skel.h" - -void test_map_ptr(void) -{ - struct map_ptr_kern *skel; - __u32 duration = 0, retval; - char buf[128]; - int err; - - skel = map_ptr_kern__open_and_load(); - if (CHECK(!skel, "skel_open_load", "open_load failed\n")) - return; - - err = bpf_prog_test_run(bpf_program__fd(skel->progs.cg_skb), 1, &pkt_v4, - sizeof(pkt_v4), buf, NULL, &retval, NULL); - - if (CHECK(err, "test_run", "err=%d errno=%d\n", err, errno)) - goto cleanup; - - if (CHECK(!retval, "retval", "retval=%d map_type=%u line=%u\n", retval, - skel->bss->g_map_type, skel->bss->g_line)) - goto cleanup; - -cleanup: - map_ptr_kern__destroy(skel); -} diff --git a/tools/testing/selftests/bpf/prog_tests/modify_return.c b/tools/testing/selftests/bpf/prog_tests/modify_return.c deleted file mode 100644 index 97fec70c600b..000000000000 --- a/tools/testing/selftests/bpf/prog_tests/modify_return.c +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* - * Copyright 2020 Google LLC. - */ - -#include -#include "modify_return.skel.h" - -#define LOWER(x) ((x) & 0xffff) -#define UPPER(x) ((x) >> 16) - - -static void run_test(__u32 input_retval, __u16 want_side_effect, __s16 want_ret) -{ - struct modify_return *skel = NULL; - int err, prog_fd; - __u32 duration = 0, retval; - __u16 side_effect; - __s16 ret; - - skel = modify_return__open_and_load(); - if (CHECK(!skel, "skel_load", "modify_return skeleton failed\n")) - goto cleanup; - - err = modify_return__attach(skel); - if (CHECK(err, "modify_return", "attach failed: %d\n", err)) - goto cleanup; - - skel->bss->input_retval = input_retval; - prog_fd = bpf_program__fd(skel->progs.fmod_ret_test); - err = bpf_prog_test_run(prog_fd, 1, NULL, 0, NULL, 0, - &retval, &duration); - - CHECK(err, "test_run", "err %d errno %d\n", err, errno); - - side_effect = UPPER(retval); - ret = LOWER(retval); - - CHECK(ret != want_ret, "test_run", - "unexpected ret: %d, expected: %d\n", ret, want_ret); - CHECK(side_effect != want_side_effect, "modify_return", - "unexpected side_effect: %d\n", side_effect); - - CHECK(skel->bss->fentry_result != 1, "modify_return", - "fentry failed\n"); - CHECK(skel->bss->fexit_result != 1, "modify_return", - "fexit failed\n"); - CHECK(skel->bss->fmod_ret_result != 1, "modify_return", - "fmod_ret failed\n"); - -cleanup: - modify_return__destroy(skel); -} - -void test_modify_return(void) -{ - run_test(0 /* input_retval */, - 1 /* want_side_effect */, - 4 /* want_ret */); - run_test(-EINVAL /* input_retval */, - 0 /* want_side_effect */, - -EINVAL /* want_ret */); -} - diff --git a/tools/testing/selftests/bpf/prog_tests/perf_branches.c b/tools/testing/selftests/bpf/prog_tests/perf_branches.c deleted file mode 100644 index e35c444902a7..000000000000 --- a/tools/testing/selftests/bpf/prog_tests/perf_branches.c +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#define _GNU_SOURCE -#include -#include -#include -#include -#include "bpf/libbpf_internal.h" -#include "test_perf_branches.skel.h" - -static void check_good_sample(struct test_perf_branches *skel) -{ - int written_global = skel->bss->written_global_out; - int required_size = skel->bss->required_size_out; - int written_stack = skel->bss->written_stack_out; - int pbe_size = sizeof(struct perf_branch_entry); - int duration = 0; - - if (CHECK(!skel->bss->valid, "output not valid", - "no valid sample from prog")) - return; - - /* - * It's hard to validate the contents of the branch entries b/c it - * would require some kind of disassembler and also encoding the - * valid jump instructions for supported architectures. So just check - * the easy stuff for now. - */ - CHECK(required_size <= 0, "read_branches_size", "err %d\n", required_size); - CHECK(written_stack < 0, "read_branches_stack", "err %d\n", written_stack); - CHECK(written_stack % pbe_size != 0, "read_branches_stack", - "stack bytes written=%d not multiple of struct size=%d\n", - written_stack, pbe_size); - CHECK(written_global < 0, "read_branches_global", "err %d\n", written_global); - CHECK(written_global % pbe_size != 0, "read_branches_global", - "global bytes written=%d not multiple of struct size=%d\n", - written_global, pbe_size); - CHECK(written_global < written_stack, "read_branches_size", - "written_global=%d < written_stack=%d\n", written_global, written_stack); -} - -static void check_bad_sample(struct test_perf_branches *skel) -{ - int written_global = skel->bss->written_global_out; - int required_size = skel->bss->required_size_out; - int written_stack = skel->bss->written_stack_out; - int duration = 0; - - if (CHECK(!skel->bss->valid, "output not valid", - "no valid sample from prog")) - return; - - CHECK((required_size != -EINVAL && required_size != -ENOENT), - "read_branches_size", "err %d\n", required_size); - CHECK((written_stack != -EINVAL && written_stack != -ENOENT), - "read_branches_stack", "written %d\n", written_stack); - CHECK((written_global != -EINVAL && written_global != -ENOENT), - "read_branches_global", "written %d\n", written_global); -} - -static void test_perf_branches_common(int perf_fd, - void (*cb)(struct test_perf_branches *)) -{ - struct test_perf_branches *skel; - int err, i, duration = 0; - bool detached = false; - struct bpf_link *link; - volatile int j = 0; - cpu_set_t cpu_set; - - skel = test_perf_branches__open_and_load(); - if (CHECK(!skel, "test_perf_branches_load", - "perf_branches skeleton failed\n")) - return; - - /* attach perf_event */ - link = bpf_program__attach_perf_event(skel->progs.perf_branches, perf_fd); - if (CHECK(IS_ERR(link), "attach_perf_event", "err %ld\n", PTR_ERR(link))) - goto out_destroy_skel; - - /* generate some branches on cpu 0 */ - CPU_ZERO(&cpu_set); - CPU_SET(0, &cpu_set); - err = pthread_setaffinity_np(pthread_self(), sizeof(cpu_set), &cpu_set); - if (CHECK(err, "set_affinity", "cpu #0, err %d\n", err)) - goto out_destroy; - /* spin the loop for a while (random high number) */ - for (i = 0; i < 1000000; ++i) - ++j; - - test_perf_branches__detach(skel); - detached = true; - - cb(skel); -out_destroy: - bpf_link__destroy(link); -out_destroy_skel: - if (!detached) - test_perf_branches__detach(skel); - test_perf_branches__destroy(skel); -} - -static void test_perf_branches_hw(void) -{ - struct perf_event_attr attr = {0}; - int duration = 0; - int pfd; - - /* create perf event */ - attr.size = sizeof(attr); - attr.type = PERF_TYPE_HARDWARE; - attr.config = PERF_COUNT_HW_CPU_CYCLES; - attr.freq = 1; - attr.sample_freq = 4000; - attr.sample_type = PERF_SAMPLE_BRANCH_STACK; - attr.branch_sample_type = PERF_SAMPLE_BRANCH_USER | PERF_SAMPLE_BRANCH_ANY; - pfd = syscall(__NR_perf_event_open, &attr, -1, 0, -1, PERF_FLAG_FD_CLOEXEC); - - /* - * Some setups don't support branch records (virtual machines, !x86), - * so skip test in this case. - */ - if (pfd == -1) { - if (errno == ENOENT || errno == EOPNOTSUPP) { - printf("%s:SKIP:no PERF_SAMPLE_BRANCH_STACK\n", - __func__); - test__skip(); - return; - } - if (CHECK(pfd < 0, "perf_event_open", "err %d errno %d\n", - pfd, errno)) - return; - } - - test_perf_branches_common(pfd, check_good_sample); - - close(pfd); -} - -/* - * Tests negative case -- run bpf_read_branch_records() on improperly configured - * perf event. - */ -static void test_perf_branches_no_hw(void) -{ - struct perf_event_attr attr = {0}; - int duration = 0; - int pfd; - - /* create perf event */ - attr.size = sizeof(attr); - attr.type = PERF_TYPE_SOFTWARE; - attr.config = PERF_COUNT_SW_CPU_CLOCK; - attr.freq = 1; - attr.sample_freq = 4000; - pfd = syscall(__NR_perf_event_open, &attr, -1, 0, -1, PERF_FLAG_FD_CLOEXEC); - if (CHECK(pfd < 0, "perf_event_open", "err %d\n", pfd)) - return; - - test_perf_branches_common(pfd, check_bad_sample); - - close(pfd); -} - -void test_perf_branches(void) -{ - if (test__start_subtest("perf_branches_hw")) - test_perf_branches_hw(); - if (test__start_subtest("perf_branches_no_hw")) - test_perf_branches_no_hw(); -} diff --git a/tools/testing/selftests/bpf/prog_tests/skb_ctx.c b/tools/testing/selftests/bpf/prog_tests/skb_ctx.c index 2d3739408b9e..e95baa32e277 100644 --- a/tools/testing/selftests/bpf/prog_tests/skb_ctx.c +++ b/tools/testing/selftests/bpf/prog_tests/skb_ctx.c @@ -10,11 +10,6 @@ void test_skb_ctx(void) .cb[3] = 4, .cb[4] = 5, .priority = 6, - .ifindex = 1, - .tstamp = 7, - .wire_len = 100, - .gso_segs = 8, - .mark = 9, }; struct bpf_prog_test_run_attr tattr = { .data_in = &pkt_v4, @@ -91,16 +86,4 @@ void test_skb_ctx(void) "ctx_out_priority", "skb->priority == %d, expected %d\n", skb.priority, 7); - CHECK_ATTR(skb.ifindex != 1, - "ctx_out_ifindex", - "skb->ifindex == %d, expected %d\n", - skb.ifindex, 1); - CHECK_ATTR(skb.tstamp != 8, - "ctx_out_tstamp", - "skb->tstamp == %lld, expected %d\n", - skb.tstamp, 8); - CHECK_ATTR(skb.mark != 10, - "ctx_out_mark", - "skb->mark == %u, expected %d\n", - skb.mark, 10); } diff --git a/tools/testing/selftests/bpf/prog_tests/test_global_funcs.c b/tools/testing/selftests/bpf/prog_tests/test_global_funcs.c deleted file mode 100644 index 32e4348b714b..000000000000 --- a/tools/testing/selftests/bpf/prog_tests/test_global_funcs.c +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2020 Facebook */ -#include - -const char *err_str; -bool found; - -static int libbpf_debug_print(enum libbpf_print_level level, - const char *format, va_list args) -{ - char *log_buf; - - if (level != LIBBPF_WARN || - strcmp(format, "libbpf: \n%s\n")) { - vprintf(format, args); - return 0; - } - - log_buf = va_arg(args, char *); - if (!log_buf) - goto out; - if (err_str && strstr(log_buf, err_str) == 0) - found = true; -out: - printf(format, log_buf); - return 0; -} - -extern int extra_prog_load_log_flags; - -static int check_load(const char *file) -{ - struct bpf_prog_load_attr attr; - struct bpf_object *obj = NULL; - int err, prog_fd; - - memset(&attr, 0, sizeof(struct bpf_prog_load_attr)); - attr.file = file; - attr.prog_type = BPF_PROG_TYPE_UNSPEC; - attr.log_level = extra_prog_load_log_flags; - attr.prog_flags = BPF_F_TEST_RND_HI32; - found = false; - err = bpf_prog_load_xattr(&attr, &obj, &prog_fd); - bpf_object__close(obj); - return err; -} - -struct test_def { - const char *file; - const char *err_str; -}; - -void test_test_global_funcs(void) -{ - struct test_def tests[] = { - { "test_global_func1.o", "combined stack size of 4 calls is 544" }, - { "test_global_func2.o" }, - { "test_global_func3.o" , "the call stack of 8 frames" }, - { "test_global_func4.o" }, - { "test_global_func5.o" , "expected pointer to ctx, but got PTR" }, - { "test_global_func6.o" , "modified ctx ptr R2" }, - { "test_global_func7.o" , "foo() doesn't return scalar" }, - { "test_global_func8.o" }, - }; - libbpf_print_fn_t old_print_fn = NULL; - int err, i, duration = 0; - - old_print_fn = libbpf_set_print(libbpf_debug_print); - - for (i = 0; i < ARRAY_SIZE(tests); i++) { - const struct test_def *test = &tests[i]; - - if (!test__start_subtest(test->file)) - continue; - - err_str = test->err_str; - err = check_load(test->file); - CHECK_FAIL(!!err ^ !!err_str); - if (err_str) - CHECK(found, "", "expected string '%s'", err_str); - } - libbpf_set_print(old_print_fn); -} diff --git a/tools/testing/selftests/bpf/prog_tests/test_lsm.c b/tools/testing/selftests/bpf/prog_tests/test_lsm.c deleted file mode 100644 index 1e4c258de09d..000000000000 --- a/tools/testing/selftests/bpf/prog_tests/test_lsm.c +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* - * Copyright (C) 2020 Google LLC. - */ - -#include -#include -#include -#include -#include -#include - -#include "lsm.skel.h" - -char *CMD_ARGS[] = {"true", NULL}; - -int heap_mprotect(void) -{ - void *buf; - long sz; - int ret; - - sz = sysconf(_SC_PAGESIZE); - if (sz < 0) - return sz; - - buf = memalign(sz, 2 * sz); - if (buf == NULL) - return -ENOMEM; - - ret = mprotect(buf, sz, PROT_READ | PROT_WRITE | PROT_EXEC); - free(buf); - return ret; -} - -int exec_cmd(int *monitored_pid) -{ - int child_pid, child_status; - - child_pid = fork(); - if (child_pid == 0) { - *monitored_pid = getpid(); - execvp(CMD_ARGS[0], CMD_ARGS); - return -EINVAL; - } else if (child_pid > 0) { - waitpid(child_pid, &child_status, 0); - return child_status; - } - - return -EINVAL; -} - -void test_test_lsm(void) -{ - struct lsm *skel = NULL; - int err, duration = 0; - - skel = lsm__open_and_load(); - if (CHECK(!skel, "skel_load", "lsm skeleton failed\n")) - goto close_prog; - - err = lsm__attach(skel); - if (CHECK(err, "attach", "lsm attach failed: %d\n", err)) - goto close_prog; - - err = exec_cmd(&skel->bss->monitored_pid); - if (CHECK(err < 0, "exec_cmd", "err %d errno %d\n", err, errno)) - goto close_prog; - - CHECK(skel->bss->bprm_count != 1, "bprm_count", "bprm_count = %d\n", - skel->bss->bprm_count); - - skel->bss->monitored_pid = getpid(); - - err = heap_mprotect(); - if (CHECK(errno != EPERM, "heap_mprotect", "want errno=EPERM, got %d\n", - errno)) - goto close_prog; - - CHECK(skel->bss->mprotect_count != 1, "mprotect_count", - "mprotect_count = %d\n", skel->bss->mprotect_count); - -close_prog: - lsm__destroy(skel); -} diff --git a/tools/testing/selftests/bpf/prog_tests/xdp_bpf2bpf.c b/tools/testing/selftests/bpf/prog_tests/xdp_bpf2bpf.c deleted file mode 100644 index a0f688c37023..000000000000 --- a/tools/testing/selftests/bpf/prog_tests/xdp_bpf2bpf.c +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include "test_xdp.skel.h" -#include "test_xdp_bpf2bpf.skel.h" - -struct meta { - int ifindex; - int pkt_len; -}; - -static void on_sample(void *ctx, int cpu, void *data, __u32 size) -{ - int duration = 0; - struct meta *meta = (struct meta *)data; - struct ipv4_packet *trace_pkt_v4 = data + sizeof(*meta); - - if (CHECK(size < sizeof(pkt_v4) + sizeof(*meta), - "check_size", "size %u < %zu\n", - size, sizeof(pkt_v4) + sizeof(*meta))) - return; - - if (CHECK(meta->ifindex != if_nametoindex("lo"), "check_meta_ifindex", - "meta->ifindex = %d\n", meta->ifindex)) - return; - - if (CHECK(meta->pkt_len != sizeof(pkt_v4), "check_meta_pkt_len", - "meta->pkt_len = %zd\n", sizeof(pkt_v4))) - return; - - if (CHECK(memcmp(trace_pkt_v4, &pkt_v4, sizeof(pkt_v4)), - "check_packet_content", "content not the same\n")) - return; - - *(bool *)ctx = true; -} - -void test_xdp_bpf2bpf(void) -{ - __u32 duration = 0, retval, size; - char buf[128]; - int err, pkt_fd, map_fd; - bool passed = false; - struct iphdr *iph = (void *)buf + sizeof(struct ethhdr); - struct iptnl_info value4 = {.family = AF_INET}; - struct test_xdp *pkt_skel = NULL; - struct test_xdp_bpf2bpf *ftrace_skel = NULL; - struct vip key4 = {.protocol = 6, .family = AF_INET}; - struct bpf_program *prog; - struct perf_buffer *pb = NULL; - struct perf_buffer_opts pb_opts = {}; - - /* Load XDP program to introspect */ - pkt_skel = test_xdp__open_and_load(); - if (CHECK(!pkt_skel, "pkt_skel_load", "test_xdp skeleton failed\n")) - return; - - pkt_fd = bpf_program__fd(pkt_skel->progs._xdp_tx_iptunnel); - - map_fd = bpf_map__fd(pkt_skel->maps.vip2tnl); - bpf_map_update_elem(map_fd, &key4, &value4, 0); - - /* Load trace program */ - ftrace_skel = test_xdp_bpf2bpf__open(); - if (CHECK(!ftrace_skel, "__open", "ftrace skeleton failed\n")) - goto out; - - /* Demonstrate the bpf_program__set_attach_target() API rather than - * the load with options, i.e. opts.attach_prog_fd. - */ - prog = ftrace_skel->progs.trace_on_entry; - bpf_program__set_expected_attach_type(prog, BPF_TRACE_FENTRY); - bpf_program__set_attach_target(prog, pkt_fd, "_xdp_tx_iptunnel"); - - prog = ftrace_skel->progs.trace_on_exit; - bpf_program__set_expected_attach_type(prog, BPF_TRACE_FEXIT); - bpf_program__set_attach_target(prog, pkt_fd, "_xdp_tx_iptunnel"); - - err = test_xdp_bpf2bpf__load(ftrace_skel); - if (CHECK(err, "__load", "ftrace skeleton failed\n")) - goto out; - - err = test_xdp_bpf2bpf__attach(ftrace_skel); - if (CHECK(err, "ftrace_attach", "ftrace attach failed: %d\n", err)) - goto out; - - /* Set up perf buffer */ - pb_opts.sample_cb = on_sample; - pb_opts.ctx = &passed; - pb = perf_buffer__new(bpf_map__fd(ftrace_skel->maps.perf_buf_map), - 1, &pb_opts); - if (CHECK(IS_ERR(pb), "perf_buf__new", "err %ld\n", PTR_ERR(pb))) - goto out; - - /* Run test program */ - err = bpf_prog_test_run(pkt_fd, 1, &pkt_v4, sizeof(pkt_v4), - buf, &size, &retval, &duration); - - if (CHECK(err || retval != XDP_TX || size != 74 || - iph->protocol != IPPROTO_IPIP, "ipv4", - "err %d errno %d retval %d size %d\n", - err, errno, retval, size)) - goto out; - - /* Make sure bpf_xdp_output() was triggered and it sent the expected - * data to the perf ring buffer. - */ - err = perf_buffer__poll(pb, 100); - if (CHECK(err < 0, "perf_buffer__poll", "err %d\n", err)) - goto out; - - CHECK_FAIL(!passed); - - /* Verify test results */ - if (CHECK(ftrace_skel->bss->test_result_fentry != if_nametoindex("lo"), - "result", "fentry failed err %llu\n", - ftrace_skel->bss->test_result_fentry)) - goto out; - - CHECK(ftrace_skel->bss->test_result_fexit != XDP_TX, "result", - "fexit failed err %llu\n", ftrace_skel->bss->test_result_fexit); - -out: - if (pb) - perf_buffer__free(pb); - test_xdp__destroy(pkt_skel); - test_xdp_bpf2bpf__destroy(ftrace_skel); -} diff --git a/tools/testing/selftests/bpf/prog_tests/xdp_devmap_attach.c b/tools/testing/selftests/bpf/prog_tests/xdp_devmap_attach.c deleted file mode 100644 index 88ef3ec8ac4c..000000000000 --- a/tools/testing/selftests/bpf/prog_tests/xdp_devmap_attach.c +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include - -#include "test_xdp_devmap_helpers.skel.h" -#include "test_xdp_with_devmap_helpers.skel.h" - -#define IFINDEX_LO 1 - -void test_xdp_with_devmap_helpers(void) -{ - struct test_xdp_with_devmap_helpers *skel; - struct bpf_prog_info info = {}; - struct bpf_devmap_val val = { - .ifindex = IFINDEX_LO, - }; - __u32 len = sizeof(info); - __u32 duration = 0, idx = 0; - int err, dm_fd, map_fd; - - - skel = test_xdp_with_devmap_helpers__open_and_load(); - if (CHECK_FAIL(!skel)) { - perror("test_xdp_with_devmap_helpers__open_and_load"); - return; - } - - /* can not attach program with DEVMAPs that allow programs - * as xdp generic - */ - dm_fd = bpf_program__fd(skel->progs.xdp_redir_prog); - err = bpf_set_link_xdp_fd(IFINDEX_LO, dm_fd, XDP_FLAGS_SKB_MODE); - CHECK(err == 0, "Generic attach of program with 8-byte devmap", - "should have failed\n"); - - dm_fd = bpf_program__fd(skel->progs.xdp_dummy_dm); - map_fd = bpf_map__fd(skel->maps.dm_ports); - err = bpf_obj_get_info_by_fd(dm_fd, &info, &len); - if (CHECK_FAIL(err)) - goto out_close; - - val.bpf_prog.fd = dm_fd; - err = bpf_map_update_elem(map_fd, &idx, &val, 0); - CHECK(err, "Add program to devmap entry", - "err %d errno %d\n", err, errno); - - err = bpf_map_lookup_elem(map_fd, &idx, &val); - CHECK(err, "Read devmap entry", "err %d errno %d\n", err, errno); - CHECK(info.id != val.bpf_prog.id, "Expected program id in devmap entry", - "expected %u read %u\n", info.id, val.bpf_prog.id); - - /* can not attach BPF_XDP_DEVMAP program to a device */ - err = bpf_set_link_xdp_fd(IFINDEX_LO, dm_fd, XDP_FLAGS_SKB_MODE); - CHECK(err == 0, "Attach of BPF_XDP_DEVMAP program", - "should have failed\n"); - - val.ifindex = 1; - val.bpf_prog.fd = bpf_program__fd(skel->progs.xdp_dummy_prog); - err = bpf_map_update_elem(map_fd, &idx, &val, 0); - CHECK(err == 0, "Add non-BPF_XDP_DEVMAP program to devmap entry", - "should have failed\n"); - -out_close: - test_xdp_with_devmap_helpers__destroy(skel); -} - -void test_neg_xdp_devmap_helpers(void) -{ - struct test_xdp_devmap_helpers *skel; - __u32 duration = 0; - - skel = test_xdp_devmap_helpers__open_and_load(); - if (CHECK(skel, - "Load of XDP program accessing egress ifindex without attach type", - "should have failed\n")) { - test_xdp_devmap_helpers__destroy(skel); - } -} - - -void test_xdp_devmap_attach(void) -{ - if (test__start_subtest("DEVMAP with programs in entries")) - test_xdp_with_devmap_helpers(); - - if (test__start_subtest("Verifier check of DEVMAP programs")) - test_neg_xdp_devmap_helpers(); -} diff --git a/tools/testing/selftests/bpf/progs/connect_force_port4.c b/tools/testing/selftests/bpf/progs/connect_force_port4.c deleted file mode 100644 index 1b8eb34b2db0..000000000000 --- a/tools/testing/selftests/bpf/progs/connect_force_port4.c +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -#include -#include -#include -#include - -#include -#include - -char _license[] SEC("license") = "GPL"; -int _version SEC("version") = 1; - -SEC("cgroup/connect4") -int _connect4(struct bpf_sock_addr *ctx) -{ - struct sockaddr_in sa = {}; - - sa.sin_family = AF_INET; - sa.sin_port = bpf_htons(22222); - sa.sin_addr.s_addr = bpf_htonl(0x7f000001); /* 127.0.0.1 */ - - if (bpf_bind(ctx, (struct sockaddr *)&sa, sizeof(sa)) != 0) - return 0; - - return 1; -} diff --git a/tools/testing/selftests/bpf/progs/connect_force_port6.c b/tools/testing/selftests/bpf/progs/connect_force_port6.c deleted file mode 100644 index ae6f7d750b4c..000000000000 --- a/tools/testing/selftests/bpf/progs/connect_force_port6.c +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -#include -#include -#include -#include - -#include -#include - -char _license[] SEC("license") = "GPL"; -int _version SEC("version") = 1; - -SEC("cgroup/connect6") -int _connect6(struct bpf_sock_addr *ctx) -{ - struct sockaddr_in6 sa = {}; - - sa.sin6_family = AF_INET6; - sa.sin6_port = bpf_htons(22223); - sa.sin6_addr.s6_addr32[3] = bpf_htonl(1); /* ::1 */ - - if (bpf_bind(ctx, (struct sockaddr *)&sa, sizeof(sa)) != 0) - return 0; - - return 1; -} diff --git a/tools/testing/selftests/bpf/progs/lsm.c b/tools/testing/selftests/bpf/progs/lsm.c deleted file mode 100644 index a4e3c223028d..000000000000 --- a/tools/testing/selftests/bpf/progs/lsm.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* - * Copyright 2020 Google LLC. - */ - -#include "vmlinux.h" -#include -#include -#include - -char _license[] SEC("license") = "GPL"; - -int monitored_pid = 0; -int mprotect_count = 0; -int bprm_count = 0; - -SEC("lsm/file_mprotect") -int BPF_PROG(test_int_hook, struct vm_area_struct *vma, - unsigned long reqprot, unsigned long prot, int ret) -{ - if (ret != 0) - return ret; - - __u32 pid = bpf_get_current_pid_tgid() >> 32; - int is_heap = 0; - - is_heap = (vma->vm_start >= vma->vm_mm->start_brk && - vma->vm_end <= vma->vm_mm->brk); - - if (is_heap && monitored_pid == pid) { - mprotect_count++; - ret = -EPERM; - } - - return ret; -} - -SEC("lsm/bprm_committed_creds") -int BPF_PROG(test_void_hook, struct linux_binprm *bprm) -{ - __u32 pid = bpf_get_current_pid_tgid() >> 32; - - if (monitored_pid == pid) - bprm_count++; - - return 0; -} diff --git a/tools/testing/selftests/bpf/progs/map_ptr_kern.c b/tools/testing/selftests/bpf/progs/map_ptr_kern.c deleted file mode 100644 index 982a2d8aa844..000000000000 --- a/tools/testing/selftests/bpf/progs/map_ptr_kern.c +++ /dev/null @@ -1,686 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2020 Facebook - -#include -#include - -#define LOOP_BOUND 0xf -#define MAX_ENTRIES 8 -#define HALF_ENTRIES (MAX_ENTRIES >> 1) - -_Static_assert(MAX_ENTRIES < LOOP_BOUND, "MAX_ENTRIES must be < LOOP_BOUND"); - -enum bpf_map_type g_map_type = BPF_MAP_TYPE_UNSPEC; -__u32 g_line = 0; - -#define VERIFY_TYPE(type, func) ({ \ - g_map_type = type; \ - if (!func()) \ - return 0; \ -}) - - -#define VERIFY(expr) ({ \ - g_line = __LINE__; \ - if (!(expr)) \ - return 0; \ -}) - -struct bpf_map_memory { - __u32 pages; -} __attribute__((preserve_access_index)); - -struct bpf_map { - enum bpf_map_type map_type; - __u32 key_size; - __u32 value_size; - __u32 max_entries; - __u32 id; - struct bpf_map_memory memory; -} __attribute__((preserve_access_index)); - -static inline int check_bpf_map_fields(struct bpf_map *map, __u32 key_size, - __u32 value_size, __u32 max_entries) -{ - VERIFY(map->map_type == g_map_type); - VERIFY(map->key_size == key_size); - VERIFY(map->value_size == value_size); - VERIFY(map->max_entries == max_entries); - VERIFY(map->id > 0); - VERIFY(map->memory.pages > 0); - - return 1; -} - -static inline int check_bpf_map_ptr(struct bpf_map *indirect, - struct bpf_map *direct) -{ - VERIFY(indirect->map_type == direct->map_type); - VERIFY(indirect->key_size == direct->key_size); - VERIFY(indirect->value_size == direct->value_size); - VERIFY(indirect->max_entries == direct->max_entries); - VERIFY(indirect->id == direct->id); - VERIFY(indirect->memory.pages == direct->memory.pages); - - return 1; -} - -static inline int check(struct bpf_map *indirect, struct bpf_map *direct, - __u32 key_size, __u32 value_size, __u32 max_entries) -{ - VERIFY(check_bpf_map_ptr(indirect, direct)); - VERIFY(check_bpf_map_fields(indirect, key_size, value_size, - max_entries)); - return 1; -} - -static inline int check_default(struct bpf_map *indirect, - struct bpf_map *direct) -{ - VERIFY(check(indirect, direct, sizeof(__u32), sizeof(__u32), - MAX_ENTRIES)); - return 1; -} - -typedef struct { - int counter; -} atomic_t; - -struct bpf_htab { - struct bpf_map map; - atomic_t count; - __u32 n_buckets; - __u32 elem_size; -} __attribute__((preserve_access_index)); - -struct { - __uint(type, BPF_MAP_TYPE_HASH); - __uint(map_flags, BPF_F_NO_PREALLOC); /* to test bpf_htab.count */ - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); -} m_hash SEC(".maps"); - -static inline int check_hash(void) -{ - struct bpf_htab *hash = (struct bpf_htab *)&m_hash; - struct bpf_map *map = (struct bpf_map *)&m_hash; - int i; - - VERIFY(check_default(&hash->map, map)); - - VERIFY(hash->n_buckets == MAX_ENTRIES); - VERIFY(hash->elem_size == 64); - - VERIFY(hash->count.counter == 0); - for (i = 0; i < HALF_ENTRIES; ++i) { - const __u32 key = i; - const __u32 val = 1; - - if (bpf_map_update_elem(hash, &key, &val, 0)) - return 0; - } - VERIFY(hash->count.counter == HALF_ENTRIES); - - return 1; -} - -struct bpf_array { - struct bpf_map map; - __u32 elem_size; -} __attribute__((preserve_access_index)); - -struct { - __uint(type, BPF_MAP_TYPE_ARRAY); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); -} m_array SEC(".maps"); - -static inline int check_array(void) -{ - struct bpf_array *array = (struct bpf_array *)&m_array; - struct bpf_map *map = (struct bpf_map *)&m_array; - int i, n_lookups = 0, n_keys = 0; - - VERIFY(check_default(&array->map, map)); - - VERIFY(array->elem_size == 8); - - for (i = 0; i < array->map.max_entries && i < LOOP_BOUND; ++i) { - const __u32 key = i; - __u32 *val = bpf_map_lookup_elem(array, &key); - - ++n_lookups; - if (val) - ++n_keys; - } - - VERIFY(n_lookups == MAX_ENTRIES); - VERIFY(n_keys == MAX_ENTRIES); - - return 1; -} - -struct { - __uint(type, BPF_MAP_TYPE_PROG_ARRAY); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); -} m_prog_array SEC(".maps"); - -static inline int check_prog_array(void) -{ - struct bpf_array *prog_array = (struct bpf_array *)&m_prog_array; - struct bpf_map *map = (struct bpf_map *)&m_prog_array; - - VERIFY(check_default(&prog_array->map, map)); - - return 1; -} - -struct { - __uint(type, BPF_MAP_TYPE_PERF_EVENT_ARRAY); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); -} m_perf_event_array SEC(".maps"); - -static inline int check_perf_event_array(void) -{ - struct bpf_array *perf_event_array = (struct bpf_array *)&m_perf_event_array; - struct bpf_map *map = (struct bpf_map *)&m_perf_event_array; - - VERIFY(check_default(&perf_event_array->map, map)); - - return 1; -} - -struct { - __uint(type, BPF_MAP_TYPE_PERCPU_HASH); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); -} m_percpu_hash SEC(".maps"); - -static inline int check_percpu_hash(void) -{ - struct bpf_htab *percpu_hash = (struct bpf_htab *)&m_percpu_hash; - struct bpf_map *map = (struct bpf_map *)&m_percpu_hash; - - VERIFY(check_default(&percpu_hash->map, map)); - - return 1; -} - -struct { - __uint(type, BPF_MAP_TYPE_PERCPU_ARRAY); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); -} m_percpu_array SEC(".maps"); - -static inline int check_percpu_array(void) -{ - struct bpf_array *percpu_array = (struct bpf_array *)&m_percpu_array; - struct bpf_map *map = (struct bpf_map *)&m_percpu_array; - - VERIFY(check_default(&percpu_array->map, map)); - - return 1; -} - -struct bpf_stack_map { - struct bpf_map map; -} __attribute__((preserve_access_index)); - -struct { - __uint(type, BPF_MAP_TYPE_STACK_TRACE); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u64); -} m_stack_trace SEC(".maps"); - -static inline int check_stack_trace(void) -{ - struct bpf_stack_map *stack_trace = - (struct bpf_stack_map *)&m_stack_trace; - struct bpf_map *map = (struct bpf_map *)&m_stack_trace; - - VERIFY(check(&stack_trace->map, map, sizeof(__u32), sizeof(__u64), - MAX_ENTRIES)); - - return 1; -} - -struct { - __uint(type, BPF_MAP_TYPE_CGROUP_ARRAY); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); -} m_cgroup_array SEC(".maps"); - -static inline int check_cgroup_array(void) -{ - struct bpf_array *cgroup_array = (struct bpf_array *)&m_cgroup_array; - struct bpf_map *map = (struct bpf_map *)&m_cgroup_array; - - VERIFY(check_default(&cgroup_array->map, map)); - - return 1; -} - -struct { - __uint(type, BPF_MAP_TYPE_LRU_HASH); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); -} m_lru_hash SEC(".maps"); - -static inline int check_lru_hash(void) -{ - struct bpf_htab *lru_hash = (struct bpf_htab *)&m_lru_hash; - struct bpf_map *map = (struct bpf_map *)&m_lru_hash; - - VERIFY(check_default(&lru_hash->map, map)); - - return 1; -} - -struct { - __uint(type, BPF_MAP_TYPE_LRU_PERCPU_HASH); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); -} m_lru_percpu_hash SEC(".maps"); - -static inline int check_lru_percpu_hash(void) -{ - struct bpf_htab *lru_percpu_hash = (struct bpf_htab *)&m_lru_percpu_hash; - struct bpf_map *map = (struct bpf_map *)&m_lru_percpu_hash; - - VERIFY(check_default(&lru_percpu_hash->map, map)); - - return 1; -} - -struct lpm_trie { - struct bpf_map map; -} __attribute__((preserve_access_index)); - -struct lpm_key { - struct bpf_lpm_trie_key trie_key; - __u32 data; -}; - -struct { - __uint(type, BPF_MAP_TYPE_LPM_TRIE); - __uint(map_flags, BPF_F_NO_PREALLOC); - __uint(max_entries, MAX_ENTRIES); - __type(key, struct lpm_key); - __type(value, __u32); -} m_lpm_trie SEC(".maps"); - -static inline int check_lpm_trie(void) -{ - struct lpm_trie *lpm_trie = (struct lpm_trie *)&m_lpm_trie; - struct bpf_map *map = (struct bpf_map *)&m_lpm_trie; - - VERIFY(check(&lpm_trie->map, map, sizeof(struct lpm_key), sizeof(__u32), - MAX_ENTRIES)); - - return 1; -} - -struct inner_map { - __uint(type, BPF_MAP_TYPE_ARRAY); - __uint(max_entries, 1); - __type(key, __u32); - __type(value, __u32); -} inner_map SEC(".maps"); - -struct { - __uint(type, BPF_MAP_TYPE_ARRAY_OF_MAPS); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); - __array(values, struct { - __uint(type, BPF_MAP_TYPE_ARRAY); - __uint(max_entries, 1); - __type(key, __u32); - __type(value, __u32); - }); -} m_array_of_maps SEC(".maps") = { - .values = { (void *)&inner_map, 0, 0, 0, 0, 0, 0, 0, 0 }, -}; - -static inline int check_array_of_maps(void) -{ - struct bpf_array *array_of_maps = (struct bpf_array *)&m_array_of_maps; - struct bpf_map *map = (struct bpf_map *)&m_array_of_maps; - - VERIFY(check_default(&array_of_maps->map, map)); - - return 1; -} - -struct { - __uint(type, BPF_MAP_TYPE_HASH_OF_MAPS); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); - __array(values, struct inner_map); -} m_hash_of_maps SEC(".maps") = { - .values = { - [2] = &inner_map, - }, -}; - -static inline int check_hash_of_maps(void) -{ - struct bpf_htab *hash_of_maps = (struct bpf_htab *)&m_hash_of_maps; - struct bpf_map *map = (struct bpf_map *)&m_hash_of_maps; - - VERIFY(check_default(&hash_of_maps->map, map)); - - return 1; -} - -struct bpf_dtab { - struct bpf_map map; -} __attribute__((preserve_access_index)); - -struct { - __uint(type, BPF_MAP_TYPE_DEVMAP); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); -} m_devmap SEC(".maps"); - -static inline int check_devmap(void) -{ - struct bpf_dtab *devmap = (struct bpf_dtab *)&m_devmap; - struct bpf_map *map = (struct bpf_map *)&m_devmap; - - VERIFY(check_default(&devmap->map, map)); - - return 1; -} - -struct bpf_stab { - struct bpf_map map; -} __attribute__((preserve_access_index)); - -struct { - __uint(type, BPF_MAP_TYPE_SOCKMAP); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); -} m_sockmap SEC(".maps"); - -static inline int check_sockmap(void) -{ - struct bpf_stab *sockmap = (struct bpf_stab *)&m_sockmap; - struct bpf_map *map = (struct bpf_map *)&m_sockmap; - - VERIFY(check_default(&sockmap->map, map)); - - return 1; -} - -struct bpf_cpu_map { - struct bpf_map map; -} __attribute__((preserve_access_index)); - -struct { - __uint(type, BPF_MAP_TYPE_CPUMAP); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); -} m_cpumap SEC(".maps"); - -static inline int check_cpumap(void) -{ - struct bpf_cpu_map *cpumap = (struct bpf_cpu_map *)&m_cpumap; - struct bpf_map *map = (struct bpf_map *)&m_cpumap; - - VERIFY(check_default(&cpumap->map, map)); - - return 1; -} - -struct xsk_map { - struct bpf_map map; -} __attribute__((preserve_access_index)); - -struct { - __uint(type, BPF_MAP_TYPE_XSKMAP); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); -} m_xskmap SEC(".maps"); - -static inline int check_xskmap(void) -{ - struct xsk_map *xskmap = (struct xsk_map *)&m_xskmap; - struct bpf_map *map = (struct bpf_map *)&m_xskmap; - - VERIFY(check_default(&xskmap->map, map)); - - return 1; -} - -struct bpf_shtab { - struct bpf_map map; -} __attribute__((preserve_access_index)); - -struct { - __uint(type, BPF_MAP_TYPE_SOCKHASH); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); -} m_sockhash SEC(".maps"); - -static inline int check_sockhash(void) -{ - struct bpf_shtab *sockhash = (struct bpf_shtab *)&m_sockhash; - struct bpf_map *map = (struct bpf_map *)&m_sockhash; - - VERIFY(check_default(&sockhash->map, map)); - - return 1; -} - -struct bpf_cgroup_storage_map { - struct bpf_map map; -} __attribute__((preserve_access_index)); - -struct { - __uint(type, BPF_MAP_TYPE_CGROUP_STORAGE); - __type(key, struct bpf_cgroup_storage_key); - __type(value, __u32); -} m_cgroup_storage SEC(".maps"); - -static inline int check_cgroup_storage(void) -{ - struct bpf_cgroup_storage_map *cgroup_storage = - (struct bpf_cgroup_storage_map *)&m_cgroup_storage; - struct bpf_map *map = (struct bpf_map *)&m_cgroup_storage; - - VERIFY(check(&cgroup_storage->map, map, - sizeof(struct bpf_cgroup_storage_key), sizeof(__u32), 0)); - - return 1; -} - -struct reuseport_array { - struct bpf_map map; -} __attribute__((preserve_access_index)); - -struct { - __uint(type, BPF_MAP_TYPE_REUSEPORT_SOCKARRAY); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); -} m_reuseport_sockarray SEC(".maps"); - -static inline int check_reuseport_sockarray(void) -{ - struct reuseport_array *reuseport_sockarray = - (struct reuseport_array *)&m_reuseport_sockarray; - struct bpf_map *map = (struct bpf_map *)&m_reuseport_sockarray; - - VERIFY(check_default(&reuseport_sockarray->map, map)); - - return 1; -} - -struct { - __uint(type, BPF_MAP_TYPE_PERCPU_CGROUP_STORAGE); - __type(key, struct bpf_cgroup_storage_key); - __type(value, __u32); -} m_percpu_cgroup_storage SEC(".maps"); - -static inline int check_percpu_cgroup_storage(void) -{ - struct bpf_cgroup_storage_map *percpu_cgroup_storage = - (struct bpf_cgroup_storage_map *)&m_percpu_cgroup_storage; - struct bpf_map *map = (struct bpf_map *)&m_percpu_cgroup_storage; - - VERIFY(check(&percpu_cgroup_storage->map, map, - sizeof(struct bpf_cgroup_storage_key), sizeof(__u32), 0)); - - return 1; -} - -struct bpf_queue_stack { - struct bpf_map map; -} __attribute__((preserve_access_index)); - -struct { - __uint(type, BPF_MAP_TYPE_QUEUE); - __uint(max_entries, MAX_ENTRIES); - __type(value, __u32); -} m_queue SEC(".maps"); - -static inline int check_queue(void) -{ - struct bpf_queue_stack *queue = (struct bpf_queue_stack *)&m_queue; - struct bpf_map *map = (struct bpf_map *)&m_queue; - - VERIFY(check(&queue->map, map, 0, sizeof(__u32), MAX_ENTRIES)); - - return 1; -} - -struct { - __uint(type, BPF_MAP_TYPE_STACK); - __uint(max_entries, MAX_ENTRIES); - __type(value, __u32); -} m_stack SEC(".maps"); - -static inline int check_stack(void) -{ - struct bpf_queue_stack *stack = (struct bpf_queue_stack *)&m_stack; - struct bpf_map *map = (struct bpf_map *)&m_stack; - - VERIFY(check(&stack->map, map, 0, sizeof(__u32), MAX_ENTRIES)); - - return 1; -} - -struct bpf_local_storage_map { - struct bpf_map map; -} __attribute__((preserve_access_index)); - -struct { - __uint(type, BPF_MAP_TYPE_SK_STORAGE); - __uint(map_flags, BPF_F_NO_PREALLOC); - __type(key, __u32); - __type(value, __u32); -} m_sk_storage SEC(".maps"); - -static inline int check_sk_storage(void) -{ - struct bpf_local_storage_map *sk_storage = - (struct bpf_local_storage_map *)&m_sk_storage; - struct bpf_map *map = (struct bpf_map *)&m_sk_storage; - - VERIFY(check(&sk_storage->map, map, sizeof(__u32), sizeof(__u32), 0)); - - return 1; -} - -struct { - __uint(type, BPF_MAP_TYPE_DEVMAP_HASH); - __uint(max_entries, MAX_ENTRIES); - __type(key, __u32); - __type(value, __u32); -} m_devmap_hash SEC(".maps"); - -static inline int check_devmap_hash(void) -{ - struct bpf_dtab *devmap_hash = (struct bpf_dtab *)&m_devmap_hash; - struct bpf_map *map = (struct bpf_map *)&m_devmap_hash; - - VERIFY(check_default(&devmap_hash->map, map)); - - return 1; -} - -struct bpf_ringbuf_map { - struct bpf_map map; -} __attribute__((preserve_access_index)); - -struct { - __uint(type, BPF_MAP_TYPE_RINGBUF); - __uint(max_entries, 1 << 12); -} m_ringbuf SEC(".maps"); - -static inline int check_ringbuf(void) -{ - struct bpf_ringbuf_map *ringbuf = (struct bpf_ringbuf_map *)&m_ringbuf; - struct bpf_map *map = (struct bpf_map *)&m_ringbuf; - - VERIFY(check(&ringbuf->map, map, 0, 0, 1 << 12)); - - return 1; -} - -SEC("cgroup_skb/egress") -int cg_skb(void *ctx) -{ - VERIFY_TYPE(BPF_MAP_TYPE_HASH, check_hash); - VERIFY_TYPE(BPF_MAP_TYPE_ARRAY, check_array); - VERIFY_TYPE(BPF_MAP_TYPE_PROG_ARRAY, check_prog_array); - VERIFY_TYPE(BPF_MAP_TYPE_PERF_EVENT_ARRAY, check_perf_event_array); - VERIFY_TYPE(BPF_MAP_TYPE_PERCPU_HASH, check_percpu_hash); - VERIFY_TYPE(BPF_MAP_TYPE_PERCPU_ARRAY, check_percpu_array); - VERIFY_TYPE(BPF_MAP_TYPE_STACK_TRACE, check_stack_trace); - VERIFY_TYPE(BPF_MAP_TYPE_CGROUP_ARRAY, check_cgroup_array); - VERIFY_TYPE(BPF_MAP_TYPE_LRU_HASH, check_lru_hash); - VERIFY_TYPE(BPF_MAP_TYPE_LRU_PERCPU_HASH, check_lru_percpu_hash); - VERIFY_TYPE(BPF_MAP_TYPE_LPM_TRIE, check_lpm_trie); - VERIFY_TYPE(BPF_MAP_TYPE_ARRAY_OF_MAPS, check_array_of_maps); - VERIFY_TYPE(BPF_MAP_TYPE_HASH_OF_MAPS, check_hash_of_maps); - VERIFY_TYPE(BPF_MAP_TYPE_DEVMAP, check_devmap); - VERIFY_TYPE(BPF_MAP_TYPE_SOCKMAP, check_sockmap); - VERIFY_TYPE(BPF_MAP_TYPE_CPUMAP, check_cpumap); - VERIFY_TYPE(BPF_MAP_TYPE_XSKMAP, check_xskmap); - VERIFY_TYPE(BPF_MAP_TYPE_SOCKHASH, check_sockhash); - VERIFY_TYPE(BPF_MAP_TYPE_CGROUP_STORAGE, check_cgroup_storage); - VERIFY_TYPE(BPF_MAP_TYPE_REUSEPORT_SOCKARRAY, - check_reuseport_sockarray); - VERIFY_TYPE(BPF_MAP_TYPE_PERCPU_CGROUP_STORAGE, - check_percpu_cgroup_storage); - VERIFY_TYPE(BPF_MAP_TYPE_QUEUE, check_queue); - VERIFY_TYPE(BPF_MAP_TYPE_STACK, check_stack); - VERIFY_TYPE(BPF_MAP_TYPE_SK_STORAGE, check_sk_storage); - VERIFY_TYPE(BPF_MAP_TYPE_DEVMAP_HASH, check_devmap_hash); - VERIFY_TYPE(BPF_MAP_TYPE_RINGBUF, check_ringbuf); - - return 1; -} - -__u32 _version SEC("version") = 1; -char _license[] SEC("license") = "GPL"; diff --git a/tools/testing/selftests/bpf/progs/modify_return.c b/tools/testing/selftests/bpf/progs/modify_return.c deleted file mode 100644 index 8b7466a15c6b..000000000000 --- a/tools/testing/selftests/bpf/progs/modify_return.c +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* - * Copyright 2020 Google LLC. - */ - -#include -#include -#include - -char _license[] SEC("license") = "GPL"; - -static int sequence = 0; -__s32 input_retval = 0; - -__u64 fentry_result = 0; -SEC("fentry/bpf_modify_return_test") -int BPF_PROG(fentry_test, int a, __u64 b) -{ - sequence++; - fentry_result = (sequence == 1); - return 0; -} - -__u64 fmod_ret_result = 0; -SEC("fmod_ret/bpf_modify_return_test") -int BPF_PROG(fmod_ret_test, int a, int *b, int ret) -{ - sequence++; - /* This is the first fmod_ret program, the ret passed should be 0 */ - fmod_ret_result = (sequence == 2 && ret == 0); - return input_retval; -} - -__u64 fexit_result = 0; -SEC("fexit/bpf_modify_return_test") -int BPF_PROG(fexit_test, int a, __u64 b, int ret) -{ - sequence++; - /* If the input_reval is non-zero a successful modification should have - * occurred. - */ - if (input_retval) - fexit_result = (sequence == 3 && ret == input_retval); - else - fexit_result = (sequence == 3 && ret == 4); - - return 0; -} diff --git a/tools/testing/selftests/bpf/progs/test_d_path.c b/tools/testing/selftests/bpf/progs/test_d_path.c deleted file mode 100644 index 84e1f883f97b..000000000000 --- a/tools/testing/selftests/bpf/progs/test_d_path.c +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "vmlinux.h" -#include -#include - -#define MAX_PATH_LEN 128 -#define MAX_FILES 7 - -pid_t my_pid = 0; -__u32 cnt_stat = 0; -__u32 cnt_close = 0; -char paths_stat[MAX_FILES][MAX_PATH_LEN] = {}; -char paths_close[MAX_FILES][MAX_PATH_LEN] = {}; -int rets_stat[MAX_FILES] = {}; -int rets_close[MAX_FILES] = {}; - -int called_stat = 0; -int called_close = 0; - -SEC("fentry/security_inode_getattr") -int BPF_PROG(prog_stat, struct path *path, struct kstat *stat, - __u32 request_mask, unsigned int query_flags) -{ - pid_t pid = bpf_get_current_pid_tgid() >> 32; - __u32 cnt = cnt_stat; - int ret; - - called_stat = 1; - - if (pid != my_pid) - return 0; - - if (cnt >= MAX_FILES) - return 0; - ret = bpf_d_path(path, paths_stat[cnt], MAX_PATH_LEN); - - rets_stat[cnt] = ret; - cnt_stat++; - return 0; -} - -SEC("fentry/filp_close") -int BPF_PROG(prog_close, struct file *file, void *id) -{ - pid_t pid = bpf_get_current_pid_tgid() >> 32; - __u32 cnt = cnt_close; - int ret; - - called_close = 1; - - if (pid != my_pid) - return 0; - - if (cnt >= MAX_FILES) - return 0; - ret = bpf_d_path(&file->f_path, - paths_close[cnt], MAX_PATH_LEN); - - rets_close[cnt] = ret; - cnt_close++; - return 0; -} - -char _license[] SEC("license") = "GPL"; diff --git a/tools/testing/selftests/bpf/progs/test_global_func1.c b/tools/testing/selftests/bpf/progs/test_global_func1.c deleted file mode 100644 index 97d57d6e244e..000000000000 --- a/tools/testing/selftests/bpf/progs/test_global_func1.c +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2020 Facebook */ -#include -#include -#include "bpf_helpers.h" - -#ifndef MAX_STACK -#define MAX_STACK (512 - 3 * 32 + 8) -#endif - -static __attribute__ ((noinline)) -int f0(int var, struct __sk_buff *skb) -{ - return skb->len; -} - -__attribute__ ((noinline)) -int f1(struct __sk_buff *skb) -{ - volatile char buf[MAX_STACK] = {}; - - return f0(0, skb) + skb->len; -} - -int f3(int, struct __sk_buff *skb, int); - -__attribute__ ((noinline)) -int f2(int val, struct __sk_buff *skb) -{ - return f1(skb) + f3(val, skb, 1); -} - -__attribute__ ((noinline)) -int f3(int val, struct __sk_buff *skb, int var) -{ - volatile char buf[MAX_STACK] = {}; - - return skb->ifindex * val * var; -} - -SEC("classifier/test") -int test_cls(struct __sk_buff *skb) -{ - return f0(1, skb) + f1(skb) + f2(2, skb) + f3(3, skb, 4); -} diff --git a/tools/testing/selftests/bpf/progs/test_global_func10.c b/tools/testing/selftests/bpf/progs/test_global_func10.c deleted file mode 100644 index 8fba3f3649e2..000000000000 --- a/tools/testing/selftests/bpf/progs/test_global_func10.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -#include -#include -#include -#include "bpf_misc.h" - -struct Small { - long x; -}; - -struct Big { - long x; - long y; -}; - -__noinline int foo(const struct Big *big) -{ - if (!big) - return 0; - - return bpf_get_prandom_u32() < big->y; -} - -SEC("cgroup_skb/ingress") -__failure __msg("invalid indirect access to stack") -int global_func10(struct __sk_buff *skb) -{ - const struct Small small = {.x = skb->len }; - - return foo((struct Big *)&small) ? 1 : 0; -} diff --git a/tools/testing/selftests/bpf/progs/test_global_func2.c b/tools/testing/selftests/bpf/progs/test_global_func2.c deleted file mode 100644 index 2c18d82923a2..000000000000 --- a/tools/testing/selftests/bpf/progs/test_global_func2.c +++ /dev/null @@ -1,4 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2020 Facebook */ -#define MAX_STACK (512 - 3 * 32) -#include "test_global_func1.c" diff --git a/tools/testing/selftests/bpf/progs/test_global_func3.c b/tools/testing/selftests/bpf/progs/test_global_func3.c deleted file mode 100644 index 514ecf9f51b0..000000000000 --- a/tools/testing/selftests/bpf/progs/test_global_func3.c +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2020 Facebook */ -#include -#include -#include "bpf_helpers.h" - -__attribute__ ((noinline)) -int f1(struct __sk_buff *skb) -{ - return skb->len; -} - -__attribute__ ((noinline)) -int f2(int val, struct __sk_buff *skb) -{ - return f1(skb) + val; -} - -__attribute__ ((noinline)) -int f3(int val, struct __sk_buff *skb, int var) -{ - return f2(var, skb) + val; -} - -__attribute__ ((noinline)) -int f4(struct __sk_buff *skb) -{ - return f3(1, skb, 2); -} - -__attribute__ ((noinline)) -int f5(struct __sk_buff *skb) -{ - return f4(skb); -} - -__attribute__ ((noinline)) -int f6(struct __sk_buff *skb) -{ - return f5(skb); -} - -__attribute__ ((noinline)) -int f7(struct __sk_buff *skb) -{ - return f6(skb); -} - -#ifndef NO_FN8 -__attribute__ ((noinline)) -int f8(struct __sk_buff *skb) -{ - return f7(skb); -} -#endif - -SEC("classifier/test") -int test_cls(struct __sk_buff *skb) -{ -#ifndef NO_FN8 - return f8(skb); -#else - return f7(skb); -#endif -} diff --git a/tools/testing/selftests/bpf/progs/test_global_func4.c b/tools/testing/selftests/bpf/progs/test_global_func4.c deleted file mode 100644 index 610f75edf276..000000000000 --- a/tools/testing/selftests/bpf/progs/test_global_func4.c +++ /dev/null @@ -1,4 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2020 Facebook */ -#define NO_FN8 -#include "test_global_func3.c" diff --git a/tools/testing/selftests/bpf/progs/test_global_func5.c b/tools/testing/selftests/bpf/progs/test_global_func5.c deleted file mode 100644 index 86787c03cea8..000000000000 --- a/tools/testing/selftests/bpf/progs/test_global_func5.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2020 Facebook */ -#include -#include -#include "bpf_helpers.h" - -__attribute__ ((noinline)) -int f1(struct __sk_buff *skb) -{ - return skb->len; -} - -int f3(int, struct __sk_buff *skb); - -__attribute__ ((noinline)) -int f2(int val, struct __sk_buff *skb) -{ - return f1(skb) + f3(val, (void *)&val); /* type mismatch */ -} - -__attribute__ ((noinline)) -int f3(int val, struct __sk_buff *skb) -{ - return skb->ifindex * val; -} - -SEC("classifier/test") -int test_cls(struct __sk_buff *skb) -{ - return f1(skb) + f2(2, skb) + f3(3, skb); -} diff --git a/tools/testing/selftests/bpf/progs/test_global_func6.c b/tools/testing/selftests/bpf/progs/test_global_func6.c deleted file mode 100644 index e215fb3e6f02..000000000000 --- a/tools/testing/selftests/bpf/progs/test_global_func6.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2020 Facebook */ -#include -#include -#include "bpf_helpers.h" - -__attribute__ ((noinline)) -int f1(struct __sk_buff *skb) -{ - return skb->len; -} - -int f3(int, struct __sk_buff *skb); - -__attribute__ ((noinline)) -int f2(int val, struct __sk_buff *skb) -{ - return f1(skb) + f3(val, skb + 1); /* type mismatch */ -} - -__attribute__ ((noinline)) -int f3(int val, struct __sk_buff *skb) -{ - return skb->ifindex * val; -} - -SEC("classifier/test") -int test_cls(struct __sk_buff *skb) -{ - return f1(skb) + f2(2, skb) + f3(3, skb); -} diff --git a/tools/testing/selftests/bpf/progs/test_global_func7.c b/tools/testing/selftests/bpf/progs/test_global_func7.c deleted file mode 100644 index ff98d93916fd..000000000000 --- a/tools/testing/selftests/bpf/progs/test_global_func7.c +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2020 Facebook */ -#include -#include -#include "bpf_helpers.h" - -__attribute__ ((noinline)) -void foo(struct __sk_buff *skb) -{ - skb->tc_index = 0; -} - -SEC("classifier/test") -int test_cls(struct __sk_buff *skb) -{ - foo(skb); - return 0; -} diff --git a/tools/testing/selftests/bpf/progs/test_global_func8.c b/tools/testing/selftests/bpf/progs/test_global_func8.c deleted file mode 100644 index d55a6544b1ab..000000000000 --- a/tools/testing/selftests/bpf/progs/test_global_func8.c +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2020 Facebook */ -#include -#include -#include - -__noinline int foo(struct __sk_buff *skb) -{ - return bpf_get_prandom_u32(); -} - -SEC("cgroup_skb/ingress") -int test_cls(struct __sk_buff *skb) -{ - if (!foo(skb)) - return 0; - - return 1; -} diff --git a/tools/testing/selftests/bpf/progs/test_map_init.c b/tools/testing/selftests/bpf/progs/test_map_init.c deleted file mode 100644 index c89d28ead673..000000000000 --- a/tools/testing/selftests/bpf/progs/test_map_init.c +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2020 Tessares SA */ - -#include "vmlinux.h" -#include - -__u64 inKey = 0; -__u64 inValue = 0; -__u32 inPid = 0; - -struct { - __uint(type, BPF_MAP_TYPE_PERCPU_HASH); - __uint(max_entries, 2); - __type(key, __u64); - __type(value, __u64); -} hashmap1 SEC(".maps"); - - -SEC("tp/syscalls/sys_enter_getpgid") -int sysenter_getpgid(const void *ctx) -{ - /* Just do it for once, when called from our own test prog. This - * ensures the map value is only updated for a single CPU. - */ - int cur_pid = bpf_get_current_pid_tgid() >> 32; - - if (cur_pid == inPid) - bpf_map_update_elem(&hashmap1, &inKey, &inValue, BPF_NOEXIST); - - return 0; -} - -char _license[] SEC("license") = "GPL"; diff --git a/tools/testing/selftests/bpf/progs/test_perf_branches.c b/tools/testing/selftests/bpf/progs/test_perf_branches.c deleted file mode 100644 index 0f7e27d97567..000000000000 --- a/tools/testing/selftests/bpf/progs/test_perf_branches.c +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2019 Facebook - -#include -#include -#include -#include -#include "bpf_trace_helpers.h" - -int valid = 0; -int required_size_out = 0; -int written_stack_out = 0; -int written_global_out = 0; - -struct { - __u64 _a; - __u64 _b; - __u64 _c; -} fpbe[30] = {0}; - -SEC("perf_event") -int perf_branches(void *ctx) -{ - __u64 entries[4 * 3] = {0}; - int required_size, written_stack, written_global; - - /* write to stack */ - written_stack = bpf_read_branch_records(ctx, entries, sizeof(entries), 0); - /* ignore spurious events */ - if (!written_stack) - return 1; - - /* get required size */ - required_size = bpf_read_branch_records(ctx, NULL, 0, - BPF_F_GET_BRANCH_RECORDS_SIZE); - - written_global = bpf_read_branch_records(ctx, fpbe, sizeof(fpbe), 0); - /* ignore spurious events */ - if (!written_global) - return 1; - - required_size_out = required_size; - written_stack_out = written_stack; - written_global_out = written_global; - valid = 1; - - return 0; -} - -char _license[] SEC("license") = "GPL"; diff --git a/tools/testing/selftests/bpf/progs/test_skb_ctx.c b/tools/testing/selftests/bpf/progs/test_skb_ctx.c index e18da87fe84f..7a80960d7df1 100644 --- a/tools/testing/selftests/bpf/progs/test_skb_ctx.c +++ b/tools/testing/selftests/bpf/progs/test_skb_ctx.c @@ -16,13 +16,6 @@ int process(struct __sk_buff *skb) skb->cb[i]++; } skb->priority++; - skb->tstamp++; - skb->mark++; - - if (skb->wire_len != 100) - return 1; - if (skb->gso_segs != 8) - return 1; return 0; } diff --git a/tools/testing/selftests/bpf/progs/test_xdp_bpf2bpf.c b/tools/testing/selftests/bpf/progs/test_xdp_bpf2bpf.c deleted file mode 100644 index 6efe6394675f..000000000000 --- a/tools/testing/selftests/bpf/progs/test_xdp_bpf2bpf.c +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include "bpf_helpers.h" -#include "bpf_trace_helpers.h" - -char _license[] SEC("license") = "GPL"; - -struct net_device { - /* Structure does not need to contain all entries, - * as "preserve_access_index" will use BTF to fix this... - */ - int ifindex; -} __attribute__((preserve_access_index)); - -struct xdp_rxq_info { - /* Structure does not need to contain all entries, - * as "preserve_access_index" will use BTF to fix this... - */ - struct net_device *dev; - __u32 queue_index; -} __attribute__((preserve_access_index)); - -struct xdp_buff { - void *data; - void *data_end; - void *data_meta; - void *data_hard_start; - unsigned long handle; - struct xdp_rxq_info *rxq; -} __attribute__((preserve_access_index)); - -struct meta { - int ifindex; - int pkt_len; -}; - -struct { - __uint(type, BPF_MAP_TYPE_PERF_EVENT_ARRAY); - __uint(key_size, sizeof(int)); - __uint(value_size, sizeof(int)); -} perf_buf_map SEC(".maps"); - -__u64 test_result_fentry = 0; -SEC("fentry/FUNC") -int BPF_PROG(trace_on_entry, struct xdp_buff *xdp) -{ - struct meta meta; - void *data_end = (void *)(long)xdp->data_end; - void *data = (void *)(long)xdp->data; - - meta.ifindex = xdp->rxq->dev->ifindex; - meta.pkt_len = data_end - data; - bpf_xdp_output(xdp, &perf_buf_map, - ((__u64) meta.pkt_len << 32) | - BPF_F_CURRENT_CPU, - &meta, sizeof(meta)); - - test_result_fentry = xdp->rxq->dev->ifindex; - return 0; -} - -__u64 test_result_fexit = 0; -SEC("fexit/FUNC") -int BPF_PROG(trace_on_exit, struct xdp_buff *xdp, int ret) -{ - test_result_fexit = ret; - return 0; -} diff --git a/tools/testing/selftests/bpf/progs/test_xdp_devmap_helpers.c b/tools/testing/selftests/bpf/progs/test_xdp_devmap_helpers.c deleted file mode 100644 index b360ba2bd441..000000000000 --- a/tools/testing/selftests/bpf/progs/test_xdp_devmap_helpers.c +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* fails to load without expected_attach_type = BPF_XDP_DEVMAP - * because of access to egress_ifindex - */ -#include -#include - -SEC("xdp_dm_log") -int xdpdm_devlog(struct xdp_md *ctx) -{ - char fmt[] = "devmap redirect: dev %u -> dev %u len %u\n"; - void *data_end = (void *)(long)ctx->data_end; - void *data = (void *)(long)ctx->data; - unsigned int len = data_end - data; - - bpf_trace_printk(fmt, sizeof(fmt), - ctx->ingress_ifindex, ctx->egress_ifindex, len); - - return XDP_PASS; -} - -char _license[] SEC("license") = "GPL"; diff --git a/tools/testing/selftests/bpf/progs/test_xdp_with_devmap_helpers.c b/tools/testing/selftests/bpf/progs/test_xdp_with_devmap_helpers.c deleted file mode 100644 index 330811260123..000000000000 --- a/tools/testing/selftests/bpf/progs/test_xdp_with_devmap_helpers.c +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include - -struct { - __uint(type, BPF_MAP_TYPE_DEVMAP); - __uint(key_size, sizeof(__u32)); - __uint(value_size, sizeof(struct bpf_devmap_val)); - __uint(max_entries, 4); -} dm_ports SEC(".maps"); - -SEC("xdp_redir") -int xdp_redir_prog(struct xdp_md *ctx) -{ - return bpf_redirect_map(&dm_ports, 1, 0); -} - -/* invalid program on DEVMAP entry; - * SEC name means expected attach type not set - */ -SEC("xdp_dummy") -int xdp_dummy_prog(struct xdp_md *ctx) -{ - return XDP_PASS; -} - -/* valid program on DEVMAP entry via SEC name; - * has access to egress and ingress ifindex - */ -SEC("xdp_devmap") -int xdp_dummy_dm(struct xdp_md *ctx) -{ - char fmt[] = "devmap redirect: dev %u -> dev %u len %u\n"; - void *data_end = (void *)(long)ctx->data_end; - void *data = (void *)(long)ctx->data; - unsigned int len = data_end - data; - - bpf_trace_printk(fmt, sizeof(fmt), - ctx->ingress_ifindex, ctx->egress_ifindex, len); - - return XDP_PASS; -} -char _license[] SEC("license") = "GPL"; diff --git a/tools/testing/selftests/bpf/prog_tests/align.c b/tools/testing/selftests/bpf/test_align.c similarity index 91% rename from tools/testing/selftests/bpf/prog_tests/align.c rename to tools/testing/selftests/bpf/test_align.c index 52414058a627..6cc29b58d670 100644 --- a/tools/testing/selftests/bpf/prog_tests/align.c +++ b/tools/testing/selftests/bpf/test_align.c @@ -1,5 +1,24 @@ -// SPDX-License-Identifier: GPL-2.0 -#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "../../../include/linux/filter.h" +#include "bpf_rlimit.h" +#include "bpf_util.h" #define MAX_INSNS 512 #define MAX_MATCHES 16 @@ -195,13 +214,13 @@ static struct bpf_align_test tests[] = { .prog_type = BPF_PROG_TYPE_SCHED_CLS, .matches = { {7, "R3_w=inv(id=0,umax_value=255,var_off=(0x0; 0xff))"}, - {8, "R4_w=inv(id=1,umax_value=255,var_off=(0x0; 0xff))"}, + {8, "R4_w=inv(id=0,umax_value=255,var_off=(0x0; 0xff))"}, {9, "R4_w=inv(id=0,umax_value=255,var_off=(0x0; 0xff))"}, - {10, "R4_w=inv(id=1,umax_value=255,var_off=(0x0; 0xff))"}, + {10, "R4_w=inv(id=0,umax_value=255,var_off=(0x0; 0xff))"}, {11, "R4_w=inv(id=0,umax_value=510,var_off=(0x0; 0x1fe))"}, - {12, "R4_w=inv(id=1,umax_value=255,var_off=(0x0; 0xff))"}, + {12, "R4_w=inv(id=0,umax_value=255,var_off=(0x0; 0xff))"}, {13, "R4_w=inv(id=0,umax_value=1020,var_off=(0x0; 0x3fc))"}, - {14, "R4_w=inv(id=1,umax_value=255,var_off=(0x0; 0xff))"}, + {14, "R4_w=inv(id=0,umax_value=255,var_off=(0x0; 0xff))"}, {15, "R4_w=inv(id=0,umax_value=2040,var_off=(0x0; 0x7f8))"}, {16, "R4_w=inv(id=0,umax_value=4080,var_off=(0x0; 0xff0))"}, }, @@ -456,10 +475,10 @@ static struct bpf_align_test tests[] = { */ {7, "R5_w=inv(id=0,smin_value=-9223372036854775806,smax_value=9223372036854775806,umin_value=2,umax_value=18446744073709551614,var_off=(0x2; 0xfffffffffffffffc)"}, /* Checked s>=0 */ - {9, "R5=inv(id=0,umin_value=2,umax_value=9223372034707292158,var_off=(0x2; 0x7fffffff7ffffffc)"}, + {9, "R5=inv(id=0,umin_value=2,umax_value=9223372036854775806,var_off=(0x2; 0x7ffffffffffffffc))"}, /* packet pointer + nonnegative (4n+2) */ - {11, "R6_w=pkt(id=1,off=0,r=0,umin_value=2,umax_value=9223372034707292158,var_off=(0x2; 0x7fffffff7ffffffc)"}, - {13, "R4_w=pkt(id=1,off=4,r=0,umin_value=2,umax_value=9223372034707292158,var_off=(0x2; 0x7fffffff7ffffffc)"}, + {11, "R6_w=pkt(id=1,off=0,r=0,umin_value=2,umax_value=9223372036854775806,var_off=(0x2; 0x7ffffffffffffffc))"}, + {13, "R4_w=pkt(id=1,off=4,r=0,umin_value=2,umax_value=9223372036854775806,var_off=(0x2; 0x7ffffffffffffffc))"}, /* NET_IP_ALIGN + (4n+2) == (4n), alignment is fine. * We checked the bounds, but it might have been able * to overflow if the packet pointer started in the @@ -467,7 +486,7 @@ static struct bpf_align_test tests[] = { * So we did not get a 'range' on R6, and the access * attempt will fail. */ - {15, "R6_w=pkt(id=1,off=0,r=0,umin_value=2,umax_value=9223372034707292158,var_off=(0x2; 0x7fffffff7ffffffc)"}, + {15, "R6_w=pkt(id=1,off=0,r=0,umin_value=2,umax_value=9223372036854775806,var_off=(0x2; 0x7ffffffffffffffc))"}, } }, { @@ -518,7 +537,7 @@ static struct bpf_align_test tests[] = { * the total offset is 4-byte aligned and meets the * load's requirements. */ - {20, "R5=pkt(id=2,off=0,r=4,umin_value=2,umax_value=1034,var_off=(0x2; 0x7fc)"}, + {20, "R5=pkt(id=1,off=0,r=4,umin_value=2,umax_value=1034,var_off=(0x2; 0x7fc)"}, }, }, @@ -561,18 +580,18 @@ static struct bpf_align_test tests[] = { /* Adding 14 makes R6 be (4n+2) */ {11, "R6_w=inv(id=0,umin_value=14,umax_value=74,var_off=(0x2; 0x7c))"}, /* Subtracting from packet pointer overflows ubounds */ - {13, "R5_w=pkt(id=2,off=0,r=8,umin_value=18446744073709551542,umax_value=18446744073709551602,var_off=(0xffffffffffffff82; 0x7c)"}, + {13, "R5_w=pkt(id=1,off=0,r=8,umin_value=18446744073709551542,umax_value=18446744073709551602,var_off=(0xffffffffffffff82; 0x7c))"}, /* New unknown value in R7 is (4n), >= 76 */ {15, "R7_w=inv(id=0,umin_value=76,umax_value=1096,var_off=(0x0; 0x7fc))"}, /* Adding it to packet pointer gives nice bounds again */ - {16, "R5_w=pkt(id=3,off=0,r=0,umin_value=2,umax_value=1082,var_off=(0x2; 0xfffffffc)"}, + {16, "R5_w=pkt(id=2,off=0,r=0,umin_value=2,umax_value=1082,var_off=(0x2; 0x7fc))"}, /* At the time the word size load is performed from R5, * its total fixed offset is NET_IP_ALIGN + reg->off (0) * which is 2. Then the variable offset is (4n+2), so * the total offset is 4-byte aligned and meets the * load's requirements. */ - {20, "R5=pkt(id=3,off=0,r=4,umin_value=2,umax_value=1082,var_off=(0x2; 0xfffffffc)"}, + {20, "R5=pkt(id=2,off=0,r=4,umin_value=2,umax_value=1082,var_off=(0x2; 0x7fc))"}, }, }, }; @@ -651,16 +670,51 @@ static int do_test_single(struct bpf_align_test *test) return ret; } -void test_align(void) +static int do_test(unsigned int from, unsigned int to) { + int all_pass = 0; + int all_fail = 0; unsigned int i; - for (i = 0; i < ARRAY_SIZE(tests); i++) { + for (i = from; i < to; i++) { struct bpf_align_test *test = &tests[i]; + int fail; - if (!test__start_subtest(test->descr)) - continue; - - CHECK_FAIL(do_test_single(test)); + printf("Test %3d: %s ... ", + i, test->descr); + fail = do_test_single(test); + if (fail) { + all_fail++; + printf("FAIL\n"); + } else { + all_pass++; + printf("PASS\n"); + } } + printf("Results: %d pass %d fail\n", + all_pass, all_fail); + return all_fail ? EXIT_FAILURE : EXIT_SUCCESS; +} + +int main(int argc, char **argv) +{ + unsigned int from = 0, to = ARRAY_SIZE(tests); + + if (argc == 3) { + unsigned int l = atoi(argv[argc - 2]); + unsigned int u = atoi(argv[argc - 1]); + + if (l < to && u < to) { + from = l; + to = u + 1; + } + } else if (argc == 2) { + unsigned int t = atoi(argv[argc - 1]); + + if (t < to) { + from = t; + to = t + 1; + } + } + return do_test(from, to); } diff --git a/tools/testing/selftests/bpf/test_lirc_mode2_user.c b/tools/testing/selftests/bpf/test_lirc_mode2_user.c index d63878bc2d5f..fb5fd6841ef3 100644 --- a/tools/testing/selftests/bpf/test_lirc_mode2_user.c +++ b/tools/testing/selftests/bpf/test_lirc_mode2_user.c @@ -73,7 +73,7 @@ int main(int argc, char **argv) /* Let's try detach it before it was ever attached */ ret = bpf_prog_detach2(progfd, lircfd, BPF_LIRC_MODE2); - if (ret != -ENOENT) { + if (ret != -1 || errno != ENOENT) { printf("bpf_prog_detach2 not attached should fail: %m\n"); return 1; } diff --git a/tools/testing/selftests/bpf/test_maps.c b/tools/testing/selftests/bpf/test_maps.c index ed743dedd730..45c7a55f0b8b 100644 --- a/tools/testing/selftests/bpf/test_maps.c +++ b/tools/testing/selftests/bpf/test_maps.c @@ -756,7 +756,11 @@ static void test_sockmap(unsigned int tasks, void *data) /* Test update without programs */ for (i = 0; i < 6; i++) { err = bpf_map_update_elem(fd, &i, &sfd[i], BPF_ANY); - if (err) { + if (i < 2 && !err) { + printf("Allowed update sockmap '%i:%i' not in ESTABLISHED\n", + i, sfd[i]); + goto out_sockmap; + } else if (i >= 2 && err) { printf("Failed noprog update sockmap '%i:%i'\n", i, sfd[i]); goto out_sockmap; diff --git a/tools/testing/selftests/bpf/test_verifier.c b/tools/testing/selftests/bpf/test_verifier.c index 83f0f2e1a645..1bd285dc55e9 100644 --- a/tools/testing/selftests/bpf/test_verifier.c +++ b/tools/testing/selftests/bpf/test_verifier.c @@ -942,12 +942,7 @@ static void do_test_single(struct bpf_test *test, bool unpriv, attr.insns = prog; attr.insns_cnt = prog_len; attr.license = "GPL"; - if (verbose) - attr.log_level = 1; - else if (expected_ret == VERBOSE_ACCEPT) - attr.log_level = 2; - else - attr.log_level = 4; + attr.log_level = verbose || expected_ret == VERBOSE_ACCEPT ? 1 : 4; attr.prog_flags = pflags; fd_prog = bpf_load_program_xattr(&attr, bpf_vlog, sizeof(bpf_vlog)); diff --git a/tools/testing/selftests/bpf/verifier/and.c b/tools/testing/selftests/bpf/verifier/and.c index d781bc86e100..e0fad1548737 100644 --- a/tools/testing/selftests/bpf/verifier/and.c +++ b/tools/testing/selftests/bpf/verifier/and.c @@ -15,7 +15,7 @@ BPF_EXIT_INSN(), }, .fixup_map_hash_48b = { 3 }, - .errstr = "R0 max value is outside of the allowed memory range", + .errstr = "R0 max value is outside of the array range", .result = REJECT, .flags = F_NEEDS_EFFICIENT_UNALIGNED_ACCESS, }, @@ -44,7 +44,7 @@ BPF_EXIT_INSN(), }, .fixup_map_hash_48b = { 3 }, - .errstr = "R0 max value is outside of the allowed memory range", + .errstr = "R0 max value is outside of the array range", .result = REJECT, .flags = F_NEEDS_EFFICIENT_UNALIGNED_ACCESS, }, diff --git a/tools/testing/selftests/bpf/verifier/array_access.c b/tools/testing/selftests/bpf/verifier/array_access.c index 25ef091b4f60..bcc87906c4c1 100644 --- a/tools/testing/selftests/bpf/verifier/array_access.c +++ b/tools/testing/selftests/bpf/verifier/array_access.c @@ -117,7 +117,7 @@ BPF_EXIT_INSN(), }, .fixup_map_hash_48b = { 3 }, - .errstr = "R0 min value is outside of the allowed memory range", + .errstr = "R0 min value is outside of the array range", .result = REJECT, .flags = F_NEEDS_EFFICIENT_UNALIGNED_ACCESS, }, @@ -137,7 +137,7 @@ BPF_EXIT_INSN(), }, .fixup_map_hash_48b = { 3 }, - .errstr = "R0 unbounded memory access, make sure to bounds check any such access", + .errstr = "R0 unbounded memory access, make sure to bounds check any array access into a map", .result = REJECT, .flags = F_NEEDS_EFFICIENT_UNALIGNED_ACCESS, }, diff --git a/tools/testing/selftests/bpf/verifier/bounds.c b/tools/testing/selftests/bpf/verifier/bounds.c index da856c2dc985..313b345eddcc 100644 --- a/tools/testing/selftests/bpf/verifier/bounds.c +++ b/tools/testing/selftests/bpf/verifier/bounds.c @@ -20,7 +20,7 @@ BPF_EXIT_INSN(), }, .fixup_map_hash_8b = { 3 }, - .errstr = "R0 max value is outside of the allowed memory range", + .errstr = "R0 max value is outside of the array range", .result = REJECT, }, { @@ -146,7 +146,7 @@ BPF_EXIT_INSN(), }, .fixup_map_hash_8b = { 3 }, - .errstr = "R0 min value is outside of the allowed memory range", + .errstr = "R0 min value is outside of the array range", .result = REJECT }, { @@ -362,7 +362,7 @@ BPF_EXIT_INSN(), }, .fixup_map_hash_8b = { 3 }, - .errstr = "R0 max value is outside of the allowed memory range", + .errstr = "R0 max value is outside of the array range", .result = REJECT }, { diff --git a/tools/testing/selftests/bpf/verifier/bounds_mix_sign_unsign.c b/tools/testing/selftests/bpf/verifier/bounds_mix_sign_unsign.c index bf82b923c5fe..c2aa6f26738b 100644 --- a/tools/testing/selftests/bpf/verifier/bounds_mix_sign_unsign.c +++ b/tools/testing/selftests/bpf/verifier/bounds_mix_sign_unsign.c @@ -1,14 +1,13 @@ { "bounds checks mixing signed and unsigned, positive bounds", .insns = { - BPF_EMIT_CALL(BPF_FUNC_ktime_get_ns), - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_0, -16), BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), BPF_LD_MAP_FD(BPF_REG_1, 0), BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0, BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 6), + BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 7), + BPF_ST_MEM(BPF_DW, BPF_REG_10, -16, -8), BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_10, -16), BPF_MOV64_IMM(BPF_REG_2, 2), BPF_JMP_REG(BPF_JGE, BPF_REG_2, BPF_REG_1, 3), @@ -18,21 +17,20 @@ BPF_MOV64_IMM(BPF_REG_0, 0), BPF_EXIT_INSN(), }, - .fixup_map_hash_8b = { 5 }, + .fixup_map_hash_8b = { 3 }, .errstr = "unbounded min value", .result = REJECT, }, { "bounds checks mixing signed and unsigned", .insns = { - BPF_EMIT_CALL(BPF_FUNC_ktime_get_ns), - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_0, -16), BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), BPF_LD_MAP_FD(BPF_REG_1, 0), BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0, BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 6), + BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 7), + BPF_ST_MEM(BPF_DW, BPF_REG_10, -16, -8), BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_10, -16), BPF_MOV64_IMM(BPF_REG_2, -1), BPF_JMP_REG(BPF_JGT, BPF_REG_1, BPF_REG_2, 3), @@ -42,21 +40,20 @@ BPF_MOV64_IMM(BPF_REG_0, 0), BPF_EXIT_INSN(), }, - .fixup_map_hash_8b = { 5 }, + .fixup_map_hash_8b = { 3 }, .errstr = "unbounded min value", .result = REJECT, }, { "bounds checks mixing signed and unsigned, variant 2", .insns = { - BPF_EMIT_CALL(BPF_FUNC_ktime_get_ns), - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_0, -16), BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), BPF_LD_MAP_FD(BPF_REG_1, 0), BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0, BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 8), + BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 9), + BPF_ST_MEM(BPF_DW, BPF_REG_10, -16, -8), BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_10, -16), BPF_MOV64_IMM(BPF_REG_2, -1), BPF_JMP_REG(BPF_JGT, BPF_REG_1, BPF_REG_2, 5), @@ -68,21 +65,20 @@ BPF_MOV64_IMM(BPF_REG_0, 0), BPF_EXIT_INSN(), }, - .fixup_map_hash_8b = { 5 }, + .fixup_map_hash_8b = { 3 }, .errstr = "unbounded min value", .result = REJECT, }, { "bounds checks mixing signed and unsigned, variant 3", .insns = { - BPF_EMIT_CALL(BPF_FUNC_ktime_get_ns), - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_0, -16), BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), BPF_LD_MAP_FD(BPF_REG_1, 0), BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0, BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 7), + BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 8), + BPF_ST_MEM(BPF_DW, BPF_REG_10, -16, -8), BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_10, -16), BPF_MOV64_IMM(BPF_REG_2, -1), BPF_JMP_REG(BPF_JGT, BPF_REG_1, BPF_REG_2, 4), @@ -93,21 +89,20 @@ BPF_MOV64_IMM(BPF_REG_0, 0), BPF_EXIT_INSN(), }, - .fixup_map_hash_8b = { 5 }, + .fixup_map_hash_8b = { 3 }, .errstr = "unbounded min value", .result = REJECT, }, { "bounds checks mixing signed and unsigned, variant 4", .insns = { - BPF_EMIT_CALL(BPF_FUNC_ktime_get_ns), - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_0, -16), BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), BPF_LD_MAP_FD(BPF_REG_1, 0), BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0, BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 6), + BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 7), + BPF_ST_MEM(BPF_DW, BPF_REG_10, -16, -8), BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_10, -16), BPF_MOV64_IMM(BPF_REG_2, 1), BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2), @@ -117,20 +112,19 @@ BPF_MOV64_IMM(BPF_REG_0, 0), BPF_EXIT_INSN(), }, - .fixup_map_hash_8b = { 5 }, + .fixup_map_hash_8b = { 3 }, .result = ACCEPT, }, { "bounds checks mixing signed and unsigned, variant 5", .insns = { - BPF_EMIT_CALL(BPF_FUNC_ktime_get_ns), - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_0, -16), BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), BPF_LD_MAP_FD(BPF_REG_1, 0), BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0, BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 8), + BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 9), + BPF_ST_MEM(BPF_DW, BPF_REG_10, -16, -8), BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_10, -16), BPF_MOV64_IMM(BPF_REG_2, -1), BPF_JMP_REG(BPF_JGT, BPF_REG_1, BPF_REG_2, 5), @@ -141,20 +135,17 @@ BPF_MOV64_IMM(BPF_REG_0, 0), BPF_EXIT_INSN(), }, - .fixup_map_hash_8b = { 5 }, + .fixup_map_hash_8b = { 3 }, .errstr = "unbounded min value", .result = REJECT, }, { "bounds checks mixing signed and unsigned, variant 6", .insns = { - BPF_MOV64_REG(BPF_REG_9, BPF_REG_1), - BPF_EMIT_CALL(BPF_FUNC_ktime_get_ns), - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_0, -16), - BPF_MOV64_REG(BPF_REG_1, BPF_REG_9), BPF_MOV64_IMM(BPF_REG_2, 0), BPF_MOV64_REG(BPF_REG_3, BPF_REG_10), BPF_ALU64_IMM(BPF_ADD, BPF_REG_3, -512), + BPF_ST_MEM(BPF_DW, BPF_REG_10, -16, -8), BPF_LDX_MEM(BPF_DW, BPF_REG_4, BPF_REG_10, -16), BPF_MOV64_IMM(BPF_REG_6, -1), BPF_JMP_REG(BPF_JGT, BPF_REG_4, BPF_REG_6, 5), @@ -172,14 +163,13 @@ { "bounds checks mixing signed and unsigned, variant 7", .insns = { - BPF_EMIT_CALL(BPF_FUNC_ktime_get_ns), - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_0, -16), BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), BPF_LD_MAP_FD(BPF_REG_1, 0), BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0, BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 6), + BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 7), + BPF_ST_MEM(BPF_DW, BPF_REG_10, -16, -8), BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_10, -16), BPF_MOV64_IMM(BPF_REG_2, 1024 * 1024 * 1024), BPF_JMP_REG(BPF_JGT, BPF_REG_1, BPF_REG_2, 3), @@ -189,20 +179,19 @@ BPF_MOV64_IMM(BPF_REG_0, 0), BPF_EXIT_INSN(), }, - .fixup_map_hash_8b = { 5 }, + .fixup_map_hash_8b = { 3 }, .result = ACCEPT, }, { "bounds checks mixing signed and unsigned, variant 8", .insns = { - BPF_EMIT_CALL(BPF_FUNC_ktime_get_ns), - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_0, -16), BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), BPF_LD_MAP_FD(BPF_REG_1, 0), BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0, BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 8), + BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 9), + BPF_ST_MEM(BPF_DW, BPF_REG_10, -16, -8), BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_10, -16), BPF_MOV64_IMM(BPF_REG_2, -1), BPF_JMP_REG(BPF_JGT, BPF_REG_2, BPF_REG_1, 2), @@ -214,21 +203,20 @@ BPF_MOV64_IMM(BPF_REG_0, 0), BPF_EXIT_INSN(), }, - .fixup_map_hash_8b = { 5 }, + .fixup_map_hash_8b = { 3 }, .errstr = "unbounded min value", .result = REJECT, }, { "bounds checks mixing signed and unsigned, variant 9", .insns = { - BPF_EMIT_CALL(BPF_FUNC_ktime_get_ns), - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_0, -16), BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), BPF_LD_MAP_FD(BPF_REG_1, 0), BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0, BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 9), + BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 10), + BPF_ST_MEM(BPF_DW, BPF_REG_10, -16, -8), BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_10, -16), BPF_LD_IMM64(BPF_REG_2, -9223372036854775808ULL), BPF_JMP_REG(BPF_JGT, BPF_REG_2, BPF_REG_1, 2), @@ -240,20 +228,19 @@ BPF_MOV64_IMM(BPF_REG_0, 0), BPF_EXIT_INSN(), }, - .fixup_map_hash_8b = { 5 }, + .fixup_map_hash_8b = { 3 }, .result = ACCEPT, }, { "bounds checks mixing signed and unsigned, variant 10", .insns = { - BPF_EMIT_CALL(BPF_FUNC_ktime_get_ns), - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_0, -16), BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), BPF_LD_MAP_FD(BPF_REG_1, 0), BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0, BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 8), + BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 9), + BPF_ST_MEM(BPF_DW, BPF_REG_10, -16, -8), BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_10, -16), BPF_MOV64_IMM(BPF_REG_2, 0), BPF_JMP_REG(BPF_JGT, BPF_REG_2, BPF_REG_1, 2), @@ -265,21 +252,20 @@ BPF_MOV64_IMM(BPF_REG_0, 0), BPF_EXIT_INSN(), }, - .fixup_map_hash_8b = { 5 }, + .fixup_map_hash_8b = { 3 }, .errstr = "unbounded min value", .result = REJECT, }, { "bounds checks mixing signed and unsigned, variant 11", .insns = { - BPF_EMIT_CALL(BPF_FUNC_ktime_get_ns), - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_0, -16), BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), BPF_LD_MAP_FD(BPF_REG_1, 0), BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0, BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 8), + BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 9), + BPF_ST_MEM(BPF_DW, BPF_REG_10, -16, -8), BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_10, -16), BPF_MOV64_IMM(BPF_REG_2, -1), BPF_JMP_REG(BPF_JGE, BPF_REG_2, BPF_REG_1, 2), @@ -292,21 +278,20 @@ BPF_MOV64_IMM(BPF_REG_0, 0), BPF_EXIT_INSN(), }, - .fixup_map_hash_8b = { 5 }, + .fixup_map_hash_8b = { 3 }, .errstr = "unbounded min value", .result = REJECT, }, { "bounds checks mixing signed and unsigned, variant 12", .insns = { - BPF_EMIT_CALL(BPF_FUNC_ktime_get_ns), - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_0, -16), BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), BPF_LD_MAP_FD(BPF_REG_1, 0), BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0, BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 8), + BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 9), + BPF_ST_MEM(BPF_DW, BPF_REG_10, -16, -8), BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_10, -16), BPF_MOV64_IMM(BPF_REG_2, -6), BPF_JMP_REG(BPF_JGE, BPF_REG_2, BPF_REG_1, 2), @@ -318,21 +303,20 @@ BPF_MOV64_IMM(BPF_REG_0, 0), BPF_EXIT_INSN(), }, - .fixup_map_hash_8b = { 5 }, + .fixup_map_hash_8b = { 3 }, .errstr = "unbounded min value", .result = REJECT, }, { "bounds checks mixing signed and unsigned, variant 13", .insns = { - BPF_EMIT_CALL(BPF_FUNC_ktime_get_ns), - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_0, -16), BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), BPF_LD_MAP_FD(BPF_REG_1, 0), BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0, BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 5), + BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 6), + BPF_ST_MEM(BPF_DW, BPF_REG_10, -16, -8), BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_10, -16), BPF_MOV64_IMM(BPF_REG_2, 2), BPF_JMP_REG(BPF_JGE, BPF_REG_2, BPF_REG_1, 2), @@ -347,7 +331,7 @@ BPF_MOV64_IMM(BPF_REG_0, 0), BPF_EXIT_INSN(), }, - .fixup_map_hash_8b = { 5 }, + .fixup_map_hash_8b = { 3 }, .errstr = "unbounded min value", .result = REJECT, }, @@ -356,14 +340,13 @@ .insns = { BPF_LDX_MEM(BPF_W, BPF_REG_9, BPF_REG_1, offsetof(struct __sk_buff, mark)), - BPF_EMIT_CALL(BPF_FUNC_ktime_get_ns), - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_0, -16), BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), BPF_LD_MAP_FD(BPF_REG_1, 0), BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0, BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 7), + BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 8), + BPF_ST_MEM(BPF_DW, BPF_REG_10, -16, -8), BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_10, -16), BPF_MOV64_IMM(BPF_REG_2, -1), BPF_MOV64_IMM(BPF_REG_8, 2), @@ -377,21 +360,20 @@ BPF_JMP_REG(BPF_JGT, BPF_REG_1, BPF_REG_2, -3), BPF_JMP_IMM(BPF_JA, 0, 0, -7), }, - .fixup_map_hash_8b = { 6 }, + .fixup_map_hash_8b = { 4 }, .errstr = "unbounded min value", .result = REJECT, }, { "bounds checks mixing signed and unsigned, variant 15", .insns = { - BPF_EMIT_CALL(BPF_FUNC_ktime_get_ns), - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_0, -16), BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), BPF_LD_MAP_FD(BPF_REG_1, 0), BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0, BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 3), + BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 4), + BPF_ST_MEM(BPF_DW, BPF_REG_10, -16, -8), BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_10, -16), BPF_MOV64_IMM(BPF_REG_2, -6), BPF_JMP_REG(BPF_JGE, BPF_REG_2, BPF_REG_1, 2), @@ -405,7 +387,7 @@ BPF_MOV64_IMM(BPF_REG_0, 0), BPF_EXIT_INSN(), }, - .fixup_map_hash_8b = { 5 }, + .fixup_map_hash_8b = { 3 }, .errstr = "unbounded min value", .result = REJECT, }, diff --git a/tools/testing/selftests/bpf/verifier/calls.c b/tools/testing/selftests/bpf/verifier/calls.c index 2bb08a5fdce5..2d752c4f8d9d 100644 --- a/tools/testing/selftests/bpf/verifier/calls.c +++ b/tools/testing/selftests/bpf/verifier/calls.c @@ -105,7 +105,7 @@ .prog_type = BPF_PROG_TYPE_SCHED_CLS, .fixup_map_hash_8b = { 16 }, .result = REJECT, - .errstr = "R0 min value is outside of the allowed memory range", + .errstr = "R0 min value is outside of the array range", }, { "calls: overlapping caller/callee", @@ -647,14 +647,13 @@ .result = REJECT, }, { - "calls: subprog call with ld_abs in main prog", + "calls: ld_abs with changing ctx data in callee", .insns = { BPF_MOV64_REG(BPF_REG_6, BPF_REG_1), BPF_LD_ABS(BPF_B, 0), BPF_LD_ABS(BPF_H, 0), BPF_LD_ABS(BPF_W, 0), BPF_MOV64_REG(BPF_REG_7, BPF_REG_6), - BPF_MOV64_REG(BPF_REG_1, BPF_REG_6), BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 1, 0, 5), BPF_MOV64_REG(BPF_REG_6, BPF_REG_7), BPF_LD_ABS(BPF_B, 0), @@ -667,7 +666,8 @@ BPF_EXIT_INSN(), }, .prog_type = BPF_PROG_TYPE_SCHED_CLS, - .result = ACCEPT, + .errstr = "BPF_LD_[ABS|IND] instructions cannot be mixed", + .result = REJECT, }, { "calls: two calls with bad fallthrough", diff --git a/tools/testing/selftests/bpf/verifier/direct_packet_access.c b/tools/testing/selftests/bpf/verifier/direct_packet_access.c index ae72536603fe..2c5fbe7bcd27 100644 --- a/tools/testing/selftests/bpf/verifier/direct_packet_access.c +++ b/tools/testing/selftests/bpf/verifier/direct_packet_access.c @@ -529,7 +529,7 @@ }, .prog_type = BPF_PROG_TYPE_SCHED_CLS, .result = REJECT, - .errstr = "invalid access to packet, off=0 size=8, R5(id=2,off=0,r=0)", + .errstr = "invalid access to packet, off=0 size=8, R5(id=1,off=0,r=0)", .flags = F_NEEDS_EFFICIENT_UNALIGNED_ACCESS, }, { diff --git a/tools/testing/selftests/bpf/verifier/direct_value_access.c b/tools/testing/selftests/bpf/verifier/direct_value_access.c index 988f46a1a4c7..b9fb28e8e224 100644 --- a/tools/testing/selftests/bpf/verifier/direct_value_access.c +++ b/tools/testing/selftests/bpf/verifier/direct_value_access.c @@ -68,7 +68,7 @@ }, .fixup_map_array_48b = { 1 }, .result = REJECT, - .errstr = "R1 min value is outside of the allowed memory range", + .errstr = "R1 min value is outside of the array range", }, { "direct map access, write test 7", @@ -220,7 +220,7 @@ }, .fixup_map_array_small = { 1 }, .result = REJECT, - .errstr = "R1 min value is outside of the allowed memory range", + .errstr = "R1 min value is outside of the array range", }, { "direct map access, write test 19", diff --git a/tools/testing/selftests/bpf/verifier/event_output.c b/tools/testing/selftests/bpf/verifier/event_output.c index 99f8f582c02b..130553e19eca 100644 --- a/tools/testing/selftests/bpf/verifier/event_output.c +++ b/tools/testing/selftests/bpf/verifier/event_output.c @@ -92,27 +92,3 @@ .result = ACCEPT, .retval = 1, }, -{ - "perfevent for cgroup dev", - .insns = { __PERF_EVENT_INSNS__ }, - .prog_type = BPF_PROG_TYPE_CGROUP_DEVICE, - .fixup_map_event_output = { 4 }, - .result = ACCEPT, - .retval = 1, -}, -{ - "perfevent for cgroup sysctl", - .insns = { __PERF_EVENT_INSNS__ }, - .prog_type = BPF_PROG_TYPE_CGROUP_SYSCTL, - .fixup_map_event_output = { 4 }, - .result = ACCEPT, - .retval = 1, -}, -{ - "perfevent for cgroup sockopt", - .insns = { __PERF_EVENT_INSNS__ }, - .prog_type = BPF_PROG_TYPE_CGROUP_SOCKOPT, - .fixup_map_event_output = { 4 }, - .result = ACCEPT, - .retval = 1, -}, diff --git a/tools/testing/selftests/bpf/verifier/helper_access_var_len.c b/tools/testing/selftests/bpf/verifier/helper_access_var_len.c index 5a605ae131a9..67ab12410050 100644 --- a/tools/testing/selftests/bpf/verifier/helper_access_var_len.c +++ b/tools/testing/selftests/bpf/verifier/helper_access_var_len.c @@ -318,7 +318,7 @@ BPF_EXIT_INSN(), }, .fixup_map_hash_48b = { 4 }, - .errstr = "R1 min value is outside of the allowed memory range", + .errstr = "R1 min value is outside of the array range", .result = REJECT, .prog_type = BPF_PROG_TYPE_TRACEPOINT, }, diff --git a/tools/testing/selftests/bpf/verifier/helper_value_access.c b/tools/testing/selftests/bpf/verifier/helper_value_access.c index 961f28139b96..7572e403ddb9 100644 --- a/tools/testing/selftests/bpf/verifier/helper_value_access.c +++ b/tools/testing/selftests/bpf/verifier/helper_value_access.c @@ -280,7 +280,7 @@ BPF_EXIT_INSN(), }, .fixup_map_hash_48b = { 3 }, - .errstr = "R1 min value is outside of the allowed memory range", + .errstr = "R1 min value is outside of the array range", .result = REJECT, .prog_type = BPF_PROG_TYPE_TRACEPOINT, }, @@ -415,7 +415,7 @@ BPF_EXIT_INSN(), }, .fixup_map_hash_48b = { 3 }, - .errstr = "R1 min value is outside of the allowed memory range", + .errstr = "R1 min value is outside of the array range", .result = REJECT, .prog_type = BPF_PROG_TYPE_TRACEPOINT, }, @@ -926,7 +926,7 @@ }, .fixup_map_hash_16b = { 3, 10 }, .result = REJECT, - .errstr = "R2 unbounded memory access, make sure to bounds check any such access", + .errstr = "R2 unbounded memory access, make sure to bounds check any array access into a map", .prog_type = BPF_PROG_TYPE_TRACEPOINT, }, { diff --git a/tools/testing/selftests/bpf/verifier/map_ptr.c b/tools/testing/selftests/bpf/verifier/map_ptr.c deleted file mode 100644 index b52209db8250..000000000000 --- a/tools/testing/selftests/bpf/verifier/map_ptr.c +++ /dev/null @@ -1,62 +0,0 @@ -{ - "bpf_map_ptr: read with negative offset rejected", - .insns = { - BPF_MOV64_REG(BPF_REG_1, BPF_REG_10), - BPF_LD_MAP_FD(BPF_REG_1, 0), - BPF_LDX_MEM(BPF_DW, BPF_REG_6, BPF_REG_1, -8), - BPF_MOV64_IMM(BPF_REG_0, 1), - BPF_EXIT_INSN(), - }, - .fixup_map_array_48b = { 1 }, - .result_unpriv = REJECT, - .errstr_unpriv = "bpf_array access is allowed only to CAP_PERFMON and CAP_SYS_ADMIN", - .result = REJECT, - .errstr = "R1 is bpf_array invalid negative access: off=-8", -}, -{ - "bpf_map_ptr: write rejected", - .insns = { - BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), - BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), - BPF_LD_MAP_FD(BPF_REG_1, 0), - BPF_STX_MEM(BPF_DW, BPF_REG_1, BPF_REG_2, 0), - BPF_MOV64_IMM(BPF_REG_0, 1), - BPF_EXIT_INSN(), - }, - .fixup_map_array_48b = { 3 }, - .result_unpriv = REJECT, - .errstr_unpriv = "bpf_array access is allowed only to CAP_PERFMON and CAP_SYS_ADMIN", - .result = REJECT, - .errstr = "only read from bpf_array is supported", -}, -{ - "bpf_map_ptr: read non-existent field rejected", - .insns = { - BPF_MOV64_IMM(BPF_REG_6, 0), - BPF_LD_MAP_FD(BPF_REG_1, 0), - BPF_LDX_MEM(BPF_W, BPF_REG_6, BPF_REG_1, 1), - BPF_MOV64_IMM(BPF_REG_0, 1), - BPF_EXIT_INSN(), - }, - .fixup_map_array_48b = { 1 }, - .result_unpriv = REJECT, - .errstr_unpriv = "bpf_array access is allowed only to CAP_PERFMON and CAP_SYS_ADMIN", - .result = REJECT, - .errstr = "cannot access ptr member ops with moff 0 in struct bpf_map with off 1 size 4", -}, -{ - "bpf_map_ptr: read ops field accepted", - .insns = { - BPF_MOV64_IMM(BPF_REG_6, 0), - BPF_LD_MAP_FD(BPF_REG_1, 0), - BPF_LDX_MEM(BPF_DW, BPF_REG_6, BPF_REG_1, 0), - BPF_MOV64_IMM(BPF_REG_0, 1), - BPF_EXIT_INSN(), - }, - .fixup_map_array_48b = { 1 }, - .result_unpriv = REJECT, - .errstr_unpriv = "bpf_array access is allowed only to CAP_PERFMON and CAP_SYS_ADMIN", - .result = ACCEPT, - .retval = 1, -}, diff --git a/tools/testing/selftests/bpf/verifier/map_ptr_mixing.c b/tools/testing/selftests/bpf/verifier/map_ptr_mixing.c index 1f2b8c4cb26d..cd26ee6b7b1d 100644 --- a/tools/testing/selftests/bpf/verifier/map_ptr_mixing.c +++ b/tools/testing/selftests/bpf/verifier/map_ptr_mixing.c @@ -56,7 +56,7 @@ .fixup_map_in_map = { 16 }, .fixup_map_array_48b = { 13 }, .result = REJECT, - .errstr = "only read from bpf_array is supported", + .errstr = "R0 invalid mem access 'map_ptr'", }, { "cond: two branches returning different map pointers for lookup (tail, tail)", diff --git a/tools/testing/selftests/bpf/verifier/regalloc.c b/tools/testing/selftests/bpf/verifier/regalloc.c deleted file mode 100644 index 4ad7e05de706..000000000000 --- a/tools/testing/selftests/bpf/verifier/regalloc.c +++ /dev/null @@ -1,269 +0,0 @@ -{ - "regalloc basic", - .insns = { - BPF_MOV64_REG(BPF_REG_6, BPF_REG_1), - BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), - BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), - BPF_LD_MAP_FD(BPF_REG_1, 0), - BPF_EMIT_CALL(BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 8), - BPF_MOV64_REG(BPF_REG_7, BPF_REG_0), - BPF_EMIT_CALL(BPF_FUNC_get_prandom_u32), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_0), - BPF_JMP_IMM(BPF_JSGT, BPF_REG_0, 20, 4), - BPF_JMP_IMM(BPF_JSLT, BPF_REG_2, 0, 3), - BPF_ALU64_REG(BPF_ADD, BPF_REG_7, BPF_REG_0), - BPF_ALU64_REG(BPF_ADD, BPF_REG_7, BPF_REG_2), - BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_7, 0), - BPF_EXIT_INSN(), - }, - .fixup_map_hash_48b = { 4 }, - .result = ACCEPT, - .prog_type = BPF_PROG_TYPE_TRACEPOINT, -}, -{ - "regalloc negative", - .insns = { - BPF_MOV64_REG(BPF_REG_6, BPF_REG_1), - BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), - BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), - BPF_LD_MAP_FD(BPF_REG_1, 0), - BPF_EMIT_CALL(BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 8), - BPF_MOV64_REG(BPF_REG_7, BPF_REG_0), - BPF_EMIT_CALL(BPF_FUNC_get_prandom_u32), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_0), - BPF_JMP_IMM(BPF_JSGT, BPF_REG_0, 24, 4), - BPF_JMP_IMM(BPF_JSLT, BPF_REG_2, 0, 3), - BPF_ALU64_REG(BPF_ADD, BPF_REG_7, BPF_REG_0), - BPF_ALU64_REG(BPF_ADD, BPF_REG_7, BPF_REG_2), - BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_7, 0), - BPF_EXIT_INSN(), - }, - .fixup_map_hash_48b = { 4 }, - .result = REJECT, - .errstr = "invalid access to map value, value_size=48 off=48 size=1", - .prog_type = BPF_PROG_TYPE_TRACEPOINT, -}, -{ - "regalloc src_reg mark", - .insns = { - BPF_MOV64_REG(BPF_REG_6, BPF_REG_1), - BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), - BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), - BPF_LD_MAP_FD(BPF_REG_1, 0), - BPF_EMIT_CALL(BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 9), - BPF_MOV64_REG(BPF_REG_7, BPF_REG_0), - BPF_EMIT_CALL(BPF_FUNC_get_prandom_u32), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_0), - BPF_JMP_IMM(BPF_JSGT, BPF_REG_0, 20, 5), - BPF_MOV64_IMM(BPF_REG_3, 0), - BPF_JMP_REG(BPF_JSGE, BPF_REG_3, BPF_REG_2, 3), - BPF_ALU64_REG(BPF_ADD, BPF_REG_7, BPF_REG_0), - BPF_ALU64_REG(BPF_ADD, BPF_REG_7, BPF_REG_2), - BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_7, 0), - BPF_EXIT_INSN(), - }, - .fixup_map_hash_48b = { 4 }, - .result = ACCEPT, - .prog_type = BPF_PROG_TYPE_TRACEPOINT, -}, -{ - "regalloc src_reg negative", - .insns = { - BPF_MOV64_REG(BPF_REG_6, BPF_REG_1), - BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), - BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), - BPF_LD_MAP_FD(BPF_REG_1, 0), - BPF_EMIT_CALL(BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 9), - BPF_MOV64_REG(BPF_REG_7, BPF_REG_0), - BPF_EMIT_CALL(BPF_FUNC_get_prandom_u32), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_0), - BPF_JMP_IMM(BPF_JSGT, BPF_REG_0, 22, 5), - BPF_MOV64_IMM(BPF_REG_3, 0), - BPF_JMP_REG(BPF_JSGE, BPF_REG_3, BPF_REG_2, 3), - BPF_ALU64_REG(BPF_ADD, BPF_REG_7, BPF_REG_0), - BPF_ALU64_REG(BPF_ADD, BPF_REG_7, BPF_REG_2), - BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_7, 0), - BPF_EXIT_INSN(), - }, - .fixup_map_hash_48b = { 4 }, - .result = REJECT, - .errstr = "invalid access to map value, value_size=48 off=44 size=8", - .prog_type = BPF_PROG_TYPE_TRACEPOINT, -}, -{ - "regalloc and spill", - .insns = { - BPF_MOV64_REG(BPF_REG_6, BPF_REG_1), - BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), - BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), - BPF_LD_MAP_FD(BPF_REG_1, 0), - BPF_EMIT_CALL(BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 11), - BPF_MOV64_REG(BPF_REG_7, BPF_REG_0), - BPF_EMIT_CALL(BPF_FUNC_get_prandom_u32), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_0), - BPF_JMP_IMM(BPF_JSGT, BPF_REG_0, 20, 7), - /* r0 has upper bound that should propagate into r2 */ - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_2, -8), /* spill r2 */ - BPF_MOV64_IMM(BPF_REG_0, 0), - BPF_MOV64_IMM(BPF_REG_2, 0), /* clear r0 and r2 */ - BPF_LDX_MEM(BPF_DW, BPF_REG_3, BPF_REG_10, -8), /* fill r3 */ - BPF_JMP_REG(BPF_JSGE, BPF_REG_0, BPF_REG_3, 2), - /* r3 has lower and upper bounds */ - BPF_ALU64_REG(BPF_ADD, BPF_REG_7, BPF_REG_3), - BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_7, 0), - BPF_EXIT_INSN(), - }, - .fixup_map_hash_48b = { 4 }, - .result = ACCEPT, - .prog_type = BPF_PROG_TYPE_TRACEPOINT, -}, -{ - "regalloc and spill negative", - .insns = { - BPF_MOV64_REG(BPF_REG_6, BPF_REG_1), - BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), - BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), - BPF_LD_MAP_FD(BPF_REG_1, 0), - BPF_EMIT_CALL(BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 11), - BPF_MOV64_REG(BPF_REG_7, BPF_REG_0), - BPF_EMIT_CALL(BPF_FUNC_get_prandom_u32), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_0), - BPF_JMP_IMM(BPF_JSGT, BPF_REG_0, 48, 7), - /* r0 has upper bound that should propagate into r2 */ - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_2, -8), /* spill r2 */ - BPF_MOV64_IMM(BPF_REG_0, 0), - BPF_MOV64_IMM(BPF_REG_2, 0), /* clear r0 and r2 */ - BPF_LDX_MEM(BPF_DW, BPF_REG_3, BPF_REG_10, -8), /* fill r3 */ - BPF_JMP_REG(BPF_JSGE, BPF_REG_0, BPF_REG_3, 2), - /* r3 has lower and upper bounds */ - BPF_ALU64_REG(BPF_ADD, BPF_REG_7, BPF_REG_3), - BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_7, 0), - BPF_EXIT_INSN(), - }, - .fixup_map_hash_48b = { 4 }, - .result = REJECT, - .errstr = "invalid access to map value, value_size=48 off=48 size=8", - .prog_type = BPF_PROG_TYPE_TRACEPOINT, -}, -{ - "regalloc three regs", - .insns = { - BPF_MOV64_REG(BPF_REG_6, BPF_REG_1), - BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), - BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), - BPF_LD_MAP_FD(BPF_REG_1, 0), - BPF_EMIT_CALL(BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 10), - BPF_MOV64_REG(BPF_REG_7, BPF_REG_0), - BPF_EMIT_CALL(BPF_FUNC_get_prandom_u32), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_0), - BPF_MOV64_REG(BPF_REG_4, BPF_REG_2), - BPF_JMP_IMM(BPF_JSGT, BPF_REG_0, 12, 5), - BPF_JMP_IMM(BPF_JSLT, BPF_REG_2, 0, 4), - BPF_ALU64_REG(BPF_ADD, BPF_REG_7, BPF_REG_0), - BPF_ALU64_REG(BPF_ADD, BPF_REG_7, BPF_REG_2), - BPF_ALU64_REG(BPF_ADD, BPF_REG_7, BPF_REG_4), - BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_7, 0), - BPF_EXIT_INSN(), - }, - .fixup_map_hash_48b = { 4 }, - .result = ACCEPT, - .prog_type = BPF_PROG_TYPE_TRACEPOINT, -}, -{ - "regalloc after call", - .insns = { - BPF_MOV64_REG(BPF_REG_6, BPF_REG_1), - BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), - BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), - BPF_LD_MAP_FD(BPF_REG_1, 0), - BPF_EMIT_CALL(BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 10), - BPF_MOV64_REG(BPF_REG_7, BPF_REG_0), - BPF_EMIT_CALL(BPF_FUNC_get_prandom_u32), - BPF_MOV64_REG(BPF_REG_8, BPF_REG_0), - BPF_MOV64_REG(BPF_REG_9, BPF_REG_0), - BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 1, 0, 6), - BPF_JMP_IMM(BPF_JSGT, BPF_REG_8, 20, 4), - BPF_JMP_IMM(BPF_JSLT, BPF_REG_9, 0, 3), - BPF_ALU64_REG(BPF_ADD, BPF_REG_7, BPF_REG_8), - BPF_ALU64_REG(BPF_ADD, BPF_REG_7, BPF_REG_9), - BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_7, 0), - BPF_EXIT_INSN(), - BPF_MOV64_IMM(BPF_REG_0, 0), - BPF_EXIT_INSN(), - }, - .fixup_map_hash_48b = { 4 }, - .result = ACCEPT, - .prog_type = BPF_PROG_TYPE_TRACEPOINT, -}, -{ - "regalloc in callee", - .insns = { - BPF_MOV64_REG(BPF_REG_6, BPF_REG_1), - BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), - BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), - BPF_LD_MAP_FD(BPF_REG_1, 0), - BPF_EMIT_CALL(BPF_FUNC_map_lookup_elem), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 6), - BPF_MOV64_REG(BPF_REG_7, BPF_REG_0), - BPF_EMIT_CALL(BPF_FUNC_get_prandom_u32), - BPF_MOV64_REG(BPF_REG_1, BPF_REG_0), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_0), - BPF_MOV64_REG(BPF_REG_3, BPF_REG_7), - BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 1, 0, 1), - BPF_EXIT_INSN(), - BPF_JMP_IMM(BPF_JSGT, BPF_REG_1, 20, 5), - BPF_JMP_IMM(BPF_JSLT, BPF_REG_2, 0, 4), - BPF_ALU64_REG(BPF_ADD, BPF_REG_3, BPF_REG_1), - BPF_ALU64_REG(BPF_ADD, BPF_REG_3, BPF_REG_2), - BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_3, 0), - BPF_EXIT_INSN(), - BPF_MOV64_IMM(BPF_REG_0, 0), - BPF_EXIT_INSN(), - }, - .fixup_map_hash_48b = { 4 }, - .result = ACCEPT, - .prog_type = BPF_PROG_TYPE_TRACEPOINT, -}, -{ - "regalloc, spill, JEQ", - .insns = { - BPF_MOV64_REG(BPF_REG_6, BPF_REG_1), - BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), - BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -8), - BPF_LD_MAP_FD(BPF_REG_1, 0), - BPF_EMIT_CALL(BPF_FUNC_map_lookup_elem), - BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_0, -8), /* spill r0 */ - BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 0), - /* The verifier will walk the rest twice with r0 == 0 and r0 == map_value */ - BPF_EMIT_CALL(BPF_FUNC_get_prandom_u32), - BPF_MOV64_REG(BPF_REG_2, BPF_REG_0), - BPF_JMP_IMM(BPF_JEQ, BPF_REG_2, 20, 0), - /* The verifier will walk the rest two more times with r0 == 20 and r0 == unknown */ - BPF_LDX_MEM(BPF_DW, BPF_REG_3, BPF_REG_10, -8), /* fill r3 with map_value */ - BPF_JMP_IMM(BPF_JEQ, BPF_REG_3, 0, 1), /* skip ldx if map_value == NULL */ - /* Buggy verifier will think that r3 == 20 here */ - BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_3, 0), /* read from map_value */ - BPF_EXIT_INSN(), - }, - .fixup_map_hash_48b = { 4 }, - .result = ACCEPT, - .prog_type = BPF_PROG_TYPE_TRACEPOINT, -}, diff --git a/tools/testing/selftests/bpf/verifier/search_pruning.c b/tools/testing/selftests/bpf/verifier/search_pruning.c index 949cbe460248..7e36078f8f48 100644 --- a/tools/testing/selftests/bpf/verifier/search_pruning.c +++ b/tools/testing/selftests/bpf/verifier/search_pruning.c @@ -128,10 +128,9 @@ BPF_EXIT_INSN(), }, .fixup_map_hash_8b = { 3 }, - .errstr_unpriv = "invalid read from stack off -16+0 size 8", - .result_unpriv = REJECT, - /* in privileged mode reads from uninitialized stack locations are permitted */ - .result = ACCEPT, + .errstr = "invalid read from stack off -16+0 size 8", + .result = REJECT, + .prog_type = BPF_PROG_TYPE_TRACEPOINT, }, { "allocated_stack", @@ -188,8 +187,6 @@ BPF_EXIT_INSN(), }, .flags = BPF_F_TEST_STATE_FREQ, - .errstr_unpriv = "invalid read from stack off -8+1 size 8", - .result_unpriv = REJECT, - /* in privileged mode reads from uninitialized stack locations are permitted */ - .result = ACCEPT, + .errstr = "invalid read from stack off -8+1 size 8", + .result = REJECT, }, diff --git a/tools/testing/selftests/bpf/verifier/sock.c b/tools/testing/selftests/bpf/verifier/sock.c index 37dbe00bed46..b2ce50bb935b 100644 --- a/tools/testing/selftests/bpf/verifier/sock.c +++ b/tools/testing/selftests/bpf/verifier/sock.c @@ -530,6 +530,33 @@ .prog_type = BPF_PROG_TYPE_SCHED_CLS, .result = ACCEPT, }, +{ + "sk_storage_get(map, skb->sk, &stack_value, 1): partially init stack_value", + .insns = { + BPF_MOV64_IMM(BPF_REG_2, 0), + BPF_STX_MEM(BPF_W, BPF_REG_10, BPF_REG_2, -8), + BPF_LDX_MEM(BPF_DW, BPF_REG_1, BPF_REG_1, offsetof(struct __sk_buff, sk)), + BPF_JMP_IMM(BPF_JNE, BPF_REG_1, 0, 2), + BPF_MOV64_IMM(BPF_REG_0, 0), + BPF_EXIT_INSN(), + BPF_EMIT_CALL(BPF_FUNC_sk_fullsock), + BPF_JMP_IMM(BPF_JNE, BPF_REG_0, 0, 2), + BPF_MOV64_IMM(BPF_REG_0, 0), + BPF_EXIT_INSN(), + BPF_MOV64_IMM(BPF_REG_4, 1), + BPF_MOV64_REG(BPF_REG_3, BPF_REG_10), + BPF_ALU64_IMM(BPF_ADD, BPF_REG_3, -8), + BPF_MOV64_REG(BPF_REG_2, BPF_REG_0), + BPF_LD_MAP_FD(BPF_REG_1, 0), + BPF_EMIT_CALL(BPF_FUNC_sk_storage_get), + BPF_MOV64_IMM(BPF_REG_0, 0), + BPF_EXIT_INSN(), + }, + .fixup_sk_storage_map = { 14 }, + .prog_type = BPF_PROG_TYPE_SCHED_CLS, + .result = REJECT, + .errstr = "invalid indirect read from stack", +}, { "bpf_map_lookup_elem(smap, &key)", .insns = { diff --git a/tools/testing/selftests/bpf/verifier/spill_fill.c b/tools/testing/selftests/bpf/verifier/spill_fill.c index 3799059ee4f6..45d43bf82f26 100644 --- a/tools/testing/selftests/bpf/verifier/spill_fill.c +++ b/tools/testing/selftests/bpf/verifier/spill_fill.c @@ -74,214 +74,3 @@ .result = ACCEPT, .retval = POINTER_VALUE, }, -{ - "Spill and refill a u32 const scalar. Offset to skb->data", - .insns = { - BPF_LDX_MEM(BPF_W, BPF_REG_2, BPF_REG_1, - offsetof(struct __sk_buff, data)), - BPF_LDX_MEM(BPF_W, BPF_REG_3, BPF_REG_1, - offsetof(struct __sk_buff, data_end)), - /* r4 = 20 */ - BPF_MOV32_IMM(BPF_REG_4, 20), - /* *(u32 *)(r10 -8) = r4 */ - BPF_STX_MEM(BPF_W, BPF_REG_10, BPF_REG_4, -8), - /* r4 = *(u32 *)(r10 -8) */ - BPF_LDX_MEM(BPF_W, BPF_REG_4, BPF_REG_10, -8), - /* r0 = r2 */ - BPF_MOV64_REG(BPF_REG_0, BPF_REG_2), - /* r0 += r4 R0=pkt R2=pkt R3=pkt_end R4=20 */ - BPF_ALU64_REG(BPF_ADD, BPF_REG_0, BPF_REG_4), - /* if (r0 > r3) R0=pkt,off=20 R2=pkt R3=pkt_end R4=20 */ - BPF_JMP_REG(BPF_JGT, BPF_REG_0, BPF_REG_3, 1), - /* r0 = *(u32 *)r2 R0=pkt,off=20,r=20 R2=pkt,r=20 R3=pkt_end R4=20 */ - BPF_LDX_MEM(BPF_W, BPF_REG_0, BPF_REG_2, 0), - BPF_MOV64_IMM(BPF_REG_0, 0), - BPF_EXIT_INSN(), - }, - .result = ACCEPT, - .prog_type = BPF_PROG_TYPE_SCHED_CLS, -}, -{ - "Spill a u32 const, refill from another half of the uninit u32 from the stack", - .insns = { - /* r4 = 20 */ - BPF_MOV32_IMM(BPF_REG_4, 20), - /* *(u32 *)(r10 -8) = r4 */ - BPF_STX_MEM(BPF_W, BPF_REG_10, BPF_REG_4, -8), - /* r4 = *(u32 *)(r10 -4) fp-8=????rrrr*/ - BPF_LDX_MEM(BPF_W, BPF_REG_4, BPF_REG_10, -4), - BPF_MOV64_IMM(BPF_REG_0, 0), - BPF_EXIT_INSN(), - }, - .result_unpriv = REJECT, - .errstr_unpriv = "invalid read from stack off -4+0 size 4", - /* in privileged mode reads from uninitialized stack locations are permitted */ - .result = ACCEPT, -}, -{ - "Spill a u32 const scalar. Refill as u16. Offset to skb->data", - .insns = { - BPF_LDX_MEM(BPF_W, BPF_REG_2, BPF_REG_1, - offsetof(struct __sk_buff, data)), - BPF_LDX_MEM(BPF_W, BPF_REG_3, BPF_REG_1, - offsetof(struct __sk_buff, data_end)), - /* r4 = 20 */ - BPF_MOV32_IMM(BPF_REG_4, 20), - /* *(u32 *)(r10 -8) = r4 */ - BPF_STX_MEM(BPF_W, BPF_REG_10, BPF_REG_4, -8), - /* r4 = *(u16 *)(r10 -8) */ - BPF_LDX_MEM(BPF_H, BPF_REG_4, BPF_REG_10, -8), - /* r0 = r2 */ - BPF_MOV64_REG(BPF_REG_0, BPF_REG_2), - /* r0 += r4 R0=pkt R2=pkt R3=pkt_end R4=umax=65535 */ - BPF_ALU64_REG(BPF_ADD, BPF_REG_0, BPF_REG_4), - /* if (r0 > r3) R0=pkt,umax=65535 R2=pkt R3=pkt_end R4=umax=65535 */ - BPF_JMP_REG(BPF_JGT, BPF_REG_0, BPF_REG_3, 1), - /* r0 = *(u32 *)r2 R0=pkt,umax=65535 R2=pkt R3=pkt_end R4=20 */ - BPF_LDX_MEM(BPF_W, BPF_REG_0, BPF_REG_2, 0), - BPF_MOV64_IMM(BPF_REG_0, 0), - BPF_EXIT_INSN(), - }, - .result = REJECT, - .errstr = "invalid access to packet", - .prog_type = BPF_PROG_TYPE_SCHED_CLS, -}, -{ - "Spill u32 const scalars. Refill as u64. Offset to skb->data", - .insns = { - BPF_LDX_MEM(BPF_W, BPF_REG_2, BPF_REG_1, - offsetof(struct __sk_buff, data)), - BPF_LDX_MEM(BPF_W, BPF_REG_3, BPF_REG_1, - offsetof(struct __sk_buff, data_end)), - /* r6 = 0 */ - BPF_MOV32_IMM(BPF_REG_6, 0), - /* r7 = 20 */ - BPF_MOV32_IMM(BPF_REG_7, 20), - /* *(u32 *)(r10 -4) = r6 */ - BPF_STX_MEM(BPF_W, BPF_REG_10, BPF_REG_6, -4), - /* *(u32 *)(r10 -8) = r7 */ - BPF_STX_MEM(BPF_W, BPF_REG_10, BPF_REG_7, -8), - /* r4 = *(u64 *)(r10 -8) */ - BPF_LDX_MEM(BPF_H, BPF_REG_4, BPF_REG_10, -8), - /* r0 = r2 */ - BPF_MOV64_REG(BPF_REG_0, BPF_REG_2), - /* r0 += r4 R0=pkt R2=pkt R3=pkt_end R4=umax=65535 */ - BPF_ALU64_REG(BPF_ADD, BPF_REG_0, BPF_REG_4), - /* if (r0 > r3) R0=pkt,umax=65535 R2=pkt R3=pkt_end R4=umax=65535 */ - BPF_JMP_REG(BPF_JGT, BPF_REG_0, BPF_REG_3, 1), - /* r0 = *(u32 *)r2 R0=pkt,umax=65535 R2=pkt R3=pkt_end R4=20 */ - BPF_LDX_MEM(BPF_W, BPF_REG_0, BPF_REG_2, 0), - BPF_MOV64_IMM(BPF_REG_0, 0), - BPF_EXIT_INSN(), - }, - .result = REJECT, - .errstr = "invalid access to packet", - .prog_type = BPF_PROG_TYPE_SCHED_CLS, -}, -{ - "Spill a u32 const scalar. Refill as u16 from fp-6. Offset to skb->data", - .insns = { - BPF_LDX_MEM(BPF_W, BPF_REG_2, BPF_REG_1, - offsetof(struct __sk_buff, data)), - BPF_LDX_MEM(BPF_W, BPF_REG_3, BPF_REG_1, - offsetof(struct __sk_buff, data_end)), - /* r4 = 20 */ - BPF_MOV32_IMM(BPF_REG_4, 20), - /* *(u32 *)(r10 -8) = r4 */ - BPF_STX_MEM(BPF_W, BPF_REG_10, BPF_REG_4, -8), - /* r4 = *(u16 *)(r10 -6) */ - BPF_LDX_MEM(BPF_H, BPF_REG_4, BPF_REG_10, -6), - /* r0 = r2 */ - BPF_MOV64_REG(BPF_REG_0, BPF_REG_2), - /* r0 += r4 R0=pkt R2=pkt R3=pkt_end R4=umax=65535 */ - BPF_ALU64_REG(BPF_ADD, BPF_REG_0, BPF_REG_4), - /* if (r0 > r3) R0=pkt,umax=65535 R2=pkt R3=pkt_end R4=umax=65535 */ - BPF_JMP_REG(BPF_JGT, BPF_REG_0, BPF_REG_3, 1), - /* r0 = *(u32 *)r2 R0=pkt,umax=65535 R2=pkt R3=pkt_end R4=20 */ - BPF_LDX_MEM(BPF_W, BPF_REG_0, BPF_REG_2, 0), - BPF_MOV64_IMM(BPF_REG_0, 0), - BPF_EXIT_INSN(), - }, - .result = REJECT, - .errstr = "invalid access to packet", - .prog_type = BPF_PROG_TYPE_SCHED_CLS, -}, -{ - "Spill and refill a u32 const scalar at non 8byte aligned stack addr. Offset to skb->data", - .insns = { - BPF_LDX_MEM(BPF_W, BPF_REG_2, BPF_REG_1, - offsetof(struct __sk_buff, data)), - BPF_LDX_MEM(BPF_W, BPF_REG_3, BPF_REG_1, - offsetof(struct __sk_buff, data_end)), - /* r4 = 20 */ - BPF_MOV32_IMM(BPF_REG_4, 20), - /* *(u32 *)(r10 -8) = r4 */ - BPF_STX_MEM(BPF_W, BPF_REG_10, BPF_REG_4, -8), - /* *(u32 *)(r10 -4) = r4 */ - BPF_STX_MEM(BPF_W, BPF_REG_10, BPF_REG_4, -4), - /* r4 = *(u32 *)(r10 -4), */ - BPF_LDX_MEM(BPF_W, BPF_REG_4, BPF_REG_10, -4), - /* r0 = r2 */ - BPF_MOV64_REG(BPF_REG_0, BPF_REG_2), - /* r0 += r4 R0=pkt R2=pkt R3=pkt_end R4=umax=U32_MAX */ - BPF_ALU64_REG(BPF_ADD, BPF_REG_0, BPF_REG_4), - /* if (r0 > r3) R0=pkt,umax=U32_MAX R2=pkt R3=pkt_end R4= */ - BPF_JMP_REG(BPF_JGT, BPF_REG_0, BPF_REG_3, 1), - /* r0 = *(u32 *)r2 R0=pkt,umax=U32_MAX R2=pkt R3=pkt_end R4= */ - BPF_LDX_MEM(BPF_W, BPF_REG_0, BPF_REG_2, 0), - BPF_MOV64_IMM(BPF_REG_0, 0), - BPF_EXIT_INSN(), - }, - .result = REJECT, - .errstr = "invalid access to packet", - .prog_type = BPF_PROG_TYPE_SCHED_CLS, -}, -{ - "Spill and refill a umax=40 bounded scalar. Offset to skb->data", - .insns = { - BPF_LDX_MEM(BPF_W, BPF_REG_2, BPF_REG_1, - offsetof(struct __sk_buff, data)), - BPF_LDX_MEM(BPF_W, BPF_REG_3, BPF_REG_1, - offsetof(struct __sk_buff, data_end)), - BPF_LDX_MEM(BPF_DW, BPF_REG_4, BPF_REG_1, - offsetof(struct __sk_buff, tstamp)), - BPF_JMP_IMM(BPF_JLE, BPF_REG_4, 40, 2), - BPF_MOV64_IMM(BPF_REG_0, 0), - BPF_EXIT_INSN(), - /* *(u32 *)(r10 -8) = r4 R4=umax=40 */ - BPF_STX_MEM(BPF_W, BPF_REG_10, BPF_REG_4, -8), - /* r4 = (*u32 *)(r10 - 8) */ - BPF_LDX_MEM(BPF_W, BPF_REG_4, BPF_REG_10, -8), - /* r2 += r4 R2=pkt R4=umax=40 */ - BPF_ALU64_REG(BPF_ADD, BPF_REG_2, BPF_REG_4), - /* r0 = r2 R2=pkt,umax=40 R4=umax=40 */ - BPF_MOV64_REG(BPF_REG_0, BPF_REG_2), - /* r2 += 20 R0=pkt,umax=40 R2=pkt,umax=40 */ - BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, 20), - /* if (r2 > r3) R0=pkt,umax=40 R2=pkt,off=20,umax=40 */ - BPF_JMP_REG(BPF_JGT, BPF_REG_2, BPF_REG_3, 1), - /* r0 = *(u32 *)r0 R0=pkt,r=20,umax=40 R2=pkt,off=20,r=20,umax=40 */ - BPF_LDX_MEM(BPF_W, BPF_REG_0, BPF_REG_0, 0), - BPF_MOV64_IMM(BPF_REG_0, 0), - BPF_EXIT_INSN(), - }, - .result = ACCEPT, - .prog_type = BPF_PROG_TYPE_SCHED_CLS, -}, -{ - "Spill a u32 scalar at fp-4 and then at fp-8", - .insns = { - /* r4 = 4321 */ - BPF_MOV32_IMM(BPF_REG_4, 4321), - /* *(u32 *)(r10 -4) = r4 */ - BPF_STX_MEM(BPF_W, BPF_REG_10, BPF_REG_4, -4), - /* *(u32 *)(r10 -8) = r4 */ - BPF_STX_MEM(BPF_W, BPF_REG_10, BPF_REG_4, -8), - /* r4 = *(u64 *)(r10 -8) */ - BPF_LDX_MEM(BPF_DW, BPF_REG_4, BPF_REG_10, -8), - BPF_MOV64_IMM(BPF_REG_0, 0), - BPF_EXIT_INSN(), - }, - .result = ACCEPT, - .prog_type = BPF_PROG_TYPE_SCHED_CLS, -}, diff --git a/tools/testing/selftests/bpf/verifier/value_ptr_arith.c b/tools/testing/selftests/bpf/verifier/value_ptr_arith.c index 62e639e45510..188ac92c56d1 100644 --- a/tools/testing/selftests/bpf/verifier/value_ptr_arith.c +++ b/tools/testing/selftests/bpf/verifier/value_ptr_arith.c @@ -48,7 +48,7 @@ .fixup_map_array_48b = { 8 }, .result = ACCEPT, .result_unpriv = REJECT, - .errstr_unpriv = "R0 min value is outside of the allowed memory range", + .errstr_unpriv = "R0 min value is outside of the array range", .retval = 1, }, { @@ -322,7 +322,7 @@ }, .fixup_map_array_48b = { 3 }, .result = REJECT, - .errstr = "R0 min value is outside of the allowed memory range", + .errstr = "R0 min value is outside of the array range", .result_unpriv = REJECT, .errstr_unpriv = "R0 pointer arithmetic of map value goes out of range", }, @@ -615,7 +615,7 @@ }, .fixup_map_array_48b = { 3 }, .result = REJECT, - .errstr = "R1 max value is outside of the allowed memory range", + .errstr = "R1 max value is outside of the array range", .errstr_unpriv = "R1 pointer arithmetic of map value goes out of range", .flags = F_NEEDS_EFFICIENT_UNALIGNED_ACCESS, }, @@ -740,7 +740,7 @@ }, .fixup_map_array_48b = { 3 }, .result = REJECT, - .errstr = "R0 min value is outside of the allowed memory range", + .errstr = "R0 min value is outside of the array range", }, { "map access: value_ptr -= known scalar, 2", diff --git a/tools/testing/selftests/clone3/.gitignore b/tools/testing/selftests/clone3/.gitignore deleted file mode 100644 index fb6d704eb61e..000000000000 --- a/tools/testing/selftests/clone3/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -clone3 -clone3_clear_sighand -clone3_set_tid -clone3_cap_checkpoint_restore diff --git a/tools/testing/selftests/clone3/Makefile b/tools/testing/selftests/clone3/Makefile deleted file mode 100644 index ef7564cb7abe..000000000000 --- a/tools/testing/selftests/clone3/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -CFLAGS += -g -I../../../../usr/include/ -LDLIBS += -lcap - -TEST_GEN_PROGS := clone3 clone3_clear_sighand clone3_set_tid \ - clone3_cap_checkpoint_restore - -include ../lib.mk diff --git a/tools/testing/selftests/clone3/clone3.c b/tools/testing/selftests/clone3/clone3.c deleted file mode 100644 index 4669b3d418e7..000000000000 --- a/tools/testing/selftests/clone3/clone3.c +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* Based on Christian Brauner's clone3() example */ - -#define _GNU_SOURCE -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../kselftest.h" -#include "clone3_selftests.h" - -/* - * Different sizes of struct clone_args - */ -#ifndef CLONE3_ARGS_SIZE_V0 -#define CLONE3_ARGS_SIZE_V0 64 -#endif - -enum test_mode { - CLONE3_ARGS_NO_TEST, - CLONE3_ARGS_ALL_0, - CLONE3_ARGS_INVAL_EXIT_SIGNAL_BIG, - CLONE3_ARGS_INVAL_EXIT_SIGNAL_NEG, - CLONE3_ARGS_INVAL_EXIT_SIGNAL_CSIG, - CLONE3_ARGS_INVAL_EXIT_SIGNAL_NSIG, -}; - -static int call_clone3(uint64_t flags, size_t size, enum test_mode test_mode) -{ - struct clone_args args = { - .flags = flags, - .exit_signal = SIGCHLD, - }; - - struct clone_args_extended { - struct clone_args args; - __aligned_u64 excess_space[2]; - } args_ext; - - pid_t pid = -1; - int status; - - memset(&args_ext, 0, sizeof(args_ext)); - if (size > sizeof(struct clone_args)) - args_ext.excess_space[1] = 1; - - if (size == 0) - size = sizeof(struct clone_args); - - switch (test_mode) { - case CLONE3_ARGS_ALL_0: - args.flags = 0; - args.exit_signal = 0; - break; - case CLONE3_ARGS_INVAL_EXIT_SIGNAL_BIG: - args.exit_signal = 0xbadc0ded00000000ULL; - break; - case CLONE3_ARGS_INVAL_EXIT_SIGNAL_NEG: - args.exit_signal = 0x0000000080000000ULL; - break; - case CLONE3_ARGS_INVAL_EXIT_SIGNAL_CSIG: - args.exit_signal = 0x0000000000000100ULL; - break; - case CLONE3_ARGS_INVAL_EXIT_SIGNAL_NSIG: - args.exit_signal = 0x00000000000000f0ULL; - break; - } - - memcpy(&args_ext.args, &args, sizeof(struct clone_args)); - - pid = sys_clone3((struct clone_args *)&args_ext, size); - if (pid < 0) { - ksft_print_msg("%s - Failed to create new process\n", - strerror(errno)); - return -errno; - } - - if (pid == 0) { - ksft_print_msg("I am the child, my PID is %d\n", getpid()); - _exit(EXIT_SUCCESS); - } - - ksft_print_msg("I am the parent (%d). My child's pid is %d\n", - getpid(), pid); - - if (waitpid(-1, &status, __WALL) < 0) { - ksft_print_msg("Child returned %s\n", strerror(errno)); - return -errno; - } - if (WEXITSTATUS(status)) - return WEXITSTATUS(status); - - return 0; -} - -static void test_clone3(uint64_t flags, size_t size, int expected, - enum test_mode test_mode) -{ - int ret; - - ksft_print_msg( - "[%d] Trying clone3() with flags %#" PRIx64 " (size %zu)\n", - getpid(), flags, size); - ret = call_clone3(flags, size, test_mode); - ksft_print_msg("[%d] clone3() with flags says: %d expected %d\n", - getpid(), ret, expected); - if (ret != expected) - ksft_test_result_fail( - "[%d] Result (%d) is different than expected (%d)\n", - getpid(), ret, expected); - else - ksft_test_result_pass( - "[%d] Result (%d) matches expectation (%d)\n", - getpid(), ret, expected); -} - -int main(int argc, char *argv[]) -{ - pid_t pid; - - uid_t uid = getuid(); - - ksft_print_header(); - ksft_set_plan(17); - - /* Just a simple clone3() should return 0.*/ - test_clone3(0, 0, 0, CLONE3_ARGS_NO_TEST); - - /* Do a clone3() in a new PID NS.*/ - if (uid == 0) - test_clone3(CLONE_NEWPID, 0, 0, CLONE3_ARGS_NO_TEST); - else - ksft_test_result_skip("Skipping clone3() with CLONE_NEWPID\n"); - - /* Do a clone3() with CLONE3_ARGS_SIZE_V0. */ - test_clone3(0, CLONE3_ARGS_SIZE_V0, 0, CLONE3_ARGS_NO_TEST); - - /* Do a clone3() with CLONE3_ARGS_SIZE_V0 - 8 */ - test_clone3(0, CLONE3_ARGS_SIZE_V0 - 8, -EINVAL, CLONE3_ARGS_NO_TEST); - - /* Do a clone3() with sizeof(struct clone_args) + 8 */ - test_clone3(0, sizeof(struct clone_args) + 8, 0, CLONE3_ARGS_NO_TEST); - - /* Do a clone3() with exit_signal having highest 32 bits non-zero */ - test_clone3(0, 0, -EINVAL, CLONE3_ARGS_INVAL_EXIT_SIGNAL_BIG); - - /* Do a clone3() with negative 32-bit exit_signal */ - test_clone3(0, 0, -EINVAL, CLONE3_ARGS_INVAL_EXIT_SIGNAL_NEG); - - /* Do a clone3() with exit_signal not fitting into CSIGNAL mask */ - test_clone3(0, 0, -EINVAL, CLONE3_ARGS_INVAL_EXIT_SIGNAL_CSIG); - - /* Do a clone3() with NSIG < exit_signal < CSIG */ - test_clone3(0, 0, -EINVAL, CLONE3_ARGS_INVAL_EXIT_SIGNAL_NSIG); - - test_clone3(0, sizeof(struct clone_args) + 8, 0, CLONE3_ARGS_ALL_0); - - test_clone3(0, sizeof(struct clone_args) + 16, -E2BIG, - CLONE3_ARGS_ALL_0); - - test_clone3(0, sizeof(struct clone_args) * 2, -E2BIG, - CLONE3_ARGS_ALL_0); - - /* Do a clone3() with > page size */ - test_clone3(0, getpagesize() + 8, -E2BIG, CLONE3_ARGS_NO_TEST); - - /* Do a clone3() with CLONE3_ARGS_SIZE_V0 in a new PID NS. */ - if (uid == 0) - test_clone3(CLONE_NEWPID, CLONE3_ARGS_SIZE_V0, 0, - CLONE3_ARGS_NO_TEST); - else - ksft_test_result_skip("Skipping clone3() with CLONE_NEWPID\n"); - - /* Do a clone3() with CLONE3_ARGS_SIZE_V0 - 8 in a new PID NS */ - test_clone3(CLONE_NEWPID, CLONE3_ARGS_SIZE_V0 - 8, -EINVAL, - CLONE3_ARGS_NO_TEST); - - /* Do a clone3() with sizeof(struct clone_args) + 8 in a new PID NS */ - if (uid == 0) - test_clone3(CLONE_NEWPID, sizeof(struct clone_args) + 8, 0, - CLONE3_ARGS_NO_TEST); - else - ksft_test_result_skip("Skipping clone3() with CLONE_NEWPID\n"); - - /* Do a clone3() with > page size in a new PID NS */ - test_clone3(CLONE_NEWPID, getpagesize() + 8, -E2BIG, - CLONE3_ARGS_NO_TEST); - - return !ksft_get_fail_cnt() ? ksft_exit_pass() : ksft_exit_fail(); -} diff --git a/tools/testing/selftests/clone3/clone3_cap_checkpoint_restore.c b/tools/testing/selftests/clone3/clone3_cap_checkpoint_restore.c deleted file mode 100644 index 9562425aa0a9..000000000000 --- a/tools/testing/selftests/clone3/clone3_cap_checkpoint_restore.c +++ /dev/null @@ -1,182 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* - * Based on Christian Brauner's clone3() example. - * These tests are assuming to be running in the host's - * PID namespace. - */ - -/* capabilities related code based on selftests/bpf/test_verifier.c */ - -#define _GNU_SOURCE -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../kselftest_harness.h" -#include "clone3_selftests.h" - -#ifndef MAX_PID_NS_LEVEL -#define MAX_PID_NS_LEVEL 32 -#endif - -static void child_exit(int ret) -{ - fflush(stdout); - fflush(stderr); - _exit(ret); -} - -static int call_clone3_set_tid(struct __test_metadata *_metadata, - pid_t *set_tid, size_t set_tid_size) -{ - int status; - pid_t pid = -1; - - struct clone_args args = { - .exit_signal = SIGCHLD, - .set_tid = ptr_to_u64(set_tid), - .set_tid_size = set_tid_size, - }; - - pid = sys_clone3(&args, sizeof(struct clone_args)); - if (pid < 0) { - TH_LOG("%s - Failed to create new process", strerror(errno)); - return -errno; - } - - if (pid == 0) { - int ret; - char tmp = 0; - - TH_LOG("I am the child, my PID is %d (expected %d)", getpid(), set_tid[0]); - - if (set_tid[0] != getpid()) - child_exit(EXIT_FAILURE); - child_exit(EXIT_SUCCESS); - } - - TH_LOG("I am the parent (%d). My child's pid is %d", getpid(), pid); - - if (waitpid(pid, &status, 0) < 0) { - TH_LOG("Child returned %s", strerror(errno)); - return -errno; - } - - if (!WIFEXITED(status)) - return -1; - - return WEXITSTATUS(status); -} - -static int test_clone3_set_tid(struct __test_metadata *_metadata, - pid_t *set_tid, size_t set_tid_size) -{ - int ret; - - TH_LOG("[%d] Trying clone3() with CLONE_SET_TID to %d", getpid(), set_tid[0]); - ret = call_clone3_set_tid(_metadata, set_tid, set_tid_size); - TH_LOG("[%d] clone3() with CLONE_SET_TID %d says:%d", getpid(), set_tid[0], ret); - return ret; -} - -struct libcap { - struct __user_cap_header_struct hdr; - struct __user_cap_data_struct data[2]; -}; - -static int set_capability(void) -{ - cap_value_t cap_values[] = { CAP_SETUID, CAP_SETGID }; - struct libcap *cap; - int ret = -1; - cap_t caps; - - caps = cap_get_proc(); - if (!caps) { - perror("cap_get_proc"); - return -1; - } - - /* Drop all capabilities */ - if (cap_clear(caps)) { - perror("cap_clear"); - goto out; - } - - cap_set_flag(caps, CAP_EFFECTIVE, 2, cap_values, CAP_SET); - cap_set_flag(caps, CAP_PERMITTED, 2, cap_values, CAP_SET); - - cap = (struct libcap *) caps; - - /* 40 -> CAP_CHECKPOINT_RESTORE */ - cap->data[1].effective |= 1 << (40 - 32); - cap->data[1].permitted |= 1 << (40 - 32); - - if (cap_set_proc(caps)) { - perror("cap_set_proc"); - goto out; - } - ret = 0; -out: - if (cap_free(caps)) - perror("cap_free"); - return ret; -} - -TEST(clone3_cap_checkpoint_restore) -{ - pid_t pid; - int status; - int ret = 0; - pid_t set_tid[1]; - - test_clone3_supported(); - - EXPECT_EQ(getuid(), 0) - XFAIL(return, "Skipping all tests as non-root\n"); - - memset(&set_tid, 0, sizeof(set_tid)); - - /* Find the current active PID */ - pid = fork(); - if (pid == 0) { - TH_LOG("Child has PID %d", getpid()); - child_exit(EXIT_SUCCESS); - } - ASSERT_GT(waitpid(pid, &status, 0), 0) - TH_LOG("Waiting for child %d failed", pid); - - /* After the child has finished, its PID should be free. */ - set_tid[0] = pid; - - ASSERT_EQ(set_capability(), 0) - TH_LOG("Could not set CAP_CHECKPOINT_RESTORE"); - - ASSERT_EQ(prctl(PR_SET_KEEPCAPS, 1, 0, 0, 0), 0); - - EXPECT_EQ(setgid(65534), 0) - TH_LOG("Failed to setgid(65534)"); - ASSERT_EQ(setuid(65534), 0); - - set_tid[0] = pid; - /* This would fail without CAP_CHECKPOINT_RESTORE */ - ASSERT_EQ(test_clone3_set_tid(_metadata, set_tid, 1), -EPERM); - ASSERT_EQ(set_capability(), 0) - TH_LOG("Could not set CAP_CHECKPOINT_RESTORE"); - /* This should work as we have CAP_CHECKPOINT_RESTORE as non-root */ - ASSERT_EQ(test_clone3_set_tid(_metadata, set_tid, 1), 0); -} - -TEST_HARNESS_MAIN diff --git a/tools/testing/selftests/clone3/clone3_clear_sighand.c b/tools/testing/selftests/clone3/clone3_clear_sighand.c deleted file mode 100644 index 456783ad19d6..000000000000 --- a/tools/testing/selftests/clone3/clone3_clear_sighand.c +++ /dev/null @@ -1,154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#define _GNU_SOURCE -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../kselftest.h" -#include "clone3_selftests.h" - -#ifndef CLONE_CLEAR_SIGHAND -#define CLONE_CLEAR_SIGHAND 0x100000000ULL -#endif - -static void test_clone3_supported(void) -{ - pid_t pid; - struct clone_args args = {}; - - if (__NR_clone3 < 0) - ksft_exit_skip("clone3() syscall is not supported\n"); - - /* Set to something that will always cause EINVAL. */ - args.exit_signal = -1; - pid = sys_clone3(&args, sizeof(args)); - if (!pid) - exit(EXIT_SUCCESS); - - if (pid > 0) { - wait(NULL); - ksft_exit_fail_msg( - "Managed to create child process with invalid exit_signal\n"); - } - - if (errno == ENOSYS) - ksft_exit_skip("clone3() syscall is not supported\n"); - - ksft_print_msg("clone3() syscall supported\n"); -} - -static void nop_handler(int signo) -{ -} - -static int wait_for_pid(pid_t pid) -{ - int status, ret; - -again: - ret = waitpid(pid, &status, 0); - if (ret == -1) { - if (errno == EINTR) - goto again; - - return -1; - } - - if (!WIFEXITED(status)) - return -1; - - return WEXITSTATUS(status); -} - -static void test_clone3_clear_sighand(void) -{ - int ret; - pid_t pid; - struct clone_args args = {}; - struct sigaction act; - - /* - * Check that CLONE_CLEAR_SIGHAND and CLONE_SIGHAND are mutually - * exclusive. - */ - args.flags |= CLONE_CLEAR_SIGHAND | CLONE_SIGHAND; - args.exit_signal = SIGCHLD; - pid = sys_clone3(&args, sizeof(args)); - if (pid > 0) - ksft_exit_fail_msg( - "clone3(CLONE_CLEAR_SIGHAND | CLONE_SIGHAND) succeeded\n"); - - act.sa_handler = nop_handler; - ret = sigemptyset(&act.sa_mask); - if (ret < 0) - ksft_exit_fail_msg("%s - sigemptyset() failed\n", - strerror(errno)); - - act.sa_flags = 0; - - /* Register signal handler for SIGUSR1 */ - ret = sigaction(SIGUSR1, &act, NULL); - if (ret < 0) - ksft_exit_fail_msg( - "%s - sigaction(SIGUSR1, &act, NULL) failed\n", - strerror(errno)); - - /* Register signal handler for SIGUSR2 */ - ret = sigaction(SIGUSR2, &act, NULL); - if (ret < 0) - ksft_exit_fail_msg( - "%s - sigaction(SIGUSR2, &act, NULL) failed\n", - strerror(errno)); - - /* Check that CLONE_CLEAR_SIGHAND works. */ - args.flags = CLONE_CLEAR_SIGHAND; - pid = sys_clone3(&args, sizeof(args)); - if (pid < 0) - ksft_exit_fail_msg("%s - clone3(CLONE_CLEAR_SIGHAND) failed\n", - strerror(errno)); - - if (pid == 0) { - ret = sigaction(SIGUSR1, NULL, &act); - if (ret < 0) - exit(EXIT_FAILURE); - - if (act.sa_handler != SIG_DFL) - exit(EXIT_FAILURE); - - ret = sigaction(SIGUSR2, NULL, &act); - if (ret < 0) - exit(EXIT_FAILURE); - - if (act.sa_handler != SIG_DFL) - exit(EXIT_FAILURE); - - exit(EXIT_SUCCESS); - } - - ret = wait_for_pid(pid); - if (ret) - ksft_exit_fail_msg( - "Failed to clear signal handler for child process\n"); - - ksft_test_result_pass("Cleared signal handlers for child process\n"); -} - -int main(int argc, char **argv) -{ - ksft_print_header(); - ksft_set_plan(1); - - test_clone3_supported(); - test_clone3_clear_sighand(); - - return ksft_exit_pass(); -} diff --git a/tools/testing/selftests/clone3/clone3_selftests.h b/tools/testing/selftests/clone3/clone3_selftests.h deleted file mode 100644 index 1a270390766a..000000000000 --- a/tools/testing/selftests/clone3/clone3_selftests.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef _CLONE3_SELFTESTS_H -#define _CLONE3_SELFTESTS_H - -#define _GNU_SOURCE -#include -#include -#include -#include - -#define ptr_to_u64(ptr) ((__u64)((uintptr_t)(ptr))) - -#ifndef __NR_clone3 -#define __NR_clone3 -1 -struct clone_args { - __aligned_u64 flags; - __aligned_u64 pidfd; - __aligned_u64 child_tid; - __aligned_u64 parent_tid; - __aligned_u64 exit_signal; - __aligned_u64 stack; - __aligned_u64 stack_size; - __aligned_u64 tls; - __aligned_u64 set_tid; - __aligned_u64 set_tid_size; -}; -#endif - -static pid_t sys_clone3(struct clone_args *args, size_t size) -{ - return syscall(__NR_clone3, args, size); -} - -#endif /* _CLONE3_SELFTESTS_H */ diff --git a/tools/testing/selftests/clone3/clone3_set_tid.c b/tools/testing/selftests/clone3/clone3_set_tid.c deleted file mode 100644 index 3480e1c46983..000000000000 --- a/tools/testing/selftests/clone3/clone3_set_tid.c +++ /dev/null @@ -1,381 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* - * Based on Christian Brauner's clone3() example. - * These tests are assuming to be running in the host's - * PID namespace. - */ - -#define _GNU_SOURCE -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../kselftest.h" -#include "clone3_selftests.h" - -#ifndef MAX_PID_NS_LEVEL -#define MAX_PID_NS_LEVEL 32 -#endif - -static int pipe_1[2]; -static int pipe_2[2]; - -static int call_clone3_set_tid(pid_t *set_tid, - size_t set_tid_size, - int flags, - int expected_pid, - bool wait_for_it) -{ - int status; - pid_t pid = -1; - - struct clone_args args = { - .flags = flags, - .exit_signal = SIGCHLD, - .set_tid = ptr_to_u64(set_tid), - .set_tid_size = set_tid_size, - }; - - pid = sys_clone3(&args, sizeof(struct clone_args)); - if (pid < 0) { - ksft_print_msg("%s - Failed to create new process\n", - strerror(errno)); - return -errno; - } - - if (pid == 0) { - int ret; - char tmp = 0; - int exit_code = EXIT_SUCCESS; - - ksft_print_msg("I am the child, my PID is %d (expected %d)\n", - getpid(), set_tid[0]); - if (wait_for_it) { - ksft_print_msg("[%d] Child is ready and waiting\n", - getpid()); - - /* Signal the parent that the child is ready */ - close(pipe_1[0]); - ret = write(pipe_1[1], &tmp, 1); - if (ret != 1) { - ksft_print_msg( - "Writing to pipe returned %d", ret); - exit_code = EXIT_FAILURE; - } - close(pipe_1[1]); - close(pipe_2[1]); - ret = read(pipe_2[0], &tmp, 1); - if (ret != 1) { - ksft_print_msg( - "Reading from pipe returned %d", ret); - exit_code = EXIT_FAILURE; - } - close(pipe_2[0]); - } - - if (set_tid[0] != getpid()) - _exit(EXIT_FAILURE); - _exit(exit_code); - } - - if (expected_pid == 0 || expected_pid == pid) { - ksft_print_msg("I am the parent (%d). My child's pid is %d\n", - getpid(), pid); - } else { - ksft_print_msg( - "Expected child pid %d does not match actual pid %d\n", - expected_pid, pid); - return -1; - } - - if (waitpid(pid, &status, 0) < 0) { - ksft_print_msg("Child returned %s\n", strerror(errno)); - return -errno; - } - - if (!WIFEXITED(status)) - return -1; - - return WEXITSTATUS(status); -} - -static void test_clone3_set_tid(pid_t *set_tid, - size_t set_tid_size, - int flags, - int expected, - int expected_pid, - bool wait_for_it) -{ - int ret; - - ksft_print_msg( - "[%d] Trying clone3() with CLONE_SET_TID to %d and 0x%x\n", - getpid(), set_tid[0], flags); - ret = call_clone3_set_tid(set_tid, set_tid_size, flags, expected_pid, - wait_for_it); - ksft_print_msg( - "[%d] clone3() with CLONE_SET_TID %d says :%d - expected %d\n", - getpid(), set_tid[0], ret, expected); - if (ret != expected) - ksft_test_result_fail( - "[%d] Result (%d) is different than expected (%d)\n", - getpid(), ret, expected); - else - ksft_test_result_pass( - "[%d] Result (%d) matches expectation (%d)\n", - getpid(), ret, expected); -} -int main(int argc, char *argv[]) -{ - FILE *f; - char buf; - char *line; - int status; - int ret = -1; - size_t len = 0; - int pid_max = 0; - uid_t uid = getuid(); - char proc_path[100] = {0}; - pid_t pid, ns1, ns2, ns3, ns_pid; - pid_t set_tid[MAX_PID_NS_LEVEL * 2]; - - if (pipe(pipe_1) < 0 || pipe(pipe_2) < 0) - ksft_exit_fail_msg("pipe() failed\n"); - - ksft_print_header(); - ksft_set_plan(27); - - f = fopen("/proc/sys/kernel/pid_max", "r"); - if (f == NULL) - ksft_exit_fail_msg( - "%s - Could not open /proc/sys/kernel/pid_max\n", - strerror(errno)); - fscanf(f, "%d", &pid_max); - fclose(f); - ksft_print_msg("/proc/sys/kernel/pid_max %d\n", pid_max); - - /* Try invalid settings */ - memset(&set_tid, 0, sizeof(set_tid)); - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL + 1, 0, -EINVAL, 0, 0); - - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL * 2, 0, -EINVAL, 0, 0); - - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL * 2 + 1, 0, - -EINVAL, 0, 0); - - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL * 42, 0, -EINVAL, 0, 0); - - /* - * This can actually work if this test running in a MAX_PID_NS_LEVEL - 1 - * nested PID namespace. - */ - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL - 1, 0, -EINVAL, 0, 0); - - memset(&set_tid, 0xff, sizeof(set_tid)); - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL + 1, 0, -EINVAL, 0, 0); - - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL * 2, 0, -EINVAL, 0, 0); - - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL * 2 + 1, 0, - -EINVAL, 0, 0); - - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL * 42, 0, -EINVAL, 0, 0); - - /* - * This can actually work if this test running in a MAX_PID_NS_LEVEL - 1 - * nested PID namespace. - */ - test_clone3_set_tid(set_tid, MAX_PID_NS_LEVEL - 1, 0, -EINVAL, 0, 0); - - memset(&set_tid, 0, sizeof(set_tid)); - /* Try with an invalid PID */ - set_tid[0] = 0; - test_clone3_set_tid(set_tid, 1, 0, -EINVAL, 0, 0); - - set_tid[0] = -1; - test_clone3_set_tid(set_tid, 1, 0, -EINVAL, 0, 0); - - /* Claim that the set_tid array actually contains 2 elements. */ - test_clone3_set_tid(set_tid, 2, 0, -EINVAL, 0, 0); - - /* Try it in a new PID namespace */ - if (uid == 0) - test_clone3_set_tid(set_tid, 1, CLONE_NEWPID, -EINVAL, 0, 0); - else - ksft_test_result_skip("Clone3() with set_tid requires root\n"); - - /* Try with a valid PID (1) this should return -EEXIST. */ - set_tid[0] = 1; - if (uid == 0) - test_clone3_set_tid(set_tid, 1, 0, -EEXIST, 0, 0); - else - ksft_test_result_skip("Clone3() with set_tid requires root\n"); - - /* Try it in a new PID namespace */ - if (uid == 0) - test_clone3_set_tid(set_tid, 1, CLONE_NEWPID, 0, 0, 0); - else - ksft_test_result_skip("Clone3() with set_tid requires root\n"); - - /* pid_max should fail everywhere */ - set_tid[0] = pid_max; - test_clone3_set_tid(set_tid, 1, 0, -EINVAL, 0, 0); - - if (uid == 0) - test_clone3_set_tid(set_tid, 1, CLONE_NEWPID, -EINVAL, 0, 0); - else - ksft_test_result_skip("Clone3() with set_tid requires root\n"); - - if (uid != 0) { - /* - * All remaining tests require root. Tell the framework - * that all those tests are skipped as non-root. - */ - ksft_cnt.ksft_xskip += ksft_plan - ksft_test_num(); - goto out; - } - - /* Find the current active PID */ - pid = fork(); - if (pid == 0) { - ksft_print_msg("Child has PID %d\n", getpid()); - _exit(EXIT_SUCCESS); - } - if (waitpid(pid, &status, 0) < 0) - ksft_exit_fail_msg("Waiting for child %d failed", pid); - - /* After the child has finished, its PID should be free. */ - set_tid[0] = pid; - test_clone3_set_tid(set_tid, 1, 0, 0, 0, 0); - - /* This should fail as there is no PID 1 in that namespace */ - test_clone3_set_tid(set_tid, 1, CLONE_NEWPID, -EINVAL, 0, 0); - - /* - * Creating a process with PID 1 in the newly created most nested - * PID namespace and PID 'pid' in the parent PID namespace. This - * needs to work. - */ - set_tid[0] = 1; - set_tid[1] = pid; - test_clone3_set_tid(set_tid, 2, CLONE_NEWPID, 0, pid, 0); - - ksft_print_msg("unshare PID namespace\n"); - if (unshare(CLONE_NEWPID) == -1) - ksft_exit_fail_msg("unshare(CLONE_NEWPID) failed: %s\n", - strerror(errno)); - - set_tid[0] = pid; - - /* This should fail as there is no PID 1 in that namespace */ - test_clone3_set_tid(set_tid, 1, 0, -EINVAL, 0, 0); - - /* Let's create a PID 1 */ - ns_pid = fork(); - if (ns_pid == 0) { - ksft_print_msg("Child in PID namespace has PID %d\n", getpid()); - set_tid[0] = 2; - test_clone3_set_tid(set_tid, 1, 0, 0, 2, 0); - - set_tid[0] = 1; - set_tid[1] = -1; - set_tid[2] = pid; - /* This should fail as there is invalid PID at level '1'. */ - test_clone3_set_tid(set_tid, 3, CLONE_NEWPID, -EINVAL, 0, 0); - - set_tid[0] = 1; - set_tid[1] = 42; - set_tid[2] = pid; - /* - * This should fail as there are not enough active PID - * namespaces. Again assuming this is running in the host's - * PID namespace. Not yet nested. - */ - test_clone3_set_tid(set_tid, 4, CLONE_NEWPID, -EINVAL, 0, 0); - - /* - * This should work and from the parent we should see - * something like 'NSpid: pid 42 1'. - */ - test_clone3_set_tid(set_tid, 3, CLONE_NEWPID, 0, 42, true); - - _exit(ksft_cnt.ksft_pass); - } - - close(pipe_1[1]); - close(pipe_2[0]); - while (read(pipe_1[0], &buf, 1) > 0) { - ksft_print_msg("[%d] Child is ready and waiting\n", getpid()); - break; - } - - snprintf(proc_path, sizeof(proc_path), "/proc/%d/status", pid); - f = fopen(proc_path, "r"); - if (f == NULL) - ksft_exit_fail_msg( - "%s - Could not open %s\n", - strerror(errno), proc_path); - - while (getline(&line, &len, f) != -1) { - if (strstr(line, "NSpid")) { - int i; - - /* Verify that all generated PIDs are as expected. */ - i = sscanf(line, "NSpid:\t%d\t%d\t%d", - &ns3, &ns2, &ns1); - if (i != 3) { - ksft_print_msg( - "Unexpected 'NSPid:' entry: %s", - line); - ns1 = ns2 = ns3 = 0; - } - break; - } - } - fclose(f); - free(line); - close(pipe_2[0]); - - /* Tell the clone3()'d child to finish. */ - write(pipe_2[1], &buf, 1); - close(pipe_2[1]); - - if (waitpid(ns_pid, &status, 0) < 0) { - ksft_print_msg("Child returned %s\n", strerror(errno)); - ret = -errno; - goto out; - } - - if (!WIFEXITED(status)) - ksft_test_result_fail("Child error\n"); - - if (WEXITSTATUS(status)) - /* - * Update the number of total tests with the tests from the - * child processes. - */ - ksft_cnt.ksft_pass = WEXITSTATUS(status); - - if (ns3 == pid && ns2 == 42 && ns1 == 1) - ksft_test_result_pass( - "PIDs in all namespaces as expected (%d,%d,%d)\n", - ns3, ns2, ns1); - else - ksft_test_result_fail( - "PIDs in all namespaces not as expected (%d,%d,%d)\n", - ns3, ns2, ns1); -out: - ret = 0; - - return !ret ? ksft_exit_pass() : ksft_exit_fail(); -} diff --git a/tools/testing/selftests/kselftest_module.h b/tools/testing/selftests/kselftest_module.h index e2ea41de3f35..e8eafaf0941a 100644 --- a/tools/testing/selftests/kselftest_module.h +++ b/tools/testing/selftests/kselftest_module.h @@ -11,8 +11,7 @@ #define KSTM_MODULE_GLOBALS() \ static unsigned int total_tests __initdata; \ -static unsigned int failed_tests __initdata; \ -static unsigned int skipped_tests __initdata +static unsigned int failed_tests __initdata #define KSTM_CHECK_ZERO(x) do { \ total_tests++; \ @@ -22,16 +21,11 @@ static unsigned int skipped_tests __initdata } \ } while (0) -static inline int kstm_report(unsigned int total_tests, unsigned int failed_tests, - unsigned int skipped_tests) +static inline int kstm_report(unsigned int total_tests, unsigned int failed_tests) { - if (failed_tests == 0) { - if (skipped_tests) { - pr_info("skipped %u tests\n", skipped_tests); - pr_info("remaining %u tests passed\n", total_tests); - } else - pr_info("all %u tests passed\n", total_tests); - } else + if (failed_tests == 0) + pr_info("all %u tests passed\n", total_tests); + else pr_warn("failed %u out of %u tests\n", failed_tests, total_tests); return failed_tests ? -EINVAL : 0; @@ -42,7 +36,7 @@ static int __init __module##_init(void) \ { \ pr_info("loaded.\n"); \ selftest(); \ - return kstm_report(total_tests, failed_tests, skipped_tests); \ + return kstm_report(total_tests, failed_tests); \ } \ static void __exit __module##_exit(void) \ { \ diff --git a/tools/testing/selftests/net/fcnal-test.sh b/tools/testing/selftests/net/fcnal-test.sh index 354c766e7c24..d2ac09b35dcf 100755 --- a/tools/testing/selftests/net/fcnal-test.sh +++ b/tools/testing/selftests/net/fcnal-test.sh @@ -164,7 +164,7 @@ show_hint() kill_procs() { killall nettest ping ping6 >/dev/null 2>&1 - slowwait 2 sh -c 'test -z "$(pgrep '"'^(nettest|ping|ping6)$'"')"' + sleep 1 } do_run_cmd() @@ -376,8 +376,6 @@ create_ns() ip netns exec ${ns} sysctl -qw net.ipv6.conf.all.keep_addr_on_down=1 ip netns exec ${ns} sysctl -qw net.ipv6.conf.all.forwarding=1 ip netns exec ${ns} sysctl -qw net.ipv6.conf.default.forwarding=1 - ip netns exec ${ns} sysctl -qw net.ipv6.conf.default.accept_dad=0 - ip netns exec ${ns} sysctl -qw net.ipv6.conf.all.accept_dad=0 } # create veth pair to connect namespaces and apply addresses. diff --git a/tools/testing/selftests/net/psock_tpacket.c b/tools/testing/selftests/net/psock_tpacket.c index ca0d9a5a9e08..404a2ce759ab 100644 --- a/tools/testing/selftests/net/psock_tpacket.c +++ b/tools/testing/selftests/net/psock_tpacket.c @@ -22,7 +22,6 @@ * - TPACKET_V3: RX_RING */ -#undef NDEBUG #include #include #include @@ -34,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -785,7 +785,7 @@ static int test_kernel_bit_width(void) static int test_user_bit_width(void) { - return sizeof(long) * 8; + return __WORDSIZE; } static const char *tpacket_str[] = { diff --git a/tools/testing/selftests/rseq/rseq.c b/tools/testing/selftests/rseq/rseq.c index 036b03aaedc3..e20191fb40d4 100644 --- a/tools/testing/selftests/rseq/rseq.c +++ b/tools/testing/selftests/rseq/rseq.c @@ -38,9 +38,9 @@ * Define weak versions to play nice with binaries that are statically linked * against a libc that doesn't support registering its own rseq. */ -extern __weak ptrdiff_t __rseq_offset; -extern __weak unsigned int __rseq_size; -extern __weak unsigned int __rseq_flags; +__weak ptrdiff_t __rseq_offset; +__weak unsigned int __rseq_size; +__weak unsigned int __rseq_flags; static const ptrdiff_t *libc_rseq_offset_p = &__rseq_offset; static const unsigned int *libc_rseq_size_p = &__rseq_size; @@ -124,7 +124,7 @@ void rseq_init(void) * libc not having registered a restartable sequence. Try to find the * symbols if that's the case. */ - if (!libc_rseq_size_p || !*libc_rseq_size_p) { + if (!*libc_rseq_size_p) { libc_rseq_offset_p = dlsym(RTLD_NEXT, "__rseq_offset"); libc_rseq_size_p = dlsym(RTLD_NEXT, "__rseq_size"); libc_rseq_flags_p = dlsym(RTLD_NEXT, "__rseq_flags"); diff --git a/tools/testing/selftests/seccomp/seccomp_benchmark.c b/tools/testing/selftests/seccomp/seccomp_benchmark.c index fcc806585266..5838c8697ec3 100644 --- a/tools/testing/selftests/seccomp/seccomp_benchmark.c +++ b/tools/testing/selftests/seccomp/seccomp_benchmark.c @@ -4,16 +4,12 @@ */ #define _GNU_SOURCE #include -#include -#include -#include #include #include #include #include #include #include -#include #include #include #include @@ -22,9 +18,9 @@ unsigned long long timing(clockid_t clk_id, unsigned long long samples) { - struct timespec start, finish; - unsigned long long i; pid_t pid, ret; + unsigned long long i; + struct timespec start, finish; pid = getpid(); assert(clock_gettime(clk_id, &start) == 0); @@ -35,208 +31,69 @@ unsigned long long timing(clockid_t clk_id, unsigned long long samples) assert(clock_gettime(clk_id, &finish) == 0); i = finish.tv_sec - start.tv_sec; - i *= 1000000000ULL; + i *= 1000000000; i += finish.tv_nsec - start.tv_nsec; - printf("%lu.%09lu - %lu.%09lu = %llu (%.1fs)\n", + printf("%lu.%09lu - %lu.%09lu = %llu\n", finish.tv_sec, finish.tv_nsec, start.tv_sec, start.tv_nsec, - i, (double)i / 1000000000.0); + i); return i; } unsigned long long calibrate(void) { - struct timespec start, finish; - unsigned long long i, samples, step = 9973; - pid_t pid, ret; - int seconds = 15; + unsigned long long i; - printf("Calibrating sample size for %d seconds worth of syscalls ...\n", seconds); + printf("Calibrating reasonable sample size...\n"); - samples = 0; - pid = getpid(); - assert(clock_gettime(CLOCK_MONOTONIC, &start) == 0); - do { - for (i = 0; i < step; i++) { - ret = syscall(__NR_getpid); - assert(pid == ret); - } - assert(clock_gettime(CLOCK_MONOTONIC, &finish) == 0); + for (i = 5; ; i++) { + unsigned long long samples = 1 << i; - samples += step; - i = finish.tv_sec - start.tv_sec; - i *= 1000000000ULL; - i += finish.tv_nsec - start.tv_nsec; - } while (i < 1000000000ULL); - - return samples * seconds; -} - -bool approx(int i_one, int i_two) -{ - double one = i_one, one_bump = one * 0.01; - double two = i_two, two_bump = two * 0.01; - - one_bump = one + MAX(one_bump, 2.0); - two_bump = two + MAX(two_bump, 2.0); - - /* Equal to, or within 1% or 2 digits */ - if (one == two || - (one > two && one <= two_bump) || - (two > one && two <= one_bump)) - return true; - return false; -} - -bool le(int i_one, int i_two) -{ - if (i_one <= i_two) - return true; - return false; -} - -long compare(const char *name_one, const char *name_eval, const char *name_two, - unsigned long long one, bool (*eval)(int, int), unsigned long long two) -{ - bool good; - - printf("\t%s %s %s (%lld %s %lld): ", name_one, name_eval, name_two, - (long long)one, name_eval, (long long)two); - if (one > INT_MAX) { - printf("Miscalculation! Measurement went negative: %lld\n", (long long)one); - return 1; + /* Find something that takes more than 5 seconds to run. */ + if (timing(CLOCK_REALTIME, samples) / 1000000000ULL > 5) + return samples; } - if (two > INT_MAX) { - printf("Miscalculation! Measurement went negative: %lld\n", (long long)two); - return 1; - } - - good = eval(one, two); - printf("%s\n", good ? "✔️" : "❌"); - - return good ? 0 : 1; } int main(int argc, char *argv[]) { - struct sock_filter bitmap_filter[] = { - BPF_STMT(BPF_LD|BPF_W|BPF_ABS, offsetof(struct seccomp_data, nr)), - BPF_STMT(BPF_RET|BPF_K, SECCOMP_RET_ALLOW), - }; - struct sock_fprog bitmap_prog = { - .len = (unsigned short)ARRAY_SIZE(bitmap_filter), - .filter = bitmap_filter, - }; struct sock_filter filter[] = { - BPF_STMT(BPF_LD|BPF_W|BPF_ABS, offsetof(struct seccomp_data, args[0])), BPF_STMT(BPF_RET|BPF_K, SECCOMP_RET_ALLOW), }; struct sock_fprog prog = { .len = (unsigned short)ARRAY_SIZE(filter), .filter = filter, }; - - long ret, bits; - unsigned long long samples, calc; - unsigned long long native, filter1, filter2, bitmap1, bitmap2; - unsigned long long entry, per_filter1, per_filter2; - - printf("Current BPF sysctl settings:\n"); - system("sysctl net.core.bpf_jit_enable"); - system("sysctl net.core.bpf_jit_harden"); + long ret; + unsigned long long samples; + unsigned long long native, filtered; if (argc > 1) samples = strtoull(argv[1], NULL, 0); else samples = calibrate(); - printf("Benchmarking %llu syscalls...\n", samples); + printf("Benchmarking %llu samples...\n", samples); - /* Native call */ native = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; printf("getpid native: %llu ns\n", native); ret = prctl(PR_SET_NO_NEW_PRIVS, 1, 0, 0, 0); assert(ret == 0); - /* One filter resulting in a bitmap */ - ret = prctl(PR_SET_SECCOMP, SECCOMP_MODE_FILTER, &bitmap_prog); - assert(ret == 0); - - bitmap1 = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; - printf("getpid RET_ALLOW 1 filter (bitmap): %llu ns\n", bitmap1); - - /* Second filter resulting in a bitmap */ - ret = prctl(PR_SET_SECCOMP, SECCOMP_MODE_FILTER, &bitmap_prog); - assert(ret == 0); - - bitmap2 = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; - printf("getpid RET_ALLOW 2 filters (bitmap): %llu ns\n", bitmap2); - - /* Third filter, can no longer be converted to bitmap */ ret = prctl(PR_SET_SECCOMP, SECCOMP_MODE_FILTER, &prog); assert(ret == 0); - filter1 = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; - printf("getpid RET_ALLOW 3 filters (full): %llu ns\n", filter1); + filtered = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; + printf("getpid RET_ALLOW: %llu ns\n", filtered); - /* Fourth filter, can not be converted to bitmap because of filter 3 */ - ret = prctl(PR_SET_SECCOMP, SECCOMP_MODE_FILTER, &bitmap_prog); - assert(ret == 0); + printf("Estimated seccomp overhead per syscall: %llu ns\n", + filtered - native); - filter2 = timing(CLOCK_PROCESS_CPUTIME_ID, samples) / samples; - printf("getpid RET_ALLOW 4 filters (full): %llu ns\n", filter2); + if (filtered == native) + printf("Trying running again with more samples.\n"); - /* Estimations */ -#define ESTIMATE(fmt, var, what) do { \ - var = (what); \ - printf("Estimated " fmt ": %llu ns\n", var); \ - if (var > INT_MAX) \ - goto more_samples; \ - } while (0) - - ESTIMATE("total seccomp overhead for 1 bitmapped filter", calc, - bitmap1 - native); - ESTIMATE("total seccomp overhead for 2 bitmapped filters", calc, - bitmap2 - native); - ESTIMATE("total seccomp overhead for 3 full filters", calc, - filter1 - native); - ESTIMATE("total seccomp overhead for 4 full filters", calc, - filter2 - native); - ESTIMATE("seccomp entry overhead", entry, - bitmap1 - native - (bitmap2 - bitmap1)); - ESTIMATE("seccomp per-filter overhead (last 2 diff)", per_filter1, - filter2 - filter1); - ESTIMATE("seccomp per-filter overhead (filters / 4)", per_filter2, - (filter2 - native - entry) / 4); - - printf("Expectations:\n"); - ret |= compare("native", "≤", "1 bitmap", native, le, bitmap1); - bits = compare("native", "≤", "1 filter", native, le, filter1); - if (bits) - goto more_samples; - - ret |= compare("per-filter (last 2 diff)", "≈", "per-filter (filters / 4)", - per_filter1, approx, per_filter2); - - bits = compare("1 bitmapped", "≈", "2 bitmapped", - bitmap1 - native, approx, bitmap2 - native); - if (bits) { - printf("Skipping constant action bitmap expectations: they appear unsupported.\n"); - goto out; - } - - ret |= compare("entry", "≈", "1 bitmapped", entry, approx, bitmap1 - native); - ret |= compare("entry", "≈", "2 bitmapped", entry, approx, bitmap2 - native); - ret |= compare("native + entry + (per filter * 4)", "≈", "4 filters total", - entry + (per_filter1 * 4) + native, approx, filter2); - if (ret == 0) - goto out; - -more_samples: - printf("Saw unexpected benchmark result. Try running again with more samples?\n"); -out: return 0; } diff --git a/tools/testing/selftests/seccomp/seccomp_bpf.c b/tools/testing/selftests/seccomp/seccomp_bpf.c index 412e69e11620..a12eea3aff10 100644 --- a/tools/testing/selftests/seccomp/seccomp_bpf.c +++ b/tools/testing/selftests/seccomp/seccomp_bpf.c @@ -3504,6 +3504,7 @@ TEST(seccomp_get_notif_sizes) /* * TODO: + * - add microbenchmarks * - expand NNP testing * - better arch-specific TRACE and TRAP handlers. * - endianness checking when appropriate @@ -3511,6 +3512,7 @@ TEST(seccomp_get_notif_sizes) * - arch value testing (x86 modes especially) * - verify that FILTER_FLAG_LOG filters generate log messages * - verify that RET_LOG generates log messages + * - ... */ TEST_HARNESS_MAIN diff --git a/tools/testing/selftests/seccomp/settings b/tools/testing/selftests/seccomp/settings deleted file mode 100644 index 6091b45d226b..000000000000 --- a/tools/testing/selftests/seccomp/settings +++ /dev/null @@ -1 +0,0 @@ -timeout=120 diff --git a/tools/testing/selftests/watchdog/watchdog-test.c b/tools/testing/selftests/watchdog/watchdog-test.c index 4056706d63f7..09773695d219 100644 --- a/tools/testing/selftests/watchdog/watchdog-test.c +++ b/tools/testing/selftests/watchdog/watchdog-test.c @@ -240,12 +240,6 @@ int main(int argc, char *argv[]) if (oneshot) goto end; - /* Check if WDIOF_KEEPALIVEPING is supported */ - if (!(info.options & WDIOF_KEEPALIVEPING)) { - printf("WDIOC_KEEPALIVE not supported by this device\n"); - goto end; - } - printf("Watchdog Ticking Away!\n"); /*